[examples] add k32w061 platform (#4930)
diff --git a/configure.ac b/configure.ac
index a3b716e..0d9bf86 100644
--- a/configure.ac
+++ b/configure.ac
@@ -788,14 +788,14 @@
AC_ARG_WITH(examples,
[AS_HELP_STRING([--with-examples=TARGET],
[Build example applications for one of: simulation, cc1352, cc2538, cc2650, cc2652, efr32mg12, efr32mg13, efr32mg21,
- gp712, jn5189, kw41z, nrf52811, nrf52833, nrf52840, qpg6095, samr21 @<:@default=no@:>@.
+ gp712, jn5189, k32w061, kw41z, nrf52811, nrf52833, nrf52840, qpg6095, samr21 @<:@default=no@:>@.
Note that building example applications also builds the associated OpenThread platform libraries
and any third_party libraries needed to support the examples.])],
[
case "${with_examples}" in
no)
;;
- simulation|cc1352|cc2538|cc2650|cc2652|efr32mg12|efr32mg13|efr32mg21|gp712|jn5189|kw41z|nrf52811|nrf52833|nrf52840|qpg6095|samr21)
+ simulation|cc1352|cc2538|cc2650|cc2652|efr32mg12|efr32mg13|efr32mg21|gp712|jn5189|k32w061|kw41z|nrf52811|nrf52833|nrf52840|qpg6095|samr21)
;;
*)
AC_MSG_RESULT(ERROR)
@@ -817,6 +817,7 @@
AM_CONDITIONAL([OPENTHREAD_EXAMPLES_EFR32MG21], [test "${with_examples}" = "efr32mg21"])
AM_CONDITIONAL([OPENTHREAD_EXAMPLES_GP712], [test "${with_examples}" = "gp712"])
AM_CONDITIONAL([OPENTHREAD_EXAMPLES_JN5189], [test "${with_examples}" = "jn5189"])
+AM_CONDITIONAL([OPENTHREAD_EXAMPLES_K32W061], [test "${with_examples}" = "k32w061"])
AM_CONDITIONAL([OPENTHREAD_EXAMPLES_KW41Z], [test "${with_examples}" = "kw41z"])
AM_CONDITIONAL([OPENTHREAD_EXAMPLES_NRF52811], [test "${with_examples}" = "nrf52811"])
AM_CONDITIONAL([OPENTHREAD_EXAMPLES_NRF52833], [test "${with_examples}" = "nrf52833"])
@@ -900,6 +901,7 @@
AM_CONDITIONAL([OPENTHREAD_PLATFORM_SIMULATION],[test "${with_platform}" = "simulation"])
AM_CONDITIONAL([OPENTHREAD_PLATFORM_NRF528XX], [test OPENTHREAD_PLATFORM_NRF52811 || test OPENTHREAD_PLATFORM_NRF52833 || test OPENTHREAD_PLATFORM_NRF52840])
+AM_CONDITIONAL([OPENTHREAD_PLATFORM_K32W], [test OPENTHREAD_PLATFORM_K32W061 || test OPENTHREAD_PLATFORM_JN5189])
AM_COND_IF([OPENTHREAD_PLATFORM_POSIX], CPPFLAGS="${CPPFLAGS} -DOPENTHREAD_PLATFORM_POSIX=1", CPPFLAGS="${CPPFLAGS} -DOPENTHREAD_PLATFORM_POSIX=0")
@@ -1056,7 +1058,7 @@
examples/platforms/efr32mg21/sleepy-demo/sleepy-demo-ftd/Makefile
examples/platforms/efr32mg21/sleepy-demo/sleepy-demo-mtd/Makefile
examples/platforms/gp712/Makefile
-examples/platforms/jn5189/Makefile
+examples/platforms/k32w/Makefile
examples/platforms/kw41z/Makefile
examples/platforms/nrf528xx/Makefile
examples/platforms/qpg6095/Makefile
diff --git a/examples/Makefile-jn5189 b/examples/Makefile-jn5189
index 78b5dc5..6cc5b67 100755
--- a/examples/Makefile-jn5189
+++ b/examples/Makefile-jn5189
@@ -43,7 +43,6 @@
configure_OPTIONS = \
--enable-cli \
- --enable-diag \
--enable-ftd \
--enable-mtd \
--enable-ncp \
@@ -61,14 +60,16 @@
JN5189_MBEDTLS_CPPFLAGS += -DMBEDTLS_USER_CONFIG_FILE='\"jn5189-mbedtls-config.h\"'
JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/include/
JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/
-JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189/
-JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189/crypto
-JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189/drivers/
-JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189/drivers/aes/
-JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189/drivers/sha/
-JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189/rom_apis/
-JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189/dk6_jn5180/
-JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/CMSIS/Include/
+JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189DK6/
+JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189DK6/devices/JN5189
+JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189DK6/middleware/mbedtls/port/ksdk/
+JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189DK6/devices/JN5189/drivers/
+JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189DK6/devices/JN5189/utilities/
+JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189DK6/devices/JN5189/utilities/debug-console/
+JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189DK6/devices/JN5189/utilities/str/
+JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189DK6/drivers/components/serial_manager/
+JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189DK6/drivers/components/uart/
+JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189DK6/CMSIS/Include/
JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/mbedtls/
JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/mbedtls/repo/include/
JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/mbedtls/repo/include/mbedtls/
@@ -77,8 +78,8 @@
AbsTopSourceDir := $(dir $(realpath $(firstword $(MAKEFILE_LIST))))..
CONFIG_FILE = OPENTHREAD_PROJECT_CORE_CONFIG_FILE='\"openthread-core-jn5189-config.h\"'
-CONFIG_FILE_PATH = $(AbsTopSourceDir)/examples/platforms/jn5189/
-SIGN_IMAGE_PATH = $(AbsTopSourceDir)/third_party/nxp/JN5189/ImageSigning/
+CONFIG_FILE_PATH = $(AbsTopSourceDir)/examples/platforms/k32w/jn5189/
+SIGN_IMAGE_PATH = $(AbsTopSourceDir)/third_party/nxp/JN5189DK6/tools/imagetool/
COMMONCFLAGS := \
-fdata-sections \
@@ -91,6 +92,7 @@
-DJENNIC_CHIP_FAMILY_NAME=_JN518x \
-DSDK_DEBUGCONSOLE=0 \
-D$(CONFIG_FILE) \
+ -DUSE_RTOS=0 \
-I$(CONFIG_FILE_PATH) \
$(NULL)
diff --git a/examples/Makefile-k32w061 b/examples/Makefile-k32w061
new file mode 100755
index 0000000..3c39573
--- /dev/null
+++ b/examples/Makefile-k32w061
@@ -0,0 +1,298 @@
+#
+# Copyright (c) 2019, The OpenThread Authors.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+# 3. Neither the name of the copyright holder nor the
+# names of its contributors may be used to endorse or promote products
+# derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+.NOTPARALLEL:
+
+AR = arm-none-eabi-ar
+CCAS = arm-none-eabi-as
+CPP = arm-none-eabi-cpp
+CC = arm-none-eabi-gcc
+CXX = arm-none-eabi-g++
+LD = arm-none-eabi-ld
+STRIP = arm-none-eabi-strip
+NM = arm-none-eabi-nm
+RANLIB = arm-none-eabi-ranlib
+OBJCOPY = arm-none-eabi-objcopy
+
+BuildJobs ?= 10
+
+configure_OPTIONS = \
+ --enable-cli \
+ --enable-diag \
+ --enable-ftd \
+ --enable-mtd \
+ --enable-ncp \
+ --with-ncp-bus=uart \
+ --enable-radio-only \
+ --enable-linker-map \
+ --with-examples=k32w061 \
+ $(NULL)
+
+ifneq ($(DISABLE_BUILTIN_MBEDTLS), 1)
+configure_OPTIONS += MBEDTLS_CPPFLAGS="$(K32W061_MBEDTLS_CPPFLAGS)"
+endif
+
+K32W061_MBEDTLS_CPPFLAGS = -DMBEDTLS_CONFIG_FILE='\"mbedtls-config.h\"'
+K32W061_MBEDTLS_CPPFLAGS += -DMBEDTLS_USER_CONFIG_FILE='\"k32w061-mbedtls-config.h\"'
+K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/include/
+K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/
+K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/K32W061DK6/
+K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/K32W061DK6/devices/K32W061
+K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/K32W061DK6/middleware/mbedtls/port/ksdk/
+K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/K32W061DK6/devices/K32W061/drivers/
+K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/K32W061DK6/devices/K32W061/utilities/
+K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/K32W061DK6/devices/K32W061/utilities/debug-console/
+K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/K32W061DK6/devices/K32W061/utilities/str/
+K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/K32W061DK6/drivers/components/serial_manager/
+K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/K32W061DK6/drivers/components/uart/
+
+K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/K32W061DK6/CMSIS/Include/
+K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/mbedtls/
+K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/mbedtls/repo/include/
+K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/mbedtls/repo/include/mbedtls/
+
+TopSourceDir := $(dir $(shell readlink $(firstword $(MAKEFILE_LIST))))..
+AbsTopSourceDir := $(dir $(realpath $(firstword $(MAKEFILE_LIST))))..
+
+CONFIG_FILE = OPENTHREAD_PROJECT_CORE_CONFIG_FILE='\"openthread-core-k32w061-config.h\"'
+CONFIG_FILE_PATH = $(AbsTopSourceDir)/examples/platforms/k32w/k32w061/
+SIGN_IMAGE_PATH = $(AbsTopSourceDir)/third_party/nxp/K32W061DK6/tools/imagetool/
+
+COMMONCFLAGS := \
+ -fdata-sections \
+ -ffunction-sections \
+ -Os \
+ -g \
+ -DCPU_K32W061HN \
+ -DCPU_JN518X \
+ -DCPU_JN518X_REV=2 \
+ -DJENNIC_CHIP_FAMILY_JN518x \
+ -DJENNIC_CHIP_FAMILY_NAME=_JN518x \
+ -DSDK_DEBUGCONSOLE=0 \
+ -D$(CONFIG_FILE) \
+ -DUSE_RTOS=0 \
+ -I$(CONFIG_FILE_PATH) \
+ $(NULL)
+
+include $(dir $(abspath $(lastword $(MAKEFILE_LIST))))/common-switches.mk
+
+CPPFLAGS += \
+ $(COMMONCFLAGS) \
+ $(target_CPPFLAGS) \
+ $(NULL)
+
+CFLAGS += \
+ $(COMMONCFLAGS) \
+ $(target_CFLAGS) \
+ $(NULL)
+
+CXXFLAGS += \
+ $(COMMONCFLAGS) \
+ $(target_CXXFLAGS) \
+ -fno-exceptions \
+ -fno-rtti \
+ $(NULL)
+
+LDFLAGS += \
+ $(COMMONCFLAGS) \
+ $(target_LDFLAGS) \
+ -specs=nano.specs \
+ -specs=nosys.specs \
+ -Wl,--gc-sections \
+ $(NULL)
+
+ECHO := @echo
+MAKE := make
+MKDIR_P := mkdir -p
+LN_S := ln -s
+RM_F := rm -f
+
+INSTALL := /usr/bin/install
+INSTALLFLAGS := -p
+
+BuildPath = build
+TopBuildDir = $(BuildPath)
+AbsTopBuildDir = $(PWD)/$(TopBuildDir)
+
+ResultPath = output
+TopResultDir = $(ResultPath)
+AbsTopResultDir = $(PWD)/$(TopResultDir)
+
+TargetTuple = k32w061
+
+ARCHS = cortex-m4
+
+TopTargetLibDir = $(TopResultDir)/$(TargetTuple)/lib
+TopTargetBinDir = $(TopResultDir)/$(TargetTuple)/bin
+
+ifndef BuildJobs
+BuildJobs := $(shell getconf _NPROCESSORS_ONLN)
+endif
+JOBSFLAG := -j$(BuildJobs)
+
+#
+# configure-arch <arch>
+#
+# Configure OpenThread for the specified architecture.
+#
+# arch - The architecture to configure.
+#
+define configure-arch
+$(ECHO) " CONFIG $(TargetTuple)..."
+(cd $(BuildPath)/$(TargetTuple) && $(AbsTopSourceDir)/configure \
+INSTALL="$(INSTALL) $(INSTALLFLAGS)" \
+CPP="$(CPP)" CC="$(CC)" CXX="$(CXX)" OBJC="$(OBJC)" OBJCXX="$(OBJCXX)" AR="$(AR)" RANLIB="$(RANLIB)" NM="$(NM)" STRIP="$(STRIP)" CPPFLAGS="$(CPPFLAGS)" CFLAGS="$(CFLAGS)" CXXFLAGS="$(CXXFLAGS)" LDFLAGS="$(LDFLAGS)" \
+--host=arm-none-eabi \
+--prefix=/ \
+--exec-prefix=/$(TargetTuple) \
+$(configure_OPTIONS))
+endef # configure-arch
+
+#
+# build-arch <arch>
+#
+# Build the OpenThread intermediate build products for the specified
+# architecture.
+#
+# arch - The architecture to build.
+#
+define build-arch
+$(ECHO) " BUILD $(TargetTuple)"
+$(MAKE) $(JOBSFLAG) -C $(BuildPath)/$(TargetTuple) --no-print-directory \
+all
+endef # build-arch
+
+#
+# stage-arch <arch>
+#
+# Stage (install) the OpenThread final build products for the specified
+# architecture.
+#
+# arch - The architecture to stage.
+#
+define stage-arch
+$(ECHO) " STAGE $(TargetTuple)"
+$(MAKE) $(JOBSFLAG) -C $(BuildPath)/$(TargetTuple) --no-print-directory \
+DESTDIR=$(AbsTopResultDir) \
+install
+endef # stage-arch
+
+#
+# ARCH_template <arch>
+#
+# Define macros, targets and rules to configure, build, and stage the
+# OpenThread for a single architecture.
+#
+# arch - The architecture to instantiate the template for.
+#
+define ARCH_template
+CONFIGURE_TARGETS += configure-$(1)
+BUILD_TARGETS += do-build-$(1)
+STAGE_TARGETS += stage-$(1)
+BUILD_DIRS += $(BuildPath)/$(TargetTuple)
+DIRECTORIES += $(BuildPath)/$(TargetTuple)
+
+configure-$(1): target_CPPFLAGS=$($(1)_target_CPPFLAGS)
+configure-$(1): target_CFLAGS=$($(1)_target_CFLAGS)
+configure-$(1): target_CXXFLAGS=$($(1)_target_CXXFLAGS)
+configure-$(1): target_LDFLAGS=$($(1)_target_LDFLAGS)
+
+configure-$(1): $(BuildPath)/$(TargetTuple)/config.status
+
+$(BuildPath)/$(TargetTuple)/config.status: | $(BuildPath)/$(TargetTuple)
+ $$(call configure-arch,$(1))
+
+do-build-$(1): configure-$(1)
+
+do-build-$(1):
+ +$$(call build-arch,$(1))
+
+stage-$(1): do-build-$(1)
+
+stage-$(1): | $(TopResultDir)
+ $$(call stage-arch,$(1))
+
+$(1): stage-$(1)
+endef # ARCH_template
+
+.DEFAULT_GOAL := all
+
+all: stage
+
+#
+# cortex-m4
+#
+
+cortex-m4_target_ABI = cortex-m4
+cortex-m4_target_CPPFLAGS = -mcpu=cortex-m4 -mfloat-abi=soft -mthumb
+cortex-m4_target_CFLAGS = -mcpu=cortex-m4 -mfloat-abi=soft -mthumb
+cortex-m4_target_CXXFLAGS = -mcpu=cortex-m4 -mfloat-abi=soft -mthumb
+cortex-m4_target_LDFLAGS = -mcpu=cortex-m4 -mfloat-abi=soft -mthumb
+
+# Instantiate an architecture-specific build template for each target
+# architecture.
+
+$(foreach arch,$(ARCHS),$(eval $(call ARCH_template,$(arch))))
+
+#
+# Common / Finalization
+#
+
+configure: $(CONFIGURE_TARGETS)
+
+build: $(BUILD_TARGETS)
+
+stage: $(STAGE_TARGETS)
+
+DIRECTORIES = $(TopResultDir) $(TopResultDir)/$(TargetTuple)/lib $(BUILD_DIRS)
+
+CLEAN_DIRS = $(TopResultDir) $(BUILD_DIRS)
+
+all: stage post-build-step
+
+$(DIRECTORIES):
+ $(ECHO) " MKDIR $@"
+ @$(MKDIR_P) "$@"
+
+post-build-step:
+ $(SIGN_IMAGE_PATH)/sign_images.sh $(TopTargetBinDir)
+
+clean:
+ $(ECHO) " CLEAN"
+ @$(RM_F) -r $(CLEAN_DIRS)
+
+help:
+ $(ECHO) "Simply type 'make -f $(firstword $(MAKEFILE_LIST))' to build OpenThread for the following "
+ $(ECHO) "architectures: "
+ $(ECHO) ""
+ $(ECHO) " $(ARCHS)"
+ $(ECHO) ""
+ $(ECHO) "To build only a particular architecture, specify: "
+ $(ECHO) ""
+ $(ECHO) " make -f $(firstword $(MAKEFILE_LIST)) <architecture>"
+ $(ECHO) ""
diff --git a/examples/platforms/Makefile.am b/examples/platforms/Makefile.am
index 0141172..395c68a 100644
--- a/examples/platforms/Makefile.am
+++ b/examples/platforms/Makefile.am
@@ -39,7 +39,7 @@
efr32mg13 \
efr32mg21 \
gp712 \
- jn5189 \
+ k32w \
kw41z \
nrf528xx \
simulation \
@@ -86,8 +86,8 @@
SUBDIRS += gp712
endif
-if OPENTHREAD_PLATFORM_JN5189
-SUBDIRS += jn5189
+if OPENTHREAD_PLATFORM_K32W
+SUBDIRS += k32w
endif
if OPENTHREAD_PLATFORM_KW41Z
diff --git a/examples/platforms/Makefile.platform.am b/examples/platforms/Makefile.platform.am
index 5823efb..a5f89be 100644
--- a/examples/platforms/Makefile.platform.am
+++ b/examples/platforms/Makefile.platform.am
@@ -74,7 +74,11 @@
endif
if OPENTHREAD_EXAMPLES_JN5189
-include $(top_srcdir)/examples/platforms/jn5189/Makefile.platform.am
+include $(top_srcdir)/examples/platforms/k32w/jn5189/Makefile.platform.am
+endif
+
+if OPENTHREAD_EXAMPLES_K32W061
+include $(top_srcdir)/examples/platforms/k32w/k32w061/Makefile.platform.am
endif
if OPENTHREAD_EXAMPLES_KW41Z
diff --git a/examples/platforms/jn5189/Makefile.am b/examples/platforms/jn5189/Makefile.am
deleted file mode 100755
index 8b408e6..0000000
--- a/examples/platforms/jn5189/Makefile.am
+++ /dev/null
@@ -1,132 +0,0 @@
-#
-# Copyright (c) 2019, The OpenThread Authors.
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-# 1. Redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer.
-# 2. Redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution.
-# 3. Neither the name of the copyright holder nor the
-# names of its contributors may be used to endorse or promote products
-# derived from this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-# POSSIBILITY OF SUCH DAMAGE.
-#
-
-include $(abs_top_nlbuild_autotools_dir)/automake/pre.am
-
-lib_LIBRARIES = \
- libopenthread-jn5189_plat.a \
- libopenthread-jn5189_sdk.a
- $(NULL)
-
-# Do not enable -pedantic-errors for jn5189 driver library
-override CFLAGS := $(filter-out -pedantic-errors,$(CFLAGS))
-override CXXFLAGS := $(filter-out -pedantic-errors,$(CXXFLAGS))
-
-# Do not enable -Wundef for jn5189 driver library
-override CFLAGS := $(filter-out -Wundef,$(CFLAGS))
-override CXXFLAGS := $(filter-out -Wundef,$(CXXFLAGS))
-
-# Do not enable -Wcast-align for this platform
-override CFLAGS := $(filter-out -Wcast-align,$(CFLAGS))
-override CXXFLAGS := $(filter-out -Wcast-align,$(CXXFLAGS))
-
-LIB_FLAGS = \
- -DCPU_JN518X \
- -DCPU_JN518X_REV=2 \
- -DJENNIC_CHIP_FAMILY_JN518x \
- -DJENNIC_CHIP_FAMILY_NAME=_JN518x \
- -I$(top_srcdir)/include \
- -I$(top_srcdir)/examples/platforms \
- -I$(top_srcdir)/src/core \
- -I$(top_srcdir)/third_party/nxp \
- -I$(top_srcdir)/third_party/nxp/JN5189 \
- -I$(top_srcdir)/third_party/nxp/JN5189/crypto \
- -I$(top_srcdir)/third_party/nxp/JN5189/drivers \
- -I$(top_srcdir)/third_party/nxp/JN5189/rom_apis \
- -I$(top_srcdir)/third_party/nxp/JN5189/dk6_jn5180 \
- -I$(top_srcdir)/third_party/nxp/CMSIS/Include \
- -I$(top_srcdir)/third_party/nxp/JN5189/uMac/Include \
- -I$(top_srcdir)/third_party/nxp/JN5189/Radio_JN5189/Include \
- -I$(top_srcdir)/third_party/nxp/JN5189/JennicCommon/Include \
- -I$(top_srcdir)/third_party/nxp/JN5189/MicroSpecific/Include \
- -Wno-unknown-pragmas \
- -Wno-sign-compare \
- -Wno-unused-function \
- -Wno-unused-parameter \
- -Wno-empty-body \
- $(NULL)
-
-libopenthread_jn5189_sdk_a_CPPFLAGS = \
- $(LIB_FLAGS) \
- $(NULL)
-
-libopenthread_jn5189_plat_a_CPPFLAGS = \
- $(LIB_FLAGS) \
- $(NULL)
-
-PLATFORM_SOURCES = \
- alarm.c \
- diag.c \
- flash.c \
- logging.c \
- misc.c \
- radio.c \
- entropy.c \
- system.c \
- uart.c \
- settings_jn5189.c \
- @top_builddir@/third_party/nxp/JN5189/drivers/fsl_assert.c \
- @top_builddir@/third_party/nxp/JN5189/crypto/aes_alt.c \
- @top_builddir@/third_party/nxp/JN5189/crypto/ksdk_mbedtls.c \
- $(NULL)
-
-libopenthread_jn5189_sdk_a_SOURCES = \
- @top_builddir@/third_party/nxp/JN5189/startup_JN5189.c \
- @top_builddir@/third_party/nxp/JN5189/system_JN5189.c \
- @top_builddir@/third_party/nxp/JN5189/dk6_jn5180/pin_mux.c \
- @top_builddir@/third_party/nxp/JN5189/dk6_jn5180/clock_config.c \
- @top_builddir@/third_party/nxp/JN5189/drivers/fsl_gpio.c \
- @top_builddir@/third_party/nxp/JN5189/drivers/fsl_clock.c \
- @top_builddir@/third_party/nxp/JN5189/drivers/fsl_ctimer.c \
- @top_builddir@/third_party/nxp/JN5189/drivers/fsl_wtimer.c \
- @top_builddir@/third_party/nxp/JN5189/drivers/fsl_flash.c \
- @top_builddir@/third_party/nxp/JN5189/drivers/fsl_usart.c \
- @top_builddir@/third_party/nxp/JN5189/drivers/fsl_rng.c \
- @top_builddir@/third_party/nxp/JN5189/drivers/fsl_flexcomm.c \
- @top_builddir@/third_party/nxp/JN5189/drivers/fsl_reset.c \
- @top_builddir@/third_party/nxp/JN5189/drivers/fsl_power.c \
- @top_builddir@/third_party/nxp/JN5189/drivers/fsl_debug_console.c \
- @top_builddir@/third_party/nxp/JN5189/drivers/aes/fsl_aes.c \
- @top_builddir@/third_party/nxp/JN5189/drivers/sha/fsl_sha.c \
- $(NULL)
-
-libopenthread_jn5189_plat_a_SOURCES = \
- $(PLATFORM_SOURCES) \
- $(NULL)
-
-PRETTY_FILES = \
- $(PLATFORM_SOURCES) \
- $(NULL)
-
-Dash = -
-libopenthread_jn5189_sdk_a_LIBADD = \
- $(shell find $(top_builddir)/examples/platforms/utils $(Dash)type f $(Dash)name "*.o")
-libopenthread_jn5189_plat_a_LIBADD = \
- $(shell find $(top_builddir)/examples/platforms/utils $(Dash)type f $(Dash)name "*.o")
-
-include $(abs_top_nlbuild_autotools_dir)/automake/post.am
diff --git a/examples/platforms/jn5189/Makefile.platform.am b/examples/platforms/k32w/Makefile.am
similarity index 69%
copy from examples/platforms/jn5189/Makefile.platform.am
copy to examples/platforms/k32w/Makefile.am
index 7e58e1a..b2f7528 100755
--- a/examples/platforms/jn5189/Makefile.platform.am
+++ b/examples/platforms/k32w/Makefile.am
@@ -26,18 +26,15 @@
# POSSIBILITY OF SUCH DAMAGE.
#
-#
-# JN5189 platform-specific Makefile
-#
+# Use automake includes since we cannot use SUBDIRS feature due to cleanup
+# errors - few targets may use the same source file but dependency file is
+# created only once which leads to errors when auto-generated Makefile tries
+# to remove .Po files that were already removed
-LDADD_COMMON += \
- $(top_builddir)/examples/platforms/jn5189/libopenthread-jn5189_plat.a \
- $(top_builddir)/examples/platforms/jn5189/libopenthread-jn5189_sdk.a \
- $(top_srcdir)/third_party/nxp/JN5189/libraries/libMiniMac.a \
- $(top_srcdir)/third_party/nxp/JN5189/libraries/libRadio.a \
- $(top_srcdir)/third_party/nxp/JN5189/libraries/libMicroSpecific_JN518x.a \
- $(NULL)
+if OPENTHREAD_EXAMPLES_JN5189
+include jn5189/Makefile.am
+endif
-LDFLAGS_COMMON += \
- -T $(top_srcdir)/examples/platforms/jn5189/jn5189.ld \
- $(NULL)
+if OPENTHREAD_EXAMPLES_K32W061
+include k32w061/Makefile.am
+endif
diff --git a/examples/platforms/k32w/README.md b/examples/platforms/k32w/README.md
new file mode 100755
index 0000000..c13d1b0
--- /dev/null
+++ b/examples/platforms/k32w/README.md
@@ -0,0 +1,14 @@
+# OpenThread on K32W Example
+
+This directory contains example platform drivers for [NXP Semiconductors K32W061 SoC][k32w061] and [NXP Semiconductors JN5189 SoC][jn5189].
+
+[k32w061]: https://www.nxp.com/products/wireless/thread/k32w061-41-high-performance-secure-and-ultra-low-power-mcu-for-zigbeethread-and-bluetooth-le-5-0-with-built-in-nfc-option:K32W061_41
+[jn5189]: https://www.nxp.com/products/wireless/thread/jn5189-88-t-high-performance-and-ultra-low-power-mcus-for-zigbee-and-thread-with-built-in-nfc-option:JN5189_88_T
+
+To learn more about building and running the examples please check:
+
+- [OpenThread on K32W061 examples][k32w061-page]
+- [OpenThread on JN5189 examples][jn5189-page]
+
+[k32w061-page]: ./k32w061/README.md
+[jn5189-page]: ./jn5189/README.md
diff --git a/examples/platforms/k32w/jn5189/Makefile.am b/examples/platforms/k32w/jn5189/Makefile.am
new file mode 100755
index 0000000..81b0408
--- /dev/null
+++ b/examples/platforms/k32w/jn5189/Makefile.am
@@ -0,0 +1,140 @@
+#
+# Copyright (c) 2019, The OpenThread Authors.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+# 3. Neither the name of the copyright holder nor the
+# names of its contributors may be used to endorse or promote products
+# derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+include $(abs_top_nlbuild_autotools_dir)/automake/pre.am
+
+lib_LIBRARIES = \
+ libopenthread-jn5189_plat.a \
+ libopenthread-jn5189_sdk.a
+ $(NULL)
+
+# Do not enable -pedantic-errors for jn5189 driver library
+override CFLAGS := $(filter-out -pedantic-errors,$(CFLAGS))
+override CXXFLAGS := $(filter-out -pedantic-errors,$(CXXFLAGS))
+
+# Do not enable -Wcast-align for jn5189 driver library
+override CFLAGS := $(filter-out -Wcast-align,$(CFLAGS))
+override CXXFLAGS := $(filter-out -Wcast-align,$(CXXFLAGS))
+
+LIB_FLAGS = \
+ -DCPU_JN518X \
+ -DCPU_JN518X_REV=2 \
+ -DJENNIC_CHIP_FAMILY_JN518x \
+ -DJENNIC_CHIP_FAMILY_NAME=_JN518x \
+ -DUSE_RTOS=0 \
+ -DgPWR_LDOMEM_0_9V_PD=0 \
+ -DNO_SYSCORECLK_UPD=0 \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/examples/platforms \
+ -I$(top_srcdir)/src/core \
+ -I$(top_srcdir)/third_party/nxp \
+ -I$(top_srcdir)/third_party/nxp/JN5189DK6 \
+ -I$(top_srcdir)/third_party/nxp/JN5189DK6/devices/JN5189 \
+ -I$(top_srcdir)/third_party/nxp/JN5189DK6/middleware/mbedtls/port/ksdk \
+ -I$(top_srcdir)/third_party/nxp/JN5189DK6/components/serial_manager \
+ -I$(top_srcdir)/third_party/nxp/JN5189DK6/components/uart \
+ -I$(top_srcdir)/third_party/nxp/JN5189DK6/devices/JN5189/drivers \
+ -I$(top_srcdir)/third_party/nxp/JN5189DK6/devices/JN5189/utilities/debug_console \
+ -I$(top_srcdir)/third_party/nxp/JN5189DK6/devices/JN5189/utilities/str \
+ -I$(top_srcdir)/third_party/nxp/JN5189DK6/boards/jn5189dk6/wireless_examples/openthread/enablement \
+ -I$(top_srcdir)/third_party/nxp/JN5189DK6/CMSIS/Include \
+ -I$(top_srcdir)/third_party/nxp/JN5189DK6/middleware/wireless/ieee-802.15.4/uMac/Include \
+ -I$(top_srcdir)/third_party/nxp/JN5189DK6/middleware/wireless/framework/XCVR/DK6/Build/Include \
+ -I$(top_srcdir)/third_party/nxp/JN5189DK6/middleware/wireless/framework/XCVR/DK6 \
+ -I$(top_srcdir)/third_party/nxp/JN5189DK6/middleware/wireless/framework/Common \
+ -Wno-unknown-pragmas \
+ -Wno-sign-compare \
+ -Wno-unused-function \
+ -Wno-unused-parameter \
+ -Wno-empty-body \
+ $(NULL)
+
+libopenthread_jn5189_sdk_a_CPPFLAGS = \
+ $(LIB_FLAGS) \
+ $(NULL)
+
+libopenthread_jn5189_plat_a_CPPFLAGS = \
+ $(LIB_FLAGS) \
+ $(NULL)
+
+PLATFORM_SOURCES = \
+ src/alarm.c \
+ src/diag.c \
+ src/flash.c \
+ src/logging.c \
+ src/misc.c \
+ src/radio.c \
+ src/entropy.c \
+ src/system.c \
+ src/uart.c \
+ src/settings_k32w.c \
+ @top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/utilities/fsl_assert.c \
+ @top_builddir@/third_party/nxp/JN5189DK6/middleware/mbedtls/port/ksdk/aes_alt.c \
+ @top_builddir@/third_party/nxp/JN5189DK6/middleware/mbedtls/port/ksdk/ksdk_mbedtls.c \
+ $(NULL)
+
+libopenthread_jn5189_sdk_a_SOURCES = \
+ @top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/mcuxpresso/startup_JN5189.c \
+ @top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/system_JN5189.c \
+ @top_builddir@/third_party/nxp/JN5189DK6/boards/jn5189dk6/wireless_examples/openthread/enablement/pin_mux.c \
+ @top_builddir@/third_party/nxp/JN5189DK6/boards/jn5189dk6/wireless_examples/openthread/enablement/clock_config.c \
+ @top_builddir@/third_party/nxp/JN5189DK6/components/serial_manager/serial_manager.c \
+ @top_builddir@/third_party/nxp/JN5189DK6/components/serial_manager/serial_port_uart.c \
+ @top_builddir@/third_party/nxp/JN5189DK6/components/uart/usart_adapter.c \
+ @top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_gpio.c \
+ @top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_clock.c \
+ @top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_ctimer.c \
+ @top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_wtimer.c \
+ @top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_flash.c \
+ @top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_usart.c \
+ @top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_rng.c \
+ @top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_flexcomm.c \
+ @top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_reset.c \
+ @top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_power.c \
+ @top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_aes.c \
+ @top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_sha.c \
+ @top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/utilities/debug_console/fsl_debug_console.c \
+ @top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/utilities/str/fsl_str.c \
+ @top_builddir@/third_party/nxp/JN5189DK6/middleware/wireless/framework/Common/MicroInt_arm_sdk2.c \
+ $(NULL)
+
+libopenthread_jn5189_plat_a_SOURCES = \
+ $(PLATFORM_SOURCES) \
+ $(NULL)
+
+PRETTY_FILES = \
+ $(PLATFORM_SOURCES) \
+ $(NULL)
+
+Dash = -
+libopenthread_jn5189_sdk_a_LIBADD = \
+ $(shell find $(top_builddir)/examples/platforms/utils $(Dash)type f $(Dash)name "*.o")
+libopenthread_jn5189_plat_a_LIBADD = \
+ $(shell find $(top_builddir)/examples/platforms/utils $(Dash)type f $(Dash)name "*.o")
+
+include $(abs_top_nlbuild_autotools_dir)/automake/post.am
diff --git a/examples/platforms/jn5189/Makefile.platform.am b/examples/platforms/k32w/jn5189/Makefile.platform.am
similarity index 75%
rename from examples/platforms/jn5189/Makefile.platform.am
rename to examples/platforms/k32w/jn5189/Makefile.platform.am
index 7e58e1a..0e279c9 100755
--- a/examples/platforms/jn5189/Makefile.platform.am
+++ b/examples/platforms/k32w/jn5189/Makefile.platform.am
@@ -30,14 +30,13 @@
# JN5189 platform-specific Makefile
#
-LDADD_COMMON += \
- $(top_builddir)/examples/platforms/jn5189/libopenthread-jn5189_plat.a \
- $(top_builddir)/examples/platforms/jn5189/libopenthread-jn5189_sdk.a \
- $(top_srcdir)/third_party/nxp/JN5189/libraries/libMiniMac.a \
- $(top_srcdir)/third_party/nxp/JN5189/libraries/libRadio.a \
- $(top_srcdir)/third_party/nxp/JN5189/libraries/libMicroSpecific_JN518x.a \
+LDADD_COMMON += \
+ $(top_builddir)/examples/platforms/k32w/libopenthread-jn5189_plat.a \
+ $(top_builddir)/examples/platforms/k32w/libopenthread-jn5189_sdk.a \
+ $(top_srcdir)/third_party/nxp/JN5189DK6/middleware/wireless/ieee-802.15.4/lib/libMiniMac.a \
+ $(top_srcdir)/third_party/nxp/JN5189DK6/middleware/wireless/framework/XCVR/lib/libRadio.a \
$(NULL)
-LDFLAGS_COMMON += \
- -T $(top_srcdir)/examples/platforms/jn5189/jn5189.ld \
+LDFLAGS_COMMON += \
+ -T $(top_srcdir)/examples/platforms/k32w/jn5189/jn5189.ld \
$(NULL)
diff --git a/examples/platforms/jn5189/README.md b/examples/platforms/k32w/jn5189/README.md
similarity index 87%
rename from examples/platforms/jn5189/README.md
rename to examples/platforms/k32w/jn5189/README.md
index b1f67b4..0210190 100755
--- a/examples/platforms/jn5189/README.md
+++ b/examples/platforms/k32w/jn5189/README.md
@@ -1,6 +1,6 @@
# OpenThread on NXP JN5189 Example
-This directory contains example platform drivers for the [NXP JN5189][https://www.nxp.com/products/wireless/thread/jn5189-88-t-high-performance-and-ultra-low-power-mcus-for-zigbee-and-thread-with-built-in-nfc-option:jn5189_88_t] based on [JN5189-DK006][https://www.nxp.com/products/wireless/zigbee/advanced-development-kit-for-jn5189-88:jn5189-dk006] hardware platform.
+This directory contains example platform drivers for the [NXP JN5189][jn5189] based on [JN5189-DK006][jn5189-dk006] hardware platform.
The example platform drivers are intended to present the minimal code necessary to support OpenThread. As a result, the example platform drivers do not necessarily highlight the platform's full capabilities.
@@ -19,7 +19,7 @@
If a network connection timeout is encountered, re-run the script.
-Python-pip is also required for the build. User can install it by running "sudo apt-get install Python-pip" in bash. After installing Python-pip, execute "pip install PyCryptodome" in bash. This is needed for signing the built binary in order to load it on the board. Also, pycrypto "pip install pycrypto" is required for PKCS1.
+Python-pip is also required for the build. User can install it by running "sudo apt-get install Python-pip" in bash. After installing Python-pip, execute "pip install pycryptodome" in bash. This is needed for signing the built binary in order to load it on the board. Also, pycrypto "pip install pycrypto" is required for PKCS1.
Windows 10 offers the possibility of running bash by installing "Ubuntu on Windows" from Microsoft Store. This application allows the user to use Ubuntu Terminal and run Ubuntu command line utilities including bash, ssh, git, apt and many more. If this option is used, it is recommended to add instructions for the path mapping in MCUXpresso IDE. This can be done after adding the project to the workspace by going to Run->"Debug Configuration"->"C/C++(NXP Semiconductors) MCU Application"->Source->Add. Then the user should create a path mapping such that MCUXpresso IDE will find the mount point for the "Ubuntu in Windows" subsystem. For example, user can enter compilation path recognized by Ubuntu as /mnt/c/<path-to-openthread>, while equivalent "Local file system path" is C:/<path-to-openthread>. This example assumes that the openthread package is installed on the C drive.
@@ -39,13 +39,13 @@
OpenThread example application compiled binaries can be found in `<path-to-openthread>/output/jn5189/bin` and include FTD (Full Thread Device) and MTD (Minimal Thread Device) variants of CLI and NCP applications. The compiled binaries can be flashed onto the JN5189 using MCUXpresso IDE. This requires the following steps:
-1. Import the JN5189 SDK into MCUXpresso IDE. This can be done by dragging and dropping the SDK archive into MCUXpresso IDE's Installed SDKs tab. The archive for SDK_2.6.0_JN5189DK6 can be downloaded from https://mcuxpresso.nxp.com.
+1. Import the JN5189 SDK into MCUXpresso IDE. This can be done by dragging and dropping the SDK archive into MCUXpresso IDE's Installed SDKs tab. The archive for SDK_2.6.0_JN5189DK6 is available for download at https://mcuxpresso.nxp.com/en/welcome
2. In MCUXpresso IDE, go to File->Import->C/C++->"Existing Code as Makefile Project" and click Next.
-3. Select the OpenThread folder as the "Existing Code Location". In the "Toolchain for Indexer Settings" list, be sure to keep the setting to "none". Click Finish.
+3. Select the OpenThread folder as the "Existing Code Location". In the "Toolchain for Indexer Settings" list, be sure to keep the setting to <none>. Click Finish.
4. Right click on the newly created openthread project in the Workspace and go to Properties->"C/C++ Build"->"MCU Settings". Select the JN518x from the SDK MCUs list.
5. Go to C/C++ Build->"Tool Chain Editor" and untick the "Display compatible toolchains only" checkbox. In the drop-down menu named "Current toolchain", select "NXP MCU Tools". Click "Apply and Close".
6. Right click on the openthread project and select "Debug As"->"MCUXpresso IDE LinkServer (inc. CMSIS-DAP) probes"
-7. A window to select the binary will appear. Select "output/jn5189/bin/ot-<application>" and click Ok. Ignore the error message.
+7. A window to select the binary will appear. Select "output/jn5189/bin/ot-<application>" and click Ok.
8. Under the menu bar, towards the center of the screen, there is a green bug icon with a drop-down arrow next to it. Click on the arrow and select "Debug Configurations".
9. In the right side of the Debug Configurations window, go to "C/C++ (NXP Semiconductors) MCU Application"->"openthread LinkServer Default".
10. Make sure that in the "C/C++ Application:" text box contains "output\jn5189\bin\ot-<application>" path.
@@ -123,7 +123,3 @@
For a list of all available commands, visit [OpenThread CLI Reference README.md][cli].
[cli]: https://github.com/openthread/openthread/blob/master/src/cli/README.md
-
-## Known limitations
-
-While running the build process in "Ubuntu on Windows" bash, user can encounter build errors from unknown reasons. The current workaround is to re-run the "make -f examples/Makefile-jn5189" command. NCP applications have not been tested.
diff --git a/examples/platforms/jn5189/jn5189-mbedtls-config.h b/examples/platforms/k32w/jn5189/jn5189-mbedtls-config.h
similarity index 100%
rename from examples/platforms/jn5189/jn5189-mbedtls-config.h
rename to examples/platforms/k32w/jn5189/jn5189-mbedtls-config.h
diff --git a/examples/platforms/jn5189/jn5189.ld b/examples/platforms/k32w/jn5189/jn5189.ld
similarity index 99%
rename from examples/platforms/jn5189/jn5189.ld
rename to examples/platforms/k32w/jn5189/jn5189.ld
index 76cb4b3..44608e8 100755
--- a/examples/platforms/jn5189/jn5189.ld
+++ b/examples/platforms/k32w/jn5189/jn5189.ld
@@ -80,6 +80,7 @@
FREESCALE_PROD_DATA_BASE_ADDR = m_fsl_prodInfo_start;
INT_STORAGE_SECTOR_SIZE = m_sector_size;
+m_app_size = 0x48000;
ENTRY(ResetISR)
diff --git a/examples/platforms/jn5189/openthread-core-jn5189-config-check.h b/examples/platforms/k32w/jn5189/openthread-core-jn5189-config-check.h
similarity index 100%
rename from examples/platforms/jn5189/openthread-core-jn5189-config-check.h
rename to examples/platforms/k32w/jn5189/openthread-core-jn5189-config-check.h
diff --git a/examples/platforms/jn5189/openthread-core-jn5189-config.h b/examples/platforms/k32w/jn5189/openthread-core-jn5189-config.h
similarity index 88%
rename from examples/platforms/jn5189/openthread-core-jn5189-config.h
rename to examples/platforms/k32w/jn5189/openthread-core-jn5189-config.h
index 0e994ea..b9df980 100755
--- a/examples/platforms/jn5189/openthread-core-jn5189-config.h
+++ b/examples/platforms/k32w/jn5189/openthread-core-jn5189-config.h
@@ -115,9 +115,6 @@
* Define to 1 if you want to use JN589 Flash implementation.
*
*/
-#ifdef OPENTHREAD_SETTINGS_RAM
-#undef OPENTHREAD_SETTINGS_RAM
-#endif
#define OPENTHREAD_SETTINGS_RAM 1
/**
@@ -129,6 +126,16 @@
#define OPENTHREAD_CONFIG_NCP_TX_BUFFER_SIZE 1024
/**
+ * @def OPENTHREAD_CONFIG_HEAP_INTERNAL_SIZE
+ *
+ * The size of heap buffer when DTLS is enabled.
+ *
+ */
+#ifndef OPENTHREAD_CONFIG_HEAP_INTERNAL_SIZE
+#define OPENTHREAD_CONFIG_HEAP_INTERNAL_SIZE (2048 * sizeof(void *))
+#endif
+
+/**
* @def OPENTHREAD_CONFIG_COAP_API_ENABLE
*
* Define to 1 to enable the CoAP API.
@@ -137,14 +144,6 @@
#define OPENTHREAD_CONFIG_COAP_API_ENABLE 1
/**
- * @def OPENTHREAD_CONFIG_COAP_SECURE_API_ENABLE
- *
- * Define to 1 to enable the CoAP Secure API.
- *
- */
-#define OPENTHREAD_CONFIG_COAP_SECURE_API_ENABLE 1
-
-/**
* @def OPENTHREAD_CONFIG_JOINER_ENABLE
*
* Define to 1 to enable Joiner support.
@@ -191,4 +190,25 @@
*
*/
#define OPENTHREAD_CONFIG_DHCP6_SERVER_ENABLE 1
+
+/**
+ * @def OPENTHREAD_CONFIG_TIME_SYNC_ENABLE
+ *
+ * Define as 1 to enable the time synchronization service feature.
+ *
+ */
+#ifndef OPENTHREAD_CONFIG_TIME_SYNC_ENABLE
+#define OPENTHREAD_CONFIG_TIME_SYNC_ENABLE 0
+#endif
+
+/**
+ * @def OPENTHREAD_CONFIG_DIAG_ENABLE
+ *
+ * Define as 1 to enable the diag feature.
+ *
+ */
+#ifndef OPENTHREAD_CONFIG_DIAG_ENABLE
+#define OPENTHREAD_CONFIG_DIAG_ENABLE 0
+#endif
+
#endif // OPENTHREAD_CORE_JN5189_CONFIG_H_
diff --git a/examples/platforms/k32w/k32w061/Makefile.am b/examples/platforms/k32w/k32w061/Makefile.am
new file mode 100755
index 0000000..31fd19f
--- /dev/null
+++ b/examples/platforms/k32w/k32w061/Makefile.am
@@ -0,0 +1,142 @@
+#
+# Copyright (c) 2019, The OpenThread Authors.
+# Copyright (c) 2019, NXP.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+# 3. Neither the name of the copyright holder nor the
+# names of its contributors may be used to endorse or promote products
+# derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+include $(abs_top_nlbuild_autotools_dir)/automake/pre.am
+
+lib_LIBRARIES = \
+ libopenthread-k32w061_plat.a \
+ libopenthread-k32w061_sdk.a
+ $(NULL)
+
+# Do not enable -pedantic-errors for k32w061 driver library
+override CFLAGS := $(filter-out -pedantic-errors,$(CFLAGS))
+override CXXFLAGS := $(filter-out -pedantic-errors,$(CXXFLAGS))
+
+# Do not enable -Wcast-align for k32w061 driver library
+override CFLAGS := $(filter-out -Wcast-align,$(CFLAGS))
+override CXXFLAGS := $(filter-out -Wcast-align,$(CXXFLAGS))
+
+LIB_FLAGS = \
+ -DCPU_K32W061HN \
+ -DCPU_JN518X \
+ -DCPU_JN518X_REV=2 \
+ -DJENNIC_CHIP_FAMILY_JN518x \
+ -DJENNIC_CHIP_FAMILY_NAME=_JN518x \
+ -DUSE_RTOS=0 \
+ -DgPWR_LDOMEM_0_9V_PD=0 \
+ -DNO_SYSCORECLK_UPD=0 \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/examples/platforms \
+ -I$(top_srcdir)/src/core \
+ -I$(top_srcdir)/third_party/nxp \
+ -I$(top_srcdir)/third_party/nxp/K32W061DK6 \
+ -I$(top_srcdir)/third_party/nxp/K32W061DK6/devices/K32W061 \
+ -I$(top_srcdir)/third_party/nxp/K32W061DK6/middleware/mbedtls/port/ksdk \
+ -I$(top_srcdir)/third_party/nxp/K32W061DK6/components/serial_manager \
+ -I$(top_srcdir)/third_party/nxp/K32W061DK6/components/uart \
+ -I$(top_srcdir)/third_party/nxp/K32W061DK6/devices/K32W061/drivers \
+ -I$(top_srcdir)/third_party/nxp/K32W061DK6/devices/K32W061/utilities/debug_console \
+ -I$(top_srcdir)/third_party/nxp/K32W061DK6/devices/K32W061/utilities/str \
+ -I$(top_srcdir)/third_party/nxp/K32W061DK6/CMSIS/Include \
+ -I$(top_srcdir)/third_party/nxp/K32W061DK6/middleware/wireless/ieee-802.15.4/uMac/Include \
+ -I$(top_srcdir)/third_party/nxp/K32W061DK6/middleware/wireless/framework/XCVR/DK6/Build/Include \
+ -I$(top_srcdir)/third_party/nxp/K32W061DK6/middleware/wireless/framework/XCVR/DK6 \
+ -I$(top_srcdir)/third_party/nxp/K32W061DK6/middleware/wireless/framework/Common/ \
+ -I$(top_srcdir)/third_party/nxp/K32W061DK6/boards/k32w061dk6/wireless_examples/openthread/enablement \
+ -Wno-unknown-pragmas \
+ -Wno-sign-compare \
+ -Wno-unused-function \
+ -Wno-unused-parameter \
+ -Wno-empty-body \
+ $(NULL)
+
+libopenthread_k32w061_sdk_a_CPPFLAGS = \
+ $(LIB_FLAGS) \
+ $(NULL)
+
+libopenthread_k32w061_plat_a_CPPFLAGS = \
+ $(LIB_FLAGS) \
+ $(NULL)
+
+PLATFORM_SOURCES = \
+ src/alarm.c \
+ src/diag.c \
+ src/flash.c \
+ src/logging.c \
+ src/misc.c \
+ src/radio.c \
+ src/entropy.c \
+ src/system.c \
+ src/uart.c \
+ src/settings_k32w.c \
+ @top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/utilities/fsl_assert.c \
+ @top_builddir@/third_party/nxp/K32W061DK6/middleware/mbedtls/port/ksdk/aes_alt.c \
+ @top_builddir@/third_party/nxp/K32W061DK6/middleware/mbedtls/port/ksdk/ksdk_mbedtls.c \
+ $(NULL)
+
+libopenthread_k32w061_sdk_a_SOURCES = \
+ @top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/mcuxpresso/startup_k32w061.c \
+ @top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/system_K32W061.c \
+ @top_builddir@/third_party/nxp/K32W061DK6/boards/k32w061dk6/wireless_examples/openthread/enablement/pin_mux.c \
+ @top_builddir@/third_party/nxp/K32W061DK6/boards/k32w061dk6/wireless_examples/openthread/enablement/clock_config.c \
+ @top_builddir@/third_party/nxp/K32W061DK6/components/serial_manager/serial_manager.c \
+ @top_builddir@/third_party/nxp/K32W061DK6/components/serial_manager/serial_port_uart.c \
+ @top_builddir@/third_party/nxp/K32W061DK6/components/uart/usart_adapter.c \
+ @top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_gpio.c \
+ @top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_clock.c \
+ @top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_ctimer.c \
+ @top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_wtimer.c \
+ @top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_flash.c \
+ @top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_usart.c \
+ @top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_rng.c \
+ @top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_flexcomm.c \
+ @top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_reset.c \
+ @top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_power.c \
+ @top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_aes.c \
+ @top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_sha.c \
+ @top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/utilities/debug_console/fsl_debug_console.c \
+ @top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/utilities/str/fsl_str.c \
+ @top_builddir@/third_party/nxp/K32W061DK6/middleware/wireless/framework/Common/MicroInt_arm_sdk2.c \
+ $(NULL)
+
+libopenthread_k32w061_plat_a_SOURCES = \
+ $(PLATFORM_SOURCES) \
+ $(NULL)
+
+PRETTY_FILES = \
+ $(PLATFORM_SOURCES) \
+ $(NULL)
+
+Dash = -
+libopenthread_k32w061_sdk_a_LIBADD = \
+ $(shell find $(top_builddir)/examples/platforms/utils $(Dash)type f $(Dash)name "*.o")
+libopenthread_k32w061_plat_a_LIBADD = \
+ $(shell find $(top_builddir)/examples/platforms/utils $(Dash)type f $(Dash)name "*.o")
+
+include $(abs_top_nlbuild_autotools_dir)/automake/post.am
diff --git a/examples/platforms/jn5189/Makefile.platform.am b/examples/platforms/k32w/k32w061/Makefile.platform.am
similarity index 73%
copy from examples/platforms/jn5189/Makefile.platform.am
copy to examples/platforms/k32w/k32w061/Makefile.platform.am
index 7e58e1a..b79dbd1 100755
--- a/examples/platforms/jn5189/Makefile.platform.am
+++ b/examples/platforms/k32w/k32w061/Makefile.platform.am
@@ -1,5 +1,6 @@
#
# Copyright (c) 2019, The OpenThread Authors.
+# Copyright (c) 2019, NXP.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -27,17 +28,16 @@
#
#
-# JN5189 platform-specific Makefile
+# K32W061 platform-specific Makefile
#
-LDADD_COMMON += \
- $(top_builddir)/examples/platforms/jn5189/libopenthread-jn5189_plat.a \
- $(top_builddir)/examples/platforms/jn5189/libopenthread-jn5189_sdk.a \
- $(top_srcdir)/third_party/nxp/JN5189/libraries/libMiniMac.a \
- $(top_srcdir)/third_party/nxp/JN5189/libraries/libRadio.a \
- $(top_srcdir)/third_party/nxp/JN5189/libraries/libMicroSpecific_JN518x.a \
+LDADD_COMMON += \
+ $(top_builddir)/examples/platforms/k32w/libopenthread-k32w061_plat.a \
+ $(top_builddir)/examples/platforms/k32w/libopenthread-k32w061_sdk.a \
+ $(top_srcdir)/third_party/nxp/K32W061DK6/middleware/wireless/ieee-802.15.4/lib/libMiniMac.a \
+ $(top_srcdir)/third_party/nxp/K32W061DK6/middleware/wireless/framework/XCVR/lib/libRadio.a \
$(NULL)
-LDFLAGS_COMMON += \
- -T $(top_srcdir)/examples/platforms/jn5189/jn5189.ld \
+LDFLAGS_COMMON += \
+ -T $(top_srcdir)/examples/platforms/k32w/k32w061/k32w061.ld \
$(NULL)
diff --git a/examples/platforms/jn5189/README.md b/examples/platforms/k32w/k32w061/README.md
similarity index 77%
copy from examples/platforms/jn5189/README.md
copy to examples/platforms/k32w/k32w061/README.md
index b1f67b4..281ef21 100755
--- a/examples/platforms/jn5189/README.md
+++ b/examples/platforms/k32w/k32w061/README.md
@@ -1,6 +1,6 @@
-# OpenThread on NXP JN5189 Example
+# OpenThread on NXP K32W061 Example
-This directory contains example platform drivers for the [NXP JN5189][https://www.nxp.com/products/wireless/thread/jn5189-88-t-high-performance-and-ultra-low-power-mcus-for-zigbee-and-thread-with-built-in-nfc-option:jn5189_88_t] based on [JN5189-DK006][https://www.nxp.com/products/wireless/zigbee/advanced-development-kit-for-jn5189-88:jn5189-dk006] hardware platform.
+This directory contains example platform drivers for the [NXP K32W061][k32w061] based on [K32W061-DK006][k32w061-dk006] hardware platform.
The example platform drivers are intended to present the minimal code necessary to support OpenThread. As a result, the example platform drivers do not necessarily highlight the platform's full capabilities.
@@ -19,7 +19,7 @@
If a network connection timeout is encountered, re-run the script.
-Python-pip is also required for the build. User can install it by running "sudo apt-get install Python-pip" in bash. After installing Python-pip, execute "pip install PyCryptodome" in bash. This is needed for signing the built binary in order to load it on the board. Also, pycrypto "pip install pycrypto" is required for PKCS1.
+Python-pip is also required for the build. User can install it by running "sudo apt-get install python-pip" in bash. After installing Python-pip, execute "pip install pycryptodome" in bash. This is needed for signing the built binary in order to load it on the board. Also, pycrypto "pip install pycrypto" is required for PKCS1.
Windows 10 offers the possibility of running bash by installing "Ubuntu on Windows" from Microsoft Store. This application allows the user to use Ubuntu Terminal and run Ubuntu command line utilities including bash, ssh, git, apt and many more. If this option is used, it is recommended to add instructions for the path mapping in MCUXpresso IDE. This can be done after adding the project to the workspace by going to Run->"Debug Configuration"->"C/C++(NXP Semiconductors) MCU Application"->Source->Add. Then the user should create a path mapping such that MCUXpresso IDE will find the mount point for the "Ubuntu in Windows" subsystem. For example, user can enter compilation path recognized by Ubuntu as /mnt/c/<path-to-openthread>, while equivalent "Local file system path" is C:/<path-to-openthread>. This example assumes that the openthread package is installed on the C drive.
@@ -28,27 +28,27 @@
```bash
$ cd <path-to-openthread>
$ ./bootstrap
-$ make -f examples/Makefile-jn5189
+$ make -f examples/Makefile-k32w061
```
-After a successful build, the `elf` files are found in `<path-to-openthread>/output/jn5189/bin`.
+After a successful build, the `elf` files are found in `<path-to-openthread>/output/k32w061/bin`.
## Flash Binaries
Connect to the board by plugging a mini-USB cable to the connector marked with TARGET on the DK6 board. This connector is situated on the same side with the power connector.
-OpenThread example application compiled binaries can be found in `<path-to-openthread>/output/jn5189/bin` and include FTD (Full Thread Device) and MTD (Minimal Thread Device) variants of CLI and NCP applications. The compiled binaries can be flashed onto the JN5189 using MCUXpresso IDE. This requires the following steps:
+OpenThread example application compiled binaries can be found in `<path-to-openthread>/output/k32w061/bin` and include FTD (Full Thread Device) and MTD (Minimal Thread Device) variants of CLI and NCP applications. The compiled binaries can be flashed onto the K32W061 using MCUXpresso IDE. This requires the following steps:
-1. Import the JN5189 SDK into MCUXpresso IDE. This can be done by dragging and dropping the SDK archive into MCUXpresso IDE's Installed SDKs tab. The archive for SDK_2.6.0_JN5189DK6 can be downloaded from https://mcuxpresso.nxp.com.
+1. Import the K32W061 SDK into MCUXpresso IDE. This can be done by dragging and dropping the SDK archive into MCUXpresso IDE's Installed SDKs tab. The archive for SDK_2.6.0_K32W061DK6 is available for download at https://mcuxpresso.nxp.com/en/welcome
2. In MCUXpresso IDE, go to File->Import->C/C++->"Existing Code as Makefile Project" and click Next.
-3. Select the OpenThread folder as the "Existing Code Location". In the "Toolchain for Indexer Settings" list, be sure to keep the setting to "none". Click Finish.
+3. Select the OpenThread folder as the "Existing Code Location". In the "Toolchain for Indexer Settings" list, be sure to keep the setting to <none>. Click Finish.
4. Right click on the newly created openthread project in the Workspace and go to Properties->"C/C++ Build"->"MCU Settings". Select the JN518x from the SDK MCUs list.
5. Go to C/C++ Build->"Tool Chain Editor" and untick the "Display compatible toolchains only" checkbox. In the drop-down menu named "Current toolchain", select "NXP MCU Tools". Click "Apply and Close".
6. Right click on the openthread project and select "Debug As"->"MCUXpresso IDE LinkServer (inc. CMSIS-DAP) probes"
-7. A window to select the binary will appear. Select "output/jn5189/bin/ot-<application>" and click Ok. Ignore the error message.
+7. A window to select the binary will appear. Select "output/k32w061/bin/ot-<application>" and click Ok.
8. Under the menu bar, towards the center of the screen, there is a green bug icon with a drop-down arrow next to it. Click on the arrow and select "Debug Configurations".
9. In the right side of the Debug Configurations window, go to "C/C++ (NXP Semiconductors) MCU Application"->"openthread LinkServer Default".
-10. Make sure that in the "C/C++ Application:" text box contains "output\jn5189\bin\ot-<application>" path.
+10. Make sure that in the "C/C++ Application:" text box contains "output\k32w061\bin\ot-<application>" path.
11. Go to "GUI Flash Tool" tab. In "Target Operations"->Program->Options, select "bin" as the "Format to use for programming". Make sure the "Base address" is 0x0.
12. Click Debug.
13. A pop-up window entitled "Errors in Workspace" will appear. Click Proceed.
@@ -123,7 +123,3 @@
For a list of all available commands, visit [OpenThread CLI Reference README.md][cli].
[cli]: https://github.com/openthread/openthread/blob/master/src/cli/README.md
-
-## Known limitations
-
-While running the build process in "Ubuntu on Windows" bash, user can encounter build errors from unknown reasons. The current workaround is to re-run the "make -f examples/Makefile-jn5189" command. NCP applications have not been tested.
diff --git a/examples/platforms/k32w/k32w061/k32w061-mbedtls-config.h b/examples/platforms/k32w/k32w061/k32w061-mbedtls-config.h
new file mode 100755
index 0000000..c82b351
--- /dev/null
+++ b/examples/platforms/k32w/k32w061/k32w061-mbedtls-config.h
@@ -0,0 +1,248 @@
+/*
+ * Copyright (c) 2019, The OpenThread Authors.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef K32W061_MBEDTLS_CONFIG_H
+#define K32W061_MBEDTLS_CONFIG_H
+
+#if defined(MBEDTLS_ECP_WINDOW_SIZE)
+#undef MBEDTLS_ECP_WINDOW_SIZE
+#define MBEDTLS_ECP_WINDOW_SIZE 4 /**< Maximum window size used */
+#endif
+
+#if defined(MBEDTLS_ECP_FIXED_POINT_OPTIM)
+#undef MBEDTLS_ECP_FIXED_POINT_OPTIM
+#define MBEDTLS_ECP_FIXED_POINT_OPTIM 1 /**< Enable fixed-point speed-up */
+#endif
+
+/**
+ * \def MBEDTLS_AES_ALT
+ *
+ * Enable hardware acceleration for the AES block cipher
+ *
+ * See MBEDTLS_AES_C for more information.
+ */
+#define MBEDTLS_AES_ALT
+
+#if defined(MBEDTLS_AES_ALT)
+/**************************** KSDK ********************************************/
+#include "fsl_device_registers.h"
+
+/* Enable LTC use in library if there is LTC on chip. */
+#if defined(FSL_FEATURE_SOC_LTC_COUNT) && (FSL_FEATURE_SOC_LTC_COUNT > 0)
+#include "fsl_ltc.h"
+
+#define LTC_INSTANCE LTC0 /* LTC base register.*/
+
+#if FSL_FEATURE_LTC_HAS_SHA
+#define MBEDTLS_FREESCALE_LTC_SHA1 /* Enable use of LTC SHA.*/
+#define MBEDTLS_FREESCALE_LTC_SHA256 /* Enable use of LTC SHA256.*/
+#endif
+#if defined(FSL_FEATURE_LTC_HAS_DES) && FSL_FEATURE_LTC_HAS_DES
+#define MBEDTLS_FREESCALE_LTC_DES /* Enable use of LTC DES.*/
+#endif
+#define MBEDTLS_FREESCALE_LTC_AES /* Enable use of LTC AES.*/
+#if defined(FSL_FEATURE_LTC_HAS_GCM) && FSL_FEATURE_LTC_HAS_GCM
+#define MBEDTLS_FREESCALE_LTC_AES_GCM /* Enable use of LTC AES GCM.*/
+#endif
+#if defined(FSL_FEATURE_LTC_HAS_PKHA) && FSL_FEATURE_LTC_HAS_PKHA
+#define MBEDTLS_FREESCALE_LTC_PKHA /* Enable use of LTC PKHA.*/
+#define FREESCALE_PKHA_INT_MAX_BYTES 256
+#endif
+#endif
+
+/* Enable MMCAU use in library if there is MMCAU on chip. */
+#if defined(FSL_FEATURE_SOC_MMCAU_COUNT) && (FSL_FEATURE_SOC_MMCAU_COUNT > 0)
+#include "fsl_mmcau.h"
+
+#define MBEDTLS_FREESCALE_MMCAU_MD5 /* Enable use of MMCAU MD5.*/
+#define MBEDTLS_FREESCALE_MMCAU_SHA1 /* Enable use of MMCAU SHA1.*/
+#define MBEDTLS_FREESCALE_MMCAU_SHA256 /* Enable use of MMCAU SHA256.*/
+#define MBEDTLS_FREESCALE_MMCAU_DES /* Enable use of MMCAU DES, when LTC is disabled.*/
+#define MBEDTLS_FREESCALE_MMCAU_AES /* Enable use of MMCAU AES, when LTC is disabled.*/
+#endif
+
+/* Enable CAU3 use in library if there is CAU3 on chip. */
+#if defined(FSL_FEATURE_SOC_CAU3_COUNT) && (FSL_FEATURE_SOC_CAU3_COUNT > 0)
+#include "cau3_pkha.h"
+#include "fsl_cau3.h"
+
+#define MBEDTLS_CAU3_COMPLETION_SIGNAL CAU3_CC_CMD_EVT
+#define MBEDTLS_SHA256_ALT_NO_224
+
+#define MBEDTLS_FREESCALE_CAU3_AES /* Enable use of CAU3 AES.*/
+#define MBEDTLS_FREESCALE_CAU3_SHA256 /* Enable use of CAU3 SHA256.*/
+#define MBEDTLS_FREESCALE_CAU3_PKHA /* Enable use of CAU3 PKHA.*/
+#define FREESCALE_PKHA_INT_MAX_BYTES 512
+#endif
+
+#if defined(MBEDTLS_FREESCALE_LTC_PKHA) || defined(MBEDTLS_FREESCALE_CAU3_PKHA)
+/*
+ * This FREESCALE_PKHA_LONG_OPERANDS_ENABLE macro can be defined.
+ * In such a case both software and hardware algorithm for TFM is linked in.
+ * The decision for which algorithm is used is determined at runtime
+ * from size of inputs. If inputs and result can fit into LTC (see FREESCALE_PKHA_INT_MAX_BYTES)
+ * then we call hardware algorithm, otherwise we call software algorithm.
+ *
+ * Note that mbedTLS algorithms break modular operations unefficiently into two steps.
+ * First is normal operation, for example non-modular multiply, which can produce number
+ * with greater size than operands. Second is modular reduction.
+ * The implication of this is that if for example FREESCALE_PKHA_INT_MAX_BYTES is 256 (2048 bits),
+ * RSA-2048 still requires the FREESCALE_PKHA_LONG_OPERANDS_ENABLE macro to be defined,
+ * otherwise it fails at runtime.
+ */
+//#define FREESCALE_PKHA_LONG_OPERANDS_ENABLE
+#endif
+
+/* Enable AES use in library if there is AES on chip. */
+#if defined(FSL_FEATURE_SOC_AES_COUNT) && (FSL_FEATURE_SOC_AES_COUNT > 0)
+#include "fsl_aes.h"
+
+#define AES_INSTANCE AES0 /* AES base register.*/
+#define MBEDTLS_FREESCALE_LPC_AES /* Enable use of LPC AES.*/
+#define MBEDTLS_FREESCALE_LPC_AES_GCM /* Enable use of LPC AES GCM.*/
+
+#endif
+
+/* Enable SHA use in library if there is SHA on chip. */
+#if defined(FSL_FEATURE_SOC_SHA_COUNT) && (FSL_FEATURE_SOC_SHA_COUNT > 0)
+#include "fsl_sha.h"
+
+//#define SHA_INSTANCE SHA0 /* AES base register.*/
+#define MBEDTLS_FREESCALE_LPC_SHA1 /* Enable use of LPC SHA.*/
+//#define MBEDTLS_FREESCALE_LPC_SHA256 /* Enable use of LPC SHA256.*/
+
+#endif
+
+/* Define ALT MMCAU & LTC functions. Do not change it. */
+#if defined(MBEDTLS_FREESCALE_MMCAU_DES) || defined(MBEDTLS_FREESCALE_LTC_DES)
+#define MBEDTLS_DES_SETKEY_ENC_ALT
+#define MBEDTLS_DES_SETKEY_DEC_ALT
+#define MBEDTLS_DES_CRYPT_ECB_ALT
+#define MBEDTLS_DES3_CRYPT_ECB_ALT
+#endif
+#if defined(MBEDTLS_FREESCALE_LTC_DES)
+#define MBEDTLS_DES_CRYPT_CBC_ALT
+#define MBEDTLS_DES3_CRYPT_CBC_ALT
+#endif
+#if defined(MBEDTLS_FREESCALE_LTC_AES) || defined(MBEDTLS_FREESCALE_MMCAU_AES) || \
+ defined(MBEDTLS_FREESCALE_LPC_AES) || defined(MBEDTLS_FREESCALE_CAU3_AES)
+#define MBEDTLS_AES_SETKEY_ENC_ALT
+#define MBEDTLS_AES_SETKEY_DEC_ALT
+#define MBEDTLS_AES_ENCRYPT_ALT
+#define MBEDTLS_AES_DECRYPT_ALT
+#endif
+#if defined(MBEDTLS_FREESCALE_LTC_AES)
+#define MBEDTLS_AES_CRYPT_CBC_ALT
+#define MBEDTLS_AES_CRYPT_CTR_ALT
+#define MBEDTLS_CCM_CRYPT_ALT
+#endif
+#if defined(MBEDTLS_FREESCALE_LTC_AES_GCM) || defined(MBEDTLS_FREESCALE_LPC_AES_GCM)
+#define MBEDTLS_GCM_CRYPT_ALT
+#endif
+#if defined(MBEDTLS_FREESCALE_LTC_PKHA) || defined(MBEDTLS_FREESCALE_CAU3_PKHA)
+#define MBEDTLS_MPI_ADD_ABS_ALT
+#define MBEDTLS_MPI_SUB_ABS_ALT
+#define MBEDTLS_MPI_MUL_MPI_ALT
+#define MBEDTLS_MPI_MOD_MPI_ALT
+#define MBEDTLS_MPI_EXP_MOD_ALT
+#define MBEDTLS_MPI_GCD_ALT
+#define MBEDTLS_MPI_INV_MOD_ALT
+#define MBEDTLS_MPI_IS_PRIME_ALT
+#if defined(MBEDTLS_FREESCALE_LTC_PKHA)
+#define MBEDTLS_ECP_MUL_COMB_ALT
+#define MBEDTLS_ECP_ADD_ALT
+#endif
+#endif
+#if defined(MBEDTLS_FREESCALE_LTC_SHA1) || defined(MBEDTLS_FREESCALE_LPC_SHA1)
+#define MBEDTLS_SHA1_ALT
+#endif
+#if defined(MBEDTLS_FREESCALE_LTC_SHA256) || defined(MBEDTLS_FREESCALE_LPC_SHA256)
+//#define MBEDTLS_SHA256_ALT
+/*
+ * LPC SHA module does not support SHA-224.
+ *
+ * Since mbed TLS does not provide separate APIs for SHA-224 and SHA-256
+ * and SHA-224 is not widely used, this implementation provides HW accelerated SHA-256 only
+ * and SHA-224 is not available at all (calls will fail).
+ *
+ * To use SHA-224 on LPC, do not define MBEDTLS_SHA256_ALT and both SHA-224 and SHA-256 will use
+ * original mbed TLS software implementation.
+ */
+#if defined(MBEDTLS_FREESCALE_LPC_SHA256)
+#define MBEDTLS_SHA256_ALT_NO_224
+#endif
+#endif
+#if defined(MBEDTLS_FREESCALE_MMCAU_MD5)
+#define MBEDTLS_MD5_PROCESS_ALT
+#endif
+#if defined(MBEDTLS_FREESCALE_MMCAU_SHA1)
+#define MBEDTLS_SHA1_PROCESS_ALT
+#endif
+#if defined(MBEDTLS_FREESCALE_MMCAU_SHA256)
+#define MBEDTLS_SHA256_PROCESS_ALT
+#endif
+#if defined(MBEDTLS_FREESCALE_CAU3_SHA256)
+#define MBEDTLS_SHA256_PROCESS_ALT
+#endif
+#if defined(MBEDTLS_FREESCALE_CAU3_AES)
+#define MBEDTLS_AES_ALT_NO_192
+#endif
+#if defined(MBEDTLS_FREESCALE_LTC_AES)
+#if !defined(FSL_FEATURE_LTC_HAS_AES192) || !FSL_FEATURE_LTC_HAS_AES192
+#define MBEDTLS_AES_ALT_NO_192
+#endif
+#if !defined(FSL_FEATURE_LTC_HAS_AES256) || !FSL_FEATURE_LTC_HAS_AES256
+#define MBEDTLS_AES_ALT_NO_256
+#endif
+#endif
+#if defined(MBEDTLS_FREESCALE_LPC_AES)
+#define MBEDTLS_AES_CRYPT_CBC_ALT
+#define MBEDTLS_AES_CRYPT_CFB_ALT
+#define MBEDTLS_AES_CRYPT_CTR_ALT
+#endif
+#if defined(MBEDTLS_FREESCALE_LPC_SHA1)
+#define MBEDTLS_SHA1_PROCESS_ALT
+#endif
+#if defined(MBEDTLS_FREESCALE_LPC_SHA256)
+#define MBEDTLS_SHA256_PROCESS_ALT
+#endif
+
+#if USE_RTOS && defined(FSL_RTOS_FREE_RTOS)
+#include "FreeRTOS.h"
+
+void *pvPortCalloc(size_t num, size_t size); /*Calloc for HEAP3.*/
+
+#define MBEDTLS_PLATFORM_MEMORY
+#define MBEDTLS_PLATFORM_STD_CALLOC pvPortCalloc
+#define MBEDTLS_PLATFORM_STD_FREE vPortFree
+
+#endif /* USE_RTOS*/
+/**************************** KSDK end ****************************************/
+#endif /* MBEDTLS_AES_ALT || MBEDTLS_SHA256_ALT */
+
+#endif // K32W061_MBEDTLS_CONFIG_H
diff --git a/examples/platforms/jn5189/jn5189.ld b/examples/platforms/k32w/k32w061/k32w061.ld
similarity index 98%
copy from examples/platforms/jn5189/jn5189.ld
copy to examples/platforms/k32w/k32w061/k32w061.ld
index 76cb4b3..fbebd64 100755
--- a/examples/platforms/jn5189/jn5189.ld
+++ b/examples/platforms/k32w/k32w061/k32w061.ld
@@ -28,7 +28,7 @@
/**
* @file
- * GCC linker script for JN5189.
+ * GCC linker script for K32W061.
*/
/*
@@ -80,6 +80,7 @@
FREESCALE_PROD_DATA_BASE_ADDR = m_fsl_prodInfo_start;
INT_STORAGE_SECTOR_SIZE = m_sector_size;
+m_app_size = 0x48000;
ENTRY(ResetISR)
diff --git a/examples/platforms/jn5189/entropy.c b/examples/platforms/k32w/k32w061/openthread-core-k32w061-config-check.h
similarity index 63%
copy from examples/platforms/jn5189/entropy.c
copy to examples/platforms/k32w/k32w061/openthread-core-k32w061-config-check.h
index 5b8d0fe..95a1124 100755
--- a/examples/platforms/jn5189/entropy.c
+++ b/examples/platforms/k32w/k32w061/openthread-core-k32w061-config-check.h
@@ -26,45 +26,17 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-/**
- * @file
- * This file implements an entropy source based on TRNG.
- *
- */
+#ifndef OPENTHREAD_CORE_K32W061_CONFIG_CHECK_H_
+#define OPENTHREAD_CORE_K32W061_CONFIG_CHECK_H_
-#include "openthread/platform/entropy.h"
-#include "fsl_device_registers.h"
-#include "fsl_rng.h"
-#include <stdint.h>
-#include <stdlib.h>
-#include <utils/code_utils.h>
+#if OPENTHREAD_CONFIG_TIME_SYNC_ENABLE
+#error "Platform k32w061 doesn't support configuration option: OPENTHREAD_CONFIG_TIME_SYNC_ENABLE"
+#endif
-void JN5189RandomInit(void)
-{
- trng_config_t config;
- uint32_t seed;
+#ifndef RADIO_CONFIG_915MHZ_OQPSK_SUPPORT
+#if OPENTHREAD_CONFIG_RADIO_915MHZ_OQPSK_SUPPORT
+#error "Platform k32w061 not configured to support configuration option: OPENTHREAD_CONFIG_RADIO_915MHZ_OQPSK_SUPPORT"
+#endif
+#endif
- TRNG_GetDefaultConfig(&config);
- config.mode = trng_FreeRunning;
-
- otEXPECT(TRNG_Init(RNG, &config) == kStatus_Success);
-
- otEXPECT(TRNG_GetRandomData(RNG, &seed, sizeof(seed)) == kStatus_Success);
-
- srand(seed);
-
-exit:
- return;
-}
-
-otError otPlatEntropyGet(uint8_t *aOutput, uint16_t aOutputLength)
-{
- otError status = OT_ERROR_NONE;
-
- otEXPECT_ACTION((aOutput != NULL), status = OT_ERROR_INVALID_ARGS);
-
- otEXPECT_ACTION(TRNG_GetRandomData(RNG, aOutput, aOutputLength) == kStatus_Success, status = OT_ERROR_FAILED);
-
-exit:
- return status;
-}
+#endif /* OPENTHREAD_CORE_K32W061_CONFIG_CHECK_H_ */
diff --git a/examples/platforms/jn5189/openthread-core-jn5189-config.h b/examples/platforms/k32w/k32w061/openthread-core-k32w061-config.h
similarity index 81%
copy from examples/platforms/jn5189/openthread-core-jn5189-config.h
copy to examples/platforms/k32w/k32w061/openthread-core-k32w061-config.h
index 0e994ea..bd2efab 100755
--- a/examples/platforms/jn5189/openthread-core-jn5189-config.h
+++ b/examples/platforms/k32w/k32w061/openthread-core-k32w061-config.h
@@ -28,12 +28,12 @@
/**
* @file
- * This file includes jn5189 compile-time configuration constants
+ * This file includes k32w061 compile-time configuration constants
* for OpenThread.
*/
-#ifndef OPENTHREAD_CORE_JN5189_CONFIG_H_
-#define OPENTHREAD_CORE_JN5189_CONFIG_H_
+#ifndef OPENTHREAD_CORE_K32W061_CONFIG_H_
+#define OPENTHREAD_CORE_K32W061_CONFIG_H_
/**
* @def OPENTHREAD_CONFIG_LOG_OUTPUT
@@ -50,7 +50,7 @@
* The platform-specific string to insert into the OpenThread version string.
*
*/
-#define OPENTHREAD_CONFIG_PLATFORM_INFO "JN5189"
+#define OPENTHREAD_CONFIG_PLATFORM_INFO "K32W061"
/**
* @def SETTINGS_CONFIG_BASE_ADDRESS
@@ -112,12 +112,9 @@
/**
* @def OPENTHREAD_SETTINGS_RAM
*
- * Define to 1 if you want to use JN589 Flash implementation.
+ * Define to 1 if you want to use K32W061 Flash implementation.
*
*/
-#ifdef OPENTHREAD_SETTINGS_RAM
-#undef OPENTHREAD_SETTINGS_RAM
-#endif
#define OPENTHREAD_SETTINGS_RAM 1
/**
@@ -129,6 +126,16 @@
#define OPENTHREAD_CONFIG_NCP_TX_BUFFER_SIZE 1024
/**
+ * @def OPENTHREAD_CONFIG_HEAP_INTERNAL_SIZE
+ *
+ * The size of heap buffer when DTLS is enabled.
+ *
+ */
+#ifndef OPENTHREAD_CONFIG_HEAP_INTERNAL_SIZE
+#define OPENTHREAD_CONFIG_HEAP_INTERNAL_SIZE (2048 * sizeof(void *))
+#endif
+
+/**
* @def OPENTHREAD_CONFIG_COAP_API_ENABLE
*
* Define to 1 to enable the CoAP API.
@@ -137,14 +144,6 @@
#define OPENTHREAD_CONFIG_COAP_API_ENABLE 1
/**
- * @def OPENTHREAD_CONFIG_COAP_SECURE_API_ENABLE
- *
- * Define to 1 to enable the CoAP Secure API.
- *
- */
-#define OPENTHREAD_CONFIG_COAP_SECURE_API_ENABLE 1
-
-/**
* @def OPENTHREAD_CONFIG_JOINER_ENABLE
*
* Define to 1 to enable Joiner support.
@@ -191,4 +190,25 @@
*
*/
#define OPENTHREAD_CONFIG_DHCP6_SERVER_ENABLE 1
-#endif // OPENTHREAD_CORE_JN5189_CONFIG_H_
+
+/**
+ * @def OPENTHREAD_CONFIG_TIME_SYNC_ENABLE
+ *
+ * Define as 1 to enable the time synchronization service feature.
+ *
+ */
+#ifndef OPENTHREAD_CONFIG_TIME_SYNC_ENABLE
+#define OPENTHREAD_CONFIG_TIME_SYNC_ENABLE 0
+#endif
+
+/**
+ * @def OPENTHREAD_CONFIG_DIAG_ENABLE
+ *
+ * Define as 1 to enable the diag feature.
+ *
+ */
+#ifndef OPENTHREAD_CONFIG_DIAG_ENABLE
+#define OPENTHREAD_CONFIG_DIAG_ENABLE 0
+#endif
+
+#endif // OPENTHREAD_CORE_K32W061_CONFIG_H_
diff --git a/examples/platforms/jn5189/alarm.c b/examples/platforms/k32w/src/alarm.c
similarity index 96%
rename from examples/platforms/jn5189/alarm.c
rename to examples/platforms/k32w/src/alarm.c
index 40cc643..5919fd2 100755
--- a/examples/platforms/jn5189/alarm.c
+++ b/examples/platforms/k32w/src/alarm.c
@@ -32,6 +32,9 @@
*
*/
+/* Openthread configuration */
+#include OPENTHREAD_PROJECT_CORE_CONFIG_FILE
+
#include "fsl_clock.h"
#include "fsl_ctimer.h"
#include "fsl_device_registers.h"
@@ -63,7 +66,7 @@
static uint32_t sRemainingTicks;
#endif
-void JN5189AlarmInit(void)
+void K32WAlarmInit(void)
{
#if ALARM_USE_CTIMER
ctimer_config_t config;
@@ -99,7 +102,7 @@
#endif
}
-void JN5189AlarmClean(void)
+void K32WAlarmClean(void)
{
#if ALARM_USE_CTIMER
CTIMER_StopTimer(CTIMER0);
@@ -118,11 +121,11 @@
#endif
}
-void JN5189AlarmProcess(otInstance *aInstance)
+void K32WAlarmProcess(otInstance *aInstance)
{
if (sEventFired)
{
-#if OPENTHREAD_ENABLE_DIAG
+#if OPENTHREAD_CONFIG_DIAG_ENABLE
if (otPlatDiagModeGet())
{
diff --git a/examples/platforms/jn5189/diag.c b/examples/platforms/k32w/src/diag.c
similarity index 90%
rename from examples/platforms/jn5189/diag.c
rename to examples/platforms/k32w/src/diag.c
index bc11f24..8682fc6 100755
--- a/examples/platforms/jn5189/diag.c
+++ b/examples/platforms/k32w/src/diag.c
@@ -32,12 +32,15 @@
*
*/
+/* Openthread configuration */
+#include OPENTHREAD_PROJECT_CORE_CONFIG_FILE
+
#include <stdio.h>
#include <openthread/config.h>
#include <openthread/platform/alarm-milli.h>
#include <openthread/platform/radio.h>
-#if OPENTHREAD_ENABLE_DIAG
+#if OPENTHREAD_CONFIG_DIAG_ENABLE
/**
* Diagnostics mode variables.
@@ -45,13 +48,13 @@
*/
static bool sDiagMode = false;
-void otPlatDiagProcess(otInstance *aInstance, uint8_t aArgsLength, char *aArgs[], char *aOutput, size_t aOutputMaxLen)
+void otPlatDiagProcess(otInstance *aInstance, int argc, char *argv[], char *aOutput, size_t aOutputMaxLen)
{
OT_UNUSED_VARIABLE(aInstance);
- OT_UNUSED_VARIABLE(aArgsLength);
+ OT_UNUSED_VARIABLE(argc);
// Add more platform specific diagnostics features here.
- snprintf(aOutput, aOutputMaxLen, "diag feature '%s' is not supported\r\n", aArgs[0]);
+ snprintf(aOutput, aOutputMaxLen, "diag feature '%s' is not supported\r\n", argv[0]);
}
void otPlatDiagModeSet(bool aMode)
diff --git a/examples/platforms/jn5189/entropy.c b/examples/platforms/k32w/src/entropy.c
similarity index 98%
rename from examples/platforms/jn5189/entropy.c
rename to examples/platforms/k32w/src/entropy.c
index 5b8d0fe..1cadb22 100755
--- a/examples/platforms/jn5189/entropy.c
+++ b/examples/platforms/k32w/src/entropy.c
@@ -39,7 +39,7 @@
#include <stdlib.h>
#include <utils/code_utils.h>
-void JN5189RandomInit(void)
+void K32WRandomInit(void)
{
trng_config_t config;
uint32_t seed;
diff --git a/examples/platforms/jn5189/flash.c b/examples/platforms/k32w/src/flash.c
similarity index 90%
rename from examples/platforms/jn5189/flash.c
rename to examples/platforms/k32w/src/flash.c
index f20780b..32f843b 100755
--- a/examples/platforms/jn5189/flash.c
+++ b/examples/platforms/k32w/src/flash.c
@@ -26,11 +26,11 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
+#include "openthread/platform/flash.h"
#include "fsl_device_registers.h"
#include "fsl_flash.h"
-#include "openthread-core-jn5189-config.h"
+#include "openthread-core-config.h"
#include <utils/code_utils.h>
-#include <utils/flash.h>
#include "openthread/platform/alarm-milli.h"
#define USE_MEM_COPY_FOR_READ 0
@@ -50,8 +50,10 @@
static void copyFromFlash(uint8_t *pDst, uint8_t *pSrc, uint32_t cBytes);
static uint32_t blankCheckAndErase(uint8_t *pageAddr);
-otError utilsFlashInit(void)
+void otPlatFlashInit(otInstance *aInstance)
{
+ OT_UNUSED_VARIABLE(aInstance);
+
extern uint32_t __nv_storage_start_address;
extern uint32_t __nv_storage_end_address;
@@ -59,13 +61,6 @@
sNvFlashStartAddr = (uint32_t)&__nv_storage_start_address;
sNvFlashEndAddr = (uint32_t)&__nv_storage_end_address;
-
- return OT_ERROR_NONE;
-}
-
-uint32_t utilsFlashGetSize(void)
-{
- return sNvFlashEndAddr - sNvFlashStartAddr;
}
otError utilsFlashErasePage(uint32_t aAddress)
@@ -91,31 +86,17 @@
return error;
}
-otError utilsFlashStatusWait(uint32_t aTimeout)
-{
- otError error = OT_ERROR_BUSY;
- uint32_t start = otPlatAlarmMilliGetNow();
-
- do
- {
- if (FLASH->INT_STATUS & FLASH_DONE)
- {
- error = OT_ERROR_NONE;
- break;
- }
- } while (aTimeout && ((otPlatAlarmMilliGetNow() - start) < aTimeout));
-
- return error;
-}
-
-uint32_t utilsFlashWrite(uint32_t aAddress, uint8_t *aData, uint32_t aSize)
+void otPlatFlashWrite(otInstance *aInstance, uint8_t aSwapIndex, uint32_t aOffset, const void *aData, uint32_t aSize)
{
uint32_t result = 0;
status_t status;
- uint32_t address = aAddress;
+ uint32_t address = aOffset;
uint32_t alignAddr;
uint32_t bytes;
+ OT_UNUSED_VARIABLE(aInstance);
+ OT_UNUSED_VARIABLE(aSwapIndex);
+
/* Map address to NV Flash space and check boundaries */
if (mapToNvFlashAddress(&address))
{
@@ -182,13 +163,21 @@
}
exit:
- return result;
+ /* There are times when the result != 0.
+ * Use this workaround until we replace the flash code with the Packet Data Manager.
+ */
+ if (result)
+ {
+ result = 0;
+ }
}
-uint32_t utilsFlashRead(uint32_t aAddress, uint8_t *aData, uint32_t aSize)
+void otPlatFlashRead(otInstance *aInstance, uint8_t aSwapIndex, uint32_t aOffset, void *aData, uint32_t aSize)
{
- uint32_t address = aAddress;
- uint32_t result = 0;
+ uint32_t address = aOffset;
+
+ OT_UNUSED_VARIABLE(aInstance);
+ OT_UNUSED_VARIABLE(aSwapIndex);
/* Map address to NV Flash space and check boundaries */
if (mapToNvFlashAddress(&address))
@@ -197,11 +186,8 @@
if ((address + aSize) <= sNvFlashEndAddr)
{
copyFromFlash(aData, (uint8_t *)address, aSize);
- result = aSize;
}
}
-
- return result;
}
static bool mapToNvFlashAddress(uint32_t *aAddress)
diff --git a/examples/platforms/jn5189/logging.c b/examples/platforms/k32w/src/logging.c
similarity index 92%
rename from examples/platforms/jn5189/logging.c
rename to examples/platforms/k32w/src/logging.c
index 0f33c82..d2c55e9 100755
--- a/examples/platforms/jn5189/logging.c
+++ b/examples/platforms/k32w/src/logging.c
@@ -32,7 +32,7 @@
*
*/
-#include "platform-jn5189.h"
+#include "platform-k32w.h"
#include <openthread-core-config.h>
#include <utils/code_utils.h>
#include <openthread/config.h>
@@ -52,7 +52,7 @@
#define EOL_CHARS_LEN 2 /* Length of EOL */
/* static functions */
-static void JN5189LogOutput(const char *aFormat, va_list ap);
+static void K32WLogOutput(const char *aFormat, va_list ap);
/* static variables */
static char sTxBuffer[TX_BUFFER_SIZE + 1]; /* Transmit Buffer */
@@ -64,7 +64,7 @@
va_list ap;
va_start(ap, aFormat);
- JN5189LogOutput(aFormat, ap);
+ K32WLogOutput(aFormat, ap);
va_end(ap);
}
@@ -75,7 +75,7 @@
* @param[in] ap Variable List Argument
*
*/
-static void JN5189LogOutput(const char *aFormat, va_list ap)
+static void K32WLogOutput(const char *aFormat, va_list ap)
{
int len = 0;
@@ -83,7 +83,7 @@
otEXPECT(len >= 0);
memcpy(sTxBuffer + len, EOL_CHARS, EOL_CHARS_LEN);
len += EOL_CHARS_LEN;
- JN5189WriteBlocking((const uint8_t *)sTxBuffer, len);
+ K32WWriteBlocking((const uint8_t *)sTxBuffer, len);
exit:
return;
diff --git a/examples/platforms/jn5189/misc.c b/examples/platforms/k32w/src/misc.c
similarity index 100%
rename from examples/platforms/jn5189/misc.c
rename to examples/platforms/k32w/src/misc.c
diff --git a/examples/platforms/jn5189/platform-jn5189.h b/examples/platforms/k32w/src/platform-k32w.h
similarity index 86%
rename from examples/platforms/jn5189/platform-jn5189.h
rename to examples/platforms/k32w/src/platform-k32w.h
index 858614d..ec32664 100755
--- a/examples/platforms/jn5189/platform-jn5189.h
+++ b/examples/platforms/k32w/src/platform-k32w.h
@@ -32,8 +32,8 @@
*
*/
-#ifndef PLATFORM_KWJN5189_H_
-#define PLATFORM_KWJN5189_H_
+#ifndef PLATFORM_K32W_H_
+#define PLATFORM_K32W_H_
#include <openthread-core-config.h>
#include <openthread/config.h>
@@ -46,7 +46,7 @@
* This function initializes the alarm service used by OpenThread.
*
*/
-void JN5189AlarmInit(void);
+void K32WAlarmInit(void);
/**
* This function performs alarm driver processing.
@@ -54,13 +54,13 @@
* @param[in] aInstance The OpenThread instance structure.
*
*/
-void JN5189AlarmProcess(otInstance *aInstance);
+void K32WAlarmProcess(otInstance *aInstance);
/**
* This function initializes the radio service used by OpenThread.
*
*/
-void JN5189RadioInit(void);
+void K32WRadioInit(void);
/**
* This function performs radio driver processing.
@@ -68,19 +68,19 @@
* @param[in] aInstance The OpenThread instance structure.
*
*/
-void JN5189RadioProcess(otInstance *aInstance);
+void K32WRadioProcess(otInstance *aInstance);
/**
* This function initializes the random number service used by OpenThread.
*
*/
-void JN5189RandomInit(void);
+void K32WRandomInit(void);
/**
* This function performs UART driver processing.
*
*/
-void JN5189UartProcess(void);
+void K32WUartProcess(void);
/**
* This function performs UART Blocking Send
@@ -89,5 +89,5 @@
* @param[in] len Length of the above buffer
*
*/
-void JN5189WriteBlocking(const uint8_t *aBuf, uint32_t len);
-#endif // PLATFORM_JN5189_H_
+void K32WWriteBlocking(const uint8_t *aBuf, uint32_t len);
+#endif // PLATFORM_K32W_H_
diff --git a/examples/platforms/jn5189/radio.c b/examples/platforms/k32w/src/radio.c
similarity index 82%
rename from examples/platforms/jn5189/radio.c
rename to examples/platforms/k32w/src/radio.c
index 1acc339..d42fd86 100755
--- a/examples/platforms/jn5189/radio.c
+++ b/examples/platforms/k32w/src/radio.c
@@ -33,16 +33,15 @@
*/
/* Openthread configuration */
-#include "openthread-core-jn5189-config.h"
+#include OPENTHREAD_PROJECT_CORE_CONFIG_FILE
/* memcpy */
#include "string.h"
/* uMac, MMAC, Radio */
-#include "BbcAndPhyRegs.h"
#include "MMAC.h"
#include "MicroSpecific_arm_sdk2.h"
-#include "radio_jn518x.h"
+#include "radio.h"
/* Openthread general */
#include <utils/code_utils.h>
@@ -59,17 +58,17 @@
#define ALL_FFs_BYTE (0xFF)
-#define JN5189_RADIO_MIN_TX_POWER_DBM (-30)
-#define JN5189_RADIO_MAX_TX_POWER_DBM (15)
-#define JN5189_RADIO_RX_SENSITIVITY_DBM (-100)
-#define JN5189_RADIO_DEFAULT_CHANNEL (11)
+#define K32W_RADIO_MIN_TX_POWER_DBM (-30)
+#define K32W_RADIO_MAX_TX_POWER_DBM (15)
+#define K32W_RADIO_RX_SENSITIVITY_DBM (-100)
+#define K32W_RADIO_DEFAULT_CHANNEL (11)
#define US_PER_SYMBOL (16) /* Duration of a single symbol in [us] */
#define SYMBOLS_TO_US(symbols) ((symbols)*US_PER_SYMBOL)
#define US_TO_MILI_DIVIDER (1000)
-#define MAX_FP_ADDRS (10) /* max number of frame pending children */
-#define JN5189_RX_BUFFERS (8) /* max number of RX buffers */
+#define MAX_FP_ADDRS (10) /* max number of frame pending children */
+#define K32W_RX_BUFFERS (8) /* max number of RX buffers */
/* check IEEE Std. 802.15.4 - 2015: Table 8-81 - MAC sublayer constants */
#define MAC_TX_ATTEMPTS (4)
@@ -98,7 +97,7 @@
typedef struct
{
- tsRxFrameFormat *buffer[JN5189_RX_BUFFERS];
+ tsRxFrameFormat *buffer[K32W_RX_BUFFERS];
uint8_t head;
uint8_t tail;
bool isFull;
@@ -155,23 +154,23 @@
} frameConversionType;
/* Private functions declaration */
-static void JN5189ISR(uint32_t u32IntBitmap);
-static void JN5189ProcessMacHeader(tsRxFrameFormat *aRxFrame);
-static void JN5189ProcessRxFrames(otInstance *aInstance);
-static void JN5189ProcessTxFrame(otInstance *aInstance);
-static bool JN5189CheckIfFpRequired(tsRxFrameFormat *aRxFrame);
-static bool_t JN5189IsDataReq(tsRxFrameFormat *aRxFrame);
-static otError JN5189FrameConversion(tsRxFrameFormat * aMacFormatFrame,
- otRadioFrame * aOtFrame,
- frameConversionType convType);
-static void JN5189Copy(uint8_t *aFieldValue, uint8_t **aPsdu, uint8_t copySize, frameConversionType convType);
-static void JN5189ResetRxRingBuffer(rxRingBuffer *aRxRing);
-static void JN5189PushRxRingBuffer(rxRingBuffer *aRxRing, tsRxFrameFormat *aRxFrame);
-static tsRxFrameFormat *JN5189PopRxRingBuffer(rxRingBuffer *aRxRing);
-static bool JN5189IsEmptyRxRingBuffer(rxRingBuffer *aRxRing);
-static tsRxFrameFormat *JN5189GetFrame(tsRxFrameFormat *aRxFrame, uint8_t *aRxFrameIndex);
-static void JN5189EnableReceive(bool_t isNewFrameNeeded);
-static void JN5189RestartRx();
+static void K32WISR(uint32_t u32IntBitmap);
+static void K32WProcessMacHeader(tsRxFrameFormat *aRxFrame);
+static void K32WProcessRxFrames(otInstance *aInstance);
+static void K32WProcessTxFrame(otInstance *aInstance);
+static bool K32WCheckIfFpRequired(tsRxFrameFormat *aRxFrame);
+static bool_t K32WIsDataReq(tsRxFrameFormat *aRxFrame);
+static otError K32WFrameConversion(tsRxFrameFormat * aMacFormatFrame,
+ otRadioFrame * aOtFrame,
+ frameConversionType convType);
+static void K32WCopy(uint8_t *aFieldValue, uint8_t **aPsdu, uint8_t copySize, frameConversionType convType);
+static void K32WResetRxRingBuffer(rxRingBuffer *aRxRing);
+static void K32WPushRxRingBuffer(rxRingBuffer *aRxRing, tsRxFrameFormat *aRxFrame);
+static tsRxFrameFormat *K32WPopRxRingBuffer(rxRingBuffer *aRxRing);
+static bool K32WIsEmptyRxRingBuffer(rxRingBuffer *aRxRing);
+static tsRxFrameFormat *K32WGetFrame(tsRxFrameFormat *aRxFrame, uint8_t *aRxFrameIndex);
+static void K32WEnableReceive(bool_t isNewFrameNeeded);
+static void K32WRestartRx(void);
/* Private variables declaration */
static otRadioState sState = OT_RADIO_STATE_DISABLED;
@@ -192,7 +191,7 @@
static uint16_t sFpExtAddrMask; /* Mask - sFpExtAddr is valid */
static rxRingBuffer sRxRing; /* Receive Ring Buffer */
-static tsRxFrameFormat sRxFrame[JN5189_RX_BUFFERS]; /* RX Buffers */
+static tsRxFrameFormat sRxFrame[K32W_RX_BUFFERS]; /* RX Buffers */
static tsRxFrameFormat *sRxFrameInProcess; /* RX Frame currently in processing */
static bool_t sIsRxDisabled; /* TRUE if RX was disabled due to no RX bufs */
static uint8_t sRxFrameIndex; /* Index tracking the sRxFrame array */
@@ -247,10 +246,10 @@
memcpy((uint8_t *)&sCustomExtAddr, aIeeeEui64, sizeof(sCustomExtAddr));
}
-void JN5189RadioInit(void)
+void K32WRadioInit(void)
{
/* RX initialization */
- memset(sRxFrame, 0, sizeof(tsRxFrameFormat) * JN5189_RX_BUFFERS);
+ memset(sRxFrame, 0, sizeof(tsRxFrameFormat) * K32W_RX_BUFFERS);
sRxFrameIndex = 0;
/* TX initialization */
@@ -258,10 +257,10 @@
sRxOtFrame.mPsdu = sRxData;
}
-void JN5189RadioProcess(otInstance *aInstance)
+void K32WRadioProcess(otInstance *aInstance)
{
- JN5189ProcessRxFrames(aInstance);
- JN5189ProcessTxFrame(aInstance);
+ K32WProcessRxFrames(aInstance);
+ K32WProcessTxFrame(aInstance);
}
otRadioState otPlatRadioGetState(otInstance *aInstance)
@@ -321,10 +320,10 @@
{
OT_UNUSED_VARIABLE(aInstance);
- JN5189ResetRxRingBuffer(&sRxRing);
+ K32WResetRxRingBuffer(&sRxRing);
sRxFrameIndex = 0;
vMMAC_Enable();
- vMMAC_EnableInterrupts(JN5189ISR);
+ vMMAC_EnableInterrupts(K32WISR);
vMMAC_ConfigureInterruptSources(E_MMAC_INT_TX_COMPLETE | E_MMAC_INT_RX_HEADER | E_MMAC_INT_RX_COMPLETE);
vMMAC_ConfigureRadio();
vMMAC_SetTxParameters(MAC_TX_ATTEMPTS, MAC_TX_CSMA_MIN_BE, MAC_TX_CSMA_MAX_BE, MAC_TX_CSMA_MAX_BACKOFFS);
@@ -353,7 +352,7 @@
otEXPECT(otPlatRadioIsEnabled(aInstance));
- JN5189ResetRxRingBuffer(&sRxRing);
+ K32WResetRxRingBuffer(&sRxRing);
sRxFrameIndex = 0;
vMMAC_Disable();
sState = OT_RADIO_STATE_DISABLED;
@@ -425,7 +424,7 @@
* in the middle of a receive operation */
isNewFrameNeeded = FALSE;
}
- JN5189EnableReceive(isNewFrameNeeded);
+ K32WEnableReceive(isNewFrameNeeded);
exit:
return error;
@@ -438,7 +437,7 @@
sIsFpEnabled = aEnable;
}
-otError otPlatRadioAddSrcMatchShortEntry(otInstance *aInstance, uint16_t aShortAddress)
+otError otPlatRadioAddSrcMatchShortEntry(otInstance *aInstance, const uint16_t aShortAddress)
{
OT_UNUSED_VARIABLE(aInstance);
@@ -483,7 +482,7 @@
return error;
}
-otError otPlatRadioClearSrcMatchShortEntry(otInstance *aInstance, uint16_t aShortAddress)
+otError otPlatRadioClearSrcMatchShortEntry(otInstance *aInstance, const uint16_t aShortAddress)
{
OT_UNUSED_VARIABLE(aInstance);
@@ -567,13 +566,13 @@
eOptions |= E_MMAC_TX_USE_CCA;
}
- JN5189FrameConversion(&sTxMacFrame, aFrame, otToMacFrame);
+ K32WFrameConversion(&sTxMacFrame, aFrame, otToMacFrame);
/* stop rx is handled by uMac tx function */
vMMAC_StartMacTransmit(&sTxMacFrame.sFrameBody, eOptions);
/* Set RX buffer pointer for ACK */
- vREG_BbcWrite(REG_BBC_RXBUFAD, (uint32)&sRxAckFrame.sFrameBody);
+ vMMAC_SetRxFrame(&sRxAckFrame);
otPlatRadioTxStarted(aInstance, aFrame);
@@ -592,7 +591,7 @@
/* in RCP designs, the RSSI function is called while the radio is in
* OT_RADIO_STATE_RECEIVE. Turn off the radio before reading RSSI,
* otherwise we may end up waiting until a packet is received
- * (in i16Radio_JN518x_GetRSSI, while loop)
+ * (in i16Radio_GetRSSI, while loop)
*/
if (sState == OT_RADIO_STATE_RECEIVE)
@@ -602,15 +601,15 @@
stateChanged = TRUE;
}
- rssiValSigned = i16Radio_Jn518x_GetRSSI(0, FALSE, NULL);
+ rssiValSigned = i16Radio_GetRSSI(0, FALSE, NULL);
if (stateChanged)
{
sState = OT_RADIO_STATE_RECEIVE;
- JN5189EnableReceive(TRUE);
+ K32WEnableReceive(TRUE);
}
- rssiValSigned = i16Radio_Jn518x_BoundRssiValue(rssiValSigned);
+ rssiValSigned = i16Radio_BoundRssiValue(rssiValSigned);
/* RSSI reported by radio is in 1/4 dBm step,
* meaning values are 4 times larger than real dBm value.
@@ -681,13 +680,13 @@
sState = OT_RADIO_STATE_SLEEP;
/* trim the values to the radio capabilities */
- if (aPower < JN5189_RADIO_MIN_TX_POWER_DBM)
+ if (aPower < K32W_RADIO_MIN_TX_POWER_DBM)
{
- aPower = JN5189_RADIO_MIN_TX_POWER_DBM;
+ aPower = K32W_RADIO_MIN_TX_POWER_DBM;
}
- else if (aPower > JN5189_RADIO_MAX_TX_POWER_DBM)
+ else if (aPower > K32W_RADIO_MAX_TX_POWER_DBM)
{
- aPower = JN5189_RADIO_MAX_TX_POWER_DBM;
+ aPower = K32W_RADIO_MAX_TX_POWER_DBM;
}
/* save for later use */
@@ -701,8 +700,8 @@
}
else
{
- /* if the channel has not yet been initialized use JN5189_RADIO_DEFAULT_CHANNEL as default */
- vMMAC_SetChannelAndPower(JN5189_RADIO_DEFAULT_CHANNEL, aPower);
+ /* if the channel has not yet been initialized use K32W_RADIO_DEFAULT_CHANNEL as default */
+ vMMAC_SetChannelAndPower(K32W_RADIO_DEFAULT_CHANNEL, aPower);
}
sState = tempState;
@@ -729,7 +728,7 @@
{
OT_UNUSED_VARIABLE(aInstance);
- return JN5189_RADIO_RX_SENSITIVITY_DBM;
+ return K32W_RADIO_RX_SENSITIVITY_DBM;
}
/**
@@ -738,7 +737,7 @@
* @param[in] u32IntBitmap Bitmap telling which interrupt fired
*
*/
-static void JN5189ISR(uint32_t u32IntBitmap)
+static void K32WISR(uint32_t u32IntBitmap)
{
tsRxFrameFormat *pRxFrame = NULL;
@@ -752,28 +751,28 @@
if (u32IntBitmap & E_MMAC_INT_RX_HEADER)
{
/* go back one index from current frame index */
- pRxFrame = &sRxFrame[(sRxFrameIndex + JN5189_RX_BUFFERS - 1) % JN5189_RX_BUFFERS];
+ pRxFrame = &sRxFrame[(sRxFrameIndex + K32W_RX_BUFFERS - 1) % K32W_RX_BUFFERS];
/* FP processing first */
- JN5189ProcessMacHeader(pRxFrame);
+ K32WProcessMacHeader(pRxFrame);
/* RX interrupt fired so it's safe to consume the frame */
- JN5189PushRxRingBuffer(&sRxRing, pRxFrame);
+ K32WPushRxRingBuffer(&sRxRing, pRxFrame);
if (0 == (pRxFrame->sFrameBody.u16FCF & kFcfAckRequest))
{
- JN5189EnableReceive(TRUE);
+ K32WEnableReceive(TRUE);
}
}
else if (u32IntBitmap & E_MMAC_INT_RX_COMPLETE)
{
- JN5189EnableReceive(TRUE);
+ K32WEnableReceive(TRUE);
}
}
else
{
/* restart RX and keep same buffer as data received contains errors */
- JN5189EnableReceive(FALSE);
+ K32WEnableReceive(FALSE);
}
BOARD_LedDongleToggle();
@@ -785,21 +784,21 @@
uint32_t txErrors = u32MMAC_GetTxErrors();
sTxDone = TRUE;
- if (txErrors & REG_BBC_TXSTAT_CCAE_MASK)
+ if (txErrors & E_MMAC_TXSTAT_CCA_BUSY)
{
sTxStatus = OT_ERROR_CHANNEL_ACCESS_FAILURE;
}
- else if (txErrors & REG_BBC_TXSTAT_ACKE_MASK)
+ else if (txErrors & E_MMAC_TXSTAT_NO_ACK)
{
sTxStatus = OT_ERROR_NO_ACK;
}
- else if (txErrors & REG_BBC_TXSTAT_OOTE_MASK)
+ else if (txErrors & E_MMAC_TXSTAT_ABORTED)
{
sTxStatus = OT_ERROR_ABORT;
}
- else if ((txErrors & REG_BBC_TXSTAT_TXPCTO_MASK) || (txErrors & REG_BBC_TXSTAT_TXTO_MASK))
+ else if ((txErrors & E_MMAC_TXSTAT_TXPCTO) || (txErrors & E_MMAC_TXSTAT_TXTO))
{
- /* The JN518x has a TXTO timeout that we are using to catch and cope with the curious
+ /* The JN518x/K32W0x1 has a TXTO timeout that we are using to catch and cope with the curious
hang-up issue */
vMMAC_AbortRadio();
@@ -815,7 +814,7 @@
BOARD_LedDongleToggle();
sState = OT_RADIO_STATE_RECEIVE;
- JN5189EnableReceive(TRUE);
+ K32WEnableReceive(TRUE);
}
break;
@@ -831,7 +830,7 @@
* @param[in] aRxFrame Pointer to the latest received MAC packet
*
*/
-static void JN5189ProcessMacHeader(tsRxFrameFormat *aRxFrame)
+static void K32WProcessMacHeader(tsRxFrameFormat *aRxFrame)
{
/* check if frame pending processing is required */
if (aRxFrame && sIsFpEnabled)
@@ -844,9 +843,9 @@
aRxFrame->sFrameBody.u16SrcPAN = aRxFrame->sFrameBody.u16DestPAN;
}
- if (JN5189IsDataReq(aRxFrame))
+ if (K32WIsDataReq(aRxFrame))
{
- vREG_BbcWrite(REG_BBC_TXPEND, JN5189CheckIfFpRequired(aRxFrame));
+ vMMAC_SetTxPend(K32WCheckIfFpRequired(aRxFrame));
}
else
{
@@ -864,7 +863,7 @@
* @return TRUE aRxFrame is a MAC Data Request Frame
* @return FALSE aRxFrame is not a MAC Data Request Frame
*/
-static bool_t JN5189IsDataReq(tsRxFrameFormat *aRxFrame)
+static bool_t K32WIsDataReq(tsRxFrameFormat *aRxFrame)
{
bool_t isDataReq = FALSE;
uint8_t offset = 0;
@@ -921,7 +920,7 @@
* @return FALSE Frame Pending bit shouldn't be set in the reply
*
*/
-static bool JN5189CheckIfFpRequired(tsRxFrameFormat *aRxFrame)
+static bool K32WCheckIfFpRequired(tsRxFrameFormat *aRxFrame)
{
bool isFpRequired = FALSE;
uint16_t panId = aRxFrame->sFrameBody.u16SrcPAN;
@@ -966,14 +965,14 @@
*
* @param[in] aInstance Pointer to OT instance
*/
-static void JN5189ProcessRxFrames(otInstance *aInstance)
+static void K32WProcessRxFrames(otInstance *aInstance)
{
tsRxFrameFormat *pRxMacFormatFrame = NULL;
uint32_t savedInterrupts;
- while ((pRxMacFormatFrame = JN5189PopRxRingBuffer(&sRxRing)) != NULL)
+ while ((pRxMacFormatFrame = K32WPopRxRingBuffer(&sRxRing)) != NULL)
{
- if (OT_ERROR_NONE == JN5189FrameConversion(pRxMacFormatFrame, &sRxOtFrame, macToOtFrame))
+ if (OT_ERROR_NONE == K32WFrameConversion(pRxMacFormatFrame, &sRxOtFrame, macToOtFrame))
{
otPlatRadioReceiveDone(aInstance, &sRxOtFrame, OT_ERROR_NONE);
}
@@ -987,7 +986,7 @@
sRxFrameInProcess = NULL;
if (sIsRxDisabled)
{
- JN5189EnableReceive(TRUE);
+ K32WEnableReceive(TRUE);
}
MICRO_RESTORE_INTERRUPTS(savedInterrupts);
}
@@ -998,14 +997,14 @@
*
* @param[in] aInstance Pointer to OT instance
*/
-static void JN5189ProcessTxFrame(otInstance *aInstance)
+static void K32WProcessTxFrame(otInstance *aInstance)
{
if (sTxDone)
{
sTxDone = FALSE;
if ((sTxOtFrame.mPsdu[kMacFcfLowOffset] & kFcfAckRequest) && (OT_ERROR_NONE == sTxStatus))
{
- JN5189FrameConversion(&sRxAckFrame, &sRxOtFrame, macToOtFrame);
+ K32WFrameConversion(&sRxAckFrame, &sRxOtFrame, macToOtFrame);
otPlatRadioTxDone(aInstance, &sTxOtFrame, &sRxOtFrame, sTxStatus);
}
else
@@ -1025,9 +1024,9 @@
* @return OT_ERROR_NONE No conversion error
* @return OT_ERROR_PARSE Conversion failed due to parsing error
*/
-static otError JN5189FrameConversion(tsRxFrameFormat * aMacFormatFrame,
- otRadioFrame * aOtFrame,
- frameConversionType convType)
+static otError K32WFrameConversion(tsRxFrameFormat * aMacFormatFrame,
+ otRadioFrame * aOtFrame,
+ frameConversionType convType)
{
tsMacFrame *pMacFrame = &aMacFormatFrame->sFrameBody;
uint8_t * pSavedStartRxPSDU = aOtFrame->mPsdu;
@@ -1036,13 +1035,13 @@
otError error = OT_ERROR_NONE;
/* frame control field */
- JN5189Copy((uint8_t *)&pMacFrame->u16FCF, &pPsdu, kFcfSize, convType);
+ K32WCopy((uint8_t *)&pMacFrame->u16FCF, &pPsdu, kFcfSize, convType);
aFcf = pMacFrame->u16FCF;
/* sequence number */
if (0 == (aFcf & kFcfSeqNbSuppresssion))
{
- JN5189Copy(&pMacFrame->u8SequenceNum, &pPsdu, kDsnSize, convType);
+ K32WCopy(&pMacFrame->u8SequenceNum, &pPsdu, kDsnSize, convType);
}
/* destination Pan Id + address */
@@ -1052,14 +1051,14 @@
break;
case kFcfDstAddrShort:
- JN5189Copy((uint8_t *)&pMacFrame->u16DestPAN, &pPsdu, sizeof(otPanId), convType);
- JN5189Copy((uint8_t *)&pMacFrame->uDestAddr.u16Short, &pPsdu, sizeof(otShortAddress), convType);
+ K32WCopy((uint8_t *)&pMacFrame->u16DestPAN, &pPsdu, sizeof(otPanId), convType);
+ K32WCopy((uint8_t *)&pMacFrame->uDestAddr.u16Short, &pPsdu, sizeof(otShortAddress), convType);
break;
case kFcfDstAddrExt:
- JN5189Copy((uint8_t *)&pMacFrame->u16DestPAN, &pPsdu, sizeof(otPanId), convType);
- JN5189Copy((uint8_t *)&pMacFrame->uDestAddr.sExt.u32L, &pPsdu, sizeof(uint32_t), convType);
- JN5189Copy((uint8_t *)&pMacFrame->uDestAddr.sExt.u32H, &pPsdu, sizeof(uint32_t), convType);
+ K32WCopy((uint8_t *)&pMacFrame->u16DestPAN, &pPsdu, sizeof(otPanId), convType);
+ K32WCopy((uint8_t *)&pMacFrame->uDestAddr.sExt.u32L, &pPsdu, sizeof(uint32_t), convType);
+ K32WCopy((uint8_t *)&pMacFrame->uDestAddr.sExt.u32H, &pPsdu, sizeof(uint32_t), convType);
break;
default:
@@ -1070,7 +1069,7 @@
/* Source Pan Id */
if ((aFcf & kFcfSrcAddrMask) != kFcfSrcAddrNone && (aFcf & kFcfPanidCompression) == 0)
{
- JN5189Copy((uint8_t *)&pMacFrame->u16SrcPAN, &pPsdu, sizeof(otPanId), convType);
+ K32WCopy((uint8_t *)&pMacFrame->u16SrcPAN, &pPsdu, sizeof(otPanId), convType);
}
/* Source Address */
@@ -1080,12 +1079,12 @@
break;
case kFcfSrcAddrShort:
- JN5189Copy((uint8_t *)&pMacFrame->uSrcAddr.u16Short, &pPsdu, sizeof(otShortAddress), convType);
+ K32WCopy((uint8_t *)&pMacFrame->uSrcAddr.u16Short, &pPsdu, sizeof(otShortAddress), convType);
break;
case kFcfSrcAddrExt:
- JN5189Copy((uint8_t *)&pMacFrame->uSrcAddr.sExt.u32L, &pPsdu, sizeof(uint32_t), convType);
- JN5189Copy((uint8_t *)&pMacFrame->uSrcAddr.sExt.u32H, &pPsdu, sizeof(uint32_t), convType);
+ K32WCopy((uint8_t *)&pMacFrame->uSrcAddr.sExt.u32L, &pPsdu, sizeof(uint32_t), convType);
+ K32WCopy((uint8_t *)&pMacFrame->uSrcAddr.sExt.u32H, &pPsdu, sizeof(uint32_t), convType);
break;
default:
@@ -1101,7 +1100,7 @@
{
aOtFrame->mInfo.mRxInfo.mAckedWithFramePending = (bool)aMacFormatFrame->sFrameBody.u16Unused;
aOtFrame->mInfo.mRxInfo.mLqi = aMacFormatFrame->u8LinkQuality;
- aOtFrame->mInfo.mRxInfo.mRssi = i8Radio_Jn518x_GetLastPacketRSSI();
+ aOtFrame->mInfo.mRxInfo.mRssi = i8Radio_GetLastPacketRSSI();
aOtFrame->mChannel = sChannel;
#if OPENTHREAD_CONFIG_TIME_SYNC_ENABLE
#error Time sync requires the timestamp of SFD rather than that of rx done!
@@ -1114,7 +1113,7 @@
aOtFrame->mLength = pPsdu + (pMacFrame->u8PayloadLength) - pSavedStartRxPSDU + sizeof(pMacFrame->u16FCS);
}
- JN5189Copy((uint8_t *)&pMacFrame->uPayload, &pPsdu, pMacFrame->u8PayloadLength, convType);
+ K32WCopy((uint8_t *)&pMacFrame->uPayload, &pPsdu, pMacFrame->u8PayloadLength, convType);
exit:
return error;
@@ -1132,7 +1131,7 @@
* @return OT_ERROR_NONE No conversion error
* @return OT_ERROR_PARSE Conversion failed due to parsing error
*/
-static void JN5189Copy(uint8_t *aFieldValue, uint8_t **aPsdu, uint8_t copySize, frameConversionType convType)
+static void K32WCopy(uint8_t *aFieldValue, uint8_t **aPsdu, uint8_t copySize, frameConversionType convType)
{
if (convType == macToOtFrame)
{
@@ -1151,7 +1150,7 @@
*
* @param[in] aRxRing Pointer to an RX Ring Buffer
*/
-static void JN5189ResetRxRingBuffer(rxRingBuffer *aRxRing)
+static void K32WResetRxRingBuffer(rxRingBuffer *aRxRing)
{
aRxRing->head = 0;
aRxRing->tail = 0;
@@ -1165,15 +1164,15 @@
* @param[in] aRxRing Pointer to the RX Ring Buffer
* @param[in] rxFrame The address for a received frame
*/
-static void JN5189PushRxRingBuffer(rxRingBuffer *aRxRing, tsRxFrameFormat *aRxFrame)
+static void K32WPushRxRingBuffer(rxRingBuffer *aRxRing, tsRxFrameFormat *aRxFrame)
{
aRxRing->buffer[aRxRing->head] = aRxFrame;
if (aRxRing->isFull)
{
- aRxRing->tail = (aRxRing->tail + 1) % JN5189_RX_BUFFERS;
+ aRxRing->tail = (aRxRing->tail + 1) % K32W_RX_BUFFERS;
}
- aRxRing->head = (aRxRing->head + 1) % JN5189_RX_BUFFERS;
+ aRxRing->head = (aRxRing->head + 1) % K32W_RX_BUFFERS;
aRxRing->isFull = (aRxRing->head == aRxRing->tail);
}
@@ -1188,17 +1187,17 @@
* @return tsRxFrameFormat Pointer to a received frame
* @return NULL In case the RX Ring buffer is empty
*/
-static tsRxFrameFormat *JN5189PopRxRingBuffer(rxRingBuffer *aRxRing)
+static tsRxFrameFormat *K32WPopRxRingBuffer(rxRingBuffer *aRxRing)
{
tsRxFrameFormat *rxFrame = NULL;
uint32_t savedInterrupts;
MICRO_DISABLE_AND_SAVE_INTERRUPTS(savedInterrupts);
- if (!JN5189IsEmptyRxRingBuffer(aRxRing))
+ if (!K32WIsEmptyRxRingBuffer(aRxRing))
{
rxFrame = aRxRing->buffer[aRxRing->tail];
aRxRing->isFull = FALSE;
- aRxRing->tail = (aRxRing->tail + 1) % JN5189_RX_BUFFERS;
+ aRxRing->tail = (aRxRing->tail + 1) % K32W_RX_BUFFERS;
}
MICRO_RESTORE_INTERRUPTS(savedInterrupts);
@@ -1213,7 +1212,7 @@
* @return TRUE RX Ring Buffer is not empty
* @return FALSE RX Ring Buffer is empty
*/
-static bool JN5189IsEmptyRxRingBuffer(rxRingBuffer *aRxRing)
+static bool K32WIsEmptyRxRingBuffer(rxRingBuffer *aRxRing)
{
return (!aRxRing->isFull && (aRxRing->head == aRxRing->tail));
}
@@ -1230,14 +1229,14 @@
*
* @return tsRxFrameFormat Pointer to a tsRxFrameFormat
*/
-static tsRxFrameFormat *JN5189GetFrame(tsRxFrameFormat *aRxFrame, uint8_t *aRxFrameIndex)
+static tsRxFrameFormat *K32WGetFrame(tsRxFrameFormat *aRxFrame, uint8_t *aRxFrameIndex)
{
tsRxFrameFormat *frame = NULL;
frame = &aRxFrame[*aRxFrameIndex];
if (frame != sRxFrameInProcess)
{
- *aRxFrameIndex = (*aRxFrameIndex + 1) % JN5189_RX_BUFFERS;
+ *aRxFrameIndex = (*aRxFrameIndex + 1) % K32W_RX_BUFFERS;
}
else
{
@@ -1262,21 +1261,21 @@
* used for a new RX operation.
*
*/
-static void JN5189EnableReceive(bool_t isNewFrameNeeded)
+static void K32WEnableReceive(bool_t isNewFrameNeeded)
{
tsRxFrameFormat *pRxFrame = NULL;
if (isNewFrameNeeded)
{
- if ((pRxFrame = JN5189GetFrame(sRxFrame, &sRxFrameIndex)) != NULL)
+ if ((pRxFrame = K32WGetFrame(sRxFrame, &sRxFrameIndex)) != NULL)
{
- vREG_BbcWrite(REG_BBC_RXBUFAD, (uint32)(&pRxFrame->sFrameBody));
- JN5189RestartRx();
+ vMMAC_SetRxFrame(pRxFrame);
+ K32WRestartRx();
}
}
else
{
- JN5189RestartRx();
+ K32WRestartRx();
}
}
@@ -1284,8 +1283,8 @@
* Function used for MMAC-RX Restart
*
*/
-static void JN5189RestartRx()
+static void K32WRestartRx(void)
{
- vREG_BbcWrite(REG_BBC_RXPROM, ((uint32)sRxOpt >> 8) & ALL_FFs_BYTE);
+ vMMAC_SetRxProm(((uint32)sRxOpt >> 8) & ALL_FFs_BYTE);
vMMAC_RxCtlUpdate(((uint32)sRxOpt) & ALL_FFs_BYTE);
}
diff --git a/examples/platforms/jn5189/random.c b/examples/platforms/k32w/src/random.c
similarity index 100%
rename from examples/platforms/jn5189/random.c
rename to examples/platforms/k32w/src/random.c
diff --git a/examples/platforms/jn5189/settings_jn5189.c b/examples/platforms/k32w/src/settings_k32w.c
similarity index 91%
rename from examples/platforms/jn5189/settings_jn5189.c
rename to examples/platforms/k32w/src/settings_k32w.c
index cf0059d..c280149 100755
--- a/examples/platforms/jn5189/settings_jn5189.c
+++ b/examples/platforms/k32w/src/settings_k32w.c
@@ -29,8 +29,8 @@
/**
* @file
* This file implements the OpenThread platform abstraction for non-volatile storage of
- * settings on JN5189 platform. It has been modified and optimized from the original
- * Open Thread settings implementation to work with JN5189's flash particularities.
+ * settings on K32W platform. It has been modified and optimized from the original
+ * Open Thread settings implementation to work with K32W's flash particularities.
*
*/
@@ -46,7 +46,7 @@
#include "utils/code_utils.h"
#include "utils/wrap_string.h"
-#include "utils/flash.h"
+#include "openthread/platform/flash.h"
#define OT_FLASH_BLOCK_ADD_BEGIN_FLAG (1 << 0)
#define OT_FLASH_BLOCK_ADD_COMPLETE_FLAG (1 << 1)
@@ -60,7 +60,7 @@
#define OT_SETTINGS_FLAG_SIZE 16
#define OT_SETTINGS_BLOCK_DATA_SIZE 256
-/* JN5189 erases the flash to value 0x00 */
+/* K32W erases the flash to value 0x00 */
#define FLASH_ERASE_VALUE 0x00
#define FLASH_ALIGN_SIZE 16
#define FLASH_BLOCK_PAD1_SIZE 10
@@ -68,6 +68,8 @@
#define OT_SETTINGS_IN_USE 0xbe5cc5ee
+extern otError utilsFlashErasePage(uint32_t aAddress);
+
/* Added padding to make settings block structure align to minimum flash write size of 16 bytes.
* The delFlag field has an offset of 16 bytes from the beginning of the structure to allow a new
* write on the field. */
@@ -179,7 +181,7 @@
static void setSettingsFlag(uint32_t aBase, uint32_t aFlag)
{
- utilsFlashWrite(aBase, (uint8_t *)&aFlag, sizeof(aFlag));
+ otPlatFlashWrite(0, 0, aBase, (uint8_t *)&aFlag, sizeof(aFlag));
}
static void eraseSettings(uint32_t aBase)
@@ -235,7 +237,7 @@
} OT_TOOL_PACKED_END addBlock;
bool valid = true;
- utilsFlashRead(swapAddress, (uint8_t *)(&addBlock.block), sizeof(struct settingsBlock));
+ otPlatFlashRead(aInstance, 0, swapAddress, (uint8_t *)(&addBlock.block), sizeof(struct settingsBlock));
swapAddress += sizeof(struct settingsBlock);
tempFlag = addBlock.block.flag;
@@ -250,7 +252,7 @@
{
struct settingsBlock block;
- utilsFlashRead(address, (uint8_t *)(&block), sizeof(block));
+ otPlatFlashRead(aInstance, 0, address, (uint8_t *)(&block), sizeof(block));
if ((FLASH_BLOCK_FLAG_IS_SET(block.flag, OT_FLASH_BLOCK_ADD_COMPLETE_FLAG)) &&
(0 == FLASH_BLOCK_FLAG_IS_SET(block.delFlag, OT_FLASH_BLOCK_DELETE_FLAG)) &&
@@ -281,7 +283,7 @@
/* current pos parameter doesn't count in this case */
writeSize += getAlignLength(0, OT_FLASH_BLOCK_COMPACT_FLAG, addBlock.block.length);
- utilsFlashRead(swapAddress, addBlock.data, addBlock.block.length);
+ otPlatFlashRead(aInstance, 0, swapAddress, addBlock.data, addBlock.block.length);
/* contents fits in current page - we can copy it to page buffer until there is
* enough data to program a page */
if ((sSettingsUsedSize % SETTINGS_CONFIG_PAGE_SIZE) + writeSize <= SETTINGS_CONFIG_PAGE_SIZE)
@@ -302,7 +304,7 @@
/* calculate page address that we are going to write */
uint32_t alignAddress = sSettingsBaseAddress + sSettingsUsedSize;
alignAddress = alignAddress - (alignAddress % SETTINGS_CONFIG_PAGE_SIZE);
- utilsFlashWrite(alignAddress, pageBuffer, SETTINGS_CONFIG_PAGE_SIZE);
+ otPlatFlashWrite(aInstance, 0, alignAddress, pageBuffer, SETTINGS_CONFIG_PAGE_SIZE);
/* After the page buffer is erased copy what dind't fit the previous page */
memset(pageBuffer, FLASH_ERASE_VALUE, SETTINGS_CONFIG_PAGE_SIZE);
@@ -324,7 +326,7 @@
/* If the page buffer has been used and it's not full write to flash at the end */
uint32_t alignAddr = sSettingsBaseAddress + sSettingsUsedSize;
alignAddr = alignAddr - (alignAddr % SETTINGS_CONFIG_PAGE_SIZE);
- utilsFlashWrite(alignAddr, pageBuffer, SETTINGS_CONFIG_PAGE_SIZE);
+ otPlatFlashWrite(aInstance, 0, alignAddr, pageBuffer, SETTINGS_CONFIG_PAGE_SIZE);
}
/* Clear the old settings zone */
eraseSettings(oldBase);
@@ -375,8 +377,8 @@
memcpy(addBlock.data, aValue, addBlock.block.length);
SET_FLASH_BLOCK_FLAG(addBlock.block.flag, OT_FLASH_BLOCK_ADD_COMPLETE_FLAG);
- utilsFlashWrite(sSettingsBaseAddress + sSettingsUsedSize, (uint8_t *)(&addBlock.block),
- sizeof(struct settingsBlock) + addBlock.block.length);
+ otPlatFlashWrite(aInstance, 0, sSettingsBaseAddress + sSettingsUsedSize, (uint8_t *)(&addBlock.block),
+ sizeof(struct settingsBlock) + addBlock.block.length);
/* The next settings block will be written to the next flash page to optimize the number of
* writes made to a page */
sSettingsUsedSize +=
@@ -400,14 +402,14 @@
sSettingsBaseAddress = SETTINGS_CONFIG_BASE_ADDRESS;
- utilsFlashInit();
+ otPlatFlashInit(aInstance);
for (index = 0; index < 2; index++)
{
uint32_t blockFlag;
sSettingsBaseAddress += settingsSize * index;
- utilsFlashRead(sSettingsBaseAddress, (uint8_t *)(&blockFlag), sizeof(blockFlag));
+ otPlatFlashRead(aInstance, 0, sSettingsBaseAddress, (uint8_t *)(&blockFlag), sizeof(blockFlag));
if (blockFlag == OT_SETTINGS_IN_USE)
{
@@ -424,7 +426,7 @@
while (sSettingsUsedSize < settingsSize)
{
- utilsFlashRead(sSettingsBaseAddress + sSettingsUsedSize, (uint8_t *)(&block), sizeof(block));
+ otPlatFlashRead(aInstance, 0, sSettingsBaseAddress + sSettingsUsedSize, (uint8_t *)(&block), sizeof(block));
if (FLASH_BLOCK_FLAG_IS_SET(block.flag, OT_FLASH_BLOCK_ADD_BEGIN_FLAG))
{
@@ -477,7 +479,7 @@
{
struct settingsBlock block;
- utilsFlashRead(address, (uint8_t *)(&block), sizeof(block));
+ otPlatFlashRead(aInstance, 0, address, (uint8_t *)(&block), sizeof(block));
if (block.key == aKey)
{
@@ -502,7 +504,7 @@
readLength = *aValueLength;
}
- utilsFlashRead(address + sizeof(struct settingsBlock), aValue, readLength);
+ otPlatFlashRead(aInstance, 0, address + sizeof(struct settingsBlock), aValue, readLength);
}
valueLength = block.length;
@@ -550,7 +552,7 @@
{
struct settingsBlock block;
- utilsFlashRead(address, (uint8_t *)(&block), sizeof(block));
+ otPlatFlashRead(aInstance, 0, address, (uint8_t *)(&block), sizeof(block));
if (block.key == aKey)
{
@@ -579,7 +581,7 @@
if (flashWrite)
{
- utilsFlashWrite(address, (uint8_t *)(&block), sizeof(block));
+ otPlatFlashWrite(aInstance, 0, address, (uint8_t *)(&block), sizeof(block));
}
index++;
diff --git a/examples/platforms/jn5189/system.c b/examples/platforms/k32w/src/system.c
similarity index 92%
rename from examples/platforms/jn5189/system.c
rename to examples/platforms/k32w/src/system.c
index 9ce509b..6dbc2de 100755
--- a/examples/platforms/jn5189/system.c
+++ b/examples/platforms/k32w/src/system.c
@@ -33,7 +33,7 @@
*/
#include "board.h"
#include "pin_mux.h"
-#include "platform-jn5189.h"
+#include "platform-k32w.h"
#include "openthread/platform/uart.h"
#include <stdbool.h>
@@ -59,9 +59,9 @@
BOARD_InitPins();
}
- JN5189AlarmInit();
- JN5189RandomInit();
- JN5189RadioInit();
+ K32WAlarmInit();
+ K32WRandomInit();
+ K32WRadioInit();
}
bool otSysPseudoResetWasRequested(void)
@@ -77,9 +77,9 @@
void otSysProcessDrivers(otInstance *aInstance)
{
- JN5189RadioProcess(aInstance);
- JN5189UartProcess();
- JN5189AlarmProcess(aInstance);
+ K32WRadioProcess(aInstance);
+ K32WUartProcess();
+ K32WAlarmProcess(aInstance);
}
void otSysEventSignalPending(void)
diff --git a/examples/platforms/jn5189/uart.c b/examples/platforms/k32w/src/uart.c
similarity index 83%
rename from examples/platforms/jn5189/uart.c
rename to examples/platforms/k32w/src/uart.c
index 396fc5a..dbb2d7f 100755
--- a/examples/platforms/jn5189/uart.c
+++ b/examples/platforms/k32w/src/uart.c
@@ -43,13 +43,13 @@
#include "openthread/platform/uart.h"
/* Defines */
-#define JN5189_UART_RX_BUFFERS 256
-#define JN5189_UART_BAUD_RATE 115200
+#define K32W_UART_RX_BUFFERS 256
+#define K32W_UART_BAUD_RATE 115200
/* Structures */
typedef struct
{
- uint8_t buffer[JN5189_UART_RX_BUFFERS];
+ uint8_t buffer[K32W_UART_RX_BUFFERS];
uint8_t head;
uint8_t tail;
bool isFull;
@@ -60,15 +60,15 @@
{
UART_IDLE, /* TX idle. */
UART_BUSY, /* TX busy. */
-} jn5189UartStates;
+} K32WUartStates;
/* Private functions declaration */
-static void JN5189ResetRxRingBuffer(rxRingBuffer *aRxRing);
-static uint8_t *JN5189PopRxRingBuffer(rxRingBuffer *aRxRing);
-static bool JN5189IsEmptyRxRingBuffer(rxRingBuffer *aRxRing);
-static void JN5189PushRxRingBuffer(rxRingBuffer *aRxRing, uint8_t aCharacter);
-static void JN5189ProcessReceive();
-static void JN5189ProcessTransmit();
+static void K32WResetRxRingBuffer(rxRingBuffer *aRxRing);
+static uint8_t *K32WPopRxRingBuffer(rxRingBuffer *aRxRing);
+static bool K32WIsEmptyRxRingBuffer(rxRingBuffer *aRxRing);
+static void K32WPushRxRingBuffer(rxRingBuffer *aRxRing, uint8_t aCharacter);
+static void K32WProcessReceive(void);
+static void K32WProcessTransmit(void);
static void USART0_IRQHandler(USART_Type *base, usart_handle_t *handle);
/* Private variables declaration */
@@ -77,12 +77,12 @@
static usart_handle_t sUartHandle; /* Handle to the UART module */
static rxRingBuffer sUartRxRing; /* Receive Ring Buffer */
-void JN5189UartProcess(void)
+void K32WUartProcess(void)
{
if (sIsUartInitialized)
{
- JN5189ProcessTransmit();
- JN5189ProcessReceive();
+ K32WProcessTransmit();
+ K32WProcessReceive();
}
}
@@ -104,7 +104,7 @@
sUartHandle.txState = UART_IDLE;
USART_GetDefaultConfig(&config);
- config.baudRate_Bps = JN5189_UART_BAUD_RATE;
+ config.baudRate_Bps = K32W_UART_BAUD_RATE;
config.enableTx = true;
config.enableRx = true;
config.rxWatermark = kUSART_RxFifo1;
@@ -112,7 +112,7 @@
uartStatus = USART_Init(USART0, &config, kPlatformClock);
otEXPECT_ACTION(uartStatus == kStatus_Success, error = OT_ERROR_INVALID_ARGS);
- JN5189ResetRxRingBuffer(&sUartRxRing);
+ K32WResetRxRingBuffer(&sUartRxRing);
FLEXCOMM_SetIRQHandler(USART0, (flexcomm_irq_handler_t)USART0_IRQHandler, &sUartHandle);
@@ -163,7 +163,7 @@
* @param[in] aBuf Pointer to the character buffer
* @param[in] len Length of the character buffer
*/
-void JN5189WriteBlocking(const uint8_t *aBuf, uint32_t len)
+void K32WWriteBlocking(const uint8_t *aBuf, uint32_t len)
{
otEXPECT(sIsUartInitialized && sUartHandle.txState != UART_BUSY);
@@ -178,7 +178,7 @@
/**
* Process TX characters in process context and call the upper layer call-backs.
*/
-static void JN5189ProcessTransmit(void)
+static void K32WProcessTransmit(void)
{
if (sIsTransmitDone)
{
@@ -190,13 +190,13 @@
/**
* Process RX characters in process context and call the upper layer call-backs.
*/
-static void JN5189ProcessReceive(void)
+static void K32WProcessReceive(void)
{
- uint8_t rx[JN5189_UART_RX_BUFFERS];
+ uint8_t rx[K32W_UART_RX_BUFFERS];
uint16_t rxIndex = 0;
uint8_t *pCharacter;
- while ((pCharacter = JN5189PopRxRingBuffer(&sUartRxRing)) != NULL)
+ while ((pCharacter = K32WPopRxRingBuffer(&sUartRxRing)) != NULL)
{
rx[rxIndex] = *pCharacter;
rxIndex++;
@@ -229,7 +229,7 @@
volatile uint8_t rx_data = USART_ReadByte(USART0);
{
- JN5189PushRxRingBuffer(&sUartRxRing, rx_data);
+ K32WPushRxRingBuffer(&sUartRxRing, rx_data);
}
}
@@ -267,16 +267,16 @@
* @param[in] aRxRing Pointer to the RX Ring Buffer
* @param[in] aCharacter The received character
*/
-static void JN5189PushRxRingBuffer(rxRingBuffer *aRxRing, uint8_t aCharacter)
+static void K32WPushRxRingBuffer(rxRingBuffer *aRxRing, uint8_t aCharacter)
{
aRxRing->buffer[aRxRing->head] = aCharacter;
if (aRxRing->isFull)
{
- aRxRing->tail = (aRxRing->tail + 1) % JN5189_UART_RX_BUFFERS;
+ aRxRing->tail = (aRxRing->tail + 1) % K32W_UART_RX_BUFFERS;
}
- aRxRing->head = (aRxRing->head + 1) % JN5189_UART_RX_BUFFERS;
+ aRxRing->head = (aRxRing->head + 1) % K32W_UART_RX_BUFFERS;
aRxRing->isFull = (aRxRing->head == aRxRing->tail);
}
@@ -291,16 +291,16 @@
* @return tsRxFrameFormat Pointer to a received character
* @return NULL In case the RX Ring buffer is empty
*/
-static uint8_t *JN5189PopRxRingBuffer(rxRingBuffer *aRxRing)
+static uint8_t *K32WPopRxRingBuffer(rxRingBuffer *aRxRing)
{
uint8_t *pCharacter = NULL;
DisableIRQ(USART0_IRQn);
- if (!JN5189IsEmptyRxRingBuffer(aRxRing))
+ if (!K32WIsEmptyRxRingBuffer(aRxRing))
{
pCharacter = &(aRxRing->buffer[aRxRing->tail]);
aRxRing->isFull = false;
- aRxRing->tail = (aRxRing->tail + 1) % JN5189_UART_RX_BUFFERS;
+ aRxRing->tail = (aRxRing->tail + 1) % K32W_UART_RX_BUFFERS;
}
EnableIRQ(USART0_IRQn);
@@ -315,7 +315,7 @@
* @return TRUE RX Ring Buffer is not empty
* @return FALSE RX Ring Buffer is empty
*/
-static bool JN5189IsEmptyRxRingBuffer(rxRingBuffer *aRxRing)
+static bool K32WIsEmptyRxRingBuffer(rxRingBuffer *aRxRing)
{
return (!aRxRing->isFull && (aRxRing->head == aRxRing->tail));
}
@@ -325,9 +325,23 @@
*
* @param[in] aRxRing Pointer to an RX Ring Buffer
*/
-static void JN5189ResetRxRingBuffer(rxRingBuffer *aRxRing)
+static void K32WResetRxRingBuffer(rxRingBuffer *aRxRing)
{
aRxRing->head = 0;
aRxRing->tail = 0;
aRxRing->isFull = false;
}
+
+/**
+ * The UART driver weak functions definition.
+ *
+ */
+OT_TOOL_WEAK void otPlatUartSendDone(void)
+{
+}
+
+OT_TOOL_WEAK void otPlatUartReceived(const uint8_t *aBuf, uint16_t aBufLength)
+{
+ OT_UNUSED_VARIABLE(aBuf);
+ OT_UNUSED_VARIABLE(aBufLength);
+}
diff --git a/src/core/common/tlvs.cpp b/src/core/common/tlvs.cpp
index 5b9c8fe..b39595e 100644
--- a/src/core/common/tlvs.cpp
+++ b/src/core/common/tlvs.cpp
@@ -59,7 +59,7 @@
{
uint32_t size = GetSize();
- OT_ASSERT(size <= UINT16_MAX);
+ // OT_ASSERT(size <= UINT16_MAX);
return aMessage.Append(this, static_cast<uint16_t>(size));
}
diff --git a/third_party/nxp/JN5189/ImageSigning/jn518x_image_tool.py b/third_party/nxp/JN5189/ImageSigning/jn518x_image_tool.py
deleted file mode 100755
index 2e4552c..0000000
--- a/third_party/nxp/JN5189/ImageSigning/jn518x_image_tool.py
+++ /dev/null
@@ -1,353 +0,0 @@
-"""
-* Copyright 2019 NXP
-* All rights reserved.
-*
-* SPDX-License-Identifier: BSD-3-Clause
-"""
-
-#!python
-
-from collections import namedtuple
-import re
-import argparse
-import subprocess
-import struct
-from Crypto.Signature import pkcs1_15
-from Crypto.PublicKey import RSA
-from Crypto.Hash import SHA256
-from Crypto.Util import number
-import binascii
-import os
-
-parser = argparse.ArgumentParser(description='JN518x Image Header Generator')
-parser.add_argument('in_file', help="Binary to be post-processed: generating header and optionally appending certificate and/or signature.")
-parser.add_argument('out_file', nargs='?')
-parser.add_argument('-g', '--signature_path', help="Sets directory from which certificate and private key are to be retrieved")
-parser.add_argument('-k', '--key', action='store_true', help="2048 bits RSA private key in PEM format used to sign the full image. If -c option is used the full image includes the certificate + the signature of the certificate. The key shall be located in the same directory as the image_tool script. See priv_key.pem example.")
-parser.add_argument('-p', '--password',help="This is the pass phrase from which the encryption key is derived. This parameter is only required if key provided through the -k option is a PEM encrypted key.")
-parser.add_argument('-c', '--certificate', action='store_true', help="When option is selected, the certificate cert.bin is appended to the image.")
-parser.add_argument('-a', '--appcore_image', action='store_true',help="This parameter is only relevant if dual application (app1 image) shall reside in flash. Do not use in conjunction with -i option.")
-parser.add_argument('-i', '--image_identifier', type=int, default=0, help="This parameter is to set the archive identifier. 0: SSBL or legacy JN518x/QN9090 applications, loaded at 0x00000000. 1: ZigBee application loaded at address 0x00004000 by default. 2: BLE image loaded at address 0x00054000 by default")
-parser.add_argument('-t', '--target_addr', type=int, help="Target address of image. Used in conjucntion with -i option to override the default set by image identifier, or with -a option to specify address of the appcore image (app1 image).")
-parser.add_argument('-r', '--rev', type=int, default=2, help="This is the revision of the JN5189 chip. Set 1 for ES1 and 2 for ES2. Default is ES2.")
-parser.add_argument('-s', '--stated_size', type=int, default=0x48000, help="This is the stated size of the image in bytes. Default is 0x48000.")
-parser.add_argument('-v', '--version', type=int, default=0, help="Image version. Default is 0.")
-parser.add_argument('-b', '--verbose', type=int, default=0, help="verbosity level. Default is 0.")
-
-args = parser.parse_args()
-
-elf_file_name = args.in_file
-bin_file_name = elf_file_name.split(".")[0]+'_temp.bin'
-
-if args.out_file is None:
- args.out_file = elf_file_name
-
-verbose = args.verbose != 0
-
-
-
-def parse_sections(file):
- sections = {}
-
- Section = namedtuple('Section', ['idx', 'name', 'size', 'vma', 'lma', 'offset', 'align', 'flags'])
-
- objdump = subprocess.check_output(['arm-none-eabi-objdump', '-h', file])
-
- section_re = re.compile(r'(?P<idx>\d*)\s'
- r'(?P<name>[.\w]*)\s*'
- r'(?P<size>[0-9a-f]{8})\s*'
- r'(?P<vma>[0-9a-f]{8})\s*'
- r'(?P<lma>[0-9a-f]{8})\s*'
- r'(?P<offset>[0-9a-f]{8})\s*'
- r'(?P<align>[0-9*]*)\s*'
- r'(?P<flags>(?:[ \t]*[\w,]*)*)')
-
- for match in re.finditer(section_re, objdump):
- sec_dict = match.groupdict()
-
- sec_dict['idx'] = int(sec_dict['idx'])
-
- for attr in ['vma', 'lma', 'size', 'offset']:
- sec_dict[attr] = int(sec_dict[attr], 16)
-
- sec_dict['align'] = eval(sec_dict['align'])
-
- sections[sec_dict['name']] = Section(**sec_dict)
-
- return sections
-
-
-#
-# JN518x ES1 version
-######################
-if args.rev == 1:
-
- BOOT_BLOCK_MARKER = 0xBB0110BB
-
- header_struct = struct.Struct('<7LLLLL')
- boot_block_struct = struct.Struct('<6LQ')
-
- sections = parse_sections(args.in_file)
-
- last_section = None
-
- for name, section in sections.iteritems():
- if 'LOAD' in section.flags:
- if last_section is None or section.lma > last_section.lma:
- if section.size > 0:
- last_section = section
-
- if args.appcore_image is True:
- image_size = last_section.lma + last_section.size - args.target_appcore_addr
- else:
- image_size = last_section.lma + last_section.size
-
- dump_section = subprocess.check_output(['arm-none-eabi-objcopy', '--dump-section', '%s=data.bin' % last_section.name, args.in_file])
-
- if args.appcore_image is True:
- boot_block = boot_block_struct.pack(BOOT_BLOCK_MARKER, 1, args.target_appcore_addr, image_size + boot_block_struct.size, 0, 0, 0)
- else:
- boot_block = boot_block_struct.pack(BOOT_BLOCK_MARKER, 0, 0, image_size + boot_block_struct.size, 0, 0, 0)
-
- with open('data.bin', 'ab') as out_file:
- out_file.write(boot_block)
-
- update_section = subprocess.check_output(['arm-none-eabi-objcopy', '--update-section', '%s=data.bin' % last_section.name, args.in_file, args.out_file])
-
- first_section = None
-
- for name, section in sections.iteritems():
- if 'LOAD' in section.flags:
- if first_section is None or section.lma < first_section.lma:
- first_section = section
-
- with open(args.out_file, 'r+b') as elf_file:
- elf_file.seek(first_section.offset)
- vectors = elf_file.read(header_struct.size)
-
- fields = list(header_struct.unpack(vectors))
-
- vectsum = 0
-
- for x in range(7):
- vectsum += fields[x]
-
- fields[7] = (~vectsum & 0xFFFFFFFF) + 1
- if args.appcore_image is True:
- fields[9] = 0x02794498
- else:
- fields[9] = 0x98447902
- #fields[9] = 0x98447902
- fields[10] = image_size
-
- print "Writing checksum {:08x} to file {:s}".format(vectsum, args.out_file)
-
- elf_file.seek(first_section.offset)
- elf_file.write(header_struct.pack(*fields))
-
-#
-# JN518x ES2 version
-######################
-else:
- is_signature = False
- if args.signature_path is not None:
- sign_dir_path = os.path.join(os.path.dirname(__file__), args.signature_path)
- priv_key_file_path = os.path.join(sign_dir_path, 'priv_key.pem')
- cert_file_path = os.path.join(sign_dir_path, 'cert.bin')
- else:
- sign_dir_path = os.path.join(os.path.dirname(__file__), '')
- priv_key_file_path = os.path.join(sign_dir_path, 'testkey_es2.pem')
- cert_file_path = os.path.join(sign_dir_path, 'certif_es2')
-
- if args.key is True:
- key_file_path = priv_key_file_path
- if verbose:
- print "key path is " + key_file_path
- if (os.path.isfile(key_file_path)):
- key_file=open(key_file_path, 'r')
- key = RSA.importKey(key_file.read(), args.password)
- print "Private RSA key processing..."
- is_signature = True
-
- bin_output = subprocess.check_output(['arm-none-eabi-objcopy', '-O', 'binary', elf_file_name, bin_file_name])
-
- with open(bin_file_name, 'rb') as in_file:
- input_file = in_file.read()
-
- BOOT_BLOCK_MARKER = 0xBB0110BB
- IMAGE_HEADER_MARKER = 0x98447902
- IMAGE_HEADER_APP_CORE = 0x02794498
- IMAGE_HEADER_ESCORE = IMAGE_HEADER_MARKER
- SSBL_OR_LEGACY_ADDRESS = 0x00000000
- SSBL_STATED_SIZE = 0x3000
- ZB_TARGET_ADDRESS = SSBL_STATED_SIZE * 2
- ZB_STATED_SIZE = 0x4f000
- BLE_TARGET_ADDRESS = ZB_TARGET_ADDRESS + ZB_STATED_SIZE
- BLE_STATED_SIZE = 0x3b000
-
- header_struct = struct.Struct('<7LLLLL')
- boot_block_struct = struct.Struct('<8L')
-
- boot_block_marker = BOOT_BLOCK_MARKER
- if args.image_identifier is not None:
- image_iden = args.image_identifier
- else:
- image_iden = 0
-
- # Set header marker and image address based on image identifier (-i option)
- if verbose:
- print "Image Identifier is {:d}".format(image_iden)
- if image_iden == 0:
- img_header_marker = IMAGE_HEADER_MARKER + image_iden
- image_addr = SSBL_OR_LEGACY_ADDRESS
- stated_size = SSBL_STATED_SIZE
- elif image_iden == 1:
- img_header_marker = IMAGE_HEADER_MARKER + image_iden
- image_addr = ZB_TARGET_ADDRESS
- stated_size = ZB_STATED_SIZE
- elif image_iden == 2:
- img_header_marker = IMAGE_HEADER_MARKER + image_iden
- image_addr = BLE_TARGET_ADDRESS
- stated_size = BLE_STATED_SIZE
- else:
- image_addr = 0
- stated_size = 0
-
- # Overwrite defaults for image address, stated size and header marker (-t, -s, -a options)
- if args.target_addr is not None:
- image_addr = args.target_addr
-
- if args.stated_size is not None:
- stated_size = args.stated_size
-
- if args.appcore_image is True:
- img_header_marker = IMAGE_HEADER_APP_CORE
-
- if verbose:
- print "image_iden=%d image_addr=%x" % (image_iden, image_addr)
- print "boot_block_marker=%x" % (boot_block_marker)
-
- sections = parse_sections(elf_file_name)
-
- last_section = None
- for name, section in sections.iteritems():
- if 'LOAD' in section.flags:
- if last_section is None or section.lma > last_section.lma:
- if section.size > 0:
- last_section = section
-
- image_size = last_section.lma + last_section.size - image_addr
- if verbose:
- print "Last Section LMA={:08x} Size={:08x}".format(last_section.lma, last_section.size)
- print "ImageAddress={:08x}".format(image_addr)
-
- first_section = None
-
- for name, section in sections.iteritems():
- # print "Section: {:s} {:s} {:x} {:x}".format(name, section.flags, section.lma, section.size)
- if 'LOAD' in section.flags:
- if first_section is None or section.lma < first_section.lma:
- first_section = section
-
- header=""
- with open(args.out_file, 'r+b') as elf_file:
- elf_file.seek(first_section.offset)
- vectors = elf_file.read(header_struct.size)
-
- fields = list(header_struct.unpack(vectors))
-
- vectsum = 0
- for x in range(7):
- vectsum += fields[x]
-
- fields[7] = (~vectsum & 0xFFFFFFFF) + 1
- fields[8] = img_header_marker
- fields[9] = image_size #offset of boot block structure
-
- #Compute crc
- head_struct = struct.Struct('<10L')
- if verbose:
- for i in range(10):
- print "Header[{:d}]= {:08x}".format(i, fields[i])
- values = head_struct.pack(fields[0],
- fields[1],
- fields[2],
- fields[3],
- fields[4],
- fields[5],
- fields[6],
- fields[7],
- fields[8],
- fields[9])
- fields[10] = binascii.crc32(values) & 0xFFFFFFFF
-
- print "Writing checksum {:08x} to file {:s}".format(vectsum, args.out_file)
- print "Writing CRC32 of header {:08x} to file {:s}".format(fields[10], args.out_file)
-
-
- elf_file.seek(first_section.offset)
- header = header_struct.pack(*fields);
- elf_file.write(header)
-
- dump_section = subprocess.check_output(['arm-none-eabi-objcopy',
- '--dump-section',
- '%s=data.bin' % last_section.name,
- args.out_file])
-
- certificate = ""
- certificate_offset = 0
- signature = ""
-
- if (args.certificate is True):
- certificate_offset = image_size + boot_block_struct.size
- certif_file_path = cert_file_path
- if verbose:
- print "Cert key path is " + cert_file_path
- if (os.path.isfile(certif_file_path)):
- certif_file=open(certif_file_path, 'rb')
- certificate = certif_file.read()
-
- print "Certificate processing..."
- if len(certificate) != (40+256+256):
- print "Certificate error"
-
- if verbose:
- print "stated size is {:08x}".format(stated_size)
-
- if args.appcore_image is True:
- boot_block_id = 1
- else:
- boot_block_id = 0
-
- boot_block = boot_block_struct.pack(boot_block_marker,
- boot_block_id,
- image_addr,
- image_size + boot_block_struct.size + len(certificate),
- stated_size,
- certificate_offset, 0, args.version)
-
- if (is_signature == True):
- # Sign the complete image
- message = header + input_file[header_struct.size:] + boot_block + certificate
- hash = SHA256.new(message)
-
- out_file_path = os.path.join(os.path.dirname(__file__), 'dump_python.bin')
- file_out=open(out_file_path, 'wb')
- file_out.write(message)
-
- signer = pkcs1_15.new(key)
- signature = signer.sign(hash)
-
- print "Signature processing..."
-
-
- with open('data.bin', 'ab') as out_file:
- out_file.write(boot_block+certificate+signature)
-
- update_section = subprocess.check_output(['arm-none-eabi-objcopy',
- '--update-section',
- '%s=data.bin' % last_section.name,
- args.out_file,
- args.out_file])
-
- os.remove(bin_file_name)
diff --git a/third_party/nxp/JN5189/MicroSpecific/Include/MicroInt.h b/third_party/nxp/JN5189/MicroSpecific/Include/MicroInt.h
deleted file mode 100755
index b73474f..0000000
--- a/third_party/nxp/JN5189/MicroSpecific/Include/MicroInt.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*****************************************************************************
- *
- * MODULE: Nested interrupt enabler
- *
- * COMPONENT: $RCSfile: MicroInt.h,v $
- *
- * VERSION: $Name: $
- *
- * REVISION: $Revision: 1.3 $
- *
- * DATED: $Date: 2009/07/15 10:44:32 $
- *
- * STATUS: $State: Exp $
- *
- * AUTHOR: CJG
- *
- * DESCRIPTION:
- * Nested interrupt functions and macros
- *
- ****************************************************************************
- *
- * (c) Copyright JENNIC Ltd 2008
- *
- ****************************************************************************
- *
- * This software is owned by Jennic and/or its supplier and is protected
- * under applicable copyright laws. All rights are reserved. We grant You,
- * and any third parties, a license to use this software solely and
- * exclusively on Jennic products. You, and any third parties must reproduce
- * the copyright and warranty notice and any other legend of ownership on each
- * copy or partial copy of the software.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS". JENNIC MAKES NO WARRANTIES, WHETHER
- * EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE,
- * ACCURACY OR LACK OF NEGLIGENCE. JENNIC SHALL NOT, IN ANY CIRCUMSTANCES,
- * BE LIABLE FOR ANY DAMAGES, INCLUDING, BUT NOT LIMITED TO, SPECIAL,
- * INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON WHATSOEVER.
- *
- * Copyright Jennic Ltd 2008. All rights reserved
- *
- ****************************************************************************/
-
-#ifndef MICRO_INT_INCLUDED
-#define MICRO_INT_INCLUDED
-
-#if defined __cplusplus
-extern "C" {
-#endif
-
-/****************************************************************************/
-/*** Include Files ***/
-/****************************************************************************/
-#include "MicroSpecific.h"
-
-/****************************************************************************/
-/*** Macro Definitions ***/
-/****************************************************************************/
-
-/****************************************************************************/
-/*** Type Definitions ***/
-/****************************************************************************/
-
-/****************************************************************************/
-/*** Exported Functions ***/
-/****************************************************************************/
-
-/****************************************************************************/
-/*** Exported Variables ***/
-/****************************************************************************/
-
-#if defined __cplusplus
-}
-#endif
-
-#endif /* MICRO_INT_INCLUDED */
-
-/****************************************************************************/
-/*** END OF FILE ***/
-/****************************************************************************/
diff --git a/third_party/nxp/JN5189/MicroSpecific/Include/MicroSpecific.h b/third_party/nxp/JN5189/MicroSpecific/Include/MicroSpecific.h
deleted file mode 100755
index cc5c9ab..0000000
--- a/third_party/nxp/JN5189/MicroSpecific/Include/MicroSpecific.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
-* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
-* Copyright 2016-2019 NXP
-* All rights reserved.
-*
-* SPDX-License-Identifier: BSD-3-Clause
-*/
-
-/****************************************************************************/
-/*** Include files ***/
-/****************************************************************************/
-
-#define EXPAND1(x) x
-#define EXPAND2(x, y) EXPAND1(x)y
-#define EXPAND3(x, y, z) EXPAND2(x, y)z
-
-/* Convoluted way to #include <MicroSpecific_JN51xx.h> */
-#undef INCLUDE_NAME
-#define INCLUDE_NAME <EXPAND3(MicroSpecific,JENNIC_CHIP_FAMILY_NAME,.h)>
-#include INCLUDE_NAME
-
-/****************************************************************************/
-/*** END OF FILE ***/
-/****************************************************************************/
diff --git a/third_party/nxp/JN5189/MicroSpecific/Include/MicroSpecific_JN518x.h b/third_party/nxp/JN5189/MicroSpecific/Include/MicroSpecific_JN518x.h
deleted file mode 100755
index e44f7dd..0000000
--- a/third_party/nxp/JN5189/MicroSpecific/Include/MicroSpecific_JN518x.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
-* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
-* Copyright 2016-2019 NXP
-* All rights reserved.
-*
-* SPDX-License-Identifier: BSD-3-Clause
-*/
-
-/****************************************************************************/
-/*** Include files ***/
-/****************************************************************************/
-
-#include "MicroSpecific_arm_sdk2.h"
-
-/****************************************************************************/
-/*** END OF FILE ***/
-/****************************************************************************/
diff --git a/third_party/nxp/JN5189/MicroSpecific/Include/MicroSpecific_arm_sdk2.h b/third_party/nxp/JN5189/MicroSpecific/Include/MicroSpecific_arm_sdk2.h
deleted file mode 100755
index c95b890..0000000
--- a/third_party/nxp/JN5189/MicroSpecific/Include/MicroSpecific_arm_sdk2.h
+++ /dev/null
@@ -1,363 +0,0 @@
-/*
-* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
-* Copyright 2016-2019 NXP
-* All rights reserved.
-*
-* SPDX-License-Identifier: BSD-3-Clause
-*/
-
-#ifndef MICRO_SPECIFIC_INCLUDED
-#define MICRO_SPECIFIC_INCLUDED
-
-#if defined __cplusplus
-extern "C" {
-#endif
-
-/****************************************************************************/
-/*** Include Files ***/
-/****************************************************************************/
-#include <jendefs.h>
-#include "JN5189.h"
-
-extern void (*isr_handlers[])(void);
-
-/****************************************************************************/
-/*** Macro Definitions ***/
-/****************************************************************************/
-
-/** @{ Defined system call numbers */
-#define SYSCALL_SEMIHOSTING 0xAB
-
-#define SEMIHOSTING_WRITE0 0x04
-#define SEMIHOSTING_READC 0x07
-/** @} */
-
-#define MICRO_INTERRUPT_EXCEPTION_OFFSET 16
-
-// number of bits are defined by the hardware
-#define MICRO_INTERRUPT_NUMBER_OF_PRIORITY_BITS __NVIC_PRIO_BITS
-
-// this macro depends on the setting of the priority group in the NVIC, setting G=3 in this case
-#define MICRO_INTERRUPT_MAX_PRIORITY ((1 << MICRO_INTERRUPT_NUMBER_OF_PRIORITY_BITS) - 1)
-// half way
-#define MICRO_INTERRUPT_MID_PRIORITY (MICRO_INTERRUPT_MAX_PRIORITY/2)
-
-// Priority levels in the arm are higher for lower values - B-Semi chips were the other way around
-#define MICRO_INTERRUPT_ELEVATED_PRIORITY (11)
-#define MICRO_INTERRUPT_MEDIUM_PRIORITY (12)
-
-// priority/sub priority register 8-bits wide
-// read/write priority
-#define MICRO_INTERRUPT_WRITE_PRIORITY_VALUE(W) ((W) << (8 - MICRO_INTERRUPT_NUMBER_OF_PRIORITY_BITS))
-#define MICRO_INTERRUPT_READ_PRIORITY_VALUE(R) ((R) >> (8 - MICRO_INTERRUPT_NUMBER_OF_PRIORITY_BITS))
-// read/write sub-priority
-#define MICRO_INTERRUPT_SUBPRIORITY_MASK ((1 << (8 - MICRO_INTERRUPT_NUMBER_OF_PRIORITY_BITS)) -1)
-#define MICRO_INTERRUPT_SUBPRIORITY_VALUE(S) ((S) & (MICRO_INTERRUPT_SUBPRIORITY_MASK))
-
-#define asm __asm__
-
-#if 0 /* CJGTODO */
-// JN5172 interrupt mappings
-
-#define MICRO_ISR_NUM_TMR2 0
-#define MICRO_ISR_NUM_TMR3 1
-#define MICRO_ISR_NUM_TMR4 2
-#define MICRO_ISR_NUM_TMR5 3
-#define MICRO_ISR_NUM_TMR6 4
-#define MICRO_ISR_NUM_TMR7 5
-#define MICRO_ISR_NUM_SYSCTRL 6
-#define MICRO_ISR_NUM_BBC 7 // MAC
-#define MICRO_ISR_NUM_AES 8
-#define MICRO_ISR_NUM_PHY 9
-#define MICRO_ISR_NUM_UART0 10
-#define MICRO_ISR_NUM_UART1 11
-#define MICRO_ISR_NUM_SPIS 12
-#define MICRO_ISR_NUM_SPIM 13
-#define MICRO_ISR_NUM_I2C 14
-#define MICRO_ISR_NUM_TMR0 15
-#define MICRO_ISR_NUM_TMR1 16
-#define MICRO_ISR_NUM_TMR8 17 // TIMER_ADC
-#define MICRO_ISR_NUM_ANPER 18
-#define MICRO_ISR_NUM_WDOG 19
-// number of interrupts
-#define MICRO_ISR_NUM 20
-// mask
-#define MICRO_ISR_EN_MASK ((1 << MICRO_ISR_NUM) - 1)
-
-/* NOTE: Following are based on values above. Not all are defined for all
- chips. So if an error is raised by the MICRO_ISR_MASK_* macros below, look
- to see if the corresponding MICRO_ISR_NUM_* macro is defined above. If it
- isn't, that peripheral is not present on the defined chip */
-#define MICRO_ISR_MASK_SYSCTRL (1 << MICRO_ISR_NUM_SYSCTRL)
-#define MICRO_ISR_MASK_BBC (1 << MICRO_ISR_NUM_BBC)
-#define MICRO_ISR_MASK_AES (1 << MICRO_ISR_NUM_AES)
-#define MICRO_ISR_MASK_PHY (1 << MICRO_ISR_NUM_PHY)
-#define MICRO_ISR_MASK_UART0 (1 << MICRO_ISR_NUM_UART0)
-#define MICRO_ISR_MASK_UART1 (1 << MICRO_ISR_NUM_UART1)
-#define MICRO_ISR_MASK_TMR0 (1 << MICRO_ISR_NUM_TMR0)
-#define MICRO_ISR_MASK_TMR1 (1 << MICRO_ISR_NUM_TMR1)
-#define MICRO_ISR_MASK_TMR2 (1 << MICRO_ISR_NUM_TMR2)
-#define MICRO_ISR_MASK_TMR3 (1 << MICRO_ISR_NUM_TMR3)
-#define MICRO_ISR_MASK_TMR4 (1 << MICRO_ISR_NUM_TMR4)
-#define MICRO_ISR_MASK_I2C (1 << MICRO_ISR_NUM_I2C)
-#define MICRO_ISR_MASK_SPIM (1 << MICRO_ISR_NUM_SPIM)
-#define MICRO_ISR_MASK_SPIS (1 << MICRO_ISR_NUM_SPIS)
-#define MICRO_ISR_MASK_INTPER (1 << MICRO_ISR_NUM_INTPER)
-#define MICRO_ISR_MASK_ANPER (1 << MICRO_ISR_NUM_ANPER)
-#define MICRO_ISR_MASK_WDOG (1 << MICRO_ISR_NUM_WDOG)
-#endif
-
-/* Handy macros for controlling interrupts, PIC, interrupt levels */
-
-#define MICRO_ENABLE_INTERRUPTS() \
- asm volatile ("CPSIE I;" : : );
-
-#define MICRO_DISABLE_INTERRUPTS() \
- asm volatile ("CPSID I;" : : );
-
-extern void vAHI_InterruptSetPriority(uint32 u32Mask, uint8 u8Level);
-extern uint8 u8AHI_InterruptGetPriority(uint32 u32InterruptNumber);
-extern void vAHI_InterruptDisable(uint32 u32EnableMask);
-extern void vAHI_TickTimerIntEnable(bool_t bIntEnable);
-extern void vAHI_InterruptSetActivePriorityLevel(uint8 u8Level);
-extern uint8 u8AHI_InterruptReadActivePriorityLevel(void);
-
-#define MICRO_ENABLE_TICK_TIMER_INTERRUPT(); \
- vAHI_TickTimerIntEnable(TRUE);
-
-// use same value as Jennic/BA devices
-#define MICRO_SET_PIC_ENABLE(A) \
- vAHI_InterruptSetPriority(A, 8);
-
-#define MICRO_CLEAR_PIC_ENABLE(A) \
- vAHI_InterruptDisable(A)
-
-#define MICRO_SET_PIC_PRIORITY_LEVEL(A,B) \
- vAHI_InterruptSetPriority(A, B);
-
-#define MICRO_GET_PIC_PRIORITY_LEVEL(A) \
- u8AHI_InterruptGetPriority(A);
-
-/* MRS Move to register from status */
-/* MSR Move to status register */
-#define MICRO_SET_ACTIVE_INT_LEVEL(A) \
- ({ \
- register uint32 __u32interruptLevelStore = A; \
- asm volatile ("MSR BASEPRI, %[intlevelstore];" \
- : \
- :[intlevelstore] "r"(__u32interruptLevelStore) \
- ); \
- })
-
-#define MICRO_SET_ACTIVE_INT_LEVEL_MAX(A) \
- ({ \
- register uint32 __u32interruptLevelStore = A; \
- asm volatile ("MSR BASEPRI_MAX, %[intlevelstore];" \
- : \
- :[intlevelstore] "r"(__u32interruptLevelStore) \
- ); \
- })
-
-#define MICRO_GET_ACTIVE_INT_LEVEL() \
- ({ \
- register uint32 __u32interruptActiveLevel; \
- asm volatile ("MRS %[activelevelstore], BASEPRI;" \
- :[activelevelstore] "=r"(__u32interruptActiveLevel) \
- : ); \
- __u32interruptActiveLevel; \
- })
-
-#define MICRO_SET_PRIMASK_LEVEL(A) \
- ({ \
- register uint32 __u32primaskLevelStore = A; \
- asm volatile ("MSR PRIMASK, %[primasklevelstore];" \
- : \
- :[primasklevelstore] "r"(__u32primaskLevelStore) \
- ); \
- })
-
-#define MICRO_GET_PRIMASK_LEVEL() \
- ({ \
- register uint32 __u32primaskLevelStore; \
- asm volatile ("MRS %[primasklevelstore], PRIMASK;" \
- :[primasklevelstore] "=r"(__u32primaskLevelStore) \
- : \
- ); \
- __u32primaskLevelStore; \
- })
-
-// read back PRIMASK status into u32Store variable then disable the interrupts
-#define MICRO_DISABLE_AND_SAVE_INTERRUPTS(u32Store) \
- ({ \
- asm volatile ("MRS %[primasklevelstore], PRIMASK;" \
- :[primasklevelstore] "=r"(u32Store) \
- : \
- ); \
- asm volatile ("CPSID I;" : : ); \
- })
-
-#define MICRO_RESTORE_INTERRUPTS(u32Store) \
- ({ \
- asm volatile ("MSR PRIMASK, %[primasklevelstore];" \
- : \
- :[primasklevelstore] "r"(u32Store) \
- ); \
- })
-
-// using AAPCS the parameter (the stack frame) will map to r0
-#define MICRO_GET_EXCEPTION_STACK_FRAME() \
- { \
- asm volatile("MRS R0, MSP"); \
- }
-
-// macro using privilege/non�privilege model
-#define MICRO_GET_EXCEPTION_STACK_FRAME_PNPM() \
- ({ \
- asm volatile("TST LR, #4"); \
- asm volatile("ITE EQ"); \
- asm volatile("MRSEQ R0, MSP"); \
- asm volatile("MRSNE R0, PSP"); \
- })
-
-#define FF1(__input) \
- ({ register uint32 __reverse, __result, __return; \
- asm volatile ("RBIT %[reverse], %[input];" \
- : [reverse] "=r" (__reverse) \
- : [input] "r" (__input) \
- ); \
- asm volatile ("CLZ %[result], %[reverse];" \
- : [result] "=r" (__result) \
- : [reverse] "r" (__reverse) \
- ); \
- __return = ((__result == 32) ? 0 : __result+1); \
- __return; })
-
-#if 0 /* In chip_jn518x\inc/core_cmInstr.h */
-/* Reverse byte order */
-#define __REV(A) \
- ({ \
- register uint32 __reverse, __input = A; \
- asm volatile ("REV %[reverse], %[input];" \
- : [reverse] "=r" (__reverse) \
- : [input] "r" (__input) \
- ); \
- __reverse; \
- })
-#endif
-
-#define MICRO_GET_LX() \
- ({ \
- register uint32 __u32lxRegister; \
- asm volatile ("MOV %[lxRegister], R14;" \
- :[lxRegister] "=r"(__u32lxRegister) \
- : \
- ); \
- __u32lxRegister; \
- })
-
-#define MICRO_GET_STACK_LEVEL() \
- ({ \
- register uint32 __u32stackRegister; \
- asm volatile ("MOV %[stackRegister], SP;" \
- :[stackRegister] "=r"(__u32stackRegister) \
- : \
- ); \
- __u32stackRegister; \
- })
-
-/* Interrupt Handler registration - only useful if you're putting the handlers
- * in RAM */
-
-/* Location of isr_handlers is no longer at a known location, but we can link
- to it directly instead */
-#define MICRO_SET_INT_HANDLER(INT, FUNC); \
- isr_handlers[(MICRO_INTERRUPT_EXCEPTION_OFFSET + INT)] = (void *)(FUNC);
-
-#define MICRO_GET_INT_HANDLER(INT) \
- (isr_handlers[(MICRO_INTERRUPT_EXCEPTION_OFFSET + INT)])
-
-/* Nested interrupt control */
-#define MICRO_INT_STORAGE tsMicroIntStorage sIntStorage
-#define MICRO_INT_ENABLE_ONLY(A) vMicroIntEnableOnly(&sIntStorage, A)
-#define MICRO_INT_RESTORE_STATE() vMicroIntRestoreState(&sIntStorage)
-
-/* Exception Handlers */
-#define MICRO_ESR_NUM_RESETISR 1
-#define MICRO_ESR_NUM_NMI 2
-#define MICRO_ESR_NUM_HARDFAULT 3
-#define MICRO_ESR_NUM_MEMMANAGE 4
-#define MICRO_ESR_NUM_BUSFAULT 5
-#define MICRO_ESR_NUM_USGFAULT 6
-// 4 reserved handlers here
-#define MICRO_ESR_NUM_SVCALL 11
-#define MICRO_ESR_NUM_DEBUGMON 12
-// 1 reserved handler here
-#define MICRO_ESR_NUM_PENDSV 14
-#define MICRO_ESR_NUM_SYSTICK 15
-
-/* Location of exception_handlers is no longer at a known location, but we can link
- to it directly instead - only useful if you're putting the handlers
- * in RAM */
-#define MICRO_SET_EXCEPTION_HANDLER(EXCEPTION, FUNC) \
- isr_handlers[EXCEPTION] = (void *)(FUNC);
-
-#define MICRO_GET_EXCEPTION_HANDLER(INT) \
- (isr_handlers[EXCEPTION])
-
-/* NOP instruction */
-#define MICRO_NOP() \
- { \
- asm volatile ("nop;"); \
- }
-
-/* TRAP instruction */
-#define MICRO_TRAP() \
- { \
- asm volatile("BKPT 0;"); \
- }
-
-#define MICRO_JUMP_TO_ADDRESS(ADDRESS) \
- ({ \
- register uint32 __u32programAddressStore = ADDRESS | 0x1; \
- asm volatile ("BLX %[programAddressStore];" \
- : \
- :[programAddressStore] "r"(__u32programAddressStore)); \
- })
-
-/****************************************************************************/
-/*** Type Definitions ***/
-/****************************************************************************/
-/* Nested interrupt control */
-typedef struct
-{
- uint8 u8Level;
-} tsMicroIntStorage;
-
-/****************************************************************************/
-/*** Exported Functions ***/
-/****************************************************************************/
-PUBLIC void vAHI_InitialiseInterruptController(uint32 *pu32InterruptVectorTable);
-
-/* Nested interrupt control */
-PUBLIC void vMicroIntSetGlobalEnable(uint32 u32EnableMask);
-PUBLIC void vMicroIntEnableOnly(tsMicroIntStorage *, uint32 u32EnableMask);
-PUBLIC void vMicroIntRestoreState(tsMicroIntStorage *);
-/* Default Exception Handler */
-PUBLIC void vIntDefaultHandler(void);
-
-PUBLIC void __attribute__((noinline)) vMicroSyscall(volatile uint32 u32SysCallNumber, ...);
-PUBLIC void __attribute__((noinline)) vMicroSemihost(volatile uint32 u32SemihostNumber, ...);
-
-/****************************************************************************/
-/*** Exported Variables ***/
-/****************************************************************************/
-
-#if defined __cplusplus
-}
-#endif
-
-#endif /* MICRO_SPECIFIC_INCLUDED */
-
-/****************************************************************************/
-/*** END OF FILE ***/
-/****************************************************************************/
diff --git a/third_party/nxp/JN5189/Radio_JN5189/.cproject b/third_party/nxp/JN5189/Radio_JN5189/.cproject
deleted file mode 100755
index b819a46..0000000
--- a/third_party/nxp/JN5189/Radio_JN5189/.cproject
+++ /dev/null
@@ -1,389 +0,0 @@
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-<TargetConfig>
-<Properties property_2="JN518x.cfx" property_3="NXP" property_4="JN5189" property_count="5" version="100200"/>
-<infoList vendor="NXP"><info chip="JN5189" flash_driver="JN518x.cfx" match_id="0x0" name="JN5189" stub="crt_emu_cm3_gen"><chip><name>JN5189</name>
-<family>JN518x</family>
-<vendor>NXP Semiconductor</vendor>
-<reset board="None" core="Real" sys="Real"/>
-<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/>
-<memory can_program="true" id="Flash" is_ro="true" type="Flash"/>
-<memory id="RAM" type="RAM"/>
-<memory id="Periph" is_volatile="true" type="Peripheral"/>
-<memoryInstance derived_from="Flash" id="Flash640" location="0x0" size="0xA0000"/>
-<memoryInstance derived_from="RAM" id="RAM0" location="0x4000400" size="0x15C00"/>
-<memoryInstance derived_from="RAM" id="RAM1" location="0x4020000" size="0x10000"/>
-<peripheralInstance derived_from="V7M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/>
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-</chip>
-<processor><name gcc_name="cortex-m4">Cortex-M4</name>
-<family>Cortex-M</family>
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- </configuration>
- <configuration configurationName="Debug Untrimmed and no MAC"/>
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- <configuration configurationName="Radio_Test_Lib_Release"/>
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- <configuration configurationName="Radio_Lib_Release"/>
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- <configuration configurationName="Debug">
- <resource resourceType="PROJECT" workspacePath="/Radio"/>
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- <configuration configurationName="Radio Lib Debug">
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diff --git a/third_party/nxp/JN5189/Radio_JN5189/.project b/third_party/nxp/JN5189/Radio_JN5189/.project
deleted file mode 100755
index 407c830..0000000
--- a/third_party/nxp/JN5189/Radio_JN5189/.project
+++ /dev/null
@@ -1,32 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
- <name>Radio</name>
- <comment></comment>
- <projects>
- </projects>
- <buildSpec>
- <buildCommand>
- <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
- <triggers>clean,full,incremental,</triggers>
- <arguments>
- </arguments>
- </buildCommand>
- <buildCommand>
- <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
- <triggers>full,incremental,</triggers>
- <arguments>
- </arguments>
- </buildCommand>
- </buildSpec>
- <natures>
- <nature>org.eclipse.cdt.core.cnature</nature>
- <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
- <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
- </natures>
- <variableList>
- <variable>
- <name>SDK_BASE_DIR</name>
- <value>$%7BPARENT-1-WORKSPACE_LOC%7D</value>
- </variable>
- </variableList>
-</projectDescription>
diff --git a/third_party/nxp/JN5189/Radio_JN5189/Include/BbcAndPhyRegs.h b/third_party/nxp/JN5189/Radio_JN5189/Include/BbcAndPhyRegs.h
deleted file mode 100755
index 399d549..0000000
--- a/third_party/nxp/JN5189/Radio_JN5189/Include/BbcAndPhyRegs.h
+++ /dev/null
@@ -1,365 +0,0 @@
-/*
-* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
-* Copyright 2016-2019 NXP
-* All rights reserved.
-*
-* SPDX-License-Identifier: BSD-3-Clause
-*/
-
-#ifndef BBC_AND_PHY_REGS_H
-#define BBC_AND_PHY_REGS_H
-
-#if defined __cplusplus
-extern "C" {
-#endif
-
-
-/****************************************************************************/
-/*** Include Files ***/
-/****************************************************************************/
-#include "jn518x.h"
-#include "jn518x_zb_mac.h"
-#include "jn518x_zb_modem.h"
-#include "jn518x_rfp_modem.h"
-
-/****************************************************************************/
-/*** Macro/Type Definitions ***/
-/****************************************************************************/
-#define vREG_BbcWrite(REG, VAL) JN518X_ZBMAC->REG = (VAL)
-#define u32REG_BbcRead(REG) (JN518X_ZBMAC->REG)
-#define vREG_PhyWrite(REG, VAL) JN518X_ZBMODEM->REG = (VAL)
-#define u32REG_PhyRead(REG) (JN518X_ZBMODEM->REG)
-#define vREG_XcvrPhyWrite(REG, VAL) JN518X_ZBMODEM->REG = (VAL)
-#define u32REG_XcvrPhyRead(REG) (JN518X_ZBMODEM->REG)
-
-#define vREG_PhyReadModWrite32(eOffset, u32Mask, u32Data) \
- vREG_PhyWrite(eOffset, (((u32Mask) & (u32Data)) \
- | (~(u32Mask) & (u32REG_PhyRead(eOffset)))))
-
-#define vREG_BbcReadModWrite32(eOffset, u32Mask, u32Data) \
- vREG_BbcWrite(eOffset, (((u32Mask) & (u32Data)) \
- | (~(u32Mask) & (u32REG_BbcRead(eOffset)))))
-
-#ifndef BIT_W_1
-#define BIT_W_1 0x00000001UL
-#define BIT_W_2 0x00000003UL
-#define BIT_W_3 0x00000007UL
-#define BIT_W_4 0x0000000FUL
-#define BIT_W_5 0x0000001FUL
-#define BIT_W_6 0x0000003FUL
-#define BIT_W_7 0x0000007FUL
-#define BIT_W_8 0x000000FFUL
-#define BIT_W_10 0x000003FFUL
-#define BIT_W_12 0x00000FFFUL
-#define BIT_W_15 0x00007FFFUL
-#define BIT_W_16 0x0000FFFFUL
-#define BIT_W_17 0x0001FFFFUL
-#define BIT_W_18 0x0003FFFFUL
-#define BIT_W_19 0x0007FFFFUL
-#define BIT_W_20 0x000FFFFFUL
-#define BIT_W_21 0x001FFFFFUL
-#define BIT_W_25 0x01FFFFFFUL
-#endif
-
-/**** BBC IER/ISR ****/
-#define REG_BBC_INT_TX_BIT 0
-#define REG_BBC_INT_TX_MASK ((uint32)(BIT_W_1 << REG_BBC_INT_TX_BIT))
-#define REG_BBC_INT_RX_H_BIT 1
-#define REG_BBC_INT_RX_H_MASK ((uint32)(BIT_W_1 << REG_BBC_INT_RX_H_BIT))
-#define REG_BBC_INT_RX_BIT 2
-#define REG_BBC_INT_RX_MASK ((uint32)(BIT_W_1 << REG_BBC_INT_RX_BIT))
-#define REG_BBC_INT_M0_BIT 4
-#define REG_BBC_INT_M0_MASK ((uint32)(BIT_W_1 << REG_BBC_INT_M0_BIT))
-#define REG_BBC_INT_M1_BIT 5
-#define REG_BBC_INT_M1_MASK ((uint32)(BIT_W_1 << REG_BBC_INT_M1_BIT))
-#define REG_BBC_INT_M2_BIT 6
-#define REG_BBC_INT_M2_MASK ((uint32)(BIT_W_1 << REG_BBC_INT_M2_BIT))
-#define REG_BBC_INT_M3_BIT 7
-#define REG_BBC_INT_M3_MASK ((uint32)(BIT_W_1 << REG_BBC_INT_M3_BIT))
-#define REG_BBC_INT_T0_BIT 8
-#define REG_BBC_INT_T0_MASK ((uint32)(BIT_W_1 << REG_BBC_INT_T0_BIT))
-#define REG_BBC_INT_T1_BIT 9
-#define REG_BBC_INT_T1_MASK ((uint32)(BIT_W_1 << REG_BBC_INT_T1_BIT))
-#define REG_BBC_INT_T2_BIT 10
-#define REG_BBC_INT_T2_MASK ((uint32)(BIT_W_1 << REG_BBC_INT_T2_BIT))
-#define REG_BBC_INT_T3_BIT 11
-#define REG_BBC_INT_T3_MASK ((uint32)(BIT_W_1 << REG_BBC_INT_T3_BIT))
-#define REG_BBC_INT_TIMER_MASK ((uint32)(BIT_W_6 << REG_BBC_INT_M0_BIT))
-
-/**** REG_BBC_TXMBEBT ****/
-#define REG_BBC_TXMBEBT_MINBE_BIT (0)
-#define REG_BBC_TXMBEBT_MINBE_MASK ((uint32)(BIT_W_4 << REG_BBC_TXMBEBT_MINBE_BIT))
-#define REG_BBC_TXMBEBT_MAXBO_BIT (4)
-#define REG_BBC_TXMBEBT_MAXBO_MASK ((uint32)(BIT_W_3 << REG_BBC_TXMBEBT_MAXBO_BIT))
-#define REG_BBC_TXMBEBT_BLE_BIT (7)
-#define REG_BBC_TXMBEBT_MAXBE_BIT (8)
-#define REG_BBC_TXMBEBT_MAXBE_MASK ((uint32)(BIT_W_4 << REG_BBC_TXMBEBT_MAXBE_BIT))
-#define REG_BBC_TXMBEBT_CSMA_DLY_BIT (12)
-#define REG_BBC_TXMBEBT_CSMA_DLY_MASK ((uint32)(BIT_W_1 << REG_BBC_TXMBEBT_CSMA_DLY_BIT))
-#define REG_BBC_TXMBEBT_DIR_DLY_BIT (13)
-#define REG_BBC_TXMBEBT_DIR_DLY_MASK ((uint32)(BIT_W_4 << REG_BBC_TXMBEBT_DIR_DLY_BIT))
-
-#define REG_BBC_TXMBEBT_FORMAT(dir_dly, min_be, ble, max_boffs, max_be) \
- (((min_be) & BIT_W_4) | \
- (((ble) & BIT_W_1) << REG_BBC_TXMBEBT_BLE_BIT) | \
- (((max_be) & BIT_W_4) << REG_BBC_TXMBEBT_MAXBE_BIT) | \
- (((max_boffs) & BIT_W_3) << REG_BBC_TXMBEBT_MAXBO_BIT) | \
- (((dir_dly) & BIT_W_4) << REG_BBC_TXMBEBT_DIR_DLY_BIT) \
- )
-
-/**** REG_TXSTAT ****/
-
-#define REG_BBC_TXSTAT_CCAE_BIT 0
-#define REG_BBC_TXSTAT_CCAE_MASK ((uint32)(BIT_W_1 << REG_BBC_TXSTAT_CCAE_BIT))
-#define REG_BBC_TXSTAT_ACKE_BIT 1
-#define REG_BBC_TXSTAT_ACKE_MASK ((uint32)(BIT_W_1 << REG_BBC_TXSTAT_ACKE_BIT))
-#define REG_BBC_TXSTAT_OOTE_BIT 2
-#define REG_BBC_TXSTAT_OOTE_MASK ((uint32)(BIT_W_1 << REG_BBC_TXSTAT_OOTE_BIT))
-#define REG_BBC_TXSTAT_RXABT_BIT 3
-#define REG_BBC_TXSTAT_RXABT_MASK ((uint32)(BIT_W_1 << REG_BBC_TXSTAT_RXABT_BIT))
-#define REG_BBC_TXSTAT_RXFP_BIT 4
-#define REG_BBC_TXSTAT_RXFP_MASK ((uint32)(BIT_W_1 << REG_BBC_TXSTAT_RXFP_BIT))
-#define REG_BBC_TXSTAT_TXTO_BIT 5
-#define REG_BBC_TXSTAT_TXTO_MASK ((uint32)(BIT_W_1 << REG_BBC_TXSTAT_TXTO_BIT))
-#define REG_BBC_TXSTAT_TXPCTO_BIT 6
-#define REG_BBC_TXSTAT_TXPCTO_MASK ((uint32)(BIT_W_1 << REG_BBC_TXSTAT_TXPCTO_BIT))
-
-/**** TXCTL ****/
-
-#define REG_BBC_TXCTL_SCH_BIT 0
-#define REG_BBC_TXCTL_SCH_MASK ((uint32)(BIT_W_1 << REG_BBC_TXCTL_SCH_BIT))
-#define REG_BBC_TXCTL_SS_BIT 1
-#define REG_BBC_TXCTL_SS_MASK ((uint32)(BIT_W_1 << REG_BBC_TXCTL_SS_BIT))
-#define REG_BBC_TXCTL_SOVR_BIT 2
-#define REG_BBC_TXCTL_SOVR_MASK ((uint32)(BIT_W_1 << REG_BBC_TXCTL_SOVR_BIT))
-#define REG_BBC_TXCTL_AA_BIT 3
-#define REG_BBC_TXCTL_AA_MASK ((uint32)(BIT_W_1 << REG_BBC_TXCTL_AA_BIT))
-#define REG_BBC_TXCTL_MODE_BIT 4
-#define REG_BBC_TXCTL_MODE_MASK ((uint32)(BIT_W_2 << REG_BBC_TXCTL_MODE_BIT))
-
-#define REG_BBC_TXCTL_VALUE(sched_basis, sched_ss, slot_override, auto_ack, mode) \
- (((sched_basis) & BIT_W_1) | \
- (((sched_ss) & BIT_W_1) << REG_BBC_TXCTL_SS_BIT) | \
- (((slot_override) & BIT_W_1) << REG_BBC_TXCTL_SOVR_BIT) | \
- (((auto_ack) & BIT_W_1) << REG_BBC_TXCTL_AA_BIT) | \
- (((mode) & BIT_W_2) << REG_BBC_TXCTL_MODE_BIT))
-
-#define REG_BBC_TXCTL_SEND_AT(mode) REG_BBC_TXCTL_VALUE(1, 1, 0, 1, (mode))
-#define REG_BBC_TXCTL_SEND_NOW(mode) REG_BBC_TXCTL_VALUE(0, 1, 0, 1, (mode))
-
-/**** RXMPID ****/
-#define REG_BBC_RXMPID_PAN_ID_BIT 0
-#define REG_BBC_RXMPID_PAN_ID_MASK ((uint32)(BIT_W_16 << REG_BBC_RXMPID_PAN_ID_BIT))
-#define REG_BBC_RXMPID_COORD_BIT 16
-#define REG_BBC_RXMPID_COORD_MASK ((uint32)(BIT_W_1 << REG_BBC_RXMPID_COORD_BIT))
-
-/**** RXPROM ****/
-#define REG_BBC_RXPROM_AM_BIT 0
-#define REG_BBC_RXPROM_AM_MASK ((uint32)(BIT_W_1 << REG_BBC_RXPROM_AM_BIT))
-#define REG_BBC_RXPROM_FCSE_BIT 1
-#define REG_BBC_RXPROM_FCSE_MASK ((uint32)(BIT_W_1 << REG_BBC_RXPROM_FCSE_BIT))
-#define REG_BBC_RXPROM_AMAL_BIT 2
-#define REG_BBC_RXPROM_AMAL_MASK ((uint32)(BIT_W_1 << REG_BBC_RXPROM_AMAL_BIT))
-
-/**** REG_RXSTAT ****/
-#define REG_BBC_RXSTAT_FCSE_BIT 0
-#define REG_BBC_RXSTAT_FCSE_MASK ((uint32)(BIT_W_1 << REG_BBC_RXSTAT_FCSE_BIT))
-#define REG_BBC_RXSTAT_ABORT_BIT 1
-#define REG_BBC_RXSTAT_ABORT_MASK ((uint32)(BIT_W_1 << REG_BBC_RXSTAT_ABORT_BIT))
-#define REG_BBC_RXSTAT_INPKT_BIT 4
-#define REG_BBC_RXSTAT_INPKT_MASK ((uint32)(BIT_W_1 << REG_BBC_RXSTAT_INPKT_BIT))
-#define REG_BBC_RXSTAT_MAL_BIT 5
-#define REG_BBC_RXSTAT_MAL_MASK ((uint32)(BIT_W_1 << REG_BBC_RXSTAT_MAL_BIT))
-
-
-/**** RXCTL ****/
-
-#define REG_BBC_RXCTL_SCH_BIT 0
-#define REG_BBC_RXCTL_SCH_MASK ((uint32)(BIT_W_1 << REG_BBC_RXCTL_SCH_BIT))
-#define REG_BBC_RXCTL_SS_BIT 1
-#define REG_BBC_RXCTL_SS_MASK ((uint32)(BIT_W_1 << REG_BBC_RXCTL_SS_BIT))
-#define REG_BBC_RXCTL_ICAP_BIT 2
-#define REG_BBC_RXCTL_ICAP_MASK ((uint32)(BIT_W_1 << REG_BBC_RXCTL_ICAP_BIT))
-#define REG_BBC_RXCTL_AA_BIT 3
-#define REG_BBC_RXCTL_AA_MASK ((uint32)(BIT_W_1 << REG_BBC_RXCTL_AA_BIT))
-#define REG_BBC_RXCTL_PRSP_BIT 4
-#define REG_BBC_RXCTL_PRSP_MASK ((uint32)(BIT_W_1 << REG_BBC_RXCTL_PRSP_BIT))
-
-#define REG_BBC_RXCTL_FORMAT(sched_basis, sched_ss, in_cap, auto_ack) \
- (((sched_basis) & BIT_W_1) | \
- (((sched_ss) & BIT_W_1) << REG_BBC_RXCTL_SS_BIT) | \
- (((in_cap) & BIT_W_1) << REG_BBC_RXCTL_ICAP_BIT) | \
- (((auto_ack) & BIT_W_1) << REG_BBC_RXCTL_AA_BIT))
-
-/**** SM_STATE ****/
-#define REG_BBC_SM_STATE_SUP_BIT 0
-#define REG_BBC_SM_STATE_SUP_MASK ((uint32)(BIT_W_4 << REG_BBC_SM_STATE_SUP_BIT))
-#define REG_BBC_SM_STATE_CSMA_BIT 4
-#define REG_BBC_SM_STATE_CSMA_MASK ((uint32)(BIT_W_3 << REG_BBC_SM_STATE_CSMA_BIT))
-#define REG_BBC_SM_STATE_ISA_BIT 8
-#define REG_BBC_SM_STATE_ISA_MASK ((uint32)(BIT_W_5 << REG_BBC_SM_STATE_ISA_BIT))
-
-/**** SCTCR ****/
-
-#define REG_BBC_SCTCR_E0_BIT 0
-#define REG_BBC_SCTCR_E0_MASK ((uint32)(BIT_W_1 << REG_BBC_SCTCR_E0_BIT))
-#define REG_BBC_SCTCR_E1_BIT 1
-#define REG_BBC_SCTCR_E1_MASK ((uint32)(BIT_W_1 << REG_BBC_SCTCR_E1_BIT))
-
-/**** SCTL ****/
-#define REG_BBC_SCTL_USE_BIT 0
-#define REG_BBC_SCTL_USE_MASK ((uint32)(BIT_W_1 << REG_BBC_SCTL_USE_BIT))
-#define REG_BBC_SCTL_SNAP_BIT 1
-#define REG_BBC_SCTL_SNAP_MASK ((uint32)(BIT_W_1 << REG_BBC_SCTL_SNAP_BIT))
-#define REG_BBC_SCTL_CO_BIT 2
-#define REG_BBC_SCTL_CO_MASK ((uint32)(BIT_W_1 << REG_BBC_SCTL_CO_BIT))
-// bit name changed
-#define REG_BBC_SCTL_CE_BIT 2
-#define REG_BBC_SCTL_CE_MASK ((uint32)(BIT_W_1 << REG_BBC_SCTL_CE_BIT))
-#define REG_BBC_SCTL_PHYON_BIT 3
-#define REG_BBC_SCTL_PHYON_MASK ((uint32)(BIT_W_1 << REG_BBC_SCTL_PHYON_BIT))
-
-/**** RXFCTL/TXFCTL ****/
-
-/* Operations on Frame header */
-#define REG_BBC_FCTL_TYPE_BIT 0
-#define REG_BBC_FCTL_TYPE_MASK ((uint32)(BIT_W_3/* << REG_BBC_FCTL_TYPE_BIT*/)) /* Optimised bit 0 */
-
-#define REG_BBC_FCTL_SEC_BIT 3
-#define REG_BBC_FCTL_SEC_MASK ((uint32)(BIT_W_1 << REG_BBC_FCTL_SEC_BIT))
-
-#define REG_BBC_FCTL_FP_BIT 4
-#define REG_BBC_FCTL_FP_MASK ((uint32)(BIT_W_1 << REG_BBC_FCTL_FP_BIT))
-
-#define REG_BBC_FCTL_ACK_BIT 5
-#define REG_BBC_FCTL_ACK_MASK ((uint32)(BIT_W_1 << REG_BBC_FCTL_ACK_BIT))
-
-#define REG_BBC_FCTL_IP_BIT 6
-#define REG_BBC_FCTL_IP_MASK ((uint32)(BIT_W_1 << REG_BBC_FCTL_IP_BIT))
-
-#define REG_BBC_FCTL_DAM_BIT 10
-#define REG_BBC_FCTL_DAM_MASK ((uint32)(BIT_W_2 << REG_BBC_FCTL_DAM_BIT))
-#define REG_BBC_FCTL_DAM(x) (((x) & REG_BBC_FCTL_DAM_MASK) >> REG_BBC_FCTL_DAM_BIT)
-
-#define REG_BBC_FCTL_SAM_BIT 14
-#define REG_BBC_FCTL_SAM_MASK ((uint32)(BIT_W_2 << REG_BBC_FCTL_SAM_BIT))
-#define REG_BBC_FCTL_SAM(x) (((x) & REG_BBC_FCTL_SAM_MASK) >> REG_BBC_FCTL_SAM_BIT)
-
-/* Frame types */
-#define REG_BBC_FCTL_TYPE_BEACON 0
-#define REG_BBC_FCTL_TYPE_DATA 1
-#define REG_BBC_FCTL_TYPE_ACK 2
-#define REG_BBC_FCTL_TYPE_CMD 3
-
-/* Addr modes */
-#define REG_BBC_FCTL_AM_NONE 0
-#define REG_BBC_FCTL_AM_RSVD 1
-#define REG_BBC_FCTL_AM_SHORT 2
-#define REG_BBC_FCTL_AM_EXT 3
-
-
-#define REG_BBC_FCTL_FORMAT(type, sec, fp, ack, ip, dam, sam) \
- (((type) & BIT_W_3) | \
- (((sec) & BIT_W_1) << REG_BBC_FCTL_SEC_BIT) | \
- (((fp) & BIT_W_1) << REG_BBC_FCTL_FP_BIT) | \
- (((ack) & BIT_W_1) << REG_BBC_FCTL_ACK_BIT) | \
- (((ip) & BIT_W_1) << REG_BBC_FCTL_IP_BIT) | \
- (((dam) & BIT_W_2) << REG_BBC_FCTL_DAM_BIT) | \
- (((sam) & BIT_W_2) << REG_BBC_FCTL_SAM_BIT))
-
-
-/**** MCCA_CTRL ****/
-#define REG_PHY_MCCA_CCAM_BIT 0
-#define REG_PHY_MCCA_CCAM_MASK ((uint32)(BIT_W_2 << REG_PHY_MCCA_CCAM_BIT))
-#define REG_PHY_MCCA_CCA_ED_THR_BIT 2
-#define REG_PHY_MCCA_CCA_ED_THR_MASK ((uint32)(BIT_W_10 << REG_PHY_MCCA_CCA_ED_THR_BIT))
-
-/**** MSTAT ****/
-#define REG_PHY_MSTAT_ED_BIT 6
-#define REG_PHY_MSTAT_ED_MASK ((uint32)(BIT_W_10 << REG_PHY_MSTAT_ED_BIT))
-#define REG_PHY_MSTAT_SQI_BIT 16
-#define REG_PHY_MSTAT_SQI_MASK ((uint32)(BIT_W_8 << REG_PHY_MSTAT_SQI_BIT))
-#define REG_PHY_MSTAT_MCCAS_BIT 24
-#define REG_PHY_MSTAT_MCCAS_MASK ((uint32)(BIT_W_1 << REG_PHY_MSTAT_MCCAS_BIT))
-
-/**** PHY_MCTRL ****/
-#define REG_PHY_MCTRL_MIOM_BIT 1
-#define REG_PHY_MCTRL_MIOM_MASK ((uint32)(BIT_W_1 << REG_PHY_MCTRL_MIOM_BIT))
-#define REG_PHY_MCTRL_MPHYON_BIT 2
-#define REG_PHY_MCTRL_MPHYON_MASK ((uint32)(BIT_W_1 << REG_PHY_MCTRL_MPHYON_BIT))
-#define REG_PHY_MCTRL_MPHYTX_BIT 3
-#define REG_PHY_MCTRL_MPHYTX_MASK ((uint32)(BIT_W_1 << REG_PHY_MCTRL_MPHYTX_BIT))
-#define REG_PHY_MCTRL_MCCAT_BIT 4
-#define REG_PHY_MCTRL_MCCAT_MASK ((uint32)(BIT_W_1 << REG_PHY_MCTRL_MCCAT_BIT))
-#define REG_PHY_MCTRL_MEDT_BIT 5
-#define REG_PHY_MCTRL_MEDT_MASK ((uint32)(BIT_W_1 << REG_PHY_MCTRL_MEDT_BIT))
-
-/**** PHY_PWR ****/
-#define REG_PHY_PWR_BIT 0
-#define REG_PHY_PWR_MASK ((uint32)(BIT_W_1 << REG_PHY_PWR_BIT))
-
-/**** PHY IER/ISR ****/
-#define REG_PHY_INT_ED_BIT 3
-#define REG_PHY_INT_ED_MASK ((uint32)(BIT_W_1 << REG_PHY_INT_ED_BIT))
-#define REG_PHY_INT_CCA_BIT 4
-#define REG_PHY_INT_CCA_MASK ((uint32)(BIT_W_1 << REG_PHY_INT_CCA_BIT))
-
-/* Register equivalents, mapping from old names to new ones */
-#define REG_BBC_ISR ISR
-#define REG_BBC_IER IER
-#define REG_BBC_RXCTL RXCTL
-#define REG_BBC_SM_STATE SM_STATE
-#define REG_BBC_MISR MISR
-#define REG_BBC_SCFRC SCFRC
-#define REG_BBC_SCESL SCESL
-#define REG_BBC_RXMPID RXMPID
-#define REG_BBC_RXMSAD RXMSAD
-#define REG_BBC_RXMEADL RXMEADL
-#define REG_BBC_RXMEADH RXMEADH
-#define REG_BBC_RXETST RXETST
-#define REG_BBC_TXCTL TXCTL
-#define REG_BBC_SCTL SCTL
-#define REG_BBC_RXBUFAD RXBUFAD
-#define REG_BBC_RXPROM RXPROM
-#define REG_BBC_RXSTAT RXSTAT
-#define REG_BBC_RXTSTP RXTSTP
-#define REG_BBC_TXRETRY TXTRIES
-#define REG_BBC_TXMBEBT TXMBEBT
-#define REG_BBC_TXTSTP TXTSTP
-#define REG_BBC_TXCSMAC TXCSMAC
-#define REG_BBC_TXBUFAD TXBUFAD
-#define REG_BBC_TXSTAT TXSTAT
-#define REG_BBC_TXASC TXASC
-#define REG_BBC_PRBSS PRBS_SEED
-#define REG_BBC_SCMR0 SCMR0
-#define REG_BBC_SCTR1 SCTR1
-#define REG_BBC_SCTCR SCTCR
-#define REG_BBC_TXPEND TXPEND
-#define REG_BBC_PRTT PHYRXTUNETIME
-#define REG_BBC_TAT TURNAROUNDTIME
-#define REG_BBC_LIFS_TURNAROUND LIFSTURNAROUNDTIME
-#define REG_BBC_SCTR0 SCTR0
-
-#define REG_PHY_CHAN PHY_CHAN
-#define REG_PHY_MCTRL PHY_MCTRL
-#define REG_PHY_MSTAT0 MSTAT
-#define REG_PHY_MCCA MCCA_CTRL
-
-/****************************************************************************/
-/*** Exported Functions ***/
-/****************************************************************************/
-
-
-/****************************************************************************/
-/*** Exported Variables ***/
-/****************************************************************************/
-
-#if defined __cplusplus
-}
-#endif
-
-#endif /* #ifndef BBC_AND_PHY_REGS_H */
-
-/****************************************************************************/
-/*** END OF FILE ***/
-/****************************************************************************/
diff --git a/third_party/nxp/JN5189/Radio_JN5189/Include/jn518x.h b/third_party/nxp/JN5189/Radio_JN5189/Include/jn518x.h
deleted file mode 100755
index 93175ed..0000000
--- a/third_party/nxp/JN5189/Radio_JN5189/Include/jn518x.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#include "JN5189.h"
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#include "jn518xHW_ES1.h"
-#else
-#include "jn518xHW.h"
-#endif
diff --git a/third_party/nxp/JN5189/Radio_JN5189/Include/jn518xHW.h b/third_party/nxp/JN5189/Radio_JN5189/Include/jn518xHW.h
deleted file mode 100755
index ede036d..0000000
--- a/third_party/nxp/JN5189/Radio_JN5189/Include/jn518xHW.h
+++ /dev/null
@@ -1,22585 +0,0 @@
-/*
-* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
-* Copyright 2016-2019 NXP
-* All rights reserved.
-*
-* SPDX-License-Identifier: BSD-3-Clause
-*/
-
-/** @addtogroup nxp.com
- * @{
- */
-
-/** @addtogroup jn518x
- * @{
- */
-
-#ifndef _JN518XHW_H_
-#define _JN518XHW_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifndef _JN5189_H_
-/* ------------------------- Interrupt Number Definition ------------------------ */
-
-typedef enum {
-/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
- Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
- MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
- and No Match */
- BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
- related Fault */
- UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
- SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
- PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
- SysTick_IRQn = -1, /*!< 15 System Tick Timer */
-/* ---------------------- jn518x Specific Interrupt Numbers --------------------- */
-System_IRQn = 0, /*!< System (BOD, Watchdog Timer, Flash controller) interrupt */
-DMA_IRQn = 1, /*!< DMA interrupt */
-GINT_IRQn = 2, /*!< GPIO global interrupt */
-IRBlaster_IRQn = 3, /*!< Infra Red Blaster */
-PINT0_IRQn = 4, /*!< Pin Interrupt (and Pattern matching) 0 */
-PINT1_IRQn = 5, /*!< Pin Interrupt (and Pattern matching) 1 */
-PINT2_IRQn = 6, /*!< Pin Interrupt (and Pattern matching) 2 */
-PINT3_IRQn = 7, /*!< Pin Interrupt (and Pattern matching) 3 */
-SPIFI_IRQn = 8, /*!< Quad-SPI flash interface interrupt */
-Timer0_IRQn = 9, /*!< Counter/Timer 0 interrupt */
-Timer1_IRQn = 10, /*!< Counter/Timer 1 interrupt */
-USART0_IRQn = 11,
-USART1_IRQn = 12,
-I2C0_IRQn = 13,
-I2C1_IRQn = 14,
-SPI0_IRQn = 15,
-SPI1_IRQn = 16,
-PWM0_IRQn = 17, /*!< PWM channel 0 interrupt */
-PWM1_IRQn = 18, /*!< PWM channel 1 interrupt */
-PWM2_IRQn = 19, /*!< PWM channel 2 interrupt */
-PWM3_IRQn = 20, /*!< PWM channel 3 interrupt */
-PWM4_IRQn = 21, /*!< PWM channel 4 interrupt */
-PWM5_IRQn = 22, /*!< PWM channel 5 interrupt */
-PWM6_IRQn = 23, /*!< PWM channel 6 interrupt */
-PWM7_IRQn = 24, /*!< PWM channel 7 interrupt */
-PWM8_IRQn = 25, /*!< PWM channel 8 interrupt */
-PWM9_IRQn = 26, /*!< PWM channel 9 interrupt */
-PWM10_IRQn = 27, /*!< PWM channel 10 interrupt */
-I2C2_IRQn = 28,
-RTC_IRQn = 29,
-NFCTag_IRQn = 30,
-MAILBOX_IRQn = 31,
-ADC_SEQA_IRQn = 32,
-ADC_SEQB_IRQn = 33,
-ADC_THCMP_OVR_IRQn = 34,
-DMIC_IRQn = 35,
-HWVAD_IRQn = 36,
-BLE_DP_IRQn = 37,
-BLE_DP0_IRQn = 38,
-BLE_DP1_IRQn = 39,
-BLE_DP2_IRQn = 40,
-BLE_LL_ALL_IRQn = 41,
-ZIGBEE_MAC_IRQn = 42,
-ZIGBEE_MODEM_IRQn = 43,
-RFP_TMU_IRQn = 44,
-RFP_AGC_IRQn = 45,
-ISO7816_IRQn = 46,
-ANA_COMP_IRQn = 47,
-WAKE_UP_TIMER0_IRQn = 48,
-WAKE_UP_TIMER1_IRQn = 49,
-PVT_AMBER0_IRQn = 50,
-PVT_RED0_IRQn = 51,
-PVT_AMBER1_IRQn = 52,
-PVT_RED1_IRQn = 53,
-BLE_WAKE_TIMER_IRQn = 54,
-HASH_IRQn = 55,
-} IRQn_Type;
-
-#else
-
-#undef AES
-#undef CODEPATCH
-#undef DMA
-#undef DMIC
-#undef FLASH
-#undef GINT
-#undef GPIO
-#undef I2C0
-#undef I2C1
-#undef I2C2
-#undef IOCON
-#undef IR
-#undef ISO7816
-#undef MAILBOX
-#undef OTPC
-#undef PINT
-#undef PMC
-#undef PVT
-#undef PWM
-#undef RNG
-#undef RTC
-#undef SPI0
-#undef SPI1
-#undef SPIFI
-#undef SYSCON
-#undef USART0
-#undef USART1
-#undef WWDT
-#undef HASH
-
-#endif
-
-/** @addtogroup Configuration_of_CMSIS
- * @{
- */
-
-
-/* ================================================================================ */
-/* ================ Processor and Core Peripheral Section ================ */
-/* ================================================================================ */
-
-#ifndef _JN5189_H_
-
-/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
- /* ES1 if explicitly configured */
-#define __CM4_REV 0x0000 /*!< Cortex-M4 Core Revision */
-#else
- /* ES2 default */
-#define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */
-#endif
-#define __MPU_PRESENT 0 /*!< MPU present or not */
-#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 0 /*!< FPU present or not */
-/** @} */ /* End of group Configuration_of_CMSIS */
-#endif
-
-#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
-#include "system_jn518x.h" /*!< jn518x System */
-
-
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
-
-
-/** @addtogroup Device_Peripheral_Registers
- * @{
- */
-
-
-/* ------------------- Start of section using anonymous unions ------------------ */
-#if defined(__CC_ARM)
- #pragma push
- #pragma anon_unions
-#elif defined(__ICCARM__)
- #pragma language=extended
-#elif defined(__GNUC__)
- /* anonymous unions are enabled by default */
-#elif defined(__TMS470__)
-/* anonymous unions are enabled by default */
-#elif defined(__TASKING__)
- #pragma warning 586
-#else
- #warning Not supported compiler type
-#endif
-
-
-typedef struct {
- union {
- __IO uint32_t CFG; /*!< Configuration register for DMA channel x */
-
- struct {
- __IO uint32_t PERIPHREQEN: 1; /*!< Peripheral request Enable. If a DMA channel is used to perform
- a memory-to-memory move, any peripheral DMA request associated
- with that channel can be disabled to prevent any interaction
- between the peripheral and the DMA controller. 0 Disabled. Peripheral
- DMA requests are disabled. 1 Enabled. Peripheral DMA requests
- are enabled. */
- __IO uint32_t HWTRIGEN : 1; /*!< Hardware Triggering Enable for this channel. 0 Disabled. Hardware
- triggering is not used. 1 Enabled. Use hardware triggering. */
- uint32_t : 2;
- __IO uint32_t TRIGPOL : 1; /*!< Trigger Polarity. Selects the polarity of a hardware trigger
- for this channel. 0 Active low - falling edge. Hardware trigger
- is active low or falling edge triggered, based on TRIGTYPE.
- 1 Active high - rising edge. Hardware trigger is active high
- or rising edge triggered, based on TRIGTYPE. */
- __IO uint32_t TRIGTYPE : 1; /*!< Trigger Type. Selects hardware trigger as edge triggered or
- level triggered. 0 Edge. Hardware trigger is edge triggered.
- Transfers will be initiated and completed, as specified for
- a single trigger. 1 Level. Hardware trigger is level triggered.
- Note that when level triggering without burst (BURSTPOWER =
- 0) is selected, only hardware triggers should be used on that
- channel. Transfers continue as long as the trigger level is
- asserted. Once the trigger is de-asserted, the transfer will
- be paused until the tri */
- __IO uint32_t TRIGBURST : 1; /*!< Trigger Burst. Selects whether hardware triggers cause a single
- or burst transfer. 0 Single transfer. Hardware trigger causes
- a single transfer. 1 Burst transfer. When the trigger for this
- channel is set to edge triggered, a hardware trigger causes
- a burst transfer, as defined by BURSTPOWER. When the trigger
- for this channel is set to level triggered, a hardware trigger
- causes transfers to continue as long as the trigger is asserted,
- unless the transfer is complete. */
- uint32_t : 1;
- __IO uint32_t BURSTPOWER : 4; /*!< Burst Power is used in two ways. It always selects the address
- wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected
- (see descriptions elsewhere in this register). When the TRIGBURST
- field elsewhere in this register = 1, Burst Power selects how
- many transfers are performed for each DMA trigger. This can
- be used, for example, with peripherals that contain a FIFO that
- can initiate a DMA operation when the FIFO reaches a certain
- level. 0000: Burst size = 1 (2^0). 0001: Burst size = 2 (2^1).
- 0010: */
- uint32_t : 2;
- __IO uint32_t SRCBURSTWRAP: 1; /*!< Source Burst Wrap. When enabled, the source data address for
- the DMA is wrapped , meaning that the source address range for
- each burst will be the same. As an example, this could be used
- to read several sequential registers from a peripheral for each
- DMA burst, reading the same registers again for each burst.
- 0 Disabled. Source burst wrapping is not enabled for this DMA
- channel. 1 Enabled. Source burst wrapping is enabled for this
- DMA channel. */
- __IO uint32_t DSTBURSTWRAP: 1; /*!< Destination Burst Wrap. When enabled, the destination data address
- for the DMA is wrapped , meaning that the destination address
- range for each burst will be the same. As an example, this could
- be used to write several sequential registers to a peripheral
- for each DMA burst, writing the same registers again for each
- burst. 0 Disabled. Destination burst wrapping is not enabled
- for this DMA channel. 1 Enabled. Destination burst wrapping
- is enabled for this DMA channel. */
- __IO uint32_t CHPRIORITY : 3; /*!< Priority of this channel when multiple DMA requests are pending.
- Eight priority levels are supported: 0x0 = highest priority.
- 0x7 = lowest priority. */
- } CFG_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t CTLSTAT; /*!< Control and status register for DMA channel x */
-
- struct {
- __I uint32_t VALIDPENDING: 1; /*!< Valid pending flag for this channel. This bit is set when a
- 1 is written to the corresponding bit in the related SETVALID
- register when CFGVALID = 1 for the same channel. 0 No effect.
- No effect on DMA operation. 1 Valid pending. */
- uint32_t : 1;
- __I uint32_t TRIG : 1; /*!< Trigger flag. Indicates that the trigger for this channel is
- currently set. This bit is cleared at the end of an entire transfer
- or upon reload when CLRTRIG = 1. 0 Not triggered. The trigger
- for this DMA channel is not set. DMA operations will not be
- carried out. 1 Triggered. The trigger for this DMA channel is
- set. DMA operations will be carried out. */
- } CTLSTAT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t XFERCFG; /*!< Transfer configuration register for DMA channel x */
-
- struct {
- __IO uint32_t CFGVALID : 1; /*!< Configuration Valid flag. This bit indicates whether the current
- channel descriptor is valid and can potentially be acted upon,
- if all other activation criteria are fulfilled. 0 Not valid.
- The channel descriptor is not considered valid until validated
- by an associated SETVALID0 setting. 1 Valid. The current channel
- descriptor is considered valid. */
- __IO uint32_t RELOAD : 1; /*!< Indicates whether the channel s control structure will be reloaded
- when the current descriptor is exhausted. Reloading allows ping-pong
- and linked transfers. 0 Disabled. Do not reload the channels
- control structure when the current descriptor is exhausted.
- 1 Enabled. Reload the channels control structure when the current
- descriptor is exhausted. */
- __IO uint32_t SWTRIG : 1; /*!< Software Trigger. 0 Not set. When written by software, the trigger
- for this channel is not set. A new trigger, as defined by the
- HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the
- channel. 1 Set. When written by software, the trigger for this
- channel is set immediately. This feature should not be used
- with level triggering when TRIGBURST = 0. */
- __IO uint32_t CLRTRIG : 1; /*!< Clear Trigger. 0 Not cleared. The trigger is not cleared when
- this descriptor is exhausted. If there is a reload, the next
- descriptor will be started. 1 Cleared. The trigger is cleared
- when this descriptor is exhausted. */
- __IO uint32_t SETINTA : 1; /*!< Set Interrupt flag A for this channel. There is no hardware
- distinction between interrupt A and B. They can be used by software
- to assist with more complex descriptor usage. By convention,
- interrupt A may be used when only one interrupt flag is needed.
- 0 No effect. 1 Set. The INTA flag for this channel will be set
- when the current descriptor is exhausted. */
- __IO uint32_t SETINTB : 1; /*!< Set Interrupt flag B for this channel. There is no hardware
- distinction between interrupt A and B. They can be used by software
- to assist with more complex descriptor usage. By convention,
- interrupt A may be used when only one interrupt flag is needed.
- 0 No effect. 1 Set. The INTB flag for this channel will be set
- when the current descriptor is exhausted. */
- uint32_t : 2;
- __IO uint32_t WIDTH : 2; /*!< Transfer width used for this DMA channel. 0x0 8-bit. 8-bit transfers
- are performed (8-bit source reads and destination writes). 0x1
- 16-bit. 6-bit transfers are performed (16-bit source reads and
- destination writes). 0x2 32-bit. 32-bit transfers are performed
- (32-bit source reads and destination writes). 0x3 Reserved.
- Reserved setting, do not use. */
- uint32_t : 2;
- __IO uint32_t SRCINC : 2; /*!< Determines whether the source address is incremented for each
- DMA transfer. 0x0 No increment. The source address is not incremented
- for each transfer. This is the usual case when the source is
- a peripheral device. 0x1 1 x width. The source address is incremented
- by the amount specified by Width for each transfer. This is
- the usual case when the source is memory. 0x2 2 x width. The
- source address is incremented by 2 times the amount specified
- by Width for each transfer. 0x3 4 x width. The source address
- is */
- __IO uint32_t DSTINC : 2; /*!< Determines whether the destination address is incremented for
- each DMA transfer. 0x0 No increment. The destination address
- is not incremented for each transfer. This is the usual case
- when the destination is a peripheral device. 0x1 1 x width.
- The destination address is incremented by the amount specified
- by Width for each transfer. This is the usual case when the
- destination is memory. 0x2 2 x width. The destination address
- is incremented by 2 times the amount specified by Width for
- each transfer. 0x3 4 x */
- __IO uint32_t XFERCOUNT : 10; /*!< Total number of transfers to be performed, minus 1 encoded.
- The number of bytes transferred is: (XFERCOUNT + 1) x data width
- (as defined by the WIDTH field). Remark: The DMA controller
- uses this bit field during transfer to count down. Hence, it
- cannot be used by software to read back the size of the transfer,
- for instance, in an interrupt handler. 0x0 = a total of 1 transfer
- will be performed. 0x1 = a total of 2 transfers will be performed.
- ... 0x3FF = a total of 1,024 transfers will be performed. */
- } XFERCFG_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t RESERVED0; /*!< Reserved */
-
- struct {
- __IO uint32_t DUMMYWORD : 32; /*!< Reserved. The value read from a reserved bit is not defined. */
- } RESERVED0_b; /*!< BitSize */
- };
-} u_dma_Channel_Type;
-
-
-/* ================================================================================ */
-/* ================ u_syscon ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component syscon. It is the System Control APB bus interface. More details will follow. (u_syscon)
- */
-
-typedef struct { /*!< u_syscon Structure */
-
- union {
- __IO uint32_t MEMORYREMAP; /*!< Memory Remap control register */
-
- struct {
- __IO uint32_t MAP : 2; /*!< Select the location of the vector table : 0:Vector Table in
- ROM 1:Vector Table in RAM 2:Vector Table in Flash 3:Vector Table
- in Flash */
- __IO uint32_t FLASH_REMAP_APP_0: 1; /*!< Controls remapping of Application 0 flash space 0 : No remapping
- of Application 0 Flash space 1 : Remapping of Application 0
- Flash space */
- __IO uint32_t FLASH_REMAP_APP_1: 1; /*!< Controls remapping of Application 1 flash space 0 : No remapping
- of Application 0 Flash space 1 : Remapping of Application 0
- Flash space */
- __IO uint32_t FLASH_APP_0_SIZE: 7; /*!< Application 0 flash size, in number of 8-KB units. Max allowed
- value is 80 (640 KB of Flash). */
- uint32_t : 1;
- __IO uint32_t FLASH_APP_1_SIZE: 7; /*!< Application 1 flash size, in number of 8-KB units. Max allowed
- value is 80 (640 KB of Flash). */
- uint32_t : 1;
- __IO uint32_t QSPI_REMAP_APP_0: 2; /*!< Address bits to use when QSPI Flash address [19:18] = 0 (256-KB
- unit page). */
- __IO uint32_t QSPI_REMAP_APP_1: 2; /*!< Address bits to use when QSPI Flash address [19:18] = 1 (256-KB
- unit page). */
- __IO uint32_t QSPI_REMAP_APP_2: 2; /*!< Address bits to use when QSPI Flash address [19:18] = 2 (256-KB
- unit page). */
- __IO uint32_t QSPI_REMAP_APP_3: 2; /*!< Address bits to use when QSPI Flash address [19:18] = 3 (256-KB
- unit page). */
- } MEMORYREMAP_b; /*!< BitSize */
- };
- __I uint32_t RESERVED0[3];
-
- union {
- __IO uint32_t AHBMATPRIO; /*!< AHB Matrix priority control register */
-
- struct {
- __IO uint32_t PRI_CM40_ICODE: 2; /*!< Cortex-M4 0 I-Code bus priority. Should typically be lower than
- PRI_DCODE for best operation. */
- __IO uint32_t PRI_CM40_DCODE: 2; /*!< Cortex-M4 0 D-Code bus priority. */
- __IO uint32_t PRI_CM40_SYS: 2; /*!< Cortex-M4 0 System bus priority. */
- __IO uint32_t PRI_DMA : 2; /*!< DMA controller priority. */
- __IO uint32_t PRI_MODEM : 2; /*!< MODEM Master priority. */
- __IO uint32_t PRI_CM41_ICODE: 2; /*!< Cortex-M4 1 I-Code bus priority. Should typically be lower than
- PRI_DCODE for best operation. */
- __IO uint32_t PRI_CM41_DCODE: 2; /*!< Cortex-M4 1 D-Code bus priority. */
- __IO uint32_t PRI_CM41_SYS: 2; /*!< Cortex-M4 1 System bus priority. */
- __IO uint32_t PRI_TPR : 2; /*!< Test Point Master bus priority. */
- } AHBMATPRIO_b; /*!< BitSize */
- };
- __I uint32_t RESERVED1[3];
-
- union {
- __IO uint32_t BUFFERINGAHB2VPB0; /*!< Buffering of write accesses on Synchronous System configuration
- APB interface */
-
- struct {
- __IO uint32_t SYSCON : 1; /*!< Enable buffering of write accesses on Synchronous System configuration
- APB interface. 0 = disable; 1 = Enable. */
- __IO uint32_t FIREWALL : 1; /*!< Enable buffering of write accesses on Firewall APB interface.
- 0 = disable; 1 = Enable. */
- __IO uint32_t OTPC : 1; /*!< Enable buffering of write accesses on eFUSE controller APB interface.
- 0 = disable; 1 = Enable. */
- __IO uint32_t I2C0 : 1; /*!< Enable buffering of write accesses on I2C0 APB interface. 0
- = disable; 1 = Enable. */
- __IO uint32_t I2C1 : 1; /*!< Enable buffering of write accesses on I2C1 APB interface. 0
- = disable; 1 = Enable. */
- __IO uint32_t I2C2 : 1; /*!< Enable buffering of write accesses on I2C2 APB interface. 0
- = disable; 1 = Enable. */
- __IO uint32_t ISO7816 : 1; /*!< Enable buffering of write accesses on ISO7816 APB interface.
- 0 = disable; 1 = Enable. */
- __IO uint32_t IR : 1; /*!< Enable buffering of write accesses on Infra red APB interface.
- 0 = disable; 1 = Enable. */
- __IO uint32_t CODEPATCH : 1; /*!< Enable buffering of write accesses on Code Patch Unit APB interface.
- 0 = disable; 1 = Enable. */
- __IO uint32_t FLASHCTRL : 1; /*!< Enable buffering of write accesses on Flash Controller APB interface.
- 0 = disable; 1 = Enable. */
- __IO uint32_t WDT : 1; /*!< Enable buffering of write accesses on Watchdog Timer APB interface.
- 0 = disable; 1 = Enable. */
- __IO uint32_t RTC : 1; /*!< Enable buffering of write accesses on RTC APB interface. 0 =
- disable; 1 = Enable. */
- __IO uint32_t PWM : 1; /*!< Enable buffering of write accesses on PWM APB interface. 0 =
- disable; 1 = Enable. */
- __IO uint32_t RNG : 1; /*!< Enable buffering of write accesses on Random Number Generator
- APB interface. 0 = disable; 1 = Enable. */
- __IO uint32_t PMUX : 1; /*!< Enable buffering of write accesses on Peripheral Input Mux APB
- interface. 0 = disable; 1 = Enable. */
- __IO uint32_t IOCON : 1; /*!< Enable buffering of write accesses on IO Configuration APB interface.
- 0 = disable; 1 = Enable. */
- __IO uint32_t GPIOINT : 1; /*!< Enable buffering of write accesses on GPIO Int APB interface.
- 0 = disable; 1 = Enable. */
- __IO uint32_t GPIOGLOBALINT: 1; /*!< Enable buffering of write accesses on GPIO Global Interrupt
- APB interface. 0 = disable; 1 = Enable. */
- __IO uint32_t PMC : 1; /*!< Enable buffering of write accesses on Power Management Controller
- APB interface. 0 = disable; 1 = Enable. */
- __IO uint32_t RFP : 1; /*!< Enable buffering of write accesses on RFP APB interface. 0 =
- disable; 1 = Enable. */
- __IO uint32_t BLE : 1; /*!< Enable buffering of write accesses on BLE Modem APB interface.
- 0 = disable; 1 = Enable. */
- } BUFFERINGAHB2VPB0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t BUFFERINGAHB2VPB1; /*!< Buffering of write accesses on Asynchronous System configuration
- APB interface */
-
- struct {
- __IO uint32_t ASYNCSYSCON: 1; /*!< Enable buffering of write accesses on Asynchronous System Configuration
- APB interface. 0 = disable; 1 = Enable. */
- __IO uint32_t CT32B0 : 1; /*!< Enable buffering of write accesses on Counter/Timer0 APB interface.
- 0 = disable; 1 = Enable. */
- __IO uint32_t CT32B1 : 1; /*!< Enable buffering of write accesses on Counter/Timer1 APB interface.
- 0 = disable; 1 = Enable. */
- } BUFFERINGAHB2VPB1_b; /*!< BitSize */
- };
- __I uint32_t RESERVED2[6];
-
- union {
- __IO uint32_t SYSTCKCAL; /*!< System tick counter calibration */
-
- struct {
- __IO uint32_t CAL : 24; /*!< Cortex System tick timer calibration value, readable from Cortex
- SYST_CALIB.TENMS register field. Set this value to be the number
- of clock periods to give 10ms period. SYSTICK freq is a function
- of the mainclk and SYSTICKCLKDIV register. If the tick timer
- is configured to use the System clock directly then this value
- must reflect the 10ms tick count for that clock. */
- __IO uint32_t SKEW : 1; /*!< Cortex System tick timer SYST_CALIB.SKEW setting. When 0, the
- value of SYST_CALIB.TENMS field is considered to be precise.
- When 1, the value of TENMS is not considered to be precise. */
- __IO uint32_t NOREF : 1; /*!< Cortex System tick timer SYST_CALIB.NOREF setting. When 0, a
- separate reference clock is available. When 1, a separate reference
- clock is not available. */
- } SYSTCKCAL_b; /*!< BitSize */
- };
- __I uint32_t RESERVED3;
-
- union {
- __IO uint32_t NMISRC; /*!< NMI Source Select */
-
- struct {
- __IO uint32_t IRQM40 : 6; /*!< The number of the interrupt source within the interrupt array
- that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M4
- 0, if enabled by NMIENM40. This can also cause the device to
- wakeup from sleep. */
- uint32_t : 2;
- __IO uint32_t IRQM41 : 6; /*!< The number of the interrupt source within the interrupt array
- that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M4
- 1, if enabled by NMIENM41. This can not cause the device to
- wakeup from sleep. */
- uint32_t : 16;
- __IO uint32_t NMIENM41 : 1; /*!< Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI)
- source selected by IRQM41 */
- __IO uint32_t NMIENM40 : 1; /*!< Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI)
- source selected by IRQM40 */
- } NMISRC_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t ASYNCAPBCTRL; /*!< Asynchronous APB Control */
-
- struct {
- __IO uint32_t ENABLE : 1; /*!< Enables the asynchronous APB bridge and subsystem */
- } ASYNCAPBCTRL_b; /*!< BitSize */
- };
- __I uint32_t RESERVED4[44];
-
- union {
- __IO uint32_t PRESETCTRL0; /*!< Peripheral reset control 0 */
-
- struct {
- uint32_t : 8;
- __IO uint32_t FLASH_RST : 1; /*!< Flash controller reset control. */
- uint32_t : 1;
- __IO uint32_t SPIFI_RST : 1; /*!< Quad SPI Flash controller reset control. */
- __IO uint32_t MUX_RST : 1; /*!< Input Mux reset control. */
- __IO uint32_t BLE_TIMING_GEN_RST: 1; /*!< BLE Low Power Control module reset */
- __IO uint32_t IOCON_RST : 1; /*!< I/O controller reset control. */
- __IO uint32_t GPIO_RST : 1; /*!< GPIO reset control. */
- uint32_t : 3;
- __IO uint32_t PINT_RST : 1; /*!< Pin interrupt (PINT) reset control. */
- __IO uint32_t GINT_RST : 1; /*!< Group interrupt (PINT) reset control. */
- __IO uint32_t DMA_RST : 1; /*!< DMA reset control. */
- __IO uint32_t ISO7816_RST: 1; /*!< ISO7816 reset control. */
- __IO uint32_t WWDT_RST : 1; /*!< Watchdog Timer reset control. */
- __IO uint32_t RTC_RST : 1; /*!< Real Time Clock (RTC) reset control. */
- __IO uint32_t ANA_INT_CTRL_RST: 1; /*!< Analog Modules Interrupt Controller reset control. */
- __IO uint32_t WAKE_UP_TIMERS_RST: 1; /*!< Wake up Timers reset control. This will clear interrupt status
- flag. However, configuration for wake timers that is in SYSCON
- will not be reset, these should be managed through the SYSCON
- regsiters. */
- __IO uint32_t MAILBOX_RST: 1; /*!< Inter CPU communication Mailbox reset control. */
- __IO uint32_t ADC_RST : 1; /*!< ADC reset control. */
- __IO uint32_t EFUSE_RST : 1; /*!< eFUSE Controller APB bus interface reset */
- __IO uint32_t PVT_RST : 1; /*!< PVT Sensors reset control */
- } PRESETCTRL0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PRESETCTRL1; /*!< Peripheral reset control 1 */
-
- struct {
- uint32_t : 11;
- __IO uint32_t USART0_RST : 1; /*!< UART0 reset control. */
- __IO uint32_t USART1_RST : 1; /*!< UART1 reset control. */
- __IO uint32_t I2C0_RST : 1; /*!< I2C0 reset control. */
- __IO uint32_t I2C1_RST : 1; /*!< I2C1 reset control. */
- __IO uint32_t SPI0_RST : 1; /*!< SPI0 reset control. */
- __IO uint32_t SPI1_RST : 1; /*!< SPI1 reset control. */
- __IO uint32_t IR_RST : 1; /*!< Infra Red reset control. */
- __IO uint32_t PWM_RST : 1; /*!< PWM reset control. */
- __IO uint32_t RNG_RST : 1; /*!< Random Number Generator reset control. */
- __IO uint32_t I2C2_RST : 1; /*!< I2C2 reset control. */
- __IO uint32_t ZIGBEE_RST : 1; /*!< Zigbee reset control. */
- __IO uint32_t BLE_RST : 1; /*!< BLE reset control. */
- __IO uint32_t MODEM_MASTER_RST: 1; /*!< MODEM AHB Master Interface reset control */
- __IO uint32_t AES_RST : 1; /*!< AES256 reset control. */
- __IO uint32_t RFP_RST : 1; /*!< RFP (Radio Front End controller) reset control */
- __IO uint32_t DMIC_RST : 1; /*!< DMIC Reset control */
- __IO uint32_t HASH_RST : 1; /*!< HASH reset control */
- __IO uint32_t TPR_RST : 1; /*!< Test Point Register Interface reset control */
- } PRESETCTRL1_b; /*!< BitSize */
- };
- __I uint32_t RESERVED5[6];
-
- union {
- __O uint32_t PRESETCTRLSET0; /*!< Set bits in PRESETCTRL0 */
-
- struct {
- uint32_t : 8;
- __O uint32_t FLASH_RST_SET: 1; /*!< Writing one to this register sets the FLASH_RST bit in the PRESETCTRL0
- register */
- uint32_t : 1;
- __O uint32_t SPIFI_RST_SET: 1; /*!< Writing one to this register sets the SPIFI_RST bit in the PRESETCTRL0
- register */
- __O uint32_t MUX_RST_SET: 1; /*!< Writing one to this register sets the MUX_RST bit in the PRESETCTRL0
- register */
- __O uint32_t BLE_TIMING_GEN_RST_SET: 1; /*!< Writing one to this register sets the BLE_TIMING_GEN_RST bit
- in the PRESETCTRL0 register */
- __O uint32_t IOCON_RST_SET: 1; /*!< Writing one to this register sets the IOCON_RST bit in the PRESETCTRL0
- register */
- __O uint32_t GPIO_RST_SET: 1; /*!< Writing one to this register sets the GPIO_RST bit in the PRESETCTRL0
- register */
- uint32_t : 3;
- __O uint32_t PINT_RST_SET: 1; /*!< Writing one to this register sets the PINT_RST bit in the PRESETCTRL0
- register */
- __O uint32_t GINT_RST_SET: 1; /*!< Writing one to this register sets the GINT_RST bit in the PRESETCTRL0
- register */
- __O uint32_t DMA_RST_SET: 1; /*!< Writing one to this register sets the DMA_RST bit in the PRESETCTRL0
- register */
- __O uint32_t ISO7816_RST_SET: 1; /*!< Writing one to this register sets the ISO7816_RST bit in the
- PRESETCTRL0 register */
- __O uint32_t WWDT_RST_SET: 1; /*!< Writing one to this register sets the WWDT_RST bit in the PRESETCTRL0
- register */
- __O uint32_t RTC_RST_SET: 1; /*!< Writing one to this register sets the RTC_RST bit in the PRESETCTRL0
- register */
- __O uint32_t ANA_INT_CTRL_RST_SET: 1; /*!< Writing one to this register sets the ANA_INT_CTRL_RST bit in
- the PRESETCTRL0 register */
- __O uint32_t WAKE_UP_TIMERS_RST_SET: 1; /*!< Writing one to this register sets the WAKE_UP_TIMERS bit in
- the PRESETCTRL0 register */
- __O uint32_t MAILBOX_RST_SET: 1; /*!< Writing one to this register sets the MAILBOX_RST bit in the
- PRESETCTRL0 register */
- __O uint32_t ADC_RST_SET: 1; /*!< Writing one to this register sets the ADC_RST bit in the PRESETCTRL0
- register */
- __O uint32_t EFUSE_RST_SET: 1; /*!< Writing one to this register sets the EFUSE_RST bit in the PRESETCTRL0
- register */
- __O uint32_t PVT_RST_SET: 1; /*!< Writing one to this register sets the PVT_RST bit in the PRESETCTRL0
- register */
- } PRESETCTRLSET0_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t PRESETCTRLSET1; /*!< Set bits in PRESETCTRL1 */
-
- struct {
- uint32_t : 11;
- __O uint32_t USART0_RST_SET: 1; /*!< Writing one to this register sets the UART0_RST bit in the PRESETCTRL1
- register */
- __O uint32_t USART1_RST_SET: 1; /*!< Writing one to this register sets the UART1_RST bit in the PRESETCTRL1
- register */
- __O uint32_t I2C0_RST_SET: 1; /*!< Writing one to this register sets the I2C0_RST bit in the PRESETCTRL1
- register */
- __O uint32_t I2C1_RST_SET: 1; /*!< Writing one to this register sets the I2C1_RST bit in the PRESETCTRL1
- register */
- __O uint32_t SPI0_RST_SET: 1; /*!< Writing one to this register sets the SPI0_RST bit in the PRESETCTRL1
- register */
- __O uint32_t SPI1_RST_SET: 1; /*!< Writing one to this register sets the SPI1_RST bit in the PRESETCTRL1
- register */
- __O uint32_t IR_RST_SET : 1; /*!< Writing one to this register sets the IR_RST bit in the PRESETCTRL1
- register */
- __O uint32_t PWM_RST_SET: 1; /*!< Writing one to this register sets the PWM_RST bit in the PRESETCTRL1
- register */
- __O uint32_t RNG_RST_SET: 1; /*!< Writing one to this register sets the RNG_RST bit in the PRESETCTRL1
- register */
- __O uint32_t I2C2_RST_SET: 1; /*!< Writing one to this register sets the I2C2_RST bit in the PRESETCTRL1
- register */
- __O uint32_t ZIGBEE_RST_SET: 1; /*!< Writing one to this register sets the ZIGBEE_RST bit in the
- PRESETCTRL1 register */
- __O uint32_t BLE_RST_SET: 1; /*!< Writing one to this register sets the BLE_RST bit in the PRESETCTRL1
- register */
- __O uint32_t MODEM_MASTER_RST_SET: 1; /*!< Writing one to this register sets the MODEM_MASTER_RST bit in
- the PRESETCTRL1 register */
- __O uint32_t AES_RST_SET: 1; /*!< Writing one to this register sets the AES_RST bit in the PRESETCTRL1
- register */
- __O uint32_t RFP_RST_SET: 1; /*!< Writing one to this register sets the RFP_RST bit in the PRESETCTRL1
- register */
- __O uint32_t DMIC_RST_SET: 1; /*!< Writing one to this register sets the DMIC_RST bit in the PRESETCTRL1
- register */
- __O uint32_t HASH_RST_SET: 1; /*!< Writing one to this register sets the HASH_RST bit in the PRESETCTRL1
- register */
- __O uint32_t TPR_RST_SET: 1; /*!< Writing one to this register sets the TPR_RST bit in the PRESETCTRL1
- register */
- } PRESETCTRLSET1_b; /*!< BitSize */
- };
- __I uint32_t RESERVED6[6];
-
- union {
- __O uint32_t PRESETCTRLCLR0; /*!< Clear bits in PRESETCTRL0 */
-
- struct {
- uint32_t : 8;
- __O uint32_t FLASH_RST_CLR: 1; /*!< Writing one to this register clears the FLASH_RST bit in the
- PRESETCTRL0 register */
- uint32_t : 1;
- __O uint32_t SPIFI_RST_CLR: 1; /*!< Writing one to this register clears the SPIFI_RST bit in the
- PRESETCTRL0 register */
- __O uint32_t MUX_RST_CLR: 1; /*!< Writing one to this register clears the MUX_RST bit in the PRESETCTRL0
- register */
- __O uint32_t BLE_TIMING_GEN_RST_CLR: 1; /*!< Writing one to this register clears the BLE_TIMING_GEN_RST bit
- in the PRESETCTRL0 register */
- __O uint32_t IOCON_RST_CLR: 1; /*!< Writing one to this register clears the IOCON_RST bit in the
- PRESETCTRL0 register */
- __O uint32_t GPIO_RST_CLR: 1; /*!< Writing one to this register clears the GPIO_RST bit in the
- PRESETCTRL0 register */
- uint32_t : 3;
- __O uint32_t PINT_RST_CLR: 1; /*!< Writing one to this register clears the PINT_RST bit in the
- PRESETCTRL0 register */
- __O uint32_t GINT_RST_CLR: 1; /*!< Writing one to this register clears the GINT_RST bit in the
- PRESETCTRL0 register */
- __O uint32_t DMA_RST_CLR: 1; /*!< Writing one to this register clears the DMA_RST bit in the PRESETCTRL0
- register */
- __O uint32_t ISO7816_RST_CLR: 1; /*!< Writing one to this register clears the ISO7816_RST bit in the
- PRESETCTRL0 register */
- __O uint32_t WWDT_RST_CLR: 1; /*!< Writing one to this register clears the WWDT_RST bit in the
- PRESETCTRL0 register */
- __O uint32_t RTC_RST_CLR: 1; /*!< Writing one to this register clears the RTC_RST bit in the PRESETCTRL0
- register */
- __O uint32_t ANA_INT_CTRL_RST_CLR: 1; /*!< Writing one to this register clears the ANA_INT_CTRL_RST bit
- in the PRESETCTRL0 register */
- __O uint32_t WAKE_UP_TIMERS_RST_CLR: 1; /*!< Writing one to this register clears the WAKE_UP_TIMERS_RST bit
- in the PRESETCTRL0 register */
- __O uint32_t MAILBOX_RST_CLR: 1; /*!< Writing one to this register clears the MAILBOX_RST bit in the
- PRESETCTRL0 register */
- __O uint32_t ADC_RST_CLR: 1; /*!< Writing one to this register clears the ADC_RST bit in the PRESETCTRL0
- register */
- __O uint32_t EFUSE_RST_CLR: 1; /*!< Writing one to this register clears the EFUSE_RST bit in the
- PRESETCTRL0 register */
- __O uint32_t PVT_RST_CLR: 1; /*!< Writing one to this register clears the PVT_RST bit in the PRESETCTRL0
- register */
- } PRESETCTRLCLR0_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t PRESETCTRLCLR1; /*!< Clear bits in PRESETCTRL1 */
-
- struct {
- uint32_t : 11;
- __O uint32_t USART0_RST_CLR: 1; /*!< Writing one to this register clears the UART0_RST bit in the
- PRESETCTRL1 register */
- __O uint32_t USART1_RST_CLR: 1; /*!< Writing one to this register clears the UART1_RST bit in the
- PRESETCTRL1 register */
- __O uint32_t I2C0_RST_CLR: 1; /*!< Writing one to this register clears the I2C0_RST bit in the
- PRESETCTRL1 register */
- __O uint32_t I2C1_RST_CLR: 1; /*!< Writing one to this register clears the I2C1_RST bit in the
- PRESETCTRL1 register */
- __O uint32_t SPI0_RST_CLR: 1; /*!< Writing one to this register clears the SPI0_RST bit in the
- PRESETCTRL1 register */
- __O uint32_t SPI1_RST_CLR: 1; /*!< Writing one to this register clears the SPI1_RST bit in the
- PRESETCTRL1 register */
- __O uint32_t IR_RST_CLR : 1; /*!< Writing one to this register clears the IR_RST bit in the PRESETCTRL1
- register */
- __O uint32_t PWM_RST_CLR: 1; /*!< Writing one to this register clears the PWM_RST bit in the PRESETCTRL1
- register */
- __O uint32_t RNG_RST_CLR: 1; /*!< Writing one to this register clears the RNG_RST bit in the PRESETCTRL1
- register */
- __O uint32_t I2C2_RST_CLR: 1; /*!< Writing one to this register clears the I2C2_RST bit in the
- PRESETCTRL1 register */
- __O uint32_t ZIGBEE_RST_CLR: 1; /*!< Writing one to this register clears the ZIGBEE_RST bit in the
- PRESETCTRL1 register */
- __O uint32_t BLE_RST_CLR: 1; /*!< Writing one to this register clears the BLE_RST bit in the PRESETCTRL1
- register */
- __O uint32_t MODEM_MASTER_RST_CLR: 1; /*!< Writing one to this register clears the MODEM_MASTER_RST bit
- in the PRESETCTRL1 register */
- __O uint32_t AES_RST_CLR: 1; /*!< Writing one to this register clears the AES_RST bit in the PRESETCTRL1
- register */
- __O uint32_t RFP_RST_CLR: 1; /*!< Writing one to this register clears the RFP_RST bit in the PRESETCTRL1
- register */
- __O uint32_t DMIC_RST_CLR: 1; /*!< Writing one to this register clears the DMIC_RST bit in the
- PRESETCTRL1 register */
- __O uint32_t HASH_RST_CLR: 1; /*!< Writing one to this register clears the HASH_RST bit in the
- PRESETCTRL1 register */
- __O uint32_t TPR_RST_CLR: 1; /*!< Writing one to this register clears the TPR_RST bit in the PRESETCTRL1
- register */
- } PRESETCTRLCLR1_b; /*!< BitSize */
- };
- __I uint32_t RESERVED7[46];
-
- union {
- __IO uint32_t AHBCLKCTRL0; /*!< AHB Clock control 0 */
-
- struct {
- uint32_t : 1;
- __IO uint32_t ROM : 1; /*!< Enables the clock for the ROM */
- uint32_t : 1;
- __IO uint32_t SRAM_CTRL0 : 1; /*!< Enables the clock for the SRAM Controller 0 (SRAM 0 to SRAM
- 5) */
- __IO uint32_t SRAM_CTRL1 : 1; /*!< Enables the clock for the SRAM Controller 1 (SRAM 6 to SRAM
- 7) */
- uint32_t : 3;
- __IO uint32_t FLASH : 1; /*!< Enables the clock for the Flash controller */
- uint32_t : 1;
- __IO uint32_t SPIFI : 1; /*!< Enables the clock for the Quad SPI Flash controller [Note: SPIFI
- IOs need configuring for high drive] */
- __IO uint32_t MUX : 1; /*!< Enables the clock for the Input Mux */
- uint32_t : 1;
- __IO uint32_t IOCON : 1; /*!< Enables the clock for the I/O controller */
- __IO uint32_t GPIO : 1; /*!< Enables the clock for the GPIO */
- uint32_t : 3;
- __IO uint32_t PINT : 1; /*!< Enables the clock for the Pin interrupt (PINT) */
- __IO uint32_t GINT : 1; /*!< Enables the clock for the Group interrupt (GINT) */
- __IO uint32_t DMA : 1; /*!< Enables the clock for the DMA */
- __IO uint32_t ISO7816 : 1; /*!< Enables the clock for the ISO7816 */
- __IO uint32_t WWDT : 1; /*!< Enables the clock for the Watchdog Timer */
- __IO uint32_t RTC : 1; /*!< Enables the clock for the RTC */
- __IO uint32_t ANA_INT_CTRL: 1; /*!< Enables the clock for the Analog Interrupt Control module (for
- BOD and comparator status and interrupt control) */
- __IO uint32_t WAKE_UP_TIMERS: 1; /*!< Enables the clock for the Wake up Timers */
- __IO uint32_t MAILBOX : 1; /*!< Enables the clock for the Mailbox */
- __IO uint32_t ADC : 1; /*!< Enables the clock for the ADC Controller */
- __IO uint32_t EFUSE : 1; /*!< Enables the (APB interface) clock for the EFUSE Controller */
- __IO uint32_t PVT : 1; /*!< Enables the clock for the PVT Controller */
- } AHBCLKCTRL0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t AHBCLKCTRL1; /*!< AHB Clock control 1 */
-
- struct {
- uint32_t : 11;
- __IO uint32_t USART0 : 1; /*!< Enable the clock for the UART0 . */
- __IO uint32_t USART1 : 1; /*!< Enable the clock for the UART1 . */
- __IO uint32_t I2C0 : 1; /*!< Enable the clock for the I2C0 . */
- __IO uint32_t I2C1 : 1; /*!< Enable the clock for the I2C1 . */
- __IO uint32_t SPI0 : 1; /*!< Enable the clock for the SPI0 . */
- __IO uint32_t SPI1 : 1; /*!< Enable the clock for the SPI1 . */
- __IO uint32_t IR : 1; /*!< Enable the clock for the Infra Red . */
- __IO uint32_t PWM : 1; /*!< Enable the clock for the PWM . */
- __IO uint32_t RNG : 1; /*!< Enable the clock for the Random Number Generator . */
- __IO uint32_t I2C2 : 1; /*!< Enable the clock for the I2C2 . */
- __IO uint32_t ZIGBEE : 1; /*!< Enable the clock for the Zigbee Modem . */
- __IO uint32_t BLE : 1; /*!< Enable the clock for the BLE Modem . */
- __IO uint32_t MODEM_MASTER: 1; /*!< Enable the clock for the Modem AHB Master Interface . */
- __IO uint32_t AES : 1; /*!< Enable the clock for the AES . */
- __IO uint32_t RFP : 1; /*!< Enable the clock for the RFP (Radio Front End controller) */
- __IO uint32_t DMIC : 1; /*!< Enable the clock for the DMIC */
- __IO uint32_t HASH : 1; /*!< Enable the clock for the Hash . */
- __IO uint32_t TPR : 1; /*!< Enable the clock for the TPR (Test Point Register) */
- } AHBCLKCTRL1_b; /*!< BitSize */
- };
- __I uint32_t RESERVED8[6];
-
- union {
- __O uint32_t AHBCLKCTRLSET0; /*!< Set bits in AHBCLKCTRL0 */
-
- struct {
- uint32_t : 1;
- __O uint32_t ROM_CLK_SET: 1; /*!< Writing one to this register sets the ROM bit in the AHBCLKCTRL0
- register. */
- uint32_t : 1;
- __O uint32_t SRAM_CTRL0_CLK_SET: 1; /*!< Writing one to this register sets the SRAM_CTRL0 bit in the
- AHBCLKCTRL0 register. */
- __O uint32_t SRAM_CTRL1_CLK_SET: 1; /*!< Writing one to this register sets the SRAM_CTRL1 bit in the
- AHBCLKCTRL0 register. */
- uint32_t : 3;
- __O uint32_t FLASH_CLK_SET: 1; /*!< Writing one to this register sets the FLASH bit in the AHBCLKCTRL0
- register. */
- uint32_t : 1;
- __O uint32_t SPIFI_CLK_SET: 1; /*!< Writing one to this register sets the SPIFI bit in the AHBCLKCTRL0
- register. */
- __O uint32_t MUX_CLK_SET: 1; /*!< Writing one to this register sets the MUX bit in the AHBCLKCTRL0
- register. */
- uint32_t : 1;
- __O uint32_t IOCON_CLK_SET: 1; /*!< Writing one to this register sets the IOCON bit in the AHBCLKCTRL0
- register. */
- __O uint32_t GPIO_CLK_SET: 1; /*!< Writing one to this register sets the GPIO bit in the AHBCLKCTRL0
- register. */
- uint32_t : 3;
- __O uint32_t PINT_CLK_SET: 1; /*!< Writing one to this register sets the PINT bit in the AHBCLKCTRL0
- register. */
- __O uint32_t GINT_CLK_SET: 1; /*!< Writing one to this register sets the GINT bit in the AHBCLKCTRL0
- register. */
- __O uint32_t DMA_CLK_SET: 1; /*!< Writing one to this register sets the DMA bit in the AHBCLKCTRL0
- register. */
- __O uint32_t ISO7816_CLK_SET: 1; /*!< Writing one to this register sets the ISO7816 bit in the AHBCLKCTRL0
- register. */
- __O uint32_t WWDT_CLK_SET: 1; /*!< Writing one to this register sets the WWDT bit in the AHBCLKCTRL0
- register. */
- __O uint32_t RTC_CLK_SET: 1; /*!< Writing one to this register sets the RTC bit in the AHBCLKCTRL0
- register. */
- __O uint32_t ANA_INT_CTRL_CLK_SET: 1; /*!< Writing one to this register sets the ANA_INT_CTRL bit in the
- AHBCLKCTRL0 register. */
- __O uint32_t WAKE_UP_TIMERS_CLK_SET: 1; /*!< Writing one to this register sets the WAKE_UP_TIMERS bit in
- the AHBCLKCTRL0 register. */
- __O uint32_t MAILBOX_CLK_SET: 1; /*!< Writing one to this register sets the MAILBOX bit in the AHBCLKCTRL0
- register. */
- __O uint32_t ADC_CLK_SET: 1; /*!< Writing one to this register sets the ADC bit in the AHBCLKCTRL0
- register. */
- __O uint32_t EFUSE_CLK_SET: 1; /*!< Writing one to this register sets the EFUSE bit in the AHBCLKCTRL0
- register. */
- __O uint32_t PVT_CLK_SET: 1; /*!< Writing one to this register sets the PVT bit in the AHBCLKCTRL0
- register. */
- } AHBCLKCTRLSET0_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t AHBCLKCTRLSET1; /*!< Set bits in AHBCLKCTRL1 */
-
- struct {
- uint32_t : 11;
- __O uint32_t USART0_CLK_SET: 1; /*!< Writing one to this register sets the UART0 bit in the AHBCLKCTRL1
- register. */
- __O uint32_t USART1_CLK_SET: 1; /*!< Writing one to this register sets the UART1 bit in the AHBCLKCTRL1
- register. */
- __O uint32_t I2C0_CLK_SET: 1; /*!< Writing one to this register sets the I2C0 bit in the AHBCLKCTRL1
- register. */
- __O uint32_t I2C1_CLK_SET: 1; /*!< Writing one to this register sets the I2C1 bit in the AHBCLKCTRL1
- register. */
- __O uint32_t SPI0_CLK_SET: 1; /*!< Writing one to this register sets the SPI0 bit in the AHBCLKCTRL1
- register. */
- __O uint32_t SPI1_CLK_SET: 1; /*!< Writing one to this register sets the SPI1 bit in the AHBCLKCTRL1
- register. */
- __O uint32_t IR_CLK_SET : 1; /*!< Writing one to this register sets the IR bit in the AHBCLKCTRL1
- register. */
- __O uint32_t PWM_CLK_SET: 1; /*!< Writing one to this register sets the PWM bit in the AHBCLKCTRL1
- register. */
- __O uint32_t RNG_CLK_SET: 1; /*!< Writing one to this register sets the RNG bit in the AHBCLKCTRL1
- register. */
- __O uint32_t I2C2_CLK_SET: 1; /*!< Writing one to this register sets the I2C2 bit in the AHBCLKCTRL1
- register. */
- __O uint32_t ZIGBEE_CLK_SET: 1; /*!< Writing one to this register sets the ZIGBEE bit in the AHBCLKCTRL1
- register. */
- __O uint32_t BLE_CLK_SET: 1; /*!< Writing one to this register sets the BLE bit in the AHBCLKCTRL1
- register. */
- __O uint32_t MODEM_MASTER_CLK_SET: 1; /*!< Writing one to this register sets the MODEM_MASTER bit in the
- AHBCLKCTRL1 register. */
- __O uint32_t AES_CLK_SET: 1; /*!< Writing one to this register sets the AES bit in the AHBCLKCTRL1
- register. */
- __O uint32_t RFP_CLK_SET: 1; /*!< Writing one to this register sets the RFP bit in the AHBCLKCTRL1
- register. */
- __O uint32_t DMIC_CLK_SET: 1; /*!< Writing one to this register sets the DMIC bit in the AHBCLKCTRL1
- register. */
- __O uint32_t HASH_CLK_SET: 1; /*!< Writing one to this register sets the HASH bit in the AHBCLKCTRL1
- register. */
- __O uint32_t TPR_CLK_SET: 1; /*!< Writing one to this register sets the TPR bit in the AHBCLKCTRL1
- register. */
- } AHBCLKCTRLSET1_b; /*!< BitSize */
- };
- __I uint32_t RESERVED9[6];
-
- union {
- __O uint32_t AHBCLKCTRLCLR0; /*!< Clear bits in AHBCLKCTRL0 */
-
- struct {
- uint32_t : 1;
- __O uint32_t ROM_CLK_CLR: 1; /*!< Writing one to this register clears the ROM bit in the AHBCLKCTRL0
- register. */
- uint32_t : 1;
- __O uint32_t SRAM_CTRL0_CLK_CLR: 1; /*!< Writing one to this register clears the SRAM_CTRL0 bit in the
- AHBCLKCTRL0 register. */
- __O uint32_t SRAM_CTRL1_CLK_CLR: 1; /*!< Writing one to this register clears the SRAM_CTRL1 bit in the
- AHBCLKCTRL0 register. */
- uint32_t : 3;
- __O uint32_t FLASH_CLK_CLR: 1; /*!< Writing one to this register clears the FLASH bit in the AHBCLKCTRL0
- register. */
- uint32_t : 1;
- __O uint32_t SPIFI_CLK_CLR: 1; /*!< Writing one to this register clears the SPIFI bit in the AHBCLKCTRL0
- register. */
- __O uint32_t MUX_CLK_CLR: 1; /*!< Writing one to this register clears the MUX bit in the AHBCLKCTRL0
- register. */
- uint32_t : 1;
- __O uint32_t IOCON_CLK_CLR: 1; /*!< Writing one to this register clears the IOCON bit in the AHBCLKCTRL0
- register. */
- __O uint32_t GPIO_CLK_CLR: 1; /*!< Writing one to this register clears the GPIO bit in the AHBCLKCTRL0
- register. */
- uint32_t : 3;
- __O uint32_t PINT_CLK_CLR: 1; /*!< Writing one to this register clears the PINT bit in the AHBCLKCTRL0
- register. */
- __O uint32_t GINT_CLK_CLR: 1; /*!< Writing one to this register clears the GINT bit in the AHBCLKCTRL0
- register. */
- __O uint32_t DMA_CLK_CLR: 1; /*!< Writing one to this register clears the DMA bit in the AHBCLKCTRL0
- register. */
- __O uint32_t ISO7816_CLK_CLR: 1; /*!< Writing one to this register clears the ISO7816 bit in the AHBCLKCTRL0
- register. */
- __O uint32_t WWDT_CLK_CLR: 1; /*!< Writing one to this register clears the WWDT bit in the AHBCLKCTRL0
- register. */
- __O uint32_t RTC_CLK_CLR: 1; /*!< Writing one to this register clears the RTC bit in the AHBCLKCTRL0
- register. */
- __O uint32_t ANA_INT_CTRL_CLK_SET: 1; /*!< Writing one to this register clears the ANA_INT_CTRL bit in
- the AHBCLKCTRL0 register. */
- __O uint32_t WAKE_UP_TIMERS_CLK_SET: 1; /*!< Writing one to this register clears the WAKE_UP_TIMERS bit in
- the AHBCLKCTRL0 register. */
- __O uint32_t MAILBOX_CLK_CLR: 1; /*!< Writing one to this register clears the MAILBOX bit in the AHBCLKCTRL0
- register. */
- __O uint32_t ADC_CLK_CLR: 1; /*!< Writing one to this register clears the ADC bit in the AHBCLKCTRL0
- register. */
- __O uint32_t EFUSE_CLK_CLR: 1; /*!< Writing one to this register clears the EFUSE bit in the AHBCLKCTRL0
- register. */
- __O uint32_t PVT_CLK_CLR: 1; /*!< Writing one to this register clears the PVT bit in the AHBCLKCTRL0
- register. */
- } AHBCLKCTRLCLR0_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t AHBCLKCTRLCLR1; /*!< Clear bits in AHBCLKCTRL1 */
-
- struct {
- uint32_t : 11;
- __O uint32_t USART0_CLK_CLR: 1; /*!< Writing one to this register clears the UART0 bit in the AHBCLKCTRL1
- register. */
- __O uint32_t USART1_CLK_CLR: 1; /*!< Writing one to this register clears the UART1 bit in the AHBCLKCTRL1
- register. */
- __O uint32_t I2C0_CLK_CLR: 1; /*!< Writing one to this register clears the I2C0 bit in the AHBCLKCTRL1
- register. */
- __O uint32_t I2C1_CLK_CLR: 1; /*!< Writing one to this register clears the I2C1 bit in the AHBCLKCTRL1
- register. */
- __O uint32_t SPI0_CLK_CLR: 1; /*!< Writing one to this register clears the SPI0 bit in the AHBCLKCTRL1
- register. */
- __O uint32_t SPI1_CLK_CLR: 1; /*!< Writing one to this register clears the SPI1 bit in the AHBCLKCTRL1
- register. */
- __O uint32_t IR_CLK_CLR : 1; /*!< Writing one to this register clears the IR bit in the AHBCLKCTRL1
- register. */
- __O uint32_t PWM_CLK_CLR: 1; /*!< Writing one to this register clears the PWM bit in the AHBCLKCTRL1
- register. */
- __O uint32_t RNG_CLK_CLR: 1; /*!< Writing one to this register clears the RNG bit in the AHBCLKCTRL1
- register. */
- __O uint32_t I2C2_CLK_CLR: 1; /*!< Writing one to this register clears the I2C2 bit in the AHBCLKCTRL1
- register. */
- __O uint32_t ZIGBEE_CLK_CLR: 1; /*!< Writing one to this register clears the ZIGBEE bit in the AHBCLKCTRL1
- register. */
- __O uint32_t BLE_CLK_CLR: 1; /*!< Writing one to this register clears the BLE bit in the AHBCLKCTRL1
- register. */
- __O uint32_t MODEM_MASTER_CLK_CLR: 1; /*!< Writing one to this register clears the MODEM_MASTER bit in
- the AHBCLKCTRL1 register. */
- __O uint32_t AES_CLK_CLR: 1; /*!< Writing one to this register clears the AES bit in the AHBCLKCTRL1
- register. */
- __O uint32_t RFP_CLK_CLR: 1; /*!< Writing one to this register clears the RFP bit in the AHBCLKCTRL1
- register. */
- __O uint32_t DMIC_CLK_CLR: 1; /*!< Writing one to this register clears the DMIC bit in the AHBCLKCTRL1
- register. */
- __O uint32_t HASH_CLK_CLR: 1; /*!< Writing one to this register clears the HASH bit in the AHBCLKCTRL1
- register. */
- __O uint32_t TPR_CLK_CLR: 1; /*!< Writing one to this register clears the TPR bit in the AHBCLKCTRL1
- register. */
- } AHBCLKCTRLCLR1_b; /*!< BitSize */
- };
- __I uint32_t RESERVED10[14];
-
- union {
- __IO uint32_t MAINCLKSEL; /*!< Main clock source select */
-
- struct {
- __IO uint32_t SEL : 3; /*!< Main clock clock source selection 000 : FRO_12MHz 001 : OSC32KCLK
- 010 : 32MHz XTAL 011 : FRO_32MHz 100 : FRO_48MHz 101 : External_CLK
- (CLKIN) 11X : FRO_1MHz */
- } MAINCLKSEL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t OSC32CLKSEL; /*!< OSC32KCLK and OSC32MCLK clock sources select. Note: this register
- is not locked by CLOCKGENUPDATELOCKOUT */
-
- struct {
- __IO uint32_t SEL32MHZ : 1; /*!< OSC32MCLK clock source selection */
- __IO uint32_t SEL32KHZ : 1; /*!< OSC32KCLK clock source selection */
- } OSC32CLKSEL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t CLKOUTSEL; /*!< CLKOUT clock source select */
-
- struct {
- __IO uint32_t SEL : 3; /*!< CLKOUT clock source selection */
- } CLKOUTSEL_b; /*!< BitSize */
- };
- __I uint32_t RESERVED11[5];
-
- union {
- __IO uint32_t SPIFICLKSEL; /*!< SPIFI clock source select */
-
- struct {
- __IO uint32_t SEL : 3; /*!< SPIFICLK clock source selection */
- } SPIFICLKSEL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t ADCCLKSEL; /*!< ADC clock source select */
-
- struct {
- __IO uint32_t SEL : 2; /*!< ADCCLK clock source selection */
- } ADCCLKSEL_b; /*!< BitSize */
- };
- __I uint32_t RESERVED12[2];
-
- union {
- __IO uint32_t USARTCLKSEL; /*!< USART0 & 1 clock source select */
-
- struct {
- __IO uint32_t SEL : 2; /*!< USARTCLK (USART0 & 1) clock source selection */
- } USARTCLKSEL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t I2CCLKSEL; /*!< I2C0 & 1 clock source select */
-
- struct {
- __IO uint32_t SEL : 2; /*!< I2CCLK (I2C0 & 1) clock source selection */
- } I2CCLKSEL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t SPICLKSEL; /*!< SPI0 & 1 clock source select */
-
- struct {
- __IO uint32_t SEL : 2; /*!< SPICLK (SPI0 & 1) clock source selection */
- } SPICLKSEL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t IRCLKSEL; /*!< Infra Red clock source select */
-
- struct {
- __IO uint32_t SEL : 2; /*!< IRCLK (IR Blaster) clock source selection */
- } IRCLKSEL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PWMCLKSEL; /*!< PWM clock source select */
-
- struct {
- __IO uint32_t SEL : 2; /*!< PWMCLK (PWM) clock source selection */
- } PWMCLKSEL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t WDTCLKSEL; /*!< Watchdog Timer clock source select */
-
- struct {
- __IO uint32_t SEL : 2; /*!< WDTCLK (Watchdog Timer) clock source selection */
- } WDTCLKSEL_b; /*!< BitSize */
- };
- __I uint32_t RESERVED13;
-
- union {
- __IO uint32_t MODEMCLKSEL; /*!< Zigbee and BLE Modems clock source select */
-
- struct {
- __IO uint32_t SEL_ZIGBEE : 1; /*!< Zigbee Modem clock source selection */
- __IO uint32_t SEL_BLE : 1; /*!< BLE 32 MHz clock source selection */
- } MODEMCLKSEL_b; /*!< BitSize */
- };
- __I uint32_t RESERVED14[6];
-
- union {
- __IO uint32_t FRGCLKSEL; /*!< Fractional Rate Generator clock source select */
-
- struct {
- __IO uint32_t SEL : 2; /*!< Fractional Rate Generator clock source selection */
- } FRGCLKSEL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t DMICCLKSEL; /*!< Digital microphone (D-Mic) subsystem clock select */
-
- struct {
- __IO uint32_t SEL : 3; /*!< DMIC clock source selection */
- } DMICCLKSEL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t WKTCLKSEL; /*!< Wake-up Timer clock select */
-
- struct {
- __IO uint32_t SEL : 2; /*!< Wake-up Timers clock source selection */
- } WKTCLKSEL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t ISO7816CLKSEL; /*!< ISO7816 clock source select */
-
- struct {
- __IO uint32_t ISO7816CLKSEL: 32; /*!< ISO7816 clock source select */
- } ISO7816CLKSEL_b; /*!< BitSize */
- };
- __I uint32_t RESERVED15[2];
-
- union {
- __IO uint32_t SYSTICKCLKDIV; /*!< SYSTICK clock divider */
-
- struct {
- __IO uint32_t DIV : 8; /*!< Clock divider value. 0: Divide by 1. 255: Divide by 256. */
- uint32_t : 21;
- __IO uint32_t RESET : 1; /*!< Resets the divider counter. Can be used to make sure a new divider
- value is used right away rather than completing the previous
- count. */
- __IO uint32_t HALT : 1; /*!< Halts the divider counter. The intent is to allow the divider
- s clock source to be changed without the risk of a glitch at
- the output. */
- __I uint32_t REQFLAG : 1; /*!< Divider status flag. Set when a change is made to the divider
- value, cleared when the change is complete. */
- } SYSTICKCLKDIV_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t TRACECLKDIV; /*!< TRACE clock divider */
-
- struct {
- __IO uint32_t DIV : 8; /*!< Clock divider value. 0: Divide by 1. 255: Divide by 256. */
- uint32_t : 21;
- __IO uint32_t RESET : 1; /*!< Resets the divider counter. Can be used to make sure a new divider
- value is used right away rather than completing the previous
- count. */
- __IO uint32_t HALT : 1; /*!< Halts the divider counter. The intent is to allow the divider
- s clock source to be changed without the risk of a glitch at
- the output. */
- __I uint32_t REQFLAG : 1; /*!< Divider status flag. Set when a change is made to the divider
- value, cleared when the change is complete. */
- } TRACECLKDIV_b; /*!< BitSize */
- };
- __I uint32_t RESERVED16[25];
-
- union {
- __IO uint32_t WDTCLKDIV; /*!< Watchdog Timer clock divider */
-
- struct {
- __IO uint32_t DIV : 8; /*!< Clock divider value. 0: Divide by 1. 255: Divide by 256. */
- uint32_t : 21;
- __IO uint32_t RESET : 1; /*!< Resets the divider counter. Can be used to make sure a new divider
- value is used right away rather than completing the previous
- count. */
- __IO uint32_t HALT : 1; /*!< Halts the divider counter. The intent is to allow the divider
- s clock source to be changed without the risk of a glitch at
- the output. */
- __I uint32_t REQFLAG : 1; /*!< Divider status flag. Set when a change is made to the divider
- value, cleared when the change is complete. */
- } WDTCLKDIV_b; /*!< BitSize */
- };
- __I uint32_t RESERVED17[2];
-
- union {
- __IO uint32_t IRCLKDIV; /*!< Infra Red clock divider */
-
- struct {
- __IO uint32_t DIV : 4; /*!< Clock divider value. 0: Divide by 1. 15: Divide by 16. */
- uint32_t : 25;
- __IO uint32_t RESET : 1; /*!< Resets the divider counter. Can be used to make sure a new divider
- value is used right away rather than completing the previous
- count. */
- __IO uint32_t HALT : 1; /*!< Halts the divider counter. The intent is to allow the divider
- s clock source to be changed without the risk of a glitch at
- the output. */
- __I uint32_t REQFLAG : 1; /*!< Divider status flag. Set when a change is made to the divider
- value, cleared when the change is complete. */
- } IRCLKDIV_b; /*!< BitSize */
- };
- __I uint32_t RESERVED18;
-
- union {
- __IO uint32_t AHBCLKDIV; /*!< System clock divider */
-
- struct {
- __IO uint32_t DIV : 8; /*!< Clock divider value. 0: Divide by 1. 255: Divide by 256. */
- uint32_t : 23;
- __I uint32_t REQFLAG : 1; /*!< Divider status flag. Set when a change is made to the divider
- value, cleared when the change is complete. */
- } AHBCLKDIV_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t CLKOUTDIV; /*!< CLKOUT clock divider */
-
- struct {
- __IO uint32_t DIV : 4; /*!< Clock divider value. 0: Divide by 1. 15: Divide by 16. */
- uint32_t : 25;
- __IO uint32_t RESET : 1; /*!< Resets the divider counter. Can be used to make sure a new divider
- value is used right away rather than completing the previous
- count. */
- __IO uint32_t HALT : 1; /*!< Halts the divider counter. The intent is to allow the divider
- s clock source to be changed without the risk of a glitch at
- the output. */
- __I uint32_t REQFLAG : 1; /*!< Divider status flag. Set when a change is made to the divider
- value, cleared when the change is complete. */
- } CLKOUTDIV_b; /*!< BitSize */
- };
- __I uint32_t RESERVED19[2];
-
- union {
- __IO uint32_t SPIFICLKDIV; /*!< SPIFI clock divider */
-
- struct {
- __IO uint32_t DIV : 2; /*!< Clock divider value. 0: Divide by 1. 3: Divide by 4. */
- uint32_t : 27;
- __IO uint32_t RESET : 1; /*!< Resets the divider counter. Can be used to make sure a new divider
- value is used right away rather than completing the previous
- count. */
- __IO uint32_t HALT : 1; /*!< Halts the divider counter. The intent is to allow the divider
- s clock source to be changed without the risk of a glitch at
- the output. */
- __I uint32_t REQFLAG : 1; /*!< Divider status flag. Set when a change is made to the divider
- value, cleared when the change is complete. */
- } SPIFICLKDIV_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t ADCCLKDIV; /*!< ADC clock divider */
-
- struct {
- __IO uint32_t DIV : 3; /*!< Clock divider value. 0: Divide by 1. 7: Divide by 8. */
- uint32_t : 26;
- __IO uint32_t RESET : 1; /*!< Resets the divider counter. Can be used to make sure a new divider
- value is used right away rather than completing the previous
- count. */
- __IO uint32_t HALT : 1; /*!< Halts the divider counter. The intent is to allow the divider
- s clock source to be changed without the risk of a glitch at
- the output. */
- __I uint32_t REQFLAG : 1; /*!< Divider status flag. Set when a change is made to the divider
- value, cleared when the change is complete. */
- } ADCCLKDIV_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t RTCCLKDIV; /*!< Real Time Clock divider (1 KHz clock generation) */
-
- struct {
- __IO uint32_t DIV : 5; /*!< Clock divider value. 0: Divide by 1. 31: Divide by 32. */
- uint32_t : 24;
- __IO uint32_t RESET : 1; /*!< Resets the divider counter. Can be used to make sure a new divider
- value is used right away rather than completing the previous
- count. */
- __IO uint32_t HALT : 1; /*!< Halts the divider counter. The intent is to allow the divider
- s clock source to be changed without the risk of a glitch at
- the output. */
- __I uint32_t REQFLAG : 1; /*!< Divider status flag. Set when a change is made to the divider
- value, cleared when the change is complete. */
- } RTCCLKDIV_b; /*!< BitSize */
- };
- __I uint32_t RESERVED20;
-
- union {
- __IO uint32_t FRGCTRL; /*!< Fractional rate divider */
-
- struct {
- __IO uint32_t DIV : 8; /*!< Denominator of the fractional divider. DIV is equal to the programmed
- value +1. Always set to 0xFF to use with the fractional baud
- rate generator : fout = fin / (1 + mult/(div+1)) */
- __IO uint32_t MULT : 8; /*!< Numerator of the fractional divider. MULT is equal to the programmed
- value */
- } FRGCTRL_b; /*!< BitSize */
- };
- __I uint32_t RESERVED21;
-
- union {
- __IO uint32_t DMICCLKDIV; /*!< DMIC clock divider */
-
- struct {
- __IO uint32_t DIV : 8; /*!< Clock divider value. 0: Divide by 1. 255: Divide by 256. */
- uint32_t : 21;
- __IO uint32_t RESET : 1; /*!< Resets the divider counter. Can be used to make sure a new divider
- value is used right away rather than completing the previous
- count. */
- __IO uint32_t HALT : 1; /*!< Halts the divider counter. The intent is to allow the divider
- s clock source to be changed without the risk of a glitch at
- the output. */
- __I uint32_t REQFLAG : 1; /*!< Divider status flag. Set when a change is made to the divider
- value, cleared when the change is complete. */
- } DMICCLKDIV_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t RTC1HZCLKDIV; /*!< Real Time Clock divider (1 Hz clock generation. The divider
- is fixed to 32768) */
-
- struct {
- uint32_t : 29;
- __IO uint32_t RESET : 1; /*!< Resets the divider counter. Can be used to make sure a new divider
- value is used right away rather than completing the previous
- count. */
- __IO uint32_t HALT : 1; /*!< Halts the divider counter. The intent is to allow the divider
- s clock source to be changed without the risk of a glitch at
- the output. */
- __I uint32_t REQFLAG : 1; /*!< Divider status flag. Set when a change is made to the divider
- value, cleared when the change is complete. */
- } RTC1HZCLKDIV_b; /*!< BitSize */
- };
- __I uint32_t RESERVED22[19];
-
- union {
- __IO uint32_t CLOCKGENUPDATELOCKOUT; /*!< Control clock configuration registers access (like xxxDIV, xxxSEL) */
-
- struct {
- __IO uint32_t LOCK : 1; /*!< Disable clock control registers access (like xxxDIV, xxxSEL).
- Affects all clock control registers except OSC32CLKSEL. */
- } CLOCKGENUPDATELOCKOUT_b; /*!< BitSize */
- };
- __I uint32_t RESERVED23[101];
-
- union {
- __IO uint32_t EFUSECLKCTRL; /*!< eFUSE controller clock control */
-
- struct {
- __IO uint32_t ENABLE : 1; /*!< Enable the eFUSE controller IP clock (FRO 12 MHz) */
- } EFUSECLKCTRL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t RNGCTRL; /*!< Random Number Generator triggering */
-
- struct {
- __IO uint32_t START : 1; /*!< Trigger the generation of a random number (Low to high transition) */
- } RNGCTRL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t RNGCLKCTRL; /*!< Random Number Generator Clocks control */
-
- struct {
- __IO uint32_t ENABLE : 1; /*!< Enable the clocks used by the Random Number Generator (RNG) */
- } RNGCLKCTRL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t SRAMCTRL; /*!< All SRAMs common control signals */
-
- struct {
- __IO uint32_t SMB : 2; /*!< Light Sleep Bias */
- __IO uint32_t RM : 3; /*!< Read Margin control settings */
- __IO uint32_t WM : 3; /*!< Write Margin control settings */
- __IO uint32_t WRME : 1; /*!< Write read margin enable */
- __IO uint32_t RAM : 4; /*!< Read assist bias settings */
- __IO uint32_t WAM : 2; /*!< Write assist bias settings */
- __IO uint32_t RAEN : 1; /*!< Read assist enable */
- __IO uint32_t WAEN : 1; /*!< Write assist enable */
- __IO uint32_t STBP : 1; /*!< Self time bypass */
- __IO uint32_t VSBTEST : 1; /*!< Source biasing testability */
- } SRAMCTRL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t SRAMCTRL0; /*!< SRAM0 to SRAM7 controls */
-
- struct {
- __IO uint32_t SRAM0_LS : 1; /*!< SRAM0 Light Sleep mode */
- __IO uint32_t SRAM0_DSB : 1; /*!< SRAM0 Deep sleep mode */
- __IO uint32_t SRAM0_DSBDEL: 1; /*!< SRAM0 Deep sleep delayed */
- __IO uint32_t SRAM0_LSDEL: 1; /*!< SRAM0 Sleep mode disable */
- __IO uint32_t SRAM1_LS : 1; /*!< SRAM1 Light Sleep mode */
- __IO uint32_t SRAM1_DSB : 1; /*!< SRAM1 Deep sleep mode */
- __IO uint32_t SRAM1_DSBDEL: 1; /*!< SRAM1 Deep sleep delayed */
- __IO uint32_t SRAM1_LSDEL: 1; /*!< SRAM1 Sleep mode disable */
- __IO uint32_t SRAM2_LS : 1; /*!< SRAM2 Light Sleep mode */
- __IO uint32_t SRAM2_DSB : 1; /*!< SRAM2 Deep sleep mode */
- __IO uint32_t SRAM2_DSBDEL: 1; /*!< SRAM2 Deep sleep delayed */
- __IO uint32_t SRAM2_LSDEL: 1; /*!< SRAM2 Sleep mode disable */
- __IO uint32_t SRAM3_LS : 1; /*!< SRAM3 Light Sleep mode */
- __IO uint32_t SRAM3_DSB : 1; /*!< SRAM3 Deep sleep mode */
- __IO uint32_t SRAM3_DSBDEL: 1; /*!< SRAM3 Deep sleep delayed */
- __IO uint32_t SRAM3_LSDEL: 1; /*!< SRAM3 Sleep mode disable */
- __IO uint32_t SRAM4_LS : 1; /*!< SRAM4 Light Sleep mode */
- __IO uint32_t SRAM4_DSB : 1; /*!< SRAM4 Deep sleep mode */
- __IO uint32_t SRAM4_DSBDEL: 1; /*!< SRAM4 Deep sleep delayed */
- __IO uint32_t SRAM4_LSDEL: 1; /*!< SRAM4 Sleep mode disable */
- __IO uint32_t SRAM5_LS : 1; /*!< SRAM5 Light Sleep mode */
- __IO uint32_t SRAM5_DSB : 1; /*!< SRAM5 Deep sleep mode */
- __IO uint32_t SRAM5_DSBDEL: 1; /*!< SRAM5 Deep sleep delayed */
- __IO uint32_t SRAM5_LSDEL: 1; /*!< SRAM5 Sleep mode disable */
- __IO uint32_t SRAM6_LS : 1; /*!< SRAM6 Light Sleep mode */
- __IO uint32_t SRAM6_DSB : 1; /*!< SRAM6 Deep sleep mode */
- __IO uint32_t SRAM6_DSBDEL: 1; /*!< SRAM6 Deep sleep delayed */
- __IO uint32_t SRAM6_LSDEL: 1; /*!< SRAM6 Sleep mode disable */
- __IO uint32_t SRAM7_LS : 1; /*!< SRAM7 Light Sleep mode */
- __IO uint32_t SRAM7_DSB : 1; /*!< SRAM7 Deep sleep mode */
- __IO uint32_t SRAM7_DSBDEL: 1; /*!< SRAM7 Deep sleep delayed */
- __IO uint32_t SRAM7_LSDEL: 1; /*!< SRAM7 Sleep mode disable */
- } SRAMCTRL0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t SRAMCTRL1; /*!< SRAM8 to SRAM11 controls */
-
- struct {
- __IO uint32_t SRAM8_LS : 1; /*!< SRAM8 Light Sleep mode */
- __IO uint32_t SRAM8_DSB : 1; /*!< SRAM8 Deep sleep mode */
- __IO uint32_t SRAM8_DSBDEL: 1; /*!< SRAM8 Deep sleep delayed */
- __IO uint32_t SRAM8_LSDEL: 1; /*!< SRAM8 Sleep mode disable */
- __IO uint32_t SRAM9_LS : 1; /*!< SRAM9 Light Sleep mode */
- __IO uint32_t SRAM9_DSB : 1; /*!< SRAM9 Deep sleep mode */
- __IO uint32_t SRAM9_DSBDEL: 1; /*!< SRAM9 Deep sleep delayed */
- __IO uint32_t SRAM9_LSDEL: 1; /*!< SRAM9 Sleep mode disable */
- __IO uint32_t SRAM10_LS : 1; /*!< SRAM10 Light Sleep mode */
- __IO uint32_t SRAM10_DSB : 1; /*!< SRAM10 Deep sleep mode */
- __IO uint32_t SRAM10_DSBDEL: 1; /*!< SRAM10 Deep sleep delayed */
- __IO uint32_t SRAM10_LSDEL: 1; /*!< SRAM10 Sleep mode disable */
- __IO uint32_t SRAM11_LS : 1; /*!< SRAM11 Light Sleep mode */
- __IO uint32_t SRAM11_DSB : 1; /*!< SRAM11 Deep sleep mode */
- __IO uint32_t SRAM11_DSBDEL: 1; /*!< SRAM11 Deep sleep delayed */
- __IO uint32_t SRAM11_LSDEL: 1; /*!< SRAM11 Sleep mode disable */
- } SRAMCTRL1_b; /*!< BitSize */
- };
- __I uint32_t RESERVED24[7];
-
- union {
- __IO uint32_t ROMCTRL; /*!< ROM control */
-
- struct {
- __IO uint32_t SDB : 1; /*!< Shutdown pin (active low) */
- __IO uint32_t SDBDEL : 1; /*!< Shutdown delayed pin (active low) */
- __IO uint32_t RME : 1; /*!< Read Margin Enable */
- __IO uint32_t RM : 4; /*!< read margin control setting */
- __IO uint32_t PM : 2; /*!< precharge margin control setting */
- __IO uint32_t VDDMIN : 1; /*!< VDDMIN enable setting */
- } ROMCTRL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t MODEMCTRL; /*!< MoDem (Zigbee and Bluetooth) control */
-
- struct {
- __IO uint32_t BLE_LP_SLEEP_TRIG: 1; /*!< (null) */
- __IO uint32_t BLE_FREQ_SEL: 1; /*!< 1 = 16 MHz ; 0 = 8 MHz */
- __IO uint32_t BLE_DP_DIV_EN: 1; /*!< 1 = enable Frequency Divider ; 0 = Disable */
- __IO uint32_t BLE_CLK32M_SEL: 1; /*!< 1 = 16 MHz ; 0 = 32 MHz */
- __IO uint32_t BLE_AHB_DIV0: 1; /*!< AHB _CLK = SYS_CLK / (AHB_DIV + 1) */
- __IO uint32_t BLE_AHB_DIV1: 1; /*!< (null) */
- __IO uint32_t BLE_HCLK_BLE_EN: 1; /*!< 1 = enable the hclk */
- __IO uint32_t BLE_PHASE_MATCH_1: 1; /*!< (null) */
- __IO uint32_t BLE_ISO_ENABLE: 1; /*!< Control isolation of BLE Low Power Control module (RW_BLE_TIMING_GEN_LP),
- namely :deep_sleep_stat, wakeup_req_trig Must not be set before
- MODEMSTATUS.BLE_LL_CLK_STATUS is high ('1') 0 : isolation is
- disable 1 : isolation is enable */
- __IO uint32_t BLE_LP_OSC32K_EN: 1; /*!< 1 = enable the Ble Low power wake up counter clock enable */
- } MODEMCTRL_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t MODEMSTATUS; /*!< MoDem (Zigbee and Bluetooth) status */
-
- struct {
- __I uint32_t BLE_LL_CLK_STATUS: 1; /*!< 1 = BLE IP in deep sleep ; 0 BLE IP active */
- __I uint32_t BLE_LP_OSC_EN: 1; /*!< Enable Oscillator / Xtal that drives the RF, active high */
- __I uint32_t BLE_LP_RADIO_EN: 1; /*!< Enable Radio, active high */
- } MODEMSTATUS_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t XTAL32KCAP; /*!< XTAL 32 KHz oscillator Capacitor test */
-
- struct {
- __IO uint32_t XO_OSC_CAP_IN: 7; /*!< Tune cap in Xi */
- __IO uint32_t XO_OSC_CAP_OUT: 7; /*!< Tune cap in Xo */
- } XTAL32KCAP_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t XTAL32MCTRL; /*!< XTAL 32 MHz oscillator control register */
-
- struct {
- __IO uint32_t DEACTIVATE_PMC_CTRL: 1; /*!< eFuse bit XTAL32MSTART_ENA will enable XTAL whenever the device
- is active; this control bit can deactivate this. 0: Enable XTAL
- 32 MHz controls coming from PMC. 1: Disable XTAL 32 MHz controls
- coming from PMC. */
- __IO uint32_t DEACTIVATE_BLE_CTRL: 1; /*!< In order to have XTAL ready for BLE after a low power cycle
- the XTAL must be started early by the BLE low power module;
- this can be deactivated. 0: Enable XTAL 32 MHz controls coming
- from BLE Low Power Control module. 1: Disable XTAL 32 MHz controls
- coming from BLE Low Power Control module. */
- } XTAL32MCTRL_b; /*!< BitSize */
- };
- __I uint32_t RESERVED25[41];
-
- union {
- __IO uint32_t STARTER0; /*!< Start logic 0 wake-up enable register. Enable an interrupt for
- wake-up from deep-sleep mode. Some bits can also control wake-up
- from powerdown mode */
-
- struct {
- __IO uint32_t WDT_BOD : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep and Powerdown. */
- __IO uint32_t DMA : 1; /*!< DMA Operation in Deep-Sleep and Powerdown not supported. Leave
- set to 0. */
- __IO uint32_t GINT : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t IRBLASTER : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t PINT0 : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t PINT1 : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t PINT2 : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t PINT3 : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t SPIFI : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t TIMER0 : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t TIMER1 : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t USART0 : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep and Powerdown. */
- __IO uint32_t USART1 : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t I2C0 : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep and Powerdown. */
- __IO uint32_t I2C1 : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t SPI0 : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep and Powerdown. */
- __IO uint32_t SPI1 : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t PWM0 : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t PWM1 : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t PWM2 : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t PWM3 : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t PWM4 : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t PWM5 : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t PWM6 : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t PWM7 : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t PWM8 : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t PWM9 : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t PWM10 : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t I2C2 : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t RTC : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep and Powerdown. */
- __IO uint32_t NFCTAG : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t MAILBOX : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- } STARTER0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t STARTER1; /*!< Start logic 1 wake-up enable register. Enable an interrupt for
- wake-up from deep-sleep mode. Some bits can also control wake-up
- from powerdown mode */
-
- struct {
- __IO uint32_t ADC_SEQA : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t ADC_SEQB : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t ADC_THCMP_OVR: 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t DMIC : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t HWVAD : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t BLE_DP : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t BLE_DP0 : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t BLE_DP1 : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t BLE_DP2 : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t BLE_LL_ALL : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t ZIGBEE_MAC : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t ZIGBEE_MODEM: 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t RFP_TMU : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t RFP_AGC : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t ISO7816 : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep. */
- __IO uint32_t ANA_COMP : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep and Powerdown. */
- __IO uint32_t WAKE_UP_TIMER0: 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep and Powerdown. */
- __IO uint32_t WAKE_UP_TIMER1: 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep and Powerdown. */
- uint32_t : 4;
- __IO uint32_t BLE_WAKE_UP_TIMER: 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep and Powerdown. */
- __IO uint32_t BLE_OSC_EN : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Valid from Deep-Sleep and Powerdown. Used as early wake-up trigger
- to allow 32M XTAL to be started and ready for BLE timeslot */
- uint32_t : 7;
- __IO uint32_t GPIO : 1; /*!< interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
- Set this bit to allow GPIO or NTAG_INT to cause a wake-up in
- Deep-Sleep and Power-down mode. */
- } STARTER1_b; /*!< BitSize */
- };
- __I uint32_t RESERVED26[6];
-
- union {
- __O uint32_t STARTERSET0; /*!< Set bits in STARTER0 */
-
- struct {
- __O uint32_t WDT_BOD_SET: 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t DMA_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t GINT_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t IRBLASTER_SET: 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t PINT0_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t PINT1_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t PINT2_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t PINT3_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t SPIFI_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t TIMER0_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t TIMER1_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t USART0_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t USART1_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t I2C0_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t I2C1_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t SPI0_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t SPI1_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t PWM0_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t PWM1_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t PWM2_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t PWM3_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t PWM4_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t PWM5_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t PWM6_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t PWM7_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t PWM8_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t PWM9_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t PWM10_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t I2C2_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t RTC_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t NFCTAG_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- __O uint32_t MAILBOX_SET: 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER0 register */
- } STARTERSET0_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t STARTERSET1; /*!< Set bits in STARTER1 */
-
- struct {
- __O uint32_t ADC_SEQA_SET: 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER1 register */
- __O uint32_t ADC_SEQB_SET: 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER1 register */
- __O uint32_t ADC_THCMP_OVR_SET: 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER1 register */
- __O uint32_t DMIC_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER1 register */
- __O uint32_t HWVAD_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER1 register */
- __O uint32_t BLE_DP_SET : 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER1 register */
- __O uint32_t BLE_DP0_SET: 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER1 register */
- __O uint32_t BLE_DP1_SET: 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER1 register */
- __O uint32_t BLE_DP2_SET: 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER1 register */
- __O uint32_t BLE_LL_ALL_SET: 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER1 register */
- __O uint32_t ZIGBEE_MAC_SET: 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER1 register */
- __O uint32_t ZIGBEE_MODEM_SET: 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER1 register */
- __O uint32_t RFP_TMU_SET: 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER1 register */
- __O uint32_t RFP_AGC_SET: 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER1 register */
- __O uint32_t ISO7816_SET: 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER1 register */
- __O uint32_t ANA_COMP_SET: 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER1 register */
- __O uint32_t WAKE_UP_TIMER0_SET: 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER1 register */
- __O uint32_t WAKE_UP_TIMER1_SET: 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER1 register */
- uint32_t : 4;
- __O uint32_t BLE_WAKE_UP_TIMER_SET: 1; /*!< Writing ones to this register sets the corresponding bit in
- the STARTER1 register */
- } STARTERSET1_b; /*!< BitSize */
- };
- __I uint32_t RESERVED27[6];
-
- union {
- __O uint32_t STARTERCLR0; /*!< Clear bits in STARTER0 */
-
- struct {
- __O uint32_t WDT_BOD_CLR: 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t DMA_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t GINT_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t IRBLASTER_CLR: 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t PINT0_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t PINT1_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t PINT2_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t PINT3_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t SPIFI_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t TIMER0_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t TIMER1_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t USART0_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t USART1_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t I2C0_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t I2C1_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t SPI0_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t SPI1_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t PWM0_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t PWM1_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t PWM2_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t PWM3_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t PWM4_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t PWM5_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t PWM6_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t PWM7_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t PWM8_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t PWM9_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t PWM10_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t I2C2_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t RTC_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t NFCTAG_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- __O uint32_t MAILBOX_CLR: 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER0 register */
- } STARTERCLR0_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t STARTERCLR1; /*!< Clear bits in STARTER1 */
-
- struct {
- __O uint32_t ADC_SEQA_CLR: 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER1 register */
- __O uint32_t ADC_SEQB_CLR: 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER1 register */
- __O uint32_t ADC_THCMP_OVR_CLR: 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER1 register */
- __O uint32_t DMIC_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER1 register */
- __O uint32_t HWVAD_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER1 register */
- __O uint32_t BLE_DP_CLR : 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER1 register */
- __O uint32_t BLE_DP0_CLR: 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER1 register */
- __O uint32_t BLE_DP1_CLR: 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER1 register */
- __O uint32_t BLE_DP2_CLR: 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER1 register */
- __O uint32_t BLE_LL_ALL_CLR: 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER1 register */
- __O uint32_t ZIGBEE_MAC_CLR: 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER1 register */
- __O uint32_t ZIGBEE_MODEM_CLR: 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER1 register */
- __O uint32_t RFP_TMU_CLR: 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER1 register */
- __O uint32_t RFP_AGC_CLR: 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER1 register */
- __O uint32_t ISO7816_CLR: 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER1 register */
- __O uint32_t ANA_COMP_CLR: 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER1 register */
- __O uint32_t WAKE_UP_TIMER0_CLR: 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER1 register */
- __O uint32_t WAKE_UP_TIMER1_CLR: 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER1 register */
- uint32_t : 4;
- __O uint32_t BLE_WAKE_UP_TIMER_CLR: 1; /*!< Writing ones to this register clears the corresponding bit in
- the STARTER1 register */
- } STARTERCLR1_b; /*!< BitSize */
- };
- __I uint32_t RESERVED28[16];
-
- union {
- __IO uint32_t RETENTIONCTRL; /*!< I/O retention control register */
-
- struct {
- __IO uint32_t IOCLAMP : 1; /*!< Global control of activation of I/O clamps (note that each I/O
- clamp must be enable/disable individually in IOCON module).
- Useful in power down mode. 0: I/O clamp is disable 1: I/O clamp
- is enable */
- } RETENTIONCTRL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t POWERDOWNSAFETY; /*!< Override some powerdown control signals (for debug purposes) */
-
- struct {
- __IO uint32_t OVERRIDEFRO: 1; /*!< Overrides the fro_is_dead' signal in Sleepcon module, in case
- this doesn't work on silicon. */
- } POWERDOWNSAFETY_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t MAINCLKSAFETY; /*!< Delay from main_clk enable from sleep controller to start of
- AHB and ASYNC_VPB clocks */
-
- struct {
- __IO uint32_t MAIN_CLK_SAFETY_DEL: 16; /*!< When sleep control enables enables main clock to system AHB
- and system_async_vpb clocks the hardware can delay this enable
- using this value, for up up 0xFFFF main clock cycles */
- } MAINCLKSAFETY_b; /*!< BitSize */
- };
- __I uint32_t RESERVED29[27];
-
- union {
- __IO uint32_t HARDWARESLEEP; /*!< NOT SUPPORTED - Do Not Use. Hardware Sleep control (used to
- postpone power down modes in case an interrupt is pending when
- the processor request deepsleep) */
-
- struct {
- __IO uint32_t FORCED : 1; /*!< Forces postponing of power down modes (should be used for test
- purposes only): 0: Disable 1: Enable */
- __IO uint32_t PERIPHERALS: 1; /*!< Controls postponing of power down modes in case the following
- interrupts are pending: USART0, USART1, SPI0, SPI1, I2C0, I2C1
- 0 : Disable 1 : Enable */
- __IO uint32_t DMIC : 1; /*!< Controls postponing of power down modes in case the following
- interrupts are pending: DMIC FIFO 0 Wake up, DMIC FIFO 1 Wake
- up 0 : Disable 1 : Enable */
- __IO uint32_t SDMA : 1; /*!< Controls postponing of power down modes in case the following
- interrupts are pending: System DMA 0 : Disable 1 : Enable */
- __IO uint32_t NFCTAG : 1; /*!< Controls postponing of power down modes in case the following
- interrupts are pending: I2C2, NFC Tag interrupt 0 : Disable
- 1 : Enable */
- __IO uint32_t BLEOSC : 1; /*!< Controls postponing of power down modes in case the following
- interrupts are pending: BLE Oscillator Enable interrupt 0 :
- Disable 1 : Enable */
- } HARDWARESLEEP_b; /*!< BitSize */
- };
- __I uint32_t RESERVED30[31];
-
- union {
- __IO uint32_t CPUCTRL; /*!< CPU Control for multiple processors */
-
- struct {
- __IO uint32_t MASTERCPU : 1; /*!< Indicates which CPU is considered the master. This is set as
- Cortex-M4 0 as the master after any IC reset. The master CPU
- cannot have its clock turned off via the related CM4nCLKEN bit
- or be reset via the related CM4xRSTEN in this register. The
- slave CPU stays reset until activated by the master CPU. 0 :
- CM4 0. Cortex-M4 0 is the master CPU. 1 : CM4 1. Cortex-M4 1
- is the master CPU. */
- uint32_t : 1;
- __IO uint32_t CM40CLKEN : 1; /*!< Cortex-M4 0 clock enable. 0 : Disabled. The Cortex-M4 0 clock
- is not enabled. 1 : Enabled. The Cortex-M4 0 clock is enabled. */
- __IO uint32_t CM41CLKEN : 1; /*!< Cortex-M4 1 clock enable. 0 : Disabled. The Cortex-M4 1 clock
- is not enabled. 1 : Enabled. The Cortex-M4 1 clock is enabled. */
- __IO uint32_t CM40RSTEN : 1; /*!< Cortex-M4 0 reset. 0 : Disabled. The Cortex-M4 0 is not being
- reset. 1 : Enabled. The Cortex-M4 0 is being reset. */
- __IO uint32_t CM41RSTEN : 1; /*!< Cortex-M4 1 reset. 0 : Disabled. The Cortex-M4 1 is not being
- reset. 1 : Enabled. The Cortex-M4 1 is being reset. */
- __IO uint32_t POWERCPU : 1; /*!< Identifies the owner of reduced power mode control: which CPU
- can cause the device to enter deep-sleep and Deep Power-down
- modes. 0 : CM4 0. Cortex-M4 0 is the owner of reduced power
- mode control. 1 : CM4 1. Cortex-M4 1 is the owner of reduced
- power mode control. */
- __IO uint32_t WAKEUPEVENT: 1; /*!< Identifies the owner of reduced power mode control: which CPU
- can cause the device to enter deep-sleep and Deep Power-down
- modes. 0 : Both processors receive the 'wake-up event' from
- the Sleep Controller. 1 : Only the owner of reduced power mode
- receives the 'wake-up event' from the Sleep Controller. */
- __IO uint32_t CM40SYSRESETEN: 1; /*!< Controls ARM System Reset requests from Cortex-M4 0. 0 : ARM
- System Reset request from Cortex-M4 0 is disable. 1 : ARM System
- Reset request from Cortex-M4 0 is enable. */
- __IO uint32_t CM41SYSRESETEN: 1; /*!< Controls ARM System Reset requests from Cortex-M4 1. 0 : ARM
- System Reset request from Cortex-M4 1 is disable. 1 : ARM System
- Reset request from Cortex-M4 1 is enable. */
- uint32_t : 5;
- __IO uint32_t RESERVED1 : 1; /*!< Reserved. Must be written as a 1 */
- __IO uint32_t RESERVEDC0C4: 16; /*!< Must be written as 0xC0C4 for the write to have an effect. */
- } CPUCTRL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t CPBOOT; /*!< Coprocessor Boot Address */
-
- struct {
- __IO uint32_t CPBOOT : 32; /*!< Coprocessor Boot Address */
- } CPBOOT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t CPSTACK; /*!< Coprocessor Stack Address */
-
- struct {
- __IO uint32_t CPSTACK : 32; /*!< Coprocessor Stack Address */
- } CPSTACK_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t CPSTAT; /*!< CPU Status */
-
- struct {
- __I uint32_t CM40SLEEPING: 1; /*!< When 1, the Cortex-M4 0 CPU is sleeping */
- __I uint32_t CM41SLEEPING: 1; /*!< When 1, the Cortex-M4 1 CPU is sleeping */
- __I uint32_t CM40LOCKUP : 1; /*!< When 1, the Cortex-M4 0 CPU is in lockup. */
- __I uint32_t CM41LOCKUP : 1; /*!< When 1, the Cortex-M4 1 CPU is in lockup. */
- } CPSTAT_b; /*!< BitSize */
- };
- __I uint32_t RESERVED31[60];
-
- union {
- __I uint32_t GPIOSECIN; /*!< GPIO Secure IN : Reading these registers returns the current
- state of the pins read, regardless of direction. */
-
- struct {
- __I uint32_t GPIOSECIN : 32; /*!< GPIO Secure IN : Reading these registers returns the current
- state of the pins read, regardless of direction. */
- } GPIOSECIN_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t GPIOSECOUT; /*!< GPIO Secure OUT : Pin output state, when the pin is configured
- as output. */
-
- struct {
- __IO uint32_t GPIOSECOUT : 32; /*!< GPIO Secure OUT : Pin output state, when the pin is configured
- as output. */
- } GPIOSECOUT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t GPIOSECDIR; /*!< GPIO Secure Direction : Direction register for configuring the
- pins as inputs or outputs. */
-
- struct {
- __IO uint32_t GPIOSECDIR : 32; /*!< GPIO Secure Direction : Direction register for configuring the
- pins as inputs or outputs. */
- } GPIOSECDIR_b; /*!< BitSize */
- };
- __I uint32_t RESERVED32[61];
-
- union {
- __IO uint32_t ANACTRL_CTRL; /*!< Analog Interrupt control register. Requires AHBCLKCTRL0.ANA_INT_CTRL
- to be set. */
-
- struct {
- __IO uint32_t COMPINTRLVL: 1; /*!< Analog Comparator interrupt type: 0 : Analog Comparator interrupt
- is edge sensitive 1 : Analog Comparator interrupt is level sensitive */
- __IO uint32_t COMPINTRPOL: 2; /*!< Analog Comparator interrupt Polarity: When COMPINTRLVL = 0 (edge
- sensitive) 00 : rising edge 01 : falling edge 10 : both edges
- (rising and falling) 11 : both edges (rising and falling) When
- COMPINTRLVL = 1 (level sensitive) 00 : Low level ('0') 01 :
- Low level ('0') 10 : High level ('1') 11 : High level ('1') */
- } ANACTRL_CTRL_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t ANACTRL_VAL; /*!< Analog modules (BOD and Analog Comparator) outputs current values
- (BOD 'Power OK' and Analog comparator out). Requires AHBCLKCTRL0.ANA_INT_C
- TRL to be set. */
-
- struct {
- __I uint32_t BODVBAT : 1; /*!< BOD VBAT Status : 0 = Power not OK ; 1 = Power OK */
- __I uint32_t BODMEM : 1; /*!< BOD Memories Status : 0 = Power not OK ; 1 = Power OK */
- __I uint32_t BODCORE : 1; /*!< BOD Core Digital Status : 0 = Power not OK ; 1 = Power OK */
- __I uint32_t ANACOMP : 1; /*!< Analog comparator Status : 0 = Comparator in 0 < in 1 ; 1 =
- Comparator in 0 > in 1. */
- __I uint32_t BODVBATHIGH: 1; /*!< Not(BODV BAT). Added here just to keep coherency with other
- registers */
- } ANACTRL_VAL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t ANACTRL_STAT; /*!< Analog modules (BOD and Analog Comparator) interrupt status.
- Requires AHBCLKCTRL0.ANA_INT_CTRL to be set. */
-
- struct {
- __IO uint32_t BODVBAT : 1; /*!< BOD VBAT Interrupt status. 0 = No interrupt pending. 1 = Interrupt
- pending. Write 1 to clear. */
- __IO uint32_t BODMEM : 1; /*!< BOD Memories Interrupt status. 0 = No interrupt pending. 1 =
- Interrupt pending. Write 1 to clear. */
- __IO uint32_t BODCORE : 1; /*!< BOD Core Digital Interrupt status. 0 = No interrupt pending.
- 1 = Interrupt pending. Write 1 to clear. */
- __IO uint32_t ANACOMP : 1; /*!< Analog comparator Interrupt status. 0 = No interrupt pending.
- 1 = Interrupt pending. Write 1 to clear. */
- __IO uint32_t BODVBATHIGH: 1; /*!< NOT(BOD VBAT) interrupt status. Will be set when BOD VBAT goes
- high */
- } ANACTRL_STAT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t ANACTRL_INTENSET; /*!< Analog modules (BOD and Analog Comparator) Interrupt Enable
- Read and Set register. Requires AHBCLKCTRL0.ANA_INT_CTRL to
- be set. */
-
- struct {
- __IO uint32_t BODVBAT : 1; /*!< BOD VBAT Interrupt Enable Read and Set register */
- __IO uint32_t BODMEM : 1; /*!< BOD Memories Interrupt Enable Read and Set register */
- __IO uint32_t BODCORE : 1; /*!< BOD Core Digital Interrupt Enable Read and Set register */
- __IO uint32_t ANACOMP : 1; /*!< Analog comparator Interrupt Enable Read and Set register */
- __IO uint32_t BODVBATHIGH: 1; /*!< NOT(BOD VBAT) Interrupt Enable Read and Set register */
- } ANACTRL_INTENSET_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t ANACTRL_INTENCLR; /*!< Analog modules (BOD and Analog Comparator) Interrupt Enable
- Clear register. Requires AHBCLKCTRL0.ANA_INT_CTRL to be set. */
-
- struct {
- __O uint32_t BODVBAT : 1; /*!< BOD VBAT Interrupt Enable Clear register */
- __O uint32_t BODMEM : 1; /*!< BOD Memories Interrupt Enable Clear register */
- __O uint32_t BODCORE : 1; /*!< BOD Core Digital Interrupt Enable Clear register */
- __O uint32_t ANACOMP : 1; /*!< Analog comparator Interrupt Enable Clear register */
- __O uint32_t BODVBATHIGH: 1; /*!< NOT(BOD VBAT) Interrupt Enable Clear register */
- } ANACTRL_INTENCLR_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t ANACTRL_INTSTAT; /*!< Analog modules (BOD and Analog Comparator) Interrupt Status
- register (masked with interrupt enable). Requires AHBCLKCTRL0.ANA_INT_CTRL
- to be set. */
-
- struct {
- __I uint32_t BODVBAT : 1; /*!< BOD VBAT Interrupt (after interrupt mask). 0 = No interrupt
- pending. 1 = Interrupt pending. Only set when BODVBAT is enable
- in INTENSET */
- __I uint32_t BODMEM : 1; /*!< BOD Memories Interrupt (after interrupt mask). 0 = No interrupt
- pending. 1 = Interrupt pending. Only set when BODMEM is enable
- in INTENSET */
- __I uint32_t BODCORE : 1; /*!< BOD Core Digital Interrupt (after interrupt mask). 0 = No interrupt
- pending. 1 = Interrupt pending. Only set when BODCORE is enable
- in INTENSET */
- __I uint32_t ANACOMP : 1; /*!< Analog comparator Interrupt (after interrupt mask). 0 = No interrupt
- pending. 1 = Interrupt pending. Only set when ANACOMP is enable
- in INTENSET */
- __I uint32_t BODVBATHIGH: 1; /*!< NOT(BOD VBAT) Interrupt (after interrupt mask). 0 = No interrupt
- pending. 1 = Interrupt pending. Only set when BODVBATHIGH is
- enable in INTENSET */
- } ANACTRL_INTSTAT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t CLOCK_CTRL; /*!< Various system clock controls : Flash clock (48 MHz) control,
- clocks to Frequency Measures */
-
- struct {
- __IO uint32_t FLASH48MHZ_ENA: 1; /*!< Enable Flash 48 MHz clock 0 = Disabled 1 = Enabled */
- __IO uint32_t XTAL32MHZ_FREQM_ENA: 1; /*!< Enable XTAL32MHz clock for Frequency Measure module. 0 = Disabled
- 1 = Enabled */
- __IO uint32_t FRO1MHZ_FREQM_ENA: 1; /*!< Enable FRO 1MHz clock for Frequency Measure module. 0 = Disabled
- 1 = Enabled */
- } CLOCK_CTRL_b; /*!< BitSize */
- };
- __I uint32_t RESERVED33;
-
- union {
- __IO uint32_t WKT_CTRL; /*!< wake-up timers control */
-
- struct {
- __IO uint32_t WKT0_ENA : 1; /*!< Enable wake-up timer 0 0 = Disabled 1 = Enabled (counter is
- running) */
- __IO uint32_t WKT1_ENA : 1; /*!< Enable wake-up timer 1 0 = Disabled 1 = Enabled (counter is
- running) */
- __IO uint32_t WKT0_CLK_ENA: 1; /*!< Enable wake-up timer 0 clock 0 = Disabled 1 = Enabled */
- __IO uint32_t WKT1_CLK_ENA: 1; /*!< Enable wake-up timer 1 clock 0 = Disabled 1 = Enabled */
- } WKT_CTRL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t WKT_LOAD_WKT0_LSB; /*!< wake-up timer 0 reload value least significant bits ([31:0]). */
-
- struct {
- __IO uint32_t WKT0_LOAD_LSB: 32; /*!< Wake-up timer 0 reload value, least significant bits ([31:0]).
- Write when timer is not enabled */
- } WKT_LOAD_WKT0_LSB_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t WKT_LOAD_WKT0_MSB; /*!< wake-up timer 0 reload value most significant bits ([8:0]). */
-
- struct {
- __IO uint32_t WKT0_LOAD_MSB: 9; /*!< Wake-up timer 0 reload value, most significant bits ([8:0]).
- Write when timer is not enabled */
- } WKT_LOAD_WKT0_MSB_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t WKT_LOAD_WKT1; /*!< wake-up timer 1 reload value. */
-
- struct {
- __IO uint32_t WKT1_LOAD : 28; /*!< Wake-up timer 1 reload value. Write when timer is not enabled */
- } WKT_LOAD_WKT1_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t WKT_VAL_WKT0_LSB; /*!< wake-up timer 0 current value least significant bits ([31:0]).
- WARNING : reading not reliable: read this register several times
- until you get a stable value. */
-
- struct {
- __I uint32_t WKT0_VAL_LSB: 32; /*!< Wake-up timer 0 value, least significant bits ([31:0]). Reread
- until stable value seen. */
- } WKT_VAL_WKT0_LSB_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t WKT_VAL_WKT0_MSB; /*!< wake-up timer 0 current value most significant bits ([8:0]).
- WARNING : reading not reliable: read this register several times
- until you get a stable value. */
-
- struct {
- __I uint32_t WKT0_VAL_MSB: 9; /*!< Wake-up timer 0 value, most significant bits ([8:0]). Reread
- until stable value seen. */
- } WKT_VAL_WKT0_MSB_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t WKT_VAL_WKT1; /*!< wake-up timer 1 current value. WARNING : reading not reliable:
- read this register several times until you get a stable value. */
-
- struct {
- __I uint32_t WKT1_VAL : 28; /*!< Wake-up timer 1 value. Reread until stable value seen. */
- } WKT_VAL_WKT1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t WKT_STAT; /*!< wake-up timers status */
-
- struct {
- __IO uint32_t WKT0_TIMEOUT: 1; /*!< Status timer 0 : 0 = timeout not reached ; 1 = timeout reached.
- Write 1 to clear. */
- __IO uint32_t WKT1_TIMEOUT: 1; /*!< Status timer 1 : 0 = timeout not reached ; 1 = timeout reached.
- Write 1 to clear. */
- __I uint32_t WKT0_RUNNING: 1; /*!< Status timer 0 : 0 = not running ; 1 = running */
- __I uint32_t WKT1_RUNNING: 1; /*!< Status timer 1 : 0 = not running ; 1 = running */
- } WKT_STAT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t WKT_INTENSET; /*!< Interrupt Enable Read and Set register */
-
- struct {
- __IO uint32_t WKT0_TIMEOUT: 1; /*!< Timer 0 Interrupt Enable Read and Set register */
- __IO uint32_t WKT1_TIMEOUT: 1; /*!< Timer 1 Interrupt Enable Read and Set register */
- } WKT_INTENSET_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t WKT_INTENCLR; /*!< Interrupt Enable Clear register */
-
- struct {
- __O uint32_t WKT0_TIMEOUT: 1; /*!< Interrupt Enable Clear register */
- __O uint32_t WKT1_TIMEOUT: 1; /*!< Interrupt Enable Clear register */
- } WKT_INTENCLR_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t WKT_INTSTAT; /*!< Interrupt Status register */
-
- struct {
- __I uint32_t WKT0_TIMEOUT: 1; /*!< Timer 0 Interrupt. 0 = No interrupt pending. 1 = Interrupt pending.
- Only set when WKT0_TIMEOUT is enable in INTENSET */
- __I uint32_t WKT1_TIMEOUT: 1; /*!< Timer 1 Interrupt. 0 = No interrupt pending. 1 = Interrupt pending.
- Only set when WKT1_TIMEOUT is enable in INTENSET */
- } WKT_INTSTAT_b; /*!< BitSize */
- };
- __I uint32_t RESERVED34[238];
-
- union {
- __IO uint32_t AUTOCLKGATEOVERRIDE; /*!< Control automatic clock gating */
-
- struct {
- __IO uint32_t ROM : 1; /*!< Override automatic clock gating of ROM controller. 0 = disable.
- 1 = enable/always clock */
- __IO uint32_t SRAM_CTRL0 : 1; /*!< Override automatic clock gating of SRAM controller 0. 0 = disable.
- 1 = enable/always clock */
- __IO uint32_t SRAM_CTRL1 : 1; /*!< Override automatic clock gating of SRAM controller 1. 0 = disable.
- 1 = enable/always clock */
- uint32_t : 2;
- __IO uint32_t SYNC_APB : 1; /*!< Override automatic clock gating of synchronous bridge controller.
- 0 = disable. 1 = enable/always clock */
- __IO uint32_t ASYNC_APB : 1; /*!< Override automatic clock gating of asynchronous bridge controller.
- 0 = disable. 1 = enable/always clock */
- uint32_t : 6;
- __IO uint32_t SDMA : 1; /*!< Override automatic clock gating of DMA controller. 0 = disable.
- 1 = enable/always clock */
- uint32_t : 1;
- __IO uint32_t SYSCON : 1; /*!< Override automatic clock gating of synchronous system controller
- registers bank. 0 = disable. 1 = enable/always clock */
- __O uint32_t ENABLEUPDATE: 16; /*!< The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers
- fields updates to have effect. */
- } AUTOCLKGATEOVERRIDE_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t GPIOPSYNC; /*!< Enable bypass of the first stage of synchonization inside GPIO_INT
- module. */
-
- struct {
- __IO uint32_t PSYNC : 1; /*!< Enable bypass of the first stage of synchonization inside GPIO_INT
- module. */
- } GPIOPSYNC_b; /*!< BitSize */
- };
- __I uint32_t RESERVED35[5];
-
- union {
- __IO uint32_t INVERTMAINCLK; /*!< Invert Main clock */
-
- struct {
- __IO uint32_t INVERT : 1; /*!< Invert main_clock (AHB system clock). This inversion should
- only be done for functional ATE patterns when each clock divider
- or clock gate is disabled. */
- } INVERTMAINCLK_b; /*!< BitSize */
- };
- __I uint32_t RESERVED36[99];
-
- union {
- __I uint32_t DIEID; /*!< Chip revision ID & Number */
-
- struct {
- __I uint32_t REV_ID : 4; /*!< Chip Revision ID */
- __I uint32_t MCO_NUM_IN_DIE_ID: 20; /*!< Chip Number (The JN518x SLDI name will be sRE211-A. 's' for
- Global foundry.) */
- } DIEID_b; /*!< BitSize */
- };
- __I uint32_t RESERVED37[8];
-
- union {
- __IO uint32_t CPUCFG; /*!< CPUs configuration register. Can only be updated if CONFIGLOCKOUT.LOCK=0.
- Do not disable both processors. */
-
- struct {
- __IO uint32_t DEFAULT : 1; /*!< Default CPU Master. During a write this bit is only valid only
- when both processors are enabled, otherwise this will be set
- to the enabled processor to prevent having a disabled processor
- as the master. 0 : CM4 0 is is default CPU master 1 : CM4 1
- is the default CPU master It is recommended to leave CPU 0 as
- the master processor. */
- __IO uint32_t CM40ENABLE : 1; /*!< Enable CM4 0 0 : CM4 0 is disable (Processor in reset) 1 : CM4
- 0 is enable */
- __IO uint32_t CM41ENABLE : 1; /*!< Enable CM4 1 0 : CM4 1 is disable (Processor in reset) 1 : CM4
- 1 is enable */
- } CPUCFG_b; /*!< BitSize */
- };
- __I uint32_t RESERVED38[3];
-
- union {
- __IO uint32_t CONFIGLOCKOUT; /*!< Disable write access to CPUDFG */
-
- struct {
- __IO uint32_t LOCK : 1; /*!< Disable write access to CPUCFG. Once set can not be cleared */
- } CONFIGLOCKOUT_b; /*!< BitSize */
- };
- __I uint32_t RESERVED39[2];
-
- union {
- __O uint32_t CODESECURITYPROT; /*!< Security code to allow test access via SWD/JTAG. Reset with
- POR, SW reset or BOD */
-
- struct {
- __O uint32_t SEC_CODE : 32; /*!< Security code to allow test access via SWD/JTAG. Write once
- register, value 0x87654321 enables the access. Any other value
- disables access and locks the mode. */
- } CODESECURITYPROT_b; /*!< BitSize */
- };
-} u_syscon_Type;
-
-
-/* ================================================================================ */
-/* ================ u_otpc ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component otpc It is an eFUSE OTP (One Time Programmable memory) controller with APB bus interface. More details will follow. (u_otpc)
- */
-
-typedef struct { /*!< u_otpc Structure */
-
- union {
- __IO uint32_t ADDR; /*!< Address register for reading/writing the E-Fuse OTP */
-
- struct {
- __IO uint32_t ADDR : 12; /*!< Address of OTP value to be read */
- } ADDR_b; /*!< BitSize */
- };
- __I uint32_t RESERVED0;
-
- union {
- __O uint32_t READ; /*!< Register for reading the E-Fuse OTP. */
-
- struct {
- __O uint32_t READ : 1; /*!< When 1 is written, the OTP is read. */
- uint32_t : 15;
- __O uint32_t SEQ : 16; /*!< Read unlock sequence: only when 0x7F12 is written is the APB
- commnad accepted. Write unlock sequence [Not supported]: only
- when 0x3A8D is written, the APB command is accepted. */
- } READ_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t RWIDTH; /*!< Register for configuring the read width of the E-Fuse OTP. */
-
- struct {
- __IO uint32_t OPCFG : 2; /*!< Not supported - all reads 16bits (Output width configuration). */
- } RWIDTH_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t HV_REQ; /*!< Register for requesting the high voltage (FSOURCE) for the E-Fuse
- OTP. */
-
- struct {
- __IO uint32_t PMC_REQ : 1; /*!< High voltage request. Setting is directly applied to the op_pmc_hv_request
- output line. */
- __IO uint32_t PAD_REQ : 1; /*!< High voltage request. Setting is directly applied to the op_pad_hv_request
- output line. */
- uint32_t : 14;
- __O uint32_t SEQ : 16; /*!< High voltage unlock sequence: only when 0xB9A5 is written, the
- APB command is accepted. */
- } HV_REQ_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t RDATA; /*!< Register for the OTP read back data. */
-
- struct {
- __I uint32_t DATA : 16; /*!< Read back data from the E-Fuse OTP. Access to the AES key will
- be blocked if E-Fuse OTP data bit AESR is set. */
- uint32_t : 15;
- __I uint32_t VALID : 1; /*!< Valid bit. This bit should be cleared when a Read command has
- been given and should be set when the sequencer has successfully
- captured the E-Fuse OTP data. */
- } RDATA_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t AES; /*!< Register for reading the AES key. */
-
- struct {
- __O uint32_t KEY : 1; /*!< Set to 0. [Two keys are not supported hence can not use this
- to select key to use] */
- uint32_t : 15;
- __O uint32_t SEQ : 16; /*!< AES read unlock sequence: only when 0x9F21 is written, the APB
- command is accepted. Key will be transferred from E-Fuse OTP
- and output to AES block. This occurs even if AES key read access
- is blocked. */
- } AES_b; /*!< BitSize */
- };
- __I uint32_t RESERVED1;
-
- union {
- __I uint32_t SECURITY; /*!< Register for reading the security status. */
-
- struct {
- __I uint32_t VALID : 1; /*!< When 1, an AES key has successfully been loaded to the PMC.
- When 0, no AES key has been successfully loaded or the operation
- is still on-going. */
- __I uint32_t MODE : 1; /*!< Reads as 0 [Two keys are not supported hence does not indicate
- key in use] */
- } SECURITY_b; /*!< BitSize */
- };
-} u_otpc_Type;
-
-
-/* ================================================================================ */
-/* ================ u0_i2c ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component i2c It is an Inter IC with APB bus interface. More details will follow. (u0_i2c)
- */
-
-typedef struct { /*!< u0_i2c Structure */
-
- union {
- __IO uint32_t CFG; /*!< Configuration for shared functions. */
-
- struct {
- __IO uint32_t MSTEN : 1; /*!< Master Enable. When disabled, configurations settings for the
- Master function are not changed, but the Master function is
- internally reset. */
- __IO uint32_t SLVEN : 1; /*!< Slave Enable. When disabled, configurations settings for the
- Slave function are not changed, but the Slave function is internally
- reset. */
- __IO uint32_t MONEN : 1; /*!< Monitor Enable. When disabled, configurations settings for the
- Monitor function are not changed, but the Monitor function is
- internally reset. */
- __IO uint32_t TIMEOUT : 1; /*!< I2C bus Time-out Enable. When disabled, the time-out function
- is internally reset. */
- __IO uint32_t MONCLKSTR : 1; /*!< Monitor function Clock Stretching. */
- __IO uint32_t HSCAPABLE : 1; /*!< High-speed mode Capable enable. Since High Speed mode alters
- the way I2C pins drive and filter, as well as the timing for
- certain I2C signalling, enabling High-speed mode applies to
- all functions: master, slave, and monitor. */
- } CFG_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t STAT; /*!< Status register for Master, Slave, and Monitor functions. */
-
- struct {
- __I uint32_t MSTPENDING : 1; /*!< Master Pending. Indicates that the Master is waiting to continue
- communication on the I2C-bus (pending) or is idle. When the
- master is pending, the MSTSTATE bits indicate what type of software
- service if any the master expects. This flag will cause an interrupt
- when set if, enabled via the INTENSET register. The MSTPENDING
- flag is not set when the DMA is handling an event (if the MSTDMA
- bit in the MSTCTL register is set). If the master is in the
- idle state, and no communication is needed, mask this interru */
- __I uint32_t MSTSTATE : 3; /*!< Master State code. The master state code reflects the master
- state when the MSTPENDING bit is set, that is the master is
- pending or in the idle state. Each value of this field indicates
- a specific required service for the Master function. All other
- values are reserved. */
- __IO uint32_t MSTARBLOSS : 1; /*!< Master Arbitration Loss flag. This flag can be cleared by software
- writing a 1 to this bit. It is also cleared automatically a
- 1 is written to MSTCONTINUE. */
- uint32_t : 1;
- __IO uint32_t MSTSTSTPERR: 1; /*!< Master Start/Stop Error flag. This flag can be cleared by software
- writing a 1 to this bit. It is also cleared automatically a
- 1 is written to MSTCONTINUE. */
- uint32_t : 1;
- __I uint32_t SLVPENDING : 1; /*!< Slave Pending. Indicates that the Slave function is waiting
- to continue communication on the I2C-bus and needs software
- service. This flag will cause an interrupt when set if enabled
- via INTENSET. The SLVPENDING flag is not set when the DMA is
- handling an event (if the SLVDMA bit in the SLVCTL register
- is set). The SLVPENDING flag is read-only and is automatically
- cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL
- register. The point in time when SlvPending is set depends on
- whether the I2C i */
- __I uint32_t SLVSTATE : 2; /*!< Slave State code. Each value of this field indicates a specific
- required service for the Slave function. All other values are
- reserved. See Table 393 for state values and actions. Remark:
- note that the occurrence of some states and how they are handled
- are affected by DMA mode and Automatic Operation modes. */
- __I uint32_t SLVNOTSTR : 1; /*!< Slave Not Stretching. Indicates when the slave function is stretching
- the I2C clock. This is needed in order to gracefully invoke
- Deep Sleep or Power-down modes during slave operation. This
- read-only flag reflects the slave function status in real time. */
- __I uint32_t SLVIDX : 2; /*!< Slave address match Index. This field is valid when the I2C
- slave function has been selected by receiving an address that
- matches one of the slave addresses defined by any enabled slave
- address registers, and provides an identification of the address
- that was matched. It is possible that more than one address
- could be matched, but only one match can be reported here. */
- __IO uint32_t SLVSEL : 1; /*!< Slave selected flag. SLVSEL is set after an address match when
- software tells the Slave function to acknowledge the address,
- or when the address has been automatically acknowledged. It
- is cleared when another address cycle presents an address that
- does not match an enabled address on the Slave function, when
- slave software decides to NACK a matched address, when there
- is a Stop detected on the bus, when the master NACKs slave data,
- and in some combinations of Automatic Operation. SLVSEL is not
- cleared if s */
- __IO uint32_t SLVDESEL : 1; /*!< Slave Deselected flag. This flag will cause an interrupt when
- set if enabled via INTENSET. This flag can be cleared by writing
- a 1 to this bit. */
- __I uint32_t MONRDY : 1; /*!< Monitor Ready. This flag is cleared when the MONRXDAT register
- is read. */
- __IO uint32_t MONOV : 1; /*!< Monitor Overflow flag. */
- __I uint32_t MONACTIVE : 1; /*!< Monitor Active flag. Indicates when the Monitor function considers
- the I2C bus to be active. Active is defined here as when some
- Master is on the bus: a bus Start has occurred more recently
- than a bus Stop. */
- __IO uint32_t MONIDLE : 1; /*!< Monitor Idle flag. This flag is set when the Monitor function
- sees the I2C bus change from active to inactive. This can be
- used by software to decide when to process data accumulated
- by the Monitor function. This flag will cause an interrupt when
- set if enabled via the INTENSET register. The flag can be cleared
- by writing a 1 to this bit. */
- uint32_t : 4;
- __IO uint32_t EVENTTIMEOUT: 1; /*!< Event Time-out Interrupt flag. Indicates when the time between
- events has been longer than the time specified by the TIMEOUT
- register. Events include Start, Stop, and clock edges. The flag
- is cleared by writing a 1 to this bit. No time-out is created
- when the I2C-bus is idle. */
- __IO uint32_t SCLTIMEOUT : 1; /*!< SCL Time-out Interrupt flag. Indicates when SCL has remained
- low longer than the time specific by the TIMEOUT register. The
- flag is cleared by writing a 1 to this bit. */
- } STAT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t INTENSET; /*!< Interrupt Enable Set and read register. */
-
- struct {
- __IO uint32_t MSTPENDINGEN: 1; /*!< Master Pending interrupt Enable. */
- uint32_t : 3;
- __IO uint32_t MSTARBLOSSEN: 1; /*!< Master Arbitration Loss interrupt Enable. */
- uint32_t : 1;
- __IO uint32_t MSTSTSTPERREN: 1; /*!< Master Start/Stop Error interrupt Enable. */
- uint32_t : 1;
- __IO uint32_t SLVPENDINGEN: 1; /*!< Slave Pending interrupt Enable. */
- uint32_t : 2;
- __IO uint32_t SLVNOTSTREN: 1; /*!< Slave Not Stretching interrupt Enable. */
- uint32_t : 3;
- __IO uint32_t SLVDESELEN : 1; /*!< Slave Deselect interrupt Enable. */
- __IO uint32_t MONRDYEN : 1; /*!< Monitor data Ready interrupt Enable. */
- __IO uint32_t MONOVEN : 1; /*!< Monitor Overrun interrupt Enable. */
- uint32_t : 1;
- __IO uint32_t MONIDLEEN : 1; /*!< Monitor Idle interrupt Enable. */
- uint32_t : 4;
- __IO uint32_t EVENTTIMEOUTEN: 1; /*!< Event time-out interrupt Enable. */
- __IO uint32_t SCLTIMEOUTEN: 1; /*!< SCL time-out interrupt Enable. */
- } INTENSET_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t INTENCLR; /*!< Interrupt Enable Clear register. */
-
- struct {
- __IO uint32_t MSTPCLRDINGCLR: 1; /*!< Master Pending interrupt clear. */
- uint32_t : 3;
- __IO uint32_t MSTARBLOSSCLR: 1; /*!< Master Arbitration Loss interrupt clear. */
- uint32_t : 1;
- __IO uint32_t MSTSTSTPERRCLR: 1; /*!< Master Start/Stop Error interrupt clear. */
- uint32_t : 1;
- __IO uint32_t SLVPENDINGCLR: 1; /*!< Slave Pending interrupt clear. */
- uint32_t : 2;
- __IO uint32_t SLVNOTSTRCLR: 1; /*!< Slave Not Stretching interrupt clear. */
- uint32_t : 3;
- __IO uint32_t SLVDESELCLR: 1; /*!< Slave Deselect interrupt clear. */
- __IO uint32_t MONRDYCLR : 1; /*!< Monitor data Ready interrupt clear. */
- __IO uint32_t MONOVCLR : 1; /*!< Monitor Overrun interrupt clear. */
- uint32_t : 1;
- __IO uint32_t MONIDLECLR : 1; /*!< Monitor Idle interrupt clear. */
- uint32_t : 4;
- __IO uint32_t EVCLRTTIMEOUTCLR: 1; /*!< Event time-out interrupt clear. */
- __IO uint32_t SCLTIMEOUTCLR: 1; /*!< SCL time-out interrupt clear. */
- } INTENCLR_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t TIMEOUT; /*!< Time-out value register. */
-
- struct {
- __IO uint32_t TOMIN : 4; /*!< Time-out time value, bottom four bits. These are hard-wired
- to 0xF. This gives a minimum time-out of 16 I2C function clocks
- and also a time-out resolution of 16 I2C function clocks. */
- __IO uint32_t TO : 12; /*!< Time-out time value. Specifies the time-out interval value in
- increments of 16 I2C function clocks, as defined by the CLKDIV
- register. To change this value while I2C is in operation, disable
- all time-outs, write a new value to TIMEOUT, then re-enable
- time-outs. 0x000 = A time-out will occur after 16 counts of
- the I2C function clock. 0x001 = A time-out will occur after
- 32 counts of the I2C function clock. ... 0xFFF = A time-out
- will occur after 65,536 counts of the I2C function clock. */
- } TIMEOUT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t CLKDIV; /*!< Clock pre-divider for the entire I2C interface. This determines
- what time increments are used for the MSTTIME register, and
- controls some timing of the Slave function. */
-
- struct {
- __IO uint32_t DIVVAL : 16; /*!< This field controls how the I2C clock (FCLK) is used by the
- I2C functions that need an internal clock in order to operate.
- I2C block should be configured for 8MHz clock, this will limit
- SCL master clock range from 444kHz to 2MHz. 0x0000 = FCLK is
- used directly by the I2C. 0x0001 = FCLK is divided by 2 before
- use. 0x0002 = FCLK is divided by 3 before use. ... 0xFFFF =
- FCLK is divided by 65,536 before use. */
- } CLKDIV_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t INTSTAT; /*!< Interrupt Status register for Master, Slave, and Monitor functions. */
-
- struct {
- __I uint32_t MSTPDING : 1; /*!< Master Pending interrupt. */
- uint32_t : 3;
- __I uint32_t MSTARBLOSS : 1; /*!< Master Arbitration Loss interrupt. */
- uint32_t : 1;
- __I uint32_t MSTSTSTPERR: 1; /*!< Master Start/Stop Error interrupt. */
- uint32_t : 1;
- __I uint32_t SLVPENDING : 1; /*!< Slave Pending interrupt. */
- uint32_t : 2;
- __I uint32_t SLVNOTSTR : 1; /*!< Slave Not Stretching interrupt. */
- uint32_t : 3;
- __I uint32_t SLVDESEL : 1; /*!< Slave Deselect interrupt. */
- __I uint32_t MONRDY : 1; /*!< Monitor data Ready interrupt. */
- __I uint32_t MONOV : 1; /*!< Monitor Overrun interrupt. */
- uint32_t : 1;
- __I uint32_t MONIDLE : 1; /*!< Monitor Idle interrupt. */
- uint32_t : 4;
- __I uint32_t EVTTIMEOUT : 1; /*!< Event time-out interrupt. */
- __I uint32_t SCLTIMEOUT : 1; /*!< SCL time-out interrupt. */
- } INTSTAT_b; /*!< BitSize */
- };
- __I uint32_t RESERVED0;
-
- union {
- __IO uint32_t MSTCTL; /*!< Master control register. */
-
- struct {
- __IO uint32_t MSTCONTINUE: 1; /*!< Master Continue. This bit is write-only. */
- __IO uint32_t MSTSTART : 1; /*!< Master Stop control. This bit is write-only. */
- __IO uint32_t MSTSTOP : 1; /*!< Master Stop control. This bit is write-only. */
- __IO uint32_t MSTDMA : 1; /*!< Master DMA enable. Data operations of the I2C can be performed
- with DMA. Protocol type operations such as Start, address, Stop,
- and address match must always be done with software, typically
- via an interrupt. Address acknowledgement must also be done
- by software except when the I2C is configured to be HSCAPABLE
- (and address acknowledgement is handled entirely by hardware)
- or when Automatic Operation is enabled. When a DMA data transfer
- is complete, MSTDMA must be cleared prior to beginning the next
- operati */
- } MSTCTL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t MSTTIME; /*!< Master timing configuration. */
-
- struct {
- __IO uint32_t MSTSCLLOW : 3; /*!< Master SCL Low time. Specifies the minimum low time that will
- be asserted by this master on SCL. Other devices on the bus
- (masters or slaves) could lengthen this time. This corresponds
- to the parameter tLOW in the I2C bus specification. I2C bus
- specification parameters tBUF and tSU;STA have the same values
- and are also controlled by MSTSCLLOW. */
- uint32_t : 1;
- __IO uint32_t MSTSCLHIGH : 3; /*!< Master SCL High time. Specifies the minimum high time that will
- be asserted by this master on SCL. Other masters in a multi-master
- system could shorten this time. This corresponds to the parameter
- tHIGH in the I2C bus specification. I2C bus specification parameters
- tSU;STO and tHD;STA have the same values and are also controlled
- by MSTSCLHIGH. */
- } MSTTIME_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t MSTDAT; /*!< Combined Master receiver and transmitter data register. */
-
- struct {
- __IO uint32_t DATA : 8; /*!< Master function data register. Read: read the most recently
- received data for the Master function. Write: transmit data
- using the Master function. */
- } MSTDAT_b; /*!< BitSize */
- };
- __I uint32_t RESERVED1[5];
-
- union {
- __IO uint32_t SLVCTL; /*!< Slave control register. */
-
- struct {
- __IO uint32_t SLVCONTINUE: 1; /*!< Slave Continue. */
- __IO uint32_t SLVNACK : 1; /*!< Slave NACK. */
- uint32_t : 1;
- __IO uint32_t SLVDMA : 1; /*!< Slave DMA enable. */
- uint32_t : 4;
- __IO uint32_t AUTOACK : 1; /*!< Automatic Acknowledge.When this bit is set, it will cause an
- I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD
- to be ACKed immediately; this is used with DMA to allow processing
- of the data without intervention. If this bit is clear and a
- header matches SLVADR0, the behavior is controlled by AUTONACK
- in the SLVADR0 register: allowing NACK or interrupt. */
- __IO uint32_t AUTOMATCHREAD: 1; /*!< When AUTOACK is set, this bit controls whether it matches a
- read or write request on the next header with an address matching
- SLVADR0. Since DMA needs to be configured to match the transfer
- direction, the direction needs to be specified. This bit allows
- a direction to be chosen for the next operation. */
- } SLVCTL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t SLVDAT; /*!< Combined Slave receiver and transmitter data register. */
-
- struct {
- __IO uint32_t DATA : 8; /*!< Slave function data register. Read: read the most recently received
- data for the Slave function. Write: transmit data using the
- Slave function. */
- } SLVDAT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t SLVADR0; /*!< Slave address 0. */
-
- struct {
- __IO uint32_t SADISABLE0 : 1; /*!< Slave Address 0 Disable. */
- __IO uint32_t SLVADR0 : 7; /*!< Slave Address. Seven bit slave address that is compared to received
- addresses if enabled. The compare can be affected by the setting
- of the SLVQUAL0 register. */
- uint32_t : 7;
- __IO uint32_t AUTONACK : 1; /*!< Automatic NACK operation. Used in conjunction with AUTOACK and
- AUTOMATCHREAD, allows software to ignore I2C traffic while handling
- previous I2C data or other operations. */
- } SLVADR0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t SLVADR1; /*!< Slave address 1. */
-
- struct {
- __IO uint32_t SADISABLE : 1; /*!< Slave Address 1 Disable. */
- __IO uint32_t SLVADR : 7; /*!< Slave Address. Seven bit slave address that is compared to received
- addresses if enabled. */
- } SLVADR1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t SLVADR2; /*!< Slave address 2. */
-
- struct {
- __IO uint32_t SADISABLE : 1; /*!< Slave Address 2 Disable. */
- __IO uint32_t SLVADR : 7; /*!< Slave Address. Seven bit slave address that is compared to received
- addresses if enabled. */
- } SLVADR2_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t SLVADR3; /*!< Slave address 3. */
-
- struct {
- __IO uint32_t SADISABLE : 1; /*!< Slave Address 3 Disable. */
- __IO uint32_t SLVADR : 7; /*!< Slave Address. Seven bit slave address that is compared to received
- addresses if enabled. */
- } SLVADR3_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t SLVQUAL0; /*!< Slave Qualification for address 0. */
-
- struct {
- __IO uint32_t QUALMODE0 : 1; /*!< Qualify mode for slave address 0. */
- __IO uint32_t SLVQUAL0 : 7; /*!< Slave address Qualifier for address 0. A value of 0 causes the
- address in SLVADR0 to be used as-is, assuming that it is enabled.
- If QUALMODE0 = 0, any bit in this field which is set to 1 will
- cause an automatic match of the corresponding bit of the received
- address when it is compared to the SLVADR0 register. If QUALMODE0
- = 1, an address range is matched for address 0. This range extends
- from the value defined by SLVADR0 to the address defined by
- SLVQUAL0 (address matches when SLVADR0[7:1] received address */
- } SLVQUAL0_b; /*!< BitSize */
- };
- __I uint32_t RESERVED2[9];
-
- union {
- __I uint32_t MONRXDAT; /*!< Monitor receiver data register. */
-
- struct {
- __I uint32_t MONRXDAT : 8; /*!< Monitor function Receiver Data. This reflects every data byte
- that passes on the I2C pins. */
- __I uint32_t MONSTART : 1; /*!< Monitor Received Start. */
- __I uint32_t MONRESTART : 1; /*!< Monitor Received Repeated Start. */
- __I uint32_t MONNACK : 1; /*!< Monitor Received NACK. */
- } MONRXDAT_b; /*!< BitSize */
- };
- __I uint32_t RESERVED3[990];
-
- union {
- __I uint32_t ID; /*!< I2C Module Identifier */
-
- struct {
- __I uint32_t APERTURE : 8; /*!< Aperture i.e. number minus 1 of consecutive packets 4 Kbytes
- reserved for this IP */
- __I uint32_t MIN_REV : 4; /*!< Minor revision i.e. with no software consequences */
- __I uint32_t MAJ_REV : 4; /*!< Major revision i.e. implies software modifications */
- __I uint32_t ID : 16; /*!< Identifier. This is the unique identifier of the module */
- } ID_b; /*!< BitSize */
- };
-} u0_i2c_Type;
-
-
-/* ================================================================================ */
-/* ================ u1_i2c ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component i2c It is an Inter IC with APB bus interface. More details will follow. (u1_i2c)
- */
-
-typedef struct { /*!< u1_i2c Structure */
-
- union {
- __IO uint32_t CFG; /*!< Configuration for shared functions. */
-
- struct {
- __IO uint32_t MSTEN : 1; /*!< Master Enable. When disabled, configurations settings for the
- Master function are not changed, but the Master function is
- internally reset. */
- __IO uint32_t SLVEN : 1; /*!< Slave Enable. When disabled, configurations settings for the
- Slave function are not changed, but the Slave function is internally
- reset. */
- __IO uint32_t MONEN : 1; /*!< Monitor Enable. When disabled, configurations settings for the
- Monitor function are not changed, but the Monitor function is
- internally reset. */
- __IO uint32_t TIMEOUT : 1; /*!< I2C bus Time-out Enable. When disabled, the time-out function
- is internally reset. */
- __IO uint32_t MONCLKSTR : 1; /*!< Monitor function Clock Stretching. */
- __IO uint32_t HSCAPABLE : 1; /*!< High-speed mode Capable enable. Since High Speed mode alters
- the way I2C pins drive and filter, as well as the timing for
- certain I2C signalling, enabling High-speed mode applies to
- all functions: master, slave, and monitor. */
- } CFG_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t STAT; /*!< Status register for Master, Slave, and Monitor functions. */
-
- struct {
- __I uint32_t MSTPENDING : 1; /*!< Master Pending. Indicates that the Master is waiting to continue
- communication on the I2C-bus (pending) or is idle. When the
- master is pending, the MSTSTATE bits indicate what type of software
- service if any the master expects. This flag will cause an interrupt
- when set if, enabled via the INTENSET register. The MSTPENDING
- flag is not set when the DMA is handling an event (if the MSTDMA
- bit in the MSTCTL register is set). If the master is in the
- idle state, and no communication is needed, mask this interru */
- __I uint32_t MSTSTATE : 3; /*!< Master State code. The master state code reflects the master
- state when the MSTPENDING bit is set, that is the master is
- pending or in the idle state. Each value of this field indicates
- a specific required service for the Master function. All other
- values are reserved. */
- __IO uint32_t MSTARBLOSS : 1; /*!< Master Arbitration Loss flag. This flag can be cleared by software
- writing a 1 to this bit. It is also cleared automatically a
- 1 is written to MSTCONTINUE. */
- uint32_t : 1;
- __IO uint32_t MSTSTSTPERR: 1; /*!< Master Start/Stop Error flag. This flag can be cleared by software
- writing a 1 to this bit. It is also cleared automatically a
- 1 is written to MSTCONTINUE. */
- uint32_t : 1;
- __I uint32_t SLVPENDING : 1; /*!< Slave Pending. Indicates that the Slave function is waiting
- to continue communication on the I2C-bus and needs software
- service. This flag will cause an interrupt when set if enabled
- via INTENSET. The SLVPENDING flag is not set when the DMA is
- handling an event (if the SLVDMA bit in the SLVCTL register
- is set). The SLVPENDING flag is read-only and is automatically
- cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL
- register. The point in time when SlvPending is set depends on
- whether the I2C i */
- __I uint32_t SLVSTATE : 2; /*!< Slave State code. Each value of this field indicates a specific
- required service for the Slave function. All other values are
- reserved. See Table 393 for state values and actions. Remark:
- note that the occurrence of some states and how they are handled
- are affected by DMA mode and Automatic Operation modes. */
- __I uint32_t SLVNOTSTR : 1; /*!< Slave Not Stretching. Indicates when the slave function is stretching
- the I2C clock. This is needed in order to gracefully invoke
- Deep Sleep or Power-down modes during slave operation. This
- read-only flag reflects the slave function status in real time. */
- __I uint32_t SLVIDX : 2; /*!< Slave address match Index. This field is valid when the I2C
- slave function has been selected by receiving an address that
- matches one of the slave addresses defined by any enabled slave
- address registers, and provides an identification of the address
- that was matched. It is possible that more than one address
- could be matched, but only one match can be reported here. */
- __IO uint32_t SLVSEL : 1; /*!< Slave selected flag. SLVSEL is set after an address match when
- software tells the Slave function to acknowledge the address,
- or when the address has been automatically acknowledged. It
- is cleared when another address cycle presents an address that
- does not match an enabled address on the Slave function, when
- slave software decides to NACK a matched address, when there
- is a Stop detected on the bus, when the master NACKs slave data,
- and in some combinations of Automatic Operation. SLVSEL is not
- cleared if s */
- __IO uint32_t SLVDESEL : 1; /*!< Slave Deselected flag. This flag will cause an interrupt when
- set if enabled via INTENSET. This flag can be cleared by writing
- a 1 to this bit. */
- __I uint32_t MONRDY : 1; /*!< Monitor Ready. This flag is cleared when the MONRXDAT register
- is read. */
- __IO uint32_t MONOV : 1; /*!< Monitor Overflow flag. */
- __I uint32_t MONACTIVE : 1; /*!< Monitor Active flag. Indicates when the Monitor function considers
- the I2C bus to be active. Active is defined here as when some
- Master is on the bus: a bus Start has occurred more recently
- than a bus Stop. */
- __IO uint32_t MONIDLE : 1; /*!< Monitor Idle flag. This flag is set when the Monitor function
- sees the I2C bus change from active to inactive. This can be
- used by software to decide when to process data accumulated
- by the Monitor function. This flag will cause an interrupt when
- set if enabled via the INTENSET register. The flag can be cleared
- by writing a 1 to this bit. */
- uint32_t : 4;
- __IO uint32_t EVENTTIMEOUT: 1; /*!< Event Time-out Interrupt flag. Indicates when the time between
- events has been longer than the time specified by the TIMEOUT
- register. Events include Start, Stop, and clock edges. The flag
- is cleared by writing a 1 to this bit. No time-out is created
- when the I2C-bus is idle. */
- __IO uint32_t SCLTIMEOUT : 1; /*!< SCL Time-out Interrupt flag. Indicates when SCL has remained
- low longer than the time specific by the TIMEOUT register. The
- flag is cleared by writing a 1 to this bit. */
- } STAT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t INTENSET; /*!< Interrupt Enable Set and read register. */
-
- struct {
- __IO uint32_t MSTPENDINGEN: 1; /*!< Master Pending interrupt Enable. */
- uint32_t : 3;
- __IO uint32_t MSTARBLOSSEN: 1; /*!< Master Arbitration Loss interrupt Enable. */
- uint32_t : 1;
- __IO uint32_t MSTSTSTPERREN: 1; /*!< Master Start/Stop Error interrupt Enable. */
- uint32_t : 1;
- __IO uint32_t SLVPENDINGEN: 1; /*!< Slave Pending interrupt Enable. */
- uint32_t : 2;
- __IO uint32_t SLVNOTSTREN: 1; /*!< Slave Not Stretching interrupt Enable. */
- uint32_t : 3;
- __IO uint32_t SLVDESELEN : 1; /*!< Slave Deselect interrupt Enable. */
- __IO uint32_t MONRDYEN : 1; /*!< Monitor data Ready interrupt Enable. */
- __IO uint32_t MONOVEN : 1; /*!< Monitor Overrun interrupt Enable. */
- uint32_t : 1;
- __IO uint32_t MONIDLEEN : 1; /*!< Monitor Idle interrupt Enable. */
- uint32_t : 4;
- __IO uint32_t EVENTTIMEOUTEN: 1; /*!< Event time-out interrupt Enable. */
- __IO uint32_t SCLTIMEOUTEN: 1; /*!< SCL time-out interrupt Enable. */
- } INTENSET_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t INTENCLR; /*!< Interrupt Enable Clear register. */
-
- struct {
- __IO uint32_t MSTPCLRDINGCLR: 1; /*!< Master Pending interrupt clear. */
- uint32_t : 3;
- __IO uint32_t MSTARBLOSSCLR: 1; /*!< Master Arbitration Loss interrupt clear. */
- uint32_t : 1;
- __IO uint32_t MSTSTSTPERRCLR: 1; /*!< Master Start/Stop Error interrupt clear. */
- uint32_t : 1;
- __IO uint32_t SLVPENDINGCLR: 1; /*!< Slave Pending interrupt clear. */
- uint32_t : 2;
- __IO uint32_t SLVNOTSTRCLR: 1; /*!< Slave Not Stretching interrupt clear. */
- uint32_t : 3;
- __IO uint32_t SLVDESELCLR: 1; /*!< Slave Deselect interrupt clear. */
- __IO uint32_t MONRDYCLR : 1; /*!< Monitor data Ready interrupt clear. */
- __IO uint32_t MONOVCLR : 1; /*!< Monitor Overrun interrupt clear. */
- uint32_t : 1;
- __IO uint32_t MONIDLECLR : 1; /*!< Monitor Idle interrupt clear. */
- uint32_t : 4;
- __IO uint32_t EVCLRTTIMEOUTCLR: 1; /*!< Event time-out interrupt clear. */
- __IO uint32_t SCLTIMEOUTCLR: 1; /*!< SCL time-out interrupt clear. */
- } INTENCLR_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t TIMEOUT; /*!< Time-out value register. */
-
- struct {
- __IO uint32_t TOMIN : 4; /*!< Time-out time value, bottom four bits. These are hard-wired
- to 0xF. This gives a minimum time-out of 16 I2C function clocks
- and also a time-out resolution of 16 I2C function clocks. */
- __IO uint32_t TO : 12; /*!< Time-out time value. Specifies the time-out interval value in
- increments of 16 I2C function clocks, as defined by the CLKDIV
- register. To change this value while I2C is in operation, disable
- all time-outs, write a new value to TIMEOUT, then re-enable
- time-outs. 0x000 = A time-out will occur after 16 counts of
- the I2C function clock. 0x001 = A time-out will occur after
- 32 counts of the I2C function clock. ... 0xFFF = A time-out
- will occur after 65,536 counts of the I2C function clock. */
- } TIMEOUT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t CLKDIV; /*!< Clock pre-divider for the entire I2C interface. This determines
- what time increments are used for the MSTTIME register, and
- controls some timing of the Slave function. */
-
- struct {
- __IO uint32_t DIVVAL : 16; /*!< This field controls how the I2C clock (FCLK) is used by the
- I2C functions that need an internal clock in order to operate.
- I2C block should be configured for 8MHz clock, this will limit
- SCL master clock range from 444kHz to 2MHz. 0x0000 = FCLK is
- used directly by the I2C. 0x0001 = FCLK is divided by 2 before
- use. 0x0002 = FCLK is divided by 3 before use. ... 0xFFFF =
- FCLK is divided by 65,536 before use. */
- } CLKDIV_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t INTSTAT; /*!< Interrupt Status register for Master, Slave, and Monitor functions. */
-
- struct {
- __I uint32_t MSTPDING : 1; /*!< Master Pending interrupt. */
- uint32_t : 3;
- __I uint32_t MSTARBLOSS : 1; /*!< Master Arbitration Loss interrupt. */
- uint32_t : 1;
- __I uint32_t MSTSTSTPERR: 1; /*!< Master Start/Stop Error interrupt. */
- uint32_t : 1;
- __I uint32_t SLVPENDING : 1; /*!< Slave Pending interrupt. */
- uint32_t : 2;
- __I uint32_t SLVNOTSTR : 1; /*!< Slave Not Stretching interrupt. */
- uint32_t : 3;
- __I uint32_t SLVDESEL : 1; /*!< Slave Deselect interrupt. */
- __I uint32_t MONRDY : 1; /*!< Monitor data Ready interrupt. */
- __I uint32_t MONOV : 1; /*!< Monitor Overrun interrupt. */
- uint32_t : 1;
- __I uint32_t MONIDLE : 1; /*!< Monitor Idle interrupt. */
- uint32_t : 4;
- __I uint32_t EVTTIMEOUT : 1; /*!< Event time-out interrupt. */
- __I uint32_t SCLTIMEOUT : 1; /*!< SCL time-out interrupt. */
- } INTSTAT_b; /*!< BitSize */
- };
- __I uint32_t RESERVED0;
-
- union {
- __IO uint32_t MSTCTL; /*!< Master control register. */
-
- struct {
- __IO uint32_t MSTCONTINUE: 1; /*!< Master Continue. This bit is write-only. */
- __IO uint32_t MSTSTART : 1; /*!< Master Stop control. This bit is write-only. */
- __IO uint32_t MSTSTOP : 1; /*!< Master Stop control. This bit is write-only. */
- __IO uint32_t MSTDMA : 1; /*!< Master DMA enable. Data operations of the I2C can be performed
- with DMA. Protocol type operations such as Start, address, Stop,
- and address match must always be done with software, typically
- via an interrupt. Address acknowledgement must also be done
- by software except when the I2C is configured to be HSCAPABLE
- (and address acknowledgement is handled entirely by hardware)
- or when Automatic Operation is enabled. When a DMA data transfer
- is complete, MSTDMA must be cleared prior to beginning the next
- operati */
- } MSTCTL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t MSTTIME; /*!< Master timing configuration. */
-
- struct {
- __IO uint32_t MSTSCLLOW : 3; /*!< Master SCL Low time. Specifies the minimum low time that will
- be asserted by this master on SCL. Other devices on the bus
- (masters or slaves) could lengthen this time. This corresponds
- to the parameter tLOW in the I2C bus specification. I2C bus
- specification parameters tBUF and tSU;STA have the same values
- and are also controlled by MSTSCLLOW. */
- uint32_t : 1;
- __IO uint32_t MSTSCLHIGH : 3; /*!< Master SCL High time. Specifies the minimum high time that will
- be asserted by this master on SCL. Other masters in a multi-master
- system could shorten this time. This corresponds to the parameter
- tHIGH in the I2C bus specification. I2C bus specification parameters
- tSU;STO and tHD;STA have the same values and are also controlled
- by MSTSCLHIGH. */
- } MSTTIME_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t MSTDAT; /*!< Combined Master receiver and transmitter data register. */
-
- struct {
- __IO uint32_t DATA : 8; /*!< Master function data register. Read: read the most recently
- received data for the Master function. Write: transmit data
- using the Master function. */
- } MSTDAT_b; /*!< BitSize */
- };
- __I uint32_t RESERVED1[5];
-
- union {
- __IO uint32_t SLVCTL; /*!< Slave control register. */
-
- struct {
- __IO uint32_t SLVCONTINUE: 1; /*!< Slave Continue. */
- __IO uint32_t SLVNACK : 1; /*!< Slave NACK. */
- uint32_t : 1;
- __IO uint32_t SLVDMA : 1; /*!< Slave DMA enable. */
- uint32_t : 4;
- __IO uint32_t AUTOACK : 1; /*!< Automatic Acknowledge.When this bit is set, it will cause an
- I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD
- to be ACKed immediately; this is used with DMA to allow processing
- of the data without intervention. If this bit is clear and a
- header matches SLVADR0, the behavior is controlled by AUTONACK
- in the SLVADR0 register: allowing NACK or interrupt. */
- __IO uint32_t AUTOMATCHREAD: 1; /*!< When AUTOACK is set, this bit controls whether it matches a
- read or write request on the next header with an address matching
- SLVADR0. Since DMA needs to be configured to match the transfer
- direction, the direction needs to be specified. This bit allows
- a direction to be chosen for the next operation. */
- } SLVCTL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t SLVDAT; /*!< Combined Slave receiver and transmitter data register. */
-
- struct {
- __IO uint32_t DATA : 8; /*!< Slave function data register. Read: read the most recently received
- data for the Slave function. Write: transmit data using the
- Slave function. */
- } SLVDAT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t SLVADR0; /*!< Slave address 0. */
-
- struct {
- __IO uint32_t SADISABLE0 : 1; /*!< Slave Address 0 Disable. */
- __IO uint32_t SLVADR0 : 7; /*!< Slave Address. Seven bit slave address that is compared to received
- addresses if enabled. The compare can be affected by the setting
- of the SLVQUAL0 register. */
- uint32_t : 7;
- __IO uint32_t AUTONACK : 1; /*!< Automatic NACK operation. Used in conjunction with AUTOACK and
- AUTOMATCHREAD, allows software to ignore I2C traffic while handling
- previous I2C data or other operations. */
- } SLVADR0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t SLVADR1; /*!< Slave address 1. */
-
- struct {
- __IO uint32_t SADISABLE : 1; /*!< Slave Address 1 Disable. */
- __IO uint32_t SLVADR : 7; /*!< Slave Address. Seven bit slave address that is compared to received
- addresses if enabled. */
- } SLVADR1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t SLVADR2; /*!< Slave address 2. */
-
- struct {
- __IO uint32_t SADISABLE : 1; /*!< Slave Address 2 Disable. */
- __IO uint32_t SLVADR : 7; /*!< Slave Address. Seven bit slave address that is compared to received
- addresses if enabled. */
- } SLVADR2_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t SLVADR3; /*!< Slave address 3. */
-
- struct {
- __IO uint32_t SADISABLE : 1; /*!< Slave Address 3 Disable. */
- __IO uint32_t SLVADR : 7; /*!< Slave Address. Seven bit slave address that is compared to received
- addresses if enabled. */
- } SLVADR3_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t SLVQUAL0; /*!< Slave Qualification for address 0. */
-
- struct {
- __IO uint32_t QUALMODE0 : 1; /*!< Qualify mode for slave address 0. */
- __IO uint32_t SLVQUAL0 : 7; /*!< Slave address Qualifier for address 0. A value of 0 causes the
- address in SLVADR0 to be used as-is, assuming that it is enabled.
- If QUALMODE0 = 0, any bit in this field which is set to 1 will
- cause an automatic match of the corresponding bit of the received
- address when it is compared to the SLVADR0 register. If QUALMODE0
- = 1, an address range is matched for address 0. This range extends
- from the value defined by SLVADR0 to the address defined by
- SLVQUAL0 (address matches when SLVADR0[7:1] received address */
- } SLVQUAL0_b; /*!< BitSize */
- };
- __I uint32_t RESERVED2[9];
-
- union {
- __I uint32_t MONRXDAT; /*!< Monitor receiver data register. */
-
- struct {
- __I uint32_t MONRXDAT : 8; /*!< Monitor function Receiver Data. This reflects every data byte
- that passes on the I2C pins. */
- __I uint32_t MONSTART : 1; /*!< Monitor Received Start. */
- __I uint32_t MONRESTART : 1; /*!< Monitor Received Repeated Start. */
- __I uint32_t MONNACK : 1; /*!< Monitor Received NACK. */
- } MONRXDAT_b; /*!< BitSize */
- };
- __I uint32_t RESERVED3[990];
-
- union {
- __I uint32_t ID; /*!< I2C Module Identifier */
-
- struct {
- __I uint32_t APERTURE : 8; /*!< Aperture i.e. number minus 1 of consecutive packets 4 Kbytes
- reserved for this IP */
- __I uint32_t MIN_REV : 4; /*!< Minor revision i.e. with no software consequences */
- __I uint32_t MAJ_REV : 4; /*!< Major revision i.e. implies software modifications */
- __I uint32_t ID : 16; /*!< Identifier. This is the unique identifier of the module */
- } ID_b; /*!< BitSize */
- };
-} u1_i2c_Type;
-
-
-/* ================================================================================ */
-/* ================ u2_i2c ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component i2c It is an Inter IC with APB bus interface. More details will follow. (u2_i2c)
- */
-
-typedef struct { /*!< u2_i2c Structure */
-
- union {
- __IO uint32_t CFG; /*!< Configuration for shared functions. */
-
- struct {
- __IO uint32_t MSTEN : 1; /*!< Master Enable. When disabled, configurations settings for the
- Master function are not changed, but the Master function is
- internally reset. */
- __IO uint32_t SLVEN : 1; /*!< Slave Enable. When disabled, configurations settings for the
- Slave function are not changed, but the Slave function is internally
- reset. */
- __IO uint32_t MONEN : 1; /*!< Monitor Enable. When disabled, configurations settings for the
- Monitor function are not changed, but the Monitor function is
- internally reset. */
- __IO uint32_t TIMEOUT : 1; /*!< I2C bus Time-out Enable. When disabled, the time-out function
- is internally reset. */
- __IO uint32_t MONCLKSTR : 1; /*!< Monitor function Clock Stretching. */
- __IO uint32_t HSCAPABLE : 1; /*!< High-speed mode Capable enable. Since High Speed mode alters
- the way I2C pins drive and filter, as well as the timing for
- certain I2C signalling, enabling High-speed mode applies to
- all functions: master, slave, and monitor. */
- } CFG_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t STAT; /*!< Status register for Master, Slave, and Monitor functions. */
-
- struct {
- __I uint32_t MSTPENDING : 1; /*!< Master Pending. Indicates that the Master is waiting to continue
- communication on the I2C-bus (pending) or is idle. When the
- master is pending, the MSTSTATE bits indicate what type of software
- service if any the master expects. This flag will cause an interrupt
- when set if, enabled via the INTENSET register. The MSTPENDING
- flag is not set when the DMA is handling an event (if the MSTDMA
- bit in the MSTCTL register is set). If the master is in the
- idle state, and no communication is needed, mask this interru */
- __I uint32_t MSTSTATE : 3; /*!< Master State code. The master state code reflects the master
- state when the MSTPENDING bit is set, that is the master is
- pending or in the idle state. Each value of this field indicates
- a specific required service for the Master function. All other
- values are reserved. */
- __IO uint32_t MSTARBLOSS : 1; /*!< Master Arbitration Loss flag. This flag can be cleared by software
- writing a 1 to this bit. It is also cleared automatically a
- 1 is written to MSTCONTINUE. */
- uint32_t : 1;
- __IO uint32_t MSTSTSTPERR: 1; /*!< Master Start/Stop Error flag. This flag can be cleared by software
- writing a 1 to this bit. It is also cleared automatically a
- 1 is written to MSTCONTINUE. */
- uint32_t : 1;
- __I uint32_t SLVPENDING : 1; /*!< Slave Pending. Indicates that the Slave function is waiting
- to continue communication on the I2C-bus and needs software
- service. This flag will cause an interrupt when set if enabled
- via INTENSET. The SLVPENDING flag is not set when the DMA is
- handling an event (if the SLVDMA bit in the SLVCTL register
- is set). The SLVPENDING flag is read-only and is automatically
- cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL
- register. The point in time when SlvPending is set depends on
- whether the I2C i */
- __I uint32_t SLVSTATE : 2; /*!< Slave State code. Each value of this field indicates a specific
- required service for the Slave function. All other values are
- reserved. See Table 393 for state values and actions. Remark:
- note that the occurrence of some states and how they are handled
- are affected by DMA mode and Automatic Operation modes. */
- __I uint32_t SLVNOTSTR : 1; /*!< Slave Not Stretching. Indicates when the slave function is stretching
- the I2C clock. This is needed in order to gracefully invoke
- Deep Sleep or Power-down modes during slave operation. This
- read-only flag reflects the slave function status in real time. */
- __I uint32_t SLVIDX : 2; /*!< Slave address match Index. This field is valid when the I2C
- slave function has been selected by receiving an address that
- matches one of the slave addresses defined by any enabled slave
- address registers, and provides an identification of the address
- that was matched. It is possible that more than one address
- could be matched, but only one match can be reported here. */
- __IO uint32_t SLVSEL : 1; /*!< Slave selected flag. SLVSEL is set after an address match when
- software tells the Slave function to acknowledge the address,
- or when the address has been automatically acknowledged. It
- is cleared when another address cycle presents an address that
- does not match an enabled address on the Slave function, when
- slave software decides to NACK a matched address, when there
- is a Stop detected on the bus, when the master NACKs slave data,
- and in some combinations of Automatic Operation. SLVSEL is not
- cleared if s */
- __IO uint32_t SLVDESEL : 1; /*!< Slave Deselected flag. This flag will cause an interrupt when
- set if enabled via INTENSET. This flag can be cleared by writing
- a 1 to this bit. */
- __I uint32_t MONRDY : 1; /*!< Monitor Ready. This flag is cleared when the MONRXDAT register
- is read. */
- __IO uint32_t MONOV : 1; /*!< Monitor Overflow flag. */
- __I uint32_t MONACTIVE : 1; /*!< Monitor Active flag. Indicates when the Monitor function considers
- the I2C bus to be active. Active is defined here as when some
- Master is on the bus: a bus Start has occurred more recently
- than a bus Stop. */
- __IO uint32_t MONIDLE : 1; /*!< Monitor Idle flag. This flag is set when the Monitor function
- sees the I2C bus change from active to inactive. This can be
- used by software to decide when to process data accumulated
- by the Monitor function. This flag will cause an interrupt when
- set if enabled via the INTENSET register. The flag can be cleared
- by writing a 1 to this bit. */
- uint32_t : 4;
- __IO uint32_t EVENTTIMEOUT: 1; /*!< Event Time-out Interrupt flag. Indicates when the time between
- events has been longer than the time specified by the TIMEOUT
- register. Events include Start, Stop, and clock edges. The flag
- is cleared by writing a 1 to this bit. No time-out is created
- when the I2C-bus is idle. */
- __IO uint32_t SCLTIMEOUT : 1; /*!< SCL Time-out Interrupt flag. Indicates when SCL has remained
- low longer than the time specific by the TIMEOUT register. The
- flag is cleared by writing a 1 to this bit. */
- } STAT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t INTENSET; /*!< Interrupt Enable Set and read register. */
-
- struct {
- __IO uint32_t MSTPENDINGEN: 1; /*!< Master Pending interrupt Enable. */
- uint32_t : 3;
- __IO uint32_t MSTARBLOSSEN: 1; /*!< Master Arbitration Loss interrupt Enable. */
- uint32_t : 1;
- __IO uint32_t MSTSTSTPERREN: 1; /*!< Master Start/Stop Error interrupt Enable. */
- uint32_t : 1;
- __IO uint32_t SLVPENDINGEN: 1; /*!< Slave Pending interrupt Enable. */
- uint32_t : 2;
- __IO uint32_t SLVNOTSTREN: 1; /*!< Slave Not Stretching interrupt Enable. */
- uint32_t : 3;
- __IO uint32_t SLVDESELEN : 1; /*!< Slave Deselect interrupt Enable. */
- __IO uint32_t MONRDYEN : 1; /*!< Monitor data Ready interrupt Enable. */
- __IO uint32_t MONOVEN : 1; /*!< Monitor Overrun interrupt Enable. */
- uint32_t : 1;
- __IO uint32_t MONIDLEEN : 1; /*!< Monitor Idle interrupt Enable. */
- uint32_t : 4;
- __IO uint32_t EVENTTIMEOUTEN: 1; /*!< Event time-out interrupt Enable. */
- __IO uint32_t SCLTIMEOUTEN: 1; /*!< SCL time-out interrupt Enable. */
- } INTENSET_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t INTENCLR; /*!< Interrupt Enable Clear register. */
-
- struct {
- __IO uint32_t MSTPCLRDINGCLR: 1; /*!< Master Pending interrupt clear. */
- uint32_t : 3;
- __IO uint32_t MSTARBLOSSCLR: 1; /*!< Master Arbitration Loss interrupt clear. */
- uint32_t : 1;
- __IO uint32_t MSTSTSTPERRCLR: 1; /*!< Master Start/Stop Error interrupt clear. */
- uint32_t : 1;
- __IO uint32_t SLVPENDINGCLR: 1; /*!< Slave Pending interrupt clear. */
- uint32_t : 2;
- __IO uint32_t SLVNOTSTRCLR: 1; /*!< Slave Not Stretching interrupt clear. */
- uint32_t : 3;
- __IO uint32_t SLVDESELCLR: 1; /*!< Slave Deselect interrupt clear. */
- __IO uint32_t MONRDYCLR : 1; /*!< Monitor data Ready interrupt clear. */
- __IO uint32_t MONOVCLR : 1; /*!< Monitor Overrun interrupt clear. */
- uint32_t : 1;
- __IO uint32_t MONIDLECLR : 1; /*!< Monitor Idle interrupt clear. */
- uint32_t : 4;
- __IO uint32_t EVCLRTTIMEOUTCLR: 1; /*!< Event time-out interrupt clear. */
- __IO uint32_t SCLTIMEOUTCLR: 1; /*!< SCL time-out interrupt clear. */
- } INTENCLR_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t TIMEOUT; /*!< Time-out value register. */
-
- struct {
- __IO uint32_t TOMIN : 4; /*!< Time-out time value, bottom four bits. These are hard-wired
- to 0xF. This gives a minimum time-out of 16 I2C function clocks
- and also a time-out resolution of 16 I2C function clocks. */
- __IO uint32_t TO : 12; /*!< Time-out time value. Specifies the time-out interval value in
- increments of 16 I2C function clocks, as defined by the CLKDIV
- register. To change this value while I2C is in operation, disable
- all time-outs, write a new value to TIMEOUT, then re-enable
- time-outs. 0x000 = A time-out will occur after 16 counts of
- the I2C function clock. 0x001 = A time-out will occur after
- 32 counts of the I2C function clock. ... 0xFFF = A time-out
- will occur after 65,536 counts of the I2C function clock. */
- } TIMEOUT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t CLKDIV; /*!< Clock pre-divider for the entire I2C interface. This determines
- what time increments are used for the MSTTIME register, and
- controls some timing of the Slave function. */
-
- struct {
- __IO uint32_t DIVVAL : 16; /*!< This field controls how the I2C clock (FCLK) is used by the
- I2C functions that need an internal clock in order to operate.
- I2C block should be configured for 8MHz clock, this will limit
- SCL master clock range from 444kHz to 2MHz. 0x0000 = FCLK is
- used directly by the I2C. 0x0001 = FCLK is divided by 2 before
- use. 0x0002 = FCLK is divided by 3 before use. ... 0xFFFF =
- FCLK is divided by 65,536 before use. */
- } CLKDIV_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t INTSTAT; /*!< Interrupt Status register for Master, Slave, and Monitor functions. */
-
- struct {
- __I uint32_t MSTPDING : 1; /*!< Master Pending interrupt. */
- uint32_t : 3;
- __I uint32_t MSTARBLOSS : 1; /*!< Master Arbitration Loss interrupt. */
- uint32_t : 1;
- __I uint32_t MSTSTSTPERR: 1; /*!< Master Start/Stop Error interrupt. */
- uint32_t : 1;
- __I uint32_t SLVPENDING : 1; /*!< Slave Pending interrupt. */
- uint32_t : 2;
- __I uint32_t SLVNOTSTR : 1; /*!< Slave Not Stretching interrupt. */
- uint32_t : 3;
- __I uint32_t SLVDESEL : 1; /*!< Slave Deselect interrupt. */
- __I uint32_t MONRDY : 1; /*!< Monitor data Ready interrupt. */
- __I uint32_t MONOV : 1; /*!< Monitor Overrun interrupt. */
- uint32_t : 1;
- __I uint32_t MONIDLE : 1; /*!< Monitor Idle interrupt. */
- uint32_t : 4;
- __I uint32_t EVTTIMEOUT : 1; /*!< Event time-out interrupt. */
- __I uint32_t SCLTIMEOUT : 1; /*!< SCL time-out interrupt. */
- } INTSTAT_b; /*!< BitSize */
- };
- __I uint32_t RESERVED0;
-
- union {
- __IO uint32_t MSTCTL; /*!< Master control register. */
-
- struct {
- __IO uint32_t MSTCONTINUE: 1; /*!< Master Continue. This bit is write-only. */
- __IO uint32_t MSTSTART : 1; /*!< Master Stop control. This bit is write-only. */
- __IO uint32_t MSTSTOP : 1; /*!< Master Stop control. This bit is write-only. */
- __IO uint32_t MSTDMA : 1; /*!< Master DMA enable. Data operations of the I2C can be performed
- with DMA. Protocol type operations such as Start, address, Stop,
- and address match must always be done with software, typically
- via an interrupt. Address acknowledgement must also be done
- by software except when the I2C is configured to be HSCAPABLE
- (and address acknowledgement is handled entirely by hardware)
- or when Automatic Operation is enabled. When a DMA data transfer
- is complete, MSTDMA must be cleared prior to beginning the next
- operati */
- } MSTCTL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t MSTTIME; /*!< Master timing configuration. */
-
- struct {
- __IO uint32_t MSTSCLLOW : 3; /*!< Master SCL Low time. Specifies the minimum low time that will
- be asserted by this master on SCL. Other devices on the bus
- (masters or slaves) could lengthen this time. This corresponds
- to the parameter tLOW in the I2C bus specification. I2C bus
- specification parameters tBUF and tSU;STA have the same values
- and are also controlled by MSTSCLLOW. */
- uint32_t : 1;
- __IO uint32_t MSTSCLHIGH : 3; /*!< Master SCL High time. Specifies the minimum high time that will
- be asserted by this master on SCL. Other masters in a multi-master
- system could shorten this time. This corresponds to the parameter
- tHIGH in the I2C bus specification. I2C bus specification parameters
- tSU;STO and tHD;STA have the same values and are also controlled
- by MSTSCLHIGH. */
- } MSTTIME_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t MSTDAT; /*!< Combined Master receiver and transmitter data register. */
-
- struct {
- __IO uint32_t DATA : 8; /*!< Master function data register. Read: read the most recently
- received data for the Master function. Write: transmit data
- using the Master function. */
- } MSTDAT_b; /*!< BitSize */
- };
- __I uint32_t RESERVED1[5];
-
- union {
- __IO uint32_t SLVCTL; /*!< Slave control register. */
-
- struct {
- __IO uint32_t SLVCONTINUE: 1; /*!< Slave Continue. */
- __IO uint32_t SLVNACK : 1; /*!< Slave NACK. */
- uint32_t : 1;
- __IO uint32_t SLVDMA : 1; /*!< Slave DMA enable. */
- uint32_t : 4;
- __IO uint32_t AUTOACK : 1; /*!< Automatic Acknowledge.When this bit is set, it will cause an
- I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD
- to be ACKed immediately; this is used with DMA to allow processing
- of the data without intervention. If this bit is clear and a
- header matches SLVADR0, the behavior is controlled by AUTONACK
- in the SLVADR0 register: allowing NACK or interrupt. */
- __IO uint32_t AUTOMATCHREAD: 1; /*!< When AUTOACK is set, this bit controls whether it matches a
- read or write request on the next header with an address matching
- SLVADR0. Since DMA needs to be configured to match the transfer
- direction, the direction needs to be specified. This bit allows
- a direction to be chosen for the next operation. */
- } SLVCTL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t SLVDAT; /*!< Combined Slave receiver and transmitter data register. */
-
- struct {
- __IO uint32_t DATA : 8; /*!< Slave function data register. Read: read the most recently received
- data for the Slave function. Write: transmit data using the
- Slave function. */
- } SLVDAT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t SLVADR0; /*!< Slave address 0. */
-
- struct {
- __IO uint32_t SADISABLE0 : 1; /*!< Slave Address 0 Disable. */
- __IO uint32_t SLVADR0 : 7; /*!< Slave Address. Seven bit slave address that is compared to received
- addresses if enabled. The compare can be affected by the setting
- of the SLVQUAL0 register. */
- uint32_t : 7;
- __IO uint32_t AUTONACK : 1; /*!< Automatic NACK operation. Used in conjunction with AUTOACK and
- AUTOMATCHREAD, allows software to ignore I2C traffic while handling
- previous I2C data or other operations. */
- } SLVADR0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t SLVADR1; /*!< Slave address 1. */
-
- struct {
- __IO uint32_t SADISABLE : 1; /*!< Slave Address 1 Disable. */
- __IO uint32_t SLVADR : 7; /*!< Slave Address. Seven bit slave address that is compared to received
- addresses if enabled. */
- } SLVADR1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t SLVADR2; /*!< Slave address 2. */
-
- struct {
- __IO uint32_t SADISABLE : 1; /*!< Slave Address 2 Disable. */
- __IO uint32_t SLVADR : 7; /*!< Slave Address. Seven bit slave address that is compared to received
- addresses if enabled. */
- } SLVADR2_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t SLVADR3; /*!< Slave address 3. */
-
- struct {
- __IO uint32_t SADISABLE : 1; /*!< Slave Address 3 Disable. */
- __IO uint32_t SLVADR : 7; /*!< Slave Address. Seven bit slave address that is compared to received
- addresses if enabled. */
- } SLVADR3_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t SLVQUAL0; /*!< Slave Qualification for address 0. */
-
- struct {
- __IO uint32_t QUALMODE0 : 1; /*!< Qualify mode for slave address 0. */
- __IO uint32_t SLVQUAL0 : 7; /*!< Slave address Qualifier for address 0. A value of 0 causes the
- address in SLVADR0 to be used as-is, assuming that it is enabled.
- If QUALMODE0 = 0, any bit in this field which is set to 1 will
- cause an automatic match of the corresponding bit of the received
- address when it is compared to the SLVADR0 register. If QUALMODE0
- = 1, an address range is matched for address 0. This range extends
- from the value defined by SLVADR0 to the address defined by
- SLVQUAL0 (address matches when SLVADR0[7:1] received address */
- } SLVQUAL0_b; /*!< BitSize */
- };
- __I uint32_t RESERVED2[9];
-
- union {
- __I uint32_t MONRXDAT; /*!< Monitor receiver data register. */
-
- struct {
- __I uint32_t MONRXDAT : 8; /*!< Monitor function Receiver Data. This reflects every data byte
- that passes on the I2C pins. */
- __I uint32_t MONSTART : 1; /*!< Monitor Received Start. */
- __I uint32_t MONRESTART : 1; /*!< Monitor Received Repeated Start. */
- __I uint32_t MONNACK : 1; /*!< Monitor Received NACK. */
- } MONRXDAT_b; /*!< BitSize */
- };
- __I uint32_t RESERVED3[990];
-
- union {
- __I uint32_t ID; /*!< I2C Module Identifier */
-
- struct {
- __I uint32_t APERTURE : 8; /*!< Aperture i.e. number minus 1 of consecutive packets 4 Kbytes
- reserved for this IP */
- __I uint32_t MIN_REV : 4; /*!< Minor revision i.e. with no software consequences */
- __I uint32_t MAJ_REV : 4; /*!< Major revision i.e. implies software modifications */
- __I uint32_t ID : 16; /*!< Identifier. This is the unique identifier of the module */
- } ID_b; /*!< BitSize */
- };
-} u2_i2c_Type;
-
-
-/* ================================================================================ */
-/* ================ u_iso7816 ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component iso7816 It is an ISO7816 controller with APB bus interface. More details will follow. (u_iso7816)
- */
-
-typedef struct { /*!< u_iso7816 Structure */
-
- union {
- __IO uint32_t SSR; /*!< Slot Select Register */
-
- struct {
- __IO uint32_t SOFTRESETN : 1; /*!< When set to logic 0 this bit resets the whole Contact UART (software
- reset), sets to logic 1 automatically by hardware after after
- one clock cycle if slot 1 is not activated else after one clock
- cycle after slot 1 has been automatically deactivated. Software
- should check soft reset is finished by reading SSR register
- before any further action. */
- } SSR_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PDR1_LSB; /*!< Programmable Divider Register (LSB) slot 1. Least significant
- byte of a 16-bit counter defining the ETU. The ETU counter counts
- a number of cycles of the Contact Interface clock, this defines
- the ETU. The minimum acceptable value is 0001 0000b. */
-
- struct {
- __IO uint32_t PDR1_LSB : 32; /*!< Programmable Divider Register (LSB) slot 1. Least significant
- byte of a 16-bit counter defining the ETU. The ETU counter counts
- a number of cycles of the Contact Interface clock, this defines
- the ETU. The minimum acceptable value is 0001 0000b. */
- } PDR1_LSB_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PDR1_MSB; /*!< Programmable Divider Register (MSB) slot 1. Most significant
- byte of a 16-bit counter defining the ETU. The ETU counter counts
- a number of cycles of the Contact Interface clock, this defines
- the ETU */
-
- struct {
- __IO uint32_t PDR1_MSB : 32; /*!< Programmable Divider Register (MSB) slot 1. Most significant
- byte of a 16-bit counter defining the ETU. The ETU counter counts
- a number of cycles of the Contact Interface clock, this defines
- the ETU */
- } PDR1_MSB_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t FCR; /*!< FIFO Control Register */
-
- struct {
- __IO uint32_t FTC : 5; /*!< FIFO Threshold Configuration: Define the number of received
- or transmitted characters in the FIFO triggering the ft bit
- in USR1. The FIFO depth is 32 bytes. In reception mode, it enables
- to know that a number equals to ftc(4:0) + 1 bytes have been
- received. In transmission mode, ftc(4:0) equals to the number
- of remaining bytes into the FIFO. Be careful: in reception mode
- 00000 = length 1, and in transmission mode 00000 = length 0. */
- __IO uint32_t PEC : 3; /*!< Parity Error Count - In protocol T = 0: Set the number of allowed
- repetitions in reception or transmission mode before setting
- pe in ct_usr1_reg. The value 000 indicates that, if only one
- parity error has occurred, bit pe is set at logic 1; the value
- 111 indicates that bit pe will be set at logic 1 after 8 parity
- errors. If a correct character is received before the programmed
- error number is reached, the error counter will be reset. If
- the programmed number of allowed parity errors is reached, bit
- pe in r */
- } FCR_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t GTR1; /*!< Guard Time Register slot 1. Value used by the Contact UART notably
- in transmission mode. The Contact UART will wait this number
- of ETUs before transmitting the character. In protocol T=1,
- gtr = FFh means operation at 11 ETUs. In protocol T=0, gtr =
- FFh means operation at 12 ETUs. */
-
- struct {
- __IO uint32_t GTR1 : 32; /*!< Guard Time Register slot 1. Value used by the Contact UART notably
- in transmission mode. The Contact UART will wait this number
- of ETUs before transmitting the character. In protocol T=1,
- gtr = FFh means operation at 11 ETUs. In protocol T=0, gtr =
- FFh means operation at 12 ETUs. */
- } GTR1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t UCR11; /*!< UART Configuration Register 1 slot 1 */
-
- struct {
- __IO uint32_t CONV : 1; /*!< CONVention: Bit CONV is set to logic 1 if the convention is
- direct. Bit CONV is either automatically written by hardware
- according to the convention detected during ATR, or by software
- if the bit AUTOCONV in register ct_ucr1_reg is set to logic
- 1. */
- __IO uint32_t LCT : 1; /*!< Last Character to Transmit: Bit LCT is set to logic 1 by software
- before writing the last character to be transmitted in register
- ct_utr_reg. It allows automatic change to reception mode. It
- is reset to logic 0 by hardware at the end of a successful transmission
- after 11.75 ETUs in protocol T = 0 and after 10.75 ETUs in protocol
- T = 1. When bit LCT is being reset to logic 0, bit T/R is also
- reset to logic 0 and the UART is ready to receive a character.
- LCT bit can be set to logic 1 by software not only whe */
- __IO uint32_t T_R : 1; /*!< Transmit/Receive: Defines the mode: logic 1 means transmission
- and logic 0 reception. Bit T/R is set by software for transmission
- mode. Bit T/R is automatically reset to logic 0 by hardware,
- if bit LCT has been used before transmitting the last character.
- Note that when switching from/to reception to/from transmission
- mode, the FIFO is flushed. Any remaining bytes are lost. */
- __IO uint32_t PROT : 1; /*!< PROTocol: Selects the protocol: logic 1 means T=1 and logic
- 0 T=0. */
- __IO uint32_t FC : 1; /*!< Described in a separated document. */
- __IO uint32_t FIP : 1; /*!< Force Inverse Parity: If bit FIP is set to logic 1, the Contact
- UART will NAK a correctly received character, and will transmit
- characters with wrong parity bits. */
- } UCR11_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t UCR21; /*!< UART Configuration Register 2 slot 1 */
-
- struct {
- __IO uint32_t AUTOCONVN : 1; /*!< AUTOmatically detected CONVention: If bit AUTOCONV = 1, then
- the convention is set by software using bit CONV in register
- ct_ucr1_reg. If the bit is reset to logic 0, then the configuration
- is automatically detected on the first received character and
- the bit automatically set after convention detection. */
- __IO uint32_t MANBGT : 1; /*!< MANual BGT: When set to logic 1, BGT is managed by software,
- else by hardware. */
- __IO uint32_t DISFT : 1; /*!< DISable Fifo Threshold interrupt bit: When set to logic 1 the
- bit ft in register ct_usr1_reg will not generate interrupt. */
- __IO uint32_t DISPE : 1; /*!< DISable Parity Error interrupt bit: When set to logic 1, the
- parity is not checked in both reception and transmission modes,
- the bit pe in register ct_usr1_reg will not generate interrupt. */
- __IO uint32_t DISATRCOUNTER: 1; /*!< DISable ATR counter: - Slot 1: When set to logic 1 the bits
- EARLY and MUTE in register ct_usr1_reg will not generate interrupt.
- This bit should be set before activating. */
- uint32_t : 1;
- __IO uint32_t FIFOFLUSH : 1; /*!< FIFO flush: When set to logic 1, the FIFO is flushed whatever
- the mode (reception or transmission) is. It can be used before
- any reception or transmission of characters but not while receiving
- or transmitting a character. It is reset to logic 0 by hardware
- after one clk_ip cycle. */
- __IO uint32_t WRDACC : 1; /*!< FIFO WoRD ACCess: When set to logic 1, the FIFO supports word
- (4 bytes) access (read and write), access failure is indicated
- by bit wrdaccerr in register USR2. When set to logic 0, the
- FIFO supports byte access (read and write). */
- } UCR21_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t CCR1; /*!< Clock Configuration Register slot 1 */
-
- struct {
- __IO uint32_t ACC : 3; /*!< Asynchronous Card Clock: Defines the card clock frequency: 000:
- card clock frequency = fclk_ip 001: card clock frequency = fclk_ip
- /2 010: card clock frequency = fclk_ip /3 011: card clock frequency
- = fclk_ip /4 100: card clock frequency = fclk_ip /5 101: card
- clock frequency = fclk_ip /6 110: card clock frequency = fclk_ip
- /8 111: card clock frequency = fclk_ip /16 All frequency changes
- are synchronous, thus ensuring that no spikes or unwanted pulse
- widths occur during changes. In conjunction with registe */
- __IO uint32_t SAN : 1; /*!< Synchronous/Asynchronous Card: - Slot 1: When set to logic 1,
- the Contact UART supports synchronous card. The Contact UART
- is then bypassed, only bit 0 of registers ct_urr_reg and ct_utr_reg
- is connected to pin I/O. In this case, the card clock is controlled
- by bit SHL and RST card is controlled by bit RSTIN in register
- ct_pcr_reg. When set to logic 0, the Contact UART supports asynchronous
- card. Dynamic change (while activated) is not supported. The
- choice should be done before activating the card. - Slot */
- __IO uint32_t CST : 1; /*!< Clock STop: - Slot 1: In the case of an asynchronous card, bit
- CST defines whether the clock to the card is stopped or not;
- if bit CST is reset to logic 0, then the clock is determined
- by bits ACC0, ACC1 and ACC2. - Slot AUX: This bit is not available
- for the auxiliary slot (ct_ccr2_reg) since clock stop feature
- is supported using CLKAUXen bit in ct_ssr_reg register. */
- __IO uint32_t SHL : 1; /*!< Stop HIGH or LOW: - Slot 1: If bits SAN = 0 and CST = 1, then
- the clock is stopped at LOW level if bit SHL = 0, and at HIGH
- level if bit SHL = 1. If bit SAN = 1, then contact CLK is the
- copy of the value of bit SHL. */
- } CCR1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PCR; /*!< Power Control Register */
-
- struct {
- __IO uint32_t PCR : 32; /*!< Power Control Register */
- } PCR_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t ECR; /*!< Early answer Counter register */
-
- struct {
- __IO uint32_t ECR : 32; /*!< Early answer Counter register */
- } ECR_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t MCRL_LSB; /*!< Mute card Counter RST Low register (LSB) */
-
- struct {
- __IO uint32_t MCRL_LSB : 32; /*!< Mute card Counter RST Low register (LSB) */
- } MCRL_LSB_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t MCRL_MSB; /*!< Mute card Counter RST Low register (MSB) */
-
- struct {
- __IO uint32_t MCRL_MSB : 32; /*!< Mute card Counter RST Low register (MSB) */
- } MCRL_MSB_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t MCRH_LSB; /*!< Mute card Counter RST High register (LSB) */
-
- struct {
- __IO uint32_t MCRH_LSB : 32; /*!< Mute card Counter RST High register (LSB) */
- } MCRH_LSB_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t MCRH_MSB; /*!< Mute card Counter RST High register (MSB) */
-
- struct {
- __IO uint32_t MCRH_MSB : 32; /*!< Mute card Counter RST High register (MSB) */
- } MCRH_MSB_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t SRR; /*!< Slew Rate configuration Register */
-
- struct {
- __IO uint32_t SRR : 32; /*!< Slew Rate configuration Register */
- } SRR_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t URR_UTR; /*!< UART Receive Register / UART Transmit Register */
-
- struct {
- __IO uint32_t URR_UTR : 32; /*!< UART Receive Register / UART Transmit Register */
- } URR_UTR_b; /*!< BitSize */
- };
- __I uint32_t RESERVED0[3];
-
- union {
- __O uint32_t TOR1; /*!< Time-Out Register 1 */
-
- struct {
- __O uint32_t TOR1 : 32; /*!< Time-Out Register 1 */
- } TOR1_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t TOR2; /*!< Time-Out Register 2 */
-
- struct {
- __O uint32_t TOR2 : 32; /*!< Time-Out Register 2 */
- } TOR2_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t TOR3; /*!< Time-Out Register 3 */
-
- struct {
- __O uint32_t TOR3 : 32; /*!< Time-Out Register 3 */
- } TOR3_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t TOC; /*!< Time-Out Configuration register */
-
- struct {
- __IO uint32_t TOC : 32; /*!< Time-Out Configuration register */
- } TOC_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t FSR; /*!< FIFO Status Register */
-
- struct {
- __I uint32_t FSR : 32; /*!< FIFO Status Register */
- } FSR_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t MSR; /*!< Mixed Status Register */
-
- struct {
- __I uint32_t MSR : 32; /*!< Mixed Status Register */
- } MSR_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t USR1; /*!< UART Status Register 1 */
-
- struct {
- __I uint32_t USR1 : 32; /*!< UART Status Register 1 */
- } USR1_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t USR2; /*!< UART Status Register 2 */
-
- struct {
- __I uint32_t USR2 : 32; /*!< UART Status Register 2 */
- } USR2_b; /*!< BitSize */
- };
-} u_iso7816_Type;
-
-
-/* ================================================================================ */
-/* ================ u_cic_irb ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component cic_irb. It is an Infra Red Blaster Controller with a VPB bus interface. More details will follow. (u_cic_irb)
- */
-
-typedef struct { /*!< u_cic_irb Structure */
-
- union {
- __IO uint32_t CONF; /*!< IR Blaster configuration */
-
- struct {
- __IO uint32_t ENV_INI : 1; /*!< Initial envelope value. This is the level of the first envelope
- after IR Blaster start or restart. */
- __IO uint32_t MODE : 1; /*!< Blaster mode */
- __IO uint32_t OUT : 2; /*!< Output logic function */
- __IO uint32_t NO_CAR : 1; /*!< No carrier */
- __IO uint32_t CAR_INI : 1; /*!< Initial carrier value. */
- } CONF_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t CARRIER; /*!< IR Blaster carrier configuration */
-
- struct {
- __IO uint32_t CTU : 16; /*!< Carrier Time Unit (CTU) CTU = CTU * TIRCP, TIRCP = IR module
- clock period = 1/48MHz. Value 0x0 is equivalent to 0x1. It is
- recommended to modify this field when the blaster unit is disable
- (i.e when ENA_ST = '0' in STATUS register) */
- __IO uint32_t CLOW : 3; /*!< Carrier low period. Carrier low level duration = (CLOW + 1)
- * CTU It is recommended to modify this field when the blaster
- unit is disable (i.e when ENA_ST = '0' in STATUS register) */
- __IO uint32_t CHIGH : 2; /*!< Carrier high period Carrier high level duration = (CHIGH + 1)
- * CTU It is recommended to modify this field when the blaster
- unit is disable (i.e when ENA_ST = '0' in STATUS register) */
- } CARRIER_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t FIFO_IN; /*!< IR Blaster Envelope FIFO input */
-
- struct {
- __IO uint32_t ENV : 12; /*!< Envelope duration expressed in carrier period number. Tenvelope
- = ENV * (CHIGH + CLOW + 2 ) * CTU Value 0x000 has the same behaviour
- has value 0x001. */
- __IO uint32_t ENV_INT : 1; /*!< Generate an interrupt when starting emission of the envelope */
- __IO uint32_t ENV_LAST : 1; /*!< Last envelope. */
- } FIFO_IN_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t STATUS; /*!< IR Blaster Status */
-
- struct {
- __I uint32_t FIFO_LVL : 5; /*!< Current IR Blaster FIFO level */
- __I uint32_t FIFO_FULL : 1; /*!< IR Blaster FIFO full flag */
- __I uint32_t FIFO_EMPTY : 1; /*!< IR Blaster FIFO empty flag */
- __I uint32_t ENA_ST : 1; /*!< IR Blaster status */
- __I uint32_t RUN_ST : 1; /*!< IR Blaster run status */
- } STATUS_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t CMD; /*!< IR Blaster Commands */
-
- struct {
- __O uint32_t ENA : 1; /*!< Enable IR Blaster. This bit is self clearing. */
- __O uint32_t DIS : 1; /*!< Disable IR Blaster. This bit is self clearing. */
- __O uint32_t START : 1; /*!< Start IR Blaster. This bit is self clearing. */
- __O uint32_t FIFO_RST : 1; /*!< Reset IR Blaster FIFO. This bit is self clearing. */
- } CMD_b; /*!< BitSize */
- };
- __I uint32_t RESERVED0[1011];
-
- union {
- __I uint32_t INT_STATUS; /*!< Interrupt Status */
-
- struct {
- __I uint32_t ENV_START_INT: 1; /*!< IR Blaster has started to transmit an envelope with ENV_INT
- bit = '1 */
- __I uint32_t ENV_LAST_INT: 1; /*!< IR Blaster has finished to transmit an envelope with ENV_LAST
- bit = '1'. */
- __I uint32_t FIFO_UFL_INT: 1; /*!< IR Blaster FIFO underflow. IR Blaster has tried to transmit
- a data but the FIFO was empty. */
- } INT_STATUS_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t INT_ENA; /*!< Interrupt Enable */
-
- struct {
- __IO uint32_t ENV_START_ENA: 1; /*!< Enable/Disable ENV_START interrupt */
- __IO uint32_t ENV_LAST_ENA: 1; /*!< Enable/Disable ENV_LAST interrupt */
- __IO uint32_t FIFO_UFL_ENA: 1; /*!< Enable/Disable FIFO_UFL interrupt */
- } INT_ENA_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t INT_CLR; /*!< Interrupt Clear */
-
- struct {
- __O uint32_t ENV_START_CLR: 1; /*!< Clear ENV_START interrupt */
- __O uint32_t ENV_LAST_CLR: 1; /*!< Clear ENV_LAST interrupt */
- __O uint32_t FIFO_UFL_CLR: 1; /*!< Clear FIFO_UFL interrupt */
- } INT_CLR_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t INT_SET; /*!< Interrupt Set */
-
- struct {
- __O uint32_t ENV_START_SET: 1; /*!< Set ENV_START interrupt */
- __O uint32_t ENV_LAST_SET: 1; /*!< Set ENV_LAST interrupt */
- __O uint32_t FIFO_UFL_SET: 1; /*!< Set FIFO_UFL interrupt */
- } INT_SET_b; /*!< BitSize */
- };
- __I uint32_t RESERVED1[3];
-
- union {
- __I uint32_t MODULE_ID; /*!< IR Blaster Module Identifier */
-
- struct {
- __I uint32_t APERTURE : 8; /*!< Aperture i.e. number minus 1 of consecutive packets 4 Kbytes
- reserved for this IP */
- __I uint32_t MIN_REV : 4; /*!< Minor revision i.e. with no software consequences */
- __I uint32_t MAJ_REV : 4; /*!< Major revision i.e. implies software modifications */
- __I uint32_t ID : 16; /*!< Identifier. This is the unique identifier of the module */
- } MODULE_ID_b; /*!< BitSize */
- };
-} u_cic_irb_Type;
-
-
-/* ================================================================================ */
-/* ================ u_codepatch ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component input mux. . More details will follow. (u_codepatch)
- */
-
-typedef struct { /*!< u_codepatch Structure */
-
- union {
- __IO uint32_t PATCH_CONTROL_REG; /*!< A bit to Enable/disable Patch operation */
-
- struct {
- __IO uint32_t PATCH_EN : 1; /*!< Used to Enable/Disable patch operation. It is independent of
- the Remap operation. If patch_en = 1 Patch operation is enabled.
- If patch_en = 0 Patch operation is disabled. */
- } PATCH_CONTROL_REG_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t CONTROL_1_REG; /*!< Commands to Enable/Disable the OFFSET_XX_REG (Patch 1 to Patch
- 32) */
-
- struct {
- __IO uint32_t ENABLE_PATCH_1: 1; /*!< Enable/Disable Patch 1 */
- __IO uint32_t ENABLE_PATCH_2: 1; /*!< Enable/Disable Patch 2 */
- __IO uint32_t ENABLE_PATCH_3: 1; /*!< Enable/Disable Patch 3 */
- __IO uint32_t ENABLE_PATCH_4: 1; /*!< Enable/Disable Patch 4 */
- __IO uint32_t ENABLE_PATCH_5: 1; /*!< Enable/Disable Patch 5 */
- __IO uint32_t ENABLE_PATCH_6: 1; /*!< Enable/Disable Patch 6 */
- __IO uint32_t ENABLE_PATCH_7: 1; /*!< Enable/Disable Patch 7 */
- __IO uint32_t ENABLE_PATCH_8: 1; /*!< Enable/Disable Patch 8 */
- __IO uint32_t ENABLE_PATCH_9: 1; /*!< Enable/Disable Patch 9 */
- __IO uint32_t ENABLE_PATCH_10: 1; /*!< Enable/Disable Patch 10 */
- __IO uint32_t ENABLE_PATCH_11: 1; /*!< Enable/Disable Patch 11 */
- __IO uint32_t ENABLE_PATCH_12: 1; /*!< Enable/Disable Patch 12 */
- __IO uint32_t ENABLE_PATCH_13: 1; /*!< Enable/Disable Patch 13 */
- __IO uint32_t ENABLE_PATCH_14: 1; /*!< Enable/Disable Patch 14 */
- __IO uint32_t ENABLE_PATCH_15: 1; /*!< Enable/Disable Patch 15 */
- __IO uint32_t ENABLE_PATCH_16: 1; /*!< Enable/Disable Patch 16 */
- __IO uint32_t ENABLE_PATCH_17: 1; /*!< Enable/Disable Patch 17 */
- __IO uint32_t ENABLE_PATCH_18: 1; /*!< Enable/Disable Patch 18 */
- __IO uint32_t ENABLE_PATCH_19: 1; /*!< Enable/Disable Patch 19 */
- __IO uint32_t ENABLE_PATCH_20: 1; /*!< Enable/Disable Patch 20 */
- __IO uint32_t ENABLE_PATCH_21: 1; /*!< Enable/Disable Patch 21 */
- __IO uint32_t ENABLE_PATCH_22: 1; /*!< Enable/Disable Patch 22 */
- __IO uint32_t ENABLE_PATCH_23: 1; /*!< Enable/Disable Patch 23 */
- __IO uint32_t ENABLE_PATCH_24: 1; /*!< Enable/Disable Patch 24 */
- __IO uint32_t ENABLE_PATCH_25: 1; /*!< Enable/Disable Patch 25 */
- __IO uint32_t ENABLE_PATCH_26: 1; /*!< Enable/Disable Patch 26 */
- __IO uint32_t ENABLE_PATCH_27: 1; /*!< Enable/Disable Patch 27 */
- __IO uint32_t ENABLE_PATCH_28: 1; /*!< Enable/Disable Patch 28 */
- __IO uint32_t ENABLE_PATCH_29: 1; /*!< Enable/Disable Patch 29 */
- __IO uint32_t ENABLE_PATCH_30: 1; /*!< Enable/Disable Patch 30 */
- __IO uint32_t ENABLE_PATCH_31: 1; /*!< Enable/Disable Patch 31 */
- __IO uint32_t ENABLE_PATCH_32: 1; /*!< Enable/Disable Patch 32 */
- } CONTROL_1_REG_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t CONTROL_2_REG; /*!< Commands to Enable/Disable the OFFSET_XX_REG (Patch 33 to Patch
- 48) */
-
- struct {
- __IO uint32_t ENABLE_PATCH_33: 1; /*!< Enable/Disable Patch 33 */
- __IO uint32_t ENABLE_PATCH_34: 1; /*!< Enable/Disable Patch 34 */
- __IO uint32_t ENABLE_PATCH_35: 1; /*!< Enable/Disable Patch 35 */
- __IO uint32_t ENABLE_PATCH_36: 1; /*!< Enable/Disable Patch 36 */
- __IO uint32_t ENABLE_PATCH_37: 1; /*!< Enable/Disable Patch 37 */
- __IO uint32_t ENABLE_PATCH_38: 1; /*!< Enable/Disable Patch 38 */
- __IO uint32_t ENABLE_PATCH_39: 1; /*!< Enable/Disable Patch 39 */
- __IO uint32_t ENABLE_PATCH_40: 1; /*!< Enable/Disable Patch 40 */
- __IO uint32_t ENABLE_PATCH_41: 1; /*!< Enable/Disable Patch 41 */
- __IO uint32_t ENABLE_PATCH_42: 1; /*!< Enable/Disable Patch 42 */
- __IO uint32_t ENABLE_PATCH_43: 1; /*!< Enable/Disable Patch 43 */
- __IO uint32_t ENABLE_PATCH_44: 1; /*!< Enable/Disable Patch 44 */
- __IO uint32_t ENABLE_PATCH_45: 1; /*!< Enable/Disable Patch 45 */
- __IO uint32_t ENABLE_PATCH_46: 1; /*!< Enable/Disable Patch 46 */
- __IO uint32_t ENABLE_PATCH_47: 1; /*!< Enable/Disable Patch 47 */
- __IO uint32_t ENABLE_PATCH_48: 1; /*!< Enable/Disable Patch 48 */
- } CONTROL_2_REG_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t TRAP_STATUS_REG; /*!< Status register to indicate the latest last 2 traps to the Code
- patch Vector */
-
- struct {
- __I uint32_t LAST_TRAP_0: 7; /*!< Indicates the Last trap code patch vector Number */
- uint32_t : 1;
- __I uint32_t LAST_TRAP_1: 7; /*!< Indicates the Last before one trap code patch vector Number */
- } TRAP_STATUS_REG_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t VT_REMAP_REG; /*!< Command to Enable/Disable the Vector Table Remap */
-
- struct {
- __IO uint32_t VT_REMAP_EN: 1; /*!< Bit used to Enable/Disable the Vector Table Remap */
- } VT_REMAP_REG_b; /*!< BitSize */
- };
- __I uint32_t RESERVED0[2];
-
- union {
- __IO uint32_t TESTBUS_SEL_REG; /*!< Register used for the Testbus Select line */
-
- struct {
- __IO uint32_t TESTBUS_SEL_REG: 32; /*!< Register used for the Testbus Select line */
- } TESTBUS_SEL_REG_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t OFFSET_REG[48]; /*!< Stores the offset address for Patch n with equivalent HEX value
- of SVC n instruction */
-
- struct {
- __IO uint32_t OFFSET_ADDR: 18; /*!< Offset address for Patch */
- } OFFSET_REG_b[48]; /*!< BitSize */
- };
-} u_codepatch_Type;
-
-
-/* ================================================================================ */
-/* ================ u_flash ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component input mux. . More details will follow. (u_flash)
- */
-
-typedef struct { /*!< u_flash Structure */
-
- union {
- __O uint32_t CMD; /*!< command register */
-
- struct {
- __O uint32_t CMD : 32; /*!< command register */
- } CMD_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t EVENT; /*!< event register */
-
- struct {
- __O uint32_t RST : 1; /*!< When bit is set, the controller and flash are reset. */
- __O uint32_t WAKEUP : 1; /*!< When bit is set, the controller wakes up from whatever low power
- or powerdown mode was active. If not in a powerdown mode, this
- bit has no effect. */
- __O uint32_t ABORT : 1; /*!< When bit is set, a running program/erase command is aborted. */
- } EVENT_b; /*!< BitSize */
- };
- __I uint32_t RESERVED0;
-
- union {
- __IO uint32_t AUTOPROG; /*!< specifies what commands are performed on AHB write */
-
- struct {
- __IO uint32_t AUTOPROG : 2; /*!< 00: auto programming switched off 01: execute write word 10:
- execute write word then, if the last word in a page was written,
- program page 11: reserved for future use / no action. */
- } AUTOPROG_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t STARTA; /*!< start (or only) address for next flash command */
-
- struct {
- __IO uint32_t STARTA : 18; /*!< Address / Start address for commands that take an address (range)
- as a parameter. The address is in units of memory words, not
- bytes. */
- } STARTA_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t STOPA; /*!< end address for next flash command, if command operates on address
- ranges */
-
- struct {
- __IO uint32_t STOPA : 18; /*!< Stop address for commands that take an address range as a parameter
- (the word specified by STOPA is included in the address range).
- The address is in units of memory words, not bytes. */
- } STOPA_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t TEST; /*!< test configuration register */
-
- struct {
- __IO uint32_t DCM1 : 8; /*!< These bit fields select which internal signal is brought onto
- the DCM1/2 pads */
- __IO uint32_t DCM2 : 8; /*!< These bit fields select which internal signal is brought onto
- the DCM1/2 pads */
- __IO uint32_t EXT48 : 1; /*!< This bit controls the extclk48mhz controller output */
- } TEST_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PARW; /*!< parity register; Memory parity data. */
-
- struct {
- __IO uint32_t PARW : 32; /*!< parity register; Memory parity data. */
- } PARW_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t FSQ[4]; /*!< Flexible SeQuence register 0-3 */
-
- struct {
- __IO uint32_t ST1 : 8; /*!< Start state of sub-sequence 1 */
- __IO uint32_t EN1 : 8; /*!< End state of sub-sequence 1 */
- __IO uint32_t ST2 : 8; /*!< Start state of sub-sequence 2 */
- __IO uint32_t EN2 : 8; /*!< End state of sub-sequence 2 */
- } FSQ_b[4]; /*!< BitSize */
- };
- __I uint32_t RESERVED1[20];
-
- union {
- __IO uint32_t DATAW[8]; /*!< data register, word 0-7; Memory data, or command parameter,
- or command result. */
-
- struct {
- __IO uint32_t DATAW : 32; /*!< data register, word 0-7; Memory data, or command parameter,
- or command result. */
- } DATAW_b[8]; /*!< BitSize */
- };
- __I uint32_t RESERVED2[974];
-
- union {
- __O uint32_t INT_CLR_ENABLE; /*!< Clear interrupt enable bits */
-
- struct {
- __O uint32_t FAIL : 1; /*!< When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE
- bit is cleared */
- __O uint32_t ERR : 1; /*!< When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE
- bit is cleared */
- __O uint32_t DONE : 1; /*!< When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE
- bit is cleared */
- __O uint32_t ECC_ERR : 1; /*!< When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE
- bit is cleared */
- } INT_CLR_ENABLE_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t INT_SET_ENABLE; /*!< Set interrupt enable bits */
-
- struct {
- __O uint32_t FAIL : 1; /*!< When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE
- bit is set */
- __O uint32_t ERR : 1; /*!< When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE
- bit is set */
- __O uint32_t DONE : 1; /*!< When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE
- bit is set */
- __O uint32_t ECC_ERR : 1; /*!< When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE
- bit is set */
- } INT_SET_ENABLE_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t INT_STATUS; /*!< Interrupt status bits */
-
- struct {
- __I uint32_t FAIL : 1; /*!< This status bit is set if execution of a (legal) command failed.
- The flag can be set at any time during command execution, not
- just at the end. */
- __I uint32_t ERR : 1; /*!< This status bit is set if execution of an illegal command is
- detected. A command is illegal if it is unknown, or it is not
- allowed in the current mode, or it is violating access restrictions,
- or it has invalid parameters. */
- __I uint32_t DONE : 1; /*!< This status bit is set at the end of command execution */
- __I uint32_t ECC_ERR : 1; /*!< This status bit is set if, during a memory read operation (either
- a user-requested read, or a speculative read, or reads performed
- by a controller command), a correctable or uncorrectable error
- is detected by ECC decoding logic. */
- } INT_STATUS_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t INT_ENABLE; /*!< Interrupt enable bits */
-
- struct {
- __I uint32_t FAIL : 1; /*!< If an INT_ENABLE bit is set, an interrupt request will be generated
- if the corresponding INT_STATUS bit is high. */
- __I uint32_t ERR : 1; /*!< If an INT_ENABLE bit is set, an interrupt request will be generated
- if the corresponding INT_STATUS bit is high. */
- __I uint32_t DONE : 1; /*!< If an INT_ENABLE bit is set, an interrupt request will be generated
- if the corresponding INT_STATUS bit is high. */
- __I uint32_t ECC_ERR : 1; /*!< If an INT_ENABLE bit is set, an interrupt request will be generated
- if the corresponding INT_STATUS bit is high. */
- } INT_ENABLE_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t INT_CLR_STATUS; /*!< Clear interrupt status bits */
-
- struct {
- __O uint32_t FAIL : 1; /*!< When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS
- bit is cleared */
- __O uint32_t ERR : 1; /*!< When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS
- bit is cleared */
- __O uint32_t DONE : 1; /*!< When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS
- bit is cleared */
- __O uint32_t ECC_ERR : 1; /*!< When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS
- bit is cleared */
- } INT_CLR_STATUS_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t INT_SET_STATUS; /*!< Set interrupt status bits */
-
- struct {
- __O uint32_t FAIL : 1; /*!< When a SET_STATUS bit is written to 1, the corresponding INT_STATUS
- bit is set */
- __O uint32_t ERR : 1; /*!< When a SET_STATUS bit is written to 1, the corresponding INT_STATUS
- bit is set */
- __O uint32_t DONE : 1; /*!< When a SET_STATUS bit is written to 1, the corresponding INT_STATUS
- bit is set */
- __O uint32_t ECC_ERR : 1; /*!< When a SET_STATUS bit is written to 1, the corresponding INT_STATUS
- bit is set */
- } INT_SET_STATUS_b; /*!< BitSize */
- };
- __I uint32_t RESERVED3[3];
-
- union {
- __I uint32_t MODULE_ID; /*!< Controller+Memory module identification */
-
- struct {
- __I uint32_t APERTURE : 8; /*!< Aperture i.e. number minus 1 of consecutive packets 4 Kbytes
- reserved for this IP */
- __I uint32_t MINOR_REV : 4; /*!< Minor revision i.e. with no software consequences */
- __I uint32_t MAJOR_REV : 4; /*!< Major revision i.e. implies software modifications */
- __I uint32_t ID : 16; /*!< Identifier. This is the unique identifier of the module */
- } MODULE_ID_b; /*!< BitSize */
- };
-} u_flash_Type;
-
-
-/* ================================================================================ */
-/* ================ u_wwdt ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component wwdt It is an Windowed Watchdog Timer with APB bus interface. More details will follow. (u_wwdt)
- */
-
-typedef struct { /*!< u_wwdt Structure */
-
- union {
- __IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode
- and status of the Watchdog Timer. */
-
- struct {
- __IO uint32_t WDEN : 1; /*!< Watchdog enable bit. Once this bit is set to one and a watchdog
- feed is performed, the watchdog timer will run permanently.
- 0 Stop. The watchdog timer is stopped. 1 Run. The watchdog timer
- is running. */
- __IO uint32_t WDRESET : 1; /*!< Watchdog reset enable bit. Once this bit has been written with
- a 1 it cannot be re-written with a 0. 0 Interrupt. A watchdog
- time-out will not cause a chip reset. 1 Reset. A watchdog time-out
- will cause a chip reset. */
- __IO uint32_t WDTOF : 1; /*!< Watchdog time-out flag. Set when the watchdog timer times out,
- by a feed error, or by events associated with WDPROTECT. Cleared
- by software writing a 0 to this bit position. Causes a chip
- reset if WDRESET = 1. */
- __IO uint32_t WDINT : 1; /*!< Warning interrupt flag. Set when the timer reaches the value
- in WDWARNINT. Cleared by software writing a 1 to this bit position.
- Note that this bit cannot be cleared while the WARNINT value
- is equal to the value of the TV register. This can occur if
- the value of WARNINT is 0 and the WDRESET bit is 0 when TV decrements
- to 0. */
- __IO uint32_t WDPROTECT : 1; /*!< Watchdog update mode. This bit can be set once by software and
- is only cleared by a reset. 0 Flexible. The watchdog time-out
- value (TC) can be changed at any time. 1 Threshold. The watchdog
- time-out value (TC) can be changed only after the counter is
- below the value of WDWARNINT and WDWINDOW. */
- __IO uint32_t LOCK : 1; /*!< Once this bit is set to one and a watchdog feed is performed,
- disabling or powering down the watchdog oscillator is prevented
- by hardware. This bit can be set once by software and is only
- cleared by any reset. */
- } MOD_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t TC; /*!< Watchdog timer constant register. This 24-bit register determines
- the time-out value. */
-
- struct {
- __IO uint32_t COUNT : 24; /*!< Watchdog time-out value. */
- } TC_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55
- to this register reloads the Watchdog timer with the value contained
- in TC. */
-
- struct {
- __O uint32_t FEED : 8; /*!< Feed value should be 0xAA followed by 0x55. Writing 0xAA followed
- by 0x55 to this register will reload the Watchdog timer with
- the TC value. This operation will also start the Watchdog if
- it is enabled via the WDMOD register. Setting the WDEN bit in
- the WDMOD register is not sufficient to enable the Watchdog.
- A valid feed sequence must be completed after setting WDEN before
- the Watchdog is capable of generating a reset. Until then, the
- Watchdog will ignore feed errors. */
- } FEED_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t TV; /*!< Watchdog timer value register. This 24-bit register reads out
- the current value of the Watchdog timer. */
-
- struct {
- __I uint32_t COUNT : 24; /*!< Counter timer value. The TV register is used to read the current
- value of Watchdog timer counter. */
- } TV_b; /*!< BitSize */
- };
- __I uint32_t RESERVED0;
-
- union {
- __IO uint32_t WARNINT; /*!< Watchdog Warning Interrupt compare value. */
-
- struct {
- __IO uint32_t WARNINT : 10; /*!< Watchdog warning interrupt compare value.A match of the watchdog
- timer counter to WARNINT occurs when the bottom 10 bits of the
- counter have the same value as the 10 bits of WARNINT, and the
- remaining upper bits of the counter are all 0. This gives a
- maximum time of 1,023 watchdog timer counts (4,096 watchdog
- clocks) for the interrupt to occur prior to a watchdog event.
- If WARNINT is 0, the interrupt will occur at the same time as
- the watchdog event. */
- } WARNINT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t WINDOW; /*!< Watchdog Window compare value. */
-
- struct {
- __IO uint32_t WINDOW : 24; /*!< Watchdog window value. The WINDOW register determines the highest
- TV value allowed when a watchdog feed is performed. If a feed
- sequence occurs when TV is greater than the value in WINDOW,
- a watchdog event will occur */
- } WINDOW_b; /*!< BitSize */
- };
-} u_wwdt_Type;
-
-
-/* ================================================================================ */
-/* ================ u_rtc ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component rtc It is Real Time Clock with APB bus interface. More details will follow. (u_rtc)
- */
-
-typedef struct { /*!< u_rtc Structure */
-
- union {
- __IO uint32_t CTRL; /*!< RTC control register */
-
- struct {
- __IO uint32_t SWRESET : 1; /*!< Software reset control. 0 Not in reset. The RTC is not held
- in reset. This bit must be cleared prior to configuring or initiating
- any operation of the RTC. 1 In reset. The RTC is held in reset.
- All register bits within the RTC will be forced to their reset
- value except the OFD bit. This bit must be cleared before writing
- to any register in the RTC - including writes to set any of
- the other bits within this register. Do not attempt to write
- to any bits of this register at the same time that the reset
- bit is */
- uint32_t : 1;
- __IO uint32_t ALARMT32B : 1; /*!< RTC 32-bit timer alarm flag status. 0 No match. No match has
- occurred on the 32-bit RTC timer. Writing a 0 has no effect.
- 1 Match. A match condition has occurred on the 32-bit RTC timer.
- This flag generates an RTC alarm interrupt request RTC_ALARM
- which can also wake up the part from low power modes (excluding
- deep power down mode). Writing a 1 clears this bit. */
- __IO uint32_t WAKET16B : 1; /*!< RTC 16-bit timer wake-up flag status. 0 Run. The RTC 16-bit
- timer is running. Writing a 0 has no effect. 1 Time-out. The
- 16-bit timer has timed out. This flag generates an RTC wake-up
- interrupt request RTC-WAKE which can also wake up the part from
- low power modes (excluding deep power down mode). Writing a
- 1 clears this bit. */
- __IO uint32_t ALARMDPD_EN: 1; /*!< RTC 32-bit timer alarm enable for Low power mode. 0 Disable.
- A match on the 32-bit RTC timer will not bring the part out
- of power-down modes. 1 Enable. A match on the 32-bit RTC timer
- bring the part out of power-down modes. */
- __IO uint32_t WAKEDPD_EN : 1; /*!< RTC 16-bit timer wake-up enable for power-down modes. 0 Disable.
- A match on the 16-bit RTC timer will not bring the part out
- of power-down modes. 1 Enable. A match on the 16-bit RTC timer
- bring the part out of power-down modes. */
- __IO uint32_t RTCT16B_EN : 1; /*!< RTC 16-bit timer clock enable. This bit can be set to 0 to conserve
- power if the 16-bit timer is not used. This bit has no effect
- when the RTC is disabled (bit 7 of this register is 0). 0 Disable.
- A match on the 16-bit RTC timer will not bring the part out
- of Deep power-down mode. 1 Enable. The 16-bit RTC timer is enabled. */
- __IO uint32_t RTC_EN : 1; /*!< RTC enable. 0 Disable. The RTC 32-bit timer and 16-bit timer
- clocks are shut down and the RTC operation is disabled. This
- bit should be 0 when writing to load a value in the RTC counter
- register. 1 Enable. The 32-bit RTC clock is running and RTC
- operation is enabled. This bit must be set to initiate operation
- of the RTC. To also enable the 16-bit timer clock, set bit 6
- in this register. */
- } CTRL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t MATCH; /*!< RTC 32-bit counter match register */
-
- struct {
- __IO uint32_t MATVAL : 32; /*!< Contains the match value against which the 1 Hz RTC timer will
- be compared to generate set the alarm flag RTC_ALARM and generate
- an alarm interrupt/wake-up if enabled. */
- } MATCH_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t COUNT; /*!< RTC 32-bit counter register */
-
- struct {
- __IO uint32_t VAL : 32; /*!< A read reflects the current value of the main,32-bit RTC timer.
- A write loads a new initial value into the timer. The RTC 32-bit
- counter will count up continuously at the 32-bit timer clock
- rate once the RTC Software Reset is removed (by clearing bit
- 0 of the CTRL register). Remark: Only write to this register
- when the RTC_EN bit in the RTC CTRL Register is 0. */
- } COUNT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t WAKE; /*!< 16-bit RTC timer register */
-
- struct {
- __IO uint32_t VAL : 16; /*!< A read reflects the current value of 16-bit timer. A write pre-loads
- a start count value into the 16-bit timer and initializes a
- count-downsequence. Do not write to this register while counting
- is in progress. */
- } WAKE_b; /*!< BitSize */
- };
-} u_rtc_Type;
-
-
-/* ================================================================================ */
-/* ================ u_pwm ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component pwm. It is a Pulse Width Modulation Controller with an APB bus interface. More details will follow. (u_pwm)
- */
-
-typedef struct { /*!< u_pwm Structure */
-
- union {
- __IO uint32_t CTRL0; /*!< PWM 1st Control Register (Channel 0 to Channel 10) for channel
- enables and interrupt enables. Note if all interrupts arre enabled
- with short period timings it will not be possible to manage
- all the interrupts. */
-
- struct {
- __IO uint32_t PWM_EN_0 : 1; /*!< PWM channel 0 enable. 0 = Disable / 1 = Enable. */
- __IO uint32_t PWM_EN_1 : 1; /*!< PWM channel 1 enable. 0 = Disable / 1 = Enable. */
- __IO uint32_t PWM_EN_2 : 1; /*!< PWM channel 2 enable. 0 = Disable / 1 = Enable. */
- __IO uint32_t PWM_EN_3 : 1; /*!< PWM channel 3 enable. 0 = Disable / 1 = Enable. */
- __IO uint32_t PWM_EN_4 : 1; /*!< PWM channel 4 enable. 0 = Disable / 1 = Enable. */
- __IO uint32_t PWM_EN_5 : 1; /*!< PWM channel 5 enable. 0 = Disable / 1 = Enable. */
- __IO uint32_t PWM_EN_6 : 1; /*!< PWM channel 6 enable. 0 = Disable / 1 = Enable. */
- __IO uint32_t PWM_EN_7 : 1; /*!< PWM channel 7 enable. 0 = Disable / 1 = Enable. */
- __IO uint32_t PWM_EN_8 : 1; /*!< PWM channel 8 enable. 0 = Disable / 1 = Enable. */
- __IO uint32_t PWM_EN_9 : 1; /*!< PWM channel 9 enable. 0 = Disable / 1 = Enable. */
- __IO uint32_t PWM_EN_10 : 1; /*!< PWM channel 10 enable. 0 = Disable / 1 = Enable. Note, this
- PWM channel can not be routed to a device pin. */
- uint32_t : 5;
- __IO uint32_t INT_EN_0 : 1; /*!< PWM channel 0 interrupt enable. 0 = Disable / 1 = Enable. */
- __IO uint32_t INT_EN_1 : 1; /*!< PWM channel 1 interrupt enable. 0 = Disable / 1 = Enable. */
- __IO uint32_t INT_EN_2 : 1; /*!< PWM channel 2 interrupt enable. 0 = Disable / 1 = Enable. */
- __IO uint32_t INT_EN_3 : 1; /*!< PWM channel 3 interrupt enable. 0 = Disable / 1 = Enable. */
- __IO uint32_t INT_EN_4 : 1; /*!< PWM channel 4 interrupt enable. 0 = Disable / 1 = Enable. */
- __IO uint32_t INT_EN_5 : 1; /*!< PWM channel 5 interrupt enable. 0 = Disable / 1 = Enable. */
- __IO uint32_t INT_EN_6 : 1; /*!< PWM channel 6 interrupt enable. 0 = Disable / 1 = Enable. */
- __IO uint32_t INT_EN_7 : 1; /*!< PWM channel 7 interrupt enable. 0 = Disable / 1 = Enable. */
- __IO uint32_t INT_EN_8 : 1; /*!< PWM channel 8 interrupt enable. 0 = Disable / 1 = Enable. */
- __IO uint32_t INT_EN_9 : 1; /*!< PWM channel 9 interrupt enable. 0 = Disable / 1 = Enable. */
- __IO uint32_t INT_EN_10 : 1; /*!< PWM channel 10 interrupt enable. 0 = Disable / 1 = Enable. */
- } CTRL0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t CTRL1; /*!< PWM 2nd Control Register (Channel 0 to Channel 10) for channel
- polarity and output state for a disabled channel. */
-
- struct {
- __IO uint32_t POL_0 : 1; /*!< PWM channel 0 waveform Polarity control. 0 : Set high on compare
- match, set low at the end of PWM period. 1 : Set low on compare
- match, set high at the end of PWM period */
- __IO uint32_t POL_1 : 1; /*!< PWM channel 1 waveform Polarity control. 0 : Set high on compare
- match, set low at the end of PWM period. 1 : Set low on compare
- match, set high at the end of PWM period */
- __IO uint32_t POL_2 : 1; /*!< PWM channel 2 waveform Polarity control. 0 : Set high on compare
- match, set low at the end of PWM period. 1 : Set low on compare
- match, set high at the end of PWM period */
- __IO uint32_t POL_3 : 1; /*!< PWM channel 3 waveform Polarity control. 0 : Set high on compare
- match, set low at the end of PWM period. 1 : Set low on compare
- match, set high at the end of PWM period */
- __IO uint32_t POL_4 : 1; /*!< PWM channel 4 waveform Polarity control. 0 : Set high on compare
- match, set low at the end of PWM period. 1 : Set low on compare
- match, set high at the end of PWM period */
- __IO uint32_t POL_5 : 1; /*!< PWM channel 5 waveform Polarity control. 0 : Set high on compare
- match, set low at the end of PWM period. 1 : Set low on compare
- match, set high at the end of PWM period */
- __IO uint32_t POL_6 : 1; /*!< PWM channel 6 waveform Polarity control. 0 : Set high on compare
- match, set low at the end of PWM period. 1 : Set low on compare
- match, set high at the end of PWM period */
- __IO uint32_t POL_7 : 1; /*!< PWM channel 7 waveform Polarity control. 0 : Set high on compare
- match, set low at the end of PWM period. 1 : Set low on compare
- match, set high at the end of PWM period */
- __IO uint32_t POL_8 : 1; /*!< PWM channel 8 waveform Polarity control. 0 : Set high on compare
- match, set low at the end of PWM period. 1 : Set low on compare
- match, set high at the end of PWM period */
- __IO uint32_t POL_9 : 1; /*!< PWM channel 9 waveform Polarity control. 0 : Set high on compare
- match, set low at the end of PWM period. 1 : Set low on compare
- match, set high at the end of PWM period */
- __IO uint32_t POL_10 : 1; /*!< PWM channel 10 waveform Polarity control. 0 : Set high on compare
- match, set low at the end of PWM period. 1 : Set low on compare
- match, set high at the end of PWM period */
- uint32_t : 5;
- __IO uint32_t DIS_LEVEL_0: 1; /*!< PWM channel 0 output level when PWM channel 0 is disable. 0
- = Low Level / 1 = High Level. */
- __IO uint32_t DIS_LEVEL_1: 1; /*!< PWM channel 1 output level when PWM channel 0 is disable. 0
- = Low Level / 1 = High Level. */
- __IO uint32_t DIS_LEVEL_2: 1; /*!< PWM channel 2 output level when PWM channel 0 is disable. 0
- = Low Level / 1 = High Level. */
- __IO uint32_t DIS_LEVEL_3: 1; /*!< PWM channel 3 output level when PWM channel 0 is disable. 0
- = Low Level / 1 = High Level. */
- __IO uint32_t DIS_LEVEL_4: 1; /*!< PWM channel 4 output level when PWM channel 0 is disable. 0
- = Low Level / 1 = High Level. */
- __IO uint32_t DIS_LEVEL_5: 1; /*!< PWM channel 5 output level when PWM channel 0 is disable. 0
- = Low Level / 1 = High Level. */
- __IO uint32_t DIS_LEVEL_6: 1; /*!< PWM channel 6 output level when PWM channel 0 is disable. 0
- = Low Level / 1 = High Level. */
- __IO uint32_t DIS_LEVEL_7: 1; /*!< PWM channel 7 output level when PWM channel 0 is disable. 0
- = Low Level / 1 = High Level. */
- __IO uint32_t DIS_LEVEL_8: 1; /*!< PWM channel 8 output level when PWM channel 0 is disable. 0
- = Low Level / 1 = High Level. */
- __IO uint32_t DIS_LEVEL_9: 1; /*!< PWM channel 9 output level when PWM channel 0 is disable. 0
- = Low Level / 1 = High Level. */
- } CTRL1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PSCL01; /*!< PWM Channels 0 & 1 prescalers */
-
- struct {
- __IO uint32_t PSCL_0 : 10; /*!< PWM channel 0 prescaler. The output frequency equals to clk/(PSCL_0
- + 1) */
- uint32_t : 6;
- __IO uint32_t PSCL_1 : 10; /*!< PWM channel 1 prescaler. The output frequency equals to clk/(PSCL_1
- + 1) */
- } PSCL01_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PSCL23; /*!< PWM Channels 2 & 3 prescalers */
-
- struct {
- __IO uint32_t PSCL_2 : 10; /*!< PWM channel 2 prescaler. The output frequency equals to clk/(PSCL_2
- + 1) */
- uint32_t : 6;
- __IO uint32_t PSCL_3 : 10; /*!< PWM channel 3 prescaler. The output frequency equals to clk/(PSCL_3
- + 1) */
- } PSCL23_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PSCL45; /*!< PWM Channels 4 & 5 prescalers */
-
- struct {
- __IO uint32_t PSCL_4 : 10; /*!< PWM channel 4 prescaler. The output frequency equals to clk/(PSCL_4
- + 1) */
- uint32_t : 6;
- __IO uint32_t PSCL_5 : 10; /*!< PWM channel 5 prescaler. The output frequency equals to clk/(PSCL_5
- + 1) */
- } PSCL45_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PSCL67; /*!< PWM Channels 6 & 7 prescalers */
-
- struct {
- __IO uint32_t PSCL_6 : 10; /*!< PWM channel 6 prescaler. The output frequency equals to clk/(PSCL_6
- + 1) */
- uint32_t : 6;
- __IO uint32_t PSCL_7 : 10; /*!< PWM channel 7 prescaler. The output frequency equals to clk/(PSCL_7
- + 1) */
- } PSCL67_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PSCL89; /*!< PWM Channels 8 & 9 prescalers */
-
- struct {
- __IO uint32_t PSCL_8 : 10; /*!< PWM channel 8 prescaler. The output frequency equals to clk/(PSCL_8
- + 1) */
- uint32_t : 6;
- __IO uint32_t PSCL_9 : 10; /*!< PWM channel 9 prescaler. The output frequency equals to clk/(PSCL_9
- + 1) */
- } PSCL89_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PSCL1011; /*!< PWM Channel 10 prescaler */
-
- struct {
- __IO uint32_t PSCL_10 : 10; /*!< PWM channel 10 prescaler. The output frequency equals to clk/(PSCL_10
- + 1) */
- } PSCL1011_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PCP0; /*!< PWM Channel 0 Period and Compare register. Counter will count
- down from period to zero. When Comapre value is reached PWM
- output will change on next counter decrement and be stable from
- 'Compare-1' to 0. */
-
- struct {
- __IO uint32_t PERIOD : 16; /*!< PWM channel 0 period register. The actual period equals to [PERIOD
- + 1]. 'PERIOD' must not be 0x0. */
- __IO uint32_t COMPARE : 16; /*!< PWM channel 0 compare register. 'COMPARE' must not be 0x0. */
- } PCP0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PCP1; /*!< PWM Channel 1 Period and Compare register. Counter will count
- down from period to zero. When Comapre value is reached PWM
- output will change on next counter decrement and be stable from
- 'Compare-1' to 0. */
-
- struct {
- __IO uint32_t PERIOD : 16; /*!< PWM channel 1 period register. The actual period equals to [PERIOD
- + 1]. 'PERIOD' must not be 0x0. */
- __IO uint32_t COMPARE : 16; /*!< PWM channel 1 compare register. 'COMPARE' must not be 0x0. */
- } PCP1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PCP2; /*!< PWM Channel 2 Period and Compare register. Counter will count
- down from period to zero. When Comapre value is reached PWM
- output will change on next counter decrement and be stable from
- 'Compare-1' to 0. */
-
- struct {
- __IO uint32_t PERIOD : 16; /*!< PWM channel 2 period register. The actual period equals to [PERIOD
- + 1]. 'PERIOD' must not be 0x0. */
- __IO uint32_t COMPARE : 16; /*!< PWM channel 2 compare register. 'COMPARE' must not be 0x0. */
- } PCP2_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PCP3; /*!< PWM Channel 3 Period and Compare register. Counter will count
- down from period to zero. When Comapre value is reached PWM
- output will change on next counter decrement and be stable from
- 'Compare-1' to 0. */
-
- struct {
- __IO uint32_t PERIOD : 16; /*!< PWM channel 3 period register. The actual period equals to [PERIOD
- + 1]. 'PERIOD' must not be 0x0. */
- __IO uint32_t COMPARE : 16; /*!< PWM channel 3 compare register. 'COMPARE' must not be 0x0. */
- } PCP3_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PCP4; /*!< PWM Channel 4 Period and Compare register. Counter will count
- down from period to zero. When Comapre value is reached PWM
- output will change on next counter decrement and be stable from
- 'Compare-1' to 0. */
-
- struct {
- __IO uint32_t PERIOD : 16; /*!< PWM channel 4 period register. The actual period equals to [PERIOD
- + 1]. 'PERIOD' must not be 0x0. */
- __IO uint32_t COMPARE : 16; /*!< PWM channel 4 compare register. 'COMPARE' must not be 0x0. */
- } PCP4_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PCP5; /*!< PWM Channel 5 Period and Compare register. Counter will count
- down from period to zero. When Comapre value is reached PWM
- output will change on next counter decrement and be stable from
- 'Compare-1' to 0. */
-
- struct {
- __IO uint32_t PERIOD : 16; /*!< PWM channel 5 period register. The actual period equals to [PERIOD
- + 1]. 'PERIOD' must not be 0x0. */
- __IO uint32_t COMPARE : 16; /*!< PWM channel 5 compare register. 'COMPARE' must not be 0x0. */
- } PCP5_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PCP6; /*!< PWM Channel 6 Period and Compare register. Counter will count
- down from period to zero. When Comapre value is reached PWM
- output will change on next counter decrement and be stable from
- 'Compare-1' to 0. */
-
- struct {
- __IO uint32_t PERIOD : 16; /*!< PWM channel 6 period register. The actual period equals to [PERIOD
- + 1]. 'PERIOD' must not be 0x0. */
- __IO uint32_t COMPARE : 16; /*!< PWM channel 6 compare register. 'COMPARE' must not be 0x0. */
- } PCP6_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PCP7; /*!< PWM Channel 7 Period and Compare register. Counter will count
- down from period to zero. When Comapre value is reached PWM
- output will change on next counter decrement and be stable from
- 'Compare-1' to 0. */
-
- struct {
- __IO uint32_t PERIOD : 16; /*!< PWM channel 7 period register. The actual period equals to [PERIOD
- + 1]. 'PERIOD' must not be 0x0. */
- __IO uint32_t COMPARE : 16; /*!< PWM channel 7 compare register. 'COMPARE' must not be 0x0. */
- } PCP7_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PCP8; /*!< PWM Channel 8 Period and Compare register. Counter will count
- down from period to zero. When Comapre value is reached PWM
- output will change on next counter decrement and be stable from
- 'Compare-1' to 0. */
-
- struct {
- __IO uint32_t PERIOD : 16; /*!< PWM channel 8 period register. The actual period equals to [PERIOD
- + 1]. 'PERIOD' must not be 0x0. */
- __IO uint32_t COMPARE : 16; /*!< PWM channel 8 compare register. 'COMPARE' must not be 0x0. */
- } PCP8_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PCP9; /*!< PWM Channel 9 Period and Compare register. Counter will count
- down from period to zero. When Comapre value is reached PWM
- output will change on next counter decrement and be stable from
- 'Compare-1' to 0. */
-
- struct {
- __IO uint32_t PERIOD : 16; /*!< PWM channel 9 period register. The actual period equals to [PERIOD
- + 1]. 'PERIOD' must not be 0x0. */
- __IO uint32_t COMPARE : 16; /*!< PWM channel 9 compare register. 'COMPARE' must not be 0x0. */
- } PCP9_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PCP10; /*!< PWM Channel 10 Period and Compare register. Counter will count
- down from period to zero. */
-
- struct {
- __IO uint32_t PERIOD : 16; /*!< PWM channel 10 period register. The actual period equals to
- [PERIOD + 1]. 'PERIOD' must not be 0x0. */
- __IO uint32_t COMPARE : 16; /*!< PWM channel 10 compare register. 'COMPARE' must not be 0x0. */
- } PCP10_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PST0; /*!< PWM 1st Status Register (Channel 0 to Channel 3) */
-
- struct {
- __IO uint32_t INT_FLG_0 : 1; /*!< PWM channel 0 interrupt flag. 0 : No interrupt pending 1 : Interrupt
- pending. Write 1 to clear the interrupt. */
- uint32_t : 7;
- __IO uint32_t INT_FLG_1 : 1; /*!< PWM channel 1 interrupt flag. 0 : No interrupt pending 1 : Interrupt
- pending. Write 1 to clear the interrupt. */
- uint32_t : 7;
- __IO uint32_t INT_FLG_2 : 1; /*!< PWM channel 2 interrupt flag. 0 : No interrupt pending 1 : Interrupt
- pending. Write 1 to clear the interrupt. */
- uint32_t : 7;
- __IO uint32_t INT_FLG_3 : 1; /*!< PWM channel 3 interrupt flag. 0 : No interrupt pending 1 : Interrupt
- pending. Write 1 to clear the interrupt. */
- } PST0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PST1; /*!< PWM 2nd Status Register (Channel 4 to Channel 7) */
-
- struct {
- __IO uint32_t INT_FLG_4 : 1; /*!< PWM channel 4 interrupt flag. 0 : No interrupt pending 1 : Interrupt
- pending. Write 1 to clear the interrupt. */
- uint32_t : 7;
- __IO uint32_t INT_FLG_5 : 1; /*!< PWM channel 5 interrupt flag. 0 : No interrupt pending 1 : Interrupt
- pending. Write 1 to clear the interrupt. */
- uint32_t : 7;
- __IO uint32_t INT_FLG_6 : 1; /*!< PWM channel 6 interrupt flag. 0 : No interrupt pending 1 : Interrupt
- pending. Write 1 to clear the interrupt. */
- uint32_t : 7;
- __IO uint32_t INT_FLG_7 : 1; /*!< PWM channel 7 interrupt flag. 0 : No interrupt pending 1 : Interrupt
- pending. Write 1 to clear the interrupt. */
- } PST1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PST2; /*!< PWM 3rd Status Register (Channel 8 to Channel 10) */
-
- struct {
- __IO uint32_t INT_FLG_8 : 1; /*!< PWM channel 8 interrupt flag. 0 : No interrupt pending 1 : Interrupt
- pending. Write 1 to clear the interrupt. */
- uint32_t : 7;
- __IO uint32_t INT_FLG_9 : 1; /*!< PWM channel 9 interrupt flag. 0 : No interrupt pending 1 : Interrupt
- pending. Write 1 to clear the interrupt. */
- uint32_t : 7;
- __IO uint32_t INT_FLG_10 : 1; /*!< PWM channel 10 interrupt flag. 0 : No interrupt pending 1 :
- Interrupt pending. Write 1 to clear the interrupt. */
- } PST2_b; /*!< BitSize */
- };
- __I uint32_t RESERVED0[1001];
-
- union {
- __I uint32_t MODULE_ID; /*!< PWM Module Identifier ( */
-
- struct {
- __I uint32_t APERTURE : 8; /*!< Aperture i.e. number minus 1 of consecutive packets 4 Kbytes
- reserved for this IP */
- __I uint32_t MIN_REV : 4; /*!< Minor revision i.e. with no software consequences */
- __I uint32_t MAJ_REV : 4; /*!< Major revision i.e. implies software modifications */
- __I uint32_t ID : 16; /*!< Identifier. This is the unique identifier of the module */
- } MODULE_ID_b; /*!< BitSize */
- };
-} u_pwm_Type;
-
-
-/* ================================================================================ */
-/* ================ u_rng ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component rng. It is an Universal Synchrnous/Asynchrnous Receiver/Transmitter with APB bus interface. More details will follow. (u_rng)
- */
-
-typedef struct { /*!< u_rng Structure */
-
- union {
- __I uint32_t RANDOM_NUMBER; /*!< This register contains a random 32 bit number which is computed
- on demand, at each time it is read. Weak cryptographic post-processing
- is used to maximize throughput */
-
- struct {
- __I uint32_t RANDOM_NUMBER: 32; /*!< This register contains a random 32 bit number which is computed
- on demand, at each time it is read. Weak cryptographic post-processing
- is used to maximize throughput */
- } RANDOM_NUMBER_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t ENCRYPTED_NUMBER; /*!< This register contains a random 32 bit number which is pre-computed.
- Take care that throughput is limited by the latency of the strong
- cryptographic module (AES). The bus is stalled till a new number
- is available. Since pre-computed, first 4 requests of a burst
- of requests will not stall the bus. */
-
- struct {
- __I uint32_t ENCRYPTED_NUMBER: 32; /*!< This register contains a random 32 bit number which is pre-computed.
- Take care that throughput is limited by the latency of the strong
- cryptographic module (AES). The bus is stalled till a new number
- is available. Since pre-computed, first 4 requests of a burst
- of requests will not stall the bus. */
- } ENCRYPTED_NUMBER_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t COUNTER_VAL; /*!< COUNTER_VAL */
-
- struct {
- __I uint32_t CLK_RATIO : 8; /*!< Gives the ratio between the internal clocks frequencies and
- the register clock frequency for evaluation and certification
- purposes. Internal clock frequencies are half the incoming ones:
- COUNTER_VAL = round[ (intFreq/2)/regFreq*256*(1<<(4*shift4x))
- ] MODULO 256 If shitf4x==0, intFreq ~= regFreq*COUNTER_VAL/256*2
- Use clock_sel to select which clock you want to measure, in
- this range: 1..5 */
- __I uint32_t REFRESH_CNT: 5; /*!< Incremented (till max possible value) each time COUNTER was
- updated since last reading to any *_NUMBER. This gives an indication
- on 'entropy refill'. Example, with 'mode'=10, 'clock_sel'=0,
- 'data_sel'=00: if 'chi' is correct then any increase in 'refresh_cnt'
- gives the indication that at least 1 bit of entropy was generated
- since last reading to any *_NUMBER. If 'data_sel'=01 and 'chi'
- is still correct then this gives 8 bits of entropy. Clocks can
- be tested separately (change 'clock_sel' to 1..5) to conclu */
- } COUNTER_VAL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t COUNTER_CFG; /*!< COUNTER_CFG */
-
- struct {
- __IO uint32_t MODE : 2; /*!< 00: disabled 01: update once. Will return to 00 once done 10:
- free running: updates countinuously. If associated to setting
- 'clock_sel'=0, this activates feature 'enhanced entropy refill',
- with some spreading among all RNGs */
- __IO uint32_t CLOCK_SEL : 3; /*!< Selects the internal clock on which to compute statistics. 1
- is for first one, 2 for second one, . And 0 is for a XOR of
- results from all clocks */
- __IO uint32_t SHIFT4X : 3; /*!< To be used to add precision to clock_ratio and determine 'entropy
- refill'. Supported range is 0..4 Used as well for ONLINE_TEST */
- __IO uint32_t DIS_ENH_ENTR_REFILL: 1; /*!< Disable 'enhanced entropy refill' feature, which is enabled
- by default when 'mode' > 00. This field should be configured
- when 'mode'=00 (since considered pseudo-static). When this bit
- is set, all other settings of this IP do not have any impact
- on the generated numbers. Do not use: for evaluation purpose
- only */
- __IO uint32_t FORCE_ENTR_SPREADING: 1; /*!< Forces entropy spreading (interactions between RNGs) even when
- 'clock_sel'>0. Usefull to evaluate 'entropy refill' for one
- clock separately. Meaningless when 'mode'=00. Do not use: for
- evaluation purpose only */
- } COUNTER_CFG_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t ONLINE_TEST_CFG; /*!< ONLINE_TEST_CFG */
-
- struct {
- __IO uint32_t ACTIVATE : 1; /*!< 0: disabled 1: activated Update rythm for VAL depends on COUNTER_CFG
- if data_sel is set to COUNTER. Otherwise VAL is updated each
- time RANDOM_NUMBER or ENCRYPTED_NUMBER is read */
- __IO uint32_t DATA_SEL : 2; /*!< Selects source on which to apply online test: 00: LSB of COUNTER:
- raw data from one or all sources of entropy 01: MSB of COUNTER:
- raw data from one or all sources of entropy 10: RANDOM_NUMBER
- 11: ENCRYPTED_NUMBER 'activate' should be set to 'disabled'
- before changing this field */
- } ONLINE_TEST_CFG_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t ONLINE_TEST_VAL; /*!< ONLINE_TEST_VAL */
-
- struct {
- __I uint32_t LIVE_CHI_SQUARED: 4; /*!< This value is updated as described in field 'activate'. Low
- value means good, high value means no good. If 'data_sel'<10,
- increase 'shift4x' till 'chi' is correct and poll 'refresh_cnt'
- before reading any *_NUMBER. */
- __I uint32_t MIN_CHI_SQUARED: 4; /*!< This field is reset when 'activate'==0 */
- __I uint32_t MAX_CHI_SQUARED: 4; /*!< This field is reset when 'activate'==0 */
- } ONLINE_TEST_VAL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t MISC_CFG; /*!< MISC_CFG */
-
- struct {
- __IO uint32_t AES_RESEED : 1; /*!< If set, ENCRYPTED_NUMBER generation becomes predictable, provided
- all secrets and current internal state are known: independant
- from entropy source. This mode is still FIPS 140-2 compliant.
- Do not use: for evaluation purpose only */
- __IO uint32_t AES_DT_CFG : 1; /*!< Set this bit to re-seed AES. Then read few RANDOM_NUMBERs. Then
- reset this bit. */
- } MISC_CFG_b; /*!< BitSize */
- };
- __I uint32_t RESERVED0[1014];
-
- union {
- __IO uint32_t POWERDOWN; /*!< Powerdown mode (standard but certainly useless here) */
-
- struct {
- __IO uint32_t SOFT_RESET : 1; /*!< Request softreset that will go low automaticaly after acknowledge
- from CORE */
- __IO uint32_t FORCE_SOFT_RESET: 1; /*!< When used with softreset it forces CORE_RESETN to low on acknowledge
- from CORE */
- uint32_t : 29;
- __IO uint32_t POWERDOWN : 1; /*!< When set all accesses to standard registers are blocked */
- } POWERDOWN_b; /*!< BitSize */
- };
- __I uint32_t RESERVED1;
-
- union {
- __I uint32_t MODULEID; /*!< IP identifier */
-
- struct {
- __I uint32_t APERTURE : 8; /*!< Aperture i.e. number minus 1 of consecutive packets 4 Kbytes
- reserved for this IP */
- __I uint32_t MIN_REV : 4; /*!< Minor revision i.e. with no software consequences */
- __I uint32_t MAJ_REV : 4; /*!< Major revision i.e. implies software modifications */
- __I uint32_t ID : 16; /*!< Identifier. This is the unique identifier of the module */
- } MODULEID_b; /*!< BitSize */
- };
-} u_rng_Type;
-
-
-/* ================================================================================ */
-/* ================ u_inmux ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component input mux. . More details will follow. (u_inmux)
- */
-
-typedef struct { /*!< u_inmux Structure */
- __I uint32_t RESERVED0[48];
-
- union {
- __IO uint32_t PINTSEL[8]; /*!< Pin interrupt select register */
-
- struct {
- __IO uint32_t INTPIN : 5; /*!< Pin number select for pin interrupt or pattern match engine
- input. */
- } PINTSEL_b[8]; /*!< BitSize */
- };
-
- union {
- __IO uint32_t DMA_ITRIG_INMUX[19]; /*!< Trigger select register for DMA channel */
-
- struct {
- __IO uint32_t INP : 5; /*!< Trigger input number (decimal value) for DMA channel n (n =
- 0 to 17). 0 = ADC0 Sequence A interrupt; 1 = ADC0 Sequence B
- interrupt; 2 = Timer CT32B0 Match 0; 3 = Timer CT32B0 Match
- 1; 4 = Timer CT32B1 Match 0; 5 = Timer CT32B1 Match 1; 6 = Pin
- interrupt 0; 7 = Pin interrupt 1; 8 = Pin interrupt 2; 9 = Pin
- interrupt 3; 10 = AES RX; 11 = AES TX; 12 = Hash RX; 13 = Hash
- TX; 14 = DMA output trigger mux 0; 15 = DMA output trigger mux
- 1; 16 = DMA output trigger mux 2; 17 = DMA output trigger mux
- 3. */
- } DMA_ITRIG_INMUX_b[19]; /*!< BitSize */
- };
- __I uint32_t RESERVED1[13];
-
- union {
- __IO uint32_t DMA_OTRIG_INMUX[4]; /*!< DMA output trigger selection to become DMA trigger */
-
- struct {
- __IO uint32_t INP : 5; /*!< DMA trigger output number (decimal value) for DMA channel n
- (n = 0 to 19). */
- } DMA_OTRIG_INMUX_b[4]; /*!< BitSize */
- };
- __I uint32_t RESERVED2[4];
-
- union {
- __IO uint32_t FREQMEAS_REF; /*!< Selection for frequency measurement reference clock */
-
- struct {
- __IO uint32_t CLKIN : 4; /*!< Clock source number (decimal value) for frequency measure function
- ref clock: 0 = CLK_IN (must be enabled in functional mux); 1
- = XTAL 32 MHz (must be enabled in clock_ctrl); 2 = FRO 1 MHz
- (must be enabled in clock_ctrl); 3 = 32 kHz oscillator (either
- FRO 32 KHz or XTAL 32 KHZ); 4 = Main clock (divided); 5 = PIO[4]
- (must be configured as GPIO); 6 = PIO[20] (must be configured
- as GPIO); 7 = PIO[16] (must be configured as GPIO); 8 = PIO[15]
- (must be configured as GPIO). */
- } FREQMEAS_REF_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t FREQMEAS_TARGET; /*!< Selection for frequency measurement target clock */
-
- struct {
- __IO uint32_t CLKIN : 4; /*!< Clock source number (decimal value) for frequency measure function
- target clock: 0 = CLK_IN (must be enabled in functional mux);
- 1 = XTAL 32 MHz (must be enabled in clock_ctrl); 2 = FRO 1 MHz
- (must be enabled in clock_ctrl); 3 = 32 kHz oscillator (either
- FRO 32 KHz or XTAL 32 KHZ); 4 = Main clock (divided); 5 = PIO[4]
- (must be configured as GPIO); 6 = PIO[20] (must be configured
- as GPIO); 7 = PIO[16] (must be configured as GPIO); 8 = PIO[15]
- (must be configured as GPIO). */
- } FREQMEAS_TARGET_b; /*!< BitSize */
- };
-} u_inmux_Type;
-
-
-/* ================================================================================ */
-/* ================ u_iocon ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component input mux. . More details will follow. (u_iocon)
- */
-
-typedef struct { /*!< u_iocon Structure */
-
- union {
- __IO uint32_t PIO[22]; /*!< Configuration array for PIO0 to PIO21. PIO[10] and PIO[11] use
- a different IO cell type to the other PIO pins and so there
- are some differences in the bit field descriptions of the PIO
- register for these Ios. Reset values vary depending on whether
- the IO is configured with a pull-up or pull-down resistor as
- default. The value is also affected by the IO type. Reset value
- 0x180 for PIO 0,3,4,5,8,9,12,13,14,15,16,21. Reset value 0x198
- for PIO 1,2,6,7,17,18,19,20. Reset value 0x188 for PIO 10,11. */
-
- struct {
- __IO uint32_t FUNC : 3; /*!< Selects pin function. 0 is for GPIO mode. For other values,
- see IO mux */
- __IO uint32_t MODE : 2; /*!< Selects function mode (on-chip pull-up/pull-down resistor control).
- For MFIO type ONLY (all PIOs except PIO10 & 11): 0x0 : Pull-up.
- Pull-up resistor enabled. 0x1 : Repeater mode (bus keeper) 0x2
- : Plain Input 0x3 : Pull-down. Pull-down resistor enabled. FOR
- IIC/GPIO type ONLY (PIO10 & 11); 0x0 : I2C S/F & FP transmit
- mode (SDA and SCL) & I2C HS transmit mode (only SDAH) 0x1/0x3
- : GPIO mode (high speed if EHS is high, low speed if EHS is
- low: see SLEW0) 0x2 : I2C HS transmit mode (SCLH) Note: When
- the regis */
- __IO uint32_t SLEW0 : 1; /*!< Driver slew rate. Note: -When the register is related to a general
- purpose MFIO type pad (that is all PIOs except PIO10 & 11),
- this bit field (Bit [5]) is connected to EHS0 input of the MFIO
- pad. To be used in combination with SLEW1 'EHS1'. The higher
- [EHS1,EHS0] the quicker -When the register is related to a combo
- I2C/GPIO (IICFPGPIO) type pad (that is PIO10 & 11), this bit
- field (Bit [5]) is connected to EHS input of the IICFPGPIO pad
- ('Speed Selection bit': high for high speed GPIO, low for low
- speed GP */
- __IO uint32_t INVERT : 1; /*!< Input polarity. 0 Disabled. Input function is not inverted.
- 1 Enabled. Input is function inverted. */
- __IO uint32_t DIGIMODE : 1; /*!< Select Analog/Digital mode. 0 Analog mode. 1 Digital mode. When
- in analog mode, the receiver path in the IO cell is disabled.
- In this mode, it is essential that the digital function (e.g.
- GPIO) is not configured as an output. Otherwise it may conflict
- with analog stuff (loopback of digital on analog input). In
- other words, it's not because the IO is in analog mode that
- the digital output is automatically switched off. As a consequence,
- it is not possible to disable the receiver path when the IO
- is used for */
- __IO uint32_t FILTEROFF : 1; /*!< Controls input glitch filter. 0 Filter enabled. Noise pulses
- below approximately 1ns (MFIO) or 3ns (I2C in GPIO mode *) are
- filtered out. 1 Filter disabled. No input filtering is done.
- (*) for PIO10&11 in I2C mode it's 50ns if 'FSEL' is 0, 10ns
- if 'FSEL' is 1 iso 3ns */
- __IO uint32_t SLEW1 : 1; /*!< Driver slew rate. Note: -When the register is related to a general
- purpose MFIO type pad (that is all PIOs except PIO10 & 11),
- this bit field (Bit [9]) is connected to EHS1 input of the MFIO
- pad. To be used in combination with SLEW0 'EHS0'. The higher
- [EHS1,EHS0] the quicker -When the register is related to a combo
- I2C/GPIO (IICFPGPIO) type pad (that is PIO10 & 11), this bit
- field (Bit [9]) is connected to FSEL input of the IICFPGPIO
- pad ('Filter Select': 0 for 50ns, 1 for 10ns in I2C mode, no
- effect in GP */
- __IO uint32_t OD : 1; /*!< Controls open-drain mode. 0 : Normal. Normal push-pull output
- 1 : Open-drain. Simulated open-drain output (high drive disabled). */
- __IO uint32_t SSEL : 1; /*!< Supply Selection bit. Valid only for combo pad GPIO/IIC -When
- the register is related to a combo I2C/GPIO (IICFPGPIO) type
- pad (that is PIO10 & 11), this bit field (Bit [11]) is connected
- to SSEL input of the IICFPGPIO pad ('Supply Selection bit').
- Note for non combo pad: - IO_CLAMP When the register is related
- to a general purpose MFIO type pad (that is all PIOs except
- PIO10 & 11), this bit field (Bit [11])controls the io_clamp
- function. Assert to freeze the IO. Also needs SYSCON:RETENTIONCTRL
- set as well */
- __IO uint32_t DBG_FUNC : 4; /*!< Select Debug function (for all PIOs expect PIO10 and PIO11).
- Note : for PIO10 and PIO11. DBG_FUNC = bits [16:13] IO_CLAMP
- = bit [12], assert to freeze the IO. Also needs SYSCON:RETENTIONCTRL
- set as well. Useful in power down mode. */
- __IO uint32_t DBG_MODE : 1; /*!< (null) */
- } PIO_b[22]; /*!< BitSize */
- };
-} u_iocon_Type;
-
-
-/* ================================================================================ */
-/* ================ u_pint ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component pint It is a Pin Interrupt & Pattern matching module with APB bus interface. More details will follow. (u_pint)
- */
-
-typedef struct { /*!< u_pint Structure */
-
- union {
- __IO uint32_t ISEL; /*!< Pin Interrupt Mode register (only interrupts 0 to 3 supported
- to processor) */
-
- struct {
- __IO uint32_t PMODE_PIN0 : 1; /*!< Selects the interrupt mode for pin interrupt 0 (selected in
- PINTSEL0). 0 = Edge sensitive 1 = Level sensitive */
- __IO uint32_t PMODE_PIN1 : 1; /*!< Selects the interrupt mode for pin interrupt 1 (selected in
- PINTSEL1). 0 = Edge sensitive 1 = Level sensitive */
- __IO uint32_t PMODE_PIN2 : 1; /*!< Selects the interrupt mode for pin interrupt 2 (selected in
- PINTSEL2). 0 = Edge sensitive 1 = Level sensitive */
- __IO uint32_t PMODE_PIN3 : 1; /*!< Selects the interrupt mode for pin interrupt 3 (selected in
- PINTSEL3). 0 = Edge sensitive 1 = Level sensitive */
- __IO uint32_t PMODE_PIN4 : 1; /*!< Selects the interrupt mode for pin interrupt 4 (selected in
- PINTSEL4). [Note interrupt not supported to processor] 0 = Edge
- sensitive 1 = Level sensitive */
- __IO uint32_t PMODE_PIN5 : 1; /*!< Selects the interrupt mode for pin interrupt 5 (selected in
- PINTSEL5). [Note interrupt not supported to processor] 0 = Edge
- sensitive 1 = Level sensitive */
- __IO uint32_t PMODE_PIN6 : 1; /*!< Selects the interrupt mode for pin interrupt 6 (selected in
- PINTSEL6). [Note interrupt not supported to processor] 0 = Edge
- sensitive 1 = Level sensitive */
- __IO uint32_t PMODE_PIN7 : 1; /*!< Selects the interrupt mode for pin interrupt 7 (selected in
- PINTSEL7). [Note interrupt not supported to processor] 0 = Edge
- sensitive 1 = Level sensitive */
- } ISEL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t IENR; /*!< Pin interrupt level or rising edge interrupt enable register
- (only interrupts 0 to 3 supported to processor) */
-
- struct {
- __IO uint32_t ENRL_PIN0 : 1; /*!< Enables the rising edge or level interrupt for pin interrupt
- 0 (selected in PINTSEL0). 0 = Disable rising edge or level interrupt.
- 1 = Enable rising edge or level interrupt. */
- __IO uint32_t ENRL_PIN1 : 1; /*!< Enables the rising edge or level interrupt for pin interrupt
- 1 (selected in PINTSEL1). 0 = Disable rising edge or level interrupt.
- 1 = Enable rising edge or level interrupt. */
- __IO uint32_t ENRL_PIN2 : 1; /*!< Enables the rising edge or level interrupt for pin interrupt
- 2 (selected in PINTSEL2). 0 = Disable rising edge or level interrupt.
- 1 = Enable rising edge or level interrupt. */
- __IO uint32_t ENRL_PIN3 : 1; /*!< Enables the rising edge or level interrupt for pin interrupt
- 3 (selected in PINTSEL3). 0 = Disable rising edge or level interrupt.
- 1 = Enable rising edge or level interrupt. */
- __IO uint32_t ENRL_PIN4 : 1; /*!< Enables the rising edge or level interrupt for pin interrupt
- 4 (selected in PINTSEL4). [Note interrupt not supported to processor]
- 0 = Disable rising edge or level interrupt. 1 = Enable rising
- edge or level interrupt. */
- __IO uint32_t ENRL_PIN5 : 1; /*!< Enables the rising edge or level interrupt for pin interrupt
- 5 (selected in PINTSEL5). [Note interrupt not supported to processor]
- 0 = Disable rising edge or level interrupt. 1 = Enable rising
- edge or level interrupt. */
- __IO uint32_t ENRL_PIN6 : 1; /*!< Enables the rising edge or level interrupt for pin interrupt
- 6 (selected in PINTSEL6). [Note interrupt not supported to processor]
- 0 = Disable rising edge or level interrupt. 1 = Enable rising
- edge or level interrupt. */
- __IO uint32_t ENRL_PIN7 : 1; /*!< Enables the rising edge or level interrupt for pin interrupt
- 7 (selected in PINTSEL7). [Note interrupt not supported to processor]
- 0 = Disable rising edge or level interrupt. 1 = Enable rising
- edge or level interrupt. */
- } IENR_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t SIENR; /*!< Pin interrupt level or rising edge interrupt set register (only
- interrupts 0 to 3 supported to processor) */
-
- struct {
- __O uint32_t SETENRL_PIN0: 1; /*!< Ones written to this address set bits in the IENR, thus enabling
- interrupts. Bit 0 sets bit 0 in the IENR register. 0 = No operation.
- 1 = Enable rising edge or level interrupt. */
- __O uint32_t SETENRL_PIN1: 1; /*!< Ones written to this address set bits in the IENR, thus enabling
- interrupts. Bit 1 sets bit 1 in the IENR register. 0 = No operation.
- 1 = Enable rising edge or level interrupt. */
- __O uint32_t SETENRL_PIN2: 1; /*!< Ones written to this address set bits in the IENR, thus enabling
- interrupts. Bit 2 sets bit 2 in the IENR register. 0 = No operation.
- 1 = Enable rising edge or level interrupt. */
- __O uint32_t SETENRL_PIN3: 1; /*!< Ones written to this address set bits in the IENR, thus enabling
- interrupts. Bit 3 sets bit 3 in the IENR register. 0 = No operation.
- 1 = Enable rising edge or level interrupt. */
- __O uint32_t SETENRL_PIN4: 1; /*!< Ones written to this address set bits in the IENR, thus enabling
- interrupts. Bit 4 sets bit 4 in the IENR register. [Note interrupt
- not supported to processor] 0 = No operation. 1 = Enable rising
- edge or level interrupt. */
- __O uint32_t SETENRL_PIN5: 1; /*!< Ones written to this address set bits in the IENR, thus enabling
- interrupts. Bit 5 sets bit 5 in the IENR register. [Note interrupt
- not supported to processor] 0 = No operation. 1 = Enable rising
- edge or level interrupt. */
- __O uint32_t SETENRL_PIN6: 1; /*!< Ones written to this address set bits in the IENR, thus enabling
- interrupts. Bit 6 sets bit 6 in the IENR register. [Note interrupt
- not supported to processor] 0 = No operation. 1 = Enable rising
- edge or level interrupt. */
- __O uint32_t SETENRL_PIN7: 1; /*!< Ones written to this address set bits in the IENR, thus enabling
- interrupts. Bit 7 sets bit 7 in the IENR register. [Note interrupt
- not supported to processor] 0 = No operation. 1 = Enable rising
- edge or level interrupt. */
- } SIENR_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t CIENR; /*!< Pin interrupt level (rising edge interrupt) clear register (only
- interrupts 0 to 3 supported to processor) */
-
- struct {
- __O uint32_t CLRENRL_PIN0: 1; /*!< Ones written to this address clear bits in the IENR, thus disabling
- the interrupts. Bit 0 clears bit 0 in the IENR register. 0 =
- No operation. 1 = Disable rising edge or level interrupt. */
- __O uint32_t CLRENRL_PIN1: 1; /*!< Ones written to this address clear bits in the IENR, thus disabling
- the interrupts. Bit 1 clears bit 1 in the IENR register. 0 =
- No operation. 1 = Disable rising edge or level interrupt. */
- __O uint32_t CLRENRL_PIN2: 1; /*!< Ones written to this address clear bits in the IENR, thus disabling
- the interrupts. Bit 2 clears bit 2 in the IENR register. 0 =
- No operation. 1 = Disable rising edge or level interrupt. */
- __O uint32_t CLRENRL_PIN3: 1; /*!< Ones written to this address clear bits in the IENR, thus disabling
- the interrupts. Bit 3 clears bit 3 in the IENR register. 0 =
- No operation. 1 = Disable rising edge or level interrupt. */
- __O uint32_t CLRENRL_PIN4: 1; /*!< Ones written to this address clear bits in the IENR, thus disabling
- the interrupts. Bit 4 clears bit 4 in the IENR register. [Note
- interrupt not supported to processor] 0 = No operation. 1 =
- Disable rising edge or level interrupt. */
- __O uint32_t CLRENRL_PIN5: 1; /*!< Ones written to this address clear bits in the IENR, thus disabling
- the interrupts. Bit 5 clears bit 5 in the IENR register. [Note
- interrupt not supported to processor] 0 = No operation. 1 =
- Disable rising edge or level interrupt. */
- __O uint32_t CLRENRL_PIN6: 1; /*!< Ones written to this address clear bits in the IENR, thus disabling
- the interrupts. Bit 6 clears bit 6 in the IENR register. [Note
- interrupt not supported to processor] 0 = No operation. 1 =
- Disable rising edge or level interrupt. */
- __O uint32_t CLRENRL_PIN7: 1; /*!< Ones written to this address clear bits in the IENR, thus disabling
- the interrupts. Bit 7 clears bit 7 in the IENR register. [Note
- interrupt not supported to processor] 0 = No operation. 1 =
- Disable rising edge or level interrupt. */
- } CIENR_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t IENF; /*!< Pin interrupt active level or falling edge interrupt enable
- register */
-
- struct {
- __IO uint32_t ENAF_PIN0 : 1; /*!< Enables the falling edge or configures the active level interrupt
- for pin interrupt 0 (selected in PINTSEL0). 0 = Disable falling
- edge interrupt or set active interrupt level LOW. 1 = Enable
- falling edge interrupt enabled or set active interrupt level
- HIGH. */
- __IO uint32_t ENAF_PIN1 : 1; /*!< Enables the falling edge or configures the active level interrupt
- for pin interrupt 1 (selected in PINTSEL1). 0 = Disable falling
- edge interrupt or set active interrupt level LOW. 1 = Enable
- falling edge interrupt enabled or set active interrupt level
- HIGH. */
- __IO uint32_t ENAF_PIN2 : 1; /*!< Enables the falling edge or configures the active level interrupt
- for pin interrupt 2 (selected in PINTSEL2). 0 = Disable falling
- edge interrupt or set active interrupt level LOW. 1 = Enable
- falling edge interrupt enabled or set active interrupt level
- HIGH. */
- __IO uint32_t ENAF_PIN3 : 1; /*!< Enables the falling edge or configures the active level interrupt
- for pin interrupt 3 (selected in PINTSEL3). 0 = Disable falling
- edge interrupt or set active interrupt level LOW. 1 = Enable
- falling edge interrupt enabled or set active interrupt level
- HIGH. */
- __IO uint32_t ENAF_PIN4 : 1; /*!< Enables the falling edge or configures the active level interrupt
- for pin interrupt 4 (selected in PINTSEL4). [Note interrupt
- not supported to processor] 0 = Disable falling edge interrupt
- or set active interrupt level LOW. 1 = Enable falling edge interrupt
- enabled or set active interrupt level HIGH. */
- __IO uint32_t ENAF_PIN5 : 1; /*!< Enables the falling edge or configures the active level interrupt
- for pin interrupt 5 (selected in PINTSEL5). [Note interrupt
- not supported to processor] 0 = Disable falling edge interrupt
- or set active interrupt level LOW. 1 = Enable falling edge interrupt
- enabled or set active interrupt level HIGH. */
- __IO uint32_t ENAF_PIN6 : 1; /*!< Enables the falling edge or configures the active level interrupt
- for pin interrupt 6 (selected in PINTSEL6). [Note interrupt
- not supported to processor] 0 = Disable falling edge interrupt
- or set active interrupt level LOW. 1 = Enable falling edge interrupt
- enabled or set active interrupt level HIGH. */
- __IO uint32_t ENAF_PIN7 : 1; /*!< Enables the falling edge or configures the active level interrupt
- for pin interrupt 7 (selected in PINTSEL7). [Note interrupt
- not supported to processor] 0 = Disable falling edge interrupt
- or set active interrupt level LOW. 1 = Enable falling edge interrupt
- enabled or set active interrupt level HIGH. */
- } IENF_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t SIENF; /*!< Pin interrupt active level or falling edge interrupt set register */
-
- struct {
- __O uint32_t SETENAF_PIN0: 1; /*!< Ones written to this address set bits in the IENF, thus enabling
- interrupts. Bit 0 sets bit 0 in the IENF register. 0 = No operation.
- 1 = Select HIGH-active interrupt or enable falling edge interrupt. */
- __O uint32_t SETENAF_PIN1: 1; /*!< Ones written to this address set bits in the IENF, thus enabling
- interrupts. Bit 1 sets bit 1 in the IENF register. 0 = No operation.
- 1 = Select HIGH-active interrupt or enable falling edge interrupt. */
- __O uint32_t SETENAF_PIN2: 1; /*!< Ones written to this address set bits in the IENF, thus enabling
- interrupts. Bit 2 sets bit 2 in the IENF register. 0 = No operation.
- 1 = Select HIGH-active interrupt or enable falling edge interrupt. */
- __O uint32_t SETENAF_PIN3: 1; /*!< Ones written to this address set bits in the IENF, thus enabling
- interrupts. Bit 3 sets bit 3 in the IENF register. 0 = No operation.
- 1 = Select HIGH-active interrupt or enable falling edge interrupt. */
- __O uint32_t SETENAF_PIN4: 1; /*!< Ones written to this address set bits in the IENF, thus enabling
- interrupts. Bit 4 sets bit 4 in the IENF register. 0 = No operation.
- 1 = Select HIGH-active interrupt or enable falling edge interrupt. */
- __O uint32_t SETENAF_PIN5: 1; /*!< Ones written to this address set bits in the IENF, thus enabling
- interrupts. Bit 5 sets bit 5 in the IENF register. 0 = No operation.
- 1 = Select HIGH-active interrupt or enable falling edge interrupt. */
- __O uint32_t SETENAF_PIN6: 1; /*!< Ones written to this address set bits in the IENF, thus enabling
- interrupts. Bit 6 sets bit 6 in the IENF register. 0 = No operation.
- 1 = Select HIGH-active interrupt or enable falling edge interrupt. */
- __O uint32_t SETENAF_PIN7: 1; /*!< Ones written to this address set bits in the IENF, thus enabling
- interrupts. Bit 7 sets bit 7 in the IENF register. 0 = No operation.
- 1 = Select HIGH-active interrupt or enable falling edge interrupt. */
- } SIENF_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t CIENF; /*!< Pin interrupt active level or falling edge interrupt clear register */
-
- struct {
- __O uint32_t CLRENAF_PIN0: 1; /*!< Ones written to this address clears bits in the IENF, thus disabling
- interrupts. Bit 0 clears bit 0 in the IENF register. 0 = No
- operation. 1 = LOW-active interrupt selected or falling edge
- interrupt disabled. */
- __O uint32_t CLRENAF_PIN1: 1; /*!< Ones written to this address clears bits in the IENF, thus disabling
- interrupts. Bit 1 clears bit 1 in the IENF register. 0 = No
- operation. 1 = LOW-active interrupt selected or falling edge
- interrupt disabled. */
- __O uint32_t CLRENAF_PIN2: 1; /*!< Ones written to this address clears bits in the IENF, thus disabling
- interrupts. Bit 2 clears bit 2 in the IENF register. 0 = No
- operation. 1 = LOW-active interrupt selected or falling edge
- interrupt disabled. */
- __O uint32_t CLRENAF_PIN3: 1; /*!< Ones written to this address clears bits in the IENF, thus disabling
- interrupts. Bit 3 clears bit 3 in the IENF register. 0 = No
- operation. 1 = LOW-active interrupt selected or falling edge
- interrupt disabled. */
- __O uint32_t CLRENAF_PIN4: 1; /*!< Ones written to this address clears bits in the IENF, thus disabling
- interrupts. Bit 4 clears bit 4 in the IENF register. 0 = No
- operation. 1 = LOW-active interrupt selected or falling edge
- interrupt disabled. */
- __O uint32_t CLRENAF_PIN5: 1; /*!< Ones written to this address clears bits in the IENF, thus disabling
- interrupts. Bit 5 clears bit 5 in the IENF register. 0 = No
- operation. 1 = LOW-active interrupt selected or falling edge
- interrupt disabled. */
- __O uint32_t CLRENAF_PIN6: 1; /*!< Ones written to this address clears bits in the IENF, thus disabling
- interrupts. Bit 6 clears bit 6 in the IENF register. 0 = No
- operation. 1 = LOW-active interrupt selected or falling edge
- interrupt disabled. */
- __O uint32_t CLRENAF_PIN7: 1; /*!< Ones written to this address clears bits in the IENF, thus disabling
- interrupts. Bit 7 clears bit 7 in the IENF register. 0 = No
- operation. 1 = LOW-active interrupt selected or falling edge
- interrupt disabled. */
- } CIENF_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t RISE; /*!< Pin interrupt rising edge register */
-
- struct {
- __IO uint32_t RDET_PIN0 : 1; /*!< Rising edge detect. Bit 0 detects the rising edge of the pin
- selected in PINTSEL0. Read 0: No rising edge has been detected
- on this pin since Reset or the last time a one was written to
- this bit. Write 0: no operation. Read 1: a rising edge has been
- detected since Reset or the last time a one was written to this
- bit. Write 1: clear rising edge detection for this pin. */
- __IO uint32_t RDET_PIN1 : 1; /*!< Rising edge detect. Bit 1 detects the rising edge of the pin
- selected in PINTSEL1. Read 0: No rising edge has been detected
- on this pin since Reset or the last time a one was written to
- this bit. Write 0: no operation. Read 1: a rising edge has been
- detected since Reset or the last time a one was written to this
- bit. Write 1: clear rising edge detection for this pin. */
- __IO uint32_t RDET_PIN2 : 1; /*!< Rising edge detect. Bit 2 detects the rising edge of the pin
- selected in PINTSEL2. Read 0: No rising edge has been detected
- on this pin since Reset or the last time a one was written to
- this bit. Write 0: no operation. Read 1: a rising edge has been
- detected since Reset or the last time a one was written to this
- bit. Write 1: clear rising edge detection for this pin. */
- __IO uint32_t RDET_PIN3 : 1; /*!< Rising edge detect. Bit 3 detects the rising edge of the pin
- selected in PINTSEL3. Read 0: No rising edge has been detected
- on this pin since Reset or the last time a one was written to
- this bit. Write 0: no operation. Read 1: a rising edge has been
- detected since Reset or the last time a one was written to this
- bit. Write 1: clear rising edge detection for this pin. */
- __IO uint32_t RDET_PIN4 : 1; /*!< Rising edge detect. Bit 4 detects the rising edge of the pin
- selected in PINTSEL4. Read 0: No rising edge has been detected
- on this pin since Reset or the last time a one was written to
- this bit. Write 0: no operation. Read 1: a rising edge has been
- detected since Reset or the last time a one was written to this
- bit. Write 1: clear rising edge detection for this pin. */
- __IO uint32_t RDET_PIN5 : 1; /*!< Rising edge detect. Bit 5 detects the rising edge of the pin
- selected in PINTSEL5. Read 0: No rising edge has been detected
- on this pin since Reset or the last time a one was written to
- this bit. Write 0: no operation. Read 1: a rising edge has been
- detected since Reset or the last time a one was written to this
- bit. Write 1: clear rising edge detection for this pin. */
- __IO uint32_t RDET_PIN6 : 1; /*!< Rising edge detect. Bit 6 detects the rising edge of the pin
- selected in PINTSEL6. Read 0: No rising edge has been detected
- on this pin since Reset or the last time a one was written to
- this bit. Write 0: no operation. Read 1: a rising edge has been
- detected since Reset or the last time a one was written to this
- bit. Write 1: clear rising edge detection for this pin. */
- __IO uint32_t RDET_PIN7 : 1; /*!< Rising edge detect. Bit 7 detects the rising edge of the pin
- selected in PINTSEL7. Read 0: No rising edge has been detected
- on this pin since Reset or the last time a one was written to
- this bit. Write 0: no operation. Read 1: a rising edge has been
- detected since Reset or the last time a one was written to this
- bit. Write 1: clear rising edge detection for this pin. */
- } RISE_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t FALL; /*!< Pin interrupt falling edge register */
-
- struct {
- __IO uint32_t FDET_PIN0 : 1; /*!< Falling edge detect. Bit 0 detects the falling edge of the pin
- selected in PINTSEL0. Read 0: No falling edge has been detected
- on this pin since Reset or the last time a one was written to
- this bit. Write 0: no operation. Read 1: a falling edge has
- been detected since Reset or the last time a one was written
- to this bit. Write 1: clear falling edge detection for this
- pin. */
- __IO uint32_t FDET_PIN1 : 1; /*!< Falling edge detect. Bit 1 detects the falling edge of the pin
- selected in PINTSEL1. Read 0: No falling edge has been detected
- on this pin since Reset or the last time a one was written to
- this bit. Write 0: no operation. Read 1: a falling edge has
- been detected since Reset or the last time a one was written
- to this bit. Write 1: clear falling edge detection for this
- pin. */
- __IO uint32_t FDET_PIN2 : 1; /*!< Falling edge detect. Bit 2 detects the falling edge of the pin
- selected in PINTSEL2. Read 0: No falling edge has been detected
- on this pin since Reset or the last time a one was written to
- this bit. Write 0: no operation. Read 1: a falling edge has
- been detected since Reset or the last time a one was written
- to this bit. Write 1: clear falling edge detection for this
- pin. */
- __IO uint32_t FDET_PIN3 : 1; /*!< Falling edge detect. Bit 3 detects the falling edge of the pin
- selected in PINTSEL3. Read 0: No falling edge has been detected
- on this pin since Reset or the last time a one was written to
- this bit. Write 0: no operation. Read 1: a falling edge has
- been detected since Reset or the last time a one was written
- to this bit. Write 1: clear falling edge detection for this
- pin. */
- __IO uint32_t FDET_PIN4 : 1; /*!< Falling edge detect. Bit 4 detects the falling edge of the pin
- selected in PINTSEL4. Read 0: No falling edge has been detected
- on this pin since Reset or the last time a one was written to
- this bit. Write 0: no operation. Read 1: a falling edge has
- been detected since Reset or the last time a one was written
- to this bit. Write 1: clear falling edge detection for this
- pin. */
- __IO uint32_t FDET_PIN5 : 1; /*!< Falling edge detect. Bit 5 detects the falling edge of the pin
- selected in PINTSEL5. Read 0: No falling edge has been detected
- on this pin since Reset or the last time a one was written to
- this bit. Write 0: no operation. Read 1: a falling edge has
- been detected since Reset or the last time a one was written
- to this bit. Write 1: clear falling edge detection for this
- pin. */
- __IO uint32_t FDET_PIN6 : 1; /*!< Falling edge detect. Bit 6 detects the falling edge of the pin
- selected in PINTSEL6. Read 0: No falling edge has been detected
- on this pin since Reset or the last time a one was written to
- this bit. Write 0: no operation. Read 1: a falling edge has
- been detected since Reset or the last time a one was written
- to this bit. Write 1: clear falling edge detection for this
- pin. */
- __IO uint32_t FDET_PIN7 : 1; /*!< Falling edge detect. Bit 7 detects the falling edge of the pin
- selected in PINTSEL7. Read 0: No falling edge has been detected
- on this pin since Reset or the last time a one was written to
- this bit. Write 0: no operation. Read 1: a falling edge has
- been detected since Reset or the last time a one was written
- to this bit. Write 1: clear falling edge detection for this
- pin. */
- } FALL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t IST; /*!< Pin interrupt status register */
-
- struct {
- __IO uint32_t PSTAT_PIN0 : 1; /*!< Pin interrupt status. Bit 0 returns the status, clears the edge
- interrupt, or inverts the active level of the pin 0 (selected
- in PINTSEL0). Read 0: interrupt is not being requested for this
- interrupt pin. Write 0: no operation. Read 1: interrupt is being
- requested for this interrupt pin. Write 1 (edge-sensitive):
- clear rising- and falling-edge detection for this pin. Write
- 1 (level-sensitive): switch the active level for this pin (in
- the IENF register). */
- __IO uint32_t PSTAT_PIN1 : 1; /*!< Pin interrupt status. Bit 1 returns the status, clears the edge
- interrupt, or inverts the active level of the pin 1 (selected
- in PINTSEL0). Read 0: interrupt is not being requested for this
- interrupt pin. Write 0: no operation. Read 1: interrupt is being
- requested for this interrupt pin. Write 1 (edge-sensitive):
- clear rising- and falling-edge detection for this pin. Write
- 1 (level-sensitive): switch the active level for this pin (in
- the IENF register). */
- __IO uint32_t PSTAT_PIN2 : 1; /*!< Pin interrupt status. Bit 2 returns the status, clears the edge
- interrupt, or inverts the active level of the pin 2 (selected
- in PINTSEL2). Read 0: interrupt is not being requested for this
- interrupt pin. Write 0: no operation. Read 1: interrupt is being
- requested for this interrupt pin. Write 1 (edge-sensitive):
- clear rising- and falling-edge detection for this pin. Write
- 1 (level-sensitive): switch the active level for this pin (in
- the IENF register). */
- __IO uint32_t PSTAT_PIN3 : 1; /*!< Pin interrupt status. Bit 3 returns the status, clears the edge
- interrupt, or inverts the active level of the pin 3 (selected
- in PINTSEL3). Read 0: interrupt is not being requested for this
- interrupt pin. Write 0: no operation. Read 1: interrupt is being
- requested for this interrupt pin. Write 1 (edge-sensitive):
- clear rising- and falling-edge detection for this pin. Write
- 1 (level-sensitive): switch the active level for this pin (in
- the IENF register). */
- __IO uint32_t PSTAT_PIN4 : 1; /*!< Pin interrupt status. Bit 4 returns the status, clears the edge
- interrupt, or inverts the active level of the pin 4 (selected
- in PINTSEL4). Read 0: interrupt is not being requested for this
- interrupt pin. Write 0: no operation. Read 1: interrupt is being
- requested for this interrupt pin. Write 1 (edge-sensitive):
- clear rising- and falling-edge detection for this pin. Write
- 1 (level-sensitive): switch the active level for this pin (in
- the IENF register). */
- __IO uint32_t PSTAT_PIN5 : 1; /*!< Pin interrupt status. Bit 5 returns the status, clears the edge
- interrupt, or inverts the active level of the pin 5 (selected
- in PINTSEL5). Read 0: interrupt is not being requested for this
- interrupt pin. Write 0: no operation. Read 1: interrupt is being
- requested for this interrupt pin. Write 1 (edge-sensitive):
- clear rising- and falling-edge detection for this pin. Write
- 1 (level-sensitive): switch the active level for this pin (in
- the IENF register). */
- __IO uint32_t PSTAT_PIN6 : 1; /*!< Pin interrupt status. Bit 6 returns the status, clears the edge
- interrupt, or inverts the active level of the pin 6 (selected
- in PINTSEL6). Read 0: interrupt is not being requested for this
- interrupt pin. Write 0: no operation. Read 1: interrupt is being
- requested for this interrupt pin. Write 1 (edge-sensitive):
- clear rising- and falling-edge detection for this pin. Write
- 1 (level-sensitive): switch the active level for this pin (in
- the IENF register). */
- __IO uint32_t PSTAT_PIN7 : 1; /*!< Pin interrupt status. Bit 7 returns the status, clears the edge
- interrupt, or inverts the active level of the pin 7 (selected
- in PINTSEL7). Read 0: interrupt is not being requested for this
- interrupt pin. Write 0: no operation. Read 1: interrupt is being
- requested for this interrupt pin. Write 1 (edge-sensitive):
- clear rising- and falling-edge detection for this pin. Write
- 1 (level-sensitive): switch the active level for this pin (in
- the IENF register). */
- } IST_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PMCTRL; /*!< Pattern match interrupt control register */
-
- struct {
- __IO uint32_t SEL_PMATCH : 1; /*!< Specifies whether the 8 pin interrupts are controlled by the
- pin interrupt function or by the pattern match function. 0 Pin
- interrupt. Interrupts are driven in response to the standard
- pin interrupt function. 1 Pattern match. Interrupts are driven
- in response to pattern matches. */
- __IO uint32_t ENA_RXEV : 1; /*!< Enables the RXEV output to the CPU and/or to a GPIO output when
- the specified boolean expression evaluates to true. 0 Disabled.
- RXEV output to the CPU is disabled. 1 Enabled. RXEV output to
- the CPU is enabled. */
- uint32_t : 22;
- __IO uint32_t PMAT : 8; /*!< This field displays the current state of pattern matches. A
- 1 in any bit of this field indicates that the corresponding
- product term is matched by the current state of the appropriate
- inputs. */
- } PMCTRL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PMSRC; /*!< Pattern match interrupt bit-slice source register */
-
- struct {
- uint32_t : 8;
- __IO uint32_t SRC0 : 3; /*!< Selects the input source for bit slice 0 0x0 Input 0. Selects
- the pin selected in the PINTSEL0 register as the source to bit
- slice 0. 0x1 Input 1. Selects the pin selected in the PINTSEL1
- register as the source to bit slice 0. 0x2 Input 2. Selects
- the pin selected in the PINTSEL2 register as the source to bit
- slice 0. 0x3 Input 3. Selects the pin selected in the PINTSEL3
- register as the source to bit slice 0. 0x4 Input 4. Selects
- the pin selected in the PINTSEL4 register as the source to bit
- slice 0. 0x5 I */
- __IO uint32_t SRC1 : 3; /*!< Selects the input source for bit slice 1 0x0 Input 0. Selects
- the pin selected in the PINTSEL0 register as the source to bit
- slice 1. 0x1 Input 1. Selects the pin selected in the PINTSEL1
- register as the source to bit slice 1. 0x2 Input 2. Selects
- the pin selected in the PINTSEL2 register as the source to bit
- slice 1. 0x3 Input 3. Selects the pin selected in the PINTSEL3
- register as the source to bit slice 1. 0x4 Input 4. Selects
- the pin selected in the PINTSEL4 register as the source to bit
- slice 1. 0x5 I */
- __IO uint32_t SRC2 : 3; /*!< Selects the input source for bit slice 2 0x0 Input 0. Selects
- the pin selected in the PINTSEL0 register as the source to bit
- slice 2. 0x1 Input 1. Selects the pin selected in the PINTSEL1
- register as the source to bit slice 2. 0x2 Input 2. Selects
- the pin selected in the PINTSEL2 register as the source to bit
- slice 2. 0x3 Input 3. Selects the pin selected in the PINTSEL3
- register as the source to bit slice 2. 0x4 Input 4. Selects
- the pin selected in the PINTSEL4 register as the source to bit
- slice 2. 0x5 I */
- __IO uint32_t SRC3 : 3; /*!< Selects the input source for bit slice 3 0x0 Input 0. Selects
- the pin selected in the PINTSEL0 register as the source to bit
- slice 3. 0x1 Input 1. Selects the pin selected in the PINTSEL1
- register as the source to bit slice 3. 0x2 Input 2. Selects
- the pin selected in the PINTSEL2 register as the source to bit
- slice 3. 0x3 Input 3. Selects the pin selected in the PINTSEL3
- register as the source to bit slice 3. 0x4 Input 4. Selects
- the pin selected in the PINTSEL4 register as the source to bit
- slice 3. 0x5 I */
- __IO uint32_t SRC4 : 3; /*!< Selects the input source for bit slice 4 0x0 Input 0. Selects
- the pin selected in the PINTSEL0 register as the source to bit
- slice 4. 0x1 Input 1. Selects the pin selected in the PINTSEL1
- register as the source to bit slice 4. 0x2 Input 2. Selects
- the pin selected in the PINTSEL2 register as the source to bit
- slice 4. 0x3 Input 3. Selects the pin selected in the PINTSEL3
- register as the source to bit slice 4. 0x4 Input 4. Selects
- the pin selected in the PINTSEL4 register as the source to bit
- slice 4. 0x5 I */
- __IO uint32_t SRC5 : 3; /*!< Selects the input source for bit slice 5 0x0 Input 0. Selects
- the pin selected in the PINTSEL0 register as the source to bit
- slice 5. 0x1 Input 1. Selects the pin selected in the PINTSEL1
- register as the source to bit slice 5. 0x2 Input 2. Selects
- the pin selected in the PINTSEL2 register as the source to bit
- slice 5. 0x3 Input 3. Selects the pin selected in the PINTSEL3
- register as the source to bit slice 5. 0x4 Input 4. Selects
- the pin selected in the PINTSEL4 register as the source to bit
- slice 5. 0x5 I */
- __IO uint32_t SRC6 : 3; /*!< Selects the input source for bit slice 6 0x0 Input 0. Selects
- the pin selected in the PINTSEL0 register as the source to bit
- slice 6. 0x1 Input 1. Selects the pin selected in the PINTSEL1
- register as the source to bit slice 6. 0x2 Input 2. Selects
- the pin selected in the PINTSEL2 register as the source to bit
- slice 6. 0x3 Input 3. Selects the pin selected in the PINTSEL3
- register as the source to bit slice 6. 0x4 Input 4. Selects
- the pin selected in the PINTSEL4 register as the source to bit
- slice 6. 0x5 I */
- __IO uint32_t SRC7 : 3; /*!< Selects the input source for bit slice 7 0x0 Input 0. Selects
- the pin selected in the PINTSEL0 register as the source to bit
- slice 7. 0x1 Input 1. Selects the pin selected in the PINTSEL1
- register as the source to bit slice 7. 0x2 Input 2. Selects
- the pin selected in the PINTSEL2 register as the source to bit
- slice 7. 0x3 Input 3. Selects the pin selected in the PINTSEL3
- register as the source to bit slice 7. 0x4 Input 4. Selects
- the pin selected in the PINTSEL4 register as the source to bit
- slice 7. 0x5 I */
- } PMSRC_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PMCFG; /*!< Pattern match interrupt bit slice configuration register */
-
- struct {
- __IO uint32_t PROD_ENDPTS0: 1; /*!< Determines whether slice 0 is an endpoint. 0 No effect. Slice
- 0 is not an endpoint. 1 endpoint. Slice 0 is the endpoint of
- a product term (minterm). Pin interrupt 0 in the NVIC is raised
- if the minterm evaluates as true. */
- __IO uint32_t PROD_ENDPTS1: 1; /*!< Determines whether slice 1 is an endpoint. 0 No effect. Slice
- 1 is not an endpoint. 1 endpoint. Slice 1 is the endpoint of
- a product term (minterm). Pin interrupt 1 in the NVIC is raised
- if the minterm evaluates as true. */
- __IO uint32_t PROD_ENDPTS2: 1; /*!< Determines whether slice 2 is an endpoint. 0 No effect. Slice
- 2 is not an endpoint. 1 endpoint. Slice 2 is the endpoint of
- a product term (minterm). Pin interrupt 2 in the NVIC is raised
- if the minterm evaluates as true. */
- __IO uint32_t PROD_ENDPTS3: 1; /*!< Determines whether slice 3 is an endpoint. 0 No effect. Slice
- 3 is not an endpoint. 1 endpoint. Slice 3 is the endpoint of
- a product term (minterm). Pin interrupt 3 in the NVIC is raised
- if the minterm evaluates as true. */
- __IO uint32_t PROD_ENDPTS4: 1; /*!< Determines whether slice 4 is an endpoint. 0 No effect. Slice
- 4 is not an endpoint. 1 endpoint. Slice 4 is the endpoint of
- a product term (minterm). Pin interrupt 4 in the NVIC is raised
- if the minterm evaluates as true. */
- __IO uint32_t PROD_ENDPTS5: 1; /*!< Determines whether slice 5 is an endpoint. 0 No effect. Slice
- 5 is not an endpoint. 1 endpoint. Slice 5 is the endpoint of
- a product term (minterm). Pin interrupt 5 in the NVIC is raised
- if the minterm evaluates as true. */
- __IO uint32_t PROD_ENDPTS6: 1; /*!< Determines whether slice 6 is an endpoint. 0 No effect. Slice
- 6 is not an endpoint. 1 endpoint. Slice 6 is the endpoint of
- a product term (minterm). Pin interrupt 6 in the NVIC is raised
- if the minterm evaluates as true. */
- uint32_t : 1;
- __IO uint32_t CFG0 : 3; /*!< Specifies the match contribution condition for bit slice 0.
- 0x0 Constant HIGH. This bit slice always contributes to a product
- term match. 0x1 Sticky rising edge. Match occurs if a rising
- edge on the specified input has occurred since the last time
- the edge detection for this bit slice was cleared. This bit
- is only cleared when the PMCFG or the PMSRC registers are written
- to. 0x2 Sticky falling edge. Match occurs if a falling edge
- on the specified input has occurred since the last time the
- edge detection fo */
- __IO uint32_t CFG1 : 3; /*!< Specifies the match contribution condition for bit slice 1.
- 0x0 Constant HIGH. This bit slice always contributes to a product
- term match. 0x1 Sticky rising edge. Match occurs if a rising
- edge on the specified input has occurred since the last time
- the edge detection for this bit slice was cleared. This bit
- is only cleared when the PMCFG or the PMSRC registers are written
- to. 0x2 Sticky falling edge. Match occurs if a falling edge
- on the specified input has occurred since the last time the
- edge detection fo */
- __IO uint32_t CFG2 : 3; /*!< Specifies the match contribution condition for bit slice 2.
- 0x0 Constant HIGH. This bit slice always contributes to a product
- term match. 0x1 Sticky rising edge. Match occurs if a rising
- edge on the specified input has occurred since the last time
- the edge detection for this bit slice was cleared. This bit
- is only cleared when the PMCFG or the PMSRC registers are written
- to. 0x2 Sticky falling edge. Match occurs if a falling edge
- on the specified input has occurred since the last time the
- edge detection fo */
- __IO uint32_t CFG3 : 3; /*!< Specifies the match contribution condition for bit slice 3.
- 0x0 Constant HIGH. This bit slice always contributes to a product
- term match. 0x1 Sticky rising edge. Match occurs if a rising
- edge on the specified input has occurred since the last time
- the edge detection for this bit slice was cleared. This bit
- is only cleared when the PMCFG or the PMSRC registers are written
- to. 0x2 Sticky falling edge. Match occurs if a falling edge
- on the specified input has occurred since the last time the
- edge detection fo */
- __IO uint32_t CFG4 : 3; /*!< Specifies the match contribution condition for bit slice 4.
- 0x0 Constant HIGH. This bit slice always contributes to a product
- term match. 0x1 Sticky rising edge. Match occurs if a rising
- edge on the specified input has occurred since the last time
- the edge detection for this bit slice was cleared. This bit
- is only cleared when the PMCFG or the PMSRC registers are written
- to. 0x2 Sticky falling edge. Match occurs if a falling edge
- on the specified input has occurred since the last time the
- edge detection fo */
- __IO uint32_t CFG5 : 3; /*!< Specifies the match contribution condition for bit slice 5.
- 0x0 Constant HIGH. This bit slice always contributes to a product
- term match. 0x1 Sticky rising edge. Match occurs if a rising
- edge on the specified input has occurred since the last time
- the edge detection for this bit slice was cleared. This bit
- is only cleared when the PMCFG or the PMSRC registers are written
- to. 0x2 Sticky falling edge. Match occurs if a falling edge
- on the specified input has occurred since the last time the
- edge detection fo */
- __IO uint32_t CFG6 : 3; /*!< Specifies the match contribution condition for bit slice 6.
- 0x0 Constant HIGH. This bit slice always contributes to a product
- term match. 0x1 Sticky rising edge. Match occurs if a rising
- edge on the specified input has occurred since the last time
- the edge detection for this bit slice was cleared. This bit
- is only cleared when the PMCFG or the PMSRC registers are written
- to. 0x2 Sticky falling edge. Match occurs if a falling edge
- on the specified input has occurred since the last time the
- edge detection fo */
- __IO uint32_t CFG7 : 3; /*!< Specifies the match contribution condition for bit slice 7.
- 0x0 Constant HIGH. This bit slice always contributes to a product
- term match. 0x1 Sticky rising edge. Match occurs if a rising
- edge on the specified input has occurred since the last time
- the edge detection for this bit slice was cleared. This bit
- is only cleared when the PMCFG or the PMSRC registers are written
- to. 0x2 Sticky falling edge. Match occurs if a falling edge
- on the specified input has occurred since the last time the
- edge detection fo */
- } PMCFG_b; /*!< BitSize */
- };
-} u_pint_Type;
-
-
-/* ================================================================================ */
-/* ================ u_gint ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component gint It is an Global Interrupt with APB bus interface. More details will follow. (u_gint)
- */
-
-typedef struct { /*!< u_gint Structure */
-
- union {
- __IO uint32_t CTRL; /*!< GPIO Grouped interrupt control register */
-
- struct {
- __IO uint32_t INT : 1; /*!< Group interrupt status. This bit is cleared by writing a one
- to it. Writing zero has no effect. */
- __IO uint32_t COMB : 1; /*!< Combine enabled inputs for group interrupt. 0 Or, OR functionality:
- A grouped interrupt is generated when any one of the enabled
- inputs is active (based on its programmed polarity) 1 And, AND
- functionality: An interrupt is generated when all enabled bits
- are active (based on their programmed polarity) */
- __IO uint32_t TRIG : 1; /*!< Group interrupt trigger. 0 Edge Triggered. 1 Level Triggered. */
- } CTRL_b; /*!< BitSize */
- };
- __I uint32_t RESERVED0[7];
-
- union {
- __IO uint32_t PORT_POL0; /*!< GPIO Grouped Interrupt polrity register */
-
- struct {
- __IO uint32_t POL_PIO0 : 1; /*!< Configure pin polarity of pin PIO0. 0 = the pin is active low.
- If the level on this pin is LOW, the pin contributes to the
- group interrupt. 1 = the pin is active HIGH. If the level on
- this pin is HIGH, the pin contributes to the group interrupt. */
- __IO uint32_t POL_PIO1 : 1; /*!< Configure pin polarity of pin PIO1. 0 = the pin is active low.
- If the level on this pin is LOW, the pin contributes to the
- group interrupt. 1 = the pin is active HIGH. If the level on
- this pin is HIGH, the pin contributes to the group interrupt. */
- __IO uint32_t POL_PIO2 : 1; /*!< Configure pin polarity of pin PIO2. 0 = the pin is active low.
- If the level on this pin is LOW, the pin contributes to the
- group interrupt. 1 = the pin is active HIGH. If the level on
- this pin is HIGH, the pin contributes to the group interrupt. */
- __IO uint32_t POL_PIO3 : 1; /*!< Configure pin polarity of pin PIO3. 0 = the pin is active low.
- If the level on this pin is LOW, the pin contributes to the
- group interrupt. 1 = the pin is active HIGH. If the level on
- this pin is HIGH, the pin contributes to the group interrupt. */
- __IO uint32_t POL_PIO4 : 1; /*!< Configure pin polarity of pin PIO4. 0 = the pin is active low.
- If the level on this pin is LOW, the pin contributes to the
- group interrupt. 1 = the pin is active HIGH. If the level on
- this pin is HIGH, the pin contributes to the group interrupt. */
- __IO uint32_t POL_PIO5 : 1; /*!< Configure pin polarity of pin PIO5. 0 = the pin is active low.
- If the level on this pin is LOW, the pin contributes to the
- group interrupt. 1 = the pin is active HIGH. If the level on
- this pin is HIGH, the pin contributes to the group interrupt. */
- __IO uint32_t POL_PIO6 : 1; /*!< Configure pin polarity of pin PIO6. 0 = the pin is active low.
- If the level on this pin is LOW, the pin contributes to the
- group interrupt. 1 = the pin is active HIGH. If the level on
- this pin is HIGH, the pin contributes to the group interrupt. */
- __IO uint32_t POL_PIO7 : 1; /*!< Configure pin polarity of pin PIO7. 0 = the pin is active low.
- If the level on this pin is LOW, the pin contributes to the
- group interrupt. 1 = the pin is active HIGH. If the level on
- this pin is HIGH, the pin contributes to the group interrupt. */
- __IO uint32_t POL_PIO8 : 1; /*!< Configure pin polarity of pin PIO8. 0 = the pin is active low.
- If the level on this pin is LOW, the pin contributes to the
- group interrupt. 1 = the pin is active HIGH. If the level on
- this pin is HIGH, the pin contributes to the group interrupt. */
- __IO uint32_t POL_PIO9 : 1; /*!< Configure pin polarity of pin PIO9. 0 = the pin is active low.
- If the level on this pin is LOW, the pin contributes to the
- group interrupt. 1 = the pin is active HIGH. If the level on
- this pin is HIGH, the pin contributes to the group interrupt. */
- __IO uint32_t POL_PIO10 : 1; /*!< Configure pin polarity of pin PIO10. 0 = the pin is active low.
- If the level on this pin is LOW, the pin contributes to the
- group interrupt. 1 = the pin is active HIGH. If the level on
- this pin is HIGH, the pin contributes to the group interrupt. */
- __IO uint32_t POL_PIO11 : 1; /*!< Configure pin polarity of pin PIO11. 0 = the pin is active low.
- If the level on this pin is LOW, the pin contributes to the
- group interrupt. 1 = the pin is active HIGH. If the level on
- this pin is HIGH, the pin contributes to the group interrupt. */
- __IO uint32_t POL_PIO12 : 1; /*!< Configure pin polarity of pin PIO12. 0 = the pin is active low.
- If the level on this pin is LOW, the pin contributes to the
- group interrupt. 1 = the pin is active HIGH. If the level on
- this pin is HIGH, the pin contributes to the group interrupt. */
- __IO uint32_t POL_PIO13 : 1; /*!< Configure pin polarity of pin PIO13. 0 = the pin is active low.
- If the level on this pin is LOW, the pin contributes to the
- group interrupt. 1 = the pin is active HIGH. If the level on
- this pin is HIGH, the pin contributes to the group interrupt. */
- __IO uint32_t POL_PIO14 : 1; /*!< Configure pin polarity of pin PIO14. 0 = the pin is active low.
- If the level on this pin is LOW, the pin contributes to the
- group interrupt. 1 = the pin is active HIGH. If the level on
- this pin is HIGH, the pin contributes to the group interrupt. */
- __IO uint32_t POL_PIO15 : 1; /*!< Configure pin polarity of pin PIO15. 0 = the pin is active low.
- If the level on this pin is LOW, the pin contributes to the
- group interrupt. 1 = the pin is active HIGH. If the level on
- this pin is HIGH, the pin contributes to the group interrupt. */
- __IO uint32_t POL_PIO16 : 1; /*!< Configure pin polarity of pin PIO16. 0 = the pin is active low.
- If the level on this pin is LOW, the pin contributes to the
- group interrupt. 1 = the pin is active HIGH. If the level on
- this pin is HIGH, the pin contributes to the group interrupt. */
- __IO uint32_t POL_PIO17 : 1; /*!< Configure pin polarity of pin PIO17. 0 = the pin is active low.
- If the level on this pin is LOW, the pin contributes to the
- group interrupt. 1 = the pin is active HIGH. If the level on
- this pin is HIGH, the pin contributes to the group interrupt. */
- __IO uint32_t POL_PIO18 : 1; /*!< Configure pin polarity of pin PIO18. 0 = the pin is active low.
- If the level on this pin is LOW, the pin contributes to the
- group interrupt. 1 = the pin is active HIGH. If the level on
- this pin is HIGH, the pin contributes to the group interrupt. */
- __IO uint32_t POL_PIO19 : 1; /*!< Configure pin polarity of pin PIO19. 0 = the pin is active low.
- If the level on this pin is LOW, the pin contributes to the
- group interrupt. 1 = the pin is active HIGH. If the level on
- this pin is HIGH, the pin contributes to the group interrupt. */
- __IO uint32_t POL_PIO20 : 1; /*!< Configure pin polarity of pin PIO20. 0 = the pin is active low.
- If the level on this pin is LOW, the pin contributes to the
- group interrupt. 1 = the pin is active HIGH. If the level on
- this pin is HIGH, the pin contributes to the group interrupt. */
- __IO uint32_t POL_PIO21 : 1; /*!< Configure pin polarity of pin PIO21. 0 = the pin is active low.
- If the level on this pin is LOW, the pin contributes to the
- group interrupt. 1 = the pin is active HIGH. If the level on
- this pin is HIGH, the pin contributes to the group interrupt. */
- } PORT_POL0_b; /*!< BitSize */
- };
- __I uint32_t RESERVED1[7];
-
- union {
- __IO uint32_t PORT_ENA0; /*!< GPIO Grouped Interrupt port enable register */
-
- struct {
- __IO uint32_t ENA_PIO0 : 1; /*!< Enable pin PIO0 for group interrupt. When set this pin contributes
- to the grouped interupt function. */
- __IO uint32_t ENA_PIO1 : 1; /*!< Enable pin PIO1 for group interrupt. When set this pin contributes
- to the grouped interupt function. */
- __IO uint32_t ENA_PIO2 : 1; /*!< Enable pin PIO2 for group interrupt. When set this pin contributes
- to the grouped interupt function. */
- __IO uint32_t ENA_PIO3 : 1; /*!< Enable pin PIO3 for group interrupt. When set this pin contributes
- to the grouped interupt function. */
- __IO uint32_t ENA_PIO4 : 1; /*!< Enable pin PIO4 for group interrupt. When set this pin contributes
- to the grouped interupt function. */
- __IO uint32_t ENA_PIO5 : 1; /*!< Enable pin PIO5 for group interrupt. When set this pin contributes
- to the grouped interupt function. */
- __IO uint32_t ENA_PIO6 : 1; /*!< Enable pin PIO6 for group interrupt. When set this pin contributes
- to the grouped interupt function. */
- __IO uint32_t ENA_PIO7 : 1; /*!< Enable pin PIO7 for group interrupt. When set this pin contributes
- to the grouped interupt function. */
- __IO uint32_t ENA_PIO8 : 1; /*!< Enable pin PIO8 for group interrupt. When set this pin contributes
- to the grouped interupt function. */
- __IO uint32_t ENA_PIO9 : 1; /*!< Enable pin PIO9 for group interrupt. When set this pin contributes
- to the grouped interupt function. */
- __IO uint32_t ENA_PIO10 : 1; /*!< Enable pin PIO10 for group interrupt. When set this pin contributes
- to the grouped interupt function. */
- __IO uint32_t ENA_PIO11 : 1; /*!< Enable pin PIO11 for group interrupt. When set this pin contributes
- to the grouped interupt function. */
- __IO uint32_t ENA_PIO12 : 1; /*!< Enable pin PIO12 for group interrupt. When set this pin contributes
- to the grouped interupt function. */
- __IO uint32_t ENA_PIO13 : 1; /*!< Enable pin PIO13 for group interrupt. When set this pin contributes
- to the grouped interupt function. */
- __IO uint32_t ENA_PIO14 : 1; /*!< Enable pin PIO14 for group interrupt. When set this pin contributes
- to the grouped interupt function. */
- __IO uint32_t ENA_PIO15 : 1; /*!< Enable pin PIO15 for group interrupt. When set this pin contributes
- to the grouped interupt function. */
- __IO uint32_t ENA_PIO16 : 1; /*!< Enable pin PIO16 for group interrupt. When set this pin contributes
- to the grouped interupt function. */
- __IO uint32_t ENA_PIO17 : 1; /*!< Enable pin PIO17 for group interrupt. When set this pin contributes
- to the grouped interupt function. */
- __IO uint32_t ENA_PIO18 : 1; /*!< Enable pin PIO18 for group interrupt. When set this pin contributes
- to the grouped interupt function. */
- __IO uint32_t ENA_PIO19 : 1; /*!< Enable pin PIO19 for group interrupt. When set this pin contributes
- to the grouped interupt function. */
- __IO uint32_t ENA_PIO20 : 1; /*!< Enable pin PIO20 for group interrupt. When set this pin contributes
- to the grouped interupt function. */
- __IO uint32_t ENA_PIO21 : 1; /*!< Enable pin PIO21 for group interrupt. When set this pin contributes
- to the grouped interupt function. */
- } PORT_ENA0_b; /*!< BitSize */
- };
-} u_gint_Type;
-
-
-/* ================================================================================ */
-/* ================ u_pmc ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component pmc. It is the Power Management Unit Controller. More details will follow. (u_pmc)
- */
-
-typedef struct { /*!< u_pmc Structure */
-
- union {
- __IO uint32_t CTRL; /*!< Power Management Control [Reset by POR, RSTN, WDT ] */
-
- struct {
- __IO uint32_t LPMODE : 2; /*!< Power Mode Control. 00 : Active 01 : Deep Sleep 10 : Power Down
- 11 : Deep Power Down */
- __IO uint32_t SYSTEMRESETENABLE: 1; /*!< ARM system reset request enable. If set enables the ARM system
- reset to affect the system. */
- __IO uint32_t WDTRESETENABLE: 1; /*!< Watchdog Timer reset enable. If set allow a watchdog timer reset
- event to affect the system. */
- __IO uint32_t WAKUPRESETENABLE: 1; /*!< Wake-up I/Os reset enable. When set, the I/O power domain is
- not shutoff in deep powerdown mode. */
- __IO uint32_t NTAGWAKUPRESETENABLE: 1; /*!< Wake-up NTAG reset enable. When set, the device can wake from
- deep power down by edge on NTAG FD signal, even if I/O power
- domain is off (see WAKUPRESETENABLE). Note that if I/O power
- domain is ON, wake-up by NTAG FD is enabled by default thus
- content of this bit does not care. Do not set unless entering
- Deep Power Down. */
- __IO uint32_t RESERVED6 : 1; /*!< Reserved. User software should write zeroes to reserved bits.
- The value read from a reserved bit is not defined. */
- __IO uint32_t SELCLOCK : 1; /*!< Select PMC functional clock : 0 = 1 MHz FRO 1 = 12 MHz FRO */
- __IO uint32_t SELLDOVOLTAGE: 1; /*!< 0 = all LDOs current output levels are determined by their associated
- VADJ bitfield. 1 = all LDOs current output levels are determined
- by their associated VADJ_2 bitfield. */
- __IO uint32_t SWRRESETENABLE: 1; /*!< Software reset enable. If set enables the software reset to
- affect the system. */
- } CTRL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t DCDC0; /*!< DCDC control register (1st) [Reset by all reset sources, except
- ARM SystemReset] */
-
- struct {
- __IO uint32_t RC : 6; /*!< Constant On-Time calibration */
- __IO uint32_t ICOMP : 2; /*!< Select the type of ZCD comparator */
- __IO uint32_t ISEL : 2; /*!< Alter Internal biasing currents */
- __IO uint32_t ICENABLE : 1; /*!< Selection of auto scaling of COT period with variations in VDD */
- __IO uint32_t TMOS : 5; /*!< One-shot generator reference current trimming signal */
- __IO uint32_t DISABLEISENSE: 1; /*!< Disable Current sensing */
- __IO uint32_t VOUT : 3; /*!< Set output regulation voltage */
- __IO uint32_t SLICINGENABLE: 1; /*!< driver_par_en */
- __IO uint32_t SLICINGPMOS: 2; /*!< open */
- __IO uint32_t SLICINGNMOS: 2; /*!< open */
- __IO uint32_t INDUCTORCLAMPENABLE: 1; /*!< ind_shrt */
- __IO uint32_t CONTINUOUSMODEENABLE: 1; /*!< open */
- } DCDC0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t DCDC1; /*!< DCDC control register (2nd) [Reset by all reset sources, except
- ARM SystemReset] */
-
- struct {
- __IO uint32_t RTRIMOFFET : 4; /*!< Adjust the offset voltage of BJT based comparator */
- __IO uint32_t RSENSETRIM : 4; /*!< Adjust Max inductor peak current limiting */
- __IO uint32_t USEEXTREF : 1; /*!< Select output bandgap value on tp1 */
- __IO uint32_t DTESTENABLE: 1; /*!< Enable Digital test signals */
- __IO uint32_t SETCURVE : 2; /*!< Bandgap calibration parameter */
- __IO uint32_t SETDC : 4; /*!< Bandgap calibration parameter */
- __IO uint32_t DTESTSEL : 3; /*!< Select the output signal for test */
- __IO uint32_t ISCALEENABLE: 1; /*!< Modify COT behavior */
- __IO uint32_t FORCEBYPASS: 1; /*!< Force bypass mode */
- __IO uint32_t TRIMAUTOCOT: 4; /*!< TrimAutoCot setting */
- __IO uint32_t LCENABLE : 1; /*!< LC enable */
- __IO uint32_t FORCEFULLCYCLE: 1; /*!< Force full cycle */
- } DCDC1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t BIAS; /*!< Bias current source control register [Reset by POR, RSTN, WDT
- ] */
-
- struct {
- __IO uint32_t DCBGAP : 5; /*!< trimming bits to adjust absolute voltage value */
- __IO uint32_t CURVE : 2; /*!< trimming bits to adjust deviations in curvature on silicon */
- uint32_t : 1;
- __IO uint32_t TRIM : 4; /*!< Control of additional current braches for PMU analog blocks */
- __IO uint32_t IREFTRIM : 6; /*!< (null) */
- __IO uint32_t ATBENABLE : 1; /*!< (null) */
- __IO uint32_t ATB : 2; /*!< (null) */
- } BIAS_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t LDOPMU; /*!< PMU & Always On domains LDO control [Reset by all reset sources,
- except ARM SystemReset] */
-
- struct {
- __IO uint32_t VADJ : 5; /*!< Sets the LDO output level (1.1V). LDO output level, in active,
- sleep and deep sleep modes, when CTRL.SELLDOVOLTAGE = 0 */
- __IO uint32_t VADJ_PWD : 5; /*!< Sets the LDO output level in power down modes (0.8V) */
- __IO uint32_t STAB : 1; /*!< (null) */
- __IO uint32_t HIGHCUR : 1; /*!< (null) */
- __IO uint32_t VADJ_BOOST : 5; /*!< Sets the LDO Boost output level (1.0V). BOOSTADJ=1 mandatory */
- __IO uint32_t VADJ_BOOST_PWD: 5; /*!< Sets the LDO Boost output level in power down modes (0.75V) */
- __IO uint32_t BOOSTADJ : 1; /*!< LDO boost enable in active, sleep and deep sleep mode, when
- CTRL.SELLDOVOLTAGE = 0 */
- __IO uint32_t BOOSTADJ_PWD: 1; /*!< LDO boost enable in power down modes */
- __IO uint32_t VADJ_2 : 5; /*!< LDO output level, in active, sleep and deep sleep modes, when
- CTRL.SELLDOVOLTAGE = 1 */
- __IO uint32_t BOOSTADJ_2 : 1; /*!< LDO boost enable in active, sleep and deep sleep modes when
- CTRL.SELLDOVOLTAGE = 1 */
- } LDOPMU_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t LDOMEM; /*!< Memories LDO control register [Reset by all reset sources, except
- ARM SystemReset] */
-
- struct {
- __IO uint32_t VADJ : 5; /*!< Sets the LDO output level (1.1V). LDO output level, in active
- and sleep modes, when CTRL.SELLDOVOLTAGE = 0 */
- __IO uint32_t VADJ_PWD : 5; /*!< Sets the LDO output level (1.1V) in power down modes */
- __IO uint32_t STAB : 1; /*!< (null) */
- __IO uint32_t HIGHCUR : 1; /*!< (null) */
- __IO uint32_t VADJ_BOOST : 5; /*!< Sets the LDO Boost output level (1.05V) */
- __IO uint32_t VADJ_BOOST_PWD: 5; /*!< Sets the LDO Boost output level in power down modes (1.05V) */
- __IO uint32_t BLEED : 1; /*!< (null) */
- __IO uint32_t VADJ_2 : 5; /*!< LDO output level, in active and sleep modes, when CTRL.SELLDOVOLTAGE
- = 1 */
- } LDOMEM_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t LDOCORE; /*!< Digital Core LDO control register [Reset by all reset sources,
- except ARM SystemReset] */
-
- struct {
- __IO uint32_t VADJ : 3; /*!< Sets the LDO output level. LDO output level, in active and sleep
- modes, when CTRL.SELLDOVOLTAGE = 0 */
- __IO uint32_t VADJ_PWD : 3; /*!< Sets the LDO output level in deep sleep mode */
- __IO uint32_t BYPASS : 1; /*!< Activate LDO bypass */
- uint32_t : 1;
- __IO uint32_t IBIAS : 2; /*!< Adjust the biasing current */
- __IO uint32_t STABMODE : 2; /*!< Stability configuration */
- __IO uint32_t VADJ_2 : 3; /*!< LDO output level, in active and sleep modes, when CTRL.SELLDOVOLTAGE
- = 1 */
- } LDOCORE_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t LDOFLASHNV; /*!< Flash LDO control register [Reset by all reset sources, except
- ARM SystemReset] */
-
- struct {
- __IO uint32_t VADJ : 3; /*!< Sets the LDO output level. LDO output level when CTRL.SELLDOVOLTAGE
- = 0 */
- __IO uint32_t BYPASS : 1; /*!< Activate LDO bypass */
- __IO uint32_t HIGHZ : 1; /*!< Put the output in high impedance state */
- __IO uint32_t IBIAS : 2; /*!< Adjust the biasing current */
- __IO uint32_t STABMODE : 1; /*!< Stability configuration */
- uint32_t : 2;
- __IO uint32_t TRIMR : 5; /*!< [Not used within PMU - do not change] R trim word, use in Flash
- reference current calibration scheme */
- __IO uint32_t VADJ_2 : 3; /*!< LDO output level when CTRL.SELLDOVOLTAGE = 1 */
- } LDOFLASHNV_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t LDOFLASHCORE; /*!< Flash Core LDO control register [Reset by all reset sources,
- except ARM SystemReset] */
-
- struct {
- __IO uint32_t VADJ : 3; /*!< Sets the LDO output level. LDO output level when CTRL.SELLDOVOLTAGE
- = 0 */
- __IO uint32_t BYPASS : 1; /*!< Activate LDO bypass */
- __IO uint32_t HIGHZ : 1; /*!< Put the output in high impedance state */
- __IO uint32_t IBIAS : 2; /*!< Adjust the biasing current */
- __IO uint32_t STABMODE : 2; /*!< Stability configuration */
- __IO uint32_t VADJ_2 : 3; /*!< LDO output level when CTRL.SELLDOVOLTAGE = 1 */
- } LDOFLASHCORE_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t LDOADC; /*!< General Purpose ADC LDO control register [Reset by all reset
- sources, except ARM SystemReset] */
-
- struct {
- __IO uint32_t VADJ : 3; /*!< Sets the LDO output level. LDO output level when CTRL.SELLDOVOLTAGE
- = 0 */
- __IO uint32_t BYPASS : 1; /*!< Activate LDO bypass */
- __IO uint32_t HIGHZ : 1; /*!< Put the output in high impedance state */
- __IO uint32_t IBIAS : 2; /*!< Adjust the biasing current */
- __IO uint32_t STABMODE : 2; /*!< Stability configuration */
- __IO uint32_t VADJ_2 : 3; /*!< LDO output level when CTRL.SELLDOVOLTAGE = 1 */
- } LDOADC_b; /*!< BitSize */
- };
- __I uint32_t RESERVED0[2];
-
- union {
- __IO uint32_t BODVBAT; /*!< VBAT Brown Out Dectector control register [Reset by POR, RSTN,
- WDT ] */
-
- struct {
- __IO uint32_t TRIGLVL : 5; /*!< BOD trigger level */
- __IO uint32_t HYST : 2; /*!< BOD Hysteresis control */
- __IO uint32_t RESETENABLE: 1; /*!< BOD reset enable. If set and BODVBAT LOW event occurs, then
- the IC will go and stay in reset forever (till hard reset on
- PAD RSTN). Suggestion is to not use this feature */
- } BODVBAT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t BODMEM; /*!< Memories Brown Out Dectector control register [Reset by all
- reset sources, except ARM SystemReset] */
-
- struct {
- __IO uint32_t TRIGLVL : 4; /*!< BOD trigger level */
- __IO uint32_t HYST : 2; /*!< BOD Hysteresis control */
- __IO uint32_t RESETENABLE: 1; /*!< BOD reset enable */
- } BODMEM_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t BODCORE; /*!< Digital Core Brown Out Dectector control register [Reset by
- all reset sources, except ARM SystemReset] */
-
- struct {
- __IO uint32_t TRIGLVL : 4; /*!< BOD trigger level */
- __IO uint32_t HYST : 2; /*!< BOD Hysteresis control */
- __IO uint32_t RESETENABLE: 1; /*!< BOD reset enable */
- } BODCORE_b; /*!< BitSize */
- };
- __I uint32_t RESERVED1;
-
- union {
- __IO uint32_t FRO192M; /*!< 192 MHz Free Running Oscillator control register [Reset by POR,
- RSTN, WDT ] */
-
- struct {
- __IO uint32_t TEMPTRIM : 6; /*!< Temperature coefficient trimming bits */
- __IO uint32_t BIASTRIM : 6; /*!< Bias trimming bits (course frequency trimming) */
- __IO uint32_t DACTRIM : 8; /*!< Curdac trimming bits (fine frequency trimming) */
- __IO uint32_t DIVSEL : 5; /*!< Mode of operation (which clock to output). FRO192M always generated.
- Bits then enable further clocks as shown. Enables are additive
- meaning that two or more clocks can be enabled together. xxxx1
- : 12MHz enabled xxx1x : 32MHz enabled xx1xx : 48MHz enabled
- x1xxx : 64MHz enabled 1xxxx : 96MHz enabled Note: 192M and 96M
- not connected in system */
- __IO uint32_t ATBCTRL : 2; /*!< Debug control bits to set the analog/digital test modes */
- } FRO192M_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t FRO1M; /*!< 1 MHz Free Running Oscillator control register [Reset by all
- reset sources, except ARM SystemReset] */
-
- struct {
- __IO uint32_t FREQSEL : 7; /*!< Frequency trimming bits */
- __IO uint32_t ATBCTRL : 2; /*!< Debug control bits to set the analog/digital test modes */
- __IO uint32_t DIVSEL : 5; /*!< Divider selection bits */
- } FRO1M_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t FRO32K; /*!< 32 KHz Free Running Oscillator (FRO) control register [Reset
- by POR, RSTN, WDT ] */
-
- struct {
- uint32_t : 1;
- __IO uint32_t NTAT : 3; /*!< Temperature coefficient trimming bits */
- __IO uint32_t PTAT : 3; /*!< Bias trimming bits (course frequency trimming) */
- __IO uint32_t CAPCAL : 9; /*!< Capacitive dac calibration bits (fine frequency trimming) */
- __IO uint32_t ATBCTRL : 2; /*!< Debug control bits to set the analog/digital test modes */
- } FRO32K_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t XTAL32K; /*!< 32 KHz Chrystal oscillator (XTAL) control register [Reset by
- all reset sources, except ARM SystemReset] */
-
- struct {
- uint32_t : 1;
- __IO uint32_t IREF : 2; /*!< reference output current selection inputs */
- __IO uint32_t TEST : 1; /*!< Oscillator Test Mode */
- __IO uint32_t IBIAS : 2; /*!< (null) */
- __IO uint32_t AMPL : 2; /*!< (null) */
- } XTAL32K_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t ANAMUXCOMP; /*!< Analog Comparator and Analog Mux control register [Reset by
- all reset sources, except ARM SystemReset] */
-
- struct {
- uint32_t : 1;
- __IO uint32_t COMP_HYST : 1; /*!< Hysteris when hyst = '1' */
- __IO uint32_t COMP_INNINT: 1; /*!< inn_int input is selected when sel_inn_int = 1 */
- __IO uint32_t COMP_LOWPOWER: 1; /*!< Low power mode */
- __IO uint32_t COMP_INPUTSWAP: 1; /*!< Input swap */
- __IO uint32_t MUX_1_SEL : 3; /*!< Analog Mux1 sel */
- __IO uint32_t MUX_2_SEL : 3; /*!< Analog Mux2 sel */
- } ANAMUXCOMP_b; /*!< BitSize */
- };
- __I uint32_t RESERVED2[3];
-
- union {
- __I uint32_t PWRSWACK; /*!< Power Switch acknowledge [Reset by all reset sources, except
- ARM SystemReset] */
-
- struct {
- __I uint32_t RESERVED0 : 1; /*!< Reserved. User software should write zeroes to reserved bits.
- The value read from a reserved bit is not defined. */
- __I uint32_t PDCOMM0 : 1; /*!< Comm0 (USART0, I2C0, SPI0) Power Domain power switch status */
- __I uint32_t PDSYSTEM : 1; /*!< System Power Domain power switch status */
- __I uint32_t PDMCURETENTION: 1; /*!< MCU Retention Power Domain power switch status */
- __I uint32_t RESERVED4 : 1; /*!< Reserved. User software should write zeroes to reserved bits.
- The value read from a reserved bit is not defined. */
- } PWRSWACK_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t DPDWKSRC; /*!< Power Down and Deep Power Down wake-up source [Reset by POR,
- RSTN, WDT ] */
-
- struct {
- __IO uint32_t PIO0 : 1; /*!< Enable / disable wakeup from Power down and Deep Power Down
- modes by GPIO0 0 : Disable 1 : Enable */
- __IO uint32_t PIO1 : 1; /*!< Enable / disable wakeup from Power down and Deep Power Down
- modes by GPIO1 0 : Disable 1 : Enable */
- __IO uint32_t PIO2 : 1; /*!< Enable / disable wakeup from Power down and Deep Power Down
- modes by GPIO2 0 : Disable 1 : Enable */
- __IO uint32_t PIO3 : 1; /*!< Enable / disable wakeup from Power down and Deep Power Down
- modes by GPIO3 0 : Disable 1 : Enable */
- __IO uint32_t PIO4 : 1; /*!< Enable / disable wakeup from Power down and Deep Power Down
- modes by GPIO4 0 : Disable 1 : Enable */
- __IO uint32_t PIO5 : 1; /*!< Enable / disable wakeup from Power down and Deep Power Down
- modes by GPIO5 0 : Disable 1 : Enable */
- __IO uint32_t PIO6 : 1; /*!< Enable / disable wakeup from Power down and Deep Power Down
- modes by GPIO6 0 : Disable 1 : Enable */
- __IO uint32_t PIO7 : 1; /*!< Enable / disable wakeup from Power down and Deep Power Down
- modes by GPIO7 0 : Disable 1 : Enable */
- __IO uint32_t PIO8 : 1; /*!< Enable / disable wakeup from Power down and Deep Power Down
- modes by GPIO8 0 : Disable 1 : Enable */
- __IO uint32_t PIO9 : 1; /*!< Enable / disable wakeup from Power down and Deep Power Down
- modes by GPIO9 0 : Disable 1 : Enable */
- __IO uint32_t PIO10 : 1; /*!< Enable / disable wakeup from Power down and Deep Power Down
- modes by GPIO10 0 : Disable 1 : Enable */
- __IO uint32_t PIO11 : 1; /*!< Enable / disable wakeup from Power down and Deep Power Down
- modes by GPIO11 0 : Disable 1 : Enable */
- __IO uint32_t PIO12 : 1; /*!< Enable / disable wakeup from Power down and Deep Power Down
- modes by GPIO12 0 : Disable 1 : Enable */
- __IO uint32_t PIO13 : 1; /*!< Enable / disable wakeup from Power down and Deep Power Down
- modes by GPIO13 0 : Disable 1 : Enable */
- __IO uint32_t PIO14 : 1; /*!< Enable / disable wakeup from Power down and Deep Power Down
- modes by GPIO14 0 : Disable 1 : Enable */
- __IO uint32_t PIO15 : 1; /*!< Enable / disable wakeup from Power down and Deep Power Down
- modes by GPIO15 0 : Disable 1 : Enable */
- __IO uint32_t PIO16 : 1; /*!< Enable / disable wakeup from Power down and Deep Power Down
- modes by GPIO16 0 : Disable 1 : Enable */
- __IO uint32_t PIO17 : 1; /*!< Enable / disable wakeup from Power down and Deep Power Down
- modes by GPIO17 0 : Disable 1 : Enable */
- __IO uint32_t PIO18 : 1; /*!< Enable / disable wakeup from Power down and Deep Power Down
- modes by GPIO18 0 : Disable 1 : Enable */
- __IO uint32_t PIO19 : 1; /*!< Enable / disable wakeup from Power down and Deep Power Down
- modes by GPIO19 0 : Disable 1 : Enable */
- __IO uint32_t PIO20 : 1; /*!< Enable / disable wakeup from Power down and Deep Power Down
- modes by GPIO20 0 : Disable 1 : Enable */
- __IO uint32_t PIO21 : 1; /*!< Enable / disable wakeup from Power down and Deep Power Down
- modes by GPIO21 0 : Disable 1 : Enable */
- __IO uint32_t NTAG_FD : 1; /*!< Enable / disable wakeup from Power down and Deep Power Down
- modes by NTAG_FD 0 : Disable 1 : Enable */
- } DPDWKSRC_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t STATUSPWR; /*!< Power OK and Ready signals from various analog modules (DCDC,
- LDO, ) [Reset by all reset sources, except ARM SystemReset] */
-
- struct {
- __I uint32_t DCDCPWROK : 1; /*!< DCDC converter power OK */
- __I uint32_t DCDCVXCTRLMON: 1; /*!< Picture of the DCDC output state */
- __I uint32_t LDOCOREPWROK: 1; /*!< CORE LDO power OK. Max switch on time 2us */
- __I uint32_t LDOFLASHNVPWROK: 1; /*!< Flash NV LDO power OK Max switch on time 20us */
- __I uint32_t LDOFLASHCOREPWROK: 1; /*!< Flash Core LDO power OK Max switch on time should be considered
- as 10us (8usec was seen in simplified environment) */
- __I uint32_t LDOADC1V1PWROK: 1; /*!< General Purpose ADC LDO power OK. Max switch on time is 8us */
- } STATUSPWR_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t STATUSCLK; /*!< FRO and XTAL status register [Reset by all reset sources, except
- ARM SystemReset] */
-
- struct {
- __I uint32_t FRO192MCLKVALID: 1; /*!< FRO 192 MHz clock valid signal. */
- __I uint32_t XTAL32KOK : 1; /*!< XTAL oscillator 32 K OK signal. When the XTAL is stable, the
- a transition from 1 to 0 will indicate a clock issue. Can not
- be used to identify a stable clock during XTAL start. */
- __I uint32_t FRO1MCLKVALID: 1; /*!< FRO 1 MHz CCO voltage detector output */
- } STATUSCLK_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t RESETCAUSE; /*!< Reset Cause register [Reset by POR] */
-
- struct {
- __IO uint32_t POR : 1; /*!< 1 : The last chip reset was caused by a Power On Reset. Write
- '1' to clear this bit */
- __IO uint32_t PADRESET : 1; /*!< 1 : The last chip reset was caused by a Pad Reset. Write '1'
- to clear this bit */
- __IO uint32_t BODRESET : 1; /*!< 1 : The last chip reset was caused by a Brown Out Detector.
- Write '1' to clear this bit */
- __IO uint32_t SYSTEMRESET: 1; /*!< 1 : The last chip reset was caused by a System Reset requested
- by the ARM CPU. Write '1' to clear this bit */
- __IO uint32_t WDTRESET : 1; /*!< 1 : The last chip reset was caused by the Watchdog Timer. Write
- '1' to clear this bit */
- __IO uint32_t WAKEUPIORESET: 1; /*!< 1 : The last chip reset was caused by a Wake-up I/O (GPIO or
- internal NTAG FD INT). Write '1' to clear this bit */
- __IO uint32_t WAKEUPPWDNRESET: 1; /*!< 1 : The last CPU reset was caused by a Wake-up from Power down
- (many sources possible: timer, IO, ...). Write '1' to clear
- this bit. Check NVIC register if not waken-up by IO (NVIC_GetPendingIRQ) */
- __IO uint32_t SWRRESET : 1; /*!< 1 : The last chip reset was caused by a Software. Write '1'
- to clear this bit */
- } RESETCAUSE_b; /*!< BitSize */
- };
- __I uint32_t RESERVED3[3];
-
- union {
- __IO uint32_t AOREG0; /*!< General purpose always on domain data storage [Reset by all
- reset sources, except ARM SystemReset] */
-
- struct {
- __IO uint32_t DATA31_0 : 32; /*!< General purpose always on domain data storage. Only writable
- 1 time after any chip reset. After the 1st write, any further
- writes are blocked. After any chip reset the write block is
- disabled until after next write. */
- } AOREG0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t AOREG1; /*!< General purpose always on domain data storage [Reset by POR,
- RSTN] */
-
- struct {
- __IO uint32_t DATA31_0 : 32; /*!< General purpose always on domain data storage. Only reinitialized
- on Power On Reset and Pin reset. */
- } AOREG1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t AOREG2; /*!< General purpose always on domain data storage [Reset by POR,
- RSTN] */
-
- struct {
- __IO uint32_t DATA31_0 : 32; /*!< General purpose always on domain data storage. Only reinitialized
- on Power On Reset and Pin reset. */
- } AOREG2_b; /*!< BitSize */
- };
- __I uint32_t RESERVED4;
-
- union {
- __IO uint32_t DUMMYCTRL; /*!< [Not in ES2] Dummy Control bus to PMU [Reset by all reset sources,
- except ARM SystemReset] */
-
- struct {
- __IO uint32_t DUMMYCTRL : 32; /*!< [Not in ES2] Dummy Control bus to PMU [Reset by all reset sources,
- except ARM SystemReset] */
- } DUMMYCTRL_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t DUMMYSTATUS; /*!< Dummy Status bus from PMU [Not reset] */
-
- struct {
- __I uint32_t DUMMYSTATUS: 8; /*!< Dummy Status - unallocated status bits from analog PMC. */
- } DUMMYSTATUS_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t DPDCTRL; /*!< Configuration parameters for Power Down and Deep Power Down
- mode [Reset by POR, RSTN, WDT ] */
-
- struct {
- __IO uint32_t XTAL32MSTARTENA: 1; /*!< enable XTAL32MHz start up at power up. Reset value set by efuse
- (wake-up by I/O only). */
- __IO uint32_t XTAL32MSTARTDLY: 2; /*!< delay between xtal ldo enable and release of reset to xtal 0:16us
- 1:32us 2:48us 3:64us. LSB reset value set by efuse (wake-up
- by I/O only). This delay is applied within PMC for Efuse controlled
- XTAL start and also BLE link layer for BLE controlled auto-start */
- } DPDCTRL_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t PIOPORCAP; /*!< The PIOPORCAP register captures the state of GPIO at power-on-reset
- or pin reset. Each bit represents the power-on reset state of
- one GPIO pin [Reset by POR, RSTN] */
-
- struct {
- __I uint32_t PIOPORCAP : 32; /*!< The PIOPORCAP register captures the state of GPIO at power-on-reset
- or pin reset. Each bit represents the power-on reset state of
- one GPIO pin [Reset by POR, RSTN] */
- } PIOPORCAP_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t PIORESCAP; /*!< The PIORESCAP0 register captures the state of GPIO port 0 when
- a reset other than a power-on reset or pin reset occurs. Each
- bit represents the reset state of one GPIO pin. [Reset by WDT,
- BOD, WAKEUP IO, ARM System reset ] */
-
- struct {
- __I uint32_t PIORESCAP : 32; /*!< The PIORESCAP0 register captures the state of GPIO port 0 when
- a reset other than a power-on reset or pin reset occurs. Each
- bit represents the reset state of one GPIO pin. [Reset by WDT,
- BOD, WAKEUP IO, ARM System reset ] */
- } PIORESCAP_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t TIMEOUTEVENTS; /*!< Record time-out errors that might occur at different stages
- during IC power up. [Reset by all reset sources, except ARM
- SystemReset] */
-
- struct {
- __I uint32_t TIMEOUTEVENTS: 32; /*!< Record time-out errors that might occur at different stages
- during IC power up. [Reset by all reset sources, except ARM
- SystemReset] */
- } TIMEOUTEVENTS_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t TIMEOUT; /*!< Various time out values used by PMC state machines. [Reset by
- all reset sources, except ARM SystemReset] */
-
- struct {
- __IO uint32_t PMUPOWEROK : 13; /*!< (400 s @ 1 MHz as default) Maximum value the PMC state machine
- will wait for an acknowledge ('Power OK') coming from any module
- in PMU before setting an error flag (in TIMEOUTEVENTS) an move
- forward */
- __IO uint32_t LDOFLASHNVDEACTIVATE: 9; /*!< (25 s @ 1 MHz as default) Time out value used when shutting
- down Flash LDOs */
- } TIMEOUT_b; /*!< BitSize */
- };
- __I uint32_t RESERVED5;
-
- union {
- __IO uint32_t PDSLEEPCFG; /*!< Controls the power to various modules in Low Power modes [Reset
- by all reset sources, except ARM SystemReset] */
-
- struct {
- __IO uint32_t PDEN_DCDC : 1; /*!< Controls DCDC power in Power down and Deep Power down modes.
- 0: DCDC is disable in Power down and Deep Power down modes 1:
- DCDC is enable in Power down and Deep Power down modes */
- __IO uint32_t PDEN_BIAS : 1; /*!< Controls Bias power in Power down and Deep Power down modes.
- 0: Bias is disable in Power down and Deep Power down modes 1:
- Bias is enable in Power down and Deep Power down modes */
- __IO uint32_t PDEN_LDO_MEM: 1; /*!< Controls LDO memories power in Power down mode. 0: LDO is disable
- in Power down mode 1: LDO is enable in Power down mode */
- __IO uint32_t PDEN_VBAT_BOD: 1; /*!< Controls VBAT BOD power in Power down and Deep Power down modes.
- 0: VBAT BOD is disable in Power down and Deep Power down modes
- 1: VBAT BOD is enable in Power down and Deep Power down modes */
- __IO uint32_t PDEN_FRO192M: 1; /*!< Controls FRO192M power in Deep Sleep, Power down and Deep Power
- down modes. 0: FRO192M is disable 1: FRO192M is enable */
- __IO uint32_t PDEN_FRO1M : 1; /*!< Controls FRO1M power in Deep Sleep, Power down and Deep Power
- down modes. 0: FRO1M is disable 1: FRO1M is enable */
- __IO uint32_t PDEN_PD_FLASH: 1; /*!< Enable Flash power domain Power Down mode (power shutoff) when
- entering in DeepSleep. In PowerDown modes this domain is automatically
- powered off. */
- __IO uint32_t PDEN_PD_COMM0: 1; /*!< Enable Comm0 power domain (USART0, I2C0, SPI0) Power Down mode
- when entering in Powerdown mode */
- __IO uint32_t EN_PDMCU_RETENTION: 1; /*!< Enable MCU Power Domain state retention when entering in 'Powerdown'
- mode for modem and radio cal values */
- __IO uint32_t RESERVED9 : 1; /*!< Reserved. User software should write zeroes to reserved bits.
- The value read from a reserved bit is not defined. */
- __IO uint32_t PDEN_PD_MEM0: 1; /*!< Enable Power Down mode of SRAM 0 when entering in Powerdown
- mode */
- __IO uint32_t PDEN_PD_MEM1: 1; /*!< Enable Power Down mode of SRAM 1 when entering in Powerdown
- mode */
- __IO uint32_t PDEN_PD_MEM2: 1; /*!< Enable Power Down mode of SRAM 2 when entering in Powerdown
- mode */
- __IO uint32_t PDEN_PD_MEM3: 1; /*!< Enable Power Down mode of SRAM 3 when entering in Powerdown
- mode */
- __IO uint32_t PDEN_PD_MEM4: 1; /*!< Enable Power Down mode of SRAM 4 when entering in Powerdown
- mode */
- __IO uint32_t PDEN_PD_MEM5: 1; /*!< Enable Power Down mode of SRAM 5 when entering in Powerdown
- mode */
- __IO uint32_t PDEN_PD_MEM6: 1; /*!< Enable Power Down mode of SRAM 6 when entering in Powerdown
- mode */
- __IO uint32_t PDEN_PD_MEM7: 1; /*!< Enable Power Down mode of SRAM 7 when entering in Powerdown
- mode */
- __IO uint32_t PDEN_PD_MEM8: 1; /*!< Enable Power Down mode of SRAM 8 when entering in Powerdown
- mode */
- __IO uint32_t PDEN_PD_MEM9: 1; /*!< Enable Power Down mode of SRAM 9 when entering in Powerdown
- mode */
- __IO uint32_t PDEN_PD_MEM10: 1; /*!< Enable Power Down mode of SRAM 10 when entering in Powerdown
- mode */
- __IO uint32_t PDEN_PD_MEM11: 1; /*!< Enable Power Down mode of SRAM 11 when entering in Powerdown
- mode */
- } PDSLEEPCFG_b; /*!< BitSize */
- };
- __I uint32_t RESERVED6;
-
- union {
- __IO uint32_t PDRUNCFG; /*!< Controls the power to various analog blocks [Reset by all reset
- sources, except ARM SystemReset] */
-
- struct {
- uint32_t : 22;
- __IO uint32_t ENA_LDO_ADC: 1; /*!< LDO ADC enable. See STATUSPWR.LDOADC1V1PWROK for when the power
- domain is ready. */
- __IO uint32_t ENA_BOD_MEM: 1; /*!< BOD MEM enable */
- __IO uint32_t ENA_BOD_CORE: 1; /*!< BOD CORE enable */
- __IO uint32_t ENA_FRO32K : 1; /*!< FRO32K enable */
- __IO uint32_t ENA_XTAL32K: 1; /*!< XTAL32K enable */
- __IO uint32_t ENA_ANA_COMP: 1; /*!< Analog Comparator enable */
- } PDRUNCFG_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t WAKEIOCAUSE; /*!< Wake-up source from Power Down and Deep Power Down modes. Allow
- to identify the Wake-up source from Power-Down mode or Deep
- Power Down mode.[Reset by POR, RSTN, WDT ] */
-
- struct {
- __I uint32_t GPIO00 : 1; /*!< Wake up was triggered by GPIO 00 */
- __I uint32_t GPIO01 : 1; /*!< Wake up was triggered by GPIO 01 */
- __I uint32_t GPIO02 : 1; /*!< Wake up was triggered by GPIO 02 */
- __I uint32_t GPIO03 : 1; /*!< Wake up was triggered by GPIO 03 */
- __I uint32_t GPIO04 : 1; /*!< Wake up was triggered by GPIO 04 */
- __I uint32_t GPIO05 : 1; /*!< Wake up was triggered by GPIO 05 */
- __I uint32_t GPIO06 : 1; /*!< Wake up was triggered by GPIO 06 */
- __I uint32_t GPIO07 : 1; /*!< Wake up was triggered by GPIO 07 */
- __I uint32_t GPIO08 : 1; /*!< Wake up was triggered by GPIO 08 */
- __I uint32_t GPIO09 : 1; /*!< Wake up was triggered by GPIO 09 */
- __I uint32_t GPIO10 : 1; /*!< Wake up was triggered by GPIO 10 */
- __I uint32_t GPIO11 : 1; /*!< Wake up was triggered by GPIO 11 */
- __I uint32_t GPIO12 : 1; /*!< Wake up was triggered by GPIO 12 */
- __I uint32_t GPIO13 : 1; /*!< Wake up was triggered by GPIO 13 */
- __I uint32_t GPIO14 : 1; /*!< Wake up was triggered by GPIO 14 */
- __I uint32_t GPIO15 : 1; /*!< Wake up was triggered by GPIO 15 */
- __I uint32_t GPIO16 : 1; /*!< Wake up was triggered by GPIO 16 */
- __I uint32_t GPIO17 : 1; /*!< Wake up was triggered by GPIO 17 */
- __I uint32_t GPIO18 : 1; /*!< Wake up was triggered by GPIO 18 */
- __I uint32_t GPIO19 : 1; /*!< Wake up was triggered by GPIO 19 */
- __I uint32_t GPIO20 : 1; /*!< Wake up was triggered by GPIO 20 */
- __I uint32_t GPIO21 : 1; /*!< Wake up was triggered by GPIO 21 */
- __I uint32_t NTAG_FD : 1; /*!< Wake up was triggered by NTAG FD */
- } WAKEIOCAUSE_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t EFUSE0; /*!< Read back decoded data from eFuse, after ECC removed. First
- 48 bits correspond to real config & trimming data (AUTO,AESR,...),
- the rest being unused RAW bits in between: 3,7, ,4*n+3, (n<(80-48)) */
-
- struct {
- __I uint32_t EFUSE0_VAL : 32; /*!< Read back decoded data from eFuse, after ECC removed. First
- 32 bits of the decoded data corresponding to real config & trimming
- data (AUTO,AESR,...). ONLY VALID AFTER INITIAL POWER-UP, AND
- RESET TO 0 AFTER ANY POWERDOWN OR DEEPPOWERDOWN */
- } EFUSE0_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t EFUSE1; /*!< Read back decoded data from eFuse, after ECC removed. First
- 48 bits correspond to real config & trimming data (AUTO,AESR,...),
- the rest being unused RAW bits in between: 3,7, ,4*n+3, (n<(80-48)) */
-
- struct {
- __I uint32_t EFUSE1_VAL : 32; /*!< Bits [23:0] correspond to Read back of decoded data from eFuse
- for data bits [53:32], after ECC removed. Bits [31:24] are unused
- RAW bits in between: 3,7, ,4*n+3, (n<(80-48)) from first 6 rows
- of efuse map. ONLY VALID AFTER INITIAL POWER-UP, AND RESET TO
- 0 AFTER ANY POWERDOWN OR DEEPPOWERDOWN */
- } EFUSE1_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t EFUSE2; /*!< Read back decoded data from eFuse, after ECC removed. First
- 48 bits correspond to real config & trimming data (AUTO,AESR,...),
- the rest being unused RAW bits in between: 3,7, ,4*n+3, (n<(80-48)) */
-
- struct {
- __I uint32_t EFUSE2_VAL : 16; /*!< Continuing from EFUSE1_VAL[31:24], these are unused RAW bits
- in between: 3,7, ,4*n+3, (n<(80-48)) from first 6 rows in efuse
- map. ONLY VALID AFTER INITIAL POWER-UP, AND RESET TO 0 AFTER
- ANY POWERDOWN OR DEEPPOWERDOWN */
- } EFUSE2_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t CTRLNORST; /*!< Extension of CTRL register, but never reset except by POR */
-
- struct {
- __IO uint32_t FASTLDOENABLE: 3; /*!< Fast LDO wake-up enable. 3 bits for the different wake-up sources:
- {generic async wake up event as selected by SLEEPCON/STARTER0&1,
- IO wake-up event, RSTN pad event} */
- } CTRLNORST_b; /*!< BitSize */
- };
-} u_pmc_Type;
-
-
-/* ================================================================================ */
-/* ================ u_ble_dp_top ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component ble_dp_top. It is Bluetooth Low Energy Data Path module APB bus interface. More details will follow. (u_ble_dp_top)
- */
-
-typedef struct { /*!< u_ble_dp_top Structure */
-
- union {
- __IO uint32_t DP_TOP_SYSTEM_CTRL; /*!< Base address of the link layer exchange memory in RAM */
-
- struct {
- __IO uint32_t RX_PDU_LEN_IN: 14; /*!< pdu length user programmed, header+payload, unit is bit. */
- __IO uint32_t AA_SEL : 1; /*!< access address selection. 0 : from ble ip 1 : user program. */
- __IO uint32_t PDU_LEN_SEL: 1; /*!< pdu length selection. 0 : from ble ip 1 : user program. */
- __IO uint32_t H_IDX : 8; /*!< h index,from 0.25 to 0.75,default is 0.5. */
- __IO uint32_t RX_EN_SEL : 1; /*!< rx enable select signal 0:from ble ip, 1:user programmed. */
- __IO uint32_t TX_EN_SEL : 1; /*!< tx enable select signal 0:from ble ip, 1:user programmed. */
- __IO uint32_t RX_REQ : 1; /*!< rx request */
- __IO uint32_t TX_REQ : 1; /*!< tx request */
- __IO uint32_t RX_MODE : 2; /*!< rx mode: 00:ble, 01:base rate, 10:ant, 11:prop */
- __IO uint32_t ANT_DATA_START: 1; /*!< ant mode, data start signal, need write 0 first, then to 1. */
- __IO uint32_t DET_MODE : 1; /*!< detection mode,0:low ppwer mode,1:high performance mode. */
- } DP_TOP_SYSTEM_CTRL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PROP_MODE_CTRL; /*!< Prop mode control */
-
- struct {
- __IO uint32_t PROP_MODE_CTRL: 32; /*!< Prop mode control */
- } PROP_MODE_CTRL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t ACCESS_ADDRESS; /*!< Access address */
-
- struct {
- __IO uint32_t AA_ADDR_IN : 32; /*!< access address user programmed. */
- } ACCESS_ADDRESS_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t ANT_PDU_DATA0; /*!< Ant pdu data0 */
-
- struct {
- __IO uint32_t ANT_PDU_DATA0: 32; /*!< Ant pdu data0 */
- } ANT_PDU_DATA0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t ANT_PDU_DATA1; /*!< Ant pdu data1 */
-
- struct {
- __IO uint32_t ANT_PDU_DATA1: 32; /*!< Ant pdu data1 */
- } ANT_PDU_DATA1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t ANT_PDU_DATA2; /*!< Ant pdu data2 */
-
- struct {
- __IO uint32_t ANT_PDU_DATA2: 32; /*!< Ant pdu data2 */
- } ANT_PDU_DATA2_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t ANT_PDU_DATA3; /*!< Ant pdu data3 */
-
- struct {
- __IO uint32_t ANT_PDU_DATA3: 32; /*!< Ant pdu data3 */
- } ANT_PDU_DATA3_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t ANT_PDU_DATA4; /*!< Ant pdu data4 */
-
- struct {
- __IO uint32_t ANT_PDU_DATA4: 32; /*!< Ant pdu data4 */
- } ANT_PDU_DATA4_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t ANT_PDU_DATA5; /*!< Ant pdu data5 */
-
- struct {
- __IO uint32_t ANT_PDU_DATA5: 32; /*!< Ant pdu data5 */
- } ANT_PDU_DATA5_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t ANT_PDU_DATA6; /*!< Ant pdu data6 */
-
- struct {
- __IO uint32_t ANT_PDU_DATA6: 32; /*!< Ant pdu data6 */
- } ANT_PDU_DATA6_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t ANT_PDU_DATA7; /*!< Ant pdu data7 */
-
- struct {
- __IO uint32_t ANT_PDU_DATA7: 32; /*!< Ant pdu data7 */
- } ANT_PDU_DATA7_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t CRC_SEED; /*!< Crc seed */
-
- struct {
- __IO uint32_t CRC_SEED_IN: 24; /*!< user programmed crc seed */
- __IO uint32_t CRC_SEED_WEN: 1; /*!< when high,enable manual program crc seed */
- } CRC_SEED_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t DP_FUNCTION_CTRL; /*!< Datapath function control */
-
- struct {
- __IO uint32_t DP_STATISTICS_SEL: 3; /*!< datapath statistics selection. */
- __IO uint32_t CHF_COEF_WEN: 1; /*!< manual select channel filter coefficent */
- __IO uint32_t CHF_COEF_IDX: 2; /*!< 0:lp coef, 1:hp32 2:hp5. */
- __IO uint32_t LP_SNR_LEN_AUTO: 1; /*!< when enable, auto adjust lp mode snr acc length, otherwise,
- the legnth fixed. */
- __IO uint32_t DOUT_ADJ_DIS: 1; /*!< data delay adjust disable. */
- __IO uint32_t LP_ADJ_MODE: 1; /*!< lp mode delay adjust mode, 0: smae as lp, 58us, 1, 49us. */
- __IO uint32_t FR_OFFSET_EN: 1; /*!< pdu frequency offset track enable. */
- __IO uint32_t DC_AVE_EN : 1; /*!< when high, enable cfo estimation average. */
- __IO uint32_t FIX_DELAY_EN: 1; /*!< 1 fix delay between max_par and burst_det,0 for bitmatch. */
- __IO uint32_t TRACK_LEN : 2; /*!< track length, 0:0, 1:16, 2:24, 3:32 */
- __IO uint32_t TRACK_LEN_WEN: 1; /*!< when high, manual track length. */
- uint32_t : 1;
- __IO uint32_t XCORR_FILT_EN: 1; /*!< when high, enable xcorr filter. */
- __IO uint32_t XCORR_FULLWIN_EN: 1; /*!< when xcorr_win_auto_en low, full sync enable. */
- __IO uint32_t XCORR_AA_LEN: 1; /*!< select access address bit number,0:16, 1:32. */
- __IO uint32_t XCORR_AA_LEN_WEN: 1; /*!< enable manual correlation aa length. */
- __IO uint32_t XCORR_WIN_AUTO_EN: 1; /*!< correlation window size auto selection enable. */
- __IO uint32_t RESAMPLER_TAP: 1; /*!< resampler tap number, 0:2, 1:9. */
- __IO uint32_t RESAMPLER_TAP_WEN: 1; /*!< when high, enable manual resampler tap number, otherwise,auto
- selection. */
- __IO uint32_t RESAMPLER_BP: 1; /*!< resampler enable or bypass, 0:enable, 1:bypass. */
- __IO uint32_t FAGC_WIN_LEN: 1; /*!< select estimation length,0:l,1:2xl. */
- __IO uint32_t FAGC_WEN : 1; /*!< when high, enable manual fine agc gain. */
- __IO uint32_t HP_CFO_EN : 1; /*!< when hp mode, cfo estimation enable,0:disable,1:enable */
- __IO uint32_t CFO_TRACK_EN: 1; /*!< tracking cfo enable */
- __IO uint32_t CFO_INI_EN : 1; /*!< initial cfo enable */
- __IO uint32_t ADC_IN_FLIP: 1; /*!< when 1 exchange i and q signals. */
- __IO uint32_t TX_EN_MODE : 1; /*!< transmit mode, 0, start one transmit use tx_req, 1: start repetitious
- transmit use tx_req */
- __IO uint32_t RX_EN_MODE : 1; /*!< receiver mode, 0, start one receiver use rx_req, 1: start repetitious
- reciver use rx_req */
- } DP_FUNCTION_CTRL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t DP_TEST_CTRL; /*!< Datapath test control */
-
- struct {
- __IO uint32_t DP_TEST_CTRL: 32; /*!< Datapath test control */
- } DP_TEST_CTRL_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t BLE_DP_STATUS1; /*!< Datapath status1 */
-
- struct {
- __I uint32_t SNR_EST : 8; /*!< snr estimation */
- __I uint32_t CNR_EST : 6; /*!< cnr estimation */
- uint32_t : 2;
- __I uint32_t AGC_RSSI : 8; /*!< signal rssi db value */
- __I uint32_t AGC_RSSI_READY: 1; /*!< signal rssi valid */
- __I uint32_t SNR_VLD : 1; /*!< snr estimation valid */
- __I uint32_t CNR_VLD : 1; /*!< cnr estimation valid */
- __I uint32_t TX_BUSY : 1; /*!< tx busy signal */
- } BLE_DP_STATUS1_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t BLE_DP_STATUS2; /*!< Datapath status2 */
-
- struct {
- __I uint32_t VALID_PCK_NUM: 16; /*!< received valid packet number */
- __I uint32_t AA_ERR_NUM : 6; /*!< access address error number */
- uint32_t : 7;
- __I uint32_t CRC_ERROR : 1; /*!< indicator of packet crc error */
- __I uint32_t BURST_DET : 1; /*!< indicator of burst detection, 0:not sync, 1:sync */
- __I uint32_t DP_STATUS_VLD_0: 1; /*!< data path status valid after access address valid. */
- } BLE_DP_STATUS2_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t BLE_DP_STATUS3; /*!< Datapath status3 */
-
- struct {
- __I uint32_t FD_CFO_TRACK: 11; /*!< normalized cfo tracking estimation */
- uint32_t : 5;
- __I uint32_t CFO_EST_FD : 11; /*!< normalized lp cfo initial estimation. */
- } BLE_DP_STATUS3_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t BLE_DP_STATUS4; /*!< Datapath status4 */
-
- struct {
- __I uint32_t RESAMPLER_PH: 10; /*!< resampler phase. */
- uint32_t : 6;
- __I uint32_t HP_CFO : 12; /*!< normalized hp cfo estimation */
- uint32_t : 3;
- __I uint32_t HP_CFO_VLD : 1; /*!< hp mode cfo estimation result valid */
- } BLE_DP_STATUS4_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t RX_FRONT_END_CTRL1; /*!< Rx front end control1 */
-
- struct {
- __IO uint32_t CFO_COMP : 15; /*!< cfo user programmed */
- uint32_t : 1;
- __IO uint32_t DCNOTCH_GIN: 2; /*!< dc notch coefficient,00:2^-3,01:2^-4,10,2^-5,11:2^-6 */
- } RX_FRONT_END_CTRL1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t RX_FRONT_END_CTRL2; /*!< Rx front end control2 */
-
- struct {
- __IO uint32_t FAGC_GAIN : 11; /*!< fine agc gain */
- __IO uint32_t FAGC_INI_VAL: 1; /*!< fagc gain initial value */
- __IO uint32_t CNR_IDX_DELTA: 4; /*!< cnr index delta */
- __IO uint32_t FAGC_REF : 8; /*!< fine agc signal reference */
- __IO uint32_t CORDIC_MIN_VIN_TH: 4; /*!< cordic input signal min threshold */
- __IO uint32_t FREQ_TRADE_EN: 1; /*!< enable frequency trade when cordic input signal small than cordic_min_vin_
- th */
- __IO uint32_t CHN_SHIFT : 3; /*!< channel filter shift, 0, not any shift, 1:x2, 2:x4, 3:x8, 4:16 */
- } RX_FRONT_END_CTRL2_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t FREQ_DOMAIN_CTRL1; /*!< Frequency domain control1 */
-
- struct {
- __IO uint32_t SYNC_WORD_IN0: 8; /*!< manul sync word [39:32] */
- __IO uint32_t SYNC_WORD_WEN: 1; /*!< when high, enable manul sync word */
- uint32_t : 6;
- __IO uint32_t SYNC_P_SEL : 1; /*!< 0: datapath will not reset if sync_p is out of syncwin, 1: datapath
- will reset, and sync_p will not upload to bleip */
- __IO uint32_t RD_EXBIT_EN: 1; /*!< when high, read an extra bit(8 samples) from dp buffer */
- __IO uint32_t RFAGC_TRACK_DLY: 3; /*!< Rfagc track delay, range is [0,7],so the track bit num is [0,
- 8:32] */
- uint32_t : 4;
- __IO uint32_t PROP_DF_16US: 8; /*!< prop mode direct found, waiting 16 us. */
- } FREQ_DOMAIN_CTRL1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t FREQ_DOMAIN_CTRL2; /*!< Frequency domain control2 */
-
- struct {
- __IO uint32_t SYNC_WORD_IN1: 32; /*!< manul sync word [31:0] */
- } FREQ_DOMAIN_CTRL2_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t FREQ_DOMAIN_CTRL3; /*!< Frequency domain control3 */
-
- struct {
- __IO uint32_t XCORR_PAR_TH3: 6; /*!< xcorr trigger par threshold3 */
- uint32_t : 2;
- __IO uint32_t XCORR_PAR_TH2: 6; /*!< xcorr trigger par threshold2 */
- uint32_t : 2;
- __IO uint32_t XCORR_PAR_TH1: 6; /*!< xcorr trigger par threshold1 */
- uint32_t : 2;
- __IO uint32_t XCORR_PAR_TH0: 6; /*!< xcorr trigger par threshold0 */
- } FREQ_DOMAIN_CTRL3_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t FREQ_DOMAIN_CTRL4; /*!< Frequency domain control4 */
-
- struct {
- __IO uint32_t XCORR_POW_TH3: 6; /*!< xcorr power threshold3 */
- uint32_t : 2;
- __IO uint32_t XCORR_POW_TH2: 6; /*!< xcorr power threshold2 */
- uint32_t : 2;
- __IO uint32_t XCORR_POW_TH1: 6; /*!< xcorr power threshold1 */
- uint32_t : 2;
- __IO uint32_t XCORR_POW_TH0: 6; /*!< xcorr power threshold0 */
- } FREQ_DOMAIN_CTRL4_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t FREQ_DOMAIN_CTRL5; /*!< Frequency domain control5 */
-
- struct {
- __IO uint32_t GAIN_TED : 2; /*!< ted gain.00:2^-2;01:2^-3;10:2^-4;11:2^-5 */
- uint32_t : 2;
- __IO uint32_t SYNC_DIN_SAT_VALUE: 3; /*!< sync din amplitude limit value, 0 to 1.75 correspond to 2 to
- 3.75 */
- __IO uint32_t SYNC_DIN_SAT_EN: 1; /*!< sync din amplitude limit enable */
- __IO uint32_t CNT_SETTLE_IDX: 3; /*!< buffer settle threshold from 32 to 256, step is 32 */
- uint32_t : 1;
- __IO uint32_t TRIG_XCORR_CNT: 4; /*!< correlation search window size */
- __IO uint32_t XCORR_RSSI_TH3: 4; /*!< xcorr triger rssi threshold3 */
- __IO uint32_t XCORR_RSSI_TH2: 4; /*!< xcorr triger rssi threshold2 */
- __IO uint32_t XCORR_RSSI_TH1: 4; /*!< xcorr triger rssi threshold1 */
- __IO uint32_t XCORR_RSSI_TH0: 4; /*!< xcorr triger rssi threshold0 */
- } FREQ_DOMAIN_CTRL5_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t FREQ_DOMAIN_CTRL6; /*!< Frequency domain control6 */
-
- struct {
- __IO uint32_t HP_TRAIN_SIZ: 5; /*!< hp mode training size */
- uint32_t : 3;
- __IO uint32_t HP_HIDX_GAIN: 8; /*!< h index reference gain when hp mode, default is 1.0 */
- __IO uint32_t H_REF_GAIN : 6; /*!< h index reference gain when frequency offset track, default
- is 1.0 */
- uint32_t : 2;
- __IO uint32_t DET_FR_IDX : 2; /*!< pdu cfo tracking loop gain: 2'b00:2^-4;2'b01:2^-5;2'b10:2^-6;2'b11:2^-7; */
- uint32_t : 2;
- __IO uint32_t CFO_FR_IDX : 2; /*!< aa cfo tracking loop gain: 2'b00:2^-4;2'b01:2^-5;2'b10:2^-6;2'b11:2^-7; */
- } FREQ_DOMAIN_CTRL6_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t HP_MODE_CTRL1; /*!< High performance mode control */
-
- struct {
- __IO uint32_t HP_BMC_P_TRACK: 6; /*!< p paramter in search period of frequency offset iir of bmc */
- uint32_t : 2;
- __IO uint32_t HP_BMC_P_TRAIN: 6; /*!< p paramter in training period of frequency offset iir of bmc */
- uint32_t : 2;
- __IO uint32_t HP_BMC_CZ1 : 6; /*!< cz1 parameter. */
- uint32_t : 2;
- __IO uint32_t BUF_IDX_DELTA: 4; /*!< buffer index delta */
- __IO uint32_t WMF2_DSAMP_IDX: 3; /*!< wmf2 down sampling position, -4 to 3 */
- __IO uint32_t HP_TRAIN_SIZ_FIX: 1; /*!< when high, hp mode training size same as cfo tracking */
- } HP_MODE_CTRL1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t HP_MODE_CTRL2; /*!< High performance mode control */
-
- struct {
- __IO uint32_t SNR_EST_REF: 8; /*!< signal amplitude used in snr estimation,whose unit is db */
- __IO uint32_t SNR_EST_LEN: 2; /*!< symbol number used in snr estimation,when pdu length is less
- than 4 8,32 will be used,otherwise the value configured from
- register will be used,00 : 32,01 : 64,10 : 128,11 : rsvd */
- uint32_t : 2;
- __IO uint32_t SNR_EST_EN : 1; /*!< snr estimation in time domain enbale,0 : disable,1 : enable */
- uint32_t : 3;
- __IO uint32_t HP_BMC_Q_TRACK: 8; /*!< q paramter in search period of phase offset iir of bmc */
- __IO uint32_t HP_BMC_Q_TRAIN: 8; /*!< q paramter in training period of phase offset iir of bmc */
- } HP_MODE_CTRL2_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t FREQ_DOMAIN_STATUS1; /*!< Frequency domain status1 */
-
- struct {
- __I uint32_t MAX_XCORR : 10; /*!< xcorr_org value at the max par position */
- uint32_t : 6;
- __I uint32_t PKT_OFFSET_COM: 9; /*!< time from access addres last bit to trigger finish */
- uint32_t : 3;
- __I uint32_t NIDX : 4; /*!< noise db buffer index */
- } FREQ_DOMAIN_STATUS1_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t FREQ_DOMAIN_STATUS2; /*!< Frequency domain status2 */
-
- struct {
- __I uint32_t MAX_PAR_SPWR: 10; /*!< spwr value at the max par position */
- uint32_t : 6;
- __I uint32_t MAX_PAR_XCORR: 10; /*!< xcorr*xcorr value at the max par position */
- } FREQ_DOMAIN_STATUS2_b; /*!< BitSize */
- };
- __I uint32_t RESERVED0[3];
-
- union {
- __IO uint32_t DP_AA_ERROR_CTRL; /*!< Datapath aa error control */
-
- struct {
- __IO uint32_t IQSWAP_SEL : 1; /*!< when high, adc data iq swap with analog iqswap. datapath mixer
- nco if selection changed with analog iqswap. */
- __IO uint32_t AA_ERROR_EN: 1; /*!< when high, it will reset datapath when aa error */
- __IO uint32_t AA_ERROR_CNR_EN: 1; /*!< when high, the aa error reset condition is cnr > threshold and
- aa error. when low, it don care cnr */
- __IO uint32_t AA_ERROR_CNR_SEL: 1; /*!< when high, the cnr threshold is 24. when low, the cnr threshold
- is 32 */
- } DP_AA_ERROR_CTRL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t DP_INT; /*!< Datapath interrupt */
-
- struct {
- __IO uint32_t DP_INTERRUPT0: 1; /*!< datapath interrupt0 */
- __IO uint32_t DP_INTERRUPT1: 1; /*!< datapath interrupt1 */
- __IO uint32_t DP_INTERRUPT2: 1; /*!< datapath interrupt2 */
- __IO uint32_t DP_INTERRUPT: 1; /*!< datapath interrupt */
- uint32_t : 12;
- __IO uint32_t DP_INTERRUPT0_SEL: 4; /*!< datapath interrupt0 selection */
- __IO uint32_t DP_INTERRUPT1_SEL: 4; /*!< datapath interrupt1 selection */
- __IO uint32_t DP_INTERRUPT2_SEL: 4; /*!< datapath interrupt2 selection */
- __IO uint32_t DP_INTERRUPT0_MSK: 1; /*!< datapath interrupt0 msk */
- __IO uint32_t DP_INTERRUPT1_MSK: 1; /*!< datapath interrupt1 msk */
- __IO uint32_t DP_INTERRUPT2_MSK: 1; /*!< datapath interrupt2 msk */
- __IO uint32_t DP_INTERRUPT_MSK: 1; /*!< datapath interrupt msk */
- } DP_INT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t DP_AA_ERROR_TH; /*!< Datapath aa error threshold control */
-
- struct {
- __IO uint32_t HP_TRAIN_POSITION: 1; /*!< when high, use the bits just ahead of pdu for rsve training.
- when low, the training bit starts at the track */
- __IO uint32_t CORDIC_IN_SCALE: 1; /*!< when high, cordic input will be auto scaled(shift) according
- to the magnitude of real/imag data */
- __IO uint32_t PAR_AUTO_HIGHER_SEL: 1; /*!< when high, par auto higher 1/4, when low, par auto higher 1/8,
- it will work together with par_auto_higher_en and rssi_good_dbm */
- __IO uint32_t PAR_AUTO_HIGHER_EN: 1; /*!< when high, when signal is good ( rssi large than rssi_good_dbm),
- it will auto higher the par threshold */
- __IO uint32_t SNR_GOOD_TH: 3; /*!< threshold for snr(fd mode calculated use aa) to reset datapath
- cooperate with cnr, snr, and aa error */
- uint32_t : 1;
- __IO uint32_t CNR_GOOD_TH: 6; /*!< threshold for cnr to reset datapath cooperate with cnr, snr,
- and aa error */
- uint32_t : 2;
- __IO uint32_t RSSI_GOOD_TH: 8; /*!< threshold for rssi to reset datapath cooperate with cnr, snr,
- and aa error. */
- __IO uint32_t RSSI_GOOD_DBM: 8; /*!< when rssi dbm large than the -rssi_good_dbm, the signal is good
- enough to higher the par threshold if the function enable */
- } DP_AA_ERROR_TH_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t DP_ANTENNA_CTRL; /*!< Direction founding antenna control */
-
- struct {
- __IO uint32_t SWITCH_MAP_SEL_8F: 2; /*!< switch antenna map selection 8 to f */
- __IO uint32_t SWITCH_MAP_SEL_07: 2; /*!< switch antenna map selection 0 to 7 */
- __IO uint32_t EXT_ANTENNA_NUM: 4; /*!< user programmed switch antenna number */
- __IO uint32_t EXT_ANTENNA_NUM_WEN: 1; /*!< user programmed switch antenna enable */
- uint32_t : 7;
- __IO uint32_t BUFFER_BP : 1; /*!< when high, bypass buffer, and not write/read buffer for datapath
- power test */
- __IO uint32_t TEST_TD_POWER: 1; /*!< when high, test rfe, td detector power, other module dont work,
- the cordic work or not decided by resampler_bp */
- __IO uint32_t TEST_FD_POWER: 1; /*!< when high, test rfe, cordic and fd detector power, other module
- dont work */
- __IO uint32_t TEST_SYNC_POWER: 1; /*!< when high, test rfe, cordic and sync power, other module dont
- work */
- __IO uint32_t TEST_RFE_CORDIC_POWER: 1; /*!< when high, test rfe and cordic power, other module dont work */
- __IO uint32_t TEST_RFE_POWER: 1; /*!< when high, test rfe power, other module dont work. */
- __IO uint32_t ADC01_SAMPLE_TIME: 1; /*!< when high, will exchange the adc0/adc1 sample time, to avoid
- the error sample time for adc0/adc1 */
- __IO uint32_t PHY_RATE_MUX: 1; /*!< ble data rate used in chip, 0: 1mbps mode, 1: 2mbps mode */
- __IO uint32_t PHY_RATE_REG: 1; /*!< 0: user programmed phy data rate, 0: 1mbps mode, 1: 2mbps mode */
- __IO uint32_t PHY_RATE_WEN: 1; /*!< 0: phy_rate come from ble ip, 1: phy_rate come from register
- phy_rate_reg */
- __IO uint32_t PDU_RSSI_WAIT_TIME: 1; /*!< 0: wait 0us, 1: wait 4us */
- __IO uint32_t PDU_RSSI_WIN_LEN: 1; /*!< select estimation length for pdu rssi calculate,0:l,1:2xl */
- __IO uint32_t CAL_PDU_RSSI_EN: 1; /*!< calculate rssi use pdu data enbale */
- __IO uint32_t PROP_CRC_AA_DIS: 1; /*!< prop mode crc check, disable check access address */
- __IO uint32_t PROP_AA_LSB_FIRST: 1; /*!< prop mode access address lsb first, for cbt test */
- __IO uint32_t PRE_NUM_WEN: 1; /*!< preamble number write enable */
- } DP_ANTENNA_CTRL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t ANTENNA_MAP01; /*!< Direction founding antenna map 01 */
-
- struct {
- __IO uint32_t ANTENNA_MAP01: 32; /*!< Direction founding antenna map 01 */
- } ANTENNA_MAP01_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t ANTENNA_MAP23; /*!< Direction founding antenna map 23 */
-
- struct {
- __IO uint32_t ANTENNA_MAP23: 32; /*!< Direction founding antenna map 23 */
- } ANTENNA_MAP23_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t ANTENNA_MAP45; /*!< Direction founding antenna map 45 */
-
- struct {
- __IO uint32_t ANTENNA_MAP45: 32; /*!< Direction founding antenna map 45 */
- } ANTENNA_MAP45_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t ANTENNA_MAP67; /*!< Direction founding antenna map 67 */
-
- struct {
- __IO uint32_t ANTENNA_MAP67: 32; /*!< Direction founding antenna map 67 */
- } ANTENNA_MAP67_b; /*!< BitSize */
- };
- __I uint32_t RESERVED1;
-
- union {
- __IO uint32_t LL_EM_BASE_ADDRESS; /*!< Exchange memory base address for Link Layer */
-
- struct {
- __IO uint32_t LL_EM_BASE_ADDRESS: 32; /*!< Exchange memory base address for Link Layer */
- } LL_EM_BASE_ADDRESS_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t RX_EARLY_EOP; /*!< Early end of packet setting */
-
- struct {
- __IO uint32_t rx_early_eop: 8; /*!< Early end of packet setting, in bits from the end of the packet */
- } RX_EARLY_EOP_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t ANT_DIVERSITY; /*!< Antenna diversity */
-
- struct {
- __IO uint32_t ble_ant_selected: 1; /*!< 0: ADE is asserted 1: ADE de-asserted */
- __IO uint32_t ble_ant_mode: 1; /*!< 0:BLE antenna diversity controlled from a register bit ble_ant_selected
- [0: ADE is asserted; 1: ADE de-asserted] 1:BLE selects same
- antenna that is selected by ZB (capture at the point of going
- into RX or TX in case ZB is trying to use the radio simultaneously
- with BLE) */
- } ANT_DIVERSITY_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t TX_M_TEST_CTRL; /*!< Test stream control on TX path */
-
- struct {
- __IO uint32_t tx_test_mode: 4; /*!< 0 : PRBS9 (defined in BLE spec) [BLL-RS-401] 1 : Repeated 11110000
- sequence [BLL-RS-406] 2 : Repeated 10101010 sequence [BLL-RS-407]
- 3 : PRBS15 (defined in BLE spec) [BLL-RS-408] 4 : Repeated 11111111
- sequence [BLL-RS-409] 5 : Repeated 11111111 sequence [BLL-RS-409]
- 6 : Repeated 00001111 sequence [BLL-RS-411] 7 : Repeated 01010101
- sequence [BLL-RS-412] */
- __IO uint32_t tx_test_speed: 1; /*!< 0:BLE=1Mbps 1:BLE=2Mbps */
- __IO uint32_t tx_test_en : 1; /*!< 0 : test pattern insertion disabled. BLE TX path uses data from
- link layer 1 : tx test pattern insertion enabled. */
- } TX_M_TEST_CTRL_b; /*!< BitSize */
- };
-} u_ble_dp_top_Type;
-
-
-/* ================================================================================ */
-/* ================ u_pvt ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component pvt It is an PVT (Process Voltage Temperature) sensor (Rinogs + Delay Lines) with APB bus interface. More details will follow. (u_pvt)
- */
-
-typedef struct { /*!< u_pvt Structure */
-
- union {
- __IO uint32_t RED_DEL_CTRL_0; /*!< RED_0 Delay line value step of 250ps in typical case */
-
- struct {
- __IO uint32_t RED_DEL_CTRL_0: 32; /*!< RED_0 Delay line value step of 250ps in typical case */
- } RED_DEL_CTRL_0_b; /*!< BitSize */
- };
- __I uint32_t RESERVED0[2];
-
- union {
- __IO uint32_t RED_REGION_CNT_0; /*!< RED_0 counter */
-
- struct {
- __IO uint32_t RED_REGION_CNT_0: 32; /*!< RED_0 counter */
- } RED_REGION_CNT_0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t RED_REGION_CNT_CTRL_0; /*!< RED_0 counter enable */
-
- struct {
- __IO uint32_t RED_REGION_CNT_CTRL_0: 32; /*!< RED_0 counter enable */
- } RED_REGION_CNT_CTRL_0_b; /*!< BitSize */
- };
- __I uint32_t RESERVED1[3];
-
- union {
- __IO uint32_t AMBER_DEL_CTRL_0; /*!< AMBER_0 Delay line value step of 250ps in typical case */
-
- struct {
- __IO uint32_t AMBER_DEL_CTRL_0: 32; /*!< AMBER_0 Delay line value step of 250ps in typical case */
- } AMBER_DEL_CTRL_0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t AMBER_RINGO_0; /*!< RINGO_0 control */
-
- struct {
- __IO uint32_t ENABLE : 1; /*!< 1: enable RINGO clock generation */
- __IO uint32_t CNT_ENABLE : 1; /*!< 1: start RINGO counter */
- __IO uint32_t CNT_RESET : 1; /*!< 1: reset RINGO counter */
- } AMBER_RINGO_0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t AMBER_RINGO_CNT_0; /*!< RINGO_0 counter */
-
- struct {
- __IO uint32_t AMBER_RINGO_CNT_0: 32; /*!< RINGO_0 counter */
- } AMBER_RINGO_CNT_0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t AMBER_REGION_CNT_0; /*!< AMBER_0 counter */
-
- struct {
- __IO uint32_t AMBER_REGION_CNT_0: 32; /*!< AMBER_0 counter */
- } AMBER_REGION_CNT_0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t AMBER_REGION_CNT_CTRL_0; /*!< AMBER_0 counter enable */
-
- struct {
- __IO uint32_t AMBER_REGION_CNT_CTRL_0: 32; /*!< AMBER_0 counter enable */
- } AMBER_REGION_CNT_CTRL_0_b; /*!< BitSize */
- };
- __I uint32_t RESERVED2[3];
-
- union {
- __IO uint32_t DFT_CTRL_0; /*!< RED_0 and AMBER_0 Delay line DFT control */
-
- struct {
- __IO uint32_t DFT_CTRL_0 : 32; /*!< RED_0 and AMBER_0 Delay line DFT control */
- } DFT_CTRL_0_b; /*!< BitSize */
- };
- __I uint32_t RESERVED3[495];
-
- union {
- __IO uint32_t RED_DEL_CTRL_1; /*!< RED_1 Delay line value step of 250ps in typical case */
-
- struct {
- __IO uint32_t RED_DEL_CTRL_1: 32; /*!< RED_1 Delay line value step of 250ps in typical case */
- } RED_DEL_CTRL_1_b; /*!< BitSize */
- };
- __I uint32_t RESERVED4[2];
-
- union {
- __IO uint32_t RED_REGION_CNT_1; /*!< RED_0 counter */
-
- struct {
- __IO uint32_t RED_REGION_CNT_1: 32; /*!< RED_0 counter */
- } RED_REGION_CNT_1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t RED_REGION_CNT_CTRL_1; /*!< RED_0 counter enable */
-
- struct {
- __IO uint32_t RED_REGION_CNT_CTRL_1: 32; /*!< RED_0 counter enable */
- } RED_REGION_CNT_CTRL_1_b; /*!< BitSize */
- };
- __I uint32_t RESERVED5[3];
-
- union {
- __IO uint32_t AMBER_DEL_CTRL_1; /*!< AMBER_1 Delay line value step of 250ps in typical case */
-
- struct {
- __IO uint32_t AMBER_DEL_CTRL_1: 32; /*!< AMBER_1 Delay line value step of 250ps in typical case */
- } AMBER_DEL_CTRL_1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t AMBER_RINGO_1; /*!< RINGO_1 control */
-
- struct {
- __IO uint32_t ENABLE : 1; /*!< 1: enable RINGO clock generation */
- __IO uint32_t CNT_ENABLE : 1; /*!< 1: start RINGO counter */
- __IO uint32_t CNT_RESET : 1; /*!< 1: reset RINGO counter */
- } AMBER_RINGO_1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t AMBER_RINGO_CNT_1; /*!< RINGO_1 counter */
-
- struct {
- __IO uint32_t AMBER_RINGO_CNT_1: 32; /*!< RINGO_1 counter */
- } AMBER_RINGO_CNT_1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t AMBER_REGION_CNT_1; /*!< AMBER_1 counter */
-
- struct {
- __IO uint32_t AMBER_REGION_CNT_1: 32; /*!< AMBER_1 counter */
- } AMBER_REGION_CNT_1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t AMBER_REGION_CNT_CTRL_1; /*!< AMBER_1 counter enable */
-
- struct {
- __IO uint32_t AMBER_REGION_CNT_CTRL_1: 32; /*!< AMBER_1 counter enable */
- } AMBER_REGION_CNT_CTRL_1_b; /*!< BitSize */
- };
- __I uint32_t RESERVED6[3];
-
- union {
- __IO uint32_t DFT_CTRL_1; /*!< RED_1 and AMBER_1 Delay line DFT control */
-
- struct {
- __IO uint32_t DFT_CTRL_1 : 32; /*!< RED_1 and AMBER_1 Delay line DFT control */
- } DFT_CTRL_1_b; /*!< BitSize */
- };
-} u_pvt_Type;
-
-
-/* ================================================================================ */
-/* ================ u_async_syscon ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component async_syscon (u_async_syscon)
- */
-
-typedef struct { /*!< u_async_syscon Structure */
-
- union {
- __IO uint32_t ASYNCPRESETCTRL; /*!< Asynchronous peripherals reset control. The ASYNCPRESETCTRL
- register allows software to reset specific peripherals attached
- to the async APB bridge. Writing a zero to any assigned bit
- in this register clears the reset and allows the specified peripheral
- to operate. Writing a one asserts the reset. */
-
- struct {
- uint32_t : 1;
- __IO uint32_t CT32B0 : 1; /*!< Controls the reset for Counter/Timer CT32B0 */
- __IO uint32_t CT32B1 : 1; /*!< Controls the reset for Counter/Timer CT32B1 */
- } ASYNCPRESETCTRL_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t ASYNCPRESETCTRLSET; /*!< Set bits in ASYNCPRESETCTRL. Writing ones to this register sets
- the corresponding bit or bits in the ASYNCPRESETCTRL register,
- if they are implemented */
-
- struct {
- uint32_t : 1;
- __O uint32_t CT32B0 : 1; /*!< Writing 1 to this register sets the bit ASYNCPRESETCTRL.CT32B0 */
- __O uint32_t CT32B1 : 1; /*!< Writing 1 to this register sets the bit ASYNCPRESETCTRL.CT32B1 */
- } ASYNCPRESETCTRLSET_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t ASYNCPRESETCTRLCLR; /*!< Clear bits in ASYNCPRESETCTRL. Writing ones to this register
- clears the corresponding bit or bits in the ASYNCPRESETCTRL
- register, if they are implemented */
-
- struct {
- uint32_t : 1;
- __O uint32_t CT32B0 : 1; /*!< Writing 1 to this register clears the bit ASYNCPRESETCTRL.CT32B0 */
- __O uint32_t CT32B1 : 1; /*!< Writing 1 to this register clears the bit ASYNCPRESETCTRL.CT32B1 */
- } ASYNCPRESETCTRLCLR_b; /*!< BitSize */
- };
- __I uint32_t RESERVED0;
-
- union {
- __IO uint32_t ASYNCAPBCLKCTRL; /*!< Asynchronous peripherals clock control. This register controls
- how the clock selected for the asynchronous APB peripherals
- is divided to provide the clock to the asynchronous peripherals */
-
- struct {
- uint32_t : 1;
- __IO uint32_t CT32B0 : 1; /*!< Controls the clock for Counter/Timer CT32B0 */
- __IO uint32_t CT32B1 : 1; /*!< Controls the clock for Counter/Timer CT32B1 */
- } ASYNCAPBCLKCTRL_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t ASYNCAPBCLKCTRLSET; /*!< Set bits in ASYNCAPBCLKCTRL. Writing ones to this register sets
- the corresponding bit or bits in the ASYNCAPBCLKCTRLSET register,
- if they are implemented */
-
- struct {
- uint32_t : 1;
- __O uint32_t CT32B0 : 1; /*!< Writing 1 to this register sets the bit ASYNCAPBCLKCTRL.CT32B0 */
- __O uint32_t CT32B1 : 1; /*!< Writing 1 to this register sets the bit ASYNCAPBCLKCTRL.CT32B1 */
- } ASYNCAPBCLKCTRLSET_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t ASYNCAPBCLKCTRLCLR; /*!< Clear bits in ASYNCAPBCLKCTRL. Writing ones to this register
- sets the corresponding bit or bits in the ASYNCAPBCLKCTRLSET
- register, if they are implemented */
-
- struct {
- uint32_t : 1;
- __O uint32_t CT32B0 : 1; /*!< Writing 1 to this register clears the bit ASYNCAPBCLKCTRL.CT32B0 */
- __O uint32_t CT32B1 : 1; /*!< Writing 1 to this register clears the bit ASYNCAPBCLKCTRL.CT32B1 */
- } ASYNCAPBCLKCTRLCLR_b; /*!< BitSize */
- };
- __I uint32_t RESERVED1;
-
- union {
- __IO uint32_t ASYNCAPBCLKSELA; /*!< Asynchronous APB clock source select */
-
- struct {
- __IO uint32_t SEL : 2; /*!< Clock source for modules beyond asynchronous Bus bridge: ASYNC_SYSCON
- itself, timers 0/1 0: main (gated) clock 1: XTAL32M 2: FRO32M
- 3: FRO48M */
- } ASYNCAPBCLKSELA_b; /*!< BitSize */
- };
- __I uint32_t RESERVED2;
-
- union {
- __IO uint32_t ASYNCAPBCLKDIV; /*!< Asynchronous APB clock division select [ES1 only] */
-
- struct {
- __IO uint32_t DIV : 8; /*!< [ES1 only] Clock divider value. 0: Divide by 1. 255: Divide
- by 256 */
- uint32_t : 21;
- __IO uint32_t RESET : 1; /*!< [ES1 only] Resets the divider counter. Can be used to make sure
- a new divider value is used right away rather than completing
- the previous count */
- __IO uint32_t HALT : 1; /*!< [ES1 only] Halts the divider counter. The intent is to allow
- the divider s clock source to be changed without the risk of
- a glitch at the output */
- __IO uint32_t REQFLAG : 1; /*!< [ES1 only] Divider status flag. Set when a change is made to
- the divider value, cleared when the change is complete */
- } ASYNCAPBCLKDIV_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t ASYNCCLKOVERRIDE; /*!< Asynchronous APB automatic clock gating override */
-
- struct {
- uint32_t : 15;
- __IO uint32_t ASYNCSYSREGBANK: 1; /*!< Override automatic clock gating of Asynchronous System Controller
- registers bank when set (i.e. always clock). Default setting
- (0) is to use clock gating. */
- __O uint32_t ENABLEUPDATE: 16; /*!< The value 0xC0DE must be written for ASYNCCLKOVERRIDE registers
- fields updates to have effect. */
- } ASYNCCLKOVERRIDE_b; /*!< BitSize */
- };
- __I uint32_t RESERVED3[28];
-
- union {
- __IO uint32_t TEMPSENSORCTRL; /*!< Temperature Sensor controls */
-
- struct {
- __IO uint32_t ENABLE : 1; /*!< Temperature sensor enable */
- __IO uint32_t SLOPE : 1; /*!< Temperature sensor sloe selection. 0x0: Unity gain slope. 0x1:
- Double gain slope. Only setting 0 should be used. */
- __IO uint32_t CM : 2; /*!< Temerature sensor common mode output voltage selection: 0x0:
- high negative offset added. 0x1: intermediate negative offset
- added. 0x2: no offset added. 0x3: low positive offset added.
- Only setting 0x2 should be used. */
- } TEMPSENSORCTRL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t NFCTAGPADSCTRL; /*!< NFC Tag pads control : I2C interface + 1 interrupt input pad */
-
- struct {
- __IO uint32_t I2C_SDA_EPD: 1; /*!< Enable weak pull down on IO pad */
- __IO uint32_t I2C_SDA_EPUN: 1; /*!< Enable weak pull up on IO pad, active low */
- __IO uint32_t I2C_SDA_EHS0: 1; /*!< Driver slew rate. */
- __IO uint32_t I2C_SDA_INVERT: 1; /*!< Input polarity. 0 : Input function is not inverted. 1 : Input
- function is inverted. */
- __IO uint32_t I2C_SDA_ENZI: 1; /*!< Receiver enable */
- __IO uint32_t I2C_SDA_FILTEROFF: 1; /*!< Controls input glitch filter 0 Filter enabled. Noise pulses
- below approximately 10 ns are filtered out. 1 Filter disabled.
- No input filtering is done. */
- __IO uint32_t I2C_SDA_EHS1: 1; /*!< Driver slew rate. */
- __IO uint32_t I2C_SDA_OD : 1; /*!< Controls open-drain mode. 0 Normal. Normal push-pull output
- 1 Open-drain. Simulated open-drain output (high drive disabled). */
- __IO uint32_t I2C_SCL_EPD: 1; /*!< Enable weak pull down on IO pad */
- __IO uint32_t I2C_SCL_EPUN: 1; /*!< Enable weak pull up on IO pad, active low */
- __IO uint32_t I2C_SCL_EHS0: 1; /*!< Driver slew rate. */
- __IO uint32_t I2C_SCL_INVERT: 1; /*!< Input polarity. 0 : Input function is not inverted. 1 : Input
- function is inverted. */
- __IO uint32_t I2C_SCL_ENZI: 1; /*!< Receiver enable */
- __IO uint32_t I2C_SCL_FILTEROFF: 1; /*!< Controls input glitch filter 0 Filter enabled. Noise pulses
- below approximately 10 ns are filtered out. 1 Filter disabled.
- No input filtering is done. */
- __IO uint32_t I2C_SCL_EHS1: 1; /*!< Driver slew rate. */
- __IO uint32_t I2C_SCL_OD : 1; /*!< Controls open-drain mode. 0 Normal. Normal push-pull output
- 1 Open-drain. Simulated open-drain output (high drive disabled). */
- __IO uint32_t INT_EPD : 1; /*!< Reserved. IO cell no longer supports pull-down */
- __IO uint32_t INT_EPUN : 1; /*!< Reserved. IO cell pull-up always on, not configurable */
- __IO uint32_t INT_INVERT : 1; /*!< Input polarity. 0 : Input function is not inverted. 1 : Input
- function is inverted. */
- __IO uint32_t INT_ENZI : 1; /*!< Reserved. IO cell always enabled, not configurable */
- __IO uint32_t INT_FILTEROFF: 1; /*!< Reserved. IO cell always filters signal, not configurable */
- __IO uint32_t VDD_EPD : 1; /*!< Enable weak pull down on IO pad */
- __IO uint32_t VDD_EPUN : 1; /*!< Enable weak pull up on IO pad, active low */
- __IO uint32_t VDD_EHS0 : 1; /*!< Driver slew rate. */
- __IO uint32_t VDD_INVERT : 1; /*!< Input polarity. 0 : Input function is not inverted. 1 : Input
- function is inverted. */
- __IO uint32_t VDD_ENZI : 1; /*!< Receiver enable */
- __IO uint32_t VDD_FILTEROFF: 1; /*!< Controls input glitch filter 0 Filter enabled. Noise pulses
- below approximately 10 ns are filtered out. 1 Filter disabled.
- No input filtering is done. */
- __IO uint32_t VDD_EHS1 : 1; /*!< Driver slew rate. */
- __IO uint32_t VDD_OD : 1; /*!< Controls open-drain mode. 0 Normal. Normal push-pull output
- 1 Open-drain. Simulated open-drain output (high drive disabled). */
- } NFCTAGPADSCTRL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t XTAL32MLDOCTRL; /*!< XTAL 32 MHz LDO control register. If XTAL has been auto started
- due to EFUSE XTAL32MSTART_ENA or BLE low power timers then the
- effect of these need disabling via SYSCON.XTAL32MCTRL before
- the full control by this register is possible. */
-
- struct {
- __IO uint32_t BYPASS : 1; /*!< Activate LDO bypass */
- __IO uint32_t ENABLE : 1; /*!< Enable the LDO */
- __IO uint32_t HIGHZ : 1; /*!< Put the output in high impedance state */
- __IO uint32_t VOUT : 3; /*!< Adjust the output voltage level */
- __IO uint32_t IBIAS : 2; /*!< Adjust the biasing current */
- __IO uint32_t STABMODE : 2; /*!< Stability configuration */
- } XTAL32MLDOCTRL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t XTAL32MCTRL; /*!< XTAL 32 MHz control register. If XTAL has been auto started
- due to EFUSE XTAL32MSTART_ENA or BLE low power timers then the
- effect of these need disabling via SYSCON.XTAL32MCTRL before
- the full control by this register is possible. */
-
- struct {
- __IO uint32_t XO_ACBUF_PASS_ENABLE: 1; /*!< Bypass enable of xo AC buffer enable in pll and top level */
- __IO uint32_t XO_AMP : 3; /*!< Amplitude selection , Min amp : 001, Max amp : 110 */
- __IO uint32_t XO_OSC_CAP_IN: 7; /*!< Tune cap in Xi */
- __IO uint32_t XO_OSC_CAP_OUT: 7; /*!< Tune cap in Xo */
- uint32_t : 4;
- __IO uint32_t XO_ENABLE : 1; /*!< Enable signal for xo */
- __IO uint32_t XO_GM : 3; /*!< Gm value for Xo */
- __IO uint32_t XO_SLAVE : 1; /*!< Xo in slave mode */
- __IO uint32_t XO_STANDALONE_ENABLE: 1; /*!< Reduce the current in XO in sleep mode */
- __IO uint32_t XO32M_TO_MCU_ENABLE: 1; /*!< Enable the 32MHz clock to MCU */
- __IO uint32_t CLK_TO_GPADC_ENABLE: 1; /*!< Enable the 16MHz clock to gpadc (pmu) */
- } XTAL32MCTRL_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t ANALOGID; /*!< Analog Interfaces (PMU and Radio) identity registers */
-
- struct {
- __I uint32_t PMUID : 6; /*!< PMU Identitty register [ES1 was 0x5] */
- __I uint32_t RADIOID : 6; /*!< Radio Identity register [ES2 not supported] */
- } ANALOGID_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t RADIOSTATUS; /*!< All Radio Analog modules status register. */
-
- struct {
- __I uint32_t PLLXOREADY : 1; /*!< (null) */
- } RADIOSTATUS_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t DIGITALSTATUS; /*!< All Digital modules global status register. */
-
- struct {
- __I uint32_t FLASHINITERROR: 1; /*!< Flash Init Error */
- } DIGITALSTATUS_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t DCBUSCTRL; /*!< DC Bus control registers */
-
- struct {
- __IO uint32_t ADDR : 9; /*!< (null) */
- __IO uint32_t MUX1 : 4; /*!< (null) */
- __IO uint32_t MUX2 : 4; /*!< (null) */
- } DCBUSCTRL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t FREQMECTRL; /*!< Frequency measure register */
-
- struct {
- __IO uint32_t CAPVAL_SCALE: 31; /*!< CAPVAL = FREQMECTRL[30:0] (Read-only) : Stores the target counter
- result from the last frequency measure activiation, this is
- used in the calculation of the unknown clock frequency of the
- reference or target clock. SCALE = FREQMECTRL[4:0] (Write-only)
- : define the count duration, (2^SCALE)-1, that reference counter
- counts to during measurement. Note that the value is 2 giving
- a minimum count 2^2-1 = 3. The result of freq_me_plus can be
- calculated as follows : freq_targetclk =freq_refclk* (CAPVAL+1)
- / ((2^S */
- __IO uint32_t PROG : 1; /*!< Set this bit to one to initiate a frequency measurement cycle.
- Hardware clears this bit when the measurement cycle has completed
- and there is valid capture data in the CAPVAL field (bits 13:0). */
- } FREQMECTRL_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t NFCTAGINTSTATUS; /*!< NFC Tag interrupt status register. */
-
- struct {
- __I uint32_t NFCTAGINT : 1; /*!< NFC Tag interrupt status bit. Reset when read. 0 : No interrupt
- has raised 1 : Interrupt has raised */
- } NFCTAGINTSTATUS_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t NFCTAG_VDD; /*!< NFCTAG VDD output control */
-
- struct {
- __IO uint32_t NFCTAG_VDD_OUT: 1; /*!< Output value for the NFC Tag Vdd IO, if enabled with NFCTAG_VDD_OE */
- __IO uint32_t NFCTAG_VDD_OE: 1; /*!< Output enable for the NFC Tag Vdd IO cell */
- } NFCTAG_VDD_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t SWRESETCTRL; /*!< Full IC reset request (from Software application). */
-
- struct {
- __O uint32_t ICRESETREQ : 1; /*!< IC reset request: 0 : No effect 1 : Request a fulll IC reset
- level reset */
- uint32_t : 15;
- __O uint32_t VECTKEY : 16; /*!< Register Key: On write, write 0x05FA to VECTKEY, otherwise the
- write is ignored. */
- } SWRESETCTRL_b; /*!< BitSize */
- };
-} u_async_syscon_Type;
-
-
-/* ================================================================================ */
-/* ================ u0_timer ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component ct32b It is standard 32-bit Counter/Timer with APB bus interface. More details will follow. (u0_timer)
- */
-
-typedef struct { /*!< u0_timer Structure */
-
- union {
- __IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts.
- The IR can be read to identify which of eight possible interrupt
- sources are pending. */
-
- struct {
- __IO uint32_t MR0INT : 1; /*!< Interrupt flag for match channel 0. */
- __IO uint32_t MR1INT : 1; /*!< Interrupt flag for match channel 1. */
- __IO uint32_t MR2INT : 1; /*!< Interrupt flag for match channel 2. */
- __IO uint32_t MR3INT : 1; /*!< Interrupt flag for match channel 3. */
- __IO uint32_t CR0INT : 1; /*!< Interrupt flag for capture channel 0 event. */
- __IO uint32_t CR1INT : 1; /*!< Interrupt flag for capture channel 1 event. */
- __IO uint32_t CR2INT : 1; /*!< Interrupt flag for capture channel 2 event. */
- __IO uint32_t CR3INT : 1; /*!< Interrupt flag for capture channel 3 event. */
- } IR_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer
- Counter functions. The Timer Counter can be disabled or reset
- through the TCR. */
-
- struct {
- __IO uint32_t CEN : 1; /*!< Counter enable. 0 Disabled.The counters are disabled. 1 Enabled.
- The Timer Counter and Prescale Counter are enabled. */
- __IO uint32_t CRST : 1; /*!< Counter reset. 0 Disabled. Do nothing. 1 Enabled. The Timer
- Counter and the Prescale Counter are synchronously reset on
- the next positive edge of the APB bus clock. The counters remain
- reset until TCR[1] is returned to zero. */
- } TCR_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t TC; /*!< Timer Counter. The 32 bit TC is incremented every PR+1 cycles
- of the APB bus clock. The TC is controlled through the TCR. */
-
- struct {
- __IO uint32_t TCVAL : 32; /*!< Timer counter value. */
- } TC_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PR; /*!< Prescale Register. When the Prescale Counter (PC) is equal to
- this value, the next clock increments the TC and clears the
- PC. */
-
- struct {
- __IO uint32_t PRVAL : 32; /*!< Prescale counter value. */
- } PR_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PC; /*!< Prescale Counter. The 32 bit PC is a counter which is incremented
- to the value stored in PR. When the value in PR is reached,
- the TC is incremented and the PC is cleared. The PC is observable
- and controllable through the bus interface. */
-
- struct {
- __IO uint32_t PCVAL : 32; /*!< Prescale counter value. */
- } PC_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt
- is generated and if the TC is reset when a Match occurs. */
-
- struct {
- __IO uint32_t MR0I : 1; /*!< Interrupt on MR0: an interrupt is generated when MR0 matches
- the value in the TC. 0 = disabled. 1 = enabled. */
- __IO uint32_t MR0R : 1; /*!< Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled.
- 1 = enabled. */
- __IO uint32_t MR0S : 1; /*!< Stop on MR0: the TC and PC will be stopped and TCR[0] will be
- set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled. */
- __IO uint32_t MR1I : 1; /*!< Interrupt on MR1: an interrupt is generated when MR1 matches
- the value in the TC. 0 = disabled. 1 = enabled. */
- __IO uint32_t MR1R : 1; /*!< Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled.
- 1 = enabled. */
- __IO uint32_t MR1S : 1; /*!< Stop on MR1: the TC and PC will be stopped and TCR[0] will be
- set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled. */
- __IO uint32_t MR2I : 1; /*!< Interrupt on MR2: an interrupt is generated when MR2 matches
- the value in the TC. 0 = disabled. 1 = enabled. */
- __IO uint32_t MR2R : 1; /*!< Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled.
- 1 = enabled. */
- __IO uint32_t MR2S : 1; /*!< Stop on MR2: the TC and PC will be stopped and TCR[0] will be
- set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled. */
- __IO uint32_t MR3I : 1; /*!< Interrupt on MR3: an interrupt is generated when MR3 matches
- the value in the TC. 0 = disabled. 1 = enabled. */
- __IO uint32_t MR3R : 1; /*!< Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled.
- 1 = enabled. */
- __IO uint32_t MR3S : 1; /*!< Stop on MR3: the TC and PC will be stopped and TCR[0] will be
- set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled. */
- } MCR_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t MR0; /*!< Match Register 0. MR0 can be enabled through the MCR to reset
- the TC, stop both the TC and PC, and/or generate an interrupt
- every time MR0 matches the TC. */
-
- struct {
- __IO uint32_t MATCH : 32; /*!< Timer counter match value. */
- } MR0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t MR1; /*!< Match Register 1. See MR0 description. */
-
- struct {
- __IO uint32_t MATCH : 32; /*!< Timer counter match value. */
- } MR1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t MR2; /*!< Match Register 2. See MR0 description. */
-
- struct {
- __IO uint32_t MATCH : 32; /*!< Timer counter match value. */
- } MR2_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t MR3; /*!< Match Register 3. See MR0 description. */
-
- struct {
- __IO uint32_t MATCH : 32; /*!< Timer counter match value. */
- } MR3_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the
- capture inputs are used to load the Capture Registers and whether
- or not an interrupt is generated when a capture takes place. */
-
- struct {
- __IO uint32_t CAP0RE : 1; /*!< Rising edge of capture channel 0: a sequence of 0 then 1 causes
- CR0 to be loaded with the contents of TC. 0 = disabled. 1 =
- enabled. */
- __IO uint32_t CAP0FE : 1; /*!< Falling edge of capture channel 0: a sequence of 1 then 0 causes
- CR0 to be loaded with the contents of TC. 0 = disabled. 1 =
- enabled. */
- __IO uint32_t CAP0I : 1; /*!< Generate interrupt on channel 0 capture event: a CR0 load generates
- an interrupt. */
- __IO uint32_t CAP1RE : 1; /*!< Rising edge of capture channel 1: a sequence of 0 then 1 causes
- CR1 to be loaded with the contents of TC. 0 = disabled. 1 =
- enabled. */
- __IO uint32_t CAP1FE : 1; /*!< Falling edge of capture channel 1: a sequence of 1 then 0 causes
- CR1 to be loaded with the contents of TC. 0 = disabled. 1 =
- enabled. */
- __IO uint32_t CAP1I : 1; /*!< Generate interrupt on channel 1 capture event: a CR1 load generates
- an interrupt. */
- __IO uint32_t CAP2RE : 1; /*!< Rising edge of capture channel 2: a sequence of 0 then 1 causes
- CR2 to be loaded with the contents of TC. 0 = disabled. 1 =
- enabled. */
- __IO uint32_t CAP2FE : 1; /*!< Falling edge of capture channel 2: a sequence of 1 then 0 causes
- CR2 to be loaded with the contents of TC. 0 = disabled. 1 =
- enabled. */
- __IO uint32_t CAP2I : 1; /*!< Generate interrupt on channel 2 capture event: a CR2 load generates
- an interrupt. */
- __IO uint32_t CAP3RE : 1; /*!< Rising edge of capture channel 3: a sequence of 0 then 1 causes
- CR3 to be loaded with the contents of TC. 0 = disabled. 1 =
- enabled. */
- __IO uint32_t CAP3FE : 1; /*!< Falling edge of capture channel 3: a sequence of 1 then 0 causes
- CR3 to be loaded with the contents of TC. 0 = disabled. 1 =
- enabled. */
- __IO uint32_t CAP3I : 1; /*!< Generate interrupt on channel 3 capture event: a CR3 load generates
- an interrupt. */
- } CCR_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t CR0; /*!< Capture Register 0. CR0 is loaded with the value of TC when
- there is an event on the CAPn.0 input. */
-
- struct {
- __I uint32_t CAP : 32; /*!< Timer counter capture value. */
- } CR0_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t CR1; /*!< Capture Register 1. See CR0 description. */
-
- struct {
- __I uint32_t CAP : 32; /*!< Timer counter capture value. */
- } CR1_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t CR2; /*!< Capture Register 2. See CR0 description. */
-
- struct {
- __I uint32_t CAP : 32; /*!< Timer counter capture value. */
- } CR2_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t CR3; /*!< Capture Register 3. See CR0 description. */
-
- struct {
- __I uint32_t CAP : 32; /*!< Timer counter capture value. */
- } CR3_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t EMR; /*!< External Match Register. The EMR controls the match function
- and the external match pins. */
-
- struct {
- __IO uint32_t EM0 : 1; /*!< External Match 0. This bit reflects the state of output MAT0,
- whether or not this output is connected to a pin. When a match
- occurs between the TC and MR0, this bit can either toggle, go
- LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit
- is driven to the MAT pins if the match function is selected
- via IOCON. 0 = LOW. 1 = HIGH. */
- __IO uint32_t EM1 : 1; /*!< External Match 1. This bit reflects the state of output MAT1,
- whether or not this output is connected to a pin. When a match
- occurs between the TC and MR1, this bit can either toggle, go
- LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit
- is driven to the MAT pins if the match function is selected
- via IOCON. 0 = LOW. 1 = HIGH. */
- __IO uint32_t EM2 : 1; /*!< External Match 2. This bit reflects the state of output MAT2,
- whether or not this output is connected to a pin. When a match
- occurs between the TC and MR2, this bit can either toggle, go
- LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit
- is driven to the MAT pins if the match function is selected
- via IOCON. 0 = LOW. 1 = HIGH */
- __IO uint32_t EM3 : 1; /*!< External Match 3. This bit reflects the state of output MAT3,
- whether or not this output is connected to a pin. When a match
- occurs between the TC and MR3, this bit can either toggle, go
- LOW, go HIGH, or do nothing, as selected by MR[11:10]. This
- bit is driven to the MAT pins if the match function is selected
- via IOCON. 0 = LOW. 1 = HIGH. */
- __IO uint32_t EMC0 : 2; /*!< External Match Control 0. Determines the functionality of External
- Match 0. 0x0 Do Nothing. 0x1 Clear. Clear the corresponding
- External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
- 0x2 Set. Set the corresponding External Match bit/output to
- 1 (MAT0 pin is HIGH if pinned out). 0x3 Toggle. Toggle the corresponding
- External Match bit/output. */
- __IO uint32_t EMC1 : 2; /*!< External Match Control 1. Determines the functionality of External
- Match 1. 0x0 Do Nothing. 0x1 Clear. Clear the corresponding
- External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
- 0x2 Set. Set the corresponding External Match bit/output to
- 1 (MAT1 pin is HIGH if pinned out). 0x3 Toggle. Toggle the corresponding
- External Match bit/output. */
- __IO uint32_t EMC2 : 2; /*!< External Match Control 2. Determines the functionality of External
- Match 2. 0x0 Do Nothing. 0x1 Clear. Clear the corresponding
- External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
- 0x2 Set. Set the corresponding External Match bit/output to
- 1 (MAT2 pin is HIGH if pinned out). 0x3 Toggle. Toggle the corresponding
- External Match bit/output. */
- __IO uint32_t EMC3 : 2; /*!< External Match Control 3. Determines the functionality of External
- Match 3. 0x0 Do Nothing. 0x1 Clear. Clear the corresponding
- External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
- 0x2 Set. Set the corresponding External Match bit/output to
- 1 (MAT3 pin is HIGH if pinned out). 0x3 Toggle. Toggle the corresponding
- External Match bit/output. */
- } EMR_b; /*!< BitSize */
- };
- __I uint32_t RESERVED0[12];
-
- union {
- __IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter
- mode, and in Counter mode selects the signal and edge(s) for
- counting. */
-
- struct {
- __IO uint32_t CTMODE : 2; /*!< Counter/Timer Mode This field selects which rising APB bus clock
- edges can increment Timer s Prescale Counter (PC), or clear
- PC and increment Timer Counter (TC). Timer Mode: the TC is incremented
- when the Prescale Counter matches the Prescale Register. 0x0
- Timer Mode. Incremented every rising APB bus clock edge. 0x1
- Counter Mode rising edge. TC is incremented on rising edges
- on the CAP input selected by bits 3:2. 0x2 Counter Mode falling
- edge. TC is incremented on falling edges on the CAP input selected
- by */
- __IO uint32_t CINSEL : 2; /*!< Count Input Select When bits 1:0 in this register are not 00,
- these bits select which CAP pin is sampled for clocking. Note:
- If Counter mode is selected for a particular CAPn input in the
- CTCR, the 3 bits for that input in the Capture Control Register
- (CCR) must be programmed as 000. However, capture and/or interrupt
- can be selected for the other 3 CAPn inputs in the same timer.
- 0x0 Channel 0. CAPn.0 for CT32Bn 0x1 Channel 1. CAPn.1 for CT32Bn
- 0x2 Channel 2. CAPn.2 for CT32Bn 0x3 Channel 3. CAPn.3 for CT32 */
- __IO uint32_t ENCC : 1; /*!< Setting this bit to 1 enables clearing of the timer and the
- prescaler when the capture-edge event specified in bits 7:5
- occurs. */
- __IO uint32_t SELCC : 3; /*!< Edge select. When bit 4 is 1, these bits select which capture
- input edge will cause the timer and prescaler to be cleared.
- These bits have no effect when bit 4 is low. Values 0x2 to 0x3
- and 0x6 to 0x7 are reserved. 0 0x0 Channel 0 Rising Edge. Rising
- edge of the signal on capture channel 0 clears the timer (if
- bit 4 is set). 0x1 Channel 0 Falling Edge. Falling edge of the
- signal on capture channel 0 clears the timer (if bit 4 is set).
- 0x2 Channel 1 Rising Edge. Rising edge of the signal on capture
- channel */
- } CTCR_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PWMC; /*!< PWM Control Register. The PWMCON enables PWM mode for the external
- match pins. */
-
- struct {
- __IO uint32_t PWMEN0 : 1; /*!< PWM mode enable for channel0. 0 Match. CT32Bn_MAT0 is controlled
- by EM0. 1 PWM. PWM mode is enabled for CT32Bn_MAT0. */
- __IO uint32_t PWMEN1 : 1; /*!< PWM mode enable for channel1. 0 Match. CT32Bn_MAT01 is controlled
- by EM1. 1 PWM. PWM mode is enabled for CT32Bn_MAT1. */
- __IO uint32_t PWMEN2 : 1; /*!< PWM mode enable for channel2. 0 Match. CT32Bn_MAT2 is controlled
- by EM2. 1 PWM. PWM mode is enabled for CT32Bn_MAT2. */
- __IO uint32_t PWMEN3 : 1; /*!< PWM mode enable for channel3. Note: It is recommended to use
- match channel 3 to set the PWM cycle. 0 Match. CT32Bn_MAT3 is
- controlled by EM3. 1 PWM. PWM mode is enabled for CT132Bn_MAT3 */
- } PWMC_b; /*!< BitSize */
- };
-} u0_timer_Type;
-
-
-/* ================================================================================ */
-/* ================ u1_timer ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component ct32b It is standard 32-bit Counter/Timer with APB bus interface. More details will follow. (u1_timer)
- */
-
-typedef struct { /*!< u1_timer Structure */
-
- union {
- __IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts.
- The IR can be read to identify which of eight possible interrupt
- sources are pending. */
-
- struct {
- __IO uint32_t MR0INT : 1; /*!< Interrupt flag for match channel 0. */
- __IO uint32_t MR1INT : 1; /*!< Interrupt flag for match channel 1. */
- __IO uint32_t MR2INT : 1; /*!< Interrupt flag for match channel 2. */
- __IO uint32_t MR3INT : 1; /*!< Interrupt flag for match channel 3. */
- __IO uint32_t CR0INT : 1; /*!< Interrupt flag for capture channel 0 event. */
- __IO uint32_t CR1INT : 1; /*!< Interrupt flag for capture channel 1 event. */
- __IO uint32_t CR2INT : 1; /*!< Interrupt flag for capture channel 2 event. */
- __IO uint32_t CR3INT : 1; /*!< Interrupt flag for capture channel 3 event. */
- } IR_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer
- Counter functions. The Timer Counter can be disabled or reset
- through the TCR. */
-
- struct {
- __IO uint32_t CEN : 1; /*!< Counter enable. 0 Disabled.The counters are disabled. 1 Enabled.
- The Timer Counter and Prescale Counter are enabled. */
- __IO uint32_t CRST : 1; /*!< Counter reset. 0 Disabled. Do nothing. 1 Enabled. The Timer
- Counter and the Prescale Counter are synchronously reset on
- the next positive edge of the APB bus clock. The counters remain
- reset until TCR[1] is returned to zero. */
- } TCR_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t TC; /*!< Timer Counter. The 32 bit TC is incremented every PR+1 cycles
- of the APB bus clock. The TC is controlled through the TCR. */
-
- struct {
- __IO uint32_t TCVAL : 32; /*!< Timer counter value. */
- } TC_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PR; /*!< Prescale Register. When the Prescale Counter (PC) is equal to
- this value, the next clock increments the TC and clears the
- PC. */
-
- struct {
- __IO uint32_t PRVAL : 32; /*!< Prescale counter value. */
- } PR_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PC; /*!< Prescale Counter. The 32 bit PC is a counter which is incremented
- to the value stored in PR. When the value in PR is reached,
- the TC is incremented and the PC is cleared. The PC is observable
- and controllable through the bus interface. */
-
- struct {
- __IO uint32_t PCVAL : 32; /*!< Prescale counter value. */
- } PC_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt
- is generated and if the TC is reset when a Match occurs. */
-
- struct {
- __IO uint32_t MR0I : 1; /*!< Interrupt on MR0: an interrupt is generated when MR0 matches
- the value in the TC. 0 = disabled. 1 = enabled. */
- __IO uint32_t MR0R : 1; /*!< Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled.
- 1 = enabled. */
- __IO uint32_t MR0S : 1; /*!< Stop on MR0: the TC and PC will be stopped and TCR[0] will be
- set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled. */
- __IO uint32_t MR1I : 1; /*!< Interrupt on MR1: an interrupt is generated when MR1 matches
- the value in the TC. 0 = disabled. 1 = enabled. */
- __IO uint32_t MR1R : 1; /*!< Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled.
- 1 = enabled. */
- __IO uint32_t MR1S : 1; /*!< Stop on MR1: the TC and PC will be stopped and TCR[0] will be
- set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled. */
- __IO uint32_t MR2I : 1; /*!< Interrupt on MR2: an interrupt is generated when MR2 matches
- the value in the TC. 0 = disabled. 1 = enabled. */
- __IO uint32_t MR2R : 1; /*!< Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled.
- 1 = enabled. */
- __IO uint32_t MR2S : 1; /*!< Stop on MR2: the TC and PC will be stopped and TCR[0] will be
- set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled. */
- __IO uint32_t MR3I : 1; /*!< Interrupt on MR3: an interrupt is generated when MR3 matches
- the value in the TC. 0 = disabled. 1 = enabled. */
- __IO uint32_t MR3R : 1; /*!< Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled.
- 1 = enabled. */
- __IO uint32_t MR3S : 1; /*!< Stop on MR3: the TC and PC will be stopped and TCR[0] will be
- set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled. */
- } MCR_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t MR0; /*!< Match Register 0. MR0 can be enabled through the MCR to reset
- the TC, stop both the TC and PC, and/or generate an interrupt
- every time MR0 matches the TC. */
-
- struct {
- __IO uint32_t MATCH : 32; /*!< Timer counter match value. */
- } MR0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t MR1; /*!< Match Register 1. See MR0 description. */
-
- struct {
- __IO uint32_t MATCH : 32; /*!< Timer counter match value. */
- } MR1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t MR2; /*!< Match Register 2. See MR0 description. */
-
- struct {
- __IO uint32_t MATCH : 32; /*!< Timer counter match value. */
- } MR2_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t MR3; /*!< Match Register 3. See MR0 description. */
-
- struct {
- __IO uint32_t MATCH : 32; /*!< Timer counter match value. */
- } MR3_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the
- capture inputs are used to load the Capture Registers and whether
- or not an interrupt is generated when a capture takes place. */
-
- struct {
- __IO uint32_t CAP0RE : 1; /*!< Rising edge of capture channel 0: a sequence of 0 then 1 causes
- CR0 to be loaded with the contents of TC. 0 = disabled. 1 =
- enabled. */
- __IO uint32_t CAP0FE : 1; /*!< Falling edge of capture channel 0: a sequence of 1 then 0 causes
- CR0 to be loaded with the contents of TC. 0 = disabled. 1 =
- enabled. */
- __IO uint32_t CAP0I : 1; /*!< Generate interrupt on channel 0 capture event: a CR0 load generates
- an interrupt. */
- __IO uint32_t CAP1RE : 1; /*!< Rising edge of capture channel 1: a sequence of 0 then 1 causes
- CR1 to be loaded with the contents of TC. 0 = disabled. 1 =
- enabled. */
- __IO uint32_t CAP1FE : 1; /*!< Falling edge of capture channel 1: a sequence of 1 then 0 causes
- CR1 to be loaded with the contents of TC. 0 = disabled. 1 =
- enabled. */
- __IO uint32_t CAP1I : 1; /*!< Generate interrupt on channel 1 capture event: a CR1 load generates
- an interrupt. */
- __IO uint32_t CAP2RE : 1; /*!< Rising edge of capture channel 2: a sequence of 0 then 1 causes
- CR2 to be loaded with the contents of TC. 0 = disabled. 1 =
- enabled. */
- __IO uint32_t CAP2FE : 1; /*!< Falling edge of capture channel 2: a sequence of 1 then 0 causes
- CR2 to be loaded with the contents of TC. 0 = disabled. 1 =
- enabled. */
- __IO uint32_t CAP2I : 1; /*!< Generate interrupt on channel 2 capture event: a CR2 load generates
- an interrupt. */
- __IO uint32_t CAP3RE : 1; /*!< Rising edge of capture channel 3: a sequence of 0 then 1 causes
- CR3 to be loaded with the contents of TC. 0 = disabled. 1 =
- enabled. */
- __IO uint32_t CAP3FE : 1; /*!< Falling edge of capture channel 3: a sequence of 1 then 0 causes
- CR3 to be loaded with the contents of TC. 0 = disabled. 1 =
- enabled. */
- __IO uint32_t CAP3I : 1; /*!< Generate interrupt on channel 3 capture event: a CR3 load generates
- an interrupt. */
- } CCR_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t CR0; /*!< Capture Register 0. CR0 is loaded with the value of TC when
- there is an event on the CAPn.0 input. */
-
- struct {
- __I uint32_t CAP : 32; /*!< Timer counter capture value. */
- } CR0_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t CR1; /*!< Capture Register 1. See CR0 description. */
-
- struct {
- __I uint32_t CAP : 32; /*!< Timer counter capture value. */
- } CR1_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t CR2; /*!< Capture Register 2. See CR0 description. */
-
- struct {
- __I uint32_t CAP : 32; /*!< Timer counter capture value. */
- } CR2_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t CR3; /*!< Capture Register 3. See CR0 description. */
-
- struct {
- __I uint32_t CAP : 32; /*!< Timer counter capture value. */
- } CR3_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t EMR; /*!< External Match Register. The EMR controls the match function
- and the external match pins. */
-
- struct {
- __IO uint32_t EM0 : 1; /*!< External Match 0. This bit reflects the state of output MAT0,
- whether or not this output is connected to a pin. When a match
- occurs between the TC and MR0, this bit can either toggle, go
- LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit
- is driven to the MAT pins if the match function is selected
- via IOCON. 0 = LOW. 1 = HIGH. */
- __IO uint32_t EM1 : 1; /*!< External Match 1. This bit reflects the state of output MAT1,
- whether or not this output is connected to a pin. When a match
- occurs between the TC and MR1, this bit can either toggle, go
- LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit
- is driven to the MAT pins if the match function is selected
- via IOCON. 0 = LOW. 1 = HIGH. */
- __IO uint32_t EM2 : 1; /*!< External Match 2. This bit reflects the state of output MAT2,
- whether or not this output is connected to a pin. When a match
- occurs between the TC and MR2, this bit can either toggle, go
- LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit
- is driven to the MAT pins if the match function is selected
- via IOCON. 0 = LOW. 1 = HIGH */
- __IO uint32_t EM3 : 1; /*!< External Match 3. This bit reflects the state of output MAT3,
- whether or not this output is connected to a pin. When a match
- occurs between the TC and MR3, this bit can either toggle, go
- LOW, go HIGH, or do nothing, as selected by MR[11:10]. This
- bit is driven to the MAT pins if the match function is selected
- via IOCON. 0 = LOW. 1 = HIGH. */
- __IO uint32_t EMC0 : 2; /*!< External Match Control 0. Determines the functionality of External
- Match 0. 0x0 Do Nothing. 0x1 Clear. Clear the corresponding
- External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
- 0x2 Set. Set the corresponding External Match bit/output to
- 1 (MAT0 pin is HIGH if pinned out). 0x3 Toggle. Toggle the corresponding
- External Match bit/output. */
- __IO uint32_t EMC1 : 2; /*!< External Match Control 1. Determines the functionality of External
- Match 1. 0x0 Do Nothing. 0x1 Clear. Clear the corresponding
- External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
- 0x2 Set. Set the corresponding External Match bit/output to
- 1 (MAT1 pin is HIGH if pinned out). 0x3 Toggle. Toggle the corresponding
- External Match bit/output. */
- __IO uint32_t EMC2 : 2; /*!< External Match Control 2. Determines the functionality of External
- Match 2. 0x0 Do Nothing. 0x1 Clear. Clear the corresponding
- External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
- 0x2 Set. Set the corresponding External Match bit/output to
- 1 (MAT2 pin is HIGH if pinned out). 0x3 Toggle. Toggle the corresponding
- External Match bit/output. */
- __IO uint32_t EMC3 : 2; /*!< External Match Control 3. Determines the functionality of External
- Match 3. 0x0 Do Nothing. 0x1 Clear. Clear the corresponding
- External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
- 0x2 Set. Set the corresponding External Match bit/output to
- 1 (MAT3 pin is HIGH if pinned out). 0x3 Toggle. Toggle the corresponding
- External Match bit/output. */
- } EMR_b; /*!< BitSize */
- };
- __I uint32_t RESERVED0[12];
-
- union {
- __IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter
- mode, and in Counter mode selects the signal and edge(s) for
- counting. */
-
- struct {
- __IO uint32_t CTMODE : 2; /*!< Counter/Timer Mode This field selects which rising APB bus clock
- edges can increment Timer s Prescale Counter (PC), or clear
- PC and increment Timer Counter (TC). Timer Mode: the TC is incremented
- when the Prescale Counter matches the Prescale Register. 0x0
- Timer Mode. Incremented every rising APB bus clock edge. 0x1
- Counter Mode rising edge. TC is incremented on rising edges
- on the CAP input selected by bits 3:2. 0x2 Counter Mode falling
- edge. TC is incremented on falling edges on the CAP input selected
- by */
- __IO uint32_t CINSEL : 2; /*!< Count Input Select When bits 1:0 in this register are not 00,
- these bits select which CAP pin is sampled for clocking. Note:
- If Counter mode is selected for a particular CAPn input in the
- CTCR, the 3 bits for that input in the Capture Control Register
- (CCR) must be programmed as 000. However, capture and/or interrupt
- can be selected for the other 3 CAPn inputs in the same timer.
- 0x0 Channel 0. CAPn.0 for CT32Bn 0x1 Channel 1. CAPn.1 for CT32Bn
- 0x2 Channel 2. CAPn.2 for CT32Bn 0x3 Channel 3. CAPn.3 for CT32 */
- __IO uint32_t ENCC : 1; /*!< Setting this bit to 1 enables clearing of the timer and the
- prescaler when the capture-edge event specified in bits 7:5
- occurs. */
- __IO uint32_t SELCC : 3; /*!< Edge select. When bit 4 is 1, these bits select which capture
- input edge will cause the timer and prescaler to be cleared.
- These bits have no effect when bit 4 is low. Values 0x2 to 0x3
- and 0x6 to 0x7 are reserved. 0 0x0 Channel 0 Rising Edge. Rising
- edge of the signal on capture channel 0 clears the timer (if
- bit 4 is set). 0x1 Channel 0 Falling Edge. Falling edge of the
- signal on capture channel 0 clears the timer (if bit 4 is set).
- 0x2 Channel 1 Rising Edge. Rising edge of the signal on capture
- channel */
- } CTCR_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PWMC; /*!< PWM Control Register. The PWMCON enables PWM mode for the external
- match pins. */
-
- struct {
- __IO uint32_t PWMEN0 : 1; /*!< PWM mode enable for channel0. 0 Match. CT32Bn_MAT0 is controlled
- by EM0. 1 PWM. PWM mode is enabled for CT32Bn_MAT0. */
- __IO uint32_t PWMEN1 : 1; /*!< PWM mode enable for channel1. 0 Match. CT32Bn_MAT01 is controlled
- by EM1. 1 PWM. PWM mode is enabled for CT32Bn_MAT1. */
- __IO uint32_t PWMEN2 : 1; /*!< PWM mode enable for channel2. 0 Match. CT32Bn_MAT2 is controlled
- by EM2. 1 PWM. PWM mode is enabled for CT32Bn_MAT2. */
- __IO uint32_t PWMEN3 : 1; /*!< PWM mode enable for channel3. Note: It is recommended to use
- match channel 3 to set the PWM cycle. 0 Match. CT32Bn_MAT3 is
- controlled by EM3. 1 PWM. PWM mode is enabled for CT132Bn_MAT3 */
- } PWMC_b; /*!< BitSize */
- };
-} u1_timer_Type;
-
-
-/* ================================================================================ */
-/* ================ u_gpio ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component gpio It is General Purpose I/O with APB bus interface. More details will follow. (u_gpio)
- */
-
-typedef struct { /*!< u_gpio Structure */
-
- union {
- __IO uint8_t B[22]; /*!< Byte pin registers Read 0: pin PIOn is LOW. Write 0: clear output
- bit. Read 0x01: pin PIOn is HIGH. Write any value 0x01 to 0xFF:
- set output bit. Remark: Only 0 or 0xFF can be read. Writing
- any value other than 0 will set the output bit. Supported pins
- depends on the specific device and package. Reset values reflects
- the state of pin given by the relevant bit of PIN reset value */
-
- struct {
- __IO uint8_t B : 8; /*!< Byte pin registers Read 0: pin PIOn is LOW. Write 0: clear output
- bit. Read 0x01: pin PIOn is HIGH. Write any value 0x01 to 0xFF:
- set output bit. Remark: Only 0 or 0xFF can be read. Writing
- any value other than 0 will set the output bit. Supported pins
- depends on the specific device and package. Reset values reflects
- the state of pin given by the relevant bit of PIN reset value */
- } B_b[22]; /*!< BitSize */
- };
- __I uint16_t RESERVED0[2037];
-
- union {
- __IO uint32_t W[22]; /*!< Word pin registers Read 0: pin PIOn is LOW. Write 0: clear output
- bit. Read 0xFFFF FFFF: pin PIOn is HIGH. Write any value 0x0000
- 0001 to 0xFFFF FFFF: set output bit. Remark: Only 0 or 0xFFFF
- FFFF can be read. Writing any value other than 0 will set the
- output bit. Supported pins depends on the specific device and
- package. Reset values reflects the state of pin given by the
- relevant bit of PIN reset value */
-
- struct {
- __IO uint32_t W : 32; /*!< Word pin registers Read 0: pin PIOn is LOW. Write 0: clear output
- bit. Read 0xFFFF FFFF: pin PIOn is HIGH. Write any value 0x0000
- 0001 to 0xFFFF FFFF: set output bit. Remark: Only 0 or 0xFFFF
- FFFF can be read. Writing any value other than 0 will set the
- output bit. Supported pins depends on the specific device and
- package. Reset values reflects the state of pin given by the
- relevant bit of PIN reset value */
- } W_b[22]; /*!< BitSize */
- };
- __I uint32_t RESERVED1[1002];
-
- union {
- __IO uint32_t DIR; /*!< Direction register */
-
- struct {
- __IO uint32_t DIRP_PIO0 : 1; /*!< Selects pin direction for pin PIO0 . 0 = input. 1 = output. */
- __IO uint32_t DIRP_PIO1 : 1; /*!< Selects pin direction for pin PIO1 . 0 = input. 1 = output. */
- __IO uint32_t DIRP_PIO2 : 1; /*!< Selects pin direction for pin PIO2 . 0 = input. 1 = output. */
- __IO uint32_t DIRP_PIO3 : 1; /*!< Selects pin direction for pin PIO3 . 0 = input. 1 = output. */
- __IO uint32_t DIRP_PIO4 : 1; /*!< Selects pin direction for pin PIO4 . 0 = input. 1 = output. */
- __IO uint32_t DIRP_PIO5 : 1; /*!< Selects pin direction for pin PIO5 . 0 = input. 1 = output. */
- __IO uint32_t DIRP_PIO6 : 1; /*!< Selects pin direction for pin PIO6 . 0 = input. 1 = output. */
- __IO uint32_t DIRP_PIO7 : 1; /*!< Selects pin direction for pin PIO7 . 0 = input. 1 = output. */
- __IO uint32_t DIRP_PIO8 : 1; /*!< Selects pin direction for pin PIO8 . 0 = input. 1 = output. */
- __IO uint32_t DIRP_PIO9 : 1; /*!< Selects pin direction for pin PIO9 . 0 = input. 1 = output. */
- __IO uint32_t DIRP_PIO10 : 1; /*!< Selects pin direction for pin PIO10 . 0 = input. 1 = output. */
- __IO uint32_t DIRP_PIO11 : 1; /*!< Selects pin direction for pin PIO11 . 0 = input. 1 = output. */
- __IO uint32_t DIRP_PIO12 : 1; /*!< Selects pin direction for pin PIO12 . 0 = input. 1 = output. */
- __IO uint32_t DIRP_PIO13 : 1; /*!< Selects pin direction for pin PIO13 . 0 = input. 1 = output. */
- __IO uint32_t DIRP_PIO14 : 1; /*!< Selects pin direction for pin PIO14 . 0 = input. 1 = output. */
- __IO uint32_t DIRP_PIO15 : 1; /*!< Selects pin direction for pin PIO15 . 0 = input. 1 = output. */
- __IO uint32_t DIRP_PIO16 : 1; /*!< Selects pin direction for pin PIO16 . 0 = input. 1 = output. */
- __IO uint32_t DIRP_PIO17 : 1; /*!< Selects pin direction for pin PIO17 . 0 = input. 1 = output. */
- __IO uint32_t DIRP_PIO18 : 1; /*!< Selects pin direction for pin PIO18 . 0 = input. 1 = output. */
- __IO uint32_t DIRP_PIO19 : 1; /*!< Selects pin direction for pin PIO19 . 0 = input. 1 = output. */
- __IO uint32_t DIRP_PIO20 : 1; /*!< Selects pin direction for pin PIO20 . 0 = input. 1 = output. */
- __IO uint32_t DIRP_PIO21 : 1; /*!< Selects pin direction for pin PIO21 . 0 = input. 1 = output. */
- } DIR_b; /*!< BitSize */
- };
- __I uint32_t RESERVED2[31];
-
- union {
- __IO uint32_t MASK; /*!< Mask register */
-
- struct {
- __IO uint32_t MASKP_PIO0 : 1; /*!< Controls if PIO0 is active in MPIN register MPIN register. 0
- = Read MPIN: pin state; write MPIN: load output bit. 1 = Read
- MPIN: 0; write MPIN: output bit not affected. */
- __IO uint32_t MASKP_PIO1 : 1; /*!< Controls if PIO1 is active in MPIN register MPIN register. 0
- = Read MPIN: pin state; write MPIN: load output bit. 1 = Read
- MPIN: 0; write MPIN: output bit not affected. */
- __IO uint32_t MASKP_PIO2 : 1; /*!< Controls if PIO2 is active in MPIN register MPIN register. 0
- = Read MPIN: pin state; write MPIN: load output bit. 1 = Read
- MPIN: 0; write MPIN: output bit not affected. */
- __IO uint32_t MASKP_PIO3 : 1; /*!< Controls if PIO3 is active in MPIN register MPIN register. 0
- = Read MPIN: pin state; write MPIN: load output bit. 1 = Read
- MPIN: 0; write MPIN: output bit not affected. */
- __IO uint32_t MASKP_PIO4 : 1; /*!< Controls if PIO4 is active in MPIN register MPIN register. 0
- = Read MPIN: pin state; write MPIN: load output bit. 1 = Read
- MPIN: 0; write MPIN: output bit not affected. */
- __IO uint32_t MASKP_PIO5 : 1; /*!< Controls if PIO5 is active in MPIN register MPIN register. 0
- = Read MPIN: pin state; write MPIN: load output bit. 1 = Read
- MPIN: 0; write MPIN: output bit not affected. */
- __IO uint32_t MASKP_PIO6 : 1; /*!< Controls if PIO6 is active in MPIN register MPIN register. 0
- = Read MPIN: pin state; write MPIN: load output bit. 1 = Read
- MPIN: 0; write MPIN: output bit not affected. */
- __IO uint32_t MASKP_PIO7 : 1; /*!< Controls if PIO7 is active in MPIN register MPIN register. 0
- = Read MPIN: pin state; write MPIN: load output bit. 1 = Read
- MPIN: 0; write MPIN: output bit not affected. */
- __IO uint32_t MASKP_PIO8 : 1; /*!< Controls if PIO8 is active in MPIN register MPIN register. 0
- = Read MPIN: pin state; write MPIN: load output bit. 1 = Read
- MPIN: 0; write MPIN: output bit not affected. */
- __IO uint32_t MASKP_PIO9 : 1; /*!< Controls if PIO9 is active in MPIN register MPIN register. 0
- = Read MPIN: pin state; write MPIN: load output bit. 1 = Read
- MPIN: 0; write MPIN: output bit not affected. */
- __IO uint32_t MASKP_PIO10: 1; /*!< Controls if PIO10 is active in MPIN register MPIN register.
- 0 = Read MPIN: pin state; write MPIN: load output bit. 1 = Read
- MPIN: 0; write MPIN: output bit not affected. */
- __IO uint32_t MASKP_PIO11: 1; /*!< Controls if PIO11 is active in MPIN register MPIN register.
- 0 = Read MPIN: pin state; write MPIN: load output bit. 1 = Read
- MPIN: 0; write MPIN: output bit not affected. */
- __IO uint32_t MASKP_PIO12: 1; /*!< Controls if PIO12 is active in MPIN register MPIN register.
- 0 = Read MPIN: pin state; write MPIN: load output bit. 1 = Read
- MPIN: 0; write MPIN: output bit not affected. */
- __IO uint32_t MASKP_PIO13: 1; /*!< Controls if PIO13 is active in MPIN register MPIN register.
- 0 = Read MPIN: pin state; write MPIN: load output bit. 1 = Read
- MPIN: 0; write MPIN: output bit not affected. */
- __IO uint32_t MASKP_PIO14: 1; /*!< Controls if PIO14 is active in MPIN register MPIN register.
- 0 = Read MPIN: pin state; write MPIN: load output bit. 1 = Read
- MPIN: 0; write MPIN: output bit not affected. */
- __IO uint32_t MASKP_PIO15: 1; /*!< Controls if PIO150 is active in MPIN register MPIN register.
- 0 = Read MPIN: pin state; write MPIN: load output bit. 1 = Read
- MPIN: 0; write MPIN: output bit not affected. */
- __IO uint32_t MASKP_PIO16: 1; /*!< Controls if PIO16 is active in MPIN register MPIN register.
- 0 = Read MPIN: pin state; write MPIN: load output bit. 1 = Read
- MPIN: 0; write MPIN: output bit not affected. */
- __IO uint32_t MASKP_PIO17: 1; /*!< Controls if PIO17 is active in MPIN register MPIN register.
- 0 = Read MPIN: pin state; write MPIN: load output bit. 1 = Read
- MPIN: 0; write MPIN: output bit not affected. */
- __IO uint32_t MASKP_PIO18: 1; /*!< Controls if PIO18 is active in MPIN register MPIN register.
- 0 = Read MPIN: pin state; write MPIN: load output bit. 1 = Read
- MPIN: 0; write MPIN: output bit not affected. */
- __IO uint32_t MASKP_PIO19: 1; /*!< Controls if PIO19 is active in MPIN register MPIN register.
- 0 = Read MPIN: pin state; write MPIN: load output bit. 1 = Read
- MPIN: 0; write MPIN: output bit not affected. */
- __IO uint32_t MASKP_PIO20: 1; /*!< Controls if PIO20 is active in MPIN register MPIN register.
- 0 = Read MPIN: pin state; write MPIN: load output bit. 1 = Read
- MPIN: 0; write MPIN: output bit not affected. */
- __IO uint32_t MASKP_PIO21: 1; /*!< Controls if PIO21 is active in MPIN register MPIN register.
- 0 = Read MPIN: pin state; write MPIN: load output bit. 1 = Read
- MPIN: 0; write MPIN: output bit not affected. */
- } MASK_b; /*!< BitSize */
- };
- __I uint32_t RESERVED3[31];
-
- union {
- __IO uint32_t PIN; /*!< Pin register */
-
- struct {
- __IO uint32_t PORT_PIO0 : 1; /*!< Reads pin states or loads output bits. 0 = Read: pin is low;
- write: clear output bit. 1 = Read: pin is high; write: set output
- bit. */
- __IO uint32_t PORT_PIO1 : 1; /*!< Reads pin states or loads output bits. 0 = Read: pin is low;
- write: clear output bit. 1 = Read: pin is high; write: set output
- bit. */
- __IO uint32_t PORT_PIO2 : 1; /*!< Reads pin states or loads output bits. 0 = Read: pin is low;
- write: clear output bit. 1 = Read: pin is high; write: set output
- bit. */
- __IO uint32_t PORT_PIO3 : 1; /*!< Reads pin states or loads output bits. 0 = Read: pin is low;
- write: clear output bit. 1 = Read: pin is high; write: set output
- bit. */
- __IO uint32_t PORT_PIO4 : 1; /*!< Reads pin states or loads output bits. 0 = Read: pin is low;
- write: clear output bit. 1 = Read: pin is high; write: set output
- bit. */
- __IO uint32_t PORT_PIO5 : 1; /*!< Reads pin states or loads output bits. 0 = Read: pin is low;
- write: clear output bit. 1 = Read: pin is high; write: set output
- bit. */
- __IO uint32_t PORT_PIO6 : 1; /*!< Reads pin states or loads output bits. 0 = Read: pin is low;
- write: clear output bit. 1 = Read: pin is high; write: set output
- bit. */
- __IO uint32_t PORT_PIO7 : 1; /*!< Reads pin states or loads output bits. 0 = Read: pin is low;
- write: clear output bit. 1 = Read: pin is high; write: set output
- bit. */
- __IO uint32_t PORT_PIO8 : 1; /*!< Reads pin states or loads output bits. 0 = Read: pin is low;
- write: clear output bit. 1 = Read: pin is high; write: set output
- bit. */
- __IO uint32_t PORT_PIO9 : 1; /*!< Reads pin states or loads output bits. 0 = Read: pin is low;
- write: clear output bit. 1 = Read: pin is high; write: set output
- bit. */
- __IO uint32_t PORT_PIO10 : 1; /*!< Reads pin states or loads output bits. 0 = Read: pin is low;
- write: clear output bit. 1 = Read: pin is high; write: set output
- bit. */
- __IO uint32_t PORT_PIO11 : 1; /*!< Reads pin states or loads output bits. 0 = Read: pin is low;
- write: clear output bit. 1 = Read: pin is high; write: set output
- bit. */
- __IO uint32_t PORT_PIO12 : 1; /*!< Reads pin states or loads output bits. 0 = Read: pin is low;
- write: clear output bit. 1 = Read: pin is high; write: set output
- bit. */
- __IO uint32_t PORT_PIO13 : 1; /*!< Reads pin states or loads output bits. 0 = Read: pin is low;
- write: clear output bit. 1 = Read: pin is high; write: set output
- bit. */
- __IO uint32_t PORT_PIO14 : 1; /*!< Reads pin states or loads output bits. 0 = Read: pin is low;
- write: clear output bit. 1 = Read: pin is high; write: set output
- bit. */
- __IO uint32_t PORT_PIO15 : 1; /*!< Reads pin states or loads output bits. 0 = Read: pin is low;
- write: clear output bit. 1 = Read: pin is high; write: set output
- bit. */
- __IO uint32_t PORT_PIO16 : 1; /*!< Reads pin states or loads output bits. 0 = Read: pin is low;
- write: clear output bit. 1 = Read: pin is high; write: set output
- bit. */
- __IO uint32_t PORT_PIO17 : 1; /*!< Reads pin states or loads output bits. 0 = Read: pin is low;
- write: clear output bit. 1 = Read: pin is high; write: set output
- bit. */
- __IO uint32_t PORT_PIO18 : 1; /*!< Reads pin states or loads output bits. 0 = Read: pin is low;
- write: clear output bit. 1 = Read: pin is high; write: set output
- bit. */
- __IO uint32_t PORT_PIO19 : 1; /*!< Reads pin states or loads output bits. 0 = Read: pin is low;
- write: clear output bit. 1 = Read: pin is high; write: set output
- bit. */
- __IO uint32_t PORT_PIO20 : 1; /*!< Reads pin states or loads output bits. 0 = Read: pin is low;
- write: clear output bit. 1 = Read: pin is high; write: set output
- bit. */
- __IO uint32_t PORT_PIO21 : 1; /*!< Reads pin states or loads output bits. 0 = Read: pin is low;
- write: clear output bit. 1 = Read: pin is high; write: set output
- bit. */
- } PIN_b; /*!< BitSize */
- };
- __I uint32_t RESERVED4[31];
-
- union {
- __IO uint32_t MPIN; /*!< Masked Pin register */
-
- struct {
- __IO uint32_t MPORT_PIO0 : 1; /*!< Masked pin register. 0 = Read: pin is LOW and/or the corresponding
- bit in the MASK register is 1; write: clear output bit if the
- corresponding bit in the MASK register is 0. 1 = Read: pin is
- HIGH and the corresponding bit in the MASK register is 0; write:
- set output bit if the corresponding bit in the MASK register
- is 0. */
- __IO uint32_t MPORT_PIO1 : 1; /*!< Masked pin register. 0 = Read: pin is LOW and/or the corresponding
- bit in the MASK register is 1; write: clear output bit if the
- corresponding bit in the MASK register is 0. 1 = Read: pin is
- HIGH and the corresponding bit in the MASK register is 0; write:
- set output bit if the corresponding bit in the MASK register
- is 0. */
- __IO uint32_t MPORT_PIO2 : 1; /*!< Masked pin register. 0 = Read: pin is LOW and/or the corresponding
- bit in the MASK register is 1; write: clear output bit if the
- corresponding bit in the MASK register is 0. 1 = Read: pin is
- HIGH and the corresponding bit in the MASK register is 0; write:
- set output bit if the corresponding bit in the MASK register
- is 0. */
- __IO uint32_t MPORT_PIO3 : 1; /*!< Masked pin register. 0 = Read: pin is LOW and/or the corresponding
- bit in the MASK register is 1; write: clear output bit if the
- corresponding bit in the MASK register is 0. 1 = Read: pin is
- HIGH and the corresponding bit in the MASK register is 0; write:
- set output bit if the corresponding bit in the MASK register
- is 0. */
- __IO uint32_t MPORT_PIO4 : 1; /*!< Masked pin register. 0 = Read: pin is LOW and/or the corresponding
- bit in the MASK register is 1; write: clear output bit if the
- corresponding bit in the MASK register is 0. 1 = Read: pin is
- HIGH and the corresponding bit in the MASK register is 0; write:
- set output bit if the corresponding bit in the MASK register
- is 0. */
- __IO uint32_t MPORT_PIO5 : 1; /*!< Masked pin register. 0 = Read: pin is LOW and/or the corresponding
- bit in the MASK register is 1; write: clear output bit if the
- corresponding bit in the MASK register is 0. 1 = Read: pin is
- HIGH and the corresponding bit in the MASK register is 0; write:
- set output bit if the corresponding bit in the MASK register
- is 0. */
- __IO uint32_t MPORT_PIO6 : 1; /*!< Masked pin register. 0 = Read: pin is LOW and/or the corresponding
- bit in the MASK register is 1; write: clear output bit if the
- corresponding bit in the MASK register is 0. 1 = Read: pin is
- HIGH and the corresponding bit in the MASK register is 0; write:
- set output bit if the corresponding bit in the MASK register
- is 0. */
- __IO uint32_t MPORT_PIO7 : 1; /*!< Masked pin register. 0 = Read: pin is LOW and/or the corresponding
- bit in the MASK register is 1; write: clear output bit if the
- corresponding bit in the MASK register is 0. 1 = Read: pin is
- HIGH and the corresponding bit in the MASK register is 0; write:
- set output bit if the corresponding bit in the MASK register
- is 0. */
- __IO uint32_t MPORT_PIO8 : 1; /*!< Masked pin register. 0 = Read: pin is LOW and/or the corresponding
- bit in the MASK register is 1; write: clear output bit if the
- corresponding bit in the MASK register is 0. 1 = Read: pin is
- HIGH and the corresponding bit in the MASK register is 0; write:
- set output bit if the corresponding bit in the MASK register
- is 0. */
- __IO uint32_t MPORT_PIO9 : 1; /*!< Masked pin register. 0 = Read: pin is LOW and/or the corresponding
- bit in the MASK register is 1; write: clear output bit if the
- corresponding bit in the MASK register is 0. 1 = Read: pin is
- HIGH and the corresponding bit in the MASK register is 0; write:
- set output bit if the corresponding bit in the MASK register
- is 0. */
- __IO uint32_t MPORT_PIO10: 1; /*!< Masked pin register. 0 = Read: pin is LOW and/or the corresponding
- bit in the MASK register is 1; write: clear output bit if the
- corresponding bit in the MASK register is 0. 1 = Read: pin is
- HIGH and the corresponding bit in the MASK register is 0; write:
- set output bit if the corresponding bit in the MASK register
- is 0. */
- __IO uint32_t MPORT_PIO11: 1; /*!< Masked pin register. 0 = Read: pin is LOW and/or the corresponding
- bit in the MASK register is 1; write: clear output bit if the
- corresponding bit in the MASK register is 0. 1 = Read: pin is
- HIGH and the corresponding bit in the MASK register is 0; write:
- set output bit if the corresponding bit in the MASK register
- is 0. */
- __IO uint32_t MPORT_PIO12: 1; /*!< Masked pin register. 0 = Read: pin is LOW and/or the corresponding
- bit in the MASK register is 1; write: clear output bit if the
- corresponding bit in the MASK register is 0. 1 = Read: pin is
- HIGH and the corresponding bit in the MASK register is 0; write:
- set output bit if the corresponding bit in the MASK register
- is 0. */
- __IO uint32_t MPORT_PIO13: 1; /*!< Masked pin register. 0 = Read: pin is LOW and/or the corresponding
- bit in the MASK register is 1; write: clear output bit if the
- corresponding bit in the MASK register is 0. 1 = Read: pin is
- HIGH and the corresponding bit in the MASK register is 0; write:
- set output bit if the corresponding bit in the MASK register
- is 0. */
- __IO uint32_t MPORT_PIO14: 1; /*!< Masked pin register. 0 = Read: pin is LOW and/or the corresponding
- bit in the MASK register is 1; write: clear output bit if the
- corresponding bit in the MASK register is 0. 1 = Read: pin is
- HIGH and the corresponding bit in the MASK register is 0; write:
- set output bit if the corresponding bit in the MASK register
- is 0. */
- __IO uint32_t MPORT_PIO15: 1; /*!< Masked pin register. 0 = Read: pin is LOW and/or the corresponding
- bit in the MASK register is 1; write: clear output bit if the
- corresponding bit in the MASK register is 0. 1 = Read: pin is
- HIGH and the corresponding bit in the MASK register is 0; write:
- set output bit if the corresponding bit in the MASK register
- is 0. */
- __IO uint32_t MPORT_PIO16: 1; /*!< Masked pin register. 0 = Read: pin is LOW and/or the corresponding
- bit in the MASK register is 1; write: clear output bit if the
- corresponding bit in the MASK register is 0. 1 = Read: pin is
- HIGH and the corresponding bit in the MASK register is 0; write:
- set output bit if the corresponding bit in the MASK register
- is 0. */
- __IO uint32_t MPORT_PIO17: 1; /*!< Masked pin register. 0 = Read: pin is LOW and/or the corresponding
- bit in the MASK register is 1; write: clear output bit if the
- corresponding bit in the MASK register is 0. 1 = Read: pin is
- HIGH and the corresponding bit in the MASK register is 0; write:
- set output bit if the corresponding bit in the MASK register
- is 0. */
- __IO uint32_t MPORT_PIO18: 1; /*!< Masked pin register. 0 = Read: pin is LOW and/or the corresponding
- bit in the MASK register is 1; write: clear output bit if the
- corresponding bit in the MASK register is 0. 1 = Read: pin is
- HIGH and the corresponding bit in the MASK register is 0; write:
- set output bit if the corresponding bit in the MASK register
- is 0. */
- __IO uint32_t MPORT_PIO19: 1; /*!< Masked pin register. 0 = Read: pin is LOW and/or the corresponding
- bit in the MASK register is 1; write: clear output bit if the
- corresponding bit in the MASK register is 0. 1 = Read: pin is
- HIGH and the corresponding bit in the MASK register is 0; write:
- set output bit if the corresponding bit in the MASK register
- is 0. */
- __IO uint32_t MPORT_PIO20: 1; /*!< Masked pin register. 0 = Read: pin is LOW and/or the corresponding
- bit in the MASK register is 1; write: clear output bit if the
- corresponding bit in the MASK register is 0. 1 = Read: pin is
- HIGH and the corresponding bit in the MASK register is 0; write:
- set output bit if the corresponding bit in the MASK register
- is 0. */
- __IO uint32_t MPORT_PIO21: 1; /*!< Masked pin register. 0 = Read: pin is LOW and/or the corresponding
- bit in the MASK register is 1; write: clear output bit if the
- corresponding bit in the MASK register is 0. 1 = Read: pin is
- HIGH and the corresponding bit in the MASK register is 0; write:
- set output bit if the corresponding bit in the MASK register
- is 0. */
- } MPIN_b; /*!< BitSize */
- };
- __I uint32_t RESERVED5[31];
-
- union {
- __IO uint32_t SET; /*!< Write: Set Pin register bits Read: output bits */
-
- struct {
- __IO uint32_t SETP_PIO0 : 1; /*!< Read or set output bits. 0 = Read: output bit: write: no operation.
- 1 = Read: output bit; write: set output bit. */
- __IO uint32_t SETP_PIO1 : 1; /*!< Read or set output bits. 0 = Read: output bit: write: no operation.
- 1 = Read: output bit; write: set output bit. */
- __IO uint32_t SETP_PIO2 : 1; /*!< Read or set output bits. 0 = Read: output bit: write: no operation.
- 1 = Read: output bit; write: set output bit. */
- __IO uint32_t SETP_PIO3 : 1; /*!< Read or set output bits. 0 = Read: output bit: write: no operation.
- 1 = Read: output bit; write: set output bit. */
- __IO uint32_t SETP_PIO4 : 1; /*!< Read or set output bits. 0 = Read: output bit: write: no operation.
- 1 = Read: output bit; write: set output bit. */
- __IO uint32_t SETP_PIO5 : 1; /*!< Read or set output bits. 0 = Read: output bit: write: no operation.
- 1 = Read: output bit; write: set output bit. */
- __IO uint32_t SETP_PIO6 : 1; /*!< Read or set output bits. 0 = Read: output bit: write: no operation.
- 1 = Read: output bit; write: set output bit. */
- __IO uint32_t SETP_PIO7 : 1; /*!< Read or set output bits. 0 = Read: output bit: write: no operation.
- 1 = Read: output bit; write: set output bit. */
- __IO uint32_t SETP_PIO8 : 1; /*!< Read or set output bits. 0 = Read: output bit: write: no operation.
- 1 = Read: output bit; write: set output bit. */
- __IO uint32_t SETP_PIO9 : 1; /*!< Read or set output bits. 0 = Read: output bit: write: no operation.
- 1 = Read: output bit; write: set output bit. */
- __IO uint32_t SETP_PIO10 : 1; /*!< Read or set output bits. 0 = Read: output bit: write: no operation.
- 1 = Read: output bit; write: set output bit. */
- __IO uint32_t SETP_PIO11 : 1; /*!< Read or set output bits. 0 = Read: output bit: write: no operation.
- 1 = Read: output bit; write: set output bit. */
- __IO uint32_t SETP_PIO12 : 1; /*!< Read or set output bits. 0 = Read: output bit: write: no operation.
- 1 = Read: output bit; write: set output bit. */
- __IO uint32_t SETP_PIO13 : 1; /*!< Read or set output bits. 0 = Read: output bit: write: no operation.
- 1 = Read: output bit; write: set output bit. */
- __IO uint32_t SETP_PIO14 : 1; /*!< Read or set output bits. 0 = Read: output bit: write: no operation.
- 1 = Read: output bit; write: set output bit. */
- __IO uint32_t SETP_PIO15 : 1; /*!< Read or set output bits. 0 = Read: output bit: write: no operation.
- 1 = Read: output bit; write: set output bit. */
- __IO uint32_t SETP_PIO16 : 1; /*!< Read or set output bits. 0 = Read: output bit: write: no operation.
- 1 = Read: output bit; write: set output bit. */
- __IO uint32_t SETP_PIO17 : 1; /*!< Read or set output bits. 0 = Read: output bit: write: no operation.
- 1 = Read: output bit; write: set output bit. */
- __IO uint32_t SETP_PIO18 : 1; /*!< Read or set output bits. 0 = Read: output bit: write: no operation.
- 1 = Read: output bit; write: set output bit. */
- __IO uint32_t SETP_PIO19 : 1; /*!< Read or set output bits. 0 = Read: output bit: write: no operation.
- 1 = Read: output bit; write: set output bit. */
- __IO uint32_t SETP_PIO20 : 1; /*!< Read or set output bits. 0 = Read: output bit: write: no operation.
- 1 = Read: output bit; write: set output bit. */
- __IO uint32_t SETP_PIO21 : 1; /*!< Read or set output bits. 0 = Read: output bit: write: no operation.
- 1 = Read: output bit; write: set output bit. */
- } SET_b; /*!< BitSize */
- };
- __I uint32_t RESERVED6[31];
-
- union {
- __O uint32_t CLR; /*!< Clear Pin register bits */
-
- struct {
- __O uint32_t CLRP_PIO0 : 1; /*!< Clear output bits. 0 = No operation. 1 = Clear output bit. */
- __O uint32_t CLRP_PIO1 : 1; /*!< Clear output bits. 0 = No operation. 1 = Clear output bit. */
- __O uint32_t CLRP_PIO2 : 1; /*!< Clear output bits. 0 = No operation. 1 = Clear output bit. */
- __O uint32_t CLRP_PIO3 : 1; /*!< Clear output bits. 0 = No operation. 1 = Clear output bit. */
- __O uint32_t CLRP_PIO4 : 1; /*!< Clear output bits. 0 = No operation. 1 = Clear output bit. */
- __O uint32_t CLRP_PIO5 : 1; /*!< Clear output bits. 0 = No operation. 1 = Clear output bit. */
- __O uint32_t CLRP_PIO6 : 1; /*!< Clear output bits. 0 = No operation. 1 = Clear output bit. */
- __O uint32_t CLRP_PIO7 : 1; /*!< Clear output bits. 0 = No operation. 1 = Clear output bit. */
- __O uint32_t CLRP_PIO8 : 1; /*!< Clear output bits. 0 = No operation. 1 = Clear output bit. */
- __O uint32_t CLRP_PIO9 : 1; /*!< Clear output bits. 0 = No operation. 1 = Clear output bit. */
- __O uint32_t CLRP_PIO10 : 1; /*!< Clear output bits. 0 = No operation. 1 = Clear output bit. */
- __O uint32_t CLRP_PIO11 : 1; /*!< Clear output bits. 0 = No operation. 1 = Clear output bit. */
- __O uint32_t CLRP_PIO12 : 1; /*!< Clear output bits. 0 = No operation. 1 = Clear output bit. */
- __O uint32_t CLRP_PIO13 : 1; /*!< Clear output bits. 0 = No operation. 1 = Clear output bit. */
- __O uint32_t CLRP_PIO14 : 1; /*!< Clear output bits. 0 = No operation. 1 = Clear output bit. */
- __O uint32_t CLRP_PIO15 : 1; /*!< Clear output bits. 0 = No operation. 1 = Clear output bit. */
- __O uint32_t CLRP_PIO16 : 1; /*!< Clear output bits. 0 = No operation. 1 = Clear output bit. */
- __O uint32_t CLRP_PIO17 : 1; /*!< Clear output bits. 0 = No operation. 1 = Clear output bit. */
- __O uint32_t CLRP_PIO18 : 1; /*!< Clear output bits. 0 = No operation. 1 = Clear output bit. */
- __O uint32_t CLRP_PIO19 : 1; /*!< Clear output bits. 0 = No operation. 1 = Clear output bit. */
- __O uint32_t CLRP_PIO20 : 1; /*!< Clear output bits. 0 = No operation. 1 = Clear output bit. */
- __O uint32_t CLRP_PIO21 : 1; /*!< Clear output bits. 0 = No operation. 1 = Clear output bit. */
- } CLR_b; /*!< BitSize */
- };
- __I uint32_t RESERVED7[31];
-
- union {
- __O uint32_t NOT; /*!< Toggle Pin register bits */
-
- struct {
- __O uint32_t NOTP_PIO0 : 1; /*!< Toggle output bits. 0 = no operation. 1 = Toggle output bit. */
- __O uint32_t NOTP_PIO1 : 1; /*!< Toggle output bits. 0 = no operation. 1 = Toggle output bit. */
- __O uint32_t NOTP_PIO2 : 1; /*!< Toggle output bits. 0 = no operation. 1 = Toggle output bit. */
- __O uint32_t NOTP_PIO3 : 1; /*!< Toggle output bits. 0 = no operation. 1 = Toggle output bit. */
- __O uint32_t NOTP_PIO4 : 1; /*!< Toggle output bits. 0 = no operation. 1 = Toggle output bit. */
- __O uint32_t NOTP_PIO5 : 1; /*!< Toggle output bits. 0 = no operation. 1 = Toggle output bit. */
- __O uint32_t NOTP_PIO6 : 1; /*!< Toggle output bits. 0 = no operation. 1 = Toggle output bit. */
- __O uint32_t NOTP_PIO7 : 1; /*!< Toggle output bits. 0 = no operation. 1 = Toggle output bit. */
- __O uint32_t NOTP_PIO8 : 1; /*!< Toggle output bits. 0 = no operation. 1 = Toggle output bit. */
- __O uint32_t NOTP_PIO9 : 1; /*!< Toggle output bits. 0 = no operation. 1 = Toggle output bit. */
- __O uint32_t NOTP_PIO10 : 1; /*!< Toggle output bits. 0 = no operation. 1 = Toggle output bit. */
- __O uint32_t NOTP_PIO11 : 1; /*!< Toggle output bits. 0 = no operation. 1 = Toggle output bit. */
- __O uint32_t NOTP_PIO12 : 1; /*!< Toggle output bits. 0 = no operation. 1 = Toggle output bit. */
- __O uint32_t NOTP_PIO13 : 1; /*!< Toggle output bits. 0 = no operation. 1 = Toggle output bit. */
- __O uint32_t NOTP_PIO14 : 1; /*!< Toggle output bits. 0 = no operation. 1 = Toggle output bit. */
- __O uint32_t NOTP_PIO15 : 1; /*!< Toggle output bits. 0 = no operation. 1 = Toggle output bit. */
- __O uint32_t NOTP_PIO16 : 1; /*!< Toggle output bits. 0 = no operation. 1 = Toggle output bit. */
- __O uint32_t NOTP_PIO17 : 1; /*!< Toggle output bits. 0 = no operation. 1 = Toggle output bit. */
- __O uint32_t NOTP_PIO18 : 1; /*!< Toggle output bits. 0 = no operation. 1 = Toggle output bit. */
- __O uint32_t NOTP_PIO19 : 1; /*!< Toggle output bits. 0 = no operation. 1 = Toggle output bit. */
- __O uint32_t NOTP_PIO20 : 1; /*!< Toggle output bits. 0 = no operation. 1 = Toggle output bit. */
- __O uint32_t NOTP_PIO21 : 1; /*!< Toggle output bits. 0 = no operation. 1 = Toggle output bit. */
- } NOT_b; /*!< BitSize */
- };
- __I uint32_t RESERVED8[31];
-
- union {
- __O uint32_t DIRSET; /*!< Set pin direction bits */
-
- struct {
- __O uint32_t DIRSETP_PIO0: 1; /*!< Set direction bits. 0 = no operation. 1 = Set direction bit. */
- __O uint32_t DIRSETP_PIO1: 1; /*!< Set direction bits. 0 = no operation. 1 = Set direction bit. */
- __O uint32_t DIRSETP_PIO2: 1; /*!< Set direction bits. 0 = no operation. 1 = Set direction bit. */
- __O uint32_t DIRSETP_PIO3: 1; /*!< Set direction bits. 0 = no operation. 1 = Set direction bit. */
- __O uint32_t DIRSETP_PIO4: 1; /*!< Set direction bits. 0 = no operation. 1 = Set direction bit. */
- __O uint32_t DIRSETP_PIO5: 1; /*!< Set direction bits. 0 = no operation. 1 = Set direction bit. */
- __O uint32_t DIRSETP_PIO6: 1; /*!< Set direction bits. 0 = no operation. 1 = Set direction bit. */
- __O uint32_t DIRSETP_PIO7: 1; /*!< Set direction bits. 0 = no operation. 1 = Set direction bit. */
- __O uint32_t DIRSETP_PIO8: 1; /*!< Set direction bits. 0 = no operation. 1 = Set direction bit. */
- __O uint32_t DIRSETP_PIO9: 1; /*!< Set direction bits. 0 = no operation. 1 = Set direction bit. */
- __O uint32_t DIRSETP_PIO10: 1; /*!< Set direction bits. 0 = no operation. 1 = Set direction bit. */
- __O uint32_t DIRSETP_PIO11: 1; /*!< Set direction bits. 0 = no operation. 1 = Set direction bit. */
- __O uint32_t DIRSETP_PIO12: 1; /*!< Set direction bits. 0 = no operation. 1 = Set direction bit. */
- __O uint32_t DIRSETP_PIO13: 1; /*!< Set direction bits. 0 = no operation. 1 = Set direction bit. */
- __O uint32_t DIRSETP_PIO14: 1; /*!< Set direction bits. 0 = no operation. 1 = Set direction bit. */
- __O uint32_t DIRSETP_PIO15: 1; /*!< Set direction bits. 0 = no operation. 1 = Set direction bit. */
- __O uint32_t DIRSETP_PIO16: 1; /*!< Set direction bits. 0 = no operation. 1 = Set direction bit. */
- __O uint32_t DIRSETP_PIO17: 1; /*!< Set direction bits. 0 = no operation. 1 = Set direction bit. */
- __O uint32_t DIRSETP_PIO18: 1; /*!< Set direction bits. 0 = no operation. 1 = Set direction bit. */
- __O uint32_t DIRSETP_PIO19: 1; /*!< Set direction bits. 0 = no operation. 1 = Set direction bit. */
- __O uint32_t DIRSETP_PIO20: 1; /*!< Set direction bits. 0 = no operation. 1 = Set direction bit. */
- __O uint32_t DIRSETP_PIO21: 1; /*!< Set direction bits. 0 = no operation. 1 = Set direction bit. */
- } DIRSET_b; /*!< BitSize */
- };
- __I uint32_t RESERVED9[31];
-
- union {
- __O uint32_t DIRCLR; /*!< Clear pin direction bits */
-
- struct {
- __O uint32_t DIRCLRP_PIO0: 1; /*!< Clear direction bits. 0 = no operation. 1 = Clear direction
- bit. */
- __O uint32_t DIRCLRP_PIO1: 1; /*!< Clear direction bits. 0 = no operation. 1 = Clear direction
- bit. */
- __O uint32_t DIRCLRP_PIO2: 1; /*!< Clear direction bits. 0 = no operation. 1 = Clear direction
- bit. */
- __O uint32_t DIRCLRP_PIO3: 1; /*!< Clear direction bits. 0 = no operation. 1 = Clear direction
- bit. */
- __O uint32_t DIRCLRP_PIO4: 1; /*!< Clear direction bits. 0 = no operation. 1 = Clear direction
- bit. */
- __O uint32_t DIRCLRP_PIO5: 1; /*!< Clear direction bits. 0 = no operation. 1 = Clear direction
- bit. */
- __O uint32_t DIRCLRP_PIO6: 1; /*!< Clear direction bits. 0 = no operation. 1 = Clear direction
- bit. */
- __O uint32_t DIRCLRP_PIO7: 1; /*!< Clear direction bits. 0 = no operation. 1 = Clear direction
- bit. */
- __O uint32_t DIRCLRP_PIO8: 1; /*!< Clear direction bits. 0 = no operation. 1 = Clear direction
- bit. */
- __O uint32_t DIRCLRP_PIO9: 1; /*!< Clear direction bits. 0 = no operation. 1 = Clear direction
- bit. */
- __O uint32_t DIRCLRP_PIO10: 1; /*!< Clear direction bits. 0 = no operation. 1 = Clear direction
- bit. */
- __O uint32_t DIRCLRP_PIO11: 1; /*!< Clear direction bits. 0 = no operation. 1 = Clear direction
- bit. */
- __O uint32_t DIRCLRP_PIO12: 1; /*!< Clear direction bits. 0 = no operation. 1 = Clear direction
- bit. */
- __O uint32_t DIRCLRP_PIO13: 1; /*!< Clear direction bits. 0 = no operation. 1 = Clear direction
- bit. */
- __O uint32_t DIRCLRP_PIO14: 1; /*!< Clear direction bits. 0 = no operation. 1 = Clear direction
- bit. */
- __O uint32_t DIRCLRP_PIO15: 1; /*!< Clear direction bits. 0 = no operation. 1 = Clear direction
- bit. */
- __O uint32_t DIRCLRP_PIO16: 1; /*!< Clear direction bits. 0 = no operation. 1 = Clear direction
- bit. */
- __O uint32_t DIRCLRP_PIO17: 1; /*!< Clear direction bits. 0 = no operation. 1 = Clear direction
- bit. */
- __O uint32_t DIRCLRP_PIO18: 1; /*!< Clear direction bits. 0 = no operation. 1 = Clear direction
- bit. */
- __O uint32_t DIRCLRP_PIO19: 1; /*!< Clear direction bits. 0 = no operation. 1 = Clear direction
- bit. */
- __O uint32_t DIRCLRP_PIO20: 1; /*!< Clear direction bits. 0 = no operation. 1 = Clear direction
- bit. */
- __O uint32_t DIRCLRP_PIO21: 1; /*!< Clear direction bits. 0 = no operation. 1 = Clear direction
- bit. */
- } DIRCLR_b; /*!< BitSize */
- };
- __I uint32_t RESERVED10[31];
-
- union {
- __O uint32_t DIRNOT; /*!< Toggle pin direction bits */
-
- struct {
- __O uint32_t DIRNOTP_PIO0: 1; /*!< Toggle direction bits. 0 = no operation. 1 = Toggle direction
- bit. */
- __O uint32_t DIRNOTP_PIO1: 1; /*!< Toggle direction bits. 0 = no operation. 1 = Toggle direction
- bit. */
- __O uint32_t DIRNOTP_PIO2: 1; /*!< Toggle direction bits. 0 = no operation. 1 = Toggle direction
- bit. */
- __O uint32_t DIRNOTP_PIO3: 1; /*!< Toggle direction bits. 0 = no operation. 1 = Toggle direction
- bit. */
- __O uint32_t DIRNOTP_PIO4: 1; /*!< Toggle direction bits. 0 = no operation. 1 = Toggle direction
- bit. */
- __O uint32_t DIRNOTP_PIO5: 1; /*!< Toggle direction bits. 0 = no operation. 1 = Toggle direction
- bit. */
- __O uint32_t DIRNOTP_PIO6: 1; /*!< Toggle direction bits. 0 = no operation. 1 = Toggle direction
- bit. */
- __O uint32_t DIRNOTP_PIO7: 1; /*!< Toggle direction bits. 0 = no operation. 1 = Toggle direction
- bit. */
- __O uint32_t DIRNOTP_PIO8: 1; /*!< Toggle direction bits. 0 = no operation. 1 = Toggle direction
- bit. */
- __O uint32_t DIRNOTP_PIO9: 1; /*!< Toggle direction bits. 0 = no operation. 1 = Toggle direction
- bit. */
- __O uint32_t DIRNOTP_PIO10: 1; /*!< Toggle direction bits. 0 = no operation. 1 = Toggle direction
- bit. */
- __O uint32_t DIRNOTP_PIO11: 1; /*!< Toggle direction bits. 0 = no operation. 1 = Toggle direction
- bit. */
- __O uint32_t DIRNOTP_PIO12: 1; /*!< Toggle direction bits. 0 = no operation. 1 = Toggle direction
- bit. */
- __O uint32_t DIRNOTP_PIO13: 1; /*!< Toggle direction bits. 0 = no operation. 1 = Toggle direction
- bit. */
- __O uint32_t DIRNOTP_PIO14: 1; /*!< Toggle direction bits. 0 = no operation. 1 = Toggle direction
- bit. */
- __O uint32_t DIRNOTP_PIO15: 1; /*!< Toggle direction bits. 0 = no operation. 1 = Toggle direction
- bit. */
- __O uint32_t DIRNOTP_PIO16: 1; /*!< Toggle direction bits. 0 = no operation. 1 = Toggle direction
- bit. */
- __O uint32_t DIRNOTP_PIO17: 1; /*!< Toggle direction bits. 0 = no operation. 1 = Toggle direction
- bit. */
- __O uint32_t DIRNOTP_PIO18: 1; /*!< Toggle direction bits. 0 = no operation. 1 = Toggle direction
- bit. */
- __O uint32_t DIRNOTP_PIO19: 1; /*!< Toggle direction bits. 0 = no operation. 1 = Toggle direction
- bit. */
- __O uint32_t DIRNOTP_PIO20: 1; /*!< Toggle direction bits. 0 = no operation. 1 = Toggle direction
- bit. */
- __O uint32_t DIRNOTP_PIO21: 1; /*!< Toggle direction bits. 0 = no operation. 1 = Toggle direction
- bit. */
- } DIRNOT_b; /*!< BitSize */
- };
-} u_gpio_Type;
-
-
-/* ================================================================================ */
-/* ================ u_spifi ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component spifi It is General Purpose I/O with APB bus interface. More details will follow. (u_spifi)
- */
-
-typedef struct { /*!< u_spifi Structure */
-
- union {
- __IO uint32_t CTRL; /*!< SPIFI control register */
-
- struct {
- __IO uint32_t TIMEOUT : 16; /*!< This field contains the number of serial clock periods without
- the processor reading data in memory mode, which will cause
- the SPIFI hardware to terminate the command by driving the CS
- pin high and negating the CMD bit in the Status register. (This
- allows the flash memory to enter a lower-power state.) If the
- processor reads data from the flash region after a time-out,
- the command in the Memory Command Register is issued again. */
- __IO uint32_t CSHIGH : 4; /*!< This field controls the minimum CS high time, expressed as a
- number of serial clock periods minus one. */
- uint32_t : 1;
- __IO uint32_t D_PRFTCH_DIS: 1; /*!< This bit allows conditioning of memory mode prefetches based
- on the AHB HPROT (instruction/data) access information. A 1
- in this register means that the SPIFI will not attempt a speculative
- prefetch when it encounters data accesses. */
- __IO uint32_t INTEN : 1; /*!< If this bit is 1 when a command ends, the SPIFI will assert
- its interrupt request output. See INTRQ in the status register
- for further details. */
- __IO uint32_t MODE3 : 1; /*!< SPI Mode 3 select. 0 SCK LOW. The SPIFI drives SCK low after
- the rising edge at which the last bit of each command is captured,
- and keeps it low while CS is HIGH. 1 SCK HIGH. the SPIFI keeps
- SCK high after the rising edge for the last bit of each command
- and while CS is HIGH, and drives it low after it drives CS LOW.
- (Known serial flash devices can handle either mode, but some
- devices may require a particular mode for proper operation.)
- Remark: MODE3, RFCLK, and FBCLK should not all be 1, because
- in this c */
- uint32_t : 3;
- __IO uint32_t PRFTCH_DIS : 1; /*!< Cache prefetching enable. The SPIFI includes an internal cache.
- A 1 in this bit disables prefetching of cache lines. 0 Enable.
- Cache prefetching enabled. 1 Disable. Disables prefetching of
- cache lines. */
- __IO uint32_t DUAL : 1; /*!< Select dual protocol. 0 Quad protocol. This protocol uses IO3:0.
- 1 Dual protocol. This protocol uses IO1:0. */
- __IO uint32_t RFCLK : 1; /*!< Select active clock edge for input data. 0 Rising edge. Read
- data is sampled on rising edges on the clock, as in classic
- SPI operation. 1 Falling edge. Read data is sampled on falling
- edges of the clock, allowing a full serial clock of of time
- in order to maximize the serial clock frequency. Remark: MODE3,
- RFCLK, and FBCLK should not all be 1, because in this case there
- is no final falling edge on SCK on which to sample the last
- data bit of the frame. */
- __IO uint32_t FBCLK : 1; /*!< Feedback clock select. 0 Internal clock. The SPIFI samples read
- data using an internal clock. 1 Feedback clock. Read data is
- sampled using a feedback clock from the SCK pin. This allows
- slightly more time for each received bit. Remark: MODE3, RFCLK,
- and FBCLK should not all be 1, because in this case there is
- no final falling edge on SCK on which to sample the last data
- bit of the frame. */
- __IO uint32_t DMAEN : 1; /*!< A 1 in this bit enables the DMA Request output from the SPIFI.
- Set this bit only when a DMA channel is used to transfer data
- in peripheral mode. Do not set this bit when a DMA channel is
- used for memory-to-memory transfers from the SPIFI memory area.
- DRQEN should only be used in Command mode. */
- } CTRL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t CMD; /*!< SPIFI command register */
-
- struct {
- __IO uint32_t DATALEN : 14; /*!< Except when the POLL bit in this register is 1, this field controls
- how many data bytes are in the command. 0 indicates that the
- command does not contain a data field. */
- __IO uint32_t POLL : 1; /*!< This bit should be written as 1 only with an opcode that a)
- contains an input data field, and b) causes the serial flash
- device to return byte status repetitively (e.g., a Read Status
- command). When this bit is 1, the SPIFI hardware continues to
- read bytes until the test specified by the DATALEN field is
- met. The hardware tests the bit in each status byte selected
- by DATALEN bits 2:0, until a bit is found that is equal to DATALEN
- bit 3. When the test succeeds, the SPIFI captures the byte that
- meets this te */
- __IO uint32_t DOUT : 1; /*!< If the DATALEN field is not zero, this bit controls the direction
- of the data: 0 Input from serial flash. 1 Output to serial flash. */
- __IO uint32_t INTLEN : 3; /*!< This field controls how many intermediate bytes precede the
- data. (Each such byte may require 8 or 2 SCK cycles, depending
- on whether the intermediate field is in serial, 2-bit, or 4-bit
- format.) Intermediate bytes are output by the SPIFI, and include
- post-address control information, dummy and delay bytes. See
- the description of the Intermediate Data register for the contents
- of such bytes. */
- __IO uint32_t FIELDFORM : 2; /*!< This field controls how the fields of the command are sent.
- 0x0 All serial. All fields of the command are serial. 0x1 Quad/dual
- data. Data field is quad/dual, other fields are serial. 0x2
- Serial opcode. Opcode field is serial. Other fields are quad/dual.
- 0x3 All quad/dual. All fields of the command are in quad/dual
- format. */
- __IO uint32_t FRAMEFORM : 3; /*!< This field controls the opcode and address fields. 0x0 Reserved.
- 0x1 Opcode. Opcode only, no address. 0x2 Opcode one byte. Opcode,
- least significant byte of address. 0x3 Opcode two bytes. Opcode,
- two least significant bytes of address. 0x4 Opcode three bytes.
- Opcode, three least significant bytes of address. 0x5 Opcode
- four bytes. Opcode, 4 bytes of address. 0x6 No opcode three
- bytes. No opcode, 3 least significant bytes of address. 0x7
- No opcode four bytes. No opcode, 4 bytes of address. */
- __IO uint32_t OPCODE : 8; /*!< The opcode of the command (not used for some FRAMEFORM values). */
- } CMD_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t ADDR; /*!< SPIFI address register */
-
- struct {
- __IO uint32_t ADDR : 32; /*!< SPIFI address register */
- } ADDR_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t IDATA; /*!< SPIFI intermediate data register */
-
- struct {
- __IO uint32_t IDATA : 32; /*!< SPIFI intermediate data register */
- } IDATA_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t CLIMIT; /*!< SPIFI limit register */
-
- struct {
- __IO uint32_t CLIMIT : 32; /*!< SPIFI limit register */
- } CLIMIT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t DATA; /*!< SPIFI data register. Input or output data */
-
- struct {
- __IO uint32_t DATA : 32; /*!< SPIFI data register. Input or output data */
- } DATA_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t MCMD; /*!< SPIFI memory command register */
-
- struct {
- uint32_t : 14;
- __IO uint32_t POLL : 1; /*!< This bit should be written as 0. */
- __IO uint32_t DOUT : 1; /*!< This bit should be written as 0. */
- __IO uint32_t INTLEN : 3; /*!< This field controls how many intermediate bytes precede the
- data. (Each such byte may require 8 or 2 SCK cycles, depending
- on whether the intermediate field is in serial, 2-bit, or 4-bit
- format.) Intermediate bytes are output by the SPIFI, and include
- post-address control information, dummy and delay bytes. See
- the description of the Intermediate Data register for the contents
- of such bytes. */
- __IO uint32_t FIELDFORM : 2; /*!< This field controls how the fields of the command are sent.
- 0x0 All serial. All fields of the command are serial. 0x1 Quad/dual
- data. Data field is quad/dual, other fields are serial. 0x2
- Serial opcode. Opcode field is serial. Other fields are quad/dual.
- 0x3 All quad/dual. All fields of the command are in quad/dual
- format. */
- __IO uint32_t FRAMEFORM : 3; /*!< This field controls the opcode and address fields. 0x0 Reserved.
- 0x1 Opcode. Opcode only, no address. 0x2 Opcode one byte. Opcode,
- least-significant byte of address. 0x3 Opcode two bytes. Opcode,
- 2 least-significant bytes of address. 0x4 Opcode three bytes.
- Opcode, 3 least-significant bytes of address. 0x5 Opcode four
- bytes. Opcode, 4 bytes of address. 0x6 No opcode three bytes.
- No opcode, 3 least-significant bytes of address. 0x7 No opcode,
- 4 bytes of address. */
- __IO uint32_t OPCODE : 8; /*!< The opcode of the command (not used for some FRAMEFORM values). */
- } MCMD_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t STAT; /*!< SPIFI status register */
-
- struct {
- __IO uint32_t MCINIT : 1; /*!< This bit is set when software successfully writes the Memory
- Command register, and is cleared by Reset or by writing a 1
- to the RESET bit in this register. */
- __IO uint32_t CMD : 1; /*!< This bit is 1 when the Command register is written. It is cleared
- by a hardware reset, a write to the RESET bit in this register,
- or the deassertion of CS which indicates that the command has
- completed communication with the SPI Flash. */
- uint32_t : 2;
- __IO uint32_t RESET : 1; /*!< Write a 1 to this bit to abort a current command or memory mode.
- This bit is cleared when the hardware is ready for a new command
- to be written to the Command register. */
- __IO uint32_t INTRQ : 1; /*!< This bit reflects the SPIFI interrupt request. Write a 1 to
- this bit to clear it. This bit is set when a CMD was previously
- 1 and has been cleared due to the deassertion of CS. */
- uint32_t : 18;
- __IO uint32_t VERSION : 8; /*!< (null) */
- } STAT_b; /*!< BitSize */
- };
-} u_spifi_Type;
-
-
-/* ================================================================================ */
-/* ================ u_dma ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief dma (u_dma)
- */
-
-typedef struct { /*!< u_dma Structure */
-
- union {
- __IO uint32_t CTRL; /*!< DMA control. */
-
- struct {
- __IO uint32_t ENABLE : 1; /*!< DMA controller master enable. 0 Disabled. The DMA controller
- is disabled. This clears any triggers that were asserted at
- the point when disabled, but does not prevent re-triggering
- when the DMA controller is re-enabled. 1 Enabled. The DMA controller
- is enabled. */
- } CTRL_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t INTSTAT; /*!< Interrupt status. */
-
- struct {
- uint32_t : 1;
- __I uint32_t ACTIVEINT : 1; /*!< Summarizes whether any enabled interrupts (other than error
- interrupts) are pending. 0 Not pending. No enabled interrupts
- are pending. 1 Pending. At least one enabled interrupt is pending. */
- __I uint32_t ACTIVEERRINT: 1; /*!< Summarizes whether any error interrupts are pending. 0 Not pending.
- No error interrupts are pending. 1 Pending. At least one error
- interrupt is pending. */
- } INTSTAT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t SRAMBASE; /*!< SRAM address of the channel configuration table. */
-
- struct {
- uint32_t : 9;
- __IO uint32_t OFFSET : 23; /*!< Address bits 31:9 of the beginning of the DMA descriptor table.
- For 19 channels, the table must begin on a 512 byte boundary. */
- } SRAMBASE_b; /*!< BitSize */
- };
- __I uint32_t RESERVED0[5];
-
- union {
- __IO uint32_t ENABLESET0; /*!< Channel Enable read and Set for all DMA channels */
-
- struct {
- __IO uint32_t ENA_CH0 : 1; /*!< Enable for DMA channels. Bit n enables or disables DMA channel
- n. 0 = disabled. 1 = enabled. */
- __IO uint32_t ENA_CH1 : 1; /*!< Enable for DMA channels. Bit n enables or disables DMA channel
- n. 0 = disabled. 1 = enabled. */
- __IO uint32_t ENA_CH2 : 1; /*!< Enable for DMA channels. Bit n enables or disables DMA channel
- n. 0 = disabled. 1 = enabled. */
- __IO uint32_t ENA_CH3 : 1; /*!< Enable for DMA channels. Bit n enables or disables DMA channel
- n. 0 = disabled. 1 = enabled. */
- __IO uint32_t ENA_CH4 : 1; /*!< Enable for DMA channels. Bit n enables or disables DMA channel
- n. 0 = disabled. 1 = enabled. */
- __IO uint32_t ENA_CH5 : 1; /*!< Enable for DMA channels. Bit n enables or disables DMA channel
- n. 0 = disabled. 1 = enabled. */
- __IO uint32_t ENA_CH6 : 1; /*!< Enable for DMA channels. Bit n enables or disables DMA channel
- n. 0 = disabled. 1 = enabled. */
- __IO uint32_t ENA_CH7 : 1; /*!< Enable for DMA channels. Bit n enables or disables DMA channel
- n. 0 = disabled. 1 = enabled. */
- __IO uint32_t ENA_CH8 : 1; /*!< Enable for DMA channels. Bit n enables or disables DMA channel
- n. 0 = disabled. 1 = enabled. */
- __IO uint32_t ENA_CH9 : 1; /*!< Enable for DMA channels. Bit n enables or disables DMA channel
- n. 0 = disabled. 1 = enabled. */
- __IO uint32_t ENA_CH10 : 1; /*!< Enable for DMA channels. Bit n enables or disables DMA channel
- n. 0 = disabled. 1 = enabled. */
- __IO uint32_t ENA_CH11 : 1; /*!< Enable for DMA channels. Bit n enables or disables DMA channel
- n. 0 = disabled. 1 = enabled. */
- __IO uint32_t ENA_CH12 : 1; /*!< Enable for DMA channels. Bit n enables or disables DMA channel
- n. 0 = disabled. 1 = enabled. */
- __IO uint32_t ENA_CH13 : 1; /*!< Enable for DMA channels. Bit n enables or disables DMA channel
- n. 0 = disabled. 1 = enabled. */
- __IO uint32_t ENA_CH14 : 1; /*!< Enable for DMA channels. Bit n enables or disables DMA channel
- n. 0 = disabled. 1 = enabled. */
- __IO uint32_t ENA_CH15 : 1; /*!< Enable for DMA channels. Bit n enables or disables DMA channel
- n. 0 = disabled. 1 = enabled. */
- __IO uint32_t ENA_CH16 : 1; /*!< Enable for DMA channels. Bit n enables or disables DMA channel
- n. 0 = disabled. 1 = enabled. */
- __IO uint32_t ENA_CH17 : 1; /*!< Enable for DMA channels. Bit n enables or disables DMA channel
- n. 0 = disabled. 1 = enabled. */
- __IO uint32_t ENA_CH18 : 1; /*!< Enable for DMA channels. Bit n enables or disables DMA channel
- n. 0 = disabled. 1 = enabled. */
- } ENABLESET0_b; /*!< BitSize */
- };
- __I uint32_t RESERVED1;
-
- union {
- __O uint32_t ENABLECLR0; /*!< Channel Enable Clear for all DMA channels. */
-
- struct {
- __O uint32_t CLR_CH0 : 1; /*!< Writing ones to this register clears the corresponding bits
- in ENABLESET0. Bit n clears the channel enable bit n. */
- __O uint32_t CLR_CH1 : 1; /*!< Writing ones to this register clears the corresponding bits
- in ENABLESET0. Bit n clears the channel enable bit n. */
- __O uint32_t CLR_CH2 : 1; /*!< Writing ones to this register clears the corresponding bits
- in ENABLESET0. Bit n clears the channel enable bit n. */
- __O uint32_t CLR_CH3 : 1; /*!< Writing ones to this register clears the corresponding bits
- in ENABLESET0. Bit n clears the channel enable bit n. */
- __O uint32_t CLR_CH4 : 1; /*!< Writing ones to this register clears the corresponding bits
- in ENABLESET0. Bit n clears the channel enable bit n. */
- __O uint32_t CLR_CH5 : 1; /*!< Writing ones to this register clears the corresponding bits
- in ENABLESET0. Bit n clears the channel enable bit n. */
- __O uint32_t CLR_CH6 : 1; /*!< Writing ones to this register clears the corresponding bits
- in ENABLESET0. Bit n clears the channel enable bit n. */
- __O uint32_t CLR_CH7 : 1; /*!< Writing ones to this register clears the corresponding bits
- in ENABLESET0. Bit n clears the channel enable bit n. */
- __O uint32_t CLR_CH8 : 1; /*!< Writing ones to this register clears the corresponding bits
- in ENABLESET0. Bit n clears the channel enable bit n. */
- __O uint32_t CLR_CH9 : 1; /*!< Writing ones to this register clears the corresponding bits
- in ENABLESET0. Bit n clears the channel enable bit n. */
- __O uint32_t CLR_CH10 : 1; /*!< Writing ones to this register clears the corresponding bits
- in ENABLESET0. Bit n clears the channel enable bit n. */
- __O uint32_t CLR_CH11 : 1; /*!< Writing ones to this register clears the corresponding bits
- in ENABLESET0. Bit n clears the channel enable bit n. */
- __O uint32_t CLR_CH12 : 1; /*!< Writing ones to this register clears the corresponding bits
- in ENABLESET0. Bit n clears the channel enable bit n. */
- __O uint32_t CLR_CH13 : 1; /*!< Writing ones to this register clears the corresponding bits
- in ENABLESET0. Bit n clears the channel enable bit n. */
- __O uint32_t CLR_CH14 : 1; /*!< Writing ones to this register clears the corresponding bits
- in ENABLESET0. Bit n clears the channel enable bit n. */
- __O uint32_t CLR_CH15 : 1; /*!< Writing ones to this register clears the corresponding bits
- in ENABLESET0. Bit n clears the channel enable bit n. */
- __O uint32_t CLR_CH16 : 1; /*!< Writing ones to this register clears the corresponding bits
- in ENABLESET0. Bit n clears the channel enable bit n. */
- __O uint32_t CLR_CH17 : 1; /*!< Writing ones to this register clears the corresponding bits
- in ENABLESET0. Bit n clears the channel enable bit n. */
- __O uint32_t CLR_CH18 : 1; /*!< Writing ones to this register clears the corresponding bits
- in ENABLESET0. Bit n clears the channel enable bit n. */
- } ENABLECLR0_b; /*!< BitSize */
- };
- __I uint32_t RESERVED2;
-
- union {
- __I uint32_t ACTIVE0; /*!< Channel Active status for all DMA channels. */
-
- struct {
- __I uint32_t ACT_CH0 : 1; /*!< Active flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not active. 1 = active. */
- __I uint32_t ACT_CH1 : 1; /*!< Active flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not active. 1 = active. */
- __I uint32_t ACT_CH2 : 1; /*!< Active flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not active. 1 = active. */
- __I uint32_t ACT_CH3 : 1; /*!< Active flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not active. 1 = active. */
- __I uint32_t ACT_CH4 : 1; /*!< Active flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not active. 1 = active. */
- __I uint32_t ACT_CH5 : 1; /*!< Active flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not active. 1 = active. */
- __I uint32_t ACT_CH6 : 1; /*!< Active flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not active. 1 = active. */
- __I uint32_t ACT_CH7 : 1; /*!< Active flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not active. 1 = active. */
- __I uint32_t ACT_CH8 : 1; /*!< Active flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not active. 1 = active. */
- __I uint32_t ACT_CH9 : 1; /*!< Active flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not active. 1 = active. */
- __I uint32_t ACT_CH10 : 1; /*!< Active flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not active. 1 = active. */
- __I uint32_t ACT_CH11 : 1; /*!< Active flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not active. 1 = active. */
- __I uint32_t ACT_CH12 : 1; /*!< Active flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not active. 1 = active. */
- __I uint32_t ACT_CH13 : 1; /*!< Active flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not active. 1 = active. */
- __I uint32_t ACT_CH14 : 1; /*!< Active flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not active. 1 = active. */
- __I uint32_t ACT_CH15 : 1; /*!< Active flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not active. 1 = active. */
- __I uint32_t ACT_CH16 : 1; /*!< Active flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not active. 1 = active. */
- __I uint32_t ACT_CH17 : 1; /*!< Active flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not active. 1 = active. */
- __I uint32_t ACT_CH18 : 1; /*!< Active flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not active. 1 = active. */
- } ACTIVE0_b; /*!< BitSize */
- };
- __I uint32_t RESERVED3;
-
- union {
- __I uint32_t BUSY0; /*!< Channel Busy status for all DMA channels. */
-
- struct {
- __I uint32_t BSY_CH0 : 1; /*!< Busy flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not busy. 1 = busy. */
- __I uint32_t BSY_CH1 : 1; /*!< Busy flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not busy. 1 = busy. */
- __I uint32_t BSY_CH2 : 1; /*!< Busy flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not busy. 1 = busy. */
- __I uint32_t BSY_CH3 : 1; /*!< Busy flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not busy. 1 = busy. */
- __I uint32_t BSY_CH4 : 1; /*!< Busy flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not busy. 1 = busy. */
- __I uint32_t BSY_CH5 : 1; /*!< Busy flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not busy. 1 = busy. */
- __I uint32_t BSY_CH6 : 1; /*!< Busy flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not busy. 1 = busy. */
- __I uint32_t BSY_CH7 : 1; /*!< Busy flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not busy. 1 = busy. */
- __I uint32_t BSY_CH8 : 1; /*!< Busy flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not busy. 1 = busy. */
- __I uint32_t BSY_CH9 : 1; /*!< Busy flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not busy. 1 = busy. */
- __I uint32_t BSY_CH10 : 1; /*!< Busy flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not busy. 1 = busy. */
- __I uint32_t BSY_CH11 : 1; /*!< Busy flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not busy. 1 = busy. */
- __I uint32_t BSY_CH12 : 1; /*!< Busy flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not busy. 1 = busy. */
- __I uint32_t BSY_CH13 : 1; /*!< Busy flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not busy. 1 = busy. */
- __I uint32_t BSY_CH14 : 1; /*!< Busy flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not busy. 1 = busy. */
- __I uint32_t BSY_CH15 : 1; /*!< Busy flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not busy. 1 = busy. */
- __I uint32_t BSY_CH16 : 1; /*!< Busy flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not busy. 1 = busy. */
- __I uint32_t BSY_CH17 : 1; /*!< Busy flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not busy. 1 = busy. */
- __I uint32_t BSY_CH18 : 1; /*!< Busy flag for DMA channel n. Bit n corresponds to DMA channel
- n. 0 = not busy. 1 = busy. */
- } BUSY0_b; /*!< BitSize */
- };
- __I uint32_t RESERVED4;
-
- union {
- __IO uint32_t ERRINT0; /*!< Error Interrupt status for all DMA channels. */
-
- struct {
- __IO uint32_t ERR_CH0 : 1; /*!< Error Interrupt flag for DMA channel n. Bit n corresponds to
- DMA channel n. 0 = error interrupt is not active. 1 = error
- interrupt is active. */
- __IO uint32_t ERR_CH1 : 1; /*!< Error Interrupt flag for DMA channel n. Bit n corresponds to
- DMA channel n. 0 = error interrupt is not active. 1 = error
- interrupt is active. */
- __IO uint32_t ERR_CH2 : 1; /*!< Error Interrupt flag for DMA channel n. Bit n corresponds to
- DMA channel n. 0 = error interrupt is not active. 1 = error
- interrupt is active. */
- __IO uint32_t ERR_CH3 : 1; /*!< Error Interrupt flag for DMA channel n. Bit n corresponds to
- DMA channel n. 0 = error interrupt is not active. 1 = error
- interrupt is active. */
- __IO uint32_t ERR_CH4 : 1; /*!< Error Interrupt flag for DMA channel n. Bit n corresponds to
- DMA channel n. 0 = error interrupt is not active. 1 = error
- interrupt is active. */
- __IO uint32_t ERR_CH5 : 1; /*!< Error Interrupt flag for DMA channel n. Bit n corresponds to
- DMA channel n. 0 = error interrupt is not active. 1 = error
- interrupt is active. */
- __IO uint32_t ERR_CH6 : 1; /*!< Error Interrupt flag for DMA channel n. Bit n corresponds to
- DMA channel n. 0 = error interrupt is not active. 1 = error
- interrupt is active. */
- __IO uint32_t ERR_CH7 : 1; /*!< Error Interrupt flag for DMA channel n. Bit n corresponds to
- DMA channel n. 0 = error interrupt is not active. 1 = error
- interrupt is active. */
- __IO uint32_t ERR_CH8 : 1; /*!< Error Interrupt flag for DMA channel n. Bit n corresponds to
- DMA channel n. 0 = error interrupt is not active. 1 = error
- interrupt is active. */
- __IO uint32_t ERR_CH9 : 1; /*!< Error Interrupt flag for DMA channel n. Bit n corresponds to
- DMA channel n. 0 = error interrupt is not active. 1 = error
- interrupt is active. */
- __IO uint32_t ERR_CH10 : 1; /*!< Error Interrupt flag for DMA channel n. Bit n corresponds to
- DMA channel n. 0 = error interrupt is not active. 1 = error
- interrupt is active. */
- __IO uint32_t ERR_CH11 : 1; /*!< Error Interrupt flag for DMA channel n. Bit n corresponds to
- DMA channel n. 0 = error interrupt is not active. 1 = error
- interrupt is active. */
- __IO uint32_t ERR_CH12 : 1; /*!< Error Interrupt flag for DMA channel n. Bit n corresponds to
- DMA channel n. 0 = error interrupt is not active. 1 = error
- interrupt is active. */
- __IO uint32_t ERR_CH13 : 1; /*!< Error Interrupt flag for DMA channel n. Bit n corresponds to
- DMA channel n. 0 = error interrupt is not active. 1 = error
- interrupt is active. */
- __IO uint32_t ERR_CH14 : 1; /*!< Error Interrupt flag for DMA channel n. Bit n corresponds to
- DMA channel n. 0 = error interrupt is not active. 1 = error
- interrupt is active. */
- __IO uint32_t ERR_CH15 : 1; /*!< Error Interrupt flag for DMA channel n. Bit n corresponds to
- DMA channel n. 0 = error interrupt is not active. 1 = error
- interrupt is active. */
- __IO uint32_t ERR_CH16 : 1; /*!< Error Interrupt flag for DMA channel n. Bit n corresponds to
- DMA channel n. 0 = error interrupt is not active. 1 = error
- interrupt is active. */
- __IO uint32_t ERR_CH17 : 1; /*!< Error Interrupt flag for DMA channel n. Bit n corresponds to
- DMA channel n. 0 = error interrupt is not active. 1 = error
- interrupt is active. */
- __IO uint32_t ERR_CH18 : 1; /*!< Error Interrupt flag for DMA channel n. Bit n corresponds to
- DMA channel n. 0 = error interrupt is not active. 1 = error
- interrupt is active. */
- } ERRINT0_b; /*!< BitSize */
- };
- __I uint32_t RESERVED5;
-
- union {
- __IO uint32_t INTENSET0; /*!< Interrupt Enable read and Set for all DMA channels. */
-
- struct {
- __IO uint32_t INTEN_CH0 : 1; /*!< Interrupt Enable read and set for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = interrupt for DMA channel is disabled.
- 1 = interrupt for DMA channel is enabled. */
- __IO uint32_t INTEN_CH1 : 1; /*!< Interrupt Enable read and set for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = interrupt for DMA channel is disabled.
- 1 = interrupt for DMA channel is enabled. */
- __IO uint32_t INTEN_CH2 : 1; /*!< Interrupt Enable read and set for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = interrupt for DMA channel is disabled.
- 1 = interrupt for DMA channel is enabled. */
- __IO uint32_t INTEN_CH3 : 1; /*!< Interrupt Enable read and set for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = interrupt for DMA channel is disabled.
- 1 = interrupt for DMA channel is enabled. */
- __IO uint32_t INTEN_CH4 : 1; /*!< Interrupt Enable read and set for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = interrupt for DMA channel is disabled.
- 1 = interrupt for DMA channel is enabled. */
- __IO uint32_t INTEN_CH5 : 1; /*!< Interrupt Enable read and set for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = interrupt for DMA channel is disabled.
- 1 = interrupt for DMA channel is enabled. */
- __IO uint32_t INTEN_CH6 : 1; /*!< Interrupt Enable read and set for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = interrupt for DMA channel is disabled.
- 1 = interrupt for DMA channel is enabled. */
- __IO uint32_t INTEN_CH7 : 1; /*!< Interrupt Enable read and set for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = interrupt for DMA channel is disabled.
- 1 = interrupt for DMA channel is enabled. */
- __IO uint32_t INTEN_CH8 : 1; /*!< Interrupt Enable read and set for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = interrupt for DMA channel is disabled.
- 1 = interrupt for DMA channel is enabled. */
- __IO uint32_t INTEN_CH9 : 1; /*!< Interrupt Enable read and set for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = interrupt for DMA channel is disabled.
- 1 = interrupt for DMA channel is enabled. */
- __IO uint32_t INTEN_CH10 : 1; /*!< Interrupt Enable read and set for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = interrupt for DMA channel is disabled.
- 1 = interrupt for DMA channel is enabled. */
- __IO uint32_t INTEN_CH11 : 1; /*!< Interrupt Enable read and set for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = interrupt for DMA channel is disabled.
- 1 = interrupt for DMA channel is enabled. */
- __IO uint32_t INTEN_CH12 : 1; /*!< Interrupt Enable read and set for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = interrupt for DMA channel is disabled.
- 1 = interrupt for DMA channel is enabled. */
- __IO uint32_t INTEN_CH13 : 1; /*!< Interrupt Enable read and set for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = interrupt for DMA channel is disabled.
- 1 = interrupt for DMA channel is enabled. */
- __IO uint32_t INTEN_CH14 : 1; /*!< Interrupt Enable read and set for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = interrupt for DMA channel is disabled.
- 1 = interrupt for DMA channel is enabled. */
- __IO uint32_t INTEN_CH15 : 1; /*!< Interrupt Enable read and set for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = interrupt for DMA channel is disabled.
- 1 = interrupt for DMA channel is enabled. */
- __IO uint32_t INTEN_CH16 : 1; /*!< Interrupt Enable read and set for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = interrupt for DMA channel is disabled.
- 1 = interrupt for DMA channel is enabled. */
- __IO uint32_t INTEN_CH17 : 1; /*!< Interrupt Enable read and set for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = interrupt for DMA channel is disabled.
- 1 = interrupt for DMA channel is enabled. */
- __IO uint32_t INTEN_CH18 : 1; /*!< Interrupt Enable read and set for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = interrupt for DMA channel is disabled.
- 1 = interrupt for DMA channel is enabled. */
- } INTENSET0_b; /*!< BitSize */
- };
- __I uint32_t RESERVED6;
-
- union {
- __O uint32_t INTENCLR0; /*!< Interrupt Enable Clear for all DMA channels. */
-
- struct {
- __O uint32_t CLR_CH0 : 1; /*!< Writing ones to this register clears corresponding bits in the
- INTENSET0. Bit n corresponds to DMA channel n. */
- __O uint32_t CLR_CH1 : 1; /*!< Writing ones to this register clears corresponding bits in the
- INTENSET0. Bit n corresponds to DMA channel n. */
- __O uint32_t CLR_CH2 : 1; /*!< Writing ones to this register clears corresponding bits in the
- INTENSET0. Bit n corresponds to DMA channel n. */
- __O uint32_t CLR_CH3 : 1; /*!< Writing ones to this register clears corresponding bits in the
- INTENSET0. Bit n corresponds to DMA channel n. */
- __O uint32_t CLR_CH4 : 1; /*!< Writing ones to this register clears corresponding bits in the
- INTENSET0. Bit n corresponds to DMA channel n. */
- __O uint32_t CLR_CH5 : 1; /*!< Writing ones to this register clears corresponding bits in the
- INTENSET0. Bit n corresponds to DMA channel n. */
- __O uint32_t CLR_CH6 : 1; /*!< Writing ones to this register clears corresponding bits in the
- INTENSET0. Bit n corresponds to DMA channel n. */
- __O uint32_t CLR_CH7 : 1; /*!< Writing ones to this register clears corresponding bits in the
- INTENSET0. Bit n corresponds to DMA channel n. */
- __O uint32_t CLR_CH8 : 1; /*!< Writing ones to this register clears corresponding bits in the
- INTENSET0. Bit n corresponds to DMA channel n. */
- __O uint32_t CLR_CH9 : 1; /*!< Writing ones to this register clears corresponding bits in the
- INTENSET0. Bit n corresponds to DMA channel n. */
- __O uint32_t CLR_CH10 : 1; /*!< Writing ones to this register clears corresponding bits in the
- INTENSET0. Bit n corresponds to DMA channel n. */
- __O uint32_t CLR_CH11 : 1; /*!< Writing ones to this register clears corresponding bits in the
- INTENSET0. Bit n corresponds to DMA channel n. */
- __O uint32_t CLR_CH12 : 1; /*!< Writing ones to this register clears corresponding bits in the
- INTENSET0. Bit n corresponds to DMA channel n. */
- __O uint32_t CLR_CH13 : 1; /*!< Writing ones to this register clears corresponding bits in the
- INTENSET0. Bit n corresponds to DMA channel n. */
- __O uint32_t CLR_CH14 : 1; /*!< Writing ones to this register clears corresponding bits in the
- INTENSET0. Bit n corresponds to DMA channel n. */
- __O uint32_t CLR_CH15 : 1; /*!< Writing ones to this register clears corresponding bits in the
- INTENSET0. Bit n corresponds to DMA channel n. */
- __O uint32_t CLR_CH16 : 1; /*!< Writing ones to this register clears corresponding bits in the
- INTENSET0. Bit n corresponds to DMA channel n. */
- __O uint32_t CLR_CH17 : 1; /*!< Writing ones to this register clears corresponding bits in the
- INTENSET0. Bit n corresponds to DMA channel n. */
- __O uint32_t CLR_CH18 : 1; /*!< Writing ones to this register clears corresponding bits in the
- INTENSET0. Bit n corresponds to DMA channel n. */
- } INTENCLR0_b; /*!< BitSize */
- };
- __I uint32_t RESERVED7;
-
- union {
- __IO uint32_t INTA0; /*!< Interrupt A status for all DMA channels. */
-
- struct {
- __IO uint32_t IA_CH0 : 1; /*!< Interrupt A status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt A is not active. 1
- = the DMA channel interrupt A is active. */
- __IO uint32_t IA_CH1 : 1; /*!< Interrupt A status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt A is not active. 1
- = the DMA channel interrupt A is active. */
- __IO uint32_t IA_CH2 : 1; /*!< Interrupt A status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt A is not active. 1
- = the DMA channel interrupt A is active. */
- __IO uint32_t IA_CH3 : 1; /*!< Interrupt A status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt A is not active. 1
- = the DMA channel interrupt A is active. */
- __IO uint32_t IA_CH4 : 1; /*!< Interrupt A status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt A is not active. 1
- = the DMA channel interrupt A is active. */
- __IO uint32_t IA_CH5 : 1; /*!< Interrupt A status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt A is not active. 1
- = the DMA channel interrupt A is active. */
- __IO uint32_t IA_CH6 : 1; /*!< Interrupt A status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt A is not active. 1
- = the DMA channel interrupt A is active. */
- __IO uint32_t IA_CH7 : 1; /*!< Interrupt A status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt A is not active. 1
- = the DMA channel interrupt A is active. */
- __IO uint32_t IA_CH8 : 1; /*!< Interrupt A status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt A is not active. 1
- = the DMA channel interrupt A is active. */
- __IO uint32_t IA_CH9 : 1; /*!< Interrupt A status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt A is not active. 1
- = the DMA channel interrupt A is active. */
- __IO uint32_t IA_CH10 : 1; /*!< Interrupt A status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt A is not active. 1
- = the DMA channel interrupt A is active. */
- __IO uint32_t IA_CH11 : 1; /*!< Interrupt A status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt A is not active. 1
- = the DMA channel interrupt A is active. */
- __IO uint32_t IA_CH12 : 1; /*!< Interrupt A status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt A is not active. 1
- = the DMA channel interrupt A is active. */
- __IO uint32_t IA_CH13 : 1; /*!< Interrupt A status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt A is not active. 1
- = the DMA channel interrupt A is active. */
- __IO uint32_t IA_CH14 : 1; /*!< Interrupt A status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt A is not active. 1
- = the DMA channel interrupt A is active. */
- __IO uint32_t IA_CH15 : 1; /*!< Interrupt A status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt A is not active. 1
- = the DMA channel interrupt A is active. */
- __IO uint32_t IA_CH16 : 1; /*!< Interrupt A status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt A is not active. 1
- = the DMA channel interrupt A is active. */
- __IO uint32_t IA_CH17 : 1; /*!< Interrupt A status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt A is not active. 1
- = the DMA channel interrupt A is active. */
- __IO uint32_t IA_CH18 : 1; /*!< Interrupt A status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt A is not active. 1
- = the DMA channel interrupt A is active. */
- } INTA0_b; /*!< BitSize */
- };
- __I uint32_t RESERVED8;
-
- union {
- __IO uint32_t INTB0; /*!< Interrupt B status for all DMA channels. */
-
- struct {
- __IO uint32_t IB_CH0 : 1; /*!< Interrupt B status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt B is not active. 1
- = the DMA channel interrupt B is active. */
- __IO uint32_t IB_CH1 : 1; /*!< Interrupt B status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt B is not active. 1
- = the DMA channel interrupt B is active. */
- __IO uint32_t IB_CH2 : 1; /*!< Interrupt B status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt B is not active. 1
- = the DMA channel interrupt B is active. */
- __IO uint32_t IB_CH3 : 1; /*!< Interrupt B status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt B is not active. 1
- = the DMA channel interrupt B is active. */
- __IO uint32_t IB_CH4 : 1; /*!< Interrupt B status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt B is not active. 1
- = the DMA channel interrupt B is active. */
- __IO uint32_t IB_CH5 : 1; /*!< Interrupt B status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt B is not active. 1
- = the DMA channel interrupt B is active. */
- __IO uint32_t IB_CH6 : 1; /*!< Interrupt B status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt B is not active. 1
- = the DMA channel interrupt B is active. */
- __IO uint32_t IB_CH7 : 1; /*!< Interrupt B status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt B is not active. 1
- = the DMA channel interrupt B is active. */
- __IO uint32_t IB_CH8 : 1; /*!< Interrupt B status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt B is not active. 1
- = the DMA channel interrupt B is active. */
- __IO uint32_t IB_CH9 : 1; /*!< Interrupt B status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt B is not active. 1
- = the DMA channel interrupt B is active. */
- __IO uint32_t IB_CH10 : 1; /*!< Interrupt B status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt B is not active. 1
- = the DMA channel interrupt B is active. */
- __IO uint32_t IB_CH11 : 1; /*!< Interrupt B status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt B is not active. 1
- = the DMA channel interrupt B is active. */
- __IO uint32_t IB_CH12 : 1; /*!< Interrupt B status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt B is not active. 1
- = the DMA channel interrupt B is active. */
- __IO uint32_t IB_CH13 : 1; /*!< Interrupt B status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt B is not active. 1
- = the DMA channel interrupt B is active. */
- __IO uint32_t IB_CH14 : 1; /*!< Interrupt B status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt B is not active. 1
- = the DMA channel interrupt B is active. */
- __IO uint32_t IB_CH15 : 1; /*!< Interrupt B status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt B is not active. 1
- = the DMA channel interrupt B is active. */
- __IO uint32_t IB_CH16 : 1; /*!< Interrupt B status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt B is not active. 1
- = the DMA channel interrupt B is active. */
- __IO uint32_t IB_CH17 : 1; /*!< Interrupt B status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt B is not active. 1
- = the DMA channel interrupt B is active. */
- __IO uint32_t IB_CH18 : 1; /*!< Interrupt B status for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = the DMA channel interrupt B is not active. 1
- = the DMA channel interrupt B is active. */
- } INTB0_b; /*!< BitSize */
- };
- __I uint32_t RESERVED9;
-
- union {
- __O uint32_t SETVALID0; /*!< Set ValidPending control bits for all DMA channels. */
-
- struct {
- __O uint32_t SV_CH0 : 1; /*!< SETVALID control for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = no effect. 1 = sets the VALIDPENDING control
- bit for DMA channel n */
- __O uint32_t SV_CH1 : 1; /*!< SETVALID control for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = no effect. 1 = sets the VALIDPENDING control
- bit for DMA channel n */
- __O uint32_t SV_CH2 : 1; /*!< SETVALID control for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = no effect. 1 = sets the VALIDPENDING control
- bit for DMA channel n */
- __O uint32_t SV_CH3 : 1; /*!< SETVALID control for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = no effect. 1 = sets the VALIDPENDING control
- bit for DMA channel n */
- __O uint32_t SV_CH4 : 1; /*!< SETVALID control for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = no effect. 1 = sets the VALIDPENDING control
- bit for DMA channel n */
- __O uint32_t SV_CH5 : 1; /*!< SETVALID control for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = no effect. 1 = sets the VALIDPENDING control
- bit for DMA channel n */
- __O uint32_t SV_CH6 : 1; /*!< SETVALID control for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = no effect. 1 = sets the VALIDPENDING control
- bit for DMA channel n */
- __O uint32_t SV_CH7 : 1; /*!< SETVALID control for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = no effect. 1 = sets the VALIDPENDING control
- bit for DMA channel n */
- __O uint32_t SV_CH8 : 1; /*!< SETVALID control for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = no effect. 1 = sets the VALIDPENDING control
- bit for DMA channel n */
- __O uint32_t SV_CH9 : 1; /*!< SETVALID control for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = no effect. 1 = sets the VALIDPENDING control
- bit for DMA channel n */
- __O uint32_t SV_CH10 : 1; /*!< SETVALID control for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = no effect. 1 = sets the VALIDPENDING control
- bit for DMA channel n */
- __O uint32_t SV_CH11 : 1; /*!< SETVALID control for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = no effect. 1 = sets the VALIDPENDING control
- bit for DMA channel n */
- __O uint32_t SV_CH12 : 1; /*!< SETVALID control for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = no effect. 1 = sets the VALIDPENDING control
- bit for DMA channel n */
- __O uint32_t SV_CH13 : 1; /*!< SETVALID control for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = no effect. 1 = sets the VALIDPENDING control
- bit for DMA channel n */
- __O uint32_t SV_CH14 : 1; /*!< SETVALID control for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = no effect. 1 = sets the VALIDPENDING control
- bit for DMA channel n */
- __O uint32_t SV_CH15 : 1; /*!< SETVALID control for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = no effect. 1 = sets the VALIDPENDING control
- bit for DMA channel n */
- __O uint32_t SV_CH16 : 1; /*!< SETVALID control for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = no effect. 1 = sets the VALIDPENDING control
- bit for DMA channel n */
- __O uint32_t SV_CH17 : 1; /*!< SETVALID control for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = no effect. 1 = sets the VALIDPENDING control
- bit for DMA channel n */
- __O uint32_t SV_CH18 : 1; /*!< SETVALID control for DMA channel n. Bit n corresponds to DMA
- channel n. 0 = no effect. 1 = sets the VALIDPENDING control
- bit for DMA channel n */
- } SETVALID0_b; /*!< BitSize */
- };
- __I uint32_t RESERVED10;
-
- union {
- __O uint32_t SETTRIG0; /*!< Set Trigger control bits for all DMA channels. */
-
- struct {
- __O uint32_t TRIG_CH0 : 1; /*!< Set Trigger control bit for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA
- channel n. */
- __O uint32_t TRIG_CH1 : 1; /*!< Set Trigger control bit for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA
- channel n. */
- __O uint32_t TRIG_CH2 : 1; /*!< Set Trigger control bit for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA
- channel n. */
- __O uint32_t TRIG_CH3 : 1; /*!< Set Trigger control bit for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA
- channel n. */
- __O uint32_t TRIG_CH4 : 1; /*!< Set Trigger control bit for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA
- channel n. */
- __O uint32_t TRIG_CH5 : 1; /*!< Set Trigger control bit for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA
- channel n. */
- __O uint32_t TRIG_CH6 : 1; /*!< Set Trigger control bit for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA
- channel n. */
- __O uint32_t TRIG_CH7 : 1; /*!< Set Trigger control bit for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA
- channel n. */
- __O uint32_t TRIG_CH8 : 1; /*!< Set Trigger control bit for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA
- channel n. */
- __O uint32_t TRIG_CH9 : 1; /*!< Set Trigger control bit for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA
- channel n. */
- __O uint32_t TRIG_CH10 : 1; /*!< Set Trigger control bit for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA
- channel n. */
- __O uint32_t TRIG_CH11 : 1; /*!< Set Trigger control bit for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA
- channel n. */
- __O uint32_t TRIG_CH12 : 1; /*!< Set Trigger control bit for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA
- channel n. */
- __O uint32_t TRIG_CH13 : 1; /*!< Set Trigger control bit for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA
- channel n. */
- __O uint32_t TRIG_CH14 : 1; /*!< Set Trigger control bit for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA
- channel n. */
- __O uint32_t TRIG_CH15 : 1; /*!< Set Trigger control bit for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA
- channel n. */
- __O uint32_t TRIG_CH16 : 1; /*!< Set Trigger control bit for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA
- channel n. */
- __O uint32_t TRIG_CH17 : 1; /*!< Set Trigger control bit for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA
- channel n. */
- __O uint32_t TRIG_CH18 : 1; /*!< Set Trigger control bit for DMA channel n. Bit n corresponds
- to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA
- channel n. */
- } SETTRIG0_b; /*!< BitSize */
- };
- __I uint32_t RESERVED11;
-
- union {
- __O uint32_t ABORT0; /*!< Channel Abort control for all DMA channels. */
-
- struct {
- __O uint32_t ABORTCTRL_CH0: 1; /*!< Abort control for DMA channel 0. Bit n corresponds to DMA channel
- n. 0 = no effect. 1 = aborts DMA operations on channel n. */
- __O uint32_t ABORTCTRL_CH1: 1; /*!< Abort control for DMA channel 0. Bit n corresponds to DMA channel
- n. 0 = no effect. 1 = aborts DMA operations on channel n. */
- __O uint32_t ABORTCTRL_CH2: 1; /*!< Abort control for DMA channel 0. Bit n corresponds to DMA channel
- n. 0 = no effect. 1 = aborts DMA operations on channel n. */
- __O uint32_t ABORTCTRL_CH3: 1; /*!< Abort control for DMA channel 0. Bit n corresponds to DMA channel
- n. 0 = no effect. 1 = aborts DMA operations on channel n. */
- __O uint32_t ABORTCTRL_CH4: 1; /*!< Abort control for DMA channel 0. Bit n corresponds to DMA channel
- n. 0 = no effect. 1 = aborts DMA operations on channel n. */
- __O uint32_t ABORTCTRL_CH5: 1; /*!< Abort control for DMA channel 0. Bit n corresponds to DMA channel
- n. 0 = no effect. 1 = aborts DMA operations on channel n. */
- __O uint32_t ABORTCTRL_CH6: 1; /*!< Abort control for DMA channel 0. Bit n corresponds to DMA channel
- n. 0 = no effect. 1 = aborts DMA operations on channel n. */
- __O uint32_t ABORTCTRL_CH7: 1; /*!< Abort control for DMA channel 0. Bit n corresponds to DMA channel
- n. 0 = no effect. 1 = aborts DMA operations on channel n. */
- __O uint32_t ABORTCTRL_CH8: 1; /*!< Abort control for DMA channel 0. Bit n corresponds to DMA channel
- n. 0 = no effect. 1 = aborts DMA operations on channel n. */
- __O uint32_t ABORTCTRL_CH9: 1; /*!< Abort control for DMA channel 0. Bit n corresponds to DMA channel
- n. 0 = no effect. 1 = aborts DMA operations on channel n. */
- __O uint32_t ABORTCTRL_CH10: 1; /*!< Abort control for DMA channel 0. Bit n corresponds to DMA channel
- n. 0 = no effect. 1 = aborts DMA operations on channel n. */
- __O uint32_t ABORTCTRL_CH11: 1; /*!< Abort control for DMA channel 0. Bit n corresponds to DMA channel
- n. 0 = no effect. 1 = aborts DMA operations on channel n. */
- __O uint32_t ABORTCTRL_CH12: 1; /*!< Abort control for DMA channel 0. Bit n corresponds to DMA channel
- n. 0 = no effect. 1 = aborts DMA operations on channel n. */
- __O uint32_t ABORTCTRL_CH13: 1; /*!< Abort control for DMA channel 0. Bit n corresponds to DMA channel
- n. 0 = no effect. 1 = aborts DMA operations on channel n. */
- __O uint32_t ABORTCTRL_CH14: 1; /*!< Abort control for DMA channel 0. Bit n corresponds to DMA channel
- n. 0 = no effect. 1 = aborts DMA operations on channel n. */
- __O uint32_t ABORTCTRL_CH15: 1; /*!< Abort control for DMA channel 0. Bit n corresponds to DMA channel
- n. 0 = no effect. 1 = aborts DMA operations on channel n. */
- __O uint32_t ABORTCTRL_CH16: 1; /*!< Abort control for DMA channel 0. Bit n corresponds to DMA channel
- n. 0 = no effect. 1 = aborts DMA operations on channel n. */
- __O uint32_t ABORTCTRL_CH17: 1; /*!< Abort control for DMA channel 0. Bit n corresponds to DMA channel
- n. 0 = no effect. 1 = aborts DMA operations on channel n. */
- __O uint32_t ABORTCTRL_CH18: 1; /*!< Abort control for DMA channel 0. Bit n corresponds to DMA channel
- n. 0 = no effect. 1 = aborts DMA operations on channel n. */
- } ABORT0_b; /*!< BitSize */
- };
- __I uint32_t RESERVED12[225];
- u_dma_Channel_Type Regs_Channel[19]; /*!< No description available */
-} u_dma_Type;
-
-
-/* ================================================================================ */
-/* ================ u_aes256 ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component aes256 It is AES 128-192-256 with GCM mode. More details will follow. (u_aes256)
- */
-
-typedef struct { /*!< u_aes256 Structure */
-
- union {
- __IO uint32_t CFG; /*!< Configuration */
-
- struct {
- __IO uint32_t PROC_EN : 2; /*!< 00 Reserved 01 Encrypt/Decrypt Only 10 GF128 Hash Only 11 Encrypt/Decrypt
- and Hash */
- __IO uint32_t GF128_SEL : 1; /*!< 0 GF128 Hash Input Text 1 GF128 Hash Output Text */
- uint32_t : 1;
- __IO uint32_t INT_BSWAP : 1; /*!< Input Text Byte Swap */
- __IO uint32_t INT_WSWAP : 1; /*!< Input Text Word Swap */
- __IO uint32_t OUTT_BSWAP : 1; /*!< Output Text Byte Swap */
- __IO uint32_t OUTT_WSWAP : 1; /*!< Output Text Word Swap */
- __IO uint32_t KEY_CFG : 2; /*!< 00 128 Bit Key 01 192 Bit Key 10 256 Bit Key 11 Reserved */
- uint32_t : 6;
- __IO uint32_t INB_FSEL : 2; /*!< Input Block Selection From: 00 Reserved 01 Input Text 10 Holding
- 11 Input Text XOR Holding */
- uint32_t : 2;
- __IO uint32_t HOLD_FSEL : 2; /*!< Holding Select From: 00 Counter 01 Input Text 10 Output Block
- 11 Input Text XOR Output Block */
- uint32_t : 2;
- __IO uint32_t OUTT_FSEL : 2; /*!< Output Text Selection From: 00 Output Block 01 Output Block
- XOR Input Text 10 Output Block XOR Holding 11 Reserved */
- } CFG_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t CMD; /*!< Command */
-
- struct {
- __O uint32_t COPY_SKEY : 1; /*!< Copies Secret Key and enables cipher. Secret key is typically
- held in OTP or other secure memory. */
- __O uint32_t COPY_TO_Y : 1; /*!< Copies Output Text to GF128 Y. Typically used for GCM where
- the Hash requires a Y input which is the result of an ECB encryption
- of 0s. Should be performed after encryption of 0s. */
- uint32_t : 2;
- __O uint32_t SWITCH_MODE: 1; /*!< Switches mode from Forward to Reverse or from Reverse to Forward.
- Must wait for Idle after command. Typically used for non-counter
- modes (ECB, CBC, CFB, OFB) to switch from forward to reverse
- mode for decryption. */
- uint32_t : 3;
- __O uint32_t ABORT : 1; /*!< Aborts Encrypt/Decrypt and GF128 Hash Clears INTEXT Clears OUTTEXT
- Clears HOLDING */
- __O uint32_t WIPE : 1; /*!< Performs Abort Clears KEY Disables cipher Clears GF128_Y */
- } CMD_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t STAT; /*!< Status */
-
- struct {
- __I uint32_t IDLE : 1; /*!< All state machines are idle */
- __I uint32_t IN_READY : 1; /*!< Input Text can be written */
- __I uint32_t OUT_READY : 1; /*!< Output Text can be read */
- uint32_t : 1;
- __I uint32_t REVERSE : 1; /*!< Cipher in reverse mode */
- __I uint32_t KEY_VALID : 1; /*!< Key is valid */
- } STAT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t CTR_INCR; /*!< Counter Increment. Increment value for HOLDING when in Counter
- modes */
-
- struct {
- __IO uint32_t CTR_INCR : 32; /*!< Counter Increment. Increment value for HOLDING when in Counter
- modes */
- } CTR_INCR_b; /*!< BitSize */
- };
- __I uint32_t RESERVED0[4];
-
- union {
- __O uint32_t KEY0; /*!< Key [31:0]. The key will be enabled by writing sequentially
- KEY0, KEY1, KEY2, */
-
- struct {
- __O uint32_t KEY0 : 32; /*!< Key [31:0]. The key will be enabled by writing sequentially
- KEY0, KEY1, KEY2, */
- } KEY0_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t KEY1; /*!< Key [63:32]. The key will be enabled by writing sequentially
- KEY0, KEY1, KEY2, */
-
- struct {
- __O uint32_t KEY1 : 32; /*!< Key [63:32]. The key will be enabled by writing sequentially
- KEY0, KEY1, KEY2, */
- } KEY1_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t KEY2; /*!< Key [95:64]. The key will be enabled by writing sequentially
- KEY0, KEY1, KEY2, */
-
- struct {
- __O uint32_t KEY2 : 32; /*!< Key [95:64]. The key will be enabled by writing sequentially
- KEY0, KEY1, KEY2, */
- } KEY2_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t KEY3; /*!< Key [127:96]. The key will be enabled by writing sequentially
- KEY0, KEY1, KEY2, */
-
- struct {
- __O uint32_t KEY3 : 32; /*!< Key [127:96]. The key will be enabled by writing sequentially
- KEY0, KEY1, KEY2, */
- } KEY3_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t KEY4; /*!< Key [159:128]. The key will be enabled by writing sequentially
- KEY0, KEY1, KEY2, */
-
- struct {
- __O uint32_t KEY4 : 32; /*!< Key [159:128]. The key will be enabled by writing sequentially
- KEY0, KEY1, KEY2, */
- } KEY4_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t KEY5; /*!< Key [191:160]. The key will be enabled by writing sequentially
- KEY0, KEY1, KEY2, */
-
- struct {
- __O uint32_t KEY5 : 32; /*!< Key [191:160]. The key will be enabled by writing sequentially
- KEY0, KEY1, KEY2, */
- } KEY5_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t KEY6; /*!< Key [223:192]. The key will be enabled by writing sequentially
- KEY0, KEY1, KEY2, */
-
- struct {
- __O uint32_t KEY6 : 32; /*!< Key [223:192]. The key will be enabled by writing sequentially
- KEY0, KEY1, KEY2, */
- } KEY6_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t KEY7; /*!< Key [255:224]. The key will be enabled by writing sequentially
- KEY0, KEY1, KEY2, */
-
- struct {
- __O uint32_t KEY7 : 32; /*!< Key [255:224]. The key will be enabled by writing sequentially
- KEY0, KEY1, KEY2, */
- } KEY7_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t IN0; /*!< Input Text [31:0]. Contains the input data for processing. Typically
- holds plaintext when encrypting and ciphertext when decrypting */
-
- struct {
- __O uint32_t IN0 : 32; /*!< Input Text [31:0]. Contains the input data for processing. Typically
- holds plaintext when encrypting and ciphertext when decrypting */
- } IN0_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t IN1; /*!< Input Text [63:32]. Contains the input data for processing.
- Typically holds plaintext when encrypting and ciphertext when
- decrypting */
-
- struct {
- __O uint32_t IN1 : 32; /*!< Input Text [63:32]. Contains the input data for processing.
- Typically holds plaintext when encrypting and ciphertext when
- decrypting */
- } IN1_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t IN2; /*!< Input Text [95:64]. Contains the input data for processing.
- Typically holds plaintext when encrypting and ciphertext when
- decrypting */
-
- struct {
- __O uint32_t IN2 : 32; /*!< Input Text [95:64]. Contains the input data for processing.
- Typically holds plaintext when encrypting and ciphertext when
- decrypting */
- } IN2_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t IN3; /*!< Input Text [127:96]. Contains the input data for processing.
- Typically holds plaintext when encrypting and ciphertext when
- decrypting */
-
- struct {
- __O uint32_t IN3 : 32; /*!< Input Text [127:96]. Contains the input data for processing.
- Typically holds plaintext when encrypting and ciphertext when
- decrypting */
- } IN3_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t HOLDING0; /*!< Holding [31:0]. Temporary storage used for processing. Begins
- with Initialization Vector (IV). */
-
- struct {
- __O uint32_t HOLDING0 : 32; /*!< Holding [31:0]. Temporary storage used for processing. Begins
- with Initialization Vector (IV). */
- } HOLDING0_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t HOLDING1; /*!< Holding [63:32]. Temporary storage used for processing. Begins
- with Initialization Vector (IV). */
-
- struct {
- __O uint32_t HOLDING1 : 32; /*!< Holding [63:32]. Temporary storage used for processing. Begins
- with Initialization Vector (IV). */
- } HOLDING1_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t HOLDING2; /*!< Holding [95:64]. Temporary storage used for processing. Begins
- with Initialization Vector (IV). */
-
- struct {
- __O uint32_t HOLDING2 : 32; /*!< Holding [95:64]. Temporary storage used for processing. Begins
- with Initialization Vector (IV). */
- } HOLDING2_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t HOLDING3; /*!< Holding [127:96]. Temporary storage used for processing. Begins
- with Initialization Vector (IV). */
-
- struct {
- __IO uint32_t HOLDING3 : 32; /*!< Holding [127:96]. Temporary storage used for processing. Begins
- with Initialization Vector (IV). */
- } HOLDING3_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t OUT0; /*!< Output Text [31:0]. Contains the output data from processing.
- Typically holds ciphertext when encrypting and plaintext when
- decrypting. */
-
- struct {
- __I uint32_t OUT0 : 32; /*!< Output Text [31:0]. Contains the output data from processing.
- Typically holds ciphertext when encrypting and plaintext when
- decrypting. */
- } OUT0_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t OUT1; /*!< Output Text [63:32]. Contains the output data from processing.
- Typically holds ciphertext when encrypting and plaintext when
- decrypting. */
-
- struct {
- __I uint32_t OUT1 : 32; /*!< Output Text [63:32]. Contains the output data from processing.
- Typically holds ciphertext when encrypting and plaintext when
- decrypting. */
- } OUT1_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t OUT2; /*!< Output Text [95:64]. Contains the output data from processing.
- Typically holds ciphertext when encrypting and plaintext when
- decrypting. */
-
- struct {
- __I uint32_t OUT2 : 32; /*!< Output Text [95:64]. Contains the output data from processing.
- Typically holds ciphertext when encrypting and plaintext when
- decrypting. */
- } OUT2_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t OUT3; /*!< Output Text [127:96]. Contains the output data from processing.
- Typically holds ciphertext when encrypting and plaintext when
- decrypting. */
-
- struct {
- __I uint32_t OUT3 : 32; /*!< Output Text [127:96]. Contains the output data from processing.
- Typically holds ciphertext when encrypting and plaintext when
- decrypting. */
- } OUT3_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t GF128_Y0; /*!< GF128 Y [31:0]. Contains Y input of GF128 hash. */
-
- struct {
- __O uint32_t GF128_Y0 : 32; /*!< GF128 Y [31:0]. Contains Y input of GF128 hash. */
- } GF128_Y0_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t GF128_Y1; /*!< GF128 Y [63:32]. Contains Y input of GF128 hash. */
-
- struct {
- __O uint32_t GF128_Y1 : 32; /*!< GF128 Y [63:32]. Contains Y input of GF128 hash. */
- } GF128_Y1_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t GF128_Y2; /*!< GF128 Y [95:64]. Contains Y input of GF128 hash. */
-
- struct {
- __O uint32_t GF128_Y2 : 32; /*!< GF128 Y [95:64]. Contains Y input of GF128 hash. */
- } GF128_Y2_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t GF128_Y3; /*!< GF128 Y [127:96]. Contains Y input of GF128 hash. */
-
- struct {
- __O uint32_t GF128_Y3 : 32; /*!< GF128 Y [127:96]. Contains Y input of GF128 hash. */
- } GF128_Y3_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t GF128_Z0; /*!< GF128 Z [31:0]. Holds the results of the GF-128 hash. Used in
- GCM modes for authentication. */
-
- struct {
- __I uint32_t GF128_Z0 : 32; /*!< GF128 Z [31:0]. Holds the results of the GF-128 hash. Used in
- GCM modes for authentication. */
- } GF128_Z0_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t GF128_Z1; /*!< GF128 Z [63:32]. Holds the results of the GF-128 hash. Used
- in GCM modes for authentication. */
-
- struct {
- __I uint32_t GF128_Z1 : 32; /*!< GF128 Z [63:32]. Holds the results of the GF-128 hash. Used
- in GCM modes for authentication. */
- } GF128_Z1_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t GF128_Z2; /*!< GF128 Z [95:64]. Holds the results of the GF-128 hash. Used
- in GCM modes for authentication. */
-
- struct {
- __I uint32_t GF128_Z2 : 32; /*!< GF128 Z [95:64]. Holds the results of the GF-128 hash. Used
- in GCM modes for authentication. */
- } GF128_Z2_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t GF128_Z3; /*!< GF128 Z [127:96]. Holds the results of the GF-128 hash. Used
- in GCM modes for authentication. */
-
- struct {
- __I uint32_t GF128_Z3 : 32; /*!< GF128 Z [127:96]. Holds the results of the GF-128 hash. Used
- in GCM modes for authentication. */
- } GF128_Z3_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t GCM_TAG0; /*!< GCM Tag [31:0]. Calculated by XORing Output Text and GF128 Z. */
-
- struct {
- __I uint32_t GCM_TAG0 : 32; /*!< GCM Tag [31:0]. Calculated by XORing Output Text and GF128 Z. */
- } GCM_TAG0_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t GCM_TAG1; /*!< GCM Tag [63:32]. Calculated by XORing Output Text and GF128
- Z. */
-
- struct {
- __I uint32_t GCM_TAG1 : 32; /*!< GCM Tag [63:32]. Calculated by XORing Output Text and GF128
- Z. */
- } GCM_TAG1_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t GCM_TAG2; /*!< GCM Tag [95:64]. Calculated by XORing Output Text and GF128
- Z. */
-
- struct {
- __I uint32_t GCM_TAG2 : 32; /*!< GCM Tag [95:64]. Calculated by XORing Output Text and GF128
- Z. */
- } GCM_TAG2_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t GCM_TAG3; /*!< GCM Tag [127:96]. Calculated by XORing Output Text and GF128
- Z. */
-
- struct {
- __I uint32_t GCM_TAG3 : 32; /*!< GCM Tag [127:96]. Calculated by XORing Output Text and GF128
- Z. */
- } GCM_TAG3_b; /*!< BitSize */
- };
-} u_aes256_Type;
-
-
-/* ================================================================================ */
-/* ================ u_mailbox ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component mailbox It is a Mailbox for inter CPU communication with AHB bus interface. More details will follow. (u_mailbox)
- */
-
-typedef struct { /*!< u_mailbox Structure */
-
- union {
- __IO uint32_t IRQ0; /*!< Interrupt request register for the Cortex-M4 0 CPU. */
-
- struct {
- __IO uint32_t INTREQ0 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ1 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ2 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ3 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ4 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ5 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ6 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ7 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ8 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ9 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ10 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ11 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ12 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ13 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ14 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ15 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ16 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ17 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ18 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ19 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ20 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ21 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ22 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ23 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ24 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ25 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ26 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ27 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ28 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ29 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ30 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- __IO uint32_t INTREQ31 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 1 interrupt controller. */
- } IRQ0_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t IRQ0SET; /*!< Set bits in IRQ0 */
-
- struct {
- __O uint32_t INTREQSET0 : 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET1 : 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET2 : 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET3 : 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET4 : 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET5 : 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET6 : 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET7 : 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET8 : 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET9 : 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET10: 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET11: 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET12: 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET13: 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET14: 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET15: 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET16: 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET17: 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET18: 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET19: 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET20: 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET21: 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET22: 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET23: 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET24: 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET25: 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET26: 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET27: 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET28: 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET29: 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET30: 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQSET31: 1; /*!< Writing 1 sets the corresponding bit in the IRQ0 register. */
- } IRQ0SET_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t IRQ0CLR; /*!< Clear bits in IRQ0 */
-
- struct {
- __O uint32_t INTREQCLR0 : 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR1 : 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR2 : 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR3 : 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR4 : 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR5 : 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR6 : 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR7 : 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR8 : 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR9 : 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR10: 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR11: 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR12: 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR13: 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR14: 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR15: 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR16: 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR17: 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR18: 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR19: 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR20: 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR21: 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR22: 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR23: 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR24: 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR25: 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR26: 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR27: 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR28: 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR29: 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR30: 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- __O uint32_t INTREQCLR31: 1; /*!< Writing 1 clears the corresponding bit in the IRQ0 register. */
- } IRQ0CLR_b; /*!< BitSize */
- };
- __I uint32_t RESERVED0;
-
- union {
- __IO uint32_t IRQ1; /*!< Interrupt request register for the Cortex-M4 1 CPU. */
-
- struct {
- __IO uint32_t INTREQ0 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ1 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ2 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ3 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ4 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ5 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ6 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ7 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ8 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ9 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ10 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ11 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ12 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ13 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ14 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ15 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ16 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ17 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ18 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ19 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ20 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ21 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ22 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ23 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ24 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ25 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ26 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ27 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ28 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ29 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ30 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- __IO uint32_t INTREQ31 : 1; /*!< If any bit is set, an interrupt request is sent to the Cortex-M4
- 0 interrupt controller. */
- } IRQ1_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t IRQ1SET; /*!< Set bits in IRQ1 */
-
- struct {
- __O uint32_t INTREQSET0 : 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET1 : 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET2 : 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET3 : 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET4 : 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET5 : 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET6 : 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET7 : 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET8 : 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET9 : 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET10: 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET11: 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET12: 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET13: 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET14: 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET15: 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET16: 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET17: 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET18: 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET19: 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET20: 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET21: 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET22: 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET23: 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET24: 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET25: 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET26: 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET27: 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET28: 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET29: 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET30: 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQSET31: 1; /*!< Writing 1 sets the corresponding bit in the IRQ1 register. */
- } IRQ1SET_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t IRQ1CLR; /*!< Clear bits in IRQ1 */
-
- struct {
- __O uint32_t INTREQCLR0 : 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR1 : 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR2 : 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR3 : 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR4 : 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR5 : 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR6 : 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR7 : 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR8 : 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR9 : 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR10: 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR11: 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR12: 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR13: 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR14: 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR15: 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR16: 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR17: 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR18: 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR19: 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR20: 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR21: 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR22: 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR23: 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR24: 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR25: 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR26: 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR27: 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR28: 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR29: 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR30: 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- __O uint32_t INTREQCLR31: 1; /*!< Writing 1 clears the corresponding bit in the IRQ1 register. */
- } IRQ1CLR_b; /*!< BitSize */
- };
- __I uint32_t RESERVED1[55];
-
- union {
- __IO uint32_t MUTEX; /*!< Mutual exclusion register */
-
- struct {
- __IO uint32_t EX : 1; /*!< Cleared when read, set when written. This register provides
- an Inter-Processor Communication handshake. When read for any
- reason, the current value will be returned and the bit will
- be cleared. The bit will be set again following any write. */
- } MUTEX_b; /*!< BitSize */
- };
-} u_mailbox_Type;
-
-
-/* ================================================================================ */
-/* ================ u_adc ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component adc It is General Purpose ADC. More details will follow. (u_adc)
- */
-
-typedef struct { /*!< u_adc Structure */
-
- union {
- __IO uint32_t CTRL; /*!< ADC Control register. Contains the clock divide value, resolution
- selection, sampling time selection, and mode controls. */
-
- struct {
- __IO uint32_t CLKDIV : 8; /*!< In synchronous mode only, the system clock is divided by this
- value plus one to produce the clock for the ADC converter, which
- should be less than or equal to 4 MHz. (default value base on
- 32MHz system clock) Typically, software should program the smallest
- value in this field that yields this maximum clock rate or slightly
- less, but in certain cases (such as a high-impedance analog
- source) a slower clock may be desirable. Remark: This field
- is ignored in the asynchronous operating mode. */
- __IO uint32_t ASYNMODE : 1; /*!< Select clock mode. 0 Synchronous mode. The ADC clock is derived
- from the system clock based on the divide value selected in
- the CLKDIV field. The ADC clock will be started in a controlled
- fashion in response to a trigger to eliminate any uncertainty
- in the launching of an ADC conversion in response to any synchronous
- (on-chip) trigger. In Synchronous mode with the SYNCBYPASS bit
- (in a sequence control register) set, sampling of the ADC input
- and start of conversion will initiate 2 system clocks after
- the l */
- __IO uint32_t RESOL : 2; /*!< The number of bits of ADC resolution. Accuracy can be reduced
- to achieve higher conversion rates. A single conversion (including
- one conversion in a burst or sequence) requires the selected
- number of bits of resolution plus 3 ADC clocks. Remark: This
- field must only be altered when the ADC is fully idle. Changing
- it during any kind of ADC operation may have unpredictable results.
- Remark: ADC clock frequencies for various resolutions must not
- exceed: - 5x the system clock rate for 12-bit resolution - 4.3x
- t */
- __IO uint32_t RESOL_MASK_DIS: 1; /*!< According RESOL bit LSB bits are automatickly masked if RESOL_MASK_DIS
- = 0. If RESOL_MASK_DIS = 1, the 12bits comming from ADC are
- directly connect to register RESULT */
- __IO uint32_t TSAMP : 3; /*!< Sample Time. The default sampling period (TSAMP = 000 ) at the
- start of each conversion is 2.5 ADC clock periods. Depending
- on a variety of factors, including operating conditions and
- the output impedance of the analog source, longer sampling times
- may be required. The TSAMP field specifies the number of additional
- ADC clock cycles, from zero to seven, by which the sample period
- will be extended. The total conversion time will increase by
- the same number of clocks. 000 - The sample period will be the
- defau */
- } CTRL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t INSEL; /*!< Input Select. Allows selection input to ADC channel X. */
-
- struct {
- __IO uint32_t INSEL : 32; /*!< Input Select. Allows selection input to ADC channel X. */
- } INSEL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t SEQA_CTRL; /*!< ADC Conversion Sequence-A control register: Controls triggering
- and channel selection for conversion sequence-A. Also specifies
- interrupt mode for sequence-A. */
-
- struct {
- __IO uint32_t CHANNELS : 8; /*!< Selects which one or more of the ADC channels will be sampled
- and converted when this sequence is launched. A 1 in any bit
- of this field will cause the corresponding channel to be included
- in the conversion sequence, where bit 0 corresponds to channel
- 0, bit 1 to channel 1 and so forth. When this conversion sequence
- is triggered, either by a hardware trigger or via software command,
- ADC conversions will be performed on each enabled channel, in
- sequence, beginning with the lowest-ordered channel. Remark:
- Th */
- uint32_t : 4;
- __IO uint32_t TRIGGER : 6; /*!< Selects which of the available hardware trigger sources will
- cause this conversion sequence to be initiated. Program the
- trigger input number in this field. See 0 : PINT0 1 : PWM8 2
- : PWM9 3 : ARM TX EV Remark: In order to avoid generating a
- spurious trigger, it is recommended writing to this field only
- when SEQA_ENA (bit 31) is low. It is safe to change this field
- and set bit 31 in the same write. */
- __IO uint32_t TRIGPOL : 1; /*!< Select the polarity of the selected input trigger for this conversion
- sequence. Remark: In order to avoid generating a spurious trigger,
- it is recommended writing to this field only when SEQA_ENA (bit
- 31) is low. It is safe to change this field and set bit 31 in
- the same write. 0 Negative edge. A negative edge launches the
- conversion sequence on the selected trigger input. 1 Positive
- edge. A positive edge launches the conversion sequence on the
- selected trigger input. */
- __IO uint32_t SYNCBYPASS : 1; /*!< Setting this bit allows the hardware trigger input to bypass
- synchronization flip-flop stages and therefore shorten the time
- between the trigger input signal and the start of a conversion.
- There are slightly different criteria for whether or not this
- bit can be set depending on the clock operating mode: Synchronous
- mode (the ASYNMODE in the CTRL register = 0): Synchronization
- may be bypassed (this bit may be set) if the selected trigger
- source is already synchronous with the main system clock (eg.
- coming f */
- uint32_t : 5;
- __IO uint32_t START_BEHAVIOUR: 1; /*!< the Start behavior used on gpadc, writing 0 for repeat start
- after each inselection changed, writing 1 for continuous start
- Remark: with 1 the word rate is divided by two. */
- __O uint32_t START : 1; /*!< Writing a 1 to this field will launch one pass through this
- conversion sequence. The behavior will be identical to a sequence
- triggered by a hardware trigger. Do not write 1 to this bit
- if the BURST bit is set. Remark: This bit is only set to a 1
- momentarily when written to launch a conversion sequence. It
- will consequently always read back as a zero. */
- __IO uint32_t BURST : 1; /*!< Writing a 1 to this bit will cause this conversion sequence
- to be continuously cycled through. Other sequence A triggers
- will be ignored while this bit is set. Repeated conversions
- can be halted by clearing this bit. The sequence currently in
- progress will be completed before conversions are terminated.
- Note that a new sequence could begin just before BURST is cleared. */
- __IO uint32_t SINGLESTEP : 1; /*!< When this bit is set, a hardware trigger or a write to the START
- bit will launch a single conversion on the next channel in the
- sequence instead of the default response of launching an entire
- sequence of conversions. Once all of the channels comprising
- a sequence have been converted, a subsequent trigger will repeat
- the sequence beginning with the first enabled channel. Interrupt
- generation will still occur either after each individual conversion
- or at the end of the entire sequence, depending on the state */
- __IO uint32_t LOWPRIO : 1; /*!< Set priority for sequence A. 0 Low priority. Any B trigger which
- occurs while an A conversion sequence is active will be ignored
- and lost. 1 High priority. Setting this bit to a 1 will permit
- any enabled B sequence trigger (including a B sequence software
- start) to immediately interrupt sequence A and launch a B sequence
- in it s place. The conversion currently in progress will be
- terminated. The A sequence that was interrupted will automatically
- resume after the B sequence completes. The channel whose conv */
- __IO uint32_t MODE : 1; /*!< Indicates whether the primary method for retrieving conversion
- results for this sequence will be accomplished via reading the
- global data register (SEQA_GDAT) at the end of each conversion,
- or the individual channel result registers at the end of the
- entire sequence. Impacts when conversion-complete interrupt/DMA
- trigger for sequence-A will be generated and which overrun conditions
- contribute to an overrun interrupt as described below. 0 End
- of conversion. The sequence A interrupt/DMA trigger will be
- set a */
- __IO uint32_t SEQA_ENA : 1; /*!< Sequence Enable. In order to avoid spuriously triggering the
- sequence, care should be taken to only set the SEQA_ENA bit
- when the selected trigger input is in its INACTIVE state (as
- defined by the TRIGPOL bit). If this condition is not met, the
- sequence will be triggered immediately upon being enabled. Remark:
- In order to avoid spuriously triggering the sequence, care should
- be taken to only set the SEQA_ENA bit when the selected trigger
- input is in its INACTIVE state (as defined by the TRIGPOL bit).
- If th */
- } SEQA_CTRL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t SEQB_CTRL; /*!< ADC Conversion Sequence-B Control register: Controls triggering
- and channel selection for conversion sequence-B. Also specifies
- interrupt mode for sequence-B. */
-
- struct {
- __IO uint32_t CHANNELS : 8; /*!< Selects which one or more of the ADC channels will be sampled
- and converted when this sequence is launched. A 1 in any bit
- of this field will cause the corresponding channel to be included
- in the conversion sequence, where bit 0 corresponds to channel
- 0, bit 1 to channel 1 and so forth. When this conversion sequence
- is triggered, either by a hardware trigger or via software command,
- ADC conversions will be performed on each enabled channel, in
- sequence, beginning with the lowest-ordered channel. Remark:
- Th */
- uint32_t : 4;
- __IO uint32_t TRIGGER : 6; /*!< Selects which of the available hardware trigger sources will
- cause this conversion sequence to be initiated. Program the
- trigger input number in this field. See 0 : PINT0 1 : PWM8 2
- : PWM9 3 : ARM TX EV Remark: In order to avoid generating a
- spurious trigger, it is recommended writing to this field only
- when SEQB_ENA (bit 31) is low. It is safe to change this field
- and set bit 31 in the same write. */
- __IO uint32_t TRIGPOL : 1; /*!< Select the polarity of the selected input trigger for this conversion
- sequence. Remark: In order to avoid generating a spurious trigger,
- it is recommended writing to this field only when SEQB_ENA (bit
- 31) is low. It is safe to change this field and set bit 31 in
- the same write. 0 Negative edge. A negative edge launches the
- conversion sequence on the selected trigger input. 1 Positive
- edge. A positive edge launches the conversion sequence on the
- selected trigger input. */
- __IO uint32_t SYNCBYPASS : 1; /*!< Setting this bit allows the hardware trigger input to bypass
- synchronization flip-flop stages and therefore shorten the time
- between the trigger input signal and the start of a conversion.
- There are slightly different criteria for whether or not this
- bit can be set depending on the clock operating mode: Synchronous
- mode (the ASYNMODE in the CTRL register = 0): Synchronization
- may be bypassed (this bit may be set) if the selected trigger
- source is already synchronous with the main system clock (eg.
- coming f */
- uint32_t : 5;
- __IO uint32_t START_BEHAVIOUR: 1; /*!< the Start behavior used on gpadc, writing 0 for repeat start
- after each inselection changed, writing 1 for continuous start
- Remark: with 1 the word rate is divided by two. */
- __O uint32_t START : 1; /*!< Writing a 1 to this field will launch one pass through this
- conversion sequence. The behavior will be identical to a sequence
- triggered by a hardware trigger. Do not write 1 to this bit
- if the BURST bit is set. Remark: This bit is only set to a 1
- momentarily when written to launch a conversion sequence. It
- will consequently always read back as a zero. */
- __IO uint32_t BURST : 1; /*!< Writing a 1 to this bit will cause this conversion sequence
- to be continuously cycled through. Other sequence A triggers
- will be ignored while this bit is set. Repeated conversions
- can be halted by clearing this bit. The sequence currently in
- progress will be completed before conversions are terminated.
- Note that a new sequence could begin just before BURST is cleared. */
- __IO uint32_t SINGLESTEP : 1; /*!< When this bit is set, a hardware trigger or a write to the START
- bit will launch a single conversion on the next channel in the
- sequence instead of the default response of launching an entire
- sequence of conversions. Once all of the channels comprising
- a sequence have been converted, a subsequent trigger will repeat
- the sequence beginning with the first enabled channel. Interrupt
- generation will still occur either after each individual conversion
- or at the end of the entire sequence, depending on the state */
- uint32_t : 1;
- __IO uint32_t MODE : 1; /*!< Indicates whether the primary method for retrieving conversion
- results for this sequence will be accomplished via reading the
- global data register (SEQB_GDAT) at the end of each conversion,
- or the individual channel result registers at the end of the
- entire sequence. Impacts when conversion-complete interrupt/DMA
- trigger for sequence-A will be generated and which overrun conditions
- contribute to an overrun interrupt as described below. 0 End
- of conversion. The sequence A interrupt/DMA trigger will be
- set a */
- __IO uint32_t SEQB_ENA : 1; /*!< Sequence Enable. In order to avoid spuriously triggering the
- sequence, care should be taken to only set the SEQB_ENA bit
- when the selected trigger input is in its INACTIVE state (as
- defined by the TRIGPOL bit). If this condition is not met, the
- sequence will be triggered immediately upon being enabled. Remark:
- In order to avoid spuriously triggering the sequence, care should
- be taken to only set the SEQB_ENA bit when the selected trigger
- input is in its INACTIVE state (as defined by the TRIGPOL bit).
- If th */
- } SEQB_CTRL_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t SEQA_GDAT; /*!< ADC Sequence-A Global Data register. This register contains
- the result of the most recent ADC conversion performed under
- sequence-A. */
-
- struct {
- uint32_t : 4;
- __I uint32_t RESULT : 12; /*!< This field contains the 12-bit ADC conversion result from the
- most recent conversion performed under conversion sequence associated
- with this register. The result is a binary fraction representing
- the voltage on the currently-selected input channel as it falls
- within the range of VREFP to VREFN. Zero in the field indicates
- that the voltage on the input pin was less than, equal to, or
- close to that on VREFN, while 0xFFF indicates that the voltage
- on the input was close to, equal to, or greater than that on
- */
- __I uint32_t THCMPRANGE : 2; /*!< Threshold Range Comparison result. 0x0 = In Range: The last
- completed conversion was greater than or equal to the value
- programmed into the designated LOW threshold register (THRn_LOW)
- but less than or equal to the value programmed into the designated
- HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The
- last completed conversion on was less than the value programmed
- into the designated LOW threshold register (THRn_LOW). 0x2 =
- Above Range: The last completed conversion was greater than
- the value prog */
- __I uint32_t THCMPCROSS : 2; /*!< Threshold Crossing Comparison result. 0x0 = No threshold Crossing
- detected: The most recent completed conversion on this channel
- had the same relationship (above or below) to the threshold
- value established by the designated LOW threshold register (THRn_LOW)
- as did the previous conversion on this channel. 0x1 = Reserved.
- 0x2 = Downward Threshold Crossing Detected. Indicates that a
- threshold crossing in the downward direction has occurred -
- i.e. the previous sample on this channel was above the threshold
- va */
- uint32_t : 6;
- __I uint32_t CHN : 4; /*!< These bits contain the channel from which the RESULT bits were
- converted (e.g. 0000 identifies channel 0, 0001 channel 1, etc.). */
- __I uint32_t OVERRUN : 1; /*!< This bit is set if a new conversion result is loaded into the
- RESULT field before a previous result has been read - i.e. while
- the DATAVALID bit is set. This bit is cleared, along with the
- DATAVALID bit, whenever this register is read. This bit will
- contribute to an overrun interrupt/DMA trigger if the MODE bit
- (in SEQA_CTRL) for the corresponding sequence is set to 0 (and
- if the overrun interrupt is enabled). */
- __I uint32_t DATAVALID : 1; /*!< This bit is set to 1 at the end of each conversion when a new
- result is loaded into the RESULT field. It is cleared whenever
- this register is read. This bit will cause a conversion-complete
- interrupt for the corresponding sequence if the MODE bit (in
- SEQA_CTRL) for that sequence is set to 0 (and if the interrupt
- is enabled). */
- } SEQA_GDAT_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t SEQB_GDAT; /*!< ADC Sequence-B Global Data register. This register contains
- the result of the most recent ADC conversion performed under
- sequence-B. */
-
- struct {
- uint32_t : 4;
- __I uint32_t RESULT : 12; /*!< This field contains the 12-bit ADC conversion result from the
- most recent conversion performed under conversion sequence associated
- with this register. The result is a binary fraction representing
- the voltage on the currently-selected input channel as it falls
- within the range of VREFP to VREFN. Zero in the field indicates
- that the voltage on the input pin was less than, equal to, or
- close to that on VREFN, while 0xFFF indicates that the voltage
- on the input was close to, equal to, or greater than that on
- */
- __I uint32_t THCMPRANGE : 2; /*!< Threshold Range Comparison result. 0x0 = In Range: The last
- completed conversion was greater than or equal to the value
- programmed into the designated LOW threshold register (THRn_LOW)
- but less than or equal to the value programmed into the designated
- HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The
- last completed conversion on was less than the value programmed
- into the designated LOW threshold register (THRn_LOW). 0x2 =
- Above Range: The last completed conversion was greater than
- the value prog */
- __I uint32_t THCMPCROSS : 2; /*!< Threshold Crossing Comparison result. 0x0 = No threshold Crossing
- detected: The most recent completed conversion on this channel
- had the same relationship (above or below) to the threshold
- value established by the designated LOW threshold register (THRn_LOW)
- as did the previous conversion on this channel. 0x1 = Reserved.
- 0x2 = Downward Threshold Crossing Detected. Indicates that a
- threshold crossing in the downward direction has occurred -
- i.e. the previous sample on this channel was above the threshold
- va */
- uint32_t : 6;
- __I uint32_t CHN : 4; /*!< These bits contain the channel from which the RESULT bits were
- converted (e.g. 0000 identifies channel 0, 0001 channel 1, etc.). */
- __I uint32_t OVERRUN : 1; /*!< This bit is set if a new conversion result is loaded into the
- RESULT field before a previous result has been read - i.e. while
- the DATAVALID bit is set. This bit is cleared, along with the
- DATAVALID bit, whenever this register is read. This bit will
- contribute to an overrun interrupt/DMA trigger if the MODE bit
- (in SEQB_CTRL) for the corresponding sequence is set to 0 (and
- if the overrun interrupt is enabled). */
- __I uint32_t DATAVALID : 1; /*!< This bit is set to 1 at the end of each conversion when a new
- result is loaded into the RESULT field. It is cleared whenever
- this register is read. This bit will cause a conversion-complete
- interrupt for the corresponding sequence if the MODE bit (in
- SEQB_CTRL) for that sequence is set to 0 (and if the interrupt
- is enabled). */
- } SEQB_GDAT_b; /*!< BitSize */
- };
- __I uint32_t RESERVED0[2];
-
- union {
- __I uint32_t DAT[8]; /*!< ADC Channel X [0:7] Data register. This register contains the
- result of the most recent conversion completed on channel X
- [0:7] . */
-
- struct {
- uint32_t : 4;
- __I uint32_t RESULT : 12; /*!< This field contains the 12-bit ADC conversion result from the
- last conversion performed on this channel. This will be a binary
- fraction representing the voltage on the AD0[n] pin, as it falls
- within the range of VREFP to VREFN. Zero in the field indicates
- that the voltage on the input pin was less than, equal to, or
- close to that on VREFN, while 0xFFF indicates that the voltage
- on the input was close to, equal to, or greater than that on
- VREFP. */
- __I uint32_t THCMPRANGE : 2; /*!< Threshold Range Comparison result. 0x0 = In Range: The last
- completed conversion was greater than or equal to the value
- programmed into the designated LOW threshold register (THRn_LOW)
- but less than or equal to the value programmed into the designated
- HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The
- last completed conversion on was less than the value programmed
- into the designated LOW threshold register (THRn_LOW). 0x2 =
- Above Range: The last completed conversion was greater than
- the value prog */
- __I uint32_t THCMPCROSS : 2; /*!< Threshold Crossing Comparison result. 0x0 = No threshold Crossing
- detected: The most recent completed conversion on this channel
- had the same relationship (above or below) to the threshold
- value established by the designated LOW threshold register (THRn_LOW)
- as did the previous conversion on this channel. 0x1 = Reserved.
- 0x2 = Downward Threshold Crossing Detected. Indicates that a
- threshold crossing in the downward direction has occurred -
- i.e. the previous sample on this channel was above the threshold
- va */
- uint32_t : 6;
- __I uint32_t CHN : 4; /*!< This field is hard-coded to contain the channel number that
- this particular register relates to (i.e. this field will contain
- 0b0000 for the DAT0 register, 0b0001 for the DAT1 register,
- etc) */
- __I uint32_t OVERRUN : 1; /*!< This bit will be set to a 1 if a new conversion on this channel
- completes and overwrites the previous contents of the RESULT
- field before it has been read - i.e. while the DONE bit is set.
- This bit is cleared, along with the DONE bit, whenever this
- register is read or when the data related to this channel is
- read from either of the global SEQn_GDAT registers. This bit
- (in any of the 12 registers) will cause an overrun interrupt/DMA
- trigger to be asserted if the overrun interrupt is enabled.
- Remark: While i */
- __I uint32_t DATAVALID : 1; /*!< This bit is set to 1 when an ADC conversion on this channel
- completes. This bit is cleared whenever this register is read
- or when the data related to this channel is read from either
- of the global SEQn_GDAT registers. Remark: While it is allowed
- to include the same channels in both conversion sequences, doing
- so may cause erratic behavior of the DONE and OVERRUN bits in
- the data registers associated with any of the channels that
- are shared between the two sequences. Any erratic OVERRUN behavior
- will also a */
- } DAT_b[8]; /*!< BitSize */
- };
- __I uint32_t RESERVED1[4];
-
- union {
- __IO uint32_t THR0_LOW; /*!< ADC Low Compare Threshold register 0: Contains the lower threshold
- level for automatic threshold comparison for any channels linked
- to threshold pair 0. */
-
- struct {
- uint32_t : 4;
- __IO uint32_t THRLOW : 12; /*!< Low threshold value against which ADC results will be compared */
- } THR0_LOW_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t THR1_LOW; /*!< ADC Low Compare Threshold register 1: Contains the lower threshold
- level for automatic threshold comparison for any channels linked
- to threshold pair 1. */
-
- struct {
- uint32_t : 4;
- __IO uint32_t THRLOW : 12; /*!< Low threshold value against which ADC results will be compared */
- } THR1_LOW_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t THR0_HIGH; /*!< ADC High Compare Threshold register 0: Contains the upper threshold
- level for automatic threshold comparison for any channels linked
- to threshold pair 0. */
-
- struct {
- uint32_t : 4;
- __IO uint32_t THRHIGH : 12; /*!< High threshold value against which ADC results will be compared */
- } THR0_HIGH_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t THR1_HIGH; /*!< ADC High Compare Threshold register 1: Contains the upper threshold
- level for automatic threshold comparison for any channels linked
- to threshold pair 1. */
-
- struct {
- uint32_t : 4;
- __IO uint32_t THRHIGH : 12; /*!< High threshold value against which ADC results will be compared */
- } THR1_HIGH_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t CHAN_THRSEL; /*!< ADC Channel-Threshold Select register. Specifies which set of
- threshold compare registers are to be used for each channel */
-
- struct {
- __IO uint32_t CH0_THRSEL : 1; /*!< Threshold select for channel 0. 0 Threshold 0. Results for this
- channel will be compared against the threshold levels indicated
- in the THR0_LOW and THR0_HIGH registers. 1 Threshold 1. Results
- for this channel will be compared against the threshold levels
- indicated in the THR1_LOW and THR1_HIGH registers. */
- __IO uint32_t CH1_THRSEL : 1; /*!< Threshold select for channel 1. See description for channel
- 0. */
- __IO uint32_t CH2_THRSEL : 1; /*!< Threshold select for channel 2. See description for channel
- 0. */
- __IO uint32_t CH3_THRSEL : 1; /*!< Threshold select for channel 3. See description for channel
- 0. */
- __IO uint32_t CH4_THRSEL : 1; /*!< Threshold select for channel 4. See description for channel
- 0. */
- __IO uint32_t CH5_THRSEL : 1; /*!< Threshold select for channel 5. See description for channel
- 0. */
- __IO uint32_t CH6_THRSEL : 1; /*!< Threshold select for channel 6. See description for channel
- 0. */
- __IO uint32_t CH7_THRSEL : 1; /*!< Threshold select for channel 7. See description for channel
- 0. */
- } CHAN_THRSEL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t INTEN; /*!< ADC Interrupt Enable register. This register contains enable
- bits that enable the sequence-A, sequence-B, threshold compare
- and data overrun interrupts to be generated. */
-
- struct {
- __IO uint32_t SEQA_INTEN : 1; /*!< Sequence A interrupt enable. 0 Disabled. The sequence A interrupt/DMA
- trigger is disabled. 1 Enabled. The sequence A interrupt/DMA
- trigger is enabled and will be asserted either upon completion
- of each individual conversion performed as part of sequence
- A, or upon completion of the entire A sequence of conversions,
- depending on the MODE bit in the SEQA_CTRL register. */
- __IO uint32_t SEQB_INTEN : 1; /*!< Sequence B interrupt enable. 0 Disabled. The sequence B interrupt/DMA
- trigger is disabled. 1 Enabled. The sequence B interrupt/DMA
- trigger is enabled and will be asserted either upon completion
- of each individual conversion performed as part of sequence
- B, or upon completion of the entire B sequence of conversions,
- depending on the MODE bit in the SEQB_CTRL register. */
- __IO uint32_t OVR_INTEN : 1; /*!< Overrun interrupt enable. 0 Disabled. The overrun interrupt
- is disabled. 1 Enabled. The overrun interrupt is enabled. Detection
- of an overrun condition on any of the 12 channel data registers
- will cause an overrun interrupt/DMA trigger. In addition, if
- the MODE bit for a particular sequence is 0, then an overrun
- in the global data register for that sequence will also cause
- this interrupt/DMA trigger to be asserted. */
- __IO uint32_t ADCMPINTEN0: 2; /*!< Threshold comparison interrupt enable for channel 0. 0x0 Disabled.
- 0x1 Outside threshold. 0x2 Crossing threshold. 0x3 Reserved */
- __IO uint32_t ADCMPINTEN1: 2; /*!< Channel 1 threshold comparison interrupt enable. See description
- for channel 0. */
- __IO uint32_t ADCMPINTEN2: 2; /*!< Channel 2 threshold comparison interrupt enable. See description
- for channel 0. */
- __IO uint32_t ADCMPINTEN3: 2; /*!< Channel 3 threshold comparison interrupt enable. See description
- for channel 0. */
- __IO uint32_t ADCMPINTEN4: 2; /*!< Channel 4 threshold comparison interrupt enable. See description
- for channel 0. */
- __IO uint32_t ADCMPINTEN5: 2; /*!< Channel 5 threshold comparison interrupt enable. See description
- for channel 0. */
- __IO uint32_t ADCMPINTEN6: 2; /*!< Channel 6 threshold comparison interrupt enable. See description
- for channel 0. */
- __IO uint32_t ADCMPINTEN7: 2; /*!< Channel 7 threshold comparison interrupt enable. See description
- for channel 0. */
- } INTEN_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t FLAGS; /*!< ADC Flags register. Contains the four interrupt/DMA trigger
- flags and the individual component overrun and threshold-compare
- flags. (The overrun bits replicate information stored in the
- result registers). */
-
- struct {
- __I uint32_t THCMP0 : 1; /*!< Threshold comparison event on Channel 0. Set to 1 upon either
- an out-of-range result or a threshold-crossing result if enabled
- to do so in the INTEN register. This bit is cleared by writing
- a 1. */
- __I uint32_t THCMP1 : 1; /*!< Threshold comparison event on Channel 1. See description for
- channel 0. */
- __I uint32_t THCMP2 : 1; /*!< Threshold comparison event on Channel 2. See description for
- channel 0. */
- __I uint32_t THCMP3 : 1; /*!< Threshold comparison event on Channel 3. See description for
- channel 0. */
- __I uint32_t THCMP4 : 1; /*!< Threshold comparison event on Channel 4. See description for
- channel 0. */
- __I uint32_t THCMP5 : 1; /*!< Threshold comparison event on Channel 5. See description for
- channel 0. */
- __I uint32_t THCMP6 : 1; /*!< Threshold comparison event on Channel 6. See description for
- channel 0. */
- __I uint32_t THCMP7 : 1; /*!< Threshold comparison event on Channel 7. See description for
- channel 0. */
- uint32_t : 4;
- __I uint32_t OVERRUN0 : 1; /*!< Mirrors the OVERRRUN status flag from the result register for
- ADC channel 0 */
- __I uint32_t OVERRUN1 : 1; /*!< Mirrors the OVERRRUN status flag from the result register for
- ADC channel 1 */
- __I uint32_t OVERRUN2 : 1; /*!< Mirrors the OVERRRUN status flag from the result register for
- ADC channel 2 */
- __I uint32_t OVERRUN3 : 1; /*!< Mirrors the OVERRRUN status flag from the result register for
- ADC channel 3 */
- __I uint32_t OVERRUN4 : 1; /*!< Mirrors the OVERRRUN status flag from the result register for
- ADC channel 4 */
- __I uint32_t OVERRUN5 : 1; /*!< Mirrors the OVERRRUN status flag from the result register for
- ADC channel 5 */
- __I uint32_t OVERRUN6 : 1; /*!< Mirrors the OVERRRUN status flag from the result register for
- ADC channel 6 */
- __I uint32_t OVERRUN7 : 1; /*!< Mirrors the OVERRRUN status flag from the result register for
- ADC channel 7 */
- uint32_t : 4;
- __I uint32_t SEQA_OVR : 1; /*!< Mirrors the global OVERRUN status flag in the SEQA_GDAT register */
- __I uint32_t SEQB_OVR : 1; /*!< Mirrors the global OVERRUN status flag in the SEQB_GDAT register */
- uint32_t : 2;
- __I uint32_t SEQA_INT : 1; /*!< Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL
- register is 0, this flag will mirror the DATAVALID bit in the
- sequence A global data register (SEQA_GDAT), which is set at
- the end of every ADC conversion performed as part of sequence
- A. It will be cleared automatically when the SEQA_GDAT register
- is read. If the MODE bit in the SEQA_CTRL register is 1, this
- flag will be set upon completion of an entire A sequence. In
- this case it must be cleared by writing a 1 to this SEQA_INT
- bit. This i */
- __I uint32_t SEQB_INT : 1; /*!< Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL
- register is 0, this flag will mirror the DATAVALID bit in the
- sequence A global data register (SEQB_GDAT), which is set at
- the end of every ADC conversion performed as part of sequence
- B. It will be cleared automatically when the SEQB_GDAT register
- is read. If the MODE bit in the SEQB_CTRL register is 1, this
- flag will be set upon completion of an entire B sequence. In
- this case it must be cleared by writing a 1 to this SEQB_INT
- bit. This i */
- __I uint32_t THCMP_INT : 1; /*!< Threshold Comparison Interrupt. This bit will be set if any
- of the THCMP flags in the lower bits of this register are set
- to 1 (due to an enabled out-of-range or threshold-crossing event
- on any channel). Each type of threshold comparison interrupt
- on each channel must be individually enabled in the INTEN register
- to cause this interrupt. This bit will be cleared when all of
- the individual threshold flags are cleared via writing 1s to
- those bits. */
- __I uint32_t OVR_INT : 1; /*!< Overrun Interrupt flag. Any overrun bit in any of the individual
- channel data registers will cause this interrupt. In addition,
- if the MODE bit in either of the SEQn_CTRL registers is 0 then
- the OVERRUN bit in the corresponding SEQn_GDAT register will
- also cause this interrupt. This interrupt must be enabled in
- the INTEN register. This bit will be cleared when all of the
- individual overrun bits have been cleared via reading the corresponding
- data registers. */
- } FLAGS_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t STARTUP; /*!< ADC Startup register (typically only used by the ADC API). */
-
- struct {
- __IO uint32_t ADC_ENA : 1; /*!< ADC Enable bit. This bit can only be set to a 1 by software.
- It is cleared automatically whenever the ADC is powered down.
- This bit must not be set until at least 10 microseconds after
- the ADC is powered up (typically by altering a system-level
- ADC power control bit). */
- } STARTUP_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t GPADC_CTRL0; /*!< Second ADC Control register : ADC internal LDO */
-
- struct {
- __IO uint32_t LDO_POWER_EN: 1; /*!< LDO Power enable signal (active high) */
- uint32_t : 2;
- __IO uint32_t LDO_SEL_OUT: 5; /*!< Select LDO output voltage (10mV step) [between 0.64V and 0.95V] */
- __IO uint32_t PASS_ENABLE: 1; /*!< Enable pass mode when set to high */
- __IO uint32_t GPADC_TSAMP: 5; /*!< 10100 */
- __IO uint32_t TEST : 2; /*!< test mode selection: '00': Normal functional mode '01': Multiplexer
- test mode '10': ADC in unity gain mode '11': Not used */
- __IO uint32_t SEL_ATB : 2; /*!< Select analog test bus '00': normal mode '01': atb_p = out_ana(LDO_output)
- atb_n = Vssa (LDO analog ground) '10': atb_p = out_ref (LDO
- output) atb_n = Vrefn (ADC negative reference) '11': atb_p =
- out_ana (LDO output) atb_n = ADC (ADC analog ground) */
- } GPADC_CTRL0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t GPADC_CTRL1; /*!< Third ADC Control register : ADC internal gain and offset */
-
- struct {
- __IO uint32_t OFFSET_CAL : 10; /*!< offset_cal */
- __IO uint32_t GAIN_CAL : 10; /*!< gain_cal */
- } GPADC_CTRL1_b; /*!< BitSize */
- };
-} u_adc_Type;
-
-
-/* ================================================================================ */
-/* ================ u_dmic ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component dmic It is General Purpose I/O with APB bus interface. More details will follow. (u_dmic)
- */
-
-typedef struct { /*!< u_dmic Structure */
-
- union {
- __IO uint32_t OSR0; /*!< Oversample Rate register 0 */
-
- struct {
- __IO uint32_t OSR : 8; /*!< Selects the oversample rate for the related input channel. */
- } OSR0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t DIVHFCLK0; /*!< DMIC Clock Register 0 */
-
- struct {
- __IO uint32_t PDMDIV : 4; /*!< PDM clock divider value. 0 = divide by 1 1 = divide by 2 2 =
- divide by 3 3 = divide by 4 4 = divide by 6 5 = divide by 8
- 6 = divide by 12 7 = divide by 16 8 = divide by 24 9 = divide
- by 32 10 = divide by 48 11 = divide by 64 12 = divide by 96
- 13 = divide by 128 others = reserved. */
- } DIVHFCLK0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PREAC2FSCOEF0; /*!< Pre-Emphasis Filter Coefficient for 2 FS register */
-
- struct {
- __IO uint32_t COMP : 2; /*!< Pre-emphasis filer coefficient for 2 FS mode. 0 = Compensation
- = 0 1 = Compensation = 16 2 = Compensation = 15 3 = Compensation
- = 13 */
- } PREAC2FSCOEF0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PREAC4FSCOEF0; /*!< Pre-Emphasis Filter Coefficient for 4 FS register */
-
- struct {
- __IO uint32_t COMP : 2; /*!< Pre-emphasis filer coefficient for 4 FS mode. 0 = Compensation
- = 0 1 = Compensation = 16 2 = Compensation = 15 3 = Compensation
- = 13 */
- } PREAC4FSCOEF0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t GAINSHIFT0; /*!< Decimator Gain Shift register */
-
- struct {
- __IO uint32_t GAIN : 6; /*!< Gain control, as a positive or negative (two s complement) number
- of bits to shift. */
- } GAINSHIFT0_b; /*!< BitSize */
- };
- __I uint32_t RESERVED0[27];
-
- union {
- __IO uint32_t FIFOCTRL0; /*!< FIFO Control register 0 */
-
- struct {
- __IO uint32_t ENABLE : 1; /*!< FIFO enable. 0 : FIFO is not enabled. Enabling a DMIC channel
- with the FIFO disabled could be useful while data is being streamed
- to the I2S, or in order to avoid a filter settling delay when
- a channel is re-enabled after a period when the data was not
- needed. 1 : FIFO is enabled. The FIFO must be enabled in order
- for the CPU or DMA to read data from the DMIC via the FIFODATA
- register. */
- __IO uint32_t RESET : 1; /*!< FIFO reset. 0 : Normal operation 1 : Reset the FIFO. This bit
- must be cleared before resuming operation */
- __IO uint32_t INTEN : 1; /*!< Interrupt enable. 0: FIFO level interrupts are not enabled.
- 1: FIFO level interrupts are enabled. */
- __IO uint32_t DMAEN : 1; /*!< DMA enable 0 : DMA requests are not enabled. 1 : DMA requests
- based on FIFO level are enabled. */
- uint32_t : 12;
- __IO uint32_t TRIGLVL : 5; /*!< FIFO trigger level. Selects the data trigger level for interrupt
- or DMA operation. If enabled to do so, the FIFO level can wake
- up the device just enough to perform DMA, then return to the
- reduced power mode See Section 4.5.66 Hardware Wake-up control
- register . 0 = trigger when the FIFO has received one entry
- (is no longer empty). 1 = trigger when the FIFO has received
- two entries. 15 = trigger when the FIFO has received 16 entries
- (has become full). */
- } FIFOCTRL0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t FIFOSTAT0; /*!< FIFO Status register 0 */
-
- struct {
- __IO uint32_t INT : 1; /*!< Interrupt flag. Asserted when FIFO data reaches the level specified
- in the FIFOCTRL register. Writing a one to this bit clears the
- flag. Remark: note that the bus clock to the DMIC subsystem
- must be running in order for an interrupt to occur. */
- __IO uint32_t OVERRUN : 1; /*!< Overrun flag. Indicates that a FIFO overflow has occurred at
- some point. Writing a one to this bit clears the flag. This
- flag does not cause an interrupt. */
- __IO uint32_t UNDERRUN : 1; /*!< Underrun flag. Indicates that a FIFO underflow has occurred
- at some point. Writing a one to this bit clears the flag. */
- } FIFOSTAT0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t FIFODATA0; /*!< FIFO Data Register 0 */
-
- struct {
- __IO uint32_t DATA : 24; /*!< Data from the top of the input filter FIFO. */
- } FIFODATA0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PDMSRCCFG0; /*!< PDM Source Configuration register 0 */
-
- struct {
- __IO uint32_t PHY_FALL : 1; /*!< Capture PDM_DATA 0 : Capture PDM_DATA on the rising edge of
- PDM_CLK. 1 : Capture PDM_DATA on the falling edge of PDM_CLK. */
- __IO uint32_t PHY_HALF : 1; /*!< Half rate sampling 0 : Standard half rate sampling. The clock
- to the DMIC is sent at the same rate as the decimator is providing.
- 1 : Use half rate sampling. The clock to the DMIC is sent at
- half the rate as the decimator is providing. */
- } PDMSRCCFG0_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t DCCTRL0; /*!< DC Control register 0 */
-
- struct {
- __IO uint32_t DCPOLE : 2; /*!< DC block filter 0: Flat response, no filter. 1:155 Hz. 2:78
- Hz. 3:39 Hz */
- uint32_t : 2;
- __IO uint32_t DCGAIN : 4; /*!< Fine gain adjustment in the form of a number of bits to downshift. */
- __IO uint32_t SATURATEAT16BIT: 1; /*!< Selects 16-bit saturation. 0:Results roll over if out range
- and do not saturate. 1:If the result overflows, it saturates
- at 0xFFFF for positive overflow and 0x8000 for negative overflow. */
- } DCCTRL0_b; /*!< BitSize */
- };
- __I uint32_t RESERVED1[27];
-
- union {
- __IO uint32_t OSR1; /*!< Oversample Rate register 1 */
-
- struct {
- __IO uint32_t OSR : 8; /*!< Selects the oversample rate for the related input channel. */
- } OSR1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t DIVHFCLK1; /*!< DMIC Clock Register 1 */
-
- struct {
- __IO uint32_t PDMDIV : 4; /*!< PDM clock divider value. 0 = divide by 1 1 = divide by 2 2 =
- divide by 3 3 = divide by 4 4 = divide by 6 5 = divide by 8
- 6 = divide by 12 7 = divide by 16 8 = divide by 24 9 = divide
- by 32 10 = divide by 48 11 = divide by 64 12 = divide by 96
- 13 = divide by 128 others = reserved. */
- } DIVHFCLK1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PREAC2FSCOEF1; /*!< Pre-Emphasis Filter Coefficient for 2 FS register */
-
- struct {
- __IO uint32_t COMP : 2; /*!< Pre-emphasis filer coefficient for 2 FS mode. 0 = Compensation
- = 0 1 = Compensation = 16 2 = Compensation = 15 3 = Compensation
- = 13 */
- } PREAC2FSCOEF1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PREAC4FSCOEF1; /*!< Pre-Emphasis Filter Coefficient for 4 FS register */
-
- struct {
- __IO uint32_t COMP : 2; /*!< Pre-emphasis filer coefficient for 4 FS mode. 0 = Compensation
- = 0 1 = Compensation = 16 2 = Compensation = 15 3 = Compensation
- = 13 */
- } PREAC4FSCOEF1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t GAINSHIFT1; /*!< Decimator Gain Shift register */
-
- struct {
- __IO uint32_t GAIN : 6; /*!< Gain control, as a positive or negative (two s complement) number
- of bits to shift. */
- } GAINSHIFT1_b; /*!< BitSize */
- };
- __I uint32_t RESERVED2[27];
-
- union {
- __IO uint32_t FIFOCTRL1; /*!< FIFO Control register 1 */
-
- struct {
- __IO uint32_t ENABLE : 1; /*!< FIFO enable. 0 : FIFO is not enabled. Enabling a DMIC channel
- with the FIFO disabled could be useful while data is being streamed
- to the I2S, or in order to avoid a filter settling delay when
- a channel is re-enabled after a period when the data was not
- needed. 1 : FIFO is enabled. The FIFO must be enabled in order
- for the CPU or DMA to read data from the DMIC via the FIFODATA
- register. */
- __IO uint32_t RESET : 1; /*!< FIFO reset. 0 : Normal operation 1 : Reset the FIFO. This bit
- must be cleared before resuming operation */
- __IO uint32_t INTEN : 1; /*!< Interrupt enable. 0: FIFO level interrupts are not enabled.
- 1: FIFO level interrupts are enabled. */
- __IO uint32_t DMAEN : 1; /*!< DMA enable 0 : DMA requests are not enabled. 1 : DMA requests
- based on FIFO level are enabled. */
- uint32_t : 12;
- __IO uint32_t TRIGLVL : 5; /*!< FIFO trigger level. Selects the data trigger level for interrupt
- or DMA operation. If enabled to do so, the FIFO level can wake
- up the device just enough to perform DMA, then return to the
- reduced power mode See Section 4.5.66 Hardware Wake-up control
- register . 0 = trigger when the FIFO has received one entry
- (is no longer empty). 1 = trigger when the FIFO has received
- two entries. 15 = trigger when the FIFO has received 16 entries
- (has become full). */
- } FIFOCTRL1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t FIFOSTAT1; /*!< FIFO Status register 1 */
-
- struct {
- __IO uint32_t INT : 1; /*!< Interrupt flag. Asserted when FIFO data reaches the level specified
- in the FIFOCTRL register. Writing a one to this bit clears the
- flag. Remark: note that the bus clock to the DMIC subsystem
- must be running in order for an interrupt to occur. */
- __IO uint32_t OVERRUN : 1; /*!< Overrun flag. Indicates that a FIFO overflow has occurred at
- some point. Writing a one to this bit clears the flag. This
- flag does not cause an interrupt. */
- __IO uint32_t UNDERRUN : 1; /*!< Underrun flag. Indicates that a FIFO underflow has occurred
- at some point. Writing a one to this bit clears the flag. */
- } FIFOSTAT1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t FIFODATA1; /*!< FIFO Data Register 1 */
-
- struct {
- __IO uint32_t DATA : 24; /*!< Data from the top of the input filter FIFO. */
- } FIFODATA1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t PDMSRCCFG1; /*!< PDM Source Configuration register 1 */
-
- struct {
- __IO uint32_t PHY_FALL : 1; /*!< Capture PDM_DATA */
- __IO uint32_t PHY_HALF : 1; /*!< Half rate sampling */
- } PDMSRCCFG1_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t DCCTRL1; /*!< DC Control register 1 */
-
- struct {
- __IO uint32_t DCPOLE : 2; /*!< DC block filter */
- uint32_t : 2;
- __IO uint32_t DCGAIN : 4; /*!< Fine gain adjustment in the form of a number of bits to downshift. */
- __IO uint32_t SATURATEAT16BIT: 1; /*!< Selects 16-bit saturation. */
- } DCCTRL1_b; /*!< BitSize */
- };
- __I uint32_t RESERVED3[859];
-
- union {
- __IO uint32_t CHANEN; /*!< Channel Enable register */
-
- struct {
- __IO uint32_t EN_CH0 : 1; /*!< Enable channel 0. When 1, PDM channel 0 is enabled. */
- __IO uint32_t EN_CH1 : 1; /*!< Enable channel 1. When 1, PDM channel 1 is enabled. */
- } CHANEN_b; /*!< BitSize */
- };
- __I uint32_t RESERVED4[2];
-
- union {
- __IO uint32_t IOCFG; /*!< I/O Configuration register */
-
- struct {
- __IO uint32_t CLK_BYPASS0: 1; /*!< Bypass CLK0. When 1, PDM_DATA1 becomes the clock for PDM channel
- 0. This provides for the possibility of an external codec taking
- over the PDM bus. */
- __IO uint32_t CLK_BYPASS1: 1; /*!< Bypass CLK1. When 1, PDM_DATA1 becomes the clock for PDM channel
- 1. This provides for the possibility of an external codec taking
- over the PDM bus. */
- __IO uint32_t STEREO_DATA0: 1; /*!< Stereo PDM select. When 1, PDM_DATA0 is routed to both PDM channels
- in a configuration that supports a single stereo digital microphone. */
- } IOCFG_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t USE2FS; /*!< Use 2FS register */
-
- struct {
- __IO uint32_t USE2FS : 1; /*!< Use 2FS register 0:Use 1FS output for PCM data. 1:Use 2FS output
- for PCM data. */
- } USE2FS_b; /*!< BitSize */
- };
- __I uint32_t RESERVED5[27];
-
- union {
- __IO uint32_t HWVADGAIN; /*!< HWVAD input gain register */
-
- struct {
- __IO uint32_t INPUTGAIN : 4; /*!< Shift value for input bits 0x00 -10 bits 0x01 -8 bits 0x02 -6
- bits 0x03 -4 bits 0x04 -2 bits 0x05 0 bits (default) 0x06 +2
- bits 0x07 +4 bits 0x08 +6 bits 0x09 +8 bits 0x0A +10 bits 0x0B
- +12 bits 0x0C +14 bits 0x0D to 0x0F Reserved. */
- } HWVADGAIN_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t HWVADHPFS; /*!< HWVAD filter control register */
-
- struct {
- __IO uint32_t HPFS : 2; /*!< High pass filter 0:First filter by-pass. 1:High pass filter
- with -3dB cut-off at 1750Hz. 2:High pass filter with -3dB cut-off
- at 215Hz. 3:Reserved. */
- } HWVADHPFS_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t HWVADST10; /*!< HWVAD control register */
-
- struct {
- __IO uint32_t ST10 : 1; /*!< Stage 0 0: Normal operation, waiting for HWVAD trigger event
- (stage 0). 1: Reset internal interrupt flag by writing a 1 pulse. */
- } HWVADST10_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t HWVADRSTT; /*!< HWVAD filter reset register */
-
- struct {
- __IO uint32_t RSTT : 1; /*!< Writing a 1 resets all filter values */
- } HWVADRSTT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t HWVADTHGN; /*!< HWVAD noise estimator gain register */
-
- struct {
- __IO uint32_t THGN : 4; /*!< Gain value for the noise estimator. Values 0 to 14. 0 corresponds
- to a gain of 1. */
- } HWVADTHGN_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t HWVADTHGS; /*!< HWVAD signal estimator gain register */
-
- struct {
- __IO uint32_t THGS : 4; /*!< Gain value for the signal estimator. Values 0 to 14. 0 corresponds
- to a gain of 1. */
- } HWVADTHGS_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t HWVADLOWZ; /*!< HWVAD noise envelope estimator register */
-
- struct {
- __I uint32_t LOWZ : 16; /*!< Noise envelope estimator value. */
- } HWVADLOWZ_b; /*!< BitSize */
- };
- __I uint32_t RESERVED6[24];
-
- union {
- __I uint32_t ID; /*!< Module Identification register */
-
- struct {
- __I uint32_t ID : 32; /*!< Indicates module ID and the number of channels in this DMIC
- interface. */
- } ID_b; /*!< BitSize */
- };
-} u_dmic_Type;
-
-
-/* ================================================================================ */
-/* ================ u0_usart ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component usart. It is an Universal Synchrnous/Asynchrnous Receiver/Transmitter with APB bus interface. More details will follow. (u0_usart)
- */
-
-typedef struct { /*!< u0_usart Structure */
-
- union {
- __IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings
- that typically are not changed during operation. */
-
- struct {
- __IO uint32_t ENABLE : 1; /*!< USART Enable. */
- uint32_t : 1;
- __IO uint32_t DATALEN : 2; /*!< Selects the data size for the USART. */
- __IO uint32_t PARITYSEL : 2; /*!< Selects what type of parity is used by the USART. */
- __IO uint32_t STOPLEN : 1; /*!< Number of stop bits appended to transmitted data. Only a single
- stop bit is required for received data. */
- __IO uint32_t MODE32K : 1; /*!< Selects standard or 32 kHz clocking mode. */
- __IO uint32_t LINMODE : 1; /*!< LIN bus break mode enable. */
- __IO uint32_t CTSEN : 1; /*!< CTS Enable. Determines whether CTS is used for flow control.
- CTS can be from the input pin, or from the USART s own RTS if
- loopback mode is enabled. */
- uint32_t : 1;
- __IO uint32_t SYNCEN : 1; /*!< Selects synchronous or asynchronous operation. */
- __IO uint32_t CLKPOL : 1; /*!< Selects the clock polarity and sampling edge of received data
- in synchronous mode. */
- uint32_t : 1;
- __IO uint32_t SYNCMST : 1; /*!< Synchronous mode Master select. */
- __IO uint32_t LOOP : 1; /*!< Selects data loopback mode. */
- __IO uint32_t IOMODE : 1; /*!< I/O output mode. */
- uint32_t : 1;
- __IO uint32_t OETA : 1; /*!< Output Enable Turnaround time enable for RS-485 operation. */
- __IO uint32_t AUTOADDR : 1; /*!< Automatic Address matching enable. */
- __IO uint32_t OESEL : 1; /*!< Output Enable Select. */
- __IO uint32_t OEPOL : 1; /*!< Output Enable Polarity. */
- __IO uint32_t RXPOL : 1; /*!< Receive data polarity. */
- __IO uint32_t TXPOL : 1; /*!< Transmit data polarity. */
- } CFG_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t CTL; /*!< USART Control register. USART control settings that are more
- likely to change during operation. */
-
- struct {
- uint32_t : 1;
- __IO uint32_t TXBRKEN : 1; /*!< Break Enable. */
- __IO uint32_t ADDRDET : 1; /*!< Enable address detect mode. */
- uint32_t : 3;
- __IO uint32_t TXDIS : 1; /*!< Transmit Disable. */
- uint32_t : 1;
- __IO uint32_t CC : 1; /*!< Continuous Clock generation. By default, SCLK is only output
- while data is being transmitted in synchronous mode. */
- __IO uint32_t CLRCCONRX : 1; /*!< Clear Continuous Clock. */
- uint32_t : 6;
- __IO uint32_t AUTOBAUD : 1; /*!< Autobaud enable. */
- } CTL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t STAT; /*!< USART Status register. The complete status value can be read
- here. Writing ones clears some bits in the register. Some bits
- can be cleared by writing a 1 to them. */
-
- struct {
- uint32_t : 1;
- __I uint32_t RXIDLE : 1; /*!< Receiver Idle. When 0, indicates that the receiver is currently
- in the process of receiving data. When 1, indicates that the
- receiver is not currently in the process of receiving data. */
- uint32_t : 1;
- __I uint32_t TXIDLE : 1; /*!< Transmitter Idle. When 0, indicates that the transmitter is
- currently in the process of sending data.When 1, indicate that
- the transmitter is not currently in the process of sending data. */
- __I uint32_t CTS : 1; /*!< This bit reflects the current state of the CTS signal, regardless
- of the setting of the CTSEN bit in the CFG register. This will
- be the value of the CTS input pin unless loopback mode is enabled. */
- __IO uint32_t DELTACTS : 1; /*!< This bit is set when a change in the state is detected for the
- CTS flag above. This bit is cleared by software. */
- __I uint32_t TXDISSTAT : 1; /*!< Transmitter Disabled Status flag. When 1, this bit indicates
- that the USART transmitter is fully idle after being disabled
- via the TXDIS bit in the CFG register (TXDIS = 1). */
- uint32_t : 1;
- __IO uint32_t OVERRUNINT : 1; /*!< Overrun Error interrupt flag. This flag is set when a new character
- is received while the receiver buffer is still in use. If this
- occurs, the newly received character in the shift register is
- lost. */
- uint32_t : 1;
- __I uint32_t RXBRK : 1; /*!< Received Break. This bit reflects the current state of the receiver
- break detection logic. It is set when the Un_RXD pin remains
- low for 16 bit times. Note that FRAMERRINT will also be set
- when this condition occurs because the stop bit(s) for the character
- would be missing. RXBRK is cleared when the Un_RXD pin goes
- high. */
- __IO uint32_t DELTARXBRK : 1; /*!< This bit is set when a change in the state of receiver break
- detection occurs. Cleared by software. */
- __IO uint32_t START : 1; /*!< This bit is set when a start is detected on the receiver input.
- Its purpose is primarily to allow wake-up from Deep sleep or
- Power-down mode immediately when a start is detected. Cleared
- by software. */
- __IO uint32_t FRAMERRINT : 1; /*!< Framing Error interrupt flag. This flag is set when a character
- is received with a missing stop bit at the expected location.
- This could be an indication of a baud rate or configuration
- mismatch with the transmitting source. */
- __IO uint32_t PARITYERRINT: 1; /*!< Parity Error interrupt flag. This flag is set when a parity
- error is detected in a received character. */
- __IO uint32_t RXNOISEINT : 1; /*!< Received Noise interrupt flag. Three samples of received data
- are taken in order to determine the value of each received data
- bit, except in synchronous mode. This acts as a noise filter
- if one sample disagrees. This flag is set when a received data
- bit contains one disagreeing sample. This could indicate line
- noise, a baud rate or character format mismatch, or loss of
- synchronization during data reception. */
- __IO uint32_t ABERR : 1; /*!< Auto baud Error. An auto baud error can occur if the BRG counts
- to its limit before the end of the start bit that is being measured,
- essentially an auto baud time-out. */
- } STAT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register for USART (not FIFO)
- status. Contains individual interrupt enable bits for each potential
- USART interrupt. A complete value may be read from this register.
- Writing a 1 to any implemented bit position causes that bit
- to be set. */
-
- struct {
- __IO uint32_t RXRDYEN : 1; /*!< When 1, enables an interrupt when RX becomes ready */
- uint32_t : 1;
- __IO uint32_t TXRDTEN : 1; /*!< When 1, enables an interrupt when TX becomes ready */
- __IO uint32_t TXIDLEEN : 1; /*!< When 1, enables an interrupt when the transmitter becomes idle
- (TXIDLE = 1). */
- uint32_t : 1;
- __IO uint32_t DELTACTSEN : 1; /*!< Transmitter Idle. When 0, indicates that the transmitter is
- currently in the process of sending data.When 1, indicate that
- the transmitter is not currently in the process of sending data. */
- __IO uint32_t TXDISEN : 1; /*!< When 1, enables an interrupt when the transmitter is fully disabled
- as indicated by the TXDISINT flag in STAT. See description of
- the TXDISINT bit for details. */
- uint32_t : 1;
- __IO uint32_t OVERRUNEN : 1; /*!< When 1, enables an interrupt when an overrun error occurred. */
- uint32_t : 2;
- __IO uint32_t DELTARXBRKEN: 1; /*!< When 1, enables an interrupt when a change of state has occurred
- in the detection of a received break condition (break condition
- asserted or deasserted). */
- __IO uint32_t STARTEN : 1; /*!< When 1, enables an interrupt when a received start bit has been
- detected. */
- __IO uint32_t FRAMERREN : 1; /*!< When 1, enables an interrupt when a framing error has been detected. */
- __IO uint32_t PARITYERREN: 1; /*!< When 1, enables an interrupt when a parity error has been detected. */
- __IO uint32_t RXNOISEEN : 1; /*!< When 1, enables an interrupt when noise is detected. */
- __IO uint32_t ABERREN : 1; /*!< When 1, enables an interrupt when an auto baud error occurs. */
- } INTENSET_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination
- of bits in the INTENSET register. Writing a 1 to any implemented
- bit position causes the corresponding bit to be cleared. */
-
- struct {
- __O uint32_t RXRDYCLR : 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- uint32_t : 1;
- __O uint32_t TXRDYCLR : 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- __O uint32_t TXIDLECLR : 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- uint32_t : 1;
- __O uint32_t DELTACTSCLR: 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- __O uint32_t TXDISCLR : 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- uint32_t : 1;
- __O uint32_t OVERRUNCLR : 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- uint32_t : 2;
- __O uint32_t DELTARXBRKCLR: 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- __O uint32_t STARTCLR : 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- __O uint32_t FRAMERRCLR : 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- __O uint32_t PARITYERRCLR: 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- __O uint32_t RXNOISECLR : 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- __O uint32_t ABERRCLR : 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- } INTENCLR_b; /*!< BitSize */
- };
- __I uint32_t RESERVED0[3];
-
- union {
- __IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor
- value. */
-
- struct {
- __IO uint32_t BRGVAL : 16; /*!< This value is used to divide the USART input clock to determine
- the baud rate, based on the input clock from the FRG. 0 = FCLK
- is used directly by the USART function. 1 = FCLK is divided
- by 2 before use by the USART function. 2 = FCLK is divided by
- 3 before use by the USART function. ... 0xFFFF = FCLK is divided
- by 65,536 before use by the USART function. */
- } BRG_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently
- enabled. */
-
- struct {
- __I uint32_t RX_RDY : 1; /*!< Receiver Ready Status */
- __I uint32_t RXIDLE : 1; /*!< Receiver Idle Status */
- __I uint32_t TX_RDY : 1; /*!< Transmitter Ready Status */
- __I uint32_t TXIDLE : 1; /*!< Transmitter Idle status. */
- uint32_t : 1;
- __I uint32_t DELTACTS : 1; /*!< This bit is set when a change in the state of the CTS input
- is detected. */
- __I uint32_t TXDIS : 1; /*!< Transmitter Disabled Interrupt flag. */
- uint32_t : 1;
- __I uint32_t OVERRUN : 1; /*!< Overrun Error interrupt flag. */
- uint32_t : 2;
- __I uint32_t DELTARXBRK : 1; /*!< This bit is set when a change in the state of receiver break
- detection occurs. */
- __I uint32_t START : 1; /*!< This bit is set when a start is detected on the receiver input. */
- __I uint32_t FRAMERR : 1; /*!< Framing Error interrupt flag. */
- __I uint32_t PARITYERR : 1; /*!< Parity Error interrupt flag. */
- __I uint32_t RXNOISE : 1; /*!< Received Noise interrupt flag. */
- __I uint32_t ABERR : 1; /*!< Auto baud Error Interrupt flag. */
- } INTSTAT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t OSR; /*!< Oversample selection register for asynchronous communication. */
-
- struct {
- __IO uint32_t OSRVAL : 4; /*!< Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function
- clocks are used to transmit and receive each data bit. 0x5 =
- 6 function clocks are used to transmit and receive each data
- bit. ... 0xF= 16 function clocks are used to transmit and receive
- each data bit. */
- } OSR_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t ADDR; /*!< Address register for automatic address matching. */
-
- struct {
- __IO uint32_t ADDRESS : 8; /*!< 8-bit address used with automatic address matching. Used when
- address detection is enabled (ADDRDET in CTL = 1) and automatic
- address matching is enabled (AUTOADDR in CFG = 1). */
- } ADDR_b; /*!< BitSize */
- };
- __I uint32_t RESERVED1[884];
-
- union {
- __IO uint32_t FIFOCFG; /*!< FIFO configuration and enable register. */
-
- struct {
- __IO uint32_t ENABLETX : 1; /*!< Enable the transmit FIFO. This is automatically enabled when
- PSELID.PERSEL is set to 1 to configure the USART functionality. */
- __IO uint32_t ENABLERX : 1; /*!< Enable the receive FIFO. This is automatically enabled when
- PSELID.PERSEL is set to 1 to configure the USART functionality. */
- uint32_t : 2;
- __I uint32_t SIZE : 2; /*!< FIFO size configuration. This is a read-only field. 0x0 = FIFO
- is configured as 4 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable. */
- uint32_t : 6;
- __IO uint32_t DMATX : 1; /*!< DMA configuration for transmit. */
- __IO uint32_t DMARX : 1; /*!< DMA configuration for receive. */
- __IO uint32_t WAKETX : 1; /*!< Wakeup for transmit FIFO level. This allows the device to be
- woken from reduced power modes (up to power-down, as long as
- the peripheral function works in that power mode) without enabling
- the TXLVL interrupt. Only DMA wakes up, processes data, and
- goes back to sleep. The CPU will remain stopped until woken
- by another cause, such as DMA completion. */
- __IO uint32_t WAKERX : 1; /*!< Wakeup for receive FIFO level. This allows the device to be
- woken from reduced power modes (up to power-down, as long as
- the peripheral function works in that power mode) without enabling
- the TXLVL interrupt. Only DMA wakes up, processes data, and
- goes back to sleep. The CPU will remain stopped until woken
- by another cause, such as DMA completion. */
- __IO uint32_t EMPTYTX : 1; /*!< Empty command for the transmit FIFO. When a 1 is written to
- this bit, the TX FIFO is emptied. */
- __IO uint32_t EMPTYRX : 1; /*!< Empty command for the receive FIFO. When a 1 is written to this
- bit, the RX FIFO is emptied. */
- __IO uint32_t POPDBG : 1; /*!< Pop FIFO for debug reads. */
- } FIFOCFG_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t FIFOSTAT; /*!< FIFO status register. */
-
- struct {
- __I uint32_t TXERR : 1; /*!< TX FIFO error. Will be set if a transmit FIFO error occurs.
- This could be an overflow caused by pushing data into a full
- FIFO, or by an underflow if the FIFO is empty when data is needed.
- Cleared by writing a 1 to this bit. */
- __I uint32_t RXERR : 1; /*!< RX FIFO error. Will be set if a receive FIFO overflow occurs,
- caused by software or DMA not emptying the FIFO fast enough.
- Cleared by writing a 1 to this bit. */
- uint32_t : 1;
- __I uint32_t PERINT : 1; /*!< Peripheral interrupt. When 1, this indicates that the peripheral
- function has asserted an interrupt. The details can be found
- by reading the peripheral s STAT register. */
- __I uint32_t TXEMPTY : 1; /*!< Transmit FIFO empty. When 1, the transmit FIFO is empty. The
- peripheral may still be processing the last piece of data. */
- __I uint32_t TXNOTFULL : 1; /*!< Transmit FIFO not full. When 1, the transmit FIFO is not full,
- so more data can be written. When 0, the transmit FIFO is full
- and another write would cause it to overflow. */
- __I uint32_t RXNOTEMPTY : 1; /*!< Receive FIFO not empty. When 1, the receive FIFO is not empty,
- so data can be read. When 0, the receive FIFO is empty. */
- __I uint32_t RXFULL : 1; /*!< Receive FIFO full. When 1, the receive FIFO is full. Data needs
- to be read out to prevent the peripheral from causing an overflow. */
- __I uint32_t TXLVL : 5; /*!< Transmit FIFO current level. A 0 means the TX FIFO is currently
- empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other
- values tell how much data is actually in the TX FIFO at the
- point where the read occurs. If the TX FIFO is full, the TXEMPTY
- and TXNOTFULL flags will be 0. */
- uint32_t : 3;
- __I uint32_t RXLVL : 5; /*!< Receive FIFO current level. A 0 means the RX FIFO is currently
- empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other
- values tell how much data is actually in the RX FIFO at the
- point where the read occurs. If the RX FIFO is full, the RXFULL
- and RXNOTEMPTY flags will be 1. */
- } FIFOSTAT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t FIFOTRIG; /*!< FIFO trigger settings for interrupt and DMA request. */
-
- struct {
- __IO uint32_t TXLVLENA : 1; /*!< Transmit FIFO level trigger enable. This trigger will become
- an interrupt if enabled in FIFOINTENSET, or a DMA trigger if
- DMATX in FIFOCFG is set. */
- __IO uint32_t RXLVLENA : 1; /*!< Receive FIFO level trigger enable. This trigger will become
- an interrupt if enabled in FIFOINTENSET, or a DMA trigger if
- DMARX in FIFOCFG is set. */
- uint32_t : 6;
- __IO uint32_t TXLVL : 4; /*!< Transmit FIFO level trigger point. This field is used only when
- TXLVLENA = 1. 0 = trigger when the TX FIFO becomes empty. 1
- = trigger when the TX FIFO level decreases to one entry. ...
- 3 = trigger when the TX FIFO level decreases to 3 entries (is
- no longer full). */
- uint32_t : 4;
- __IO uint32_t RXLVL : 4; /*!< Receive FIFO level trigger point. The RX FIFO level is checked
- when a new piece of data is received. This field is used only
- when RXLVLENA = 1. 0 = trigger when the RX FIFO has received
- one entry (is no longer empty). 1 = trigger when the RX FIFO
- has received two entries. ... 3 = trigger when the RX FIFO has
- received 3 entries (has become full). */
- } FIFOTRIG_b; /*!< BitSize */
- };
- __I uint32_t RESERVED2;
-
- union {
- __IO uint32_t FIFOINTENSET; /*!< FIFO interrupt enable set (enable) and read register. */
-
- struct {
- __IO uint32_t TXERR : 1; /*!< Determines whether an interrupt occurs when a transmit error
- occurs, based on the TXERR flag in the FIFOSTAT register. */
- __IO uint32_t RXERR : 1; /*!< Determines whether an interrupt occurs when a receive error
- occurs, based on the RXERR flag in the FIFOSTAT register. */
- __IO uint32_t TXLVL : 1; /*!< Determines whether an interrupt occurs when a the transmit FIFO
- reaches the level specified by the TXLVL field in the FIFOTRIG
- register. */
- __IO uint32_t RXLVL : 1; /*!< Determines whether an interrupt occurs when a the receive FIFO
- reaches the level specified by the TXLVL field in the FIFOTRIG
- register. */
- } FIFOINTENSET_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t FIFOINTENCLR; /*!< FIFO interrupt enable clear (disable) and read register. */
-
- struct {
- __IO uint32_t TXERR : 1; /*!< Writing 1 clears the corresponding bit in the FIFOINTENSET register */
- __IO uint32_t RXERR : 1; /*!< Writing 1 clears the corresponding bit in the FIFOINTENSET register */
- __IO uint32_t TXLVL : 1; /*!< Writing 1 clears the corresponding bit in the FIFOINTENSET register */
- __IO uint32_t RXLVL : 1; /*!< Writing 1 clears the corresponding bit in the FIFOINTENSET register */
- } FIFOINTENCLR_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t FIFOINTSTAT; /*!< FIFO interrupt status register. */
-
- struct {
- __I uint32_t TXERR : 1; /*!< TX FIFO error. */
- __I uint32_t RXERR : 1; /*!< RX FIFO error. */
- __I uint32_t TXLVL : 1; /*!< Transmit FIFO level interrupt. */
- __I uint32_t RXLVL : 1; /*!< Receive FIFO level interrupt. */
- __I uint32_t PERINT : 1; /*!< Peripheral interrupt. */
- } FIFOINTSTAT_b; /*!< BitSize */
- };
- __I uint32_t RESERVED3;
-
- union {
- __O uint32_t FIFOWR; /*!< FIFO write data. */
-
- struct {
- __O uint32_t TXDATA : 8; /*!< Transmit data to the FIFO. */
- } FIFOWR_b; /*!< BitSize */
- };
- __I uint32_t RESERVED4[3];
-
- union {
- __I uint32_t FIFORD; /*!< FIFO read data. */
-
- struct {
- __I uint32_t RXDATA : 9; /*!< Received data from the FIFO. The number of bits used depends
- on the DATALEN and PARITYSEL settings. */
- uint32_t : 4;
- __I uint32_t FRAMERR : 1; /*!< Framing Error status flag. This bit reflects the status for
- the data it is read along with from the FIFO, and indicates
- that the character was received with a missing stop bit at the
- expected location. This could be an indication of a baud rate
- or configuration mismatch with the transmitting source. */
- __I uint32_t PARITYERR : 1; /*!< Parity Error status flag. This bit reflects the status for the
- data it is read along with from the FIFO. This bit will be set
- when a parity error is detected in a received character. */
- __I uint32_t RXNOISE : 1; /*!< Received Noise flag. */
- } FIFORD_b; /*!< BitSize */
- };
- __I uint32_t RESERVED5[3];
-
- union {
- __I uint32_t FIFORDNOPOP; /*!< FIFO data read with no FIFO pop. */
-
- struct {
- __I uint32_t RXDATA : 9; /*!< Received data from the FIFO. The number of bits used depends
- on the DATALEN and PARITYSEL settings. */
- uint32_t : 4;
- __I uint32_t FRAMERR : 1; /*!< Framing Error status flag. This bit reflects the status for
- the data it is read along with from the FIFO, and indicates
- that the character was received with a missing stop bit at the
- expected location. This could be an indication of a baud rate
- or configuration mismatch with the transmitting source. */
- __I uint32_t PARITYERR : 1; /*!< Parity Error status flag. This bit reflects the status for the
- data it is read along with from the FIFO. This bit will be set
- when a parity error is detected in a received character. */
- __I uint32_t RXNOISE : 1; /*!< Received Noise flag. */
- } FIFORDNOPOP_b; /*!< BitSize */
- };
- __I uint32_t RESERVED6[109];
-
- union {
- __IO uint32_t PSELID; /*!< Flexcomm ID and peripheral function select register */
-
- struct {
- __IO uint32_t PERSEL : 3; /*!< Peripheral Select. This field is writable by software. 0x0 No
- peripheral selected. 0x1 USART function selected 0x2 Reserved.
- 0x3 Reserved. 0x4 Reserved. 0x5 Reserved. 0x6 Reserved 0x7 Reserved */
- __IO uint32_t LOCK : 1; /*!< Lock the peripheral select. This field is writable by software.
- 0 Peripheral select can be changed by software. 1 Peripheral
- select is locked and cannot be changed until this Flexcomm or
- the entire device is reset. */
- __I uint32_t USARTPRESENT: 1; /*!< USART present indicator. This field is Read-only. 0 This Flexcomm
- does not include the USART function. 1 This Flexcomm includes
- the USART function. */
- uint32_t : 7;
- __I uint32_t ID : 20; /*!< Flexcomm ID. */
- } PSELID_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t ID; /*!< USART Module Identifier */
-
- struct {
- __I uint32_t APERTURE : 8; /*!< Aperture i.e. number minus 1 of consecutive packets 4 Kbytes
- reserved for this IP */
- __I uint32_t MIN_REV : 4; /*!< Minor revision i.e. with no software consequences */
- __I uint32_t MAJ_REV : 4; /*!< Major revision i.e. implies software modifications */
- __I uint32_t ID : 16; /*!< Identifier. This is the unique identifier of the module */
- } ID_b; /*!< BitSize */
- };
-} u0_usart_Type;
-
-
-/* ================================================================================ */
-/* ================ u1_usart ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component usart. It is an Universal Synchrnous/Asynchrnous Receiver/Transmitter with APB bus interface. More details will follow. (u1_usart)
- */
-
-typedef struct { /*!< u1_usart Structure */
-
- union {
- __IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings
- that typically are not changed during operation. */
-
- struct {
- __IO uint32_t ENABLE : 1; /*!< USART Enable. */
- uint32_t : 1;
- __IO uint32_t DATALEN : 2; /*!< Selects the data size for the USART. */
- __IO uint32_t PARITYSEL : 2; /*!< Selects what type of parity is used by the USART. */
- __IO uint32_t STOPLEN : 1; /*!< Number of stop bits appended to transmitted data. Only a single
- stop bit is required for received data. */
- __IO uint32_t MODE32K : 1; /*!< Selects standard or 32 kHz clocking mode. */
- __IO uint32_t LINMODE : 1; /*!< LIN bus break mode enable. */
- __IO uint32_t CTSEN : 1; /*!< CTS Enable. Determines whether CTS is used for flow control.
- CTS can be from the input pin, or from the USART s own RTS if
- loopback mode is enabled. */
- uint32_t : 1;
- __IO uint32_t SYNCEN : 1; /*!< Selects synchronous or asynchronous operation. */
- __IO uint32_t CLKPOL : 1; /*!< Selects the clock polarity and sampling edge of received data
- in synchronous mode. */
- uint32_t : 1;
- __IO uint32_t SYNCMST : 1; /*!< Synchronous mode Master select. */
- __IO uint32_t LOOP : 1; /*!< Selects data loopback mode. */
- __IO uint32_t IOMODE : 1; /*!< I/O output mode. */
- uint32_t : 1;
- __IO uint32_t OETA : 1; /*!< Output Enable Turnaround time enable for RS-485 operation. */
- __IO uint32_t AUTOADDR : 1; /*!< Automatic Address matching enable. */
- __IO uint32_t OESEL : 1; /*!< Output Enable Select. */
- __IO uint32_t OEPOL : 1; /*!< Output Enable Polarity. */
- __IO uint32_t RXPOL : 1; /*!< Receive data polarity. */
- __IO uint32_t TXPOL : 1; /*!< Transmit data polarity. */
- } CFG_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t CTL; /*!< USART Control register. USART control settings that are more
- likely to change during operation. */
-
- struct {
- uint32_t : 1;
- __IO uint32_t TXBRKEN : 1; /*!< Break Enable. */
- __IO uint32_t ADDRDET : 1; /*!< Enable address detect mode. */
- uint32_t : 3;
- __IO uint32_t TXDIS : 1; /*!< Transmit Disable. */
- uint32_t : 1;
- __IO uint32_t CC : 1; /*!< Continuous Clock generation. By default, SCLK is only output
- while data is being transmitted in synchronous mode. */
- __IO uint32_t CLRCCONRX : 1; /*!< Clear Continuous Clock. */
- uint32_t : 6;
- __IO uint32_t AUTOBAUD : 1; /*!< Autobaud enable. */
- } CTL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t STAT; /*!< USART Status register. The complete status value can be read
- here. Writing ones clears some bits in the register. Some bits
- can be cleared by writing a 1 to them. */
-
- struct {
- uint32_t : 1;
- __I uint32_t RXIDLE : 1; /*!< Receiver Idle. When 0, indicates that the receiver is currently
- in the process of receiving data. When 1, indicates that the
- receiver is not currently in the process of receiving data. */
- uint32_t : 1;
- __I uint32_t TXIDLE : 1; /*!< Transmitter Idle. When 0, indicates that the transmitter is
- currently in the process of sending data.When 1, indicate that
- the transmitter is not currently in the process of sending data. */
- __I uint32_t CTS : 1; /*!< This bit reflects the current state of the CTS signal, regardless
- of the setting of the CTSEN bit in the CFG register. This will
- be the value of the CTS input pin unless loopback mode is enabled. */
- __IO uint32_t DELTACTS : 1; /*!< This bit is set when a change in the state is detected for the
- CTS flag above. This bit is cleared by software. */
- __I uint32_t TXDISSTAT : 1; /*!< Transmitter Disabled Status flag. When 1, this bit indicates
- that the USART transmitter is fully idle after being disabled
- via the TXDIS bit in the CFG register (TXDIS = 1). */
- uint32_t : 1;
- __IO uint32_t OVERRUNINT : 1; /*!< Overrun Error interrupt flag. This flag is set when a new character
- is received while the receiver buffer is still in use. If this
- occurs, the newly received character in the shift register is
- lost. */
- uint32_t : 1;
- __I uint32_t RXBRK : 1; /*!< Received Break. This bit reflects the current state of the receiver
- break detection logic. It is set when the Un_RXD pin remains
- low for 16 bit times. Note that FRAMERRINT will also be set
- when this condition occurs because the stop bit(s) for the character
- would be missing. RXBRK is cleared when the Un_RXD pin goes
- high. */
- __IO uint32_t DELTARXBRK : 1; /*!< This bit is set when a change in the state of receiver break
- detection occurs. Cleared by software. */
- __IO uint32_t START : 1; /*!< This bit is set when a start is detected on the receiver input.
- Its purpose is primarily to allow wake-up from Deep sleep or
- Power-down mode immediately when a start is detected. Cleared
- by software. */
- __IO uint32_t FRAMERRINT : 1; /*!< Framing Error interrupt flag. This flag is set when a character
- is received with a missing stop bit at the expected location.
- This could be an indication of a baud rate or configuration
- mismatch with the transmitting source. */
- __IO uint32_t PARITYERRINT: 1; /*!< Parity Error interrupt flag. This flag is set when a parity
- error is detected in a received character. */
- __IO uint32_t RXNOISEINT : 1; /*!< Received Noise interrupt flag. Three samples of received data
- are taken in order to determine the value of each received data
- bit, except in synchronous mode. This acts as a noise filter
- if one sample disagrees. This flag is set when a received data
- bit contains one disagreeing sample. This could indicate line
- noise, a baud rate or character format mismatch, or loss of
- synchronization during data reception. */
- __IO uint32_t ABERR : 1; /*!< Auto baud Error. An auto baud error can occur if the BRG counts
- to its limit before the end of the start bit that is being measured,
- essentially an auto baud time-out. */
- } STAT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register for USART (not FIFO)
- status. Contains individual interrupt enable bits for each potential
- USART interrupt. A complete value may be read from this register.
- Writing a 1 to any implemented bit position causes that bit
- to be set. */
-
- struct {
- __IO uint32_t RXRDYEN : 1; /*!< When 1, enables an interrupt when RX becomes ready */
- uint32_t : 1;
- __IO uint32_t TXRDTEN : 1; /*!< When 1, enables an interrupt when TX becomes ready */
- __IO uint32_t TXIDLEEN : 1; /*!< When 1, enables an interrupt when the transmitter becomes idle
- (TXIDLE = 1). */
- uint32_t : 1;
- __IO uint32_t DELTACTSEN : 1; /*!< Transmitter Idle. When 0, indicates that the transmitter is
- currently in the process of sending data.When 1, indicate that
- the transmitter is not currently in the process of sending data. */
- __IO uint32_t TXDISEN : 1; /*!< When 1, enables an interrupt when the transmitter is fully disabled
- as indicated by the TXDISINT flag in STAT. See description of
- the TXDISINT bit for details. */
- uint32_t : 1;
- __IO uint32_t OVERRUNEN : 1; /*!< When 1, enables an interrupt when an overrun error occurred. */
- uint32_t : 2;
- __IO uint32_t DELTARXBRKEN: 1; /*!< When 1, enables an interrupt when a change of state has occurred
- in the detection of a received break condition (break condition
- asserted or deasserted). */
- __IO uint32_t STARTEN : 1; /*!< When 1, enables an interrupt when a received start bit has been
- detected. */
- __IO uint32_t FRAMERREN : 1; /*!< When 1, enables an interrupt when a framing error has been detected. */
- __IO uint32_t PARITYERREN: 1; /*!< When 1, enables an interrupt when a parity error has been detected. */
- __IO uint32_t RXNOISEEN : 1; /*!< When 1, enables an interrupt when noise is detected. */
- __IO uint32_t ABERREN : 1; /*!< When 1, enables an interrupt when an auto baud error occurs. */
- } INTENSET_b; /*!< BitSize */
- };
-
- union {
- __O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination
- of bits in the INTENSET register. Writing a 1 to any implemented
- bit position causes the corresponding bit to be cleared. */
-
- struct {
- __O uint32_t RXRDYCLR : 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- uint32_t : 1;
- __O uint32_t TXRDYCLR : 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- __O uint32_t TXIDLECLR : 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- uint32_t : 1;
- __O uint32_t DELTACTSCLR: 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- __O uint32_t TXDISCLR : 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- uint32_t : 1;
- __O uint32_t OVERRUNCLR : 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- uint32_t : 2;
- __O uint32_t DELTARXBRKCLR: 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- __O uint32_t STARTCLR : 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- __O uint32_t FRAMERRCLR : 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- __O uint32_t PARITYERRCLR: 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- __O uint32_t RXNOISECLR : 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- __O uint32_t ABERRCLR : 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- } INTENCLR_b; /*!< BitSize */
- };
- __I uint32_t RESERVED0[3];
-
- union {
- __IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor
- value. */
-
- struct {
- __IO uint32_t BRGVAL : 16; /*!< This value is used to divide the USART input clock to determine
- the baud rate, based on the input clock from the FRG. 0 = FCLK
- is used directly by the USART function. 1 = FCLK is divided
- by 2 before use by the USART function. 2 = FCLK is divided by
- 3 before use by the USART function. ... 0xFFFF = FCLK is divided
- by 65,536 before use by the USART function. */
- } BRG_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently
- enabled. */
-
- struct {
- __I uint32_t RX_RDY : 1; /*!< Receiver Ready Status */
- __I uint32_t RXIDLE : 1; /*!< Receiver Idle Status */
- __I uint32_t TX_RDY : 1; /*!< Transmitter Ready Status */
- __I uint32_t TXIDLE : 1; /*!< Transmitter Idle status. */
- uint32_t : 1;
- __I uint32_t DELTACTS : 1; /*!< This bit is set when a change in the state of the CTS input
- is detected. */
- __I uint32_t TXDIS : 1; /*!< Transmitter Disabled Interrupt flag. */
- uint32_t : 1;
- __I uint32_t OVERRUN : 1; /*!< Overrun Error interrupt flag. */
- uint32_t : 2;
- __I uint32_t DELTARXBRK : 1; /*!< This bit is set when a change in the state of receiver break
- detection occurs. */
- __I uint32_t START : 1; /*!< This bit is set when a start is detected on the receiver input. */
- __I uint32_t FRAMERR : 1; /*!< Framing Error interrupt flag. */
- __I uint32_t PARITYERR : 1; /*!< Parity Error interrupt flag. */
- __I uint32_t RXNOISE : 1; /*!< Received Noise interrupt flag. */
- __I uint32_t ABERR : 1; /*!< Auto baud Error Interrupt flag. */
- } INTSTAT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t OSR; /*!< Oversample selection register for asynchronous communication. */
-
- struct {
- __IO uint32_t OSRVAL : 4; /*!< Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function
- clocks are used to transmit and receive each data bit. 0x5 =
- 6 function clocks are used to transmit and receive each data
- bit. ... 0xF= 16 function clocks are used to transmit and receive
- each data bit. */
- } OSR_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t ADDR; /*!< Address register for automatic address matching. */
-
- struct {
- __IO uint32_t ADDRESS : 8; /*!< 8-bit address used with automatic address matching. Used when
- address detection is enabled (ADDRDET in CTL = 1) and automatic
- address matching is enabled (AUTOADDR in CFG = 1). */
- } ADDR_b; /*!< BitSize */
- };
- __I uint32_t RESERVED1[884];
-
- union {
- __IO uint32_t FIFOCFG; /*!< FIFO configuration and enable register. */
-
- struct {
- __IO uint32_t ENABLETX : 1; /*!< Enable the transmit FIFO. This is automatically enabled when
- PSELID.PERSEL is set to 1 to configure the USART functionality. */
- __IO uint32_t ENABLERX : 1; /*!< Enable the receive FIFO. This is automatically enabled when
- PSELID.PERSEL is set to 1 to configure the USART functionality. */
- uint32_t : 2;
- __I uint32_t SIZE : 2; /*!< FIFO size configuration. This is a read-only field. 0x0 = FIFO
- is configured as 4 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable. */
- uint32_t : 6;
- __IO uint32_t DMATX : 1; /*!< DMA configuration for transmit. */
- __IO uint32_t DMARX : 1; /*!< DMA configuration for receive. */
- __IO uint32_t WAKETX : 1; /*!< Wakeup for transmit FIFO level. This allows the device to be
- woken from reduced power modes (up to power-down, as long as
- the peripheral function works in that power mode) without enabling
- the TXLVL interrupt. Only DMA wakes up, processes data, and
- goes back to sleep. The CPU will remain stopped until woken
- by another cause, such as DMA completion. */
- __IO uint32_t WAKERX : 1; /*!< Wakeup for receive FIFO level. This allows the device to be
- woken from reduced power modes (up to power-down, as long as
- the peripheral function works in that power mode) without enabling
- the TXLVL interrupt. Only DMA wakes up, processes data, and
- goes back to sleep. The CPU will remain stopped until woken
- by another cause, such as DMA completion. */
- __IO uint32_t EMPTYTX : 1; /*!< Empty command for the transmit FIFO. When a 1 is written to
- this bit, the TX FIFO is emptied. */
- __IO uint32_t EMPTYRX : 1; /*!< Empty command for the receive FIFO. When a 1 is written to this
- bit, the RX FIFO is emptied. */
- __IO uint32_t POPDBG : 1; /*!< Pop FIFO for debug reads. */
- } FIFOCFG_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t FIFOSTAT; /*!< FIFO status register. */
-
- struct {
- __I uint32_t TXERR : 1; /*!< TX FIFO error. Will be set if a transmit FIFO error occurs.
- This could be an overflow caused by pushing data into a full
- FIFO, or by an underflow if the FIFO is empty when data is needed.
- Cleared by writing a 1 to this bit. */
- __I uint32_t RXERR : 1; /*!< RX FIFO error. Will be set if a receive FIFO overflow occurs,
- caused by software or DMA not emptying the FIFO fast enough.
- Cleared by writing a 1 to this bit. */
- uint32_t : 1;
- __I uint32_t PERINT : 1; /*!< Peripheral interrupt. When 1, this indicates that the peripheral
- function has asserted an interrupt. The details can be found
- by reading the peripheral s STAT register. */
- __I uint32_t TXEMPTY : 1; /*!< Transmit FIFO empty. When 1, the transmit FIFO is empty. The
- peripheral may still be processing the last piece of data. */
- __I uint32_t TXNOTFULL : 1; /*!< Transmit FIFO not full. When 1, the transmit FIFO is not full,
- so more data can be written. When 0, the transmit FIFO is full
- and another write would cause it to overflow. */
- __I uint32_t RXNOTEMPTY : 1; /*!< Receive FIFO not empty. When 1, the receive FIFO is not empty,
- so data can be read. When 0, the receive FIFO is empty. */
- __I uint32_t RXFULL : 1; /*!< Receive FIFO full. When 1, the receive FIFO is full. Data needs
- to be read out to prevent the peripheral from causing an overflow. */
- __I uint32_t TXLVL : 5; /*!< Transmit FIFO current level. A 0 means the TX FIFO is currently
- empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other
- values tell how much data is actually in the TX FIFO at the
- point where the read occurs. If the TX FIFO is full, the TXEMPTY
- and TXNOTFULL flags will be 0. */
- uint32_t : 3;
- __I uint32_t RXLVL : 5; /*!< Receive FIFO current level. A 0 means the RX FIFO is currently
- empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other
- values tell how much data is actually in the RX FIFO at the
- point where the read occurs. If the RX FIFO is full, the RXFULL
- and RXNOTEMPTY flags will be 1. */
- } FIFOSTAT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t FIFOTRIG; /*!< FIFO trigger settings for interrupt and DMA request. */
-
- struct {
- __IO uint32_t TXLVLENA : 1; /*!< Transmit FIFO level trigger enable. This trigger will become
- an interrupt if enabled in FIFOINTENSET, or a DMA trigger if
- DMATX in FIFOCFG is set. */
- __IO uint32_t RXLVLENA : 1; /*!< Receive FIFO level trigger enable. This trigger will become
- an interrupt if enabled in FIFOINTENSET, or a DMA trigger if
- DMARX in FIFOCFG is set. */
- uint32_t : 6;
- __IO uint32_t TXLVL : 4; /*!< Transmit FIFO level trigger point. This field is used only when
- TXLVLENA = 1. 0 = trigger when the TX FIFO becomes empty. 1
- = trigger when the TX FIFO level decreases to one entry. ...
- 3 = trigger when the TX FIFO level decreases to 3 entries (is
- no longer full). */
- uint32_t : 4;
- __IO uint32_t RXLVL : 4; /*!< Receive FIFO level trigger point. The RX FIFO level is checked
- when a new piece of data is received. This field is used only
- when RXLVLENA = 1. 0 = trigger when the RX FIFO has received
- one entry (is no longer empty). 1 = trigger when the RX FIFO
- has received two entries. ... 3 = trigger when the RX FIFO has
- received 3 entries (has become full). */
- } FIFOTRIG_b; /*!< BitSize */
- };
- __I uint32_t RESERVED2;
-
- union {
- __IO uint32_t FIFOINTENSET; /*!< FIFO interrupt enable set (enable) and read register. */
-
- struct {
- __IO uint32_t TXERR : 1; /*!< Determines whether an interrupt occurs when a transmit error
- occurs, based on the TXERR flag in the FIFOSTAT register. */
- __IO uint32_t RXERR : 1; /*!< Determines whether an interrupt occurs when a receive error
- occurs, based on the RXERR flag in the FIFOSTAT register. */
- __IO uint32_t TXLVL : 1; /*!< Determines whether an interrupt occurs when a the transmit FIFO
- reaches the level specified by the TXLVL field in the FIFOTRIG
- register. */
- __IO uint32_t RXLVL : 1; /*!< Determines whether an interrupt occurs when a the receive FIFO
- reaches the level specified by the TXLVL field in the FIFOTRIG
- register. */
- } FIFOINTENSET_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t FIFOINTENCLR; /*!< FIFO interrupt enable clear (disable) and read register. */
-
- struct {
- __IO uint32_t TXERR : 1; /*!< Writing 1 clears the corresponding bit in the FIFOINTENSET register */
- __IO uint32_t RXERR : 1; /*!< Writing 1 clears the corresponding bit in the FIFOINTENSET register */
- __IO uint32_t TXLVL : 1; /*!< Writing 1 clears the corresponding bit in the FIFOINTENSET register */
- __IO uint32_t RXLVL : 1; /*!< Writing 1 clears the corresponding bit in the FIFOINTENSET register */
- } FIFOINTENCLR_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t FIFOINTSTAT; /*!< FIFO interrupt status register. */
-
- struct {
- __I uint32_t TXERR : 1; /*!< TX FIFO error. */
- __I uint32_t RXERR : 1; /*!< RX FIFO error. */
- __I uint32_t TXLVL : 1; /*!< Transmit FIFO level interrupt. */
- __I uint32_t RXLVL : 1; /*!< Receive FIFO level interrupt. */
- __I uint32_t PERINT : 1; /*!< Peripheral interrupt. */
- } FIFOINTSTAT_b; /*!< BitSize */
- };
- __I uint32_t RESERVED3;
-
- union {
- __O uint32_t FIFOWR; /*!< FIFO write data. */
-
- struct {
- __O uint32_t TXDATA : 8; /*!< Transmit data to the FIFO. */
- } FIFOWR_b; /*!< BitSize */
- };
- __I uint32_t RESERVED4[3];
-
- union {
- __I uint32_t FIFORD; /*!< FIFO read data. */
-
- struct {
- __I uint32_t RXDATA : 9; /*!< Received data from the FIFO. The number of bits used depends
- on the DATALEN and PARITYSEL settings. */
- uint32_t : 4;
- __I uint32_t FRAMERR : 1; /*!< Framing Error status flag. This bit reflects the status for
- the data it is read along with from the FIFO, and indicates
- that the character was received with a missing stop bit at the
- expected location. This could be an indication of a baud rate
- or configuration mismatch with the transmitting source. */
- __I uint32_t PARITYERR : 1; /*!< Parity Error status flag. This bit reflects the status for the
- data it is read along with from the FIFO. This bit will be set
- when a parity error is detected in a received character. */
- __I uint32_t RXNOISE : 1; /*!< Received Noise flag. */
- } FIFORD_b; /*!< BitSize */
- };
- __I uint32_t RESERVED5[3];
-
- union {
- __I uint32_t FIFORDNOPOP; /*!< FIFO data read with no FIFO pop. */
-
- struct {
- __I uint32_t RXDATA : 9; /*!< Received data from the FIFO. The number of bits used depends
- on the DATALEN and PARITYSEL settings. */
- uint32_t : 4;
- __I uint32_t FRAMERR : 1; /*!< Framing Error status flag. This bit reflects the status for
- the data it is read along with from the FIFO, and indicates
- that the character was received with a missing stop bit at the
- expected location. This could be an indication of a baud rate
- or configuration mismatch with the transmitting source. */
- __I uint32_t PARITYERR : 1; /*!< Parity Error status flag. This bit reflects the status for the
- data it is read along with from the FIFO. This bit will be set
- when a parity error is detected in a received character. */
- __I uint32_t RXNOISE : 1; /*!< Received Noise flag. */
- } FIFORDNOPOP_b; /*!< BitSize */
- };
- __I uint32_t RESERVED6[109];
-
- union {
- __IO uint32_t PSELID; /*!< Flexcomm ID and peripheral function select register */
-
- struct {
- __IO uint32_t PERSEL : 3; /*!< Peripheral Select. This field is writable by software. 0x0 No
- peripheral selected. 0x1 USART function selected 0x2 Reserved.
- 0x3 Reserved. 0x4 Reserved. 0x5 Reserved. 0x6 Reserved 0x7 Reserved */
- __IO uint32_t LOCK : 1; /*!< Lock the peripheral select. This field is writable by software.
- 0 Peripheral select can be changed by software. 1 Peripheral
- select is locked and cannot be changed until this Flexcomm or
- the entire device is reset. */
- __I uint32_t USARTPRESENT: 1; /*!< USART present indicator. This field is Read-only. 0 This Flexcomm
- does not include the USART function. 1 This Flexcomm includes
- the USART function. */
- uint32_t : 7;
- __I uint32_t ID : 20; /*!< Flexcomm ID. */
- } PSELID_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t ID; /*!< USART Module Identifier */
-
- struct {
- __I uint32_t APERTURE : 8; /*!< Aperture i.e. number minus 1 of consecutive packets 4 Kbytes
- reserved for this IP */
- __I uint32_t MIN_REV : 4; /*!< Minor revision i.e. with no software consequences */
- __I uint32_t MAJ_REV : 4; /*!< Major revision i.e. implies software modifications */
- __I uint32_t ID : 16; /*!< Identifier. This is the unique identifier of the module */
- } ID_b; /*!< BitSize */
- };
-} u1_usart_Type;
-
-
-/* ================================================================================ */
-/* ================ u0_spi ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component spi. It is a Serial Peripheral Interface with APB bus interface. More details will follow. (u0_spi)
- */
-
-typedef struct { /*!< u0_spi Structure */
- __I uint32_t RESERVED0[256];
-
- union {
- __IO uint32_t CFG; /*!< SPI Configuration register */
-
- struct {
- __IO uint32_t ENABLE : 1; /*!< SPI enable. */
- uint32_t : 1;
- __IO uint32_t MASTER : 1; /*!< Master mode select. */
- __IO uint32_t LSBF : 1; /*!< LSB First mode enable. */
- __IO uint32_t CPHA : 1; /*!< Clock Phase select. */
- __IO uint32_t CPOL : 1; /*!< Clock Polarity select. */
- uint32_t : 1;
- __IO uint32_t LOOP : 1; /*!< Loopback mode enable. Loopback mode applies only to Master mode,
- and connects transmit and receive data connected together to
- allow simple software testing. */
- __IO uint32_t SPOL0 : 1; /*!< SSEL0 Polarity select. */
- __IO uint32_t SPOL1 : 1; /*!< SSEL1 Polarity select. Valid only for SPI-1 */
- __IO uint32_t SPOL2 : 1; /*!< SSEL2 Polarity select. Valid only for SPI-1 */
- __IO uint32_t SPOL3 : 1; /*!< [Reserved] SSEL3 Polarity select. */
- } CFG_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t DLY; /*!< SPI Delay register */
-
- struct {
- __IO uint32_t PRE_DELAY : 4; /*!< Controls the amount of time between SSEL assertion and the beginning
- of a data transfer. There is always one SPI clock time between
- SSEL assertion and the first clock edge. This is not considered
- part of the pre-delay. 0x0 = No additional time is inserted.
- 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times
- are inserted. ... 0xF = 15 SPI clock times are inserted. */
- __IO uint32_t POST_DELAY : 4; /*!< Controls the amount of time between the end of a data transfer
- and SSEL deassertion. 0x0 = No additional time is inserted.
- 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times
- are inserted. ... 0xF = 15 SPI clock times are inserted. */
- __IO uint32_t FRAME_DELAY: 4; /*!< If the EOFR flag is set, controls the minimum amount of time
- between the current frame and the next frame (or SSEL deassertion
- if EOTR). 0x0 = No additional time is inserted. 0x1 = 1 SPI
- clock time is inserted. 0x2 = 2 SPI clock times are inserted.
- ... 0xF = 15 SPI clock times are inserted. */
- __IO uint32_t TRANSFER_DELAY: 4; /*!< Controls the minimum amount of time that the SSEL is deasserted
- between transfers. 0x0 = The minimum time that SSEL is deasserted
- is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time
- that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum
- time that SSEL is deasserted is 3 SPI clock times. ... 0xF =
- The minimum time that SSEL is deasserted is 16 SPI clock times. */
- } DLY_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t STAT; /*!< SPI Status. Some status flags can be cleared by writing a 1
- to that bit position. */
-
- struct {
- uint32_t : 2;
- __IO uint32_t RXOV : 1; /*!< Receiver Overrun interrupt flag. This flag applies only to slave
- mode (Master = 0). This flag is set when the beginning of a
- received character is detected while the receiver buffer is
- still in use. If this occurs, the receiver buffer contents are
- preserved, and the incoming data is lost. Data received by the
- SPI should be considered undefined if RxOv is set. */
- __IO uint32_t TXUR : 1; /*!< Transmitter Underrun interrupt flag. This flag applies only
- to slave mode (Master = 0). In this case, the transmitter must
- begin sending new data on the next input clock if the transmitter
- is idle. If that data is not available in the transmitter holding
- register at that point, there is no data to transmit and the
- TXUR flag is set. Data transmitted by the SPI should be considered
- undefined if TXUR is set. */
- __IO uint32_t SSA : 1; /*!< Slave Select Assert. This flag is set whenever any slave select
- transitions from deasserted to asserted, in both master and
- slave modes. This allows determining when the SPI transmit/receive
- functions become busy, and allows waking up the device from
- reduced power modes when a slave mode access begins. This flag
- is cleared by software. */
- __IO uint32_t SSD : 1; /*!< Slave Select Deassert. This flag is set whenever any asserted
- slave selects transition to deasserted, in both master and slave
- modes. This allows determining when the SPI transmit/receive
- functions become idle. This flag is cleared by software. */
- __I uint32_t STALLED : 1; /*!< Stalled status flag. This indicates whether the SPI is currently
- in a stall condition. */
- __IO uint32_t ENDTRANSFER: 1; /*!< End Transfer control bit. Software can set this bit to force
- an end to the current transfer when the transmitter finishes
- any activity already in progress, as if the EOTR flag had been
- set prior to the last transmission. This capability is included
- to support cases where it is not known when transmit data is
- written that it will be the end of a transfer. The bit is cleared
- when the transmitter becomes idle as the transfer comes to an
- end. Forcing an end of transfer in this manner causes any specified
- FRAME */
- __I uint32_t MSTIDLE : 1; /*!< Master idle status flag. This bit is 1 whenever the SPI master
- function is fully idle. This means that the transmit holding
- register is empty and the transmitter is not in the process
- of sending data. */
- } STAT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t INTENSET; /*!< SPI Interrupt Enable read and Set. A complete value may be read
- from this register. Writing a 1 to any implemented bit position
- causes that bit to be set. */
-
- struct {
- uint32_t : 2;
- __IO uint32_t RXOVEN : 1; /*!< RX overrun interrupt enable. Determines whether an interrupt
- occurs when a receiver overrun occurs. This happens in slave
- mode when there is a need for the receiver to move newly received
- data to the RXDAT register when it is already in use. The interface
- prevents receiver overrun in Master mode by not allowing a new
- transmission to begin when a receiver overrun would otherwise
- occur. */
- __IO uint32_t TXUREN : 1; /*!< TX underrun interrupt enable. Determines whether an interrupt
- occurs when a transmitter underrun occurs. This happens in slave
- mode when there is a need to transmit data when none is available. */
- __IO uint32_t SSAEN : 1; /*!< Slave select assert interrupt enable. Determines whether an
- interrupt occurs when the Slave Select is asserted. */
- __IO uint32_t SSDEN : 1; /*!< Slave select deassert interrupt enable. Determines whether an
- interrupt occurs when the Slave Select is deasserted. */
- uint32_t : 2;
- __IO uint32_t MSTIDLEEN : 1; /*!< Master idle interrupt enable. */
- } INTENSET_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t INTENCLR; /*!< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit
- position causes the corresponding bit in INTENSET to be cleared. */
-
- struct {
- uint32_t : 2;
- __IO uint32_t RXOVCLR : 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- __IO uint32_t TXURCLR : 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- __IO uint32_t SSACLR : 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- __IO uint32_t SSDCLR : 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- uint32_t : 2;
- __IO uint32_t MSTIDLECLR : 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- } INTENCLR_b; /*!< BitSize */
- };
- __I uint32_t RESERVED1[3];
-
- union {
- __IO uint32_t TXCTL; /*!< SPI Transmit Control. If Transmit FIFO is enabled, in FIFOCFG,
- then values read in this register are affected values in FIFO. */
-
- struct {
- uint32_t : 16;
- __IO uint32_t TXSSEL0_N : 1; /*!< Transmit Slave Select 0. */
- __IO uint32_t TXSSEL1_N : 1; /*!< Transmit Slave Select 1. Valid only for SPI-1 */
- __IO uint32_t TXSSEL2_N : 1; /*!< Transmit Slave Select 2. Valid only for SPI-1 */
- __IO uint32_t TXSSEL3_N : 1; /*!< [Reserved] Transmit Slave Select 3. */
- __IO uint32_t EOTR : 1; /*!< End of Transfer. */
- __IO uint32_t EOFR : 1; /*!< End of Frame. */
- __IO uint32_t RXIGNORE : 1; /*!< Receive Ignore. */
- uint32_t : 1;
- __IO uint32_t LEN : 4; /*!< Data transfer Length. */
- } TXCTL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t DIV; /*!< SPI clock Divider */
-
- struct {
- __IO uint32_t DIVVAL : 16; /*!< Rate divider value. Specifies how the SPI Module clock is divided
- to produce the SPI clock rate in master mode. DIVVAL is -1 encoded
- such that the value 0 results in SPICLK/1, the value 1 results
- in SPICLK/2, up to the maximum possible divide value of 0xFFFF,
- which results in SPICLK/65536. */
- } DIV_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t INTSTAT; /*!< SPI Interrupt Status */
-
- struct {
- uint32_t : 2;
- __I uint32_t RXOV : 1; /*!< Receiver Overrun interrupt flag. */
- __I uint32_t TXUR : 1; /*!< Transmitter Underrun interrupt flag. */
- __I uint32_t SSA : 1; /*!< Slave Select Assert. */
- __I uint32_t SSD : 1; /*!< Slave Select Deassert. */
- uint32_t : 2;
- __I uint32_t MSTIDLE : 1; /*!< Master Idle status flag. */
- } INTSTAT_b; /*!< BitSize */
- };
- __I uint32_t RESERVED2[629];
-
- union {
- __IO uint32_t FIFOCFG; /*!< FIFO configuration and enable register. */
-
- struct {
- __IO uint32_t ENABLETX : 1; /*!< Enable the transmit FIFO. This is automatically enabled when
- PSELID.PERSEL is set to 2 to configure for SPI functionality */
- __IO uint32_t ENABLERX : 1; /*!< Enable the receive FIFO. This is automatically enabled when
- PSELID.PERSEL is set to 2 to configure for SPI functionality */
- uint32_t : 2;
- __I uint32_t SIZE : 2; /*!< FIFO size configuration. This is a read-only field. 0x0 = Reset
- value. 0x1 = FIFO is configured as 4 entries of 16bits. This
- value is read after PSELID.PERSEL=2 for SPI functionlaity. 0x2,
- 0x3 = not applicable. */
- uint32_t : 6;
- __IO uint32_t DMATX : 1; /*!< DMA configuration for transmit. */
- __IO uint32_t DMARX : 1; /*!< DMA configuration for receive. */
- __IO uint32_t WAKETX : 1; /*!< Wakeup for transmit FIFO level. This allows the device to be
- woken from reduced power modes (up to power-down, as long as
- the peripheral function works in that power mode) without enabling
- the TXLVL interrupt. Only DMA wakes up, processes data, and
- goes back to sleep. The CPU will remain stopped until woken
- by another cause, such as DMA completion. */
- __IO uint32_t WAKERX : 1; /*!< Wakeup for receive FIFO level. This allows the device to be
- woken from reduced power modes (up to power-down, as long as
- the peripheral function works in that power mode) without enabling
- the TXLVL interrupt. Only DMA wakes up, processes data, and
- goes back to sleep. The CPU will remain stopped until woken
- by another cause, such as DMA completion. */
- __IO uint32_t EMPTYTX : 1; /*!< Empty command for the transmit FIFO. When a 1 is written to
- this bit, the TX FIFO is emptied. */
- __IO uint32_t EMPTYRX : 1; /*!< Empty command for the receive FIFO. When a 1 is written to this
- bit, the RX FIFO is emptied. */
- __IO uint32_t POPDBG : 1; /*!< Pop FIFO for debug reads. */
- } FIFOCFG_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t FIFOSTAT; /*!< FIFO status register. */
-
- struct {
- __I uint32_t TXERR : 1; /*!< TX FIFO error. Will be set if a transmit FIFO error occurs.
- This could be an overflow caused by pushing data into a full
- FIFO, or by an underflow if the FIFO is empty when data is needed.
- Cleared by writing a 1 to this bit. */
- __I uint32_t RXERR : 1; /*!< RX FIFO error. Will be set if a receive FIFO overflow occurs,
- caused by software or DMA not emptying the FIFO fast enough.
- Cleared by writing a 1 to this bit. */
- uint32_t : 1;
- __I uint32_t PERINT : 1; /*!< Peripheral interrupt. When 1, this indicates that the peripheral
- function has asserted an interrupt. The details can be found
- by reading the peripheral s STAT register. */
- __I uint32_t TXEMPTY : 1; /*!< Transmit FIFO empty. When 1, the transmit FIFO is empty. The
- peripheral may still be processing the last piece of data. */
- __I uint32_t TXNOTFULL : 1; /*!< Transmit FIFO not full. When 1, the transmit FIFO is not full,
- so more data can be written. When 0, the transmit FIFO is full
- and another write would cause it to overflow. */
- __I uint32_t RXNOTEMPTY : 1; /*!< Receive FIFO not empty. When 1, the receive FIFO is not empty,
- so data can be read. When 0, the receive FIFO is empty. */
- __I uint32_t RXFULL : 1; /*!< Receive FIFO full. When 1, the receive FIFO is full. Data needs
- to be read out to prevent the peripheral from causing an overflow. */
- __I uint32_t TXLVL : 5; /*!< Transmit FIFO current level. A 0 means the TX FIFO is currently
- empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other
- values tell how much data is actually in the TX FIFO at the
- point where the read occurs. If the TX FIFO is full, the TXEMPTY
- and TXNOTFULL flags will be 0. */
- uint32_t : 3;
- __I uint32_t RXLVL : 5; /*!< Receive FIFO current level. A 0 means the RX FIFO is currently
- empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other
- values tell how much data is actually in the RX FIFO at the
- point where the read occurs. If the RX FIFO is full, the RXFULL
- and RXNOTEMPTY flags will be 1. */
- } FIFOSTAT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t FIFOTRIG; /*!< FIFO trigger settings for interrupt and DMA request. */
-
- struct {
- __IO uint32_t TXLVLENA : 1; /*!< Transmit FIFO level trigger enable. This trigger will become
- an interrupt if enabled in FIFOINTENSET, or a DMA trigger if
- DMATX in FIFOCFG is set. */
- __IO uint32_t RXLVLENA : 1; /*!< Receive FIFO level trigger enable. This trigger will become
- an interrupt if enabled in FIFOINTENSET, or a DMA trigger if
- DMARX in FIFOCFG is set. */
- uint32_t : 6;
- __IO uint32_t TXLVL : 4; /*!< Transmit FIFO level trigger point. This field is used only when
- TXLVLENA = 1. 0 = trigger when the TX FIFO becomes empty. 1
- = trigger when the TX FIFO level decreases to one entry. ...
- 7 = 1 = trigger when the TX FIFO level decreases to 7 entries
- (is no longer full). */
- uint32_t : 4;
- __IO uint32_t RXLVL : 4; /*!< Receive FIFO level trigger point. The RX FIFO level is checked
- when a new piece of data is received. This field is used only
- when RXLVLENA = 1. 0 = trigger when the RX FIFO has received
- one entry (is no longer empty). 1 = trigger when the RX FIFO
- has received two entries. ... 7 = trigger when the RX FIFO has
- received 8 entries (has become full). */
- } FIFOTRIG_b; /*!< BitSize */
- };
- __I uint32_t RESERVED3;
-
- union {
- __IO uint32_t FIFOINTENSET; /*!< FIFO interrupt enable set (enable) and read register. */
-
- struct {
- __IO uint32_t TXERR : 1; /*!< Determines whether an interrupt occurs when a transmit error
- occurs, based on the TXERR flag in the FIFOSTAT register. */
- __IO uint32_t RXERR : 1; /*!< Determines whether an interrupt occurs when a receive error
- occurs, based on the RXERR flag in the FIFOSTAT register. */
- __IO uint32_t TXLVL : 1; /*!< Determines whether an interrupt occurs when a the transmit FIFO
- reaches the level specified by the TXLVL field in the FIFOTRIG
- register. */
- __IO uint32_t RXLVL : 1; /*!< Determines whether an interrupt occurs when a the receive FIFO
- reaches the level specified by the TXLVL field in the FIFOTRIG
- register. */
- } FIFOINTENSET_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t FIFOINTENCLR; /*!< FIFO interrupt enable clear (disable) and read register. */
-
- struct {
- __IO uint32_t TXERR : 1; /*!< Writing 1 clears the corresponding bit in the FIFOINTENSET register */
- __IO uint32_t RXERR : 1; /*!< Writing 1 clears the corresponding bit in the FIFOINTENSET register */
- __IO uint32_t TXLVL : 1; /*!< Writing 1 clears the corresponding bit in the FIFOINTENSET register */
- __IO uint32_t RXLVL : 1; /*!< Writing 1 clears the corresponding bit in the FIFOINTENSET register */
- } FIFOINTENCLR_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t FIFOINTSTAT; /*!< FIFO interrupt status register. */
-
- struct {
- __I uint32_t TXERR : 1; /*!< TX FIFO error. */
- __I uint32_t RXERR : 1; /*!< RX FIFO error. */
- __I uint32_t TXLVL : 1; /*!< Transmit FIFO level interrupt. */
- __I uint32_t RXLVL : 1; /*!< Receive FIFO level interrupt. */
- __I uint32_t PERINT : 1; /*!< Peripheral interrupt. */
- } FIFOINTSTAT_b; /*!< BitSize */
- };
- __I uint32_t RESERVED4;
-
- union {
- __O uint32_t FIFOWR; /*!< FIFO write data. FIFO data not reset by block reset */
-
- struct {
- __O uint32_t TXDATA : 16; /*!< Transmit data to the FIFO. */
- __O uint32_t TXSSEL0_N : 1; /*!< Transmit Slave Select. This field asserts SSEL0 in master mode.
- The output on the pin is active LOW by default. Remark: The
- active state of the SSEL0 pin is configured by bits in the CFG
- register. */
- __O uint32_t TXSSEL1_N : 1; /*!< Transmit Slave Select. This field asserts SSEL1 in master mode.
- The output on the pin is active LOW by default. Remark: The
- active state of the SSEL1 pin is configured by bits in the CFG
- register. */
- __O uint32_t TXSSEL2_N : 1; /*!< Transmit Slave Select. This field asserts SSEL2 in master mode.
- The output on the pin is active LOW by default. Remark: The
- active state of the SSEL2 pin is configured by bits in the CFG
- register. */
- __O uint32_t TXSSEL3_N : 1; /*!< Transmit Slave Select. This field asserts SSEL3 in master mode.
- The output on the pin is active LOW by default. Remark: The
- active state of the SSEL3 pin is configured by bits in the CFG
- register. */
- __O uint32_t EOTR : 1; /*!< End of Transfer. The asserted SSEL will be deasserted at the
- end of a transfer, and remain so for at least the time specified
- by the Transfer_delay value in the DLY register. */
- __O uint32_t EOFR : 1; /*!< End of Frame. Between frames, a delay may be inserted, as defined
- by the FRAME_DELAY value in the DLY register. The end of a frame
- may not be particularly meaningful if the FRAME_DELAY value
- = 0. This control can be used as part of the support for frame
- lengths greater than 16 bits. */
- __O uint32_t RXIGNORE : 1; /*!< Receive Ignore. This allows data to be transmitted using the
- SPI without the need to read unneeded data from the receiver.Setting
- this bit simplifies the transmit process and can be used with
- the DMA. */
- uint32_t : 1;
- __O uint32_t LEN : 4; /*!< Data Length. Specifies the data length from 1 to 16 bits. Note
- that transfer lengths greater than 16 bits are supported by
- implementing multiple sequential transmits. 0x0 = Data transfer
- is 1 bit in length. Note: when LEN = 0, the underrun status
- is not meaningful. 0x1 = Data transfer is 2 bits in length.
- 0x2 = Data transfer is 3 bits in length. ... 0xF = Data transfer
- is 16 bits in length. */
- } FIFOWR_b; /*!< BitSize */
- };
- __I uint32_t RESERVED5[3];
-
- union {
- __I uint32_t FIFORD; /*!< FIFO read data. */
-
- struct {
- __I uint32_t RXDATA : 16; /*!< Received data from the FIFO. */
- __I uint32_t RXSSEL0_N : 1; /*!< Slave Select for receive. This field allows the state of the
- SSEL0 pin to be saved along with received data. The value will
- reflect the SSEL0 pin for both master and slave operation. A
- zero indicates that a slave select is active. The actual polarity
- of each slave select pin is configured by the related SPOL bit
- in CFG. */
- __I uint32_t RXSSEL1_N : 1; /*!< Slave Select for receive. This field allows the state of the
- SSEL1 pin to be saved along with received data. The value will
- reflect the SSEL1 pin for both master and slave operation. A
- zero indicates that a slave select is active. The actual polarity
- of each slave select pin is configured by the related SPOL bit
- in CFG. */
- __I uint32_t RXSSEL2_N : 1; /*!< Slave Select for receive. This field allows the state of the
- SSEL2 pin to be saved along with received data. The value will
- reflect the SSEL2 pin for both master and slave operation. A
- zero indicates that a slave select is active. The actual polarity
- of each slave select pin is configured by the related SPOL bit
- in CFG. */
- __I uint32_t RXSSEL3_N : 1; /*!< Slave Select for receive. This field allows the state of the
- SSEL3 pin to be saved along with received data. The value will
- reflect the SSEL3 pin for both master and slave operation. A
- zero indicates that a slave select is active. The actual polarity
- of each slave select pin is configured by the related SPOL bit
- in CFG. */
- __I uint32_t SOT : 1; /*!< Start of Transfer flag. This flag will be 1 if this is the first
- data after the SSELs went from deasserted to asserted (i.e.,
- any previous transfer has ended). This information can be used
- to identify the first piece of data in cases where the transfer
- length is greater than 16 bit. */
- } FIFORD_b; /*!< BitSize */
- };
- __I uint32_t RESERVED6[3];
-
- union {
- __I uint32_t FIFORDNOPOP; /*!< FIFO data read with no FIFO pop. */
-
- struct {
- __I uint32_t RXDATA : 16; /*!< Received data from the FIFO. */
- __I uint32_t RXSSEL0_N : 1; /*!< Slave Select for receive. This field allows the state of the
- SSEL0 pin to be saved along with received data. The value will
- reflect the SSEL0 pin for both master and slave operation. A
- zero indicates that a slave select is active. The actual polarity
- of each slave select pin is configured by the related SPOL bit
- in CFG. */
- __I uint32_t RXSSEL1_N : 1; /*!< Slave Select for receive. This field allows the state of the
- SSEL1 pin to be saved along with received data. The value will
- reflect the SSEL1 pin for both master and slave operation. A
- zero indicates that a slave select is active. The actual polarity
- of each slave select pin is configured by the related SPOL bit
- in CFG. */
- __I uint32_t RXSSEL2_N : 1; /*!< Slave Select for receive. This field allows the state of the
- SSEL2 pin to be saved along with received data. The value will
- reflect the SSEL2 pin for both master and slave operation. A
- zero indicates that a slave select is active. The actual polarity
- of each slave select pin is configured by the related SPOL bit
- in CFG. */
- __I uint32_t RXSSEL3_N : 1; /*!< Slave Select for receive. This field allows the state of the
- SSEL3 pin to be saved along with received data. The value will
- reflect the SSEL3 pin for both master and slave operation. A
- zero indicates that a slave select is active. The actual polarity
- of each slave select pin is configured by the related SPOL bit
- in CFG. */
- __I uint32_t SOT : 1; /*!< Start of Transfer flag. This flag will be 1 if this is the first
- data after the SSELs went from deasserted to asserted (i.e.,
- any previous transfer has ended). This information can be used
- to identify the first piece of data in cases where the transfer
- length is greater than 16 bit. */
- } FIFORDNOPOP_b; /*!< BitSize */
- };
- __I uint32_t RESERVED7[109];
-
- union {
- __IO uint32_t PSELID; /*!< Flexcomm ID and peripheral function select register */
-
- struct {
- __IO uint32_t PERSEL : 3; /*!< Peripheral Select. This field is writable by software. 0x0 No
- peripheral selected. 0x1 Reserved. 0x2 SPI function selected
- 0x3 Reserved. 0x4 Reserved. 0x5 Reserved. 0x6 Reserved 0x7 Reserved */
- __IO uint32_t LOCK : 1; /*!< Lock the peripheral select. This field is writable by software.
- 0 Peripheral select can be changed by software. 1 Peripheral
- select is locked and cannot be changed until this Flexcomm or
- the entire device is reset. */
- uint32_t : 1;
- __I uint32_t SPIPRESENT : 1; /*!< SPI present indicator. This field is Read-only. 0 This peripheral
- does not include the SPI function. 1 This peripheral includes
- the SPI function. */
- uint32_t : 6;
- __I uint32_t ID : 20; /*!< Flexcomm ID. */
- } PSELID_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t ID; /*!< SPI Module Identifier */
-
- struct {
- __I uint32_t APERTURE : 8; /*!< Aperture i.e. number minus 1 of consecutive packets 4 Kbytes
- reserved for this IP */
- __I uint32_t MIN_REV : 4; /*!< Minor revision i.e. with no software consequences */
- __I uint32_t MAJ_REV : 4; /*!< Major revision i.e. implies software modifications */
- __I uint32_t ID : 16; /*!< Identifier. This is the unique identifier of the module */
- } ID_b; /*!< BitSize */
- };
-} u0_spi_Type;
-
-
-/* ================================================================================ */
-/* ================ u1_spi ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component spi. It is a Serial Peripheral Interface with APB bus interface. More details will follow. (u1_spi)
- */
-
-typedef struct { /*!< u1_spi Structure */
- __I uint32_t RESERVED0[256];
-
- union {
- __IO uint32_t CFG; /*!< SPI Configuration register */
-
- struct {
- __IO uint32_t ENABLE : 1; /*!< SPI enable. */
- uint32_t : 1;
- __IO uint32_t MASTER : 1; /*!< Master mode select. */
- __IO uint32_t LSBF : 1; /*!< LSB First mode enable. */
- __IO uint32_t CPHA : 1; /*!< Clock Phase select. */
- __IO uint32_t CPOL : 1; /*!< Clock Polarity select. */
- uint32_t : 1;
- __IO uint32_t LOOP : 1; /*!< Loopback mode enable. Loopback mode applies only to Master mode,
- and connects transmit and receive data connected together to
- allow simple software testing. */
- __IO uint32_t SPOL0 : 1; /*!< SSEL0 Polarity select. */
- __IO uint32_t SPOL1 : 1; /*!< SSEL1 Polarity select. Valid only for SPI-1 */
- __IO uint32_t SPOL2 : 1; /*!< SSEL2 Polarity select. Valid only for SPI-1 */
- __IO uint32_t SPOL3 : 1; /*!< [Reserved] SSEL3 Polarity select. */
- } CFG_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t DLY; /*!< SPI Delay register */
-
- struct {
- __IO uint32_t PRE_DELAY : 4; /*!< Controls the amount of time between SSEL assertion and the beginning
- of a data transfer. There is always one SPI clock time between
- SSEL assertion and the first clock edge. This is not considered
- part of the pre-delay. 0x0 = No additional time is inserted.
- 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times
- are inserted. ... 0xF = 15 SPI clock times are inserted. */
- __IO uint32_t POST_DELAY : 4; /*!< Controls the amount of time between the end of a data transfer
- and SSEL deassertion. 0x0 = No additional time is inserted.
- 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times
- are inserted. ... 0xF = 15 SPI clock times are inserted. */
- __IO uint32_t FRAME_DELAY: 4; /*!< If the EOFR flag is set, controls the minimum amount of time
- between the current frame and the next frame (or SSEL deassertion
- if EOTR). 0x0 = No additional time is inserted. 0x1 = 1 SPI
- clock time is inserted. 0x2 = 2 SPI clock times are inserted.
- ... 0xF = 15 SPI clock times are inserted. */
- __IO uint32_t TRANSFER_DELAY: 4; /*!< Controls the minimum amount of time that the SSEL is deasserted
- between transfers. 0x0 = The minimum time that SSEL is deasserted
- is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time
- that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum
- time that SSEL is deasserted is 3 SPI clock times. ... 0xF =
- The minimum time that SSEL is deasserted is 16 SPI clock times. */
- } DLY_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t STAT; /*!< SPI Status. Some status flags can be cleared by writing a 1
- to that bit position. */
-
- struct {
- uint32_t : 2;
- __IO uint32_t RXOV : 1; /*!< Receiver Overrun interrupt flag. This flag applies only to slave
- mode (Master = 0). This flag is set when the beginning of a
- received character is detected while the receiver buffer is
- still in use. If this occurs, the receiver buffer contents are
- preserved, and the incoming data is lost. Data received by the
- SPI should be considered undefined if RxOv is set. */
- __IO uint32_t TXUR : 1; /*!< Transmitter Underrun interrupt flag. This flag applies only
- to slave mode (Master = 0). In this case, the transmitter must
- begin sending new data on the next input clock if the transmitter
- is idle. If that data is not available in the transmitter holding
- register at that point, there is no data to transmit and the
- TXUR flag is set. Data transmitted by the SPI should be considered
- undefined if TXUR is set. */
- __IO uint32_t SSA : 1; /*!< Slave Select Assert. This flag is set whenever any slave select
- transitions from deasserted to asserted, in both master and
- slave modes. This allows determining when the SPI transmit/receive
- functions become busy, and allows waking up the device from
- reduced power modes when a slave mode access begins. This flag
- is cleared by software. */
- __IO uint32_t SSD : 1; /*!< Slave Select Deassert. This flag is set whenever any asserted
- slave selects transition to deasserted, in both master and slave
- modes. This allows determining when the SPI transmit/receive
- functions become idle. This flag is cleared by software. */
- __I uint32_t STALLED : 1; /*!< Stalled status flag. This indicates whether the SPI is currently
- in a stall condition. */
- __IO uint32_t ENDTRANSFER: 1; /*!< End Transfer control bit. Software can set this bit to force
- an end to the current transfer when the transmitter finishes
- any activity already in progress, as if the EOTR flag had been
- set prior to the last transmission. This capability is included
- to support cases where it is not known when transmit data is
- written that it will be the end of a transfer. The bit is cleared
- when the transmitter becomes idle as the transfer comes to an
- end. Forcing an end of transfer in this manner causes any specified
- FRAME */
- __I uint32_t MSTIDLE : 1; /*!< Master idle status flag. This bit is 1 whenever the SPI master
- function is fully idle. This means that the transmit holding
- register is empty and the transmitter is not in the process
- of sending data. */
- } STAT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t INTENSET; /*!< SPI Interrupt Enable read and Set. A complete value may be read
- from this register. Writing a 1 to any implemented bit position
- causes that bit to be set. */
-
- struct {
- uint32_t : 2;
- __IO uint32_t RXOVEN : 1; /*!< RX overrun interrupt enable. Determines whether an interrupt
- occurs when a receiver overrun occurs. This happens in slave
- mode when there is a need for the receiver to move newly received
- data to the RXDAT register when it is already in use. The interface
- prevents receiver overrun in Master mode by not allowing a new
- transmission to begin when a receiver overrun would otherwise
- occur. */
- __IO uint32_t TXUREN : 1; /*!< TX underrun interrupt enable. Determines whether an interrupt
- occurs when a transmitter underrun occurs. This happens in slave
- mode when there is a need to transmit data when none is available. */
- __IO uint32_t SSAEN : 1; /*!< Slave select assert interrupt enable. Determines whether an
- interrupt occurs when the Slave Select is asserted. */
- __IO uint32_t SSDEN : 1; /*!< Slave select deassert interrupt enable. Determines whether an
- interrupt occurs when the Slave Select is deasserted. */
- uint32_t : 2;
- __IO uint32_t MSTIDLEEN : 1; /*!< Master idle interrupt enable. */
- } INTENSET_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t INTENCLR; /*!< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit
- position causes the corresponding bit in INTENSET to be cleared. */
-
- struct {
- uint32_t : 2;
- __IO uint32_t RXOVCLR : 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- __IO uint32_t TXURCLR : 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- __IO uint32_t SSACLR : 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- __IO uint32_t SSDCLR : 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- uint32_t : 2;
- __IO uint32_t MSTIDLECLR : 1; /*!< Writing 1 clears the corresponding bit in the INTENSET register. */
- } INTENCLR_b; /*!< BitSize */
- };
- __I uint32_t RESERVED1[3];
-
- union {
- __IO uint32_t TXCTL; /*!< SPI Transmit Control. If Transmit FIFO is enabled, in FIFOCFG,
- then values read in this register are affected values in FIFO. */
-
- struct {
- uint32_t : 16;
- __IO uint32_t TXSSEL0_N : 1; /*!< Transmit Slave Select 0. */
- __IO uint32_t TXSSEL1_N : 1; /*!< Transmit Slave Select 1. Valid only for SPI-1 */
- __IO uint32_t TXSSEL2_N : 1; /*!< Transmit Slave Select 2. Valid only for SPI-1 */
- __IO uint32_t TXSSEL3_N : 1; /*!< [Reserved] Transmit Slave Select 3. */
- __IO uint32_t EOTR : 1; /*!< End of Transfer. */
- __IO uint32_t EOFR : 1; /*!< End of Frame. */
- __IO uint32_t RXIGNORE : 1; /*!< Receive Ignore. */
- uint32_t : 1;
- __IO uint32_t LEN : 4; /*!< Data transfer Length. */
- } TXCTL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t DIV; /*!< SPI clock Divider */
-
- struct {
- __IO uint32_t DIVVAL : 16; /*!< Rate divider value. Specifies how the SPI Module clock is divided
- to produce the SPI clock rate in master mode. DIVVAL is -1 encoded
- such that the value 0 results in SPICLK/1, the value 1 results
- in SPICLK/2, up to the maximum possible divide value of 0xFFFF,
- which results in SPICLK/65536. */
- } DIV_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t INTSTAT; /*!< SPI Interrupt Status */
-
- struct {
- uint32_t : 2;
- __I uint32_t RXOV : 1; /*!< Receiver Overrun interrupt flag. */
- __I uint32_t TXUR : 1; /*!< Transmitter Underrun interrupt flag. */
- __I uint32_t SSA : 1; /*!< Slave Select Assert. */
- __I uint32_t SSD : 1; /*!< Slave Select Deassert. */
- uint32_t : 2;
- __I uint32_t MSTIDLE : 1; /*!< Master Idle status flag. */
- } INTSTAT_b; /*!< BitSize */
- };
- __I uint32_t RESERVED2[629];
-
- union {
- __IO uint32_t FIFOCFG; /*!< FIFO configuration and enable register. */
-
- struct {
- __IO uint32_t ENABLETX : 1; /*!< Enable the transmit FIFO. This is automatically enabled when
- PSELID.PERSEL is set to 2 to configure for SPI functionality */
- __IO uint32_t ENABLERX : 1; /*!< Enable the receive FIFO. This is automatically enabled when
- PSELID.PERSEL is set to 2 to configure for SPI functionality */
- uint32_t : 2;
- __I uint32_t SIZE : 2; /*!< FIFO size configuration. This is a read-only field. 0x0 = Reset
- value. 0x1 = FIFO is configured as 4 entries of 16bits. This
- value is read after PSELID.PERSEL=2 for SPI functionlaity. 0x2,
- 0x3 = not applicable. */
- uint32_t : 6;
- __IO uint32_t DMATX : 1; /*!< DMA configuration for transmit. */
- __IO uint32_t DMARX : 1; /*!< DMA configuration for receive. */
- __IO uint32_t WAKETX : 1; /*!< Wakeup for transmit FIFO level. This allows the device to be
- woken from reduced power modes (up to power-down, as long as
- the peripheral function works in that power mode) without enabling
- the TXLVL interrupt. Only DMA wakes up, processes data, and
- goes back to sleep. The CPU will remain stopped until woken
- by another cause, such as DMA completion. */
- __IO uint32_t WAKERX : 1; /*!< Wakeup for receive FIFO level. This allows the device to be
- woken from reduced power modes (up to power-down, as long as
- the peripheral function works in that power mode) without enabling
- the TXLVL interrupt. Only DMA wakes up, processes data, and
- goes back to sleep. The CPU will remain stopped until woken
- by another cause, such as DMA completion. */
- __IO uint32_t EMPTYTX : 1; /*!< Empty command for the transmit FIFO. When a 1 is written to
- this bit, the TX FIFO is emptied. */
- __IO uint32_t EMPTYRX : 1; /*!< Empty command for the receive FIFO. When a 1 is written to this
- bit, the RX FIFO is emptied. */
- __IO uint32_t POPDBG : 1; /*!< Pop FIFO for debug reads. */
- } FIFOCFG_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t FIFOSTAT; /*!< FIFO status register. */
-
- struct {
- __I uint32_t TXERR : 1; /*!< TX FIFO error. Will be set if a transmit FIFO error occurs.
- This could be an overflow caused by pushing data into a full
- FIFO, or by an underflow if the FIFO is empty when data is needed.
- Cleared by writing a 1 to this bit. */
- __I uint32_t RXERR : 1; /*!< RX FIFO error. Will be set if a receive FIFO overflow occurs,
- caused by software or DMA not emptying the FIFO fast enough.
- Cleared by writing a 1 to this bit. */
- uint32_t : 1;
- __I uint32_t PERINT : 1; /*!< Peripheral interrupt. When 1, this indicates that the peripheral
- function has asserted an interrupt. The details can be found
- by reading the peripheral s STAT register. */
- __I uint32_t TXEMPTY : 1; /*!< Transmit FIFO empty. When 1, the transmit FIFO is empty. The
- peripheral may still be processing the last piece of data. */
- __I uint32_t TXNOTFULL : 1; /*!< Transmit FIFO not full. When 1, the transmit FIFO is not full,
- so more data can be written. When 0, the transmit FIFO is full
- and another write would cause it to overflow. */
- __I uint32_t RXNOTEMPTY : 1; /*!< Receive FIFO not empty. When 1, the receive FIFO is not empty,
- so data can be read. When 0, the receive FIFO is empty. */
- __I uint32_t RXFULL : 1; /*!< Receive FIFO full. When 1, the receive FIFO is full. Data needs
- to be read out to prevent the peripheral from causing an overflow. */
- __I uint32_t TXLVL : 5; /*!< Transmit FIFO current level. A 0 means the TX FIFO is currently
- empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other
- values tell how much data is actually in the TX FIFO at the
- point where the read occurs. If the TX FIFO is full, the TXEMPTY
- and TXNOTFULL flags will be 0. */
- uint32_t : 3;
- __I uint32_t RXLVL : 5; /*!< Receive FIFO current level. A 0 means the RX FIFO is currently
- empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other
- values tell how much data is actually in the RX FIFO at the
- point where the read occurs. If the RX FIFO is full, the RXFULL
- and RXNOTEMPTY flags will be 1. */
- } FIFOSTAT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t FIFOTRIG; /*!< FIFO trigger settings for interrupt and DMA request. */
-
- struct {
- __IO uint32_t TXLVLENA : 1; /*!< Transmit FIFO level trigger enable. This trigger will become
- an interrupt if enabled in FIFOINTENSET, or a DMA trigger if
- DMATX in FIFOCFG is set. */
- __IO uint32_t RXLVLENA : 1; /*!< Receive FIFO level trigger enable. This trigger will become
- an interrupt if enabled in FIFOINTENSET, or a DMA trigger if
- DMARX in FIFOCFG is set. */
- uint32_t : 6;
- __IO uint32_t TXLVL : 4; /*!< Transmit FIFO level trigger point. This field is used only when
- TXLVLENA = 1. 0 = trigger when the TX FIFO becomes empty. 1
- = trigger when the TX FIFO level decreases to one entry. ...
- 7 = 1 = trigger when the TX FIFO level decreases to 7 entries
- (is no longer full). */
- uint32_t : 4;
- __IO uint32_t RXLVL : 4; /*!< Receive FIFO level trigger point. The RX FIFO level is checked
- when a new piece of data is received. This field is used only
- when RXLVLENA = 1. 0 = trigger when the RX FIFO has received
- one entry (is no longer empty). 1 = trigger when the RX FIFO
- has received two entries. ... 7 = trigger when the RX FIFO has
- received 8 entries (has become full). */
- } FIFOTRIG_b; /*!< BitSize */
- };
- __I uint32_t RESERVED3;
-
- union {
- __IO uint32_t FIFOINTENSET; /*!< FIFO interrupt enable set (enable) and read register. */
-
- struct {
- __IO uint32_t TXERR : 1; /*!< Determines whether an interrupt occurs when a transmit error
- occurs, based on the TXERR flag in the FIFOSTAT register. */
- __IO uint32_t RXERR : 1; /*!< Determines whether an interrupt occurs when a receive error
- occurs, based on the RXERR flag in the FIFOSTAT register. */
- __IO uint32_t TXLVL : 1; /*!< Determines whether an interrupt occurs when a the transmit FIFO
- reaches the level specified by the TXLVL field in the FIFOTRIG
- register. */
- __IO uint32_t RXLVL : 1; /*!< Determines whether an interrupt occurs when a the receive FIFO
- reaches the level specified by the TXLVL field in the FIFOTRIG
- register. */
- } FIFOINTENSET_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t FIFOINTENCLR; /*!< FIFO interrupt enable clear (disable) and read register. */
-
- struct {
- __IO uint32_t TXERR : 1; /*!< Writing 1 clears the corresponding bit in the FIFOINTENSET register */
- __IO uint32_t RXERR : 1; /*!< Writing 1 clears the corresponding bit in the FIFOINTENSET register */
- __IO uint32_t TXLVL : 1; /*!< Writing 1 clears the corresponding bit in the FIFOINTENSET register */
- __IO uint32_t RXLVL : 1; /*!< Writing 1 clears the corresponding bit in the FIFOINTENSET register */
- } FIFOINTENCLR_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t FIFOINTSTAT; /*!< FIFO interrupt status register. */
-
- struct {
- __I uint32_t TXERR : 1; /*!< TX FIFO error. */
- __I uint32_t RXERR : 1; /*!< RX FIFO error. */
- __I uint32_t TXLVL : 1; /*!< Transmit FIFO level interrupt. */
- __I uint32_t RXLVL : 1; /*!< Receive FIFO level interrupt. */
- __I uint32_t PERINT : 1; /*!< Peripheral interrupt. */
- } FIFOINTSTAT_b; /*!< BitSize */
- };
- __I uint32_t RESERVED4;
-
- union {
- __O uint32_t FIFOWR; /*!< FIFO write data. FIFO data not reset by block reset */
-
- struct {
- __O uint32_t TXDATA : 16; /*!< Transmit data to the FIFO. */
- __O uint32_t TXSSEL0_N : 1; /*!< Transmit Slave Select. This field asserts SSEL0 in master mode.
- The output on the pin is active LOW by default. Remark: The
- active state of the SSEL0 pin is configured by bits in the CFG
- register. */
- __O uint32_t TXSSEL1_N : 1; /*!< Transmit Slave Select. This field asserts SSEL1 in master mode.
- The output on the pin is active LOW by default. Remark: The
- active state of the SSEL1 pin is configured by bits in the CFG
- register. */
- __O uint32_t TXSSEL2_N : 1; /*!< Transmit Slave Select. This field asserts SSEL2 in master mode.
- The output on the pin is active LOW by default. Remark: The
- active state of the SSEL2 pin is configured by bits in the CFG
- register. */
- __O uint32_t TXSSEL3_N : 1; /*!< Transmit Slave Select. This field asserts SSEL3 in master mode.
- The output on the pin is active LOW by default. Remark: The
- active state of the SSEL3 pin is configured by bits in the CFG
- register. */
- __O uint32_t EOTR : 1; /*!< End of Transfer. The asserted SSEL will be deasserted at the
- end of a transfer, and remain so for at least the time specified
- by the Transfer_delay value in the DLY register. */
- __O uint32_t EOFR : 1; /*!< End of Frame. Between frames, a delay may be inserted, as defined
- by the FRAME_DELAY value in the DLY register. The end of a frame
- may not be particularly meaningful if the FRAME_DELAY value
- = 0. This control can be used as part of the support for frame
- lengths greater than 16 bits. */
- __O uint32_t RXIGNORE : 1; /*!< Receive Ignore. This allows data to be transmitted using the
- SPI without the need to read unneeded data from the receiver.Setting
- this bit simplifies the transmit process and can be used with
- the DMA. */
- uint32_t : 1;
- __O uint32_t LEN : 4; /*!< Data Length. Specifies the data length from 1 to 16 bits. Note
- that transfer lengths greater than 16 bits are supported by
- implementing multiple sequential transmits. 0x0 = Data transfer
- is 1 bit in length. Note: when LEN = 0, the underrun status
- is not meaningful. 0x1 = Data transfer is 2 bits in length.
- 0x2 = Data transfer is 3 bits in length. ... 0xF = Data transfer
- is 16 bits in length. */
- } FIFOWR_b; /*!< BitSize */
- };
- __I uint32_t RESERVED5[3];
-
- union {
- __I uint32_t FIFORD; /*!< FIFO read data. */
-
- struct {
- __I uint32_t RXDATA : 16; /*!< Received data from the FIFO. */
- __I uint32_t RXSSEL0_N : 1; /*!< Slave Select for receive. This field allows the state of the
- SSEL0 pin to be saved along with received data. The value will
- reflect the SSEL0 pin for both master and slave operation. A
- zero indicates that a slave select is active. The actual polarity
- of each slave select pin is configured by the related SPOL bit
- in CFG. */
- __I uint32_t RXSSEL1_N : 1; /*!< Slave Select for receive. This field allows the state of the
- SSEL1 pin to be saved along with received data. The value will
- reflect the SSEL1 pin for both master and slave operation. A
- zero indicates that a slave select is active. The actual polarity
- of each slave select pin is configured by the related SPOL bit
- in CFG. */
- __I uint32_t RXSSEL2_N : 1; /*!< Slave Select for receive. This field allows the state of the
- SSEL2 pin to be saved along with received data. The value will
- reflect the SSEL2 pin for both master and slave operation. A
- zero indicates that a slave select is active. The actual polarity
- of each slave select pin is configured by the related SPOL bit
- in CFG. */
- __I uint32_t RXSSEL3_N : 1; /*!< Slave Select for receive. This field allows the state of the
- SSEL3 pin to be saved along with received data. The value will
- reflect the SSEL3 pin for both master and slave operation. A
- zero indicates that a slave select is active. The actual polarity
- of each slave select pin is configured by the related SPOL bit
- in CFG. */
- __I uint32_t SOT : 1; /*!< Start of Transfer flag. This flag will be 1 if this is the first
- data after the SSELs went from deasserted to asserted (i.e.,
- any previous transfer has ended). This information can be used
- to identify the first piece of data in cases where the transfer
- length is greater than 16 bit. */
- } FIFORD_b; /*!< BitSize */
- };
- __I uint32_t RESERVED6[3];
-
- union {
- __I uint32_t FIFORDNOPOP; /*!< FIFO data read with no FIFO pop. */
-
- struct {
- __I uint32_t RXDATA : 16; /*!< Received data from the FIFO. */
- __I uint32_t RXSSEL0_N : 1; /*!< Slave Select for receive. This field allows the state of the
- SSEL0 pin to be saved along with received data. The value will
- reflect the SSEL0 pin for both master and slave operation. A
- zero indicates that a slave select is active. The actual polarity
- of each slave select pin is configured by the related SPOL bit
- in CFG. */
- __I uint32_t RXSSEL1_N : 1; /*!< Slave Select for receive. This field allows the state of the
- SSEL1 pin to be saved along with received data. The value will
- reflect the SSEL1 pin for both master and slave operation. A
- zero indicates that a slave select is active. The actual polarity
- of each slave select pin is configured by the related SPOL bit
- in CFG. */
- __I uint32_t RXSSEL2_N : 1; /*!< Slave Select for receive. This field allows the state of the
- SSEL2 pin to be saved along with received data. The value will
- reflect the SSEL2 pin for both master and slave operation. A
- zero indicates that a slave select is active. The actual polarity
- of each slave select pin is configured by the related SPOL bit
- in CFG. */
- __I uint32_t RXSSEL3_N : 1; /*!< Slave Select for receive. This field allows the state of the
- SSEL3 pin to be saved along with received data. The value will
- reflect the SSEL3 pin for both master and slave operation. A
- zero indicates that a slave select is active. The actual polarity
- of each slave select pin is configured by the related SPOL bit
- in CFG. */
- __I uint32_t SOT : 1; /*!< Start of Transfer flag. This flag will be 1 if this is the first
- data after the SSELs went from deasserted to asserted (i.e.,
- any previous transfer has ended). This information can be used
- to identify the first piece of data in cases where the transfer
- length is greater than 16 bit. */
- } FIFORDNOPOP_b; /*!< BitSize */
- };
- __I uint32_t RESERVED7[109];
-
- union {
- __IO uint32_t PSELID; /*!< Flexcomm ID and peripheral function select register */
-
- struct {
- __IO uint32_t PERSEL : 3; /*!< Peripheral Select. This field is writable by software. 0x0 No
- peripheral selected. 0x1 Reserved. 0x2 SPI function selected
- 0x3 Reserved. 0x4 Reserved. 0x5 Reserved. 0x6 Reserved 0x7 Reserved */
- __IO uint32_t LOCK : 1; /*!< Lock the peripheral select. This field is writable by software.
- 0 Peripheral select can be changed by software. 1 Peripheral
- select is locked and cannot be changed until this Flexcomm or
- the entire device is reset. */
- uint32_t : 1;
- __I uint32_t SPIPRESENT : 1; /*!< SPI present indicator. This field is Read-only. 0 This peripheral
- does not include the SPI function. 1 This peripheral includes
- the SPI function. */
- uint32_t : 6;
- __I uint32_t ID : 20; /*!< Flexcomm ID. */
- } PSELID_b; /*!< BitSize */
- };
-
- union {
- __I uint32_t ID; /*!< SPI Module Identifier */
-
- struct {
- __I uint32_t APERTURE : 8; /*!< Aperture i.e. number minus 1 of consecutive packets 4 Kbytes
- reserved for this IP */
- __I uint32_t MIN_REV : 4; /*!< Minor revision i.e. with no software consequences */
- __I uint32_t MAJ_REV : 4; /*!< Major revision i.e. implies software modifications */
- __I uint32_t ID : 16; /*!< Identifier. This is the unique identifier of the module */
- } ID_b; /*!< BitSize */
- };
-} u1_spi_Type;
-
-
-/* ================================================================================ */
-/* ================ u_hash ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief This is the description of component hash It is AES 128-192-256 with GCM mode. More details will follow. (u_hash)
- */
-
-typedef struct { /*!< u_hash Structure */
-
- union {
- __IO uint32_t CTRL; /*!< CTRL */
-
- struct {
- __IO uint32_t CTRL : 32; /*!< (null) */
- } CTRL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t STAT; /*!< STAT */
-
- struct {
- __IO uint32_t STAT : 32; /*!< (null) */
- } STAT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t INTEN; /*!< INTEN */
-
- struct {
- __IO uint32_t INTEN : 32; /*!< (null) */
- } INTEN_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t INTCLR; /*!< INTCLR */
-
- struct {
- __IO uint32_t INTCLR : 32; /*!< (null) */
- } INTCLR_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t MEMCTRL; /*!< MEMCTRL */
-
- struct {
- __IO uint32_t MEMCTRL : 32; /*!< (null) */
- } MEMCTRL_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t MEMADDR; /*!< MEMADDR */
-
- struct {
- __IO uint32_t MEMADDR : 32; /*!< (null) */
- } MEMADDR_b; /*!< BitSize */
- };
- __I uint32_t RESERVED0[2];
-
- union {
- __IO uint32_t INDATA; /*!< INDATA */
-
- struct {
- __IO uint32_t INDATA : 32; /*!< (null) */
- } INDATA_b; /*!< BitSize */
- };
- __I uint32_t RESERVED1[7];
-
- union {
- __IO uint32_t DIGEST; /*!< DIGEST */
-
- struct {
- __IO uint32_t DIGEST : 32; /*!< (null) */
- } DIGEST_b; /*!< BitSize */
- };
- __I uint32_t RESERVED2[7];
-
- union {
- __IO uint32_t OUTD2; /*!< OUTD2 */
-
- struct {
- __IO uint32_t OUTD2 : 32; /*!< (null) */
- } OUTD2_b; /*!< BitSize */
- };
- __I uint32_t RESERVED3[7];
-
- union {
- __IO uint32_t CRYPT; /*!< CRYPT */
-
- struct {
- __IO uint32_t CRYPT : 32; /*!< (null) */
- } CRYPT_b; /*!< BitSize */
- };
-
- union {
- __IO uint32_t CONFIG; /*!< CONFIG */
-
- struct {
- __IO uint32_t CONFIG : 32; /*!< (null) */
- } CONFIG_b; /*!< BitSize */
- };
- __I uint32_t RESERVED4[2];
-
- union {
- __IO uint32_t MASK; /*!< MASK */
-
- struct {
- __IO uint32_t MASK : 32; /*!< (null) */
- } MASK_b; /*!< BitSize */
- };
- __I uint32_t RESERVED5[986];
-
- union {
- __I uint32_t ID; /*!< IP identifier */
-
- struct {
- __I uint32_t APERTURE : 8; /*!< Aperture i.e. number minus 1 of consecutive packets 4 Kbytes
- reserved for this IP */
- __I uint32_t MIN_REV : 4; /*!< Minor revision i.e. with no software consequences */
- __I uint32_t MAJ_REV : 4; /*!< Major revision i.e. implies software modifications */
- __I uint32_t ID : 16; /*!< Identifier. This is the unique identifier of the module */
- } ID_b; /*!< BitSize */
- };
-} u_hash_Type;
-
-
-#include "jn518x_zb_modem.h"
-#include "jn518x_zb_mac.h"
-#include "jn518x_ble_link.h"
-#define APB_ALLOW_BITFIELDS
-#include "jn518x_rfp_modem.h"
-
-/* -------------------- End of section using anonymous unions ------------------- */
-#if defined(__CC_ARM)
- #pragma pop
-#elif defined(__ICCARM__)
- /* leave anonymous unions enabled */
-#elif defined(__GNUC__)
- /* anonymous unions are enabled by default */
-#elif defined(__TMS470__)
- /* anonymous unions are enabled by default */
-#elif defined(__TASKING__)
- #pragma warning restore
-#else
- #warning Not supported compiler type
-#endif
-
-
-
-/* ================================================================================ */
-/* ================ struct 'u_syscon' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* ---------------------------- u_syscon_MEMORYREMAP ---------------------------- */
-#define SYSCON_MEMORYREMAP_MAP_Pos 0 /*!< SYSCON MEMORYREMAP: MAP Position */
-#define SYSCON_MEMORYREMAP_MAP_Msk (0x03UL << SYSCON_MEMORYREMAP_MAP_Pos) /*!< SYSCON MEMORYREMAP: MAP Mask */
-#define SYSCON_MEMORYREMAP_FLASH_REMAP_APP_0_Pos 2 /*!< SYSCON MEMORYREMAP: FLASH_REMAP_APP_0 Position */
-#define SYSCON_MEMORYREMAP_FLASH_REMAP_APP_0_Msk (0x01UL << SYSCON_MEMORYREMAP_FLASH_REMAP_APP_0_Pos)/*!< SYSCON MEMORYREMAP: FLASH_REMAP_APP_0 Mask */
-#define SYSCON_MEMORYREMAP_FLASH_REMAP_APP_1_Pos 3 /*!< SYSCON MEMORYREMAP: FLASH_REMAP_APP_1 Position */
-#define SYSCON_MEMORYREMAP_FLASH_REMAP_APP_1_Msk (0x01UL << SYSCON_MEMORYREMAP_FLASH_REMAP_APP_1_Pos)/*!< SYSCON MEMORYREMAP: FLASH_REMAP_APP_1 Mask */
-#define SYSCON_MEMORYREMAP_FLASH_APP_0_SIZE_Pos 4 /*!< SYSCON MEMORYREMAP: FLASH_APP_0_SIZE Position */
-#define SYSCON_MEMORYREMAP_FLASH_APP_0_SIZE_Msk (0x7fUL << SYSCON_MEMORYREMAP_FLASH_APP_0_SIZE_Pos)/*!< SYSCON MEMORYREMAP: FLASH_APP_0_SIZE Mask */
-#define SYSCON_MEMORYREMAP_FLASH_APP_1_SIZE_Pos 12 /*!< SYSCON MEMORYREMAP: FLASH_APP_1_SIZE Position */
-#define SYSCON_MEMORYREMAP_FLASH_APP_1_SIZE_Msk (0x7fUL << SYSCON_MEMORYREMAP_FLASH_APP_1_SIZE_Pos)/*!< SYSCON MEMORYREMAP: FLASH_APP_1_SIZE Mask */
-#define SYSCON_MEMORYREMAP_QSPI_REMAP_APP_0_Pos 20 /*!< SYSCON MEMORYREMAP: QSPI_REMAP_APP_0 Position */
-#define SYSCON_MEMORYREMAP_QSPI_REMAP_APP_0_Msk (0x03UL << SYSCON_MEMORYREMAP_QSPI_REMAP_APP_0_Pos)/*!< SYSCON MEMORYREMAP: QSPI_REMAP_APP_0 Mask */
-#define SYSCON_MEMORYREMAP_QSPI_REMAP_APP_1_Pos 22 /*!< SYSCON MEMORYREMAP: QSPI_REMAP_APP_1 Position */
-#define SYSCON_MEMORYREMAP_QSPI_REMAP_APP_1_Msk (0x03UL << SYSCON_MEMORYREMAP_QSPI_REMAP_APP_1_Pos)/*!< SYSCON MEMORYREMAP: QSPI_REMAP_APP_1 Mask */
-#define SYSCON_MEMORYREMAP_QSPI_REMAP_APP_2_Pos 24 /*!< SYSCON MEMORYREMAP: QSPI_REMAP_APP_2 Position */
-#define SYSCON_MEMORYREMAP_QSPI_REMAP_APP_2_Msk (0x03UL << SYSCON_MEMORYREMAP_QSPI_REMAP_APP_2_Pos)/*!< SYSCON MEMORYREMAP: QSPI_REMAP_APP_2 Mask */
-#define SYSCON_MEMORYREMAP_QSPI_REMAP_APP_3_Pos 26 /*!< SYSCON MEMORYREMAP: QSPI_REMAP_APP_3 Position */
-#define SYSCON_MEMORYREMAP_QSPI_REMAP_APP_3_Msk (0x03UL << SYSCON_MEMORYREMAP_QSPI_REMAP_APP_3_Pos)/*!< SYSCON MEMORYREMAP: QSPI_REMAP_APP_3 Mask */
-
-/* ----------------------------- u_syscon_AHBMATPRIO ---------------------------- */
-#define SYSCON_AHBMATPRIO_PRI_CM40_ICODE_Pos 0 /*!< SYSCON AHBMATPRIO: PRI_CM40_ICODE Position */
-#define SYSCON_AHBMATPRIO_PRI_CM40_ICODE_Msk (0x03UL << SYSCON_AHBMATPRIO_PRI_CM40_ICODE_Pos) /*!< SYSCON AHBMATPRIO: PRI_CM40_ICODE Mask */
-#define SYSCON_AHBMATPRIO_PRI_CM40_DCODE_Pos 2 /*!< SYSCON AHBMATPRIO: PRI_CM40_DCODE Position */
-#define SYSCON_AHBMATPRIO_PRI_CM40_DCODE_Msk (0x03UL << SYSCON_AHBMATPRIO_PRI_CM40_DCODE_Pos) /*!< SYSCON AHBMATPRIO: PRI_CM40_DCODE Mask */
-#define SYSCON_AHBMATPRIO_PRI_CM40_SYS_Pos 4 /*!< SYSCON AHBMATPRIO: PRI_CM40_SYS Position */
-#define SYSCON_AHBMATPRIO_PRI_CM40_SYS_Msk (0x03UL << SYSCON_AHBMATPRIO_PRI_CM40_SYS_Pos) /*!< SYSCON AHBMATPRIO: PRI_CM40_SYS Mask */
-#define SYSCON_AHBMATPRIO_PRI_DMA_Pos 6 /*!< SYSCON AHBMATPRIO: PRI_DMA Position */
-#define SYSCON_AHBMATPRIO_PRI_DMA_Msk (0x03UL << SYSCON_AHBMATPRIO_PRI_DMA_Pos) /*!< SYSCON AHBMATPRIO: PRI_DMA Mask */
-#define SYSCON_AHBMATPRIO_PRI_MODEM_Pos 8 /*!< SYSCON AHBMATPRIO: PRI_MODEM Position */
-#define SYSCON_AHBMATPRIO_PRI_MODEM_Msk (0x03UL << SYSCON_AHBMATPRIO_PRI_MODEM_Pos) /*!< SYSCON AHBMATPRIO: PRI_MODEM Mask */
-#define SYSCON_AHBMATPRIO_PRI_CM41_ICODE_Pos 10 /*!< SYSCON AHBMATPRIO: PRI_CM41_ICODE Position */
-#define SYSCON_AHBMATPRIO_PRI_CM41_ICODE_Msk (0x03UL << SYSCON_AHBMATPRIO_PRI_CM41_ICODE_Pos) /*!< SYSCON AHBMATPRIO: PRI_CM41_ICODE Mask */
-#define SYSCON_AHBMATPRIO_PRI_CM41_DCODE_Pos 12 /*!< SYSCON AHBMATPRIO: PRI_CM41_DCODE Position */
-#define SYSCON_AHBMATPRIO_PRI_CM41_DCODE_Msk (0x03UL << SYSCON_AHBMATPRIO_PRI_CM41_DCODE_Pos) /*!< SYSCON AHBMATPRIO: PRI_CM41_DCODE Mask */
-#define SYSCON_AHBMATPRIO_PRI_CM41_SYS_Pos 14 /*!< SYSCON AHBMATPRIO: PRI_CM41_SYS Position */
-#define SYSCON_AHBMATPRIO_PRI_CM41_SYS_Msk (0x03UL << SYSCON_AHBMATPRIO_PRI_CM41_SYS_Pos) /*!< SYSCON AHBMATPRIO: PRI_CM41_SYS Mask */
-#define SYSCON_AHBMATPRIO_PRI_TPR_Pos 16 /*!< SYSCON AHBMATPRIO: PRI_TPR Position */
-#define SYSCON_AHBMATPRIO_PRI_TPR_Msk (0x03UL << SYSCON_AHBMATPRIO_PRI_TPR_Pos) /*!< SYSCON AHBMATPRIO: PRI_TPR Mask */
-
-/* ------------------------- u_syscon_BUFFERINGAHB2VPB0 ------------------------- */
-#define SYSCON_BUFFERINGAHB2VPB0_SYSCON_Pos 0 /*!< SYSCON BUFFERINGAHB2VPB0: SYSCON Position */
-#define SYSCON_BUFFERINGAHB2VPB0_SYSCON_Msk (0x01UL << SYSCON_BUFFERINGAHB2VPB0_SYSCON_Pos) /*!< SYSCON BUFFERINGAHB2VPB0: SYSCON Mask */
-#define SYSCON_BUFFERINGAHB2VPB0_FIREWALL_Pos 1 /*!< SYSCON BUFFERINGAHB2VPB0: FIREWALL Position */
-#define SYSCON_BUFFERINGAHB2VPB0_FIREWALL_Msk (0x01UL << SYSCON_BUFFERINGAHB2VPB0_FIREWALL_Pos) /*!< SYSCON BUFFERINGAHB2VPB0: FIREWALL Mask */
-#define SYSCON_BUFFERINGAHB2VPB0_OTPC_Pos 2 /*!< SYSCON BUFFERINGAHB2VPB0: OTPC Position */
-#define SYSCON_BUFFERINGAHB2VPB0_OTPC_Msk (0x01UL << SYSCON_BUFFERINGAHB2VPB0_OTPC_Pos) /*!< SYSCON BUFFERINGAHB2VPB0: OTPC Mask */
-#define SYSCON_BUFFERINGAHB2VPB0_I2C0_Pos 3 /*!< SYSCON BUFFERINGAHB2VPB0: I2C0 Position */
-#define SYSCON_BUFFERINGAHB2VPB0_I2C0_Msk (0x01UL << SYSCON_BUFFERINGAHB2VPB0_I2C0_Pos) /*!< SYSCON BUFFERINGAHB2VPB0: I2C0 Mask */
-#define SYSCON_BUFFERINGAHB2VPB0_I2C1_Pos 4 /*!< SYSCON BUFFERINGAHB2VPB0: I2C1 Position */
-#define SYSCON_BUFFERINGAHB2VPB0_I2C1_Msk (0x01UL << SYSCON_BUFFERINGAHB2VPB0_I2C1_Pos) /*!< SYSCON BUFFERINGAHB2VPB0: I2C1 Mask */
-#define SYSCON_BUFFERINGAHB2VPB0_I2C2_Pos 5 /*!< SYSCON BUFFERINGAHB2VPB0: I2C2 Position */
-#define SYSCON_BUFFERINGAHB2VPB0_I2C2_Msk (0x01UL << SYSCON_BUFFERINGAHB2VPB0_I2C2_Pos) /*!< SYSCON BUFFERINGAHB2VPB0: I2C2 Mask */
-#define SYSCON_BUFFERINGAHB2VPB0_ISO7816_Pos 6 /*!< SYSCON BUFFERINGAHB2VPB0: ISO7816 Position */
-#define SYSCON_BUFFERINGAHB2VPB0_ISO7816_Msk (0x01UL << SYSCON_BUFFERINGAHB2VPB0_ISO7816_Pos) /*!< SYSCON BUFFERINGAHB2VPB0: ISO7816 Mask */
-#define SYSCON_BUFFERINGAHB2VPB0_IR_Pos 7 /*!< SYSCON BUFFERINGAHB2VPB0: IR Position */
-#define SYSCON_BUFFERINGAHB2VPB0_IR_Msk (0x01UL << SYSCON_BUFFERINGAHB2VPB0_IR_Pos) /*!< SYSCON BUFFERINGAHB2VPB0: IR Mask */
-#define SYSCON_BUFFERINGAHB2VPB0_CODEPATCH_Pos 8 /*!< SYSCON BUFFERINGAHB2VPB0: CODEPATCH Position */
-#define SYSCON_BUFFERINGAHB2VPB0_CODEPATCH_Msk (0x01UL << SYSCON_BUFFERINGAHB2VPB0_CODEPATCH_Pos) /*!< SYSCON BUFFERINGAHB2VPB0: CODEPATCH Mask */
-#define SYSCON_BUFFERINGAHB2VPB0_FLASHCTRL_Pos 9 /*!< SYSCON BUFFERINGAHB2VPB0: FLASHCTRL Position */
-#define SYSCON_BUFFERINGAHB2VPB0_FLASHCTRL_Msk (0x01UL << SYSCON_BUFFERINGAHB2VPB0_FLASHCTRL_Pos) /*!< SYSCON BUFFERINGAHB2VPB0: FLASHCTRL Mask */
-#define SYSCON_BUFFERINGAHB2VPB0_WDT_Pos 10 /*!< SYSCON BUFFERINGAHB2VPB0: WDT Position */
-#define SYSCON_BUFFERINGAHB2VPB0_WDT_Msk (0x01UL << SYSCON_BUFFERINGAHB2VPB0_WDT_Pos) /*!< SYSCON BUFFERINGAHB2VPB0: WDT Mask */
-#define SYSCON_BUFFERINGAHB2VPB0_RTC_Pos 11 /*!< SYSCON BUFFERINGAHB2VPB0: RTC Position */
-#define SYSCON_BUFFERINGAHB2VPB0_RTC_Msk (0x01UL << SYSCON_BUFFERINGAHB2VPB0_RTC_Pos) /*!< SYSCON BUFFERINGAHB2VPB0: RTC Mask */
-#define SYSCON_BUFFERINGAHB2VPB0_PWM_Pos 12 /*!< SYSCON BUFFERINGAHB2VPB0: PWM Position */
-#define SYSCON_BUFFERINGAHB2VPB0_PWM_Msk (0x01UL << SYSCON_BUFFERINGAHB2VPB0_PWM_Pos) /*!< SYSCON BUFFERINGAHB2VPB0: PWM Mask */
-#define SYSCON_BUFFERINGAHB2VPB0_RNG_Pos 13 /*!< SYSCON BUFFERINGAHB2VPB0: RNG Position */
-#define SYSCON_BUFFERINGAHB2VPB0_RNG_Msk (0x01UL << SYSCON_BUFFERINGAHB2VPB0_RNG_Pos) /*!< SYSCON BUFFERINGAHB2VPB0: RNG Mask */
-#define SYSCON_BUFFERINGAHB2VPB0_PMUX_Pos 14 /*!< SYSCON BUFFERINGAHB2VPB0: PMUX Position */
-#define SYSCON_BUFFERINGAHB2VPB0_PMUX_Msk (0x01UL << SYSCON_BUFFERINGAHB2VPB0_PMUX_Pos) /*!< SYSCON BUFFERINGAHB2VPB0: PMUX Mask */
-#define SYSCON_BUFFERINGAHB2VPB0_IOCON_Pos 15 /*!< SYSCON BUFFERINGAHB2VPB0: IOCON Position */
-#define SYSCON_BUFFERINGAHB2VPB0_IOCON_Msk (0x01UL << SYSCON_BUFFERINGAHB2VPB0_IOCON_Pos) /*!< SYSCON BUFFERINGAHB2VPB0: IOCON Mask */
-#define SYSCON_BUFFERINGAHB2VPB0_GPIOINT_Pos 16 /*!< SYSCON BUFFERINGAHB2VPB0: GPIOINT Position */
-#define SYSCON_BUFFERINGAHB2VPB0_GPIOINT_Msk (0x01UL << SYSCON_BUFFERINGAHB2VPB0_GPIOINT_Pos) /*!< SYSCON BUFFERINGAHB2VPB0: GPIOINT Mask */
-#define SYSCON_BUFFERINGAHB2VPB0_GPIOGLOBALINT_Pos 17 /*!< SYSCON BUFFERINGAHB2VPB0: GPIOGLOBALINT Position */
-#define SYSCON_BUFFERINGAHB2VPB0_GPIOGLOBALINT_Msk (0x01UL << SYSCON_BUFFERINGAHB2VPB0_GPIOGLOBALINT_Pos)/*!< SYSCON BUFFERINGAHB2VPB0: GPIOGLOBALINT Mask */
-#define SYSCON_BUFFERINGAHB2VPB0_PMC_Pos 18 /*!< SYSCON BUFFERINGAHB2VPB0: PMC Position */
-#define SYSCON_BUFFERINGAHB2VPB0_PMC_Msk (0x01UL << SYSCON_BUFFERINGAHB2VPB0_PMC_Pos) /*!< SYSCON BUFFERINGAHB2VPB0: PMC Mask */
-#define SYSCON_BUFFERINGAHB2VPB0_RFP_Pos 19 /*!< SYSCON BUFFERINGAHB2VPB0: RFP Position */
-#define SYSCON_BUFFERINGAHB2VPB0_RFP_Msk (0x01UL << SYSCON_BUFFERINGAHB2VPB0_RFP_Pos) /*!< SYSCON BUFFERINGAHB2VPB0: RFP Mask */
-#define SYSCON_BUFFERINGAHB2VPB0_BLE_Pos 20 /*!< SYSCON BUFFERINGAHB2VPB0: BLE Position */
-#define SYSCON_BUFFERINGAHB2VPB0_BLE_Msk (0x01UL << SYSCON_BUFFERINGAHB2VPB0_BLE_Pos) /*!< SYSCON BUFFERINGAHB2VPB0: BLE Mask */
-
-/* ------------------------- u_syscon_BUFFERINGAHB2VPB1 ------------------------- */
-#define SYSCON_BUFFERINGAHB2VPB1_ASYNCSYSCON_Pos 0 /*!< SYSCON BUFFERINGAHB2VPB1: ASYNCSYSCON Position */
-#define SYSCON_BUFFERINGAHB2VPB1_ASYNCSYSCON_Msk (0x01UL << SYSCON_BUFFERINGAHB2VPB1_ASYNCSYSCON_Pos)/*!< SYSCON BUFFERINGAHB2VPB1: ASYNCSYSCON Mask */
-#define SYSCON_BUFFERINGAHB2VPB1_CT32B0_Pos 1 /*!< SYSCON BUFFERINGAHB2VPB1: CT32B0 Position */
-#define SYSCON_BUFFERINGAHB2VPB1_CT32B0_Msk (0x01UL << SYSCON_BUFFERINGAHB2VPB1_CT32B0_Pos) /*!< SYSCON BUFFERINGAHB2VPB1: CT32B0 Mask */
-#define SYSCON_BUFFERINGAHB2VPB1_CT32B1_Pos 2 /*!< SYSCON BUFFERINGAHB2VPB1: CT32B1 Position */
-#define SYSCON_BUFFERINGAHB2VPB1_CT32B1_Msk (0x01UL << SYSCON_BUFFERINGAHB2VPB1_CT32B1_Pos) /*!< SYSCON BUFFERINGAHB2VPB1: CT32B1 Mask */
-
-/* ----------------------------- u_syscon_SYSTCKCAL ----------------------------- */
-#define SYSCON_SYSTCKCAL_CAL_Pos 0 /*!< SYSCON SYSTCKCAL: CAL Position */
-#define SYSCON_SYSTCKCAL_CAL_Msk (0x00ffffffUL << SYSCON_SYSTCKCAL_CAL_Pos) /*!< SYSCON SYSTCKCAL: CAL Mask */
-#define SYSCON_SYSTCKCAL_SKEW_Pos 24 /*!< SYSCON SYSTCKCAL: SKEW Position */
-#define SYSCON_SYSTCKCAL_SKEW_Msk (0x01UL << SYSCON_SYSTCKCAL_SKEW_Pos) /*!< SYSCON SYSTCKCAL: SKEW Mask */
-#define SYSCON_SYSTCKCAL_NOREF_Pos 25 /*!< SYSCON SYSTCKCAL: NOREF Position */
-#define SYSCON_SYSTCKCAL_NOREF_Msk (0x01UL << SYSCON_SYSTCKCAL_NOREF_Pos) /*!< SYSCON SYSTCKCAL: NOREF Mask */
-
-/* ------------------------------- u_syscon_NMISRC ------------------------------ */
-#define SYSCON_NMISRC_IRQM40_Pos 0 /*!< SYSCON NMISRC: IRQM40 Position */
-#define SYSCON_NMISRC_IRQM40_Msk (0x3fUL << SYSCON_NMISRC_IRQM40_Pos) /*!< SYSCON NMISRC: IRQM40 Mask */
-#define SYSCON_NMISRC_IRQM41_Pos 8 /*!< SYSCON NMISRC: IRQM41 Position */
-#define SYSCON_NMISRC_IRQM41_Msk (0x3fUL << SYSCON_NMISRC_IRQM41_Pos) /*!< SYSCON NMISRC: IRQM41 Mask */
-#define SYSCON_NMISRC_NMIENM41_Pos 30 /*!< SYSCON NMISRC: NMIENM41 Position */
-#define SYSCON_NMISRC_NMIENM41_Msk (0x01UL << SYSCON_NMISRC_NMIENM41_Pos) /*!< SYSCON NMISRC: NMIENM41 Mask */
-#define SYSCON_NMISRC_NMIENM40_Pos 31 /*!< SYSCON NMISRC: NMIENM40 Position */
-#define SYSCON_NMISRC_NMIENM40_Msk (0x01UL << SYSCON_NMISRC_NMIENM40_Pos) /*!< SYSCON NMISRC: NMIENM40 Mask */
-
-/* ---------------------------- u_syscon_ASYNCAPBCTRL --------------------------- */
-#define SYSCON_ASYNCAPBCTRL_ENABLE_Pos 0 /*!< SYSCON ASYNCAPBCTRL: ENABLE Position */
-#define SYSCON_ASYNCAPBCTRL_ENABLE_Msk (0x01UL << SYSCON_ASYNCAPBCTRL_ENABLE_Pos) /*!< SYSCON ASYNCAPBCTRL: ENABLE Mask */
-
-/* ---------------------------- u_syscon_PRESETCTRL0 ---------------------------- */
-#define SYSCON_PRESETCTRL0_FLASH_RST_Pos 8 /*!< SYSCON PRESETCTRL0: FLASH_RST Position */
-#define SYSCON_PRESETCTRL0_FLASH_RST_Msk (0x01UL << SYSCON_PRESETCTRL0_FLASH_RST_Pos) /*!< SYSCON PRESETCTRL0: FLASH_RST Mask */
-#define SYSCON_PRESETCTRL0_SPIFI_RST_Pos 10 /*!< SYSCON PRESETCTRL0: SPIFI_RST Position */
-#define SYSCON_PRESETCTRL0_SPIFI_RST_Msk (0x01UL << SYSCON_PRESETCTRL0_SPIFI_RST_Pos) /*!< SYSCON PRESETCTRL0: SPIFI_RST Mask */
-#define SYSCON_PRESETCTRL0_MUX_RST_Pos 11 /*!< SYSCON PRESETCTRL0: MUX_RST Position */
-#define SYSCON_PRESETCTRL0_MUX_RST_Msk (0x01UL << SYSCON_PRESETCTRL0_MUX_RST_Pos) /*!< SYSCON PRESETCTRL0: MUX_RST Mask */
-#define SYSCON_PRESETCTRL0_BLE_TIMING_GEN_RST_Pos 12 /*!< SYSCON PRESETCTRL0: BLE_TIMING_GEN_RST Position */
-#define SYSCON_PRESETCTRL0_BLE_TIMING_GEN_RST_Msk (0x01UL << SYSCON_PRESETCTRL0_BLE_TIMING_GEN_RST_Pos)/*!< SYSCON PRESETCTRL0: BLE_TIMING_GEN_RST Mask */
-#define SYSCON_PRESETCTRL0_IOCON_RST_Pos 13 /*!< SYSCON PRESETCTRL0: IOCON_RST Position */
-#define SYSCON_PRESETCTRL0_IOCON_RST_Msk (0x01UL << SYSCON_PRESETCTRL0_IOCON_RST_Pos) /*!< SYSCON PRESETCTRL0: IOCON_RST Mask */
-#define SYSCON_PRESETCTRL0_GPIO_RST_Pos 14 /*!< SYSCON PRESETCTRL0: GPIO_RST Position */
-#define SYSCON_PRESETCTRL0_GPIO_RST_Msk (0x01UL << SYSCON_PRESETCTRL0_GPIO_RST_Pos) /*!< SYSCON PRESETCTRL0: GPIO_RST Mask */
-#define SYSCON_PRESETCTRL0_PINT_RST_Pos 18 /*!< SYSCON PRESETCTRL0: PINT_RST Position */
-#define SYSCON_PRESETCTRL0_PINT_RST_Msk (0x01UL << SYSCON_PRESETCTRL0_PINT_RST_Pos) /*!< SYSCON PRESETCTRL0: PINT_RST Mask */
-#define SYSCON_PRESETCTRL0_GINT_RST_Pos 19 /*!< SYSCON PRESETCTRL0: GINT_RST Position */
-#define SYSCON_PRESETCTRL0_GINT_RST_Msk (0x01UL << SYSCON_PRESETCTRL0_GINT_RST_Pos) /*!< SYSCON PRESETCTRL0: GINT_RST Mask */
-#define SYSCON_PRESETCTRL0_DMA_RST_Pos 20 /*!< SYSCON PRESETCTRL0: DMA_RST Position */
-#define SYSCON_PRESETCTRL0_DMA_RST_Msk (0x01UL << SYSCON_PRESETCTRL0_DMA_RST_Pos) /*!< SYSCON PRESETCTRL0: DMA_RST Mask */
-#define SYSCON_PRESETCTRL0_ISO7816_RST_Pos 21 /*!< SYSCON PRESETCTRL0: ISO7816_RST Position */
-#define SYSCON_PRESETCTRL0_ISO7816_RST_Msk (0x01UL << SYSCON_PRESETCTRL0_ISO7816_RST_Pos) /*!< SYSCON PRESETCTRL0: ISO7816_RST Mask */
-#define SYSCON_PRESETCTRL0_WWDT_RST_Pos 22 /*!< SYSCON PRESETCTRL0: WWDT_RST Position */
-#define SYSCON_PRESETCTRL0_WWDT_RST_Msk (0x01UL << SYSCON_PRESETCTRL0_WWDT_RST_Pos) /*!< SYSCON PRESETCTRL0: WWDT_RST Mask */
-#define SYSCON_PRESETCTRL0_RTC_RST_Pos 23 /*!< SYSCON PRESETCTRL0: RTC_RST Position */
-#define SYSCON_PRESETCTRL0_RTC_RST_Msk (0x01UL << SYSCON_PRESETCTRL0_RTC_RST_Pos) /*!< SYSCON PRESETCTRL0: RTC_RST Mask */
-#define SYSCON_PRESETCTRL0_ANA_INT_CTRL_RST_Pos 24 /*!< SYSCON PRESETCTRL0: ANA_INT_CTRL_RST Position */
-#define SYSCON_PRESETCTRL0_ANA_INT_CTRL_RST_Msk (0x01UL << SYSCON_PRESETCTRL0_ANA_INT_CTRL_RST_Pos)/*!< SYSCON PRESETCTRL0: ANA_INT_CTRL_RST Mask */
-#define SYSCON_PRESETCTRL0_WAKE_UP_TIMERS_RST_Pos 25 /*!< SYSCON PRESETCTRL0: WAKE_UP_TIMERS_RST Position */
-#define SYSCON_PRESETCTRL0_WAKE_UP_TIMERS_RST_Msk (0x01UL << SYSCON_PRESETCTRL0_WAKE_UP_TIMERS_RST_Pos)/*!< SYSCON PRESETCTRL0: WAKE_UP_TIMERS_RST Mask */
-#define SYSCON_PRESETCTRL0_MAILBOX_RST_Pos 26 /*!< SYSCON PRESETCTRL0: MAILBOX_RST Position */
-#define SYSCON_PRESETCTRL0_MAILBOX_RST_Msk (0x01UL << SYSCON_PRESETCTRL0_MAILBOX_RST_Pos) /*!< SYSCON PRESETCTRL0: MAILBOX_RST Mask */
-#define SYSCON_PRESETCTRL0_ADC_RST_Pos 27 /*!< SYSCON PRESETCTRL0: ADC_RST Position */
-#define SYSCON_PRESETCTRL0_ADC_RST_Msk (0x01UL << SYSCON_PRESETCTRL0_ADC_RST_Pos) /*!< SYSCON PRESETCTRL0: ADC_RST Mask */
-#define SYSCON_PRESETCTRL0_EFUSE_RST_Pos 28 /*!< SYSCON PRESETCTRL0: EFUSE_RST Position */
-#define SYSCON_PRESETCTRL0_EFUSE_RST_Msk (0x01UL << SYSCON_PRESETCTRL0_EFUSE_RST_Pos) /*!< SYSCON PRESETCTRL0: EFUSE_RST Mask */
-#define SYSCON_PRESETCTRL0_PVT_RST_Pos 29 /*!< SYSCON PRESETCTRL0: PVT_RST Position */
-#define SYSCON_PRESETCTRL0_PVT_RST_Msk (0x01UL << SYSCON_PRESETCTRL0_PVT_RST_Pos) /*!< SYSCON PRESETCTRL0: PVT_RST Mask */
-
-/* ---------------------------- u_syscon_PRESETCTRL1 ---------------------------- */
-#define SYSCON_PRESETCTRL1_USART0_RST_Pos 11 /*!< SYSCON PRESETCTRL1: USART0_RST Position */
-#define SYSCON_PRESETCTRL1_USART0_RST_Msk (0x01UL << SYSCON_PRESETCTRL1_USART0_RST_Pos) /*!< SYSCON PRESETCTRL1: USART0_RST Mask */
-#define SYSCON_PRESETCTRL1_USART1_RST_Pos 12 /*!< SYSCON PRESETCTRL1: USART1_RST Position */
-#define SYSCON_PRESETCTRL1_USART1_RST_Msk (0x01UL << SYSCON_PRESETCTRL1_USART1_RST_Pos) /*!< SYSCON PRESETCTRL1: USART1_RST Mask */
-#define SYSCON_PRESETCTRL1_I2C0_RST_Pos 13 /*!< SYSCON PRESETCTRL1: I2C0_RST Position */
-#define SYSCON_PRESETCTRL1_I2C0_RST_Msk (0x01UL << SYSCON_PRESETCTRL1_I2C0_RST_Pos) /*!< SYSCON PRESETCTRL1: I2C0_RST Mask */
-#define SYSCON_PRESETCTRL1_I2C1_RST_Pos 14 /*!< SYSCON PRESETCTRL1: I2C1_RST Position */
-#define SYSCON_PRESETCTRL1_I2C1_RST_Msk (0x01UL << SYSCON_PRESETCTRL1_I2C1_RST_Pos) /*!< SYSCON PRESETCTRL1: I2C1_RST Mask */
-#define SYSCON_PRESETCTRL1_SPI0_RST_Pos 15 /*!< SYSCON PRESETCTRL1: SPI0_RST Position */
-#define SYSCON_PRESETCTRL1_SPI0_RST_Msk (0x01UL << SYSCON_PRESETCTRL1_SPI0_RST_Pos) /*!< SYSCON PRESETCTRL1: SPI0_RST Mask */
-#define SYSCON_PRESETCTRL1_SPI1_RST_Pos 16 /*!< SYSCON PRESETCTRL1: SPI1_RST Position */
-#define SYSCON_PRESETCTRL1_SPI1_RST_Msk (0x01UL << SYSCON_PRESETCTRL1_SPI1_RST_Pos) /*!< SYSCON PRESETCTRL1: SPI1_RST Mask */
-#define SYSCON_PRESETCTRL1_IR_RST_Pos 17 /*!< SYSCON PRESETCTRL1: IR_RST Position */
-#define SYSCON_PRESETCTRL1_IR_RST_Msk (0x01UL << SYSCON_PRESETCTRL1_IR_RST_Pos) /*!< SYSCON PRESETCTRL1: IR_RST Mask */
-#define SYSCON_PRESETCTRL1_PWM_RST_Pos 18 /*!< SYSCON PRESETCTRL1: PWM_RST Position */
-#define SYSCON_PRESETCTRL1_PWM_RST_Msk (0x01UL << SYSCON_PRESETCTRL1_PWM_RST_Pos) /*!< SYSCON PRESETCTRL1: PWM_RST Mask */
-#define SYSCON_PRESETCTRL1_RNG_RST_Pos 19 /*!< SYSCON PRESETCTRL1: RNG_RST Position */
-#define SYSCON_PRESETCTRL1_RNG_RST_Msk (0x01UL << SYSCON_PRESETCTRL1_RNG_RST_Pos) /*!< SYSCON PRESETCTRL1: RNG_RST Mask */
-#define SYSCON_PRESETCTRL1_I2C2_RST_Pos 20 /*!< SYSCON PRESETCTRL1: I2C2_RST Position */
-#define SYSCON_PRESETCTRL1_I2C2_RST_Msk (0x01UL << SYSCON_PRESETCTRL1_I2C2_RST_Pos) /*!< SYSCON PRESETCTRL1: I2C2_RST Mask */
-#define SYSCON_PRESETCTRL1_ZIGBEE_RST_Pos 21 /*!< SYSCON PRESETCTRL1: ZIGBEE_RST Position */
-#define SYSCON_PRESETCTRL1_ZIGBEE_RST_Msk (0x01UL << SYSCON_PRESETCTRL1_ZIGBEE_RST_Pos) /*!< SYSCON PRESETCTRL1: ZIGBEE_RST Mask */
-#define SYSCON_PRESETCTRL1_BLE_RST_Pos 22 /*!< SYSCON PRESETCTRL1: BLE_RST Position */
-#define SYSCON_PRESETCTRL1_BLE_RST_Msk (0x01UL << SYSCON_PRESETCTRL1_BLE_RST_Pos) /*!< SYSCON PRESETCTRL1: BLE_RST Mask */
-#define SYSCON_PRESETCTRL1_MODEM_MASTER_RST_Pos 23 /*!< SYSCON PRESETCTRL1: MODEM_MASTER_RST Position */
-#define SYSCON_PRESETCTRL1_MODEM_MASTER_RST_Msk (0x01UL << SYSCON_PRESETCTRL1_MODEM_MASTER_RST_Pos)/*!< SYSCON PRESETCTRL1: MODEM_MASTER_RST Mask */
-#define SYSCON_PRESETCTRL1_AES_RST_Pos 24 /*!< SYSCON PRESETCTRL1: AES_RST Position */
-#define SYSCON_PRESETCTRL1_AES_RST_Msk (0x01UL << SYSCON_PRESETCTRL1_AES_RST_Pos) /*!< SYSCON PRESETCTRL1: AES_RST Mask */
-#define SYSCON_PRESETCTRL1_RFP_RST_Pos 25 /*!< SYSCON PRESETCTRL1: RFP_RST Position */
-#define SYSCON_PRESETCTRL1_RFP_RST_Msk (0x01UL << SYSCON_PRESETCTRL1_RFP_RST_Pos) /*!< SYSCON PRESETCTRL1: RFP_RST Mask */
-#define SYSCON_PRESETCTRL1_DMIC_RST_Pos 26 /*!< SYSCON PRESETCTRL1: DMIC_RST Position */
-#define SYSCON_PRESETCTRL1_DMIC_RST_Msk (0x01UL << SYSCON_PRESETCTRL1_DMIC_RST_Pos) /*!< SYSCON PRESETCTRL1: DMIC_RST Mask */
-#define SYSCON_PRESETCTRL1_HASH_RST_Pos 27 /*!< SYSCON PRESETCTRL1: HASH_RST Position */
-#define SYSCON_PRESETCTRL1_HASH_RST_Msk (0x01UL << SYSCON_PRESETCTRL1_HASH_RST_Pos) /*!< SYSCON PRESETCTRL1: HASH_RST Mask */
-#define SYSCON_PRESETCTRL1_TPR_RST_Pos 28 /*!< SYSCON PRESETCTRL1: TPR_RST Position */
-#define SYSCON_PRESETCTRL1_TPR_RST_Msk (0x01UL << SYSCON_PRESETCTRL1_TPR_RST_Pos) /*!< SYSCON PRESETCTRL1: TPR_RST Mask */
-
-/* --------------------------- u_syscon_PRESETCTRLSET0 -------------------------- */
-#define SYSCON_PRESETCTRLSET0_FLASH_RST_SET_Pos 8 /*!< SYSCON PRESETCTRLSET0: FLASH_RST_SET Position */
-#define SYSCON_PRESETCTRLSET0_FLASH_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET0_FLASH_RST_SET_Pos)/*!< SYSCON PRESETCTRLSET0: FLASH_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET0_SPIFI_RST_SET_Pos 10 /*!< SYSCON PRESETCTRLSET0: SPIFI_RST_SET Position */
-#define SYSCON_PRESETCTRLSET0_SPIFI_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET0_SPIFI_RST_SET_Pos)/*!< SYSCON PRESETCTRLSET0: SPIFI_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET0_MUX_RST_SET_Pos 11 /*!< SYSCON PRESETCTRLSET0: MUX_RST_SET Position */
-#define SYSCON_PRESETCTRLSET0_MUX_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET0_MUX_RST_SET_Pos) /*!< SYSCON PRESETCTRLSET0: MUX_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET0_BLE_TIMING_GEN_RST_SET_Pos 12 /*!< SYSCON PRESETCTRLSET0: BLE_TIMING_GEN_RST_SET Position */
-#define SYSCON_PRESETCTRLSET0_BLE_TIMING_GEN_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET0_BLE_TIMING_GEN_RST_SET_Pos)/*!< SYSCON PRESETCTRLSET0: BLE_TIMING_GEN_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET0_IOCON_RST_SET_Pos 13 /*!< SYSCON PRESETCTRLSET0: IOCON_RST_SET Position */
-#define SYSCON_PRESETCTRLSET0_IOCON_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET0_IOCON_RST_SET_Pos)/*!< SYSCON PRESETCTRLSET0: IOCON_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET0_GPIO_RST_SET_Pos 14 /*!< SYSCON PRESETCTRLSET0: GPIO_RST_SET Position */
-#define SYSCON_PRESETCTRLSET0_GPIO_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET0_GPIO_RST_SET_Pos) /*!< SYSCON PRESETCTRLSET0: GPIO_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET0_PINT_RST_SET_Pos 18 /*!< SYSCON PRESETCTRLSET0: PINT_RST_SET Position */
-#define SYSCON_PRESETCTRLSET0_PINT_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET0_PINT_RST_SET_Pos) /*!< SYSCON PRESETCTRLSET0: PINT_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET0_GINT_RST_SET_Pos 19 /*!< SYSCON PRESETCTRLSET0: GINT_RST_SET Position */
-#define SYSCON_PRESETCTRLSET0_GINT_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET0_GINT_RST_SET_Pos) /*!< SYSCON PRESETCTRLSET0: GINT_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET0_DMA_RST_SET_Pos 20 /*!< SYSCON PRESETCTRLSET0: DMA_RST_SET Position */
-#define SYSCON_PRESETCTRLSET0_DMA_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET0_DMA_RST_SET_Pos) /*!< SYSCON PRESETCTRLSET0: DMA_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET0_ISO7816_RST_SET_Pos 21 /*!< SYSCON PRESETCTRLSET0: ISO7816_RST_SET Position */
-#define SYSCON_PRESETCTRLSET0_ISO7816_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET0_ISO7816_RST_SET_Pos)/*!< SYSCON PRESETCTRLSET0: ISO7816_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET0_WWDT_RST_SET_Pos 22 /*!< SYSCON PRESETCTRLSET0: WWDT_RST_SET Position */
-#define SYSCON_PRESETCTRLSET0_WWDT_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET0_WWDT_RST_SET_Pos) /*!< SYSCON PRESETCTRLSET0: WWDT_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET0_RTC_RST_SET_Pos 23 /*!< SYSCON PRESETCTRLSET0: RTC_RST_SET Position */
-#define SYSCON_PRESETCTRLSET0_RTC_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET0_RTC_RST_SET_Pos) /*!< SYSCON PRESETCTRLSET0: RTC_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET0_ANA_INT_CTRL_RST_SET_Pos 24 /*!< SYSCON PRESETCTRLSET0: ANA_INT_CTRL_RST_SET Position */
-#define SYSCON_PRESETCTRLSET0_ANA_INT_CTRL_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET0_ANA_INT_CTRL_RST_SET_Pos)/*!< SYSCON PRESETCTRLSET0: ANA_INT_CTRL_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET0_WAKE_UP_TIMERS_RST_SET_Pos 25 /*!< SYSCON PRESETCTRLSET0: WAKE_UP_TIMERS_RST_SET Position */
-#define SYSCON_PRESETCTRLSET0_WAKE_UP_TIMERS_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET0_WAKE_UP_TIMERS_RST_SET_Pos)/*!< SYSCON PRESETCTRLSET0: WAKE_UP_TIMERS_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET0_MAILBOX_RST_SET_Pos 26 /*!< SYSCON PRESETCTRLSET0: MAILBOX_RST_SET Position */
-#define SYSCON_PRESETCTRLSET0_MAILBOX_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET0_MAILBOX_RST_SET_Pos)/*!< SYSCON PRESETCTRLSET0: MAILBOX_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET0_ADC_RST_SET_Pos 27 /*!< SYSCON PRESETCTRLSET0: ADC_RST_SET Position */
-#define SYSCON_PRESETCTRLSET0_ADC_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET0_ADC_RST_SET_Pos) /*!< SYSCON PRESETCTRLSET0: ADC_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET0_EFUSE_RST_SET_Pos 28 /*!< SYSCON PRESETCTRLSET0: EFUSE_RST_SET Position */
-#define SYSCON_PRESETCTRLSET0_EFUSE_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET0_EFUSE_RST_SET_Pos)/*!< SYSCON PRESETCTRLSET0: EFUSE_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET0_PVT_RST_SET_Pos 29 /*!< SYSCON PRESETCTRLSET0: PVT_RST_SET Position */
-#define SYSCON_PRESETCTRLSET0_PVT_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET0_PVT_RST_SET_Pos) /*!< SYSCON PRESETCTRLSET0: PVT_RST_SET Mask */
-
-/* --------------------------- u_syscon_PRESETCTRLSET1 -------------------------- */
-#define SYSCON_PRESETCTRLSET1_USART0_RST_SET_Pos 11 /*!< SYSCON PRESETCTRLSET1: USART0_RST_SET Position */
-#define SYSCON_PRESETCTRLSET1_USART0_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET1_USART0_RST_SET_Pos)/*!< SYSCON PRESETCTRLSET1: USART0_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET1_USART1_RST_SET_Pos 12 /*!< SYSCON PRESETCTRLSET1: USART1_RST_SET Position */
-#define SYSCON_PRESETCTRLSET1_USART1_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET1_USART1_RST_SET_Pos)/*!< SYSCON PRESETCTRLSET1: USART1_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET1_I2C0_RST_SET_Pos 13 /*!< SYSCON PRESETCTRLSET1: I2C0_RST_SET Position */
-#define SYSCON_PRESETCTRLSET1_I2C0_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET1_I2C0_RST_SET_Pos) /*!< SYSCON PRESETCTRLSET1: I2C0_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET1_I2C1_RST_SET_Pos 14 /*!< SYSCON PRESETCTRLSET1: I2C1_RST_SET Position */
-#define SYSCON_PRESETCTRLSET1_I2C1_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET1_I2C1_RST_SET_Pos) /*!< SYSCON PRESETCTRLSET1: I2C1_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET1_SPI0_RST_SET_Pos 15 /*!< SYSCON PRESETCTRLSET1: SPI0_RST_SET Position */
-#define SYSCON_PRESETCTRLSET1_SPI0_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET1_SPI0_RST_SET_Pos) /*!< SYSCON PRESETCTRLSET1: SPI0_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET1_SPI1_RST_SET_Pos 16 /*!< SYSCON PRESETCTRLSET1: SPI1_RST_SET Position */
-#define SYSCON_PRESETCTRLSET1_SPI1_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET1_SPI1_RST_SET_Pos) /*!< SYSCON PRESETCTRLSET1: SPI1_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET1_IR_RST_SET_Pos 17 /*!< SYSCON PRESETCTRLSET1: IR_RST_SET Position */
-#define SYSCON_PRESETCTRLSET1_IR_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET1_IR_RST_SET_Pos) /*!< SYSCON PRESETCTRLSET1: IR_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET1_PWM_RST_SET_Pos 18 /*!< SYSCON PRESETCTRLSET1: PWM_RST_SET Position */
-#define SYSCON_PRESETCTRLSET1_PWM_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET1_PWM_RST_SET_Pos) /*!< SYSCON PRESETCTRLSET1: PWM_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET1_RNG_RST_SET_Pos 19 /*!< SYSCON PRESETCTRLSET1: RNG_RST_SET Position */
-#define SYSCON_PRESETCTRLSET1_RNG_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET1_RNG_RST_SET_Pos) /*!< SYSCON PRESETCTRLSET1: RNG_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET1_I2C2_RST_SET_Pos 20 /*!< SYSCON PRESETCTRLSET1: I2C2_RST_SET Position */
-#define SYSCON_PRESETCTRLSET1_I2C2_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET1_I2C2_RST_SET_Pos) /*!< SYSCON PRESETCTRLSET1: I2C2_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET1_ZIGBEE_RST_SET_Pos 21 /*!< SYSCON PRESETCTRLSET1: ZIGBEE_RST_SET Position */
-#define SYSCON_PRESETCTRLSET1_ZIGBEE_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET1_ZIGBEE_RST_SET_Pos)/*!< SYSCON PRESETCTRLSET1: ZIGBEE_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET1_BLE_RST_SET_Pos 22 /*!< SYSCON PRESETCTRLSET1: BLE_RST_SET Position */
-#define SYSCON_PRESETCTRLSET1_BLE_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET1_BLE_RST_SET_Pos) /*!< SYSCON PRESETCTRLSET1: BLE_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET1_MODEM_MASTER_RST_SET_Pos 23 /*!< SYSCON PRESETCTRLSET1: MODEM_MASTER_RST_SET Position */
-#define SYSCON_PRESETCTRLSET1_MODEM_MASTER_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET1_MODEM_MASTER_RST_SET_Pos)/*!< SYSCON PRESETCTRLSET1: MODEM_MASTER_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET1_AES_RST_SET_Pos 24 /*!< SYSCON PRESETCTRLSET1: AES_RST_SET Position */
-#define SYSCON_PRESETCTRLSET1_AES_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET1_AES_RST_SET_Pos) /*!< SYSCON PRESETCTRLSET1: AES_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET1_RFP_RST_SET_Pos 25 /*!< SYSCON PRESETCTRLSET1: RFP_RST_SET Position */
-#define SYSCON_PRESETCTRLSET1_RFP_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET1_RFP_RST_SET_Pos) /*!< SYSCON PRESETCTRLSET1: RFP_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET1_DMIC_RST_SET_Pos 26 /*!< SYSCON PRESETCTRLSET1: DMIC_RST_SET Position */
-#define SYSCON_PRESETCTRLSET1_DMIC_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET1_DMIC_RST_SET_Pos) /*!< SYSCON PRESETCTRLSET1: DMIC_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET1_HASH_RST_SET_Pos 27 /*!< SYSCON PRESETCTRLSET1: HASH_RST_SET Position */
-#define SYSCON_PRESETCTRLSET1_HASH_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET1_HASH_RST_SET_Pos) /*!< SYSCON PRESETCTRLSET1: HASH_RST_SET Mask */
-#define SYSCON_PRESETCTRLSET1_TPR_RST_SET_Pos 28 /*!< SYSCON PRESETCTRLSET1: TPR_RST_SET Position */
-#define SYSCON_PRESETCTRLSET1_TPR_RST_SET_Msk (0x01UL << SYSCON_PRESETCTRLSET1_TPR_RST_SET_Pos) /*!< SYSCON PRESETCTRLSET1: TPR_RST_SET Mask */
-
-/* --------------------------- u_syscon_PRESETCTRLCLR0 -------------------------- */
-#define SYSCON_PRESETCTRLCLR0_FLASH_RST_CLR_Pos 8 /*!< SYSCON PRESETCTRLCLR0: FLASH_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR0_FLASH_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR0_FLASH_RST_CLR_Pos)/*!< SYSCON PRESETCTRLCLR0: FLASH_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR0_SPIFI_RST_CLR_Pos 10 /*!< SYSCON PRESETCTRLCLR0: SPIFI_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR0_SPIFI_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR0_SPIFI_RST_CLR_Pos)/*!< SYSCON PRESETCTRLCLR0: SPIFI_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR0_MUX_RST_CLR_Pos 11 /*!< SYSCON PRESETCTRLCLR0: MUX_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR0_MUX_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR0_MUX_RST_CLR_Pos) /*!< SYSCON PRESETCTRLCLR0: MUX_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR0_BLE_TIMING_GEN_RST_CLR_Pos 12 /*!< SYSCON PRESETCTRLCLR0: BLE_TIMING_GEN_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR0_BLE_TIMING_GEN_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR0_BLE_TIMING_GEN_RST_CLR_Pos)/*!< SYSCON PRESETCTRLCLR0: BLE_TIMING_GEN_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR0_IOCON_RST_CLR_Pos 13 /*!< SYSCON PRESETCTRLCLR0: IOCON_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR0_IOCON_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR0_IOCON_RST_CLR_Pos)/*!< SYSCON PRESETCTRLCLR0: IOCON_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR0_GPIO_RST_CLR_Pos 14 /*!< SYSCON PRESETCTRLCLR0: GPIO_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR0_GPIO_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR0_GPIO_RST_CLR_Pos) /*!< SYSCON PRESETCTRLCLR0: GPIO_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR0_PINT_RST_CLR_Pos 18 /*!< SYSCON PRESETCTRLCLR0: PINT_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR0_PINT_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR0_PINT_RST_CLR_Pos) /*!< SYSCON PRESETCTRLCLR0: PINT_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR0_GINT_RST_CLR_Pos 19 /*!< SYSCON PRESETCTRLCLR0: GINT_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR0_GINT_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR0_GINT_RST_CLR_Pos) /*!< SYSCON PRESETCTRLCLR0: GINT_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR0_DMA_RST_CLR_Pos 20 /*!< SYSCON PRESETCTRLCLR0: DMA_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR0_DMA_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR0_DMA_RST_CLR_Pos) /*!< SYSCON PRESETCTRLCLR0: DMA_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR0_ISO7816_RST_CLR_Pos 21 /*!< SYSCON PRESETCTRLCLR0: ISO7816_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR0_ISO7816_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR0_ISO7816_RST_CLR_Pos)/*!< SYSCON PRESETCTRLCLR0: ISO7816_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR0_WWDT_RST_CLR_Pos 22 /*!< SYSCON PRESETCTRLCLR0: WWDT_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR0_WWDT_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR0_WWDT_RST_CLR_Pos) /*!< SYSCON PRESETCTRLCLR0: WWDT_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR0_RTC_RST_CLR_Pos 23 /*!< SYSCON PRESETCTRLCLR0: RTC_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR0_RTC_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR0_RTC_RST_CLR_Pos) /*!< SYSCON PRESETCTRLCLR0: RTC_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR0_ANA_INT_CTRL_RST_CLR_Pos 24 /*!< SYSCON PRESETCTRLCLR0: ANA_INT_CTRL_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR0_ANA_INT_CTRL_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR0_ANA_INT_CTRL_RST_CLR_Pos)/*!< SYSCON PRESETCTRLCLR0: ANA_INT_CTRL_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR0_WAKE_UP_TIMERS_RST_CLR_Pos 25 /*!< SYSCON PRESETCTRLCLR0: WAKE_UP_TIMERS_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR0_WAKE_UP_TIMERS_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR0_WAKE_UP_TIMERS_RST_CLR_Pos)/*!< SYSCON PRESETCTRLCLR0: WAKE_UP_TIMERS_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR0_MAILBOX_RST_CLR_Pos 26 /*!< SYSCON PRESETCTRLCLR0: MAILBOX_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR0_MAILBOX_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR0_MAILBOX_RST_CLR_Pos)/*!< SYSCON PRESETCTRLCLR0: MAILBOX_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR0_ADC_RST_CLR_Pos 27 /*!< SYSCON PRESETCTRLCLR0: ADC_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR0_ADC_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR0_ADC_RST_CLR_Pos) /*!< SYSCON PRESETCTRLCLR0: ADC_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR0_EFUSE_RST_CLR_Pos 28 /*!< SYSCON PRESETCTRLCLR0: EFUSE_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR0_EFUSE_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR0_EFUSE_RST_CLR_Pos)/*!< SYSCON PRESETCTRLCLR0: EFUSE_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR0_PVT_RST_CLR_Pos 29 /*!< SYSCON PRESETCTRLCLR0: PVT_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR0_PVT_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR0_PVT_RST_CLR_Pos) /*!< SYSCON PRESETCTRLCLR0: PVT_RST_CLR Mask */
-
-/* --------------------------- u_syscon_PRESETCTRLCLR1 -------------------------- */
-#define SYSCON_PRESETCTRLCLR1_USART0_RST_CLR_Pos 11 /*!< SYSCON PRESETCTRLCLR1: USART0_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR1_USART0_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR1_USART0_RST_CLR_Pos)/*!< SYSCON PRESETCTRLCLR1: USART0_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR1_USART1_RST_CLR_Pos 12 /*!< SYSCON PRESETCTRLCLR1: USART1_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR1_USART1_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR1_USART1_RST_CLR_Pos)/*!< SYSCON PRESETCTRLCLR1: USART1_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR1_I2C0_RST_CLR_Pos 13 /*!< SYSCON PRESETCTRLCLR1: I2C0_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR1_I2C0_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR1_I2C0_RST_CLR_Pos) /*!< SYSCON PRESETCTRLCLR1: I2C0_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR1_I2C1_RST_CLR_Pos 14 /*!< SYSCON PRESETCTRLCLR1: I2C1_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR1_I2C1_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR1_I2C1_RST_CLR_Pos) /*!< SYSCON PRESETCTRLCLR1: I2C1_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR1_SPI0_RST_CLR_Pos 15 /*!< SYSCON PRESETCTRLCLR1: SPI0_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR1_SPI0_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR1_SPI0_RST_CLR_Pos) /*!< SYSCON PRESETCTRLCLR1: SPI0_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR1_SPI1_RST_CLR_Pos 16 /*!< SYSCON PRESETCTRLCLR1: SPI1_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR1_SPI1_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR1_SPI1_RST_CLR_Pos) /*!< SYSCON PRESETCTRLCLR1: SPI1_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR1_IR_RST_CLR_Pos 17 /*!< SYSCON PRESETCTRLCLR1: IR_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR1_IR_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR1_IR_RST_CLR_Pos) /*!< SYSCON PRESETCTRLCLR1: IR_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR1_PWM_RST_CLR_Pos 18 /*!< SYSCON PRESETCTRLCLR1: PWM_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR1_PWM_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR1_PWM_RST_CLR_Pos) /*!< SYSCON PRESETCTRLCLR1: PWM_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR1_RNG_RST_CLR_Pos 19 /*!< SYSCON PRESETCTRLCLR1: RNG_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR1_RNG_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR1_RNG_RST_CLR_Pos) /*!< SYSCON PRESETCTRLCLR1: RNG_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR1_I2C2_RST_CLR_Pos 20 /*!< SYSCON PRESETCTRLCLR1: I2C2_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR1_I2C2_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR1_I2C2_RST_CLR_Pos) /*!< SYSCON PRESETCTRLCLR1: I2C2_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR1_ZIGBEE_RST_CLR_Pos 21 /*!< SYSCON PRESETCTRLCLR1: ZIGBEE_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR1_ZIGBEE_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR1_ZIGBEE_RST_CLR_Pos)/*!< SYSCON PRESETCTRLCLR1: ZIGBEE_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR1_BLE_RST_CLR_Pos 22 /*!< SYSCON PRESETCTRLCLR1: BLE_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR1_BLE_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR1_BLE_RST_CLR_Pos) /*!< SYSCON PRESETCTRLCLR1: BLE_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR1_MODEM_MASTER_RST_CLR_Pos 23 /*!< SYSCON PRESETCTRLCLR1: MODEM_MASTER_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR1_MODEM_MASTER_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR1_MODEM_MASTER_RST_CLR_Pos)/*!< SYSCON PRESETCTRLCLR1: MODEM_MASTER_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR1_AES_RST_CLR_Pos 24 /*!< SYSCON PRESETCTRLCLR1: AES_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR1_AES_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR1_AES_RST_CLR_Pos) /*!< SYSCON PRESETCTRLCLR1: AES_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR1_RFP_RST_CLR_Pos 25 /*!< SYSCON PRESETCTRLCLR1: RFP_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR1_RFP_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR1_RFP_RST_CLR_Pos) /*!< SYSCON PRESETCTRLCLR1: RFP_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR1_DMIC_RST_CLR_Pos 26 /*!< SYSCON PRESETCTRLCLR1: DMIC_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR1_DMIC_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR1_DMIC_RST_CLR_Pos) /*!< SYSCON PRESETCTRLCLR1: DMIC_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR1_HASH_RST_CLR_Pos 27 /*!< SYSCON PRESETCTRLCLR1: HASH_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR1_HASH_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR1_HASH_RST_CLR_Pos) /*!< SYSCON PRESETCTRLCLR1: HASH_RST_CLR Mask */
-#define SYSCON_PRESETCTRLCLR1_TPR_RST_CLR_Pos 28 /*!< SYSCON PRESETCTRLCLR1: TPR_RST_CLR Position */
-#define SYSCON_PRESETCTRLCLR1_TPR_RST_CLR_Msk (0x01UL << SYSCON_PRESETCTRLCLR1_TPR_RST_CLR_Pos) /*!< SYSCON PRESETCTRLCLR1: TPR_RST_CLR Mask */
-
-/* ---------------------------- u_syscon_AHBCLKCTRL0 ---------------------------- */
-#define SYSCON_AHBCLKCTRL0_ROM_Pos 1 /*!< SYSCON AHBCLKCTRL0: ROM Position */
-#define SYSCON_AHBCLKCTRL0_ROM_Msk (0x01UL << SYSCON_AHBCLKCTRL0_ROM_Pos) /*!< SYSCON AHBCLKCTRL0: ROM Mask */
-#define SYSCON_AHBCLKCTRL0_SRAM_CTRL0_Pos 3 /*!< SYSCON AHBCLKCTRL0: SRAM_CTRL0 Position */
-#define SYSCON_AHBCLKCTRL0_SRAM_CTRL0_Msk (0x01UL << SYSCON_AHBCLKCTRL0_SRAM_CTRL0_Pos) /*!< SYSCON AHBCLKCTRL0: SRAM_CTRL0 Mask */
-#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_Pos 4 /*!< SYSCON AHBCLKCTRL0: SRAM_CTRL1 Position */
-#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_Msk (0x01UL << SYSCON_AHBCLKCTRL0_SRAM_CTRL1_Pos) /*!< SYSCON AHBCLKCTRL0: SRAM_CTRL1 Mask */
-#define SYSCON_AHBCLKCTRL0_FLASH_Pos 8 /*!< SYSCON AHBCLKCTRL0: FLASH Position */
-#define SYSCON_AHBCLKCTRL0_FLASH_Msk (0x01UL << SYSCON_AHBCLKCTRL0_FLASH_Pos) /*!< SYSCON AHBCLKCTRL0: FLASH Mask */
-#define SYSCON_AHBCLKCTRL0_SPIFI_Pos 10 /*!< SYSCON AHBCLKCTRL0: SPIFI Position */
-#define SYSCON_AHBCLKCTRL0_SPIFI_Msk (0x01UL << SYSCON_AHBCLKCTRL0_SPIFI_Pos) /*!< SYSCON AHBCLKCTRL0: SPIFI Mask */
-#define SYSCON_AHBCLKCTRL0_MUX_Pos 11 /*!< SYSCON AHBCLKCTRL0: MUX Position */
-#define SYSCON_AHBCLKCTRL0_MUX_Msk (0x01UL << SYSCON_AHBCLKCTRL0_MUX_Pos) /*!< SYSCON AHBCLKCTRL0: MUX Mask */
-#define SYSCON_AHBCLKCTRL0_IOCON_Pos 13 /*!< SYSCON AHBCLKCTRL0: IOCON Position */
-#define SYSCON_AHBCLKCTRL0_IOCON_Msk (0x01UL << SYSCON_AHBCLKCTRL0_IOCON_Pos) /*!< SYSCON AHBCLKCTRL0: IOCON Mask */
-#define SYSCON_AHBCLKCTRL0_GPIO_Pos 14 /*!< SYSCON AHBCLKCTRL0: GPIO Position */
-#define SYSCON_AHBCLKCTRL0_GPIO_Msk (0x01UL << SYSCON_AHBCLKCTRL0_GPIO_Pos) /*!< SYSCON AHBCLKCTRL0: GPIO Mask */
-#define SYSCON_AHBCLKCTRL0_PINT_Pos 18 /*!< SYSCON AHBCLKCTRL0: PINT Position */
-#define SYSCON_AHBCLKCTRL0_PINT_Msk (0x01UL << SYSCON_AHBCLKCTRL0_PINT_Pos) /*!< SYSCON AHBCLKCTRL0: PINT Mask */
-#define SYSCON_AHBCLKCTRL0_GINT_Pos 19 /*!< SYSCON AHBCLKCTRL0: GINT Position */
-#define SYSCON_AHBCLKCTRL0_GINT_Msk (0x01UL << SYSCON_AHBCLKCTRL0_GINT_Pos) /*!< SYSCON AHBCLKCTRL0: GINT Mask */
-#define SYSCON_AHBCLKCTRL0_DMA_Pos 20 /*!< SYSCON AHBCLKCTRL0: DMA Position */
-#define SYSCON_AHBCLKCTRL0_DMA_Msk (0x01UL << SYSCON_AHBCLKCTRL0_DMA_Pos) /*!< SYSCON AHBCLKCTRL0: DMA Mask */
-#define SYSCON_AHBCLKCTRL0_ISO7816_Pos 21 /*!< SYSCON AHBCLKCTRL0: ISO7816 Position */
-#define SYSCON_AHBCLKCTRL0_ISO7816_Msk (0x01UL << SYSCON_AHBCLKCTRL0_ISO7816_Pos) /*!< SYSCON AHBCLKCTRL0: ISO7816 Mask */
-#define SYSCON_AHBCLKCTRL0_WWDT_Pos 22 /*!< SYSCON AHBCLKCTRL0: WWDT Position */
-#define SYSCON_AHBCLKCTRL0_WWDT_Msk (0x01UL << SYSCON_AHBCLKCTRL0_WWDT_Pos) /*!< SYSCON AHBCLKCTRL0: WWDT Mask */
-#define SYSCON_AHBCLKCTRL0_RTC_Pos 23 /*!< SYSCON AHBCLKCTRL0: RTC Position */
-#define SYSCON_AHBCLKCTRL0_RTC_Msk (0x01UL << SYSCON_AHBCLKCTRL0_RTC_Pos) /*!< SYSCON AHBCLKCTRL0: RTC Mask */
-#define SYSCON_AHBCLKCTRL0_ANA_INT_CTRL_Pos 24 /*!< SYSCON AHBCLKCTRL0: ANA_INT_CTRL Position */
-#define SYSCON_AHBCLKCTRL0_ANA_INT_CTRL_Msk (0x01UL << SYSCON_AHBCLKCTRL0_ANA_INT_CTRL_Pos) /*!< SYSCON AHBCLKCTRL0: ANA_INT_CTRL Mask */
-#define SYSCON_AHBCLKCTRL0_WAKE_UP_TIMERS_Pos 25 /*!< SYSCON AHBCLKCTRL0: WAKE_UP_TIMERS Position */
-#define SYSCON_AHBCLKCTRL0_WAKE_UP_TIMERS_Msk (0x01UL << SYSCON_AHBCLKCTRL0_WAKE_UP_TIMERS_Pos) /*!< SYSCON AHBCLKCTRL0: WAKE_UP_TIMERS Mask */
-#define SYSCON_AHBCLKCTRL0_MAILBOX_Pos 26 /*!< SYSCON AHBCLKCTRL0: MAILBOX Position */
-#define SYSCON_AHBCLKCTRL0_MAILBOX_Msk (0x01UL << SYSCON_AHBCLKCTRL0_MAILBOX_Pos) /*!< SYSCON AHBCLKCTRL0: MAILBOX Mask */
-#define SYSCON_AHBCLKCTRL0_ADC_Pos 27 /*!< SYSCON AHBCLKCTRL0: ADC Position */
-#define SYSCON_AHBCLKCTRL0_ADC_Msk (0x01UL << SYSCON_AHBCLKCTRL0_ADC_Pos) /*!< SYSCON AHBCLKCTRL0: ADC Mask */
-#define SYSCON_AHBCLKCTRL0_EFUSE_Pos 28 /*!< SYSCON AHBCLKCTRL0: EFUSE Position */
-#define SYSCON_AHBCLKCTRL0_EFUSE_Msk (0x01UL << SYSCON_AHBCLKCTRL0_EFUSE_Pos) /*!< SYSCON AHBCLKCTRL0: EFUSE Mask */
-#define SYSCON_AHBCLKCTRL0_PVT_Pos 29 /*!< SYSCON AHBCLKCTRL0: PVT Position */
-#define SYSCON_AHBCLKCTRL0_PVT_Msk (0x01UL << SYSCON_AHBCLKCTRL0_PVT_Pos) /*!< SYSCON AHBCLKCTRL0: PVT Mask */
-
-/* ---------------------------- u_syscon_AHBCLKCTRL1 ---------------------------- */
-#define SYSCON_AHBCLKCTRL1_USART0_Pos 11 /*!< SYSCON AHBCLKCTRL1: USART0 Position */
-#define SYSCON_AHBCLKCTRL1_USART0_Msk (0x01UL << SYSCON_AHBCLKCTRL1_USART0_Pos) /*!< SYSCON AHBCLKCTRL1: USART0 Mask */
-#define SYSCON_AHBCLKCTRL1_USART1_Pos 12 /*!< SYSCON AHBCLKCTRL1: USART1 Position */
-#define SYSCON_AHBCLKCTRL1_USART1_Msk (0x01UL << SYSCON_AHBCLKCTRL1_USART1_Pos) /*!< SYSCON AHBCLKCTRL1: USART1 Mask */
-#define SYSCON_AHBCLKCTRL1_I2C0_Pos 13 /*!< SYSCON AHBCLKCTRL1: I2C0 Position */
-#define SYSCON_AHBCLKCTRL1_I2C0_Msk (0x01UL << SYSCON_AHBCLKCTRL1_I2C0_Pos) /*!< SYSCON AHBCLKCTRL1: I2C0 Mask */
-#define SYSCON_AHBCLKCTRL1_I2C1_Pos 14 /*!< SYSCON AHBCLKCTRL1: I2C1 Position */
-#define SYSCON_AHBCLKCTRL1_I2C1_Msk (0x01UL << SYSCON_AHBCLKCTRL1_I2C1_Pos) /*!< SYSCON AHBCLKCTRL1: I2C1 Mask */
-#define SYSCON_AHBCLKCTRL1_SPI0_Pos 15 /*!< SYSCON AHBCLKCTRL1: SPI0 Position */
-#define SYSCON_AHBCLKCTRL1_SPI0_Msk (0x01UL << SYSCON_AHBCLKCTRL1_SPI0_Pos) /*!< SYSCON AHBCLKCTRL1: SPI0 Mask */
-#define SYSCON_AHBCLKCTRL1_SPI1_Pos 16 /*!< SYSCON AHBCLKCTRL1: SPI1 Position */
-#define SYSCON_AHBCLKCTRL1_SPI1_Msk (0x01UL << SYSCON_AHBCLKCTRL1_SPI1_Pos) /*!< SYSCON AHBCLKCTRL1: SPI1 Mask */
-#define SYSCON_AHBCLKCTRL1_IR_Pos 17 /*!< SYSCON AHBCLKCTRL1: IR Position */
-#define SYSCON_AHBCLKCTRL1_IR_Msk (0x01UL << SYSCON_AHBCLKCTRL1_IR_Pos) /*!< SYSCON AHBCLKCTRL1: IR Mask */
-#define SYSCON_AHBCLKCTRL1_PWM_Pos 18 /*!< SYSCON AHBCLKCTRL1: PWM Position */
-#define SYSCON_AHBCLKCTRL1_PWM_Msk (0x01UL << SYSCON_AHBCLKCTRL1_PWM_Pos) /*!< SYSCON AHBCLKCTRL1: PWM Mask */
-#define SYSCON_AHBCLKCTRL1_RNG_Pos 19 /*!< SYSCON AHBCLKCTRL1: RNG Position */
-#define SYSCON_AHBCLKCTRL1_RNG_Msk (0x01UL << SYSCON_AHBCLKCTRL1_RNG_Pos) /*!< SYSCON AHBCLKCTRL1: RNG Mask */
-#define SYSCON_AHBCLKCTRL1_I2C2_Pos 20 /*!< SYSCON AHBCLKCTRL1: I2C2 Position */
-#define SYSCON_AHBCLKCTRL1_I2C2_Msk (0x01UL << SYSCON_AHBCLKCTRL1_I2C2_Pos) /*!< SYSCON AHBCLKCTRL1: I2C2 Mask */
-#define SYSCON_AHBCLKCTRL1_ZIGBEE_Pos 21 /*!< SYSCON AHBCLKCTRL1: ZIGBEE Position */
-#define SYSCON_AHBCLKCTRL1_ZIGBEE_Msk (0x01UL << SYSCON_AHBCLKCTRL1_ZIGBEE_Pos) /*!< SYSCON AHBCLKCTRL1: ZIGBEE Mask */
-#define SYSCON_AHBCLKCTRL1_BLE_Pos 22 /*!< SYSCON AHBCLKCTRL1: BLE Position */
-#define SYSCON_AHBCLKCTRL1_BLE_Msk (0x01UL << SYSCON_AHBCLKCTRL1_BLE_Pos) /*!< SYSCON AHBCLKCTRL1: BLE Mask */
-#define SYSCON_AHBCLKCTRL1_MODEM_MASTER_Pos 23 /*!< SYSCON AHBCLKCTRL1: MODEM_MASTER Position */
-#define SYSCON_AHBCLKCTRL1_MODEM_MASTER_Msk (0x01UL << SYSCON_AHBCLKCTRL1_MODEM_MASTER_Pos) /*!< SYSCON AHBCLKCTRL1: MODEM_MASTER Mask */
-#define SYSCON_AHBCLKCTRL1_AES_Pos 24 /*!< SYSCON AHBCLKCTRL1: AES Position */
-#define SYSCON_AHBCLKCTRL1_AES_Msk (0x01UL << SYSCON_AHBCLKCTRL1_AES_Pos) /*!< SYSCON AHBCLKCTRL1: AES Mask */
-#define SYSCON_AHBCLKCTRL1_RFP_Pos 25 /*!< SYSCON AHBCLKCTRL1: RFP Position */
-#define SYSCON_AHBCLKCTRL1_RFP_Msk (0x01UL << SYSCON_AHBCLKCTRL1_RFP_Pos) /*!< SYSCON AHBCLKCTRL1: RFP Mask */
-#define SYSCON_AHBCLKCTRL1_DMIC_Pos 26 /*!< SYSCON AHBCLKCTRL1: DMIC Position */
-#define SYSCON_AHBCLKCTRL1_DMIC_Msk (0x01UL << SYSCON_AHBCLKCTRL1_DMIC_Pos) /*!< SYSCON AHBCLKCTRL1: DMIC Mask */
-#define SYSCON_AHBCLKCTRL1_HASH_Pos 27 /*!< SYSCON AHBCLKCTRL1: HASH Position */
-#define SYSCON_AHBCLKCTRL1_HASH_Msk (0x01UL << SYSCON_AHBCLKCTRL1_HASH_Pos) /*!< SYSCON AHBCLKCTRL1: HASH Mask */
-#define SYSCON_AHBCLKCTRL1_TPR_Pos 28 /*!< SYSCON AHBCLKCTRL1: TPR Position */
-#define SYSCON_AHBCLKCTRL1_TPR_Msk (0x01UL << SYSCON_AHBCLKCTRL1_TPR_Pos) /*!< SYSCON AHBCLKCTRL1: TPR Mask */
-
-/* --------------------------- u_syscon_AHBCLKCTRLSET0 -------------------------- */
-#define SYSCON_AHBCLKCTRLSET0_ROM_CLK_SET_Pos 1 /*!< SYSCON AHBCLKCTRLSET0: ROM_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET0_ROM_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET0_ROM_CLK_SET_Pos) /*!< SYSCON AHBCLKCTRLSET0: ROM_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET0_SRAM_CTRL0_CLK_SET_Pos 3 /*!< SYSCON AHBCLKCTRLSET0: SRAM_CTRL0_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET0_SRAM_CTRL0_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET0_SRAM_CTRL0_CLK_SET_Pos)/*!< SYSCON AHBCLKCTRLSET0: SRAM_CTRL0_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET0_SRAM_CTRL1_CLK_SET_Pos 4 /*!< SYSCON AHBCLKCTRLSET0: SRAM_CTRL1_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET0_SRAM_CTRL1_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET0_SRAM_CTRL1_CLK_SET_Pos)/*!< SYSCON AHBCLKCTRLSET0: SRAM_CTRL1_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET0_FLASH_CLK_SET_Pos 8 /*!< SYSCON AHBCLKCTRLSET0: FLASH_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET0_FLASH_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET0_FLASH_CLK_SET_Pos)/*!< SYSCON AHBCLKCTRLSET0: FLASH_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET0_SPIFI_CLK_SET_Pos 10 /*!< SYSCON AHBCLKCTRLSET0: SPIFI_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET0_SPIFI_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET0_SPIFI_CLK_SET_Pos)/*!< SYSCON AHBCLKCTRLSET0: SPIFI_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET0_MUX_CLK_SET_Pos 11 /*!< SYSCON AHBCLKCTRLSET0: MUX_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET0_MUX_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET0_MUX_CLK_SET_Pos) /*!< SYSCON AHBCLKCTRLSET0: MUX_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET0_IOCON_CLK_SET_Pos 13 /*!< SYSCON AHBCLKCTRLSET0: IOCON_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET0_IOCON_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET0_IOCON_CLK_SET_Pos)/*!< SYSCON AHBCLKCTRLSET0: IOCON_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET0_GPIO_CLK_SET_Pos 14 /*!< SYSCON AHBCLKCTRLSET0: GPIO_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET0_GPIO_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET0_GPIO_CLK_SET_Pos) /*!< SYSCON AHBCLKCTRLSET0: GPIO_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET0_PINT_CLK_SET_Pos 18 /*!< SYSCON AHBCLKCTRLSET0: PINT_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET0_PINT_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET0_PINT_CLK_SET_Pos) /*!< SYSCON AHBCLKCTRLSET0: PINT_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET0_GINT_CLK_SET_Pos 19 /*!< SYSCON AHBCLKCTRLSET0: GINT_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET0_GINT_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET0_GINT_CLK_SET_Pos) /*!< SYSCON AHBCLKCTRLSET0: GINT_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET0_DMA_CLK_SET_Pos 20 /*!< SYSCON AHBCLKCTRLSET0: DMA_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET0_DMA_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET0_DMA_CLK_SET_Pos) /*!< SYSCON AHBCLKCTRLSET0: DMA_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET0_ISO7816_CLK_SET_Pos 21 /*!< SYSCON AHBCLKCTRLSET0: ISO7816_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET0_ISO7816_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET0_ISO7816_CLK_SET_Pos)/*!< SYSCON AHBCLKCTRLSET0: ISO7816_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET0_WWDT_CLK_SET_Pos 22 /*!< SYSCON AHBCLKCTRLSET0: WWDT_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET0_WWDT_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET0_WWDT_CLK_SET_Pos) /*!< SYSCON AHBCLKCTRLSET0: WWDT_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET0_RTC_CLK_SET_Pos 23 /*!< SYSCON AHBCLKCTRLSET0: RTC_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET0_RTC_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET0_RTC_CLK_SET_Pos) /*!< SYSCON AHBCLKCTRLSET0: RTC_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET0_ANA_INT_CTRL_CLK_SET_Pos 24 /*!< SYSCON AHBCLKCTRLSET0: ANA_INT_CTRL_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET0_ANA_INT_CTRL_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET0_ANA_INT_CTRL_CLK_SET_Pos)/*!< SYSCON AHBCLKCTRLSET0: ANA_INT_CTRL_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET0_WAKE_UP_TIMERS_CLK_SET_Pos 25 /*!< SYSCON AHBCLKCTRLSET0: WAKE_UP_TIMERS_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET0_WAKE_UP_TIMERS_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET0_WAKE_UP_TIMERS_CLK_SET_Pos)/*!< SYSCON AHBCLKCTRLSET0: WAKE_UP_TIMERS_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET0_MAILBOX_CLK_SET_Pos 26 /*!< SYSCON AHBCLKCTRLSET0: MAILBOX_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET0_MAILBOX_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET0_MAILBOX_CLK_SET_Pos)/*!< SYSCON AHBCLKCTRLSET0: MAILBOX_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET0_ADC_CLK_SET_Pos 27 /*!< SYSCON AHBCLKCTRLSET0: ADC_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET0_ADC_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET0_ADC_CLK_SET_Pos) /*!< SYSCON AHBCLKCTRLSET0: ADC_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET0_EFUSE_CLK_SET_Pos 28 /*!< SYSCON AHBCLKCTRLSET0: EFUSE_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET0_EFUSE_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET0_EFUSE_CLK_SET_Pos)/*!< SYSCON AHBCLKCTRLSET0: EFUSE_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET0_PVT_CLK_SET_Pos 29 /*!< SYSCON AHBCLKCTRLSET0: PVT_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET0_PVT_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET0_PVT_CLK_SET_Pos) /*!< SYSCON AHBCLKCTRLSET0: PVT_CLK_SET Mask */
-
-/* --------------------------- u_syscon_AHBCLKCTRLSET1 -------------------------- */
-#define SYSCON_AHBCLKCTRLSET1_USART0_CLK_SET_Pos 11 /*!< SYSCON AHBCLKCTRLSET1: USART0_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET1_USART0_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET1_USART0_CLK_SET_Pos)/*!< SYSCON AHBCLKCTRLSET1: USART0_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET1_USART1_CLK_SET_Pos 12 /*!< SYSCON AHBCLKCTRLSET1: USART1_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET1_USART1_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET1_USART1_CLK_SET_Pos)/*!< SYSCON AHBCLKCTRLSET1: USART1_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET1_I2C0_CLK_SET_Pos 13 /*!< SYSCON AHBCLKCTRLSET1: I2C0_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET1_I2C0_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET1_I2C0_CLK_SET_Pos) /*!< SYSCON AHBCLKCTRLSET1: I2C0_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET1_I2C1_CLK_SET_Pos 14 /*!< SYSCON AHBCLKCTRLSET1: I2C1_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET1_I2C1_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET1_I2C1_CLK_SET_Pos) /*!< SYSCON AHBCLKCTRLSET1: I2C1_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET1_SPI0_CLK_SET_Pos 15 /*!< SYSCON AHBCLKCTRLSET1: SPI0_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET1_SPI0_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET1_SPI0_CLK_SET_Pos) /*!< SYSCON AHBCLKCTRLSET1: SPI0_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET1_SPI1_CLK_SET_Pos 16 /*!< SYSCON AHBCLKCTRLSET1: SPI1_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET1_SPI1_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET1_SPI1_CLK_SET_Pos) /*!< SYSCON AHBCLKCTRLSET1: SPI1_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET1_IR_CLK_SET_Pos 17 /*!< SYSCON AHBCLKCTRLSET1: IR_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET1_IR_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET1_IR_CLK_SET_Pos) /*!< SYSCON AHBCLKCTRLSET1: IR_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET1_PWM_CLK_SET_Pos 18 /*!< SYSCON AHBCLKCTRLSET1: PWM_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET1_PWM_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET1_PWM_CLK_SET_Pos) /*!< SYSCON AHBCLKCTRLSET1: PWM_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET1_RNG_CLK_SET_Pos 19 /*!< SYSCON AHBCLKCTRLSET1: RNG_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET1_RNG_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET1_RNG_CLK_SET_Pos) /*!< SYSCON AHBCLKCTRLSET1: RNG_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET1_I2C2_CLK_SET_Pos 20 /*!< SYSCON AHBCLKCTRLSET1: I2C2_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET1_I2C2_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET1_I2C2_CLK_SET_Pos) /*!< SYSCON AHBCLKCTRLSET1: I2C2_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET1_ZIGBEE_CLK_SET_Pos 21 /*!< SYSCON AHBCLKCTRLSET1: ZIGBEE_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET1_ZIGBEE_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET1_ZIGBEE_CLK_SET_Pos)/*!< SYSCON AHBCLKCTRLSET1: ZIGBEE_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET1_BLE_CLK_SET_Pos 22 /*!< SYSCON AHBCLKCTRLSET1: BLE_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET1_BLE_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET1_BLE_CLK_SET_Pos) /*!< SYSCON AHBCLKCTRLSET1: BLE_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET1_MODEM_MASTER_CLK_SET_Pos 23 /*!< SYSCON AHBCLKCTRLSET1: MODEM_MASTER_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET1_MODEM_MASTER_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET1_MODEM_MASTER_CLK_SET_Pos)/*!< SYSCON AHBCLKCTRLSET1: MODEM_MASTER_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET1_AES_CLK_SET_Pos 24 /*!< SYSCON AHBCLKCTRLSET1: AES_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET1_AES_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET1_AES_CLK_SET_Pos) /*!< SYSCON AHBCLKCTRLSET1: AES_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET1_RFP_CLK_SET_Pos 25 /*!< SYSCON AHBCLKCTRLSET1: RFP_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET1_RFP_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET1_RFP_CLK_SET_Pos) /*!< SYSCON AHBCLKCTRLSET1: RFP_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET1_DMIC_CLK_SET_Pos 26 /*!< SYSCON AHBCLKCTRLSET1: DMIC_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET1_DMIC_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET1_DMIC_CLK_SET_Pos) /*!< SYSCON AHBCLKCTRLSET1: DMIC_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET1_HASH_CLK_SET_Pos 27 /*!< SYSCON AHBCLKCTRLSET1: HASH_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET1_HASH_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET1_HASH_CLK_SET_Pos) /*!< SYSCON AHBCLKCTRLSET1: HASH_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLSET1_TPR_CLK_SET_Pos 28 /*!< SYSCON AHBCLKCTRLSET1: TPR_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLSET1_TPR_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLSET1_TPR_CLK_SET_Pos) /*!< SYSCON AHBCLKCTRLSET1: TPR_CLK_SET Mask */
-
-/* --------------------------- u_syscon_AHBCLKCTRLCLR0 -------------------------- */
-#define SYSCON_AHBCLKCTRLCLR0_ROM_CLK_CLR_Pos 1 /*!< SYSCON AHBCLKCTRLCLR0: ROM_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR0_ROM_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR0_ROM_CLK_CLR_Pos) /*!< SYSCON AHBCLKCTRLCLR0: ROM_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR0_SRAM_CTRL0_CLK_CLR_Pos 3 /*!< SYSCON AHBCLKCTRLCLR0: SRAM_CTRL0_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR0_SRAM_CTRL0_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR0_SRAM_CTRL0_CLK_CLR_Pos)/*!< SYSCON AHBCLKCTRLCLR0: SRAM_CTRL0_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR0_SRAM_CTRL1_CLK_CLR_Pos 4 /*!< SYSCON AHBCLKCTRLCLR0: SRAM_CTRL1_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR0_SRAM_CTRL1_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR0_SRAM_CTRL1_CLK_CLR_Pos)/*!< SYSCON AHBCLKCTRLCLR0: SRAM_CTRL1_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR0_FLASH_CLK_CLR_Pos 8 /*!< SYSCON AHBCLKCTRLCLR0: FLASH_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR0_FLASH_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR0_FLASH_CLK_CLR_Pos)/*!< SYSCON AHBCLKCTRLCLR0: FLASH_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR0_SPIFI_CLK_CLR_Pos 10 /*!< SYSCON AHBCLKCTRLCLR0: SPIFI_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR0_SPIFI_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR0_SPIFI_CLK_CLR_Pos)/*!< SYSCON AHBCLKCTRLCLR0: SPIFI_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR0_MUX_CLK_CLR_Pos 11 /*!< SYSCON AHBCLKCTRLCLR0: MUX_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR0_MUX_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR0_MUX_CLK_CLR_Pos) /*!< SYSCON AHBCLKCTRLCLR0: MUX_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR0_IOCON_CLK_CLR_Pos 13 /*!< SYSCON AHBCLKCTRLCLR0: IOCON_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR0_IOCON_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR0_IOCON_CLK_CLR_Pos)/*!< SYSCON AHBCLKCTRLCLR0: IOCON_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR0_GPIO_CLK_CLR_Pos 14 /*!< SYSCON AHBCLKCTRLCLR0: GPIO_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR0_GPIO_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR0_GPIO_CLK_CLR_Pos) /*!< SYSCON AHBCLKCTRLCLR0: GPIO_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR0_PINT_CLK_CLR_Pos 18 /*!< SYSCON AHBCLKCTRLCLR0: PINT_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR0_PINT_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR0_PINT_CLK_CLR_Pos) /*!< SYSCON AHBCLKCTRLCLR0: PINT_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR0_GINT_CLK_CLR_Pos 19 /*!< SYSCON AHBCLKCTRLCLR0: GINT_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR0_GINT_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR0_GINT_CLK_CLR_Pos) /*!< SYSCON AHBCLKCTRLCLR0: GINT_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR0_DMA_CLK_CLR_Pos 20 /*!< SYSCON AHBCLKCTRLCLR0: DMA_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR0_DMA_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR0_DMA_CLK_CLR_Pos) /*!< SYSCON AHBCLKCTRLCLR0: DMA_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR0_ISO7816_CLK_CLR_Pos 21 /*!< SYSCON AHBCLKCTRLCLR0: ISO7816_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR0_ISO7816_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR0_ISO7816_CLK_CLR_Pos)/*!< SYSCON AHBCLKCTRLCLR0: ISO7816_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR0_WWDT_CLK_CLR_Pos 22 /*!< SYSCON AHBCLKCTRLCLR0: WWDT_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR0_WWDT_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR0_WWDT_CLK_CLR_Pos) /*!< SYSCON AHBCLKCTRLCLR0: WWDT_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR0_RTC_CLK_CLR_Pos 23 /*!< SYSCON AHBCLKCTRLCLR0: RTC_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR0_RTC_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR0_RTC_CLK_CLR_Pos) /*!< SYSCON AHBCLKCTRLCLR0: RTC_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR0_ANA_INT_CTRL_CLK_SET_Pos 24 /*!< SYSCON AHBCLKCTRLCLR0: ANA_INT_CTRL_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLCLR0_ANA_INT_CTRL_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR0_ANA_INT_CTRL_CLK_SET_Pos)/*!< SYSCON AHBCLKCTRLCLR0: ANA_INT_CTRL_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLCLR0_WAKE_UP_TIMERS_CLK_SET_Pos 25 /*!< SYSCON AHBCLKCTRLCLR0: WAKE_UP_TIMERS_CLK_SET Position */
-#define SYSCON_AHBCLKCTRLCLR0_WAKE_UP_TIMERS_CLK_SET_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR0_WAKE_UP_TIMERS_CLK_SET_Pos)/*!< SYSCON AHBCLKCTRLCLR0: WAKE_UP_TIMERS_CLK_SET Mask */
-#define SYSCON_AHBCLKCTRLCLR0_MAILBOX_CLK_CLR_Pos 26 /*!< SYSCON AHBCLKCTRLCLR0: MAILBOX_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR0_MAILBOX_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR0_MAILBOX_CLK_CLR_Pos)/*!< SYSCON AHBCLKCTRLCLR0: MAILBOX_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR0_ADC_CLK_CLR_Pos 27 /*!< SYSCON AHBCLKCTRLCLR0: ADC_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR0_ADC_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR0_ADC_CLK_CLR_Pos) /*!< SYSCON AHBCLKCTRLCLR0: ADC_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR0_EFUSE_CLK_CLR_Pos 28 /*!< SYSCON AHBCLKCTRLCLR0: EFUSE_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR0_EFUSE_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR0_EFUSE_CLK_CLR_Pos)/*!< SYSCON AHBCLKCTRLCLR0: EFUSE_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR0_PVT_CLK_CLR_Pos 29 /*!< SYSCON AHBCLKCTRLCLR0: PVT_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR0_PVT_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR0_PVT_CLK_CLR_Pos) /*!< SYSCON AHBCLKCTRLCLR0: PVT_CLK_CLR Mask */
-
-/* --------------------------- u_syscon_AHBCLKCTRLCLR1 -------------------------- */
-#define SYSCON_AHBCLKCTRLCLR1_USART0_CLK_CLR_Pos 11 /*!< SYSCON AHBCLKCTRLCLR1: USART0_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR1_USART0_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR1_USART0_CLK_CLR_Pos)/*!< SYSCON AHBCLKCTRLCLR1: USART0_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR1_USART1_CLK_CLR_Pos 12 /*!< SYSCON AHBCLKCTRLCLR1: USART1_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR1_USART1_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR1_USART1_CLK_CLR_Pos)/*!< SYSCON AHBCLKCTRLCLR1: USART1_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR1_I2C0_CLK_CLR_Pos 13 /*!< SYSCON AHBCLKCTRLCLR1: I2C0_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR1_I2C0_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR1_I2C0_CLK_CLR_Pos) /*!< SYSCON AHBCLKCTRLCLR1: I2C0_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR1_I2C1_CLK_CLR_Pos 14 /*!< SYSCON AHBCLKCTRLCLR1: I2C1_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR1_I2C1_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR1_I2C1_CLK_CLR_Pos) /*!< SYSCON AHBCLKCTRLCLR1: I2C1_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR1_SPI0_CLK_CLR_Pos 15 /*!< SYSCON AHBCLKCTRLCLR1: SPI0_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR1_SPI0_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR1_SPI0_CLK_CLR_Pos) /*!< SYSCON AHBCLKCTRLCLR1: SPI0_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR1_SPI1_CLK_CLR_Pos 16 /*!< SYSCON AHBCLKCTRLCLR1: SPI1_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR1_SPI1_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR1_SPI1_CLK_CLR_Pos) /*!< SYSCON AHBCLKCTRLCLR1: SPI1_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR1_IR_CLK_CLR_Pos 17 /*!< SYSCON AHBCLKCTRLCLR1: IR_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR1_IR_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR1_IR_CLK_CLR_Pos) /*!< SYSCON AHBCLKCTRLCLR1: IR_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR1_PWM_CLK_CLR_Pos 18 /*!< SYSCON AHBCLKCTRLCLR1: PWM_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR1_PWM_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR1_PWM_CLK_CLR_Pos) /*!< SYSCON AHBCLKCTRLCLR1: PWM_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR1_RNG_CLK_CLR_Pos 19 /*!< SYSCON AHBCLKCTRLCLR1: RNG_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR1_RNG_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR1_RNG_CLK_CLR_Pos) /*!< SYSCON AHBCLKCTRLCLR1: RNG_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR1_I2C2_CLK_CLR_Pos 20 /*!< SYSCON AHBCLKCTRLCLR1: I2C2_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR1_I2C2_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR1_I2C2_CLK_CLR_Pos) /*!< SYSCON AHBCLKCTRLCLR1: I2C2_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR1_ZIGBEE_CLK_CLR_Pos 21 /*!< SYSCON AHBCLKCTRLCLR1: ZIGBEE_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR1_ZIGBEE_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR1_ZIGBEE_CLK_CLR_Pos)/*!< SYSCON AHBCLKCTRLCLR1: ZIGBEE_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR1_BLE_CLK_CLR_Pos 22 /*!< SYSCON AHBCLKCTRLCLR1: BLE_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR1_BLE_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR1_BLE_CLK_CLR_Pos) /*!< SYSCON AHBCLKCTRLCLR1: BLE_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR1_MODEM_MASTER_CLK_CLR_Pos 23 /*!< SYSCON AHBCLKCTRLCLR1: MODEM_MASTER_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR1_MODEM_MASTER_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR1_MODEM_MASTER_CLK_CLR_Pos)/*!< SYSCON AHBCLKCTRLCLR1: MODEM_MASTER_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR1_AES_CLK_CLR_Pos 24 /*!< SYSCON AHBCLKCTRLCLR1: AES_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR1_AES_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR1_AES_CLK_CLR_Pos) /*!< SYSCON AHBCLKCTRLCLR1: AES_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR1_RFP_CLK_CLR_Pos 25 /*!< SYSCON AHBCLKCTRLCLR1: RFP_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR1_RFP_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR1_RFP_CLK_CLR_Pos) /*!< SYSCON AHBCLKCTRLCLR1: RFP_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR1_DMIC_CLK_CLR_Pos 26 /*!< SYSCON AHBCLKCTRLCLR1: DMIC_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR1_DMIC_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR1_DMIC_CLK_CLR_Pos) /*!< SYSCON AHBCLKCTRLCLR1: DMIC_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR1_HASH_CLK_CLR_Pos 27 /*!< SYSCON AHBCLKCTRLCLR1: HASH_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR1_HASH_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR1_HASH_CLK_CLR_Pos) /*!< SYSCON AHBCLKCTRLCLR1: HASH_CLK_CLR Mask */
-#define SYSCON_AHBCLKCTRLCLR1_TPR_CLK_CLR_Pos 28 /*!< SYSCON AHBCLKCTRLCLR1: TPR_CLK_CLR Position */
-#define SYSCON_AHBCLKCTRLCLR1_TPR_CLK_CLR_Msk (0x01UL << SYSCON_AHBCLKCTRLCLR1_TPR_CLK_CLR_Pos) /*!< SYSCON AHBCLKCTRLCLR1: TPR_CLK_CLR Mask */
-
-/* ----------------------------- u_syscon_MAINCLKSEL ---------------------------- */
-#define SYSCON_MAINCLKSEL_SEL_Pos 0 /*!< SYSCON MAINCLKSEL: SEL Position */
-#define SYSCON_MAINCLKSEL_SEL_Msk (0x07UL << SYSCON_MAINCLKSEL_SEL_Pos) /*!< SYSCON MAINCLKSEL: SEL Mask */
-
-/* ---------------------------- u_syscon_OSC32CLKSEL ---------------------------- */
-#define SYSCON_OSC32CLKSEL_SEL32MHZ_Pos 0 /*!< SYSCON OSC32CLKSEL: SEL32MHZ Position */
-#define SYSCON_OSC32CLKSEL_SEL32MHZ_Msk (0x01UL << SYSCON_OSC32CLKSEL_SEL32MHZ_Pos) /*!< SYSCON OSC32CLKSEL: SEL32MHZ Mask */
-#define SYSCON_OSC32CLKSEL_SEL32KHZ_Pos 1 /*!< SYSCON OSC32CLKSEL: SEL32KHZ Position */
-#define SYSCON_OSC32CLKSEL_SEL32KHZ_Msk (0x01UL << SYSCON_OSC32CLKSEL_SEL32KHZ_Pos) /*!< SYSCON OSC32CLKSEL: SEL32KHZ Mask */
-
-/* ----------------------------- u_syscon_CLKOUTSEL ----------------------------- */
-#define SYSCON_CLKOUTSEL_SEL_Pos 0 /*!< SYSCON CLKOUTSEL: SEL Position */
-#define SYSCON_CLKOUTSEL_SEL_Msk (0x07UL << SYSCON_CLKOUTSEL_SEL_Pos) /*!< SYSCON CLKOUTSEL: SEL Mask */
-
-/* ---------------------------- u_syscon_SPIFICLKSEL ---------------------------- */
-#define SYSCON_SPIFICLKSEL_SEL_Pos 0 /*!< SYSCON SPIFICLKSEL: SEL Position */
-#define SYSCON_SPIFICLKSEL_SEL_Msk (0x07UL << SYSCON_SPIFICLKSEL_SEL_Pos) /*!< SYSCON SPIFICLKSEL: SEL Mask */
-
-/* ----------------------------- u_syscon_ADCCLKSEL ----------------------------- */
-#define SYSCON_ADCCLKSEL_SEL_Pos 0 /*!< SYSCON ADCCLKSEL: SEL Position */
-#define SYSCON_ADCCLKSEL_SEL_Msk (0x03UL << SYSCON_ADCCLKSEL_SEL_Pos) /*!< SYSCON ADCCLKSEL: SEL Mask */
-
-/* ---------------------------- u_syscon_USARTCLKSEL ---------------------------- */
-#define SYSCON_USARTCLKSEL_SEL_Pos 0 /*!< SYSCON USARTCLKSEL: SEL Position */
-#define SYSCON_USARTCLKSEL_SEL_Msk (0x03UL << SYSCON_USARTCLKSEL_SEL_Pos) /*!< SYSCON USARTCLKSEL: SEL Mask */
-
-/* ----------------------------- u_syscon_I2CCLKSEL ----------------------------- */
-#define u_syscon_I2CCLKSEL_SEL_Pos 0 /*!< u_syscon I2CCLKSEL: SEL Position */
-#define u_syscon_I2CCLKSEL_SEL_Msk (0x03UL << u_syscon_I2CCLKSEL_SEL_Pos) /*!< u_syscon I2CCLKSEL: SEL Mask */
-
-/* ----------------------------- u_syscon_SPICLKSEL ----------------------------- */
-#define SYSCON_SPICLKSEL_SEL_Pos 0 /*!< SYSCON SPICLKSEL: SEL Position */
-#define SYSCON_SPICLKSEL_SEL_Msk (0x03UL << SYSCON_SPICLKSEL_SEL_Pos) /*!< SYSCON SPICLKSEL: SEL Mask */
-
-/* ------------------------------ u_syscon_IRCLKSEL ----------------------------- */
-#define SYSCON_IRCLKSEL_SEL_Pos 0 /*!< SYSCON IRCLKSEL: SEL Position */
-#define SYSCON_IRCLKSEL_SEL_Msk (0x03UL << SYSCON_IRCLKSEL_SEL_Pos) /*!< SYSCON IRCLKSEL: SEL Mask */
-
-/* ----------------------------- u_syscon_PWMCLKSEL ----------------------------- */
-#define SYSCON_PWMCLKSEL_SEL_Pos 0 /*!< SYSCON PWMCLKSEL: SEL Position */
-#define SYSCON_PWMCLKSEL_SEL_Msk (0x03UL << SYSCON_PWMCLKSEL_SEL_Pos) /*!< SYSCON PWMCLKSEL: SEL Mask */
-
-/* ----------------------------- u_syscon_WDTCLKSEL ----------------------------- */
-#define SYSCON_WDTCLKSEL_SEL_Pos 0 /*!< SYSCON WDTCLKSEL: SEL Position */
-#define SYSCON_WDTCLKSEL_SEL_Msk (0x03UL << SYSCON_WDTCLKSEL_SEL_Pos) /*!< SYSCON WDTCLKSEL: SEL Mask */
-
-/* ---------------------------- u_syscon_MODEMCLKSEL ---------------------------- */
-#define SYSCON_MODEMCLKSEL_SEL_ZIGBEE_Pos 0 /*!< SYSCON MODEMCLKSEL: SEL_ZIGBEE Position */
-#define SYSCON_MODEMCLKSEL_SEL_ZIGBEE_Msk (0x01UL << SYSCON_MODEMCLKSEL_SEL_ZIGBEE_Pos) /*!< SYSCON MODEMCLKSEL: SEL_ZIGBEE Mask */
-#define SYSCON_MODEMCLKSEL_SEL_BLE_Pos 1 /*!< SYSCON MODEMCLKSEL: SEL_BLE Position */
-#define SYSCON_MODEMCLKSEL_SEL_BLE_Msk (0x01UL << SYSCON_MODEMCLKSEL_SEL_BLE_Pos) /*!< SYSCON MODEMCLKSEL: SEL_BLE Mask */
-
-/* ----------------------------- u_syscon_FRGCLKSEL ----------------------------- */
-#define SYSCON_FRGCLKSEL_SEL_Pos 0 /*!< SYSCON FRGCLKSEL: SEL Position */
-#define SYSCON_FRGCLKSEL_SEL_Msk (0x03UL << SYSCON_FRGCLKSEL_SEL_Pos) /*!< SYSCON FRGCLKSEL: SEL Mask */
-
-/* ----------------------------- u_syscon_DMICCLKSEL ---------------------------- */
-#define SYSCON_DMICCLKSEL_SEL_Pos 0 /*!< SYSCON DMICCLKSEL: SEL Position */
-#define SYSCON_DMICCLKSEL_SEL_Msk (0x07UL << SYSCON_DMICCLKSEL_SEL_Pos) /*!< SYSCON DMICCLKSEL: SEL Mask */
-
-/* ----------------------------- u_syscon_WKTCLKSEL ----------------------------- */
-#define SYSCON_WKTCLKSEL_SEL_Pos 0 /*!< SYSCON WKTCLKSEL: SEL Position */
-#define SYSCON_WKTCLKSEL_SEL_Msk (0x03UL << SYSCON_WKTCLKSEL_SEL_Pos) /*!< SYSCON WKTCLKSEL: SEL Mask */
-
-/* --------------------------- u_syscon_ISO7816CLKSEL --------------------------- */
-#define SYSCON_ISO7816CLKSEL_ISO7816CLKSEL_Pos 0 /*!< SYSCON ISO7816CLKSEL: ISO7816CLKSEL Position */
-#define SYSCON_ISO7816CLKSEL_ISO7816CLKSEL_Msk (0xffffffffUL << SYSCON_ISO7816CLKSEL_ISO7816CLKSEL_Pos)/*!< SYSCON ISO7816CLKSEL: ISO7816CLKSEL Mask */
-
-/* --------------------------- u_syscon_SYSTICKCLKDIV --------------------------- */
-#define SYSCON_SYSTICKCLKDIV_DIV_Pos 0 /*!< SYSCON SYSTICKCLKDIV: DIV Position */
-#define SYSCON_SYSTICKCLKDIV_DIV_Msk (0x000000ffUL << SYSCON_SYSTICKCLKDIV_DIV_Pos) /*!< SYSCON SYSTICKCLKDIV: DIV Mask */
-#define SYSCON_SYSTICKCLKDIV_RESET_Pos 29 /*!< SYSCON SYSTICKCLKDIV: RESET Position */
-#define SYSCON_SYSTICKCLKDIV_RESET_Msk (0x01UL << SYSCON_SYSTICKCLKDIV_RESET_Pos) /*!< SYSCON SYSTICKCLKDIV: RESET Mask */
-#define SYSCON_SYSTICKCLKDIV_HALT_Pos 30 /*!< SYSCON SYSTICKCLKDIV: HALT Position */
-#define SYSCON_SYSTICKCLKDIV_HALT_Msk (0x01UL << SYSCON_SYSTICKCLKDIV_HALT_Pos) /*!< SYSCON SYSTICKCLKDIV: HALT Mask */
-#define SYSCON_SYSTICKCLKDIV_REQFLAG_Pos 31 /*!< SYSCON SYSTICKCLKDIV: REQFLAG Position */
-#define SYSCON_SYSTICKCLKDIV_REQFLAG_Msk (0x01UL << SYSCON_SYSTICKCLKDIV_REQFLAG_Pos) /*!< SYSCON SYSTICKCLKDIV: REQFLAG Mask */
-
-/* ---------------------------- u_syscon_TRACECLKDIV ---------------------------- */
-#define SYSCON_TRACECLKDIV_DIV_Pos 0 /*!< SYSCON TRACECLKDIV: DIV Position */
-#define SYSCON_TRACECLKDIV_DIV_Msk (0x000000ffUL << SYSCON_TRACECLKDIV_DIV_Pos) /*!< SYSCON TRACECLKDIV: DIV Mask */
-#define SYSCON_TRACECLKDIV_RESET_Pos 29 /*!< SYSCON TRACECLKDIV: RESET Position */
-#define SYSCON_TRACECLKDIV_RESET_Msk (0x01UL << SYSCON_TRACECLKDIV_RESET_Pos) /*!< SYSCON TRACECLKDIV: RESET Mask */
-#define SYSCON_TRACECLKDIV_HALT_Pos 30 /*!< SYSCON TRACECLKDIV: HALT Position */
-#define SYSCON_TRACECLKDIV_HALT_Msk (0x01UL << SYSCON_TRACECLKDIV_HALT_Pos) /*!< SYSCON TRACECLKDIV: HALT Mask */
-#define SYSCON_TRACECLKDIV_REQFLAG_Pos 31 /*!< SYSCON TRACECLKDIV: REQFLAG Position */
-#define SYSCON_TRACECLKDIV_REQFLAG_Msk (0x01UL << SYSCON_TRACECLKDIV_REQFLAG_Pos) /*!< SYSCON TRACECLKDIV: REQFLAG Mask */
-
-/* ----------------------------- u_syscon_WDTCLKDIV ----------------------------- */
-#define SYSCON_WDTCLKDIV_DIV_Pos 0 /*!< SYSCON WDTCLKDIV: DIV Position */
-#define SYSCON_WDTCLKDIV_DIV_Msk (0x000000ffUL << SYSCON_WDTCLKDIV_DIV_Pos) /*!< SYSCON WDTCLKDIV: DIV Mask */
-#define SYSCON_WDTCLKDIV_RESET_Pos 29 /*!< SYSCON WDTCLKDIV: RESET Position */
-#define SYSCON_WDTCLKDIV_RESET_Msk (0x01UL << SYSCON_WDTCLKDIV_RESET_Pos) /*!< SYSCON WDTCLKDIV: RESET Mask */
-#define SYSCON_WDTCLKDIV_HALT_Pos 30 /*!< SYSCON WDTCLKDIV: HALT Position */
-#define SYSCON_WDTCLKDIV_HALT_Msk (0x01UL << SYSCON_WDTCLKDIV_HALT_Pos) /*!< SYSCON WDTCLKDIV: HALT Mask */
-#define SYSCON_WDTCLKDIV_REQFLAG_Pos 31 /*!< SYSCON WDTCLKDIV: REQFLAG Position */
-#define SYSCON_WDTCLKDIV_REQFLAG_Msk (0x01UL << SYSCON_WDTCLKDIV_REQFLAG_Pos) /*!< SYSCON WDTCLKDIV: REQFLAG Mask */
-
-/* ------------------------------ u_syscon_IRCLKDIV ----------------------------- */
-#define SYSCON_IRCLKDIV_DIV_Pos 0 /*!< SYSCON IRCLKDIV: DIV Position */
-#define SYSCON_IRCLKDIV_DIV_Msk (0x0fUL << SYSCON_IRCLKDIV_DIV_Pos) /*!< SYSCON IRCLKDIV: DIV Mask */
-#define SYSCON_IRCLKDIV_RESET_Pos 29 /*!< SYSCON IRCLKDIV: RESET Position */
-#define SYSCON_IRCLKDIV_RESET_Msk (0x01UL << SYSCON_IRCLKDIV_RESET_Pos) /*!< SYSCON IRCLKDIV: RESET Mask */
-#define SYSCON_IRCLKDIV_HALT_Pos 30 /*!< SYSCON IRCLKDIV: HALT Position */
-#define SYSCON_IRCLKDIV_HALT_Msk (0x01UL << SYSCON_IRCLKDIV_HALT_Pos) /*!< SYSCON IRCLKDIV: HALT Mask */
-#define SYSCON_IRCLKDIV_REQFLAG_Pos 31 /*!< SYSCON IRCLKDIV: REQFLAG Position */
-#define SYSCON_IRCLKDIV_REQFLAG_Msk (0x01UL << SYSCON_IRCLKDIV_REQFLAG_Pos) /*!< SYSCON IRCLKDIV: REQFLAG Mask */
-
-/* ----------------------------- u_syscon_AHBCLKDIV ----------------------------- */
-#define SYSCON_AHBCLKDIV_DIV_Pos 0 /*!< SYSCON AHBCLKDIV: DIV Position */
-#define SYSCON_AHBCLKDIV_DIV_Msk (0x000000ffUL << SYSCON_AHBCLKDIV_DIV_Pos) /*!< SYSCON AHBCLKDIV: DIV Mask */
-#define SYSCON_AHBCLKDIV_REQFLAG_Pos 31 /*!< SYSCON AHBCLKDIV: REQFLAG Position */
-#define SYSCON_AHBCLKDIV_REQFLAG_Msk (0x01UL << SYSCON_AHBCLKDIV_REQFLAG_Pos) /*!< SYSCON AHBCLKDIV: REQFLAG Mask */
-
-/* ----------------------------- u_syscon_CLKOUTDIV ----------------------------- */
-#define SYSCON_CLKOUTDIV_DIV_Pos 0 /*!< SYSCON CLKOUTDIV: DIV Position */
-#define SYSCON_CLKOUTDIV_DIV_Msk (0x0fUL << SYSCON_CLKOUTDIV_DIV_Pos) /*!< SYSCON CLKOUTDIV: DIV Mask */
-#define SYSCON_CLKOUTDIV_RESET_Pos 29 /*!< SYSCON CLKOUTDIV: RESET Position */
-#define SYSCON_CLKOUTDIV_RESET_Msk (0x01UL << SYSCON_CLKOUTDIV_RESET_Pos) /*!< SYSCON CLKOUTDIV: RESET Mask */
-#define SYSCON_CLKOUTDIV_HALT_Pos 30 /*!< SYSCON CLKOUTDIV: HALT Position */
-#define SYSCON_CLKOUTDIV_HALT_Msk (0x01UL << SYSCON_CLKOUTDIV_HALT_Pos) /*!< SYSCON CLKOUTDIV: HALT Mask */
-#define SYSCON_CLKOUTDIV_REQFLAG_Pos 31 /*!< SYSCON CLKOUTDIV: REQFLAG Position */
-#define SYSCON_CLKOUTDIV_REQFLAG_Msk (0x01UL << SYSCON_CLKOUTDIV_REQFLAG_Pos) /*!< SYSCON CLKOUTDIV: REQFLAG Mask */
-
-/* ---------------------------- u_syscon_SPIFICLKDIV ---------------------------- */
-#define SYSCON_SPIFICLKDIV_DIV_Pos 0 /*!< SYSCON SPIFICLKDIV: DIV Position */
-#define SYSCON_SPIFICLKDIV_DIV_Msk (0x03UL << SYSCON_SPIFICLKDIV_DIV_Pos) /*!< SYSCON SPIFICLKDIV: DIV Mask */
-#define SYSCON_SPIFICLKDIV_RESET_Pos 29 /*!< SYSCON SPIFICLKDIV: RESET Position */
-#define SYSCON_SPIFICLKDIV_RESET_Msk (0x01UL << SYSCON_SPIFICLKDIV_RESET_Pos) /*!< SYSCON SPIFICLKDIV: RESET Mask */
-#define SYSCON_SPIFICLKDIV_HALT_Pos 30 /*!< SYSCON SPIFICLKDIV: HALT Position */
-#define SYSCON_SPIFICLKDIV_HALT_Msk (0x01UL << SYSCON_SPIFICLKDIV_HALT_Pos) /*!< SYSCON SPIFICLKDIV: HALT Mask */
-#define SYSCON_SPIFICLKDIV_REQFLAG_Pos 31 /*!< SYSCON SPIFICLKDIV: REQFLAG Position */
-#define SYSCON_SPIFICLKDIV_REQFLAG_Msk (0x01UL << SYSCON_SPIFICLKDIV_REQFLAG_Pos) /*!< SYSCON SPIFICLKDIV: REQFLAG Mask */
-
-/* ----------------------------- u_syscon_ADCCLKDIV ----------------------------- */
-#define SYSCON_ADCCLKDIV_DIV_Pos 0 /*!< SYSCON ADCCLKDIV: DIV Position */
-#define SYSCON_ADCCLKDIV_DIV_Msk (0x07UL << SYSCON_ADCCLKDIV_DIV_Pos) /*!< SYSCON ADCCLKDIV: DIV Mask */
-#define SYSCON_ADCCLKDIV_RESET_Pos 29 /*!< SYSCON ADCCLKDIV: RESET Position */
-#define SYSCON_ADCCLKDIV_RESET_Msk (0x01UL << SYSCON_ADCCLKDIV_RESET_Pos) /*!< SYSCON ADCCLKDIV: RESET Mask */
-#define SYSCON_ADCCLKDIV_HALT_Pos 30 /*!< SYSCON ADCCLKDIV: HALT Position */
-#define SYSCON_ADCCLKDIV_HALT_Msk (0x01UL << SYSCON_ADCCLKDIV_HALT_Pos) /*!< SYSCON ADCCLKDIV: HALT Mask */
-#define SYSCON_ADCCLKDIV_REQFLAG_Pos 31 /*!< SYSCON ADCCLKDIV: REQFLAG Position */
-#define SYSCON_ADCCLKDIV_REQFLAG_Msk (0x01UL << SYSCON_ADCCLKDIV_REQFLAG_Pos) /*!< SYSCON ADCCLKDIV: REQFLAG Mask */
-
-/* ----------------------------- u_syscon_RTCCLKDIV ----------------------------- */
-#define SYSCON_RTCCLKDIV_DIV_Pos 0 /*!< SYSCON RTCCLKDIV: DIV Position */
-#define SYSCON_RTCCLKDIV_DIV_Msk (0x1fUL << SYSCON_RTCCLKDIV_DIV_Pos) /*!< SYSCON RTCCLKDIV: DIV Mask */
-#define SYSCON_RTCCLKDIV_RESET_Pos 29 /*!< SYSCON RTCCLKDIV: RESET Position */
-#define SYSCON_RTCCLKDIV_RESET_Msk (0x01UL << SYSCON_RTCCLKDIV_RESET_Pos) /*!< SYSCON RTCCLKDIV: RESET Mask */
-#define SYSCON_RTCCLKDIV_HALT_Pos 30 /*!< SYSCON RTCCLKDIV: HALT Position */
-#define SYSCON_RTCCLKDIV_HALT_Msk (0x01UL << SYSCON_RTCCLKDIV_HALT_Pos) /*!< SYSCON RTCCLKDIV: HALT Mask */
-#define SYSCON_RTCCLKDIV_REQFLAG_Pos 31 /*!< SYSCON RTCCLKDIV: REQFLAG Position */
-#define SYSCON_RTCCLKDIV_REQFLAG_Msk (0x01UL << SYSCON_RTCCLKDIV_REQFLAG_Pos) /*!< SYSCON RTCCLKDIV: REQFLAG Mask */
-
-/* ------------------------------ u_syscon_FRGCTRL ------------------------------ */
-#define SYSCON_FRGCTRL_DIV_Pos 0 /*!< SYSCON FRGCTRL: DIV Position */
-#define SYSCON_FRGCTRL_DIV_Msk (0x000000ffUL << SYSCON_FRGCTRL_DIV_Pos) /*!< SYSCON FRGCTRL: DIV Mask */
-#define SYSCON_FRGCTRL_MULT_Pos 8 /*!< SYSCON FRGCTRL: MULT Position */
-#define SYSCON_FRGCTRL_MULT_Msk (0x000000ffUL << SYSCON_FRGCTRL_MULT_Pos) /*!< SYSCON FRGCTRL: MULT Mask */
-
-/* ----------------------------- u_syscon_DMICCLKDIV ---------------------------- */
-#define SYSCON_DMICCLKDIV_DIV_Pos 0 /*!< SYSCON DMICCLKDIV: DIV Position */
-#define SYSCON_DMICCLKDIV_DIV_Msk (0x000000ffUL << SYSCON_DMICCLKDIV_DIV_Pos) /*!< SYSCON DMICCLKDIV: DIV Mask */
-#define SYSCON_DMICCLKDIV_RESET_Pos 29 /*!< SYSCON DMICCLKDIV: RESET Position */
-#define SYSCON_DMICCLKDIV_RESET_Msk (0x01UL << SYSCON_DMICCLKDIV_RESET_Pos) /*!< SYSCON DMICCLKDIV: RESET Mask */
-#define SYSCON_DMICCLKDIV_HALT_Pos 30 /*!< SYSCON DMICCLKDIV: HALT Position */
-#define SYSCON_DMICCLKDIV_HALT_Msk (0x01UL << SYSCON_DMICCLKDIV_HALT_Pos) /*!< SYSCON DMICCLKDIV: HALT Mask */
-#define SYSCON_DMICCLKDIV_REQFLAG_Pos 31 /*!< SYSCON DMICCLKDIV: REQFLAG Position */
-#define SYSCON_DMICCLKDIV_REQFLAG_Msk (0x01UL << SYSCON_DMICCLKDIV_REQFLAG_Pos) /*!< SYSCON DMICCLKDIV: REQFLAG Mask */
-
-/* ---------------------------- u_syscon_RTC1HZCLKDIV --------------------------- */
-#define SYSCON_RTC1HZCLKDIV_RESET_Pos 29 /*!< SYSCON RTC1HZCLKDIV: RESET Position */
-#define SYSCON_RTC1HZCLKDIV_RESET_Msk (0x01UL << SYSCON_RTC1HZCLKDIV_RESET_Pos) /*!< SYSCON RTC1HZCLKDIV: RESET Mask */
-#define SYSCON_RTC1HZCLKDIV_HALT_Pos 30 /*!< SYSCON RTC1HZCLKDIV: HALT Position */
-#define SYSCON_RTC1HZCLKDIV_HALT_Msk (0x01UL << SYSCON_RTC1HZCLKDIV_HALT_Pos) /*!< SYSCON RTC1HZCLKDIV: HALT Mask */
-#define SYSCON_RTC1HZCLKDIV_REQFLAG_Pos 31 /*!< SYSCON RTC1HZCLKDIV: REQFLAG Position */
-#define SYSCON_RTC1HZCLKDIV_REQFLAG_Msk (0x01UL << SYSCON_RTC1HZCLKDIV_REQFLAG_Pos) /*!< SYSCON RTC1HZCLKDIV: REQFLAG Mask */
-
-/* ----------------------- u_syscon_CLOCKGENUPDATELOCKOUT ----------------------- */
-#define SYSCON_CLOCKGENUPDATELOCKOUT_LOCK_Pos 0 /*!< SYSCON CLOCKGENUPDATELOCKOUT: LOCK Position */
-#define SYSCON_CLOCKGENUPDATELOCKOUT_LOCK_Msk (0x01UL << SYSCON_CLOCKGENUPDATELOCKOUT_LOCK_Pos) /*!< SYSCON CLOCKGENUPDATELOCKOUT: LOCK Mask */
-
-/* ---------------------------- u_syscon_EFUSECLKCTRL --------------------------- */
-#define SYSCON_EFUSECLKCTRL_ENABLE_Pos 0 /*!< SYSCON EFUSECLKCTRL: ENABLE Position */
-#define SYSCON_EFUSECLKCTRL_ENABLE_Msk (0x01UL << SYSCON_EFUSECLKCTRL_ENABLE_Pos) /*!< SYSCON EFUSECLKCTRL: ENABLE Mask */
-
-/* ------------------------------ u_syscon_RNGCTRL ------------------------------ */
-#define SYSCON_RNGCTRL_START_Pos 0 /*!< SYSCON RNGCTRL: START Position */
-#define SYSCON_RNGCTRL_START_Msk (0x01UL << SYSCON_RNGCTRL_START_Pos) /*!< SYSCON RNGCTRL: START Mask */
-
-/* ----------------------------- u_syscon_RNGCLKCTRL ---------------------------- */
-#define SYSCON_RNGCLKCTRL_ENABLE_Pos 0 /*!< SYSCON RNGCLKCTRL: ENABLE Position */
-#define SYSCON_RNGCLKCTRL_ENABLE_Msk (0x01UL << SYSCON_RNGCLKCTRL_ENABLE_Pos) /*!< SYSCON RNGCLKCTRL: ENABLE Mask */
-
-/* ------------------------------ u_syscon_SRAMCTRL ----------------------------- */
-#define SYSCON_SRAMCTRL_SMB_Pos 0 /*!< SYSCON SRAMCTRL: SMB Position */
-#define SYSCON_SRAMCTRL_SMB_Msk (0x03UL << SYSCON_SRAMCTRL_SMB_Pos) /*!< SYSCON SRAMCTRL: SMB Mask */
-#define SYSCON_SRAMCTRL_RM_Pos 2 /*!< SYSCON SRAMCTRL: RM Position */
-#define SYSCON_SRAMCTRL_RM_Msk (0x07UL << SYSCON_SRAMCTRL_RM_Pos) /*!< SYSCON SRAMCTRL: RM Mask */
-#define SYSCON_SRAMCTRL_WM_Pos 5 /*!< SYSCON SRAMCTRL: WM Position */
-#define SYSCON_SRAMCTRL_WM_Msk (0x07UL << SYSCON_SRAMCTRL_WM_Pos) /*!< SYSCON SRAMCTRL: WM Mask */
-#define SYSCON_SRAMCTRL_WRME_Pos 8 /*!< SYSCON SRAMCTRL: WRME Position */
-#define SYSCON_SRAMCTRL_WRME_Msk (0x01UL << SYSCON_SRAMCTRL_WRME_Pos) /*!< SYSCON SRAMCTRL: WRME Mask */
-#define SYSCON_SRAMCTRL_RAM_Pos 9 /*!< SYSCON SRAMCTRL: RAM Position */
-#define SYSCON_SRAMCTRL_RAM_Msk (0x0fUL << SYSCON_SRAMCTRL_RAM_Pos) /*!< SYSCON SRAMCTRL: RAM Mask */
-#define SYSCON_SRAMCTRL_WAM_Pos 13 /*!< SYSCON SRAMCTRL: WAM Position */
-#define SYSCON_SRAMCTRL_WAM_Msk (0x03UL << SYSCON_SRAMCTRL_WAM_Pos) /*!< SYSCON SRAMCTRL: WAM Mask */
-#define SYSCON_SRAMCTRL_RAEN_Pos 15 /*!< SYSCON SRAMCTRL: RAEN Position */
-#define SYSCON_SRAMCTRL_RAEN_Msk (0x01UL << SYSCON_SRAMCTRL_RAEN_Pos) /*!< SYSCON SRAMCTRL: RAEN Mask */
-#define SYSCON_SRAMCTRL_WAEN_Pos 16 /*!< SYSCON SRAMCTRL: WAEN Position */
-#define SYSCON_SRAMCTRL_WAEN_Msk (0x01UL << SYSCON_SRAMCTRL_WAEN_Pos) /*!< SYSCON SRAMCTRL: WAEN Mask */
-#define SYSCON_SRAMCTRL_STBP_Pos 17 /*!< SYSCON SRAMCTRL: STBP Position */
-#define SYSCON_SRAMCTRL_STBP_Msk (0x01UL << SYSCON_SRAMCTRL_STBP_Pos) /*!< SYSCON SRAMCTRL: STBP Mask */
-#define SYSCON_SRAMCTRL_VSBTEST_Pos 18 /*!< SYSCON SRAMCTRL: VSBTEST Position */
-#define SYSCON_SRAMCTRL_VSBTEST_Msk (0x01UL << SYSCON_SRAMCTRL_VSBTEST_Pos) /*!< SYSCON SRAMCTRL: VSBTEST Mask */
-
-/* ----------------------------- u_syscon_SRAMCTRL0 ----------------------------- */
-#define SYSCON_SRAMCTRL0_SRAM0_LS_Pos 0 /*!< SYSCON SRAMCTRL0: SRAM0_LS Position */
-#define SYSCON_SRAMCTRL0_SRAM0_LS_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM0_LS_Pos) /*!< SYSCON SRAMCTRL0: SRAM0_LS Mask */
-#define SYSCON_SRAMCTRL0_SRAM0_DSB_Pos 1 /*!< SYSCON SRAMCTRL0: SRAM0_DSB Position */
-#define SYSCON_SRAMCTRL0_SRAM0_DSB_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM0_DSB_Pos) /*!< SYSCON SRAMCTRL0: SRAM0_DSB Mask */
-#define SYSCON_SRAMCTRL0_SRAM0_DSBDEL_Pos 2 /*!< SYSCON SRAMCTRL0: SRAM0_DSBDEL Position */
-#define SYSCON_SRAMCTRL0_SRAM0_DSBDEL_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM0_DSBDEL_Pos) /*!< SYSCON SRAMCTRL0: SRAM0_DSBDEL Mask */
-#define SYSCON_SRAMCTRL0_SRAM0_LSDEL_Pos 3 /*!< SYSCON SRAMCTRL0: SRAM0_LSDEL Position */
-#define SYSCON_SRAMCTRL0_SRAM0_LSDEL_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM0_LSDEL_Pos) /*!< SYSCON SRAMCTRL0: SRAM0_LSDEL Mask */
-#define SYSCON_SRAMCTRL0_SRAM1_LS_Pos 4 /*!< SYSCON SRAMCTRL0: SRAM1_LS Position */
-#define SYSCON_SRAMCTRL0_SRAM1_LS_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM1_LS_Pos) /*!< SYSCON SRAMCTRL0: SRAM1_LS Mask */
-#define SYSCON_SRAMCTRL0_SRAM1_DSB_Pos 5 /*!< SYSCON SRAMCTRL0: SRAM1_DSB Position */
-#define SYSCON_SRAMCTRL0_SRAM1_DSB_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM1_DSB_Pos) /*!< SYSCON SRAMCTRL0: SRAM1_DSB Mask */
-#define SYSCON_SRAMCTRL0_SRAM1_DSBDEL_Pos 6 /*!< SYSCON SRAMCTRL0: SRAM1_DSBDEL Position */
-#define SYSCON_SRAMCTRL0_SRAM1_DSBDEL_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM1_DSBDEL_Pos) /*!< SYSCON SRAMCTRL0: SRAM1_DSBDEL Mask */
-#define SYSCON_SRAMCTRL0_SRAM1_LSDEL_Pos 7 /*!< SYSCON SRAMCTRL0: SRAM1_LSDEL Position */
-#define SYSCON_SRAMCTRL0_SRAM1_LSDEL_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM1_LSDEL_Pos) /*!< SYSCON SRAMCTRL0: SRAM1_LSDEL Mask */
-#define SYSCON_SRAMCTRL0_SRAM2_LS_Pos 8 /*!< SYSCON SRAMCTRL0: SRAM2_LS Position */
-#define SYSCON_SRAMCTRL0_SRAM2_LS_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM2_LS_Pos) /*!< SYSCON SRAMCTRL0: SRAM2_LS Mask */
-#define SYSCON_SRAMCTRL0_SRAM2_DSB_Pos 9 /*!< SYSCON SRAMCTRL0: SRAM2_DSB Position */
-#define SYSCON_SRAMCTRL0_SRAM2_DSB_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM2_DSB_Pos) /*!< SYSCON SRAMCTRL0: SRAM2_DSB Mask */
-#define SYSCON_SRAMCTRL0_SRAM2_DSBDEL_Pos 10 /*!< SYSCON SRAMCTRL0: SRAM2_DSBDEL Position */
-#define SYSCON_SRAMCTRL0_SRAM2_DSBDEL_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM2_DSBDEL_Pos) /*!< SYSCON SRAMCTRL0: SRAM2_DSBDEL Mask */
-#define SYSCON_SRAMCTRL0_SRAM2_LSDEL_Pos 11 /*!< SYSCON SRAMCTRL0: SRAM2_LSDEL Position */
-#define SYSCON_SRAMCTRL0_SRAM2_LSDEL_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM2_LSDEL_Pos) /*!< SYSCON SRAMCTRL0: SRAM2_LSDEL Mask */
-#define SYSCON_SRAMCTRL0_SRAM3_LS_Pos 12 /*!< SYSCON SRAMCTRL0: SRAM3_LS Position */
-#define SYSCON_SRAMCTRL0_SRAM3_LS_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM3_LS_Pos) /*!< SYSCON SRAMCTRL0: SRAM3_LS Mask */
-#define SYSCON_SRAMCTRL0_SRAM3_DSB_Pos 13 /*!< SYSCON SRAMCTRL0: SRAM3_DSB Position */
-#define SYSCON_SRAMCTRL0_SRAM3_DSB_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM3_DSB_Pos) /*!< SYSCON SRAMCTRL0: SRAM3_DSB Mask */
-#define SYSCON_SRAMCTRL0_SRAM3_DSBDEL_Pos 14 /*!< SYSCON SRAMCTRL0: SRAM3_DSBDEL Position */
-#define SYSCON_SRAMCTRL0_SRAM3_DSBDEL_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM3_DSBDEL_Pos) /*!< SYSCON SRAMCTRL0: SRAM3_DSBDEL Mask */
-#define SYSCON_SRAMCTRL0_SRAM3_LSDEL_Pos 15 /*!< SYSCON SRAMCTRL0: SRAM3_LSDEL Position */
-#define SYSCON_SRAMCTRL0_SRAM3_LSDEL_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM3_LSDEL_Pos) /*!< SYSCON SRAMCTRL0: SRAM3_LSDEL Mask */
-#define SYSCON_SRAMCTRL0_SRAM4_LS_Pos 16 /*!< SYSCON SRAMCTRL0: SRAM4_LS Position */
-#define SYSCON_SRAMCTRL0_SRAM4_LS_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM4_LS_Pos) /*!< SYSCON SRAMCTRL0: SRAM4_LS Mask */
-#define SYSCON_SRAMCTRL0_SRAM4_DSB_Pos 17 /*!< SYSCON SRAMCTRL0: SRAM4_DSB Position */
-#define SYSCON_SRAMCTRL0_SRAM4_DSB_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM4_DSB_Pos) /*!< SYSCON SRAMCTRL0: SRAM4_DSB Mask */
-#define SYSCON_SRAMCTRL0_SRAM4_DSBDEL_Pos 18 /*!< SYSCON SRAMCTRL0: SRAM4_DSBDEL Position */
-#define SYSCON_SRAMCTRL0_SRAM4_DSBDEL_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM4_DSBDEL_Pos) /*!< SYSCON SRAMCTRL0: SRAM4_DSBDEL Mask */
-#define SYSCON_SRAMCTRL0_SRAM4_LSDEL_Pos 19 /*!< SYSCON SRAMCTRL0: SRAM4_LSDEL Position */
-#define SYSCON_SRAMCTRL0_SRAM4_LSDEL_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM4_LSDEL_Pos) /*!< SYSCON SRAMCTRL0: SRAM4_LSDEL Mask */
-#define SYSCON_SRAMCTRL0_SRAM5_LS_Pos 20 /*!< SYSCON SRAMCTRL0: SRAM5_LS Position */
-#define SYSCON_SRAMCTRL0_SRAM5_LS_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM5_LS_Pos) /*!< SYSCON SRAMCTRL0: SRAM5_LS Mask */
-#define SYSCON_SRAMCTRL0_SRAM5_DSB_Pos 21 /*!< SYSCON SRAMCTRL0: SRAM5_DSB Position */
-#define SYSCON_SRAMCTRL0_SRAM5_DSB_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM5_DSB_Pos) /*!< SYSCON SRAMCTRL0: SRAM5_DSB Mask */
-#define SYSCON_SRAMCTRL0_SRAM5_DSBDEL_Pos 22 /*!< SYSCON SRAMCTRL0: SRAM5_DSBDEL Position */
-#define SYSCON_SRAMCTRL0_SRAM5_DSBDEL_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM5_DSBDEL_Pos) /*!< SYSCON SRAMCTRL0: SRAM5_DSBDEL Mask */
-#define SYSCON_SRAMCTRL0_SRAM5_LSDEL_Pos 23 /*!< SYSCON SRAMCTRL0: SRAM5_LSDEL Position */
-#define SYSCON_SRAMCTRL0_SRAM5_LSDEL_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM5_LSDEL_Pos) /*!< SYSCON SRAMCTRL0: SRAM5_LSDEL Mask */
-#define SYSCON_SRAMCTRL0_SRAM6_LS_Pos 24 /*!< SYSCON SRAMCTRL0: SRAM6_LS Position */
-#define SYSCON_SRAMCTRL0_SRAM6_LS_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM6_LS_Pos) /*!< SYSCON SRAMCTRL0: SRAM6_LS Mask */
-#define SYSCON_SRAMCTRL0_SRAM6_DSB_Pos 25 /*!< SYSCON SRAMCTRL0: SRAM6_DSB Position */
-#define SYSCON_SRAMCTRL0_SRAM6_DSB_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM6_DSB_Pos) /*!< SYSCON SRAMCTRL0: SRAM6_DSB Mask */
-#define SYSCON_SRAMCTRL0_SRAM6_DSBDEL_Pos 26 /*!< SYSCON SRAMCTRL0: SRAM6_DSBDEL Position */
-#define SYSCON_SRAMCTRL0_SRAM6_DSBDEL_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM6_DSBDEL_Pos) /*!< SYSCON SRAMCTRL0: SRAM6_DSBDEL Mask */
-#define SYSCON_SRAMCTRL0_SRAM6_LSDEL_Pos 27 /*!< SYSCON SRAMCTRL0: SRAM6_LSDEL Position */
-#define SYSCON_SRAMCTRL0_SRAM6_LSDEL_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM6_LSDEL_Pos) /*!< SYSCON SRAMCTRL0: SRAM6_LSDEL Mask */
-#define SYSCON_SRAMCTRL0_SRAM7_LS_Pos 28 /*!< SYSCON SRAMCTRL0: SRAM7_LS Position */
-#define SYSCON_SRAMCTRL0_SRAM7_LS_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM7_LS_Pos) /*!< SYSCON SRAMCTRL0: SRAM7_LS Mask */
-#define SYSCON_SRAMCTRL0_SRAM7_DSB_Pos 29 /*!< SYSCON SRAMCTRL0: SRAM7_DSB Position */
-#define SYSCON_SRAMCTRL0_SRAM7_DSB_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM7_DSB_Pos) /*!< SYSCON SRAMCTRL0: SRAM7_DSB Mask */
-#define SYSCON_SRAMCTRL0_SRAM7_DSBDEL_Pos 30 /*!< SYSCON SRAMCTRL0: SRAM7_DSBDEL Position */
-#define SYSCON_SRAMCTRL0_SRAM7_DSBDEL_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM7_DSBDEL_Pos) /*!< SYSCON SRAMCTRL0: SRAM7_DSBDEL Mask */
-#define SYSCON_SRAMCTRL0_SRAM7_LSDEL_Pos 31 /*!< SYSCON SRAMCTRL0: SRAM7_LSDEL Position */
-#define SYSCON_SRAMCTRL0_SRAM7_LSDEL_Msk (0x01UL << SYSCON_SRAMCTRL0_SRAM7_LSDEL_Pos) /*!< SYSCON SRAMCTRL0: SRAM7_LSDEL Mask */
-
-/* ----------------------------- u_syscon_SRAMCTRL1 ----------------------------- */
-#define SYSCON_SRAMCTRL1_SRAM8_LS_Pos 0 /*!< SYSCON SRAMCTRL1: SRAM8_LS Position */
-#define SYSCON_SRAMCTRL1_SRAM8_LS_Msk (0x01UL << SYSCON_SRAMCTRL1_SRAM8_LS_Pos) /*!< SYSCON SRAMCTRL1: SRAM8_LS Mask */
-#define SYSCON_SRAMCTRL1_SRAM8_DSB_Pos 1 /*!< SYSCON SRAMCTRL1: SRAM8_DSB Position */
-#define SYSCON_SRAMCTRL1_SRAM8_DSB_Msk (0x01UL << SYSCON_SRAMCTRL1_SRAM8_DSB_Pos) /*!< SYSCON SRAMCTRL1: SRAM8_DSB Mask */
-#define SYSCON_SRAMCTRL1_SRAM8_DSBDEL_Pos 2 /*!< SYSCON SRAMCTRL1: SRAM8_DSBDEL Position */
-#define SYSCON_SRAMCTRL1_SRAM8_DSBDEL_Msk (0x01UL << SYSCON_SRAMCTRL1_SRAM8_DSBDEL_Pos) /*!< SYSCON SRAMCTRL1: SRAM8_DSBDEL Mask */
-#define SYSCON_SRAMCTRL1_SRAM8_LSDEL_Pos 3 /*!< SYSCON SRAMCTRL1: SRAM8_LSDEL Position */
-#define SYSCON_SRAMCTRL1_SRAM8_LSDEL_Msk (0x01UL << SYSCON_SRAMCTRL1_SRAM8_LSDEL_Pos) /*!< SYSCON SRAMCTRL1: SRAM8_LSDEL Mask */
-#define SYSCON_SRAMCTRL1_SRAM9_LS_Pos 4 /*!< SYSCON SRAMCTRL1: SRAM9_LS Position */
-#define SYSCON_SRAMCTRL1_SRAM9_LS_Msk (0x01UL << SYSCON_SRAMCTRL1_SRAM9_LS_Pos) /*!< SYSCON SRAMCTRL1: SRAM9_LS Mask */
-#define SYSCON_SRAMCTRL1_SRAM9_DSB_Pos 5 /*!< SYSCON SRAMCTRL1: SRAM9_DSB Position */
-#define SYSCON_SRAMCTRL1_SRAM9_DSB_Msk (0x01UL << SYSCON_SRAMCTRL1_SRAM9_DSB_Pos) /*!< SYSCON SRAMCTRL1: SRAM9_DSB Mask */
-#define SYSCON_SRAMCTRL1_SRAM9_DSBDEL_Pos 6 /*!< SYSCON SRAMCTRL1: SRAM9_DSBDEL Position */
-#define SYSCON_SRAMCTRL1_SRAM9_DSBDEL_Msk (0x01UL << SYSCON_SRAMCTRL1_SRAM9_DSBDEL_Pos) /*!< SYSCON SRAMCTRL1: SRAM9_DSBDEL Mask */
-#define SYSCON_SRAMCTRL1_SRAM9_LSDEL_Pos 7 /*!< SYSCON SRAMCTRL1: SRAM9_LSDEL Position */
-#define SYSCON_SRAMCTRL1_SRAM9_LSDEL_Msk (0x01UL << SYSCON_SRAMCTRL1_SRAM9_LSDEL_Pos) /*!< SYSCON SRAMCTRL1: SRAM9_LSDEL Mask */
-#define SYSCON_SRAMCTRL1_SRAM10_LS_Pos 8 /*!< SYSCON SRAMCTRL1: SRAM10_LS Position */
-#define SYSCON_SRAMCTRL1_SRAM10_LS_Msk (0x01UL << SYSCON_SRAMCTRL1_SRAM10_LS_Pos) /*!< SYSCON SRAMCTRL1: SRAM10_LS Mask */
-#define SYSCON_SRAMCTRL1_SRAM10_DSB_Pos 9 /*!< SYSCON SRAMCTRL1: SRAM10_DSB Position */
-#define SYSCON_SRAMCTRL1_SRAM10_DSB_Msk (0x01UL << SYSCON_SRAMCTRL1_SRAM10_DSB_Pos) /*!< SYSCON SRAMCTRL1: SRAM10_DSB Mask */
-#define SYSCON_SRAMCTRL1_SRAM10_DSBDEL_Pos 10 /*!< SYSCON SRAMCTRL1: SRAM10_DSBDEL Position */
-#define SYSCON_SRAMCTRL1_SRAM10_DSBDEL_Msk (0x01UL << SYSCON_SRAMCTRL1_SRAM10_DSBDEL_Pos) /*!< SYSCON SRAMCTRL1: SRAM10_DSBDEL Mask */
-#define SYSCON_SRAMCTRL1_SRAM10_LSDEL_Pos 11 /*!< SYSCON SRAMCTRL1: SRAM10_LSDEL Position */
-#define SYSCON_SRAMCTRL1_SRAM10_LSDEL_Msk (0x01UL << SYSCON_SRAMCTRL1_SRAM10_LSDEL_Pos) /*!< SYSCON SRAMCTRL1: SRAM10_LSDEL Mask */
-#define SYSCON_SRAMCTRL1_SRAM11_LS_Pos 12 /*!< SYSCON SRAMCTRL1: SRAM11_LS Position */
-#define SYSCON_SRAMCTRL1_SRAM11_LS_Msk (0x01UL << SYSCON_SRAMCTRL1_SRAM11_LS_Pos) /*!< SYSCON SRAMCTRL1: SRAM11_LS Mask */
-#define SYSCON_SRAMCTRL1_SRAM11_DSB_Pos 13 /*!< SYSCON SRAMCTRL1: SRAM11_DSB Position */
-#define SYSCON_SRAMCTRL1_SRAM11_DSB_Msk (0x01UL << SYSCON_SRAMCTRL1_SRAM11_DSB_Pos) /*!< SYSCON SRAMCTRL1: SRAM11_DSB Mask */
-#define SYSCON_SRAMCTRL1_SRAM11_DSBDEL_Pos 14 /*!< SYSCON SRAMCTRL1: SRAM11_DSBDEL Position */
-#define SYSCON_SRAMCTRL1_SRAM11_DSBDEL_Msk (0x01UL << SYSCON_SRAMCTRL1_SRAM11_DSBDEL_Pos) /*!< SYSCON SRAMCTRL1: SRAM11_DSBDEL Mask */
-#define SYSCON_SRAMCTRL1_SRAM11_LSDEL_Pos 15 /*!< SYSCON SRAMCTRL1: SRAM11_LSDEL Position */
-#define SYSCON_SRAMCTRL1_SRAM11_LSDEL_Msk (0x01UL << SYSCON_SRAMCTRL1_SRAM11_LSDEL_Pos) /*!< SYSCON SRAMCTRL1: SRAM11_LSDEL Mask */
-
-/* ------------------------------ u_syscon_ROMCTRL ------------------------------ */
-#define SYSCON_ROMCTRL_SDB_Pos 0 /*!< SYSCON ROMCTRL: SDB Position */
-#define SYSCON_ROMCTRL_SDB_Msk (0x01UL << SYSCON_ROMCTRL_SDB_Pos) /*!< SYSCON ROMCTRL: SDB Mask */
-#define SYSCON_ROMCTRL_SDBDEL_Pos 1 /*!< SYSCON ROMCTRL: SDBDEL Position */
-#define SYSCON_ROMCTRL_SDBDEL_Msk (0x01UL << SYSCON_ROMCTRL_SDBDEL_Pos) /*!< SYSCON ROMCTRL: SDBDEL Mask */
-#define SYSCON_ROMCTRL_RME_Pos 2 /*!< SYSCON ROMCTRL: RME Position */
-#define SYSCON_ROMCTRL_RME_Msk (0x01UL << SYSCON_ROMCTRL_RME_Pos) /*!< SYSCON ROMCTRL: RME Mask */
-#define SYSCON_ROMCTRL_RM_Pos 3 /*!< SYSCON ROMCTRL: RM Position */
-#define SYSCON_ROMCTRL_RM_Msk (0x0fUL << SYSCON_ROMCTRL_RM_Pos) /*!< SYSCON ROMCTRL: RM Mask */
-#define SYSCON_ROMCTRL_PM_Pos 7 /*!< SYSCON ROMCTRL: PM Position */
-#define SYSCON_ROMCTRL_PM_Msk (0x03UL << SYSCON_ROMCTRL_PM_Pos) /*!< SYSCON ROMCTRL: PM Mask */
-#define SYSCON_ROMCTRL_VDDMIN_Pos 9 /*!< SYSCON ROMCTRL: VDDMIN Position */
-#define SYSCON_ROMCTRL_VDDMIN_Msk (0x01UL << SYSCON_ROMCTRL_VDDMIN_Pos) /*!< SYSCON ROMCTRL: VDDMIN Mask */
-
-/* ----------------------------- u_syscon_MODEMCTRL ----------------------------- */
-#define SYSCON_MODEMCTRL_BLE_LP_SLEEP_TRIG_Pos 0 /*!< SYSCON MODEMCTRL: BLE_LP_SLEEP_TRIG Position */
-#define SYSCON_MODEMCTRL_BLE_LP_SLEEP_TRIG_Msk (0x01UL << SYSCON_MODEMCTRL_BLE_LP_SLEEP_TRIG_Pos) /*!< SYSCON MODEMCTRL: BLE_LP_SLEEP_TRIG Mask */
-#define SYSCON_MODEMCTRL_BLE_FREQ_SEL_Pos 1 /*!< SYSCON MODEMCTRL: BLE_FREQ_SEL Position */
-#define SYSCON_MODEMCTRL_BLE_FREQ_SEL_Msk (0x01UL << SYSCON_MODEMCTRL_BLE_FREQ_SEL_Pos) /*!< SYSCON MODEMCTRL: BLE_FREQ_SEL Mask */
-#define SYSCON_MODEMCTRL_BLE_DP_DIV_EN_Pos 2 /*!< SYSCON MODEMCTRL: BLE_DP_DIV_EN Position */
-#define SYSCON_MODEMCTRL_BLE_DP_DIV_EN_Msk (0x01UL << SYSCON_MODEMCTRL_BLE_DP_DIV_EN_Pos) /*!< SYSCON MODEMCTRL: BLE_DP_DIV_EN Mask */
-#define SYSCON_MODEMCTRL_BLE_CLK32M_SEL_Pos 3 /*!< SYSCON MODEMCTRL: BLE_CLK32M_SEL Position */
-#define SYSCON_MODEMCTRL_BLE_CLK32M_SEL_Msk (0x01UL << SYSCON_MODEMCTRL_BLE_CLK32M_SEL_Pos) /*!< SYSCON MODEMCTRL: BLE_CLK32M_SEL Mask */
-#define SYSCON_MODEMCTRL_BLE_AHB_DIV0_Pos 4 /*!< SYSCON MODEMCTRL: BLE_AHB_DIV0 Position */
-#define SYSCON_MODEMCTRL_BLE_AHB_DIV0_Msk (0x01UL << SYSCON_MODEMCTRL_BLE_AHB_DIV0_Pos) /*!< SYSCON MODEMCTRL: BLE_AHB_DIV0 Mask */
-#define SYSCON_MODEMCTRL_BLE_AHB_DIV1_Pos 5 /*!< SYSCON MODEMCTRL: BLE_AHB_DIV1 Position */
-#define SYSCON_MODEMCTRL_BLE_AHB_DIV1_Msk (0x01UL << SYSCON_MODEMCTRL_BLE_AHB_DIV1_Pos) /*!< SYSCON MODEMCTRL: BLE_AHB_DIV1 Mask */
-#define SYSCON_MODEMCTRL_BLE_HCLK_BLE_EN_Pos 6 /*!< SYSCON MODEMCTRL: BLE_HCLK_BLE_EN Position */
-#define SYSCON_MODEMCTRL_BLE_HCLK_BLE_EN_Msk (0x01UL << SYSCON_MODEMCTRL_BLE_HCLK_BLE_EN_Pos) /*!< SYSCON MODEMCTRL: BLE_HCLK_BLE_EN Mask */
-#define SYSCON_MODEMCTRL_BLE_PHASE_MATCH_1_Pos 7 /*!< SYSCON MODEMCTRL: BLE_PHASE_MATCH_1 Position */
-#define SYSCON_MODEMCTRL_BLE_PHASE_MATCH_1_Msk (0x01UL << SYSCON_MODEMCTRL_BLE_PHASE_MATCH_1_Pos) /*!< SYSCON MODEMCTRL: BLE_PHASE_MATCH_1 Mask */
-#define SYSCON_MODEMCTRL_BLE_ISO_ENABLE_Pos 8 /*!< SYSCON MODEMCTRL: BLE_ISO_ENABLE Position */
-#define SYSCON_MODEMCTRL_BLE_ISO_ENABLE_Msk (0x01UL << SYSCON_MODEMCTRL_BLE_ISO_ENABLE_Pos) /*!< SYSCON MODEMCTRL: BLE_ISO_ENABLE Mask */
-#define SYSCON_MODEMCTRL_BLE_LP_OSC32K_EN_Pos 9 /*!< SYSCON MODEMCTRL: BLE_LP_OSC32K_EN Position */
-#define SYSCON_MODEMCTRL_BLE_LP_OSC32K_EN_Msk (0x01UL << SYSCON_MODEMCTRL_BLE_LP_OSC32K_EN_Pos) /*!< SYSCON MODEMCTRL: BLE_LP_OSC32K_EN Mask */
-
-/* ---------------------------- u_syscon_MODEMSTATUS ---------------------------- */
-#define SYSCON_MODEMSTATUS_BLE_LL_CLK_STATUS_Pos 0 /*!< SYSCON MODEMSTATUS: BLE_LL_CLK_STATUS Position */
-#define SYSCON_MODEMSTATUS_BLE_LL_CLK_STATUS_Msk (0x01UL << SYSCON_MODEMSTATUS_BLE_LL_CLK_STATUS_Pos)/*!< SYSCON MODEMSTATUS: BLE_LL_CLK_STATUS Mask */
-#define SYSCON_MODEMSTATUS_BLE_LP_OSC_EN_Pos 1 /*!< SYSCON MODEMSTATUS: BLE_LP_OSC_EN Position */
-#define SYSCON_MODEMSTATUS_BLE_LP_OSC_EN_Msk (0x01UL << SYSCON_MODEMSTATUS_BLE_LP_OSC_EN_Pos) /*!< SYSCON MODEMSTATUS: BLE_LP_OSC_EN Mask */
-#define SYSCON_MODEMSTATUS_BLE_LP_RADIO_EN_Pos 2 /*!< SYSCON MODEMSTATUS: BLE_LP_RADIO_EN Position */
-#define SYSCON_MODEMSTATUS_BLE_LP_RADIO_EN_Msk (0x01UL << SYSCON_MODEMSTATUS_BLE_LP_RADIO_EN_Pos) /*!< SYSCON MODEMSTATUS: BLE_LP_RADIO_EN Mask */
-
-/* ----------------------------- u_syscon_XTAL32KCAP ---------------------------- */
-#define SYSCON_XTAL32KCAP_XO_OSC_CAP_IN_Pos 0 /*!< SYSCON XTAL32KCAP: XO_OSC_CAP_IN Position */
-#define SYSCON_XTAL32KCAP_XO_OSC_CAP_IN_Msk (0x7fUL << SYSCON_XTAL32KCAP_XO_OSC_CAP_IN_Pos) /*!< SYSCON XTAL32KCAP: XO_OSC_CAP_IN Mask */
-#define SYSCON_XTAL32KCAP_XO_OSC_CAP_OUT_Pos 7 /*!< SYSCON XTAL32KCAP: XO_OSC_CAP_OUT Position */
-#define SYSCON_XTAL32KCAP_XO_OSC_CAP_OUT_Msk (0x7fUL << SYSCON_XTAL32KCAP_XO_OSC_CAP_OUT_Pos) /*!< SYSCON XTAL32KCAP: XO_OSC_CAP_OUT Mask */
-
-/* ---------------------------- u_syscon_XTAL32MCTRL ---------------------------- */
-#define SYSCON_XTAL32MCTRL_DEACTIVATE_PMC_CTRL_Pos 0 /*!< SYSCON XTAL32MCTRL: DEACTIVATE_PMC_CTRL Position */
-#define SYSCON_XTAL32MCTRL_DEACTIVATE_PMC_CTRL_Msk (0x01UL << SYSCON_XTAL32MCTRL_DEACTIVATE_PMC_CTRL_Pos)/*!< SYSCON XTAL32MCTRL: DEACTIVATE_PMC_CTRL Mask */
-#define SYSCON_XTAL32MCTRL_DEACTIVATE_BLE_CTRL_Pos 1 /*!< SYSCON XTAL32MCTRL: DEACTIVATE_BLE_CTRL Position */
-#define SYSCON_XTAL32MCTRL_DEACTIVATE_BLE_CTRL_Msk (0x01UL << SYSCON_XTAL32MCTRL_DEACTIVATE_BLE_CTRL_Pos)/*!< SYSCON XTAL32MCTRL: DEACTIVATE_BLE_CTRL Mask */
-
-/* ------------------------------ u_syscon_STARTER0 ----------------------------- */
-#define SYSCON_STARTER0_WDT_BOD_Pos 0 /*!< SYSCON STARTER0: WDT_BOD Position */
-#define SYSCON_STARTER0_WDT_BOD_Msk (0x01UL << SYSCON_STARTER0_WDT_BOD_Pos) /*!< SYSCON STARTER0: WDT_BOD Mask */
-#define SYSCON_STARTER0_DMA_Pos 1 /*!< SYSCON STARTER0: DMA Position */
-#define SYSCON_STARTER0_DMA_Msk (0x01UL << SYSCON_STARTER0_DMA_Pos) /*!< SYSCON STARTER0: DMA Mask */
-#define SYSCON_STARTER0_GINT_Pos 2 /*!< SYSCON STARTER0: GINT Position */
-#define SYSCON_STARTER0_GINT_Msk (0x01UL << SYSCON_STARTER0_GINT_Pos) /*!< SYSCON STARTER0: GINT Mask */
-#define SYSCON_STARTER0_IRBLASTER_Pos 3 /*!< SYSCON STARTER0: IRBLASTER Position */
-#define SYSCON_STARTER0_IRBLASTER_Msk (0x01UL << SYSCON_STARTER0_IRBLASTER_Pos) /*!< SYSCON STARTER0: IRBLASTER Mask */
-#define SYSCON_STARTER0_PINT0_Pos 4 /*!< SYSCON STARTER0: PINT0 Position */
-#define SYSCON_STARTER0_PINT0_Msk (0x01UL << SYSCON_STARTER0_PINT0_Pos) /*!< SYSCON STARTER0: PINT0 Mask */
-#define SYSCON_STARTER0_PINT1_Pos 5 /*!< SYSCON STARTER0: PINT1 Position */
-#define SYSCON_STARTER0_PINT1_Msk (0x01UL << SYSCON_STARTER0_PINT1_Pos) /*!< SYSCON STARTER0: PINT1 Mask */
-#define SYSCON_STARTER0_PINT2_Pos 6 /*!< SYSCON STARTER0: PINT2 Position */
-#define SYSCON_STARTER0_PINT2_Msk (0x01UL << SYSCON_STARTER0_PINT2_Pos) /*!< SYSCON STARTER0: PINT2 Mask */
-#define SYSCON_STARTER0_PINT3_Pos 7 /*!< SYSCON STARTER0: PINT3 Position */
-#define SYSCON_STARTER0_PINT3_Msk (0x01UL << SYSCON_STARTER0_PINT3_Pos) /*!< SYSCON STARTER0: PINT3 Mask */
-#define SYSCON_STARTER0_SPIFI_Pos 8 /*!< SYSCON STARTER0: SPIFI Position */
-#define SYSCON_STARTER0_SPIFI_Msk (0x01UL << SYSCON_STARTER0_SPIFI_Pos) /*!< SYSCON STARTER0: SPIFI Mask */
-#define SYSCON_STARTER0_TIMER0_Pos 9 /*!< SYSCON STARTER0: TIMER0 Position */
-#define SYSCON_STARTER0_TIMER0_Msk (0x01UL << SYSCON_STARTER0_TIMER0_Pos) /*!< SYSCON STARTER0: TIMER0 Mask */
-#define SYSCON_STARTER0_TIMER1_Pos 10 /*!< SYSCON STARTER0: TIMER1 Position */
-#define SYSCON_STARTER0_TIMER1_Msk (0x01UL << SYSCON_STARTER0_TIMER1_Pos) /*!< SYSCON STARTER0: TIMER1 Mask */
-#define SYSCON_STARTER0_USART0_Pos 11 /*!< SYSCON STARTER0: USART0 Position */
-#define SYSCON_STARTER0_USART0_Msk (0x01UL << SYSCON_STARTER0_USART0_Pos) /*!< SYSCON STARTER0: USART0 Mask */
-#define SYSCON_STARTER0_USART1_Pos 12 /*!< SYSCON STARTER0: USART1 Position */
-#define SYSCON_STARTER0_USART1_Msk (0x01UL << SYSCON_STARTER0_USART1_Pos) /*!< SYSCON STARTER0: USART1 Mask */
-#define SYSCON_STARTER0_I2C0_Pos 13 /*!< SYSCON STARTER0: I2C0 Position */
-#define SYSCON_STARTER0_I2C0_Msk (0x01UL << SYSCON_STARTER0_I2C0_Pos) /*!< SYSCON STARTER0: I2C0 Mask */
-#define SYSCON_STARTER0_I2C1_Pos 14 /*!< SYSCON STARTER0: I2C1 Position */
-#define SYSCON_STARTER0_I2C1_Msk (0x01UL << SYSCON_STARTER0_I2C1_Pos) /*!< SYSCON STARTER0: I2C1 Mask */
-#define SYSCON_STARTER0_SPI0_Pos 15 /*!< SYSCON STARTER0: SPI0 Position */
-#define SYSCON_STARTER0_SPI0_Msk (0x01UL << SYSCON_STARTER0_SPI0_Pos) /*!< SYSCON STARTER0: SPI0 Mask */
-#define SYSCON_STARTER0_SPI1_Pos 16 /*!< SYSCON STARTER0: SPI1 Position */
-#define SYSCON_STARTER0_SPI1_Msk (0x01UL << SYSCON_STARTER0_SPI1_Pos) /*!< SYSCON STARTER0: SPI1 Mask */
-#define SYSCON_STARTER0_PWM0_Pos 17 /*!< SYSCON STARTER0: PWM0 Position */
-#define SYSCON_STARTER0_PWM0_Msk (0x01UL << SYSCON_STARTER0_PWM0_Pos) /*!< SYSCON STARTER0: PWM0 Mask */
-#define SYSCON_STARTER0_PWM1_Pos 18 /*!< SYSCON STARTER0: PWM1 Position */
-#define SYSCON_STARTER0_PWM1_Msk (0x01UL << SYSCON_STARTER0_PWM1_Pos) /*!< SYSCON STARTER0: PWM1 Mask */
-#define SYSCON_STARTER0_PWM2_Pos 19 /*!< SYSCON STARTER0: PWM2 Position */
-#define SYSCON_STARTER0_PWM2_Msk (0x01UL << SYSCON_STARTER0_PWM2_Pos) /*!< SYSCON STARTER0: PWM2 Mask */
-#define SYSCON_STARTER0_PWM3_Pos 20 /*!< SYSCON STARTER0: PWM3 Position */
-#define SYSCON_STARTER0_PWM3_Msk (0x01UL << SYSCON_STARTER0_PWM3_Pos) /*!< SYSCON STARTER0: PWM3 Mask */
-#define SYSCON_STARTER0_PWM4_Pos 21 /*!< SYSCON STARTER0: PWM4 Position */
-#define SYSCON_STARTER0_PWM4_Msk (0x01UL << SYSCON_STARTER0_PWM4_Pos) /*!< SYSCON STARTER0: PWM4 Mask */
-#define SYSCON_STARTER0_PWM5_Pos 22 /*!< SYSCON STARTER0: PWM5 Position */
-#define SYSCON_STARTER0_PWM5_Msk (0x01UL << SYSCON_STARTER0_PWM5_Pos) /*!< SYSCON STARTER0: PWM5 Mask */
-#define SYSCON_STARTER0_PWM6_Pos 23 /*!< SYSCON STARTER0: PWM6 Position */
-#define SYSCON_STARTER0_PWM6_Msk (0x01UL << SYSCON_STARTER0_PWM6_Pos) /*!< SYSCON STARTER0: PWM6 Mask */
-#define SYSCON_STARTER0_PWM7_Pos 24 /*!< SYSCON STARTER0: PWM7 Position */
-#define SYSCON_STARTER0_PWM7_Msk (0x01UL << SYSCON_STARTER0_PWM7_Pos) /*!< SYSCON STARTER0: PWM7 Mask */
-#define SYSCON_STARTER0_PWM8_Pos 25 /*!< SYSCON STARTER0: PWM8 Position */
-#define SYSCON_STARTER0_PWM8_Msk (0x01UL << SYSCON_STARTER0_PWM8_Pos) /*!< SYSCON STARTER0: PWM8 Mask */
-#define SYSCON_STARTER0_PWM9_Pos 26 /*!< SYSCON STARTER0: PWM9 Position */
-#define SYSCON_STARTER0_PWM9_Msk (0x01UL << SYSCON_STARTER0_PWM9_Pos) /*!< SYSCON STARTER0: PWM9 Mask */
-#define SYSCON_STARTER0_PWM10_Pos 27 /*!< SYSCON STARTER0: PWM10 Position */
-#define SYSCON_STARTER0_PWM10_Msk (0x01UL << SYSCON_STARTER0_PWM10_Pos) /*!< SYSCON STARTER0: PWM10 Mask */
-#define SYSCON_STARTER0_I2C2_Pos 28 /*!< SYSCON STARTER0: I2C2 Position */
-#define SYSCON_STARTER0_I2C2_Msk (0x01UL << SYSCON_STARTER0_I2C2_Pos) /*!< SYSCON STARTER0: I2C2 Mask */
-#define SYSCON_STARTER0_RTC_Pos 29 /*!< SYSCON STARTER0: RTC Position */
-#define SYSCON_STARTER0_RTC_Msk (0x01UL << SYSCON_STARTER0_RTC_Pos) /*!< SYSCON STARTER0: RTC Mask */
-#define SYSCON_STARTER0_NFCTAG_Pos 30 /*!< SYSCON STARTER0: NFCTAG Position */
-#define SYSCON_STARTER0_NFCTAG_Msk (0x01UL << SYSCON_STARTER0_NFCTAG_Pos) /*!< SYSCON STARTER0: NFCTAG Mask */
-#define SYSCON_STARTER0_MAILBOX_Pos 31 /*!< SYSCON STARTER0: MAILBOX Position */
-#define SYSCON_STARTER0_MAILBOX_Msk (0x01UL << SYSCON_STARTER0_MAILBOX_Pos) /*!< SYSCON STARTER0: MAILBOX Mask */
-
-/* ------------------------------ u_syscon_STARTER1 ----------------------------- */
-#define SYSCON_STARTER1_ADC_SEQA_Pos 0 /*!< SYSCON STARTER1: ADC_SEQA Position */
-#define SYSCON_STARTER1_ADC_SEQA_Msk (0x01UL << SYSCON_STARTER1_ADC_SEQA_Pos) /*!< SYSCON STARTER1: ADC_SEQA Mask */
-#define SYSCON_STARTER1_ADC_SEQB_Pos 1 /*!< SYSCON STARTER1: ADC_SEQB Position */
-#define SYSCON_STARTER1_ADC_SEQB_Msk (0x01UL << SYSCON_STARTER1_ADC_SEQB_Pos) /*!< SYSCON STARTER1: ADC_SEQB Mask */
-#define SYSCON_STARTER1_ADC_THCMP_OVR_Pos 2 /*!< SYSCON STARTER1: ADC_THCMP_OVR Position */
-#define SYSCON_STARTER1_ADC_THCMP_OVR_Msk (0x01UL << SYSCON_STARTER1_ADC_THCMP_OVR_Pos) /*!< SYSCON STARTER1: ADC_THCMP_OVR Mask */
-#define SYSCON_STARTER1_DMIC_Pos 3 /*!< SYSCON STARTER1: DMIC Position */
-#define SYSCON_STARTER1_DMIC_Msk (0x01UL << SYSCON_STARTER1_DMIC_Pos) /*!< SYSCON STARTER1: DMIC Mask */
-#define SYSCON_STARTER1_HWVAD_Pos 4 /*!< SYSCON STARTER1: HWVAD Position */
-#define SYSCON_STARTER1_HWVAD_Msk (0x01UL << SYSCON_STARTER1_HWVAD_Pos) /*!< SYSCON STARTER1: HWVAD Mask */
-#define SYSCON_STARTER1_BLE_DP_Pos 5 /*!< SYSCON STARTER1: BLE_DP Position */
-#define SYSCON_STARTER1_BLE_DP_Msk (0x01UL << SYSCON_STARTER1_BLE_DP_Pos) /*!< SYSCON STARTER1: BLE_DP Mask */
-#define SYSCON_STARTER1_BLE_DP0_Pos 6 /*!< SYSCON STARTER1: BLE_DP0 Position */
-#define SYSCON_STARTER1_BLE_DP0_Msk (0x01UL << SYSCON_STARTER1_BLE_DP0_Pos) /*!< SYSCON STARTER1: BLE_DP0 Mask */
-#define SYSCON_STARTER1_BLE_DP1_Pos 7 /*!< SYSCON STARTER1: BLE_DP1 Position */
-#define SYSCON_STARTER1_BLE_DP1_Msk (0x01UL << SYSCON_STARTER1_BLE_DP1_Pos) /*!< SYSCON STARTER1: BLE_DP1 Mask */
-#define SYSCON_STARTER1_BLE_DP2_Pos 8 /*!< SYSCON STARTER1: BLE_DP2 Position */
-#define SYSCON_STARTER1_BLE_DP2_Msk (0x01UL << SYSCON_STARTER1_BLE_DP2_Pos) /*!< SYSCON STARTER1: BLE_DP2 Mask */
-#define SYSCON_STARTER1_BLE_LL_ALL_Pos 9 /*!< SYSCON STARTER1: BLE_LL_ALL Position */
-#define SYSCON_STARTER1_BLE_LL_ALL_Msk (0x01UL << SYSCON_STARTER1_BLE_LL_ALL_Pos) /*!< SYSCON STARTER1: BLE_LL_ALL Mask */
-#define SYSCON_STARTER1_ZIGBEE_MAC_Pos 10 /*!< SYSCON STARTER1: ZIGBEE_MAC Position */
-#define SYSCON_STARTER1_ZIGBEE_MAC_Msk (0x01UL << SYSCON_STARTER1_ZIGBEE_MAC_Pos) /*!< SYSCON STARTER1: ZIGBEE_MAC Mask */
-#define SYSCON_STARTER1_ZIGBEE_MODEM_Pos 11 /*!< SYSCON STARTER1: ZIGBEE_MODEM Position */
-#define SYSCON_STARTER1_ZIGBEE_MODEM_Msk (0x01UL << SYSCON_STARTER1_ZIGBEE_MODEM_Pos) /*!< SYSCON STARTER1: ZIGBEE_MODEM Mask */
-#define SYSCON_STARTER1_RFP_TMU_Pos 12 /*!< SYSCON STARTER1: RFP_TMU Position */
-#define SYSCON_STARTER1_RFP_TMU_Msk (0x01UL << SYSCON_STARTER1_RFP_TMU_Pos) /*!< SYSCON STARTER1: RFP_TMU Mask */
-#define SYSCON_STARTER1_RFP_AGC_Pos 13 /*!< SYSCON STARTER1: RFP_AGC Position */
-#define SYSCON_STARTER1_RFP_AGC_Msk (0x01UL << SYSCON_STARTER1_RFP_AGC_Pos) /*!< SYSCON STARTER1: RFP_AGC Mask */
-#define SYSCON_STARTER1_ISO7816_Pos 14 /*!< SYSCON STARTER1: ISO7816 Position */
-#define SYSCON_STARTER1_ISO7816_Msk (0x01UL << SYSCON_STARTER1_ISO7816_Pos) /*!< SYSCON STARTER1: ISO7816 Mask */
-#define SYSCON_STARTER1_ANA_COMP_Pos 15 /*!< SYSCON STARTER1: ANA_COMP Position */
-#define SYSCON_STARTER1_ANA_COMP_Msk (0x01UL << SYSCON_STARTER1_ANA_COMP_Pos) /*!< SYSCON STARTER1: ANA_COMP Mask */
-#define SYSCON_STARTER1_WAKE_UP_TIMER0_Pos 16 /*!< SYSCON STARTER1: WAKE_UP_TIMER0 Position */
-#define SYSCON_STARTER1_WAKE_UP_TIMER0_Msk (0x01UL << SYSCON_STARTER1_WAKE_UP_TIMER0_Pos) /*!< SYSCON STARTER1: WAKE_UP_TIMER0 Mask */
-#define SYSCON_STARTER1_WAKE_UP_TIMER1_Pos 17 /*!< SYSCON STARTER1: WAKE_UP_TIMER1 Position */
-#define SYSCON_STARTER1_WAKE_UP_TIMER1_Msk (0x01UL << SYSCON_STARTER1_WAKE_UP_TIMER1_Pos) /*!< SYSCON STARTER1: WAKE_UP_TIMER1 Mask */
-#define SYSCON_STARTER1_BLE_WAKE_UP_TIMER_Pos 22 /*!< SYSCON STARTER1: BLE_WAKE_UP_TIMER Position */
-#define SYSCON_STARTER1_BLE_WAKE_UP_TIMER_Msk (0x01UL << SYSCON_STARTER1_BLE_WAKE_UP_TIMER_Pos) /*!< SYSCON STARTER1: BLE_WAKE_UP_TIMER Mask */
-#define SYSCON_STARTER1_BLE_OSC_EN_Pos 23 /*!< SYSCON STARTER1: BLE_OSC_EN Position */
-#define SYSCON_STARTER1_BLE_OSC_EN_Msk (0x01UL << SYSCON_STARTER1_BLE_OSC_EN_Pos) /*!< SYSCON STARTER1: BLE_OSC_EN Mask */
-#define SYSCON_STARTER1_GPIO_Pos 31 /*!< SYSCON STARTER1: GPIO Position */
-#define SYSCON_STARTER1_GPIO_Msk (0x01UL << SYSCON_STARTER1_GPIO_Pos) /*!< SYSCON STARTER1: GPIO Mask */
-
-/* ---------------------------- u_syscon_STARTERSET0 ---------------------------- */
-#define SYSCON_STARTERSET0_WDT_BOD_SET_Pos 0 /*!< SYSCON STARTERSET0: WDT_BOD_SET Position */
-#define SYSCON_STARTERSET0_WDT_BOD_SET_Msk (0x01UL << SYSCON_STARTERSET0_WDT_BOD_SET_Pos) /*!< SYSCON STARTERSET0: WDT_BOD_SET Mask */
-#define SYSCON_STARTERSET0_DMA_SET_Pos 1 /*!< SYSCON STARTERSET0: DMA_SET Position */
-#define SYSCON_STARTERSET0_DMA_SET_Msk (0x01UL << SYSCON_STARTERSET0_DMA_SET_Pos) /*!< SYSCON STARTERSET0: DMA_SET Mask */
-#define SYSCON_STARTERSET0_GINT_SET_Pos 2 /*!< SYSCON STARTERSET0: GINT_SET Position */
-#define SYSCON_STARTERSET0_GINT_SET_Msk (0x01UL << SYSCON_STARTERSET0_GINT_SET_Pos) /*!< SYSCON STARTERSET0: GINT_SET Mask */
-#define SYSCON_STARTERSET0_IRBLASTER_SET_Pos 3 /*!< SYSCON STARTERSET0: IRBLASTER_SET Position */
-#define SYSCON_STARTERSET0_IRBLASTER_SET_Msk (0x01UL << SYSCON_STARTERSET0_IRBLASTER_SET_Pos) /*!< SYSCON STARTERSET0: IRBLASTER_SET Mask */
-#define SYSCON_STARTERSET0_PINT0_SET_Pos 4 /*!< SYSCON STARTERSET0: PINT0_SET Position */
-#define SYSCON_STARTERSET0_PINT0_SET_Msk (0x01UL << SYSCON_STARTERSET0_PINT0_SET_Pos) /*!< SYSCON STARTERSET0: PINT0_SET Mask */
-#define SYSCON_STARTERSET0_PINT1_SET_Pos 5 /*!< SYSCON STARTERSET0: PINT1_SET Position */
-#define SYSCON_STARTERSET0_PINT1_SET_Msk (0x01UL << SYSCON_STARTERSET0_PINT1_SET_Pos) /*!< SYSCON STARTERSET0: PINT1_SET Mask */
-#define SYSCON_STARTERSET0_PINT2_SET_Pos 6 /*!< SYSCON STARTERSET0: PINT2_SET Position */
-#define SYSCON_STARTERSET0_PINT2_SET_Msk (0x01UL << SYSCON_STARTERSET0_PINT2_SET_Pos) /*!< SYSCON STARTERSET0: PINT2_SET Mask */
-#define SYSCON_STARTERSET0_PINT3_SET_Pos 7 /*!< SYSCON STARTERSET0: PINT3_SET Position */
-#define SYSCON_STARTERSET0_PINT3_SET_Msk (0x01UL << SYSCON_STARTERSET0_PINT3_SET_Pos) /*!< SYSCON STARTERSET0: PINT3_SET Mask */
-#define SYSCON_STARTERSET0_SPIFI_SET_Pos 8 /*!< SYSCON STARTERSET0: SPIFI_SET Position */
-#define SYSCON_STARTERSET0_SPIFI_SET_Msk (0x01UL << SYSCON_STARTERSET0_SPIFI_SET_Pos) /*!< SYSCON STARTERSET0: SPIFI_SET Mask */
-#define SYSCON_STARTERSET0_TIMER0_SET_Pos 9 /*!< SYSCON STARTERSET0: TIMER0_SET Position */
-#define SYSCON_STARTERSET0_TIMER0_SET_Msk (0x01UL << SYSCON_STARTERSET0_TIMER0_SET_Pos) /*!< SYSCON STARTERSET0: TIMER0_SET Mask */
-#define SYSCON_STARTERSET0_TIMER1_SET_Pos 10 /*!< SYSCON STARTERSET0: TIMER1_SET Position */
-#define SYSCON_STARTERSET0_TIMER1_SET_Msk (0x01UL << SYSCON_STARTERSET0_TIMER1_SET_Pos) /*!< SYSCON STARTERSET0: TIMER1_SET Mask */
-#define SYSCON_STARTERSET0_USART0_SET_Pos 11 /*!< SYSCON STARTERSET0: USART0_SET Position */
-#define SYSCON_STARTERSET0_USART0_SET_Msk (0x01UL << SYSCON_STARTERSET0_USART0_SET_Pos) /*!< SYSCON STARTERSET0: USART0_SET Mask */
-#define SYSCON_STARTERSET0_USART1_SET_Pos 12 /*!< SYSCON STARTERSET0: USART1_SET Position */
-#define SYSCON_STARTERSET0_USART1_SET_Msk (0x01UL << SYSCON_STARTERSET0_USART1_SET_Pos) /*!< SYSCON STARTERSET0: USART1_SET Mask */
-#define SYSCON_STARTERSET0_I2C0_SET_Pos 13 /*!< SYSCON STARTERSET0: I2C0_SET Position */
-#define SYSCON_STARTERSET0_I2C0_SET_Msk (0x01UL << SYSCON_STARTERSET0_I2C0_SET_Pos) /*!< SYSCON STARTERSET0: I2C0_SET Mask */
-#define SYSCON_STARTERSET0_I2C1_SET_Pos 14 /*!< SYSCON STARTERSET0: I2C1_SET Position */
-#define SYSCON_STARTERSET0_I2C1_SET_Msk (0x01UL << SYSCON_STARTERSET0_I2C1_SET_Pos) /*!< SYSCON STARTERSET0: I2C1_SET Mask */
-#define SYSCON_STARTERSET0_SPI0_SET_Pos 15 /*!< SYSCON STARTERSET0: SPI0_SET Position */
-#define SYSCON_STARTERSET0_SPI0_SET_Msk (0x01UL << SYSCON_STARTERSET0_SPI0_SET_Pos) /*!< SYSCON STARTERSET0: SPI0_SET Mask */
-#define SYSCON_STARTERSET0_SPI1_SET_Pos 16 /*!< SYSCON STARTERSET0: SPI1_SET Position */
-#define SYSCON_STARTERSET0_SPI1_SET_Msk (0x01UL << SYSCON_STARTERSET0_SPI1_SET_Pos) /*!< SYSCON STARTERSET0: SPI1_SET Mask */
-#define SYSCON_STARTERSET0_PWM0_SET_Pos 17 /*!< SYSCON STARTERSET0: PWM0_SET Position */
-#define SYSCON_STARTERSET0_PWM0_SET_Msk (0x01UL << SYSCON_STARTERSET0_PWM0_SET_Pos) /*!< SYSCON STARTERSET0: PWM0_SET Mask */
-#define SYSCON_STARTERSET0_PWM1_SET_Pos 18 /*!< SYSCON STARTERSET0: PWM1_SET Position */
-#define SYSCON_STARTERSET0_PWM1_SET_Msk (0x01UL << SYSCON_STARTERSET0_PWM1_SET_Pos) /*!< SYSCON STARTERSET0: PWM1_SET Mask */
-#define SYSCON_STARTERSET0_PWM2_SET_Pos 19 /*!< SYSCON STARTERSET0: PWM2_SET Position */
-#define SYSCON_STARTERSET0_PWM2_SET_Msk (0x01UL << SYSCON_STARTERSET0_PWM2_SET_Pos) /*!< SYSCON STARTERSET0: PWM2_SET Mask */
-#define SYSCON_STARTERSET0_PWM3_SET_Pos 20 /*!< SYSCON STARTERSET0: PWM3_SET Position */
-#define SYSCON_STARTERSET0_PWM3_SET_Msk (0x01UL << SYSCON_STARTERSET0_PWM3_SET_Pos) /*!< SYSCON STARTERSET0: PWM3_SET Mask */
-#define SYSCON_STARTERSET0_PWM4_SET_Pos 21 /*!< SYSCON STARTERSET0: PWM4_SET Position */
-#define SYSCON_STARTERSET0_PWM4_SET_Msk (0x01UL << SYSCON_STARTERSET0_PWM4_SET_Pos) /*!< SYSCON STARTERSET0: PWM4_SET Mask */
-#define SYSCON_STARTERSET0_PWM5_SET_Pos 22 /*!< SYSCON STARTERSET0: PWM5_SET Position */
-#define SYSCON_STARTERSET0_PWM5_SET_Msk (0x01UL << SYSCON_STARTERSET0_PWM5_SET_Pos) /*!< SYSCON STARTERSET0: PWM5_SET Mask */
-#define SYSCON_STARTERSET0_PWM6_SET_Pos 23 /*!< SYSCON STARTERSET0: PWM6_SET Position */
-#define SYSCON_STARTERSET0_PWM6_SET_Msk (0x01UL << SYSCON_STARTERSET0_PWM6_SET_Pos) /*!< SYSCON STARTERSET0: PWM6_SET Mask */
-#define SYSCON_STARTERSET0_PWM7_SET_Pos 24 /*!< SYSCON STARTERSET0: PWM7_SET Position */
-#define SYSCON_STARTERSET0_PWM7_SET_Msk (0x01UL << SYSCON_STARTERSET0_PWM7_SET_Pos) /*!< SYSCON STARTERSET0: PWM7_SET Mask */
-#define SYSCON_STARTERSET0_PWM8_SET_Pos 25 /*!< SYSCON STARTERSET0: PWM8_SET Position */
-#define SYSCON_STARTERSET0_PWM8_SET_Msk (0x01UL << SYSCON_STARTERSET0_PWM8_SET_Pos) /*!< SYSCON STARTERSET0: PWM8_SET Mask */
-#define SYSCON_STARTERSET0_PWM9_SET_Pos 26 /*!< SYSCON STARTERSET0: PWM9_SET Position */
-#define SYSCON_STARTERSET0_PWM9_SET_Msk (0x01UL << SYSCON_STARTERSET0_PWM9_SET_Pos) /*!< SYSCON STARTERSET0: PWM9_SET Mask */
-#define SYSCON_STARTERSET0_PWM10_SET_Pos 27 /*!< SYSCON STARTERSET0: PWM10_SET Position */
-#define SYSCON_STARTERSET0_PWM10_SET_Msk (0x01UL << SYSCON_STARTERSET0_PWM10_SET_Pos) /*!< SYSCON STARTERSET0: PWM10_SET Mask */
-#define SYSCON_STARTERSET0_I2C2_SET_Pos 28 /*!< SYSCON STARTERSET0: I2C2_SET Position */
-#define SYSCON_STARTERSET0_I2C2_SET_Msk (0x01UL << SYSCON_STARTERSET0_I2C2_SET_Pos) /*!< SYSCON STARTERSET0: I2C2_SET Mask */
-#define SYSCON_STARTERSET0_RTC_SET_Pos 29 /*!< SYSCON STARTERSET0: RTC_SET Position */
-#define SYSCON_STARTERSET0_RTC_SET_Msk (0x01UL << SYSCON_STARTERSET0_RTC_SET_Pos) /*!< SYSCON STARTERSET0: RTC_SET Mask */
-#define SYSCON_STARTERSET0_NFCTAG_SET_Pos 30 /*!< SYSCON STARTERSET0: NFCTAG_SET Position */
-#define SYSCON_STARTERSET0_NFCTAG_SET_Msk (0x01UL << SYSCON_STARTERSET0_NFCTAG_SET_Pos) /*!< SYSCON STARTERSET0: NFCTAG_SET Mask */
-#define SYSCON_STARTERSET0_MAILBOX_SET_Pos 31 /*!< SYSCON STARTERSET0: MAILBOX_SET Position */
-#define SYSCON_STARTERSET0_MAILBOX_SET_Msk (0x01UL << SYSCON_STARTERSET0_MAILBOX_SET_Pos) /*!< SYSCON STARTERSET0: MAILBOX_SET Mask */
-
-/* ---------------------------- u_syscon_STARTERSET1 ---------------------------- */
-#define SYSCON_STARTERSET1_ADC_SEQA_SET_Pos 0 /*!< SYSCON STARTERSET1: ADC_SEQA_SET Position */
-#define SYSCON_STARTERSET1_ADC_SEQA_SET_Msk (0x01UL << SYSCON_STARTERSET1_ADC_SEQA_SET_Pos) /*!< SYSCON STARTERSET1: ADC_SEQA_SET Mask */
-#define SYSCON_STARTERSET1_ADC_SEQB_SET_Pos 1 /*!< SYSCON STARTERSET1: ADC_SEQB_SET Position */
-#define SYSCON_STARTERSET1_ADC_SEQB_SET_Msk (0x01UL << SYSCON_STARTERSET1_ADC_SEQB_SET_Pos) /*!< SYSCON STARTERSET1: ADC_SEQB_SET Mask */
-#define SYSCON_STARTERSET1_ADC_THCMP_OVR_SET_Pos 2 /*!< SYSCON STARTERSET1: ADC_THCMP_OVR_SET Position */
-#define SYSCON_STARTERSET1_ADC_THCMP_OVR_SET_Msk (0x01UL << SYSCON_STARTERSET1_ADC_THCMP_OVR_SET_Pos)/*!< SYSCON STARTERSET1: ADC_THCMP_OVR_SET Mask */
-#define SYSCON_STARTERSET1_DMIC_SET_Pos 3 /*!< SYSCON STARTERSET1: DMIC_SET Position */
-#define SYSCON_STARTERSET1_DMIC_SET_Msk (0x01UL << SYSCON_STARTERSET1_DMIC_SET_Pos) /*!< SYSCON STARTERSET1: DMIC_SET Mask */
-#define SYSCON_STARTERSET1_HWVAD_SET_Pos 4 /*!< SYSCON STARTERSET1: HWVAD_SET Position */
-#define SYSCON_STARTERSET1_HWVAD_SET_Msk (0x01UL << SYSCON_STARTERSET1_HWVAD_SET_Pos) /*!< SYSCON STARTERSET1: HWVAD_SET Mask */
-#define SYSCON_STARTERSET1_BLE_DP_SET_Pos 5 /*!< SYSCON STARTERSET1: BLE_DP_SET Position */
-#define SYSCON_STARTERSET1_BLE_DP_SET_Msk (0x01UL << SYSCON_STARTERSET1_BLE_DP_SET_Pos) /*!< SYSCON STARTERSET1: BLE_DP_SET Mask */
-#define SYSCON_STARTERSET1_BLE_DP0_SET_Pos 6 /*!< SYSCON STARTERSET1: BLE_DP0_SET Position */
-#define SYSCON_STARTERSET1_BLE_DP0_SET_Msk (0x01UL << SYSCON_STARTERSET1_BLE_DP0_SET_Pos) /*!< SYSCON STARTERSET1: BLE_DP0_SET Mask */
-#define SYSCON_STARTERSET1_BLE_DP1_SET_Pos 7 /*!< SYSCON STARTERSET1: BLE_DP1_SET Position */
-#define SYSCON_STARTERSET1_BLE_DP1_SET_Msk (0x01UL << SYSCON_STARTERSET1_BLE_DP1_SET_Pos) /*!< SYSCON STARTERSET1: BLE_DP1_SET Mask */
-#define SYSCON_STARTERSET1_BLE_DP2_SET_Pos 8 /*!< SYSCON STARTERSET1: BLE_DP2_SET Position */
-#define SYSCON_STARTERSET1_BLE_DP2_SET_Msk (0x01UL << SYSCON_STARTERSET1_BLE_DP2_SET_Pos) /*!< SYSCON STARTERSET1: BLE_DP2_SET Mask */
-#define SYSCON_STARTERSET1_BLE_LL_ALL_SET_Pos 9 /*!< SYSCON STARTERSET1: BLE_LL_ALL_SET Position */
-#define SYSCON_STARTERSET1_BLE_LL_ALL_SET_Msk (0x01UL << SYSCON_STARTERSET1_BLE_LL_ALL_SET_Pos) /*!< SYSCON STARTERSET1: BLE_LL_ALL_SET Mask */
-#define SYSCON_STARTERSET1_ZIGBEE_MAC_SET_Pos 10 /*!< SYSCON STARTERSET1: ZIGBEE_MAC_SET Position */
-#define SYSCON_STARTERSET1_ZIGBEE_MAC_SET_Msk (0x01UL << SYSCON_STARTERSET1_ZIGBEE_MAC_SET_Pos) /*!< SYSCON STARTERSET1: ZIGBEE_MAC_SET Mask */
-#define SYSCON_STARTERSET1_ZIGBEE_MODEM_SET_Pos 11 /*!< SYSCON STARTERSET1: ZIGBEE_MODEM_SET Position */
-#define SYSCON_STARTERSET1_ZIGBEE_MODEM_SET_Msk (0x01UL << SYSCON_STARTERSET1_ZIGBEE_MODEM_SET_Pos)/*!< SYSCON STARTERSET1: ZIGBEE_MODEM_SET Mask */
-#define SYSCON_STARTERSET1_RFP_TMU_SET_Pos 12 /*!< SYSCON STARTERSET1: RFP_TMU_SET Position */
-#define SYSCON_STARTERSET1_RFP_TMU_SET_Msk (0x01UL << SYSCON_STARTERSET1_RFP_TMU_SET_Pos) /*!< SYSCON STARTERSET1: RFP_TMU_SET Mask */
-#define SYSCON_STARTERSET1_RFP_AGC_SET_Pos 13 /*!< SYSCON STARTERSET1: RFP_AGC_SET Position */
-#define SYSCON_STARTERSET1_RFP_AGC_SET_Msk (0x01UL << SYSCON_STARTERSET1_RFP_AGC_SET_Pos) /*!< SYSCON STARTERSET1: RFP_AGC_SET Mask */
-#define SYSCON_STARTERSET1_ISO7816_SET_Pos 14 /*!< SYSCON STARTERSET1: ISO7816_SET Position */
-#define SYSCON_STARTERSET1_ISO7816_SET_Msk (0x01UL << SYSCON_STARTERSET1_ISO7816_SET_Pos) /*!< SYSCON STARTERSET1: ISO7816_SET Mask */
-#define SYSCON_STARTERSET1_ANA_COMP_SET_Pos 15 /*!< SYSCON STARTERSET1: ANA_COMP_SET Position */
-#define SYSCON_STARTERSET1_ANA_COMP_SET_Msk (0x01UL << SYSCON_STARTERSET1_ANA_COMP_SET_Pos) /*!< SYSCON STARTERSET1: ANA_COMP_SET Mask */
-#define SYSCON_STARTERSET1_WAKE_UP_TIMER0_SET_Pos 16 /*!< SYSCON STARTERSET1: WAKE_UP_TIMER0_SET Position */
-#define SYSCON_STARTERSET1_WAKE_UP_TIMER0_SET_Msk (0x01UL << SYSCON_STARTERSET1_WAKE_UP_TIMER0_SET_Pos)/*!< SYSCON STARTERSET1: WAKE_UP_TIMER0_SET Mask */
-#define SYSCON_STARTERSET1_WAKE_UP_TIMER1_SET_Pos 17 /*!< SYSCON STARTERSET1: WAKE_UP_TIMER1_SET Position */
-#define SYSCON_STARTERSET1_WAKE_UP_TIMER1_SET_Msk (0x01UL << SYSCON_STARTERSET1_WAKE_UP_TIMER1_SET_Pos)/*!< SYSCON STARTERSET1: WAKE_UP_TIMER1_SET Mask */
-#define SYSCON_STARTERSET1_BLE_WAKE_UP_TIMER_SET_Pos 22 /*!< SYSCON STARTERSET1: BLE_WAKE_UP_TIMER_SET Position */
-#define SYSCON_STARTERSET1_BLE_WAKE_UP_TIMER_SET_Msk (0x01UL << SYSCON_STARTERSET1_BLE_WAKE_UP_TIMER_SET_Pos)/*!< SYSCON STARTERSET1: BLE_WAKE_UP_TIMER_SET Mask */
-
-/* ---------------------------- u_syscon_STARTERCLR0 ---------------------------- */
-#define SYSCON_STARTERCLR0_WDT_BOD_CLR_Pos 0 /*!< SYSCON STARTERCLR0: WDT_BOD_CLR Position */
-#define SYSCON_STARTERCLR0_WDT_BOD_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_WDT_BOD_CLR_Pos) /*!< SYSCON STARTERCLR0: WDT_BOD_CLR Mask */
-#define SYSCON_STARTERCLR0_DMA_CLR_Pos 1 /*!< SYSCON STARTERCLR0: DMA_CLR Position */
-#define SYSCON_STARTERCLR0_DMA_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_DMA_CLR_Pos) /*!< SYSCON STARTERCLR0: DMA_CLR Mask */
-#define SYSCON_STARTERCLR0_GINT_CLR_Pos 2 /*!< SYSCON STARTERCLR0: GINT_CLR Position */
-#define SYSCON_STARTERCLR0_GINT_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_GINT_CLR_Pos) /*!< SYSCON STARTERCLR0: GINT_CLR Mask */
-#define SYSCON_STARTERCLR0_IRBLASTER_CLR_Pos 3 /*!< SYSCON STARTERCLR0: IRBLASTER_CLR Position */
-#define SYSCON_STARTERCLR0_IRBLASTER_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_IRBLASTER_CLR_Pos) /*!< SYSCON STARTERCLR0: IRBLASTER_CLR Mask */
-#define SYSCON_STARTERCLR0_PINT0_CLR_Pos 4 /*!< SYSCON STARTERCLR0: PINT0_CLR Position */
-#define SYSCON_STARTERCLR0_PINT0_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_PINT0_CLR_Pos) /*!< SYSCON STARTERCLR0: PINT0_CLR Mask */
-#define SYSCON_STARTERCLR0_PINT1_CLR_Pos 5 /*!< SYSCON STARTERCLR0: PINT1_CLR Position */
-#define SYSCON_STARTERCLR0_PINT1_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_PINT1_CLR_Pos) /*!< SYSCON STARTERCLR0: PINT1_CLR Mask */
-#define SYSCON_STARTERCLR0_PINT2_CLR_Pos 6 /*!< SYSCON STARTERCLR0: PINT2_CLR Position */
-#define SYSCON_STARTERCLR0_PINT2_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_PINT2_CLR_Pos) /*!< SYSCON STARTERCLR0: PINT2_CLR Mask */
-#define SYSCON_STARTERCLR0_PINT3_CLR_Pos 7 /*!< SYSCON STARTERCLR0: PINT3_CLR Position */
-#define SYSCON_STARTERCLR0_PINT3_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_PINT3_CLR_Pos) /*!< SYSCON STARTERCLR0: PINT3_CLR Mask */
-#define SYSCON_STARTERCLR0_SPIFI_CLR_Pos 8 /*!< SYSCON STARTERCLR0: SPIFI_CLR Position */
-#define SYSCON_STARTERCLR0_SPIFI_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_SPIFI_CLR_Pos) /*!< SYSCON STARTERCLR0: SPIFI_CLR Mask */
-#define SYSCON_STARTERCLR0_TIMER0_CLR_Pos 9 /*!< SYSCON STARTERCLR0: TIMER0_CLR Position */
-#define SYSCON_STARTERCLR0_TIMER0_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_TIMER0_CLR_Pos) /*!< SYSCON STARTERCLR0: TIMER0_CLR Mask */
-#define SYSCON_STARTERCLR0_TIMER1_CLR_Pos 10 /*!< SYSCON STARTERCLR0: TIMER1_CLR Position */
-#define SYSCON_STARTERCLR0_TIMER1_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_TIMER1_CLR_Pos) /*!< SYSCON STARTERCLR0: TIMER1_CLR Mask */
-#define SYSCON_STARTERCLR0_USART0_CLR_Pos 11 /*!< SYSCON STARTERCLR0: USART0_CLR Position */
-#define SYSCON_STARTERCLR0_USART0_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_USART0_CLR_Pos) /*!< SYSCON STARTERCLR0: USART0_CLR Mask */
-#define SYSCON_STARTERCLR0_USART1_CLR_Pos 12 /*!< SYSCON STARTERCLR0: USART1_CLR Position */
-#define SYSCON_STARTERCLR0_USART1_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_USART1_CLR_Pos) /*!< SYSCON STARTERCLR0: USART1_CLR Mask */
-#define SYSCON_STARTERCLR0_I2C0_CLR_Pos 13 /*!< SYSCON STARTERCLR0: I2C0_CLR Position */
-#define SYSCON_STARTERCLR0_I2C0_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_I2C0_CLR_Pos) /*!< SYSCON STARTERCLR0: I2C0_CLR Mask */
-#define SYSCON_STARTERCLR0_I2C1_CLR_Pos 14 /*!< SYSCON STARTERCLR0: I2C1_CLR Position */
-#define SYSCON_STARTERCLR0_I2C1_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_I2C1_CLR_Pos) /*!< SYSCON STARTERCLR0: I2C1_CLR Mask */
-#define SYSCON_STARTERCLR0_SPI0_CLR_Pos 15 /*!< SYSCON STARTERCLR0: SPI0_CLR Position */
-#define SYSCON_STARTERCLR0_SPI0_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_SPI0_CLR_Pos) /*!< SYSCON STARTERCLR0: SPI0_CLR Mask */
-#define SYSCON_STARTERCLR0_SPI1_CLR_Pos 16 /*!< SYSCON STARTERCLR0: SPI1_CLR Position */
-#define SYSCON_STARTERCLR0_SPI1_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_SPI1_CLR_Pos) /*!< SYSCON STARTERCLR0: SPI1_CLR Mask */
-#define SYSCON_STARTERCLR0_PWM0_CLR_Pos 17 /*!< SYSCON STARTERCLR0: PWM0_CLR Position */
-#define SYSCON_STARTERCLR0_PWM0_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_PWM0_CLR_Pos) /*!< SYSCON STARTERCLR0: PWM0_CLR Mask */
-#define SYSCON_STARTERCLR0_PWM1_CLR_Pos 18 /*!< SYSCON STARTERCLR0: PWM1_CLR Position */
-#define SYSCON_STARTERCLR0_PWM1_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_PWM1_CLR_Pos) /*!< SYSCON STARTERCLR0: PWM1_CLR Mask */
-#define SYSCON_STARTERCLR0_PWM2_CLR_Pos 19 /*!< SYSCON STARTERCLR0: PWM2_CLR Position */
-#define SYSCON_STARTERCLR0_PWM2_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_PWM2_CLR_Pos) /*!< SYSCON STARTERCLR0: PWM2_CLR Mask */
-#define SYSCON_STARTERCLR0_PWM3_CLR_Pos 20 /*!< SYSCON STARTERCLR0: PWM3_CLR Position */
-#define SYSCON_STARTERCLR0_PWM3_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_PWM3_CLR_Pos) /*!< SYSCON STARTERCLR0: PWM3_CLR Mask */
-#define SYSCON_STARTERCLR0_PWM4_CLR_Pos 21 /*!< SYSCON STARTERCLR0: PWM4_CLR Position */
-#define SYSCON_STARTERCLR0_PWM4_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_PWM4_CLR_Pos) /*!< SYSCON STARTERCLR0: PWM4_CLR Mask */
-#define SYSCON_STARTERCLR0_PWM5_CLR_Pos 22 /*!< SYSCON STARTERCLR0: PWM5_CLR Position */
-#define SYSCON_STARTERCLR0_PWM5_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_PWM5_CLR_Pos) /*!< SYSCON STARTERCLR0: PWM5_CLR Mask */
-#define SYSCON_STARTERCLR0_PWM6_CLR_Pos 23 /*!< SYSCON STARTERCLR0: PWM6_CLR Position */
-#define SYSCON_STARTERCLR0_PWM6_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_PWM6_CLR_Pos) /*!< SYSCON STARTERCLR0: PWM6_CLR Mask */
-#define SYSCON_STARTERCLR0_PWM7_CLR_Pos 24 /*!< SYSCON STARTERCLR0: PWM7_CLR Position */
-#define SYSCON_STARTERCLR0_PWM7_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_PWM7_CLR_Pos) /*!< SYSCON STARTERCLR0: PWM7_CLR Mask */
-#define SYSCON_STARTERCLR0_PWM8_CLR_Pos 25 /*!< SYSCON STARTERCLR0: PWM8_CLR Position */
-#define SYSCON_STARTERCLR0_PWM8_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_PWM8_CLR_Pos) /*!< SYSCON STARTERCLR0: PWM8_CLR Mask */
-#define SYSCON_STARTERCLR0_PWM9_CLR_Pos 26 /*!< SYSCON STARTERCLR0: PWM9_CLR Position */
-#define SYSCON_STARTERCLR0_PWM9_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_PWM9_CLR_Pos) /*!< SYSCON STARTERCLR0: PWM9_CLR Mask */
-#define SYSCON_STARTERCLR0_PWM10_CLR_Pos 27 /*!< SYSCON STARTERCLR0: PWM10_CLR Position */
-#define SYSCON_STARTERCLR0_PWM10_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_PWM10_CLR_Pos) /*!< SYSCON STARTERCLR0: PWM10_CLR Mask */
-#define SYSCON_STARTERCLR0_I2C2_CLR_Pos 28 /*!< SYSCON STARTERCLR0: I2C2_CLR Position */
-#define SYSCON_STARTERCLR0_I2C2_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_I2C2_CLR_Pos) /*!< SYSCON STARTERCLR0: I2C2_CLR Mask */
-#define SYSCON_STARTERCLR0_RTC_CLR_Pos 29 /*!< SYSCON STARTERCLR0: RTC_CLR Position */
-#define SYSCON_STARTERCLR0_RTC_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_RTC_CLR_Pos) /*!< SYSCON STARTERCLR0: RTC_CLR Mask */
-#define SYSCON_STARTERCLR0_NFCTAG_CLR_Pos 30 /*!< SYSCON STARTERCLR0: NFCTAG_CLR Position */
-#define SYSCON_STARTERCLR0_NFCTAG_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_NFCTAG_CLR_Pos) /*!< SYSCON STARTERCLR0: NFCTAG_CLR Mask */
-#define SYSCON_STARTERCLR0_MAILBOX_CLR_Pos 31 /*!< SYSCON STARTERCLR0: MAILBOX_CLR Position */
-#define SYSCON_STARTERCLR0_MAILBOX_CLR_Msk (0x01UL << SYSCON_STARTERCLR0_MAILBOX_CLR_Pos) /*!< SYSCON STARTERCLR0: MAILBOX_CLR Mask */
-
-/* ---------------------------- u_syscon_STARTERCLR1 ---------------------------- */
-#define SYSCON_STARTERCLR1_ADC_SEQA_CLR_Pos 0 /*!< SYSCON STARTERCLR1: ADC_SEQA_CLR Position */
-#define SYSCON_STARTERCLR1_ADC_SEQA_CLR_Msk (0x01UL << SYSCON_STARTERCLR1_ADC_SEQA_CLR_Pos) /*!< SYSCON STARTERCLR1: ADC_SEQA_CLR Mask */
-#define SYSCON_STARTERCLR1_ADC_SEQB_CLR_Pos 1 /*!< SYSCON STARTERCLR1: ADC_SEQB_CLR Position */
-#define SYSCON_STARTERCLR1_ADC_SEQB_CLR_Msk (0x01UL << SYSCON_STARTERCLR1_ADC_SEQB_CLR_Pos) /*!< SYSCON STARTERCLR1: ADC_SEQB_CLR Mask */
-#define SYSCON_STARTERCLR1_ADC_THCMP_OVR_CLR_Pos 2 /*!< SYSCON STARTERCLR1: ADC_THCMP_OVR_CLR Position */
-#define SYSCON_STARTERCLR1_ADC_THCMP_OVR_CLR_Msk (0x01UL << SYSCON_STARTERCLR1_ADC_THCMP_OVR_CLR_Pos)/*!< SYSCON STARTERCLR1: ADC_THCMP_OVR_CLR Mask */
-#define SYSCON_STARTERCLR1_DMIC_CLR_Pos 3 /*!< SYSCON STARTERCLR1: DMIC_CLR Position */
-#define SYSCON_STARTERCLR1_DMIC_CLR_Msk (0x01UL << SYSCON_STARTERCLR1_DMIC_CLR_Pos) /*!< SYSCON STARTERCLR1: DMIC_CLR Mask */
-#define SYSCON_STARTERCLR1_HWVAD_CLR_Pos 4 /*!< SYSCON STARTERCLR1: HWVAD_CLR Position */
-#define SYSCON_STARTERCLR1_HWVAD_CLR_Msk (0x01UL << SYSCON_STARTERCLR1_HWVAD_CLR_Pos) /*!< SYSCON STARTERCLR1: HWVAD_CLR Mask */
-#define SYSCON_STARTERCLR1_BLE_DP_CLR_Pos 5 /*!< SYSCON STARTERCLR1: BLE_DP_CLR Position */
-#define SYSCON_STARTERCLR1_BLE_DP_CLR_Msk (0x01UL << SYSCON_STARTERCLR1_BLE_DP_CLR_Pos) /*!< SYSCON STARTERCLR1: BLE_DP_CLR Mask */
-#define SYSCON_STARTERCLR1_BLE_DP0_CLR_Pos 6 /*!< SYSCON STARTERCLR1: BLE_DP0_CLR Position */
-#define SYSCON_STARTERCLR1_BLE_DP0_CLR_Msk (0x01UL << SYSCON_STARTERCLR1_BLE_DP0_CLR_Pos) /*!< SYSCON STARTERCLR1: BLE_DP0_CLR Mask */
-#define SYSCON_STARTERCLR1_BLE_DP1_CLR_Pos 7 /*!< SYSCON STARTERCLR1: BLE_DP1_CLR Position */
-#define SYSCON_STARTERCLR1_BLE_DP1_CLR_Msk (0x01UL << SYSCON_STARTERCLR1_BLE_DP1_CLR_Pos) /*!< SYSCON STARTERCLR1: BLE_DP1_CLR Mask */
-#define SYSCON_STARTERCLR1_BLE_DP2_CLR_Pos 8 /*!< SYSCON STARTERCLR1: BLE_DP2_CLR Position */
-#define SYSCON_STARTERCLR1_BLE_DP2_CLR_Msk (0x01UL << SYSCON_STARTERCLR1_BLE_DP2_CLR_Pos) /*!< SYSCON STARTERCLR1: BLE_DP2_CLR Mask */
-#define SYSCON_STARTERCLR1_BLE_LL_ALL_CLR_Pos 9 /*!< SYSCON STARTERCLR1: BLE_LL_ALL_CLR Position */
-#define SYSCON_STARTERCLR1_BLE_LL_ALL_CLR_Msk (0x01UL << SYSCON_STARTERCLR1_BLE_LL_ALL_CLR_Pos) /*!< SYSCON STARTERCLR1: BLE_LL_ALL_CLR Mask */
-#define SYSCON_STARTERCLR1_ZIGBEE_MAC_CLR_Pos 10 /*!< SYSCON STARTERCLR1: ZIGBEE_MAC_CLR Position */
-#define SYSCON_STARTERCLR1_ZIGBEE_MAC_CLR_Msk (0x01UL << SYSCON_STARTERCLR1_ZIGBEE_MAC_CLR_Pos) /*!< SYSCON STARTERCLR1: ZIGBEE_MAC_CLR Mask */
-#define SYSCON_STARTERCLR1_ZIGBEE_MODEM_CLR_Pos 11 /*!< SYSCON STARTERCLR1: ZIGBEE_MODEM_CLR Position */
-#define SYSCON_STARTERCLR1_ZIGBEE_MODEM_CLR_Msk (0x01UL << SYSCON_STARTERCLR1_ZIGBEE_MODEM_CLR_Pos)/*!< SYSCON STARTERCLR1: ZIGBEE_MODEM_CLR Mask */
-#define SYSCON_STARTERCLR1_RFP_TMU_CLR_Pos 12 /*!< SYSCON STARTERCLR1: RFP_TMU_CLR Position */
-#define SYSCON_STARTERCLR1_RFP_TMU_CLR_Msk (0x01UL << SYSCON_STARTERCLR1_RFP_TMU_CLR_Pos) /*!< SYSCON STARTERCLR1: RFP_TMU_CLR Mask */
-#define SYSCON_STARTERCLR1_RFP_AGC_CLR_Pos 13 /*!< SYSCON STARTERCLR1: RFP_AGC_CLR Position */
-#define SYSCON_STARTERCLR1_RFP_AGC_CLR_Msk (0x01UL << SYSCON_STARTERCLR1_RFP_AGC_CLR_Pos) /*!< SYSCON STARTERCLR1: RFP_AGC_CLR Mask */
-#define SYSCON_STARTERCLR1_ISO7816_CLR_Pos 14 /*!< SYSCON STARTERCLR1: ISO7816_CLR Position */
-#define SYSCON_STARTERCLR1_ISO7816_CLR_Msk (0x01UL << SYSCON_STARTERCLR1_ISO7816_CLR_Pos) /*!< SYSCON STARTERCLR1: ISO7816_CLR Mask */
-#define SYSCON_STARTERCLR1_ANA_COMP_CLR_Pos 15 /*!< SYSCON STARTERCLR1: ANA_COMP_CLR Position */
-#define SYSCON_STARTERCLR1_ANA_COMP_CLR_Msk (0x01UL << SYSCON_STARTERCLR1_ANA_COMP_CLR_Pos) /*!< SYSCON STARTERCLR1: ANA_COMP_CLR Mask */
-#define SYSCON_STARTERCLR1_WAKE_UP_TIMER0_CLR_Pos 16 /*!< SYSCON STARTERCLR1: WAKE_UP_TIMER0_CLR Position */
-#define SYSCON_STARTERCLR1_WAKE_UP_TIMER0_CLR_Msk (0x01UL << SYSCON_STARTERCLR1_WAKE_UP_TIMER0_CLR_Pos)/*!< SYSCON STARTERCLR1: WAKE_UP_TIMER0_CLR Mask */
-#define SYSCON_STARTERCLR1_WAKE_UP_TIMER1_CLR_Pos 17 /*!< SYSCON STARTERCLR1: WAKE_UP_TIMER1_CLR Position */
-#define SYSCON_STARTERCLR1_WAKE_UP_TIMER1_CLR_Msk (0x01UL << SYSCON_STARTERCLR1_WAKE_UP_TIMER1_CLR_Pos)/*!< SYSCON STARTERCLR1: WAKE_UP_TIMER1_CLR Mask */
-#define SYSCON_STARTERCLR1_BLE_WAKE_UP_TIMER_CLR_Pos 22 /*!< SYSCON STARTERCLR1: BLE_WAKE_UP_TIMER_CLR Position */
-#define SYSCON_STARTERCLR1_BLE_WAKE_UP_TIMER_CLR_Msk (0x01UL << SYSCON_STARTERCLR1_BLE_WAKE_UP_TIMER_CLR_Pos)/*!< SYSCON STARTERCLR1: BLE_WAKE_UP_TIMER_CLR Mask */
-
-/* --------------------------- u_syscon_RETENTIONCTRL --------------------------- */
-#define SYSCON_RETENTIONCTRL_IOCLAMP_Pos 0 /*!< SYSCON RETENTIONCTRL: IOCLAMP Position */
-#define SYSCON_RETENTIONCTRL_IOCLAMP_Msk (0x01UL << SYSCON_RETENTIONCTRL_IOCLAMP_Pos) /*!< SYSCON RETENTIONCTRL: IOCLAMP Mask */
-
-/* -------------------------- u_syscon_POWERDOWNSAFETY -------------------------- */
-#define SYSCON_POWERDOWNSAFETY_OVERRIDEFRO_Pos 0 /*!< SYSCON POWERDOWNSAFETY: OVERRIDEFRO Position */
-#define SYSCON_POWERDOWNSAFETY_OVERRIDEFRO_Msk (0x01UL << SYSCON_POWERDOWNSAFETY_OVERRIDEFRO_Pos) /*!< SYSCON POWERDOWNSAFETY: OVERRIDEFRO Mask */
-
-/* --------------------------- u_syscon_MAINCLKSAFETY --------------------------- */
-#define SYSCON_MAINCLKSAFETY_MAIN_CLK_SAFETY_DEL_Pos 0 /*!< SYSCON MAINCLKSAFETY: MAIN_CLK_SAFETY_DEL Position */
-#define SYSCON_MAINCLKSAFETY_MAIN_CLK_SAFETY_DEL_Msk (0x0000ffffUL << SYSCON_MAINCLKSAFETY_MAIN_CLK_SAFETY_DEL_Pos)/*!< SYSCON MAINCLKSAFETY: MAIN_CLK_SAFETY_DEL Mask */
-
-/* --------------------------- u_syscon_HARDWARESLEEP --------------------------- */
-#define SYSCON_HARDWARESLEEP_FORCED_Pos 0 /*!< SYSCON HARDWARESLEEP: FORCED Position */
-#define SYSCON_HARDWARESLEEP_FORCED_Msk (0x01UL << SYSCON_HARDWARESLEEP_FORCED_Pos) /*!< SYSCON HARDWARESLEEP: FORCED Mask */
-#define SYSCON_HARDWARESLEEP_PERIPHERALS_Pos 1 /*!< SYSCON HARDWARESLEEP: PERIPHERALS Position */
-#define SYSCON_HARDWARESLEEP_PERIPHERALS_Msk (0x01UL << SYSCON_HARDWARESLEEP_PERIPHERALS_Pos) /*!< SYSCON HARDWARESLEEP: PERIPHERALS Mask */
-#define SYSCON_HARDWARESLEEP_DMIC_Pos 2 /*!< SYSCON HARDWARESLEEP: DMIC Position */
-#define SYSCON_HARDWARESLEEP_DMIC_Msk (0x01UL << SYSCON_HARDWARESLEEP_DMIC_Pos) /*!< SYSCON HARDWARESLEEP: DMIC Mask */
-#define SYSCON_HARDWARESLEEP_SDMA_Pos 3 /*!< SYSCON HARDWARESLEEP: SDMA Position */
-#define SYSCON_HARDWARESLEEP_SDMA_Msk (0x01UL << SYSCON_HARDWARESLEEP_SDMA_Pos) /*!< SYSCON HARDWARESLEEP: SDMA Mask */
-#define SYSCON_HARDWARESLEEP_NFCTAG_Pos 4 /*!< SYSCON HARDWARESLEEP: NFCTAG Position */
-#define SYSCON_HARDWARESLEEP_NFCTAG_Msk (0x01UL << SYSCON_HARDWARESLEEP_NFCTAG_Pos) /*!< SYSCON HARDWARESLEEP: NFCTAG Mask */
-#define SYSCON_HARDWARESLEEP_BLEOSC_Pos 5 /*!< SYSCON HARDWARESLEEP: BLEOSC Position */
-#define SYSCON_HARDWARESLEEP_BLEOSC_Msk (0x01UL << SYSCON_HARDWARESLEEP_BLEOSC_Pos) /*!< SYSCON HARDWARESLEEP: BLEOSC Mask */
-
-/* ------------------------------ u_syscon_CPUCTRL ------------------------------ */
-#define SYSCON_CPUCTRL_MASTERCPU_Pos 0 /*!< SYSCON CPUCTRL: MASTERCPU Position */
-#define SYSCON_CPUCTRL_MASTERCPU_Msk (0x01UL << SYSCON_CPUCTRL_MASTERCPU_Pos) /*!< SYSCON CPUCTRL: MASTERCPU Mask */
-#define SYSCON_CPUCTRL_CM40CLKEN_Pos 2 /*!< SYSCON CPUCTRL: CM40CLKEN Position */
-#define SYSCON_CPUCTRL_CM40CLKEN_Msk (0x01UL << SYSCON_CPUCTRL_CM40CLKEN_Pos) /*!< SYSCON CPUCTRL: CM40CLKEN Mask */
-#define SYSCON_CPUCTRL_CM41CLKEN_Pos 3 /*!< SYSCON CPUCTRL: CM41CLKEN Position */
-#define SYSCON_CPUCTRL_CM41CLKEN_Msk (0x01UL << SYSCON_CPUCTRL_CM41CLKEN_Pos) /*!< SYSCON CPUCTRL: CM41CLKEN Mask */
-#define SYSCON_CPUCTRL_CM40RSTEN_Pos 4 /*!< SYSCON CPUCTRL: CM40RSTEN Position */
-#define SYSCON_CPUCTRL_CM40RSTEN_Msk (0x01UL << SYSCON_CPUCTRL_CM40RSTEN_Pos) /*!< SYSCON CPUCTRL: CM40RSTEN Mask */
-#define SYSCON_CPUCTRL_CM41RSTEN_Pos 5 /*!< SYSCON CPUCTRL: CM41RSTEN Position */
-#define SYSCON_CPUCTRL_CM41RSTEN_Msk (0x01UL << SYSCON_CPUCTRL_CM41RSTEN_Pos) /*!< SYSCON CPUCTRL: CM41RSTEN Mask */
-#define SYSCON_CPUCTRL_POWERCPU_Pos 6 /*!< SYSCON CPUCTRL: POWERCPU Position */
-#define SYSCON_CPUCTRL_POWERCPU_Msk (0x01UL << SYSCON_CPUCTRL_POWERCPU_Pos) /*!< SYSCON CPUCTRL: POWERCPU Mask */
-#define SYSCON_CPUCTRL_WAKEUPEVENT_Pos 7 /*!< SYSCON CPUCTRL: WAKEUPEVENT Position */
-#define SYSCON_CPUCTRL_WAKEUPEVENT_Msk (0x01UL << SYSCON_CPUCTRL_WAKEUPEVENT_Pos) /*!< SYSCON CPUCTRL: WAKEUPEVENT Mask */
-#define SYSCON_CPUCTRL_CM40SYSRESETEN_Pos 8 /*!< SYSCON CPUCTRL: CM40SYSRESETEN Position */
-#define SYSCON_CPUCTRL_CM40SYSRESETEN_Msk (0x01UL << SYSCON_CPUCTRL_CM40SYSRESETEN_Pos) /*!< SYSCON CPUCTRL: CM40SYSRESETEN Mask */
-#define SYSCON_CPUCTRL_CM41SYSRESETEN_Pos 9 /*!< SYSCON CPUCTRL: CM41SYSRESETEN Position */
-#define SYSCON_CPUCTRL_CM41SYSRESETEN_Msk (0x01UL << SYSCON_CPUCTRL_CM41SYSRESETEN_Pos) /*!< SYSCON CPUCTRL: CM41SYSRESETEN Mask */
-#define SYSCON_CPUCTRL_RESERVED1_Pos 15 /*!< SYSCON CPUCTRL: RESERVED1 Position */
-#define SYSCON_CPUCTRL_RESERVED1_Msk (0x01UL << SYSCON_CPUCTRL_RESERVED1_Pos) /*!< SYSCON CPUCTRL: RESERVED1 Mask */
-#define SYSCON_CPUCTRL_RESERVEDC0C4_Pos 16 /*!< SYSCON CPUCTRL: RESERVEDC0C4 Position */
-#define SYSCON_CPUCTRL_RESERVEDC0C4_Msk (0x0000ffffUL << SYSCON_CPUCTRL_RESERVEDC0C4_Pos) /*!< SYSCON CPUCTRL: RESERVEDC0C4 Mask */
-
-/* ------------------------------- u_syscon_CPBOOT ------------------------------ */
-#define SYSCON_CPBOOT_CPBOOT_Pos 0 /*!< SYSCON CPBOOT: CPBOOT Position */
-#define SYSCON_CPBOOT_CPBOOT_Msk (0xffffffffUL << SYSCON_CPBOOT_CPBOOT_Pos) /*!< SYSCON CPBOOT: CPBOOT Mask */
-
-/* ------------------------------ u_syscon_CPSTACK ------------------------------ */
-#define SYSCON_CPSTACK_CPSTACK_Pos 0 /*!< SYSCON CPSTACK: CPSTACK Position */
-#define SYSCON_CPSTACK_CPSTACK_Msk (0xffffffffUL << SYSCON_CPSTACK_CPSTACK_Pos) /*!< SYSCON CPSTACK: CPSTACK Mask */
-
-/* ------------------------------- u_syscon_CPSTAT ------------------------------ */
-#define SYSCON_CPSTAT_CM40SLEEPING_Pos 0 /*!< SYSCON CPSTAT: CM40SLEEPING Position */
-#define SYSCON_CPSTAT_CM40SLEEPING_Msk (0x01UL << SYSCON_CPSTAT_CM40SLEEPING_Pos) /*!< SYSCON CPSTAT: CM40SLEEPING Mask */
-#define SYSCON_CPSTAT_CM41SLEEPING_Pos 1 /*!< SYSCON CPSTAT: CM41SLEEPING Position */
-#define SYSCON_CPSTAT_CM41SLEEPING_Msk (0x01UL << SYSCON_CPSTAT_CM41SLEEPING_Pos) /*!< SYSCON CPSTAT: CM41SLEEPING Mask */
-#define SYSCON_CPSTAT_CM40LOCKUP_Pos 2 /*!< SYSCON CPSTAT: CM40LOCKUP Position */
-#define SYSCON_CPSTAT_CM40LOCKUP_Msk (0x01UL << SYSCON_CPSTAT_CM40LOCKUP_Pos) /*!< SYSCON CPSTAT: CM40LOCKUP Mask */
-#define SYSCON_CPSTAT_CM41LOCKUP_Pos 3 /*!< SYSCON CPSTAT: CM41LOCKUP Position */
-#define SYSCON_CPSTAT_CM41LOCKUP_Msk (0x01UL << SYSCON_CPSTAT_CM41LOCKUP_Pos) /*!< SYSCON CPSTAT: CM41LOCKUP Mask */
-
-/* ----------------------------- u_syscon_GPIOSECIN ----------------------------- */
-#define SYSCON_GPIOSECIN_GPIOSECIN_Pos 0 /*!< SYSCON GPIOSECIN: GPIOSECIN Position */
-#define SYSCON_GPIOSECIN_GPIOSECIN_Msk (0xffffffffUL << SYSCON_GPIOSECIN_GPIOSECIN_Pos) /*!< SYSCON GPIOSECIN: GPIOSECIN Mask */
-
-/* ----------------------------- u_syscon_GPIOSECOUT ---------------------------- */
-#define SYSCON_GPIOSECOUT_GPIOSECOUT_Pos 0 /*!< SYSCON GPIOSECOUT: GPIOSECOUT Position */
-#define SYSCON_GPIOSECOUT_GPIOSECOUT_Msk (0xffffffffUL << SYSCON_GPIOSECOUT_GPIOSECOUT_Pos) /*!< SYSCON GPIOSECOUT: GPIOSECOUT Mask */
-
-/* ----------------------------- u_syscon_GPIOSECDIR ---------------------------- */
-#define SYSCON_GPIOSECDIR_GPIOSECDIR_Pos 0 /*!< SYSCON GPIOSECDIR: GPIOSECDIR Position */
-#define SYSCON_GPIOSECDIR_GPIOSECDIR_Msk (0xffffffffUL << SYSCON_GPIOSECDIR_GPIOSECDIR_Pos) /*!< SYSCON GPIOSECDIR: GPIOSECDIR Mask */
-
-/* ---------------------------- u_syscon_ANACTRL_CTRL --------------------------- */
-#define SYSCON_ANACTRL_CTRL_COMPINTRLVL_Pos 0 /*!< SYSCON ANACTRL_CTRL: COMPINTRLVL Position */
-#define SYSCON_ANACTRL_CTRL_COMPINTRLVL_Msk (0x01UL << SYSCON_ANACTRL_CTRL_COMPINTRLVL_Pos) /*!< SYSCON ANACTRL_CTRL: COMPINTRLVL Mask */
-#define SYSCON_ANACTRL_CTRL_COMPINTRPOL_Pos 1 /*!< SYSCON ANACTRL_CTRL: COMPINTRPOL Position */
-#define SYSCON_ANACTRL_CTRL_COMPINTRPOL_Msk (0x03UL << SYSCON_ANACTRL_CTRL_COMPINTRPOL_Pos) /*!< SYSCON ANACTRL_CTRL: COMPINTRPOL Mask */
-
-/* ---------------------------- u_syscon_ANACTRL_VAL ---------------------------- */
-#define SYSCON_ANACTRL_VAL_BODVBAT_Pos 0 /*!< SYSCON ANACTRL_VAL: BODVBAT Position */
-#define SYSCON_ANACTRL_VAL_BODVBAT_Msk (0x01UL << SYSCON_ANACTRL_VAL_BODVBAT_Pos) /*!< SYSCON ANACTRL_VAL: BODVBAT Mask */
-#define SYSCON_ANACTRL_VAL_BODMEM_Pos 1 /*!< SYSCON ANACTRL_VAL: BODMEM Position */
-#define SYSCON_ANACTRL_VAL_BODMEM_Msk (0x01UL << SYSCON_ANACTRL_VAL_BODMEM_Pos) /*!< SYSCON ANACTRL_VAL: BODMEM Mask */
-#define SYSCON_ANACTRL_VAL_BODCORE_Pos 2 /*!< SYSCON ANACTRL_VAL: BODCORE Position */
-#define SYSCON_ANACTRL_VAL_BODCORE_Msk (0x01UL << SYSCON_ANACTRL_VAL_BODCORE_Pos) /*!< SYSCON ANACTRL_VAL: BODCORE Mask */
-#define SYSCON_ANACTRL_VAL_ANACOMP_Pos 3 /*!< SYSCON ANACTRL_VAL: ANACOMP Position */
-#define SYSCON_ANACTRL_VAL_ANACOMP_Msk (0x01UL << SYSCON_ANACTRL_VAL_ANACOMP_Pos) /*!< SYSCON ANACTRL_VAL: ANACOMP Mask */
-#define SYSCON_ANACTRL_VAL_BODVBATHIGH_Pos 4 /*!< SYSCON ANACTRL_VAL: BODVBATHIGH Position */
-#define SYSCON_ANACTRL_VAL_BODVBATHIGH_Msk (0x01UL << SYSCON_ANACTRL_VAL_BODVBATHIGH_Pos) /*!< SYSCON ANACTRL_VAL: BODVBATHIGH Mask */
-
-/* ---------------------------- u_syscon_ANACTRL_STAT --------------------------- */
-#define SYSCON_ANACTRL_STAT_BODVBAT_Pos 0 /*!< SYSCON ANACTRL_STAT: BODVBAT Position */
-#define SYSCON_ANACTRL_STAT_BODVBAT_Msk (0x01UL << SYSCON_ANACTRL_STAT_BODVBAT_Pos) /*!< SYSCON ANACTRL_STAT: BODVBAT Mask */
-#define SYSCON_ANACTRL_STAT_BODMEM_Pos 1 /*!< SYSCON ANACTRL_STAT: BODMEM Position */
-#define SYSCON_ANACTRL_STAT_BODMEM_Msk (0x01UL << SYSCON_ANACTRL_STAT_BODMEM_Pos) /*!< SYSCON ANACTRL_STAT: BODMEM Mask */
-#define SYSCON_ANACTRL_STAT_BODCORE_Pos 2 /*!< SYSCON ANACTRL_STAT: BODCORE Position */
-#define SYSCON_ANACTRL_STAT_BODCORE_Msk (0x01UL << SYSCON_ANACTRL_STAT_BODCORE_Pos) /*!< SYSCON ANACTRL_STAT: BODCORE Mask */
-#define SYSCON_ANACTRL_STAT_ANACOMP_Pos 3 /*!< SYSCON ANACTRL_STAT: ANACOMP Position */
-#define SYSCON_ANACTRL_STAT_ANACOMP_Msk (0x01UL << SYSCON_ANACTRL_STAT_ANACOMP_Pos) /*!< SYSCON ANACTRL_STAT: ANACOMP Mask */
-#define SYSCON_ANACTRL_STAT_BODVBATHIGH_Pos 4 /*!< SYSCON ANACTRL_STAT: BODVBATHIGH Position */
-#define SYSCON_ANACTRL_STAT_BODVBATHIGH_Msk (0x01UL << SYSCON_ANACTRL_STAT_BODVBATHIGH_Pos) /*!< SYSCON ANACTRL_STAT: BODVBATHIGH Mask */
-
-/* -------------------------- u_syscon_ANACTRL_INTENSET ------------------------- */
-#define SYSCON_ANACTRL_INTENSET_BODVBAT_Pos 0 /*!< SYSCON ANACTRL_INTENSET: BODVBAT Position */
-#define SYSCON_ANACTRL_INTENSET_BODVBAT_Msk (0x01UL << SYSCON_ANACTRL_INTENSET_BODVBAT_Pos) /*!< SYSCON ANACTRL_INTENSET: BODVBAT Mask */
-#define SYSCON_ANACTRL_INTENSET_BODMEM_Pos 1 /*!< SYSCON ANACTRL_INTENSET: BODMEM Position */
-#define SYSCON_ANACTRL_INTENSET_BODMEM_Msk (0x01UL << SYSCON_ANACTRL_INTENSET_BODMEM_Pos) /*!< SYSCON ANACTRL_INTENSET: BODMEM Mask */
-#define SYSCON_ANACTRL_INTENSET_BODCORE_Pos 2 /*!< SYSCON ANACTRL_INTENSET: BODCORE Position */
-#define SYSCON_ANACTRL_INTENSET_BODCORE_Msk (0x01UL << SYSCON_ANACTRL_INTENSET_BODCORE_Pos) /*!< SYSCON ANACTRL_INTENSET: BODCORE Mask */
-#define SYSCON_ANACTRL_INTENSET_ANACOMP_Pos 3 /*!< SYSCON ANACTRL_INTENSET: ANACOMP Position */
-#define SYSCON_ANACTRL_INTENSET_ANACOMP_Msk (0x01UL << SYSCON_ANACTRL_INTENSET_ANACOMP_Pos) /*!< SYSCON ANACTRL_INTENSET: ANACOMP Mask */
-#define SYSCON_ANACTRL_INTENSET_BODVBATHIGH_Pos 4 /*!< SYSCON ANACTRL_INTENSET: BODVBATHIGH Position */
-#define SYSCON_ANACTRL_INTENSET_BODVBATHIGH_Msk (0x01UL << SYSCON_ANACTRL_INTENSET_BODVBATHIGH_Pos)/*!< SYSCON ANACTRL_INTENSET: BODVBATHIGH Mask */
-
-/* -------------------------- u_syscon_ANACTRL_INTENCLR ------------------------- */
-#define SYSCON_ANACTRL_INTENCLR_BODVBAT_Pos 0 /*!< SYSCON ANACTRL_INTENCLR: BODVBAT Position */
-#define SYSCON_ANACTRL_INTENCLR_BODVBAT_Msk (0x01UL << SYSCON_ANACTRL_INTENCLR_BODVBAT_Pos) /*!< SYSCON ANACTRL_INTENCLR: BODVBAT Mask */
-#define SYSCON_ANACTRL_INTENCLR_BODMEM_Pos 1 /*!< SYSCON ANACTRL_INTENCLR: BODMEM Position */
-#define SYSCON_ANACTRL_INTENCLR_BODMEM_Msk (0x01UL << SYSCON_ANACTRL_INTENCLR_BODMEM_Pos) /*!< SYSCON ANACTRL_INTENCLR: BODMEM Mask */
-#define SYSCON_ANACTRL_INTENCLR_BODCORE_Pos 2 /*!< SYSCON ANACTRL_INTENCLR: BODCORE Position */
-#define SYSCON_ANACTRL_INTENCLR_BODCORE_Msk (0x01UL << SYSCON_ANACTRL_INTENCLR_BODCORE_Pos) /*!< SYSCON ANACTRL_INTENCLR: BODCORE Mask */
-#define SYSCON_ANACTRL_INTENCLR_ANACOMP_Pos 3 /*!< SYSCON ANACTRL_INTENCLR: ANACOMP Position */
-#define SYSCON_ANACTRL_INTENCLR_ANACOMP_Msk (0x01UL << SYSCON_ANACTRL_INTENCLR_ANACOMP_Pos) /*!< SYSCON ANACTRL_INTENCLR: ANACOMP Mask */
-#define SYSCON_ANACTRL_INTENCLR_BODVBATHIGH_Pos 4 /*!< SYSCON ANACTRL_INTENCLR: BODVBATHIGH Position */
-#define SYSCON_ANACTRL_INTENCLR_BODVBATHIGH_Msk (0x01UL << SYSCON_ANACTRL_INTENCLR_BODVBATHIGH_Pos)/*!< SYSCON ANACTRL_INTENCLR: BODVBATHIGH Mask */
-
-/* -------------------------- u_syscon_ANACTRL_INTSTAT -------------------------- */
-#define SYSCON_ANACTRL_INTSTAT_BODVBAT_Pos 0 /*!< SYSCON ANACTRL_INTSTAT: BODVBAT Position */
-#define SYSCON_ANACTRL_INTSTAT_BODVBAT_Msk (0x01UL << SYSCON_ANACTRL_INTSTAT_BODVBAT_Pos) /*!< SYSCON ANACTRL_INTSTAT: BODVBAT Mask */
-#define SYSCON_ANACTRL_INTSTAT_BODMEM_Pos 1 /*!< SYSCON ANACTRL_INTSTAT: BODMEM Position */
-#define SYSCON_ANACTRL_INTSTAT_BODMEM_Msk (0x01UL << SYSCON_ANACTRL_INTSTAT_BODMEM_Pos) /*!< SYSCON ANACTRL_INTSTAT: BODMEM Mask */
-#define SYSCON_ANACTRL_INTSTAT_BODCORE_Pos 2 /*!< SYSCON ANACTRL_INTSTAT: BODCORE Position */
-#define SYSCON_ANACTRL_INTSTAT_BODCORE_Msk (0x01UL << SYSCON_ANACTRL_INTSTAT_BODCORE_Pos) /*!< SYSCON ANACTRL_INTSTAT: BODCORE Mask */
-#define SYSCON_ANACTRL_INTSTAT_ANACOMP_Pos 3 /*!< SYSCON ANACTRL_INTSTAT: ANACOMP Position */
-#define SYSCON_ANACTRL_INTSTAT_ANACOMP_Msk (0x01UL << SYSCON_ANACTRL_INTSTAT_ANACOMP_Pos) /*!< SYSCON ANACTRL_INTSTAT: ANACOMP Mask */
-#define SYSCON_ANACTRL_INTSTAT_BODVBATHIGH_Pos 4 /*!< SYSCON ANACTRL_INTSTAT: BODVBATHIGH Position */
-#define SYSCON_ANACTRL_INTSTAT_BODVBATHIGH_Msk (0x01UL << SYSCON_ANACTRL_INTSTAT_BODVBATHIGH_Pos) /*!< SYSCON ANACTRL_INTSTAT: BODVBATHIGH Mask */
-
-/* ----------------------------- u_syscon_CLOCK_CTRL ---------------------------- */
-#define SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_Pos 0 /*!< SYSCON CLOCK_CTRL: FLASH48MHZ_ENA Position */
-#define SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_Msk (0x01UL << SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_Pos) /*!< SYSCON CLOCK_CTRL: FLASH48MHZ_ENA Mask */
-#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_Pos 1 /*!< SYSCON CLOCK_CTRL: XTAL32MHZ_FREQM_ENA Position */
-#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_Msk (0x01UL << SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_Pos)/*!< SYSCON CLOCK_CTRL: XTAL32MHZ_FREQM_ENA Mask */
-#define SYSCON_CLOCK_CTRL_FRO1MHZ_FREQM_ENA_Pos 2 /*!< SYSCON CLOCK_CTRL: FRO1MHZ_FREQM_ENA Position */
-#define SYSCON_CLOCK_CTRL_FRO1MHZ_FREQM_ENA_Msk (0x01UL << SYSCON_CLOCK_CTRL_FRO1MHZ_FREQM_ENA_Pos)/*!< SYSCON CLOCK_CTRL: FRO1MHZ_FREQM_ENA Mask */
-
-/* ------------------------------ u_syscon_WKT_CTRL ----------------------------- */
-#define SYSCON_WKT_CTRL_WKT0_ENA_Pos 0 /*!< SYSCON WKT_CTRL: WKT0_ENA Position */
-#define SYSCON_WKT_CTRL_WKT0_ENA_Msk (0x01UL << SYSCON_WKT_CTRL_WKT0_ENA_Pos) /*!< SYSCON WKT_CTRL: WKT0_ENA Mask */
-#define SYSCON_WKT_CTRL_WKT1_ENA_Pos 1 /*!< SYSCON WKT_CTRL: WKT1_ENA Position */
-#define SYSCON_WKT_CTRL_WKT1_ENA_Msk (0x01UL << SYSCON_WKT_CTRL_WKT1_ENA_Pos) /*!< SYSCON WKT_CTRL: WKT1_ENA Mask */
-#define SYSCON_WKT_CTRL_WKT0_CLK_ENA_Pos 2 /*!< SYSCON WKT_CTRL: WKT0_CLK_ENA Position */
-#define SYSCON_WKT_CTRL_WKT0_CLK_ENA_Msk (0x01UL << SYSCON_WKT_CTRL_WKT0_CLK_ENA_Pos) /*!< SYSCON WKT_CTRL: WKT0_CLK_ENA Mask */
-#define SYSCON_WKT_CTRL_WKT1_CLK_ENA_Pos 3 /*!< SYSCON WKT_CTRL: WKT1_CLK_ENA Position */
-#define SYSCON_WKT_CTRL_WKT1_CLK_ENA_Msk (0x01UL << SYSCON_WKT_CTRL_WKT1_CLK_ENA_Pos) /*!< SYSCON WKT_CTRL: WKT1_CLK_ENA Mask */
-
-/* ------------------------- u_syscon_WKT_LOAD_WKT0_LSB ------------------------- */
-#define SYSCON_WKT_LOAD_WKT0_LSB_WKT0_LOAD_LSB_Pos 0 /*!< SYSCON WKT_LOAD_WKT0_LSB: WKT0_LOAD_LSB Position */
-#define SYSCON_WKT_LOAD_WKT0_LSB_WKT0_LOAD_LSB_Msk (0xffffffffUL << SYSCON_WKT_LOAD_WKT0_LSB_WKT0_LOAD_LSB_Pos)/*!< SYSCON WKT_LOAD_WKT0_LSB: WKT0_LOAD_LSB Mask */
-
-/* ------------------------- u_syscon_WKT_LOAD_WKT0_MSB ------------------------- */
-#define SYSCON_WKT_LOAD_WKT0_MSB_WKT0_LOAD_MSB_Pos 0 /*!< SYSCON WKT_LOAD_WKT0_MSB: WKT0_LOAD_MSB Position */
-#define SYSCON_WKT_LOAD_WKT0_MSB_WKT0_LOAD_MSB_Msk (0x000001ffUL << SYSCON_WKT_LOAD_WKT0_MSB_WKT0_LOAD_MSB_Pos)/*!< SYSCON WKT_LOAD_WKT0_MSB: WKT0_LOAD_MSB Mask */
-
-/* --------------------------- u_syscon_WKT_LOAD_WKT1 --------------------------- */
-#define SYSCON_WKT_LOAD_WKT1_WKT1_LOAD_Pos 0 /*!< SYSCON WKT_LOAD_WKT1: WKT1_LOAD Position */
-#define SYSCON_WKT_LOAD_WKT1_WKT1_LOAD_Msk (0x0fffffffUL << SYSCON_WKT_LOAD_WKT1_WKT1_LOAD_Pos) /*!< SYSCON WKT_LOAD_WKT1: WKT1_LOAD Mask */
-
-/* -------------------------- u_syscon_WKT_VAL_WKT0_LSB ------------------------- */
-#define SYSCON_WKT_VAL_WKT0_LSB_WKT0_VAL_LSB_Pos 0 /*!< SYSCON WKT_VAL_WKT0_LSB: WKT0_VAL_LSB Position */
-#define SYSCON_WKT_VAL_WKT0_LSB_WKT0_VAL_LSB_Msk (0xffffffffUL << SYSCON_WKT_VAL_WKT0_LSB_WKT0_VAL_LSB_Pos)/*!< SYSCON WKT_VAL_WKT0_LSB: WKT0_VAL_LSB Mask */
-
-/* -------------------------- u_syscon_WKT_VAL_WKT0_MSB ------------------------- */
-#define SYSCON_WKT_VAL_WKT0_MSB_WKT0_VAL_MSB_Pos 0 /*!< SYSCON WKT_VAL_WKT0_MSB: WKT0_VAL_MSB Position */
-#define SYSCON_WKT_VAL_WKT0_MSB_WKT0_VAL_MSB_Msk (0x000001ffUL << SYSCON_WKT_VAL_WKT0_MSB_WKT0_VAL_MSB_Pos)/*!< SYSCON WKT_VAL_WKT0_MSB: WKT0_VAL_MSB Mask */
-
-/* ---------------------------- u_syscon_WKT_VAL_WKT1 --------------------------- */
-#define SYSCON_WKT_VAL_WKT1_WKT1_VAL_Pos 0 /*!< SYSCON WKT_VAL_WKT1: WKT1_VAL Position */
-#define SYSCON_WKT_VAL_WKT1_WKT1_VAL_Msk (0x0fffffffUL << SYSCON_WKT_VAL_WKT1_WKT1_VAL_Pos) /*!< SYSCON WKT_VAL_WKT1: WKT1_VAL Mask */
-
-/* ------------------------------ u_syscon_WKT_STAT ----------------------------- */
-#define SYSCON_WKT_STAT_WKT0_TIMEOUT_Pos 0 /*!< SYSCON WKT_STAT: WKT0_TIMEOUT Position */
-#define SYSCON_WKT_STAT_WKT0_TIMEOUT_Msk (0x01UL << SYSCON_WKT_STAT_WKT0_TIMEOUT_Pos) /*!< SYSCON WKT_STAT: WKT0_TIMEOUT Mask */
-#define SYSCON_WKT_STAT_WKT1_TIMEOUT_Pos 1 /*!< SYSCON WKT_STAT: WKT1_TIMEOUT Position */
-#define SYSCON_WKT_STAT_WKT1_TIMEOUT_Msk (0x01UL << SYSCON_WKT_STAT_WKT1_TIMEOUT_Pos) /*!< SYSCON WKT_STAT: WKT1_TIMEOUT Mask */
-#define SYSCON_WKT_STAT_WKT0_RUNNING_Pos 2 /*!< SYSCON WKT_STAT: WKT0_RUNNING Position */
-#define SYSCON_WKT_STAT_WKT0_RUNNING_Msk (0x01UL << SYSCON_WKT_STAT_WKT0_RUNNING_Pos) /*!< SYSCON WKT_STAT: WKT0_RUNNING Mask */
-#define SYSCON_WKT_STAT_WKT1_RUNNING_Pos 3 /*!< SYSCON WKT_STAT: WKT1_RUNNING Position */
-#define SYSCON_WKT_STAT_WKT1_RUNNING_Msk (0x01UL << SYSCON_WKT_STAT_WKT1_RUNNING_Pos) /*!< SYSCON WKT_STAT: WKT1_RUNNING Mask */
-
-/* ---------------------------- u_syscon_WKT_INTENSET --------------------------- */
-#define SYSCON_WKT_INTENSET_WKT0_TIMEOUT_Pos 0 /*!< SYSCON WKT_INTENSET: WKT0_TIMEOUT Position */
-#define SYSCON_WKT_INTENSET_WKT0_TIMEOUT_Msk (0x01UL << SYSCON_WKT_INTENSET_WKT0_TIMEOUT_Pos) /*!< SYSCON WKT_INTENSET: WKT0_TIMEOUT Mask */
-#define SYSCON_WKT_INTENSET_WKT1_TIMEOUT_Pos 1 /*!< SYSCON WKT_INTENSET: WKT1_TIMEOUT Position */
-#define SYSCON_WKT_INTENSET_WKT1_TIMEOUT_Msk (0x01UL << SYSCON_WKT_INTENSET_WKT1_TIMEOUT_Pos) /*!< SYSCON WKT_INTENSET: WKT1_TIMEOUT Mask */
-
-/* ---------------------------- u_syscon_WKT_INTENCLR --------------------------- */
-#define SYSCON_WKT_INTENCLR_WKT0_TIMEOUT_Pos 0 /*!< SYSCON WKT_INTENCLR: WKT0_TIMEOUT Position */
-#define SYSCON_WKT_INTENCLR_WKT0_TIMEOUT_Msk (0x01UL << SYSCON_WKT_INTENCLR_WKT0_TIMEOUT_Pos) /*!< SYSCON WKT_INTENCLR: WKT0_TIMEOUT Mask */
-#define SYSCON_WKT_INTENCLR_WKT1_TIMEOUT_Pos 1 /*!< SYSCON WKT_INTENCLR: WKT1_TIMEOUT Position */
-#define SYSCON_WKT_INTENCLR_WKT1_TIMEOUT_Msk (0x01UL << SYSCON_WKT_INTENCLR_WKT1_TIMEOUT_Pos) /*!< SYSCON WKT_INTENCLR: WKT1_TIMEOUT Mask */
-
-/* ---------------------------- u_syscon_WKT_INTSTAT ---------------------------- */
-#define SYSCON_WKT_INTSTAT_WKT0_TIMEOUT_Pos 0 /*!< SYSCON WKT_INTSTAT: WKT0_TIMEOUT Position */
-#define SYSCON_WKT_INTSTAT_WKT0_TIMEOUT_Msk (0x01UL << SYSCON_WKT_INTSTAT_WKT0_TIMEOUT_Pos) /*!< SYSCON WKT_INTSTAT: WKT0_TIMEOUT Mask */
-#define SYSCON_WKT_INTSTAT_WKT1_TIMEOUT_Pos 1 /*!< SYSCON WKT_INTSTAT: WKT1_TIMEOUT Position */
-#define SYSCON_WKT_INTSTAT_WKT1_TIMEOUT_Msk (0x01UL << SYSCON_WKT_INTSTAT_WKT1_TIMEOUT_Pos) /*!< SYSCON WKT_INTSTAT: WKT1_TIMEOUT Mask */
-
-/* ------------------------ u_syscon_AUTOCLKGATEOVERRIDE ------------------------ */
-#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_Pos 0 /*!< SYSCON AUTOCLKGATEOVERRIDE: ROM Position */
-#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_Msk (0x01UL << SYSCON_AUTOCLKGATEOVERRIDE_ROM_Pos) /*!< SYSCON AUTOCLKGATEOVERRIDE: ROM Mask */
-#define SYSCON_AUTOCLKGATEOVERRIDE_SRAM_CTRL0_Pos 1 /*!< SYSCON AUTOCLKGATEOVERRIDE: SRAM_CTRL0 Position */
-#define SYSCON_AUTOCLKGATEOVERRIDE_SRAM_CTRL0_Msk (0x01UL << SYSCON_AUTOCLKGATEOVERRIDE_SRAM_CTRL0_Pos)/*!< SYSCON AUTOCLKGATEOVERRIDE: SRAM_CTRL0 Mask */
-#define SYSCON_AUTOCLKGATEOVERRIDE_SRAM_CTRL1_Pos 2 /*!< SYSCON AUTOCLKGATEOVERRIDE: SRAM_CTRL1 Position */
-#define SYSCON_AUTOCLKGATEOVERRIDE_SRAM_CTRL1_Msk (0x01UL << SYSCON_AUTOCLKGATEOVERRIDE_SRAM_CTRL1_Pos)/*!< SYSCON AUTOCLKGATEOVERRIDE: SRAM_CTRL1 Mask */
-#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC_APB_Pos 5 /*!< SYSCON AUTOCLKGATEOVERRIDE: SYNC_APB Position */
-#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC_APB_Msk (0x01UL << SYSCON_AUTOCLKGATEOVERRIDE_SYNC_APB_Pos)/*!< SYSCON AUTOCLKGATEOVERRIDE: SYNC_APB Mask */
-#define SYSCON_AUTOCLKGATEOVERRIDE_ASYNC_APB_Pos 6 /*!< SYSCON AUTOCLKGATEOVERRIDE: ASYNC_APB Position */
-#define SYSCON_AUTOCLKGATEOVERRIDE_ASYNC_APB_Msk (0x01UL << SYSCON_AUTOCLKGATEOVERRIDE_ASYNC_APB_Pos)/*!< SYSCON AUTOCLKGATEOVERRIDE: ASYNC_APB Mask */
-#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA_Pos 13 /*!< SYSCON AUTOCLKGATEOVERRIDE: SDMA Position */
-#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA_Msk (0x01UL << SYSCON_AUTOCLKGATEOVERRIDE_SDMA_Pos) /*!< SYSCON AUTOCLKGATEOVERRIDE: SDMA Mask */
-#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_Pos 15 /*!< SYSCON AUTOCLKGATEOVERRIDE: SYSCON Position */
-#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_Msk (0x01UL << SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_Pos) /*!< SYSCON AUTOCLKGATEOVERRIDE: SYSCON Mask */
-#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_Pos 16 /*!< SYSCON AUTOCLKGATEOVERRIDE: ENABLEUPDATE Position */
-#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_Msk (0x0000ffffUL << SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_Pos)/*!< SYSCON AUTOCLKGATEOVERRIDE: ENABLEUPDATE Mask */
-
-/* ----------------------------- u_syscon_GPIOPSYNC ----------------------------- */
-#define SYSCON_GPIOPSYNC_PSYNC_Pos 0 /*!< SYSCON GPIOPSYNC: PSYNC Position */
-#define SYSCON_GPIOPSYNC_PSYNC_Msk (0x01UL << SYSCON_GPIOPSYNC_PSYNC_Pos) /*!< SYSCON GPIOPSYNC: PSYNC Mask */
-
-/* --------------------------- u_syscon_INVERTMAINCLK --------------------------- */
-#define SYSCON_INVERTMAINCLK_INVERT_Pos 0 /*!< SYSCON INVERTMAINCLK: INVERT Position */
-#define SYSCON_INVERTMAINCLK_INVERT_Msk (0x01UL << SYSCON_INVERTMAINCLK_INVERT_Pos) /*!< SYSCON INVERTMAINCLK: INVERT Mask */
-
-/* ------------------------------- u_syscon_DIEID ------------------------------- */
-#define SYSCON_DIEID_REV_ID_Pos 0 /*!< SYSCON DIEID: REV_ID Position */
-#define SYSCON_DIEID_REV_ID_Msk (0x0fUL << SYSCON_DIEID_REV_ID_Pos) /*!< SYSCON DIEID: REV_ID Mask */
-#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_Pos 4 /*!< SYSCON DIEID: MCO_NUM_IN_DIE_ID Position */
-#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_Msk (0x000fffffUL << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_Pos) /*!< SYSCON DIEID: MCO_NUM_IN_DIE_ID Mask */
-
-/* ------------------------------- u_syscon_CPUCFG ------------------------------ */
-#define SYSCON_CPUCFG_DEFAULT_Pos 0 /*!< SYSCON CPUCFG: DEFAULT Position */
-#define SYSCON_CPUCFG_DEFAULT_Msk (0x01UL << SYSCON_CPUCFG_DEFAULT_Pos) /*!< SYSCON CPUCFG: DEFAULT Mask */
-#define SYSCON_CPUCFG_CM40ENABLE_Pos 1 /*!< SYSCON CPUCFG: CM40ENABLE Position */
-#define SYSCON_CPUCFG_CM40ENABLE_Msk (0x01UL << SYSCON_CPUCFG_CM40ENABLE_Pos) /*!< SYSCON CPUCFG: CM40ENABLE Mask */
-#define SYSCON_CPUCFG_CM41ENABLE_Pos 2 /*!< SYSCON CPUCFG: CM41ENABLE Position */
-#define SYSCON_CPUCFG_CM41ENABLE_Msk (0x01UL << SYSCON_CPUCFG_CM41ENABLE_Pos) /*!< SYSCON CPUCFG: CM41ENABLE Mask */
-
-/* --------------------------- u_syscon_CONFIGLOCKOUT --------------------------- */
-#define SYSCON_CONFIGLOCKOUT_LOCK_Pos 0 /*!< SYSCON CONFIGLOCKOUT: LOCK Position */
-#define SYSCON_CONFIGLOCKOUT_LOCK_Msk (0x01UL << SYSCON_CONFIGLOCKOUT_LOCK_Pos) /*!< SYSCON CONFIGLOCKOUT: LOCK Mask */
-
-/* -------------------------- u_syscon_CODESECURITYPROT ------------------------- */
-#define SYSCON_CODESECURITYPROT_SEC_CODE_Pos 0 /*!< SYSCON CODESECURITYPROT: SEC_CODE Position */
-#define SYSCON_CODESECURITYPROT_SEC_CODE_Msk (0xffffffffUL << SYSCON_CODESECURITYPROT_SEC_CODE_Pos)/*!< SYSCON CODESECURITYPROT: SEC_CODE Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u_otpc' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* --------------------------------- u_otpc_ADDR -------------------------------- */
-#define OTPC_ADDR_ADDR_Pos 0 /*!< OTPC ADDR: ADDR Position */
-#define OTPC_ADDR_ADDR_Msk (0x00000fffUL << OTPC_ADDR_ADDR_Pos) /*!< OTPC ADDR: ADDR Mask */
-
-/* --------------------------------- u_otpc_READ -------------------------------- */
-#define OTPC_READ_READ_Pos 0 /*!< OTPC READ: READ Position */
-#define OTPC_READ_READ_Msk (0x01UL << OTPC_READ_READ_Pos) /*!< OTPC READ: READ Mask */
-#define OTPC_READ_SEQ_Pos 16 /*!< OTPC READ: SEQ Position */
-#define OTPC_READ_SEQ_Msk (0x0000ffffUL << OTPC_READ_SEQ_Pos) /*!< OTPC READ: SEQ Mask */
-
-/* -------------------------------- u_otpc_RWIDTH ------------------------------- */
-#define OTPC_RWIDTH_OPCFG_Pos 0 /*!< OTPC RWIDTH: OPCFG Position */
-#define OTPC_RWIDTH_OPCFG_Msk (0x03UL << OTPC_RWIDTH_OPCFG_Pos) /*!< OTPC RWIDTH: OPCFG Mask */
-
-/* -------------------------------- u_otpc_HV_REQ ------------------------------- */
-#define OTPC_HV_REQ_PMC_REQ_Pos 0 /*!< OTPC HV_REQ: PMC_REQ Position */
-#define OTPC_HV_REQ_PMC_REQ_Msk (0x01UL << OTPC_HV_REQ_PMC_REQ_Pos) /*!< OTPC HV_REQ: PMC_REQ Mask */
-#define OTPC_HV_REQ_PAD_REQ_Pos 1 /*!< OTPC HV_REQ: PAD_REQ Position */
-#define OTPC_HV_REQ_PAD_REQ_Msk (0x01UL << OTPC_HV_REQ_PAD_REQ_Pos) /*!< OTPC HV_REQ: PAD_REQ Mask */
-#define OTPC_HV_REQ_SEQ_Pos 16 /*!< OTPC HV_REQ: SEQ Position */
-#define OTPC_HV_REQ_SEQ_Msk (0x0000ffffUL << OTPC_HV_REQ_SEQ_Pos) /*!< OTPC HV_REQ: SEQ Mask */
-
-/* -------------------------------- u_otpc_RDATA -------------------------------- */
-#define OTPC_RDATA_DATA_Pos 0 /*!< OTPC RDATA: DATA Position */
-#define OTPC_RDATA_DATA_Msk (0x0000ffffUL << OTPC_RDATA_DATA_Pos) /*!< OTPC RDATA: DATA Mask */
-#define OTPC_RDATA_VALID_Pos 31 /*!< OTPC RDATA: VALID Position */
-#define OTPC_RDATA_VALID_Msk (0x01UL << OTPC_RDATA_VALID_Pos) /*!< OTPC RDATA: VALID Mask */
-
-/* --------------------------------- u_otpc_AES --------------------------------- */
-#define OTPC_AES_KEY_Pos 0 /*!< OTPC AES: KEY Position */
-#define OTPC_AES_KEY_Msk (0x01UL << OTPC_AES_KEY_Pos) /*!< OTPC AES: KEY Mask */
-#define OTPC_AES_SEQ_Pos 16 /*!< OTPC AES: SEQ Position */
-#define OTPC_AES_SEQ_Msk (0x0000ffffUL << OTPC_AES_SEQ_Pos) /*!< OTPC AES: SEQ Mask */
-
-/* ------------------------------- u_otpc_SECURITY ------------------------------ */
-#define OTPC_SECURITY_VALID_Pos 0 /*!< OTPC SECURITY: VALID Position */
-#define OTPC_SECURITY_VALID_Msk (0x01UL << OTPC_SECURITY_VALID_Pos) /*!< OTPC SECURITY: VALID Mask */
-#define OTPC_SECURITY_MODE_Pos 1 /*!< OTPC SECURITY: MODE Position */
-#define OTPC_SECURITY_MODE_Msk (0x01UL << OTPC_SECURITY_MODE_Pos) /*!< OTPC SECURITY: MODE Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u0_i2c' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* --------------------------------- u0_i2c_CFG --------------------------------- */
-#define I2C0_CFG_MSTEN_Pos 0 /*!< I2C0 CFG: MSTEN Position */
-#define I2C0_CFG_MSTEN_Msk (0x01UL << I2C0_CFG_MSTEN_Pos) /*!< I2C0 CFG: MSTEN Mask */
-#define I2C0_CFG_SLVEN_Pos 1 /*!< I2C0 CFG: SLVEN Position */
-#define I2C0_CFG_SLVEN_Msk (0x01UL << I2C0_CFG_SLVEN_Pos) /*!< I2C0 CFG: SLVEN Mask */
-#define I2C0_CFG_MONEN_Pos 2 /*!< I2C0 CFG: MONEN Position */
-#define I2C0_CFG_MONEN_Msk (0x01UL << I2C0_CFG_MONEN_Pos) /*!< I2C0 CFG: MONEN Mask */
-#define I2C0_CFG_TIMEOUT_Pos 3 /*!< I2C0 CFG: TIMEOUT Position */
-#define I2C0_CFG_TIMEOUT_Msk (0x01UL << I2C0_CFG_TIMEOUT_Pos) /*!< I2C0 CFG: TIMEOUT Mask */
-#define I2C0_CFG_MONCLKSTR_Pos 4 /*!< I2C0 CFG: MONCLKSTR Position */
-#define I2C0_CFG_MONCLKSTR_Msk (0x01UL << I2C0_CFG_MONCLKSTR_Pos) /*!< I2C0 CFG: MONCLKSTR Mask */
-#define I2C0_CFG_HSCAPABLE_Pos 5 /*!< I2C0 CFG: HSCAPABLE Position */
-#define I2C0_CFG_HSCAPABLE_Msk (0x01UL << I2C0_CFG_HSCAPABLE_Pos) /*!< I2C0 CFG: HSCAPABLE Mask */
-
-/* --------------------------------- u0_i2c_STAT -------------------------------- */
-#define I2C0_STAT_MSTPENDING_Pos 0 /*!< I2C0 STAT: MSTPENDING Position */
-#define I2C0_STAT_MSTPENDING_Msk (0x01UL << I2C0_STAT_MSTPENDING_Pos) /*!< I2C0 STAT: MSTPENDING Mask */
-#define I2C0_STAT_MSTSTATE_Pos 1 /*!< I2C0 STAT: MSTSTATE Position */
-#define I2C0_STAT_MSTSTATE_Msk (0x07UL << I2C0_STAT_MSTSTATE_Pos) /*!< I2C0 STAT: MSTSTATE Mask */
-#define I2C0_STAT_MSTARBLOSS_Pos 4 /*!< I2C0 STAT: MSTARBLOSS Position */
-#define I2C0_STAT_MSTARBLOSS_Msk (0x01UL << I2C0_STAT_MSTARBLOSS_Pos) /*!< I2C0 STAT: MSTARBLOSS Mask */
-#define I2C0_STAT_MSTSTSTPERR_Pos 6 /*!< I2C0 STAT: MSTSTSTPERR Position */
-#define I2C0_STAT_MSTSTSTPERR_Msk (0x01UL << I2C0_STAT_MSTSTSTPERR_Pos) /*!< I2C0 STAT: MSTSTSTPERR Mask */
-#define I2C0_STAT_SLVPENDING_Pos 8 /*!< I2C0 STAT: SLVPENDING Position */
-#define I2C0_STAT_SLVPENDING_Msk (0x01UL << I2C0_STAT_SLVPENDING_Pos) /*!< I2C0 STAT: SLVPENDING Mask */
-#define I2C0_STAT_SLVSTATE_Pos 9 /*!< I2C0 STAT: SLVSTATE Position */
-#define I2C0_STAT_SLVSTATE_Msk (0x03UL << I2C0_STAT_SLVSTATE_Pos) /*!< I2C0 STAT: SLVSTATE Mask */
-#define I2C0_STAT_SLVNOTSTR_Pos 11 /*!< I2C0 STAT: SLVNOTSTR Position */
-#define I2C0_STAT_SLVNOTSTR_Msk (0x01UL << I2C0_STAT_SLVNOTSTR_Pos) /*!< I2C0 STAT: SLVNOTSTR Mask */
-#define I2C0_STAT_SLVIDX_Pos 12 /*!< I2C0 STAT: SLVIDX Position */
-#define I2C0_STAT_SLVIDX_Msk (0x03UL << I2C0_STAT_SLVIDX_Pos) /*!< I2C0 STAT: SLVIDX Mask */
-#define I2C0_STAT_SLVSEL_Pos 14 /*!< I2C0 STAT: SLVSEL Position */
-#define I2C0_STAT_SLVSEL_Msk (0x01UL << I2C0_STAT_SLVSEL_Pos) /*!< I2C0 STAT: SLVSEL Mask */
-#define I2C0_STAT_SLVDESEL_Pos 15 /*!< I2C0 STAT: SLVDESEL Position */
-#define I2C0_STAT_SLVDESEL_Msk (0x01UL << I2C0_STAT_SLVDESEL_Pos) /*!< I2C0 STAT: SLVDESEL Mask */
-#define I2C0_STAT_MONRDY_Pos 16 /*!< I2C0 STAT: MONRDY Position */
-#define I2C0_STAT_MONRDY_Msk (0x01UL << I2C0_STAT_MONRDY_Pos) /*!< I2C0 STAT: MONRDY Mask */
-#define I2C0_STAT_MONOV_Pos 17 /*!< I2C0 STAT: MONOV Position */
-#define I2C0_STAT_MONOV_Msk (0x01UL << I2C0_STAT_MONOV_Pos) /*!< I2C0 STAT: MONOV Mask */
-#define I2C0_STAT_MONACTIVE_Pos 18 /*!< I2C0 STAT: MONACTIVE Position */
-#define I2C0_STAT_MONACTIVE_Msk (0x01UL << I2C0_STAT_MONACTIVE_Pos) /*!< I2C0 STAT: MONACTIVE Mask */
-#define I2C0_STAT_MONIDLE_Pos 19 /*!< I2C0 STAT: MONIDLE Position */
-#define I2C0_STAT_MONIDLE_Msk (0x01UL << I2C0_STAT_MONIDLE_Pos) /*!< I2C0 STAT: MONIDLE Mask */
-#define I2C0_STAT_EVENTTIMEOUT_Pos 24 /*!< I2C0 STAT: EVENTTIMEOUT Position */
-#define I2C0_STAT_EVENTTIMEOUT_Msk (0x01UL << I2C0_STAT_EVENTTIMEOUT_Pos) /*!< I2C0 STAT: EVENTTIMEOUT Mask */
-#define I2C0_STAT_SCLTIMEOUT_Pos 25 /*!< I2C0 STAT: SCLTIMEOUT Position */
-#define I2C0_STAT_SCLTIMEOUT_Msk (0x01UL << I2C0_STAT_SCLTIMEOUT_Pos) /*!< I2C0 STAT: SCLTIMEOUT Mask */
-
-/* ------------------------------- u0_i2c_INTENSET ------------------------------ */
-#define I2C0_INTENSET_MSTPENDINGEN_Pos 0 /*!< I2C0 INTENSET: MSTPENDINGEN Position */
-#define I2C0_INTENSET_MSTPENDINGEN_Msk (0x01UL << I2C0_INTENSET_MSTPENDINGEN_Pos) /*!< I2C0 INTENSET: MSTPENDINGEN Mask */
-#define I2C0_INTENSET_MSTARBLOSSEN_Pos 4 /*!< I2C0 INTENSET: MSTARBLOSSEN Position */
-#define I2C0_INTENSET_MSTARBLOSSEN_Msk (0x01UL << I2C0_INTENSET_MSTARBLOSSEN_Pos) /*!< I2C0 INTENSET: MSTARBLOSSEN Mask */
-#define I2C0_INTENSET_MSTSTSTPERREN_Pos 6 /*!< I2C0 INTENSET: MSTSTSTPERREN Position */
-#define I2C0_INTENSET_MSTSTSTPERREN_Msk (0x01UL << I2C0_INTENSET_MSTSTSTPERREN_Pos) /*!< I2C0 INTENSET: MSTSTSTPERREN Mask */
-#define I2C0_INTENSET_SLVPENDINGEN_Pos 8 /*!< I2C0 INTENSET: SLVPENDINGEN Position */
-#define I2C0_INTENSET_SLVPENDINGEN_Msk (0x01UL << I2C0_INTENSET_SLVPENDINGEN_Pos) /*!< I2C0 INTENSET: SLVPENDINGEN Mask */
-#define I2C0_INTENSET_SLVNOTSTREN_Pos 11 /*!< I2C0 INTENSET: SLVNOTSTREN Position */
-#define I2C0_INTENSET_SLVNOTSTREN_Msk (0x01UL << I2C0_INTENSET_SLVNOTSTREN_Pos) /*!< I2C0 INTENSET: SLVNOTSTREN Mask */
-#define I2C0_INTENSET_SLVDESELEN_Pos 15 /*!< I2C0 INTENSET: SLVDESELEN Position */
-#define I2C0_INTENSET_SLVDESELEN_Msk (0x01UL << I2C0_INTENSET_SLVDESELEN_Pos) /*!< I2C0 INTENSET: SLVDESELEN Mask */
-#define I2C0_INTENSET_MONRDYEN_Pos 16 /*!< I2C0 INTENSET: MONRDYEN Position */
-#define I2C0_INTENSET_MONRDYEN_Msk (0x01UL << I2C0_INTENSET_MONRDYEN_Pos) /*!< I2C0 INTENSET: MONRDYEN Mask */
-#define I2C0_INTENSET_MONOVEN_Pos 17 /*!< I2C0 INTENSET: MONOVEN Position */
-#define I2C0_INTENSET_MONOVEN_Msk (0x01UL << I2C0_INTENSET_MONOVEN_Pos) /*!< I2C0 INTENSET: MONOVEN Mask */
-#define I2C0_INTENSET_MONIDLEEN_Pos 19 /*!< I2C0 INTENSET: MONIDLEEN Position */
-#define I2C0_INTENSET_MONIDLEEN_Msk (0x01UL << I2C0_INTENSET_MONIDLEEN_Pos) /*!< I2C0 INTENSET: MONIDLEEN Mask */
-#define I2C0_INTENSET_EVENTTIMEOUTEN_Pos 24 /*!< I2C0 INTENSET: EVENTTIMEOUTEN Position */
-#define I2C0_INTENSET_EVENTTIMEOUTEN_Msk (0x01UL << I2C0_INTENSET_EVENTTIMEOUTEN_Pos) /*!< I2C0 INTENSET: EVENTTIMEOUTEN Mask */
-#define I2C0_INTENSET_SCLTIMEOUTEN_Pos 25 /*!< I2C0 INTENSET: SCLTIMEOUTEN Position */
-#define I2C0_INTENSET_SCLTIMEOUTEN_Msk (0x01UL << I2C0_INTENSET_SCLTIMEOUTEN_Pos) /*!< I2C0 INTENSET: SCLTIMEOUTEN Mask */
-
-/* ------------------------------- u0_i2c_INTENCLR ------------------------------ */
-#define I2C0_INTENCLR_MSTPCLRDINGCLR_Pos 0 /*!< I2C0 INTENCLR: MSTPCLRDINGCLR Position */
-#define I2C0_INTENCLR_MSTPCLRDINGCLR_Msk (0x01UL << I2C0_INTENCLR_MSTPCLRDINGCLR_Pos) /*!< I2C0 INTENCLR: MSTPCLRDINGCLR Mask */
-#define I2C0_INTENCLR_MSTARBLOSSCLR_Pos 4 /*!< I2C0 INTENCLR: MSTARBLOSSCLR Position */
-#define I2C0_INTENCLR_MSTARBLOSSCLR_Msk (0x01UL << I2C0_INTENCLR_MSTARBLOSSCLR_Pos) /*!< I2C0 INTENCLR: MSTARBLOSSCLR Mask */
-#define I2C0_INTENCLR_MSTSTSTPERRCLR_Pos 6 /*!< I2C0 INTENCLR: MSTSTSTPERRCLR Position */
-#define I2C0_INTENCLR_MSTSTSTPERRCLR_Msk (0x01UL << I2C0_INTENCLR_MSTSTSTPERRCLR_Pos) /*!< I2C0 INTENCLR: MSTSTSTPERRCLR Mask */
-#define I2C0_INTENCLR_SLVPENDINGCLR_Pos 8 /*!< I2C0 INTENCLR: SLVPENDINGCLR Position */
-#define I2C0_INTENCLR_SLVPENDINGCLR_Msk (0x01UL << I2C0_INTENCLR_SLVPENDINGCLR_Pos) /*!< I2C0 INTENCLR: SLVPENDINGCLR Mask */
-#define I2C0_INTENCLR_SLVNOTSTRCLR_Pos 11 /*!< I2C0 INTENCLR: SLVNOTSTRCLR Position */
-#define I2C0_INTENCLR_SLVNOTSTRCLR_Msk (0x01UL << I2C0_INTENCLR_SLVNOTSTRCLR_Pos) /*!< I2C0 INTENCLR: SLVNOTSTRCLR Mask */
-#define I2C0_INTENCLR_SLVDESELCLR_Pos 15 /*!< I2C0 INTENCLR: SLVDESELCLR Position */
-#define I2C0_INTENCLR_SLVDESELCLR_Msk (0x01UL << I2C0_INTENCLR_SLVDESELCLR_Pos) /*!< I2C0 INTENCLR: SLVDESELCLR Mask */
-#define I2C0_INTENCLR_MONRDYCLR_Pos 16 /*!< I2C0 INTENCLR: MONRDYCLR Position */
-#define I2C0_INTENCLR_MONRDYCLR_Msk (0x01UL << I2C0_INTENCLR_MONRDYCLR_Pos) /*!< I2C0 INTENCLR: MONRDYCLR Mask */
-#define I2C0_INTENCLR_MONOVCLR_Pos 17 /*!< I2C0 INTENCLR: MONOVCLR Position */
-#define I2C0_INTENCLR_MONOVCLR_Msk (0x01UL << I2C0_INTENCLR_MONOVCLR_Pos) /*!< I2C0 INTENCLR: MONOVCLR Mask */
-#define I2C0_INTENCLR_MONIDLECLR_Pos 19 /*!< I2C0 INTENCLR: MONIDLECLR Position */
-#define I2C0_INTENCLR_MONIDLECLR_Msk (0x01UL << I2C0_INTENCLR_MONIDLECLR_Pos) /*!< I2C0 INTENCLR: MONIDLECLR Mask */
-#define I2C0_INTENCLR_EVCLRTTIMEOUTCLR_Pos 24 /*!< I2C0 INTENCLR: EVCLRTTIMEOUTCLR Position */
-#define I2C0_INTENCLR_EVCLRTTIMEOUTCLR_Msk (0x01UL << I2C0_INTENCLR_EVCLRTTIMEOUTCLR_Pos) /*!< I2C0 INTENCLR: EVCLRTTIMEOUTCLR Mask */
-#define I2C0_INTENCLR_SCLTIMEOUTCLR_Pos 25 /*!< I2C0 INTENCLR: SCLTIMEOUTCLR Position */
-#define I2C0_INTENCLR_SCLTIMEOUTCLR_Msk (0x01UL << I2C0_INTENCLR_SCLTIMEOUTCLR_Pos) /*!< I2C0 INTENCLR: SCLTIMEOUTCLR Mask */
-
-/* ------------------------------- u0_i2c_TIMEOUT ------------------------------- */
-#define I2C0_TIMEOUT_TOMIN_Pos 0 /*!< I2C0 TIMEOUT: TOMIN Position */
-#define I2C0_TIMEOUT_TOMIN_Msk (0x0fUL << I2C0_TIMEOUT_TOMIN_Pos) /*!< I2C0 TIMEOUT: TOMIN Mask */
-#define I2C0_TIMEOUT_TO_Pos 4 /*!< I2C0 TIMEOUT: TO Position */
-#define I2C0_TIMEOUT_TO_Msk (0x00000fffUL << I2C0_TIMEOUT_TO_Pos) /*!< I2C0 TIMEOUT: TO Mask */
-
-/* -------------------------------- u0_i2c_CLKDIV ------------------------------- */
-#define I2C0_CLKDIV_DIVVAL_Pos 0 /*!< I2C0 CLKDIV: DIVVAL Position */
-#define I2C0_CLKDIV_DIVVAL_Msk (0x0000ffffUL << I2C0_CLKDIV_DIVVAL_Pos) /*!< I2C0 CLKDIV: DIVVAL Mask */
-
-/* ------------------------------- u0_i2c_INTSTAT ------------------------------- */
-#define I2C0_INTSTAT_MSTPDING_Pos 0 /*!< I2C0 INTSTAT: MSTPDING Position */
-#define I2C0_INTSTAT_MSTPDING_Msk (0x01UL << I2C0_INTSTAT_MSTPDING_Pos) /*!< I2C0 INTSTAT: MSTPDING Mask */
-#define I2C0_INTSTAT_MSTARBLOSS_Pos 4 /*!< I2C0 INTSTAT: MSTARBLOSS Position */
-#define I2C0_INTSTAT_MSTARBLOSS_Msk (0x01UL << I2C0_INTSTAT_MSTARBLOSS_Pos) /*!< I2C0 INTSTAT: MSTARBLOSS Mask */
-#define I2C0_INTSTAT_MSTSTSTPERR_Pos 6 /*!< I2C0 INTSTAT: MSTSTSTPERR Position */
-#define I2C0_INTSTAT_MSTSTSTPERR_Msk (0x01UL << I2C0_INTSTAT_MSTSTSTPERR_Pos) /*!< I2C0 INTSTAT: MSTSTSTPERR Mask */
-#define I2C0_INTSTAT_SLVPENDING_Pos 8 /*!< I2C0 INTSTAT: SLVPENDING Position */
-#define I2C0_INTSTAT_SLVPENDING_Msk (0x01UL << I2C0_INTSTAT_SLVPENDING_Pos) /*!< I2C0 INTSTAT: SLVPENDING Mask */
-#define I2C0_INTSTAT_SLVNOTSTR_Pos 11 /*!< I2C0 INTSTAT: SLVNOTSTR Position */
-#define I2C0_INTSTAT_SLVNOTSTR_Msk (0x01UL << I2C0_INTSTAT_SLVNOTSTR_Pos) /*!< I2C0 INTSTAT: SLVNOTSTR Mask */
-#define I2C0_INTSTAT_SLVDESEL_Pos 15 /*!< I2C0 INTSTAT: SLVDESEL Position */
-#define I2C0_INTSTAT_SLVDESEL_Msk (0x01UL << I2C0_INTSTAT_SLVDESEL_Pos) /*!< I2C0 INTSTAT: SLVDESEL Mask */
-#define I2C0_INTSTAT_MONRDY_Pos 16 /*!< I2C0 INTSTAT: MONRDY Position */
-#define I2C0_INTSTAT_MONRDY_Msk (0x01UL << I2C0_INTSTAT_MONRDY_Pos) /*!< I2C0 INTSTAT: MONRDY Mask */
-#define I2C0_INTSTAT_MONOV_Pos 17 /*!< I2C0 INTSTAT: MONOV Position */
-#define I2C0_INTSTAT_MONOV_Msk (0x01UL << I2C0_INTSTAT_MONOV_Pos) /*!< I2C0 INTSTAT: MONOV Mask */
-#define I2C0_INTSTAT_MONIDLE_Pos 19 /*!< I2C0 INTSTAT: MONIDLE Position */
-#define I2C0_INTSTAT_MONIDLE_Msk (0x01UL << I2C0_INTSTAT_MONIDLE_Pos) /*!< I2C0 INTSTAT: MONIDLE Mask */
-#define I2C0_INTSTAT_EVTTIMEOUT_Pos 24 /*!< I2C0 INTSTAT: EVTTIMEOUT Position */
-#define I2C0_INTSTAT_EVTTIMEOUT_Msk (0x01UL << I2C0_INTSTAT_EVTTIMEOUT_Pos) /*!< I2C0 INTSTAT: EVTTIMEOUT Mask */
-#define I2C0_INTSTAT_SCLTIMEOUT_Pos 25 /*!< I2C0 INTSTAT: SCLTIMEOUT Position */
-#define I2C0_INTSTAT_SCLTIMEOUT_Msk (0x01UL << I2C0_INTSTAT_SCLTIMEOUT_Pos) /*!< I2C0 INTSTAT: SCLTIMEOUT Mask */
-
-/* -------------------------------- u0_i2c_MSTCTL ------------------------------- */
-#define I2C0_MSTCTL_MSTCONTINUE_Pos 0 /*!< I2C0 MSTCTL: MSTCONTINUE Position */
-#define I2C0_MSTCTL_MSTCONTINUE_Msk (0x01UL << I2C0_MSTCTL_MSTCONTINUE_Pos) /*!< I2C0 MSTCTL: MSTCONTINUE Mask */
-#define I2C0_MSTCTL_MSTSTART_Pos 1 /*!< I2C0 MSTCTL: MSTSTART Position */
-#define I2C0_MSTCTL_MSTSTART_Msk (0x01UL << I2C0_MSTCTL_MSTSTART_Pos) /*!< I2C0 MSTCTL: MSTSTART Mask */
-#define I2C0_MSTCTL_MSTSTOP_Pos 2 /*!< I2C0 MSTCTL: MSTSTOP Position */
-#define I2C0_MSTCTL_MSTSTOP_Msk (0x01UL << I2C0_MSTCTL_MSTSTOP_Pos) /*!< I2C0 MSTCTL: MSTSTOP Mask */
-#define I2C0_MSTCTL_MSTDMA_Pos 3 /*!< I2C0 MSTCTL: MSTDMA Position */
-#define I2C0_MSTCTL_MSTDMA_Msk (0x01UL << I2C0_MSTCTL_MSTDMA_Pos) /*!< I2C0 MSTCTL: MSTDMA Mask */
-
-/* ------------------------------- u0_i2c_MSTTIME ------------------------------- */
-#define I2C0_MSTTIME_MSTSCLLOW_Pos 0 /*!< I2C0 MSTTIME: MSTSCLLOW Position */
-#define I2C0_MSTTIME_MSTSCLLOW_Msk (0x07UL << I2C0_MSTTIME_MSTSCLLOW_Pos) /*!< I2C0 MSTTIME: MSTSCLLOW Mask */
-#define I2C0_MSTTIME_MSTSCLHIGH_Pos 4 /*!< I2C0 MSTTIME: MSTSCLHIGH Position */
-#define I2C0_MSTTIME_MSTSCLHIGH_Msk (0x07UL << I2C0_MSTTIME_MSTSCLHIGH_Pos) /*!< I2C0 MSTTIME: MSTSCLHIGH Mask */
-
-/* -------------------------------- u0_i2c_MSTDAT ------------------------------- */
-#define I2C0_MSTDAT_DATA_Pos 0 /*!< I2C0 MSTDAT: DATA Position */
-#define I2C0_MSTDAT_DATA_Msk (0x000000ffUL << I2C0_MSTDAT_DATA_Pos) /*!< I2C0 MSTDAT: DATA Mask */
-
-/* -------------------------------- u0_i2c_SLVCTL ------------------------------- */
-#define I2C0_SLVCTL_SLVCONTINUE_Pos 0 /*!< I2C0 SLVCTL: SLVCONTINUE Position */
-#define I2C0_SLVCTL_SLVCONTINUE_Msk (0x01UL << I2C0_SLVCTL_SLVCONTINUE_Pos) /*!< I2C0 SLVCTL: SLVCONTINUE Mask */
-#define I2C0_SLVCTL_SLVNACK_Pos 1 /*!< I2C0 SLVCTL: SLVNACK Position */
-#define I2C0_SLVCTL_SLVNACK_Msk (0x01UL << I2C0_SLVCTL_SLVNACK_Pos) /*!< I2C0 SLVCTL: SLVNACK Mask */
-#define I2C0_SLVCTL_SLVDMA_Pos 3 /*!< I2C0 SLVCTL: SLVDMA Position */
-#define I2C0_SLVCTL_SLVDMA_Msk (0x01UL << I2C0_SLVCTL_SLVDMA_Pos) /*!< I2C0 SLVCTL: SLVDMA Mask */
-#define I2C0_SLVCTL_AUTOACK_Pos 8 /*!< I2C0 SLVCTL: AUTOACK Position */
-#define I2C0_SLVCTL_AUTOACK_Msk (0x01UL << I2C0_SLVCTL_AUTOACK_Pos) /*!< I2C0 SLVCTL: AUTOACK Mask */
-#define I2C0_SLVCTL_AUTOMATCHREAD_Pos 9 /*!< I2C0 SLVCTL: AUTOMATCHREAD Position */
-#define I2C0_SLVCTL_AUTOMATCHREAD_Msk (0x01UL << I2C0_SLVCTL_AUTOMATCHREAD_Pos) /*!< I2C0 SLVCTL: AUTOMATCHREAD Mask */
-
-/* -------------------------------- u0_i2c_SLVDAT ------------------------------- */
-#define I2C0_SLVDAT_DATA_Pos 0 /*!< I2C0 SLVDAT: DATA Position */
-#define I2C0_SLVDAT_DATA_Msk (0x000000ffUL << I2C0_SLVDAT_DATA_Pos) /*!< I2C0 SLVDAT: DATA Mask */
-
-/* ------------------------------- u0_i2c_SLVADR0 ------------------------------- */
-#define I2C0_SLVADR0_SADISABLE0_Pos 0 /*!< I2C0 SLVADR0: SADISABLE0 Position */
-#define I2C0_SLVADR0_SADISABLE0_Msk (0x01UL << I2C0_SLVADR0_SADISABLE0_Pos) /*!< I2C0 SLVADR0: SADISABLE0 Mask */
-#define I2C0_SLVADR0_SLVADR0_Pos 1 /*!< I2C0 SLVADR0: SLVADR0 Position */
-#define I2C0_SLVADR0_SLVADR0_Msk (0x7fUL << I2C0_SLVADR0_SLVADR0_Pos) /*!< I2C0 SLVADR0: SLVADR0 Mask */
-#define I2C0_SLVADR0_AUTONACK_Pos 15 /*!< I2C0 SLVADR0: AUTONACK Position */
-#define I2C0_SLVADR0_AUTONACK_Msk (0x01UL << I2C0_SLVADR0_AUTONACK_Pos) /*!< I2C0 SLVADR0: AUTONACK Mask */
-
-/* ------------------------------- u0_i2c_SLVADR1 ------------------------------- */
-#define I2C0_SLVADR1_SADISABLE_Pos 0 /*!< I2C0 SLVADR1: SADISABLE Position */
-#define I2C0_SLVADR1_SADISABLE_Msk (0x01UL << I2C0_SLVADR1_SADISABLE_Pos) /*!< I2C0 SLVADR1: SADISABLE Mask */
-#define I2C0_SLVADR1_SLVADR_Pos 1 /*!< I2C0 SLVADR1: SLVADR Position */
-#define I2C0_SLVADR1_SLVADR_Msk (0x7fUL << I2C0_SLVADR1_SLVADR_Pos) /*!< I2C0 SLVADR1: SLVADR Mask */
-
-/* ------------------------------- u0_i2c_SLVADR2 ------------------------------- */
-#define I2C0_SLVADR2_SADISABLE_Pos 0 /*!< I2C0 SLVADR2: SADISABLE Position */
-#define I2C0_SLVADR2_SADISABLE_Msk (0x01UL << I2C0_SLVADR2_SADISABLE_Pos) /*!< I2C0 SLVADR2: SADISABLE Mask */
-#define I2C0_SLVADR2_SLVADR_Pos 1 /*!< I2C0 SLVADR2: SLVADR Position */
-#define I2C0_SLVADR2_SLVADR_Msk (0x7fUL << I2C0_SLVADR2_SLVADR_Pos) /*!< I2C0 SLVADR2: SLVADR Mask */
-
-/* ------------------------------- u0_i2c_SLVADR3 ------------------------------- */
-#define I2C0_SLVADR3_SADISABLE_Pos 0 /*!< I2C0 SLVADR3: SADISABLE Position */
-#define I2C0_SLVADR3_SADISABLE_Msk (0x01UL << I2C0_SLVADR3_SADISABLE_Pos) /*!< I2C0 SLVADR3: SADISABLE Mask */
-#define I2C0_SLVADR3_SLVADR_Pos 1 /*!< I2C0 SLVADR3: SLVADR Position */
-#define I2C0_SLVADR3_SLVADR_Msk (0x7fUL << I2C0_SLVADR3_SLVADR_Pos) /*!< I2C0 SLVADR3: SLVADR Mask */
-
-/* ------------------------------- u0_i2c_SLVQUAL0 ------------------------------ */
-#define I2C0_SLVQUAL0_QUALMODE0_Pos 0 /*!< I2C0 SLVQUAL0: QUALMODE0 Position */
-#define I2C0_SLVQUAL0_QUALMODE0_Msk (0x01UL << I2C0_SLVQUAL0_QUALMODE0_Pos) /*!< I2C0 SLVQUAL0: QUALMODE0 Mask */
-#define I2C0_SLVQUAL0_SLVQUAL0_Pos 1 /*!< I2C0 SLVQUAL0: SLVQUAL0 Position */
-#define I2C0_SLVQUAL0_SLVQUAL0_Msk (0x7fUL << I2C0_SLVQUAL0_SLVQUAL0_Pos) /*!< I2C0 SLVQUAL0: SLVQUAL0 Mask */
-
-/* ------------------------------- u0_i2c_MONRXDAT ------------------------------ */
-#define I2C0_MONRXDAT_MONRXDAT_Pos 0 /*!< I2C0 MONRXDAT: MONRXDAT Position */
-#define I2C0_MONRXDAT_MONRXDAT_Msk (0x000000ffUL << I2C0_MONRXDAT_MONRXDAT_Pos) /*!< I2C0 MONRXDAT: MONRXDAT Mask */
-#define I2C0_MONRXDAT_MONSTART_Pos 8 /*!< I2C0 MONRXDAT: MONSTART Position */
-#define I2C0_MONRXDAT_MONSTART_Msk (0x01UL << I2C0_MONRXDAT_MONSTART_Pos) /*!< I2C0 MONRXDAT: MONSTART Mask */
-#define I2C0_MONRXDAT_MONRESTART_Pos 9 /*!< I2C0 MONRXDAT: MONRESTART Position */
-#define I2C0_MONRXDAT_MONRESTART_Msk (0x01UL << I2C0_MONRXDAT_MONRESTART_Pos) /*!< I2C0 MONRXDAT: MONRESTART Mask */
-#define I2C0_MONRXDAT_MONNACK_Pos 10 /*!< I2C0 MONRXDAT: MONNACK Position */
-#define I2C0_MONRXDAT_MONNACK_Msk (0x01UL << I2C0_MONRXDAT_MONNACK_Pos) /*!< I2C0 MONRXDAT: MONNACK Mask */
-
-/* ---------------------------------- u0_i2c_ID --------------------------------- */
-#define I2C0_ID_APERTURE_Pos 0 /*!< I2C0 ID: APERTURE Position */
-#define I2C0_ID_APERTURE_Msk (0x000000ffUL << I2C0_ID_APERTURE_Pos) /*!< I2C0 ID: APERTURE Mask */
-#define I2C0_ID_MIN_REV_Pos 8 /*!< I2C0 ID: MIN_REV Position */
-#define I2C0_ID_MIN_REV_Msk (0x0fUL << I2C0_ID_MIN_REV_Pos) /*!< I2C0 ID: MIN_REV Mask */
-#define I2C0_ID_MAJ_REV_Pos 12 /*!< I2C0 ID: MAJ_REV Position */
-#define I2C0_ID_MAJ_REV_Msk (0x0fUL << I2C0_ID_MAJ_REV_Pos) /*!< I2C0 ID: MAJ_REV Mask */
-#define I2C0_ID_ID_Pos 16 /*!< I2C0 ID: ID Position */
-#define I2C0_ID_ID_Msk (0x0000ffffUL << I2C0_ID_ID_Pos) /*!< I2C0 ID: ID Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u1_i2c' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* --------------------------------- u1_i2c_CFG --------------------------------- */
-#define I2C1_CFG_MSTEN_Pos 0 /*!< I2C1 CFG: MSTEN Position */
-#define I2C1_CFG_MSTEN_Msk (0x01UL << I2C1_CFG_MSTEN_Pos) /*!< I2C1 CFG: MSTEN Mask */
-#define I2C1_CFG_SLVEN_Pos 1 /*!< I2C1 CFG: SLVEN Position */
-#define I2C1_CFG_SLVEN_Msk (0x01UL << I2C1_CFG_SLVEN_Pos) /*!< I2C1 CFG: SLVEN Mask */
-#define I2C1_CFG_MONEN_Pos 2 /*!< I2C1 CFG: MONEN Position */
-#define I2C1_CFG_MONEN_Msk (0x01UL << I2C1_CFG_MONEN_Pos) /*!< I2C1 CFG: MONEN Mask */
-#define I2C1_CFG_TIMEOUT_Pos 3 /*!< I2C1 CFG: TIMEOUT Position */
-#define I2C1_CFG_TIMEOUT_Msk (0x01UL << I2C1_CFG_TIMEOUT_Pos) /*!< I2C1 CFG: TIMEOUT Mask */
-#define I2C1_CFG_MONCLKSTR_Pos 4 /*!< I2C1 CFG: MONCLKSTR Position */
-#define I2C1_CFG_MONCLKSTR_Msk (0x01UL << I2C1_CFG_MONCLKSTR_Pos) /*!< I2C1 CFG: MONCLKSTR Mask */
-#define I2C1_CFG_HSCAPABLE_Pos 5 /*!< I2C1 CFG: HSCAPABLE Position */
-#define I2C1_CFG_HSCAPABLE_Msk (0x01UL << I2C1_CFG_HSCAPABLE_Pos) /*!< I2C1 CFG: HSCAPABLE Mask */
-
-/* --------------------------------- u1_i2c_STAT -------------------------------- */
-#define I2C1_STAT_MSTPENDING_Pos 0 /*!< I2C1 STAT: MSTPENDING Position */
-#define I2C1_STAT_MSTPENDING_Msk (0x01UL << I2C1_STAT_MSTPENDING_Pos) /*!< I2C1 STAT: MSTPENDING Mask */
-#define I2C1_STAT_MSTSTATE_Pos 1 /*!< I2C1 STAT: MSTSTATE Position */
-#define I2C1_STAT_MSTSTATE_Msk (0x07UL << I2C1_STAT_MSTSTATE_Pos) /*!< I2C1 STAT: MSTSTATE Mask */
-#define I2C1_STAT_MSTARBLOSS_Pos 4 /*!< I2C1 STAT: MSTARBLOSS Position */
-#define I2C1_STAT_MSTARBLOSS_Msk (0x01UL << I2C1_STAT_MSTARBLOSS_Pos) /*!< I2C1 STAT: MSTARBLOSS Mask */
-#define I2C1_STAT_MSTSTSTPERR_Pos 6 /*!< I2C1 STAT: MSTSTSTPERR Position */
-#define I2C1_STAT_MSTSTSTPERR_Msk (0x01UL << I2C1_STAT_MSTSTSTPERR_Pos) /*!< I2C1 STAT: MSTSTSTPERR Mask */
-#define I2C1_STAT_SLVPENDING_Pos 8 /*!< I2C1 STAT: SLVPENDING Position */
-#define I2C1_STAT_SLVPENDING_Msk (0x01UL << I2C1_STAT_SLVPENDING_Pos) /*!< I2C1 STAT: SLVPENDING Mask */
-#define I2C1_STAT_SLVSTATE_Pos 9 /*!< I2C1 STAT: SLVSTATE Position */
-#define I2C1_STAT_SLVSTATE_Msk (0x03UL << I2C1_STAT_SLVSTATE_Pos) /*!< I2C1 STAT: SLVSTATE Mask */
-#define I2C1_STAT_SLVNOTSTR_Pos 11 /*!< I2C1 STAT: SLVNOTSTR Position */
-#define I2C1_STAT_SLVNOTSTR_Msk (0x01UL << I2C1_STAT_SLVNOTSTR_Pos) /*!< I2C1 STAT: SLVNOTSTR Mask */
-#define I2C1_STAT_SLVIDX_Pos 12 /*!< I2C1 STAT: SLVIDX Position */
-#define I2C1_STAT_SLVIDX_Msk (0x03UL << I2C1_STAT_SLVIDX_Pos) /*!< I2C1 STAT: SLVIDX Mask */
-#define I2C1_STAT_SLVSEL_Pos 14 /*!< I2C1 STAT: SLVSEL Position */
-#define I2C1_STAT_SLVSEL_Msk (0x01UL << I2C1_STAT_SLVSEL_Pos) /*!< I2C1 STAT: SLVSEL Mask */
-#define I2C1_STAT_SLVDESEL_Pos 15 /*!< I2C1 STAT: SLVDESEL Position */
-#define I2C1_STAT_SLVDESEL_Msk (0x01UL << I2C1_STAT_SLVDESEL_Pos) /*!< I2C1 STAT: SLVDESEL Mask */
-#define I2C1_STAT_MONRDY_Pos 16 /*!< I2C1 STAT: MONRDY Position */
-#define I2C1_STAT_MONRDY_Msk (0x01UL << I2C1_STAT_MONRDY_Pos) /*!< I2C1 STAT: MONRDY Mask */
-#define I2C1_STAT_MONOV_Pos 17 /*!< I2C1 STAT: MONOV Position */
-#define I2C1_STAT_MONOV_Msk (0x01UL << I2C1_STAT_MONOV_Pos) /*!< I2C1 STAT: MONOV Mask */
-#define I2C1_STAT_MONACTIVE_Pos 18 /*!< I2C1 STAT: MONACTIVE Position */
-#define I2C1_STAT_MONACTIVE_Msk (0x01UL << I2C1_STAT_MONACTIVE_Pos) /*!< I2C1 STAT: MONACTIVE Mask */
-#define I2C1_STAT_MONIDLE_Pos 19 /*!< I2C1 STAT: MONIDLE Position */
-#define I2C1_STAT_MONIDLE_Msk (0x01UL << I2C1_STAT_MONIDLE_Pos) /*!< I2C1 STAT: MONIDLE Mask */
-#define I2C1_STAT_EVENTTIMEOUT_Pos 24 /*!< I2C1 STAT: EVENTTIMEOUT Position */
-#define I2C1_STAT_EVENTTIMEOUT_Msk (0x01UL << I2C1_STAT_EVENTTIMEOUT_Pos) /*!< I2C1 STAT: EVENTTIMEOUT Mask */
-#define I2C1_STAT_SCLTIMEOUT_Pos 25 /*!< I2C1 STAT: SCLTIMEOUT Position */
-#define I2C1_STAT_SCLTIMEOUT_Msk (0x01UL << I2C1_STAT_SCLTIMEOUT_Pos) /*!< I2C1 STAT: SCLTIMEOUT Mask */
-
-/* ------------------------------- u1_i2c_INTENSET ------------------------------ */
-#define I2C1_INTENSET_MSTPENDINGEN_Pos 0 /*!< I2C1 INTENSET: MSTPENDINGEN Position */
-#define I2C1_INTENSET_MSTPENDINGEN_Msk (0x01UL << I2C1_INTENSET_MSTPENDINGEN_Pos) /*!< I2C1 INTENSET: MSTPENDINGEN Mask */
-#define I2C1_INTENSET_MSTARBLOSSEN_Pos 4 /*!< I2C1 INTENSET: MSTARBLOSSEN Position */
-#define I2C1_INTENSET_MSTARBLOSSEN_Msk (0x01UL << I2C1_INTENSET_MSTARBLOSSEN_Pos) /*!< I2C1 INTENSET: MSTARBLOSSEN Mask */
-#define I2C1_INTENSET_MSTSTSTPERREN_Pos 6 /*!< I2C1 INTENSET: MSTSTSTPERREN Position */
-#define I2C1_INTENSET_MSTSTSTPERREN_Msk (0x01UL << I2C1_INTENSET_MSTSTSTPERREN_Pos) /*!< I2C1 INTENSET: MSTSTSTPERREN Mask */
-#define I2C1_INTENSET_SLVPENDINGEN_Pos 8 /*!< I2C1 INTENSET: SLVPENDINGEN Position */
-#define I2C1_INTENSET_SLVPENDINGEN_Msk (0x01UL << I2C1_INTENSET_SLVPENDINGEN_Pos) /*!< I2C1 INTENSET: SLVPENDINGEN Mask */
-#define I2C1_INTENSET_SLVNOTSTREN_Pos 11 /*!< I2C1 INTENSET: SLVNOTSTREN Position */
-#define I2C1_INTENSET_SLVNOTSTREN_Msk (0x01UL << I2C1_INTENSET_SLVNOTSTREN_Pos) /*!< I2C1 INTENSET: SLVNOTSTREN Mask */
-#define I2C1_INTENSET_SLVDESELEN_Pos 15 /*!< I2C1 INTENSET: SLVDESELEN Position */
-#define I2C1_INTENSET_SLVDESELEN_Msk (0x01UL << I2C1_INTENSET_SLVDESELEN_Pos) /*!< I2C1 INTENSET: SLVDESELEN Mask */
-#define I2C1_INTENSET_MONRDYEN_Pos 16 /*!< I2C1 INTENSET: MONRDYEN Position */
-#define I2C1_INTENSET_MONRDYEN_Msk (0x01UL << I2C1_INTENSET_MONRDYEN_Pos) /*!< I2C1 INTENSET: MONRDYEN Mask */
-#define I2C1_INTENSET_MONOVEN_Pos 17 /*!< I2C1 INTENSET: MONOVEN Position */
-#define I2C1_INTENSET_MONOVEN_Msk (0x01UL << I2C1_INTENSET_MONOVEN_Pos) /*!< I2C1 INTENSET: MONOVEN Mask */
-#define I2C1_INTENSET_MONIDLEEN_Pos 19 /*!< I2C1 INTENSET: MONIDLEEN Position */
-#define I2C1_INTENSET_MONIDLEEN_Msk (0x01UL << I2C1_INTENSET_MONIDLEEN_Pos) /*!< I2C1 INTENSET: MONIDLEEN Mask */
-#define I2C1_INTENSET_EVENTTIMEOUTEN_Pos 24 /*!< I2C1 INTENSET: EVENTTIMEOUTEN Position */
-#define I2C1_INTENSET_EVENTTIMEOUTEN_Msk (0x01UL << I2C1_INTENSET_EVENTTIMEOUTEN_Pos) /*!< I2C1 INTENSET: EVENTTIMEOUTEN Mask */
-#define I2C1_INTENSET_SCLTIMEOUTEN_Pos 25 /*!< I2C1 INTENSET: SCLTIMEOUTEN Position */
-#define I2C1_INTENSET_SCLTIMEOUTEN_Msk (0x01UL << I2C1_INTENSET_SCLTIMEOUTEN_Pos) /*!< I2C1 INTENSET: SCLTIMEOUTEN Mask */
-
-/* ------------------------------- u1_i2c_INTENCLR ------------------------------ */
-#define I2C1_INTENCLR_MSTPCLRDINGCLR_Pos 0 /*!< I2C1 INTENCLR: MSTPCLRDINGCLR Position */
-#define I2C1_INTENCLR_MSTPCLRDINGCLR_Msk (0x01UL << I2C1_INTENCLR_MSTPCLRDINGCLR_Pos) /*!< I2C1 INTENCLR: MSTPCLRDINGCLR Mask */
-#define I2C1_INTENCLR_MSTARBLOSSCLR_Pos 4 /*!< I2C1 INTENCLR: MSTARBLOSSCLR Position */
-#define I2C1_INTENCLR_MSTARBLOSSCLR_Msk (0x01UL << I2C1_INTENCLR_MSTARBLOSSCLR_Pos) /*!< I2C1 INTENCLR: MSTARBLOSSCLR Mask */
-#define I2C1_INTENCLR_MSTSTSTPERRCLR_Pos 6 /*!< I2C1 INTENCLR: MSTSTSTPERRCLR Position */
-#define I2C1_INTENCLR_MSTSTSTPERRCLR_Msk (0x01UL << I2C1_INTENCLR_MSTSTSTPERRCLR_Pos) /*!< I2C1 INTENCLR: MSTSTSTPERRCLR Mask */
-#define I2C1_INTENCLR_SLVPENDINGCLR_Pos 8 /*!< I2C1 INTENCLR: SLVPENDINGCLR Position */
-#define I2C1_INTENCLR_SLVPENDINGCLR_Msk (0x01UL << I2C1_INTENCLR_SLVPENDINGCLR_Pos) /*!< I2C1 INTENCLR: SLVPENDINGCLR Mask */
-#define I2C1_INTENCLR_SLVNOTSTRCLR_Pos 11 /*!< I2C1 INTENCLR: SLVNOTSTRCLR Position */
-#define I2C1_INTENCLR_SLVNOTSTRCLR_Msk (0x01UL << I2C1_INTENCLR_SLVNOTSTRCLR_Pos) /*!< I2C1 INTENCLR: SLVNOTSTRCLR Mask */
-#define I2C1_INTENCLR_SLVDESELCLR_Pos 15 /*!< I2C1 INTENCLR: SLVDESELCLR Position */
-#define I2C1_INTENCLR_SLVDESELCLR_Msk (0x01UL << I2C1_INTENCLR_SLVDESELCLR_Pos) /*!< I2C1 INTENCLR: SLVDESELCLR Mask */
-#define I2C1_INTENCLR_MONRDYCLR_Pos 16 /*!< I2C1 INTENCLR: MONRDYCLR Position */
-#define I2C1_INTENCLR_MONRDYCLR_Msk (0x01UL << I2C1_INTENCLR_MONRDYCLR_Pos) /*!< I2C1 INTENCLR: MONRDYCLR Mask */
-#define I2C1_INTENCLR_MONOVCLR_Pos 17 /*!< I2C1 INTENCLR: MONOVCLR Position */
-#define I2C1_INTENCLR_MONOVCLR_Msk (0x01UL << I2C1_INTENCLR_MONOVCLR_Pos) /*!< I2C1 INTENCLR: MONOVCLR Mask */
-#define I2C1_INTENCLR_MONIDLECLR_Pos 19 /*!< I2C1 INTENCLR: MONIDLECLR Position */
-#define I2C1_INTENCLR_MONIDLECLR_Msk (0x01UL << I2C1_INTENCLR_MONIDLECLR_Pos) /*!< I2C1 INTENCLR: MONIDLECLR Mask */
-#define I2C1_INTENCLR_EVCLRTTIMEOUTCLR_Pos 24 /*!< I2C1 INTENCLR: EVCLRTTIMEOUTCLR Position */
-#define I2C1_INTENCLR_EVCLRTTIMEOUTCLR_Msk (0x01UL << I2C1_INTENCLR_EVCLRTTIMEOUTCLR_Pos) /*!< I2C1 INTENCLR: EVCLRTTIMEOUTCLR Mask */
-#define I2C1_INTENCLR_SCLTIMEOUTCLR_Pos 25 /*!< I2C1 INTENCLR: SCLTIMEOUTCLR Position */
-#define I2C1_INTENCLR_SCLTIMEOUTCLR_Msk (0x01UL << I2C1_INTENCLR_SCLTIMEOUTCLR_Pos) /*!< I2C1 INTENCLR: SCLTIMEOUTCLR Mask */
-
-/* ------------------------------- u1_i2c_TIMEOUT ------------------------------- */
-#define I2C1_TIMEOUT_TOMIN_Pos 0 /*!< I2C1 TIMEOUT: TOMIN Position */
-#define I2C1_TIMEOUT_TOMIN_Msk (0x0fUL << I2C1_TIMEOUT_TOMIN_Pos) /*!< I2C1 TIMEOUT: TOMIN Mask */
-#define I2C1_TIMEOUT_TO_Pos 4 /*!< I2C1 TIMEOUT: TO Position */
-#define I2C1_TIMEOUT_TO_Msk (0x00000fffUL << I2C1_TIMEOUT_TO_Pos) /*!< I2C1 TIMEOUT: TO Mask */
-
-/* -------------------------------- u1_i2c_CLKDIV ------------------------------- */
-#define I2C1_CLKDIV_DIVVAL_Pos 0 /*!< I2C1 CLKDIV: DIVVAL Position */
-#define I2C1_CLKDIV_DIVVAL_Msk (0x0000ffffUL << I2C1_CLKDIV_DIVVAL_Pos) /*!< I2C1 CLKDIV: DIVVAL Mask */
-
-/* ------------------------------- u1_i2c_INTSTAT ------------------------------- */
-#define I2C1_INTSTAT_MSTPDING_Pos 0 /*!< I2C1 INTSTAT: MSTPDING Position */
-#define I2C1_INTSTAT_MSTPDING_Msk (0x01UL << I2C1_INTSTAT_MSTPDING_Pos) /*!< I2C1 INTSTAT: MSTPDING Mask */
-#define I2C1_INTSTAT_MSTARBLOSS_Pos 4 /*!< I2C1 INTSTAT: MSTARBLOSS Position */
-#define I2C1_INTSTAT_MSTARBLOSS_Msk (0x01UL << I2C1_INTSTAT_MSTARBLOSS_Pos) /*!< I2C1 INTSTAT: MSTARBLOSS Mask */
-#define I2C1_INTSTAT_MSTSTSTPERR_Pos 6 /*!< I2C1 INTSTAT: MSTSTSTPERR Position */
-#define I2C1_INTSTAT_MSTSTSTPERR_Msk (0x01UL << I2C1_INTSTAT_MSTSTSTPERR_Pos) /*!< I2C1 INTSTAT: MSTSTSTPERR Mask */
-#define I2C1_INTSTAT_SLVPENDING_Pos 8 /*!< I2C1 INTSTAT: SLVPENDING Position */
-#define I2C1_INTSTAT_SLVPENDING_Msk (0x01UL << I2C1_INTSTAT_SLVPENDING_Pos) /*!< I2C1 INTSTAT: SLVPENDING Mask */
-#define I2C1_INTSTAT_SLVNOTSTR_Pos 11 /*!< I2C1 INTSTAT: SLVNOTSTR Position */
-#define I2C1_INTSTAT_SLVNOTSTR_Msk (0x01UL << I2C1_INTSTAT_SLVNOTSTR_Pos) /*!< I2C1 INTSTAT: SLVNOTSTR Mask */
-#define I2C1_INTSTAT_SLVDESEL_Pos 15 /*!< I2C1 INTSTAT: SLVDESEL Position */
-#define I2C1_INTSTAT_SLVDESEL_Msk (0x01UL << I2C1_INTSTAT_SLVDESEL_Pos) /*!< I2C1 INTSTAT: SLVDESEL Mask */
-#define I2C1_INTSTAT_MONRDY_Pos 16 /*!< I2C1 INTSTAT: MONRDY Position */
-#define I2C1_INTSTAT_MONRDY_Msk (0x01UL << I2C1_INTSTAT_MONRDY_Pos) /*!< I2C1 INTSTAT: MONRDY Mask */
-#define I2C1_INTSTAT_MONOV_Pos 17 /*!< I2C1 INTSTAT: MONOV Position */
-#define I2C1_INTSTAT_MONOV_Msk (0x01UL << I2C1_INTSTAT_MONOV_Pos) /*!< I2C1 INTSTAT: MONOV Mask */
-#define I2C1_INTSTAT_MONIDLE_Pos 19 /*!< I2C1 INTSTAT: MONIDLE Position */
-#define I2C1_INTSTAT_MONIDLE_Msk (0x01UL << I2C1_INTSTAT_MONIDLE_Pos) /*!< I2C1 INTSTAT: MONIDLE Mask */
-#define I2C1_INTSTAT_EVTTIMEOUT_Pos 24 /*!< I2C1 INTSTAT: EVTTIMEOUT Position */
-#define I2C1_INTSTAT_EVTTIMEOUT_Msk (0x01UL << I2C1_INTSTAT_EVTTIMEOUT_Pos) /*!< I2C1 INTSTAT: EVTTIMEOUT Mask */
-#define I2C1_INTSTAT_SCLTIMEOUT_Pos 25 /*!< I2C1 INTSTAT: SCLTIMEOUT Position */
-#define I2C1_INTSTAT_SCLTIMEOUT_Msk (0x01UL << I2C1_INTSTAT_SCLTIMEOUT_Pos) /*!< I2C1 INTSTAT: SCLTIMEOUT Mask */
-
-/* -------------------------------- u1_i2c_MSTCTL ------------------------------- */
-#define I2C1_MSTCTL_MSTCONTINUE_Pos 0 /*!< I2C1 MSTCTL: MSTCONTINUE Position */
-#define I2C1_MSTCTL_MSTCONTINUE_Msk (0x01UL << I2C1_MSTCTL_MSTCONTINUE_Pos) /*!< I2C1 MSTCTL: MSTCONTINUE Mask */
-#define I2C1_MSTCTL_MSTSTART_Pos 1 /*!< I2C1 MSTCTL: MSTSTART Position */
-#define I2C1_MSTCTL_MSTSTART_Msk (0x01UL << I2C1_MSTCTL_MSTSTART_Pos) /*!< I2C1 MSTCTL: MSTSTART Mask */
-#define I2C1_MSTCTL_MSTSTOP_Pos 2 /*!< I2C1 MSTCTL: MSTSTOP Position */
-#define I2C1_MSTCTL_MSTSTOP_Msk (0x01UL << I2C1_MSTCTL_MSTSTOP_Pos) /*!< I2C1 MSTCTL: MSTSTOP Mask */
-#define I2C1_MSTCTL_MSTDMA_Pos 3 /*!< I2C1 MSTCTL: MSTDMA Position */
-#define I2C1_MSTCTL_MSTDMA_Msk (0x01UL << I2C1_MSTCTL_MSTDMA_Pos) /*!< I2C1 MSTCTL: MSTDMA Mask */
-
-/* ------------------------------- u1_i2c_MSTTIME ------------------------------- */
-#define I2C1_MSTTIME_MSTSCLLOW_Pos 0 /*!< I2C1 MSTTIME: MSTSCLLOW Position */
-#define I2C1_MSTTIME_MSTSCLLOW_Msk (0x07UL << I2C1_MSTTIME_MSTSCLLOW_Pos) /*!< I2C1 MSTTIME: MSTSCLLOW Mask */
-#define I2C1_MSTTIME_MSTSCLHIGH_Pos 4 /*!< I2C1 MSTTIME: MSTSCLHIGH Position */
-#define I2C1_MSTTIME_MSTSCLHIGH_Msk (0x07UL << I2C1_MSTTIME_MSTSCLHIGH_Pos) /*!< I2C1 MSTTIME: MSTSCLHIGH Mask */
-
-/* -------------------------------- u1_i2c_MSTDAT ------------------------------- */
-#define I2C1_MSTDAT_DATA_Pos 0 /*!< I2C1 MSTDAT: DATA Position */
-#define I2C1_MSTDAT_DATA_Msk (0x000000ffUL << I2C1_MSTDAT_DATA_Pos) /*!< I2C1 MSTDAT: DATA Mask */
-
-/* -------------------------------- u1_i2c_SLVCTL ------------------------------- */
-#define I2C1_SLVCTL_SLVCONTINUE_Pos 0 /*!< I2C1 SLVCTL: SLVCONTINUE Position */
-#define I2C1_SLVCTL_SLVCONTINUE_Msk (0x01UL << I2C1_SLVCTL_SLVCONTINUE_Pos) /*!< I2C1 SLVCTL: SLVCONTINUE Mask */
-#define I2C1_SLVCTL_SLVNACK_Pos 1 /*!< I2C1 SLVCTL: SLVNACK Position */
-#define I2C1_SLVCTL_SLVNACK_Msk (0x01UL << I2C1_SLVCTL_SLVNACK_Pos) /*!< I2C1 SLVCTL: SLVNACK Mask */
-#define I2C1_SLVCTL_SLVDMA_Pos 3 /*!< I2C1 SLVCTL: SLVDMA Position */
-#define I2C1_SLVCTL_SLVDMA_Msk (0x01UL << I2C1_SLVCTL_SLVDMA_Pos) /*!< I2C1 SLVCTL: SLVDMA Mask */
-#define I2C1_SLVCTL_AUTOACK_Pos 8 /*!< I2C1 SLVCTL: AUTOACK Position */
-#define I2C1_SLVCTL_AUTOACK_Msk (0x01UL << I2C1_SLVCTL_AUTOACK_Pos) /*!< I2C1 SLVCTL: AUTOACK Mask */
-#define I2C1_SLVCTL_AUTOMATCHREAD_Pos 9 /*!< I2C1 SLVCTL: AUTOMATCHREAD Position */
-#define I2C1_SLVCTL_AUTOMATCHREAD_Msk (0x01UL << I2C1_SLVCTL_AUTOMATCHREAD_Pos) /*!< I2C1 SLVCTL: AUTOMATCHREAD Mask */
-
-/* -------------------------------- u1_i2c_SLVDAT ------------------------------- */
-#define I2C1_SLVDAT_DATA_Pos 0 /*!< I2C1 SLVDAT: DATA Position */
-#define I2C1_SLVDAT_DATA_Msk (0x000000ffUL << I2C1_SLVDAT_DATA_Pos) /*!< I2C1 SLVDAT: DATA Mask */
-
-/* ------------------------------- u1_i2c_SLVADR0 ------------------------------- */
-#define I2C1_SLVADR0_SADISABLE0_Pos 0 /*!< I2C1 SLVADR0: SADISABLE0 Position */
-#define I2C1_SLVADR0_SADISABLE0_Msk (0x01UL << I2C1_SLVADR0_SADISABLE0_Pos) /*!< I2C1 SLVADR0: SADISABLE0 Mask */
-#define I2C1_SLVADR0_SLVADR0_Pos 1 /*!< I2C1 SLVADR0: SLVADR0 Position */
-#define I2C1_SLVADR0_SLVADR0_Msk (0x7fUL << I2C1_SLVADR0_SLVADR0_Pos) /*!< I2C1 SLVADR0: SLVADR0 Mask */
-#define I2C1_SLVADR0_AUTONACK_Pos 15 /*!< I2C1 SLVADR0: AUTONACK Position */
-#define I2C1_SLVADR0_AUTONACK_Msk (0x01UL << I2C1_SLVADR0_AUTONACK_Pos) /*!< I2C1 SLVADR0: AUTONACK Mask */
-
-/* ------------------------------- u1_i2c_SLVADR1 ------------------------------- */
-#define I2C1_SLVADR1_SADISABLE_Pos 0 /*!< I2C1 SLVADR1: SADISABLE Position */
-#define I2C1_SLVADR1_SADISABLE_Msk (0x01UL << I2C1_SLVADR1_SADISABLE_Pos) /*!< I2C1 SLVADR1: SADISABLE Mask */
-#define I2C1_SLVADR1_SLVADR_Pos 1 /*!< I2C1 SLVADR1: SLVADR Position */
-#define I2C1_SLVADR1_SLVADR_Msk (0x7fUL << I2C1_SLVADR1_SLVADR_Pos) /*!< I2C1 SLVADR1: SLVADR Mask */
-
-/* ------------------------------- u1_i2c_SLVADR2 ------------------------------- */
-#define I2C1_SLVADR2_SADISABLE_Pos 0 /*!< I2C1 SLVADR2: SADISABLE Position */
-#define I2C1_SLVADR2_SADISABLE_Msk (0x01UL << I2C1_SLVADR2_SADISABLE_Pos) /*!< I2C1 SLVADR2: SADISABLE Mask */
-#define I2C1_SLVADR2_SLVADR_Pos 1 /*!< I2C1 SLVADR2: SLVADR Position */
-#define I2C1_SLVADR2_SLVADR_Msk (0x7fUL << I2C1_SLVADR2_SLVADR_Pos) /*!< I2C1 SLVADR2: SLVADR Mask */
-
-/* ------------------------------- u1_i2c_SLVADR3 ------------------------------- */
-#define I2C1_SLVADR3_SADISABLE_Pos 0 /*!< I2C1 SLVADR3: SADISABLE Position */
-#define I2C1_SLVADR3_SADISABLE_Msk (0x01UL << I2C1_SLVADR3_SADISABLE_Pos) /*!< I2C1 SLVADR3: SADISABLE Mask */
-#define I2C1_SLVADR3_SLVADR_Pos 1 /*!< I2C1 SLVADR3: SLVADR Position */
-#define I2C1_SLVADR3_SLVADR_Msk (0x7fUL << I2C1_SLVADR3_SLVADR_Pos) /*!< I2C1 SLVADR3: SLVADR Mask */
-
-/* ------------------------------- u1_i2c_SLVQUAL0 ------------------------------ */
-#define I2C1_SLVQUAL0_QUALMODE0_Pos 0 /*!< I2C1 SLVQUAL0: QUALMODE0 Position */
-#define I2C1_SLVQUAL0_QUALMODE0_Msk (0x01UL << I2C1_SLVQUAL0_QUALMODE0_Pos) /*!< I2C1 SLVQUAL0: QUALMODE0 Mask */
-#define I2C1_SLVQUAL0_SLVQUAL0_Pos 1 /*!< I2C1 SLVQUAL0: SLVQUAL0 Position */
-#define I2C1_SLVQUAL0_SLVQUAL0_Msk (0x7fUL << I2C1_SLVQUAL0_SLVQUAL0_Pos) /*!< I2C1 SLVQUAL0: SLVQUAL0 Mask */
-
-/* ------------------------------- u1_i2c_MONRXDAT ------------------------------ */
-#define I2C1_MONRXDAT_MONRXDAT_Pos 0 /*!< I2C1 MONRXDAT: MONRXDAT Position */
-#define I2C1_MONRXDAT_MONRXDAT_Msk (0x000000ffUL << I2C1_MONRXDAT_MONRXDAT_Pos) /*!< I2C1 MONRXDAT: MONRXDAT Mask */
-#define I2C1_MONRXDAT_MONSTART_Pos 8 /*!< I2C1 MONRXDAT: MONSTART Position */
-#define I2C1_MONRXDAT_MONSTART_Msk (0x01UL << I2C1_MONRXDAT_MONSTART_Pos) /*!< I2C1 MONRXDAT: MONSTART Mask */
-#define I2C1_MONRXDAT_MONRESTART_Pos 9 /*!< I2C1 MONRXDAT: MONRESTART Position */
-#define I2C1_MONRXDAT_MONRESTART_Msk (0x01UL << I2C1_MONRXDAT_MONRESTART_Pos) /*!< I2C1 MONRXDAT: MONRESTART Mask */
-#define I2C1_MONRXDAT_MONNACK_Pos 10 /*!< I2C1 MONRXDAT: MONNACK Position */
-#define I2C1_MONRXDAT_MONNACK_Msk (0x01UL << I2C1_MONRXDAT_MONNACK_Pos) /*!< I2C1 MONRXDAT: MONNACK Mask */
-
-/* ---------------------------------- u1_i2c_ID --------------------------------- */
-#define I2C1_ID_APERTURE_Pos 0 /*!< I2C1 ID: APERTURE Position */
-#define I2C1_ID_APERTURE_Msk (0x000000ffUL << I2C1_ID_APERTURE_Pos) /*!< I2C1 ID: APERTURE Mask */
-#define I2C1_ID_MIN_REV_Pos 8 /*!< I2C1 ID: MIN_REV Position */
-#define I2C1_ID_MIN_REV_Msk (0x0fUL << I2C1_ID_MIN_REV_Pos) /*!< I2C1 ID: MIN_REV Mask */
-#define I2C1_ID_MAJ_REV_Pos 12 /*!< I2C1 ID: MAJ_REV Position */
-#define I2C1_ID_MAJ_REV_Msk (0x0fUL << I2C1_ID_MAJ_REV_Pos) /*!< I2C1 ID: MAJ_REV Mask */
-#define I2C1_ID_ID_Pos 16 /*!< I2C1 ID: ID Position */
-#define I2C1_ID_ID_Msk (0x0000ffffUL << I2C1_ID_ID_Pos) /*!< I2C1 ID: ID Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u2_i2c' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* --------------------------------- u2_i2c_CFG --------------------------------- */
-#define I2C2_CFG_MSTEN_Pos 0 /*!< I2C2 CFG: MSTEN Position */
-#define I2C2_CFG_MSTEN_Msk (0x01UL << I2C2_CFG_MSTEN_Pos) /*!< I2C2 CFG: MSTEN Mask */
-#define I2C2_CFG_SLVEN_Pos 1 /*!< I2C2 CFG: SLVEN Position */
-#define I2C2_CFG_SLVEN_Msk (0x01UL << I2C2_CFG_SLVEN_Pos) /*!< I2C2 CFG: SLVEN Mask */
-#define I2C2_CFG_MONEN_Pos 2 /*!< I2C2 CFG: MONEN Position */
-#define I2C2_CFG_MONEN_Msk (0x01UL << I2C2_CFG_MONEN_Pos) /*!< I2C2 CFG: MONEN Mask */
-#define I2C2_CFG_TIMEOUT_Pos 3 /*!< I2C2 CFG: TIMEOUT Position */
-#define I2C2_CFG_TIMEOUT_Msk (0x01UL << I2C2_CFG_TIMEOUT_Pos) /*!< I2C2 CFG: TIMEOUT Mask */
-#define I2C2_CFG_MONCLKSTR_Pos 4 /*!< I2C2 CFG: MONCLKSTR Position */
-#define I2C2_CFG_MONCLKSTR_Msk (0x01UL << I2C2_CFG_MONCLKSTR_Pos) /*!< I2C2 CFG: MONCLKSTR Mask */
-#define I2C2_CFG_HSCAPABLE_Pos 5 /*!< I2C2 CFG: HSCAPABLE Position */
-#define I2C2_CFG_HSCAPABLE_Msk (0x01UL << I2C2_CFG_HSCAPABLE_Pos) /*!< I2C2 CFG: HSCAPABLE Mask */
-
-/* --------------------------------- u2_i2c_STAT -------------------------------- */
-#define I2C2_STAT_MSTPENDING_Pos 0 /*!< I2C2 STAT: MSTPENDING Position */
-#define I2C2_STAT_MSTPENDING_Msk (0x01UL << I2C2_STAT_MSTPENDING_Pos) /*!< I2C2 STAT: MSTPENDING Mask */
-#define I2C2_STAT_MSTSTATE_Pos 1 /*!< I2C2 STAT: MSTSTATE Position */
-#define I2C2_STAT_MSTSTATE_Msk (0x07UL << I2C2_STAT_MSTSTATE_Pos) /*!< I2C2 STAT: MSTSTATE Mask */
-#define I2C2_STAT_MSTARBLOSS_Pos 4 /*!< I2C2 STAT: MSTARBLOSS Position */
-#define I2C2_STAT_MSTARBLOSS_Msk (0x01UL << I2C2_STAT_MSTARBLOSS_Pos) /*!< I2C2 STAT: MSTARBLOSS Mask */
-#define I2C2_STAT_MSTSTSTPERR_Pos 6 /*!< I2C2 STAT: MSTSTSTPERR Position */
-#define I2C2_STAT_MSTSTSTPERR_Msk (0x01UL << I2C2_STAT_MSTSTSTPERR_Pos) /*!< I2C2 STAT: MSTSTSTPERR Mask */
-#define I2C2_STAT_SLVPENDING_Pos 8 /*!< I2C2 STAT: SLVPENDING Position */
-#define I2C2_STAT_SLVPENDING_Msk (0x01UL << I2C2_STAT_SLVPENDING_Pos) /*!< I2C2 STAT: SLVPENDING Mask */
-#define I2C2_STAT_SLVSTATE_Pos 9 /*!< I2C2 STAT: SLVSTATE Position */
-#define I2C2_STAT_SLVSTATE_Msk (0x03UL << I2C2_STAT_SLVSTATE_Pos) /*!< I2C2 STAT: SLVSTATE Mask */
-#define I2C2_STAT_SLVNOTSTR_Pos 11 /*!< I2C2 STAT: SLVNOTSTR Position */
-#define I2C2_STAT_SLVNOTSTR_Msk (0x01UL << I2C2_STAT_SLVNOTSTR_Pos) /*!< I2C2 STAT: SLVNOTSTR Mask */
-#define I2C2_STAT_SLVIDX_Pos 12 /*!< I2C2 STAT: SLVIDX Position */
-#define I2C2_STAT_SLVIDX_Msk (0x03UL << I2C2_STAT_SLVIDX_Pos) /*!< I2C2 STAT: SLVIDX Mask */
-#define I2C2_STAT_SLVSEL_Pos 14 /*!< I2C2 STAT: SLVSEL Position */
-#define I2C2_STAT_SLVSEL_Msk (0x01UL << I2C2_STAT_SLVSEL_Pos) /*!< I2C2 STAT: SLVSEL Mask */
-#define I2C2_STAT_SLVDESEL_Pos 15 /*!< I2C2 STAT: SLVDESEL Position */
-#define I2C2_STAT_SLVDESEL_Msk (0x01UL << I2C2_STAT_SLVDESEL_Pos) /*!< I2C2 STAT: SLVDESEL Mask */
-#define I2C2_STAT_MONRDY_Pos 16 /*!< I2C2 STAT: MONRDY Position */
-#define I2C2_STAT_MONRDY_Msk (0x01UL << I2C2_STAT_MONRDY_Pos) /*!< I2C2 STAT: MONRDY Mask */
-#define I2C2_STAT_MONOV_Pos 17 /*!< I2C2 STAT: MONOV Position */
-#define I2C2_STAT_MONOV_Msk (0x01UL << I2C2_STAT_MONOV_Pos) /*!< I2C2 STAT: MONOV Mask */
-#define I2C2_STAT_MONACTIVE_Pos 18 /*!< I2C2 STAT: MONACTIVE Position */
-#define I2C2_STAT_MONACTIVE_Msk (0x01UL << I2C2_STAT_MONACTIVE_Pos) /*!< I2C2 STAT: MONACTIVE Mask */
-#define I2C2_STAT_MONIDLE_Pos 19 /*!< I2C2 STAT: MONIDLE Position */
-#define I2C2_STAT_MONIDLE_Msk (0x01UL << I2C2_STAT_MONIDLE_Pos) /*!< I2C2 STAT: MONIDLE Mask */
-#define I2C2_STAT_EVENTTIMEOUT_Pos 24 /*!< I2C2 STAT: EVENTTIMEOUT Position */
-#define I2C2_STAT_EVENTTIMEOUT_Msk (0x01UL << I2C2_STAT_EVENTTIMEOUT_Pos) /*!< I2C2 STAT: EVENTTIMEOUT Mask */
-#define I2C2_STAT_SCLTIMEOUT_Pos 25 /*!< I2C2 STAT: SCLTIMEOUT Position */
-#define I2C2_STAT_SCLTIMEOUT_Msk (0x01UL << I2C2_STAT_SCLTIMEOUT_Pos) /*!< I2C2 STAT: SCLTIMEOUT Mask */
-
-/* ------------------------------- u2_i2c_INTENSET ------------------------------ */
-#define I2C2_INTENSET_MSTPENDINGEN_Pos 0 /*!< I2C2 INTENSET: MSTPENDINGEN Position */
-#define I2C2_INTENSET_MSTPENDINGEN_Msk (0x01UL << I2C2_INTENSET_MSTPENDINGEN_Pos) /*!< I2C2 INTENSET: MSTPENDINGEN Mask */
-#define I2C2_INTENSET_MSTARBLOSSEN_Pos 4 /*!< I2C2 INTENSET: MSTARBLOSSEN Position */
-#define I2C2_INTENSET_MSTARBLOSSEN_Msk (0x01UL << I2C2_INTENSET_MSTARBLOSSEN_Pos) /*!< I2C2 INTENSET: MSTARBLOSSEN Mask */
-#define I2C2_INTENSET_MSTSTSTPERREN_Pos 6 /*!< I2C2 INTENSET: MSTSTSTPERREN Position */
-#define I2C2_INTENSET_MSTSTSTPERREN_Msk (0x01UL << I2C2_INTENSET_MSTSTSTPERREN_Pos) /*!< I2C2 INTENSET: MSTSTSTPERREN Mask */
-#define I2C2_INTENSET_SLVPENDINGEN_Pos 8 /*!< I2C2 INTENSET: SLVPENDINGEN Position */
-#define I2C2_INTENSET_SLVPENDINGEN_Msk (0x01UL << I2C2_INTENSET_SLVPENDINGEN_Pos) /*!< I2C2 INTENSET: SLVPENDINGEN Mask */
-#define I2C2_INTENSET_SLVNOTSTREN_Pos 11 /*!< I2C2 INTENSET: SLVNOTSTREN Position */
-#define I2C2_INTENSET_SLVNOTSTREN_Msk (0x01UL << I2C2_INTENSET_SLVNOTSTREN_Pos) /*!< I2C2 INTENSET: SLVNOTSTREN Mask */
-#define I2C2_INTENSET_SLVDESELEN_Pos 15 /*!< I2C2 INTENSET: SLVDESELEN Position */
-#define I2C2_INTENSET_SLVDESELEN_Msk (0x01UL << I2C2_INTENSET_SLVDESELEN_Pos) /*!< I2C2 INTENSET: SLVDESELEN Mask */
-#define I2C2_INTENSET_MONRDYEN_Pos 16 /*!< I2C2 INTENSET: MONRDYEN Position */
-#define I2C2_INTENSET_MONRDYEN_Msk (0x01UL << I2C2_INTENSET_MONRDYEN_Pos) /*!< I2C2 INTENSET: MONRDYEN Mask */
-#define I2C2_INTENSET_MONOVEN_Pos 17 /*!< I2C2 INTENSET: MONOVEN Position */
-#define I2C2_INTENSET_MONOVEN_Msk (0x01UL << I2C2_INTENSET_MONOVEN_Pos) /*!< I2C2 INTENSET: MONOVEN Mask */
-#define I2C2_INTENSET_MONIDLEEN_Pos 19 /*!< I2C2 INTENSET: MONIDLEEN Position */
-#define I2C2_INTENSET_MONIDLEEN_Msk (0x01UL << I2C2_INTENSET_MONIDLEEN_Pos) /*!< I2C2 INTENSET: MONIDLEEN Mask */
-#define I2C2_INTENSET_EVENTTIMEOUTEN_Pos 24 /*!< I2C2 INTENSET: EVENTTIMEOUTEN Position */
-#define I2C2_INTENSET_EVENTTIMEOUTEN_Msk (0x01UL << I2C2_INTENSET_EVENTTIMEOUTEN_Pos) /*!< I2C2 INTENSET: EVENTTIMEOUTEN Mask */
-#define I2C2_INTENSET_SCLTIMEOUTEN_Pos 25 /*!< I2C2 INTENSET: SCLTIMEOUTEN Position */
-#define I2C2_INTENSET_SCLTIMEOUTEN_Msk (0x01UL << I2C2_INTENSET_SCLTIMEOUTEN_Pos) /*!< I2C2 INTENSET: SCLTIMEOUTEN Mask */
-
-/* ------------------------------- u2_i2c_INTENCLR ------------------------------ */
-#define I2C2_INTENCLR_MSTPCLRDINGCLR_Pos 0 /*!< I2C2 INTENCLR: MSTPCLRDINGCLR Position */
-#define I2C2_INTENCLR_MSTPCLRDINGCLR_Msk (0x01UL << I2C2_INTENCLR_MSTPCLRDINGCLR_Pos) /*!< I2C2 INTENCLR: MSTPCLRDINGCLR Mask */
-#define I2C2_INTENCLR_MSTARBLOSSCLR_Pos 4 /*!< I2C2 INTENCLR: MSTARBLOSSCLR Position */
-#define I2C2_INTENCLR_MSTARBLOSSCLR_Msk (0x01UL << I2C2_INTENCLR_MSTARBLOSSCLR_Pos) /*!< I2C2 INTENCLR: MSTARBLOSSCLR Mask */
-#define I2C2_INTENCLR_MSTSTSTPERRCLR_Pos 6 /*!< I2C2 INTENCLR: MSTSTSTPERRCLR Position */
-#define I2C2_INTENCLR_MSTSTSTPERRCLR_Msk (0x01UL << I2C2_INTENCLR_MSTSTSTPERRCLR_Pos) /*!< I2C2 INTENCLR: MSTSTSTPERRCLR Mask */
-#define I2C2_INTENCLR_SLVPENDINGCLR_Pos 8 /*!< I2C2 INTENCLR: SLVPENDINGCLR Position */
-#define I2C2_INTENCLR_SLVPENDINGCLR_Msk (0x01UL << I2C2_INTENCLR_SLVPENDINGCLR_Pos) /*!< I2C2 INTENCLR: SLVPENDINGCLR Mask */
-#define I2C2_INTENCLR_SLVNOTSTRCLR_Pos 11 /*!< I2C2 INTENCLR: SLVNOTSTRCLR Position */
-#define I2C2_INTENCLR_SLVNOTSTRCLR_Msk (0x01UL << I2C2_INTENCLR_SLVNOTSTRCLR_Pos) /*!< I2C2 INTENCLR: SLVNOTSTRCLR Mask */
-#define I2C2_INTENCLR_SLVDESELCLR_Pos 15 /*!< I2C2 INTENCLR: SLVDESELCLR Position */
-#define I2C2_INTENCLR_SLVDESELCLR_Msk (0x01UL << I2C2_INTENCLR_SLVDESELCLR_Pos) /*!< I2C2 INTENCLR: SLVDESELCLR Mask */
-#define I2C2_INTENCLR_MONRDYCLR_Pos 16 /*!< I2C2 INTENCLR: MONRDYCLR Position */
-#define I2C2_INTENCLR_MONRDYCLR_Msk (0x01UL << I2C2_INTENCLR_MONRDYCLR_Pos) /*!< I2C2 INTENCLR: MONRDYCLR Mask */
-#define I2C2_INTENCLR_MONOVCLR_Pos 17 /*!< I2C2 INTENCLR: MONOVCLR Position */
-#define I2C2_INTENCLR_MONOVCLR_Msk (0x01UL << I2C2_INTENCLR_MONOVCLR_Pos) /*!< I2C2 INTENCLR: MONOVCLR Mask */
-#define I2C2_INTENCLR_MONIDLECLR_Pos 19 /*!< I2C2 INTENCLR: MONIDLECLR Position */
-#define I2C2_INTENCLR_MONIDLECLR_Msk (0x01UL << I2C2_INTENCLR_MONIDLECLR_Pos) /*!< I2C2 INTENCLR: MONIDLECLR Mask */
-#define I2C2_INTENCLR_EVCLRTTIMEOUTCLR_Pos 24 /*!< I2C2 INTENCLR: EVCLRTTIMEOUTCLR Position */
-#define I2C2_INTENCLR_EVCLRTTIMEOUTCLR_Msk (0x01UL << I2C2_INTENCLR_EVCLRTTIMEOUTCLR_Pos) /*!< I2C2 INTENCLR: EVCLRTTIMEOUTCLR Mask */
-#define I2C2_INTENCLR_SCLTIMEOUTCLR_Pos 25 /*!< I2C2 INTENCLR: SCLTIMEOUTCLR Position */
-#define I2C2_INTENCLR_SCLTIMEOUTCLR_Msk (0x01UL << I2C2_INTENCLR_SCLTIMEOUTCLR_Pos) /*!< I2C2 INTENCLR: SCLTIMEOUTCLR Mask */
-
-/* ------------------------------- u2_i2c_TIMEOUT ------------------------------- */
-#define I2C2_TIMEOUT_TOMIN_Pos 0 /*!< I2C2 TIMEOUT: TOMIN Position */
-#define I2C2_TIMEOUT_TOMIN_Msk (0x0fUL << I2C2_TIMEOUT_TOMIN_Pos) /*!< I2C2 TIMEOUT: TOMIN Mask */
-#define I2C2_TIMEOUT_TO_Pos 4 /*!< I2C2 TIMEOUT: TO Position */
-#define I2C2_TIMEOUT_TO_Msk (0x00000fffUL << I2C2_TIMEOUT_TO_Pos) /*!< I2C2 TIMEOUT: TO Mask */
-
-/* -------------------------------- u2_i2c_CLKDIV ------------------------------- */
-#define I2C2_CLKDIV_DIVVAL_Pos 0 /*!< I2C2 CLKDIV: DIVVAL Position */
-#define I2C2_CLKDIV_DIVVAL_Msk (0x0000ffffUL << I2C2_CLKDIV_DIVVAL_Pos) /*!< I2C2 CLKDIV: DIVVAL Mask */
-
-/* ------------------------------- u2_i2c_INTSTAT ------------------------------- */
-#define I2C2_INTSTAT_MSTPDING_Pos 0 /*!< I2C2 INTSTAT: MSTPDING Position */
-#define I2C2_INTSTAT_MSTPDING_Msk (0x01UL << I2C2_INTSTAT_MSTPDING_Pos) /*!< I2C2 INTSTAT: MSTPDING Mask */
-#define I2C2_INTSTAT_MSTARBLOSS_Pos 4 /*!< I2C2 INTSTAT: MSTARBLOSS Position */
-#define I2C2_INTSTAT_MSTARBLOSS_Msk (0x01UL << I2C2_INTSTAT_MSTARBLOSS_Pos) /*!< I2C2 INTSTAT: MSTARBLOSS Mask */
-#define I2C2_INTSTAT_MSTSTSTPERR_Pos 6 /*!< I2C2 INTSTAT: MSTSTSTPERR Position */
-#define I2C2_INTSTAT_MSTSTSTPERR_Msk (0x01UL << I2C2_INTSTAT_MSTSTSTPERR_Pos) /*!< I2C2 INTSTAT: MSTSTSTPERR Mask */
-#define I2C2_INTSTAT_SLVPENDING_Pos 8 /*!< I2C2 INTSTAT: SLVPENDING Position */
-#define I2C2_INTSTAT_SLVPENDING_Msk (0x01UL << I2C2_INTSTAT_SLVPENDING_Pos) /*!< I2C2 INTSTAT: SLVPENDING Mask */
-#define I2C2_INTSTAT_SLVNOTSTR_Pos 11 /*!< I2C2 INTSTAT: SLVNOTSTR Position */
-#define I2C2_INTSTAT_SLVNOTSTR_Msk (0x01UL << I2C2_INTSTAT_SLVNOTSTR_Pos) /*!< I2C2 INTSTAT: SLVNOTSTR Mask */
-#define I2C2_INTSTAT_SLVDESEL_Pos 15 /*!< I2C2 INTSTAT: SLVDESEL Position */
-#define I2C2_INTSTAT_SLVDESEL_Msk (0x01UL << I2C2_INTSTAT_SLVDESEL_Pos) /*!< I2C2 INTSTAT: SLVDESEL Mask */
-#define I2C2_INTSTAT_MONRDY_Pos 16 /*!< I2C2 INTSTAT: MONRDY Position */
-#define I2C2_INTSTAT_MONRDY_Msk (0x01UL << I2C2_INTSTAT_MONRDY_Pos) /*!< I2C2 INTSTAT: MONRDY Mask */
-#define I2C2_INTSTAT_MONOV_Pos 17 /*!< I2C2 INTSTAT: MONOV Position */
-#define I2C2_INTSTAT_MONOV_Msk (0x01UL << I2C2_INTSTAT_MONOV_Pos) /*!< I2C2 INTSTAT: MONOV Mask */
-#define I2C2_INTSTAT_MONIDLE_Pos 19 /*!< I2C2 INTSTAT: MONIDLE Position */
-#define I2C2_INTSTAT_MONIDLE_Msk (0x01UL << I2C2_INTSTAT_MONIDLE_Pos) /*!< I2C2 INTSTAT: MONIDLE Mask */
-#define I2C2_INTSTAT_EVTTIMEOUT_Pos 24 /*!< I2C2 INTSTAT: EVTTIMEOUT Position */
-#define I2C2_INTSTAT_EVTTIMEOUT_Msk (0x01UL << I2C2_INTSTAT_EVTTIMEOUT_Pos) /*!< I2C2 INTSTAT: EVTTIMEOUT Mask */
-#define I2C2_INTSTAT_SCLTIMEOUT_Pos 25 /*!< I2C2 INTSTAT: SCLTIMEOUT Position */
-#define I2C2_INTSTAT_SCLTIMEOUT_Msk (0x01UL << I2C2_INTSTAT_SCLTIMEOUT_Pos) /*!< I2C2 INTSTAT: SCLTIMEOUT Mask */
-
-/* -------------------------------- u2_i2c_MSTCTL ------------------------------- */
-#define I2C2_MSTCTL_MSTCONTINUE_Pos 0 /*!< I2C2 MSTCTL: MSTCONTINUE Position */
-#define I2C2_MSTCTL_MSTCONTINUE_Msk (0x01UL << I2C2_MSTCTL_MSTCONTINUE_Pos) /*!< I2C2 MSTCTL: MSTCONTINUE Mask */
-#define I2C2_MSTCTL_MSTSTART_Pos 1 /*!< I2C2 MSTCTL: MSTSTART Position */
-#define I2C2_MSTCTL_MSTSTART_Msk (0x01UL << I2C2_MSTCTL_MSTSTART_Pos) /*!< I2C2 MSTCTL: MSTSTART Mask */
-#define I2C2_MSTCTL_MSTSTOP_Pos 2 /*!< I2C2 MSTCTL: MSTSTOP Position */
-#define I2C2_MSTCTL_MSTSTOP_Msk (0x01UL << I2C2_MSTCTL_MSTSTOP_Pos) /*!< I2C2 MSTCTL: MSTSTOP Mask */
-#define I2C2_MSTCTL_MSTDMA_Pos 3 /*!< I2C2 MSTCTL: MSTDMA Position */
-#define I2C2_MSTCTL_MSTDMA_Msk (0x01UL << I2C2_MSTCTL_MSTDMA_Pos) /*!< I2C2 MSTCTL: MSTDMA Mask */
-
-/* ------------------------------- u2_i2c_MSTTIME ------------------------------- */
-#define I2C2_MSTTIME_MSTSCLLOW_Pos 0 /*!< I2C2 MSTTIME: MSTSCLLOW Position */
-#define I2C2_MSTTIME_MSTSCLLOW_Msk (0x07UL << I2C2_MSTTIME_MSTSCLLOW_Pos) /*!< I2C2 MSTTIME: MSTSCLLOW Mask */
-#define I2C2_MSTTIME_MSTSCLHIGH_Pos 4 /*!< I2C2 MSTTIME: MSTSCLHIGH Position */
-#define I2C2_MSTTIME_MSTSCLHIGH_Msk (0x07UL << I2C2_MSTTIME_MSTSCLHIGH_Pos) /*!< I2C2 MSTTIME: MSTSCLHIGH Mask */
-
-/* -------------------------------- u2_i2c_MSTDAT ------------------------------- */
-#define I2C2_MSTDAT_DATA_Pos 0 /*!< I2C2 MSTDAT: DATA Position */
-#define I2C2_MSTDAT_DATA_Msk (0x000000ffUL << I2C2_MSTDAT_DATA_Pos) /*!< I2C2 MSTDAT: DATA Mask */
-
-/* -------------------------------- u2_i2c_SLVCTL ------------------------------- */
-#define I2C2_SLVCTL_SLVCONTINUE_Pos 0 /*!< I2C2 SLVCTL: SLVCONTINUE Position */
-#define I2C2_SLVCTL_SLVCONTINUE_Msk (0x01UL << I2C2_SLVCTL_SLVCONTINUE_Pos) /*!< I2C2 SLVCTL: SLVCONTINUE Mask */
-#define I2C2_SLVCTL_SLVNACK_Pos 1 /*!< I2C2 SLVCTL: SLVNACK Position */
-#define I2C2_SLVCTL_SLVNACK_Msk (0x01UL << I2C2_SLVCTL_SLVNACK_Pos) /*!< I2C2 SLVCTL: SLVNACK Mask */
-#define I2C2_SLVCTL_SLVDMA_Pos 3 /*!< I2C2 SLVCTL: SLVDMA Position */
-#define I2C2_SLVCTL_SLVDMA_Msk (0x01UL << I2C2_SLVCTL_SLVDMA_Pos) /*!< I2C2 SLVCTL: SLVDMA Mask */
-#define I2C2_SLVCTL_AUTOACK_Pos 8 /*!< I2C2 SLVCTL: AUTOACK Position */
-#define I2C2_SLVCTL_AUTOACK_Msk (0x01UL << I2C2_SLVCTL_AUTOACK_Pos) /*!< I2C2 SLVCTL: AUTOACK Mask */
-#define I2C2_SLVCTL_AUTOMATCHREAD_Pos 9 /*!< I2C2 SLVCTL: AUTOMATCHREAD Position */
-#define I2C2_SLVCTL_AUTOMATCHREAD_Msk (0x01UL << I2C2_SLVCTL_AUTOMATCHREAD_Pos) /*!< I2C2 SLVCTL: AUTOMATCHREAD Mask */
-
-/* -------------------------------- u2_i2c_SLVDAT ------------------------------- */
-#define I2C2_SLVDAT_DATA_Pos 0 /*!< I2C2 SLVDAT: DATA Position */
-#define I2C2_SLVDAT_DATA_Msk (0x000000ffUL << I2C2_SLVDAT_DATA_Pos) /*!< I2C2 SLVDAT: DATA Mask */
-
-/* ------------------------------- u2_i2c_SLVADR0 ------------------------------- */
-#define I2C2_SLVADR0_SADISABLE0_Pos 0 /*!< I2C2 SLVADR0: SADISABLE0 Position */
-#define I2C2_SLVADR0_SADISABLE0_Msk (0x01UL << I2C2_SLVADR0_SADISABLE0_Pos) /*!< I2C2 SLVADR0: SADISABLE0 Mask */
-#define I2C2_SLVADR0_SLVADR0_Pos 1 /*!< I2C2 SLVADR0: SLVADR0 Position */
-#define I2C2_SLVADR0_SLVADR0_Msk (0x7fUL << I2C2_SLVADR0_SLVADR0_Pos) /*!< I2C2 SLVADR0: SLVADR0 Mask */
-#define I2C2_SLVADR0_AUTONACK_Pos 15 /*!< I2C2 SLVADR0: AUTONACK Position */
-#define I2C2_SLVADR0_AUTONACK_Msk (0x01UL << I2C2_SLVADR0_AUTONACK_Pos) /*!< I2C2 SLVADR0: AUTONACK Mask */
-
-/* ------------------------------- u2_i2c_SLVADR1 ------------------------------- */
-#define I2C2_SLVADR1_SADISABLE_Pos 0 /*!< I2C2 SLVADR1: SADISABLE Position */
-#define I2C2_SLVADR1_SADISABLE_Msk (0x01UL << I2C2_SLVADR1_SADISABLE_Pos) /*!< I2C2 SLVADR1: SADISABLE Mask */
-#define I2C2_SLVADR1_SLVADR_Pos 1 /*!< I2C2 SLVADR1: SLVADR Position */
-#define I2C2_SLVADR1_SLVADR_Msk (0x7fUL << I2C2_SLVADR1_SLVADR_Pos) /*!< I2C2 SLVADR1: SLVADR Mask */
-
-/* ------------------------------- u2_i2c_SLVADR2 ------------------------------- */
-#define I2C2_SLVADR2_SADISABLE_Pos 0 /*!< I2C2 SLVADR2: SADISABLE Position */
-#define I2C2_SLVADR2_SADISABLE_Msk (0x01UL << I2C2_SLVADR2_SADISABLE_Pos) /*!< I2C2 SLVADR2: SADISABLE Mask */
-#define I2C2_SLVADR2_SLVADR_Pos 1 /*!< I2C2 SLVADR2: SLVADR Position */
-#define I2C2_SLVADR2_SLVADR_Msk (0x7fUL << I2C2_SLVADR2_SLVADR_Pos) /*!< I2C2 SLVADR2: SLVADR Mask */
-
-/* ------------------------------- u2_i2c_SLVADR3 ------------------------------- */
-#define I2C2_SLVADR3_SADISABLE_Pos 0 /*!< I2C2 SLVADR3: SADISABLE Position */
-#define I2C2_SLVADR3_SADISABLE_Msk (0x01UL << I2C2_SLVADR3_SADISABLE_Pos) /*!< I2C2 SLVADR3: SADISABLE Mask */
-#define I2C2_SLVADR3_SLVADR_Pos 1 /*!< I2C2 SLVADR3: SLVADR Position */
-#define I2C2_SLVADR3_SLVADR_Msk (0x7fUL << I2C2_SLVADR3_SLVADR_Pos) /*!< I2C2 SLVADR3: SLVADR Mask */
-
-/* ------------------------------- u2_i2c_SLVQUAL0 ------------------------------ */
-#define I2C2_SLVQUAL0_QUALMODE0_Pos 0 /*!< I2C2 SLVQUAL0: QUALMODE0 Position */
-#define I2C2_SLVQUAL0_QUALMODE0_Msk (0x01UL << I2C2_SLVQUAL0_QUALMODE0_Pos) /*!< I2C2 SLVQUAL0: QUALMODE0 Mask */
-#define I2C2_SLVQUAL0_SLVQUAL0_Pos 1 /*!< I2C2 SLVQUAL0: SLVQUAL0 Position */
-#define I2C2_SLVQUAL0_SLVQUAL0_Msk (0x7fUL << I2C2_SLVQUAL0_SLVQUAL0_Pos) /*!< I2C2 SLVQUAL0: SLVQUAL0 Mask */
-
-/* ------------------------------- u2_i2c_MONRXDAT ------------------------------ */
-#define I2C2_MONRXDAT_MONRXDAT_Pos 0 /*!< I2C2 MONRXDAT: MONRXDAT Position */
-#define I2C2_MONRXDAT_MONRXDAT_Msk (0x000000ffUL << I2C2_MONRXDAT_MONRXDAT_Pos) /*!< I2C2 MONRXDAT: MONRXDAT Mask */
-#define I2C2_MONRXDAT_MONSTART_Pos 8 /*!< I2C2 MONRXDAT: MONSTART Position */
-#define I2C2_MONRXDAT_MONSTART_Msk (0x01UL << I2C2_MONRXDAT_MONSTART_Pos) /*!< I2C2 MONRXDAT: MONSTART Mask */
-#define I2C2_MONRXDAT_MONRESTART_Pos 9 /*!< I2C2 MONRXDAT: MONRESTART Position */
-#define I2C2_MONRXDAT_MONRESTART_Msk (0x01UL << I2C2_MONRXDAT_MONRESTART_Pos) /*!< I2C2 MONRXDAT: MONRESTART Mask */
-#define I2C2_MONRXDAT_MONNACK_Pos 10 /*!< I2C2 MONRXDAT: MONNACK Position */
-#define I2C2_MONRXDAT_MONNACK_Msk (0x01UL << I2C2_MONRXDAT_MONNACK_Pos) /*!< I2C2 MONRXDAT: MONNACK Mask */
-
-/* ---------------------------------- u2_i2c_ID --------------------------------- */
-#define I2C2_ID_APERTURE_Pos 0 /*!< I2C2 ID: APERTURE Position */
-#define I2C2_ID_APERTURE_Msk (0x000000ffUL << I2C2_ID_APERTURE_Pos) /*!< I2C2 ID: APERTURE Mask */
-#define I2C2_ID_MIN_REV_Pos 8 /*!< I2C2 ID: MIN_REV Position */
-#define I2C2_ID_MIN_REV_Msk (0x0fUL << I2C2_ID_MIN_REV_Pos) /*!< I2C2 ID: MIN_REV Mask */
-#define I2C2_ID_MAJ_REV_Pos 12 /*!< I2C2 ID: MAJ_REV Position */
-#define I2C2_ID_MAJ_REV_Msk (0x0fUL << I2C2_ID_MAJ_REV_Pos) /*!< I2C2 ID: MAJ_REV Mask */
-#define I2C2_ID_ID_Pos 16 /*!< I2C2 ID: ID Position */
-#define I2C2_ID_ID_Msk (0x0000ffffUL << I2C2_ID_ID_Pos) /*!< I2C2 ID: ID Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u_iso7816' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* -------------------------------- u_iso7816_SSR ------------------------------- */
-#define ISO7816_SSR_SOFTRESETN_Pos 0 /*!< ISO7816 SSR: SOFTRESETN Position */
-#define ISO7816_SSR_SOFTRESETN_Msk (0x01UL << ISO7816_SSR_SOFTRESETN_Pos) /*!< ISO7816 SSR: SOFTRESETN Mask */
-
-/* ----------------------------- u_iso7816_PDR1_LSB ----------------------------- */
-#define ISO7816_PDR1_LSB_PDR1_LSB_Pos 0 /*!< ISO7816 PDR1_LSB: PDR1_LSB Position */
-#define ISO7816_PDR1_LSB_PDR1_LSB_Msk (0xffffffffUL << ISO7816_PDR1_LSB_PDR1_LSB_Pos) /*!< ISO7816 PDR1_LSB: PDR1_LSB Mask */
-
-/* ----------------------------- u_iso7816_PDR1_MSB ----------------------------- */
-#define ISO7816_PDR1_MSB_PDR1_MSB_Pos 0 /*!< ISO7816 PDR1_MSB: PDR1_MSB Position */
-#define ISO7816_PDR1_MSB_PDR1_MSB_Msk (0xffffffffUL << ISO7816_PDR1_MSB_PDR1_MSB_Pos) /*!< ISO7816 PDR1_MSB: PDR1_MSB Mask */
-
-/* -------------------------------- u_iso7816_FCR ------------------------------- */
-#define ISO7816_FCR_FTC_Pos 0 /*!< ISO7816 FCR: FTC Position */
-#define ISO7816_FCR_FTC_Msk (0x1fUL << ISO7816_FCR_FTC_Pos) /*!< ISO7816 FCR: FTC Mask */
-#define ISO7816_FCR_PEC_Pos 5 /*!< ISO7816 FCR: PEC Position */
-#define ISO7816_FCR_PEC_Msk (0x07UL << ISO7816_FCR_PEC_Pos) /*!< ISO7816 FCR: PEC Mask */
-
-/* ------------------------------- u_iso7816_GTR1 ------------------------------- */
-#define ISO7816_GTR1_GTR1_Pos 0 /*!< ISO7816 GTR1: GTR1 Position */
-#define ISO7816_GTR1_GTR1_Msk (0xffffffffUL << ISO7816_GTR1_GTR1_Pos) /*!< ISO7816 GTR1: GTR1 Mask */
-
-/* ------------------------------- u_iso7816_UCR11 ------------------------------ */
-#define ISO7816_UCR11_CONV_Pos 0 /*!< ISO7816 UCR11: CONV Position */
-#define ISO7816_UCR11_CONV_Msk (0x01UL << ISO7816_UCR11_CONV_Pos) /*!< ISO7816 UCR11: CONV Mask */
-#define ISO7816_UCR11_LCT_Pos 1 /*!< ISO7816 UCR11: LCT Position */
-#define ISO7816_UCR11_LCT_Msk (0x01UL << ISO7816_UCR11_LCT_Pos) /*!< ISO7816 UCR11: LCT Mask */
-#define ISO7816_UCR11_T_R_Pos 2 /*!< ISO7816 UCR11: T_R Position */
-#define ISO7816_UCR11_T_R_Msk (0x01UL << ISO7816_UCR11_T_R_Pos) /*!< ISO7816 UCR11: T_R Mask */
-#define ISO7816_UCR11_PROT_Pos 3 /*!< ISO7816 UCR11: PROT Position */
-#define ISO7816_UCR11_PROT_Msk (0x01UL << ISO7816_UCR11_PROT_Pos) /*!< ISO7816 UCR11: PROT Mask */
-#define ISO7816_UCR11_FC_Pos 4 /*!< ISO7816 UCR11: FC Position */
-#define ISO7816_UCR11_FC_Msk (0x01UL << ISO7816_UCR11_FC_Pos) /*!< ISO7816 UCR11: FC Mask */
-#define ISO7816_UCR11_FIP_Pos 5 /*!< ISO7816 UCR11: FIP Position */
-#define ISO7816_UCR11_FIP_Msk (0x01UL << ISO7816_UCR11_FIP_Pos) /*!< ISO7816 UCR11: FIP Mask */
-
-/* ------------------------------- u_iso7816_UCR21 ------------------------------ */
-#define ISO7816_UCR21_AUTOCONVN_Pos 0 /*!< ISO7816 UCR21: AUTOCONVN Position */
-#define ISO7816_UCR21_AUTOCONVN_Msk (0x01UL << ISO7816_UCR21_AUTOCONVN_Pos) /*!< ISO7816 UCR21: AUTOCONVN Mask */
-#define ISO7816_UCR21_MANBGT_Pos 1 /*!< ISO7816 UCR21: MANBGT Position */
-#define ISO7816_UCR21_MANBGT_Msk (0x01UL << ISO7816_UCR21_MANBGT_Pos) /*!< ISO7816 UCR21: MANBGT Mask */
-#define ISO7816_UCR21_DISFT_Pos 2 /*!< ISO7816 UCR21: DISFT Position */
-#define ISO7816_UCR21_DISFT_Msk (0x01UL << ISO7816_UCR21_DISFT_Pos) /*!< ISO7816 UCR21: DISFT Mask */
-#define ISO7816_UCR21_DISPE_Pos 3 /*!< ISO7816 UCR21: DISPE Position */
-#define ISO7816_UCR21_DISPE_Msk (0x01UL << ISO7816_UCR21_DISPE_Pos) /*!< ISO7816 UCR21: DISPE Mask */
-#define ISO7816_UCR21_DISATRCOUNTER_Pos 4 /*!< ISO7816 UCR21: DISATRCOUNTER Position */
-#define ISO7816_UCR21_DISATRCOUNTER_Msk (0x01UL << ISO7816_UCR21_DISATRCOUNTER_Pos) /*!< ISO7816 UCR21: DISATRCOUNTER Mask */
-#define ISO7816_UCR21_FIFOFLUSH_Pos 6 /*!< ISO7816 UCR21: FIFOFLUSH Position */
-#define ISO7816_UCR21_FIFOFLUSH_Msk (0x01UL << ISO7816_UCR21_FIFOFLUSH_Pos) /*!< ISO7816 UCR21: FIFOFLUSH Mask */
-#define ISO7816_UCR21_WRDACC_Pos 7 /*!< ISO7816 UCR21: WRDACC Position */
-#define ISO7816_UCR21_WRDACC_Msk (0x01UL << ISO7816_UCR21_WRDACC_Pos) /*!< ISO7816 UCR21: WRDACC Mask */
-
-/* ------------------------------- u_iso7816_CCR1 ------------------------------- */
-#define ISO7816_CCR1_ACC_Pos 0 /*!< ISO7816 CCR1: ACC Position */
-#define ISO7816_CCR1_ACC_Msk (0x07UL << ISO7816_CCR1_ACC_Pos) /*!< ISO7816 CCR1: ACC Mask */
-#define ISO7816_CCR1_SAN_Pos 3 /*!< ISO7816 CCR1: SAN Position */
-#define ISO7816_CCR1_SAN_Msk (0x01UL << ISO7816_CCR1_SAN_Pos) /*!< ISO7816 CCR1: SAN Mask */
-#define ISO7816_CCR1_CST_Pos 4 /*!< ISO7816 CCR1: CST Position */
-#define ISO7816_CCR1_CST_Msk (0x01UL << ISO7816_CCR1_CST_Pos) /*!< ISO7816 CCR1: CST Mask */
-#define ISO7816_CCR1_SHL_Pos 5 /*!< ISO7816 CCR1: SHL Position */
-#define ISO7816_CCR1_SHL_Msk (0x01UL << ISO7816_CCR1_SHL_Pos) /*!< ISO7816 CCR1: SHL Mask */
-
-/* -------------------------------- u_iso7816_PCR ------------------------------- */
-#define ISO7816_PCR_PCR_Pos 0 /*!< ISO7816 PCR: PCR Position */
-#define ISO7816_PCR_PCR_Msk (0xffffffffUL << ISO7816_PCR_PCR_Pos) /*!< ISO7816 PCR: PCR Mask */
-
-/* -------------------------------- u_iso7816_ECR ------------------------------- */
-#define ISO7816_ECR_ECR_Pos 0 /*!< ISO7816 ECR: ECR Position */
-#define ISO7816_ECR_ECR_Msk (0xffffffffUL << ISO7816_ECR_ECR_Pos) /*!< ISO7816 ECR: ECR Mask */
-
-/* ----------------------------- u_iso7816_MCRL_LSB ----------------------------- */
-#define ISO7816_MCRL_LSB_MCRL_LSB_Pos 0 /*!< ISO7816 MCRL_LSB: MCRL_LSB Position */
-#define ISO7816_MCRL_LSB_MCRL_LSB_Msk (0xffffffffUL << ISO7816_MCRL_LSB_MCRL_LSB_Pos) /*!< ISO7816 MCRL_LSB: MCRL_LSB Mask */
-
-/* ----------------------------- u_iso7816_MCRL_MSB ----------------------------- */
-#define ISO7816_MCRL_MSB_MCRL_MSB_Pos 0 /*!< ISO7816 MCRL_MSB: MCRL_MSB Position */
-#define ISO7816_MCRL_MSB_MCRL_MSB_Msk (0xffffffffUL << ISO7816_MCRL_MSB_MCRL_MSB_Pos) /*!< ISO7816 MCRL_MSB: MCRL_MSB Mask */
-
-/* ----------------------------- u_iso7816_MCRH_LSB ----------------------------- */
-#define ISO7816_MCRH_LSB_MCRH_LSB_Pos 0 /*!< ISO7816 MCRH_LSB: MCRH_LSB Position */
-#define ISO7816_MCRH_LSB_MCRH_LSB_Msk (0xffffffffUL << ISO7816_MCRH_LSB_MCRH_LSB_Pos) /*!< ISO7816 MCRH_LSB: MCRH_LSB Mask */
-
-/* ----------------------------- u_iso7816_MCRH_MSB ----------------------------- */
-#define ISO7816_MCRH_MSB_MCRH_MSB_Pos 0 /*!< ISO7816 MCRH_MSB: MCRH_MSB Position */
-#define ISO7816_MCRH_MSB_MCRH_MSB_Msk (0xffffffffUL << ISO7816_MCRH_MSB_MCRH_MSB_Pos) /*!< ISO7816 MCRH_MSB: MCRH_MSB Mask */
-
-/* -------------------------------- u_iso7816_SRR ------------------------------- */
-#define ISO7816_SRR_SRR_Pos 0 /*!< ISO7816 SRR: SRR Position */
-#define ISO7816_SRR_SRR_Msk (0xffffffffUL << ISO7816_SRR_SRR_Pos) /*!< ISO7816 SRR: SRR Mask */
-
-/* ------------------------------ u_iso7816_URR_UTR ----------------------------- */
-#define ISO7816_URR_UTR_URR_UTR_Pos 0 /*!< ISO7816 URR_UTR: URR_UTR Position */
-#define ISO7816_URR_UTR_URR_UTR_Msk (0xffffffffUL << ISO7816_URR_UTR_URR_UTR_Pos) /*!< ISO7816 URR_UTR: URR_UTR Mask */
-
-/* ------------------------------- u_iso7816_TOR1 ------------------------------- */
-#define ISO7816_TOR1_TOR1_Pos 0 /*!< ISO7816 TOR1: TOR1 Position */
-#define ISO7816_TOR1_TOR1_Msk (0xffffffffUL << ISO7816_TOR1_TOR1_Pos) /*!< ISO7816 TOR1: TOR1 Mask */
-
-/* ------------------------------- u_iso7816_TOR2 ------------------------------- */
-#define ISO7816_TOR2_TOR2_Pos 0 /*!< ISO7816 TOR2: TOR2 Position */
-#define ISO7816_TOR2_TOR2_Msk (0xffffffffUL << ISO7816_TOR2_TOR2_Pos) /*!< ISO7816 TOR2: TOR2 Mask */
-
-/* ------------------------------- u_iso7816_TOR3 ------------------------------- */
-#define ISO7816_TOR3_TOR3_Pos 0 /*!< ISO7816 TOR3: TOR3 Position */
-#define ISO7816_TOR3_TOR3_Msk (0xffffffffUL << ISO7816_TOR3_TOR3_Pos) /*!< ISO7816 TOR3: TOR3 Mask */
-
-/* -------------------------------- u_iso7816_TOC ------------------------------- */
-#define ISO7816_TOC_TOC_Pos 0 /*!< ISO7816 TOC: TOC Position */
-#define ISO7816_TOC_TOC_Msk (0xffffffffUL << ISO7816_TOC_TOC_Pos) /*!< ISO7816 TOC: TOC Mask */
-
-/* -------------------------------- u_iso7816_FSR ------------------------------- */
-#define ISO7816_FSR_FSR_Pos 0 /*!< ISO7816 FSR: FSR Position */
-#define ISO7816_FSR_FSR_Msk (0xffffffffUL << ISO7816_FSR_FSR_Pos) /*!< ISO7816 FSR: FSR Mask */
-
-/* -------------------------------- u_iso7816_MSR ------------------------------- */
-#define ISO7816_MSR_MSR_Pos 0 /*!< ISO7816 MSR: MSR Position */
-#define ISO7816_MSR_MSR_Msk (0xffffffffUL << ISO7816_MSR_MSR_Pos) /*!< ISO7816 MSR: MSR Mask */
-
-/* ------------------------------- u_iso7816_USR1 ------------------------------- */
-#define ISO7816_USR1_USR1_Pos 0 /*!< ISO7816 USR1: USR1 Position */
-#define ISO7816_USR1_USR1_Msk (0xffffffffUL << ISO7816_USR1_USR1_Pos) /*!< ISO7816 USR1: USR1 Mask */
-
-/* ------------------------------- u_iso7816_USR2 ------------------------------- */
-#define ISO7816_USR2_USR2_Pos 0 /*!< ISO7816 USR2: USR2 Position */
-#define ISO7816_USR2_USR2_Msk (0xffffffffUL << ISO7816_USR2_USR2_Pos) /*!< ISO7816 USR2: USR2 Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u_cic_irb' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* ------------------------------- u_cic_irb_CONF ------------------------------- */
-#define IRB_CONF_ENV_INI_Pos 0 /*!< IRB CONF: ENV_INI Position */
-#define IRB_CONF_ENV_INI_Msk (0x01UL << IRB_CONF_ENV_INI_Pos) /*!< IRB CONF: ENV_INI Mask */
-#define IRB_CONF_MODE_Pos 1 /*!< IRB CONF: MODE Position */
-#define IRB_CONF_MODE_Msk (0x01UL << IRB_CONF_MODE_Pos) /*!< IRB CONF: MODE Mask */
-#define IRB_CONF_OUT_Pos 2 /*!< IRB CONF: OUT Position */
-#define IRB_CONF_OUT_Msk (0x03UL << IRB_CONF_OUT_Pos) /*!< IRB CONF: OUT Mask */
-#define IRB_CONF_NO_CAR_Pos 4 /*!< IRB CONF: NO_CAR Position */
-#define IRB_CONF_NO_CAR_Msk (0x01UL << IRB_CONF_NO_CAR_Pos) /*!< IRB CONF: NO_CAR Mask */
-#define IRB_CONF_CAR_INI_Pos 5 /*!< IRB CONF: CAR_INI Position */
-#define IRB_CONF_CAR_INI_Msk (0x01UL << IRB_CONF_CAR_INI_Pos) /*!< IRB CONF: CAR_INI Mask */
-
-/* ------------------------------ u_cic_irb_CARRIER ----------------------------- */
-#define IRB_CARRIER_CTU_Pos 0 /*!< IRB CARRIER: CTU Position */
-#define IRB_CARRIER_CTU_Msk (0x0000ffffUL << IRB_CARRIER_CTU_Pos) /*!< IRB CARRIER: CTU Mask */
-#define IRB_CARRIER_CLOW_Pos 16 /*!< IRB CARRIER: CLOW Position */
-#define IRB_CARRIER_CLOW_Msk (0x07UL << IRB_CARRIER_CLOW_Pos) /*!< IRB CARRIER: CLOW Mask */
-#define IRB_CARRIER_CHIGH_Pos 19 /*!< IRB CARRIER: CHIGH Position */
-#define IRB_CARRIER_CHIGH_Msk (0x03UL << IRB_CARRIER_CHIGH_Pos) /*!< IRB CARRIER: CHIGH Mask */
-
-/* ------------------------------ u_cic_irb_FIFO_IN ----------------------------- */
-#define IRB_FIFO_IN_ENV_Pos 0 /*!< IRB FIFO_IN: ENV Position */
-#define IRB_FIFO_IN_ENV_Msk (0x00000fffUL << IRB_FIFO_IN_ENV_Pos) /*!< IRB FIFO_IN: ENV Mask */
-#define IRB_FIFO_IN_ENV_INT_Pos 12 /*!< IRB FIFO_IN: ENV_INT Position */
-#define IRB_FIFO_IN_ENV_INT_Msk (0x01UL << IRB_FIFO_IN_ENV_INT_Pos) /*!< IRB FIFO_IN: ENV_INT Mask */
-#define IRB_FIFO_IN_ENV_LAST_Pos 13 /*!< IRB FIFO_IN: ENV_LAST Position */
-#define IRB_FIFO_IN_ENV_LAST_Msk (0x01UL << IRB_FIFO_IN_ENV_LAST_Pos) /*!< IRB FIFO_IN: ENV_LAST Mask */
-
-/* ------------------------------ u_cic_irb_STATUS ------------------------------ */
-#define IRB_STATUS_FIFO_LVL_Pos 0 /*!< IRB STATUS: FIFO_LVL Position */
-#define IRB_STATUS_FIFO_LVL_Msk (0x1fUL << IRB_STATUS_FIFO_LVL_Pos) /*!< IRB STATUS: FIFO_LVL Mask */
-#define IRB_STATUS_FIFO_FULL_Pos 5 /*!< IRB STATUS: FIFO_FULL Position */
-#define IRB_STATUS_FIFO_FULL_Msk (0x01UL << IRB_STATUS_FIFO_FULL_Pos) /*!< IRB STATUS: FIFO_FULL Mask */
-#define IRB_STATUS_FIFO_EMPTY_Pos 6 /*!< IRB STATUS: FIFO_EMPTY Position */
-#define IRB_STATUS_FIFO_EMPTY_Msk (0x01UL << IRB_STATUS_FIFO_EMPTY_Pos) /*!< IRB STATUS: FIFO_EMPTY Mask */
-#define IRB_STATUS_ENA_ST_Pos 7 /*!< IRB STATUS: ENA_ST Position */
-#define IRB_STATUS_ENA_ST_Msk (0x01UL << IRB_STATUS_ENA_ST_Pos) /*!< IRB STATUS: ENA_ST Mask */
-#define IRB_STATUS_RUN_ST_Pos 8 /*!< IRB STATUS: RUN_ST Position */
-#define IRB_STATUS_RUN_ST_Msk (0x01UL << IRB_STATUS_RUN_ST_Pos) /*!< IRB STATUS: RUN_ST Mask */
-
-/* -------------------------------- u_cic_irb_CMD ------------------------------- */
-#define IRB_CMD_ENA_Pos 0 /*!< IRB CMD: ENA Position */
-#define IRB_CMD_ENA_Msk (0x01UL << IRB_CMD_ENA_Pos) /*!< IRB CMD: ENA Mask */
-#define IRB_CMD_DIS_Pos 1 /*!< IRB CMD: DIS Position */
-#define IRB_CMD_DIS_Msk (0x01UL << IRB_CMD_DIS_Pos) /*!< IRB CMD: DIS Mask */
-#define IRB_CMD_START_Pos 2 /*!< IRB CMD: START Position */
-#define IRB_CMD_START_Msk (0x01UL << IRB_CMD_START_Pos) /*!< IRB CMD: START Mask */
-#define IRB_CMD_FIFO_RST_Pos 3 /*!< IRB CMD: FIFO_RST Position */
-#define IRB_CMD_FIFO_RST_Msk (0x01UL << IRB_CMD_FIFO_RST_Pos) /*!< IRB CMD: FIFO_RST Mask */
-
-/* ---------------------------- u_cic_irb_INT_STATUS ---------------------------- */
-#define IRB_INT_STATUS_ENV_START_INT_Pos 0 /*!< IRB INT_STATUS: ENV_START_INT Position */
-#define IRB_INT_STATUS_ENV_START_INT_Msk (0x01UL << IRB_INT_STATUS_ENV_START_INT_Pos) /*!< IRB INT_STATUS: ENV_START_INT Mask */
-#define IRB_INT_STATUS_ENV_LAST_INT_Pos 1 /*!< IRB INT_STATUS: ENV_LAST_INT Position */
-#define IRB_INT_STATUS_ENV_LAST_INT_Msk (0x01UL << IRB_INT_STATUS_ENV_LAST_INT_Pos) /*!< IRB INT_STATUS: ENV_LAST_INT Mask */
-#define IRB_INT_STATUS_FIFO_UFL_INT_Pos 2 /*!< IRB INT_STATUS: FIFO_UFL_INT Position */
-#define IRB_INT_STATUS_FIFO_UFL_INT_Msk (0x01UL << IRB_INT_STATUS_FIFO_UFL_INT_Pos) /*!< IRB INT_STATUS: FIFO_UFL_INT Mask */
-
-/* ------------------------------ u_cic_irb_INT_ENA ----------------------------- */
-#define IRB_INT_ENA_ENV_START_ENA_Pos 0 /*!< IRB INT_ENA: ENV_START_ENA Position */
-#define IRB_INT_ENA_ENV_START_ENA_Msk (0x01UL << IRB_INT_ENA_ENV_START_ENA_Pos) /*!< IRB INT_ENA: ENV_START_ENA Mask */
-#define IRB_INT_ENA_ENV_LAST_ENA_Pos 1 /*!< IRB INT_ENA: ENV_LAST_ENA Position */
-#define IRB_INT_ENA_ENV_LAST_ENA_Msk (0x01UL << IRB_INT_ENA_ENV_LAST_ENA_Pos) /*!< IRB INT_ENA: ENV_LAST_ENA Mask */
-#define IRB_INT_ENA_FIFO_UFL_ENA_Pos 2 /*!< IRB INT_ENA: FIFO_UFL_ENA Position */
-#define IRB_INT_ENA_FIFO_UFL_ENA_Msk (0x01UL << IRB_INT_ENA_FIFO_UFL_ENA_Pos) /*!< IRB INT_ENA: FIFO_UFL_ENA Mask */
-
-/* ------------------------------ u_cic_irb_INT_CLR ----------------------------- */
-#define IRB_INT_CLR_ENV_START_CLR_Pos 0 /*!< IRB INT_CLR: ENV_START_CLR Position */
-#define IRB_INT_CLR_ENV_START_CLR_Msk (0x01UL << IRB_INT_CLR_ENV_START_CLR_Pos) /*!< IRB INT_CLR: ENV_START_CLR Mask */
-#define IRB_INT_CLR_ENV_LAST_CLR_Pos 1 /*!< IRB INT_CLR: ENV_LAST_CLR Position */
-#define IRB_INT_CLR_ENV_LAST_CLR_Msk (0x01UL << IRB_INT_CLR_ENV_LAST_CLR_Pos) /*!< IRB INT_CLR: ENV_LAST_CLR Mask */
-#define IRB_INT_CLR_FIFO_UFL_CLR_Pos 2 /*!< IRB INT_CLR: FIFO_UFL_CLR Position */
-#define IRB_INT_CLR_FIFO_UFL_CLR_Msk (0x01UL << IRB_INT_CLR_FIFO_UFL_CLR_Pos) /*!< IRB INT_CLR: FIFO_UFL_CLR Mask */
-
-/* ------------------------------ u_cic_irb_INT_SET ----------------------------- */
-#define IRB_INT_SET_ENV_START_SET_Pos 0 /*!< IRB INT_SET: ENV_START_SET Position */
-#define IRB_INT_SET_ENV_START_SET_Msk (0x01UL << IRB_INT_SET_ENV_START_SET_Pos) /*!< IRB INT_SET: ENV_START_SET Mask */
-#define IRB_INT_SET_ENV_LAST_SET_Pos 1 /*!< IRB INT_SET: ENV_LAST_SET Position */
-#define IRB_INT_SET_ENV_LAST_SET_Msk (0x01UL << IRB_INT_SET_ENV_LAST_SET_Pos) /*!< IRB INT_SET: ENV_LAST_SET Mask */
-#define IRB_INT_SET_FIFO_UFL_SET_Pos 2 /*!< IRB INT_SET: FIFO_UFL_SET Position */
-#define IRB_INT_SET_FIFO_UFL_SET_Msk (0x01UL << IRB_INT_SET_FIFO_UFL_SET_Pos) /*!< IRB INT_SET: FIFO_UFL_SET Mask */
-
-/* ----------------------------- u_cic_irb_MODULE_ID ---------------------------- */
-#define IRB_MODULE_ID_APERTURE_Pos 0 /*!< IRB MODULE_ID: APERTURE Position */
-#define IRB_MODULE_ID_APERTURE_Msk (0x000000ffUL << IRB_MODULE_ID_APERTURE_Pos) /*!< IRB MODULE_ID: APERTURE Mask */
-#define IRB_MODULE_ID_MIN_REV_Pos 8 /*!< IRB MODULE_ID: MIN_REV Position */
-#define IRB_MODULE_ID_MIN_REV_Msk (0x0fUL << IRB_MODULE_ID_MIN_REV_Pos) /*!< IRB MODULE_ID: MIN_REV Mask */
-#define IRB_MODULE_ID_MAJ_REV_Pos 12 /*!< IRB MODULE_ID: MAJ_REV Position */
-#define IRB_MODULE_ID_MAJ_REV_Msk (0x0fUL << IRB_MODULE_ID_MAJ_REV_Pos) /*!< IRB MODULE_ID: MAJ_REV Mask */
-#define IRB_MODULE_ID_ID_Pos 16 /*!< IRB MODULE_ID: ID Position */
-#define IRB_MODULE_ID_ID_Msk (0x0000ffffUL << IRB_MODULE_ID_ID_Pos) /*!< IRB MODULE_ID: ID Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u_codepatch' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* ------------------------ u_codepatch_PATCH_CONTROL_REG ----------------------- */
-#define CODEPATCH_PATCH_CONTROL_REG_PATCH_EN_Pos 0 /*!< CODEPATCH PATCH_CONTROL_REG: PATCH_EN Position */
-#define CODEPATCH_PATCH_CONTROL_REG_PATCH_EN_Msk (0x01UL << CODEPATCH_PATCH_CONTROL_REG_PATCH_EN_Pos)/*!< CODEPATCH PATCH_CONTROL_REG: PATCH_EN Mask */
-
-/* -------------------------- u_codepatch_CONTROL_1_REG ------------------------- */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_1_Pos 0 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_1 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_1_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_1_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_1 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_2_Pos 1 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_2 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_2_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_2_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_2 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_3_Pos 2 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_3 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_3_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_3_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_3 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_4_Pos 3 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_4 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_4_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_4_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_4 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_5_Pos 4 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_5 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_5_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_5_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_5 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_6_Pos 5 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_6 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_6_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_6_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_6 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_7_Pos 6 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_7 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_7_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_7_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_7 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_8_Pos 7 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_8 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_8_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_8_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_8 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_9_Pos 8 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_9 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_9_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_9_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_9 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_10_Pos 9 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_10 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_10_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_10_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_10 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_11_Pos 10 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_11 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_11_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_11_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_11 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_12_Pos 11 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_12 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_12_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_12_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_12 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_13_Pos 12 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_13 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_13_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_13_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_13 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_14_Pos 13 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_14 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_14_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_14_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_14 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_15_Pos 14 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_15 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_15_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_15_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_15 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_16_Pos 15 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_16 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_16_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_16_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_16 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_17_Pos 16 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_17 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_17_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_17_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_17 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_18_Pos 17 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_18 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_18_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_18_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_18 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_19_Pos 18 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_19 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_19_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_19_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_19 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_20_Pos 19 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_20 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_20_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_20_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_20 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_21_Pos 20 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_21 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_21_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_21_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_21 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_22_Pos 21 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_22 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_22_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_22_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_22 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_23_Pos 22 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_23 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_23_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_23_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_23 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_24_Pos 23 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_24 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_24_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_24_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_24 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_25_Pos 24 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_25 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_25_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_25_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_25 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_26_Pos 25 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_26 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_26_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_26_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_26 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_27_Pos 26 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_27 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_27_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_27_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_27 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_28_Pos 27 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_28 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_28_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_28_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_28 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_29_Pos 28 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_29 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_29_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_29_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_29 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_30_Pos 29 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_30 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_30_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_30_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_30 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_31_Pos 30 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_31 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_31_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_31_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_31 Mask */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_32_Pos 31 /*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_32 Position */
-#define CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_32_Msk (0x01UL << CODEPATCH_CONTROL_1_REG_ENABLE_PATCH_32_Pos)/*!< CODEPATCH CONTROL_1_REG: ENABLE_PATCH_32 Mask */
-
-/* -------------------------- u_codepatch_CONTROL_2_REG ------------------------- */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_33_Pos 0 /*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_33 Position */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_33_Msk (0x01UL << CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_33_Pos)/*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_33 Mask */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_34_Pos 1 /*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_34 Position */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_34_Msk (0x01UL << CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_34_Pos)/*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_34 Mask */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_35_Pos 2 /*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_35 Position */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_35_Msk (0x01UL << CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_35_Pos)/*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_35 Mask */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_36_Pos 3 /*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_36 Position */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_36_Msk (0x01UL << CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_36_Pos)/*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_36 Mask */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_37_Pos 4 /*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_37 Position */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_37_Msk (0x01UL << CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_37_Pos)/*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_37 Mask */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_38_Pos 5 /*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_38 Position */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_38_Msk (0x01UL << CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_38_Pos)/*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_38 Mask */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_39_Pos 6 /*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_39 Position */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_39_Msk (0x01UL << CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_39_Pos)/*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_39 Mask */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_40_Pos 7 /*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_40 Position */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_40_Msk (0x01UL << CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_40_Pos)/*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_40 Mask */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_41_Pos 8 /*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_41 Position */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_41_Msk (0x01UL << CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_41_Pos)/*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_41 Mask */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_42_Pos 9 /*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_42 Position */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_42_Msk (0x01UL << CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_42_Pos)/*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_42 Mask */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_43_Pos 10 /*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_43 Position */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_43_Msk (0x01UL << CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_43_Pos)/*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_43 Mask */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_44_Pos 11 /*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_44 Position */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_44_Msk (0x01UL << CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_44_Pos)/*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_44 Mask */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_45_Pos 12 /*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_45 Position */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_45_Msk (0x01UL << CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_45_Pos)/*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_45 Mask */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_46_Pos 13 /*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_46 Position */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_46_Msk (0x01UL << CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_46_Pos)/*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_46 Mask */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_47_Pos 14 /*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_47 Position */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_47_Msk (0x01UL << CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_47_Pos)/*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_47 Mask */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_48_Pos 15 /*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_48 Position */
-#define CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_48_Msk (0x01UL << CODEPATCH_CONTROL_2_REG_ENABLE_PATCH_48_Pos)/*!< CODEPATCH CONTROL_2_REG: ENABLE_PATCH_48 Mask */
-
-/* ------------------------- u_codepatch_TRAP_STATUS_REG ------------------------ */
-#define CODEPATCH_TRAP_STATUS_REG_LAST_TRAP_0_Pos 0 /*!< CODEPATCH TRAP_STATUS_REG: LAST_TRAP_0 Position */
-#define CODEPATCH_TRAP_STATUS_REG_LAST_TRAP_0_Msk (0x7fUL << CODEPATCH_TRAP_STATUS_REG_LAST_TRAP_0_Pos)/*!< CODEPATCH TRAP_STATUS_REG: LAST_TRAP_0 Mask */
-#define CODEPATCH_TRAP_STATUS_REG_LAST_TRAP_1_Pos 8 /*!< CODEPATCH TRAP_STATUS_REG: LAST_TRAP_1 Position */
-#define CODEPATCH_TRAP_STATUS_REG_LAST_TRAP_1_Msk (0x7fUL << CODEPATCH_TRAP_STATUS_REG_LAST_TRAP_1_Pos)/*!< CODEPATCH TRAP_STATUS_REG: LAST_TRAP_1 Mask */
-
-/* -------------------------- u_codepatch_VT_REMAP_REG -------------------------- */
-#define CODEPATCH_VT_REMAP_REG_VT_REMAP_EN_Pos 0 /*!< CODEPATCH VT_REMAP_REG: VT_REMAP_EN Position */
-#define CODEPATCH_VT_REMAP_REG_VT_REMAP_EN_Msk (0x01UL << CODEPATCH_VT_REMAP_REG_VT_REMAP_EN_Pos) /*!< CODEPATCH VT_REMAP_REG: VT_REMAP_EN Mask */
-
-/* ------------------------- u_codepatch_TESTBUS_SEL_REG ------------------------ */
-#define CODEPATCH_TESTBUS_SEL_REG_TESTBUS_SEL_REG_Pos 0 /*!< CODEPATCH TESTBUS_SEL_REG: TESTBUS_SEL_REG Position */
-#define CODEPATCH_TESTBUS_SEL_REG_TESTBUS_SEL_REG_Msk (0xffffffffUL << CODEPATCH_TESTBUS_SEL_REG_TESTBUS_SEL_REG_Pos)/*!< CODEPATCH TESTBUS_SEL_REG: TESTBUS_SEL_REG Mask */
-
-/* --------------------------- u_codepatch_OFFSET_REG --------------------------- */
-#define CODEPATCH_OFFSET_REG_OFFSET_ADDR_Pos 0 /*!< CODEPATCH OFFSET_REG: OFFSET_ADDR Position */
-#define CODEPATCH_OFFSET_REG_OFFSET_ADDR_Msk (0x0003ffffUL << CODEPATCH_OFFSET_REG_OFFSET_ADDR_Pos)/*!< CODEPATCH OFFSET_REG: OFFSET_ADDR Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u_flash' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* --------------------------------- u_flash_CMD -------------------------------- */
-#define FLASH_CMD_CMD_Pos 0 /*!< FLASH CMD: CMD Position */
-#define FLASH_CMD_CMD_Msk (0xffffffffUL << FLASH_CMD_CMD_Pos) /*!< FLASH CMD: CMD Mask */
-
-/* -------------------------------- u_flash_EVENT ------------------------------- */
-#define FLASH_EVENT_RST_Pos 0 /*!< FLASH EVENT: RST Position */
-#define FLASH_EVENT_RST_Msk (0x01UL << FLASH_EVENT_RST_Pos) /*!< FLASH EVENT: RST Mask */
-#define FLASH_EVENT_WAKEUP_Pos 1 /*!< FLASH EVENT: WAKEUP Position */
-#define FLASH_EVENT_WAKEUP_Msk (0x01UL << FLASH_EVENT_WAKEUP_Pos) /*!< FLASH EVENT: WAKEUP Mask */
-#define FLASH_EVENT_ABORT_Pos 2 /*!< FLASH EVENT: ABORT Position */
-#define FLASH_EVENT_ABORT_Msk (0x01UL << FLASH_EVENT_ABORT_Pos) /*!< FLASH EVENT: ABORT Mask */
-
-/* ------------------------------ u_flash_AUTOPROG ------------------------------ */
-#define FLASH_AUTOPROG_AUTOPROG_Pos 0 /*!< FLASH AUTOPROG: AUTOPROG Position */
-#define FLASH_AUTOPROG_AUTOPROG_Msk (0x03UL << FLASH_AUTOPROG_AUTOPROG_Pos) /*!< FLASH AUTOPROG: AUTOPROG Mask */
-
-/* ------------------------------- u_flash_STARTA ------------------------------- */
-#define FLASH_STARTA_STARTA_Pos 0 /*!< FLASH STARTA: STARTA Position */
-#define FLASH_STARTA_STARTA_Msk (0x0003ffffUL << FLASH_STARTA_STARTA_Pos) /*!< FLASH STARTA: STARTA Mask */
-
-/* -------------------------------- u_flash_STOPA ------------------------------- */
-#define FLASH_STOPA_STOPA_Pos 0 /*!< FLASH STOPA: STOPA Position */
-#define FLASH_STOPA_STOPA_Msk (0x0003ffffUL << FLASH_STOPA_STOPA_Pos) /*!< FLASH STOPA: STOPA Mask */
-
-/* -------------------------------- u_flash_TEST -------------------------------- */
-#define FLASH_TEST_DCM1_Pos 0 /*!< FLASH TEST: DCM1 Position */
-#define FLASH_TEST_DCM1_Msk (0x000000ffUL << FLASH_TEST_DCM1_Pos) /*!< FLASH TEST: DCM1 Mask */
-#define FLASH_TEST_DCM2_Pos 8 /*!< FLASH TEST: DCM2 Position */
-#define FLASH_TEST_DCM2_Msk (0x000000ffUL << FLASH_TEST_DCM2_Pos) /*!< FLASH TEST: DCM2 Mask */
-#define FLASH_TEST_EXT48_Pos 16 /*!< FLASH TEST: EXT48 Position */
-#define FLASH_TEST_EXT48_Msk (0x01UL << FLASH_TEST_EXT48_Pos) /*!< FLASH TEST: EXT48 Mask */
-
-/* -------------------------------- u_flash_PARW -------------------------------- */
-#define FLASH_PARW_PARW_Pos 0 /*!< FLASH PARW: PARW Position */
-#define FLASH_PARW_PARW_Msk (0xffffffffUL << FLASH_PARW_PARW_Pos) /*!< FLASH PARW: PARW Mask */
-
-/* --------------------------------- u_flash_FSQ -------------------------------- */
-#define FLASH_FSQ_ST1_Pos 0 /*!< FLASH FSQ: ST1 Position */
-#define FLASH_FSQ_ST1_Msk (0x000000ffUL << FLASH_FSQ_ST1_Pos) /*!< FLASH FSQ: ST1 Mask */
-#define FLASH_FSQ_EN1_Pos 8 /*!< FLASH FSQ: EN1 Position */
-#define FLASH_FSQ_EN1_Msk (0x000000ffUL << FLASH_FSQ_EN1_Pos) /*!< FLASH FSQ: EN1 Mask */
-#define FLASH_FSQ_ST2_Pos 16 /*!< FLASH FSQ: ST2 Position */
-#define FLASH_FSQ_ST2_Msk (0x000000ffUL << FLASH_FSQ_ST2_Pos) /*!< FLASH FSQ: ST2 Mask */
-#define FLASH_FSQ_EN2_Pos 24 /*!< FLASH FSQ: EN2 Position */
-#define FLASH_FSQ_EN2_Msk (0x000000ffUL << FLASH_FSQ_EN2_Pos) /*!< FLASH FSQ: EN2 Mask */
-
-/* -------------------------------- u_flash_DATAW ------------------------------- */
-#define FLASH_DATAW_DATAW_Pos 0 /*!< FLASH DATAW: DATAW Position */
-#define FLASH_DATAW_DATAW_Msk (0xffffffffUL << FLASH_DATAW_DATAW_Pos) /*!< FLASH DATAW: DATAW Mask */
-
-/* --------------------------- u_flash_INT_CLR_ENABLE --------------------------- */
-#define FLASH_INT_CLR_ENABLE_FAIL_Pos 0 /*!< FLASH INT_CLR_ENABLE: FAIL Position */
-#define FLASH_INT_CLR_ENABLE_FAIL_Msk (0x01UL << FLASH_INT_CLR_ENABLE_FAIL_Pos) /*!< FLASH INT_CLR_ENABLE: FAIL Mask */
-#define FLASH_INT_CLR_ENABLE_ERR_Pos 1 /*!< FLASH INT_CLR_ENABLE: ERR Position */
-#define FLASH_INT_CLR_ENABLE_ERR_Msk (0x01UL << FLASH_INT_CLR_ENABLE_ERR_Pos) /*!< FLASH INT_CLR_ENABLE: ERR Mask */
-#define FLASH_INT_CLR_ENABLE_DONE_Pos 2 /*!< FLASH INT_CLR_ENABLE: DONE Position */
-#define FLASH_INT_CLR_ENABLE_DONE_Msk (0x01UL << FLASH_INT_CLR_ENABLE_DONE_Pos) /*!< FLASH INT_CLR_ENABLE: DONE Mask */
-#define FLASH_INT_CLR_ENABLE_ECC_ERR_Pos 3 /*!< FLASH INT_CLR_ENABLE: ECC_ERR Position */
-#define FLASH_INT_CLR_ENABLE_ECC_ERR_Msk (0x01UL << FLASH_INT_CLR_ENABLE_ECC_ERR_Pos) /*!< FLASH INT_CLR_ENABLE: ECC_ERR Mask */
-
-/* --------------------------- u_flash_INT_SET_ENABLE --------------------------- */
-#define FLASH_INT_SET_ENABLE_FAIL_Pos 0 /*!< FLASH INT_SET_ENABLE: FAIL Position */
-#define FLASH_INT_SET_ENABLE_FAIL_Msk (0x01UL << FLASH_INT_SET_ENABLE_FAIL_Pos) /*!< FLASH INT_SET_ENABLE: FAIL Mask */
-#define FLASH_INT_SET_ENABLE_ERR_Pos 1 /*!< FLASH INT_SET_ENABLE: ERR Position */
-#define FLASH_INT_SET_ENABLE_ERR_Msk (0x01UL << FLASH_INT_SET_ENABLE_ERR_Pos) /*!< FLASH INT_SET_ENABLE: ERR Mask */
-#define FLASH_INT_SET_ENABLE_DONE_Pos 2 /*!< FLASH INT_SET_ENABLE: DONE Position */
-#define FLASH_INT_SET_ENABLE_DONE_Msk (0x01UL << FLASH_INT_SET_ENABLE_DONE_Pos) /*!< FLASH INT_SET_ENABLE: DONE Mask */
-#define FLASH_INT_SET_ENABLE_ECC_ERR_Pos 3 /*!< FLASH INT_SET_ENABLE: ECC_ERR Position */
-#define FLASH_INT_SET_ENABLE_ECC_ERR_Msk (0x01UL << FLASH_INT_SET_ENABLE_ECC_ERR_Pos) /*!< FLASH INT_SET_ENABLE: ECC_ERR Mask */
-
-/* ----------------------------- u_flash_INT_STATUS ----------------------------- */
-#define FLASH_INT_STATUS_FAIL_Pos 0 /*!< FLASH INT_STATUS: FAIL Position */
-#define FLASH_INT_STATUS_FAIL_Msk (0x01UL << FLASH_INT_STATUS_FAIL_Pos) /*!< FLASH INT_STATUS: FAIL Mask */
-#define FLASH_INT_STATUS_ERR_Pos 1 /*!< FLASH INT_STATUS: ERR Position */
-#define FLASH_INT_STATUS_ERR_Msk (0x01UL << FLASH_INT_STATUS_ERR_Pos) /*!< FLASH INT_STATUS: ERR Mask */
-#define FLASH_INT_STATUS_DONE_Pos 2 /*!< FLASH INT_STATUS: DONE Position */
-#define FLASH_INT_STATUS_DONE_Msk (0x01UL << FLASH_INT_STATUS_DONE_Pos) /*!< FLASH INT_STATUS: DONE Mask */
-#define FLASH_INT_STATUS_ECC_ERR_Pos 3 /*!< FLASH INT_STATUS: ECC_ERR Position */
-#define FLASH_INT_STATUS_ECC_ERR_Msk (0x01UL << FLASH_INT_STATUS_ECC_ERR_Pos) /*!< FLASH INT_STATUS: ECC_ERR Mask */
-
-/* ----------------------------- u_flash_INT_ENABLE ----------------------------- */
-#define FLASH_INT_ENABLE_FAIL_Pos 0 /*!< FLASH INT_ENABLE: FAIL Position */
-#define FLASH_INT_ENABLE_FAIL_Msk (0x01UL << FLASH_INT_ENABLE_FAIL_Pos) /*!< FLASH INT_ENABLE: FAIL Mask */
-#define FLASH_INT_ENABLE_ERR_Pos 1 /*!< FLASH INT_ENABLE: ERR Position */
-#define FLASH_INT_ENABLE_ERR_Msk (0x01UL << FLASH_INT_ENABLE_ERR_Pos) /*!< FLASH INT_ENABLE: ERR Mask */
-#define FLASH_INT_ENABLE_DONE_Pos 2 /*!< FLASH INT_ENABLE: DONE Position */
-#define FLASH_INT_ENABLE_DONE_Msk (0x01UL << FLASH_INT_ENABLE_DONE_Pos) /*!< FLASH INT_ENABLE: DONE Mask */
-#define FLASH_INT_ENABLE_ECC_ERR_Pos 3 /*!< FLASH INT_ENABLE: ECC_ERR Position */
-#define FLASH_INT_ENABLE_ECC_ERR_Msk (0x01UL << FLASH_INT_ENABLE_ECC_ERR_Pos) /*!< FLASH INT_ENABLE: ECC_ERR Mask */
-
-/* --------------------------- u_flash_INT_CLR_STATUS --------------------------- */
-#define FLASH_INT_CLR_STATUS_FAIL_Pos 0 /*!< FLASH INT_CLR_STATUS: FAIL Position */
-#define FLASH_INT_CLR_STATUS_FAIL_Msk (0x01UL << FLASH_INT_CLR_STATUS_FAIL_Pos) /*!< FLASH INT_CLR_STATUS: FAIL Mask */
-#define FLASH_INT_CLR_STATUS_ERR_Pos 1 /*!< FLASH INT_CLR_STATUS: ERR Position */
-#define FLASH_INT_CLR_STATUS_ERR_Msk (0x01UL << FLASH_INT_CLR_STATUS_ERR_Pos) /*!< FLASH INT_CLR_STATUS: ERR Mask */
-#define FLASH_INT_CLR_STATUS_DONE_Pos 2 /*!< FLASH INT_CLR_STATUS: DONE Position */
-#define FLASH_INT_CLR_STATUS_DONE_Msk (0x01UL << FLASH_INT_CLR_STATUS_DONE_Pos) /*!< FLASH INT_CLR_STATUS: DONE Mask */
-#define FLASH_INT_CLR_STATUS_ECC_ERR_Pos 3 /*!< FLASH INT_CLR_STATUS: ECC_ERR Position */
-#define FLASH_INT_CLR_STATUS_ECC_ERR_Msk (0x01UL << FLASH_INT_CLR_STATUS_ECC_ERR_Pos) /*!< FLASH INT_CLR_STATUS: ECC_ERR Mask */
-
-/* --------------------------- u_flash_INT_SET_STATUS --------------------------- */
-#define FLASH_INT_SET_STATUS_FAIL_Pos 0 /*!< FLASH INT_SET_STATUS: FAIL Position */
-#define FLASH_INT_SET_STATUS_FAIL_Msk (0x01UL << FLASH_INT_SET_STATUS_FAIL_Pos) /*!< FLASH INT_SET_STATUS: FAIL Mask */
-#define FLASH_INT_SET_STATUS_ERR_Pos 1 /*!< FLASH INT_SET_STATUS: ERR Position */
-#define FLASH_INT_SET_STATUS_ERR_Msk (0x01UL << FLASH_INT_SET_STATUS_ERR_Pos) /*!< FLASH INT_SET_STATUS: ERR Mask */
-#define FLASH_INT_SET_STATUS_DONE_Pos 2 /*!< FLASH INT_SET_STATUS: DONE Position */
-#define FLASH_INT_SET_STATUS_DONE_Msk (0x01UL << FLASH_INT_SET_STATUS_DONE_Pos) /*!< FLASH INT_SET_STATUS: DONE Mask */
-#define FLASH_INT_SET_STATUS_ECC_ERR_Pos 3 /*!< FLASH INT_SET_STATUS: ECC_ERR Position */
-#define FLASH_INT_SET_STATUS_ECC_ERR_Msk (0x01UL << FLASH_INT_SET_STATUS_ECC_ERR_Pos) /*!< FLASH INT_SET_STATUS: ECC_ERR Mask */
-
-/* ------------------------------ u_flash_MODULE_ID ----------------------------- */
-#define FLASH_MODULE_ID_APERTURE_Pos 0 /*!< FLASH MODULE_ID: APERTURE Position */
-#define FLASH_MODULE_ID_APERTURE_Msk (0x000000ffUL << FLASH_MODULE_ID_APERTURE_Pos) /*!< FLASH MODULE_ID: APERTURE Mask */
-#define FLASH_MODULE_ID_MINOR_REV_Pos 8 /*!< FLASH MODULE_ID: MINOR_REV Position */
-#define FLASH_MODULE_ID_MINOR_REV_Msk (0x0fUL << FLASH_MODULE_ID_MINOR_REV_Pos) /*!< FLASH MODULE_ID: MINOR_REV Mask */
-#define FLASH_MODULE_ID_MAJOR_REV_Pos 12 /*!< FLASH MODULE_ID: MAJOR_REV Position */
-#define FLASH_MODULE_ID_MAJOR_REV_Msk (0x0fUL << FLASH_MODULE_ID_MAJOR_REV_Pos) /*!< FLASH MODULE_ID: MAJOR_REV Mask */
-#define FLASH_MODULE_ID_ID_Pos 16 /*!< FLASH MODULE_ID: ID Position */
-#define FLASH_MODULE_ID_ID_Msk (0x0000ffffUL << FLASH_MODULE_ID_ID_Pos) /*!< FLASH MODULE_ID: ID Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u_wwdt' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* --------------------------------- u_wwdt_MOD --------------------------------- */
-#define WWDT_MOD_WDEN_Pos 0 /*!< WWDT MOD: WDEN Position */
-#define WWDT_MOD_WDEN_Msk (0x01UL << WWDT_MOD_WDEN_Pos) /*!< WWDT MOD: WDEN Mask */
-#define WWDT_MOD_WDRESET_Pos 1 /*!< WWDT MOD: WDRESET Position */
-#define WWDT_MOD_WDRESET_Msk (0x01UL << WWDT_MOD_WDRESET_Pos) /*!< WWDT MOD: WDRESET Mask */
-#define WWDT_MOD_WDTOF_Pos 2 /*!< WWDT MOD: WDTOF Position */
-#define WWDT_MOD_WDTOF_Msk (0x01UL << WWDT_MOD_WDTOF_Pos) /*!< WWDT MOD: WDTOF Mask */
-#define WWDT_MOD_WDINT_Pos 3 /*!< WWDT MOD: WDINT Position */
-#define WWDT_MOD_WDINT_Msk (0x01UL << WWDT_MOD_WDINT_Pos) /*!< WWDT MOD: WDINT Mask */
-#define WWDT_MOD_WDPROTECT_Pos 4 /*!< WWDT MOD: WDPROTECT Position */
-#define WWDT_MOD_WDPROTECT_Msk (0x01UL << WWDT_MOD_WDPROTECT_Pos) /*!< WWDT MOD: WDPROTECT Mask */
-#define WWDT_MOD_LOCK_Pos 5 /*!< WWDT MOD: LOCK Position */
-#define WWDT_MOD_LOCK_Msk (0x01UL << WWDT_MOD_LOCK_Pos) /*!< WWDT MOD: LOCK Mask */
-
-/* ---------------------------------- u_wwdt_TC --------------------------------- */
-#define WWDT_TC_COUNT_Pos 0 /*!< WWDT TC: COUNT Position */
-#define WWDT_TC_COUNT_Msk (0x00ffffffUL << WWDT_TC_COUNT_Pos) /*!< WWDT TC: COUNT Mask */
-
-/* --------------------------------- u_wwdt_FEED -------------------------------- */
-#define WWDT_FEED_FEED_Pos 0 /*!< WWDT FEED: FEED Position */
-#define WWDT_FEED_FEED_Msk (0x000000ffUL << WWDT_FEED_FEED_Pos) /*!< WWDT FEED: FEED Mask */
-
-/* ---------------------------------- u_wwdt_TV --------------------------------- */
-#define WWDT_TV_COUNT_Pos 0 /*!< WWDT TV: COUNT Position */
-#define WWDT_TV_COUNT_Msk (0x00ffffffUL << WWDT_TV_COUNT_Pos) /*!< WWDT TV: COUNT Mask */
-
-/* ------------------------------- u_wwdt_WARNINT ------------------------------- */
-#define WWDT_WARNINT_WARNINT_Pos 0 /*!< WWDT WARNINT: WARNINT Position */
-#define WWDT_WARNINT_WARNINT_Msk (0x000003ffUL << WWDT_WARNINT_WARNINT_Pos) /*!< WWDT WARNINT: WARNINT Mask */
-
-/* -------------------------------- u_wwdt_WINDOW ------------------------------- */
-#define WWDT_WINDOW_WINDOW_Pos 0 /*!< WWDT WINDOW: WINDOW Position */
-#define WWDT_WINDOW_WINDOW_Msk (0x00ffffffUL << WWDT_WINDOW_WINDOW_Pos) /*!< WWDT WINDOW: WINDOW Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u_rtc' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* --------------------------------- u_rtc_CTRL --------------------------------- */
-#define RTC_CTRL_SWRESET_Pos 0 /*!< RTC CTRL: SWRESET Position */
-#define RTC_CTRL_SWRESET_Msk (0x01UL << RTC_CTRL_SWRESET_Pos) /*!< RTC CTRL: SWRESET Mask */
-#define RTC_CTRL_ALARMT32B_Pos 2 /*!< RTC CTRL: ALARMT32B Position */
-#define RTC_CTRL_ALARMT32B_Msk (0x01UL << RTC_CTRL_ALARMT32B_Pos) /*!< RTC CTRL: ALARMT32B Mask */
-#define RTC_CTRL_WAKET16B_Pos 3 /*!< RTC CTRL: WAKET16B Position */
-#define RTC_CTRL_WAKET16B_Msk (0x01UL << RTC_CTRL_WAKET16B_Pos) /*!< RTC CTRL: WAKET16B Mask */
-#define RTC_CTRL_ALARMDPD_EN_Pos 4 /*!< RTC CTRL: ALARMDPD_EN Position */
-#define RTC_CTRL_ALARMDPD_EN_Msk (0x01UL << RTC_CTRL_ALARMDPD_EN_Pos) /*!< RTC CTRL: ALARMDPD_EN Mask */
-#define RTC_CTRL_WAKEDPD_EN_Pos 5 /*!< RTC CTRL: WAKEDPD_EN Position */
-#define RTC_CTRL_WAKEDPD_EN_Msk (0x01UL << RTC_CTRL_WAKEDPD_EN_Pos) /*!< RTC CTRL: WAKEDPD_EN Mask */
-#define RTC_CTRL_RTCT16B_EN_Pos 6 /*!< RTC CTRL: RTCT16B_EN Position */
-#define RTC_CTRL_RTCT16B_EN_Msk (0x01UL << RTC_CTRL_RTCT16B_EN_Pos) /*!< RTC CTRL: RTCT16B_EN Mask */
-#define RTC_CTRL_RTC_EN_Pos 7 /*!< RTC CTRL: RTC_EN Position */
-#define RTC_CTRL_RTC_EN_Msk (0x01UL << RTC_CTRL_RTC_EN_Pos) /*!< RTC CTRL: RTC_EN Mask */
-
-/* --------------------------------- u_rtc_MATCH -------------------------------- */
-#define RTC_MATCH_MATVAL_Pos 0 /*!< RTC MATCH: MATVAL Position */
-#define RTC_MATCH_MATVAL_Msk (0xffffffffUL << RTC_MATCH_MATVAL_Pos) /*!< RTC MATCH: MATVAL Mask */
-
-/* --------------------------------- u_rtc_COUNT -------------------------------- */
-#define RTC_COUNT_VAL_Pos 0 /*!< RTC COUNT: VAL Position */
-#define RTC_COUNT_VAL_Msk (0xffffffffUL << RTC_COUNT_VAL_Pos) /*!< RTC COUNT: VAL Mask */
-
-/* --------------------------------- u_rtc_WAKE --------------------------------- */
-#define RTC_WAKE_VAL_Pos 0 /*!< RTC WAKE: VAL Position */
-#define RTC_WAKE_VAL_Msk (0x0000ffffUL << RTC_WAKE_VAL_Pos) /*!< RTC WAKE: VAL Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u_pwm' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* --------------------------------- u_pwm_CTRL0 -------------------------------- */
-#define PWM_CTRL0_PWM_EN_0_Pos 0 /*!< PWM CTRL0: PWM_EN_0 Position */
-#define PWM_CTRL0_PWM_EN_0_Msk (0x01UL << PWM_CTRL0_PWM_EN_0_Pos) /*!< PWM CTRL0: PWM_EN_0 Mask */
-#define PWM_CTRL0_PWM_EN_1_Pos 1 /*!< PWM CTRL0: PWM_EN_1 Position */
-#define PWM_CTRL0_PWM_EN_1_Msk (0x01UL << PWM_CTRL0_PWM_EN_1_Pos) /*!< PWM CTRL0: PWM_EN_1 Mask */
-#define PWM_CTRL0_PWM_EN_2_Pos 2 /*!< PWM CTRL0: PWM_EN_2 Position */
-#define PWM_CTRL0_PWM_EN_2_Msk (0x01UL << PWM_CTRL0_PWM_EN_2_Pos) /*!< PWM CTRL0: PWM_EN_2 Mask */
-#define PWM_CTRL0_PWM_EN_3_Pos 3 /*!< PWM CTRL0: PWM_EN_3 Position */
-#define PWM_CTRL0_PWM_EN_3_Msk (0x01UL << PWM_CTRL0_PWM_EN_3_Pos) /*!< PWM CTRL0: PWM_EN_3 Mask */
-#define PWM_CTRL0_PWM_EN_4_Pos 4 /*!< PWM CTRL0: PWM_EN_4 Position */
-#define PWM_CTRL0_PWM_EN_4_Msk (0x01UL << PWM_CTRL0_PWM_EN_4_Pos) /*!< PWM CTRL0: PWM_EN_4 Mask */
-#define PWM_CTRL0_PWM_EN_5_Pos 5 /*!< PWM CTRL0: PWM_EN_5 Position */
-#define PWM_CTRL0_PWM_EN_5_Msk (0x01UL << PWM_CTRL0_PWM_EN_5_Pos) /*!< PWM CTRL0: PWM_EN_5 Mask */
-#define PWM_CTRL0_PWM_EN_6_Pos 6 /*!< PWM CTRL0: PWM_EN_6 Position */
-#define PWM_CTRL0_PWM_EN_6_Msk (0x01UL << PWM_CTRL0_PWM_EN_6_Pos) /*!< PWM CTRL0: PWM_EN_6 Mask */
-#define PWM_CTRL0_PWM_EN_7_Pos 7 /*!< PWM CTRL0: PWM_EN_7 Position */
-#define PWM_CTRL0_PWM_EN_7_Msk (0x01UL << PWM_CTRL0_PWM_EN_7_Pos) /*!< PWM CTRL0: PWM_EN_7 Mask */
-#define PWM_CTRL0_PWM_EN_8_Pos 8 /*!< PWM CTRL0: PWM_EN_8 Position */
-#define PWM_CTRL0_PWM_EN_8_Msk (0x01UL << PWM_CTRL0_PWM_EN_8_Pos) /*!< PWM CTRL0: PWM_EN_8 Mask */
-#define PWM_CTRL0_PWM_EN_9_Pos 9 /*!< PWM CTRL0: PWM_EN_9 Position */
-#define PWM_CTRL0_PWM_EN_9_Msk (0x01UL << PWM_CTRL0_PWM_EN_9_Pos) /*!< PWM CTRL0: PWM_EN_9 Mask */
-#define PWM_CTRL0_PWM_EN_10_Pos 10 /*!< PWM CTRL0: PWM_EN_10 Position */
-#define PWM_CTRL0_PWM_EN_10_Msk (0x01UL << PWM_CTRL0_PWM_EN_10_Pos) /*!< PWM CTRL0: PWM_EN_10 Mask */
-#define PWM_CTRL0_INT_EN_0_Pos 16 /*!< PWM CTRL0: INT_EN_0 Position */
-#define PWM_CTRL0_INT_EN_0_Msk (0x01UL << PWM_CTRL0_INT_EN_0_Pos) /*!< PWM CTRL0: INT_EN_0 Mask */
-#define PWM_CTRL0_INT_EN_1_Pos 17 /*!< PWM CTRL0: INT_EN_1 Position */
-#define PWM_CTRL0_INT_EN_1_Msk (0x01UL << PWM_CTRL0_INT_EN_1_Pos) /*!< PWM CTRL0: INT_EN_1 Mask */
-#define PWM_CTRL0_INT_EN_2_Pos 18 /*!< PWM CTRL0: INT_EN_2 Position */
-#define PWM_CTRL0_INT_EN_2_Msk (0x01UL << PWM_CTRL0_INT_EN_2_Pos) /*!< PWM CTRL0: INT_EN_2 Mask */
-#define PWM_CTRL0_INT_EN_3_Pos 19 /*!< PWM CTRL0: INT_EN_3 Position */
-#define PWM_CTRL0_INT_EN_3_Msk (0x01UL << PWM_CTRL0_INT_EN_3_Pos) /*!< PWM CTRL0: INT_EN_3 Mask */
-#define PWM_CTRL0_INT_EN_4_Pos 20 /*!< PWM CTRL0: INT_EN_4 Position */
-#define PWM_CTRL0_INT_EN_4_Msk (0x01UL << PWM_CTRL0_INT_EN_4_Pos) /*!< PWM CTRL0: INT_EN_4 Mask */
-#define PWM_CTRL0_INT_EN_5_Pos 21 /*!< PWM CTRL0: INT_EN_5 Position */
-#define PWM_CTRL0_INT_EN_5_Msk (0x01UL << PWM_CTRL0_INT_EN_5_Pos) /*!< PWM CTRL0: INT_EN_5 Mask */
-#define PWM_CTRL0_INT_EN_6_Pos 22 /*!< PWM CTRL0: INT_EN_6 Position */
-#define PWM_CTRL0_INT_EN_6_Msk (0x01UL << PWM_CTRL0_INT_EN_6_Pos) /*!< PWM CTRL0: INT_EN_6 Mask */
-#define PWM_CTRL0_INT_EN_7_Pos 23 /*!< PWM CTRL0: INT_EN_7 Position */
-#define PWM_CTRL0_INT_EN_7_Msk (0x01UL << PWM_CTRL0_INT_EN_7_Pos) /*!< PWM CTRL0: INT_EN_7 Mask */
-#define PWM_CTRL0_INT_EN_8_Pos 24 /*!< PWM CTRL0: INT_EN_8 Position */
-#define PWM_CTRL0_INT_EN_8_Msk (0x01UL << PWM_CTRL0_INT_EN_8_Pos) /*!< PWM CTRL0: INT_EN_8 Mask */
-#define PWM_CTRL0_INT_EN_9_Pos 25 /*!< PWM CTRL0: INT_EN_9 Position */
-#define PWM_CTRL0_INT_EN_9_Msk (0x01UL << PWM_CTRL0_INT_EN_9_Pos) /*!< PWM CTRL0: INT_EN_9 Mask */
-#define PWM_CTRL0_INT_EN_10_Pos 26 /*!< PWM CTRL0: INT_EN_10 Position */
-#define PWM_CTRL0_INT_EN_10_Msk (0x01UL << PWM_CTRL0_INT_EN_10_Pos) /*!< PWM CTRL0: INT_EN_10 Mask */
-
-/* --------------------------------- u_pwm_CTRL1 -------------------------------- */
-#define PWM_CTRL1_POL_0_Pos 0 /*!< PWM CTRL1: POL_0 Position */
-#define PWM_CTRL1_POL_0_Msk (0x01UL << PWM_CTRL1_POL_0_Pos) /*!< PWM CTRL1: POL_0 Mask */
-#define PWM_CTRL1_POL_1_Pos 1 /*!< PWM CTRL1: POL_1 Position */
-#define PWM_CTRL1_POL_1_Msk (0x01UL << PWM_CTRL1_POL_1_Pos) /*!< PWM CTRL1: POL_1 Mask */
-#define PWM_CTRL1_POL_2_Pos 2 /*!< PWM CTRL1: POL_2 Position */
-#define PWM_CTRL1_POL_2_Msk (0x01UL << PWM_CTRL1_POL_2_Pos) /*!< PWM CTRL1: POL_2 Mask */
-#define PWM_CTRL1_POL_3_Pos 3 /*!< PWM CTRL1: POL_3 Position */
-#define PWM_CTRL1_POL_3_Msk (0x01UL << PWM_CTRL1_POL_3_Pos) /*!< PWM CTRL1: POL_3 Mask */
-#define PWM_CTRL1_POL_4_Pos 4 /*!< PWM CTRL1: POL_4 Position */
-#define PWM_CTRL1_POL_4_Msk (0x01UL << PWM_CTRL1_POL_4_Pos) /*!< PWM CTRL1: POL_4 Mask */
-#define PWM_CTRL1_POL_5_Pos 5 /*!< PWM CTRL1: POL_5 Position */
-#define PWM_CTRL1_POL_5_Msk (0x01UL << PWM_CTRL1_POL_5_Pos) /*!< PWM CTRL1: POL_5 Mask */
-#define PWM_CTRL1_POL_6_Pos 6 /*!< PWM CTRL1: POL_6 Position */
-#define PWM_CTRL1_POL_6_Msk (0x01UL << PWM_CTRL1_POL_6_Pos) /*!< PWM CTRL1: POL_6 Mask */
-#define PWM_CTRL1_POL_7_Pos 7 /*!< PWM CTRL1: POL_7 Position */
-#define PWM_CTRL1_POL_7_Msk (0x01UL << PWM_CTRL1_POL_7_Pos) /*!< PWM CTRL1: POL_7 Mask */
-#define PWM_CTRL1_POL_8_Pos 8 /*!< PWM CTRL1: POL_8 Position */
-#define PWM_CTRL1_POL_8_Msk (0x01UL << PWM_CTRL1_POL_8_Pos) /*!< PWM CTRL1: POL_8 Mask */
-#define PWM_CTRL1_POL_9_Pos 9 /*!< PWM CTRL1: POL_9 Position */
-#define PWM_CTRL1_POL_9_Msk (0x01UL << PWM_CTRL1_POL_9_Pos) /*!< PWM CTRL1: POL_9 Mask */
-#define PWM_CTRL1_POL_10_Pos 10 /*!< PWM CTRL1: POL_10 Position */
-#define PWM_CTRL1_POL_10_Msk (0x01UL << PWM_CTRL1_POL_10_Pos) /*!< PWM CTRL1: POL_10 Mask */
-#define PWM_CTRL1_DIS_LEVEL_0_Pos 16 /*!< PWM CTRL1: DIS_LEVEL_0 Position */
-#define PWM_CTRL1_DIS_LEVEL_0_Msk (0x01UL << PWM_CTRL1_DIS_LEVEL_0_Pos) /*!< PWM CTRL1: DIS_LEVEL_0 Mask */
-#define PWM_CTRL1_DIS_LEVEL_1_Pos 17 /*!< PWM CTRL1: DIS_LEVEL_1 Position */
-#define PWM_CTRL1_DIS_LEVEL_1_Msk (0x01UL << PWM_CTRL1_DIS_LEVEL_1_Pos) /*!< PWM CTRL1: DIS_LEVEL_1 Mask */
-#define PWM_CTRL1_DIS_LEVEL_2_Pos 18 /*!< PWM CTRL1: DIS_LEVEL_2 Position */
-#define PWM_CTRL1_DIS_LEVEL_2_Msk (0x01UL << PWM_CTRL1_DIS_LEVEL_2_Pos) /*!< PWM CTRL1: DIS_LEVEL_2 Mask */
-#define PWM_CTRL1_DIS_LEVEL_3_Pos 19 /*!< PWM CTRL1: DIS_LEVEL_3 Position */
-#define PWM_CTRL1_DIS_LEVEL_3_Msk (0x01UL << PWM_CTRL1_DIS_LEVEL_3_Pos) /*!< PWM CTRL1: DIS_LEVEL_3 Mask */
-#define PWM_CTRL1_DIS_LEVEL_4_Pos 20 /*!< PWM CTRL1: DIS_LEVEL_4 Position */
-#define PWM_CTRL1_DIS_LEVEL_4_Msk (0x01UL << PWM_CTRL1_DIS_LEVEL_4_Pos) /*!< PWM CTRL1: DIS_LEVEL_4 Mask */
-#define PWM_CTRL1_DIS_LEVEL_5_Pos 21 /*!< PWM CTRL1: DIS_LEVEL_5 Position */
-#define PWM_CTRL1_DIS_LEVEL_5_Msk (0x01UL << PWM_CTRL1_DIS_LEVEL_5_Pos) /*!< PWM CTRL1: DIS_LEVEL_5 Mask */
-#define PWM_CTRL1_DIS_LEVEL_6_Pos 22 /*!< PWM CTRL1: DIS_LEVEL_6 Position */
-#define PWM_CTRL1_DIS_LEVEL_6_Msk (0x01UL << PWM_CTRL1_DIS_LEVEL_6_Pos) /*!< PWM CTRL1: DIS_LEVEL_6 Mask */
-#define PWM_CTRL1_DIS_LEVEL_7_Pos 23 /*!< PWM CTRL1: DIS_LEVEL_7 Position */
-#define PWM_CTRL1_DIS_LEVEL_7_Msk (0x01UL << PWM_CTRL1_DIS_LEVEL_7_Pos) /*!< PWM CTRL1: DIS_LEVEL_7 Mask */
-#define PWM_CTRL1_DIS_LEVEL_8_Pos 24 /*!< PWM CTRL1: DIS_LEVEL_8 Position */
-#define PWM_CTRL1_DIS_LEVEL_8_Msk (0x01UL << PWM_CTRL1_DIS_LEVEL_8_Pos) /*!< PWM CTRL1: DIS_LEVEL_8 Mask */
-#define PWM_CTRL1_DIS_LEVEL_9_Pos 25 /*!< PWM CTRL1: DIS_LEVEL_9 Position */
-#define PWM_CTRL1_DIS_LEVEL_9_Msk (0x01UL << PWM_CTRL1_DIS_LEVEL_9_Pos) /*!< PWM CTRL1: DIS_LEVEL_9 Mask */
-
-/* -------------------------------- u_pwm_PSCL01 -------------------------------- */
-#define PWM_PSCL01_PSCL_0_Pos 0 /*!< PWM PSCL01: PSCL_0 Position */
-#define PWM_PSCL01_PSCL_0_Msk (0x000003ffUL << PWM_PSCL01_PSCL_0_Pos) /*!< PWM PSCL01: PSCL_0 Mask */
-#define PWM_PSCL01_PSCL_1_Pos 16 /*!< PWM PSCL01: PSCL_1 Position */
-#define PWM_PSCL01_PSCL_1_Msk (0x000003ffUL << PWM_PSCL01_PSCL_1_Pos) /*!< PWM PSCL01: PSCL_1 Mask */
-
-/* -------------------------------- u_pwm_PSCL23 -------------------------------- */
-#define PWM_PSCL23_PSCL_2_Pos 0 /*!< PWM PSCL23: PSCL_2 Position */
-#define PWM_PSCL23_PSCL_2_Msk (0x000003ffUL << PWM_PSCL23_PSCL_2_Pos) /*!< PWM PSCL23: PSCL_2 Mask */
-#define PWM_PSCL23_PSCL_3_Pos 16 /*!< PWM PSCL23: PSCL_3 Position */
-#define PWM_PSCL23_PSCL_3_Msk (0x000003ffUL << PWM_PSCL23_PSCL_3_Pos) /*!< PWM PSCL23: PSCL_3 Mask */
-
-/* -------------------------------- u_pwm_PSCL45 -------------------------------- */
-#define PWM_PSCL45_PSCL_4_Pos 0 /*!< PWM PSCL45: PSCL_4 Position */
-#define PWM_PSCL45_PSCL_4_Msk (0x000003ffUL << PWM_PSCL45_PSCL_4_Pos) /*!< PWM PSCL45: PSCL_4 Mask */
-#define PWM_PSCL45_PSCL_5_Pos 16 /*!< PWM PSCL45: PSCL_5 Position */
-#define PWM_PSCL45_PSCL_5_Msk (0x000003ffUL << PWM_PSCL45_PSCL_5_Pos) /*!< PWM PSCL45: PSCL_5 Mask */
-
-/* -------------------------------- u_pwm_PSCL67 -------------------------------- */
-#define PWM_PSCL67_PSCL_6_Pos 0 /*!< PWM PSCL67: PSCL_6 Position */
-#define PWM_PSCL67_PSCL_6_Msk (0x000003ffUL << PWM_PSCL67_PSCL_6_Pos) /*!< PWM PSCL67: PSCL_6 Mask */
-#define PWM_PSCL67_PSCL_7_Pos 16 /*!< PWM PSCL67: PSCL_7 Position */
-#define PWM_PSCL67_PSCL_7_Msk (0x000003ffUL << PWM_PSCL67_PSCL_7_Pos) /*!< PWM PSCL67: PSCL_7 Mask */
-
-/* -------------------------------- u_pwm_PSCL89 -------------------------------- */
-#define PWM_PSCL89_PSCL_8_Pos 0 /*!< PWM PSCL89: PSCL_8 Position */
-#define PWM_PSCL89_PSCL_8_Msk (0x000003ffUL << PWM_PSCL89_PSCL_8_Pos) /*!< PWM PSCL89: PSCL_8 Mask */
-#define PWM_PSCL89_PSCL_9_Pos 16 /*!< PWM PSCL89: PSCL_9 Position */
-#define PWM_PSCL89_PSCL_9_Msk (0x000003ffUL << PWM_PSCL89_PSCL_9_Pos) /*!< PWM PSCL89: PSCL_9 Mask */
-
-/* ------------------------------- u_pwm_PSCL1011 ------------------------------- */
-#define PWM_PSCL1011_PSCL_10_Pos 0 /*!< PWM PSCL1011: PSCL_10 Position */
-#define PWM_PSCL1011_PSCL_10_Msk (0x000003ffUL << PWM_PSCL1011_PSCL_10_Pos) /*!< PWM PSCL1011: PSCL_10 Mask */
-
-/* --------------------------------- u_pwm_PCP0 --------------------------------- */
-#define PWM_PCP0_PERIOD_Pos 0 /*!< PWM PCP0: PERIOD Position */
-#define PWM_PCP0_PERIOD_Msk (0x0000ffffUL << PWM_PCP0_PERIOD_Pos) /*!< PWM PCP0: PERIOD Mask */
-#define PWM_PCP0_COMPARE_Pos 16 /*!< PWM PCP0: COMPARE Position */
-#define PWM_PCP0_COMPARE_Msk (0x0000ffffUL << PWM_PCP0_COMPARE_Pos) /*!< PWM PCP0: COMPARE Mask */
-
-/* --------------------------------- u_pwm_PCP1 --------------------------------- */
-#define PWM_PCP1_PERIOD_Pos 0 /*!< PWM PCP1: PERIOD Position */
-#define PWM_PCP1_PERIOD_Msk (0x0000ffffUL << PWM_PCP1_PERIOD_Pos) /*!< PWM PCP1: PERIOD Mask */
-#define PWM_PCP1_COMPARE_Pos 16 /*!< PWM PCP1: COMPARE Position */
-#define PWM_PCP1_COMPARE_Msk (0x0000ffffUL << PWM_PCP1_COMPARE_Pos) /*!< PWM PCP1: COMPARE Mask */
-
-/* --------------------------------- u_pwm_PCP2 --------------------------------- */
-#define PWM_PCP2_PERIOD_Pos 0 /*!< PWM PCP2: PERIOD Position */
-#define PWM_PCP2_PERIOD_Msk (0x0000ffffUL << PWM_PCP2_PERIOD_Pos) /*!< PWM PCP2: PERIOD Mask */
-#define PWM_PCP2_COMPARE_Pos 16 /*!< PWM PCP2: COMPARE Position */
-#define PWM_PCP2_COMPARE_Msk (0x0000ffffUL << PWM_PCP2_COMPARE_Pos) /*!< PWM PCP2: COMPARE Mask */
-
-/* --------------------------------- u_pwm_PCP3 --------------------------------- */
-#define PWM_PCP3_PERIOD_Pos 0 /*!< PWM PCP3: PERIOD Position */
-#define PWM_PCP3_PERIOD_Msk (0x0000ffffUL << PWM_PCP3_PERIOD_Pos) /*!< PWM PCP3: PERIOD Mask */
-#define PWM_PCP3_COMPARE_Pos 16 /*!< PWM PCP3: COMPARE Position */
-#define PWM_PCP3_COMPARE_Msk (0x0000ffffUL << PWM_PCP3_COMPARE_Pos) /*!< PWM PCP3: COMPARE Mask */
-
-/* --------------------------------- u_pwm_PCP4 --------------------------------- */
-#define PWM_PCP4_PERIOD_Pos 0 /*!< PWM PCP4: PERIOD Position */
-#define PWM_PCP4_PERIOD_Msk (0x0000ffffUL << PWM_PCP4_PERIOD_Pos) /*!< PWM PCP4: PERIOD Mask */
-#define PWM_PCP4_COMPARE_Pos 16 /*!< PWM PCP4: COMPARE Position */
-#define PWM_PCP4_COMPARE_Msk (0x0000ffffUL << PWM_PCP4_COMPARE_Pos) /*!< PWM PCP4: COMPARE Mask */
-
-/* --------------------------------- u_pwm_PCP5 --------------------------------- */
-#define PWM_PCP5_PERIOD_Pos 0 /*!< PWM PCP5: PERIOD Position */
-#define PWM_PCP5_PERIOD_Msk (0x0000ffffUL << PWM_PCP5_PERIOD_Pos) /*!< PWM PCP5: PERIOD Mask */
-#define PWM_PCP5_COMPARE_Pos 16 /*!< PWM PCP5: COMPARE Position */
-#define PWM_PCP5_COMPARE_Msk (0x0000ffffUL << PWM_PCP5_COMPARE_Pos) /*!< PWM PCP5: COMPARE Mask */
-
-/* --------------------------------- u_pwm_PCP6 --------------------------------- */
-#define PWM_PCP6_PERIOD_Pos 0 /*!< PWM PCP6: PERIOD Position */
-#define PWM_PCP6_PERIOD_Msk (0x0000ffffUL << PWM_PCP6_PERIOD_Pos) /*!< PWM PCP6: PERIOD Mask */
-#define PWM_PCP6_COMPARE_Pos 16 /*!< PWM PCP6: COMPARE Position */
-#define PWM_PCP6_COMPARE_Msk (0x0000ffffUL << PWM_PCP6_COMPARE_Pos) /*!< PWM PCP6: COMPARE Mask */
-
-/* --------------------------------- u_pwm_PCP7 --------------------------------- */
-#define PWM_PCP7_PERIOD_Pos 0 /*!< PWM PCP7: PERIOD Position */
-#define PWM_PCP7_PERIOD_Msk (0x0000ffffUL << PWM_PCP7_PERIOD_Pos) /*!< PWM PCP7: PERIOD Mask */
-#define PWM_PCP7_COMPARE_Pos 16 /*!< PWM PCP7: COMPARE Position */
-#define PWM_PCP7_COMPARE_Msk (0x0000ffffUL << PWM_PCP7_COMPARE_Pos) /*!< PWM PCP7: COMPARE Mask */
-
-/* --------------------------------- u_pwm_PCP8 --------------------------------- */
-#define PWM_PCP8_PERIOD_Pos 0 /*!< PWM PCP8: PERIOD Position */
-#define PWM_PCP8_PERIOD_Msk (0x0000ffffUL << PWM_PCP8_PERIOD_Pos) /*!< PWM PCP8: PERIOD Mask */
-#define PWM_PCP8_COMPARE_Pos 16 /*!< PWM PCP8: COMPARE Position */
-#define PWM_PCP8_COMPARE_Msk (0x0000ffffUL << PWM_PCP8_COMPARE_Pos) /*!< PWM PCP8: COMPARE Mask */
-
-/* --------------------------------- u_pwm_PCP9 --------------------------------- */
-#define PWM_PCP9_PERIOD_Pos 0 /*!< PWM PCP9: PERIOD Position */
-#define PWM_PCP9_PERIOD_Msk (0x0000ffffUL << PWM_PCP9_PERIOD_Pos) /*!< PWM PCP9: PERIOD Mask */
-#define PWM_PCP9_COMPARE_Pos 16 /*!< PWM PCP9: COMPARE Position */
-#define PWM_PCP9_COMPARE_Msk (0x0000ffffUL << PWM_PCP9_COMPARE_Pos) /*!< PWM PCP9: COMPARE Mask */
-
-/* --------------------------------- u_pwm_PCP10 -------------------------------- */
-#define PWM_PCP10_PERIOD_Pos 0 /*!< PWM PCP10: PERIOD Position */
-#define PWM_PCP10_PERIOD_Msk (0x0000ffffUL << PWM_PCP10_PERIOD_Pos) /*!< PWM PCP10: PERIOD Mask */
-#define PWM_PCP10_COMPARE_Pos 16 /*!< PWM PCP10: COMPARE Position */
-#define PWM_PCP10_COMPARE_Msk (0x0000ffffUL << PWM_PCP10_COMPARE_Pos) /*!< PWM PCP10: COMPARE Mask */
-
-/* --------------------------------- u_pwm_PST0 --------------------------------- */
-#define PWM_PST0_INT_FLG_0_Pos 0 /*!< PWM PST0: INT_FLG_0 Position */
-#define PWM_PST0_INT_FLG_0_Msk (0x01UL << PWM_PST0_INT_FLG_0_Pos) /*!< PWM PST0: INT_FLG_0 Mask */
-#define PWM_PST0_INT_FLG_1_Pos 8 /*!< PWM PST0: INT_FLG_1 Position */
-#define PWM_PST0_INT_FLG_1_Msk (0x01UL << PWM_PST0_INT_FLG_1_Pos) /*!< PWM PST0: INT_FLG_1 Mask */
-#define PWM_PST0_INT_FLG_2_Pos 16 /*!< PWM PST0: INT_FLG_2 Position */
-#define PWM_PST0_INT_FLG_2_Msk (0x01UL << PWM_PST0_INT_FLG_2_Pos) /*!< PWM PST0: INT_FLG_2 Mask */
-#define PWM_PST0_INT_FLG_3_Pos 24 /*!< PWM PST0: INT_FLG_3 Position */
-#define PWM_PST0_INT_FLG_3_Msk (0x01UL << PWM_PST0_INT_FLG_3_Pos) /*!< PWM PST0: INT_FLG_3 Mask */
-
-/* --------------------------------- u_pwm_PST1 --------------------------------- */
-#define PWM_PST1_INT_FLG_4_Pos 0 /*!< PWM PST1: INT_FLG_4 Position */
-#define PWM_PST1_INT_FLG_4_Msk (0x01UL << PWM_PST1_INT_FLG_4_Pos) /*!< PWM PST1: INT_FLG_4 Mask */
-#define PWM_PST1_INT_FLG_5_Pos 8 /*!< PWM PST1: INT_FLG_5 Position */
-#define PWM_PST1_INT_FLG_5_Msk (0x01UL << PWM_PST1_INT_FLG_5_Pos) /*!< PWM PST1: INT_FLG_5 Mask */
-#define PWM_PST1_INT_FLG_6_Pos 16 /*!< PWM PST1: INT_FLG_6 Position */
-#define PWM_PST1_INT_FLG_6_Msk (0x01UL << PWM_PST1_INT_FLG_6_Pos) /*!< PWM PST1: INT_FLG_6 Mask */
-#define PWM_PST1_INT_FLG_7_Pos 24 /*!< PWM PST1: INT_FLG_7 Position */
-#define PWM_PST1_INT_FLG_7_Msk (0x01UL << PWM_PST1_INT_FLG_7_Pos) /*!< PWM PST1: INT_FLG_7 Mask */
-
-/* --------------------------------- u_pwm_PST2 --------------------------------- */
-#define PWM_PST2_INT_FLG_8_Pos 0 /*!< PWM PST2: INT_FLG_8 Position */
-#define PWM_PST2_INT_FLG_8_Msk (0x01UL << PWM_PST2_INT_FLG_8_Pos) /*!< PWM PST2: INT_FLG_8 Mask */
-#define PWM_PST2_INT_FLG_9_Pos 8 /*!< PWM PST2: INT_FLG_9 Position */
-#define PWM_PST2_INT_FLG_9_Msk (0x01UL << PWM_PST2_INT_FLG_9_Pos) /*!< PWM PST2: INT_FLG_9 Mask */
-#define PWM_PST2_INT_FLG_10_Pos 16 /*!< PWM PST2: INT_FLG_10 Position */
-#define PWM_PST2_INT_FLG_10_Msk (0x01UL << PWM_PST2_INT_FLG_10_Pos) /*!< PWM PST2: INT_FLG_10 Mask */
-
-/* ------------------------------- u_pwm_MODULE_ID ------------------------------ */
-#define PWM_MODULE_ID_APERTURE_Pos 0 /*!< PWM MODULE_ID: APERTURE Position */
-#define PWM_MODULE_ID_APERTURE_Msk (0x000000ffUL << PWM_MODULE_ID_APERTURE_Pos) /*!< PWM MODULE_ID: APERTURE Mask */
-#define PWM_MODULE_ID_MIN_REV_Pos 8 /*!< PWM MODULE_ID: MIN_REV Position */
-#define PWM_MODULE_ID_MIN_REV_Msk (0x0fUL << PWM_MODULE_ID_MIN_REV_Pos) /*!< PWM MODULE_ID: MIN_REV Mask */
-#define PWM_MODULE_ID_MAJ_REV_Pos 12 /*!< PWM MODULE_ID: MAJ_REV Position */
-#define PWM_MODULE_ID_MAJ_REV_Msk (0x0fUL << PWM_MODULE_ID_MAJ_REV_Pos) /*!< PWM MODULE_ID: MAJ_REV Mask */
-#define PWM_MODULE_ID_ID_Pos 16 /*!< PWM MODULE_ID: ID Position */
-#define PWM_MODULE_ID_ID_Msk (0x0000ffffUL << PWM_MODULE_ID_ID_Pos) /*!< PWM MODULE_ID: ID Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u_rng' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* ----------------------------- u_rng_RANDOM_NUMBER ---------------------------- */
-#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_Pos 0 /*!< RNG RANDOM_NUMBER: RANDOM_NUMBER Position */
-#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_Msk (0xffffffffUL << RNG_RANDOM_NUMBER_RANDOM_NUMBER_Pos) /*!< RNG RANDOM_NUMBER: RANDOM_NUMBER Mask */
-
-/* --------------------------- u_rng_ENCRYPTED_NUMBER --------------------------- */
-#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_Pos 0 /*!< RNG ENCRYPTED_NUMBER: ENCRYPTED_NUMBER Position */
-#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_Msk (0xffffffffUL << RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_Pos)/*!< RNG ENCRYPTED_NUMBER: ENCRYPTED_NUMBER Mask */
-
-/* ------------------------------ u_rng_COUNTER_VAL ----------------------------- */
-#define RNG_COUNTER_VAL_CLK_RATIO_Pos 0 /*!< RNG COUNTER_VAL: CLK_RATIO Position */
-#define RNG_COUNTER_VAL_CLK_RATIO_Msk (0x000000ffUL << RNG_COUNTER_VAL_CLK_RATIO_Pos) /*!< RNG COUNTER_VAL: CLK_RATIO Mask */
-#define RNG_COUNTER_VAL_REFRESH_CNT_Pos 8 /*!< RNG COUNTER_VAL: REFRESH_CNT Position */
-#define RNG_COUNTER_VAL_REFRESH_CNT_Msk (0x1fUL << RNG_COUNTER_VAL_REFRESH_CNT_Pos) /*!< RNG COUNTER_VAL: REFRESH_CNT Mask */
-
-/* ------------------------------ u_rng_COUNTER_CFG ----------------------------- */
-#define RNG_COUNTER_CFG_MODE_Pos 0 /*!< RNG COUNTER_CFG: MODE Position */
-#define RNG_COUNTER_CFG_MODE_Msk (0x03UL << RNG_COUNTER_CFG_MODE_Pos) /*!< RNG COUNTER_CFG: MODE Mask */
-#define RNG_COUNTER_CFG_CLOCK_SEL_Pos 2 /*!< RNG COUNTER_CFG: CLOCK_SEL Position */
-#define RNG_COUNTER_CFG_CLOCK_SEL_Msk (0x07UL << RNG_COUNTER_CFG_CLOCK_SEL_Pos) /*!< RNG COUNTER_CFG: CLOCK_SEL Mask */
-#define RNG_COUNTER_CFG_SHIFT4X_Pos 5 /*!< RNG COUNTER_CFG: SHIFT4X Position */
-#define RNG_COUNTER_CFG_SHIFT4X_Msk (0x07UL << RNG_COUNTER_CFG_SHIFT4X_Pos) /*!< RNG COUNTER_CFG: SHIFT4X Mask */
-#define RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_Pos 8 /*!< RNG COUNTER_CFG: DIS_ENH_ENTR_REFILL Position */
-#define RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_Msk (0x01UL << RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_Pos)/*!< RNG COUNTER_CFG: DIS_ENH_ENTR_REFILL Mask */
-#define RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_Pos 9 /*!< RNG COUNTER_CFG: FORCE_ENTR_SPREADING Position */
-#define RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_Msk (0x01UL << RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_Pos)/*!< RNG COUNTER_CFG: FORCE_ENTR_SPREADING Mask */
-
-/* ---------------------------- u_rng_ONLINE_TEST_CFG --------------------------- */
-#define RNG_ONLINE_TEST_CFG_ACTIVATE_Pos 0 /*!< RNG ONLINE_TEST_CFG: ACTIVATE Position */
-#define RNG_ONLINE_TEST_CFG_ACTIVATE_Msk (0x01UL << RNG_ONLINE_TEST_CFG_ACTIVATE_Pos) /*!< RNG ONLINE_TEST_CFG: ACTIVATE Mask */
-#define RNG_ONLINE_TEST_CFG_DATA_SEL_Pos 1 /*!< RNG ONLINE_TEST_CFG: DATA_SEL Position */
-#define RNG_ONLINE_TEST_CFG_DATA_SEL_Msk (0x03UL << RNG_ONLINE_TEST_CFG_DATA_SEL_Pos) /*!< RNG ONLINE_TEST_CFG: DATA_SEL Mask */
-
-/* ---------------------------- u_rng_ONLINE_TEST_VAL --------------------------- */
-#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_Pos 0 /*!< RNG ONLINE_TEST_VAL: LIVE_CHI_SQUARED Position */
-#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_Msk (0x0fUL << RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_Pos)/*!< RNG ONLINE_TEST_VAL: LIVE_CHI_SQUARED Mask */
-#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_Pos 4 /*!< RNG ONLINE_TEST_VAL: MIN_CHI_SQUARED Position */
-#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_Msk (0x0fUL << RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_Pos)/*!< RNG ONLINE_TEST_VAL: MIN_CHI_SQUARED Mask */
-#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_Pos 8 /*!< RNG ONLINE_TEST_VAL: MAX_CHI_SQUARED Position */
-#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_Msk (0x0fUL << RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_Pos)/*!< RNG ONLINE_TEST_VAL: MAX_CHI_SQUARED Mask */
-
-/* ------------------------------- u_rng_MISC_CFG ------------------------------- */
-#define RNG_MISC_CFG_AES_RESEED_Pos 0 /*!< RNG MISC_CFG: AES_RESEED Position */
-#define RNG_MISC_CFG_AES_RESEED_Msk (0x01UL << RNG_MISC_CFG_AES_RESEED_Pos) /*!< RNG MISC_CFG: AES_RESEED Mask */
-#define RNG_MISC_CFG_AES_DT_CFG_Pos 1 /*!< RNG MISC_CFG: AES_DT_CFG Position */
-#define RNG_MISC_CFG_AES_DT_CFG_Msk (0x01UL << RNG_MISC_CFG_AES_DT_CFG_Pos) /*!< RNG MISC_CFG: AES_DT_CFG Mask */
-
-/* ------------------------------- u_rng_POWERDOWN ------------------------------ */
-#define RNG_POWERDOWN_SOFT_RESET_Pos 0 /*!< RNG POWERDOWN: SOFT_RESET Position */
-#define RNG_POWERDOWN_SOFT_RESET_Msk (0x01UL << RNG_POWERDOWN_SOFT_RESET_Pos) /*!< RNG POWERDOWN: SOFT_RESET Mask */
-#define RNG_POWERDOWN_FORCE_SOFT_RESET_Pos 1 /*!< RNG POWERDOWN: FORCE_SOFT_RESET Position */
-#define RNG_POWERDOWN_FORCE_SOFT_RESET_Msk (0x01UL << RNG_POWERDOWN_FORCE_SOFT_RESET_Pos) /*!< RNG POWERDOWN: FORCE_SOFT_RESET Mask */
-#define RNG_POWERDOWN_POWERDOWN_Pos 31 /*!< RNG POWERDOWN: POWERDOWN Position */
-#define RNG_POWERDOWN_POWERDOWN_Msk (0x01UL << RNG_POWERDOWN_POWERDOWN_Pos) /*!< RNG POWERDOWN: POWERDOWN Mask */
-
-/* ------------------------------- u_rng_MODULEID ------------------------------- */
-#define RNG_MODULEID_APERTURE_Pos 0 /*!< RNG MODULEID: APERTURE Position */
-#define RNG_MODULEID_APERTURE_Msk (0x000000ffUL << RNG_MODULEID_APERTURE_Pos) /*!< RNG MODULEID: APERTURE Mask */
-#define RNG_MODULEID_MIN_REV_Pos 8 /*!< RNG MODULEID: MIN_REV Position */
-#define RNG_MODULEID_MIN_REV_Msk (0x0fUL << RNG_MODULEID_MIN_REV_Pos) /*!< RNG MODULEID: MIN_REV Mask */
-#define RNG_MODULEID_MAJ_REV_Pos 12 /*!< RNG MODULEID: MAJ_REV Position */
-#define RNG_MODULEID_MAJ_REV_Msk (0x0fUL << RNG_MODULEID_MAJ_REV_Pos) /*!< RNG MODULEID: MAJ_REV Mask */
-#define RNG_MODULEID_ID_Pos 16 /*!< RNG MODULEID: ID Position */
-#define RNG_MODULEID_ID_Msk (0x0000ffffUL << RNG_MODULEID_ID_Pos) /*!< RNG MODULEID: ID Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u_inmux' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* ------------------------------- u_inmux_PINTSEL ------------------------------ */
-#define INMUX_PINTSEL_INTPIN_Pos 0 /*!< INMUX PINTSEL: INTPIN Position */
-#define INMUX_PINTSEL_INTPIN_Msk (0x1fUL << INMUX_PINTSEL_INTPIN_Pos) /*!< INMUX PINTSEL: INTPIN Mask */
-
-/* --------------------------- u_inmux_DMA_ITRIG_INMUX -------------------------- */
-#define INMUX_DMA_ITRIG_INMUX_INP_Pos 0 /*!< INMUX DMA_ITRIG_INMUX: INP Position */
-#define INMUX_DMA_ITRIG_INMUX_INP_Msk (0x1fUL << INMUX_DMA_ITRIG_INMUX_INP_Pos) /*!< INMUX DMA_ITRIG_INMUX: INP Mask */
-
-/* --------------------------- u_inmux_DMA_OTRIG_INMUX -------------------------- */
-#define INMUX_DMA_OTRIG_INMUX_INP_Pos 0 /*!< INMUX DMA_OTRIG_INMUX: INP Position */
-#define INMUX_DMA_OTRIG_INMUX_INP_Msk (0x1fUL << INMUX_DMA_OTRIG_INMUX_INP_Pos) /*!< INMUX DMA_OTRIG_INMUX: INP Mask */
-
-/* ---------------------------- u_inmux_FREQMEAS_REF ---------------------------- */
-#define INMUX_FREQMEAS_REF_CLKIN_Pos 0 /*!< INMUX FREQMEAS_REF: CLKIN Position */
-#define INMUX_FREQMEAS_REF_CLKIN_Msk (0x0fUL << INMUX_FREQMEAS_REF_CLKIN_Pos) /*!< INMUX FREQMEAS_REF: CLKIN Mask */
-
-/* --------------------------- u_inmux_FREQMEAS_TARGET -------------------------- */
-#define INMUX_FREQMEAS_TARGET_CLKIN_Pos 0 /*!< INMUX FREQMEAS_TARGET: CLKIN Position */
-#define INMUX_FREQMEAS_TARGET_CLKIN_Msk (0x0fUL << INMUX_FREQMEAS_TARGET_CLKIN_Pos) /*!< INMUX FREQMEAS_TARGET: CLKIN Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u_iocon' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* --------------------------------- u_iocon_PIO -------------------------------- */
-#define IOCON_PIO_FUNC_Pos 0 /*!< IOCON PIO: FUNC Position */
-#define IOCON_PIO_FUNC_Msk (0x07UL << IOCON_PIO_FUNC_Pos) /*!< IOCON PIO: FUNC Mask */
-#define IOCON_PIO_MODE_Pos 3 /*!< IOCON PIO: MODE Position */
-#define IOCON_PIO_MODE_Msk (0x03UL << IOCON_PIO_MODE_Pos) /*!< IOCON PIO: MODE Mask */
-#define IOCON_PIO_SLEW0_Pos 5 /*!< IOCON PIO: SLEW0 Position */
-#define IOCON_PIO_SLEW0_Msk (0x01UL << IOCON_PIO_SLEW0_Pos) /*!< IOCON PIO: SLEW0 Mask */
-#define IOCON_PIO_INVERT_Pos 6 /*!< IOCON PIO: INVERT Position */
-#define IOCON_PIO_INVERT_Msk (0x01UL << IOCON_PIO_INVERT_Pos) /*!< IOCON PIO: INVERT Mask */
-#define IOCON_PIO_DIGIMODE_Pos 7 /*!< IOCON PIO: DIGIMODE Position */
-#define IOCON_PIO_DIGIMODE_Msk (0x01UL << IOCON_PIO_DIGIMODE_Pos) /*!< IOCON PIO: DIGIMODE Mask */
-#define IOCON_PIO_FILTEROFF_Pos 8 /*!< IOCON PIO: FILTEROFF Position */
-#define IOCON_PIO_FILTEROFF_Msk (0x01UL << IOCON_PIO_FILTEROFF_Pos) /*!< IOCON PIO: FILTEROFF Mask */
-#define IOCON_PIO_SLEW1_Pos 9 /*!< IOCON PIO: SLEW1 Position */
-#define IOCON_PIO_SLEW1_Msk (0x01UL << IOCON_PIO_SLEW1_Pos) /*!< IOCON PIO: SLEW1 Mask */
-#define IOCON_PIO_OD_Pos 10 /*!< IOCON PIO: OD Position */
-#define IOCON_PIO_OD_Msk (0x01UL << IOCON_PIO_OD_Pos) /*!< IOCON PIO: OD Mask */
-#define IOCON_PIO_SSEL_Pos 11 /*!< IOCON PIO: SSEL Position */
-#define IOCON_PIO_SSEL_Msk (0x01UL << IOCON_PIO_SSEL_Pos) /*!< IOCON PIO: SSEL Mask */
-#define IOCON_PIO_DBG_FUNC_Pos 12 /*!< IOCON PIO: DBG_FUNC Position */
-#define IOCON_PIO_DBG_FUNC_Msk (0x0fUL << IOCON_PIO_DBG_FUNC_Pos) /*!< IOCON PIO: DBG_FUNC Mask */
-#define IOCON_PIO_DBG_MODE_Pos 16 /*!< IOCON PIO: DBG_MODE Position */
-#define IOCON_PIO_DBG_MODE_Msk (0x01UL << IOCON_PIO_DBG_MODE_Pos) /*!< IOCON PIO: DBG_MODE Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u_pint' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* --------------------------------- u_pint_ISEL -------------------------------- */
-#define PININT_ISEL_PMODE_PIN0_Pos 0 /*!< PININT ISEL: PMODE_PIN0 Position */
-#define PININT_ISEL_PMODE_PIN0_Msk (0x01UL << PININT_ISEL_PMODE_PIN0_Pos) /*!< PININT ISEL: PMODE_PIN0 Mask */
-#define PININT_ISEL_PMODE_PIN1_Pos 1 /*!< PININT ISEL: PMODE_PIN1 Position */
-#define PININT_ISEL_PMODE_PIN1_Msk (0x01UL << PININT_ISEL_PMODE_PIN1_Pos) /*!< PININT ISEL: PMODE_PIN1 Mask */
-#define PININT_ISEL_PMODE_PIN2_Pos 2 /*!< PININT ISEL: PMODE_PIN2 Position */
-#define PININT_ISEL_PMODE_PIN2_Msk (0x01UL << PININT_ISEL_PMODE_PIN2_Pos) /*!< PININT ISEL: PMODE_PIN2 Mask */
-#define PININT_ISEL_PMODE_PIN3_Pos 3 /*!< PININT ISEL: PMODE_PIN3 Position */
-#define PININT_ISEL_PMODE_PIN3_Msk (0x01UL << PININT_ISEL_PMODE_PIN3_Pos) /*!< PININT ISEL: PMODE_PIN3 Mask */
-#define PININT_ISEL_PMODE_PIN4_Pos 4 /*!< PININT ISEL: PMODE_PIN4 Position */
-#define PININT_ISEL_PMODE_PIN4_Msk (0x01UL << PININT_ISEL_PMODE_PIN4_Pos) /*!< PININT ISEL: PMODE_PIN4 Mask */
-#define PININT_ISEL_PMODE_PIN5_Pos 5 /*!< PININT ISEL: PMODE_PIN5 Position */
-#define PININT_ISEL_PMODE_PIN5_Msk (0x01UL << PININT_ISEL_PMODE_PIN5_Pos) /*!< PININT ISEL: PMODE_PIN5 Mask */
-#define PININT_ISEL_PMODE_PIN6_Pos 6 /*!< PININT ISEL: PMODE_PIN6 Position */
-#define PININT_ISEL_PMODE_PIN6_Msk (0x01UL << PININT_ISEL_PMODE_PIN6_Pos) /*!< PININT ISEL: PMODE_PIN6 Mask */
-#define PININT_ISEL_PMODE_PIN7_Pos 7 /*!< PININT ISEL: PMODE_PIN7 Position */
-#define PININT_ISEL_PMODE_PIN7_Msk (0x01UL << PININT_ISEL_PMODE_PIN7_Pos) /*!< PININT ISEL: PMODE_PIN7 Mask */
-
-/* --------------------------------- u_pint_IENR -------------------------------- */
-#define PININT_IENR_ENRL_PIN0_Pos 0 /*!< PININT IENR: ENRL_PIN0 Position */
-#define PININT_IENR_ENRL_PIN0_Msk (0x01UL << PININT_IENR_ENRL_PIN0_Pos) /*!< PININT IENR: ENRL_PIN0 Mask */
-#define PININT_IENR_ENRL_PIN1_Pos 1 /*!< PININT IENR: ENRL_PIN1 Position */
-#define PININT_IENR_ENRL_PIN1_Msk (0x01UL << PININT_IENR_ENRL_PIN1_Pos) /*!< PININT IENR: ENRL_PIN1 Mask */
-#define PININT_IENR_ENRL_PIN2_Pos 2 /*!< PININT IENR: ENRL_PIN2 Position */
-#define PININT_IENR_ENRL_PIN2_Msk (0x01UL << PININT_IENR_ENRL_PIN2_Pos) /*!< PININT IENR: ENRL_PIN2 Mask */
-#define PININT_IENR_ENRL_PIN3_Pos 3 /*!< PININT IENR: ENRL_PIN3 Position */
-#define PININT_IENR_ENRL_PIN3_Msk (0x01UL << PININT_IENR_ENRL_PIN3_Pos) /*!< PININT IENR: ENRL_PIN3 Mask */
-#define PININT_IENR_ENRL_PIN4_Pos 4 /*!< PININT IENR: ENRL_PIN4 Position */
-#define PININT_IENR_ENRL_PIN4_Msk (0x01UL << PININT_IENR_ENRL_PIN4_Pos) /*!< PININT IENR: ENRL_PIN4 Mask */
-#define PININT_IENR_ENRL_PIN5_Pos 5 /*!< PININT IENR: ENRL_PIN5 Position */
-#define PININT_IENR_ENRL_PIN5_Msk (0x01UL << PININT_IENR_ENRL_PIN5_Pos) /*!< PININT IENR: ENRL_PIN5 Mask */
-#define PININT_IENR_ENRL_PIN6_Pos 6 /*!< PININT IENR: ENRL_PIN6 Position */
-#define PININT_IENR_ENRL_PIN6_Msk (0x01UL << PININT_IENR_ENRL_PIN6_Pos) /*!< PININT IENR: ENRL_PIN6 Mask */
-#define PININT_IENR_ENRL_PIN7_Pos 7 /*!< PININT IENR: ENRL_PIN7 Position */
-#define PININT_IENR_ENRL_PIN7_Msk (0x01UL << PININT_IENR_ENRL_PIN7_Pos) /*!< PININT IENR: ENRL_PIN7 Mask */
-
-/* -------------------------------- u_pint_SIENR -------------------------------- */
-#define PININT_SIENR_SETENRL_PIN0_Pos 0 /*!< PININT SIENR: SETENRL_PIN0 Position */
-#define PININT_SIENR_SETENRL_PIN0_Msk (0x01UL << PININT_SIENR_SETENRL_PIN0_Pos) /*!< PININT SIENR: SETENRL_PIN0 Mask */
-#define PININT_SIENR_SETENRL_PIN1_Pos 1 /*!< PININT SIENR: SETENRL_PIN1 Position */
-#define PININT_SIENR_SETENRL_PIN1_Msk (0x01UL << PININT_SIENR_SETENRL_PIN1_Pos) /*!< PININT SIENR: SETENRL_PIN1 Mask */
-#define PININT_SIENR_SETENRL_PIN2_Pos 2 /*!< PININT SIENR: SETENRL_PIN2 Position */
-#define PININT_SIENR_SETENRL_PIN2_Msk (0x01UL << PININT_SIENR_SETENRL_PIN2_Pos) /*!< PININT SIENR: SETENRL_PIN2 Mask */
-#define PININT_SIENR_SETENRL_PIN3_Pos 3 /*!< PININT SIENR: SETENRL_PIN3 Position */
-#define PININT_SIENR_SETENRL_PIN3_Msk (0x01UL << PININT_SIENR_SETENRL_PIN3_Pos) /*!< PININT SIENR: SETENRL_PIN3 Mask */
-#define PININT_SIENR_SETENRL_PIN4_Pos 4 /*!< PININT SIENR: SETENRL_PIN4 Position */
-#define PININT_SIENR_SETENRL_PIN4_Msk (0x01UL << PININT_SIENR_SETENRL_PIN4_Pos) /*!< PININT SIENR: SETENRL_PIN4 Mask */
-#define PININT_SIENR_SETENRL_PIN5_Pos 5 /*!< PININT SIENR: SETENRL_PIN5 Position */
-#define PININT_SIENR_SETENRL_PIN5_Msk (0x01UL << PININT_SIENR_SETENRL_PIN5_Pos) /*!< PININT SIENR: SETENRL_PIN5 Mask */
-#define PININT_SIENR_SETENRL_PIN6_Pos 6 /*!< PININT SIENR: SETENRL_PIN6 Position */
-#define PININT_SIENR_SETENRL_PIN6_Msk (0x01UL << PININT_SIENR_SETENRL_PIN6_Pos) /*!< PININT SIENR: SETENRL_PIN6 Mask */
-#define PININT_SIENR_SETENRL_PIN7_Pos 7 /*!< PININT SIENR: SETENRL_PIN7 Position */
-#define PININT_SIENR_SETENRL_PIN7_Msk (0x01UL << PININT_SIENR_SETENRL_PIN7_Pos) /*!< PININT SIENR: SETENRL_PIN7 Mask */
-
-/* -------------------------------- u_pint_CIENR -------------------------------- */
-#define PININT_CIENR_CLRENRL_PIN0_Pos 0 /*!< PININT CIENR: CLRENRL_PIN0 Position */
-#define PININT_CIENR_CLRENRL_PIN0_Msk (0x01UL << PININT_CIENR_CLRENRL_PIN0_Pos) /*!< PININT CIENR: CLRENRL_PIN0 Mask */
-#define PININT_CIENR_CLRENRL_PIN1_Pos 1 /*!< PININT CIENR: CLRENRL_PIN1 Position */
-#define PININT_CIENR_CLRENRL_PIN1_Msk (0x01UL << PININT_CIENR_CLRENRL_PIN1_Pos) /*!< PININT CIENR: CLRENRL_PIN1 Mask */
-#define PININT_CIENR_CLRENRL_PIN2_Pos 2 /*!< PININT CIENR: CLRENRL_PIN2 Position */
-#define PININT_CIENR_CLRENRL_PIN2_Msk (0x01UL << PININT_CIENR_CLRENRL_PIN2_Pos) /*!< PININT CIENR: CLRENRL_PIN2 Mask */
-#define PININT_CIENR_CLRENRL_PIN3_Pos 3 /*!< PININT CIENR: CLRENRL_PIN3 Position */
-#define PININT_CIENR_CLRENRL_PIN3_Msk (0x01UL << PININT_CIENR_CLRENRL_PIN3_Pos) /*!< PININT CIENR: CLRENRL_PIN3 Mask */
-#define PININT_CIENR_CLRENRL_PIN4_Pos 4 /*!< PININT CIENR: CLRENRL_PIN4 Position */
-#define PININT_CIENR_CLRENRL_PIN4_Msk (0x01UL << PININT_CIENR_CLRENRL_PIN4_Pos) /*!< PININT CIENR: CLRENRL_PIN4 Mask */
-#define PININT_CIENR_CLRENRL_PIN5_Pos 5 /*!< PININT CIENR: CLRENRL_PIN5 Position */
-#define PININT_CIENR_CLRENRL_PIN5_Msk (0x01UL << PININT_CIENR_CLRENRL_PIN5_Pos) /*!< PININT CIENR: CLRENRL_PIN5 Mask */
-#define PININT_CIENR_CLRENRL_PIN6_Pos 6 /*!< PININT CIENR: CLRENRL_PIN6 Position */
-#define PININT_CIENR_CLRENRL_PIN6_Msk (0x01UL << PININT_CIENR_CLRENRL_PIN6_Pos) /*!< PININT CIENR: CLRENRL_PIN6 Mask */
-#define PININT_CIENR_CLRENRL_PIN7_Pos 7 /*!< PININT CIENR: CLRENRL_PIN7 Position */
-#define PININT_CIENR_CLRENRL_PIN7_Msk (0x01UL << PININT_CIENR_CLRENRL_PIN7_Pos) /*!< PININT CIENR: CLRENRL_PIN7 Mask */
-
-/* --------------------------------- u_pint_IENF -------------------------------- */
-#define PININT_IENF_ENAF_PIN0_Pos 0 /*!< PININT IENF: ENAF_PIN0 Position */
-#define PININT_IENF_ENAF_PIN0_Msk (0x01UL << PININT_IENF_ENAF_PIN0_Pos) /*!< PININT IENF: ENAF_PIN0 Mask */
-#define PININT_IENF_ENAF_PIN1_Pos 1 /*!< PININT IENF: ENAF_PIN1 Position */
-#define PININT_IENF_ENAF_PIN1_Msk (0x01UL << PININT_IENF_ENAF_PIN1_Pos) /*!< PININT IENF: ENAF_PIN1 Mask */
-#define PININT_IENF_ENAF_PIN2_Pos 2 /*!< PININT IENF: ENAF_PIN2 Position */
-#define PININT_IENF_ENAF_PIN2_Msk (0x01UL << PININT_IENF_ENAF_PIN2_Pos) /*!< PININT IENF: ENAF_PIN2 Mask */
-#define PININT_IENF_ENAF_PIN3_Pos 3 /*!< PININT IENF: ENAF_PIN3 Position */
-#define PININT_IENF_ENAF_PIN3_Msk (0x01UL << PININT_IENF_ENAF_PIN3_Pos) /*!< PININT IENF: ENAF_PIN3 Mask */
-#define PININT_IENF_ENAF_PIN4_Pos 4 /*!< PININT IENF: ENAF_PIN4 Position */
-#define PININT_IENF_ENAF_PIN4_Msk (0x01UL << PININT_IENF_ENAF_PIN4_Pos) /*!< PININT IENF: ENAF_PIN4 Mask */
-#define PININT_IENF_ENAF_PIN5_Pos 5 /*!< PININT IENF: ENAF_PIN5 Position */
-#define PININT_IENF_ENAF_PIN5_Msk (0x01UL << PININT_IENF_ENAF_PIN5_Pos) /*!< PININT IENF: ENAF_PIN5 Mask */
-#define PININT_IENF_ENAF_PIN6_Pos 6 /*!< PININT IENF: ENAF_PIN6 Position */
-#define PININT_IENF_ENAF_PIN6_Msk (0x01UL << PININT_IENF_ENAF_PIN6_Pos) /*!< PININT IENF: ENAF_PIN6 Mask */
-#define PININT_IENF_ENAF_PIN7_Pos 7 /*!< PININT IENF: ENAF_PIN7 Position */
-#define PININT_IENF_ENAF_PIN7_Msk (0x01UL << PININT_IENF_ENAF_PIN7_Pos) /*!< PININT IENF: ENAF_PIN7 Mask */
-
-/* -------------------------------- u_pint_SIENF -------------------------------- */
-#define PININT_SIENF_SETENAF_PIN0_Pos 0 /*!< PININT SIENF: SETENAF_PIN0 Position */
-#define PININT_SIENF_SETENAF_PIN0_Msk (0x01UL << PININT_SIENF_SETENAF_PIN0_Pos) /*!< PININT SIENF: SETENAF_PIN0 Mask */
-#define PININT_SIENF_SETENAF_PIN1_Pos 1 /*!< PININT SIENF: SETENAF_PIN1 Position */
-#define PININT_SIENF_SETENAF_PIN1_Msk (0x01UL << PININT_SIENF_SETENAF_PIN1_Pos) /*!< PININT SIENF: SETENAF_PIN1 Mask */
-#define PININT_SIENF_SETENAF_PIN2_Pos 2 /*!< PININT SIENF: SETENAF_PIN2 Position */
-#define PININT_SIENF_SETENAF_PIN2_Msk (0x01UL << PININT_SIENF_SETENAF_PIN2_Pos) /*!< PININT SIENF: SETENAF_PIN2 Mask */
-#define PININT_SIENF_SETENAF_PIN3_Pos 3 /*!< PININT SIENF: SETENAF_PIN3 Position */
-#define PININT_SIENF_SETENAF_PIN3_Msk (0x01UL << PININT_SIENF_SETENAF_PIN3_Pos) /*!< PININT SIENF: SETENAF_PIN3 Mask */
-#define PININT_SIENF_SETENAF_PIN4_Pos 4 /*!< PININT SIENF: SETENAF_PIN4 Position */
-#define PININT_SIENF_SETENAF_PIN4_Msk (0x01UL << PININT_SIENF_SETENAF_PIN4_Pos) /*!< PININT SIENF: SETENAF_PIN4 Mask */
-#define PININT_SIENF_SETENAF_PIN5_Pos 5 /*!< PININT SIENF: SETENAF_PIN5 Position */
-#define PININT_SIENF_SETENAF_PIN5_Msk (0x01UL << PININT_SIENF_SETENAF_PIN5_Pos) /*!< PININT SIENF: SETENAF_PIN5 Mask */
-#define PININT_SIENF_SETENAF_PIN6_Pos 6 /*!< PININT SIENF: SETENAF_PIN6 Position */
-#define PININT_SIENF_SETENAF_PIN6_Msk (0x01UL << PININT_SIENF_SETENAF_PIN6_Pos) /*!< PININT SIENF: SETENAF_PIN6 Mask */
-#define PININT_SIENF_SETENAF_PIN7_Pos 7 /*!< PININT SIENF: SETENAF_PIN7 Position */
-#define PININT_SIENF_SETENAF_PIN7_Msk (0x01UL << PININT_SIENF_SETENAF_PIN7_Pos) /*!< PININT SIENF: SETENAF_PIN7 Mask */
-
-/* -------------------------------- u_pint_CIENF -------------------------------- */
-#define PININT_CIENF_CLRENAF_PIN0_Pos 0 /*!< PININT CIENF: CLRENAF_PIN0 Position */
-#define PININT_CIENF_CLRENAF_PIN0_Msk (0x01UL << PININT_CIENF_CLRENAF_PIN0_Pos) /*!< PININT CIENF: CLRENAF_PIN0 Mask */
-#define PININT_CIENF_CLRENAF_PIN1_Pos 1 /*!< PININT CIENF: CLRENAF_PIN1 Position */
-#define PININT_CIENF_CLRENAF_PIN1_Msk (0x01UL << PININT_CIENF_CLRENAF_PIN1_Pos) /*!< PININT CIENF: CLRENAF_PIN1 Mask */
-#define PININT_CIENF_CLRENAF_PIN2_Pos 2 /*!< PININT CIENF: CLRENAF_PIN2 Position */
-#define PININT_CIENF_CLRENAF_PIN2_Msk (0x01UL << PININT_CIENF_CLRENAF_PIN2_Pos) /*!< PININT CIENF: CLRENAF_PIN2 Mask */
-#define PININT_CIENF_CLRENAF_PIN3_Pos 3 /*!< PININT CIENF: CLRENAF_PIN3 Position */
-#define PININT_CIENF_CLRENAF_PIN3_Msk (0x01UL << PININT_CIENF_CLRENAF_PIN3_Pos) /*!< PININT CIENF: CLRENAF_PIN3 Mask */
-#define PININT_CIENF_CLRENAF_PIN4_Pos 4 /*!< PININT CIENF: CLRENAF_PIN4 Position */
-#define PININT_CIENF_CLRENAF_PIN4_Msk (0x01UL << PININT_CIENF_CLRENAF_PIN4_Pos) /*!< PININT CIENF: CLRENAF_PIN4 Mask */
-#define PININT_CIENF_CLRENAF_PIN5_Pos 5 /*!< PININT CIENF: CLRENAF_PIN5 Position */
-#define PININT_CIENF_CLRENAF_PIN5_Msk (0x01UL << PININT_CIENF_CLRENAF_PIN5_Pos) /*!< PININT CIENF: CLRENAF_PIN5 Mask */
-#define PININT_CIENF_CLRENAF_PIN6_Pos 6 /*!< PININT CIENF: CLRENAF_PIN6 Position */
-#define PININT_CIENF_CLRENAF_PIN6_Msk (0x01UL << PININT_CIENF_CLRENAF_PIN6_Pos) /*!< PININT CIENF: CLRENAF_PIN6 Mask */
-#define PININT_CIENF_CLRENAF_PIN7_Pos 7 /*!< PININT CIENF: CLRENAF_PIN7 Position */
-#define PININT_CIENF_CLRENAF_PIN7_Msk (0x01UL << PININT_CIENF_CLRENAF_PIN7_Pos) /*!< PININT CIENF: CLRENAF_PIN7 Mask */
-
-/* --------------------------------- u_pint_RISE -------------------------------- */
-#define PININT_RISE_RDET_PIN0_Pos 0 /*!< PININT RISE: RDET_PIN0 Position */
-#define PININT_RISE_RDET_PIN0_Msk (0x01UL << PININT_RISE_RDET_PIN0_Pos) /*!< PININT RISE: RDET_PIN0 Mask */
-#define PININT_RISE_RDET_PIN1_Pos 1 /*!< PININT RISE: RDET_PIN1 Position */
-#define PININT_RISE_RDET_PIN1_Msk (0x01UL << PININT_RISE_RDET_PIN1_Pos) /*!< PININT RISE: RDET_PIN1 Mask */
-#define PININT_RISE_RDET_PIN2_Pos 2 /*!< PININT RISE: RDET_PIN2 Position */
-#define PININT_RISE_RDET_PIN2_Msk (0x01UL << PININT_RISE_RDET_PIN2_Pos) /*!< PININT RISE: RDET_PIN2 Mask */
-#define PININT_RISE_RDET_PIN3_Pos 3 /*!< PININT RISE: RDET_PIN3 Position */
-#define PININT_RISE_RDET_PIN3_Msk (0x01UL << PININT_RISE_RDET_PIN3_Pos) /*!< PININT RISE: RDET_PIN3 Mask */
-#define PININT_RISE_RDET_PIN4_Pos 4 /*!< PININT RISE: RDET_PIN4 Position */
-#define PININT_RISE_RDET_PIN4_Msk (0x01UL << PININT_RISE_RDET_PIN4_Pos) /*!< PININT RISE: RDET_PIN4 Mask */
-#define PININT_RISE_RDET_PIN5_Pos 5 /*!< PININT RISE: RDET_PIN5 Position */
-#define PININT_RISE_RDET_PIN5_Msk (0x01UL << PININT_RISE_RDET_PIN5_Pos) /*!< PININT RISE: RDET_PIN5 Mask */
-#define PININT_RISE_RDET_PIN6_Pos 6 /*!< PININT RISE: RDET_PIN6 Position */
-#define PININT_RISE_RDET_PIN6_Msk (0x01UL << PININT_RISE_RDET_PIN6_Pos) /*!< PININT RISE: RDET_PIN6 Mask */
-#define PININT_RISE_RDET_PIN7_Pos 7 /*!< PININT RISE: RDET_PIN7 Position */
-#define PININT_RISE_RDET_PIN7_Msk (0x01UL << PININT_RISE_RDET_PIN7_Pos) /*!< PININT RISE: RDET_PIN7 Mask */
-
-/* --------------------------------- u_pint_FALL -------------------------------- */
-#define PININT_FALL_FDET_PIN0_Pos 0 /*!< PININT FALL: FDET_PIN0 Position */
-#define PININT_FALL_FDET_PIN0_Msk (0x01UL << PININT_FALL_FDET_PIN0_Pos) /*!< PININT FALL: FDET_PIN0 Mask */
-#define PININT_FALL_FDET_PIN1_Pos 1 /*!< PININT FALL: FDET_PIN1 Position */
-#define PININT_FALL_FDET_PIN1_Msk (0x01UL << PININT_FALL_FDET_PIN1_Pos) /*!< PININT FALL: FDET_PIN1 Mask */
-#define PININT_FALL_FDET_PIN2_Pos 2 /*!< PININT FALL: FDET_PIN2 Position */
-#define PININT_FALL_FDET_PIN2_Msk (0x01UL << PININT_FALL_FDET_PIN2_Pos) /*!< PININT FALL: FDET_PIN2 Mask */
-#define PININT_FALL_FDET_PIN3_Pos 3 /*!< PININT FALL: FDET_PIN3 Position */
-#define PININT_FALL_FDET_PIN3_Msk (0x01UL << PININT_FALL_FDET_PIN3_Pos) /*!< PININT FALL: FDET_PIN3 Mask */
-#define PININT_FALL_FDET_PIN4_Pos 4 /*!< PININT FALL: FDET_PIN4 Position */
-#define PININT_FALL_FDET_PIN4_Msk (0x01UL << PININT_FALL_FDET_PIN4_Pos) /*!< PININT FALL: FDET_PIN4 Mask */
-#define PININT_FALL_FDET_PIN5_Pos 5 /*!< PININT FALL: FDET_PIN5 Position */
-#define PININT_FALL_FDET_PIN5_Msk (0x01UL << PININT_FALL_FDET_PIN5_Pos) /*!< PININT FALL: FDET_PIN5 Mask */
-#define PININT_FALL_FDET_PIN6_Pos 6 /*!< PININT FALL: FDET_PIN6 Position */
-#define PININT_FALL_FDET_PIN6_Msk (0x01UL << PININT_FALL_FDET_PIN6_Pos) /*!< PININT FALL: FDET_PIN6 Mask */
-#define PININT_FALL_FDET_PIN7_Pos 7 /*!< PININT FALL: FDET_PIN7 Position */
-#define PININT_FALL_FDET_PIN7_Msk (0x01UL << PININT_FALL_FDET_PIN7_Pos) /*!< PININT FALL: FDET_PIN7 Mask */
-
-/* --------------------------------- u_pint_IST --------------------------------- */
-#define PININT_IST_PSTAT_PIN0_Pos 0 /*!< PININT IST: PSTAT_PIN0 Position */
-#define PININT_IST_PSTAT_PIN0_Msk (0x01UL << PININT_IST_PSTAT_PIN0_Pos) /*!< PININT IST: PSTAT_PIN0 Mask */
-#define PININT_IST_PSTAT_PIN1_Pos 1 /*!< PININT IST: PSTAT_PIN1 Position */
-#define PININT_IST_PSTAT_PIN1_Msk (0x01UL << PININT_IST_PSTAT_PIN1_Pos) /*!< PININT IST: PSTAT_PIN1 Mask */
-#define PININT_IST_PSTAT_PIN2_Pos 2 /*!< PININT IST: PSTAT_PIN2 Position */
-#define PININT_IST_PSTAT_PIN2_Msk (0x01UL << PININT_IST_PSTAT_PIN2_Pos) /*!< PININT IST: PSTAT_PIN2 Mask */
-#define PININT_IST_PSTAT_PIN3_Pos 3 /*!< PININT IST: PSTAT_PIN3 Position */
-#define PININT_IST_PSTAT_PIN3_Msk (0x01UL << PININT_IST_PSTAT_PIN3_Pos) /*!< PININT IST: PSTAT_PIN3 Mask */
-#define PININT_IST_PSTAT_PIN4_Pos 4 /*!< PININT IST: PSTAT_PIN4 Position */
-#define PININT_IST_PSTAT_PIN4_Msk (0x01UL << PININT_IST_PSTAT_PIN4_Pos) /*!< PININT IST: PSTAT_PIN4 Mask */
-#define PININT_IST_PSTAT_PIN5_Pos 5 /*!< PININT IST: PSTAT_PIN5 Position */
-#define PININT_IST_PSTAT_PIN5_Msk (0x01UL << PININT_IST_PSTAT_PIN5_Pos) /*!< PININT IST: PSTAT_PIN5 Mask */
-#define PININT_IST_PSTAT_PIN6_Pos 6 /*!< PININT IST: PSTAT_PIN6 Position */
-#define PININT_IST_PSTAT_PIN6_Msk (0x01UL << PININT_IST_PSTAT_PIN6_Pos) /*!< PININT IST: PSTAT_PIN6 Mask */
-#define PININT_IST_PSTAT_PIN7_Pos 7 /*!< PININT IST: PSTAT_PIN7 Position */
-#define PININT_IST_PSTAT_PIN7_Msk (0x01UL << PININT_IST_PSTAT_PIN7_Pos) /*!< PININT IST: PSTAT_PIN7 Mask */
-
-/* -------------------------------- u_pint_PMCTRL ------------------------------- */
-#define PININT_PMCTRL_SEL_PMATCH_Pos 0 /*!< PININT PMCTRL: SEL_PMATCH Position */
-#define PININT_PMCTRL_SEL_PMATCH_Msk (0x01UL << PININT_PMCTRL_SEL_PMATCH_Pos) /*!< PININT PMCTRL: SEL_PMATCH Mask */
-#define PININT_PMCTRL_ENA_RXEV_Pos 1 /*!< PININT PMCTRL: ENA_RXEV Position */
-#define PININT_PMCTRL_ENA_RXEV_Msk (0x01UL << PININT_PMCTRL_ENA_RXEV_Pos) /*!< PININT PMCTRL: ENA_RXEV Mask */
-#define PININT_PMCTRL_PMAT_Pos 24 /*!< PININT PMCTRL: PMAT Position */
-#define PININT_PMCTRL_PMAT_Msk (0x000000ffUL << PININT_PMCTRL_PMAT_Pos) /*!< PININT PMCTRL: PMAT Mask */
-
-/* -------------------------------- u_pint_PMSRC -------------------------------- */
-#define PININT_PMSRC_SRC0_Pos 8 /*!< PININT PMSRC: SRC0 Position */
-#define PININT_PMSRC_SRC0_Msk (0x07UL << PININT_PMSRC_SRC0_Pos) /*!< PININT PMSRC: SRC0 Mask */
-#define PININT_PMSRC_SRC1_Pos 11 /*!< PININT PMSRC: SRC1 Position */
-#define PININT_PMSRC_SRC1_Msk (0x07UL << PININT_PMSRC_SRC1_Pos) /*!< PININT PMSRC: SRC1 Mask */
-#define PININT_PMSRC_SRC2_Pos 14 /*!< PININT PMSRC: SRC2 Position */
-#define PININT_PMSRC_SRC2_Msk (0x07UL << PININT_PMSRC_SRC2_Pos) /*!< PININT PMSRC: SRC2 Mask */
-#define PININT_PMSRC_SRC3_Pos 17 /*!< PININT PMSRC: SRC3 Position */
-#define PININT_PMSRC_SRC3_Msk (0x07UL << PININT_PMSRC_SRC3_Pos) /*!< PININT PMSRC: SRC3 Mask */
-#define PININT_PMSRC_SRC4_Pos 20 /*!< PININT PMSRC: SRC4 Position */
-#define PININT_PMSRC_SRC4_Msk (0x07UL << PININT_PMSRC_SRC4_Pos) /*!< PININT PMSRC: SRC4 Mask */
-#define PININT_PMSRC_SRC5_Pos 23 /*!< PININT PMSRC: SRC5 Position */
-#define PININT_PMSRC_SRC5_Msk (0x07UL << PININT_PMSRC_SRC5_Pos) /*!< PININT PMSRC: SRC5 Mask */
-#define PININT_PMSRC_SRC6_Pos 26 /*!< PININT PMSRC: SRC6 Position */
-#define PININT_PMSRC_SRC6_Msk (0x07UL << PININT_PMSRC_SRC6_Pos) /*!< PININT PMSRC: SRC6 Mask */
-#define PININT_PMSRC_SRC7_Pos 29 /*!< PININT PMSRC: SRC7 Position */
-#define PININT_PMSRC_SRC7_Msk (0x07UL << PININT_PMSRC_SRC7_Pos) /*!< PININT PMSRC: SRC7 Mask */
-
-/* -------------------------------- u_pint_PMCFG -------------------------------- */
-#define PININT_PMCFG_PROD_ENDPTS0_Pos 0 /*!< PININT PMCFG: PROD_ENDPTS0 Position */
-#define PININT_PMCFG_PROD_ENDPTS0_Msk (0x01UL << PININT_PMCFG_PROD_ENDPTS0_Pos) /*!< PININT PMCFG: PROD_ENDPTS0 Mask */
-#define PININT_PMCFG_PROD_ENDPTS1_Pos 1 /*!< PININT PMCFG: PROD_ENDPTS1 Position */
-#define PININT_PMCFG_PROD_ENDPTS1_Msk (0x01UL << PININT_PMCFG_PROD_ENDPTS1_Pos) /*!< PININT PMCFG: PROD_ENDPTS1 Mask */
-#define PININT_PMCFG_PROD_ENDPTS2_Pos 2 /*!< PININT PMCFG: PROD_ENDPTS2 Position */
-#define PININT_PMCFG_PROD_ENDPTS2_Msk (0x01UL << PININT_PMCFG_PROD_ENDPTS2_Pos) /*!< PININT PMCFG: PROD_ENDPTS2 Mask */
-#define PININT_PMCFG_PROD_ENDPTS3_Pos 3 /*!< PININT PMCFG: PROD_ENDPTS3 Position */
-#define PININT_PMCFG_PROD_ENDPTS3_Msk (0x01UL << PININT_PMCFG_PROD_ENDPTS3_Pos) /*!< PININT PMCFG: PROD_ENDPTS3 Mask */
-#define PININT_PMCFG_PROD_ENDPTS4_Pos 4 /*!< PININT PMCFG: PROD_ENDPTS4 Position */
-#define PININT_PMCFG_PROD_ENDPTS4_Msk (0x01UL << PININT_PMCFG_PROD_ENDPTS4_Pos) /*!< PININT PMCFG: PROD_ENDPTS4 Mask */
-#define PININT_PMCFG_PROD_ENDPTS5_Pos 5 /*!< PININT PMCFG: PROD_ENDPTS5 Position */
-#define PININT_PMCFG_PROD_ENDPTS5_Msk (0x01UL << PININT_PMCFG_PROD_ENDPTS5_Pos) /*!< PININT PMCFG: PROD_ENDPTS5 Mask */
-#define PININT_PMCFG_PROD_ENDPTS6_Pos 6 /*!< PININT PMCFG: PROD_ENDPTS6 Position */
-#define PININT_PMCFG_PROD_ENDPTS6_Msk (0x01UL << PININT_PMCFG_PROD_ENDPTS6_Pos) /*!< PININT PMCFG: PROD_ENDPTS6 Mask */
-#define PININT_PMCFG_CFG0_Pos 8 /*!< PININT PMCFG: CFG0 Position */
-#define PININT_PMCFG_CFG0_Msk (0x07UL << PININT_PMCFG_CFG0_Pos) /*!< PININT PMCFG: CFG0 Mask */
-#define PININT_PMCFG_CFG1_Pos 11 /*!< PININT PMCFG: CFG1 Position */
-#define PININT_PMCFG_CFG1_Msk (0x07UL << PININT_PMCFG_CFG1_Pos) /*!< PININT PMCFG: CFG1 Mask */
-#define PININT_PMCFG_CFG2_Pos 14 /*!< PININT PMCFG: CFG2 Position */
-#define PININT_PMCFG_CFG2_Msk (0x07UL << PININT_PMCFG_CFG2_Pos) /*!< PININT PMCFG: CFG2 Mask */
-#define PININT_PMCFG_CFG3_Pos 17 /*!< PININT PMCFG: CFG3 Position */
-#define PININT_PMCFG_CFG3_Msk (0x07UL << PININT_PMCFG_CFG3_Pos) /*!< PININT PMCFG: CFG3 Mask */
-#define PININT_PMCFG_CFG4_Pos 20 /*!< PININT PMCFG: CFG4 Position */
-#define PININT_PMCFG_CFG4_Msk (0x07UL << PININT_PMCFG_CFG4_Pos) /*!< PININT PMCFG: CFG4 Mask */
-#define PININT_PMCFG_CFG5_Pos 23 /*!< PININT PMCFG: CFG5 Position */
-#define PININT_PMCFG_CFG5_Msk (0x07UL << PININT_PMCFG_CFG5_Pos) /*!< PININT PMCFG: CFG5 Mask */
-#define PININT_PMCFG_CFG6_Pos 26 /*!< PININT PMCFG: CFG6 Position */
-#define PININT_PMCFG_CFG6_Msk (0x07UL << PININT_PMCFG_CFG6_Pos) /*!< PININT PMCFG: CFG6 Mask */
-#define PININT_PMCFG_CFG7_Pos 29 /*!< PININT PMCFG: CFG7 Position */
-#define PININT_PMCFG_CFG7_Msk (0x07UL << PININT_PMCFG_CFG7_Pos) /*!< PININT PMCFG: CFG7 Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u_gint' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* --------------------------------- u_gint_CTRL -------------------------------- */
-#define GPIOINT_CTRL_INT_Pos 0 /*!< GPIOINT CTRL: INT Position */
-#define GPIOINT_CTRL_INT_Msk (0x01UL << GPIOINT_CTRL_INT_Pos) /*!< GPIOINT CTRL: INT Mask */
-#define GPIOINT_CTRL_COMB_Pos 1 /*!< GPIOINT CTRL: COMB Position */
-#define GPIOINT_CTRL_COMB_Msk (0x01UL << GPIOINT_CTRL_COMB_Pos) /*!< GPIOINT CTRL: COMB Mask */
-#define GPIOINT_CTRL_TRIG_Pos 2 /*!< GPIOINT CTRL: TRIG Position */
-#define GPIOINT_CTRL_TRIG_Msk (0x01UL << GPIOINT_CTRL_TRIG_Pos) /*!< GPIOINT CTRL: TRIG Mask */
-
-/* ------------------------------ u_gint_PORT_POL0 ------------------------------ */
-#define GPIOINT_PORT_POL0_POL_PIO0_Pos 0 /*!< GPIOINT PORT_POL0: POL_PIO0 Position */
-#define GPIOINT_PORT_POL0_POL_PIO0_Msk (0x01UL << GPIOINT_PORT_POL0_POL_PIO0_Pos) /*!< GPIOINT PORT_POL0: POL_PIO0 Mask */
-#define GPIOINT_PORT_POL0_POL_PIO1_Pos 1 /*!< GPIOINT PORT_POL0: POL_PIO1 Position */
-#define GPIOINT_PORT_POL0_POL_PIO1_Msk (0x01UL << GPIOINT_PORT_POL0_POL_PIO1_Pos) /*!< GPIOINT PORT_POL0: POL_PIO1 Mask */
-#define GPIOINT_PORT_POL0_POL_PIO2_Pos 2 /*!< GPIOINT PORT_POL0: POL_PIO2 Position */
-#define GPIOINT_PORT_POL0_POL_PIO2_Msk (0x01UL << GPIOINT_PORT_POL0_POL_PIO2_Pos) /*!< GPIOINT PORT_POL0: POL_PIO2 Mask */
-#define GPIOINT_PORT_POL0_POL_PIO3_Pos 3 /*!< GPIOINT PORT_POL0: POL_PIO3 Position */
-#define GPIOINT_PORT_POL0_POL_PIO3_Msk (0x01UL << GPIOINT_PORT_POL0_POL_PIO3_Pos) /*!< GPIOINT PORT_POL0: POL_PIO3 Mask */
-#define GPIOINT_PORT_POL0_POL_PIO4_Pos 4 /*!< GPIOINT PORT_POL0: POL_PIO4 Position */
-#define GPIOINT_PORT_POL0_POL_PIO4_Msk (0x01UL << GPIOINT_PORT_POL0_POL_PIO4_Pos) /*!< GPIOINT PORT_POL0: POL_PIO4 Mask */
-#define GPIOINT_PORT_POL0_POL_PIO5_Pos 5 /*!< GPIOINT PORT_POL0: POL_PIO5 Position */
-#define GPIOINT_PORT_POL0_POL_PIO5_Msk (0x01UL << GPIOINT_PORT_POL0_POL_PIO5_Pos) /*!< GPIOINT PORT_POL0: POL_PIO5 Mask */
-#define GPIOINT_PORT_POL0_POL_PIO6_Pos 6 /*!< GPIOINT PORT_POL0: POL_PIO6 Position */
-#define GPIOINT_PORT_POL0_POL_PIO6_Msk (0x01UL << GPIOINT_PORT_POL0_POL_PIO6_Pos) /*!< GPIOINT PORT_POL0: POL_PIO6 Mask */
-#define GPIOINT_PORT_POL0_POL_PIO7_Pos 7 /*!< GPIOINT PORT_POL0: POL_PIO7 Position */
-#define GPIOINT_PORT_POL0_POL_PIO7_Msk (0x01UL << GPIOINT_PORT_POL0_POL_PIO7_Pos) /*!< GPIOINT PORT_POL0: POL_PIO7 Mask */
-#define GPIOINT_PORT_POL0_POL_PIO8_Pos 8 /*!< GPIOINT PORT_POL0: POL_PIO8 Position */
-#define GPIOINT_PORT_POL0_POL_PIO8_Msk (0x01UL << GPIOINT_PORT_POL0_POL_PIO8_Pos) /*!< GPIOINT PORT_POL0: POL_PIO8 Mask */
-#define GPIOINT_PORT_POL0_POL_PIO9_Pos 9 /*!< GPIOINT PORT_POL0: POL_PIO9 Position */
-#define GPIOINT_PORT_POL0_POL_PIO9_Msk (0x01UL << GPIOINT_PORT_POL0_POL_PIO9_Pos) /*!< GPIOINT PORT_POL0: POL_PIO9 Mask */
-#define GPIOINT_PORT_POL0_POL_PIO10_Pos 10 /*!< GPIOINT PORT_POL0: POL_PIO10 Position */
-#define GPIOINT_PORT_POL0_POL_PIO10_Msk (0x01UL << GPIOINT_PORT_POL0_POL_PIO10_Pos) /*!< GPIOINT PORT_POL0: POL_PIO10 Mask */
-#define GPIOINT_PORT_POL0_POL_PIO11_Pos 11 /*!< GPIOINT PORT_POL0: POL_PIO11 Position */
-#define GPIOINT_PORT_POL0_POL_PIO11_Msk (0x01UL << GPIOINT_PORT_POL0_POL_PIO11_Pos) /*!< GPIOINT PORT_POL0: POL_PIO11 Mask */
-#define GPIOINT_PORT_POL0_POL_PIO12_Pos 12 /*!< GPIOINT PORT_POL0: POL_PIO12 Position */
-#define GPIOINT_PORT_POL0_POL_PIO12_Msk (0x01UL << GPIOINT_PORT_POL0_POL_PIO12_Pos) /*!< GPIOINT PORT_POL0: POL_PIO12 Mask */
-#define GPIOINT_PORT_POL0_POL_PIO13_Pos 13 /*!< GPIOINT PORT_POL0: POL_PIO13 Position */
-#define GPIOINT_PORT_POL0_POL_PIO13_Msk (0x01UL << GPIOINT_PORT_POL0_POL_PIO13_Pos) /*!< GPIOINT PORT_POL0: POL_PIO13 Mask */
-#define GPIOINT_PORT_POL0_POL_PIO14_Pos 14 /*!< GPIOINT PORT_POL0: POL_PIO14 Position */
-#define GPIOINT_PORT_POL0_POL_PIO14_Msk (0x01UL << GPIOINT_PORT_POL0_POL_PIO14_Pos) /*!< GPIOINT PORT_POL0: POL_PIO14 Mask */
-#define GPIOINT_PORT_POL0_POL_PIO15_Pos 15 /*!< GPIOINT PORT_POL0: POL_PIO15 Position */
-#define GPIOINT_PORT_POL0_POL_PIO15_Msk (0x01UL << GPIOINT_PORT_POL0_POL_PIO15_Pos) /*!< GPIOINT PORT_POL0: POL_PIO15 Mask */
-#define GPIOINT_PORT_POL0_POL_PIO16_Pos 16 /*!< GPIOINT PORT_POL0: POL_PIO16 Position */
-#define GPIOINT_PORT_POL0_POL_PIO16_Msk (0x01UL << GPIOINT_PORT_POL0_POL_PIO16_Pos) /*!< GPIOINT PORT_POL0: POL_PIO16 Mask */
-#define GPIOINT_PORT_POL0_POL_PIO17_Pos 17 /*!< GPIOINT PORT_POL0: POL_PIO17 Position */
-#define GPIOINT_PORT_POL0_POL_PIO17_Msk (0x01UL << GPIOINT_PORT_POL0_POL_PIO17_Pos) /*!< GPIOINT PORT_POL0: POL_PIO17 Mask */
-#define GPIOINT_PORT_POL0_POL_PIO18_Pos 18 /*!< GPIOINT PORT_POL0: POL_PIO18 Position */
-#define GPIOINT_PORT_POL0_POL_PIO18_Msk (0x01UL << GPIOINT_PORT_POL0_POL_PIO18_Pos) /*!< GPIOINT PORT_POL0: POL_PIO18 Mask */
-#define GPIOINT_PORT_POL0_POL_PIO19_Pos 19 /*!< GPIOINT PORT_POL0: POL_PIO19 Position */
-#define GPIOINT_PORT_POL0_POL_PIO19_Msk (0x01UL << GPIOINT_PORT_POL0_POL_PIO19_Pos) /*!< GPIOINT PORT_POL0: POL_PIO19 Mask */
-#define GPIOINT_PORT_POL0_POL_PIO20_Pos 20 /*!< GPIOINT PORT_POL0: POL_PIO20 Position */
-#define GPIOINT_PORT_POL0_POL_PIO20_Msk (0x01UL << GPIOINT_PORT_POL0_POL_PIO20_Pos) /*!< GPIOINT PORT_POL0: POL_PIO20 Mask */
-#define GPIOINT_PORT_POL0_POL_PIO21_Pos 21 /*!< GPIOINT PORT_POL0: POL_PIO21 Position */
-#define GPIOINT_PORT_POL0_POL_PIO21_Msk (0x01UL << GPIOINT_PORT_POL0_POL_PIO21_Pos) /*!< GPIOINT PORT_POL0: POL_PIO21 Mask */
-
-/* ------------------------------ u_gint_PORT_ENA0 ------------------------------ */
-#define GPIOINT_PORT_ENA0_ENA_PIO0_Pos 0 /*!< GPIOINT PORT_ENA0: ENA_PIO0 Position */
-#define GPIOINT_PORT_ENA0_ENA_PIO0_Msk (0x01UL << GPIOINT_PORT_ENA0_ENA_PIO0_Pos) /*!< GPIOINT PORT_ENA0: ENA_PIO0 Mask */
-#define GPIOINT_PORT_ENA0_ENA_PIO1_Pos 1 /*!< GPIOINT PORT_ENA0: ENA_PIO1 Position */
-#define GPIOINT_PORT_ENA0_ENA_PIO1_Msk (0x01UL << GPIOINT_PORT_ENA0_ENA_PIO1_Pos) /*!< GPIOINT PORT_ENA0: ENA_PIO1 Mask */
-#define GPIOINT_PORT_ENA0_ENA_PIO2_Pos 2 /*!< GPIOINT PORT_ENA0: ENA_PIO2 Position */
-#define GPIOINT_PORT_ENA0_ENA_PIO2_Msk (0x01UL << GPIOINT_PORT_ENA0_ENA_PIO2_Pos) /*!< GPIOINT PORT_ENA0: ENA_PIO2 Mask */
-#define GPIOINT_PORT_ENA0_ENA_PIO3_Pos 3 /*!< GPIOINT PORT_ENA0: ENA_PIO3 Position */
-#define GPIOINT_PORT_ENA0_ENA_PIO3_Msk (0x01UL << GPIOINT_PORT_ENA0_ENA_PIO3_Pos) /*!< GPIOINT PORT_ENA0: ENA_PIO3 Mask */
-#define GPIOINT_PORT_ENA0_ENA_PIO4_Pos 4 /*!< GPIOINT PORT_ENA0: ENA_PIO4 Position */
-#define GPIOINT_PORT_ENA0_ENA_PIO4_Msk (0x01UL << GPIOINT_PORT_ENA0_ENA_PIO4_Pos) /*!< GPIOINT PORT_ENA0: ENA_PIO4 Mask */
-#define GPIOINT_PORT_ENA0_ENA_PIO5_Pos 5 /*!< GPIOINT PORT_ENA0: ENA_PIO5 Position */
-#define GPIOINT_PORT_ENA0_ENA_PIO5_Msk (0x01UL << GPIOINT_PORT_ENA0_ENA_PIO5_Pos) /*!< GPIOINT PORT_ENA0: ENA_PIO5 Mask */
-#define GPIOINT_PORT_ENA0_ENA_PIO6_Pos 6 /*!< GPIOINT PORT_ENA0: ENA_PIO6 Position */
-#define GPIOINT_PORT_ENA0_ENA_PIO6_Msk (0x01UL << GPIOINT_PORT_ENA0_ENA_PIO6_Pos) /*!< GPIOINT PORT_ENA0: ENA_PIO6 Mask */
-#define GPIOINT_PORT_ENA0_ENA_PIO7_Pos 7 /*!< GPIOINT PORT_ENA0: ENA_PIO7 Position */
-#define GPIOINT_PORT_ENA0_ENA_PIO7_Msk (0x01UL << GPIOINT_PORT_ENA0_ENA_PIO7_Pos) /*!< GPIOINT PORT_ENA0: ENA_PIO7 Mask */
-#define GPIOINT_PORT_ENA0_ENA_PIO8_Pos 8 /*!< GPIOINT PORT_ENA0: ENA_PIO8 Position */
-#define GPIOINT_PORT_ENA0_ENA_PIO8_Msk (0x01UL << GPIOINT_PORT_ENA0_ENA_PIO8_Pos) /*!< GPIOINT PORT_ENA0: ENA_PIO8 Mask */
-#define GPIOINT_PORT_ENA0_ENA_PIO9_Pos 9 /*!< GPIOINT PORT_ENA0: ENA_PIO9 Position */
-#define GPIOINT_PORT_ENA0_ENA_PIO9_Msk (0x01UL << GPIOINT_PORT_ENA0_ENA_PIO9_Pos) /*!< GPIOINT PORT_ENA0: ENA_PIO9 Mask */
-#define GPIOINT_PORT_ENA0_ENA_PIO10_Pos 10 /*!< GPIOINT PORT_ENA0: ENA_PIO10 Position */
-#define GPIOINT_PORT_ENA0_ENA_PIO10_Msk (0x01UL << GPIOINT_PORT_ENA0_ENA_PIO10_Pos) /*!< GPIOINT PORT_ENA0: ENA_PIO10 Mask */
-#define GPIOINT_PORT_ENA0_ENA_PIO11_Pos 11 /*!< GPIOINT PORT_ENA0: ENA_PIO11 Position */
-#define GPIOINT_PORT_ENA0_ENA_PIO11_Msk (0x01UL << GPIOINT_PORT_ENA0_ENA_PIO11_Pos) /*!< GPIOINT PORT_ENA0: ENA_PIO11 Mask */
-#define GPIOINT_PORT_ENA0_ENA_PIO12_Pos 12 /*!< GPIOINT PORT_ENA0: ENA_PIO12 Position */
-#define GPIOINT_PORT_ENA0_ENA_PIO12_Msk (0x01UL << GPIOINT_PORT_ENA0_ENA_PIO12_Pos) /*!< GPIOINT PORT_ENA0: ENA_PIO12 Mask */
-#define GPIOINT_PORT_ENA0_ENA_PIO13_Pos 13 /*!< GPIOINT PORT_ENA0: ENA_PIO13 Position */
-#define GPIOINT_PORT_ENA0_ENA_PIO13_Msk (0x01UL << GPIOINT_PORT_ENA0_ENA_PIO13_Pos) /*!< GPIOINT PORT_ENA0: ENA_PIO13 Mask */
-#define GPIOINT_PORT_ENA0_ENA_PIO14_Pos 14 /*!< GPIOINT PORT_ENA0: ENA_PIO14 Position */
-#define GPIOINT_PORT_ENA0_ENA_PIO14_Msk (0x01UL << GPIOINT_PORT_ENA0_ENA_PIO14_Pos) /*!< GPIOINT PORT_ENA0: ENA_PIO14 Mask */
-#define GPIOINT_PORT_ENA0_ENA_PIO15_Pos 15 /*!< GPIOINT PORT_ENA0: ENA_PIO15 Position */
-#define GPIOINT_PORT_ENA0_ENA_PIO15_Msk (0x01UL << GPIOINT_PORT_ENA0_ENA_PIO15_Pos) /*!< GPIOINT PORT_ENA0: ENA_PIO15 Mask */
-#define GPIOINT_PORT_ENA0_ENA_PIO16_Pos 16 /*!< GPIOINT PORT_ENA0: ENA_PIO16 Position */
-#define GPIOINT_PORT_ENA0_ENA_PIO16_Msk (0x01UL << GPIOINT_PORT_ENA0_ENA_PIO16_Pos) /*!< GPIOINT PORT_ENA0: ENA_PIO16 Mask */
-#define GPIOINT_PORT_ENA0_ENA_PIO17_Pos 17 /*!< GPIOINT PORT_ENA0: ENA_PIO17 Position */
-#define GPIOINT_PORT_ENA0_ENA_PIO17_Msk (0x01UL << GPIOINT_PORT_ENA0_ENA_PIO17_Pos) /*!< GPIOINT PORT_ENA0: ENA_PIO17 Mask */
-#define GPIOINT_PORT_ENA0_ENA_PIO18_Pos 18 /*!< GPIOINT PORT_ENA0: ENA_PIO18 Position */
-#define GPIOINT_PORT_ENA0_ENA_PIO18_Msk (0x01UL << GPIOINT_PORT_ENA0_ENA_PIO18_Pos) /*!< GPIOINT PORT_ENA0: ENA_PIO18 Mask */
-#define GPIOINT_PORT_ENA0_ENA_PIO19_Pos 19 /*!< GPIOINT PORT_ENA0: ENA_PIO19 Position */
-#define GPIOINT_PORT_ENA0_ENA_PIO19_Msk (0x01UL << GPIOINT_PORT_ENA0_ENA_PIO19_Pos) /*!< GPIOINT PORT_ENA0: ENA_PIO19 Mask */
-#define GPIOINT_PORT_ENA0_ENA_PIO20_Pos 20 /*!< GPIOINT PORT_ENA0: ENA_PIO20 Position */
-#define GPIOINT_PORT_ENA0_ENA_PIO20_Msk (0x01UL << GPIOINT_PORT_ENA0_ENA_PIO20_Pos) /*!< GPIOINT PORT_ENA0: ENA_PIO20 Mask */
-#define GPIOINT_PORT_ENA0_ENA_PIO21_Pos 21 /*!< GPIOINT PORT_ENA0: ENA_PIO21 Position */
-#define GPIOINT_PORT_ENA0_ENA_PIO21_Msk (0x01UL << GPIOINT_PORT_ENA0_ENA_PIO21_Pos) /*!< GPIOINT PORT_ENA0: ENA_PIO21 Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u_pmc' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* --------------------------------- u_pmc_CTRL --------------------------------- */
-#define PMC_CTRL_LPMODE_Pos 0 /*!< PMC CTRL: LPMODE Position */
-#define PMC_CTRL_LPMODE_Msk (0x03UL << PMC_CTRL_LPMODE_Pos) /*!< PMC CTRL: LPMODE Mask */
-#define PMC_CTRL_SYSTEMRESETENABLE_Pos 2 /*!< PMC CTRL: SYSTEMRESETENABLE Position */
-#define PMC_CTRL_SYSTEMRESETENABLE_Msk (0x01UL << PMC_CTRL_SYSTEMRESETENABLE_Pos) /*!< PMC CTRL: SYSTEMRESETENABLE Mask */
-#define PMC_CTRL_WDTRESETENABLE_Pos 3 /*!< PMC CTRL: WDTRESETENABLE Position */
-#define PMC_CTRL_WDTRESETENABLE_Msk (0x01UL << PMC_CTRL_WDTRESETENABLE_Pos) /*!< PMC CTRL: WDTRESETENABLE Mask */
-#define PMC_CTRL_WAKUPRESETENABLE_Pos 4 /*!< PMC CTRL: WAKUPRESETENABLE Position */
-#define PMC_CTRL_WAKUPRESETENABLE_Msk (0x01UL << PMC_CTRL_WAKUPRESETENABLE_Pos) /*!< PMC CTRL: WAKUPRESETENABLE Mask */
-#define PMC_CTRL_NTAGWAKUPRESETENABLE_Pos 5 /*!< PMC CTRL: NTAGWAKUPRESETENABLE Position */
-#define PMC_CTRL_NTAGWAKUPRESETENABLE_Msk (0x01UL << PMC_CTRL_NTAGWAKUPRESETENABLE_Pos) /*!< PMC CTRL: NTAGWAKUPRESETENABLE Mask */
-#define PMC_CTRL_RESERVED6_Pos 6 /*!< PMC CTRL: RESERVED6 Position */
-#define PMC_CTRL_RESERVED6_Msk (0x01UL << PMC_CTRL_RESERVED6_Pos) /*!< PMC CTRL: RESERVED6 Mask */
-#define PMC_CTRL_SELCLOCK_Pos 7 /*!< PMC CTRL: SELCLOCK Position */
-#define PMC_CTRL_SELCLOCK_Msk (0x01UL << PMC_CTRL_SELCLOCK_Pos) /*!< PMC CTRL: SELCLOCK Mask */
-#define PMC_CTRL_SELLDOVOLTAGE_Pos 8 /*!< PMC CTRL: SELLDOVOLTAGE Position */
-#define PMC_CTRL_SELLDOVOLTAGE_Msk (0x01UL << PMC_CTRL_SELLDOVOLTAGE_Pos) /*!< PMC CTRL: SELLDOVOLTAGE Mask */
-#define PMC_CTRL_SWRRESETENABLE_Pos 9 /*!< PMC CTRL: SWRRESETENABLE Position */
-#define PMC_CTRL_SWRRESETENABLE_Msk (0x01UL << PMC_CTRL_SWRRESETENABLE_Pos) /*!< PMC CTRL: SWRRESETENABLE Mask */
-
-/* --------------------------------- u_pmc_DCDC0 -------------------------------- */
-#define PMC_DCDC0_RC_Pos 0 /*!< PMC DCDC0: RC Position */
-#define PMC_DCDC0_RC_Msk (0x3fUL << PMC_DCDC0_RC_Pos) /*!< PMC DCDC0: RC Mask */
-#define PMC_DCDC0_ICOMP_Pos 6 /*!< PMC DCDC0: ICOMP Position */
-#define PMC_DCDC0_ICOMP_Msk (0x03UL << PMC_DCDC0_ICOMP_Pos) /*!< PMC DCDC0: ICOMP Mask */
-#define PMC_DCDC0_ISEL_Pos 8 /*!< PMC DCDC0: ISEL Position */
-#define PMC_DCDC0_ISEL_Msk (0x03UL << PMC_DCDC0_ISEL_Pos) /*!< PMC DCDC0: ISEL Mask */
-#define PMC_DCDC0_ICENABLE_Pos 10 /*!< PMC DCDC0: ICENABLE Position */
-#define PMC_DCDC0_ICENABLE_Msk (0x01UL << PMC_DCDC0_ICENABLE_Pos) /*!< PMC DCDC0: ICENABLE Mask */
-#define PMC_DCDC0_TMOS_Pos 11 /*!< PMC DCDC0: TMOS Position */
-#define PMC_DCDC0_TMOS_Msk (0x1fUL << PMC_DCDC0_TMOS_Pos) /*!< PMC DCDC0: TMOS Mask */
-#define PMC_DCDC0_DISABLEISENSE_Pos 16 /*!< PMC DCDC0: DISABLEISENSE Position */
-#define PMC_DCDC0_DISABLEISENSE_Msk (0x01UL << PMC_DCDC0_DISABLEISENSE_Pos) /*!< PMC DCDC0: DISABLEISENSE Mask */
-#define PMC_DCDC0_VOUT_Pos 17 /*!< PMC DCDC0: VOUT Position */
-#define PMC_DCDC0_VOUT_Msk (0x07UL << PMC_DCDC0_VOUT_Pos) /*!< PMC DCDC0: VOUT Mask */
-#define PMC_DCDC0_SLICINGENABLE_Pos 20 /*!< PMC DCDC0: SLICINGENABLE Position */
-#define PMC_DCDC0_SLICINGENABLE_Msk (0x01UL << PMC_DCDC0_SLICINGENABLE_Pos) /*!< PMC DCDC0: SLICINGENABLE Mask */
-#define PMC_DCDC0_SLICINGPMOS_Pos 21 /*!< PMC DCDC0: SLICINGPMOS Position */
-#define PMC_DCDC0_SLICINGPMOS_Msk (0x03UL << PMC_DCDC0_SLICINGPMOS_Pos) /*!< PMC DCDC0: SLICINGPMOS Mask */
-#define PMC_DCDC0_SLICINGNMOS_Pos 23 /*!< PMC DCDC0: SLICINGNMOS Position */
-#define PMC_DCDC0_SLICINGNMOS_Msk (0x03UL << PMC_DCDC0_SLICINGNMOS_Pos) /*!< PMC DCDC0: SLICINGNMOS Mask */
-#define PMC_DCDC0_INDUCTORCLAMPENABLE_Pos 25 /*!< PMC DCDC0: INDUCTORCLAMPENABLE Position */
-#define PMC_DCDC0_INDUCTORCLAMPENABLE_Msk (0x01UL << PMC_DCDC0_INDUCTORCLAMPENABLE_Pos) /*!< PMC DCDC0: INDUCTORCLAMPENABLE Mask */
-#define PMC_DCDC0_CONTINUOUSMODEENABLE_Pos 26 /*!< PMC DCDC0: CONTINUOUSMODEENABLE Position */
-#define PMC_DCDC0_CONTINUOUSMODEENABLE_Msk (0x01UL << PMC_DCDC0_CONTINUOUSMODEENABLE_Pos) /*!< PMC DCDC0: CONTINUOUSMODEENABLE Mask */
-
-/* --------------------------------- u_pmc_DCDC1 -------------------------------- */
-#define PMC_DCDC1_RTRIMOFFET_Pos 0 /*!< PMC DCDC1: RTRIMOFFET Position */
-#define PMC_DCDC1_RTRIMOFFET_Msk (0x0fUL << PMC_DCDC1_RTRIMOFFET_Pos) /*!< PMC DCDC1: RTRIMOFFET Mask */
-#define PMC_DCDC1_RSENSETRIM_Pos 4 /*!< PMC DCDC1: RSENSETRIM Position */
-#define PMC_DCDC1_RSENSETRIM_Msk (0x0fUL << PMC_DCDC1_RSENSETRIM_Pos) /*!< PMC DCDC1: RSENSETRIM Mask */
-#define PMC_DCDC1_USEEXTREF_Pos 8 /*!< PMC DCDC1: USEEXTREF Position */
-#define PMC_DCDC1_USEEXTREF_Msk (0x01UL << PMC_DCDC1_USEEXTREF_Pos) /*!< PMC DCDC1: USEEXTREF Mask */
-#define PMC_DCDC1_DTESTENABLE_Pos 9 /*!< PMC DCDC1: DTESTENABLE Position */
-#define PMC_DCDC1_DTESTENABLE_Msk (0x01UL << PMC_DCDC1_DTESTENABLE_Pos) /*!< PMC DCDC1: DTESTENABLE Mask */
-#define PMC_DCDC1_SETCURVE_Pos 10 /*!< PMC DCDC1: SETCURVE Position */
-#define PMC_DCDC1_SETCURVE_Msk (0x03UL << PMC_DCDC1_SETCURVE_Pos) /*!< PMC DCDC1: SETCURVE Mask */
-#define PMC_DCDC1_SETDC_Pos 12 /*!< PMC DCDC1: SETDC Position */
-#define PMC_DCDC1_SETDC_Msk (0x0fUL << PMC_DCDC1_SETDC_Pos) /*!< PMC DCDC1: SETDC Mask */
-#define PMC_DCDC1_DTESTSEL_Pos 16 /*!< PMC DCDC1: DTESTSEL Position */
-#define PMC_DCDC1_DTESTSEL_Msk (0x07UL << PMC_DCDC1_DTESTSEL_Pos) /*!< PMC DCDC1: DTESTSEL Mask */
-#define PMC_DCDC1_ISCALEENABLE_Pos 19 /*!< PMC DCDC1: ISCALEENABLE Position */
-#define PMC_DCDC1_ISCALEENABLE_Msk (0x01UL << PMC_DCDC1_ISCALEENABLE_Pos) /*!< PMC DCDC1: ISCALEENABLE Mask */
-#define PMC_DCDC1_FORCEBYPASS_Pos 20 /*!< PMC DCDC1: FORCEBYPASS Position */
-#define PMC_DCDC1_FORCEBYPASS_Msk (0x01UL << PMC_DCDC1_FORCEBYPASS_Pos) /*!< PMC DCDC1: FORCEBYPASS Mask */
-#define PMC_DCDC1_TRIMAUTOCOT_Pos 21 /*!< PMC DCDC1: TRIMAUTOCOT Position */
-#define PMC_DCDC1_TRIMAUTOCOT_Msk (0x0fUL << PMC_DCDC1_TRIMAUTOCOT_Pos) /*!< PMC DCDC1: TRIMAUTOCOT Mask */
-#define PMC_DCDC1_LCENABLE_Pos 25 /*!< PMC DCDC1: LCENABLE Position */
-#define PMC_DCDC1_LCENABLE_Msk (0x01UL << PMC_DCDC1_LCENABLE_Pos) /*!< PMC DCDC1: LCENABLE Mask */
-#define PMC_DCDC1_FORCEFULLCYCLE_Pos 26 /*!< PMC DCDC1: FORCEFULLCYCLE Position */
-#define PMC_DCDC1_FORCEFULLCYCLE_Msk (0x01UL << PMC_DCDC1_FORCEFULLCYCLE_Pos) /*!< PMC DCDC1: FORCEFULLCYCLE Mask */
-
-/* --------------------------------- u_pmc_BIAS --------------------------------- */
-#define PMC_BIAS_DCBGAP_Pos 0 /*!< PMC BIAS: DCBGAP Position */
-#define PMC_BIAS_DCBGAP_Msk (0x1fUL << PMC_BIAS_DCBGAP_Pos) /*!< PMC BIAS: DCBGAP Mask */
-#define PMC_BIAS_CURVE_Pos 5 /*!< PMC BIAS: CURVE Position */
-#define PMC_BIAS_CURVE_Msk (0x03UL << PMC_BIAS_CURVE_Pos) /*!< PMC BIAS: CURVE Mask */
-#define PMC_BIAS_TRIM_Pos 8 /*!< PMC BIAS: TRIM Position */
-#define PMC_BIAS_TRIM_Msk (0x0fUL << PMC_BIAS_TRIM_Pos) /*!< PMC BIAS: TRIM Mask */
-#define PMC_BIAS_IREFTRIM_Pos 12 /*!< PMC BIAS: IREFTRIM Position */
-#define PMC_BIAS_IREFTRIM_Msk (0x3fUL << PMC_BIAS_IREFTRIM_Pos) /*!< PMC BIAS: IREFTRIM Mask */
-#define PMC_BIAS_ATBENABLE_Pos 18 /*!< PMC BIAS: ATBENABLE Position */
-#define PMC_BIAS_ATBENABLE_Msk (0x01UL << PMC_BIAS_ATBENABLE_Pos) /*!< PMC BIAS: ATBENABLE Mask */
-#define PMC_BIAS_ATB_Pos 19 /*!< PMC BIAS: ATB Position */
-#define PMC_BIAS_ATB_Msk (0x03UL << PMC_BIAS_ATB_Pos) /*!< PMC BIAS: ATB Mask */
-
-/* -------------------------------- u_pmc_LDOPMU -------------------------------- */
-#define PMC_LDOPMU_VADJ_Pos 0 /*!< PMC LDOPMU: VADJ Position */
-#define PMC_LDOPMU_VADJ_Msk (0x1fUL << PMC_LDOPMU_VADJ_Pos) /*!< PMC LDOPMU: VADJ Mask */
-#define PMC_LDOPMU_VADJ_PWD_Pos 5 /*!< PMC LDOPMU: VADJ_PWD Position */
-#define PMC_LDOPMU_VADJ_PWD_Msk (0x1fUL << PMC_LDOPMU_VADJ_PWD_Pos) /*!< PMC LDOPMU: VADJ_PWD Mask */
-#define PMC_LDOPMU_STAB_Pos 10 /*!< PMC LDOPMU: STAB Position */
-#define PMC_LDOPMU_STAB_Msk (0x01UL << PMC_LDOPMU_STAB_Pos) /*!< PMC LDOPMU: STAB Mask */
-#define PMC_LDOPMU_HIGHCUR_Pos 11 /*!< PMC LDOPMU: HIGHCUR Position */
-#define PMC_LDOPMU_HIGHCUR_Msk (0x01UL << PMC_LDOPMU_HIGHCUR_Pos) /*!< PMC LDOPMU: HIGHCUR Mask */
-#define PMC_LDOPMU_VADJ_BOOST_Pos 12 /*!< PMC LDOPMU: VADJ_BOOST Position */
-#define PMC_LDOPMU_VADJ_BOOST_Msk (0x1fUL << PMC_LDOPMU_VADJ_BOOST_Pos) /*!< PMC LDOPMU: VADJ_BOOST Mask */
-#define PMC_LDOPMU_VADJ_BOOST_PWD_Pos 17 /*!< PMC LDOPMU: VADJ_BOOST_PWD Position */
-#define PMC_LDOPMU_VADJ_BOOST_PWD_Msk (0x1fUL << PMC_LDOPMU_VADJ_BOOST_PWD_Pos) /*!< PMC LDOPMU: VADJ_BOOST_PWD Mask */
-#define PMC_LDOPMU_BOOSTADJ_Pos 22 /*!< PMC LDOPMU: BOOSTADJ Position */
-#define PMC_LDOPMU_BOOSTADJ_Msk (0x01UL << PMC_LDOPMU_BOOSTADJ_Pos) /*!< PMC LDOPMU: BOOSTADJ Mask */
-#define PMC_LDOPMU_BOOSTADJ_PWD_Pos 23 /*!< PMC LDOPMU: BOOSTADJ_PWD Position */
-#define PMC_LDOPMU_BOOSTADJ_PWD_Msk (0x01UL << PMC_LDOPMU_BOOSTADJ_PWD_Pos) /*!< PMC LDOPMU: BOOSTADJ_PWD Mask */
-#define PMC_LDOPMU_VADJ_2_Pos 24 /*!< PMC LDOPMU: VADJ_2 Position */
-#define PMC_LDOPMU_VADJ_2_Msk (0x1fUL << PMC_LDOPMU_VADJ_2_Pos) /*!< PMC LDOPMU: VADJ_2 Mask */
-#define PMC_LDOPMU_BOOSTADJ_2_Pos 29 /*!< PMC LDOPMU: BOOSTADJ_2 Position */
-#define PMC_LDOPMU_BOOSTADJ_2_Msk (0x01UL << PMC_LDOPMU_BOOSTADJ_2_Pos) /*!< PMC LDOPMU: BOOSTADJ_2 Mask */
-
-/* -------------------------------- u_pmc_LDOMEM -------------------------------- */
-#define PMC_LDOMEM_VADJ_Pos 0 /*!< PMC LDOMEM: VADJ Position */
-#define PMC_LDOMEM_VADJ_Msk (0x1fUL << PMC_LDOMEM_VADJ_Pos) /*!< PMC LDOMEM: VADJ Mask */
-#define PMC_LDOMEM_VADJ_PWD_Pos 5 /*!< PMC LDOMEM: VADJ_PWD Position */
-#define PMC_LDOMEM_VADJ_PWD_Msk (0x1fUL << PMC_LDOMEM_VADJ_PWD_Pos) /*!< PMC LDOMEM: VADJ_PWD Mask */
-#define PMC_LDOMEM_STAB_Pos 10 /*!< PMC LDOMEM: STAB Position */
-#define PMC_LDOMEM_STAB_Msk (0x01UL << PMC_LDOMEM_STAB_Pos) /*!< PMC LDOMEM: STAB Mask */
-#define PMC_LDOMEM_HIGHCUR_Pos 11 /*!< PMC LDOMEM: HIGHCUR Position */
-#define PMC_LDOMEM_HIGHCUR_Msk (0x01UL << PMC_LDOMEM_HIGHCUR_Pos) /*!< PMC LDOMEM: HIGHCUR Mask */
-#define PMC_LDOMEM_VADJ_BOOST_Pos 12 /*!< PMC LDOMEM: VADJ_BOOST Position */
-#define PMC_LDOMEM_VADJ_BOOST_Msk (0x1fUL << PMC_LDOMEM_VADJ_BOOST_Pos) /*!< PMC LDOMEM: VADJ_BOOST Mask */
-#define PMC_LDOMEM_VADJ_BOOST_PWD_Pos 17 /*!< PMC LDOMEM: VADJ_BOOST_PWD Position */
-#define PMC_LDOMEM_VADJ_BOOST_PWD_Msk (0x1fUL << PMC_LDOMEM_VADJ_BOOST_PWD_Pos) /*!< PMC LDOMEM: VADJ_BOOST_PWD Mask */
-#define PMC_LDOMEM_BLEED_Pos 22 /*!< PMC LDOMEM: BLEED Position */
-#define PMC_LDOMEM_BLEED_Msk (0x01UL << PMC_LDOMEM_BLEED_Pos) /*!< PMC LDOMEM: BLEED Mask */
-#define PMC_LDOMEM_VADJ_2_Pos 23 /*!< PMC LDOMEM: VADJ_2 Position */
-#define PMC_LDOMEM_VADJ_2_Msk (0x1fUL << PMC_LDOMEM_VADJ_2_Pos) /*!< PMC LDOMEM: VADJ_2 Mask */
-
-/* -------------------------------- u_pmc_LDOCORE ------------------------------- */
-#define PMC_LDOCORE_VADJ_Pos 0 /*!< PMC LDOCORE: VADJ Position */
-#define PMC_LDOCORE_VADJ_Msk (0x07UL << PMC_LDOCORE_VADJ_Pos) /*!< PMC LDOCORE: VADJ Mask */
-#define PMC_LDOCORE_VADJ_PWD_Pos 3 /*!< PMC LDOCORE: VADJ_PWD Position */
-#define PMC_LDOCORE_VADJ_PWD_Msk (0x07UL << PMC_LDOCORE_VADJ_PWD_Pos) /*!< PMC LDOCORE: VADJ_PWD Mask */
-#define PMC_LDOCORE_BYPASS_Pos 6 /*!< PMC LDOCORE: BYPASS Position */
-#define PMC_LDOCORE_BYPASS_Msk (0x01UL << PMC_LDOCORE_BYPASS_Pos) /*!< PMC LDOCORE: BYPASS Mask */
-#define PMC_LDOCORE_IBIAS_Pos 8 /*!< PMC LDOCORE: IBIAS Position */
-#define PMC_LDOCORE_IBIAS_Msk (0x03UL << PMC_LDOCORE_IBIAS_Pos) /*!< PMC LDOCORE: IBIAS Mask */
-#define PMC_LDOCORE_STABMODE_Pos 10 /*!< PMC LDOCORE: STABMODE Position */
-#define PMC_LDOCORE_STABMODE_Msk (0x03UL << PMC_LDOCORE_STABMODE_Pos) /*!< PMC LDOCORE: STABMODE Mask */
-#define PMC_LDOCORE_VADJ_2_Pos 12 /*!< PMC LDOCORE: VADJ_2 Position */
-#define PMC_LDOCORE_VADJ_2_Msk (0x07UL << PMC_LDOCORE_VADJ_2_Pos) /*!< PMC LDOCORE: VADJ_2 Mask */
-
-/* ------------------------------ u_pmc_LDOFLASHNV ------------------------------ */
-#define PMC_LDOFLASHNV_VADJ_Pos 0 /*!< PMC LDOFLASHNV: VADJ Position */
-#define PMC_LDOFLASHNV_VADJ_Msk (0x07UL << PMC_LDOFLASHNV_VADJ_Pos) /*!< PMC LDOFLASHNV: VADJ Mask */
-#define PMC_LDOFLASHNV_BYPASS_Pos 3 /*!< PMC LDOFLASHNV: BYPASS Position */
-#define PMC_LDOFLASHNV_BYPASS_Msk (0x01UL << PMC_LDOFLASHNV_BYPASS_Pos) /*!< PMC LDOFLASHNV: BYPASS Mask */
-#define PMC_LDOFLASHNV_HIGHZ_Pos 4 /*!< PMC LDOFLASHNV: HIGHZ Position */
-#define PMC_LDOFLASHNV_HIGHZ_Msk (0x01UL << PMC_LDOFLASHNV_HIGHZ_Pos) /*!< PMC LDOFLASHNV: HIGHZ Mask */
-#define PMC_LDOFLASHNV_IBIAS_Pos 5 /*!< PMC LDOFLASHNV: IBIAS Position */
-#define PMC_LDOFLASHNV_IBIAS_Msk (0x03UL << PMC_LDOFLASHNV_IBIAS_Pos) /*!< PMC LDOFLASHNV: IBIAS Mask */
-#define PMC_LDOFLASHNV_STABMODE_Pos 7 /*!< PMC LDOFLASHNV: STABMODE Position */
-#define PMC_LDOFLASHNV_STABMODE_Msk (0x01UL << PMC_LDOFLASHNV_STABMODE_Pos) /*!< PMC LDOFLASHNV: STABMODE Mask */
-#define PMC_LDOFLASHNV_TRIMR_Pos 10 /*!< PMC LDOFLASHNV: TRIMR Position */
-#define PMC_LDOFLASHNV_TRIMR_Msk (0x1fUL << PMC_LDOFLASHNV_TRIMR_Pos) /*!< PMC LDOFLASHNV: TRIMR Mask */
-#define PMC_LDOFLASHNV_VADJ_2_Pos 15 /*!< PMC LDOFLASHNV: VADJ_2 Position */
-#define PMC_LDOFLASHNV_VADJ_2_Msk (0x07UL << PMC_LDOFLASHNV_VADJ_2_Pos) /*!< PMC LDOFLASHNV: VADJ_2 Mask */
-
-/* ----------------------------- u_pmc_LDOFLASHCORE ----------------------------- */
-#define PMC_LDOFLASHCORE_VADJ_Pos 0 /*!< PMC LDOFLASHCORE: VADJ Position */
-#define PMC_LDOFLASHCORE_VADJ_Msk (0x07UL << PMC_LDOFLASHCORE_VADJ_Pos) /*!< PMC LDOFLASHCORE: VADJ Mask */
-#define PMC_LDOFLASHCORE_BYPASS_Pos 3 /*!< PMC LDOFLASHCORE: BYPASS Position */
-#define PMC_LDOFLASHCORE_BYPASS_Msk (0x01UL << PMC_LDOFLASHCORE_BYPASS_Pos) /*!< PMC LDOFLASHCORE: BYPASS Mask */
-#define PMC_LDOFLASHCORE_HIGHZ_Pos 4 /*!< PMC LDOFLASHCORE: HIGHZ Position */
-#define PMC_LDOFLASHCORE_HIGHZ_Msk (0x01UL << PMC_LDOFLASHCORE_HIGHZ_Pos) /*!< PMC LDOFLASHCORE: HIGHZ Mask */
-#define PMC_LDOFLASHCORE_IBIAS_Pos 5 /*!< PMC LDOFLASHCORE: IBIAS Position */
-#define PMC_LDOFLASHCORE_IBIAS_Msk (0x03UL << PMC_LDOFLASHCORE_IBIAS_Pos) /*!< PMC LDOFLASHCORE: IBIAS Mask */
-#define PMC_LDOFLASHCORE_STABMODE_Pos 7 /*!< PMC LDOFLASHCORE: STABMODE Position */
-#define PMC_LDOFLASHCORE_STABMODE_Msk (0x03UL << PMC_LDOFLASHCORE_STABMODE_Pos) /*!< PMC LDOFLASHCORE: STABMODE Mask */
-#define PMC_LDOFLASHCORE_VADJ_2_Pos 9 /*!< PMC LDOFLASHCORE: VADJ_2 Position */
-#define PMC_LDOFLASHCORE_VADJ_2_Msk (0x07UL << PMC_LDOFLASHCORE_VADJ_2_Pos) /*!< PMC LDOFLASHCORE: VADJ_2 Mask */
-
-/* -------------------------------- u_pmc_LDOADC -------------------------------- */
-#define PMC_LDOADC_VADJ_Pos 0 /*!< PMC LDOADC: VADJ Position */
-#define PMC_LDOADC_VADJ_Msk (0x07UL << PMC_LDOADC_VADJ_Pos) /*!< PMC LDOADC: VADJ Mask */
-#define PMC_LDOADC_BYPASS_Pos 3 /*!< PMC LDOADC: BYPASS Position */
-#define PMC_LDOADC_BYPASS_Msk (0x01UL << PMC_LDOADC_BYPASS_Pos) /*!< PMC LDOADC: BYPASS Mask */
-#define PMC_LDOADC_HIGHZ_Pos 4 /*!< PMC LDOADC: HIGHZ Position */
-#define PMC_LDOADC_HIGHZ_Msk (0x01UL << PMC_LDOADC_HIGHZ_Pos) /*!< PMC LDOADC: HIGHZ Mask */
-#define PMC_LDOADC_IBIAS_Pos 5 /*!< PMC LDOADC: IBIAS Position */
-#define PMC_LDOADC_IBIAS_Msk (0x03UL << PMC_LDOADC_IBIAS_Pos) /*!< PMC LDOADC: IBIAS Mask */
-#define PMC_LDOADC_STABMODE_Pos 7 /*!< PMC LDOADC: STABMODE Position */
-#define PMC_LDOADC_STABMODE_Msk (0x03UL << PMC_LDOADC_STABMODE_Pos) /*!< PMC LDOADC: STABMODE Mask */
-#define PMC_LDOADC_VADJ_2_Pos 9 /*!< PMC LDOADC: VADJ_2 Position */
-#define PMC_LDOADC_VADJ_2_Msk (0x07UL << PMC_LDOADC_VADJ_2_Pos) /*!< PMC LDOADC: VADJ_2 Mask */
-
-/* -------------------------------- u_pmc_BODVBAT ------------------------------- */
-#define PMC_BODVBAT_TRIGLVL_Pos 0 /*!< PMC BODVBAT: TRIGLVL Position */
-#define PMC_BODVBAT_TRIGLVL_Msk (0x1fUL << PMC_BODVBAT_TRIGLVL_Pos) /*!< PMC BODVBAT: TRIGLVL Mask */
-#define PMC_BODVBAT_HYST_Pos 5 /*!< PMC BODVBAT: HYST Position */
-#define PMC_BODVBAT_HYST_Msk (0x03UL << PMC_BODVBAT_HYST_Pos) /*!< PMC BODVBAT: HYST Mask */
-#define PMC_BODVBAT_RESETENABLE_Pos 7 /*!< PMC BODVBAT: RESETENABLE Position */
-#define PMC_BODVBAT_RESETENABLE_Msk (0x01UL << PMC_BODVBAT_RESETENABLE_Pos) /*!< PMC BODVBAT: RESETENABLE Mask */
-
-/* -------------------------------- u_pmc_BODMEM -------------------------------- */
-#define PMC_BODMEM_TRIGLVL_Pos 0 /*!< PMC BODMEM: TRIGLVL Position */
-#define PMC_BODMEM_TRIGLVL_Msk (0x0fUL << PMC_BODMEM_TRIGLVL_Pos) /*!< PMC BODMEM: TRIGLVL Mask */
-#define PMC_BODMEM_HYST_Pos 4 /*!< PMC BODMEM: HYST Position */
-#define PMC_BODMEM_HYST_Msk (0x03UL << PMC_BODMEM_HYST_Pos) /*!< PMC BODMEM: HYST Mask */
-#define PMC_BODMEM_RESETENABLE_Pos 6 /*!< PMC BODMEM: RESETENABLE Position */
-#define PMC_BODMEM_RESETENABLE_Msk (0x01UL << PMC_BODMEM_RESETENABLE_Pos) /*!< PMC BODMEM: RESETENABLE Mask */
-
-/* -------------------------------- u_pmc_BODCORE ------------------------------- */
-#define PMC_BODCORE_TRIGLVL_Pos 0 /*!< PMC BODCORE: TRIGLVL Position */
-#define PMC_BODCORE_TRIGLVL_Msk (0x0fUL << PMC_BODCORE_TRIGLVL_Pos) /*!< PMC BODCORE: TRIGLVL Mask */
-#define PMC_BODCORE_HYST_Pos 4 /*!< PMC BODCORE: HYST Position */
-#define PMC_BODCORE_HYST_Msk (0x03UL << PMC_BODCORE_HYST_Pos) /*!< PMC BODCORE: HYST Mask */
-#define PMC_BODCORE_RESETENABLE_Pos 6 /*!< PMC BODCORE: RESETENABLE Position */
-#define PMC_BODCORE_RESETENABLE_Msk (0x01UL << PMC_BODCORE_RESETENABLE_Pos) /*!< PMC BODCORE: RESETENABLE Mask */
-
-/* -------------------------------- u_pmc_FRO192M ------------------------------- */
-#define PMC_FRO192M_TEMPTRIM_Pos 0 /*!< PMC FRO192M: TEMPTRIM Position */
-#define PMC_FRO192M_TEMPTRIM_Msk (0x3fUL << PMC_FRO192M_TEMPTRIM_Pos) /*!< PMC FRO192M: TEMPTRIM Mask */
-#define PMC_FRO192M_BIASTRIM_Pos 6 /*!< PMC FRO192M: BIASTRIM Position */
-#define PMC_FRO192M_BIASTRIM_Msk (0x3fUL << PMC_FRO192M_BIASTRIM_Pos) /*!< PMC FRO192M: BIASTRIM Mask */
-#define PMC_FRO192M_DACTRIM_Pos 12 /*!< PMC FRO192M: DACTRIM Position */
-#define PMC_FRO192M_DACTRIM_Msk (0x000000ffUL << PMC_FRO192M_DACTRIM_Pos) /*!< PMC FRO192M: DACTRIM Mask */
-#define PMC_FRO192M_DIVSEL_Pos 20 /*!< PMC FRO192M: DIVSEL Position */
-#define PMC_FRO192M_DIVSEL_Msk (0x1fUL << PMC_FRO192M_DIVSEL_Pos) /*!< PMC FRO192M: DIVSEL Mask */
-#define PMC_FRO192M_ATBCTRL_Pos 25 /*!< PMC FRO192M: ATBCTRL Position */
-#define PMC_FRO192M_ATBCTRL_Msk (0x03UL << PMC_FRO192M_ATBCTRL_Pos) /*!< PMC FRO192M: ATBCTRL Mask */
-
-/* --------------------------------- u_pmc_FRO1M -------------------------------- */
-#define PMC_FRO1M_FREQSEL_Pos 0 /*!< PMC FRO1M: FREQSEL Position */
-#define PMC_FRO1M_FREQSEL_Msk (0x7fUL << PMC_FRO1M_FREQSEL_Pos) /*!< PMC FRO1M: FREQSEL Mask */
-#define PMC_FRO1M_ATBCTRL_Pos 7 /*!< PMC FRO1M: ATBCTRL Position */
-#define PMC_FRO1M_ATBCTRL_Msk (0x03UL << PMC_FRO1M_ATBCTRL_Pos) /*!< PMC FRO1M: ATBCTRL Mask */
-#define PMC_FRO1M_DIVSEL_Pos 9 /*!< PMC FRO1M: DIVSEL Position */
-#define PMC_FRO1M_DIVSEL_Msk (0x1fUL << PMC_FRO1M_DIVSEL_Pos) /*!< PMC FRO1M: DIVSEL Mask */
-
-/* -------------------------------- u_pmc_FRO32K -------------------------------- */
-#define PMC_FRO32K_NTAT_Pos 1 /*!< PMC FRO32K: NTAT Position */
-#define PMC_FRO32K_NTAT_Msk (0x07UL << PMC_FRO32K_NTAT_Pos) /*!< PMC FRO32K: NTAT Mask */
-#define PMC_FRO32K_PTAT_Pos 4 /*!< PMC FRO32K: PTAT Position */
-#define PMC_FRO32K_PTAT_Msk (0x07UL << PMC_FRO32K_PTAT_Pos) /*!< PMC FRO32K: PTAT Mask */
-#define PMC_FRO32K_CAPCAL_Pos 7 /*!< PMC FRO32K: CAPCAL Position */
-#define PMC_FRO32K_CAPCAL_Msk (0x000001ffUL << PMC_FRO32K_CAPCAL_Pos) /*!< PMC FRO32K: CAPCAL Mask */
-#define PMC_FRO32K_ATBCTRL_Pos 16 /*!< PMC FRO32K: ATBCTRL Position */
-#define PMC_FRO32K_ATBCTRL_Msk (0x03UL << PMC_FRO32K_ATBCTRL_Pos) /*!< PMC FRO32K: ATBCTRL Mask */
-
-/* -------------------------------- u_pmc_XTAL32K ------------------------------- */
-#define PMC_XTAL32K_IREF_Pos 1 /*!< PMC XTAL32K: IREF Position */
-#define PMC_XTAL32K_IREF_Msk (0x03UL << PMC_XTAL32K_IREF_Pos) /*!< PMC XTAL32K: IREF Mask */
-#define PMC_XTAL32K_TEST_Pos 3 /*!< PMC XTAL32K: TEST Position */
-#define PMC_XTAL32K_TEST_Msk (0x01UL << PMC_XTAL32K_TEST_Pos) /*!< PMC XTAL32K: TEST Mask */
-#define PMC_XTAL32K_IBIAS_Pos 4 /*!< PMC XTAL32K: IBIAS Position */
-#define PMC_XTAL32K_IBIAS_Msk (0x03UL << PMC_XTAL32K_IBIAS_Pos) /*!< PMC XTAL32K: IBIAS Mask */
-#define PMC_XTAL32K_AMPL_Pos 6 /*!< PMC XTAL32K: AMPL Position */
-#define PMC_XTAL32K_AMPL_Msk (0x03UL << PMC_XTAL32K_AMPL_Pos) /*!< PMC XTAL32K: AMPL Mask */
-
-/* ------------------------------ u_pmc_ANAMUXCOMP ------------------------------ */
-#define PMC_ANAMUXCOMP_COMP_HYST_Pos 1 /*!< PMC ANAMUXCOMP: COMP_HYST Position */
-#define PMC_ANAMUXCOMP_COMP_HYST_Msk (0x01UL << PMC_ANAMUXCOMP_COMP_HYST_Pos) /*!< PMC ANAMUXCOMP: COMP_HYST Mask */
-#define PMC_ANAMUXCOMP_COMP_INNINT_Pos 2 /*!< PMC ANAMUXCOMP: COMP_INNINT Position */
-#define PMC_ANAMUXCOMP_COMP_INNINT_Msk (0x01UL << PMC_ANAMUXCOMP_COMP_INNINT_Pos) /*!< PMC ANAMUXCOMP: COMP_INNINT Mask */
-#define PMC_ANAMUXCOMP_COMP_LOWPOWER_Pos 3 /*!< PMC ANAMUXCOMP: COMP_LOWPOWER Position */
-#define PMC_ANAMUXCOMP_COMP_LOWPOWER_Msk (0x01UL << PMC_ANAMUXCOMP_COMP_LOWPOWER_Pos) /*!< PMC ANAMUXCOMP: COMP_LOWPOWER Mask */
-#define PMC_ANAMUXCOMP_COMP_INPUTSWAP_Pos 4 /*!< PMC ANAMUXCOMP: COMP_INPUTSWAP Position */
-#define PMC_ANAMUXCOMP_COMP_INPUTSWAP_Msk (0x01UL << PMC_ANAMUXCOMP_COMP_INPUTSWAP_Pos) /*!< PMC ANAMUXCOMP: COMP_INPUTSWAP Mask */
-#define PMC_ANAMUXCOMP_MUX_1_SEL_Pos 5 /*!< PMC ANAMUXCOMP: MUX_1_SEL Position */
-#define PMC_ANAMUXCOMP_MUX_1_SEL_Msk (0x07UL << PMC_ANAMUXCOMP_MUX_1_SEL_Pos) /*!< PMC ANAMUXCOMP: MUX_1_SEL Mask */
-#define PMC_ANAMUXCOMP_MUX_2_SEL_Pos 8 /*!< PMC ANAMUXCOMP: MUX_2_SEL Position */
-#define PMC_ANAMUXCOMP_MUX_2_SEL_Msk (0x07UL << PMC_ANAMUXCOMP_MUX_2_SEL_Pos) /*!< PMC ANAMUXCOMP: MUX_2_SEL Mask */
-
-/* ------------------------------- u_pmc_PWRSWACK ------------------------------- */
-#define PMC_PWRSWACK_RESERVED0_Pos 0 /*!< PMC PWRSWACK: RESERVED0 Position */
-#define PMC_PWRSWACK_RESERVED0_Msk (0x01UL << PMC_PWRSWACK_RESERVED0_Pos) /*!< PMC PWRSWACK: RESERVED0 Mask */
-#define PMC_PWRSWACK_PDCOMM0_Pos 1 /*!< PMC PWRSWACK: PDCOMM0 Position */
-#define PMC_PWRSWACK_PDCOMM0_Msk (0x01UL << PMC_PWRSWACK_PDCOMM0_Pos) /*!< PMC PWRSWACK: PDCOMM0 Mask */
-#define PMC_PWRSWACK_PDSYSTEM_Pos 2 /*!< PMC PWRSWACK: PDSYSTEM Position */
-#define PMC_PWRSWACK_PDSYSTEM_Msk (0x01UL << PMC_PWRSWACK_PDSYSTEM_Pos) /*!< PMC PWRSWACK: PDSYSTEM Mask */
-#define PMC_PWRSWACK_PDMCURETENTION_Pos 3 /*!< PMC PWRSWACK: PDMCURETENTION Position */
-#define PMC_PWRSWACK_PDMCURETENTION_Msk (0x01UL << PMC_PWRSWACK_PDMCURETENTION_Pos) /*!< PMC PWRSWACK: PDMCURETENTION Mask */
-#define PMC_PWRSWACK_RESERVED4_Pos 4 /*!< PMC PWRSWACK: RESERVED4 Position */
-#define PMC_PWRSWACK_RESERVED4_Msk (0x01UL << PMC_PWRSWACK_RESERVED4_Pos) /*!< PMC PWRSWACK: RESERVED4 Mask */
-
-/* ------------------------------- u_pmc_DPDWKSRC ------------------------------- */
-#define PMC_DPDWKSRC_PIO0_Pos 0 /*!< PMC DPDWKSRC: PIO0 Position */
-#define PMC_DPDWKSRC_PIO0_Msk (0x01UL << PMC_DPDWKSRC_PIO0_Pos) /*!< PMC DPDWKSRC: PIO0 Mask */
-#define PMC_DPDWKSRC_PIO1_Pos 1 /*!< PMC DPDWKSRC: PIO1 Position */
-#define PMC_DPDWKSRC_PIO1_Msk (0x01UL << PMC_DPDWKSRC_PIO1_Pos) /*!< PMC DPDWKSRC: PIO1 Mask */
-#define PMC_DPDWKSRC_PIO2_Pos 2 /*!< PMC DPDWKSRC: PIO2 Position */
-#define PMC_DPDWKSRC_PIO2_Msk (0x01UL << PMC_DPDWKSRC_PIO2_Pos) /*!< PMC DPDWKSRC: PIO2 Mask */
-#define PMC_DPDWKSRC_PIO3_Pos 3 /*!< PMC DPDWKSRC: PIO3 Position */
-#define PMC_DPDWKSRC_PIO3_Msk (0x01UL << PMC_DPDWKSRC_PIO3_Pos) /*!< PMC DPDWKSRC: PIO3 Mask */
-#define PMC_DPDWKSRC_PIO4_Pos 4 /*!< PMC DPDWKSRC: PIO4 Position */
-#define PMC_DPDWKSRC_PIO4_Msk (0x01UL << PMC_DPDWKSRC_PIO4_Pos) /*!< PMC DPDWKSRC: PIO4 Mask */
-#define PMC_DPDWKSRC_PIO5_Pos 5 /*!< PMC DPDWKSRC: PIO5 Position */
-#define PMC_DPDWKSRC_PIO5_Msk (0x01UL << PMC_DPDWKSRC_PIO5_Pos) /*!< PMC DPDWKSRC: PIO5 Mask */
-#define PMC_DPDWKSRC_PIO6_Pos 6 /*!< PMC DPDWKSRC: PIO6 Position */
-#define PMC_DPDWKSRC_PIO6_Msk (0x01UL << PMC_DPDWKSRC_PIO6_Pos) /*!< PMC DPDWKSRC: PIO6 Mask */
-#define PMC_DPDWKSRC_PIO7_Pos 7 /*!< PMC DPDWKSRC: PIO7 Position */
-#define PMC_DPDWKSRC_PIO7_Msk (0x01UL << PMC_DPDWKSRC_PIO7_Pos) /*!< PMC DPDWKSRC: PIO7 Mask */
-#define PMC_DPDWKSRC_PIO8_Pos 8 /*!< PMC DPDWKSRC: PIO8 Position */
-#define PMC_DPDWKSRC_PIO8_Msk (0x01UL << PMC_DPDWKSRC_PIO8_Pos) /*!< PMC DPDWKSRC: PIO8 Mask */
-#define PMC_DPDWKSRC_PIO9_Pos 9 /*!< PMC DPDWKSRC: PIO9 Position */
-#define PMC_DPDWKSRC_PIO9_Msk (0x01UL << PMC_DPDWKSRC_PIO9_Pos) /*!< PMC DPDWKSRC: PIO9 Mask */
-#define PMC_DPDWKSRC_PIO10_Pos 10 /*!< PMC DPDWKSRC: PIO10 Position */
-#define PMC_DPDWKSRC_PIO10_Msk (0x01UL << PMC_DPDWKSRC_PIO10_Pos) /*!< PMC DPDWKSRC: PIO10 Mask */
-#define PMC_DPDWKSRC_PIO11_Pos 11 /*!< PMC DPDWKSRC: PIO11 Position */
-#define PMC_DPDWKSRC_PIO11_Msk (0x01UL << PMC_DPDWKSRC_PIO11_Pos) /*!< PMC DPDWKSRC: PIO11 Mask */
-#define PMC_DPDWKSRC_PIO12_Pos 12 /*!< PMC DPDWKSRC: PIO12 Position */
-#define PMC_DPDWKSRC_PIO12_Msk (0x01UL << PMC_DPDWKSRC_PIO12_Pos) /*!< PMC DPDWKSRC: PIO12 Mask */
-#define PMC_DPDWKSRC_PIO13_Pos 13 /*!< PMC DPDWKSRC: PIO13 Position */
-#define PMC_DPDWKSRC_PIO13_Msk (0x01UL << PMC_DPDWKSRC_PIO13_Pos) /*!< PMC DPDWKSRC: PIO13 Mask */
-#define PMC_DPDWKSRC_PIO14_Pos 14 /*!< PMC DPDWKSRC: PIO14 Position */
-#define PMC_DPDWKSRC_PIO14_Msk (0x01UL << PMC_DPDWKSRC_PIO14_Pos) /*!< PMC DPDWKSRC: PIO14 Mask */
-#define PMC_DPDWKSRC_PIO15_Pos 15 /*!< PMC DPDWKSRC: PIO15 Position */
-#define PMC_DPDWKSRC_PIO15_Msk (0x01UL << PMC_DPDWKSRC_PIO15_Pos) /*!< PMC DPDWKSRC: PIO15 Mask */
-#define PMC_DPDWKSRC_PIO16_Pos 16 /*!< PMC DPDWKSRC: PIO16 Position */
-#define PMC_DPDWKSRC_PIO16_Msk (0x01UL << PMC_DPDWKSRC_PIO16_Pos) /*!< PMC DPDWKSRC: PIO16 Mask */
-#define PMC_DPDWKSRC_PIO17_Pos 17 /*!< PMC DPDWKSRC: PIO17 Position */
-#define PMC_DPDWKSRC_PIO17_Msk (0x01UL << PMC_DPDWKSRC_PIO17_Pos) /*!< PMC DPDWKSRC: PIO17 Mask */
-#define PMC_DPDWKSRC_PIO18_Pos 18 /*!< PMC DPDWKSRC: PIO18 Position */
-#define PMC_DPDWKSRC_PIO18_Msk (0x01UL << PMC_DPDWKSRC_PIO18_Pos) /*!< PMC DPDWKSRC: PIO18 Mask */
-#define PMC_DPDWKSRC_PIO19_Pos 19 /*!< PMC DPDWKSRC: PIO19 Position */
-#define PMC_DPDWKSRC_PIO19_Msk (0x01UL << PMC_DPDWKSRC_PIO19_Pos) /*!< PMC DPDWKSRC: PIO19 Mask */
-#define PMC_DPDWKSRC_PIO20_Pos 20 /*!< PMC DPDWKSRC: PIO20 Position */
-#define PMC_DPDWKSRC_PIO20_Msk (0x01UL << PMC_DPDWKSRC_PIO20_Pos) /*!< PMC DPDWKSRC: PIO20 Mask */
-#define PMC_DPDWKSRC_PIO21_Pos 21 /*!< PMC DPDWKSRC: PIO21 Position */
-#define PMC_DPDWKSRC_PIO21_Msk (0x01UL << PMC_DPDWKSRC_PIO21_Pos) /*!< PMC DPDWKSRC: PIO21 Mask */
-#define PMC_DPDWKSRC_NTAG_FD_Pos 22 /*!< PMC DPDWKSRC: NTAG_FD Position */
-#define PMC_DPDWKSRC_NTAG_FD_Msk (0x01UL << PMC_DPDWKSRC_NTAG_FD_Pos) /*!< PMC DPDWKSRC: NTAG_FD Mask */
-
-/* ------------------------------- u_pmc_STATUSPWR ------------------------------ */
-#define PMC_STATUSPWR_DCDCPWROK_Pos 0 /*!< PMC STATUSPWR: DCDCPWROK Position */
-#define PMC_STATUSPWR_DCDCPWROK_Msk (0x01UL << PMC_STATUSPWR_DCDCPWROK_Pos) /*!< PMC STATUSPWR: DCDCPWROK Mask */
-#define PMC_STATUSPWR_DCDCVXCTRLMON_Pos 1 /*!< PMC STATUSPWR: DCDCVXCTRLMON Position */
-#define PMC_STATUSPWR_DCDCVXCTRLMON_Msk (0x01UL << PMC_STATUSPWR_DCDCVXCTRLMON_Pos) /*!< PMC STATUSPWR: DCDCVXCTRLMON Mask */
-#define PMC_STATUSPWR_LDOCOREPWROK_Pos 2 /*!< PMC STATUSPWR: LDOCOREPWROK Position */
-#define PMC_STATUSPWR_LDOCOREPWROK_Msk (0x01UL << PMC_STATUSPWR_LDOCOREPWROK_Pos) /*!< PMC STATUSPWR: LDOCOREPWROK Mask */
-#define PMC_STATUSPWR_LDOFLASHNVPWROK_Pos 3 /*!< PMC STATUSPWR: LDOFLASHNVPWROK Position */
-#define PMC_STATUSPWR_LDOFLASHNVPWROK_Msk (0x01UL << PMC_STATUSPWR_LDOFLASHNVPWROK_Pos) /*!< PMC STATUSPWR: LDOFLASHNVPWROK Mask */
-#define PMC_STATUSPWR_LDOFLASHCOREPWROK_Pos 4 /*!< PMC STATUSPWR: LDOFLASHCOREPWROK Position */
-#define PMC_STATUSPWR_LDOFLASHCOREPWROK_Msk (0x01UL << PMC_STATUSPWR_LDOFLASHCOREPWROK_Pos) /*!< PMC STATUSPWR: LDOFLASHCOREPWROK Mask */
-#define PMC_STATUSPWR_LDOADC1V1PWROK_Pos 5 /*!< PMC STATUSPWR: LDOADC1V1PWROK Position */
-#define PMC_STATUSPWR_LDOADC1V1PWROK_Msk (0x01UL << PMC_STATUSPWR_LDOADC1V1PWROK_Pos) /*!< PMC STATUSPWR: LDOADC1V1PWROK Mask */
-
-/* ------------------------------- u_pmc_STATUSCLK ------------------------------ */
-#define PMC_STATUSCLK_FRO192MCLKVALID_Pos 0 /*!< PMC STATUSCLK: FRO192MCLKVALID Position */
-#define PMC_STATUSCLK_FRO192MCLKVALID_Msk (0x01UL << PMC_STATUSCLK_FRO192MCLKVALID_Pos) /*!< PMC STATUSCLK: FRO192MCLKVALID Mask */
-#define PMC_STATUSCLK_XTAL32KOK_Pos 1 /*!< PMC STATUSCLK: XTAL32KOK Position */
-#define PMC_STATUSCLK_XTAL32KOK_Msk (0x01UL << PMC_STATUSCLK_XTAL32KOK_Pos) /*!< PMC STATUSCLK: XTAL32KOK Mask */
-#define PMC_STATUSCLK_FRO1MCLKVALID_Pos 2 /*!< PMC STATUSCLK: FRO1MCLKVALID Position */
-#define PMC_STATUSCLK_FRO1MCLKVALID_Msk (0x01UL << PMC_STATUSCLK_FRO1MCLKVALID_Pos) /*!< PMC STATUSCLK: FRO1MCLKVALID Mask */
-
-/* ------------------------------ u_pmc_RESETCAUSE ------------------------------ */
-#define PMC_RESETCAUSE_POR_Pos 0 /*!< PMC RESETCAUSE: POR Position */
-#define PMC_RESETCAUSE_POR_Msk (0x01UL << PMC_RESETCAUSE_POR_Pos) /*!< PMC RESETCAUSE: POR Mask */
-#define PMC_RESETCAUSE_PADRESET_Pos 1 /*!< PMC RESETCAUSE: PADRESET Position */
-#define PMC_RESETCAUSE_PADRESET_Msk (0x01UL << PMC_RESETCAUSE_PADRESET_Pos) /*!< PMC RESETCAUSE: PADRESET Mask */
-#define PMC_RESETCAUSE_BODRESET_Pos 2 /*!< PMC RESETCAUSE: BODRESET Position */
-#define PMC_RESETCAUSE_BODRESET_Msk (0x01UL << PMC_RESETCAUSE_BODRESET_Pos) /*!< PMC RESETCAUSE: BODRESET Mask */
-#define PMC_RESETCAUSE_SYSTEMRESET_Pos 3 /*!< PMC RESETCAUSE: SYSTEMRESET Position */
-#define PMC_RESETCAUSE_SYSTEMRESET_Msk (0x01UL << PMC_RESETCAUSE_SYSTEMRESET_Pos) /*!< PMC RESETCAUSE: SYSTEMRESET Mask */
-#define PMC_RESETCAUSE_WDTRESET_Pos 4 /*!< PMC RESETCAUSE: WDTRESET Position */
-#define PMC_RESETCAUSE_WDTRESET_Msk (0x01UL << PMC_RESETCAUSE_WDTRESET_Pos) /*!< PMC RESETCAUSE: WDTRESET Mask */
-#define PMC_RESETCAUSE_WAKEUPIORESET_Pos 5 /*!< PMC RESETCAUSE: WAKEUPIORESET Position */
-#define PMC_RESETCAUSE_WAKEUPIORESET_Msk (0x01UL << PMC_RESETCAUSE_WAKEUPIORESET_Pos) /*!< PMC RESETCAUSE: WAKEUPIORESET Mask */
-#define PMC_RESETCAUSE_WAKEUPPWDNRESET_Pos 6 /*!< PMC RESETCAUSE: WAKEUPPWDNRESET Position */
-#define PMC_RESETCAUSE_WAKEUPPWDNRESET_Msk (0x01UL << PMC_RESETCAUSE_WAKEUPPWDNRESET_Pos) /*!< PMC RESETCAUSE: WAKEUPPWDNRESET Mask */
-#define PMC_RESETCAUSE_SWRRESET_Pos 7 /*!< PMC RESETCAUSE: SWRRESET Position */
-#define PMC_RESETCAUSE_SWRRESET_Msk (0x01UL << PMC_RESETCAUSE_SWRRESET_Pos) /*!< PMC RESETCAUSE: SWRRESET Mask */
-
-/* -------------------------------- u_pmc_AOREG0 -------------------------------- */
-#define PMC_AOREG0_DATA31_0_Pos 0 /*!< PMC AOREG0: DATA31_0 Position */
-#define PMC_AOREG0_DATA31_0_Msk (0xffffffffUL << PMC_AOREG0_DATA31_0_Pos) /*!< PMC AOREG0: DATA31_0 Mask */
-
-/* -------------------------------- u_pmc_AOREG1 -------------------------------- */
-#define PMC_AOREG1_DATA31_0_Pos 0 /*!< PMC AOREG1: DATA31_0 Position */
-#define PMC_AOREG1_DATA31_0_Msk (0xffffffffUL << PMC_AOREG1_DATA31_0_Pos) /*!< PMC AOREG1: DATA31_0 Mask */
-
-/* -------------------------------- u_pmc_AOREG2 -------------------------------- */
-#define PMC_AOREG2_DATA31_0_Pos 0 /*!< PMC AOREG2: DATA31_0 Position */
-#define PMC_AOREG2_DATA31_0_Msk (0xffffffffUL << PMC_AOREG2_DATA31_0_Pos) /*!< PMC AOREG2: DATA31_0 Mask */
-
-/* ------------------------------- u_pmc_DUMMYCTRL ------------------------------ */
-#define PMC_DUMMYCTRL_DUMMYCTRL_Pos 0 /*!< PMC DUMMYCTRL: DUMMYCTRL Position */
-#define PMC_DUMMYCTRL_DUMMYCTRL_Msk (0xffffffffUL << PMC_DUMMYCTRL_DUMMYCTRL_Pos) /*!< PMC DUMMYCTRL: DUMMYCTRL Mask */
-
-/* ------------------------------ u_pmc_DUMMYSTATUS ----------------------------- */
-#define PMC_DUMMYSTATUS_DUMMYSTATUS_Pos 0 /*!< PMC DUMMYSTATUS: DUMMYSTATUS Position */
-#define PMC_DUMMYSTATUS_DUMMYSTATUS_Msk (0x000000ffUL << PMC_DUMMYSTATUS_DUMMYSTATUS_Pos) /*!< PMC DUMMYSTATUS: DUMMYSTATUS Mask */
-
-/* -------------------------------- u_pmc_DPDCTRL ------------------------------- */
-#define PMC_DPDCTRL_XTAL32MSTARTENA_Pos 0 /*!< PMC DPDCTRL: XTAL32MSTARTENA Position */
-#define PMC_DPDCTRL_XTAL32MSTARTENA_Msk (0x01UL << PMC_DPDCTRL_XTAL32MSTARTENA_Pos) /*!< PMC DPDCTRL: XTAL32MSTARTENA Mask */
-#define PMC_DPDCTRL_XTAL32MSTARTDLY_Pos 1 /*!< PMC DPDCTRL: XTAL32MSTARTDLY Position */
-#define PMC_DPDCTRL_XTAL32MSTARTDLY_Msk (0x03UL << PMC_DPDCTRL_XTAL32MSTARTDLY_Pos) /*!< PMC DPDCTRL: XTAL32MSTARTDLY Mask */
-
-/* ------------------------------- u_pmc_PIOPORCAP ------------------------------ */
-#define PMC_PIOPORCAP_PIOPORCAP_Pos 0 /*!< PMC PIOPORCAP: PIOPORCAP Position */
-#define PMC_PIOPORCAP_PIOPORCAP_Msk (0xffffffffUL << PMC_PIOPORCAP_PIOPORCAP_Pos) /*!< PMC PIOPORCAP: PIOPORCAP Mask */
-
-/* ------------------------------- u_pmc_PIORESCAP ------------------------------ */
-#define PMC_PIORESCAP_PIORESCAP_Pos 0 /*!< PMC PIORESCAP: PIORESCAP Position */
-#define PMC_PIORESCAP_PIORESCAP_Msk (0xffffffffUL << PMC_PIORESCAP_PIORESCAP_Pos) /*!< PMC PIORESCAP: PIORESCAP Mask */
-
-/* ----------------------------- u_pmc_TIMEOUTEVENTS ---------------------------- */
-#define PMC_TIMEOUTEVENTS_TIMEOUTEVENTS_Pos 0 /*!< PMC TIMEOUTEVENTS: TIMEOUTEVENTS Position */
-#define PMC_TIMEOUTEVENTS_TIMEOUTEVENTS_Msk (0xffffffffUL << PMC_TIMEOUTEVENTS_TIMEOUTEVENTS_Pos) /*!< PMC TIMEOUTEVENTS: TIMEOUTEVENTS Mask */
-
-/* -------------------------------- u_pmc_TIMEOUT ------------------------------- */
-#define PMC_TIMEOUT_PMUPOWEROK_Pos 0 /*!< PMC TIMEOUT: PMUPOWEROK Position */
-#define PMC_TIMEOUT_PMUPOWEROK_Msk (0x00001fffUL << PMC_TIMEOUT_PMUPOWEROK_Pos) /*!< PMC TIMEOUT: PMUPOWEROK Mask */
-#define PMC_TIMEOUT_LDOFLASHNVDEACTIVATE_Pos 13 /*!< PMC TIMEOUT: LDOFLASHNVDEACTIVATE Position */
-#define PMC_TIMEOUT_LDOFLASHNVDEACTIVATE_Msk (0x000001ffUL << PMC_TIMEOUT_LDOFLASHNVDEACTIVATE_Pos)/*!< PMC TIMEOUT: LDOFLASHNVDEACTIVATE Mask */
-
-/* ------------------------------ u_pmc_PDSLEEPCFG ------------------------------ */
-#define PMC_PDSLEEPCFG_PDEN_DCDC_Pos 0 /*!< PMC PDSLEEPCFG: PDEN_DCDC Position */
-#define PMC_PDSLEEPCFG_PDEN_DCDC_Msk (0x01UL << PMC_PDSLEEPCFG_PDEN_DCDC_Pos) /*!< PMC PDSLEEPCFG: PDEN_DCDC Mask */
-#define PMC_PDSLEEPCFG_PDEN_BIAS_Pos 1 /*!< PMC PDSLEEPCFG: PDEN_BIAS Position */
-#define PMC_PDSLEEPCFG_PDEN_BIAS_Msk (0x01UL << PMC_PDSLEEPCFG_PDEN_BIAS_Pos) /*!< PMC PDSLEEPCFG: PDEN_BIAS Mask */
-#define PMC_PDSLEEPCFG_PDEN_LDO_MEM_Pos 2 /*!< PMC PDSLEEPCFG: PDEN_LDO_MEM Position */
-#define PMC_PDSLEEPCFG_PDEN_LDO_MEM_Msk (0x01UL << PMC_PDSLEEPCFG_PDEN_LDO_MEM_Pos) /*!< PMC PDSLEEPCFG: PDEN_LDO_MEM Mask */
-#define PMC_PDSLEEPCFG_PDEN_VBAT_BOD_Pos 3 /*!< PMC PDSLEEPCFG: PDEN_VBAT_BOD Position */
-#define PMC_PDSLEEPCFG_PDEN_VBAT_BOD_Msk (0x01UL << PMC_PDSLEEPCFG_PDEN_VBAT_BOD_Pos) /*!< PMC PDSLEEPCFG: PDEN_VBAT_BOD Mask */
-#define PMC_PDSLEEPCFG_PDEN_FRO192M_Pos 4 /*!< PMC PDSLEEPCFG: PDEN_FRO192M Position */
-#define PMC_PDSLEEPCFG_PDEN_FRO192M_Msk (0x01UL << PMC_PDSLEEPCFG_PDEN_FRO192M_Pos) /*!< PMC PDSLEEPCFG: PDEN_FRO192M Mask */
-#define PMC_PDSLEEPCFG_PDEN_FRO1M_Pos 5 /*!< PMC PDSLEEPCFG: PDEN_FRO1M Position */
-#define PMC_PDSLEEPCFG_PDEN_FRO1M_Msk (0x01UL << PMC_PDSLEEPCFG_PDEN_FRO1M_Pos) /*!< PMC PDSLEEPCFG: PDEN_FRO1M Mask */
-#define PMC_PDSLEEPCFG_PDEN_PD_FLASH_Pos 6 /*!< PMC PDSLEEPCFG: PDEN_PD_FLASH Position */
-#define PMC_PDSLEEPCFG_PDEN_PD_FLASH_Msk (0x01UL << PMC_PDSLEEPCFG_PDEN_PD_FLASH_Pos) /*!< PMC PDSLEEPCFG: PDEN_PD_FLASH Mask */
-#define PMC_PDSLEEPCFG_PDEN_PD_COMM0_Pos 7 /*!< PMC PDSLEEPCFG: PDEN_PD_COMM0 Position */
-#define PMC_PDSLEEPCFG_PDEN_PD_COMM0_Msk (0x01UL << PMC_PDSLEEPCFG_PDEN_PD_COMM0_Pos) /*!< PMC PDSLEEPCFG: PDEN_PD_COMM0 Mask */
-#define PMC_PDSLEEPCFG_EN_PDMCU_RETENTION_Pos 8 /*!< PMC PDSLEEPCFG: EN_PDMCU_RETENTION Position */
-#define PMC_PDSLEEPCFG_EN_PDMCU_RETENTION_Msk (0x01UL << PMC_PDSLEEPCFG_EN_PDMCU_RETENTION_Pos) /*!< PMC PDSLEEPCFG: EN_PDMCU_RETENTION Mask */
-#define PMC_PDSLEEPCFG_RESERVED9_Pos 9 /*!< PMC PDSLEEPCFG: RESERVED9 Position */
-#define PMC_PDSLEEPCFG_RESERVED9_Msk (0x01UL << PMC_PDSLEEPCFG_RESERVED9_Pos) /*!< PMC PDSLEEPCFG: RESERVED9 Mask */
-#define PMC_PDSLEEPCFG_PDEN_PD_MEM0_Pos 10 /*!< PMC PDSLEEPCFG: PDEN_PD_MEM0 Position */
-#define PMC_PDSLEEPCFG_PDEN_PD_MEM0_Msk (0x01UL << PMC_PDSLEEPCFG_PDEN_PD_MEM0_Pos) /*!< PMC PDSLEEPCFG: PDEN_PD_MEM0 Mask */
-#define PMC_PDSLEEPCFG_PDEN_PD_MEM1_Pos 11 /*!< PMC PDSLEEPCFG: PDEN_PD_MEM1 Position */
-#define PMC_PDSLEEPCFG_PDEN_PD_MEM1_Msk (0x01UL << PMC_PDSLEEPCFG_PDEN_PD_MEM1_Pos) /*!< PMC PDSLEEPCFG: PDEN_PD_MEM1 Mask */
-#define PMC_PDSLEEPCFG_PDEN_PD_MEM2_Pos 12 /*!< PMC PDSLEEPCFG: PDEN_PD_MEM2 Position */
-#define PMC_PDSLEEPCFG_PDEN_PD_MEM2_Msk (0x01UL << PMC_PDSLEEPCFG_PDEN_PD_MEM2_Pos) /*!< PMC PDSLEEPCFG: PDEN_PD_MEM2 Mask */
-#define PMC_PDSLEEPCFG_PDEN_PD_MEM3_Pos 13 /*!< PMC PDSLEEPCFG: PDEN_PD_MEM3 Position */
-#define PMC_PDSLEEPCFG_PDEN_PD_MEM3_Msk (0x01UL << PMC_PDSLEEPCFG_PDEN_PD_MEM3_Pos) /*!< PMC PDSLEEPCFG: PDEN_PD_MEM3 Mask */
-#define PMC_PDSLEEPCFG_PDEN_PD_MEM4_Pos 14 /*!< PMC PDSLEEPCFG: PDEN_PD_MEM4 Position */
-#define PMC_PDSLEEPCFG_PDEN_PD_MEM4_Msk (0x01UL << PMC_PDSLEEPCFG_PDEN_PD_MEM4_Pos) /*!< PMC PDSLEEPCFG: PDEN_PD_MEM4 Mask */
-#define PMC_PDSLEEPCFG_PDEN_PD_MEM5_Pos 15 /*!< PMC PDSLEEPCFG: PDEN_PD_MEM5 Position */
-#define PMC_PDSLEEPCFG_PDEN_PD_MEM5_Msk (0x01UL << PMC_PDSLEEPCFG_PDEN_PD_MEM5_Pos) /*!< PMC PDSLEEPCFG: PDEN_PD_MEM5 Mask */
-#define PMC_PDSLEEPCFG_PDEN_PD_MEM6_Pos 16 /*!< PMC PDSLEEPCFG: PDEN_PD_MEM6 Position */
-#define PMC_PDSLEEPCFG_PDEN_PD_MEM6_Msk (0x01UL << PMC_PDSLEEPCFG_PDEN_PD_MEM6_Pos) /*!< PMC PDSLEEPCFG: PDEN_PD_MEM6 Mask */
-#define PMC_PDSLEEPCFG_PDEN_PD_MEM7_Pos 17 /*!< PMC PDSLEEPCFG: PDEN_PD_MEM7 Position */
-#define PMC_PDSLEEPCFG_PDEN_PD_MEM7_Msk (0x01UL << PMC_PDSLEEPCFG_PDEN_PD_MEM7_Pos) /*!< PMC PDSLEEPCFG: PDEN_PD_MEM7 Mask */
-#define PMC_PDSLEEPCFG_PDEN_PD_MEM8_Pos 18 /*!< PMC PDSLEEPCFG: PDEN_PD_MEM8 Position */
-#define PMC_PDSLEEPCFG_PDEN_PD_MEM8_Msk (0x01UL << PMC_PDSLEEPCFG_PDEN_PD_MEM8_Pos) /*!< PMC PDSLEEPCFG: PDEN_PD_MEM8 Mask */
-#define PMC_PDSLEEPCFG_PDEN_PD_MEM9_Pos 19 /*!< PMC PDSLEEPCFG: PDEN_PD_MEM9 Position */
-#define PMC_PDSLEEPCFG_PDEN_PD_MEM9_Msk (0x01UL << PMC_PDSLEEPCFG_PDEN_PD_MEM9_Pos) /*!< PMC PDSLEEPCFG: PDEN_PD_MEM9 Mask */
-#define PMC_PDSLEEPCFG_PDEN_PD_MEM10_Pos 20 /*!< PMC PDSLEEPCFG: PDEN_PD_MEM10 Position */
-#define PMC_PDSLEEPCFG_PDEN_PD_MEM10_Msk (0x01UL << PMC_PDSLEEPCFG_PDEN_PD_MEM10_Pos) /*!< PMC PDSLEEPCFG: PDEN_PD_MEM10 Mask */
-#define PMC_PDSLEEPCFG_PDEN_PD_MEM11_Pos 21 /*!< PMC PDSLEEPCFG: PDEN_PD_MEM11 Position */
-#define PMC_PDSLEEPCFG_PDEN_PD_MEM11_Msk (0x01UL << PMC_PDSLEEPCFG_PDEN_PD_MEM11_Pos) /*!< PMC PDSLEEPCFG: PDEN_PD_MEM11 Mask */
-
-/* ------------------------------- u_pmc_PDRUNCFG ------------------------------- */
-#define PMC_PDRUNCFG_ENA_LDO_ADC_Pos 22 /*!< PMC PDRUNCFG: ENA_LDO_ADC Position */
-#define PMC_PDRUNCFG_ENA_LDO_ADC_Msk (0x01UL << PMC_PDRUNCFG_ENA_LDO_ADC_Pos) /*!< PMC PDRUNCFG: ENA_LDO_ADC Mask */
-#define PMC_PDRUNCFG_ENA_BOD_MEM_Pos 23 /*!< PMC PDRUNCFG: ENA_BOD_MEM Position */
-#define PMC_PDRUNCFG_ENA_BOD_MEM_Msk (0x01UL << PMC_PDRUNCFG_ENA_BOD_MEM_Pos) /*!< PMC PDRUNCFG: ENA_BOD_MEM Mask */
-#define PMC_PDRUNCFG_ENA_BOD_CORE_Pos 24 /*!< PMC PDRUNCFG: ENA_BOD_CORE Position */
-#define PMC_PDRUNCFG_ENA_BOD_CORE_Msk (0x01UL << PMC_PDRUNCFG_ENA_BOD_CORE_Pos) /*!< PMC PDRUNCFG: ENA_BOD_CORE Mask */
-#define PMC_PDRUNCFG_ENA_FRO32K_Pos 25 /*!< PMC PDRUNCFG: ENA_FRO32K Position */
-#define PMC_PDRUNCFG_ENA_FRO32K_Msk (0x01UL << PMC_PDRUNCFG_ENA_FRO32K_Pos) /*!< PMC PDRUNCFG: ENA_FRO32K Mask */
-#define PMC_PDRUNCFG_ENA_XTAL32K_Pos 26 /*!< PMC PDRUNCFG: ENA_XTAL32K Position */
-#define PMC_PDRUNCFG_ENA_XTAL32K_Msk (0x01UL << PMC_PDRUNCFG_ENA_XTAL32K_Pos) /*!< PMC PDRUNCFG: ENA_XTAL32K Mask */
-#define PMC_PDRUNCFG_ENA_ANA_COMP_Pos 27 /*!< PMC PDRUNCFG: ENA_ANA_COMP Position */
-#define PMC_PDRUNCFG_ENA_ANA_COMP_Msk (0x01UL << PMC_PDRUNCFG_ENA_ANA_COMP_Pos) /*!< PMC PDRUNCFG: ENA_ANA_COMP Mask */
-
-/* ------------------------------ u_pmc_WAKEIOCAUSE ----------------------------- */
-#define PMC_WAKEIOCAUSE_GPIO00_Pos 0 /*!< PMC WAKEIOCAUSE: GPIO00 Position */
-#define PMC_WAKEIOCAUSE_GPIO00_Msk (0x01UL << PMC_WAKEIOCAUSE_GPIO00_Pos) /*!< PMC WAKEIOCAUSE: GPIO00 Mask */
-#define PMC_WAKEIOCAUSE_GPIO01_Pos 1 /*!< PMC WAKEIOCAUSE: GPIO01 Position */
-#define PMC_WAKEIOCAUSE_GPIO01_Msk (0x01UL << PMC_WAKEIOCAUSE_GPIO01_Pos) /*!< PMC WAKEIOCAUSE: GPIO01 Mask */
-#define PMC_WAKEIOCAUSE_GPIO02_Pos 2 /*!< PMC WAKEIOCAUSE: GPIO02 Position */
-#define PMC_WAKEIOCAUSE_GPIO02_Msk (0x01UL << PMC_WAKEIOCAUSE_GPIO02_Pos) /*!< PMC WAKEIOCAUSE: GPIO02 Mask */
-#define PMC_WAKEIOCAUSE_GPIO03_Pos 3 /*!< PMC WAKEIOCAUSE: GPIO03 Position */
-#define PMC_WAKEIOCAUSE_GPIO03_Msk (0x01UL << PMC_WAKEIOCAUSE_GPIO03_Pos) /*!< PMC WAKEIOCAUSE: GPIO03 Mask */
-#define PMC_WAKEIOCAUSE_GPIO04_Pos 4 /*!< PMC WAKEIOCAUSE: GPIO04 Position */
-#define PMC_WAKEIOCAUSE_GPIO04_Msk (0x01UL << PMC_WAKEIOCAUSE_GPIO04_Pos) /*!< PMC WAKEIOCAUSE: GPIO04 Mask */
-#define PMC_WAKEIOCAUSE_GPIO05_Pos 5 /*!< PMC WAKEIOCAUSE: GPIO05 Position */
-#define PMC_WAKEIOCAUSE_GPIO05_Msk (0x01UL << PMC_WAKEIOCAUSE_GPIO05_Pos) /*!< PMC WAKEIOCAUSE: GPIO05 Mask */
-#define PMC_WAKEIOCAUSE_GPIO06_Pos 6 /*!< PMC WAKEIOCAUSE: GPIO06 Position */
-#define PMC_WAKEIOCAUSE_GPIO06_Msk (0x01UL << PMC_WAKEIOCAUSE_GPIO06_Pos) /*!< PMC WAKEIOCAUSE: GPIO06 Mask */
-#define PMC_WAKEIOCAUSE_GPIO07_Pos 7 /*!< PMC WAKEIOCAUSE: GPIO07 Position */
-#define PMC_WAKEIOCAUSE_GPIO07_Msk (0x01UL << PMC_WAKEIOCAUSE_GPIO07_Pos) /*!< PMC WAKEIOCAUSE: GPIO07 Mask */
-#define PMC_WAKEIOCAUSE_GPIO08_Pos 8 /*!< PMC WAKEIOCAUSE: GPIO08 Position */
-#define PMC_WAKEIOCAUSE_GPIO08_Msk (0x01UL << PMC_WAKEIOCAUSE_GPIO08_Pos) /*!< PMC WAKEIOCAUSE: GPIO08 Mask */
-#define PMC_WAKEIOCAUSE_GPIO09_Pos 9 /*!< PMC WAKEIOCAUSE: GPIO09 Position */
-#define PMC_WAKEIOCAUSE_GPIO09_Msk (0x01UL << PMC_WAKEIOCAUSE_GPIO09_Pos) /*!< PMC WAKEIOCAUSE: GPIO09 Mask */
-#define PMC_WAKEIOCAUSE_GPIO10_Pos 10 /*!< PMC WAKEIOCAUSE: GPIO10 Position */
-#define PMC_WAKEIOCAUSE_GPIO10_Msk (0x01UL << PMC_WAKEIOCAUSE_GPIO10_Pos) /*!< PMC WAKEIOCAUSE: GPIO10 Mask */
-#define PMC_WAKEIOCAUSE_GPIO11_Pos 11 /*!< PMC WAKEIOCAUSE: GPIO11 Position */
-#define PMC_WAKEIOCAUSE_GPIO11_Msk (0x01UL << PMC_WAKEIOCAUSE_GPIO11_Pos) /*!< PMC WAKEIOCAUSE: GPIO11 Mask */
-#define PMC_WAKEIOCAUSE_GPIO12_Pos 12 /*!< PMC WAKEIOCAUSE: GPIO12 Position */
-#define PMC_WAKEIOCAUSE_GPIO12_Msk (0x01UL << PMC_WAKEIOCAUSE_GPIO12_Pos) /*!< PMC WAKEIOCAUSE: GPIO12 Mask */
-#define PMC_WAKEIOCAUSE_GPIO13_Pos 13 /*!< PMC WAKEIOCAUSE: GPIO13 Position */
-#define PMC_WAKEIOCAUSE_GPIO13_Msk (0x01UL << PMC_WAKEIOCAUSE_GPIO13_Pos) /*!< PMC WAKEIOCAUSE: GPIO13 Mask */
-#define PMC_WAKEIOCAUSE_GPIO14_Pos 14 /*!< PMC WAKEIOCAUSE: GPIO14 Position */
-#define PMC_WAKEIOCAUSE_GPIO14_Msk (0x01UL << PMC_WAKEIOCAUSE_GPIO14_Pos) /*!< PMC WAKEIOCAUSE: GPIO14 Mask */
-#define PMC_WAKEIOCAUSE_GPIO15_Pos 15 /*!< PMC WAKEIOCAUSE: GPIO15 Position */
-#define PMC_WAKEIOCAUSE_GPIO15_Msk (0x01UL << PMC_WAKEIOCAUSE_GPIO15_Pos) /*!< PMC WAKEIOCAUSE: GPIO15 Mask */
-#define PMC_WAKEIOCAUSE_GPIO16_Pos 16 /*!< PMC WAKEIOCAUSE: GPIO16 Position */
-#define PMC_WAKEIOCAUSE_GPIO16_Msk (0x01UL << PMC_WAKEIOCAUSE_GPIO16_Pos) /*!< PMC WAKEIOCAUSE: GPIO16 Mask */
-#define PMC_WAKEIOCAUSE_GPIO17_Pos 17 /*!< PMC WAKEIOCAUSE: GPIO17 Position */
-#define PMC_WAKEIOCAUSE_GPIO17_Msk (0x01UL << PMC_WAKEIOCAUSE_GPIO17_Pos) /*!< PMC WAKEIOCAUSE: GPIO17 Mask */
-#define PMC_WAKEIOCAUSE_GPIO18_Pos 18 /*!< PMC WAKEIOCAUSE: GPIO18 Position */
-#define PMC_WAKEIOCAUSE_GPIO18_Msk (0x01UL << PMC_WAKEIOCAUSE_GPIO18_Pos) /*!< PMC WAKEIOCAUSE: GPIO18 Mask */
-#define PMC_WAKEIOCAUSE_GPIO19_Pos 19 /*!< PMC WAKEIOCAUSE: GPIO19 Position */
-#define PMC_WAKEIOCAUSE_GPIO19_Msk (0x01UL << PMC_WAKEIOCAUSE_GPIO19_Pos) /*!< PMC WAKEIOCAUSE: GPIO19 Mask */
-#define PMC_WAKEIOCAUSE_GPIO20_Pos 20 /*!< PMC WAKEIOCAUSE: GPIO20 Position */
-#define PMC_WAKEIOCAUSE_GPIO20_Msk (0x01UL << PMC_WAKEIOCAUSE_GPIO20_Pos) /*!< PMC WAKEIOCAUSE: GPIO20 Mask */
-#define PMC_WAKEIOCAUSE_GPIO21_Pos 21 /*!< PMC WAKEIOCAUSE: GPIO21 Position */
-#define PMC_WAKEIOCAUSE_GPIO21_Msk (0x01UL << PMC_WAKEIOCAUSE_GPIO21_Pos) /*!< PMC WAKEIOCAUSE: GPIO21 Mask */
-#define PMC_WAKEIOCAUSE_NTAG_FD_Pos 22 /*!< PMC WAKEIOCAUSE: NTAG_FD Position */
-#define PMC_WAKEIOCAUSE_NTAG_FD_Msk (0x01UL << PMC_WAKEIOCAUSE_NTAG_FD_Pos) /*!< PMC WAKEIOCAUSE: NTAG_FD Mask */
-
-/* -------------------------------- u_pmc_EFUSE0 -------------------------------- */
-#define PMC_EFUSE0_EFUSE0_VAL_Pos 0 /*!< PMC EFUSE0: EFUSE0_VAL Position */
-#define PMC_EFUSE0_EFUSE0_VAL_Msk (0xffffffffUL << PMC_EFUSE0_EFUSE0_VAL_Pos) /*!< PMC EFUSE0: EFUSE0_VAL Mask */
-
-/* -------------------------------- u_pmc_EFUSE1 -------------------------------- */
-#define PMC_EFUSE1_EFUSE1_VAL_Pos 0 /*!< PMC EFUSE1: EFUSE1_VAL Position */
-#define PMC_EFUSE1_EFUSE1_VAL_Msk (0xffffffffUL << PMC_EFUSE1_EFUSE1_VAL_Pos) /*!< PMC EFUSE1: EFUSE1_VAL Mask */
-
-/* -------------------------------- u_pmc_EFUSE2 -------------------------------- */
-#define PMC_EFUSE2_EFUSE2_VAL_Pos 0 /*!< PMC EFUSE2: EFUSE2_VAL Position */
-#define PMC_EFUSE2_EFUSE2_VAL_Msk (0x0000ffffUL << PMC_EFUSE2_EFUSE2_VAL_Pos) /*!< PMC EFUSE2: EFUSE2_VAL Mask */
-
-/* ------------------------------- u_pmc_CTRLNORST ------------------------------ */
-#define PMC_CTRLNORST_FASTLDOENABLE_Pos 0 /*!< PMC CTRLNORST: FASTLDOENABLE Position */
-#define PMC_CTRLNORST_FASTLDOENABLE_Msk (0x07UL << PMC_CTRLNORST_FASTLDOENABLE_Pos) /*!< PMC CTRLNORST: FASTLDOENABLE Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u_ble_dp_top' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* ----------------------- u_ble_dp_top_DP_TOP_SYSTEM_CTRL ---------------------- */
-#define BLEMODEM_DP_TOP_SYSTEM_CTRL_RX_PDU_LEN_IN_Pos 0 /*!< BLEMODEM DP_TOP_SYSTEM_CTRL: RX_PDU_LEN_IN Position */
-#define BLEMODEM_DP_TOP_SYSTEM_CTRL_RX_PDU_LEN_IN_Msk (0x00003fffUL << BLEMODEM_DP_TOP_SYSTEM_CTRL_RX_PDU_LEN_IN_Pos)/*!< BLEMODEM DP_TOP_SYSTEM_CTRL: RX_PDU_LEN_IN Mask */
-#define BLEMODEM_DP_TOP_SYSTEM_CTRL_AA_SEL_Pos 14 /*!< BLEMODEM DP_TOP_SYSTEM_CTRL: AA_SEL Position */
-#define BLEMODEM_DP_TOP_SYSTEM_CTRL_AA_SEL_Msk (0x01UL << BLEMODEM_DP_TOP_SYSTEM_CTRL_AA_SEL_Pos)/*!< BLEMODEM DP_TOP_SYSTEM_CTRL: AA_SEL Mask */
-#define BLEMODEM_DP_TOP_SYSTEM_CTRL_PDU_LEN_SEL_Pos 15 /*!< BLEMODEM DP_TOP_SYSTEM_CTRL: PDU_LEN_SEL Position */
-#define BLEMODEM_DP_TOP_SYSTEM_CTRL_PDU_LEN_SEL_Msk (0x01UL << BLEMODEM_DP_TOP_SYSTEM_CTRL_PDU_LEN_SEL_Pos)/*!< BLEMODEM DP_TOP_SYSTEM_CTRL: PDU_LEN_SEL Mask */
-#define BLEMODEM_DP_TOP_SYSTEM_CTRL_H_IDX_Pos 16 /*!< BLEMODEM DP_TOP_SYSTEM_CTRL: H_IDX Position */
-#define BLEMODEM_DP_TOP_SYSTEM_CTRL_H_IDX_Msk (0x000000ffUL << BLEMODEM_DP_TOP_SYSTEM_CTRL_H_IDX_Pos)/*!< BLEMODEM DP_TOP_SYSTEM_CTRL: H_IDX Mask */
-#define BLEMODEM_DP_TOP_SYSTEM_CTRL_RX_EN_SEL_Pos 24 /*!< BLEMODEM DP_TOP_SYSTEM_CTRL: RX_EN_SEL Position */
-#define BLEMODEM_DP_TOP_SYSTEM_CTRL_RX_EN_SEL_Msk (0x01UL << BLEMODEM_DP_TOP_SYSTEM_CTRL_RX_EN_SEL_Pos)/*!< BLEMODEM DP_TOP_SYSTEM_CTRL: RX_EN_SEL Mask */
-#define BLEMODEM_DP_TOP_SYSTEM_CTRL_TX_EN_SEL_Pos 25 /*!< BLEMODEM DP_TOP_SYSTEM_CTRL: TX_EN_SEL Position */
-#define BLEMODEM_DP_TOP_SYSTEM_CTRL_TX_EN_SEL_Msk (0x01UL << BLEMODEM_DP_TOP_SYSTEM_CTRL_TX_EN_SEL_Pos)/*!< BLEMODEM DP_TOP_SYSTEM_CTRL: TX_EN_SEL Mask */
-#define BLEMODEM_DP_TOP_SYSTEM_CTRL_RX_REQ_Pos 26 /*!< BLEMODEM DP_TOP_SYSTEM_CTRL: RX_REQ Position */
-#define BLEMODEM_DP_TOP_SYSTEM_CTRL_RX_REQ_Msk (0x01UL << BLEMODEM_DP_TOP_SYSTEM_CTRL_RX_REQ_Pos)/*!< BLEMODEM DP_TOP_SYSTEM_CTRL: RX_REQ Mask */
-#define BLEMODEM_DP_TOP_SYSTEM_CTRL_TX_REQ_Pos 27 /*!< BLEMODEM DP_TOP_SYSTEM_CTRL: TX_REQ Position */
-#define BLEMODEM_DP_TOP_SYSTEM_CTRL_TX_REQ_Msk (0x01UL << BLEMODEM_DP_TOP_SYSTEM_CTRL_TX_REQ_Pos)/*!< BLEMODEM DP_TOP_SYSTEM_CTRL: TX_REQ Mask */
-#define BLEMODEM_DP_TOP_SYSTEM_CTRL_RX_MODE_Pos 28 /*!< BLEMODEM DP_TOP_SYSTEM_CTRL: RX_MODE Position */
-#define BLEMODEM_DP_TOP_SYSTEM_CTRL_RX_MODE_Msk (0x03UL << BLEMODEM_DP_TOP_SYSTEM_CTRL_RX_MODE_Pos)/*!< BLEMODEM DP_TOP_SYSTEM_CTRL: RX_MODE Mask */
-#define BLEMODEM_DP_TOP_SYSTEM_CTRL_ANT_DATA_START_Pos 30 /*!< BLEMODEM DP_TOP_SYSTEM_CTRL: ANT_DATA_START Position */
-#define BLEMODEM_DP_TOP_SYSTEM_CTRL_ANT_DATA_START_Msk (0x01UL << BLEMODEM_DP_TOP_SYSTEM_CTRL_ANT_DATA_START_Pos)/*!< BLEMODEM DP_TOP_SYSTEM_CTRL: ANT_DATA_START Mask */
-#define BLEMODEM_DP_TOP_SYSTEM_CTRL_DET_MODE_Pos 31 /*!< BLEMODEM DP_TOP_SYSTEM_CTRL: DET_MODE Position */
-#define BLEMODEM_DP_TOP_SYSTEM_CTRL_DET_MODE_Msk (0x01UL << BLEMODEM_DP_TOP_SYSTEM_CTRL_DET_MODE_Pos)/*!< BLEMODEM DP_TOP_SYSTEM_CTRL: DET_MODE Mask */
-
-/* ------------------------- u_ble_dp_top_PROP_MODE_CTRL ------------------------ */
-#define BLEMODEM_PROP_MODE_CTRL_PROP_MODE_CTRL_Pos 0 /*!< BLEMODEM PROP_MODE_CTRL: PROP_MODE_CTRL Position */
-#define BLEMODEM_PROP_MODE_CTRL_PROP_MODE_CTRL_Msk (0xffffffffUL << BLEMODEM_PROP_MODE_CTRL_PROP_MODE_CTRL_Pos)/*!< BLEMODEM PROP_MODE_CTRL: PROP_MODE_CTRL Mask */
-
-/* ------------------------- u_ble_dp_top_ACCESS_ADDRESS ------------------------ */
-#define BLEMODEM_ACCESS_ADDRESS_AA_ADDR_IN_Pos 0 /*!< BLEMODEM ACCESS_ADDRESS: AA_ADDR_IN Position */
-#define BLEMODEM_ACCESS_ADDRESS_AA_ADDR_IN_Msk (0xffffffffUL << BLEMODEM_ACCESS_ADDRESS_AA_ADDR_IN_Pos)/*!< BLEMODEM ACCESS_ADDRESS: AA_ADDR_IN Mask */
-
-/* ------------------------- u_ble_dp_top_ANT_PDU_DATA0 ------------------------- */
-#define BLEMODEM_ANT_PDU_DATA0_ANT_PDU_DATA0_Pos 0 /*!< BLEMODEM ANT_PDU_DATA0: ANT_PDU_DATA0 Position */
-#define BLEMODEM_ANT_PDU_DATA0_ANT_PDU_DATA0_Msk (0xffffffffUL << BLEMODEM_ANT_PDU_DATA0_ANT_PDU_DATA0_Pos)/*!< BLEMODEM ANT_PDU_DATA0: ANT_PDU_DATA0 Mask */
-
-/* ------------------------- u_ble_dp_top_ANT_PDU_DATA1 ------------------------- */
-#define BLEMODEM_ANT_PDU_DATA1_ANT_PDU_DATA1_Pos 0 /*!< BLEMODEM ANT_PDU_DATA1: ANT_PDU_DATA1 Position */
-#define BLEMODEM_ANT_PDU_DATA1_ANT_PDU_DATA1_Msk (0xffffffffUL << BLEMODEM_ANT_PDU_DATA1_ANT_PDU_DATA1_Pos)/*!< BLEMODEM ANT_PDU_DATA1: ANT_PDU_DATA1 Mask */
-
-/* ------------------------- u_ble_dp_top_ANT_PDU_DATA2 ------------------------- */
-#define BLEMODEM_ANT_PDU_DATA2_ANT_PDU_DATA2_Pos 0 /*!< BLEMODEM ANT_PDU_DATA2: ANT_PDU_DATA2 Position */
-#define BLEMODEM_ANT_PDU_DATA2_ANT_PDU_DATA2_Msk (0xffffffffUL << BLEMODEM_ANT_PDU_DATA2_ANT_PDU_DATA2_Pos)/*!< BLEMODEM ANT_PDU_DATA2: ANT_PDU_DATA2 Mask */
-
-/* ------------------------- u_ble_dp_top_ANT_PDU_DATA3 ------------------------- */
-#define BLEMODEM_ANT_PDU_DATA3_ANT_PDU_DATA3_Pos 0 /*!< BLEMODEM ANT_PDU_DATA3: ANT_PDU_DATA3 Position */
-#define BLEMODEM_ANT_PDU_DATA3_ANT_PDU_DATA3_Msk (0xffffffffUL << BLEMODEM_ANT_PDU_DATA3_ANT_PDU_DATA3_Pos)/*!< BLEMODEM ANT_PDU_DATA3: ANT_PDU_DATA3 Mask */
-
-/* ------------------------- u_ble_dp_top_ANT_PDU_DATA4 ------------------------- */
-#define BLEMODEM_ANT_PDU_DATA4_ANT_PDU_DATA4_Pos 0 /*!< BLEMODEM ANT_PDU_DATA4: ANT_PDU_DATA4 Position */
-#define BLEMODEM_ANT_PDU_DATA4_ANT_PDU_DATA4_Msk (0xffffffffUL << BLEMODEM_ANT_PDU_DATA4_ANT_PDU_DATA4_Pos)/*!< BLEMODEM ANT_PDU_DATA4: ANT_PDU_DATA4 Mask */
-
-/* ------------------------- u_ble_dp_top_ANT_PDU_DATA5 ------------------------- */
-#define BLEMODEM_ANT_PDU_DATA5_ANT_PDU_DATA5_Pos 0 /*!< BLEMODEM ANT_PDU_DATA5: ANT_PDU_DATA5 Position */
-#define BLEMODEM_ANT_PDU_DATA5_ANT_PDU_DATA5_Msk (0xffffffffUL << BLEMODEM_ANT_PDU_DATA5_ANT_PDU_DATA5_Pos)/*!< BLEMODEM ANT_PDU_DATA5: ANT_PDU_DATA5 Mask */
-
-/* ------------------------- u_ble_dp_top_ANT_PDU_DATA6 ------------------------- */
-#define BLEMODEM_ANT_PDU_DATA6_ANT_PDU_DATA6_Pos 0 /*!< BLEMODEM ANT_PDU_DATA6: ANT_PDU_DATA6 Position */
-#define BLEMODEM_ANT_PDU_DATA6_ANT_PDU_DATA6_Msk (0xffffffffUL << BLEMODEM_ANT_PDU_DATA6_ANT_PDU_DATA6_Pos)/*!< BLEMODEM ANT_PDU_DATA6: ANT_PDU_DATA6 Mask */
-
-/* ------------------------- u_ble_dp_top_ANT_PDU_DATA7 ------------------------- */
-#define BLEMODEM_ANT_PDU_DATA7_ANT_PDU_DATA7_Pos 0 /*!< BLEMODEM ANT_PDU_DATA7: ANT_PDU_DATA7 Position */
-#define BLEMODEM_ANT_PDU_DATA7_ANT_PDU_DATA7_Msk (0xffffffffUL << BLEMODEM_ANT_PDU_DATA7_ANT_PDU_DATA7_Pos)/*!< BLEMODEM ANT_PDU_DATA7: ANT_PDU_DATA7 Mask */
-
-/* ---------------------------- u_ble_dp_top_CRC_SEED --------------------------- */
-#define BLEMODEM_CRC_SEED_CRC_SEED_IN_Pos 0 /*!< BLEMODEM CRC_SEED: CRC_SEED_IN Position */
-#define BLEMODEM_CRC_SEED_CRC_SEED_IN_Msk (0x00ffffffUL << BLEMODEM_CRC_SEED_CRC_SEED_IN_Pos) /*!< BLEMODEM CRC_SEED: CRC_SEED_IN Mask */
-#define BLEMODEM_CRC_SEED_CRC_SEED_WEN_Pos 24 /*!< BLEMODEM CRC_SEED: CRC_SEED_WEN Position */
-#define BLEMODEM_CRC_SEED_CRC_SEED_WEN_Msk (0x01UL << BLEMODEM_CRC_SEED_CRC_SEED_WEN_Pos) /*!< BLEMODEM CRC_SEED: CRC_SEED_WEN Mask */
-
-/* ------------------------ u_ble_dp_top_DP_FUNCTION_CTRL ----------------------- */
-#define BLEMODEM_DP_FUNCTION_CTRL_DP_STATISTICS_SEL_Pos 0 /*!< BLEMODEM DP_FUNCTION_CTRL: DP_STATISTICS_SEL Position */
-#define BLEMODEM_DP_FUNCTION_CTRL_DP_STATISTICS_SEL_Msk (0x07UL << BLEMODEM_DP_FUNCTION_CTRL_DP_STATISTICS_SEL_Pos)/*!< BLEMODEM DP_FUNCTION_CTRL: DP_STATISTICS_SEL Mask */
-#define BLEMODEM_DP_FUNCTION_CTRL_CHF_COEF_WEN_Pos 3 /*!< BLEMODEM DP_FUNCTION_CTRL: CHF_COEF_WEN Position */
-#define BLEMODEM_DP_FUNCTION_CTRL_CHF_COEF_WEN_Msk (0x01UL << BLEMODEM_DP_FUNCTION_CTRL_CHF_COEF_WEN_Pos)/*!< BLEMODEM DP_FUNCTION_CTRL: CHF_COEF_WEN Mask */
-#define BLEMODEM_DP_FUNCTION_CTRL_CHF_COEF_IDX_Pos 4 /*!< BLEMODEM DP_FUNCTION_CTRL: CHF_COEF_IDX Position */
-#define BLEMODEM_DP_FUNCTION_CTRL_CHF_COEF_IDX_Msk (0x03UL << BLEMODEM_DP_FUNCTION_CTRL_CHF_COEF_IDX_Pos)/*!< BLEMODEM DP_FUNCTION_CTRL: CHF_COEF_IDX Mask */
-#define BLEMODEM_DP_FUNCTION_CTRL_LP_SNR_LEN_AUTO_Pos 6 /*!< BLEMODEM DP_FUNCTION_CTRL: LP_SNR_LEN_AUTO Position */
-#define BLEMODEM_DP_FUNCTION_CTRL_LP_SNR_LEN_AUTO_Msk (0x01UL << BLEMODEM_DP_FUNCTION_CTRL_LP_SNR_LEN_AUTO_Pos)/*!< BLEMODEM DP_FUNCTION_CTRL: LP_SNR_LEN_AUTO Mask */
-#define BLEMODEM_DP_FUNCTION_CTRL_DOUT_ADJ_DIS_Pos 7 /*!< BLEMODEM DP_FUNCTION_CTRL: DOUT_ADJ_DIS Position */
-#define BLEMODEM_DP_FUNCTION_CTRL_DOUT_ADJ_DIS_Msk (0x01UL << BLEMODEM_DP_FUNCTION_CTRL_DOUT_ADJ_DIS_Pos)/*!< BLEMODEM DP_FUNCTION_CTRL: DOUT_ADJ_DIS Mask */
-#define BLEMODEM_DP_FUNCTION_CTRL_LP_ADJ_MODE_Pos 8 /*!< BLEMODEM DP_FUNCTION_CTRL: LP_ADJ_MODE Position */
-#define BLEMODEM_DP_FUNCTION_CTRL_LP_ADJ_MODE_Msk (0x01UL << BLEMODEM_DP_FUNCTION_CTRL_LP_ADJ_MODE_Pos)/*!< BLEMODEM DP_FUNCTION_CTRL: LP_ADJ_MODE Mask */
-#define BLEMODEM_DP_FUNCTION_CTRL_FR_OFFSET_EN_Pos 9 /*!< BLEMODEM DP_FUNCTION_CTRL: FR_OFFSET_EN Position */
-#define BLEMODEM_DP_FUNCTION_CTRL_FR_OFFSET_EN_Msk (0x01UL << BLEMODEM_DP_FUNCTION_CTRL_FR_OFFSET_EN_Pos)/*!< BLEMODEM DP_FUNCTION_CTRL: FR_OFFSET_EN Mask */
-#define BLEMODEM_DP_FUNCTION_CTRL_DC_AVE_EN_Pos 10 /*!< BLEMODEM DP_FUNCTION_CTRL: DC_AVE_EN Position */
-#define BLEMODEM_DP_FUNCTION_CTRL_DC_AVE_EN_Msk (0x01UL << BLEMODEM_DP_FUNCTION_CTRL_DC_AVE_EN_Pos)/*!< BLEMODEM DP_FUNCTION_CTRL: DC_AVE_EN Mask */
-#define BLEMODEM_DP_FUNCTION_CTRL_FIX_DELAY_EN_Pos 11 /*!< BLEMODEM DP_FUNCTION_CTRL: FIX_DELAY_EN Position */
-#define BLEMODEM_DP_FUNCTION_CTRL_FIX_DELAY_EN_Msk (0x01UL << BLEMODEM_DP_FUNCTION_CTRL_FIX_DELAY_EN_Pos)/*!< BLEMODEM DP_FUNCTION_CTRL: FIX_DELAY_EN Mask */
-#define BLEMODEM_DP_FUNCTION_CTRL_TRACK_LEN_Pos 12 /*!< BLEMODEM DP_FUNCTION_CTRL: TRACK_LEN Position */
-#define BLEMODEM_DP_FUNCTION_CTRL_TRACK_LEN_Msk (0x03UL << BLEMODEM_DP_FUNCTION_CTRL_TRACK_LEN_Pos)/*!< BLEMODEM DP_FUNCTION_CTRL: TRACK_LEN Mask */
-#define BLEMODEM_DP_FUNCTION_CTRL_TRACK_LEN_WEN_Pos 14 /*!< BLEMODEM DP_FUNCTION_CTRL: TRACK_LEN_WEN Position */
-#define BLEMODEM_DP_FUNCTION_CTRL_TRACK_LEN_WEN_Msk (0x01UL << BLEMODEM_DP_FUNCTION_CTRL_TRACK_LEN_WEN_Pos)/*!< BLEMODEM DP_FUNCTION_CTRL: TRACK_LEN_WEN Mask */
-#define BLEMODEM_DP_FUNCTION_CTRL_XCORR_FILT_EN_Pos 16 /*!< BLEMODEM DP_FUNCTION_CTRL: XCORR_FILT_EN Position */
-#define BLEMODEM_DP_FUNCTION_CTRL_XCORR_FILT_EN_Msk (0x01UL << BLEMODEM_DP_FUNCTION_CTRL_XCORR_FILT_EN_Pos)/*!< BLEMODEM DP_FUNCTION_CTRL: XCORR_FILT_EN Mask */
-#define BLEMODEM_DP_FUNCTION_CTRL_XCORR_FULLWIN_EN_Pos 17 /*!< BLEMODEM DP_FUNCTION_CTRL: XCORR_FULLWIN_EN Position */
-#define BLEMODEM_DP_FUNCTION_CTRL_XCORR_FULLWIN_EN_Msk (0x01UL << BLEMODEM_DP_FUNCTION_CTRL_XCORR_FULLWIN_EN_Pos)/*!< BLEMODEM DP_FUNCTION_CTRL: XCORR_FULLWIN_EN Mask */
-#define BLEMODEM_DP_FUNCTION_CTRL_XCORR_AA_LEN_Pos 18 /*!< BLEMODEM DP_FUNCTION_CTRL: XCORR_AA_LEN Position */
-#define BLEMODEM_DP_FUNCTION_CTRL_XCORR_AA_LEN_Msk (0x01UL << BLEMODEM_DP_FUNCTION_CTRL_XCORR_AA_LEN_Pos)/*!< BLEMODEM DP_FUNCTION_CTRL: XCORR_AA_LEN Mask */
-#define BLEMODEM_DP_FUNCTION_CTRL_XCORR_AA_LEN_WEN_Pos 19 /*!< BLEMODEM DP_FUNCTION_CTRL: XCORR_AA_LEN_WEN Position */
-#define BLEMODEM_DP_FUNCTION_CTRL_XCORR_AA_LEN_WEN_Msk (0x01UL << BLEMODEM_DP_FUNCTION_CTRL_XCORR_AA_LEN_WEN_Pos)/*!< BLEMODEM DP_FUNCTION_CTRL: XCORR_AA_LEN_WEN Mask */
-#define BLEMODEM_DP_FUNCTION_CTRL_XCORR_WIN_AUTO_EN_Pos 20 /*!< BLEMODEM DP_FUNCTION_CTRL: XCORR_WIN_AUTO_EN Position */
-#define BLEMODEM_DP_FUNCTION_CTRL_XCORR_WIN_AUTO_EN_Msk (0x01UL << BLEMODEM_DP_FUNCTION_CTRL_XCORR_WIN_AUTO_EN_Pos)/*!< BLEMODEM DP_FUNCTION_CTRL: XCORR_WIN_AUTO_EN Mask */
-#define BLEMODEM_DP_FUNCTION_CTRL_RESAMPLER_TAP_Pos 21 /*!< BLEMODEM DP_FUNCTION_CTRL: RESAMPLER_TAP Position */
-#define BLEMODEM_DP_FUNCTION_CTRL_RESAMPLER_TAP_Msk (0x01UL << BLEMODEM_DP_FUNCTION_CTRL_RESAMPLER_TAP_Pos)/*!< BLEMODEM DP_FUNCTION_CTRL: RESAMPLER_TAP Mask */
-#define BLEMODEM_DP_FUNCTION_CTRL_RESAMPLER_TAP_WEN_Pos 22 /*!< BLEMODEM DP_FUNCTION_CTRL: RESAMPLER_TAP_WEN Position */
-#define BLEMODEM_DP_FUNCTION_CTRL_RESAMPLER_TAP_WEN_Msk (0x01UL << BLEMODEM_DP_FUNCTION_CTRL_RESAMPLER_TAP_WEN_Pos)/*!< BLEMODEM DP_FUNCTION_CTRL: RESAMPLER_TAP_WEN Mask */
-#define BLEMODEM_DP_FUNCTION_CTRL_RESAMPLER_BP_Pos 23 /*!< BLEMODEM DP_FUNCTION_CTRL: RESAMPLER_BP Position */
-#define BLEMODEM_DP_FUNCTION_CTRL_RESAMPLER_BP_Msk (0x01UL << BLEMODEM_DP_FUNCTION_CTRL_RESAMPLER_BP_Pos)/*!< BLEMODEM DP_FUNCTION_CTRL: RESAMPLER_BP Mask */
-#define BLEMODEM_DP_FUNCTION_CTRL_FAGC_WIN_LEN_Pos 24 /*!< BLEMODEM DP_FUNCTION_CTRL: FAGC_WIN_LEN Position */
-#define BLEMODEM_DP_FUNCTION_CTRL_FAGC_WIN_LEN_Msk (0x01UL << BLEMODEM_DP_FUNCTION_CTRL_FAGC_WIN_LEN_Pos)/*!< BLEMODEM DP_FUNCTION_CTRL: FAGC_WIN_LEN Mask */
-#define BLEMODEM_DP_FUNCTION_CTRL_FAGC_WEN_Pos 25 /*!< BLEMODEM DP_FUNCTION_CTRL: FAGC_WEN Position */
-#define BLEMODEM_DP_FUNCTION_CTRL_FAGC_WEN_Msk (0x01UL << BLEMODEM_DP_FUNCTION_CTRL_FAGC_WEN_Pos)/*!< BLEMODEM DP_FUNCTION_CTRL: FAGC_WEN Mask */
-#define BLEMODEM_DP_FUNCTION_CTRL_HP_CFO_EN_Pos 26 /*!< BLEMODEM DP_FUNCTION_CTRL: HP_CFO_EN Position */
-#define BLEMODEM_DP_FUNCTION_CTRL_HP_CFO_EN_Msk (0x01UL << BLEMODEM_DP_FUNCTION_CTRL_HP_CFO_EN_Pos)/*!< BLEMODEM DP_FUNCTION_CTRL: HP_CFO_EN Mask */
-#define BLEMODEM_DP_FUNCTION_CTRL_CFO_TRACK_EN_Pos 27 /*!< BLEMODEM DP_FUNCTION_CTRL: CFO_TRACK_EN Position */
-#define BLEMODEM_DP_FUNCTION_CTRL_CFO_TRACK_EN_Msk (0x01UL << BLEMODEM_DP_FUNCTION_CTRL_CFO_TRACK_EN_Pos)/*!< BLEMODEM DP_FUNCTION_CTRL: CFO_TRACK_EN Mask */
-#define BLEMODEM_DP_FUNCTION_CTRL_CFO_INI_EN_Pos 28 /*!< BLEMODEM DP_FUNCTION_CTRL: CFO_INI_EN Position */
-#define BLEMODEM_DP_FUNCTION_CTRL_CFO_INI_EN_Msk (0x01UL << BLEMODEM_DP_FUNCTION_CTRL_CFO_INI_EN_Pos)/*!< BLEMODEM DP_FUNCTION_CTRL: CFO_INI_EN Mask */
-#define BLEMODEM_DP_FUNCTION_CTRL_ADC_IN_FLIP_Pos 29 /*!< BLEMODEM DP_FUNCTION_CTRL: ADC_IN_FLIP Position */
-#define BLEMODEM_DP_FUNCTION_CTRL_ADC_IN_FLIP_Msk (0x01UL << BLEMODEM_DP_FUNCTION_CTRL_ADC_IN_FLIP_Pos)/*!< BLEMODEM DP_FUNCTION_CTRL: ADC_IN_FLIP Mask */
-#define BLEMODEM_DP_FUNCTION_CTRL_TX_EN_MODE_Pos 30 /*!< BLEMODEM DP_FUNCTION_CTRL: TX_EN_MODE Position */
-#define BLEMODEM_DP_FUNCTION_CTRL_TX_EN_MODE_Msk (0x01UL << BLEMODEM_DP_FUNCTION_CTRL_TX_EN_MODE_Pos)/*!< BLEMODEM DP_FUNCTION_CTRL: TX_EN_MODE Mask */
-#define BLEMODEM_DP_FUNCTION_CTRL_RX_EN_MODE_Pos 31 /*!< BLEMODEM DP_FUNCTION_CTRL: RX_EN_MODE Position */
-#define BLEMODEM_DP_FUNCTION_CTRL_RX_EN_MODE_Msk (0x01UL << BLEMODEM_DP_FUNCTION_CTRL_RX_EN_MODE_Pos)/*!< BLEMODEM DP_FUNCTION_CTRL: RX_EN_MODE Mask */
-
-/* -------------------------- u_ble_dp_top_DP_TEST_CTRL ------------------------- */
-#define BLEMODEM_DP_TEST_CTRL_DP_TEST_CTRL_Pos 0 /*!< BLEMODEM DP_TEST_CTRL: DP_TEST_CTRL Position */
-#define BLEMODEM_DP_TEST_CTRL_DP_TEST_CTRL_Msk (0xffffffffUL << BLEMODEM_DP_TEST_CTRL_DP_TEST_CTRL_Pos)/*!< BLEMODEM DP_TEST_CTRL: DP_TEST_CTRL Mask */
-
-/* ------------------------- u_ble_dp_top_BLE_DP_STATUS1 ------------------------ */
-#define BLEMODEM_BLE_DP_STATUS1_SNR_EST_Pos 0 /*!< BLEMODEM BLE_DP_STATUS1: SNR_EST Position */
-#define BLEMODEM_BLE_DP_STATUS1_SNR_EST_Msk (0x000000ffUL << BLEMODEM_BLE_DP_STATUS1_SNR_EST_Pos)/*!< BLEMODEM BLE_DP_STATUS1: SNR_EST Mask */
-#define BLEMODEM_BLE_DP_STATUS1_CNR_EST_Pos 8 /*!< BLEMODEM BLE_DP_STATUS1: CNR_EST Position */
-#define BLEMODEM_BLE_DP_STATUS1_CNR_EST_Msk (0x3fUL << BLEMODEM_BLE_DP_STATUS1_CNR_EST_Pos) /*!< BLEMODEM BLE_DP_STATUS1: CNR_EST Mask */
-#define BLEMODEM_BLE_DP_STATUS1_AGC_RSSI_Pos 16 /*!< BLEMODEM BLE_DP_STATUS1: AGC_RSSI Position */
-#define BLEMODEM_BLE_DP_STATUS1_AGC_RSSI_Msk (0x000000ffUL << BLEMODEM_BLE_DP_STATUS1_AGC_RSSI_Pos)/*!< BLEMODEM BLE_DP_STATUS1: AGC_RSSI Mask */
-#define BLEMODEM_BLE_DP_STATUS1_AGC_RSSI_READY_Pos 24 /*!< BLEMODEM BLE_DP_STATUS1: AGC_RSSI_READY Position */
-#define BLEMODEM_BLE_DP_STATUS1_AGC_RSSI_READY_Msk (0x01UL << BLEMODEM_BLE_DP_STATUS1_AGC_RSSI_READY_Pos)/*!< BLEMODEM BLE_DP_STATUS1: AGC_RSSI_READY Mask */
-#define BLEMODEM_BLE_DP_STATUS1_SNR_VLD_Pos 25 /*!< BLEMODEM BLE_DP_STATUS1: SNR_VLD Position */
-#define BLEMODEM_BLE_DP_STATUS1_SNR_VLD_Msk (0x01UL << BLEMODEM_BLE_DP_STATUS1_SNR_VLD_Pos) /*!< BLEMODEM BLE_DP_STATUS1: SNR_VLD Mask */
-#define BLEMODEM_BLE_DP_STATUS1_CNR_VLD_Pos 26 /*!< BLEMODEM BLE_DP_STATUS1: CNR_VLD Position */
-#define BLEMODEM_BLE_DP_STATUS1_CNR_VLD_Msk (0x01UL << BLEMODEM_BLE_DP_STATUS1_CNR_VLD_Pos) /*!< BLEMODEM BLE_DP_STATUS1: CNR_VLD Mask */
-#define BLEMODEM_BLE_DP_STATUS1_TX_BUSY_Pos 27 /*!< BLEMODEM BLE_DP_STATUS1: TX_BUSY Position */
-#define BLEMODEM_BLE_DP_STATUS1_TX_BUSY_Msk (0x01UL << BLEMODEM_BLE_DP_STATUS1_TX_BUSY_Pos) /*!< BLEMODEM BLE_DP_STATUS1: TX_BUSY Mask */
-
-/* ------------------------- u_ble_dp_top_BLE_DP_STATUS2 ------------------------ */
-#define BLEMODEM_BLE_DP_STATUS2_VALID_PCK_NUM_Pos 0 /*!< BLEMODEM BLE_DP_STATUS2: VALID_PCK_NUM Position */
-#define BLEMODEM_BLE_DP_STATUS2_VALID_PCK_NUM_Msk (0x0000ffffUL << BLEMODEM_BLE_DP_STATUS2_VALID_PCK_NUM_Pos)/*!< BLEMODEM BLE_DP_STATUS2: VALID_PCK_NUM Mask */
-#define BLEMODEM_BLE_DP_STATUS2_AA_ERR_NUM_Pos 16 /*!< BLEMODEM BLE_DP_STATUS2: AA_ERR_NUM Position */
-#define BLEMODEM_BLE_DP_STATUS2_AA_ERR_NUM_Msk (0x3fUL << BLEMODEM_BLE_DP_STATUS2_AA_ERR_NUM_Pos)/*!< BLEMODEM BLE_DP_STATUS2: AA_ERR_NUM Mask */
-#define BLEMODEM_BLE_DP_STATUS2_CRC_ERROR_Pos 29 /*!< BLEMODEM BLE_DP_STATUS2: CRC_ERROR Position */
-#define BLEMODEM_BLE_DP_STATUS2_CRC_ERROR_Msk (0x01UL << BLEMODEM_BLE_DP_STATUS2_CRC_ERROR_Pos)/*!< BLEMODEM BLE_DP_STATUS2: CRC_ERROR Mask */
-#define BLEMODEM_BLE_DP_STATUS2_BURST_DET_Pos 30 /*!< BLEMODEM BLE_DP_STATUS2: BURST_DET Position */
-#define BLEMODEM_BLE_DP_STATUS2_BURST_DET_Msk (0x01UL << BLEMODEM_BLE_DP_STATUS2_BURST_DET_Pos)/*!< BLEMODEM BLE_DP_STATUS2: BURST_DET Mask */
-#define BLEMODEM_BLE_DP_STATUS2_DP_STATUS_VLD_0_Pos 31 /*!< BLEMODEM BLE_DP_STATUS2: DP_STATUS_VLD_0 Position */
-#define BLEMODEM_BLE_DP_STATUS2_DP_STATUS_VLD_0_Msk (0x01UL << BLEMODEM_BLE_DP_STATUS2_DP_STATUS_VLD_0_Pos)/*!< BLEMODEM BLE_DP_STATUS2: DP_STATUS_VLD_0 Mask */
-
-/* ------------------------- u_ble_dp_top_BLE_DP_STATUS3 ------------------------ */
-#define BLEMODEM_BLE_DP_STATUS3_FD_CFO_TRACK_Pos 0 /*!< BLEMODEM BLE_DP_STATUS3: FD_CFO_TRACK Position */
-#define BLEMODEM_BLE_DP_STATUS3_FD_CFO_TRACK_Msk (0x000007ffUL << BLEMODEM_BLE_DP_STATUS3_FD_CFO_TRACK_Pos)/*!< BLEMODEM BLE_DP_STATUS3: FD_CFO_TRACK Mask */
-#define BLEMODEM_BLE_DP_STATUS3_CFO_EST_FD_Pos 16 /*!< BLEMODEM BLE_DP_STATUS3: CFO_EST_FD Position */
-#define BLEMODEM_BLE_DP_STATUS3_CFO_EST_FD_Msk (0x000007ffUL << BLEMODEM_BLE_DP_STATUS3_CFO_EST_FD_Pos)/*!< BLEMODEM BLE_DP_STATUS3: CFO_EST_FD Mask */
-
-/* ------------------------- u_ble_dp_top_BLE_DP_STATUS4 ------------------------ */
-#define BLEMODEM_BLE_DP_STATUS4_RESAMPLER_PH_Pos 0 /*!< BLEMODEM BLE_DP_STATUS4: RESAMPLER_PH Position */
-#define BLEMODEM_BLE_DP_STATUS4_RESAMPLER_PH_Msk (0x000003ffUL << BLEMODEM_BLE_DP_STATUS4_RESAMPLER_PH_Pos)/*!< BLEMODEM BLE_DP_STATUS4: RESAMPLER_PH Mask */
-#define BLEMODEM_BLE_DP_STATUS4_HP_CFO_Pos 16 /*!< BLEMODEM BLE_DP_STATUS4: HP_CFO Position */
-#define BLEMODEM_BLE_DP_STATUS4_HP_CFO_Msk (0x00000fffUL << BLEMODEM_BLE_DP_STATUS4_HP_CFO_Pos)/*!< BLEMODEM BLE_DP_STATUS4: HP_CFO Mask */
-#define BLEMODEM_BLE_DP_STATUS4_HP_CFO_VLD_Pos 31 /*!< BLEMODEM BLE_DP_STATUS4: HP_CFO_VLD Position */
-#define BLEMODEM_BLE_DP_STATUS4_HP_CFO_VLD_Msk (0x01UL << BLEMODEM_BLE_DP_STATUS4_HP_CFO_VLD_Pos)/*!< BLEMODEM BLE_DP_STATUS4: HP_CFO_VLD Mask */
-
-/* ----------------------- u_ble_dp_top_RX_FRONT_END_CTRL1 ---------------------- */
-#define BLEMODEM_RX_FRONT_END_CTRL1_CFO_COMP_Pos 0 /*!< BLEMODEM RX_FRONT_END_CTRL1: CFO_COMP Position */
-#define BLEMODEM_RX_FRONT_END_CTRL1_CFO_COMP_Msk (0x00007fffUL << BLEMODEM_RX_FRONT_END_CTRL1_CFO_COMP_Pos)/*!< BLEMODEM RX_FRONT_END_CTRL1: CFO_COMP Mask */
-#define BLEMODEM_RX_FRONT_END_CTRL1_DCNOTCH_GIN_Pos 16 /*!< BLEMODEM RX_FRONT_END_CTRL1: DCNOTCH_GIN Position */
-#define BLEMODEM_RX_FRONT_END_CTRL1_DCNOTCH_GIN_Msk (0x03UL << BLEMODEM_RX_FRONT_END_CTRL1_DCNOTCH_GIN_Pos)/*!< BLEMODEM RX_FRONT_END_CTRL1: DCNOTCH_GIN Mask */
-
-/* ----------------------- u_ble_dp_top_RX_FRONT_END_CTRL2 ---------------------- */
-#define BLEMODEM_RX_FRONT_END_CTRL2_FAGC_GAIN_Pos 0 /*!< BLEMODEM RX_FRONT_END_CTRL2: FAGC_GAIN Position */
-#define BLEMODEM_RX_FRONT_END_CTRL2_FAGC_GAIN_Msk (0x000007ffUL << BLEMODEM_RX_FRONT_END_CTRL2_FAGC_GAIN_Pos)/*!< BLEMODEM RX_FRONT_END_CTRL2: FAGC_GAIN Mask */
-#define BLEMODEM_RX_FRONT_END_CTRL2_FAGC_INI_VAL_Pos 11 /*!< BLEMODEM RX_FRONT_END_CTRL2: FAGC_INI_VAL Position */
-#define BLEMODEM_RX_FRONT_END_CTRL2_FAGC_INI_VAL_Msk (0x01UL << BLEMODEM_RX_FRONT_END_CTRL2_FAGC_INI_VAL_Pos)/*!< BLEMODEM RX_FRONT_END_CTRL2: FAGC_INI_VAL Mask */
-#define BLEMODEM_RX_FRONT_END_CTRL2_CNR_IDX_DELTA_Pos 12 /*!< BLEMODEM RX_FRONT_END_CTRL2: CNR_IDX_DELTA Position */
-#define BLEMODEM_RX_FRONT_END_CTRL2_CNR_IDX_DELTA_Msk (0x0fUL << BLEMODEM_RX_FRONT_END_CTRL2_CNR_IDX_DELTA_Pos)/*!< BLEMODEM RX_FRONT_END_CTRL2: CNR_IDX_DELTA Mask */
-#define BLEMODEM_RX_FRONT_END_CTRL2_FAGC_REF_Pos 16 /*!< BLEMODEM RX_FRONT_END_CTRL2: FAGC_REF Position */
-#define BLEMODEM_RX_FRONT_END_CTRL2_FAGC_REF_Msk (0x000000ffUL << BLEMODEM_RX_FRONT_END_CTRL2_FAGC_REF_Pos)/*!< BLEMODEM RX_FRONT_END_CTRL2: FAGC_REF Mask */
-#define BLEMODEM_RX_FRONT_END_CTRL2_CORDIC_MIN_VIN_TH_Pos 24 /*!< BLEMODEM RX_FRONT_END_CTRL2: CORDIC_MIN_VIN_TH Position */
-#define BLEMODEM_RX_FRONT_END_CTRL2_CORDIC_MIN_VIN_TH_Msk (0x0fUL << BLEMODEM_RX_FRONT_END_CTRL2_CORDIC_MIN_VIN_TH_Pos)/*!< BLEMODEM RX_FRONT_END_CTRL2: CORDIC_MIN_VIN_TH Mask */
-#define BLEMODEM_RX_FRONT_END_CTRL2_FREQ_TRADE_EN_Pos 28 /*!< BLEMODEM RX_FRONT_END_CTRL2: FREQ_TRADE_EN Position */
-#define BLEMODEM_RX_FRONT_END_CTRL2_FREQ_TRADE_EN_Msk (0x01UL << BLEMODEM_RX_FRONT_END_CTRL2_FREQ_TRADE_EN_Pos)/*!< BLEMODEM RX_FRONT_END_CTRL2: FREQ_TRADE_EN Mask */
-#define BLEMODEM_RX_FRONT_END_CTRL2_CHN_SHIFT_Pos 29 /*!< BLEMODEM RX_FRONT_END_CTRL2: CHN_SHIFT Position */
-#define BLEMODEM_RX_FRONT_END_CTRL2_CHN_SHIFT_Msk (0x07UL << BLEMODEM_RX_FRONT_END_CTRL2_CHN_SHIFT_Pos)/*!< BLEMODEM RX_FRONT_END_CTRL2: CHN_SHIFT Mask */
-
-/* ----------------------- u_ble_dp_top_FREQ_DOMAIN_CTRL1 ----------------------- */
-#define BLEMODEM_FREQ_DOMAIN_CTRL1_SYNC_WORD_IN0_Pos 0 /*!< BLEMODEM FREQ_DOMAIN_CTRL1: SYNC_WORD_IN0 Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL1_SYNC_WORD_IN0_Msk (0x000000ffUL << BLEMODEM_FREQ_DOMAIN_CTRL1_SYNC_WORD_IN0_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL1: SYNC_WORD_IN0 Mask */
-#define BLEMODEM_FREQ_DOMAIN_CTRL1_SYNC_WORD_WEN_Pos 8 /*!< BLEMODEM FREQ_DOMAIN_CTRL1: SYNC_WORD_WEN Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL1_SYNC_WORD_WEN_Msk (0x01UL << BLEMODEM_FREQ_DOMAIN_CTRL1_SYNC_WORD_WEN_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL1: SYNC_WORD_WEN Mask */
-#define BLEMODEM_FREQ_DOMAIN_CTRL1_SYNC_P_SEL_Pos 15 /*!< BLEMODEM FREQ_DOMAIN_CTRL1: SYNC_P_SEL Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL1_SYNC_P_SEL_Msk (0x01UL << BLEMODEM_FREQ_DOMAIN_CTRL1_SYNC_P_SEL_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL1: SYNC_P_SEL Mask */
-#define BLEMODEM_FREQ_DOMAIN_CTRL1_RD_EXBIT_EN_Pos 16 /*!< BLEMODEM FREQ_DOMAIN_CTRL1: RD_EXBIT_EN Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL1_RD_EXBIT_EN_Msk (0x01UL << BLEMODEM_FREQ_DOMAIN_CTRL1_RD_EXBIT_EN_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL1: RD_EXBIT_EN Mask */
-#define BLEMODEM_FREQ_DOMAIN_CTRL1_RFAGC_TRACK_DLY_Pos 17 /*!< BLEMODEM FREQ_DOMAIN_CTRL1: RFAGC_TRACK_DLY Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL1_RFAGC_TRACK_DLY_Msk (0x07UL << BLEMODEM_FREQ_DOMAIN_CTRL1_RFAGC_TRACK_DLY_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL1: RFAGC_TRACK_DLY Mask */
-#define BLEMODEM_FREQ_DOMAIN_CTRL1_PROP_DF_16US_Pos 24 /*!< BLEMODEM FREQ_DOMAIN_CTRL1: PROP_DF_16US Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL1_PROP_DF_16US_Msk (0x000000ffUL << BLEMODEM_FREQ_DOMAIN_CTRL1_PROP_DF_16US_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL1: PROP_DF_16US Mask */
-
-/* ----------------------- u_ble_dp_top_FREQ_DOMAIN_CTRL2 ----------------------- */
-#define BLEMODEM_FREQ_DOMAIN_CTRL2_SYNC_WORD_IN1_Pos 0 /*!< BLEMODEM FREQ_DOMAIN_CTRL2: SYNC_WORD_IN1 Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL2_SYNC_WORD_IN1_Msk (0xffffffffUL << BLEMODEM_FREQ_DOMAIN_CTRL2_SYNC_WORD_IN1_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL2: SYNC_WORD_IN1 Mask */
-
-/* ----------------------- u_ble_dp_top_FREQ_DOMAIN_CTRL3 ----------------------- */
-#define BLEMODEM_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH3_Pos 0 /*!< BLEMODEM FREQ_DOMAIN_CTRL3: XCORR_PAR_TH3 Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH3_Msk (0x3fUL << BLEMODEM_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH3_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL3: XCORR_PAR_TH3 Mask */
-#define BLEMODEM_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH2_Pos 8 /*!< BLEMODEM FREQ_DOMAIN_CTRL3: XCORR_PAR_TH2 Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH2_Msk (0x3fUL << BLEMODEM_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH2_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL3: XCORR_PAR_TH2 Mask */
-#define BLEMODEM_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH1_Pos 16 /*!< BLEMODEM FREQ_DOMAIN_CTRL3: XCORR_PAR_TH1 Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH1_Msk (0x3fUL << BLEMODEM_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH1_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL3: XCORR_PAR_TH1 Mask */
-#define BLEMODEM_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH0_Pos 24 /*!< BLEMODEM FREQ_DOMAIN_CTRL3: XCORR_PAR_TH0 Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH0_Msk (0x3fUL << BLEMODEM_FREQ_DOMAIN_CTRL3_XCORR_PAR_TH0_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL3: XCORR_PAR_TH0 Mask */
-
-/* ----------------------- u_ble_dp_top_FREQ_DOMAIN_CTRL4 ----------------------- */
-#define BLEMODEM_FREQ_DOMAIN_CTRL4_XCORR_POW_TH3_Pos 0 /*!< BLEMODEM FREQ_DOMAIN_CTRL4: XCORR_POW_TH3 Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL4_XCORR_POW_TH3_Msk (0x3fUL << BLEMODEM_FREQ_DOMAIN_CTRL4_XCORR_POW_TH3_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL4: XCORR_POW_TH3 Mask */
-#define BLEMODEM_FREQ_DOMAIN_CTRL4_XCORR_POW_TH2_Pos 8 /*!< BLEMODEM FREQ_DOMAIN_CTRL4: XCORR_POW_TH2 Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL4_XCORR_POW_TH2_Msk (0x3fUL << BLEMODEM_FREQ_DOMAIN_CTRL4_XCORR_POW_TH2_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL4: XCORR_POW_TH2 Mask */
-#define BLEMODEM_FREQ_DOMAIN_CTRL4_XCORR_POW_TH1_Pos 16 /*!< BLEMODEM FREQ_DOMAIN_CTRL4: XCORR_POW_TH1 Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL4_XCORR_POW_TH1_Msk (0x3fUL << BLEMODEM_FREQ_DOMAIN_CTRL4_XCORR_POW_TH1_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL4: XCORR_POW_TH1 Mask */
-#define BLEMODEM_FREQ_DOMAIN_CTRL4_XCORR_POW_TH0_Pos 24 /*!< BLEMODEM FREQ_DOMAIN_CTRL4: XCORR_POW_TH0 Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL4_XCORR_POW_TH0_Msk (0x3fUL << BLEMODEM_FREQ_DOMAIN_CTRL4_XCORR_POW_TH0_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL4: XCORR_POW_TH0 Mask */
-
-/* ----------------------- u_ble_dp_top_FREQ_DOMAIN_CTRL5 ----------------------- */
-#define BLEMODEM_FREQ_DOMAIN_CTRL5_GAIN_TED_Pos 0 /*!< BLEMODEM FREQ_DOMAIN_CTRL5: GAIN_TED Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL5_GAIN_TED_Msk (0x03UL << BLEMODEM_FREQ_DOMAIN_CTRL5_GAIN_TED_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL5: GAIN_TED Mask */
-#define BLEMODEM_FREQ_DOMAIN_CTRL5_SYNC_DIN_SAT_VALUE_Pos 4 /*!< BLEMODEM FREQ_DOMAIN_CTRL5: SYNC_DIN_SAT_VALUE Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL5_SYNC_DIN_SAT_VALUE_Msk (0x07UL << BLEMODEM_FREQ_DOMAIN_CTRL5_SYNC_DIN_SAT_VALUE_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL5: SYNC_DIN_SAT_VALUE Mask */
-#define BLEMODEM_FREQ_DOMAIN_CTRL5_SYNC_DIN_SAT_EN_Pos 7 /*!< BLEMODEM FREQ_DOMAIN_CTRL5: SYNC_DIN_SAT_EN Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL5_SYNC_DIN_SAT_EN_Msk (0x01UL << BLEMODEM_FREQ_DOMAIN_CTRL5_SYNC_DIN_SAT_EN_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL5: SYNC_DIN_SAT_EN Mask */
-#define BLEMODEM_FREQ_DOMAIN_CTRL5_CNT_SETTLE_IDX_Pos 8 /*!< BLEMODEM FREQ_DOMAIN_CTRL5: CNT_SETTLE_IDX Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL5_CNT_SETTLE_IDX_Msk (0x07UL << BLEMODEM_FREQ_DOMAIN_CTRL5_CNT_SETTLE_IDX_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL5: CNT_SETTLE_IDX Mask */
-#define BLEMODEM_FREQ_DOMAIN_CTRL5_TRIG_XCORR_CNT_Pos 12 /*!< BLEMODEM FREQ_DOMAIN_CTRL5: TRIG_XCORR_CNT Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL5_TRIG_XCORR_CNT_Msk (0x0fUL << BLEMODEM_FREQ_DOMAIN_CTRL5_TRIG_XCORR_CNT_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL5: TRIG_XCORR_CNT Mask */
-#define BLEMODEM_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH3_Pos 16 /*!< BLEMODEM FREQ_DOMAIN_CTRL5: XCORR_RSSI_TH3 Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH3_Msk (0x0fUL << BLEMODEM_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH3_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL5: XCORR_RSSI_TH3 Mask */
-#define BLEMODEM_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH2_Pos 20 /*!< BLEMODEM FREQ_DOMAIN_CTRL5: XCORR_RSSI_TH2 Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH2_Msk (0x0fUL << BLEMODEM_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH2_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL5: XCORR_RSSI_TH2 Mask */
-#define BLEMODEM_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH1_Pos 24 /*!< BLEMODEM FREQ_DOMAIN_CTRL5: XCORR_RSSI_TH1 Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH1_Msk (0x0fUL << BLEMODEM_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH1_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL5: XCORR_RSSI_TH1 Mask */
-#define BLEMODEM_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH0_Pos 28 /*!< BLEMODEM FREQ_DOMAIN_CTRL5: XCORR_RSSI_TH0 Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH0_Msk (0x0fUL << BLEMODEM_FREQ_DOMAIN_CTRL5_XCORR_RSSI_TH0_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL5: XCORR_RSSI_TH0 Mask */
-
-/* ----------------------- u_ble_dp_top_FREQ_DOMAIN_CTRL6 ----------------------- */
-#define BLEMODEM_FREQ_DOMAIN_CTRL6_HP_TRAIN_SIZ_Pos 0 /*!< BLEMODEM FREQ_DOMAIN_CTRL6: HP_TRAIN_SIZ Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL6_HP_TRAIN_SIZ_Msk (0x1fUL << BLEMODEM_FREQ_DOMAIN_CTRL6_HP_TRAIN_SIZ_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL6: HP_TRAIN_SIZ Mask */
-#define BLEMODEM_FREQ_DOMAIN_CTRL6_HP_HIDX_GAIN_Pos 8 /*!< BLEMODEM FREQ_DOMAIN_CTRL6: HP_HIDX_GAIN Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL6_HP_HIDX_GAIN_Msk (0x000000ffUL << BLEMODEM_FREQ_DOMAIN_CTRL6_HP_HIDX_GAIN_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL6: HP_HIDX_GAIN Mask */
-#define BLEMODEM_FREQ_DOMAIN_CTRL6_H_REF_GAIN_Pos 16 /*!< BLEMODEM FREQ_DOMAIN_CTRL6: H_REF_GAIN Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL6_H_REF_GAIN_Msk (0x3fUL << BLEMODEM_FREQ_DOMAIN_CTRL6_H_REF_GAIN_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL6: H_REF_GAIN Mask */
-#define BLEMODEM_FREQ_DOMAIN_CTRL6_DET_FR_IDX_Pos 24 /*!< BLEMODEM FREQ_DOMAIN_CTRL6: DET_FR_IDX Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL6_DET_FR_IDX_Msk (0x03UL << BLEMODEM_FREQ_DOMAIN_CTRL6_DET_FR_IDX_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL6: DET_FR_IDX Mask */
-#define BLEMODEM_FREQ_DOMAIN_CTRL6_CFO_FR_IDX_Pos 28 /*!< BLEMODEM FREQ_DOMAIN_CTRL6: CFO_FR_IDX Position */
-#define BLEMODEM_FREQ_DOMAIN_CTRL6_CFO_FR_IDX_Msk (0x03UL << BLEMODEM_FREQ_DOMAIN_CTRL6_CFO_FR_IDX_Pos)/*!< BLEMODEM FREQ_DOMAIN_CTRL6: CFO_FR_IDX Mask */
-
-/* ------------------------- u_ble_dp_top_HP_MODE_CTRL1 ------------------------- */
-#define BLEMODEM_HP_MODE_CTRL1_HP_BMC_P_TRACK_Pos 0 /*!< BLEMODEM HP_MODE_CTRL1: HP_BMC_P_TRACK Position */
-#define BLEMODEM_HP_MODE_CTRL1_HP_BMC_P_TRACK_Msk (0x3fUL << BLEMODEM_HP_MODE_CTRL1_HP_BMC_P_TRACK_Pos)/*!< BLEMODEM HP_MODE_CTRL1: HP_BMC_P_TRACK Mask */
-#define BLEMODEM_HP_MODE_CTRL1_HP_BMC_P_TRAIN_Pos 8 /*!< BLEMODEM HP_MODE_CTRL1: HP_BMC_P_TRAIN Position */
-#define BLEMODEM_HP_MODE_CTRL1_HP_BMC_P_TRAIN_Msk (0x3fUL << BLEMODEM_HP_MODE_CTRL1_HP_BMC_P_TRAIN_Pos)/*!< BLEMODEM HP_MODE_CTRL1: HP_BMC_P_TRAIN Mask */
-#define BLEMODEM_HP_MODE_CTRL1_HP_BMC_CZ1_Pos 16 /*!< BLEMODEM HP_MODE_CTRL1: HP_BMC_CZ1 Position */
-#define BLEMODEM_HP_MODE_CTRL1_HP_BMC_CZ1_Msk (0x3fUL << BLEMODEM_HP_MODE_CTRL1_HP_BMC_CZ1_Pos)/*!< BLEMODEM HP_MODE_CTRL1: HP_BMC_CZ1 Mask */
-#define BLEMODEM_HP_MODE_CTRL1_BUF_IDX_DELTA_Pos 24 /*!< BLEMODEM HP_MODE_CTRL1: BUF_IDX_DELTA Position */
-#define BLEMODEM_HP_MODE_CTRL1_BUF_IDX_DELTA_Msk (0x0fUL << BLEMODEM_HP_MODE_CTRL1_BUF_IDX_DELTA_Pos)/*!< BLEMODEM HP_MODE_CTRL1: BUF_IDX_DELTA Mask */
-#define BLEMODEM_HP_MODE_CTRL1_WMF2_DSAMP_IDX_Pos 28 /*!< BLEMODEM HP_MODE_CTRL1: WMF2_DSAMP_IDX Position */
-#define BLEMODEM_HP_MODE_CTRL1_WMF2_DSAMP_IDX_Msk (0x07UL << BLEMODEM_HP_MODE_CTRL1_WMF2_DSAMP_IDX_Pos)/*!< BLEMODEM HP_MODE_CTRL1: WMF2_DSAMP_IDX Mask */
-#define BLEMODEM_HP_MODE_CTRL1_HP_TRAIN_SIZ_FIX_Pos 31 /*!< BLEMODEM HP_MODE_CTRL1: HP_TRAIN_SIZ_FIX Position */
-#define BLEMODEM_HP_MODE_CTRL1_HP_TRAIN_SIZ_FIX_Msk (0x01UL << BLEMODEM_HP_MODE_CTRL1_HP_TRAIN_SIZ_FIX_Pos)/*!< BLEMODEM HP_MODE_CTRL1: HP_TRAIN_SIZ_FIX Mask */
-
-/* ------------------------- u_ble_dp_top_HP_MODE_CTRL2 ------------------------- */
-#define BLEMODEM_HP_MODE_CTRL2_SNR_EST_REF_Pos 0 /*!< BLEMODEM HP_MODE_CTRL2: SNR_EST_REF Position */
-#define BLEMODEM_HP_MODE_CTRL2_SNR_EST_REF_Msk (0x000000ffUL << BLEMODEM_HP_MODE_CTRL2_SNR_EST_REF_Pos)/*!< BLEMODEM HP_MODE_CTRL2: SNR_EST_REF Mask */
-#define BLEMODEM_HP_MODE_CTRL2_SNR_EST_LEN_Pos 8 /*!< BLEMODEM HP_MODE_CTRL2: SNR_EST_LEN Position */
-#define BLEMODEM_HP_MODE_CTRL2_SNR_EST_LEN_Msk (0x03UL << BLEMODEM_HP_MODE_CTRL2_SNR_EST_LEN_Pos)/*!< BLEMODEM HP_MODE_CTRL2: SNR_EST_LEN Mask */
-#define BLEMODEM_HP_MODE_CTRL2_SNR_EST_EN_Pos 12 /*!< BLEMODEM HP_MODE_CTRL2: SNR_EST_EN Position */
-#define BLEMODEM_HP_MODE_CTRL2_SNR_EST_EN_Msk (0x01UL << BLEMODEM_HP_MODE_CTRL2_SNR_EST_EN_Pos)/*!< BLEMODEM HP_MODE_CTRL2: SNR_EST_EN Mask */
-#define BLEMODEM_HP_MODE_CTRL2_HP_BMC_Q_TRACK_Pos 16 /*!< BLEMODEM HP_MODE_CTRL2: HP_BMC_Q_TRACK Position */
-#define BLEMODEM_HP_MODE_CTRL2_HP_BMC_Q_TRACK_Msk (0x000000ffUL << BLEMODEM_HP_MODE_CTRL2_HP_BMC_Q_TRACK_Pos)/*!< BLEMODEM HP_MODE_CTRL2: HP_BMC_Q_TRACK Mask */
-#define BLEMODEM_HP_MODE_CTRL2_HP_BMC_Q_TRAIN_Pos 24 /*!< BLEMODEM HP_MODE_CTRL2: HP_BMC_Q_TRAIN Position */
-#define BLEMODEM_HP_MODE_CTRL2_HP_BMC_Q_TRAIN_Msk (0x000000ffUL << BLEMODEM_HP_MODE_CTRL2_HP_BMC_Q_TRAIN_Pos)/*!< BLEMODEM HP_MODE_CTRL2: HP_BMC_Q_TRAIN Mask */
-
-/* ---------------------- u_ble_dp_top_FREQ_DOMAIN_STATUS1 ---------------------- */
-#define BLEMODEM_FREQ_DOMAIN_STATUS1_MAX_XCORR_Pos 0 /*!< BLEMODEM FREQ_DOMAIN_STATUS1: MAX_XCORR Position */
-#define BLEMODEM_FREQ_DOMAIN_STATUS1_MAX_XCORR_Msk (0x000003ffUL << BLEMODEM_FREQ_DOMAIN_STATUS1_MAX_XCORR_Pos)/*!< BLEMODEM FREQ_DOMAIN_STATUS1: MAX_XCORR Mask */
-#define BLEMODEM_FREQ_DOMAIN_STATUS1_PKT_OFFSET_COM_Pos 16 /*!< BLEMODEM FREQ_DOMAIN_STATUS1: PKT_OFFSET_COM Position */
-#define BLEMODEM_FREQ_DOMAIN_STATUS1_PKT_OFFSET_COM_Msk (0x000001ffUL << BLEMODEM_FREQ_DOMAIN_STATUS1_PKT_OFFSET_COM_Pos)/*!< BLEMODEM FREQ_DOMAIN_STATUS1: PKT_OFFSET_COM Mask */
-#define BLEMODEM_FREQ_DOMAIN_STATUS1_NIDX_Pos 28 /*!< BLEMODEM FREQ_DOMAIN_STATUS1: NIDX Position */
-#define BLEMODEM_FREQ_DOMAIN_STATUS1_NIDX_Msk (0x0fUL << BLEMODEM_FREQ_DOMAIN_STATUS1_NIDX_Pos)/*!< BLEMODEM FREQ_DOMAIN_STATUS1: NIDX Mask */
-
-/* ---------------------- u_ble_dp_top_FREQ_DOMAIN_STATUS2 ---------------------- */
-#define BLEMODEM_FREQ_DOMAIN_STATUS2_MAX_PAR_SPWR_Pos 0 /*!< BLEMODEM FREQ_DOMAIN_STATUS2: MAX_PAR_SPWR Position */
-#define BLEMODEM_FREQ_DOMAIN_STATUS2_MAX_PAR_SPWR_Msk (0x000003ffUL << BLEMODEM_FREQ_DOMAIN_STATUS2_MAX_PAR_SPWR_Pos)/*!< BLEMODEM FREQ_DOMAIN_STATUS2: MAX_PAR_SPWR Mask */
-#define BLEMODEM_FREQ_DOMAIN_STATUS2_MAX_PAR_XCORR_Pos 16 /*!< BLEMODEM FREQ_DOMAIN_STATUS2: MAX_PAR_XCORR Position */
-#define BLEMODEM_FREQ_DOMAIN_STATUS2_MAX_PAR_XCORR_Msk (0x000003ffUL << BLEMODEM_FREQ_DOMAIN_STATUS2_MAX_PAR_XCORR_Pos)/*!< BLEMODEM FREQ_DOMAIN_STATUS2: MAX_PAR_XCORR Mask */
-
-/* ------------------------ u_ble_dp_top_DP_AA_ERROR_CTRL ----------------------- */
-#define BLEMODEM_DP_AA_ERROR_CTRL_IQSWAP_SEL_Pos 0 /*!< BLEMODEM DP_AA_ERROR_CTRL: IQSWAP_SEL Position */
-#define BLEMODEM_DP_AA_ERROR_CTRL_IQSWAP_SEL_Msk (0x01UL << BLEMODEM_DP_AA_ERROR_CTRL_IQSWAP_SEL_Pos)/*!< BLEMODEM DP_AA_ERROR_CTRL: IQSWAP_SEL Mask */
-#define BLEMODEM_DP_AA_ERROR_CTRL_AA_ERROR_EN_Pos 1 /*!< BLEMODEM DP_AA_ERROR_CTRL: AA_ERROR_EN Position */
-#define BLEMODEM_DP_AA_ERROR_CTRL_AA_ERROR_EN_Msk (0x01UL << BLEMODEM_DP_AA_ERROR_CTRL_AA_ERROR_EN_Pos)/*!< BLEMODEM DP_AA_ERROR_CTRL: AA_ERROR_EN Mask */
-#define BLEMODEM_DP_AA_ERROR_CTRL_AA_ERROR_CNR_EN_Pos 2 /*!< BLEMODEM DP_AA_ERROR_CTRL: AA_ERROR_CNR_EN Position */
-#define BLEMODEM_DP_AA_ERROR_CTRL_AA_ERROR_CNR_EN_Msk (0x01UL << BLEMODEM_DP_AA_ERROR_CTRL_AA_ERROR_CNR_EN_Pos)/*!< BLEMODEM DP_AA_ERROR_CTRL: AA_ERROR_CNR_EN Mask */
-#define BLEMODEM_DP_AA_ERROR_CTRL_AA_ERROR_CNR_SEL_Pos 3 /*!< BLEMODEM DP_AA_ERROR_CTRL: AA_ERROR_CNR_SEL Position */
-#define BLEMODEM_DP_AA_ERROR_CTRL_AA_ERROR_CNR_SEL_Msk (0x01UL << BLEMODEM_DP_AA_ERROR_CTRL_AA_ERROR_CNR_SEL_Pos)/*!< BLEMODEM DP_AA_ERROR_CTRL: AA_ERROR_CNR_SEL Mask */
-
-/* ----------------------------- u_ble_dp_top_DP_INT ---------------------------- */
-#define BLEMODEM_DP_INT_DP_INTERRUPT0_Pos 0 /*!< BLEMODEM DP_INT: DP_INTERRUPT0 Position */
-#define BLEMODEM_DP_INT_DP_INTERRUPT0_Msk (0x01UL << BLEMODEM_DP_INT_DP_INTERRUPT0_Pos) /*!< BLEMODEM DP_INT: DP_INTERRUPT0 Mask */
-#define BLEMODEM_DP_INT_DP_INTERRUPT1_Pos 1 /*!< BLEMODEM DP_INT: DP_INTERRUPT1 Position */
-#define BLEMODEM_DP_INT_DP_INTERRUPT1_Msk (0x01UL << BLEMODEM_DP_INT_DP_INTERRUPT1_Pos) /*!< BLEMODEM DP_INT: DP_INTERRUPT1 Mask */
-#define BLEMODEM_DP_INT_DP_INTERRUPT2_Pos 2 /*!< BLEMODEM DP_INT: DP_INTERRUPT2 Position */
-#define BLEMODEM_DP_INT_DP_INTERRUPT2_Msk (0x01UL << BLEMODEM_DP_INT_DP_INTERRUPT2_Pos) /*!< BLEMODEM DP_INT: DP_INTERRUPT2 Mask */
-#define BLEMODEM_DP_INT_DP_INTERRUPT_Pos 3 /*!< BLEMODEM DP_INT: DP_INTERRUPT Position */
-#define BLEMODEM_DP_INT_DP_INTERRUPT_Msk (0x01UL << BLEMODEM_DP_INT_DP_INTERRUPT_Pos) /*!< BLEMODEM DP_INT: DP_INTERRUPT Mask */
-#define BLEMODEM_DP_INT_DP_INTERRUPT0_SEL_Pos 16 /*!< BLEMODEM DP_INT: DP_INTERRUPT0_SEL Position */
-#define BLEMODEM_DP_INT_DP_INTERRUPT0_SEL_Msk (0x0fUL << BLEMODEM_DP_INT_DP_INTERRUPT0_SEL_Pos)/*!< BLEMODEM DP_INT: DP_INTERRUPT0_SEL Mask */
-#define BLEMODEM_DP_INT_DP_INTERRUPT1_SEL_Pos 20 /*!< BLEMODEM DP_INT: DP_INTERRUPT1_SEL Position */
-#define BLEMODEM_DP_INT_DP_INTERRUPT1_SEL_Msk (0x0fUL << BLEMODEM_DP_INT_DP_INTERRUPT1_SEL_Pos)/*!< BLEMODEM DP_INT: DP_INTERRUPT1_SEL Mask */
-#define BLEMODEM_DP_INT_DP_INTERRUPT2_SEL_Pos 24 /*!< BLEMODEM DP_INT: DP_INTERRUPT2_SEL Position */
-#define BLEMODEM_DP_INT_DP_INTERRUPT2_SEL_Msk (0x0fUL << BLEMODEM_DP_INT_DP_INTERRUPT2_SEL_Pos)/*!< BLEMODEM DP_INT: DP_INTERRUPT2_SEL Mask */
-#define BLEMODEM_DP_INT_DP_INTERRUPT0_MSK_Pos 28 /*!< BLEMODEM DP_INT: DP_INTERRUPT0_MSK Position */
-#define BLEMODEM_DP_INT_DP_INTERRUPT0_MSK_Msk (0x01UL << BLEMODEM_DP_INT_DP_INTERRUPT0_MSK_Pos)/*!< BLEMODEM DP_INT: DP_INTERRUPT0_MSK Mask */
-#define BLEMODEM_DP_INT_DP_INTERRUPT1_MSK_Pos 29 /*!< BLEMODEM DP_INT: DP_INTERRUPT1_MSK Position */
-#define BLEMODEM_DP_INT_DP_INTERRUPT1_MSK_Msk (0x01UL << BLEMODEM_DP_INT_DP_INTERRUPT1_MSK_Pos)/*!< BLEMODEM DP_INT: DP_INTERRUPT1_MSK Mask */
-#define BLEMODEM_DP_INT_DP_INTERRUPT2_MSK_Pos 30 /*!< BLEMODEM DP_INT: DP_INTERRUPT2_MSK Position */
-#define BLEMODEM_DP_INT_DP_INTERRUPT2_MSK_Msk (0x01UL << BLEMODEM_DP_INT_DP_INTERRUPT2_MSK_Pos)/*!< BLEMODEM DP_INT: DP_INTERRUPT2_MSK Mask */
-#define BLEMODEM_DP_INT_DP_INTERRUPT_MSK_Pos 31 /*!< BLEMODEM DP_INT: DP_INTERRUPT_MSK Position */
-#define BLEMODEM_DP_INT_DP_INTERRUPT_MSK_Msk (0x01UL << BLEMODEM_DP_INT_DP_INTERRUPT_MSK_Pos) /*!< BLEMODEM DP_INT: DP_INTERRUPT_MSK Mask */
-
-/* ------------------------- u_ble_dp_top_DP_AA_ERROR_TH ------------------------ */
-#define BLEMODEM_DP_AA_ERROR_TH_HP_TRAIN_POSITION_Pos 0 /*!< BLEMODEM DP_AA_ERROR_TH: HP_TRAIN_POSITION Position */
-#define BLEMODEM_DP_AA_ERROR_TH_HP_TRAIN_POSITION_Msk (0x01UL << BLEMODEM_DP_AA_ERROR_TH_HP_TRAIN_POSITION_Pos)/*!< BLEMODEM DP_AA_ERROR_TH: HP_TRAIN_POSITION Mask */
-#define BLEMODEM_DP_AA_ERROR_TH_CORDIC_IN_SCALE_Pos 1 /*!< BLEMODEM DP_AA_ERROR_TH: CORDIC_IN_SCALE Position */
-#define BLEMODEM_DP_AA_ERROR_TH_CORDIC_IN_SCALE_Msk (0x01UL << BLEMODEM_DP_AA_ERROR_TH_CORDIC_IN_SCALE_Pos)/*!< BLEMODEM DP_AA_ERROR_TH: CORDIC_IN_SCALE Mask */
-#define BLEMODEM_DP_AA_ERROR_TH_PAR_AUTO_HIGHER_SEL_Pos 2 /*!< BLEMODEM DP_AA_ERROR_TH: PAR_AUTO_HIGHER_SEL Position */
-#define BLEMODEM_DP_AA_ERROR_TH_PAR_AUTO_HIGHER_SEL_Msk (0x01UL << BLEMODEM_DP_AA_ERROR_TH_PAR_AUTO_HIGHER_SEL_Pos)/*!< BLEMODEM DP_AA_ERROR_TH: PAR_AUTO_HIGHER_SEL Mask */
-#define BLEMODEM_DP_AA_ERROR_TH_PAR_AUTO_HIGHER_EN_Pos 3 /*!< BLEMODEM DP_AA_ERROR_TH: PAR_AUTO_HIGHER_EN Position */
-#define BLEMODEM_DP_AA_ERROR_TH_PAR_AUTO_HIGHER_EN_Msk (0x01UL << BLEMODEM_DP_AA_ERROR_TH_PAR_AUTO_HIGHER_EN_Pos)/*!< BLEMODEM DP_AA_ERROR_TH: PAR_AUTO_HIGHER_EN Mask */
-#define BLEMODEM_DP_AA_ERROR_TH_SNR_GOOD_TH_Pos 4 /*!< BLEMODEM DP_AA_ERROR_TH: SNR_GOOD_TH Position */
-#define BLEMODEM_DP_AA_ERROR_TH_SNR_GOOD_TH_Msk (0x07UL << BLEMODEM_DP_AA_ERROR_TH_SNR_GOOD_TH_Pos)/*!< BLEMODEM DP_AA_ERROR_TH: SNR_GOOD_TH Mask */
-#define BLEMODEM_DP_AA_ERROR_TH_CNR_GOOD_TH_Pos 8 /*!< BLEMODEM DP_AA_ERROR_TH: CNR_GOOD_TH Position */
-#define BLEMODEM_DP_AA_ERROR_TH_CNR_GOOD_TH_Msk (0x3fUL << BLEMODEM_DP_AA_ERROR_TH_CNR_GOOD_TH_Pos)/*!< BLEMODEM DP_AA_ERROR_TH: CNR_GOOD_TH Mask */
-#define BLEMODEM_DP_AA_ERROR_TH_RSSI_GOOD_TH_Pos 16 /*!< BLEMODEM DP_AA_ERROR_TH: RSSI_GOOD_TH Position */
-#define BLEMODEM_DP_AA_ERROR_TH_RSSI_GOOD_TH_Msk (0x000000ffUL << BLEMODEM_DP_AA_ERROR_TH_RSSI_GOOD_TH_Pos)/*!< BLEMODEM DP_AA_ERROR_TH: RSSI_GOOD_TH Mask */
-#define BLEMODEM_DP_AA_ERROR_TH_RSSI_GOOD_DBM_Pos 24 /*!< BLEMODEM DP_AA_ERROR_TH: RSSI_GOOD_DBM Position */
-#define BLEMODEM_DP_AA_ERROR_TH_RSSI_GOOD_DBM_Msk (0x000000ffUL << BLEMODEM_DP_AA_ERROR_TH_RSSI_GOOD_DBM_Pos)/*!< BLEMODEM DP_AA_ERROR_TH: RSSI_GOOD_DBM Mask */
-
-/* ------------------------ u_ble_dp_top_DP_ANTENNA_CTRL ------------------------ */
-#define BLEMODEM_DP_ANTENNA_CTRL_SWITCH_MAP_SEL_8F_Pos 0 /*!< BLEMODEM DP_ANTENNA_CTRL: SWITCH_MAP_SEL_8F Position */
-#define BLEMODEM_DP_ANTENNA_CTRL_SWITCH_MAP_SEL_8F_Msk (0x03UL << BLEMODEM_DP_ANTENNA_CTRL_SWITCH_MAP_SEL_8F_Pos)/*!< BLEMODEM DP_ANTENNA_CTRL: SWITCH_MAP_SEL_8F Mask */
-#define BLEMODEM_DP_ANTENNA_CTRL_SWITCH_MAP_SEL_07_Pos 2 /*!< BLEMODEM DP_ANTENNA_CTRL: SWITCH_MAP_SEL_07 Position */
-#define BLEMODEM_DP_ANTENNA_CTRL_SWITCH_MAP_SEL_07_Msk (0x03UL << BLEMODEM_DP_ANTENNA_CTRL_SWITCH_MAP_SEL_07_Pos)/*!< BLEMODEM DP_ANTENNA_CTRL: SWITCH_MAP_SEL_07 Mask */
-#define BLEMODEM_DP_ANTENNA_CTRL_EXT_ANTENNA_NUM_Pos 4 /*!< BLEMODEM DP_ANTENNA_CTRL: EXT_ANTENNA_NUM Position */
-#define BLEMODEM_DP_ANTENNA_CTRL_EXT_ANTENNA_NUM_Msk (0x0fUL << BLEMODEM_DP_ANTENNA_CTRL_EXT_ANTENNA_NUM_Pos)/*!< BLEMODEM DP_ANTENNA_CTRL: EXT_ANTENNA_NUM Mask */
-#define BLEMODEM_DP_ANTENNA_CTRL_EXT_ANTENNA_NUM_WEN_Pos 8 /*!< BLEMODEM DP_ANTENNA_CTRL: EXT_ANTENNA_NUM_WEN Position */
-#define BLEMODEM_DP_ANTENNA_CTRL_EXT_ANTENNA_NUM_WEN_Msk (0x01UL << BLEMODEM_DP_ANTENNA_CTRL_EXT_ANTENNA_NUM_WEN_Pos)/*!< BLEMODEM DP_ANTENNA_CTRL: EXT_ANTENNA_NUM_WEN Mask */
-#define BLEMODEM_DP_ANTENNA_CTRL_BUFFER_BP_Pos 16 /*!< BLEMODEM DP_ANTENNA_CTRL: BUFFER_BP Position */
-#define BLEMODEM_DP_ANTENNA_CTRL_BUFFER_BP_Msk (0x01UL << BLEMODEM_DP_ANTENNA_CTRL_BUFFER_BP_Pos)/*!< BLEMODEM DP_ANTENNA_CTRL: BUFFER_BP Mask */
-#define BLEMODEM_DP_ANTENNA_CTRL_TEST_TD_POWER_Pos 17 /*!< BLEMODEM DP_ANTENNA_CTRL: TEST_TD_POWER Position */
-#define BLEMODEM_DP_ANTENNA_CTRL_TEST_TD_POWER_Msk (0x01UL << BLEMODEM_DP_ANTENNA_CTRL_TEST_TD_POWER_Pos)/*!< BLEMODEM DP_ANTENNA_CTRL: TEST_TD_POWER Mask */
-#define BLEMODEM_DP_ANTENNA_CTRL_TEST_FD_POWER_Pos 18 /*!< BLEMODEM DP_ANTENNA_CTRL: TEST_FD_POWER Position */
-#define BLEMODEM_DP_ANTENNA_CTRL_TEST_FD_POWER_Msk (0x01UL << BLEMODEM_DP_ANTENNA_CTRL_TEST_FD_POWER_Pos)/*!< BLEMODEM DP_ANTENNA_CTRL: TEST_FD_POWER Mask */
-#define BLEMODEM_DP_ANTENNA_CTRL_TEST_SYNC_POWER_Pos 19 /*!< BLEMODEM DP_ANTENNA_CTRL: TEST_SYNC_POWER Position */
-#define BLEMODEM_DP_ANTENNA_CTRL_TEST_SYNC_POWER_Msk (0x01UL << BLEMODEM_DP_ANTENNA_CTRL_TEST_SYNC_POWER_Pos)/*!< BLEMODEM DP_ANTENNA_CTRL: TEST_SYNC_POWER Mask */
-#define BLEMODEM_DP_ANTENNA_CTRL_TEST_RFE_CORDIC_POWER_Pos 20 /*!< BLEMODEM DP_ANTENNA_CTRL: TEST_RFE_CORDIC_POWER Position */
-#define BLEMODEM_DP_ANTENNA_CTRL_TEST_RFE_CORDIC_POWER_Msk (0x01UL << BLEMODEM_DP_ANTENNA_CTRL_TEST_RFE_CORDIC_POWER_Pos)/*!< BLEMODEM DP_ANTENNA_CTRL: TEST_RFE_CORDIC_POWER Mask */
-#define BLEMODEM_DP_ANTENNA_CTRL_TEST_RFE_POWER_Pos 21 /*!< BLEMODEM DP_ANTENNA_CTRL: TEST_RFE_POWER Position */
-#define BLEMODEM_DP_ANTENNA_CTRL_TEST_RFE_POWER_Msk (0x01UL << BLEMODEM_DP_ANTENNA_CTRL_TEST_RFE_POWER_Pos)/*!< BLEMODEM DP_ANTENNA_CTRL: TEST_RFE_POWER Mask */
-#define BLEMODEM_DP_ANTENNA_CTRL_ADC01_SAMPLE_TIME_Pos 22 /*!< BLEMODEM DP_ANTENNA_CTRL: ADC01_SAMPLE_TIME Position */
-#define BLEMODEM_DP_ANTENNA_CTRL_ADC01_SAMPLE_TIME_Msk (0x01UL << BLEMODEM_DP_ANTENNA_CTRL_ADC01_SAMPLE_TIME_Pos)/*!< BLEMODEM DP_ANTENNA_CTRL: ADC01_SAMPLE_TIME Mask */
-#define BLEMODEM_DP_ANTENNA_CTRL_PHY_RATE_MUX_Pos 23 /*!< BLEMODEM DP_ANTENNA_CTRL: PHY_RATE_MUX Position */
-#define BLEMODEM_DP_ANTENNA_CTRL_PHY_RATE_MUX_Msk (0x01UL << BLEMODEM_DP_ANTENNA_CTRL_PHY_RATE_MUX_Pos)/*!< BLEMODEM DP_ANTENNA_CTRL: PHY_RATE_MUX Mask */
-#define BLEMODEM_DP_ANTENNA_CTRL_PHY_RATE_REG_Pos 24 /*!< BLEMODEM DP_ANTENNA_CTRL: PHY_RATE_REG Position */
-#define BLEMODEM_DP_ANTENNA_CTRL_PHY_RATE_REG_Msk (0x01UL << BLEMODEM_DP_ANTENNA_CTRL_PHY_RATE_REG_Pos)/*!< BLEMODEM DP_ANTENNA_CTRL: PHY_RATE_REG Mask */
-#define BLEMODEM_DP_ANTENNA_CTRL_PHY_RATE_WEN_Pos 25 /*!< BLEMODEM DP_ANTENNA_CTRL: PHY_RATE_WEN Position */
-#define BLEMODEM_DP_ANTENNA_CTRL_PHY_RATE_WEN_Msk (0x01UL << BLEMODEM_DP_ANTENNA_CTRL_PHY_RATE_WEN_Pos)/*!< BLEMODEM DP_ANTENNA_CTRL: PHY_RATE_WEN Mask */
-#define BLEMODEM_DP_ANTENNA_CTRL_PDU_RSSI_WAIT_TIME_Pos 26 /*!< BLEMODEM DP_ANTENNA_CTRL: PDU_RSSI_WAIT_TIME Position */
-#define BLEMODEM_DP_ANTENNA_CTRL_PDU_RSSI_WAIT_TIME_Msk (0x01UL << BLEMODEM_DP_ANTENNA_CTRL_PDU_RSSI_WAIT_TIME_Pos)/*!< BLEMODEM DP_ANTENNA_CTRL: PDU_RSSI_WAIT_TIME Mask */
-#define BLEMODEM_DP_ANTENNA_CTRL_PDU_RSSI_WIN_LEN_Pos 27 /*!< BLEMODEM DP_ANTENNA_CTRL: PDU_RSSI_WIN_LEN Position */
-#define BLEMODEM_DP_ANTENNA_CTRL_PDU_RSSI_WIN_LEN_Msk (0x01UL << BLEMODEM_DP_ANTENNA_CTRL_PDU_RSSI_WIN_LEN_Pos)/*!< BLEMODEM DP_ANTENNA_CTRL: PDU_RSSI_WIN_LEN Mask */
-#define BLEMODEM_DP_ANTENNA_CTRL_CAL_PDU_RSSI_EN_Pos 28 /*!< BLEMODEM DP_ANTENNA_CTRL: CAL_PDU_RSSI_EN Position */
-#define BLEMODEM_DP_ANTENNA_CTRL_CAL_PDU_RSSI_EN_Msk (0x01UL << BLEMODEM_DP_ANTENNA_CTRL_CAL_PDU_RSSI_EN_Pos)/*!< BLEMODEM DP_ANTENNA_CTRL: CAL_PDU_RSSI_EN Mask */
-#define BLEMODEM_DP_ANTENNA_CTRL_PROP_CRC_AA_DIS_Pos 29 /*!< BLEMODEM DP_ANTENNA_CTRL: PROP_CRC_AA_DIS Position */
-#define BLEMODEM_DP_ANTENNA_CTRL_PROP_CRC_AA_DIS_Msk (0x01UL << BLEMODEM_DP_ANTENNA_CTRL_PROP_CRC_AA_DIS_Pos)/*!< BLEMODEM DP_ANTENNA_CTRL: PROP_CRC_AA_DIS Mask */
-#define BLEMODEM_DP_ANTENNA_CTRL_PROP_AA_LSB_FIRST_Pos 30 /*!< BLEMODEM DP_ANTENNA_CTRL: PROP_AA_LSB_FIRST Position */
-#define BLEMODEM_DP_ANTENNA_CTRL_PROP_AA_LSB_FIRST_Msk (0x01UL << BLEMODEM_DP_ANTENNA_CTRL_PROP_AA_LSB_FIRST_Pos)/*!< BLEMODEM DP_ANTENNA_CTRL: PROP_AA_LSB_FIRST Mask */
-#define BLEMODEM_DP_ANTENNA_CTRL_PRE_NUM_WEN_Pos 31 /*!< BLEMODEM DP_ANTENNA_CTRL: PRE_NUM_WEN Position */
-#define BLEMODEM_DP_ANTENNA_CTRL_PRE_NUM_WEN_Msk (0x01UL << BLEMODEM_DP_ANTENNA_CTRL_PRE_NUM_WEN_Pos)/*!< BLEMODEM DP_ANTENNA_CTRL: PRE_NUM_WEN Mask */
-
-/* ------------------------- u_ble_dp_top_ANTENNA_MAP01 ------------------------- */
-#define BLEMODEM_ANTENNA_MAP01_ANTENNA_MAP01_Pos 0 /*!< BLEMODEM ANTENNA_MAP01: ANTENNA_MAP01 Position */
-#define BLEMODEM_ANTENNA_MAP01_ANTENNA_MAP01_Msk (0xffffffffUL << BLEMODEM_ANTENNA_MAP01_ANTENNA_MAP01_Pos)/*!< BLEMODEM ANTENNA_MAP01: ANTENNA_MAP01 Mask */
-
-/* ------------------------- u_ble_dp_top_ANTENNA_MAP23 ------------------------- */
-#define BLEMODEM_ANTENNA_MAP23_ANTENNA_MAP23_Pos 0 /*!< BLEMODEM ANTENNA_MAP23: ANTENNA_MAP23 Position */
-#define BLEMODEM_ANTENNA_MAP23_ANTENNA_MAP23_Msk (0xffffffffUL << BLEMODEM_ANTENNA_MAP23_ANTENNA_MAP23_Pos)/*!< BLEMODEM ANTENNA_MAP23: ANTENNA_MAP23 Mask */
-
-/* ------------------------- u_ble_dp_top_ANTENNA_MAP45 ------------------------- */
-#define BLEMODEM_ANTENNA_MAP45_ANTENNA_MAP45_Pos 0 /*!< BLEMODEM ANTENNA_MAP45: ANTENNA_MAP45 Position */
-#define BLEMODEM_ANTENNA_MAP45_ANTENNA_MAP45_Msk (0xffffffffUL << BLEMODEM_ANTENNA_MAP45_ANTENNA_MAP45_Pos)/*!< BLEMODEM ANTENNA_MAP45: ANTENNA_MAP45 Mask */
-
-/* ------------------------- u_ble_dp_top_ANTENNA_MAP67 ------------------------- */
-#define BLEMODEM_ANTENNA_MAP67_ANTENNA_MAP67_Pos 0 /*!< BLEMODEM ANTENNA_MAP67: ANTENNA_MAP67 Position */
-#define BLEMODEM_ANTENNA_MAP67_ANTENNA_MAP67_Msk (0xffffffffUL << BLEMODEM_ANTENNA_MAP67_ANTENNA_MAP67_Pos)/*!< BLEMODEM ANTENNA_MAP67: ANTENNA_MAP67 Mask */
-
-/* ----------------------- u_ble_dp_top_LL_EM_BASE_ADDRESS ---------------------- */
-#define BLEMODEM_LL_EM_BASE_ADDRESS_LL_EM_BASE_ADDRESS_Pos 0 /*!< BLEMODEM LL_EM_BASE_ADDRESS: LL_EM_BASE_ADDRESS Position */
-#define BLEMODEM_LL_EM_BASE_ADDRESS_LL_EM_BASE_ADDRESS_Msk (0xffffffffUL << BLEMODEM_LL_EM_BASE_ADDRESS_LL_EM_BASE_ADDRESS_Pos)/*!< BLEMODEM LL_EM_BASE_ADDRESS: LL_EM_BASE_ADDRESS Mask */
-
-/* -------------------------- u_ble_dp_top_RX_EARLY_EOP ------------------------- */
-#define BLEMODEM_RX_EARLY_EOP_rx_early_eop_Pos 0 /*!< BLEMODEM RX_EARLY_EOP: rx_early_eop Position */
-#define BLEMODEM_RX_EARLY_EOP_rx_early_eop_Msk (0x000000ffUL << BLEMODEM_RX_EARLY_EOP_rx_early_eop_Pos)/*!< BLEMODEM RX_EARLY_EOP: rx_early_eop Mask */
-
-/* ------------------------- u_ble_dp_top_ANT_DIVERSITY ------------------------- */
-#define BLEMODEM_ANT_DIVERSITY_ble_ant_selected_Pos 0 /*!< BLEMODEM ANT_DIVERSITY: ble_ant_selected Position */
-#define BLEMODEM_ANT_DIVERSITY_ble_ant_selected_Msk (0x01UL << BLEMODEM_ANT_DIVERSITY_ble_ant_selected_Pos)/*!< BLEMODEM ANT_DIVERSITY: ble_ant_selected Mask */
-#define BLEMODEM_ANT_DIVERSITY_ble_ant_mode_Pos 1 /*!< BLEMODEM ANT_DIVERSITY: ble_ant_mode Position */
-#define BLEMODEM_ANT_DIVERSITY_ble_ant_mode_Msk (0x01UL << BLEMODEM_ANT_DIVERSITY_ble_ant_mode_Pos)/*!< BLEMODEM ANT_DIVERSITY: ble_ant_mode Mask */
-
-/* ------------------------- u_ble_dp_top_TX_M_TEST_CTRL ------------------------ */
-#define BLEMODEM_TX_M_TEST_CTRL_tx_test_mode_Pos 0 /*!< BLEMODEM TX_M_TEST_CTRL: tx_test_mode Position */
-#define BLEMODEM_TX_M_TEST_CTRL_tx_test_mode_Msk (0x0fUL << BLEMODEM_TX_M_TEST_CTRL_tx_test_mode_Pos)/*!< BLEMODEM TX_M_TEST_CTRL: tx_test_mode Mask */
-#define BLEMODEM_TX_M_TEST_CTRL_tx_test_speed_Pos 4 /*!< BLEMODEM TX_M_TEST_CTRL: tx_test_speed Position */
-#define BLEMODEM_TX_M_TEST_CTRL_tx_test_speed_Msk (0x01UL << BLEMODEM_TX_M_TEST_CTRL_tx_test_speed_Pos)/*!< BLEMODEM TX_M_TEST_CTRL: tx_test_speed Mask */
-#define BLEMODEM_TX_M_TEST_CTRL_tx_test_en_Pos 5 /*!< BLEMODEM TX_M_TEST_CTRL: tx_test_en Position */
-#define BLEMODEM_TX_M_TEST_CTRL_tx_test_en_Msk (0x01UL << BLEMODEM_TX_M_TEST_CTRL_tx_test_en_Pos)/*!< BLEMODEM TX_M_TEST_CTRL: tx_test_en Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u_pvt' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* ---------------------------- u_pvt_RED_DEL_CTRL_0 ---------------------------- */
-#define PVT_RED_DEL_CTRL_0_RED_DEL_CTRL_0_Pos 0 /*!< PVT RED_DEL_CTRL_0: RED_DEL_CTRL_0 Position */
-#define PVT_RED_DEL_CTRL_0_RED_DEL_CTRL_0_Msk (0xffffffffUL << PVT_RED_DEL_CTRL_0_RED_DEL_CTRL_0_Pos)/*!< PVT RED_DEL_CTRL_0: RED_DEL_CTRL_0 Mask */
-
-/* --------------------------- u_pvt_RED_REGION_CNT_0 --------------------------- */
-#define PVT_RED_REGION_CNT_0_RED_REGION_CNT_0_Pos 0 /*!< PVT RED_REGION_CNT_0: RED_REGION_CNT_0 Position */
-#define PVT_RED_REGION_CNT_0_RED_REGION_CNT_0_Msk (0xffffffffUL << PVT_RED_REGION_CNT_0_RED_REGION_CNT_0_Pos)/*!< PVT RED_REGION_CNT_0: RED_REGION_CNT_0 Mask */
-
-/* ------------------------- u_pvt_RED_REGION_CNT_CTRL_0 ------------------------ */
-#define PVT_RED_REGION_CNT_CTRL_0_RED_REGION_CNT_CTRL_0_Pos 0 /*!< PVT RED_REGION_CNT_CTRL_0: RED_REGION_CNT_CTRL_0 Position */
-#define PVT_RED_REGION_CNT_CTRL_0_RED_REGION_CNT_CTRL_0_Msk (0xffffffffUL << PVT_RED_REGION_CNT_CTRL_0_RED_REGION_CNT_CTRL_0_Pos)/*!< PVT RED_REGION_CNT_CTRL_0: RED_REGION_CNT_CTRL_0 Mask */
-
-/* --------------------------- u_pvt_AMBER_DEL_CTRL_0 --------------------------- */
-#define PVT_AMBER_DEL_CTRL_0_AMBER_DEL_CTRL_0_Pos 0 /*!< PVT AMBER_DEL_CTRL_0: AMBER_DEL_CTRL_0 Position */
-#define PVT_AMBER_DEL_CTRL_0_AMBER_DEL_CTRL_0_Msk (0xffffffffUL << PVT_AMBER_DEL_CTRL_0_AMBER_DEL_CTRL_0_Pos)/*!< PVT AMBER_DEL_CTRL_0: AMBER_DEL_CTRL_0 Mask */
-
-/* ----------------------------- u_pvt_AMBER_RINGO_0 ---------------------------- */
-#define PVT_AMBER_RINGO_0_ENABLE_Pos 0 /*!< PVT AMBER_RINGO_0: ENABLE Position */
-#define PVT_AMBER_RINGO_0_ENABLE_Msk (0x01UL << PVT_AMBER_RINGO_0_ENABLE_Pos) /*!< PVT AMBER_RINGO_0: ENABLE Mask */
-#define PVT_AMBER_RINGO_0_CNT_ENABLE_Pos 1 /*!< PVT AMBER_RINGO_0: CNT_ENABLE Position */
-#define PVT_AMBER_RINGO_0_CNT_ENABLE_Msk (0x01UL << PVT_AMBER_RINGO_0_CNT_ENABLE_Pos) /*!< PVT AMBER_RINGO_0: CNT_ENABLE Mask */
-#define PVT_AMBER_RINGO_0_CNT_RESET_Pos 2 /*!< PVT AMBER_RINGO_0: CNT_RESET Position */
-#define PVT_AMBER_RINGO_0_CNT_RESET_Msk (0x01UL << PVT_AMBER_RINGO_0_CNT_RESET_Pos) /*!< PVT AMBER_RINGO_0: CNT_RESET Mask */
-
-/* --------------------------- u_pvt_AMBER_RINGO_CNT_0 -------------------------- */
-#define PVT_AMBER_RINGO_CNT_0_AMBER_RINGO_CNT_0_Pos 0 /*!< PVT AMBER_RINGO_CNT_0: AMBER_RINGO_CNT_0 Position */
-#define PVT_AMBER_RINGO_CNT_0_AMBER_RINGO_CNT_0_Msk (0xffffffffUL << PVT_AMBER_RINGO_CNT_0_AMBER_RINGO_CNT_0_Pos)/*!< PVT AMBER_RINGO_CNT_0: AMBER_RINGO_CNT_0 Mask */
-
-/* -------------------------- u_pvt_AMBER_REGION_CNT_0 -------------------------- */
-#define PVT_AMBER_REGION_CNT_0_AMBER_REGION_CNT_0_Pos 0 /*!< PVT AMBER_REGION_CNT_0: AMBER_REGION_CNT_0 Position */
-#define PVT_AMBER_REGION_CNT_0_AMBER_REGION_CNT_0_Msk (0xffffffffUL << PVT_AMBER_REGION_CNT_0_AMBER_REGION_CNT_0_Pos)/*!< PVT AMBER_REGION_CNT_0: AMBER_REGION_CNT_0 Mask */
-
-/* ------------------------ u_pvt_AMBER_REGION_CNT_CTRL_0 ----------------------- */
-#define PVT_AMBER_REGION_CNT_CTRL_0_AMBER_REGION_CNT_CTRL_0_Pos 0 /*!< PVT AMBER_REGION_CNT_CTRL_0: AMBER_REGION_CNT_CTRL_0 Position */
-#define PVT_AMBER_REGION_CNT_CTRL_0_AMBER_REGION_CNT_CTRL_0_Msk (0xffffffffUL << PVT_AMBER_REGION_CNT_CTRL_0_AMBER_REGION_CNT_CTRL_0_Pos)/*!< PVT AMBER_REGION_CNT_CTRL_0: AMBER_REGION_CNT_CTRL_0 Mask */
-
-/* ------------------------------ u_pvt_DFT_CTRL_0 ------------------------------ */
-#define PVT_DFT_CTRL_0_DFT_CTRL_0_Pos 0 /*!< PVT DFT_CTRL_0: DFT_CTRL_0 Position */
-#define PVT_DFT_CTRL_0_DFT_CTRL_0_Msk (0xffffffffUL << PVT_DFT_CTRL_0_DFT_CTRL_0_Pos) /*!< PVT DFT_CTRL_0: DFT_CTRL_0 Mask */
-
-/* ---------------------------- u_pvt_RED_DEL_CTRL_1 ---------------------------- */
-#define PVT_RED_DEL_CTRL_1_RED_DEL_CTRL_1_Pos 0 /*!< PVT RED_DEL_CTRL_1: RED_DEL_CTRL_1 Position */
-#define PVT_RED_DEL_CTRL_1_RED_DEL_CTRL_1_Msk (0xffffffffUL << PVT_RED_DEL_CTRL_1_RED_DEL_CTRL_1_Pos)/*!< PVT RED_DEL_CTRL_1: RED_DEL_CTRL_1 Mask */
-
-/* --------------------------- u_pvt_RED_REGION_CNT_1 --------------------------- */
-#define PVT_RED_REGION_CNT_1_RED_REGION_CNT_1_Pos 0 /*!< PVT RED_REGION_CNT_1: RED_REGION_CNT_1 Position */
-#define PVT_RED_REGION_CNT_1_RED_REGION_CNT_1_Msk (0xffffffffUL << PVT_RED_REGION_CNT_1_RED_REGION_CNT_1_Pos)/*!< PVT RED_REGION_CNT_1: RED_REGION_CNT_1 Mask */
-
-/* ------------------------- u_pvt_RED_REGION_CNT_CTRL_1 ------------------------ */
-#define PVT_RED_REGION_CNT_CTRL_1_RED_REGION_CNT_CTRL_1_Pos 0 /*!< PVT RED_REGION_CNT_CTRL_1: RED_REGION_CNT_CTRL_1 Position */
-#define PVT_RED_REGION_CNT_CTRL_1_RED_REGION_CNT_CTRL_1_Msk (0xffffffffUL << PVT_RED_REGION_CNT_CTRL_1_RED_REGION_CNT_CTRL_1_Pos)/*!< PVT RED_REGION_CNT_CTRL_1: RED_REGION_CNT_CTRL_1 Mask */
-
-/* --------------------------- u_pvt_AMBER_DEL_CTRL_1 --------------------------- */
-#define PVT_AMBER_DEL_CTRL_1_AMBER_DEL_CTRL_1_Pos 0 /*!< PVT AMBER_DEL_CTRL_1: AMBER_DEL_CTRL_1 Position */
-#define PVT_AMBER_DEL_CTRL_1_AMBER_DEL_CTRL_1_Msk (0xffffffffUL << PVT_AMBER_DEL_CTRL_1_AMBER_DEL_CTRL_1_Pos)/*!< PVT AMBER_DEL_CTRL_1: AMBER_DEL_CTRL_1 Mask */
-
-/* ----------------------------- u_pvt_AMBER_RINGO_1 ---------------------------- */
-#define PVT_AMBER_RINGO_1_ENABLE_Pos 0 /*!< PVT AMBER_RINGO_1: ENABLE Position */
-#define PVT_AMBER_RINGO_1_ENABLE_Msk (0x01UL << PVT_AMBER_RINGO_1_ENABLE_Pos) /*!< PVT AMBER_RINGO_1: ENABLE Mask */
-#define PVT_AMBER_RINGO_1_CNT_ENABLE_Pos 1 /*!< PVT AMBER_RINGO_1: CNT_ENABLE Position */
-#define PVT_AMBER_RINGO_1_CNT_ENABLE_Msk (0x01UL << PVT_AMBER_RINGO_1_CNT_ENABLE_Pos) /*!< PVT AMBER_RINGO_1: CNT_ENABLE Mask */
-#define PVT_AMBER_RINGO_1_CNT_RESET_Pos 2 /*!< PVT AMBER_RINGO_1: CNT_RESET Position */
-#define PVT_AMBER_RINGO_1_CNT_RESET_Msk (0x01UL << PVT_AMBER_RINGO_1_CNT_RESET_Pos) /*!< PVT AMBER_RINGO_1: CNT_RESET Mask */
-
-/* --------------------------- u_pvt_AMBER_RINGO_CNT_1 -------------------------- */
-#define PVT_AMBER_RINGO_CNT_1_AMBER_RINGO_CNT_1_Pos 0 /*!< PVT AMBER_RINGO_CNT_1: AMBER_RINGO_CNT_1 Position */
-#define PVT_AMBER_RINGO_CNT_1_AMBER_RINGO_CNT_1_Msk (0xffffffffUL << PVT_AMBER_RINGO_CNT_1_AMBER_RINGO_CNT_1_Pos)/*!< PVT AMBER_RINGO_CNT_1: AMBER_RINGO_CNT_1 Mask */
-
-/* -------------------------- u_pvt_AMBER_REGION_CNT_1 -------------------------- */
-#define PVT_AMBER_REGION_CNT_1_AMBER_REGION_CNT_1_Pos 0 /*!< PVT AMBER_REGION_CNT_1: AMBER_REGION_CNT_1 Position */
-#define PVT_AMBER_REGION_CNT_1_AMBER_REGION_CNT_1_Msk (0xffffffffUL << PVT_AMBER_REGION_CNT_1_AMBER_REGION_CNT_1_Pos)/*!< PVT AMBER_REGION_CNT_1: AMBER_REGION_CNT_1 Mask */
-
-/* ------------------------ u_pvt_AMBER_REGION_CNT_CTRL_1 ----------------------- */
-#define PVT_AMBER_REGION_CNT_CTRL_1_AMBER_REGION_CNT_CTRL_1_Pos 0 /*!< PVT AMBER_REGION_CNT_CTRL_1: AMBER_REGION_CNT_CTRL_1 Position */
-#define PVT_AMBER_REGION_CNT_CTRL_1_AMBER_REGION_CNT_CTRL_1_Msk (0xffffffffUL << PVT_AMBER_REGION_CNT_CTRL_1_AMBER_REGION_CNT_CTRL_1_Pos)/*!< PVT AMBER_REGION_CNT_CTRL_1: AMBER_REGION_CNT_CTRL_1 Mask */
-
-/* ------------------------------ u_pvt_DFT_CTRL_1 ------------------------------ */
-#define PVT_DFT_CTRL_1_DFT_CTRL_1_Pos 0 /*!< PVT DFT_CTRL_1: DFT_CTRL_1 Position */
-#define PVT_DFT_CTRL_1_DFT_CTRL_1_Msk (0xffffffffUL << PVT_DFT_CTRL_1_DFT_CTRL_1_Pos) /*!< PVT DFT_CTRL_1: DFT_CTRL_1 Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u_async_syscon' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* ----------------------- u_async_syscon_ASYNCPRESETCTRL ----------------------- */
-#define ASYSCON_ASYNCPRESETCTRL_CT32B0_Pos 1 /*!< ASYSCON ASYNCPRESETCTRL: CT32B0 Position */
-#define ASYSCON_ASYNCPRESETCTRL_CT32B0_Msk (0x01UL << ASYSCON_ASYNCPRESETCTRL_CT32B0_Pos)/*!< ASYSCON ASYNCPRESETCTRL: CT32B0 Mask */
-#define ASYSCON_ASYNCPRESETCTRL_CT32B1_Pos 2 /*!< ASYSCON ASYNCPRESETCTRL: CT32B1 Position */
-#define ASYSCON_ASYNCPRESETCTRL_CT32B1_Msk (0x01UL << ASYSCON_ASYNCPRESETCTRL_CT32B1_Pos)/*!< ASYSCON ASYNCPRESETCTRL: CT32B1 Mask */
-
-/* ---------------------- u_async_syscon_ASYNCPRESETCTRLSET --------------------- */
-#define ASYSCON_ASYNCPRESETCTRLSET_CT32B0_Pos 1 /*!< ASYSCON ASYNCPRESETCTRLSET: CT32B0 Position */
-#define ASYSCON_ASYNCPRESETCTRLSET_CT32B0_Msk (0x01UL << ASYSCON_ASYNCPRESETCTRLSET_CT32B0_Pos)/*!< ASYSCON ASYNCPRESETCTRLSET: CT32B0 Mask */
-#define ASYSCON_ASYNCPRESETCTRLSET_CT32B1_Pos 2 /*!< ASYSCON ASYNCPRESETCTRLSET: CT32B1 Position */
-#define ASYSCON_ASYNCPRESETCTRLSET_CT32B1_Msk (0x01UL << ASYSCON_ASYNCPRESETCTRLSET_CT32B1_Pos)/*!< ASYSCON ASYNCPRESETCTRLSET: CT32B1 Mask */
-
-/* ---------------------- u_async_syscon_ASYNCPRESETCTRLCLR --------------------- */
-#define ASYSCON_ASYNCPRESETCTRLCLR_CT32B0_Pos 1 /*!< ASYSCON ASYNCPRESETCTRLCLR: CT32B0 Position */
-#define ASYSCON_ASYNCPRESETCTRLCLR_CT32B0_Msk (0x01UL << ASYSCON_ASYNCPRESETCTRLCLR_CT32B0_Pos)/*!< ASYSCON ASYNCPRESETCTRLCLR: CT32B0 Mask */
-#define ASYSCON_ASYNCPRESETCTRLCLR_CT32B1_Pos 2 /*!< ASYSCON ASYNCPRESETCTRLCLR: CT32B1 Position */
-#define ASYSCON_ASYNCPRESETCTRLCLR_CT32B1_Msk (0x01UL << ASYSCON_ASYNCPRESETCTRLCLR_CT32B1_Pos)/*!< ASYSCON ASYNCPRESETCTRLCLR: CT32B1 Mask */
-
-/* ----------------------- u_async_syscon_ASYNCAPBCLKCTRL ----------------------- */
-#define ASYSCON_ASYNCAPBCLKCTRL_CT32B0_Pos 1 /*!< ASYSCON ASYNCAPBCLKCTRL: CT32B0 Position */
-#define ASYSCON_ASYNCAPBCLKCTRL_CT32B0_Msk (0x01UL << ASYSCON_ASYNCAPBCLKCTRL_CT32B0_Pos)/*!< ASYSCON ASYNCAPBCLKCTRL: CT32B0 Mask */
-#define ASYSCON_ASYNCAPBCLKCTRL_CT32B1_Pos 2 /*!< ASYSCON ASYNCAPBCLKCTRL: CT32B1 Position */
-#define ASYSCON_ASYNCAPBCLKCTRL_CT32B1_Msk (0x01UL << ASYSCON_ASYNCAPBCLKCTRL_CT32B1_Pos)/*!< ASYSCON ASYNCAPBCLKCTRL: CT32B1 Mask */
-
-/* ---------------------- u_async_syscon_ASYNCAPBCLKCTRLSET --------------------- */
-#define ASYSCON_ASYNCAPBCLKCTRLSET_CT32B0_Pos 1 /*!< ASYSCON ASYNCAPBCLKCTRLSET: CT32B0 Position */
-#define ASYSCON_ASYNCAPBCLKCTRLSET_CT32B0_Msk (0x01UL << ASYSCON_ASYNCAPBCLKCTRLSET_CT32B0_Pos)/*!< ASYSCON ASYNCAPBCLKCTRLSET: CT32B0 Mask */
-#define ASYSCON_ASYNCAPBCLKCTRLSET_CT32B1_Pos 2 /*!< ASYSCON ASYNCAPBCLKCTRLSET: CT32B1 Position */
-#define ASYSCON_ASYNCAPBCLKCTRLSET_CT32B1_Msk (0x01UL << ASYSCON_ASYNCAPBCLKCTRLSET_CT32B1_Pos)/*!< ASYSCON ASYNCAPBCLKCTRLSET: CT32B1 Mask */
-
-/* ---------------------- u_async_syscon_ASYNCAPBCLKCTRLCLR --------------------- */
-#define ASYSCON_ASYNCAPBCLKCTRLCLR_CT32B0_Pos 1 /*!< ASYSCON ASYNCAPBCLKCTRLCLR: CT32B0 Position */
-#define ASYSCON_ASYNCAPBCLKCTRLCLR_CT32B0_Msk (0x01UL << ASYSCON_ASYNCAPBCLKCTRLCLR_CT32B0_Pos)/*!< ASYSCON ASYNCAPBCLKCTRLCLR: CT32B0 Mask */
-#define ASYSCON_ASYNCAPBCLKCTRLCLR_CT32B1_Pos 2 /*!< ASYSCON ASYNCAPBCLKCTRLCLR: CT32B1 Position */
-#define ASYSCON_ASYNCAPBCLKCTRLCLR_CT32B1_Msk (0x01UL << ASYSCON_ASYNCAPBCLKCTRLCLR_CT32B1_Pos)/*!< ASYSCON ASYNCAPBCLKCTRLCLR: CT32B1 Mask */
-
-/* ----------------------- u_async_syscon_ASYNCAPBCLKSELA ----------------------- */
-#define ASYSCON_ASYNCAPBCLKSELA_SEL_Pos 0 /*!< ASYSCON ASYNCAPBCLKSELA: SEL Position */
-#define ASYSCON_ASYNCAPBCLKSELA_SEL_Msk (0x03UL << ASYSCON_ASYNCAPBCLKSELA_SEL_Pos) /*!< ASYSCON ASYNCAPBCLKSELA: SEL Mask */
-
-/* ------------------------ u_async_syscon_ASYNCAPBCLKDIV ----------------------- */
-#define ASYSCON_ASYNCAPBCLKDIV_DIV_Pos 0 /*!< ASYSCON ASYNCAPBCLKDIV: DIV Position */
-#define ASYSCON_ASYNCAPBCLKDIV_DIV_Msk (0x000000ffUL << ASYSCON_ASYNCAPBCLKDIV_DIV_Pos) /*!< ASYSCON ASYNCAPBCLKDIV: DIV Mask */
-#define ASYSCON_ASYNCAPBCLKDIV_RESET_Pos 29 /*!< ASYSCON ASYNCAPBCLKDIV: RESET Position */
-#define ASYSCON_ASYNCAPBCLKDIV_RESET_Msk (0x01UL << ASYSCON_ASYNCAPBCLKDIV_RESET_Pos) /*!< ASYSCON ASYNCAPBCLKDIV: RESET Mask */
-#define ASYSCON_ASYNCAPBCLKDIV_HALT_Pos 30 /*!< ASYSCON ASYNCAPBCLKDIV: HALT Position */
-#define ASYSCON_ASYNCAPBCLKDIV_HALT_Msk (0x01UL << ASYSCON_ASYNCAPBCLKDIV_HALT_Pos) /*!< ASYSCON ASYNCAPBCLKDIV: HALT Mask */
-#define ASYSCON_ASYNCAPBCLKDIV_REQFLAG_Pos 31 /*!< ASYSCON ASYNCAPBCLKDIV: REQFLAG Position */
-#define ASYSCON_ASYNCAPBCLKDIV_REQFLAG_Msk (0x01UL << ASYSCON_ASYNCAPBCLKDIV_REQFLAG_Pos)/*!< ASYSCON ASYNCAPBCLKDIV: REQFLAG Mask */
-
-/* ----------------------- u_async_syscon_ASYNCCLKOVERRIDE ---------------------- */
-#define ASYSCON_ASYNCCLKOVERRIDE_ASYNCSYSREGBANK_Pos 15 /*!< ASYSCON ASYNCCLKOVERRIDE: ASYNCSYSREGBANK Position */
-#define ASYSCON_ASYNCCLKOVERRIDE_ASYNCSYSREGBANK_Msk (0x01UL << ASYSCON_ASYNCCLKOVERRIDE_ASYNCSYSREGBANK_Pos)/*!< ASYSCON ASYNCCLKOVERRIDE: ASYNCSYSREGBANK Mask */
-#define ASYSCON_ASYNCCLKOVERRIDE_ENABLEUPDATE_Pos 16 /*!< ASYSCON ASYNCCLKOVERRIDE: ENABLEUPDATE Position */
-#define ASYSCON_ASYNCCLKOVERRIDE_ENABLEUPDATE_Msk (0x0000ffffUL << ASYSCON_ASYNCCLKOVERRIDE_ENABLEUPDATE_Pos)/*!< ASYSCON ASYNCCLKOVERRIDE: ENABLEUPDATE Mask */
-
-/* ------------------------ u_async_syscon_TEMPSENSORCTRL ----------------------- */
-#define ASYSCON_TEMPSENSORCTRL_ENABLE_Pos 0 /*!< ASYSCON TEMPSENSORCTRL: ENABLE Position */
-#define ASYSCON_TEMPSENSORCTRL_ENABLE_Msk (0x01UL << ASYSCON_TEMPSENSORCTRL_ENABLE_Pos) /*!< ASYSCON TEMPSENSORCTRL: ENABLE Mask */
-#define ASYSCON_TEMPSENSORCTRL_SLOPE_Pos 1 /*!< ASYSCON TEMPSENSORCTRL: SLOPE Position */
-#define ASYSCON_TEMPSENSORCTRL_SLOPE_Msk (0x01UL << ASYSCON_TEMPSENSORCTRL_SLOPE_Pos) /*!< ASYSCON TEMPSENSORCTRL: SLOPE Mask */
-#define ASYSCON_TEMPSENSORCTRL_CM_Pos 2 /*!< ASYSCON TEMPSENSORCTRL: CM Position */
-#define ASYSCON_TEMPSENSORCTRL_CM_Msk (0x03UL << ASYSCON_TEMPSENSORCTRL_CM_Pos) /*!< ASYSCON TEMPSENSORCTRL: CM Mask */
-
-/* ------------------------ u_async_syscon_NFCTAGPADSCTRL ----------------------- */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SDA_EPD_Pos 0 /*!< ASYSCON NFCTAGPADSCTRL: I2C_SDA_EPD Position */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SDA_EPD_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_I2C_SDA_EPD_Pos)/*!< ASYSCON NFCTAGPADSCTRL: I2C_SDA_EPD Mask */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SDA_EPUN_Pos 1 /*!< ASYSCON NFCTAGPADSCTRL: I2C_SDA_EPUN Position */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SDA_EPUN_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_I2C_SDA_EPUN_Pos)/*!< ASYSCON NFCTAGPADSCTRL: I2C_SDA_EPUN Mask */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SDA_EHS0_Pos 2 /*!< ASYSCON NFCTAGPADSCTRL: I2C_SDA_EHS0 Position */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SDA_EHS0_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_I2C_SDA_EHS0_Pos)/*!< ASYSCON NFCTAGPADSCTRL: I2C_SDA_EHS0 Mask */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SDA_INVERT_Pos 3 /*!< ASYSCON NFCTAGPADSCTRL: I2C_SDA_INVERT Position */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SDA_INVERT_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_I2C_SDA_INVERT_Pos)/*!< ASYSCON NFCTAGPADSCTRL: I2C_SDA_INVERT Mask */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SDA_ENZI_Pos 4 /*!< ASYSCON NFCTAGPADSCTRL: I2C_SDA_ENZI Position */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SDA_ENZI_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_I2C_SDA_ENZI_Pos)/*!< ASYSCON NFCTAGPADSCTRL: I2C_SDA_ENZI Mask */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SDA_FILTEROFF_Pos 5 /*!< ASYSCON NFCTAGPADSCTRL: I2C_SDA_FILTEROFF Position */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SDA_FILTEROFF_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_I2C_SDA_FILTEROFF_Pos)/*!< ASYSCON NFCTAGPADSCTRL: I2C_SDA_FILTEROFF Mask */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SDA_EHS1_Pos 6 /*!< ASYSCON NFCTAGPADSCTRL: I2C_SDA_EHS1 Position */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SDA_EHS1_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_I2C_SDA_EHS1_Pos)/*!< ASYSCON NFCTAGPADSCTRL: I2C_SDA_EHS1 Mask */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SDA_OD_Pos 7 /*!< ASYSCON NFCTAGPADSCTRL: I2C_SDA_OD Position */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SDA_OD_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_I2C_SDA_OD_Pos)/*!< ASYSCON NFCTAGPADSCTRL: I2C_SDA_OD Mask */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SCL_EPD_Pos 8 /*!< ASYSCON NFCTAGPADSCTRL: I2C_SCL_EPD Position */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SCL_EPD_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_I2C_SCL_EPD_Pos)/*!< ASYSCON NFCTAGPADSCTRL: I2C_SCL_EPD Mask */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SCL_EPUN_Pos 9 /*!< ASYSCON NFCTAGPADSCTRL: I2C_SCL_EPUN Position */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SCL_EPUN_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_I2C_SCL_EPUN_Pos)/*!< ASYSCON NFCTAGPADSCTRL: I2C_SCL_EPUN Mask */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SCL_EHS0_Pos 10 /*!< ASYSCON NFCTAGPADSCTRL: I2C_SCL_EHS0 Position */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SCL_EHS0_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_I2C_SCL_EHS0_Pos)/*!< ASYSCON NFCTAGPADSCTRL: I2C_SCL_EHS0 Mask */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SCL_INVERT_Pos 11 /*!< ASYSCON NFCTAGPADSCTRL: I2C_SCL_INVERT Position */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SCL_INVERT_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_I2C_SCL_INVERT_Pos)/*!< ASYSCON NFCTAGPADSCTRL: I2C_SCL_INVERT Mask */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SCL_ENZI_Pos 12 /*!< ASYSCON NFCTAGPADSCTRL: I2C_SCL_ENZI Position */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SCL_ENZI_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_I2C_SCL_ENZI_Pos)/*!< ASYSCON NFCTAGPADSCTRL: I2C_SCL_ENZI Mask */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SCL_FILTEROFF_Pos 13 /*!< ASYSCON NFCTAGPADSCTRL: I2C_SCL_FILTEROFF Position */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SCL_FILTEROFF_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_I2C_SCL_FILTEROFF_Pos)/*!< ASYSCON NFCTAGPADSCTRL: I2C_SCL_FILTEROFF Mask */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SCL_EHS1_Pos 14 /*!< ASYSCON NFCTAGPADSCTRL: I2C_SCL_EHS1 Position */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SCL_EHS1_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_I2C_SCL_EHS1_Pos)/*!< ASYSCON NFCTAGPADSCTRL: I2C_SCL_EHS1 Mask */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SCL_OD_Pos 15 /*!< ASYSCON NFCTAGPADSCTRL: I2C_SCL_OD Position */
-#define ASYSCON_NFCTAGPADSCTRL_I2C_SCL_OD_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_I2C_SCL_OD_Pos)/*!< ASYSCON NFCTAGPADSCTRL: I2C_SCL_OD Mask */
-#define ASYSCON_NFCTAGPADSCTRL_INT_EPD_Pos 16 /*!< ASYSCON NFCTAGPADSCTRL: INT_EPD Position */
-#define ASYSCON_NFCTAGPADSCTRL_INT_EPD_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_INT_EPD_Pos)/*!< ASYSCON NFCTAGPADSCTRL: INT_EPD Mask */
-#define ASYSCON_NFCTAGPADSCTRL_INT_EPUN_Pos 17 /*!< ASYSCON NFCTAGPADSCTRL: INT_EPUN Position */
-#define ASYSCON_NFCTAGPADSCTRL_INT_EPUN_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_INT_EPUN_Pos)/*!< ASYSCON NFCTAGPADSCTRL: INT_EPUN Mask */
-#define ASYSCON_NFCTAGPADSCTRL_INT_INVERT_Pos 18 /*!< ASYSCON NFCTAGPADSCTRL: INT_INVERT Position */
-#define ASYSCON_NFCTAGPADSCTRL_INT_INVERT_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_INT_INVERT_Pos)/*!< ASYSCON NFCTAGPADSCTRL: INT_INVERT Mask */
-#define ASYSCON_NFCTAGPADSCTRL_INT_ENZI_Pos 19 /*!< ASYSCON NFCTAGPADSCTRL: INT_ENZI Position */
-#define ASYSCON_NFCTAGPADSCTRL_INT_ENZI_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_INT_ENZI_Pos)/*!< ASYSCON NFCTAGPADSCTRL: INT_ENZI Mask */
-#define ASYSCON_NFCTAGPADSCTRL_INT_FILTEROFF_Pos 20 /*!< ASYSCON NFCTAGPADSCTRL: INT_FILTEROFF Position */
-#define ASYSCON_NFCTAGPADSCTRL_INT_FILTEROFF_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_INT_FILTEROFF_Pos)/*!< ASYSCON NFCTAGPADSCTRL: INT_FILTEROFF Mask */
-#define ASYSCON_NFCTAGPADSCTRL_VDD_EPD_Pos 21 /*!< ASYSCON NFCTAGPADSCTRL: VDD_EPD Position */
-#define ASYSCON_NFCTAGPADSCTRL_VDD_EPD_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_VDD_EPD_Pos)/*!< ASYSCON NFCTAGPADSCTRL: VDD_EPD Mask */
-#define ASYSCON_NFCTAGPADSCTRL_VDD_EPUN_Pos 22 /*!< ASYSCON NFCTAGPADSCTRL: VDD_EPUN Position */
-#define ASYSCON_NFCTAGPADSCTRL_VDD_EPUN_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_VDD_EPUN_Pos)/*!< ASYSCON NFCTAGPADSCTRL: VDD_EPUN Mask */
-#define ASYSCON_NFCTAGPADSCTRL_VDD_EHS0_Pos 23 /*!< ASYSCON NFCTAGPADSCTRL: VDD_EHS0 Position */
-#define ASYSCON_NFCTAGPADSCTRL_VDD_EHS0_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_VDD_EHS0_Pos)/*!< ASYSCON NFCTAGPADSCTRL: VDD_EHS0 Mask */
-#define ASYSCON_NFCTAGPADSCTRL_VDD_INVERT_Pos 24 /*!< ASYSCON NFCTAGPADSCTRL: VDD_INVERT Position */
-#define ASYSCON_NFCTAGPADSCTRL_VDD_INVERT_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_VDD_INVERT_Pos)/*!< ASYSCON NFCTAGPADSCTRL: VDD_INVERT Mask */
-#define ASYSCON_NFCTAGPADSCTRL_VDD_ENZI_Pos 25 /*!< ASYSCON NFCTAGPADSCTRL: VDD_ENZI Position */
-#define ASYSCON_NFCTAGPADSCTRL_VDD_ENZI_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_VDD_ENZI_Pos)/*!< ASYSCON NFCTAGPADSCTRL: VDD_ENZI Mask */
-#define ASYSCON_NFCTAGPADSCTRL_VDD_FILTEROFF_Pos 26 /*!< ASYSCON NFCTAGPADSCTRL: VDD_FILTEROFF Position */
-#define ASYSCON_NFCTAGPADSCTRL_VDD_FILTEROFF_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_VDD_FILTEROFF_Pos)/*!< ASYSCON NFCTAGPADSCTRL: VDD_FILTEROFF Mask */
-#define ASYSCON_NFCTAGPADSCTRL_VDD_EHS1_Pos 27 /*!< ASYSCON NFCTAGPADSCTRL: VDD_EHS1 Position */
-#define ASYSCON_NFCTAGPADSCTRL_VDD_EHS1_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_VDD_EHS1_Pos)/*!< ASYSCON NFCTAGPADSCTRL: VDD_EHS1 Mask */
-#define ASYSCON_NFCTAGPADSCTRL_VDD_OD_Pos 28 /*!< ASYSCON NFCTAGPADSCTRL: VDD_OD Position */
-#define ASYSCON_NFCTAGPADSCTRL_VDD_OD_Msk (0x01UL << ASYSCON_NFCTAGPADSCTRL_VDD_OD_Pos) /*!< ASYSCON NFCTAGPADSCTRL: VDD_OD Mask */
-
-/* ------------------------ u_async_syscon_XTAL32MLDOCTRL ----------------------- */
-#define ASYSCON_XTAL32MLDOCTRL_BYPASS_Pos 0 /*!< ASYSCON XTAL32MLDOCTRL: BYPASS Position */
-#define ASYSCON_XTAL32MLDOCTRL_BYPASS_Msk (0x01UL << ASYSCON_XTAL32MLDOCTRL_BYPASS_Pos) /*!< ASYSCON XTAL32MLDOCTRL: BYPASS Mask */
-#define ASYSCON_XTAL32MLDOCTRL_ENABLE_Pos 1 /*!< ASYSCON XTAL32MLDOCTRL: ENABLE Position */
-#define ASYSCON_XTAL32MLDOCTRL_ENABLE_Msk (0x01UL << ASYSCON_XTAL32MLDOCTRL_ENABLE_Pos) /*!< ASYSCON XTAL32MLDOCTRL: ENABLE Mask */
-#define ASYSCON_XTAL32MLDOCTRL_HIGHZ_Pos 2 /*!< ASYSCON XTAL32MLDOCTRL: HIGHZ Position */
-#define ASYSCON_XTAL32MLDOCTRL_HIGHZ_Msk (0x01UL << ASYSCON_XTAL32MLDOCTRL_HIGHZ_Pos) /*!< ASYSCON XTAL32MLDOCTRL: HIGHZ Mask */
-#define ASYSCON_XTAL32MLDOCTRL_VOUT_Pos 3 /*!< ASYSCON XTAL32MLDOCTRL: VOUT Position */
-#define ASYSCON_XTAL32MLDOCTRL_VOUT_Msk (0x07UL << ASYSCON_XTAL32MLDOCTRL_VOUT_Pos) /*!< ASYSCON XTAL32MLDOCTRL: VOUT Mask */
-#define ASYSCON_XTAL32MLDOCTRL_IBIAS_Pos 6 /*!< ASYSCON XTAL32MLDOCTRL: IBIAS Position */
-#define ASYSCON_XTAL32MLDOCTRL_IBIAS_Msk (0x03UL << ASYSCON_XTAL32MLDOCTRL_IBIAS_Pos) /*!< ASYSCON XTAL32MLDOCTRL: IBIAS Mask */
-#define ASYSCON_XTAL32MLDOCTRL_STABMODE_Pos 8 /*!< ASYSCON XTAL32MLDOCTRL: STABMODE Position */
-#define ASYSCON_XTAL32MLDOCTRL_STABMODE_Msk (0x03UL << ASYSCON_XTAL32MLDOCTRL_STABMODE_Pos)/*!< ASYSCON XTAL32MLDOCTRL: STABMODE Mask */
-
-/* ------------------------- u_async_syscon_XTAL32MCTRL ------------------------- */
-#define ASYSCON_XTAL32MCTRL_XO_ACBUF_PASS_ENABLE_Pos 0 /*!< ASYSCON XTAL32MCTRL: XO_ACBUF_PASS_ENABLE Position */
-#define ASYSCON_XTAL32MCTRL_XO_ACBUF_PASS_ENABLE_Msk (0x01UL << ASYSCON_XTAL32MCTRL_XO_ACBUF_PASS_ENABLE_Pos)/*!< ASYSCON XTAL32MCTRL: XO_ACBUF_PASS_ENABLE Mask */
-#define ASYSCON_XTAL32MCTRL_XO_AMP_Pos 1 /*!< ASYSCON XTAL32MCTRL: XO_AMP Position */
-#define ASYSCON_XTAL32MCTRL_XO_AMP_Msk (0x07UL << ASYSCON_XTAL32MCTRL_XO_AMP_Pos) /*!< ASYSCON XTAL32MCTRL: XO_AMP Mask */
-#define ASYSCON_XTAL32MCTRL_XO_OSC_CAP_IN_Pos 4 /*!< ASYSCON XTAL32MCTRL: XO_OSC_CAP_IN Position */
-#define ASYSCON_XTAL32MCTRL_XO_OSC_CAP_IN_Msk (0x7fUL << ASYSCON_XTAL32MCTRL_XO_OSC_CAP_IN_Pos)/*!< ASYSCON XTAL32MCTRL: XO_OSC_CAP_IN Mask */
-#define ASYSCON_XTAL32MCTRL_XO_OSC_CAP_OUT_Pos 11 /*!< ASYSCON XTAL32MCTRL: XO_OSC_CAP_OUT Position */
-#define ASYSCON_XTAL32MCTRL_XO_OSC_CAP_OUT_Msk (0x7fUL << ASYSCON_XTAL32MCTRL_XO_OSC_CAP_OUT_Pos)/*!< ASYSCON XTAL32MCTRL: XO_OSC_CAP_OUT Mask */
-#define ASYSCON_XTAL32MCTRL_XO_ENABLE_Pos 22 /*!< ASYSCON XTAL32MCTRL: XO_ENABLE Position */
-#define ASYSCON_XTAL32MCTRL_XO_ENABLE_Msk (0x01UL << ASYSCON_XTAL32MCTRL_XO_ENABLE_Pos) /*!< ASYSCON XTAL32MCTRL: XO_ENABLE Mask */
-#define ASYSCON_XTAL32MCTRL_XO_GM_Pos 23 /*!< ASYSCON XTAL32MCTRL: XO_GM Position */
-#define ASYSCON_XTAL32MCTRL_XO_GM_Msk (0x07UL << ASYSCON_XTAL32MCTRL_XO_GM_Pos) /*!< ASYSCON XTAL32MCTRL: XO_GM Mask */
-#define ASYSCON_XTAL32MCTRL_XO_SLAVE_Pos 26 /*!< ASYSCON XTAL32MCTRL: XO_SLAVE Position */
-#define ASYSCON_XTAL32MCTRL_XO_SLAVE_Msk (0x01UL << ASYSCON_XTAL32MCTRL_XO_SLAVE_Pos) /*!< ASYSCON XTAL32MCTRL: XO_SLAVE Mask */
-#define ASYSCON_XTAL32MCTRL_XO_STANDALONE_ENABLE_Pos 27 /*!< ASYSCON XTAL32MCTRL: XO_STANDALONE_ENABLE Position */
-#define ASYSCON_XTAL32MCTRL_XO_STANDALONE_ENABLE_Msk (0x01UL << ASYSCON_XTAL32MCTRL_XO_STANDALONE_ENABLE_Pos)/*!< ASYSCON XTAL32MCTRL: XO_STANDALONE_ENABLE Mask */
-#define ASYSCON_XTAL32MCTRL_XO32M_TO_MCU_ENABLE_Pos 28 /*!< ASYSCON XTAL32MCTRL: XO32M_TO_MCU_ENABLE Position */
-#define ASYSCON_XTAL32MCTRL_XO32M_TO_MCU_ENABLE_Msk (0x01UL << ASYSCON_XTAL32MCTRL_XO32M_TO_MCU_ENABLE_Pos)/*!< ASYSCON XTAL32MCTRL: XO32M_TO_MCU_ENABLE Mask */
-#define ASYSCON_XTAL32MCTRL_CLK_TO_GPADC_ENABLE_Pos 29 /*!< ASYSCON XTAL32MCTRL: CLK_TO_GPADC_ENABLE Position */
-#define ASYSCON_XTAL32MCTRL_CLK_TO_GPADC_ENABLE_Msk (0x01UL << ASYSCON_XTAL32MCTRL_CLK_TO_GPADC_ENABLE_Pos)/*!< ASYSCON XTAL32MCTRL: CLK_TO_GPADC_ENABLE Mask */
-
-/* --------------------------- u_async_syscon_ANALOGID -------------------------- */
-#define ASYSCON_ANALOGID_PMUID_Pos 0 /*!< ASYSCON ANALOGID: PMUID Position */
-#define ASYSCON_ANALOGID_PMUID_Msk (0x3fUL << ASYSCON_ANALOGID_PMUID_Pos) /*!< ASYSCON ANALOGID: PMUID Mask */
-#define ASYSCON_ANALOGID_RADIOID_Pos 6 /*!< ASYSCON ANALOGID: RADIOID Position */
-#define ASYSCON_ANALOGID_RADIOID_Msk (0x3fUL << ASYSCON_ANALOGID_RADIOID_Pos) /*!< ASYSCON ANALOGID: RADIOID Mask */
-
-/* ------------------------- u_async_syscon_RADIOSTATUS ------------------------- */
-#define ASYSCON_RADIOSTATUS_PLLXOREADY_Pos 0 /*!< ASYSCON RADIOSTATUS: PLLXOREADY Position */
-#define ASYSCON_RADIOSTATUS_PLLXOREADY_Msk (0x01UL << ASYSCON_RADIOSTATUS_PLLXOREADY_Pos)/*!< ASYSCON RADIOSTATUS: PLLXOREADY Mask */
-
-/* ------------------------ u_async_syscon_DIGITALSTATUS ------------------------ */
-#define ASYSCON_DIGITALSTATUS_FLASHINITERROR_Pos 0 /*!< ASYSCON DIGITALSTATUS: FLASHINITERROR Position */
-#define ASYSCON_DIGITALSTATUS_FLASHINITERROR_Msk (0x01UL << ASYSCON_DIGITALSTATUS_FLASHINITERROR_Pos)/*!< ASYSCON DIGITALSTATUS: FLASHINITERROR Mask */
-
-/* -------------------------- u_async_syscon_DCBUSCTRL -------------------------- */
-#define ASYSCON_DCBUSCTRL_ADDR_Pos 0 /*!< ASYSCON DCBUSCTRL: ADDR Position */
-#define ASYSCON_DCBUSCTRL_ADDR_Msk (0x000001ffUL << ASYSCON_DCBUSCTRL_ADDR_Pos) /*!< ASYSCON DCBUSCTRL: ADDR Mask */
-#define ASYSCON_DCBUSCTRL_MUX1_Pos 9 /*!< ASYSCON DCBUSCTRL: MUX1 Position */
-#define ASYSCON_DCBUSCTRL_MUX1_Msk (0x0fUL << ASYSCON_DCBUSCTRL_MUX1_Pos) /*!< ASYSCON DCBUSCTRL: MUX1 Mask */
-#define ASYSCON_DCBUSCTRL_MUX2_Pos 13 /*!< ASYSCON DCBUSCTRL: MUX2 Position */
-#define ASYSCON_DCBUSCTRL_MUX2_Msk (0x0fUL << ASYSCON_DCBUSCTRL_MUX2_Pos) /*!< ASYSCON DCBUSCTRL: MUX2 Mask */
-
-/* -------------------------- u_async_syscon_FREQMECTRL ------------------------- */
-#define ASYSCON_FREQMECTRL_CAPVAL_SCALE_Pos 0 /*!< ASYSCON FREQMECTRL: CAPVAL_SCALE Position */
-#define ASYSCON_FREQMECTRL_CAPVAL_SCALE_Msk (0x7fffffffUL << ASYSCON_FREQMECTRL_CAPVAL_SCALE_Pos)/*!< ASYSCON FREQMECTRL: CAPVAL_SCALE Mask */
-#define ASYSCON_FREQMECTRL_PROG_Pos 31 /*!< ASYSCON FREQMECTRL: PROG Position */
-#define ASYSCON_FREQMECTRL_PROG_Msk (0x01UL << ASYSCON_FREQMECTRL_PROG_Pos) /*!< ASYSCON FREQMECTRL: PROG Mask */
-
-/* ----------------------- u_async_syscon_NFCTAGINTSTATUS ----------------------- */
-#define ASYSCON_NFCTAGINTSTATUS_NFCTAGINT_Pos 0 /*!< ASYSCON NFCTAGINTSTATUS: NFCTAGINT Position */
-#define ASYSCON_NFCTAGINTSTATUS_NFCTAGINT_Msk (0x01UL << ASYSCON_NFCTAGINTSTATUS_NFCTAGINT_Pos)/*!< ASYSCON NFCTAGINTSTATUS: NFCTAGINT Mask */
-
-/* -------------------------- u_async_syscon_NFCTAG_VDD ------------------------- */
-#define ASYSCON_NFCTAG_VDD_NFCTAG_VDD_OUT_Pos 0 /*!< ASYSCON NFCTAG_VDD: NFCTAG_VDD_OUT Position */
-#define ASYSCON_NFCTAG_VDD_NFCTAG_VDD_OUT_Msk (0x01UL << ASYSCON_NFCTAG_VDD_NFCTAG_VDD_OUT_Pos)/*!< ASYSCON NFCTAG_VDD: NFCTAG_VDD_OUT Mask */
-#define ASYSCON_NFCTAG_VDD_NFCTAG_VDD_OE_Pos 1 /*!< ASYSCON NFCTAG_VDD: NFCTAG_VDD_OE Position */
-#define ASYSCON_NFCTAG_VDD_NFCTAG_VDD_OE_Msk (0x01UL << ASYSCON_NFCTAG_VDD_NFCTAG_VDD_OE_Pos)/*!< ASYSCON NFCTAG_VDD: NFCTAG_VDD_OE Mask */
-
-/* ------------------------- u_async_syscon_SWRESETCTRL ------------------------- */
-#define ASYSCON_SWRESETCTRL_ICRESETREQ_Pos 0 /*!< ASYSCON SWRESETCTRL: ICRESETREQ Position */
-#define ASYSCON_SWRESETCTRL_ICRESETREQ_Msk (0x01UL << ASYSCON_SWRESETCTRL_ICRESETREQ_Pos)/*!< ASYSCON SWRESETCTRL: ICRESETREQ Mask */
-#define ASYSCON_SWRESETCTRL_VECTKEY_Pos 16 /*!< ASYSCON SWRESETCTRL: VECTKEY Position */
-#define ASYSCON_SWRESETCTRL_VECTKEY_Msk (0x0000ffffUL << ASYSCON_SWRESETCTRL_VECTKEY_Pos)/*!< ASYSCON SWRESETCTRL: VECTKEY Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u0_timer' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* --------------------------------- u0_timer_IR -------------------------------- */
-#define CTIMER0_IR_MR0INT_Pos 0 /*!< CTIMER0 IR: MR0INT Position */
-#define CTIMER0_IR_MR0INT_Msk (0x01UL << CTIMER0_IR_MR0INT_Pos) /*!< CTIMER0 IR: MR0INT Mask */
-#define CTIMER0_IR_MR1INT_Pos 1 /*!< CTIMER0 IR: MR1INT Position */
-#define CTIMER0_IR_MR1INT_Msk (0x01UL << CTIMER0_IR_MR1INT_Pos) /*!< CTIMER0 IR: MR1INT Mask */
-#define CTIMER0_IR_MR2INT_Pos 2 /*!< CTIMER0 IR: MR2INT Position */
-#define CTIMER0_IR_MR2INT_Msk (0x01UL << CTIMER0_IR_MR2INT_Pos) /*!< CTIMER0 IR: MR2INT Mask */
-#define CTIMER0_IR_MR3INT_Pos 3 /*!< CTIMER0 IR: MR3INT Position */
-#define CTIMER0_IR_MR3INT_Msk (0x01UL << CTIMER0_IR_MR3INT_Pos) /*!< CTIMER0 IR: MR3INT Mask */
-#define CTIMER0_IR_CR0INT_Pos 4 /*!< CTIMER0 IR: CR0INT Position */
-#define CTIMER0_IR_CR0INT_Msk (0x01UL << CTIMER0_IR_CR0INT_Pos) /*!< CTIMER0 IR: CR0INT Mask */
-#define CTIMER0_IR_CR1INT_Pos 5 /*!< CTIMER0 IR: CR1INT Position */
-#define CTIMER0_IR_CR1INT_Msk (0x01UL << CTIMER0_IR_CR1INT_Pos) /*!< CTIMER0 IR: CR1INT Mask */
-#define CTIMER0_IR_CR2INT_Pos 6 /*!< CTIMER0 IR: CR2INT Position */
-#define CTIMER0_IR_CR2INT_Msk (0x01UL << CTIMER0_IR_CR2INT_Pos) /*!< CTIMER0 IR: CR2INT Mask */
-#define CTIMER0_IR_CR3INT_Pos 7 /*!< CTIMER0 IR: CR3INT Position */
-#define CTIMER0_IR_CR3INT_Msk (0x01UL << CTIMER0_IR_CR3INT_Pos) /*!< CTIMER0 IR: CR3INT Mask */
-
-/* -------------------------------- u0_timer_TCR -------------------------------- */
-#define CTIMER0_TCR_CEN_Pos 0 /*!< CTIMER0 TCR: CEN Position */
-#define CTIMER0_TCR_CEN_Msk (0x01UL << CTIMER0_TCR_CEN_Pos) /*!< CTIMER0 TCR: CEN Mask */
-#define CTIMER0_TCR_CRST_Pos 1 /*!< CTIMER0 TCR: CRST Position */
-#define CTIMER0_TCR_CRST_Msk (0x01UL << CTIMER0_TCR_CRST_Pos) /*!< CTIMER0 TCR: CRST Mask */
-
-/* --------------------------------- u0_timer_TC -------------------------------- */
-#define CTIMER0_TC_TCVAL_Pos 0 /*!< CTIMER0 TC: TCVAL Position */
-#define CTIMER0_TC_TCVAL_Msk (0xffffffffUL << CTIMER0_TC_TCVAL_Pos) /*!< CTIMER0 TC: TCVAL Mask */
-
-/* --------------------------------- u0_timer_PR -------------------------------- */
-#define CTIMER0_PR_PRVAL_Pos 0 /*!< CTIMER0 PR: PRVAL Position */
-#define CTIMER0_PR_PRVAL_Msk (0xffffffffUL << CTIMER0_PR_PRVAL_Pos) /*!< CTIMER0 PR: PRVAL Mask */
-
-/* --------------------------------- u0_timer_PC -------------------------------- */
-#define CTIMER0_PC_PCVAL_Pos 0 /*!< CTIMER0 PC: PCVAL Position */
-#define CTIMER0_PC_PCVAL_Msk (0xffffffffUL << CTIMER0_PC_PCVAL_Pos) /*!< CTIMER0 PC: PCVAL Mask */
-
-/* -------------------------------- u0_timer_MCR -------------------------------- */
-#define CTIMER0_MCR_MR0I_Pos 0 /*!< CTIMER0 MCR: MR0I Position */
-#define CTIMER0_MCR_MR0I_Msk (0x01UL << CTIMER0_MCR_MR0I_Pos) /*!< CTIMER0 MCR: MR0I Mask */
-#define CTIMER0_MCR_MR0R_Pos 1 /*!< CTIMER0 MCR: MR0R Position */
-#define CTIMER0_MCR_MR0R_Msk (0x01UL << CTIMER0_MCR_MR0R_Pos) /*!< CTIMER0 MCR: MR0R Mask */
-#define CTIMER0_MCR_MR0S_Pos 2 /*!< CTIMER0 MCR: MR0S Position */
-#define CTIMER0_MCR_MR0S_Msk (0x01UL << CTIMER0_MCR_MR0S_Pos) /*!< CTIMER0 MCR: MR0S Mask */
-#define CTIMER0_MCR_MR1I_Pos 3 /*!< CTIMER0 MCR: MR1I Position */
-#define CTIMER0_MCR_MR1I_Msk (0x01UL << CTIMER0_MCR_MR1I_Pos) /*!< CTIMER0 MCR: MR1I Mask */
-#define CTIMER0_MCR_MR1R_Pos 4 /*!< CTIMER0 MCR: MR1R Position */
-#define CTIMER0_MCR_MR1R_Msk (0x01UL << CTIMER0_MCR_MR1R_Pos) /*!< CTIMER0 MCR: MR1R Mask */
-#define CTIMER0_MCR_MR1S_Pos 5 /*!< CTIMER0 MCR: MR1S Position */
-#define CTIMER0_MCR_MR1S_Msk (0x01UL << CTIMER0_MCR_MR1S_Pos) /*!< CTIMER0 MCR: MR1S Mask */
-#define CTIMER0_MCR_MR2I_Pos 6 /*!< CTIMER0 MCR: MR2I Position */
-#define CTIMER0_MCR_MR2I_Msk (0x01UL << CTIMER0_MCR_MR2I_Pos) /*!< CTIMER0 MCR: MR2I Mask */
-#define CTIMER0_MCR_MR2R_Pos 7 /*!< CTIMER0 MCR: MR2R Position */
-#define CTIMER0_MCR_MR2R_Msk (0x01UL << CTIMER0_MCR_MR2R_Pos) /*!< CTIMER0 MCR: MR2R Mask */
-#define CTIMER0_MCR_MR2S_Pos 8 /*!< CTIMER0 MCR: MR2S Position */
-#define CTIMER0_MCR_MR2S_Msk (0x01UL << CTIMER0_MCR_MR2S_Pos) /*!< CTIMER0 MCR: MR2S Mask */
-#define CTIMER0_MCR_MR3I_Pos 9 /*!< CTIMER0 MCR: MR3I Position */
-#define CTIMER0_MCR_MR3I_Msk (0x01UL << CTIMER0_MCR_MR3I_Pos) /*!< CTIMER0 MCR: MR3I Mask */
-#define CTIMER0_MCR_MR3R_Pos 10 /*!< CTIMER0 MCR: MR3R Position */
-#define CTIMER0_MCR_MR3R_Msk (0x01UL << CTIMER0_MCR_MR3R_Pos) /*!< CTIMER0 MCR: MR3R Mask */
-#define CTIMER0_MCR_MR3S_Pos 11 /*!< CTIMER0 MCR: MR3S Position */
-#define CTIMER0_MCR_MR3S_Msk (0x01UL << CTIMER0_MCR_MR3S_Pos) /*!< CTIMER0 MCR: MR3S Mask */
-
-/* -------------------------------- u0_timer_MR0 -------------------------------- */
-#define CTIMER0_MR0_MATCH_Pos 0 /*!< CTIMER0 MR0: MATCH Position */
-#define CTIMER0_MR0_MATCH_Msk (0xffffffffUL << CTIMER0_MR0_MATCH_Pos) /*!< CTIMER0 MR0: MATCH Mask */
-
-/* -------------------------------- u0_timer_MR1 -------------------------------- */
-#define CTIMER0_MR1_MATCH_Pos 0 /*!< CTIMER0 MR1: MATCH Position */
-#define CTIMER0_MR1_MATCH_Msk (0xffffffffUL << CTIMER0_MR1_MATCH_Pos) /*!< CTIMER0 MR1: MATCH Mask */
-
-/* -------------------------------- u0_timer_MR2 -------------------------------- */
-#define CTIMER0_MR2_MATCH_Pos 0 /*!< CTIMER0 MR2: MATCH Position */
-#define CTIMER0_MR2_MATCH_Msk (0xffffffffUL << CTIMER0_MR2_MATCH_Pos) /*!< CTIMER0 MR2: MATCH Mask */
-
-/* -------------------------------- u0_timer_MR3 -------------------------------- */
-#define CTIMER0_MR3_MATCH_Pos 0 /*!< CTIMER0 MR3: MATCH Position */
-#define CTIMER0_MR3_MATCH_Msk (0xffffffffUL << CTIMER0_MR3_MATCH_Pos) /*!< CTIMER0 MR3: MATCH Mask */
-
-/* -------------------------------- u0_timer_CCR -------------------------------- */
-#define CTIMER0_CCR_CAP0RE_Pos 0 /*!< CTIMER0 CCR: CAP0RE Position */
-#define CTIMER0_CCR_CAP0RE_Msk (0x01UL << CTIMER0_CCR_CAP0RE_Pos) /*!< CTIMER0 CCR: CAP0RE Mask */
-#define CTIMER0_CCR_CAP0FE_Pos 1 /*!< CTIMER0 CCR: CAP0FE Position */
-#define CTIMER0_CCR_CAP0FE_Msk (0x01UL << CTIMER0_CCR_CAP0FE_Pos) /*!< CTIMER0 CCR: CAP0FE Mask */
-#define CTIMER0_CCR_CAP0I_Pos 2 /*!< CTIMER0 CCR: CAP0I Position */
-#define CTIMER0_CCR_CAP0I_Msk (0x01UL << CTIMER0_CCR_CAP0I_Pos) /*!< CTIMER0 CCR: CAP0I Mask */
-#define CTIMER0_CCR_CAP1RE_Pos 3 /*!< CTIMER0 CCR: CAP1RE Position */
-#define CTIMER0_CCR_CAP1RE_Msk (0x01UL << CTIMER0_CCR_CAP1RE_Pos) /*!< CTIMER0 CCR: CAP1RE Mask */
-#define CTIMER0_CCR_CAP1FE_Pos 4 /*!< CTIMER0 CCR: CAP1FE Position */
-#define CTIMER0_CCR_CAP1FE_Msk (0x01UL << CTIMER0_CCR_CAP1FE_Pos) /*!< CTIMER0 CCR: CAP1FE Mask */
-#define CTIMER0_CCR_CAP1I_Pos 5 /*!< CTIMER0 CCR: CAP1I Position */
-#define CTIMER0_CCR_CAP1I_Msk (0x01UL << CTIMER0_CCR_CAP1I_Pos) /*!< CTIMER0 CCR: CAP1I Mask */
-#define CTIMER0_CCR_CAP2RE_Pos 6 /*!< CTIMER0 CCR: CAP2RE Position */
-#define CTIMER0_CCR_CAP2RE_Msk (0x01UL << CTIMER0_CCR_CAP2RE_Pos) /*!< CTIMER0 CCR: CAP2RE Mask */
-#define CTIMER0_CCR_CAP2FE_Pos 7 /*!< CTIMER0 CCR: CAP2FE Position */
-#define CTIMER0_CCR_CAP2FE_Msk (0x01UL << CTIMER0_CCR_CAP2FE_Pos) /*!< CTIMER0 CCR: CAP2FE Mask */
-#define CTIMER0_CCR_CAP2I_Pos 8 /*!< CTIMER0 CCR: CAP2I Position */
-#define CTIMER0_CCR_CAP2I_Msk (0x01UL << CTIMER0_CCR_CAP2I_Pos) /*!< CTIMER0 CCR: CAP2I Mask */
-#define CTIMER0_CCR_CAP3RE_Pos 9 /*!< CTIMER0 CCR: CAP3RE Position */
-#define CTIMER0_CCR_CAP3RE_Msk (0x01UL << CTIMER0_CCR_CAP3RE_Pos) /*!< CTIMER0 CCR: CAP3RE Mask */
-#define CTIMER0_CCR_CAP3FE_Pos 10 /*!< CTIMER0 CCR: CAP3FE Position */
-#define CTIMER0_CCR_CAP3FE_Msk (0x01UL << CTIMER0_CCR_CAP3FE_Pos) /*!< CTIMER0 CCR: CAP3FE Mask */
-#define CTIMER0_CCR_CAP3I_Pos 11 /*!< CTIMER0 CCR: CAP3I Position */
-#define CTIMER0_CCR_CAP3I_Msk (0x01UL << CTIMER0_CCR_CAP3I_Pos) /*!< CTIMER0 CCR: CAP3I Mask */
-
-/* -------------------------------- u0_timer_CR0 -------------------------------- */
-#define CTIMER0_CR0_CAP_Pos 0 /*!< CTIMER0 CR0: CAP Position */
-#define CTIMER0_CR0_CAP_Msk (0xffffffffUL << CTIMER0_CR0_CAP_Pos) /*!< CTIMER0 CR0: CAP Mask */
-
-/* -------------------------------- u0_timer_CR1 -------------------------------- */
-#define CTIMER0_CR1_CAP_Pos 0 /*!< CTIMER0 CR1: CAP Position */
-#define CTIMER0_CR1_CAP_Msk (0xffffffffUL << CTIMER0_CR1_CAP_Pos) /*!< CTIMER0 CR1: CAP Mask */
-
-/* -------------------------------- u0_timer_CR2 -------------------------------- */
-#define CTIMER0_CR2_CAP_Pos 0 /*!< CTIMER0 CR2: CAP Position */
-#define CTIMER0_CR2_CAP_Msk (0xffffffffUL << CTIMER0_CR2_CAP_Pos) /*!< CTIMER0 CR2: CAP Mask */
-
-/* -------------------------------- u0_timer_CR3 -------------------------------- */
-#define CTIMER0_CR3_CAP_Pos 0 /*!< CTIMER0 CR3: CAP Position */
-#define CTIMER0_CR3_CAP_Msk (0xffffffffUL << CTIMER0_CR3_CAP_Pos) /*!< CTIMER0 CR3: CAP Mask */
-
-/* -------------------------------- u0_timer_EMR -------------------------------- */
-#define CTIMER0_EMR_EM0_Pos 0 /*!< CTIMER0 EMR: EM0 Position */
-#define CTIMER0_EMR_EM0_Msk (0x01UL << CTIMER0_EMR_EM0_Pos) /*!< CTIMER0 EMR: EM0 Mask */
-#define CTIMER0_EMR_EM1_Pos 1 /*!< CTIMER0 EMR: EM1 Position */
-#define CTIMER0_EMR_EM1_Msk (0x01UL << CTIMER0_EMR_EM1_Pos) /*!< CTIMER0 EMR: EM1 Mask */
-#define CTIMER0_EMR_EM2_Pos 2 /*!< CTIMER0 EMR: EM2 Position */
-#define CTIMER0_EMR_EM2_Msk (0x01UL << CTIMER0_EMR_EM2_Pos) /*!< CTIMER0 EMR: EM2 Mask */
-#define CTIMER0_EMR_EM3_Pos 3 /*!< CTIMER0 EMR: EM3 Position */
-#define CTIMER0_EMR_EM3_Msk (0x01UL << CTIMER0_EMR_EM3_Pos) /*!< CTIMER0 EMR: EM3 Mask */
-#define CTIMER0_EMR_EMC0_Pos 4 /*!< CTIMER0 EMR: EMC0 Position */
-#define CTIMER0_EMR_EMC0_Msk (0x03UL << CTIMER0_EMR_EMC0_Pos) /*!< CTIMER0 EMR: EMC0 Mask */
-#define CTIMER0_EMR_EMC1_Pos 6 /*!< CTIMER0 EMR: EMC1 Position */
-#define CTIMER0_EMR_EMC1_Msk (0x03UL << CTIMER0_EMR_EMC1_Pos) /*!< CTIMER0 EMR: EMC1 Mask */
-#define CTIMER0_EMR_EMC2_Pos 8 /*!< CTIMER0 EMR: EMC2 Position */
-#define CTIMER0_EMR_EMC2_Msk (0x03UL << CTIMER0_EMR_EMC2_Pos) /*!< CTIMER0 EMR: EMC2 Mask */
-#define CTIMER0_EMR_EMC3_Pos 10 /*!< CTIMER0 EMR: EMC3 Position */
-#define CTIMER0_EMR_EMC3_Msk (0x03UL << CTIMER0_EMR_EMC3_Pos) /*!< CTIMER0 EMR: EMC3 Mask */
-
-/* -------------------------------- u0_timer_CTCR ------------------------------- */
-#define CTIMER0_CTCR_CTMODE_Pos 0 /*!< CTIMER0 CTCR: CTMODE Position */
-#define CTIMER0_CTCR_CTMODE_Msk (0x03UL << CTIMER0_CTCR_CTMODE_Pos) /*!< CTIMER0 CTCR: CTMODE Mask */
-#define CTIMER0_CTCR_CINSEL_Pos 2 /*!< CTIMER0 CTCR: CINSEL Position */
-#define CTIMER0_CTCR_CINSEL_Msk (0x03UL << CTIMER0_CTCR_CINSEL_Pos) /*!< CTIMER0 CTCR: CINSEL Mask */
-#define CTIMER0_CTCR_ENCC_Pos 4 /*!< CTIMER0 CTCR: ENCC Position */
-#define CTIMER0_CTCR_ENCC_Msk (0x01UL << CTIMER0_CTCR_ENCC_Pos) /*!< CTIMER0 CTCR: ENCC Mask */
-#define CTIMER0_CTCR_SELCC_Pos 5 /*!< CTIMER0 CTCR: SELCC Position */
-#define CTIMER0_CTCR_SELCC_Msk (0x07UL << CTIMER0_CTCR_SELCC_Pos) /*!< CTIMER0 CTCR: SELCC Mask */
-
-/* -------------------------------- u0_timer_PWMC ------------------------------- */
-#define CTIMER0_PWMC_PWMEN0_Pos 0 /*!< CTIMER0 PWMC: PWMEN0 Position */
-#define CTIMER0_PWMC_PWMEN0_Msk (0x01UL << CTIMER0_PWMC_PWMEN0_Pos) /*!< CTIMER0 PWMC: PWMEN0 Mask */
-#define CTIMER0_PWMC_PWMEN1_Pos 1 /*!< CTIMER0 PWMC: PWMEN1 Position */
-#define CTIMER0_PWMC_PWMEN1_Msk (0x01UL << CTIMER0_PWMC_PWMEN1_Pos) /*!< CTIMER0 PWMC: PWMEN1 Mask */
-#define CTIMER0_PWMC_PWMEN2_Pos 2 /*!< CTIMER0 PWMC: PWMEN2 Position */
-#define CTIMER0_PWMC_PWMEN2_Msk (0x01UL << CTIMER0_PWMC_PWMEN2_Pos) /*!< CTIMER0 PWMC: PWMEN2 Mask */
-#define CTIMER0_PWMC_PWMEN3_Pos 3 /*!< CTIMER0 PWMC: PWMEN3 Position */
-#define CTIMER0_PWMC_PWMEN3_Msk (0x01UL << CTIMER0_PWMC_PWMEN3_Pos) /*!< CTIMER0 PWMC: PWMEN3 Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u1_timer' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* --------------------------------- u1_timer_IR -------------------------------- */
-#define CTIMER1_IR_MR0INT_Pos 0 /*!< CTIMER1 IR: MR0INT Position */
-#define CTIMER1_IR_MR0INT_Msk (0x01UL << CTIMER1_IR_MR0INT_Pos) /*!< CTIMER1 IR: MR0INT Mask */
-#define CTIMER1_IR_MR1INT_Pos 1 /*!< CTIMER1 IR: MR1INT Position */
-#define CTIMER1_IR_MR1INT_Msk (0x01UL << CTIMER1_IR_MR1INT_Pos) /*!< CTIMER1 IR: MR1INT Mask */
-#define CTIMER1_IR_MR2INT_Pos 2 /*!< CTIMER1 IR: MR2INT Position */
-#define CTIMER1_IR_MR2INT_Msk (0x01UL << CTIMER1_IR_MR2INT_Pos) /*!< CTIMER1 IR: MR2INT Mask */
-#define CTIMER1_IR_MR3INT_Pos 3 /*!< CTIMER1 IR: MR3INT Position */
-#define CTIMER1_IR_MR3INT_Msk (0x01UL << CTIMER1_IR_MR3INT_Pos) /*!< CTIMER1 IR: MR3INT Mask */
-#define CTIMER1_IR_CR0INT_Pos 4 /*!< CTIMER1 IR: CR0INT Position */
-#define CTIMER1_IR_CR0INT_Msk (0x01UL << CTIMER1_IR_CR0INT_Pos) /*!< CTIMER1 IR: CR0INT Mask */
-#define CTIMER1_IR_CR1INT_Pos 5 /*!< CTIMER1 IR: CR1INT Position */
-#define CTIMER1_IR_CR1INT_Msk (0x01UL << CTIMER1_IR_CR1INT_Pos) /*!< CTIMER1 IR: CR1INT Mask */
-#define CTIMER1_IR_CR2INT_Pos 6 /*!< CTIMER1 IR: CR2INT Position */
-#define CTIMER1_IR_CR2INT_Msk (0x01UL << CTIMER1_IR_CR2INT_Pos) /*!< CTIMER1 IR: CR2INT Mask */
-#define CTIMER1_IR_CR3INT_Pos 7 /*!< CTIMER1 IR: CR3INT Position */
-#define CTIMER1_IR_CR3INT_Msk (0x01UL << CTIMER1_IR_CR3INT_Pos) /*!< CTIMER1 IR: CR3INT Mask */
-
-/* -------------------------------- u1_timer_TCR -------------------------------- */
-#define CTIMER1_TCR_CEN_Pos 0 /*!< CTIMER1 TCR: CEN Position */
-#define CTIMER1_TCR_CEN_Msk (0x01UL << CTIMER1_TCR_CEN_Pos) /*!< CTIMER1 TCR: CEN Mask */
-#define CTIMER1_TCR_CRST_Pos 1 /*!< CTIMER1 TCR: CRST Position */
-#define CTIMER1_TCR_CRST_Msk (0x01UL << CTIMER1_TCR_CRST_Pos) /*!< CTIMER1 TCR: CRST Mask */
-
-/* --------------------------------- u1_timer_TC -------------------------------- */
-#define CTIMER1_TC_TCVAL_Pos 0 /*!< CTIMER1 TC: TCVAL Position */
-#define CTIMER1_TC_TCVAL_Msk (0xffffffffUL << CTIMER1_TC_TCVAL_Pos) /*!< CTIMER1 TC: TCVAL Mask */
-
-/* --------------------------------- u1_timer_PR -------------------------------- */
-#define CTIMER1_PR_PRVAL_Pos 0 /*!< CTIMER1 PR: PRVAL Position */
-#define CTIMER1_PR_PRVAL_Msk (0xffffffffUL << CTIMER1_PR_PRVAL_Pos) /*!< CTIMER1 PR: PRVAL Mask */
-
-/* --------------------------------- u1_timer_PC -------------------------------- */
-#define CTIMER1_PC_PCVAL_Pos 0 /*!< CTIMER1 PC: PCVAL Position */
-#define CTIMER1_PC_PCVAL_Msk (0xffffffffUL << CTIMER1_PC_PCVAL_Pos) /*!< CTIMER1 PC: PCVAL Mask */
-
-/* -------------------------------- u1_timer_MCR -------------------------------- */
-#define CTIMER1_MCR_MR0I_Pos 0 /*!< CTIMER1 MCR: MR0I Position */
-#define CTIMER1_MCR_MR0I_Msk (0x01UL << CTIMER1_MCR_MR0I_Pos) /*!< CTIMER1 MCR: MR0I Mask */
-#define CTIMER1_MCR_MR0R_Pos 1 /*!< CTIMER1 MCR: MR0R Position */
-#define CTIMER1_MCR_MR0R_Msk (0x01UL << CTIMER1_MCR_MR0R_Pos) /*!< CTIMER1 MCR: MR0R Mask */
-#define CTIMER1_MCR_MR0S_Pos 2 /*!< CTIMER1 MCR: MR0S Position */
-#define CTIMER1_MCR_MR0S_Msk (0x01UL << CTIMER1_MCR_MR0S_Pos) /*!< CTIMER1 MCR: MR0S Mask */
-#define CTIMER1_MCR_MR1I_Pos 3 /*!< CTIMER1 MCR: MR1I Position */
-#define CTIMER1_MCR_MR1I_Msk (0x01UL << CTIMER1_MCR_MR1I_Pos) /*!< CTIMER1 MCR: MR1I Mask */
-#define CTIMER1_MCR_MR1R_Pos 4 /*!< CTIMER1 MCR: MR1R Position */
-#define CTIMER1_MCR_MR1R_Msk (0x01UL << CTIMER1_MCR_MR1R_Pos) /*!< CTIMER1 MCR: MR1R Mask */
-#define CTIMER1_MCR_MR1S_Pos 5 /*!< CTIMER1 MCR: MR1S Position */
-#define CTIMER1_MCR_MR1S_Msk (0x01UL << CTIMER1_MCR_MR1S_Pos) /*!< CTIMER1 MCR: MR1S Mask */
-#define CTIMER1_MCR_MR2I_Pos 6 /*!< CTIMER1 MCR: MR2I Position */
-#define CTIMER1_MCR_MR2I_Msk (0x01UL << CTIMER1_MCR_MR2I_Pos) /*!< CTIMER1 MCR: MR2I Mask */
-#define CTIMER1_MCR_MR2R_Pos 7 /*!< CTIMER1 MCR: MR2R Position */
-#define CTIMER1_MCR_MR2R_Msk (0x01UL << CTIMER1_MCR_MR2R_Pos) /*!< CTIMER1 MCR: MR2R Mask */
-#define CTIMER1_MCR_MR2S_Pos 8 /*!< CTIMER1 MCR: MR2S Position */
-#define CTIMER1_MCR_MR2S_Msk (0x01UL << CTIMER1_MCR_MR2S_Pos) /*!< CTIMER1 MCR: MR2S Mask */
-#define CTIMER1_MCR_MR3I_Pos 9 /*!< CTIMER1 MCR: MR3I Position */
-#define CTIMER1_MCR_MR3I_Msk (0x01UL << CTIMER1_MCR_MR3I_Pos) /*!< CTIMER1 MCR: MR3I Mask */
-#define CTIMER1_MCR_MR3R_Pos 10 /*!< CTIMER1 MCR: MR3R Position */
-#define CTIMER1_MCR_MR3R_Msk (0x01UL << CTIMER1_MCR_MR3R_Pos) /*!< CTIMER1 MCR: MR3R Mask */
-#define CTIMER1_MCR_MR3S_Pos 11 /*!< CTIMER1 MCR: MR3S Position */
-#define CTIMER1_MCR_MR3S_Msk (0x01UL << CTIMER1_MCR_MR3S_Pos) /*!< CTIMER1 MCR: MR3S Mask */
-
-/* -------------------------------- u1_timer_MR0 -------------------------------- */
-#define CTIMER1_MR0_MATCH_Pos 0 /*!< CTIMER1 MR0: MATCH Position */
-#define CTIMER1_MR0_MATCH_Msk (0xffffffffUL << CTIMER1_MR0_MATCH_Pos) /*!< CTIMER1 MR0: MATCH Mask */
-
-/* -------------------------------- u1_timer_MR1 -------------------------------- */
-#define CTIMER1_MR1_MATCH_Pos 0 /*!< CTIMER1 MR1: MATCH Position */
-#define CTIMER1_MR1_MATCH_Msk (0xffffffffUL << CTIMER1_MR1_MATCH_Pos) /*!< CTIMER1 MR1: MATCH Mask */
-
-/* -------------------------------- u1_timer_MR2 -------------------------------- */
-#define CTIMER1_MR2_MATCH_Pos 0 /*!< CTIMER1 MR2: MATCH Position */
-#define CTIMER1_MR2_MATCH_Msk (0xffffffffUL << CTIMER1_MR2_MATCH_Pos) /*!< CTIMER1 MR2: MATCH Mask */
-
-/* -------------------------------- u1_timer_MR3 -------------------------------- */
-#define CTIMER1_MR3_MATCH_Pos 0 /*!< CTIMER1 MR3: MATCH Position */
-#define CTIMER1_MR3_MATCH_Msk (0xffffffffUL << CTIMER1_MR3_MATCH_Pos) /*!< CTIMER1 MR3: MATCH Mask */
-
-/* -------------------------------- u1_timer_CCR -------------------------------- */
-#define CTIMER1_CCR_CAP0RE_Pos 0 /*!< CTIMER1 CCR: CAP0RE Position */
-#define CTIMER1_CCR_CAP0RE_Msk (0x01UL << CTIMER1_CCR_CAP0RE_Pos) /*!< CTIMER1 CCR: CAP0RE Mask */
-#define CTIMER1_CCR_CAP0FE_Pos 1 /*!< CTIMER1 CCR: CAP0FE Position */
-#define CTIMER1_CCR_CAP0FE_Msk (0x01UL << CTIMER1_CCR_CAP0FE_Pos) /*!< CTIMER1 CCR: CAP0FE Mask */
-#define CTIMER1_CCR_CAP0I_Pos 2 /*!< CTIMER1 CCR: CAP0I Position */
-#define CTIMER1_CCR_CAP0I_Msk (0x01UL << CTIMER1_CCR_CAP0I_Pos) /*!< CTIMER1 CCR: CAP0I Mask */
-#define CTIMER1_CCR_CAP1RE_Pos 3 /*!< CTIMER1 CCR: CAP1RE Position */
-#define CTIMER1_CCR_CAP1RE_Msk (0x01UL << CTIMER1_CCR_CAP1RE_Pos) /*!< CTIMER1 CCR: CAP1RE Mask */
-#define CTIMER1_CCR_CAP1FE_Pos 4 /*!< CTIMER1 CCR: CAP1FE Position */
-#define CTIMER1_CCR_CAP1FE_Msk (0x01UL << CTIMER1_CCR_CAP1FE_Pos) /*!< CTIMER1 CCR: CAP1FE Mask */
-#define CTIMER1_CCR_CAP1I_Pos 5 /*!< CTIMER1 CCR: CAP1I Position */
-#define CTIMER1_CCR_CAP1I_Msk (0x01UL << CTIMER1_CCR_CAP1I_Pos) /*!< CTIMER1 CCR: CAP1I Mask */
-#define CTIMER1_CCR_CAP2RE_Pos 6 /*!< CTIMER1 CCR: CAP2RE Position */
-#define CTIMER1_CCR_CAP2RE_Msk (0x01UL << CTIMER1_CCR_CAP2RE_Pos) /*!< CTIMER1 CCR: CAP2RE Mask */
-#define CTIMER1_CCR_CAP2FE_Pos 7 /*!< CTIMER1 CCR: CAP2FE Position */
-#define CTIMER1_CCR_CAP2FE_Msk (0x01UL << CTIMER1_CCR_CAP2FE_Pos) /*!< CTIMER1 CCR: CAP2FE Mask */
-#define CTIMER1_CCR_CAP2I_Pos 8 /*!< CTIMER1 CCR: CAP2I Position */
-#define CTIMER1_CCR_CAP2I_Msk (0x01UL << CTIMER1_CCR_CAP2I_Pos) /*!< CTIMER1 CCR: CAP2I Mask */
-#define CTIMER1_CCR_CAP3RE_Pos 9 /*!< CTIMER1 CCR: CAP3RE Position */
-#define CTIMER1_CCR_CAP3RE_Msk (0x01UL << CTIMER1_CCR_CAP3RE_Pos) /*!< CTIMER1 CCR: CAP3RE Mask */
-#define CTIMER1_CCR_CAP3FE_Pos 10 /*!< CTIMER1 CCR: CAP3FE Position */
-#define CTIMER1_CCR_CAP3FE_Msk (0x01UL << CTIMER1_CCR_CAP3FE_Pos) /*!< CTIMER1 CCR: CAP3FE Mask */
-#define CTIMER1_CCR_CAP3I_Pos 11 /*!< CTIMER1 CCR: CAP3I Position */
-#define CTIMER1_CCR_CAP3I_Msk (0x01UL << CTIMER1_CCR_CAP3I_Pos) /*!< CTIMER1 CCR: CAP3I Mask */
-
-/* -------------------------------- u1_timer_CR0 -------------------------------- */
-#define CTIMER1_CR0_CAP_Pos 0 /*!< CTIMER1 CR0: CAP Position */
-#define CTIMER1_CR0_CAP_Msk (0xffffffffUL << CTIMER1_CR0_CAP_Pos) /*!< CTIMER1 CR0: CAP Mask */
-
-/* -------------------------------- u1_timer_CR1 -------------------------------- */
-#define CTIMER1_CR1_CAP_Pos 0 /*!< CTIMER1 CR1: CAP Position */
-#define CTIMER1_CR1_CAP_Msk (0xffffffffUL << CTIMER1_CR1_CAP_Pos) /*!< CTIMER1 CR1: CAP Mask */
-
-/* -------------------------------- u1_timer_CR2 -------------------------------- */
-#define CTIMER1_CR2_CAP_Pos 0 /*!< CTIMER1 CR2: CAP Position */
-#define CTIMER1_CR2_CAP_Msk (0xffffffffUL << CTIMER1_CR2_CAP_Pos) /*!< CTIMER1 CR2: CAP Mask */
-
-/* -------------------------------- u1_timer_CR3 -------------------------------- */
-#define CTIMER1_CR3_CAP_Pos 0 /*!< CTIMER1 CR3: CAP Position */
-#define CTIMER1_CR3_CAP_Msk (0xffffffffUL << CTIMER1_CR3_CAP_Pos) /*!< CTIMER1 CR3: CAP Mask */
-
-/* -------------------------------- u1_timer_EMR -------------------------------- */
-#define CTIMER1_EMR_EM0_Pos 0 /*!< CTIMER1 EMR: EM0 Position */
-#define CTIMER1_EMR_EM0_Msk (0x01UL << CTIMER1_EMR_EM0_Pos) /*!< CTIMER1 EMR: EM0 Mask */
-#define CTIMER1_EMR_EM1_Pos 1 /*!< CTIMER1 EMR: EM1 Position */
-#define CTIMER1_EMR_EM1_Msk (0x01UL << CTIMER1_EMR_EM1_Pos) /*!< CTIMER1 EMR: EM1 Mask */
-#define CTIMER1_EMR_EM2_Pos 2 /*!< CTIMER1 EMR: EM2 Position */
-#define CTIMER1_EMR_EM2_Msk (0x01UL << CTIMER1_EMR_EM2_Pos) /*!< CTIMER1 EMR: EM2 Mask */
-#define CTIMER1_EMR_EM3_Pos 3 /*!< CTIMER1 EMR: EM3 Position */
-#define CTIMER1_EMR_EM3_Msk (0x01UL << CTIMER1_EMR_EM3_Pos) /*!< CTIMER1 EMR: EM3 Mask */
-#define CTIMER1_EMR_EMC0_Pos 4 /*!< CTIMER1 EMR: EMC0 Position */
-#define CTIMER1_EMR_EMC0_Msk (0x03UL << CTIMER1_EMR_EMC0_Pos) /*!< CTIMER1 EMR: EMC0 Mask */
-#define CTIMER1_EMR_EMC1_Pos 6 /*!< CTIMER1 EMR: EMC1 Position */
-#define CTIMER1_EMR_EMC1_Msk (0x03UL << CTIMER1_EMR_EMC1_Pos) /*!< CTIMER1 EMR: EMC1 Mask */
-#define CTIMER1_EMR_EMC2_Pos 8 /*!< CTIMER1 EMR: EMC2 Position */
-#define CTIMER1_EMR_EMC2_Msk (0x03UL << CTIMER1_EMR_EMC2_Pos) /*!< CTIMER1 EMR: EMC2 Mask */
-#define CTIMER1_EMR_EMC3_Pos 10 /*!< CTIMER1 EMR: EMC3 Position */
-#define CTIMER1_EMR_EMC3_Msk (0x03UL << CTIMER1_EMR_EMC3_Pos) /*!< CTIMER1 EMR: EMC3 Mask */
-
-/* -------------------------------- u1_timer_CTCR ------------------------------- */
-#define CTIMER1_CTCR_CTMODE_Pos 0 /*!< CTIMER1 CTCR: CTMODE Position */
-#define CTIMER1_CTCR_CTMODE_Msk (0x03UL << CTIMER1_CTCR_CTMODE_Pos) /*!< CTIMER1 CTCR: CTMODE Mask */
-#define CTIMER1_CTCR_CINSEL_Pos 2 /*!< CTIMER1 CTCR: CINSEL Position */
-#define CTIMER1_CTCR_CINSEL_Msk (0x03UL << CTIMER1_CTCR_CINSEL_Pos) /*!< CTIMER1 CTCR: CINSEL Mask */
-#define CTIMER1_CTCR_ENCC_Pos 4 /*!< CTIMER1 CTCR: ENCC Position */
-#define CTIMER1_CTCR_ENCC_Msk (0x01UL << CTIMER1_CTCR_ENCC_Pos) /*!< CTIMER1 CTCR: ENCC Mask */
-#define CTIMER1_CTCR_SELCC_Pos 5 /*!< CTIMER1 CTCR: SELCC Position */
-#define CTIMER1_CTCR_SELCC_Msk (0x07UL << CTIMER1_CTCR_SELCC_Pos) /*!< CTIMER1 CTCR: SELCC Mask */
-
-/* -------------------------------- u1_timer_PWMC ------------------------------- */
-#define CTIMER1_PWMC_PWMEN0_Pos 0 /*!< CTIMER1 PWMC: PWMEN0 Position */
-#define CTIMER1_PWMC_PWMEN0_Msk (0x01UL << CTIMER1_PWMC_PWMEN0_Pos) /*!< CTIMER1 PWMC: PWMEN0 Mask */
-#define CTIMER1_PWMC_PWMEN1_Pos 1 /*!< CTIMER1 PWMC: PWMEN1 Position */
-#define CTIMER1_PWMC_PWMEN1_Msk (0x01UL << CTIMER1_PWMC_PWMEN1_Pos) /*!< CTIMER1 PWMC: PWMEN1 Mask */
-#define CTIMER1_PWMC_PWMEN2_Pos 2 /*!< CTIMER1 PWMC: PWMEN2 Position */
-#define CTIMER1_PWMC_PWMEN2_Msk (0x01UL << CTIMER1_PWMC_PWMEN2_Pos) /*!< CTIMER1 PWMC: PWMEN2 Mask */
-#define CTIMER1_PWMC_PWMEN3_Pos 3 /*!< CTIMER1 PWMC: PWMEN3 Position */
-#define CTIMER1_PWMC_PWMEN3_Msk (0x01UL << CTIMER1_PWMC_PWMEN3_Pos) /*!< CTIMER1 PWMC: PWMEN3 Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u_gpio' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* ---------------------------------- u_gpio_B ---------------------------------- */
-#define GPIO_B_B_Pos 0 /*!< GPIO B: B Position */
-#define GPIO_B_B_Msk (0x000000ffUL << GPIO_B_B_Pos) /*!< GPIO B: B Mask */
-
-/* ---------------------------------- u_gpio_W ---------------------------------- */
-#define GPIO_W_W_Pos 0 /*!< GPIO W: W Position */
-#define GPIO_W_W_Msk (0xffffffffUL << GPIO_W_W_Pos) /*!< GPIO W: W Mask */
-
-/* --------------------------------- u_gpio_DIR --------------------------------- */
-#define GPIO_DIR_DIRP_PIO0_Pos 0 /*!< GPIO DIR: DIRP_PIO0 Position */
-#define GPIO_DIR_DIRP_PIO0_Msk (0x01UL << GPIO_DIR_DIRP_PIO0_Pos) /*!< GPIO DIR: DIRP_PIO0 Mask */
-#define GPIO_DIR_DIRP_PIO1_Pos 1 /*!< GPIO DIR: DIRP_PIO1 Position */
-#define GPIO_DIR_DIRP_PIO1_Msk (0x01UL << GPIO_DIR_DIRP_PIO1_Pos) /*!< GPIO DIR: DIRP_PIO1 Mask */
-#define GPIO_DIR_DIRP_PIO2_Pos 2 /*!< GPIO DIR: DIRP_PIO2 Position */
-#define GPIO_DIR_DIRP_PIO2_Msk (0x01UL << GPIO_DIR_DIRP_PIO2_Pos) /*!< GPIO DIR: DIRP_PIO2 Mask */
-#define GPIO_DIR_DIRP_PIO3_Pos 3 /*!< GPIO DIR: DIRP_PIO3 Position */
-#define GPIO_DIR_DIRP_PIO3_Msk (0x01UL << GPIO_DIR_DIRP_PIO3_Pos) /*!< GPIO DIR: DIRP_PIO3 Mask */
-#define GPIO_DIR_DIRP_PIO4_Pos 4 /*!< GPIO DIR: DIRP_PIO4 Position */
-#define GPIO_DIR_DIRP_PIO4_Msk (0x01UL << GPIO_DIR_DIRP_PIO4_Pos) /*!< GPIO DIR: DIRP_PIO4 Mask */
-#define GPIO_DIR_DIRP_PIO5_Pos 5 /*!< GPIO DIR: DIRP_PIO5 Position */
-#define GPIO_DIR_DIRP_PIO5_Msk (0x01UL << GPIO_DIR_DIRP_PIO5_Pos) /*!< GPIO DIR: DIRP_PIO5 Mask */
-#define GPIO_DIR_DIRP_PIO6_Pos 6 /*!< GPIO DIR: DIRP_PIO6 Position */
-#define GPIO_DIR_DIRP_PIO6_Msk (0x01UL << GPIO_DIR_DIRP_PIO6_Pos) /*!< GPIO DIR: DIRP_PIO6 Mask */
-#define GPIO_DIR_DIRP_PIO7_Pos 7 /*!< GPIO DIR: DIRP_PIO7 Position */
-#define GPIO_DIR_DIRP_PIO7_Msk (0x01UL << GPIO_DIR_DIRP_PIO7_Pos) /*!< GPIO DIR: DIRP_PIO7 Mask */
-#define GPIO_DIR_DIRP_PIO8_Pos 8 /*!< GPIO DIR: DIRP_PIO8 Position */
-#define GPIO_DIR_DIRP_PIO8_Msk (0x01UL << GPIO_DIR_DIRP_PIO8_Pos) /*!< GPIO DIR: DIRP_PIO8 Mask */
-#define GPIO_DIR_DIRP_PIO9_Pos 9 /*!< GPIO DIR: DIRP_PIO9 Position */
-#define GPIO_DIR_DIRP_PIO9_Msk (0x01UL << GPIO_DIR_DIRP_PIO9_Pos) /*!< GPIO DIR: DIRP_PIO9 Mask */
-#define GPIO_DIR_DIRP_PIO10_Pos 10 /*!< GPIO DIR: DIRP_PIO10 Position */
-#define GPIO_DIR_DIRP_PIO10_Msk (0x01UL << GPIO_DIR_DIRP_PIO10_Pos) /*!< GPIO DIR: DIRP_PIO10 Mask */
-#define GPIO_DIR_DIRP_PIO11_Pos 11 /*!< GPIO DIR: DIRP_PIO11 Position */
-#define GPIO_DIR_DIRP_PIO11_Msk (0x01UL << GPIO_DIR_DIRP_PIO11_Pos) /*!< GPIO DIR: DIRP_PIO11 Mask */
-#define GPIO_DIR_DIRP_PIO12_Pos 12 /*!< GPIO DIR: DIRP_PIO12 Position */
-#define GPIO_DIR_DIRP_PIO12_Msk (0x01UL << GPIO_DIR_DIRP_PIO12_Pos) /*!< GPIO DIR: DIRP_PIO12 Mask */
-#define GPIO_DIR_DIRP_PIO13_Pos 13 /*!< GPIO DIR: DIRP_PIO13 Position */
-#define GPIO_DIR_DIRP_PIO13_Msk (0x01UL << GPIO_DIR_DIRP_PIO13_Pos) /*!< GPIO DIR: DIRP_PIO13 Mask */
-#define GPIO_DIR_DIRP_PIO14_Pos 14 /*!< GPIO DIR: DIRP_PIO14 Position */
-#define GPIO_DIR_DIRP_PIO14_Msk (0x01UL << GPIO_DIR_DIRP_PIO14_Pos) /*!< GPIO DIR: DIRP_PIO14 Mask */
-#define GPIO_DIR_DIRP_PIO15_Pos 15 /*!< GPIO DIR: DIRP_PIO15 Position */
-#define GPIO_DIR_DIRP_PIO15_Msk (0x01UL << GPIO_DIR_DIRP_PIO15_Pos) /*!< GPIO DIR: DIRP_PIO15 Mask */
-#define GPIO_DIR_DIRP_PIO16_Pos 16 /*!< GPIO DIR: DIRP_PIO16 Position */
-#define GPIO_DIR_DIRP_PIO16_Msk (0x01UL << GPIO_DIR_DIRP_PIO16_Pos) /*!< GPIO DIR: DIRP_PIO16 Mask */
-#define GPIO_DIR_DIRP_PIO17_Pos 17 /*!< GPIO DIR: DIRP_PIO17 Position */
-#define GPIO_DIR_DIRP_PIO17_Msk (0x01UL << GPIO_DIR_DIRP_PIO17_Pos) /*!< GPIO DIR: DIRP_PIO17 Mask */
-#define GPIO_DIR_DIRP_PIO18_Pos 18 /*!< GPIO DIR: DIRP_PIO18 Position */
-#define GPIO_DIR_DIRP_PIO18_Msk (0x01UL << GPIO_DIR_DIRP_PIO18_Pos) /*!< GPIO DIR: DIRP_PIO18 Mask */
-#define GPIO_DIR_DIRP_PIO19_Pos 19 /*!< GPIO DIR: DIRP_PIO19 Position */
-#define GPIO_DIR_DIRP_PIO19_Msk (0x01UL << GPIO_DIR_DIRP_PIO19_Pos) /*!< GPIO DIR: DIRP_PIO19 Mask */
-#define GPIO_DIR_DIRP_PIO20_Pos 20 /*!< GPIO DIR: DIRP_PIO20 Position */
-#define GPIO_DIR_DIRP_PIO20_Msk (0x01UL << GPIO_DIR_DIRP_PIO20_Pos) /*!< GPIO DIR: DIRP_PIO20 Mask */
-#define GPIO_DIR_DIRP_PIO21_Pos 21 /*!< GPIO DIR: DIRP_PIO21 Position */
-#define GPIO_DIR_DIRP_PIO21_Msk (0x01UL << GPIO_DIR_DIRP_PIO21_Pos) /*!< GPIO DIR: DIRP_PIO21 Mask */
-
-/* --------------------------------- u_gpio_MASK -------------------------------- */
-#define GPIO_MASK_MASKP_PIO0_Pos 0 /*!< GPIO MASK: MASKP_PIO0 Position */
-#define GPIO_MASK_MASKP_PIO0_Msk (0x01UL << GPIO_MASK_MASKP_PIO0_Pos) /*!< GPIO MASK: MASKP_PIO0 Mask */
-#define GPIO_MASK_MASKP_PIO1_Pos 1 /*!< GPIO MASK: MASKP_PIO1 Position */
-#define GPIO_MASK_MASKP_PIO1_Msk (0x01UL << GPIO_MASK_MASKP_PIO1_Pos) /*!< GPIO MASK: MASKP_PIO1 Mask */
-#define GPIO_MASK_MASKP_PIO2_Pos 2 /*!< GPIO MASK: MASKP_PIO2 Position */
-#define GPIO_MASK_MASKP_PIO2_Msk (0x01UL << GPIO_MASK_MASKP_PIO2_Pos) /*!< GPIO MASK: MASKP_PIO2 Mask */
-#define GPIO_MASK_MASKP_PIO3_Pos 3 /*!< GPIO MASK: MASKP_PIO3 Position */
-#define GPIO_MASK_MASKP_PIO3_Msk (0x01UL << GPIO_MASK_MASKP_PIO3_Pos) /*!< GPIO MASK: MASKP_PIO3 Mask */
-#define GPIO_MASK_MASKP_PIO4_Pos 4 /*!< GPIO MASK: MASKP_PIO4 Position */
-#define GPIO_MASK_MASKP_PIO4_Msk (0x01UL << GPIO_MASK_MASKP_PIO4_Pos) /*!< GPIO MASK: MASKP_PIO4 Mask */
-#define GPIO_MASK_MASKP_PIO5_Pos 5 /*!< GPIO MASK: MASKP_PIO5 Position */
-#define GPIO_MASK_MASKP_PIO5_Msk (0x01UL << GPIO_MASK_MASKP_PIO5_Pos) /*!< GPIO MASK: MASKP_PIO5 Mask */
-#define GPIO_MASK_MASKP_PIO6_Pos 6 /*!< GPIO MASK: MASKP_PIO6 Position */
-#define GPIO_MASK_MASKP_PIO6_Msk (0x01UL << GPIO_MASK_MASKP_PIO6_Pos) /*!< GPIO MASK: MASKP_PIO6 Mask */
-#define GPIO_MASK_MASKP_PIO7_Pos 7 /*!< GPIO MASK: MASKP_PIO7 Position */
-#define GPIO_MASK_MASKP_PIO7_Msk (0x01UL << GPIO_MASK_MASKP_PIO7_Pos) /*!< GPIO MASK: MASKP_PIO7 Mask */
-#define GPIO_MASK_MASKP_PIO8_Pos 8 /*!< GPIO MASK: MASKP_PIO8 Position */
-#define GPIO_MASK_MASKP_PIO8_Msk (0x01UL << GPIO_MASK_MASKP_PIO8_Pos) /*!< GPIO MASK: MASKP_PIO8 Mask */
-#define GPIO_MASK_MASKP_PIO9_Pos 9 /*!< GPIO MASK: MASKP_PIO9 Position */
-#define GPIO_MASK_MASKP_PIO9_Msk (0x01UL << GPIO_MASK_MASKP_PIO9_Pos) /*!< GPIO MASK: MASKP_PIO9 Mask */
-#define GPIO_MASK_MASKP_PIO10_Pos 10 /*!< GPIO MASK: MASKP_PIO10 Position */
-#define GPIO_MASK_MASKP_PIO10_Msk (0x01UL << GPIO_MASK_MASKP_PIO10_Pos) /*!< GPIO MASK: MASKP_PIO10 Mask */
-#define GPIO_MASK_MASKP_PIO11_Pos 11 /*!< GPIO MASK: MASKP_PIO11 Position */
-#define GPIO_MASK_MASKP_PIO11_Msk (0x01UL << GPIO_MASK_MASKP_PIO11_Pos) /*!< GPIO MASK: MASKP_PIO11 Mask */
-#define GPIO_MASK_MASKP_PIO12_Pos 12 /*!< GPIO MASK: MASKP_PIO12 Position */
-#define GPIO_MASK_MASKP_PIO12_Msk (0x01UL << GPIO_MASK_MASKP_PIO12_Pos) /*!< GPIO MASK: MASKP_PIO12 Mask */
-#define GPIO_MASK_MASKP_PIO13_Pos 13 /*!< GPIO MASK: MASKP_PIO13 Position */
-#define GPIO_MASK_MASKP_PIO13_Msk (0x01UL << GPIO_MASK_MASKP_PIO13_Pos) /*!< GPIO MASK: MASKP_PIO13 Mask */
-#define GPIO_MASK_MASKP_PIO14_Pos 14 /*!< GPIO MASK: MASKP_PIO14 Position */
-#define GPIO_MASK_MASKP_PIO14_Msk (0x01UL << GPIO_MASK_MASKP_PIO14_Pos) /*!< GPIO MASK: MASKP_PIO14 Mask */
-#define GPIO_MASK_MASKP_PIO15_Pos 15 /*!< GPIO MASK: MASKP_PIO15 Position */
-#define GPIO_MASK_MASKP_PIO15_Msk (0x01UL << GPIO_MASK_MASKP_PIO15_Pos) /*!< GPIO MASK: MASKP_PIO15 Mask */
-#define GPIO_MASK_MASKP_PIO16_Pos 16 /*!< GPIO MASK: MASKP_PIO16 Position */
-#define GPIO_MASK_MASKP_PIO16_Msk (0x01UL << GPIO_MASK_MASKP_PIO16_Pos) /*!< GPIO MASK: MASKP_PIO16 Mask */
-#define GPIO_MASK_MASKP_PIO17_Pos 17 /*!< GPIO MASK: MASKP_PIO17 Position */
-#define GPIO_MASK_MASKP_PIO17_Msk (0x01UL << GPIO_MASK_MASKP_PIO17_Pos) /*!< GPIO MASK: MASKP_PIO17 Mask */
-#define GPIO_MASK_MASKP_PIO18_Pos 18 /*!< GPIO MASK: MASKP_PIO18 Position */
-#define GPIO_MASK_MASKP_PIO18_Msk (0x01UL << GPIO_MASK_MASKP_PIO18_Pos) /*!< GPIO MASK: MASKP_PIO18 Mask */
-#define GPIO_MASK_MASKP_PIO19_Pos 19 /*!< GPIO MASK: MASKP_PIO19 Position */
-#define GPIO_MASK_MASKP_PIO19_Msk (0x01UL << GPIO_MASK_MASKP_PIO19_Pos) /*!< GPIO MASK: MASKP_PIO19 Mask */
-#define GPIO_MASK_MASKP_PIO20_Pos 20 /*!< GPIO MASK: MASKP_PIO20 Position */
-#define GPIO_MASK_MASKP_PIO20_Msk (0x01UL << GPIO_MASK_MASKP_PIO20_Pos) /*!< GPIO MASK: MASKP_PIO20 Mask */
-#define GPIO_MASK_MASKP_PIO21_Pos 21 /*!< GPIO MASK: MASKP_PIO21 Position */
-#define GPIO_MASK_MASKP_PIO21_Msk (0x01UL << GPIO_MASK_MASKP_PIO21_Pos) /*!< GPIO MASK: MASKP_PIO21 Mask */
-
-/* --------------------------------- u_gpio_PIN --------------------------------- */
-#define GPIO_PIN_PORT_PIO0_Pos 0 /*!< GPIO PIN: PORT_PIO0 Position */
-#define GPIO_PIN_PORT_PIO0_Msk (0x01UL << GPIO_PIN_PORT_PIO0_Pos) /*!< GPIO PIN: PORT_PIO0 Mask */
-#define GPIO_PIN_PORT_PIO1_Pos 1 /*!< GPIO PIN: PORT_PIO1 Position */
-#define GPIO_PIN_PORT_PIO1_Msk (0x01UL << GPIO_PIN_PORT_PIO1_Pos) /*!< GPIO PIN: PORT_PIO1 Mask */
-#define GPIO_PIN_PORT_PIO2_Pos 2 /*!< GPIO PIN: PORT_PIO2 Position */
-#define GPIO_PIN_PORT_PIO2_Msk (0x01UL << GPIO_PIN_PORT_PIO2_Pos) /*!< GPIO PIN: PORT_PIO2 Mask */
-#define GPIO_PIN_PORT_PIO3_Pos 3 /*!< GPIO PIN: PORT_PIO3 Position */
-#define GPIO_PIN_PORT_PIO3_Msk (0x01UL << GPIO_PIN_PORT_PIO3_Pos) /*!< GPIO PIN: PORT_PIO3 Mask */
-#define GPIO_PIN_PORT_PIO4_Pos 4 /*!< GPIO PIN: PORT_PIO4 Position */
-#define GPIO_PIN_PORT_PIO4_Msk (0x01UL << GPIO_PIN_PORT_PIO4_Pos) /*!< GPIO PIN: PORT_PIO4 Mask */
-#define GPIO_PIN_PORT_PIO5_Pos 5 /*!< GPIO PIN: PORT_PIO5 Position */
-#define GPIO_PIN_PORT_PIO5_Msk (0x01UL << GPIO_PIN_PORT_PIO5_Pos) /*!< GPIO PIN: PORT_PIO5 Mask */
-#define GPIO_PIN_PORT_PIO6_Pos 6 /*!< GPIO PIN: PORT_PIO6 Position */
-#define GPIO_PIN_PORT_PIO6_Msk (0x01UL << GPIO_PIN_PORT_PIO6_Pos) /*!< GPIO PIN: PORT_PIO6 Mask */
-#define GPIO_PIN_PORT_PIO7_Pos 7 /*!< GPIO PIN: PORT_PIO7 Position */
-#define GPIO_PIN_PORT_PIO7_Msk (0x01UL << GPIO_PIN_PORT_PIO7_Pos) /*!< GPIO PIN: PORT_PIO7 Mask */
-#define GPIO_PIN_PORT_PIO8_Pos 8 /*!< GPIO PIN: PORT_PIO8 Position */
-#define GPIO_PIN_PORT_PIO8_Msk (0x01UL << GPIO_PIN_PORT_PIO8_Pos) /*!< GPIO PIN: PORT_PIO8 Mask */
-#define GPIO_PIN_PORT_PIO9_Pos 9 /*!< GPIO PIN: PORT_PIO9 Position */
-#define GPIO_PIN_PORT_PIO9_Msk (0x01UL << GPIO_PIN_PORT_PIO9_Pos) /*!< GPIO PIN: PORT_PIO9 Mask */
-#define GPIO_PIN_PORT_PIO10_Pos 10 /*!< GPIO PIN: PORT_PIO10 Position */
-#define GPIO_PIN_PORT_PIO10_Msk (0x01UL << GPIO_PIN_PORT_PIO10_Pos) /*!< GPIO PIN: PORT_PIO10 Mask */
-#define GPIO_PIN_PORT_PIO11_Pos 11 /*!< GPIO PIN: PORT_PIO11 Position */
-#define GPIO_PIN_PORT_PIO11_Msk (0x01UL << GPIO_PIN_PORT_PIO11_Pos) /*!< GPIO PIN: PORT_PIO11 Mask */
-#define GPIO_PIN_PORT_PIO12_Pos 12 /*!< GPIO PIN: PORT_PIO12 Position */
-#define GPIO_PIN_PORT_PIO12_Msk (0x01UL << GPIO_PIN_PORT_PIO12_Pos) /*!< GPIO PIN: PORT_PIO12 Mask */
-#define GPIO_PIN_PORT_PIO13_Pos 13 /*!< GPIO PIN: PORT_PIO13 Position */
-#define GPIO_PIN_PORT_PIO13_Msk (0x01UL << GPIO_PIN_PORT_PIO13_Pos) /*!< GPIO PIN: PORT_PIO13 Mask */
-#define GPIO_PIN_PORT_PIO14_Pos 14 /*!< GPIO PIN: PORT_PIO14 Position */
-#define GPIO_PIN_PORT_PIO14_Msk (0x01UL << GPIO_PIN_PORT_PIO14_Pos) /*!< GPIO PIN: PORT_PIO14 Mask */
-#define GPIO_PIN_PORT_PIO15_Pos 15 /*!< GPIO PIN: PORT_PIO15 Position */
-#define GPIO_PIN_PORT_PIO15_Msk (0x01UL << GPIO_PIN_PORT_PIO15_Pos) /*!< GPIO PIN: PORT_PIO15 Mask */
-#define GPIO_PIN_PORT_PIO16_Pos 16 /*!< GPIO PIN: PORT_PIO16 Position */
-#define GPIO_PIN_PORT_PIO16_Msk (0x01UL << GPIO_PIN_PORT_PIO16_Pos) /*!< GPIO PIN: PORT_PIO16 Mask */
-#define GPIO_PIN_PORT_PIO17_Pos 17 /*!< GPIO PIN: PORT_PIO17 Position */
-#define GPIO_PIN_PORT_PIO17_Msk (0x01UL << GPIO_PIN_PORT_PIO17_Pos) /*!< GPIO PIN: PORT_PIO17 Mask */
-#define GPIO_PIN_PORT_PIO18_Pos 18 /*!< GPIO PIN: PORT_PIO18 Position */
-#define GPIO_PIN_PORT_PIO18_Msk (0x01UL << GPIO_PIN_PORT_PIO18_Pos) /*!< GPIO PIN: PORT_PIO18 Mask */
-#define GPIO_PIN_PORT_PIO19_Pos 19 /*!< GPIO PIN: PORT_PIO19 Position */
-#define GPIO_PIN_PORT_PIO19_Msk (0x01UL << GPIO_PIN_PORT_PIO19_Pos) /*!< GPIO PIN: PORT_PIO19 Mask */
-#define GPIO_PIN_PORT_PIO20_Pos 20 /*!< GPIO PIN: PORT_PIO20 Position */
-#define GPIO_PIN_PORT_PIO20_Msk (0x01UL << GPIO_PIN_PORT_PIO20_Pos) /*!< GPIO PIN: PORT_PIO20 Mask */
-#define GPIO_PIN_PORT_PIO21_Pos 21 /*!< GPIO PIN: PORT_PIO21 Position */
-#define GPIO_PIN_PORT_PIO21_Msk (0x01UL << GPIO_PIN_PORT_PIO21_Pos) /*!< GPIO PIN: PORT_PIO21 Mask */
-
-/* --------------------------------- u_gpio_MPIN -------------------------------- */
-#define GPIO_MPIN_MPORT_PIO0_Pos 0 /*!< GPIO MPIN: MPORT_PIO0 Position */
-#define GPIO_MPIN_MPORT_PIO0_Msk (0x01UL << GPIO_MPIN_MPORT_PIO0_Pos) /*!< GPIO MPIN: MPORT_PIO0 Mask */
-#define GPIO_MPIN_MPORT_PIO1_Pos 1 /*!< GPIO MPIN: MPORT_PIO1 Position */
-#define GPIO_MPIN_MPORT_PIO1_Msk (0x01UL << GPIO_MPIN_MPORT_PIO1_Pos) /*!< GPIO MPIN: MPORT_PIO1 Mask */
-#define GPIO_MPIN_MPORT_PIO2_Pos 2 /*!< GPIO MPIN: MPORT_PIO2 Position */
-#define GPIO_MPIN_MPORT_PIO2_Msk (0x01UL << GPIO_MPIN_MPORT_PIO2_Pos) /*!< GPIO MPIN: MPORT_PIO2 Mask */
-#define GPIO_MPIN_MPORT_PIO3_Pos 3 /*!< GPIO MPIN: MPORT_PIO3 Position */
-#define GPIO_MPIN_MPORT_PIO3_Msk (0x01UL << GPIO_MPIN_MPORT_PIO3_Pos) /*!< GPIO MPIN: MPORT_PIO3 Mask */
-#define GPIO_MPIN_MPORT_PIO4_Pos 4 /*!< GPIO MPIN: MPORT_PIO4 Position */
-#define GPIO_MPIN_MPORT_PIO4_Msk (0x01UL << GPIO_MPIN_MPORT_PIO4_Pos) /*!< GPIO MPIN: MPORT_PIO4 Mask */
-#define GPIO_MPIN_MPORT_PIO5_Pos 5 /*!< GPIO MPIN: MPORT_PIO5 Position */
-#define GPIO_MPIN_MPORT_PIO5_Msk (0x01UL << GPIO_MPIN_MPORT_PIO5_Pos) /*!< GPIO MPIN: MPORT_PIO5 Mask */
-#define GPIO_MPIN_MPORT_PIO6_Pos 6 /*!< GPIO MPIN: MPORT_PIO6 Position */
-#define GPIO_MPIN_MPORT_PIO6_Msk (0x01UL << GPIO_MPIN_MPORT_PIO6_Pos) /*!< GPIO MPIN: MPORT_PIO6 Mask */
-#define GPIO_MPIN_MPORT_PIO7_Pos 7 /*!< GPIO MPIN: MPORT_PIO7 Position */
-#define GPIO_MPIN_MPORT_PIO7_Msk (0x01UL << GPIO_MPIN_MPORT_PIO7_Pos) /*!< GPIO MPIN: MPORT_PIO7 Mask */
-#define GPIO_MPIN_MPORT_PIO8_Pos 8 /*!< GPIO MPIN: MPORT_PIO8 Position */
-#define GPIO_MPIN_MPORT_PIO8_Msk (0x01UL << GPIO_MPIN_MPORT_PIO8_Pos) /*!< GPIO MPIN: MPORT_PIO8 Mask */
-#define GPIO_MPIN_MPORT_PIO9_Pos 9 /*!< GPIO MPIN: MPORT_PIO9 Position */
-#define GPIO_MPIN_MPORT_PIO9_Msk (0x01UL << GPIO_MPIN_MPORT_PIO9_Pos) /*!< GPIO MPIN: MPORT_PIO9 Mask */
-#define GPIO_MPIN_MPORT_PIO10_Pos 10 /*!< GPIO MPIN: MPORT_PIO10 Position */
-#define GPIO_MPIN_MPORT_PIO10_Msk (0x01UL << GPIO_MPIN_MPORT_PIO10_Pos) /*!< GPIO MPIN: MPORT_PIO10 Mask */
-#define GPIO_MPIN_MPORT_PIO11_Pos 11 /*!< GPIO MPIN: MPORT_PIO11 Position */
-#define GPIO_MPIN_MPORT_PIO11_Msk (0x01UL << GPIO_MPIN_MPORT_PIO11_Pos) /*!< GPIO MPIN: MPORT_PIO11 Mask */
-#define GPIO_MPIN_MPORT_PIO12_Pos 12 /*!< GPIO MPIN: MPORT_PIO12 Position */
-#define GPIO_MPIN_MPORT_PIO12_Msk (0x01UL << GPIO_MPIN_MPORT_PIO12_Pos) /*!< GPIO MPIN: MPORT_PIO12 Mask */
-#define GPIO_MPIN_MPORT_PIO13_Pos 13 /*!< GPIO MPIN: MPORT_PIO13 Position */
-#define GPIO_MPIN_MPORT_PIO13_Msk (0x01UL << GPIO_MPIN_MPORT_PIO13_Pos) /*!< GPIO MPIN: MPORT_PIO13 Mask */
-#define GPIO_MPIN_MPORT_PIO14_Pos 14 /*!< GPIO MPIN: MPORT_PIO14 Position */
-#define GPIO_MPIN_MPORT_PIO14_Msk (0x01UL << GPIO_MPIN_MPORT_PIO14_Pos) /*!< GPIO MPIN: MPORT_PIO14 Mask */
-#define GPIO_MPIN_MPORT_PIO15_Pos 15 /*!< GPIO MPIN: MPORT_PIO15 Position */
-#define GPIO_MPIN_MPORT_PIO15_Msk (0x01UL << GPIO_MPIN_MPORT_PIO15_Pos) /*!< GPIO MPIN: MPORT_PIO15 Mask */
-#define GPIO_MPIN_MPORT_PIO16_Pos 16 /*!< GPIO MPIN: MPORT_PIO16 Position */
-#define GPIO_MPIN_MPORT_PIO16_Msk (0x01UL << GPIO_MPIN_MPORT_PIO16_Pos) /*!< GPIO MPIN: MPORT_PIO16 Mask */
-#define GPIO_MPIN_MPORT_PIO17_Pos 17 /*!< GPIO MPIN: MPORT_PIO17 Position */
-#define GPIO_MPIN_MPORT_PIO17_Msk (0x01UL << GPIO_MPIN_MPORT_PIO17_Pos) /*!< GPIO MPIN: MPORT_PIO17 Mask */
-#define GPIO_MPIN_MPORT_PIO18_Pos 18 /*!< GPIO MPIN: MPORT_PIO18 Position */
-#define GPIO_MPIN_MPORT_PIO18_Msk (0x01UL << GPIO_MPIN_MPORT_PIO18_Pos) /*!< GPIO MPIN: MPORT_PIO18 Mask */
-#define GPIO_MPIN_MPORT_PIO19_Pos 19 /*!< GPIO MPIN: MPORT_PIO19 Position */
-#define GPIO_MPIN_MPORT_PIO19_Msk (0x01UL << GPIO_MPIN_MPORT_PIO19_Pos) /*!< GPIO MPIN: MPORT_PIO19 Mask */
-#define GPIO_MPIN_MPORT_PIO20_Pos 20 /*!< GPIO MPIN: MPORT_PIO20 Position */
-#define GPIO_MPIN_MPORT_PIO20_Msk (0x01UL << GPIO_MPIN_MPORT_PIO20_Pos) /*!< GPIO MPIN: MPORT_PIO20 Mask */
-#define GPIO_MPIN_MPORT_PIO21_Pos 21 /*!< GPIO MPIN: MPORT_PIO21 Position */
-#define GPIO_MPIN_MPORT_PIO21_Msk (0x01UL << GPIO_MPIN_MPORT_PIO21_Pos) /*!< GPIO MPIN: MPORT_PIO21 Mask */
-
-/* --------------------------------- u_gpio_SET --------------------------------- */
-#define GPIO_SET_SETP_PIO0_Pos 0 /*!< GPIO SET: SETP_PIO0 Position */
-#define GPIO_SET_SETP_PIO0_Msk (0x01UL << GPIO_SET_SETP_PIO0_Pos) /*!< GPIO SET: SETP_PIO0 Mask */
-#define GPIO_SET_SETP_PIO1_Pos 1 /*!< GPIO SET: SETP_PIO1 Position */
-#define GPIO_SET_SETP_PIO1_Msk (0x01UL << GPIO_SET_SETP_PIO1_Pos) /*!< GPIO SET: SETP_PIO1 Mask */
-#define GPIO_SET_SETP_PIO2_Pos 2 /*!< GPIO SET: SETP_PIO2 Position */
-#define GPIO_SET_SETP_PIO2_Msk (0x01UL << GPIO_SET_SETP_PIO2_Pos) /*!< GPIO SET: SETP_PIO2 Mask */
-#define GPIO_SET_SETP_PIO3_Pos 3 /*!< GPIO SET: SETP_PIO3 Position */
-#define GPIO_SET_SETP_PIO3_Msk (0x01UL << GPIO_SET_SETP_PIO3_Pos) /*!< GPIO SET: SETP_PIO3 Mask */
-#define GPIO_SET_SETP_PIO4_Pos 4 /*!< GPIO SET: SETP_PIO4 Position */
-#define GPIO_SET_SETP_PIO4_Msk (0x01UL << GPIO_SET_SETP_PIO4_Pos) /*!< GPIO SET: SETP_PIO4 Mask */
-#define GPIO_SET_SETP_PIO5_Pos 5 /*!< GPIO SET: SETP_PIO5 Position */
-#define GPIO_SET_SETP_PIO5_Msk (0x01UL << GPIO_SET_SETP_PIO5_Pos) /*!< GPIO SET: SETP_PIO5 Mask */
-#define GPIO_SET_SETP_PIO6_Pos 6 /*!< GPIO SET: SETP_PIO6 Position */
-#define GPIO_SET_SETP_PIO6_Msk (0x01UL << GPIO_SET_SETP_PIO6_Pos) /*!< GPIO SET: SETP_PIO6 Mask */
-#define GPIO_SET_SETP_PIO7_Pos 7 /*!< GPIO SET: SETP_PIO7 Position */
-#define GPIO_SET_SETP_PIO7_Msk (0x01UL << GPIO_SET_SETP_PIO7_Pos) /*!< GPIO SET: SETP_PIO7 Mask */
-#define GPIO_SET_SETP_PIO8_Pos 8 /*!< GPIO SET: SETP_PIO8 Position */
-#define GPIO_SET_SETP_PIO8_Msk (0x01UL << GPIO_SET_SETP_PIO8_Pos) /*!< GPIO SET: SETP_PIO8 Mask */
-#define GPIO_SET_SETP_PIO9_Pos 9 /*!< GPIO SET: SETP_PIO9 Position */
-#define GPIO_SET_SETP_PIO9_Msk (0x01UL << GPIO_SET_SETP_PIO9_Pos) /*!< GPIO SET: SETP_PIO9 Mask */
-#define GPIO_SET_SETP_PIO10_Pos 10 /*!< GPIO SET: SETP_PIO10 Position */
-#define GPIO_SET_SETP_PIO10_Msk (0x01UL << GPIO_SET_SETP_PIO10_Pos) /*!< GPIO SET: SETP_PIO10 Mask */
-#define GPIO_SET_SETP_PIO11_Pos 11 /*!< GPIO SET: SETP_PIO11 Position */
-#define GPIO_SET_SETP_PIO11_Msk (0x01UL << GPIO_SET_SETP_PIO11_Pos) /*!< GPIO SET: SETP_PIO11 Mask */
-#define GPIO_SET_SETP_PIO12_Pos 12 /*!< GPIO SET: SETP_PIO12 Position */
-#define GPIO_SET_SETP_PIO12_Msk (0x01UL << GPIO_SET_SETP_PIO12_Pos) /*!< GPIO SET: SETP_PIO12 Mask */
-#define GPIO_SET_SETP_PIO13_Pos 13 /*!< GPIO SET: SETP_PIO13 Position */
-#define GPIO_SET_SETP_PIO13_Msk (0x01UL << GPIO_SET_SETP_PIO13_Pos) /*!< GPIO SET: SETP_PIO13 Mask */
-#define GPIO_SET_SETP_PIO14_Pos 14 /*!< GPIO SET: SETP_PIO14 Position */
-#define GPIO_SET_SETP_PIO14_Msk (0x01UL << GPIO_SET_SETP_PIO14_Pos) /*!< GPIO SET: SETP_PIO14 Mask */
-#define GPIO_SET_SETP_PIO15_Pos 15 /*!< GPIO SET: SETP_PIO15 Position */
-#define GPIO_SET_SETP_PIO15_Msk (0x01UL << GPIO_SET_SETP_PIO15_Pos) /*!< GPIO SET: SETP_PIO15 Mask */
-#define GPIO_SET_SETP_PIO16_Pos 16 /*!< GPIO SET: SETP_PIO16 Position */
-#define GPIO_SET_SETP_PIO16_Msk (0x01UL << GPIO_SET_SETP_PIO16_Pos) /*!< GPIO SET: SETP_PIO16 Mask */
-#define GPIO_SET_SETP_PIO17_Pos 17 /*!< GPIO SET: SETP_PIO17 Position */
-#define GPIO_SET_SETP_PIO17_Msk (0x01UL << GPIO_SET_SETP_PIO17_Pos) /*!< GPIO SET: SETP_PIO17 Mask */
-#define GPIO_SET_SETP_PIO18_Pos 18 /*!< GPIO SET: SETP_PIO18 Position */
-#define GPIO_SET_SETP_PIO18_Msk (0x01UL << GPIO_SET_SETP_PIO18_Pos) /*!< GPIO SET: SETP_PIO18 Mask */
-#define GPIO_SET_SETP_PIO19_Pos 19 /*!< GPIO SET: SETP_PIO19 Position */
-#define GPIO_SET_SETP_PIO19_Msk (0x01UL << GPIO_SET_SETP_PIO19_Pos) /*!< GPIO SET: SETP_PIO19 Mask */
-#define GPIO_SET_SETP_PIO20_Pos 20 /*!< GPIO SET: SETP_PIO20 Position */
-#define GPIO_SET_SETP_PIO20_Msk (0x01UL << GPIO_SET_SETP_PIO20_Pos) /*!< GPIO SET: SETP_PIO20 Mask */
-#define GPIO_SET_SETP_PIO21_Pos 21 /*!< GPIO SET: SETP_PIO21 Position */
-#define GPIO_SET_SETP_PIO21_Msk (0x01UL << GPIO_SET_SETP_PIO21_Pos) /*!< GPIO SET: SETP_PIO21 Mask */
-
-/* --------------------------------- u_gpio_CLR --------------------------------- */
-#define GPIO_CLR_CLRP_PIO0_Pos 0 /*!< GPIO CLR: CLRP_PIO0 Position */
-#define GPIO_CLR_CLRP_PIO0_Msk (0x01UL << GPIO_CLR_CLRP_PIO0_Pos) /*!< GPIO CLR: CLRP_PIO0 Mask */
-#define GPIO_CLR_CLRP_PIO1_Pos 1 /*!< GPIO CLR: CLRP_PIO1 Position */
-#define GPIO_CLR_CLRP_PIO1_Msk (0x01UL << GPIO_CLR_CLRP_PIO1_Pos) /*!< GPIO CLR: CLRP_PIO1 Mask */
-#define GPIO_CLR_CLRP_PIO2_Pos 2 /*!< GPIO CLR: CLRP_PIO2 Position */
-#define GPIO_CLR_CLRP_PIO2_Msk (0x01UL << GPIO_CLR_CLRP_PIO2_Pos) /*!< GPIO CLR: CLRP_PIO2 Mask */
-#define GPIO_CLR_CLRP_PIO3_Pos 3 /*!< GPIO CLR: CLRP_PIO3 Position */
-#define GPIO_CLR_CLRP_PIO3_Msk (0x01UL << GPIO_CLR_CLRP_PIO3_Pos) /*!< GPIO CLR: CLRP_PIO3 Mask */
-#define GPIO_CLR_CLRP_PIO4_Pos 4 /*!< GPIO CLR: CLRP_PIO4 Position */
-#define GPIO_CLR_CLRP_PIO4_Msk (0x01UL << GPIO_CLR_CLRP_PIO4_Pos) /*!< GPIO CLR: CLRP_PIO4 Mask */
-#define GPIO_CLR_CLRP_PIO5_Pos 5 /*!< GPIO CLR: CLRP_PIO5 Position */
-#define GPIO_CLR_CLRP_PIO5_Msk (0x01UL << GPIO_CLR_CLRP_PIO5_Pos) /*!< GPIO CLR: CLRP_PIO5 Mask */
-#define GPIO_CLR_CLRP_PIO6_Pos 6 /*!< GPIO CLR: CLRP_PIO6 Position */
-#define GPIO_CLR_CLRP_PIO6_Msk (0x01UL << GPIO_CLR_CLRP_PIO6_Pos) /*!< GPIO CLR: CLRP_PIO6 Mask */
-#define GPIO_CLR_CLRP_PIO7_Pos 7 /*!< GPIO CLR: CLRP_PIO7 Position */
-#define GPIO_CLR_CLRP_PIO7_Msk (0x01UL << GPIO_CLR_CLRP_PIO7_Pos) /*!< GPIO CLR: CLRP_PIO7 Mask */
-#define GPIO_CLR_CLRP_PIO8_Pos 8 /*!< GPIO CLR: CLRP_PIO8 Position */
-#define GPIO_CLR_CLRP_PIO8_Msk (0x01UL << GPIO_CLR_CLRP_PIO8_Pos) /*!< GPIO CLR: CLRP_PIO8 Mask */
-#define GPIO_CLR_CLRP_PIO9_Pos 9 /*!< GPIO CLR: CLRP_PIO9 Position */
-#define GPIO_CLR_CLRP_PIO9_Msk (0x01UL << GPIO_CLR_CLRP_PIO9_Pos) /*!< GPIO CLR: CLRP_PIO9 Mask */
-#define GPIO_CLR_CLRP_PIO10_Pos 10 /*!< GPIO CLR: CLRP_PIO10 Position */
-#define GPIO_CLR_CLRP_PIO10_Msk (0x01UL << GPIO_CLR_CLRP_PIO10_Pos) /*!< GPIO CLR: CLRP_PIO10 Mask */
-#define GPIO_CLR_CLRP_PIO11_Pos 11 /*!< GPIO CLR: CLRP_PIO11 Position */
-#define GPIO_CLR_CLRP_PIO11_Msk (0x01UL << GPIO_CLR_CLRP_PIO11_Pos) /*!< GPIO CLR: CLRP_PIO11 Mask */
-#define GPIO_CLR_CLRP_PIO12_Pos 12 /*!< GPIO CLR: CLRP_PIO12 Position */
-#define GPIO_CLR_CLRP_PIO12_Msk (0x01UL << GPIO_CLR_CLRP_PIO12_Pos) /*!< GPIO CLR: CLRP_PIO12 Mask */
-#define GPIO_CLR_CLRP_PIO13_Pos 13 /*!< GPIO CLR: CLRP_PIO13 Position */
-#define GPIO_CLR_CLRP_PIO13_Msk (0x01UL << GPIO_CLR_CLRP_PIO13_Pos) /*!< GPIO CLR: CLRP_PIO13 Mask */
-#define GPIO_CLR_CLRP_PIO14_Pos 14 /*!< GPIO CLR: CLRP_PIO14 Position */
-#define GPIO_CLR_CLRP_PIO14_Msk (0x01UL << GPIO_CLR_CLRP_PIO14_Pos) /*!< GPIO CLR: CLRP_PIO14 Mask */
-#define GPIO_CLR_CLRP_PIO15_Pos 15 /*!< GPIO CLR: CLRP_PIO15 Position */
-#define GPIO_CLR_CLRP_PIO15_Msk (0x01UL << GPIO_CLR_CLRP_PIO15_Pos) /*!< GPIO CLR: CLRP_PIO15 Mask */
-#define GPIO_CLR_CLRP_PIO16_Pos 16 /*!< GPIO CLR: CLRP_PIO16 Position */
-#define GPIO_CLR_CLRP_PIO16_Msk (0x01UL << GPIO_CLR_CLRP_PIO16_Pos) /*!< GPIO CLR: CLRP_PIO16 Mask */
-#define GPIO_CLR_CLRP_PIO17_Pos 17 /*!< GPIO CLR: CLRP_PIO17 Position */
-#define GPIO_CLR_CLRP_PIO17_Msk (0x01UL << GPIO_CLR_CLRP_PIO17_Pos) /*!< GPIO CLR: CLRP_PIO17 Mask */
-#define GPIO_CLR_CLRP_PIO18_Pos 18 /*!< GPIO CLR: CLRP_PIO18 Position */
-#define GPIO_CLR_CLRP_PIO18_Msk (0x01UL << GPIO_CLR_CLRP_PIO18_Pos) /*!< GPIO CLR: CLRP_PIO18 Mask */
-#define GPIO_CLR_CLRP_PIO19_Pos 19 /*!< GPIO CLR: CLRP_PIO19 Position */
-#define GPIO_CLR_CLRP_PIO19_Msk (0x01UL << GPIO_CLR_CLRP_PIO19_Pos) /*!< GPIO CLR: CLRP_PIO19 Mask */
-#define GPIO_CLR_CLRP_PIO20_Pos 20 /*!< GPIO CLR: CLRP_PIO20 Position */
-#define GPIO_CLR_CLRP_PIO20_Msk (0x01UL << GPIO_CLR_CLRP_PIO20_Pos) /*!< GPIO CLR: CLRP_PIO20 Mask */
-#define GPIO_CLR_CLRP_PIO21_Pos 21 /*!< GPIO CLR: CLRP_PIO21 Position */
-#define GPIO_CLR_CLRP_PIO21_Msk (0x01UL << GPIO_CLR_CLRP_PIO21_Pos) /*!< GPIO CLR: CLRP_PIO21 Mask */
-
-/* --------------------------------- u_gpio_NOT --------------------------------- */
-#define GPIO_NOT_NOTP_PIO0_Pos 0 /*!< GPIO NOT: NOTP_PIO0 Position */
-#define GPIO_NOT_NOTP_PIO0_Msk (0x01UL << GPIO_NOT_NOTP_PIO0_Pos) /*!< GPIO NOT: NOTP_PIO0 Mask */
-#define GPIO_NOT_NOTP_PIO1_Pos 1 /*!< GPIO NOT: NOTP_PIO1 Position */
-#define GPIO_NOT_NOTP_PIO1_Msk (0x01UL << GPIO_NOT_NOTP_PIO1_Pos) /*!< GPIO NOT: NOTP_PIO1 Mask */
-#define GPIO_NOT_NOTP_PIO2_Pos 2 /*!< GPIO NOT: NOTP_PIO2 Position */
-#define GPIO_NOT_NOTP_PIO2_Msk (0x01UL << GPIO_NOT_NOTP_PIO2_Pos) /*!< GPIO NOT: NOTP_PIO2 Mask */
-#define GPIO_NOT_NOTP_PIO3_Pos 3 /*!< GPIO NOT: NOTP_PIO3 Position */
-#define GPIO_NOT_NOTP_PIO3_Msk (0x01UL << GPIO_NOT_NOTP_PIO3_Pos) /*!< GPIO NOT: NOTP_PIO3 Mask */
-#define GPIO_NOT_NOTP_PIO4_Pos 4 /*!< GPIO NOT: NOTP_PIO4 Position */
-#define GPIO_NOT_NOTP_PIO4_Msk (0x01UL << GPIO_NOT_NOTP_PIO4_Pos) /*!< GPIO NOT: NOTP_PIO4 Mask */
-#define GPIO_NOT_NOTP_PIO5_Pos 5 /*!< GPIO NOT: NOTP_PIO5 Position */
-#define GPIO_NOT_NOTP_PIO5_Msk (0x01UL << GPIO_NOT_NOTP_PIO5_Pos) /*!< GPIO NOT: NOTP_PIO5 Mask */
-#define GPIO_NOT_NOTP_PIO6_Pos 6 /*!< GPIO NOT: NOTP_PIO6 Position */
-#define GPIO_NOT_NOTP_PIO6_Msk (0x01UL << GPIO_NOT_NOTP_PIO6_Pos) /*!< GPIO NOT: NOTP_PIO6 Mask */
-#define GPIO_NOT_NOTP_PIO7_Pos 7 /*!< GPIO NOT: NOTP_PIO7 Position */
-#define GPIO_NOT_NOTP_PIO7_Msk (0x01UL << GPIO_NOT_NOTP_PIO7_Pos) /*!< GPIO NOT: NOTP_PIO7 Mask */
-#define GPIO_NOT_NOTP_PIO8_Pos 8 /*!< GPIO NOT: NOTP_PIO8 Position */
-#define GPIO_NOT_NOTP_PIO8_Msk (0x01UL << GPIO_NOT_NOTP_PIO8_Pos) /*!< GPIO NOT: NOTP_PIO8 Mask */
-#define GPIO_NOT_NOTP_PIO9_Pos 9 /*!< GPIO NOT: NOTP_PIO9 Position */
-#define GPIO_NOT_NOTP_PIO9_Msk (0x01UL << GPIO_NOT_NOTP_PIO9_Pos) /*!< GPIO NOT: NOTP_PIO9 Mask */
-#define GPIO_NOT_NOTP_PIO10_Pos 10 /*!< GPIO NOT: NOTP_PIO10 Position */
-#define GPIO_NOT_NOTP_PIO10_Msk (0x01UL << GPIO_NOT_NOTP_PIO10_Pos) /*!< GPIO NOT: NOTP_PIO10 Mask */
-#define GPIO_NOT_NOTP_PIO11_Pos 11 /*!< GPIO NOT: NOTP_PIO11 Position */
-#define GPIO_NOT_NOTP_PIO11_Msk (0x01UL << GPIO_NOT_NOTP_PIO11_Pos) /*!< GPIO NOT: NOTP_PIO11 Mask */
-#define GPIO_NOT_NOTP_PIO12_Pos 12 /*!< GPIO NOT: NOTP_PIO12 Position */
-#define GPIO_NOT_NOTP_PIO12_Msk (0x01UL << GPIO_NOT_NOTP_PIO12_Pos) /*!< GPIO NOT: NOTP_PIO12 Mask */
-#define GPIO_NOT_NOTP_PIO13_Pos 13 /*!< GPIO NOT: NOTP_PIO13 Position */
-#define GPIO_NOT_NOTP_PIO13_Msk (0x01UL << GPIO_NOT_NOTP_PIO13_Pos) /*!< GPIO NOT: NOTP_PIO13 Mask */
-#define GPIO_NOT_NOTP_PIO14_Pos 14 /*!< GPIO NOT: NOTP_PIO14 Position */
-#define GPIO_NOT_NOTP_PIO14_Msk (0x01UL << GPIO_NOT_NOTP_PIO14_Pos) /*!< GPIO NOT: NOTP_PIO14 Mask */
-#define GPIO_NOT_NOTP_PIO15_Pos 15 /*!< GPIO NOT: NOTP_PIO15 Position */
-#define GPIO_NOT_NOTP_PIO15_Msk (0x01UL << GPIO_NOT_NOTP_PIO15_Pos) /*!< GPIO NOT: NOTP_PIO15 Mask */
-#define GPIO_NOT_NOTP_PIO16_Pos 16 /*!< GPIO NOT: NOTP_PIO16 Position */
-#define GPIO_NOT_NOTP_PIO16_Msk (0x01UL << GPIO_NOT_NOTP_PIO16_Pos) /*!< GPIO NOT: NOTP_PIO16 Mask */
-#define GPIO_NOT_NOTP_PIO17_Pos 17 /*!< GPIO NOT: NOTP_PIO17 Position */
-#define GPIO_NOT_NOTP_PIO17_Msk (0x01UL << GPIO_NOT_NOTP_PIO17_Pos) /*!< GPIO NOT: NOTP_PIO17 Mask */
-#define GPIO_NOT_NOTP_PIO18_Pos 18 /*!< GPIO NOT: NOTP_PIO18 Position */
-#define GPIO_NOT_NOTP_PIO18_Msk (0x01UL << GPIO_NOT_NOTP_PIO18_Pos) /*!< GPIO NOT: NOTP_PIO18 Mask */
-#define GPIO_NOT_NOTP_PIO19_Pos 19 /*!< GPIO NOT: NOTP_PIO19 Position */
-#define GPIO_NOT_NOTP_PIO19_Msk (0x01UL << GPIO_NOT_NOTP_PIO19_Pos) /*!< GPIO NOT: NOTP_PIO19 Mask */
-#define GPIO_NOT_NOTP_PIO20_Pos 20 /*!< GPIO NOT: NOTP_PIO20 Position */
-#define GPIO_NOT_NOTP_PIO20_Msk (0x01UL << GPIO_NOT_NOTP_PIO20_Pos) /*!< GPIO NOT: NOTP_PIO20 Mask */
-#define GPIO_NOT_NOTP_PIO21_Pos 21 /*!< GPIO NOT: NOTP_PIO21 Position */
-#define GPIO_NOT_NOTP_PIO21_Msk (0x01UL << GPIO_NOT_NOTP_PIO21_Pos) /*!< GPIO NOT: NOTP_PIO21 Mask */
-
-/* -------------------------------- u_gpio_DIRSET ------------------------------- */
-#define GPIO_DIRSET_DIRSETP_PIO0_Pos 0 /*!< GPIO DIRSET: DIRSETP_PIO0 Position */
-#define GPIO_DIRSET_DIRSETP_PIO0_Msk (0x01UL << GPIO_DIRSET_DIRSETP_PIO0_Pos) /*!< GPIO DIRSET: DIRSETP_PIO0 Mask */
-#define GPIO_DIRSET_DIRSETP_PIO1_Pos 1 /*!< GPIO DIRSET: DIRSETP_PIO1 Position */
-#define GPIO_DIRSET_DIRSETP_PIO1_Msk (0x01UL << GPIO_DIRSET_DIRSETP_PIO1_Pos) /*!< GPIO DIRSET: DIRSETP_PIO1 Mask */
-#define GPIO_DIRSET_DIRSETP_PIO2_Pos 2 /*!< GPIO DIRSET: DIRSETP_PIO2 Position */
-#define GPIO_DIRSET_DIRSETP_PIO2_Msk (0x01UL << GPIO_DIRSET_DIRSETP_PIO2_Pos) /*!< GPIO DIRSET: DIRSETP_PIO2 Mask */
-#define GPIO_DIRSET_DIRSETP_PIO3_Pos 3 /*!< GPIO DIRSET: DIRSETP_PIO3 Position */
-#define GPIO_DIRSET_DIRSETP_PIO3_Msk (0x01UL << GPIO_DIRSET_DIRSETP_PIO3_Pos) /*!< GPIO DIRSET: DIRSETP_PIO3 Mask */
-#define GPIO_DIRSET_DIRSETP_PIO4_Pos 4 /*!< GPIO DIRSET: DIRSETP_PIO4 Position */
-#define GPIO_DIRSET_DIRSETP_PIO4_Msk (0x01UL << GPIO_DIRSET_DIRSETP_PIO4_Pos) /*!< GPIO DIRSET: DIRSETP_PIO4 Mask */
-#define GPIO_DIRSET_DIRSETP_PIO5_Pos 5 /*!< GPIO DIRSET: DIRSETP_PIO5 Position */
-#define GPIO_DIRSET_DIRSETP_PIO5_Msk (0x01UL << GPIO_DIRSET_DIRSETP_PIO5_Pos) /*!< GPIO DIRSET: DIRSETP_PIO5 Mask */
-#define GPIO_DIRSET_DIRSETP_PIO6_Pos 6 /*!< GPIO DIRSET: DIRSETP_PIO6 Position */
-#define GPIO_DIRSET_DIRSETP_PIO6_Msk (0x01UL << GPIO_DIRSET_DIRSETP_PIO6_Pos) /*!< GPIO DIRSET: DIRSETP_PIO6 Mask */
-#define GPIO_DIRSET_DIRSETP_PIO7_Pos 7 /*!< GPIO DIRSET: DIRSETP_PIO7 Position */
-#define GPIO_DIRSET_DIRSETP_PIO7_Msk (0x01UL << GPIO_DIRSET_DIRSETP_PIO7_Pos) /*!< GPIO DIRSET: DIRSETP_PIO7 Mask */
-#define GPIO_DIRSET_DIRSETP_PIO8_Pos 8 /*!< GPIO DIRSET: DIRSETP_PIO8 Position */
-#define GPIO_DIRSET_DIRSETP_PIO8_Msk (0x01UL << GPIO_DIRSET_DIRSETP_PIO8_Pos) /*!< GPIO DIRSET: DIRSETP_PIO8 Mask */
-#define GPIO_DIRSET_DIRSETP_PIO9_Pos 9 /*!< GPIO DIRSET: DIRSETP_PIO9 Position */
-#define GPIO_DIRSET_DIRSETP_PIO9_Msk (0x01UL << GPIO_DIRSET_DIRSETP_PIO9_Pos) /*!< GPIO DIRSET: DIRSETP_PIO9 Mask */
-#define GPIO_DIRSET_DIRSETP_PIO10_Pos 10 /*!< GPIO DIRSET: DIRSETP_PIO10 Position */
-#define GPIO_DIRSET_DIRSETP_PIO10_Msk (0x01UL << GPIO_DIRSET_DIRSETP_PIO10_Pos) /*!< GPIO DIRSET: DIRSETP_PIO10 Mask */
-#define GPIO_DIRSET_DIRSETP_PIO11_Pos 11 /*!< GPIO DIRSET: DIRSETP_PIO11 Position */
-#define GPIO_DIRSET_DIRSETP_PIO11_Msk (0x01UL << GPIO_DIRSET_DIRSETP_PIO11_Pos) /*!< GPIO DIRSET: DIRSETP_PIO11 Mask */
-#define GPIO_DIRSET_DIRSETP_PIO12_Pos 12 /*!< GPIO DIRSET: DIRSETP_PIO12 Position */
-#define GPIO_DIRSET_DIRSETP_PIO12_Msk (0x01UL << GPIO_DIRSET_DIRSETP_PIO12_Pos) /*!< GPIO DIRSET: DIRSETP_PIO12 Mask */
-#define GPIO_DIRSET_DIRSETP_PIO13_Pos 13 /*!< GPIO DIRSET: DIRSETP_PIO13 Position */
-#define GPIO_DIRSET_DIRSETP_PIO13_Msk (0x01UL << GPIO_DIRSET_DIRSETP_PIO13_Pos) /*!< GPIO DIRSET: DIRSETP_PIO13 Mask */
-#define GPIO_DIRSET_DIRSETP_PIO14_Pos 14 /*!< GPIO DIRSET: DIRSETP_PIO14 Position */
-#define GPIO_DIRSET_DIRSETP_PIO14_Msk (0x01UL << GPIO_DIRSET_DIRSETP_PIO14_Pos) /*!< GPIO DIRSET: DIRSETP_PIO14 Mask */
-#define GPIO_DIRSET_DIRSETP_PIO15_Pos 15 /*!< GPIO DIRSET: DIRSETP_PIO15 Position */
-#define GPIO_DIRSET_DIRSETP_PIO15_Msk (0x01UL << GPIO_DIRSET_DIRSETP_PIO15_Pos) /*!< GPIO DIRSET: DIRSETP_PIO15 Mask */
-#define GPIO_DIRSET_DIRSETP_PIO16_Pos 16 /*!< GPIO DIRSET: DIRSETP_PIO16 Position */
-#define GPIO_DIRSET_DIRSETP_PIO16_Msk (0x01UL << GPIO_DIRSET_DIRSETP_PIO16_Pos) /*!< GPIO DIRSET: DIRSETP_PIO16 Mask */
-#define GPIO_DIRSET_DIRSETP_PIO17_Pos 17 /*!< GPIO DIRSET: DIRSETP_PIO17 Position */
-#define GPIO_DIRSET_DIRSETP_PIO17_Msk (0x01UL << GPIO_DIRSET_DIRSETP_PIO17_Pos) /*!< GPIO DIRSET: DIRSETP_PIO17 Mask */
-#define GPIO_DIRSET_DIRSETP_PIO18_Pos 18 /*!< GPIO DIRSET: DIRSETP_PIO18 Position */
-#define GPIO_DIRSET_DIRSETP_PIO18_Msk (0x01UL << GPIO_DIRSET_DIRSETP_PIO18_Pos) /*!< GPIO DIRSET: DIRSETP_PIO18 Mask */
-#define GPIO_DIRSET_DIRSETP_PIO19_Pos 19 /*!< GPIO DIRSET: DIRSETP_PIO19 Position */
-#define GPIO_DIRSET_DIRSETP_PIO19_Msk (0x01UL << GPIO_DIRSET_DIRSETP_PIO19_Pos) /*!< GPIO DIRSET: DIRSETP_PIO19 Mask */
-#define GPIO_DIRSET_DIRSETP_PIO20_Pos 20 /*!< GPIO DIRSET: DIRSETP_PIO20 Position */
-#define GPIO_DIRSET_DIRSETP_PIO20_Msk (0x01UL << GPIO_DIRSET_DIRSETP_PIO20_Pos) /*!< GPIO DIRSET: DIRSETP_PIO20 Mask */
-#define GPIO_DIRSET_DIRSETP_PIO21_Pos 21 /*!< GPIO DIRSET: DIRSETP_PIO21 Position */
-#define GPIO_DIRSET_DIRSETP_PIO21_Msk (0x01UL << GPIO_DIRSET_DIRSETP_PIO21_Pos) /*!< GPIO DIRSET: DIRSETP_PIO21 Mask */
-
-/* -------------------------------- u_gpio_DIRCLR ------------------------------- */
-#define GPIO_DIRCLR_DIRCLRP_PIO0_Pos 0 /*!< GPIO DIRCLR: DIRCLRP_PIO0 Position */
-#define GPIO_DIRCLR_DIRCLRP_PIO0_Msk (0x01UL << GPIO_DIRCLR_DIRCLRP_PIO0_Pos) /*!< GPIO DIRCLR: DIRCLRP_PIO0 Mask */
-#define GPIO_DIRCLR_DIRCLRP_PIO1_Pos 1 /*!< GPIO DIRCLR: DIRCLRP_PIO1 Position */
-#define GPIO_DIRCLR_DIRCLRP_PIO1_Msk (0x01UL << GPIO_DIRCLR_DIRCLRP_PIO1_Pos) /*!< GPIO DIRCLR: DIRCLRP_PIO1 Mask */
-#define GPIO_DIRCLR_DIRCLRP_PIO2_Pos 2 /*!< GPIO DIRCLR: DIRCLRP_PIO2 Position */
-#define GPIO_DIRCLR_DIRCLRP_PIO2_Msk (0x01UL << GPIO_DIRCLR_DIRCLRP_PIO2_Pos) /*!< GPIO DIRCLR: DIRCLRP_PIO2 Mask */
-#define GPIO_DIRCLR_DIRCLRP_PIO3_Pos 3 /*!< GPIO DIRCLR: DIRCLRP_PIO3 Position */
-#define GPIO_DIRCLR_DIRCLRP_PIO3_Msk (0x01UL << GPIO_DIRCLR_DIRCLRP_PIO3_Pos) /*!< GPIO DIRCLR: DIRCLRP_PIO3 Mask */
-#define GPIO_DIRCLR_DIRCLRP_PIO4_Pos 4 /*!< GPIO DIRCLR: DIRCLRP_PIO4 Position */
-#define GPIO_DIRCLR_DIRCLRP_PIO4_Msk (0x01UL << GPIO_DIRCLR_DIRCLRP_PIO4_Pos) /*!< GPIO DIRCLR: DIRCLRP_PIO4 Mask */
-#define GPIO_DIRCLR_DIRCLRP_PIO5_Pos 5 /*!< GPIO DIRCLR: DIRCLRP_PIO5 Position */
-#define GPIO_DIRCLR_DIRCLRP_PIO5_Msk (0x01UL << GPIO_DIRCLR_DIRCLRP_PIO5_Pos) /*!< GPIO DIRCLR: DIRCLRP_PIO5 Mask */
-#define GPIO_DIRCLR_DIRCLRP_PIO6_Pos 6 /*!< GPIO DIRCLR: DIRCLRP_PIO6 Position */
-#define GPIO_DIRCLR_DIRCLRP_PIO6_Msk (0x01UL << GPIO_DIRCLR_DIRCLRP_PIO6_Pos) /*!< GPIO DIRCLR: DIRCLRP_PIO6 Mask */
-#define GPIO_DIRCLR_DIRCLRP_PIO7_Pos 7 /*!< GPIO DIRCLR: DIRCLRP_PIO7 Position */
-#define GPIO_DIRCLR_DIRCLRP_PIO7_Msk (0x01UL << GPIO_DIRCLR_DIRCLRP_PIO7_Pos) /*!< GPIO DIRCLR: DIRCLRP_PIO7 Mask */
-#define GPIO_DIRCLR_DIRCLRP_PIO8_Pos 8 /*!< GPIO DIRCLR: DIRCLRP_PIO8 Position */
-#define GPIO_DIRCLR_DIRCLRP_PIO8_Msk (0x01UL << GPIO_DIRCLR_DIRCLRP_PIO8_Pos) /*!< GPIO DIRCLR: DIRCLRP_PIO8 Mask */
-#define GPIO_DIRCLR_DIRCLRP_PIO9_Pos 9 /*!< GPIO DIRCLR: DIRCLRP_PIO9 Position */
-#define GPIO_DIRCLR_DIRCLRP_PIO9_Msk (0x01UL << GPIO_DIRCLR_DIRCLRP_PIO9_Pos) /*!< GPIO DIRCLR: DIRCLRP_PIO9 Mask */
-#define GPIO_DIRCLR_DIRCLRP_PIO10_Pos 10 /*!< GPIO DIRCLR: DIRCLRP_PIO10 Position */
-#define GPIO_DIRCLR_DIRCLRP_PIO10_Msk (0x01UL << GPIO_DIRCLR_DIRCLRP_PIO10_Pos) /*!< GPIO DIRCLR: DIRCLRP_PIO10 Mask */
-#define GPIO_DIRCLR_DIRCLRP_PIO11_Pos 11 /*!< GPIO DIRCLR: DIRCLRP_PIO11 Position */
-#define GPIO_DIRCLR_DIRCLRP_PIO11_Msk (0x01UL << GPIO_DIRCLR_DIRCLRP_PIO11_Pos) /*!< GPIO DIRCLR: DIRCLRP_PIO11 Mask */
-#define GPIO_DIRCLR_DIRCLRP_PIO12_Pos 12 /*!< GPIO DIRCLR: DIRCLRP_PIO12 Position */
-#define GPIO_DIRCLR_DIRCLRP_PIO12_Msk (0x01UL << GPIO_DIRCLR_DIRCLRP_PIO12_Pos) /*!< GPIO DIRCLR: DIRCLRP_PIO12 Mask */
-#define GPIO_DIRCLR_DIRCLRP_PIO13_Pos 13 /*!< GPIO DIRCLR: DIRCLRP_PIO13 Position */
-#define GPIO_DIRCLR_DIRCLRP_PIO13_Msk (0x01UL << GPIO_DIRCLR_DIRCLRP_PIO13_Pos) /*!< GPIO DIRCLR: DIRCLRP_PIO13 Mask */
-#define GPIO_DIRCLR_DIRCLRP_PIO14_Pos 14 /*!< GPIO DIRCLR: DIRCLRP_PIO14 Position */
-#define GPIO_DIRCLR_DIRCLRP_PIO14_Msk (0x01UL << GPIO_DIRCLR_DIRCLRP_PIO14_Pos) /*!< GPIO DIRCLR: DIRCLRP_PIO14 Mask */
-#define GPIO_DIRCLR_DIRCLRP_PIO15_Pos 15 /*!< GPIO DIRCLR: DIRCLRP_PIO15 Position */
-#define GPIO_DIRCLR_DIRCLRP_PIO15_Msk (0x01UL << GPIO_DIRCLR_DIRCLRP_PIO15_Pos) /*!< GPIO DIRCLR: DIRCLRP_PIO15 Mask */
-#define GPIO_DIRCLR_DIRCLRP_PIO16_Pos 16 /*!< GPIO DIRCLR: DIRCLRP_PIO16 Position */
-#define GPIO_DIRCLR_DIRCLRP_PIO16_Msk (0x01UL << GPIO_DIRCLR_DIRCLRP_PIO16_Pos) /*!< GPIO DIRCLR: DIRCLRP_PIO16 Mask */
-#define GPIO_DIRCLR_DIRCLRP_PIO17_Pos 17 /*!< GPIO DIRCLR: DIRCLRP_PIO17 Position */
-#define GPIO_DIRCLR_DIRCLRP_PIO17_Msk (0x01UL << GPIO_DIRCLR_DIRCLRP_PIO17_Pos) /*!< GPIO DIRCLR: DIRCLRP_PIO17 Mask */
-#define GPIO_DIRCLR_DIRCLRP_PIO18_Pos 18 /*!< GPIO DIRCLR: DIRCLRP_PIO18 Position */
-#define GPIO_DIRCLR_DIRCLRP_PIO18_Msk (0x01UL << GPIO_DIRCLR_DIRCLRP_PIO18_Pos) /*!< GPIO DIRCLR: DIRCLRP_PIO18 Mask */
-#define GPIO_DIRCLR_DIRCLRP_PIO19_Pos 19 /*!< GPIO DIRCLR: DIRCLRP_PIO19 Position */
-#define GPIO_DIRCLR_DIRCLRP_PIO19_Msk (0x01UL << GPIO_DIRCLR_DIRCLRP_PIO19_Pos) /*!< GPIO DIRCLR: DIRCLRP_PIO19 Mask */
-#define GPIO_DIRCLR_DIRCLRP_PIO20_Pos 20 /*!< GPIO DIRCLR: DIRCLRP_PIO20 Position */
-#define GPIO_DIRCLR_DIRCLRP_PIO20_Msk (0x01UL << GPIO_DIRCLR_DIRCLRP_PIO20_Pos) /*!< GPIO DIRCLR: DIRCLRP_PIO20 Mask */
-#define GPIO_DIRCLR_DIRCLRP_PIO21_Pos 21 /*!< GPIO DIRCLR: DIRCLRP_PIO21 Position */
-#define GPIO_DIRCLR_DIRCLRP_PIO21_Msk (0x01UL << GPIO_DIRCLR_DIRCLRP_PIO21_Pos) /*!< GPIO DIRCLR: DIRCLRP_PIO21 Mask */
-
-/* -------------------------------- u_gpio_DIRNOT ------------------------------- */
-#define GPIO_DIRNOT_DIRNOTP_PIO0_Pos 0 /*!< GPIO DIRNOT: DIRNOTP_PIO0 Position */
-#define GPIO_DIRNOT_DIRNOTP_PIO0_Msk (0x01UL << GPIO_DIRNOT_DIRNOTP_PIO0_Pos) /*!< GPIO DIRNOT: DIRNOTP_PIO0 Mask */
-#define GPIO_DIRNOT_DIRNOTP_PIO1_Pos 1 /*!< GPIO DIRNOT: DIRNOTP_PIO1 Position */
-#define GPIO_DIRNOT_DIRNOTP_PIO1_Msk (0x01UL << GPIO_DIRNOT_DIRNOTP_PIO1_Pos) /*!< GPIO DIRNOT: DIRNOTP_PIO1 Mask */
-#define GPIO_DIRNOT_DIRNOTP_PIO2_Pos 2 /*!< GPIO DIRNOT: DIRNOTP_PIO2 Position */
-#define GPIO_DIRNOT_DIRNOTP_PIO2_Msk (0x01UL << GPIO_DIRNOT_DIRNOTP_PIO2_Pos) /*!< GPIO DIRNOT: DIRNOTP_PIO2 Mask */
-#define GPIO_DIRNOT_DIRNOTP_PIO3_Pos 3 /*!< GPIO DIRNOT: DIRNOTP_PIO3 Position */
-#define GPIO_DIRNOT_DIRNOTP_PIO3_Msk (0x01UL << GPIO_DIRNOT_DIRNOTP_PIO3_Pos) /*!< GPIO DIRNOT: DIRNOTP_PIO3 Mask */
-#define GPIO_DIRNOT_DIRNOTP_PIO4_Pos 4 /*!< GPIO DIRNOT: DIRNOTP_PIO4 Position */
-#define GPIO_DIRNOT_DIRNOTP_PIO4_Msk (0x01UL << GPIO_DIRNOT_DIRNOTP_PIO4_Pos) /*!< GPIO DIRNOT: DIRNOTP_PIO4 Mask */
-#define GPIO_DIRNOT_DIRNOTP_PIO5_Pos 5 /*!< GPIO DIRNOT: DIRNOTP_PIO5 Position */
-#define GPIO_DIRNOT_DIRNOTP_PIO5_Msk (0x01UL << GPIO_DIRNOT_DIRNOTP_PIO5_Pos) /*!< GPIO DIRNOT: DIRNOTP_PIO5 Mask */
-#define GPIO_DIRNOT_DIRNOTP_PIO6_Pos 6 /*!< GPIO DIRNOT: DIRNOTP_PIO6 Position */
-#define GPIO_DIRNOT_DIRNOTP_PIO6_Msk (0x01UL << GPIO_DIRNOT_DIRNOTP_PIO6_Pos) /*!< GPIO DIRNOT: DIRNOTP_PIO6 Mask */
-#define GPIO_DIRNOT_DIRNOTP_PIO7_Pos 7 /*!< GPIO DIRNOT: DIRNOTP_PIO7 Position */
-#define GPIO_DIRNOT_DIRNOTP_PIO7_Msk (0x01UL << GPIO_DIRNOT_DIRNOTP_PIO7_Pos) /*!< GPIO DIRNOT: DIRNOTP_PIO7 Mask */
-#define GPIO_DIRNOT_DIRNOTP_PIO8_Pos 8 /*!< GPIO DIRNOT: DIRNOTP_PIO8 Position */
-#define GPIO_DIRNOT_DIRNOTP_PIO8_Msk (0x01UL << GPIO_DIRNOT_DIRNOTP_PIO8_Pos) /*!< GPIO DIRNOT: DIRNOTP_PIO8 Mask */
-#define GPIO_DIRNOT_DIRNOTP_PIO9_Pos 9 /*!< GPIO DIRNOT: DIRNOTP_PIO9 Position */
-#define GPIO_DIRNOT_DIRNOTP_PIO9_Msk (0x01UL << GPIO_DIRNOT_DIRNOTP_PIO9_Pos) /*!< GPIO DIRNOT: DIRNOTP_PIO9 Mask */
-#define GPIO_DIRNOT_DIRNOTP_PIO10_Pos 10 /*!< GPIO DIRNOT: DIRNOTP_PIO10 Position */
-#define GPIO_DIRNOT_DIRNOTP_PIO10_Msk (0x01UL << GPIO_DIRNOT_DIRNOTP_PIO10_Pos) /*!< GPIO DIRNOT: DIRNOTP_PIO10 Mask */
-#define GPIO_DIRNOT_DIRNOTP_PIO11_Pos 11 /*!< GPIO DIRNOT: DIRNOTP_PIO11 Position */
-#define GPIO_DIRNOT_DIRNOTP_PIO11_Msk (0x01UL << GPIO_DIRNOT_DIRNOTP_PIO11_Pos) /*!< GPIO DIRNOT: DIRNOTP_PIO11 Mask */
-#define GPIO_DIRNOT_DIRNOTP_PIO12_Pos 12 /*!< GPIO DIRNOT: DIRNOTP_PIO12 Position */
-#define GPIO_DIRNOT_DIRNOTP_PIO12_Msk (0x01UL << GPIO_DIRNOT_DIRNOTP_PIO12_Pos) /*!< GPIO DIRNOT: DIRNOTP_PIO12 Mask */
-#define GPIO_DIRNOT_DIRNOTP_PIO13_Pos 13 /*!< GPIO DIRNOT: DIRNOTP_PIO13 Position */
-#define GPIO_DIRNOT_DIRNOTP_PIO13_Msk (0x01UL << GPIO_DIRNOT_DIRNOTP_PIO13_Pos) /*!< GPIO DIRNOT: DIRNOTP_PIO13 Mask */
-#define GPIO_DIRNOT_DIRNOTP_PIO14_Pos 14 /*!< GPIO DIRNOT: DIRNOTP_PIO14 Position */
-#define GPIO_DIRNOT_DIRNOTP_PIO14_Msk (0x01UL << GPIO_DIRNOT_DIRNOTP_PIO14_Pos) /*!< GPIO DIRNOT: DIRNOTP_PIO14 Mask */
-#define GPIO_DIRNOT_DIRNOTP_PIO15_Pos 15 /*!< GPIO DIRNOT: DIRNOTP_PIO15 Position */
-#define GPIO_DIRNOT_DIRNOTP_PIO15_Msk (0x01UL << GPIO_DIRNOT_DIRNOTP_PIO15_Pos) /*!< GPIO DIRNOT: DIRNOTP_PIO15 Mask */
-#define GPIO_DIRNOT_DIRNOTP_PIO16_Pos 16 /*!< GPIO DIRNOT: DIRNOTP_PIO16 Position */
-#define GPIO_DIRNOT_DIRNOTP_PIO16_Msk (0x01UL << GPIO_DIRNOT_DIRNOTP_PIO16_Pos) /*!< GPIO DIRNOT: DIRNOTP_PIO16 Mask */
-#define GPIO_DIRNOT_DIRNOTP_PIO17_Pos 17 /*!< GPIO DIRNOT: DIRNOTP_PIO17 Position */
-#define GPIO_DIRNOT_DIRNOTP_PIO17_Msk (0x01UL << GPIO_DIRNOT_DIRNOTP_PIO17_Pos) /*!< GPIO DIRNOT: DIRNOTP_PIO17 Mask */
-#define GPIO_DIRNOT_DIRNOTP_PIO18_Pos 18 /*!< GPIO DIRNOT: DIRNOTP_PIO18 Position */
-#define GPIO_DIRNOT_DIRNOTP_PIO18_Msk (0x01UL << GPIO_DIRNOT_DIRNOTP_PIO18_Pos) /*!< GPIO DIRNOT: DIRNOTP_PIO18 Mask */
-#define GPIO_DIRNOT_DIRNOTP_PIO19_Pos 19 /*!< GPIO DIRNOT: DIRNOTP_PIO19 Position */
-#define GPIO_DIRNOT_DIRNOTP_PIO19_Msk (0x01UL << GPIO_DIRNOT_DIRNOTP_PIO19_Pos) /*!< GPIO DIRNOT: DIRNOTP_PIO19 Mask */
-#define GPIO_DIRNOT_DIRNOTP_PIO20_Pos 20 /*!< GPIO DIRNOT: DIRNOTP_PIO20 Position */
-#define GPIO_DIRNOT_DIRNOTP_PIO20_Msk (0x01UL << GPIO_DIRNOT_DIRNOTP_PIO20_Pos) /*!< GPIO DIRNOT: DIRNOTP_PIO20 Mask */
-#define GPIO_DIRNOT_DIRNOTP_PIO21_Pos 21 /*!< GPIO DIRNOT: DIRNOTP_PIO21 Position */
-#define GPIO_DIRNOT_DIRNOTP_PIO21_Msk (0x01UL << GPIO_DIRNOT_DIRNOTP_PIO21_Pos) /*!< GPIO DIRNOT: DIRNOTP_PIO21 Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u_spifi' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* -------------------------------- u_spifi_CTRL -------------------------------- */
-#define SPIFI_CTRL_TIMEOUT_Pos 0 /*!< SPIFI CTRL: TIMEOUT Position */
-#define SPIFI_CTRL_TIMEOUT_Msk (0x0000ffffUL << SPIFI_CTRL_TIMEOUT_Pos) /*!< SPIFI CTRL: TIMEOUT Mask */
-#define SPIFI_CTRL_CSHIGH_Pos 16 /*!< SPIFI CTRL: CSHIGH Position */
-#define SPIFI_CTRL_CSHIGH_Msk (0x0fUL << SPIFI_CTRL_CSHIGH_Pos) /*!< SPIFI CTRL: CSHIGH Mask */
-#define SPIFI_CTRL_D_PRFTCH_DIS_Pos 21 /*!< SPIFI CTRL: D_PRFTCH_DIS Position */
-#define SPIFI_CTRL_D_PRFTCH_DIS_Msk (0x01UL << SPIFI_CTRL_D_PRFTCH_DIS_Pos) /*!< SPIFI CTRL: D_PRFTCH_DIS Mask */
-#define SPIFI_CTRL_INTEN_Pos 22 /*!< SPIFI CTRL: INTEN Position */
-#define SPIFI_CTRL_INTEN_Msk (0x01UL << SPIFI_CTRL_INTEN_Pos) /*!< SPIFI CTRL: INTEN Mask */
-#define SPIFI_CTRL_MODE3_Pos 23 /*!< SPIFI CTRL: MODE3 Position */
-#define SPIFI_CTRL_MODE3_Msk (0x01UL << SPIFI_CTRL_MODE3_Pos) /*!< SPIFI CTRL: MODE3 Mask */
-#define SPIFI_CTRL_PRFTCH_DIS_Pos 27 /*!< SPIFI CTRL: PRFTCH_DIS Position */
-#define SPIFI_CTRL_PRFTCH_DIS_Msk (0x01UL << SPIFI_CTRL_PRFTCH_DIS_Pos) /*!< SPIFI CTRL: PRFTCH_DIS Mask */
-#define SPIFI_CTRL_DUAL_Pos 28 /*!< SPIFI CTRL: DUAL Position */
-#define SPIFI_CTRL_DUAL_Msk (0x01UL << SPIFI_CTRL_DUAL_Pos) /*!< SPIFI CTRL: DUAL Mask */
-#define SPIFI_CTRL_RFCLK_Pos 29 /*!< SPIFI CTRL: RFCLK Position */
-#define SPIFI_CTRL_RFCLK_Msk (0x01UL << SPIFI_CTRL_RFCLK_Pos) /*!< SPIFI CTRL: RFCLK Mask */
-#define SPIFI_CTRL_FBCLK_Pos 30 /*!< SPIFI CTRL: FBCLK Position */
-#define SPIFI_CTRL_FBCLK_Msk (0x01UL << SPIFI_CTRL_FBCLK_Pos) /*!< SPIFI CTRL: FBCLK Mask */
-#define SPIFI_CTRL_DMAEN_Pos 31 /*!< SPIFI CTRL: DMAEN Position */
-#define SPIFI_CTRL_DMAEN_Msk (0x01UL << SPIFI_CTRL_DMAEN_Pos) /*!< SPIFI CTRL: DMAEN Mask */
-
-/* --------------------------------- u_spifi_CMD -------------------------------- */
-#define SPIFI_CMD_DATALEN_Pos 0 /*!< SPIFI CMD: DATALEN Position */
-#define SPIFI_CMD_DATALEN_Msk (0x00003fffUL << SPIFI_CMD_DATALEN_Pos) /*!< SPIFI CMD: DATALEN Mask */
-#define SPIFI_CMD_POLL_Pos 14 /*!< SPIFI CMD: POLL Position */
-#define SPIFI_CMD_POLL_Msk (0x01UL << SPIFI_CMD_POLL_Pos) /*!< SPIFI CMD: POLL Mask */
-#define SPIFI_CMD_DOUT_Pos 15 /*!< SPIFI CMD: DOUT Position */
-#define SPIFI_CMD_DOUT_Msk (0x01UL << SPIFI_CMD_DOUT_Pos) /*!< SPIFI CMD: DOUT Mask */
-#define SPIFI_CMD_INTLEN_Pos 16 /*!< SPIFI CMD: INTLEN Position */
-#define SPIFI_CMD_INTLEN_Msk (0x07UL << SPIFI_CMD_INTLEN_Pos) /*!< SPIFI CMD: INTLEN Mask */
-#define SPIFI_CMD_FIELDFORM_Pos 19 /*!< SPIFI CMD: FIELDFORM Position */
-#define SPIFI_CMD_FIELDFORM_Msk (0x03UL << SPIFI_CMD_FIELDFORM_Pos) /*!< SPIFI CMD: FIELDFORM Mask */
-#define SPIFI_CMD_FRAMEFORM_Pos 21 /*!< SPIFI CMD: FRAMEFORM Position */
-#define SPIFI_CMD_FRAMEFORM_Msk (0x07UL << SPIFI_CMD_FRAMEFORM_Pos) /*!< SPIFI CMD: FRAMEFORM Mask */
-#define SPIFI_CMD_OPCODE_Pos 24 /*!< SPIFI CMD: OPCODE Position */
-#define SPIFI_CMD_OPCODE_Msk (0x000000ffUL << SPIFI_CMD_OPCODE_Pos) /*!< SPIFI CMD: OPCODE Mask */
-
-/* -------------------------------- u_spifi_ADDR -------------------------------- */
-#define SPIFI_ADDR_ADDR_Pos 0 /*!< SPIFI ADDR: ADDR Position */
-#define SPIFI_ADDR_ADDR_Msk (0xffffffffUL << SPIFI_ADDR_ADDR_Pos) /*!< SPIFI ADDR: ADDR Mask */
-
-/* -------------------------------- u_spifi_IDATA ------------------------------- */
-#define SPIFI_IDATA_IDATA_Pos 0 /*!< SPIFI IDATA: IDATA Position */
-#define SPIFI_IDATA_IDATA_Msk (0xffffffffUL << SPIFI_IDATA_IDATA_Pos) /*!< SPIFI IDATA: IDATA Mask */
-
-/* ------------------------------- u_spifi_CLIMIT ------------------------------- */
-#define SPIFI_CLIMIT_CLIMIT_Pos 0 /*!< SPIFI CLIMIT: CLIMIT Position */
-#define SPIFI_CLIMIT_CLIMIT_Msk (0xffffffffUL << SPIFI_CLIMIT_CLIMIT_Pos) /*!< SPIFI CLIMIT: CLIMIT Mask */
-
-/* -------------------------------- u_spifi_DATA -------------------------------- */
-#define SPIFI_DATA_DATA_Pos 0 /*!< SPIFI DATA: DATA Position */
-#define SPIFI_DATA_DATA_Msk (0xffffffffUL << SPIFI_DATA_DATA_Pos) /*!< SPIFI DATA: DATA Mask */
-
-/* -------------------------------- u_spifi_MCMD -------------------------------- */
-#define SPIFI_MCMD_POLL_Pos 14 /*!< SPIFI MCMD: POLL Position */
-#define SPIFI_MCMD_POLL_Msk (0x01UL << SPIFI_MCMD_POLL_Pos) /*!< SPIFI MCMD: POLL Mask */
-#define SPIFI_MCMD_DOUT_Pos 15 /*!< SPIFI MCMD: DOUT Position */
-#define SPIFI_MCMD_DOUT_Msk (0x01UL << SPIFI_MCMD_DOUT_Pos) /*!< SPIFI MCMD: DOUT Mask */
-#define SPIFI_MCMD_INTLEN_Pos 16 /*!< SPIFI MCMD: INTLEN Position */
-#define SPIFI_MCMD_INTLEN_Msk (0x07UL << SPIFI_MCMD_INTLEN_Pos) /*!< SPIFI MCMD: INTLEN Mask */
-#define SPIFI_MCMD_FIELDFORM_Pos 19 /*!< SPIFI MCMD: FIELDFORM Position */
-#define SPIFI_MCMD_FIELDFORM_Msk (0x03UL << SPIFI_MCMD_FIELDFORM_Pos) /*!< SPIFI MCMD: FIELDFORM Mask */
-#define SPIFI_MCMD_FRAMEFORM_Pos 21 /*!< SPIFI MCMD: FRAMEFORM Position */
-#define SPIFI_MCMD_FRAMEFORM_Msk (0x07UL << SPIFI_MCMD_FRAMEFORM_Pos) /*!< SPIFI MCMD: FRAMEFORM Mask */
-#define SPIFI_MCMD_OPCODE_Pos 24 /*!< SPIFI MCMD: OPCODE Position */
-#define SPIFI_MCMD_OPCODE_Msk (0x000000ffUL << SPIFI_MCMD_OPCODE_Pos) /*!< SPIFI MCMD: OPCODE Mask */
-
-/* -------------------------------- u_spifi_STAT -------------------------------- */
-#define SPIFI_STAT_MCINIT_Pos 0 /*!< SPIFI STAT: MCINIT Position */
-#define SPIFI_STAT_MCINIT_Msk (0x01UL << SPIFI_STAT_MCINIT_Pos) /*!< SPIFI STAT: MCINIT Mask */
-#define SPIFI_STAT_CMD_Pos 1 /*!< SPIFI STAT: CMD Position */
-#define SPIFI_STAT_CMD_Msk (0x01UL << SPIFI_STAT_CMD_Pos) /*!< SPIFI STAT: CMD Mask */
-#define SPIFI_STAT_RESET_Pos 4 /*!< SPIFI STAT: RESET Position */
-#define SPIFI_STAT_RESET_Msk (0x01UL << SPIFI_STAT_RESET_Pos) /*!< SPIFI STAT: RESET Mask */
-#define SPIFI_STAT_INTRQ_Pos 5 /*!< SPIFI STAT: INTRQ Position */
-#define SPIFI_STAT_INTRQ_Msk (0x01UL << SPIFI_STAT_INTRQ_Pos) /*!< SPIFI STAT: INTRQ Mask */
-#define SPIFI_STAT_VERSION_Pos 24 /*!< SPIFI STAT: VERSION Position */
-#define SPIFI_STAT_VERSION_Msk (0x000000ffUL << SPIFI_STAT_VERSION_Pos) /*!< SPIFI STAT: VERSION Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u_dma' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* --------------------------------- u_dma_CTRL --------------------------------- */
-#define DMA_CTRL_ENABLE_Pos 0 /*!< DMA CTRL: ENABLE Position */
-#define DMA_CTRL_ENABLE_Msk (0x01UL << DMA_CTRL_ENABLE_Pos) /*!< DMA CTRL: ENABLE Mask */
-
-/* -------------------------------- u_dma_INTSTAT ------------------------------- */
-#define DMA_INTSTAT_ACTIVEINT_Pos 1 /*!< DMA INTSTAT: ACTIVEINT Position */
-#define DMA_INTSTAT_ACTIVEINT_Msk (0x01UL << DMA_INTSTAT_ACTIVEINT_Pos) /*!< DMA INTSTAT: ACTIVEINT Mask */
-#define DMA_INTSTAT_ACTIVEERRINT_Pos 2 /*!< DMA INTSTAT: ACTIVEERRINT Position */
-#define DMA_INTSTAT_ACTIVEERRINT_Msk (0x01UL << DMA_INTSTAT_ACTIVEERRINT_Pos) /*!< DMA INTSTAT: ACTIVEERRINT Mask */
-
-/* ------------------------------- u_dma_SRAMBASE ------------------------------- */
-#define DMA_SRAMBASE_OFFSET_Pos 9 /*!< DMA SRAMBASE: OFFSET Position */
-#define DMA_SRAMBASE_OFFSET_Msk (0x007fffffUL << DMA_SRAMBASE_OFFSET_Pos) /*!< DMA SRAMBASE: OFFSET Mask */
-
-/* ------------------------------ u_dma_ENABLESET0 ------------------------------ */
-#define DMA_ENABLESET0_ENA_CH0_Pos 0 /*!< DMA ENABLESET0: ENA_CH0 Position */
-#define DMA_ENABLESET0_ENA_CH0_Msk (0x01UL << DMA_ENABLESET0_ENA_CH0_Pos) /*!< DMA ENABLESET0: ENA_CH0 Mask */
-#define DMA_ENABLESET0_ENA_CH1_Pos 1 /*!< DMA ENABLESET0: ENA_CH1 Position */
-#define DMA_ENABLESET0_ENA_CH1_Msk (0x01UL << DMA_ENABLESET0_ENA_CH1_Pos) /*!< DMA ENABLESET0: ENA_CH1 Mask */
-#define DMA_ENABLESET0_ENA_CH2_Pos 2 /*!< DMA ENABLESET0: ENA_CH2 Position */
-#define DMA_ENABLESET0_ENA_CH2_Msk (0x01UL << DMA_ENABLESET0_ENA_CH2_Pos) /*!< DMA ENABLESET0: ENA_CH2 Mask */
-#define DMA_ENABLESET0_ENA_CH3_Pos 3 /*!< DMA ENABLESET0: ENA_CH3 Position */
-#define DMA_ENABLESET0_ENA_CH3_Msk (0x01UL << DMA_ENABLESET0_ENA_CH3_Pos) /*!< DMA ENABLESET0: ENA_CH3 Mask */
-#define DMA_ENABLESET0_ENA_CH4_Pos 4 /*!< DMA ENABLESET0: ENA_CH4 Position */
-#define DMA_ENABLESET0_ENA_CH4_Msk (0x01UL << DMA_ENABLESET0_ENA_CH4_Pos) /*!< DMA ENABLESET0: ENA_CH4 Mask */
-#define DMA_ENABLESET0_ENA_CH5_Pos 5 /*!< DMA ENABLESET0: ENA_CH5 Position */
-#define DMA_ENABLESET0_ENA_CH5_Msk (0x01UL << DMA_ENABLESET0_ENA_CH5_Pos) /*!< DMA ENABLESET0: ENA_CH5 Mask */
-#define DMA_ENABLESET0_ENA_CH6_Pos 6 /*!< DMA ENABLESET0: ENA_CH6 Position */
-#define DMA_ENABLESET0_ENA_CH6_Msk (0x01UL << DMA_ENABLESET0_ENA_CH6_Pos) /*!< DMA ENABLESET0: ENA_CH6 Mask */
-#define DMA_ENABLESET0_ENA_CH7_Pos 7 /*!< DMA ENABLESET0: ENA_CH7 Position */
-#define DMA_ENABLESET0_ENA_CH7_Msk (0x01UL << DMA_ENABLESET0_ENA_CH7_Pos) /*!< DMA ENABLESET0: ENA_CH7 Mask */
-#define DMA_ENABLESET0_ENA_CH8_Pos 8 /*!< DMA ENABLESET0: ENA_CH8 Position */
-#define DMA_ENABLESET0_ENA_CH8_Msk (0x01UL << DMA_ENABLESET0_ENA_CH8_Pos) /*!< DMA ENABLESET0: ENA_CH8 Mask */
-#define DMA_ENABLESET0_ENA_CH9_Pos 9 /*!< DMA ENABLESET0: ENA_CH9 Position */
-#define DMA_ENABLESET0_ENA_CH9_Msk (0x01UL << DMA_ENABLESET0_ENA_CH9_Pos) /*!< DMA ENABLESET0: ENA_CH9 Mask */
-#define DMA_ENABLESET0_ENA_CH10_Pos 10 /*!< DMA ENABLESET0: ENA_CH10 Position */
-#define DMA_ENABLESET0_ENA_CH10_Msk (0x01UL << DMA_ENABLESET0_ENA_CH10_Pos) /*!< DMA ENABLESET0: ENA_CH10 Mask */
-#define DMA_ENABLESET0_ENA_CH11_Pos 11 /*!< DMA ENABLESET0: ENA_CH11 Position */
-#define DMA_ENABLESET0_ENA_CH11_Msk (0x01UL << DMA_ENABLESET0_ENA_CH11_Pos) /*!< DMA ENABLESET0: ENA_CH11 Mask */
-#define DMA_ENABLESET0_ENA_CH12_Pos 12 /*!< DMA ENABLESET0: ENA_CH12 Position */
-#define DMA_ENABLESET0_ENA_CH12_Msk (0x01UL << DMA_ENABLESET0_ENA_CH12_Pos) /*!< DMA ENABLESET0: ENA_CH12 Mask */
-#define DMA_ENABLESET0_ENA_CH13_Pos 13 /*!< DMA ENABLESET0: ENA_CH13 Position */
-#define DMA_ENABLESET0_ENA_CH13_Msk (0x01UL << DMA_ENABLESET0_ENA_CH13_Pos) /*!< DMA ENABLESET0: ENA_CH13 Mask */
-#define DMA_ENABLESET0_ENA_CH14_Pos 14 /*!< DMA ENABLESET0: ENA_CH14 Position */
-#define DMA_ENABLESET0_ENA_CH14_Msk (0x01UL << DMA_ENABLESET0_ENA_CH14_Pos) /*!< DMA ENABLESET0: ENA_CH14 Mask */
-#define DMA_ENABLESET0_ENA_CH15_Pos 15 /*!< DMA ENABLESET0: ENA_CH15 Position */
-#define DMA_ENABLESET0_ENA_CH15_Msk (0x01UL << DMA_ENABLESET0_ENA_CH15_Pos) /*!< DMA ENABLESET0: ENA_CH15 Mask */
-#define DMA_ENABLESET0_ENA_CH16_Pos 16 /*!< DMA ENABLESET0: ENA_CH16 Position */
-#define DMA_ENABLESET0_ENA_CH16_Msk (0x01UL << DMA_ENABLESET0_ENA_CH16_Pos) /*!< DMA ENABLESET0: ENA_CH16 Mask */
-#define DMA_ENABLESET0_ENA_CH17_Pos 17 /*!< DMA ENABLESET0: ENA_CH17 Position */
-#define DMA_ENABLESET0_ENA_CH17_Msk (0x01UL << DMA_ENABLESET0_ENA_CH17_Pos) /*!< DMA ENABLESET0: ENA_CH17 Mask */
-#define DMA_ENABLESET0_ENA_CH18_Pos 18 /*!< DMA ENABLESET0: ENA_CH18 Position */
-#define DMA_ENABLESET0_ENA_CH18_Msk (0x01UL << DMA_ENABLESET0_ENA_CH18_Pos) /*!< DMA ENABLESET0: ENA_CH18 Mask */
-
-/* ------------------------------ u_dma_ENABLECLR0 ------------------------------ */
-#define DMA_ENABLECLR0_CLR_CH0_Pos 0 /*!< DMA ENABLECLR0: CLR_CH0 Position */
-#define DMA_ENABLECLR0_CLR_CH0_Msk (0x01UL << DMA_ENABLECLR0_CLR_CH0_Pos) /*!< DMA ENABLECLR0: CLR_CH0 Mask */
-#define DMA_ENABLECLR0_CLR_CH1_Pos 1 /*!< DMA ENABLECLR0: CLR_CH1 Position */
-#define DMA_ENABLECLR0_CLR_CH1_Msk (0x01UL << DMA_ENABLECLR0_CLR_CH1_Pos) /*!< DMA ENABLECLR0: CLR_CH1 Mask */
-#define DMA_ENABLECLR0_CLR_CH2_Pos 2 /*!< DMA ENABLECLR0: CLR_CH2 Position */
-#define DMA_ENABLECLR0_CLR_CH2_Msk (0x01UL << DMA_ENABLECLR0_CLR_CH2_Pos) /*!< DMA ENABLECLR0: CLR_CH2 Mask */
-#define DMA_ENABLECLR0_CLR_CH3_Pos 3 /*!< DMA ENABLECLR0: CLR_CH3 Position */
-#define DMA_ENABLECLR0_CLR_CH3_Msk (0x01UL << DMA_ENABLECLR0_CLR_CH3_Pos) /*!< DMA ENABLECLR0: CLR_CH3 Mask */
-#define DMA_ENABLECLR0_CLR_CH4_Pos 4 /*!< DMA ENABLECLR0: CLR_CH4 Position */
-#define DMA_ENABLECLR0_CLR_CH4_Msk (0x01UL << DMA_ENABLECLR0_CLR_CH4_Pos) /*!< DMA ENABLECLR0: CLR_CH4 Mask */
-#define DMA_ENABLECLR0_CLR_CH5_Pos 5 /*!< DMA ENABLECLR0: CLR_CH5 Position */
-#define DMA_ENABLECLR0_CLR_CH5_Msk (0x01UL << DMA_ENABLECLR0_CLR_CH5_Pos) /*!< DMA ENABLECLR0: CLR_CH5 Mask */
-#define DMA_ENABLECLR0_CLR_CH6_Pos 6 /*!< DMA ENABLECLR0: CLR_CH6 Position */
-#define DMA_ENABLECLR0_CLR_CH6_Msk (0x01UL << DMA_ENABLECLR0_CLR_CH6_Pos) /*!< DMA ENABLECLR0: CLR_CH6 Mask */
-#define DMA_ENABLECLR0_CLR_CH7_Pos 7 /*!< DMA ENABLECLR0: CLR_CH7 Position */
-#define DMA_ENABLECLR0_CLR_CH7_Msk (0x01UL << DMA_ENABLECLR0_CLR_CH7_Pos) /*!< DMA ENABLECLR0: CLR_CH7 Mask */
-#define DMA_ENABLECLR0_CLR_CH8_Pos 8 /*!< DMA ENABLECLR0: CLR_CH8 Position */
-#define DMA_ENABLECLR0_CLR_CH8_Msk (0x01UL << DMA_ENABLECLR0_CLR_CH8_Pos) /*!< DMA ENABLECLR0: CLR_CH8 Mask */
-#define DMA_ENABLECLR0_CLR_CH9_Pos 9 /*!< DMA ENABLECLR0: CLR_CH9 Position */
-#define DMA_ENABLECLR0_CLR_CH9_Msk (0x01UL << DMA_ENABLECLR0_CLR_CH9_Pos) /*!< DMA ENABLECLR0: CLR_CH9 Mask */
-#define DMA_ENABLECLR0_CLR_CH10_Pos 10 /*!< DMA ENABLECLR0: CLR_CH10 Position */
-#define DMA_ENABLECLR0_CLR_CH10_Msk (0x01UL << DMA_ENABLECLR0_CLR_CH10_Pos) /*!< DMA ENABLECLR0: CLR_CH10 Mask */
-#define DMA_ENABLECLR0_CLR_CH11_Pos 11 /*!< DMA ENABLECLR0: CLR_CH11 Position */
-#define DMA_ENABLECLR0_CLR_CH11_Msk (0x01UL << DMA_ENABLECLR0_CLR_CH11_Pos) /*!< DMA ENABLECLR0: CLR_CH11 Mask */
-#define DMA_ENABLECLR0_CLR_CH12_Pos 12 /*!< DMA ENABLECLR0: CLR_CH12 Position */
-#define DMA_ENABLECLR0_CLR_CH12_Msk (0x01UL << DMA_ENABLECLR0_CLR_CH12_Pos) /*!< DMA ENABLECLR0: CLR_CH12 Mask */
-#define DMA_ENABLECLR0_CLR_CH13_Pos 13 /*!< DMA ENABLECLR0: CLR_CH13 Position */
-#define DMA_ENABLECLR0_CLR_CH13_Msk (0x01UL << DMA_ENABLECLR0_CLR_CH13_Pos) /*!< DMA ENABLECLR0: CLR_CH13 Mask */
-#define DMA_ENABLECLR0_CLR_CH14_Pos 14 /*!< DMA ENABLECLR0: CLR_CH14 Position */
-#define DMA_ENABLECLR0_CLR_CH14_Msk (0x01UL << DMA_ENABLECLR0_CLR_CH14_Pos) /*!< DMA ENABLECLR0: CLR_CH14 Mask */
-#define DMA_ENABLECLR0_CLR_CH15_Pos 15 /*!< DMA ENABLECLR0: CLR_CH15 Position */
-#define DMA_ENABLECLR0_CLR_CH15_Msk (0x01UL << DMA_ENABLECLR0_CLR_CH15_Pos) /*!< DMA ENABLECLR0: CLR_CH15 Mask */
-#define DMA_ENABLECLR0_CLR_CH16_Pos 16 /*!< DMA ENABLECLR0: CLR_CH16 Position */
-#define DMA_ENABLECLR0_CLR_CH16_Msk (0x01UL << DMA_ENABLECLR0_CLR_CH16_Pos) /*!< DMA ENABLECLR0: CLR_CH16 Mask */
-#define DMA_ENABLECLR0_CLR_CH17_Pos 17 /*!< DMA ENABLECLR0: CLR_CH17 Position */
-#define DMA_ENABLECLR0_CLR_CH17_Msk (0x01UL << DMA_ENABLECLR0_CLR_CH17_Pos) /*!< DMA ENABLECLR0: CLR_CH17 Mask */
-#define DMA_ENABLECLR0_CLR_CH18_Pos 18 /*!< DMA ENABLECLR0: CLR_CH18 Position */
-#define DMA_ENABLECLR0_CLR_CH18_Msk (0x01UL << DMA_ENABLECLR0_CLR_CH18_Pos) /*!< DMA ENABLECLR0: CLR_CH18 Mask */
-
-/* -------------------------------- u_dma_ACTIVE0 ------------------------------- */
-#define DMA_ACTIVE0_ACT_CH0_Pos 0 /*!< DMA ACTIVE0: ACT_CH0 Position */
-#define DMA_ACTIVE0_ACT_CH0_Msk (0x01UL << DMA_ACTIVE0_ACT_CH0_Pos) /*!< DMA ACTIVE0: ACT_CH0 Mask */
-#define DMA_ACTIVE0_ACT_CH1_Pos 1 /*!< DMA ACTIVE0: ACT_CH1 Position */
-#define DMA_ACTIVE0_ACT_CH1_Msk (0x01UL << DMA_ACTIVE0_ACT_CH1_Pos) /*!< DMA ACTIVE0: ACT_CH1 Mask */
-#define DMA_ACTIVE0_ACT_CH2_Pos 2 /*!< DMA ACTIVE0: ACT_CH2 Position */
-#define DMA_ACTIVE0_ACT_CH2_Msk (0x01UL << DMA_ACTIVE0_ACT_CH2_Pos) /*!< DMA ACTIVE0: ACT_CH2 Mask */
-#define DMA_ACTIVE0_ACT_CH3_Pos 3 /*!< DMA ACTIVE0: ACT_CH3 Position */
-#define DMA_ACTIVE0_ACT_CH3_Msk (0x01UL << DMA_ACTIVE0_ACT_CH3_Pos) /*!< DMA ACTIVE0: ACT_CH3 Mask */
-#define DMA_ACTIVE0_ACT_CH4_Pos 4 /*!< DMA ACTIVE0: ACT_CH4 Position */
-#define DMA_ACTIVE0_ACT_CH4_Msk (0x01UL << DMA_ACTIVE0_ACT_CH4_Pos) /*!< DMA ACTIVE0: ACT_CH4 Mask */
-#define DMA_ACTIVE0_ACT_CH5_Pos 5 /*!< DMA ACTIVE0: ACT_CH5 Position */
-#define DMA_ACTIVE0_ACT_CH5_Msk (0x01UL << DMA_ACTIVE0_ACT_CH5_Pos) /*!< DMA ACTIVE0: ACT_CH5 Mask */
-#define DMA_ACTIVE0_ACT_CH6_Pos 6 /*!< DMA ACTIVE0: ACT_CH6 Position */
-#define DMA_ACTIVE0_ACT_CH6_Msk (0x01UL << DMA_ACTIVE0_ACT_CH6_Pos) /*!< DMA ACTIVE0: ACT_CH6 Mask */
-#define DMA_ACTIVE0_ACT_CH7_Pos 7 /*!< DMA ACTIVE0: ACT_CH7 Position */
-#define DMA_ACTIVE0_ACT_CH7_Msk (0x01UL << DMA_ACTIVE0_ACT_CH7_Pos) /*!< DMA ACTIVE0: ACT_CH7 Mask */
-#define DMA_ACTIVE0_ACT_CH8_Pos 8 /*!< DMA ACTIVE0: ACT_CH8 Position */
-#define DMA_ACTIVE0_ACT_CH8_Msk (0x01UL << DMA_ACTIVE0_ACT_CH8_Pos) /*!< DMA ACTIVE0: ACT_CH8 Mask */
-#define DMA_ACTIVE0_ACT_CH9_Pos 9 /*!< DMA ACTIVE0: ACT_CH9 Position */
-#define DMA_ACTIVE0_ACT_CH9_Msk (0x01UL << DMA_ACTIVE0_ACT_CH9_Pos) /*!< DMA ACTIVE0: ACT_CH9 Mask */
-#define DMA_ACTIVE0_ACT_CH10_Pos 10 /*!< DMA ACTIVE0: ACT_CH10 Position */
-#define DMA_ACTIVE0_ACT_CH10_Msk (0x01UL << DMA_ACTIVE0_ACT_CH10_Pos) /*!< DMA ACTIVE0: ACT_CH10 Mask */
-#define DMA_ACTIVE0_ACT_CH11_Pos 11 /*!< DMA ACTIVE0: ACT_CH11 Position */
-#define DMA_ACTIVE0_ACT_CH11_Msk (0x01UL << DMA_ACTIVE0_ACT_CH11_Pos) /*!< DMA ACTIVE0: ACT_CH11 Mask */
-#define DMA_ACTIVE0_ACT_CH12_Pos 12 /*!< DMA ACTIVE0: ACT_CH12 Position */
-#define DMA_ACTIVE0_ACT_CH12_Msk (0x01UL << DMA_ACTIVE0_ACT_CH12_Pos) /*!< DMA ACTIVE0: ACT_CH12 Mask */
-#define DMA_ACTIVE0_ACT_CH13_Pos 13 /*!< DMA ACTIVE0: ACT_CH13 Position */
-#define DMA_ACTIVE0_ACT_CH13_Msk (0x01UL << DMA_ACTIVE0_ACT_CH13_Pos) /*!< DMA ACTIVE0: ACT_CH13 Mask */
-#define DMA_ACTIVE0_ACT_CH14_Pos 14 /*!< DMA ACTIVE0: ACT_CH14 Position */
-#define DMA_ACTIVE0_ACT_CH14_Msk (0x01UL << DMA_ACTIVE0_ACT_CH14_Pos) /*!< DMA ACTIVE0: ACT_CH14 Mask */
-#define DMA_ACTIVE0_ACT_CH15_Pos 15 /*!< DMA ACTIVE0: ACT_CH15 Position */
-#define DMA_ACTIVE0_ACT_CH15_Msk (0x01UL << DMA_ACTIVE0_ACT_CH15_Pos) /*!< DMA ACTIVE0: ACT_CH15 Mask */
-#define DMA_ACTIVE0_ACT_CH16_Pos 16 /*!< DMA ACTIVE0: ACT_CH16 Position */
-#define DMA_ACTIVE0_ACT_CH16_Msk (0x01UL << DMA_ACTIVE0_ACT_CH16_Pos) /*!< DMA ACTIVE0: ACT_CH16 Mask */
-#define DMA_ACTIVE0_ACT_CH17_Pos 17 /*!< DMA ACTIVE0: ACT_CH17 Position */
-#define DMA_ACTIVE0_ACT_CH17_Msk (0x01UL << DMA_ACTIVE0_ACT_CH17_Pos) /*!< DMA ACTIVE0: ACT_CH17 Mask */
-#define DMA_ACTIVE0_ACT_CH18_Pos 18 /*!< DMA ACTIVE0: ACT_CH18 Position */
-#define DMA_ACTIVE0_ACT_CH18_Msk (0x01UL << DMA_ACTIVE0_ACT_CH18_Pos) /*!< DMA ACTIVE0: ACT_CH18 Mask */
-
-/* --------------------------------- u_dma_BUSY0 -------------------------------- */
-#define DMA_BUSY0_BSY_CH0_Pos 0 /*!< DMA BUSY0: BSY_CH0 Position */
-#define DMA_BUSY0_BSY_CH0_Msk (0x01UL << DMA_BUSY0_BSY_CH0_Pos) /*!< DMA BUSY0: BSY_CH0 Mask */
-#define DMA_BUSY0_BSY_CH1_Pos 1 /*!< DMA BUSY0: BSY_CH1 Position */
-#define DMA_BUSY0_BSY_CH1_Msk (0x01UL << DMA_BUSY0_BSY_CH1_Pos) /*!< DMA BUSY0: BSY_CH1 Mask */
-#define DMA_BUSY0_BSY_CH2_Pos 2 /*!< DMA BUSY0: BSY_CH2 Position */
-#define DMA_BUSY0_BSY_CH2_Msk (0x01UL << DMA_BUSY0_BSY_CH2_Pos) /*!< DMA BUSY0: BSY_CH2 Mask */
-#define DMA_BUSY0_BSY_CH3_Pos 3 /*!< DMA BUSY0: BSY_CH3 Position */
-#define DMA_BUSY0_BSY_CH3_Msk (0x01UL << DMA_BUSY0_BSY_CH3_Pos) /*!< DMA BUSY0: BSY_CH3 Mask */
-#define DMA_BUSY0_BSY_CH4_Pos 4 /*!< DMA BUSY0: BSY_CH4 Position */
-#define DMA_BUSY0_BSY_CH4_Msk (0x01UL << DMA_BUSY0_BSY_CH4_Pos) /*!< DMA BUSY0: BSY_CH4 Mask */
-#define DMA_BUSY0_BSY_CH5_Pos 5 /*!< DMA BUSY0: BSY_CH5 Position */
-#define DMA_BUSY0_BSY_CH5_Msk (0x01UL << DMA_BUSY0_BSY_CH5_Pos) /*!< DMA BUSY0: BSY_CH5 Mask */
-#define DMA_BUSY0_BSY_CH6_Pos 6 /*!< DMA BUSY0: BSY_CH6 Position */
-#define DMA_BUSY0_BSY_CH6_Msk (0x01UL << DMA_BUSY0_BSY_CH6_Pos) /*!< DMA BUSY0: BSY_CH6 Mask */
-#define DMA_BUSY0_BSY_CH7_Pos 7 /*!< DMA BUSY0: BSY_CH7 Position */
-#define DMA_BUSY0_BSY_CH7_Msk (0x01UL << DMA_BUSY0_BSY_CH7_Pos) /*!< DMA BUSY0: BSY_CH7 Mask */
-#define DMA_BUSY0_BSY_CH8_Pos 8 /*!< DMA BUSY0: BSY_CH8 Position */
-#define DMA_BUSY0_BSY_CH8_Msk (0x01UL << DMA_BUSY0_BSY_CH8_Pos) /*!< DMA BUSY0: BSY_CH8 Mask */
-#define DMA_BUSY0_BSY_CH9_Pos 9 /*!< DMA BUSY0: BSY_CH9 Position */
-#define DMA_BUSY0_BSY_CH9_Msk (0x01UL << DMA_BUSY0_BSY_CH9_Pos) /*!< DMA BUSY0: BSY_CH9 Mask */
-#define DMA_BUSY0_BSY_CH10_Pos 10 /*!< DMA BUSY0: BSY_CH10 Position */
-#define DMA_BUSY0_BSY_CH10_Msk (0x01UL << DMA_BUSY0_BSY_CH10_Pos) /*!< DMA BUSY0: BSY_CH10 Mask */
-#define DMA_BUSY0_BSY_CH11_Pos 11 /*!< DMA BUSY0: BSY_CH11 Position */
-#define DMA_BUSY0_BSY_CH11_Msk (0x01UL << DMA_BUSY0_BSY_CH11_Pos) /*!< DMA BUSY0: BSY_CH11 Mask */
-#define DMA_BUSY0_BSY_CH12_Pos 12 /*!< DMA BUSY0: BSY_CH12 Position */
-#define DMA_BUSY0_BSY_CH12_Msk (0x01UL << DMA_BUSY0_BSY_CH12_Pos) /*!< DMA BUSY0: BSY_CH12 Mask */
-#define DMA_BUSY0_BSY_CH13_Pos 13 /*!< DMA BUSY0: BSY_CH13 Position */
-#define DMA_BUSY0_BSY_CH13_Msk (0x01UL << DMA_BUSY0_BSY_CH13_Pos) /*!< DMA BUSY0: BSY_CH13 Mask */
-#define DMA_BUSY0_BSY_CH14_Pos 14 /*!< DMA BUSY0: BSY_CH14 Position */
-#define DMA_BUSY0_BSY_CH14_Msk (0x01UL << DMA_BUSY0_BSY_CH14_Pos) /*!< DMA BUSY0: BSY_CH14 Mask */
-#define DMA_BUSY0_BSY_CH15_Pos 15 /*!< DMA BUSY0: BSY_CH15 Position */
-#define DMA_BUSY0_BSY_CH15_Msk (0x01UL << DMA_BUSY0_BSY_CH15_Pos) /*!< DMA BUSY0: BSY_CH15 Mask */
-#define DMA_BUSY0_BSY_CH16_Pos 16 /*!< DMA BUSY0: BSY_CH16 Position */
-#define DMA_BUSY0_BSY_CH16_Msk (0x01UL << DMA_BUSY0_BSY_CH16_Pos) /*!< DMA BUSY0: BSY_CH16 Mask */
-#define DMA_BUSY0_BSY_CH17_Pos 17 /*!< DMA BUSY0: BSY_CH17 Position */
-#define DMA_BUSY0_BSY_CH17_Msk (0x01UL << DMA_BUSY0_BSY_CH17_Pos) /*!< DMA BUSY0: BSY_CH17 Mask */
-#define DMA_BUSY0_BSY_CH18_Pos 18 /*!< DMA BUSY0: BSY_CH18 Position */
-#define DMA_BUSY0_BSY_CH18_Msk (0x01UL << DMA_BUSY0_BSY_CH18_Pos) /*!< DMA BUSY0: BSY_CH18 Mask */
-
-/* -------------------------------- u_dma_ERRINT0 ------------------------------- */
-#define DMA_ERRINT0_ERR_CH0_Pos 0 /*!< DMA ERRINT0: ERR_CH0 Position */
-#define DMA_ERRINT0_ERR_CH0_Msk (0x01UL << DMA_ERRINT0_ERR_CH0_Pos) /*!< DMA ERRINT0: ERR_CH0 Mask */
-#define DMA_ERRINT0_ERR_CH1_Pos 1 /*!< DMA ERRINT0: ERR_CH1 Position */
-#define DMA_ERRINT0_ERR_CH1_Msk (0x01UL << DMA_ERRINT0_ERR_CH1_Pos) /*!< DMA ERRINT0: ERR_CH1 Mask */
-#define DMA_ERRINT0_ERR_CH2_Pos 2 /*!< DMA ERRINT0: ERR_CH2 Position */
-#define DMA_ERRINT0_ERR_CH2_Msk (0x01UL << DMA_ERRINT0_ERR_CH2_Pos) /*!< DMA ERRINT0: ERR_CH2 Mask */
-#define DMA_ERRINT0_ERR_CH3_Pos 3 /*!< DMA ERRINT0: ERR_CH3 Position */
-#define DMA_ERRINT0_ERR_CH3_Msk (0x01UL << DMA_ERRINT0_ERR_CH3_Pos) /*!< DMA ERRINT0: ERR_CH3 Mask */
-#define DMA_ERRINT0_ERR_CH4_Pos 4 /*!< DMA ERRINT0: ERR_CH4 Position */
-#define DMA_ERRINT0_ERR_CH4_Msk (0x01UL << DMA_ERRINT0_ERR_CH4_Pos) /*!< DMA ERRINT0: ERR_CH4 Mask */
-#define DMA_ERRINT0_ERR_CH5_Pos 5 /*!< DMA ERRINT0: ERR_CH5 Position */
-#define DMA_ERRINT0_ERR_CH5_Msk (0x01UL << DMA_ERRINT0_ERR_CH5_Pos) /*!< DMA ERRINT0: ERR_CH5 Mask */
-#define DMA_ERRINT0_ERR_CH6_Pos 6 /*!< DMA ERRINT0: ERR_CH6 Position */
-#define DMA_ERRINT0_ERR_CH6_Msk (0x01UL << DMA_ERRINT0_ERR_CH6_Pos) /*!< DMA ERRINT0: ERR_CH6 Mask */
-#define DMA_ERRINT0_ERR_CH7_Pos 7 /*!< DMA ERRINT0: ERR_CH7 Position */
-#define DMA_ERRINT0_ERR_CH7_Msk (0x01UL << DMA_ERRINT0_ERR_CH7_Pos) /*!< DMA ERRINT0: ERR_CH7 Mask */
-#define DMA_ERRINT0_ERR_CH8_Pos 8 /*!< DMA ERRINT0: ERR_CH8 Position */
-#define DMA_ERRINT0_ERR_CH8_Msk (0x01UL << DMA_ERRINT0_ERR_CH8_Pos) /*!< DMA ERRINT0: ERR_CH8 Mask */
-#define DMA_ERRINT0_ERR_CH9_Pos 9 /*!< DMA ERRINT0: ERR_CH9 Position */
-#define DMA_ERRINT0_ERR_CH9_Msk (0x01UL << DMA_ERRINT0_ERR_CH9_Pos) /*!< DMA ERRINT0: ERR_CH9 Mask */
-#define DMA_ERRINT0_ERR_CH10_Pos 10 /*!< DMA ERRINT0: ERR_CH10 Position */
-#define DMA_ERRINT0_ERR_CH10_Msk (0x01UL << DMA_ERRINT0_ERR_CH10_Pos) /*!< DMA ERRINT0: ERR_CH10 Mask */
-#define DMA_ERRINT0_ERR_CH11_Pos 11 /*!< DMA ERRINT0: ERR_CH11 Position */
-#define DMA_ERRINT0_ERR_CH11_Msk (0x01UL << DMA_ERRINT0_ERR_CH11_Pos) /*!< DMA ERRINT0: ERR_CH11 Mask */
-#define DMA_ERRINT0_ERR_CH12_Pos 12 /*!< DMA ERRINT0: ERR_CH12 Position */
-#define DMA_ERRINT0_ERR_CH12_Msk (0x01UL << DMA_ERRINT0_ERR_CH12_Pos) /*!< DMA ERRINT0: ERR_CH12 Mask */
-#define DMA_ERRINT0_ERR_CH13_Pos 13 /*!< DMA ERRINT0: ERR_CH13 Position */
-#define DMA_ERRINT0_ERR_CH13_Msk (0x01UL << DMA_ERRINT0_ERR_CH13_Pos) /*!< DMA ERRINT0: ERR_CH13 Mask */
-#define DMA_ERRINT0_ERR_CH14_Pos 14 /*!< DMA ERRINT0: ERR_CH14 Position */
-#define DMA_ERRINT0_ERR_CH14_Msk (0x01UL << DMA_ERRINT0_ERR_CH14_Pos) /*!< DMA ERRINT0: ERR_CH14 Mask */
-#define DMA_ERRINT0_ERR_CH15_Pos 15 /*!< DMA ERRINT0: ERR_CH15 Position */
-#define DMA_ERRINT0_ERR_CH15_Msk (0x01UL << DMA_ERRINT0_ERR_CH15_Pos) /*!< DMA ERRINT0: ERR_CH15 Mask */
-#define DMA_ERRINT0_ERR_CH16_Pos 16 /*!< DMA ERRINT0: ERR_CH16 Position */
-#define DMA_ERRINT0_ERR_CH16_Msk (0x01UL << DMA_ERRINT0_ERR_CH16_Pos) /*!< DMA ERRINT0: ERR_CH16 Mask */
-#define DMA_ERRINT0_ERR_CH17_Pos 17 /*!< DMA ERRINT0: ERR_CH17 Position */
-#define DMA_ERRINT0_ERR_CH17_Msk (0x01UL << DMA_ERRINT0_ERR_CH17_Pos) /*!< DMA ERRINT0: ERR_CH17 Mask */
-#define DMA_ERRINT0_ERR_CH18_Pos 18 /*!< DMA ERRINT0: ERR_CH18 Position */
-#define DMA_ERRINT0_ERR_CH18_Msk (0x01UL << DMA_ERRINT0_ERR_CH18_Pos) /*!< DMA ERRINT0: ERR_CH18 Mask */
-
-/* ------------------------------- u_dma_INTENSET0 ------------------------------ */
-#define DMA_INTENSET0_INTEN_CH0_Pos 0 /*!< DMA INTENSET0: INTEN_CH0 Position */
-#define DMA_INTENSET0_INTEN_CH0_Msk (0x01UL << DMA_INTENSET0_INTEN_CH0_Pos) /*!< DMA INTENSET0: INTEN_CH0 Mask */
-#define DMA_INTENSET0_INTEN_CH1_Pos 1 /*!< DMA INTENSET0: INTEN_CH1 Position */
-#define DMA_INTENSET0_INTEN_CH1_Msk (0x01UL << DMA_INTENSET0_INTEN_CH1_Pos) /*!< DMA INTENSET0: INTEN_CH1 Mask */
-#define DMA_INTENSET0_INTEN_CH2_Pos 2 /*!< DMA INTENSET0: INTEN_CH2 Position */
-#define DMA_INTENSET0_INTEN_CH2_Msk (0x01UL << DMA_INTENSET0_INTEN_CH2_Pos) /*!< DMA INTENSET0: INTEN_CH2 Mask */
-#define DMA_INTENSET0_INTEN_CH3_Pos 3 /*!< DMA INTENSET0: INTEN_CH3 Position */
-#define DMA_INTENSET0_INTEN_CH3_Msk (0x01UL << DMA_INTENSET0_INTEN_CH3_Pos) /*!< DMA INTENSET0: INTEN_CH3 Mask */
-#define DMA_INTENSET0_INTEN_CH4_Pos 4 /*!< DMA INTENSET0: INTEN_CH4 Position */
-#define DMA_INTENSET0_INTEN_CH4_Msk (0x01UL << DMA_INTENSET0_INTEN_CH4_Pos) /*!< DMA INTENSET0: INTEN_CH4 Mask */
-#define DMA_INTENSET0_INTEN_CH5_Pos 5 /*!< DMA INTENSET0: INTEN_CH5 Position */
-#define DMA_INTENSET0_INTEN_CH5_Msk (0x01UL << DMA_INTENSET0_INTEN_CH5_Pos) /*!< DMA INTENSET0: INTEN_CH5 Mask */
-#define DMA_INTENSET0_INTEN_CH6_Pos 6 /*!< DMA INTENSET0: INTEN_CH6 Position */
-#define DMA_INTENSET0_INTEN_CH6_Msk (0x01UL << DMA_INTENSET0_INTEN_CH6_Pos) /*!< DMA INTENSET0: INTEN_CH6 Mask */
-#define DMA_INTENSET0_INTEN_CH7_Pos 7 /*!< DMA INTENSET0: INTEN_CH7 Position */
-#define DMA_INTENSET0_INTEN_CH7_Msk (0x01UL << DMA_INTENSET0_INTEN_CH7_Pos) /*!< DMA INTENSET0: INTEN_CH7 Mask */
-#define DMA_INTENSET0_INTEN_CH8_Pos 8 /*!< DMA INTENSET0: INTEN_CH8 Position */
-#define DMA_INTENSET0_INTEN_CH8_Msk (0x01UL << DMA_INTENSET0_INTEN_CH8_Pos) /*!< DMA INTENSET0: INTEN_CH8 Mask */
-#define DMA_INTENSET0_INTEN_CH9_Pos 9 /*!< DMA INTENSET0: INTEN_CH9 Position */
-#define DMA_INTENSET0_INTEN_CH9_Msk (0x01UL << DMA_INTENSET0_INTEN_CH9_Pos) /*!< DMA INTENSET0: INTEN_CH9 Mask */
-#define DMA_INTENSET0_INTEN_CH10_Pos 10 /*!< DMA INTENSET0: INTEN_CH10 Position */
-#define DMA_INTENSET0_INTEN_CH10_Msk (0x01UL << DMA_INTENSET0_INTEN_CH10_Pos) /*!< DMA INTENSET0: INTEN_CH10 Mask */
-#define DMA_INTENSET0_INTEN_CH11_Pos 11 /*!< DMA INTENSET0: INTEN_CH11 Position */
-#define DMA_INTENSET0_INTEN_CH11_Msk (0x01UL << DMA_INTENSET0_INTEN_CH11_Pos) /*!< DMA INTENSET0: INTEN_CH11 Mask */
-#define DMA_INTENSET0_INTEN_CH12_Pos 12 /*!< DMA INTENSET0: INTEN_CH12 Position */
-#define DMA_INTENSET0_INTEN_CH12_Msk (0x01UL << DMA_INTENSET0_INTEN_CH12_Pos) /*!< DMA INTENSET0: INTEN_CH12 Mask */
-#define DMA_INTENSET0_INTEN_CH13_Pos 13 /*!< DMA INTENSET0: INTEN_CH13 Position */
-#define DMA_INTENSET0_INTEN_CH13_Msk (0x01UL << DMA_INTENSET0_INTEN_CH13_Pos) /*!< DMA INTENSET0: INTEN_CH13 Mask */
-#define DMA_INTENSET0_INTEN_CH14_Pos 14 /*!< DMA INTENSET0: INTEN_CH14 Position */
-#define DMA_INTENSET0_INTEN_CH14_Msk (0x01UL << DMA_INTENSET0_INTEN_CH14_Pos) /*!< DMA INTENSET0: INTEN_CH14 Mask */
-#define DMA_INTENSET0_INTEN_CH15_Pos 15 /*!< DMA INTENSET0: INTEN_CH15 Position */
-#define DMA_INTENSET0_INTEN_CH15_Msk (0x01UL << DMA_INTENSET0_INTEN_CH15_Pos) /*!< DMA INTENSET0: INTEN_CH15 Mask */
-#define DMA_INTENSET0_INTEN_CH16_Pos 16 /*!< DMA INTENSET0: INTEN_CH16 Position */
-#define DMA_INTENSET0_INTEN_CH16_Msk (0x01UL << DMA_INTENSET0_INTEN_CH16_Pos) /*!< DMA INTENSET0: INTEN_CH16 Mask */
-#define DMA_INTENSET0_INTEN_CH17_Pos 17 /*!< DMA INTENSET0: INTEN_CH17 Position */
-#define DMA_INTENSET0_INTEN_CH17_Msk (0x01UL << DMA_INTENSET0_INTEN_CH17_Pos) /*!< DMA INTENSET0: INTEN_CH17 Mask */
-#define DMA_INTENSET0_INTEN_CH18_Pos 18 /*!< DMA INTENSET0: INTEN_CH18 Position */
-#define DMA_INTENSET0_INTEN_CH18_Msk (0x01UL << DMA_INTENSET0_INTEN_CH18_Pos) /*!< DMA INTENSET0: INTEN_CH18 Mask */
-
-/* ------------------------------- u_dma_INTENCLR0 ------------------------------ */
-#define DMA_INTENCLR0_CLR_CH0_Pos 0 /*!< DMA INTENCLR0: CLR_CH0 Position */
-#define DMA_INTENCLR0_CLR_CH0_Msk (0x01UL << DMA_INTENCLR0_CLR_CH0_Pos) /*!< DMA INTENCLR0: CLR_CH0 Mask */
-#define DMA_INTENCLR0_CLR_CH1_Pos 1 /*!< DMA INTENCLR0: CLR_CH1 Position */
-#define DMA_INTENCLR0_CLR_CH1_Msk (0x01UL << DMA_INTENCLR0_CLR_CH1_Pos) /*!< DMA INTENCLR0: CLR_CH1 Mask */
-#define DMA_INTENCLR0_CLR_CH2_Pos 2 /*!< DMA INTENCLR0: CLR_CH2 Position */
-#define DMA_INTENCLR0_CLR_CH2_Msk (0x01UL << DMA_INTENCLR0_CLR_CH2_Pos) /*!< DMA INTENCLR0: CLR_CH2 Mask */
-#define DMA_INTENCLR0_CLR_CH3_Pos 3 /*!< DMA INTENCLR0: CLR_CH3 Position */
-#define DMA_INTENCLR0_CLR_CH3_Msk (0x01UL << DMA_INTENCLR0_CLR_CH3_Pos) /*!< DMA INTENCLR0: CLR_CH3 Mask */
-#define DMA_INTENCLR0_CLR_CH4_Pos 4 /*!< DMA INTENCLR0: CLR_CH4 Position */
-#define DMA_INTENCLR0_CLR_CH4_Msk (0x01UL << DMA_INTENCLR0_CLR_CH4_Pos) /*!< DMA INTENCLR0: CLR_CH4 Mask */
-#define DMA_INTENCLR0_CLR_CH5_Pos 5 /*!< DMA INTENCLR0: CLR_CH5 Position */
-#define DMA_INTENCLR0_CLR_CH5_Msk (0x01UL << DMA_INTENCLR0_CLR_CH5_Pos) /*!< DMA INTENCLR0: CLR_CH5 Mask */
-#define DMA_INTENCLR0_CLR_CH6_Pos 6 /*!< DMA INTENCLR0: CLR_CH6 Position */
-#define DMA_INTENCLR0_CLR_CH6_Msk (0x01UL << DMA_INTENCLR0_CLR_CH6_Pos) /*!< DMA INTENCLR0: CLR_CH6 Mask */
-#define DMA_INTENCLR0_CLR_CH7_Pos 7 /*!< DMA INTENCLR0: CLR_CH7 Position */
-#define DMA_INTENCLR0_CLR_CH7_Msk (0x01UL << DMA_INTENCLR0_CLR_CH7_Pos) /*!< DMA INTENCLR0: CLR_CH7 Mask */
-#define DMA_INTENCLR0_CLR_CH8_Pos 8 /*!< DMA INTENCLR0: CLR_CH8 Position */
-#define DMA_INTENCLR0_CLR_CH8_Msk (0x01UL << DMA_INTENCLR0_CLR_CH8_Pos) /*!< DMA INTENCLR0: CLR_CH8 Mask */
-#define DMA_INTENCLR0_CLR_CH9_Pos 9 /*!< DMA INTENCLR0: CLR_CH9 Position */
-#define DMA_INTENCLR0_CLR_CH9_Msk (0x01UL << DMA_INTENCLR0_CLR_CH9_Pos) /*!< DMA INTENCLR0: CLR_CH9 Mask */
-#define DMA_INTENCLR0_CLR_CH10_Pos 10 /*!< DMA INTENCLR0: CLR_CH10 Position */
-#define DMA_INTENCLR0_CLR_CH10_Msk (0x01UL << DMA_INTENCLR0_CLR_CH10_Pos) /*!< DMA INTENCLR0: CLR_CH10 Mask */
-#define DMA_INTENCLR0_CLR_CH11_Pos 11 /*!< DMA INTENCLR0: CLR_CH11 Position */
-#define DMA_INTENCLR0_CLR_CH11_Msk (0x01UL << DMA_INTENCLR0_CLR_CH11_Pos) /*!< DMA INTENCLR0: CLR_CH11 Mask */
-#define DMA_INTENCLR0_CLR_CH12_Pos 12 /*!< DMA INTENCLR0: CLR_CH12 Position */
-#define DMA_INTENCLR0_CLR_CH12_Msk (0x01UL << DMA_INTENCLR0_CLR_CH12_Pos) /*!< DMA INTENCLR0: CLR_CH12 Mask */
-#define DMA_INTENCLR0_CLR_CH13_Pos 13 /*!< DMA INTENCLR0: CLR_CH13 Position */
-#define DMA_INTENCLR0_CLR_CH13_Msk (0x01UL << DMA_INTENCLR0_CLR_CH13_Pos) /*!< DMA INTENCLR0: CLR_CH13 Mask */
-#define DMA_INTENCLR0_CLR_CH14_Pos 14 /*!< DMA INTENCLR0: CLR_CH14 Position */
-#define DMA_INTENCLR0_CLR_CH14_Msk (0x01UL << DMA_INTENCLR0_CLR_CH14_Pos) /*!< DMA INTENCLR0: CLR_CH14 Mask */
-#define DMA_INTENCLR0_CLR_CH15_Pos 15 /*!< DMA INTENCLR0: CLR_CH15 Position */
-#define DMA_INTENCLR0_CLR_CH15_Msk (0x01UL << DMA_INTENCLR0_CLR_CH15_Pos) /*!< DMA INTENCLR0: CLR_CH15 Mask */
-#define DMA_INTENCLR0_CLR_CH16_Pos 16 /*!< DMA INTENCLR0: CLR_CH16 Position */
-#define DMA_INTENCLR0_CLR_CH16_Msk (0x01UL << DMA_INTENCLR0_CLR_CH16_Pos) /*!< DMA INTENCLR0: CLR_CH16 Mask */
-#define DMA_INTENCLR0_CLR_CH17_Pos 17 /*!< DMA INTENCLR0: CLR_CH17 Position */
-#define DMA_INTENCLR0_CLR_CH17_Msk (0x01UL << DMA_INTENCLR0_CLR_CH17_Pos) /*!< DMA INTENCLR0: CLR_CH17 Mask */
-#define DMA_INTENCLR0_CLR_CH18_Pos 18 /*!< DMA INTENCLR0: CLR_CH18 Position */
-#define DMA_INTENCLR0_CLR_CH18_Msk (0x01UL << DMA_INTENCLR0_CLR_CH18_Pos) /*!< DMA INTENCLR0: CLR_CH18 Mask */
-
-/* --------------------------------- u_dma_INTA0 -------------------------------- */
-#define DMA_INTA0_IA_CH0_Pos 0 /*!< DMA INTA0: IA_CH0 Position */
-#define DMA_INTA0_IA_CH0_Msk (0x01UL << DMA_INTA0_IA_CH0_Pos) /*!< DMA INTA0: IA_CH0 Mask */
-#define DMA_INTA0_IA_CH1_Pos 1 /*!< DMA INTA0: IA_CH1 Position */
-#define DMA_INTA0_IA_CH1_Msk (0x01UL << DMA_INTA0_IA_CH1_Pos) /*!< DMA INTA0: IA_CH1 Mask */
-#define DMA_INTA0_IA_CH2_Pos 2 /*!< DMA INTA0: IA_CH2 Position */
-#define DMA_INTA0_IA_CH2_Msk (0x01UL << DMA_INTA0_IA_CH2_Pos) /*!< DMA INTA0: IA_CH2 Mask */
-#define DMA_INTA0_IA_CH3_Pos 3 /*!< DMA INTA0: IA_CH3 Position */
-#define DMA_INTA0_IA_CH3_Msk (0x01UL << DMA_INTA0_IA_CH3_Pos) /*!< DMA INTA0: IA_CH3 Mask */
-#define DMA_INTA0_IA_CH4_Pos 4 /*!< DMA INTA0: IA_CH4 Position */
-#define DMA_INTA0_IA_CH4_Msk (0x01UL << DMA_INTA0_IA_CH4_Pos) /*!< DMA INTA0: IA_CH4 Mask */
-#define DMA_INTA0_IA_CH5_Pos 5 /*!< DMA INTA0: IA_CH5 Position */
-#define DMA_INTA0_IA_CH5_Msk (0x01UL << DMA_INTA0_IA_CH5_Pos) /*!< DMA INTA0: IA_CH5 Mask */
-#define DMA_INTA0_IA_CH6_Pos 6 /*!< DMA INTA0: IA_CH6 Position */
-#define DMA_INTA0_IA_CH6_Msk (0x01UL << DMA_INTA0_IA_CH6_Pos) /*!< DMA INTA0: IA_CH6 Mask */
-#define DMA_INTA0_IA_CH7_Pos 7 /*!< DMA INTA0: IA_CH7 Position */
-#define DMA_INTA0_IA_CH7_Msk (0x01UL << DMA_INTA0_IA_CH7_Pos) /*!< DMA INTA0: IA_CH7 Mask */
-#define DMA_INTA0_IA_CH8_Pos 8 /*!< DMA INTA0: IA_CH8 Position */
-#define DMA_INTA0_IA_CH8_Msk (0x01UL << DMA_INTA0_IA_CH8_Pos) /*!< DMA INTA0: IA_CH8 Mask */
-#define DMA_INTA0_IA_CH9_Pos 9 /*!< DMA INTA0: IA_CH9 Position */
-#define DMA_INTA0_IA_CH9_Msk (0x01UL << DMA_INTA0_IA_CH9_Pos) /*!< DMA INTA0: IA_CH9 Mask */
-#define DMA_INTA0_IA_CH10_Pos 10 /*!< DMA INTA0: IA_CH10 Position */
-#define DMA_INTA0_IA_CH10_Msk (0x01UL << DMA_INTA0_IA_CH10_Pos) /*!< DMA INTA0: IA_CH10 Mask */
-#define DMA_INTA0_IA_CH11_Pos 11 /*!< DMA INTA0: IA_CH11 Position */
-#define DMA_INTA0_IA_CH11_Msk (0x01UL << DMA_INTA0_IA_CH11_Pos) /*!< DMA INTA0: IA_CH11 Mask */
-#define DMA_INTA0_IA_CH12_Pos 12 /*!< DMA INTA0: IA_CH12 Position */
-#define DMA_INTA0_IA_CH12_Msk (0x01UL << DMA_INTA0_IA_CH12_Pos) /*!< DMA INTA0: IA_CH12 Mask */
-#define DMA_INTA0_IA_CH13_Pos 13 /*!< DMA INTA0: IA_CH13 Position */
-#define DMA_INTA0_IA_CH13_Msk (0x01UL << DMA_INTA0_IA_CH13_Pos) /*!< DMA INTA0: IA_CH13 Mask */
-#define DMA_INTA0_IA_CH14_Pos 14 /*!< DMA INTA0: IA_CH14 Position */
-#define DMA_INTA0_IA_CH14_Msk (0x01UL << DMA_INTA0_IA_CH14_Pos) /*!< DMA INTA0: IA_CH14 Mask */
-#define DMA_INTA0_IA_CH15_Pos 15 /*!< DMA INTA0: IA_CH15 Position */
-#define DMA_INTA0_IA_CH15_Msk (0x01UL << DMA_INTA0_IA_CH15_Pos) /*!< DMA INTA0: IA_CH15 Mask */
-#define DMA_INTA0_IA_CH16_Pos 16 /*!< DMA INTA0: IA_CH16 Position */
-#define DMA_INTA0_IA_CH16_Msk (0x01UL << DMA_INTA0_IA_CH16_Pos) /*!< DMA INTA0: IA_CH16 Mask */
-#define DMA_INTA0_IA_CH17_Pos 17 /*!< DMA INTA0: IA_CH17 Position */
-#define DMA_INTA0_IA_CH17_Msk (0x01UL << DMA_INTA0_IA_CH17_Pos) /*!< DMA INTA0: IA_CH17 Mask */
-#define DMA_INTA0_IA_CH18_Pos 18 /*!< DMA INTA0: IA_CH18 Position */
-#define DMA_INTA0_IA_CH18_Msk (0x01UL << DMA_INTA0_IA_CH18_Pos) /*!< DMA INTA0: IA_CH18 Mask */
-
-/* --------------------------------- u_dma_INTB0 -------------------------------- */
-#define DMA_INTB0_IB_CH0_Pos 0 /*!< DMA INTB0: IB_CH0 Position */
-#define DMA_INTB0_IB_CH0_Msk (0x01UL << DMA_INTB0_IB_CH0_Pos) /*!< DMA INTB0: IB_CH0 Mask */
-#define DMA_INTB0_IB_CH1_Pos 1 /*!< DMA INTB0: IB_CH1 Position */
-#define DMA_INTB0_IB_CH1_Msk (0x01UL << DMA_INTB0_IB_CH1_Pos) /*!< DMA INTB0: IB_CH1 Mask */
-#define DMA_INTB0_IB_CH2_Pos 2 /*!< DMA INTB0: IB_CH2 Position */
-#define DMA_INTB0_IB_CH2_Msk (0x01UL << DMA_INTB0_IB_CH2_Pos) /*!< DMA INTB0: IB_CH2 Mask */
-#define DMA_INTB0_IB_CH3_Pos 3 /*!< DMA INTB0: IB_CH3 Position */
-#define DMA_INTB0_IB_CH3_Msk (0x01UL << DMA_INTB0_IB_CH3_Pos) /*!< DMA INTB0: IB_CH3 Mask */
-#define DMA_INTB0_IB_CH4_Pos 4 /*!< DMA INTB0: IB_CH4 Position */
-#define DMA_INTB0_IB_CH4_Msk (0x01UL << DMA_INTB0_IB_CH4_Pos) /*!< DMA INTB0: IB_CH4 Mask */
-#define DMA_INTB0_IB_CH5_Pos 5 /*!< DMA INTB0: IB_CH5 Position */
-#define DMA_INTB0_IB_CH5_Msk (0x01UL << DMA_INTB0_IB_CH5_Pos) /*!< DMA INTB0: IB_CH5 Mask */
-#define DMA_INTB0_IB_CH6_Pos 6 /*!< DMA INTB0: IB_CH6 Position */
-#define DMA_INTB0_IB_CH6_Msk (0x01UL << DMA_INTB0_IB_CH6_Pos) /*!< DMA INTB0: IB_CH6 Mask */
-#define DMA_INTB0_IB_CH7_Pos 7 /*!< DMA INTB0: IB_CH7 Position */
-#define DMA_INTB0_IB_CH7_Msk (0x01UL << DMA_INTB0_IB_CH7_Pos) /*!< DMA INTB0: IB_CH7 Mask */
-#define DMA_INTB0_IB_CH8_Pos 8 /*!< DMA INTB0: IB_CH8 Position */
-#define DMA_INTB0_IB_CH8_Msk (0x01UL << DMA_INTB0_IB_CH8_Pos) /*!< DMA INTB0: IB_CH8 Mask */
-#define DMA_INTB0_IB_CH9_Pos 9 /*!< DMA INTB0: IB_CH9 Position */
-#define DMA_INTB0_IB_CH9_Msk (0x01UL << DMA_INTB0_IB_CH9_Pos) /*!< DMA INTB0: IB_CH9 Mask */
-#define DMA_INTB0_IB_CH10_Pos 10 /*!< DMA INTB0: IB_CH10 Position */
-#define DMA_INTB0_IB_CH10_Msk (0x01UL << DMA_INTB0_IB_CH10_Pos) /*!< DMA INTB0: IB_CH10 Mask */
-#define DMA_INTB0_IB_CH11_Pos 11 /*!< DMA INTB0: IB_CH11 Position */
-#define DMA_INTB0_IB_CH11_Msk (0x01UL << DMA_INTB0_IB_CH11_Pos) /*!< DMA INTB0: IB_CH11 Mask */
-#define DMA_INTB0_IB_CH12_Pos 12 /*!< DMA INTB0: IB_CH12 Position */
-#define DMA_INTB0_IB_CH12_Msk (0x01UL << DMA_INTB0_IB_CH12_Pos) /*!< DMA INTB0: IB_CH12 Mask */
-#define DMA_INTB0_IB_CH13_Pos 13 /*!< DMA INTB0: IB_CH13 Position */
-#define DMA_INTB0_IB_CH13_Msk (0x01UL << DMA_INTB0_IB_CH13_Pos) /*!< DMA INTB0: IB_CH13 Mask */
-#define DMA_INTB0_IB_CH14_Pos 14 /*!< DMA INTB0: IB_CH14 Position */
-#define DMA_INTB0_IB_CH14_Msk (0x01UL << DMA_INTB0_IB_CH14_Pos) /*!< DMA INTB0: IB_CH14 Mask */
-#define DMA_INTB0_IB_CH15_Pos 15 /*!< DMA INTB0: IB_CH15 Position */
-#define DMA_INTB0_IB_CH15_Msk (0x01UL << DMA_INTB0_IB_CH15_Pos) /*!< DMA INTB0: IB_CH15 Mask */
-#define DMA_INTB0_IB_CH16_Pos 16 /*!< DMA INTB0: IB_CH16 Position */
-#define DMA_INTB0_IB_CH16_Msk (0x01UL << DMA_INTB0_IB_CH16_Pos) /*!< DMA INTB0: IB_CH16 Mask */
-#define DMA_INTB0_IB_CH17_Pos 17 /*!< DMA INTB0: IB_CH17 Position */
-#define DMA_INTB0_IB_CH17_Msk (0x01UL << DMA_INTB0_IB_CH17_Pos) /*!< DMA INTB0: IB_CH17 Mask */
-#define DMA_INTB0_IB_CH18_Pos 18 /*!< DMA INTB0: IB_CH18 Position */
-#define DMA_INTB0_IB_CH18_Msk (0x01UL << DMA_INTB0_IB_CH18_Pos) /*!< DMA INTB0: IB_CH18 Mask */
-
-/* ------------------------------- u_dma_SETVALID0 ------------------------------ */
-#define DMA_SETVALID0_SV_CH0_Pos 0 /*!< DMA SETVALID0: SV_CH0 Position */
-#define DMA_SETVALID0_SV_CH0_Msk (0x01UL << DMA_SETVALID0_SV_CH0_Pos) /*!< DMA SETVALID0: SV_CH0 Mask */
-#define DMA_SETVALID0_SV_CH1_Pos 1 /*!< DMA SETVALID0: SV_CH1 Position */
-#define DMA_SETVALID0_SV_CH1_Msk (0x01UL << DMA_SETVALID0_SV_CH1_Pos) /*!< DMA SETVALID0: SV_CH1 Mask */
-#define DMA_SETVALID0_SV_CH2_Pos 2 /*!< DMA SETVALID0: SV_CH2 Position */
-#define DMA_SETVALID0_SV_CH2_Msk (0x01UL << DMA_SETVALID0_SV_CH2_Pos) /*!< DMA SETVALID0: SV_CH2 Mask */
-#define DMA_SETVALID0_SV_CH3_Pos 3 /*!< DMA SETVALID0: SV_CH3 Position */
-#define DMA_SETVALID0_SV_CH3_Msk (0x01UL << DMA_SETVALID0_SV_CH3_Pos) /*!< DMA SETVALID0: SV_CH3 Mask */
-#define DMA_SETVALID0_SV_CH4_Pos 4 /*!< DMA SETVALID0: SV_CH4 Position */
-#define DMA_SETVALID0_SV_CH4_Msk (0x01UL << DMA_SETVALID0_SV_CH4_Pos) /*!< DMA SETVALID0: SV_CH4 Mask */
-#define DMA_SETVALID0_SV_CH5_Pos 5 /*!< DMA SETVALID0: SV_CH5 Position */
-#define DMA_SETVALID0_SV_CH5_Msk (0x01UL << DMA_SETVALID0_SV_CH5_Pos) /*!< DMA SETVALID0: SV_CH5 Mask */
-#define DMA_SETVALID0_SV_CH6_Pos 6 /*!< DMA SETVALID0: SV_CH6 Position */
-#define DMA_SETVALID0_SV_CH6_Msk (0x01UL << DMA_SETVALID0_SV_CH6_Pos) /*!< DMA SETVALID0: SV_CH6 Mask */
-#define DMA_SETVALID0_SV_CH7_Pos 7 /*!< DMA SETVALID0: SV_CH7 Position */
-#define DMA_SETVALID0_SV_CH7_Msk (0x01UL << DMA_SETVALID0_SV_CH7_Pos) /*!< DMA SETVALID0: SV_CH7 Mask */
-#define DMA_SETVALID0_SV_CH8_Pos 8 /*!< DMA SETVALID0: SV_CH8 Position */
-#define DMA_SETVALID0_SV_CH8_Msk (0x01UL << DMA_SETVALID0_SV_CH8_Pos) /*!< DMA SETVALID0: SV_CH8 Mask */
-#define DMA_SETVALID0_SV_CH9_Pos 9 /*!< DMA SETVALID0: SV_CH9 Position */
-#define DMA_SETVALID0_SV_CH9_Msk (0x01UL << DMA_SETVALID0_SV_CH9_Pos) /*!< DMA SETVALID0: SV_CH9 Mask */
-#define DMA_SETVALID0_SV_CH10_Pos 10 /*!< DMA SETVALID0: SV_CH10 Position */
-#define DMA_SETVALID0_SV_CH10_Msk (0x01UL << DMA_SETVALID0_SV_CH10_Pos) /*!< DMA SETVALID0: SV_CH10 Mask */
-#define DMA_SETVALID0_SV_CH11_Pos 11 /*!< DMA SETVALID0: SV_CH11 Position */
-#define DMA_SETVALID0_SV_CH11_Msk (0x01UL << DMA_SETVALID0_SV_CH11_Pos) /*!< DMA SETVALID0: SV_CH11 Mask */
-#define DMA_SETVALID0_SV_CH12_Pos 12 /*!< DMA SETVALID0: SV_CH12 Position */
-#define DMA_SETVALID0_SV_CH12_Msk (0x01UL << DMA_SETVALID0_SV_CH12_Pos) /*!< DMA SETVALID0: SV_CH12 Mask */
-#define DMA_SETVALID0_SV_CH13_Pos 13 /*!< DMA SETVALID0: SV_CH13 Position */
-#define DMA_SETVALID0_SV_CH13_Msk (0x01UL << DMA_SETVALID0_SV_CH13_Pos) /*!< DMA SETVALID0: SV_CH13 Mask */
-#define DMA_SETVALID0_SV_CH14_Pos 14 /*!< DMA SETVALID0: SV_CH14 Position */
-#define DMA_SETVALID0_SV_CH14_Msk (0x01UL << DMA_SETVALID0_SV_CH14_Pos) /*!< DMA SETVALID0: SV_CH14 Mask */
-#define DMA_SETVALID0_SV_CH15_Pos 15 /*!< DMA SETVALID0: SV_CH15 Position */
-#define DMA_SETVALID0_SV_CH15_Msk (0x01UL << DMA_SETVALID0_SV_CH15_Pos) /*!< DMA SETVALID0: SV_CH15 Mask */
-#define DMA_SETVALID0_SV_CH16_Pos 16 /*!< DMA SETVALID0: SV_CH16 Position */
-#define DMA_SETVALID0_SV_CH16_Msk (0x01UL << DMA_SETVALID0_SV_CH16_Pos) /*!< DMA SETVALID0: SV_CH16 Mask */
-#define DMA_SETVALID0_SV_CH17_Pos 17 /*!< DMA SETVALID0: SV_CH17 Position */
-#define DMA_SETVALID0_SV_CH17_Msk (0x01UL << DMA_SETVALID0_SV_CH17_Pos) /*!< DMA SETVALID0: SV_CH17 Mask */
-#define DMA_SETVALID0_SV_CH18_Pos 18 /*!< DMA SETVALID0: SV_CH18 Position */
-#define DMA_SETVALID0_SV_CH18_Msk (0x01UL << DMA_SETVALID0_SV_CH18_Pos) /*!< DMA SETVALID0: SV_CH18 Mask */
-
-/* ------------------------------- u_dma_SETTRIG0 ------------------------------- */
-#define DMA_SETTRIG0_TRIG_CH0_Pos 0 /*!< DMA SETTRIG0: TRIG_CH0 Position */
-#define DMA_SETTRIG0_TRIG_CH0_Msk (0x01UL << DMA_SETTRIG0_TRIG_CH0_Pos) /*!< DMA SETTRIG0: TRIG_CH0 Mask */
-#define DMA_SETTRIG0_TRIG_CH1_Pos 1 /*!< DMA SETTRIG0: TRIG_CH1 Position */
-#define DMA_SETTRIG0_TRIG_CH1_Msk (0x01UL << DMA_SETTRIG0_TRIG_CH1_Pos) /*!< DMA SETTRIG0: TRIG_CH1 Mask */
-#define DMA_SETTRIG0_TRIG_CH2_Pos 2 /*!< DMA SETTRIG0: TRIG_CH2 Position */
-#define DMA_SETTRIG0_TRIG_CH2_Msk (0x01UL << DMA_SETTRIG0_TRIG_CH2_Pos) /*!< DMA SETTRIG0: TRIG_CH2 Mask */
-#define DMA_SETTRIG0_TRIG_CH3_Pos 3 /*!< DMA SETTRIG0: TRIG_CH3 Position */
-#define DMA_SETTRIG0_TRIG_CH3_Msk (0x01UL << DMA_SETTRIG0_TRIG_CH3_Pos) /*!< DMA SETTRIG0: TRIG_CH3 Mask */
-#define DMA_SETTRIG0_TRIG_CH4_Pos 4 /*!< DMA SETTRIG0: TRIG_CH4 Position */
-#define DMA_SETTRIG0_TRIG_CH4_Msk (0x01UL << DMA_SETTRIG0_TRIG_CH4_Pos) /*!< DMA SETTRIG0: TRIG_CH4 Mask */
-#define DMA_SETTRIG0_TRIG_CH5_Pos 5 /*!< DMA SETTRIG0: TRIG_CH5 Position */
-#define DMA_SETTRIG0_TRIG_CH5_Msk (0x01UL << DMA_SETTRIG0_TRIG_CH5_Pos) /*!< DMA SETTRIG0: TRIG_CH5 Mask */
-#define DMA_SETTRIG0_TRIG_CH6_Pos 6 /*!< DMA SETTRIG0: TRIG_CH6 Position */
-#define DMA_SETTRIG0_TRIG_CH6_Msk (0x01UL << DMA_SETTRIG0_TRIG_CH6_Pos) /*!< DMA SETTRIG0: TRIG_CH6 Mask */
-#define DMA_SETTRIG0_TRIG_CH7_Pos 7 /*!< DMA SETTRIG0: TRIG_CH7 Position */
-#define DMA_SETTRIG0_TRIG_CH7_Msk (0x01UL << DMA_SETTRIG0_TRIG_CH7_Pos) /*!< DMA SETTRIG0: TRIG_CH7 Mask */
-#define DMA_SETTRIG0_TRIG_CH8_Pos 8 /*!< DMA SETTRIG0: TRIG_CH8 Position */
-#define DMA_SETTRIG0_TRIG_CH8_Msk (0x01UL << DMA_SETTRIG0_TRIG_CH8_Pos) /*!< DMA SETTRIG0: TRIG_CH8 Mask */
-#define DMA_SETTRIG0_TRIG_CH9_Pos 9 /*!< DMA SETTRIG0: TRIG_CH9 Position */
-#define DMA_SETTRIG0_TRIG_CH9_Msk (0x01UL << DMA_SETTRIG0_TRIG_CH9_Pos) /*!< DMA SETTRIG0: TRIG_CH9 Mask */
-#define DMA_SETTRIG0_TRIG_CH10_Pos 10 /*!< DMA SETTRIG0: TRIG_CH10 Position */
-#define DMA_SETTRIG0_TRIG_CH10_Msk (0x01UL << DMA_SETTRIG0_TRIG_CH10_Pos) /*!< DMA SETTRIG0: TRIG_CH10 Mask */
-#define DMA_SETTRIG0_TRIG_CH11_Pos 11 /*!< DMA SETTRIG0: TRIG_CH11 Position */
-#define DMA_SETTRIG0_TRIG_CH11_Msk (0x01UL << DMA_SETTRIG0_TRIG_CH11_Pos) /*!< DMA SETTRIG0: TRIG_CH11 Mask */
-#define DMA_SETTRIG0_TRIG_CH12_Pos 12 /*!< DMA SETTRIG0: TRIG_CH12 Position */
-#define DMA_SETTRIG0_TRIG_CH12_Msk (0x01UL << DMA_SETTRIG0_TRIG_CH12_Pos) /*!< DMA SETTRIG0: TRIG_CH12 Mask */
-#define DMA_SETTRIG0_TRIG_CH13_Pos 13 /*!< DMA SETTRIG0: TRIG_CH13 Position */
-#define DMA_SETTRIG0_TRIG_CH13_Msk (0x01UL << DMA_SETTRIG0_TRIG_CH13_Pos) /*!< DMA SETTRIG0: TRIG_CH13 Mask */
-#define DMA_SETTRIG0_TRIG_CH14_Pos 14 /*!< DMA SETTRIG0: TRIG_CH14 Position */
-#define DMA_SETTRIG0_TRIG_CH14_Msk (0x01UL << DMA_SETTRIG0_TRIG_CH14_Pos) /*!< DMA SETTRIG0: TRIG_CH14 Mask */
-#define DMA_SETTRIG0_TRIG_CH15_Pos 15 /*!< DMA SETTRIG0: TRIG_CH15 Position */
-#define DMA_SETTRIG0_TRIG_CH15_Msk (0x01UL << DMA_SETTRIG0_TRIG_CH15_Pos) /*!< DMA SETTRIG0: TRIG_CH15 Mask */
-#define DMA_SETTRIG0_TRIG_CH16_Pos 16 /*!< DMA SETTRIG0: TRIG_CH16 Position */
-#define DMA_SETTRIG0_TRIG_CH16_Msk (0x01UL << DMA_SETTRIG0_TRIG_CH16_Pos) /*!< DMA SETTRIG0: TRIG_CH16 Mask */
-#define DMA_SETTRIG0_TRIG_CH17_Pos 17 /*!< DMA SETTRIG0: TRIG_CH17 Position */
-#define DMA_SETTRIG0_TRIG_CH17_Msk (0x01UL << DMA_SETTRIG0_TRIG_CH17_Pos) /*!< DMA SETTRIG0: TRIG_CH17 Mask */
-#define DMA_SETTRIG0_TRIG_CH18_Pos 18 /*!< DMA SETTRIG0: TRIG_CH18 Position */
-#define DMA_SETTRIG0_TRIG_CH18_Msk (0x01UL << DMA_SETTRIG0_TRIG_CH18_Pos) /*!< DMA SETTRIG0: TRIG_CH18 Mask */
-
-/* -------------------------------- u_dma_ABORT0 -------------------------------- */
-#define DMA_ABORT0_ABORTCTRL_CH0_Pos 0 /*!< DMA ABORT0: ABORTCTRL_CH0 Position */
-#define DMA_ABORT0_ABORTCTRL_CH0_Msk (0x01UL << DMA_ABORT0_ABORTCTRL_CH0_Pos) /*!< DMA ABORT0: ABORTCTRL_CH0 Mask */
-#define DMA_ABORT0_ABORTCTRL_CH1_Pos 1 /*!< DMA ABORT0: ABORTCTRL_CH1 Position */
-#define DMA_ABORT0_ABORTCTRL_CH1_Msk (0x01UL << DMA_ABORT0_ABORTCTRL_CH1_Pos) /*!< DMA ABORT0: ABORTCTRL_CH1 Mask */
-#define DMA_ABORT0_ABORTCTRL_CH2_Pos 2 /*!< DMA ABORT0: ABORTCTRL_CH2 Position */
-#define DMA_ABORT0_ABORTCTRL_CH2_Msk (0x01UL << DMA_ABORT0_ABORTCTRL_CH2_Pos) /*!< DMA ABORT0: ABORTCTRL_CH2 Mask */
-#define DMA_ABORT0_ABORTCTRL_CH3_Pos 3 /*!< DMA ABORT0: ABORTCTRL_CH3 Position */
-#define DMA_ABORT0_ABORTCTRL_CH3_Msk (0x01UL << DMA_ABORT0_ABORTCTRL_CH3_Pos) /*!< DMA ABORT0: ABORTCTRL_CH3 Mask */
-#define DMA_ABORT0_ABORTCTRL_CH4_Pos 4 /*!< DMA ABORT0: ABORTCTRL_CH4 Position */
-#define DMA_ABORT0_ABORTCTRL_CH4_Msk (0x01UL << DMA_ABORT0_ABORTCTRL_CH4_Pos) /*!< DMA ABORT0: ABORTCTRL_CH4 Mask */
-#define DMA_ABORT0_ABORTCTRL_CH5_Pos 5 /*!< DMA ABORT0: ABORTCTRL_CH5 Position */
-#define DMA_ABORT0_ABORTCTRL_CH5_Msk (0x01UL << DMA_ABORT0_ABORTCTRL_CH5_Pos) /*!< DMA ABORT0: ABORTCTRL_CH5 Mask */
-#define DMA_ABORT0_ABORTCTRL_CH6_Pos 6 /*!< DMA ABORT0: ABORTCTRL_CH6 Position */
-#define DMA_ABORT0_ABORTCTRL_CH6_Msk (0x01UL << DMA_ABORT0_ABORTCTRL_CH6_Pos) /*!< DMA ABORT0: ABORTCTRL_CH6 Mask */
-#define DMA_ABORT0_ABORTCTRL_CH7_Pos 7 /*!< DMA ABORT0: ABORTCTRL_CH7 Position */
-#define DMA_ABORT0_ABORTCTRL_CH7_Msk (0x01UL << DMA_ABORT0_ABORTCTRL_CH7_Pos) /*!< DMA ABORT0: ABORTCTRL_CH7 Mask */
-#define DMA_ABORT0_ABORTCTRL_CH8_Pos 8 /*!< DMA ABORT0: ABORTCTRL_CH8 Position */
-#define DMA_ABORT0_ABORTCTRL_CH8_Msk (0x01UL << DMA_ABORT0_ABORTCTRL_CH8_Pos) /*!< DMA ABORT0: ABORTCTRL_CH8 Mask */
-#define DMA_ABORT0_ABORTCTRL_CH9_Pos 9 /*!< DMA ABORT0: ABORTCTRL_CH9 Position */
-#define DMA_ABORT0_ABORTCTRL_CH9_Msk (0x01UL << DMA_ABORT0_ABORTCTRL_CH9_Pos) /*!< DMA ABORT0: ABORTCTRL_CH9 Mask */
-#define DMA_ABORT0_ABORTCTRL_CH10_Pos 10 /*!< DMA ABORT0: ABORTCTRL_CH10 Position */
-#define DMA_ABORT0_ABORTCTRL_CH10_Msk (0x01UL << DMA_ABORT0_ABORTCTRL_CH10_Pos) /*!< DMA ABORT0: ABORTCTRL_CH10 Mask */
-#define DMA_ABORT0_ABORTCTRL_CH11_Pos 11 /*!< DMA ABORT0: ABORTCTRL_CH11 Position */
-#define DMA_ABORT0_ABORTCTRL_CH11_Msk (0x01UL << DMA_ABORT0_ABORTCTRL_CH11_Pos) /*!< DMA ABORT0: ABORTCTRL_CH11 Mask */
-#define DMA_ABORT0_ABORTCTRL_CH12_Pos 12 /*!< DMA ABORT0: ABORTCTRL_CH12 Position */
-#define DMA_ABORT0_ABORTCTRL_CH12_Msk (0x01UL << DMA_ABORT0_ABORTCTRL_CH12_Pos) /*!< DMA ABORT0: ABORTCTRL_CH12 Mask */
-#define DMA_ABORT0_ABORTCTRL_CH13_Pos 13 /*!< DMA ABORT0: ABORTCTRL_CH13 Position */
-#define DMA_ABORT0_ABORTCTRL_CH13_Msk (0x01UL << DMA_ABORT0_ABORTCTRL_CH13_Pos) /*!< DMA ABORT0: ABORTCTRL_CH13 Mask */
-#define DMA_ABORT0_ABORTCTRL_CH14_Pos 14 /*!< DMA ABORT0: ABORTCTRL_CH14 Position */
-#define DMA_ABORT0_ABORTCTRL_CH14_Msk (0x01UL << DMA_ABORT0_ABORTCTRL_CH14_Pos) /*!< DMA ABORT0: ABORTCTRL_CH14 Mask */
-#define DMA_ABORT0_ABORTCTRL_CH15_Pos 15 /*!< DMA ABORT0: ABORTCTRL_CH15 Position */
-#define DMA_ABORT0_ABORTCTRL_CH15_Msk (0x01UL << DMA_ABORT0_ABORTCTRL_CH15_Pos) /*!< DMA ABORT0: ABORTCTRL_CH15 Mask */
-#define DMA_ABORT0_ABORTCTRL_CH16_Pos 16 /*!< DMA ABORT0: ABORTCTRL_CH16 Position */
-#define DMA_ABORT0_ABORTCTRL_CH16_Msk (0x01UL << DMA_ABORT0_ABORTCTRL_CH16_Pos) /*!< DMA ABORT0: ABORTCTRL_CH16 Mask */
-#define DMA_ABORT0_ABORTCTRL_CH17_Pos 17 /*!< DMA ABORT0: ABORTCTRL_CH17 Position */
-#define DMA_ABORT0_ABORTCTRL_CH17_Msk (0x01UL << DMA_ABORT0_ABORTCTRL_CH17_Pos) /*!< DMA ABORT0: ABORTCTRL_CH17 Mask */
-#define DMA_ABORT0_ABORTCTRL_CH18_Pos 18 /*!< DMA ABORT0: ABORTCTRL_CH18 Position */
-#define DMA_ABORT0_ABORTCTRL_CH18_Msk (0x01UL << DMA_ABORT0_ABORTCTRL_CH18_Pos) /*!< DMA ABORT0: ABORTCTRL_CH18 Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'Channel' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* --------------------------------- Channel_CFG -------------------------------- */
-#define Channel_CFG_PERIPHREQEN_Pos 0 /*!< Channel CFG: PERIPHREQEN Position */
-#define Channel_CFG_PERIPHREQEN_Msk (0x01UL << Channel_CFG_PERIPHREQEN_Pos) /*!< Channel CFG: PERIPHREQEN Mask */
-#define Channel_CFG_HWTRIGEN_Pos 1 /*!< Channel CFG: HWTRIGEN Position */
-#define Channel_CFG_HWTRIGEN_Msk (0x01UL << Channel_CFG_HWTRIGEN_Pos) /*!< Channel CFG: HWTRIGEN Mask */
-#define Channel_CFG_TRIGPOL_Pos 4 /*!< Channel CFG: TRIGPOL Position */
-#define Channel_CFG_TRIGPOL_Msk (0x01UL << Channel_CFG_TRIGPOL_Pos) /*!< Channel CFG: TRIGPOL Mask */
-#define Channel_CFG_TRIGTYPE_Pos 5 /*!< Channel CFG: TRIGTYPE Position */
-#define Channel_CFG_TRIGTYPE_Msk (0x01UL << Channel_CFG_TRIGTYPE_Pos) /*!< Channel CFG: TRIGTYPE Mask */
-#define Channel_CFG_TRIGBURST_Pos 6 /*!< Channel CFG: TRIGBURST Position */
-#define Channel_CFG_TRIGBURST_Msk (0x01UL << Channel_CFG_TRIGBURST_Pos) /*!< Channel CFG: TRIGBURST Mask */
-#define Channel_CFG_BURSTPOWER_Pos 8 /*!< Channel CFG: BURSTPOWER Position */
-#define Channel_CFG_BURSTPOWER_Msk (0x0fUL << Channel_CFG_BURSTPOWER_Pos) /*!< Channel CFG: BURSTPOWER Mask */
-#define Channel_CFG_SRCBURSTWRAP_Pos 14 /*!< Channel CFG: SRCBURSTWRAP Position */
-#define Channel_CFG_SRCBURSTWRAP_Msk (0x01UL << Channel_CFG_SRCBURSTWRAP_Pos) /*!< Channel CFG: SRCBURSTWRAP Mask */
-#define Channel_CFG_DSTBURSTWRAP_Pos 15 /*!< Channel CFG: DSTBURSTWRAP Position */
-#define Channel_CFG_DSTBURSTWRAP_Msk (0x01UL << Channel_CFG_DSTBURSTWRAP_Pos) /*!< Channel CFG: DSTBURSTWRAP Mask */
-#define Channel_CFG_CHPRIORITY_Pos 16 /*!< Channel CFG: CHPRIORITY Position */
-#define Channel_CFG_CHPRIORITY_Msk (0x07UL << Channel_CFG_CHPRIORITY_Pos) /*!< Channel CFG: CHPRIORITY Mask */
-
-/* ------------------------------- Channel_CTLSTAT ------------------------------ */
-#define Channel_CTLSTAT_VALIDPENDING_Pos 0 /*!< Channel CTLSTAT: VALIDPENDING Position */
-#define Channel_CTLSTAT_VALIDPENDING_Msk (0x01UL << Channel_CTLSTAT_VALIDPENDING_Pos) /*!< Channel CTLSTAT: VALIDPENDING Mask */
-#define Channel_CTLSTAT_TRIG_Pos 2 /*!< Channel CTLSTAT: TRIG Position */
-#define Channel_CTLSTAT_TRIG_Msk (0x01UL << Channel_CTLSTAT_TRIG_Pos) /*!< Channel CTLSTAT: TRIG Mask */
-
-/* ------------------------------- Channel_XFERCFG ------------------------------ */
-#define Channel_XFERCFG_CFGVALID_Pos 0 /*!< Channel XFERCFG: CFGVALID Position */
-#define Channel_XFERCFG_CFGVALID_Msk (0x01UL << Channel_XFERCFG_CFGVALID_Pos) /*!< Channel XFERCFG: CFGVALID Mask */
-#define Channel_XFERCFG_RELOAD_Pos 1 /*!< Channel XFERCFG: RELOAD Position */
-#define Channel_XFERCFG_RELOAD_Msk (0x01UL << Channel_XFERCFG_RELOAD_Pos) /*!< Channel XFERCFG: RELOAD Mask */
-#define Channel_XFERCFG_SWTRIG_Pos 2 /*!< Channel XFERCFG: SWTRIG Position */
-#define Channel_XFERCFG_SWTRIG_Msk (0x01UL << Channel_XFERCFG_SWTRIG_Pos) /*!< Channel XFERCFG: SWTRIG Mask */
-#define Channel_XFERCFG_CLRTRIG_Pos 3 /*!< Channel XFERCFG: CLRTRIG Position */
-#define Channel_XFERCFG_CLRTRIG_Msk (0x01UL << Channel_XFERCFG_CLRTRIG_Pos) /*!< Channel XFERCFG: CLRTRIG Mask */
-#define Channel_XFERCFG_SETINTA_Pos 4 /*!< Channel XFERCFG: SETINTA Position */
-#define Channel_XFERCFG_SETINTA_Msk (0x01UL << Channel_XFERCFG_SETINTA_Pos) /*!< Channel XFERCFG: SETINTA Mask */
-#define Channel_XFERCFG_SETINTB_Pos 5 /*!< Channel XFERCFG: SETINTB Position */
-#define Channel_XFERCFG_SETINTB_Msk (0x01UL << Channel_XFERCFG_SETINTB_Pos) /*!< Channel XFERCFG: SETINTB Mask */
-#define Channel_XFERCFG_WIDTH_Pos 8 /*!< Channel XFERCFG: WIDTH Position */
-#define Channel_XFERCFG_WIDTH_Msk (0x03UL << Channel_XFERCFG_WIDTH_Pos) /*!< Channel XFERCFG: WIDTH Mask */
-#define Channel_XFERCFG_SRCINC_Pos 12 /*!< Channel XFERCFG: SRCINC Position */
-#define Channel_XFERCFG_SRCINC_Msk (0x03UL << Channel_XFERCFG_SRCINC_Pos) /*!< Channel XFERCFG: SRCINC Mask */
-#define Channel_XFERCFG_DSTINC_Pos 14 /*!< Channel XFERCFG: DSTINC Position */
-#define Channel_XFERCFG_DSTINC_Msk (0x03UL << Channel_XFERCFG_DSTINC_Pos) /*!< Channel XFERCFG: DSTINC Mask */
-#define Channel_XFERCFG_XFERCOUNT_Pos 16 /*!< Channel XFERCFG: XFERCOUNT Position */
-#define Channel_XFERCFG_XFERCOUNT_Msk (0x000003ffUL << Channel_XFERCFG_XFERCOUNT_Pos) /*!< Channel XFERCFG: XFERCOUNT Mask */
-
-/* ------------------------------ Channel_RESERVED0 ----------------------------- */
-#define Channel_RESERVED0_DUMMYWORD_Pos 0 /*!< Channel RESERVED0: DUMMYWORD Position */
-#define Channel_RESERVED0_DUMMYWORD_Msk (0xffffffffUL << Channel_RESERVED0_DUMMYWORD_Pos) /*!< Channel RESERVED0: DUMMYWORD Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u_aes256' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* -------------------------------- u_aes256_CFG -------------------------------- */
-#define AES256_CFG_PROC_EN_Pos 0 /*!< AES256 CFG: PROC_EN Position */
-#define AES256_CFG_PROC_EN_Msk (0x03UL << AES256_CFG_PROC_EN_Pos) /*!< AES256 CFG: PROC_EN Mask */
-#define AES256_CFG_GF128_SEL_Pos 2 /*!< AES256 CFG: GF128_SEL Position */
-#define AES256_CFG_GF128_SEL_Msk (0x01UL << AES256_CFG_GF128_SEL_Pos) /*!< AES256 CFG: GF128_SEL Mask */
-#define AES256_CFG_INT_BSWAP_Pos 4 /*!< AES256 CFG: INT_BSWAP Position */
-#define AES256_CFG_INT_BSWAP_Msk (0x01UL << AES256_CFG_INT_BSWAP_Pos) /*!< AES256 CFG: INT_BSWAP Mask */
-#define AES256_CFG_INT_WSWAP_Pos 5 /*!< AES256 CFG: INT_WSWAP Position */
-#define AES256_CFG_INT_WSWAP_Msk (0x01UL << AES256_CFG_INT_WSWAP_Pos) /*!< AES256 CFG: INT_WSWAP Mask */
-#define AES256_CFG_OUTT_BSWAP_Pos 6 /*!< AES256 CFG: OUTT_BSWAP Position */
-#define AES256_CFG_OUTT_BSWAP_Msk (0x01UL << AES256_CFG_OUTT_BSWAP_Pos) /*!< AES256 CFG: OUTT_BSWAP Mask */
-#define AES256_CFG_OUTT_WSWAP_Pos 7 /*!< AES256 CFG: OUTT_WSWAP Position */
-#define AES256_CFG_OUTT_WSWAP_Msk (0x01UL << AES256_CFG_OUTT_WSWAP_Pos) /*!< AES256 CFG: OUTT_WSWAP Mask */
-#define AES256_CFG_KEY_CFG_Pos 8 /*!< AES256 CFG: KEY_CFG Position */
-#define AES256_CFG_KEY_CFG_Msk (0x03UL << AES256_CFG_KEY_CFG_Pos) /*!< AES256 CFG: KEY_CFG Mask */
-#define AES256_CFG_INB_FSEL_Pos 16 /*!< AES256 CFG: INB_FSEL Position */
-#define AES256_CFG_INB_FSEL_Msk (0x03UL << AES256_CFG_INB_FSEL_Pos) /*!< AES256 CFG: INB_FSEL Mask */
-#define AES256_CFG_HOLD_FSEL_Pos 20 /*!< AES256 CFG: HOLD_FSEL Position */
-#define AES256_CFG_HOLD_FSEL_Msk (0x03UL << AES256_CFG_HOLD_FSEL_Pos) /*!< AES256 CFG: HOLD_FSEL Mask */
-#define AES256_CFG_OUTT_FSEL_Pos 24 /*!< AES256 CFG: OUTT_FSEL Position */
-#define AES256_CFG_OUTT_FSEL_Msk (0x03UL << AES256_CFG_OUTT_FSEL_Pos) /*!< AES256 CFG: OUTT_FSEL Mask */
-
-/* -------------------------------- u_aes256_CMD -------------------------------- */
-#define AES256_CMD_COPY_SKEY_Pos 0 /*!< AES256 CMD: COPY_SKEY Position */
-#define AES256_CMD_COPY_SKEY_Msk (0x01UL << AES256_CMD_COPY_SKEY_Pos) /*!< AES256 CMD: COPY_SKEY Mask */
-#define AES256_CMD_COPY_TO_Y_Pos 1 /*!< AES256 CMD: COPY_TO_Y Position */
-#define AES256_CMD_COPY_TO_Y_Msk (0x01UL << AES256_CMD_COPY_TO_Y_Pos) /*!< AES256 CMD: COPY_TO_Y Mask */
-#define AES256_CMD_SWITCH_MODE_Pos 4 /*!< AES256 CMD: SWITCH_MODE Position */
-#define AES256_CMD_SWITCH_MODE_Msk (0x01UL << AES256_CMD_SWITCH_MODE_Pos) /*!< AES256 CMD: SWITCH_MODE Mask */
-#define AES256_CMD_ABORT_Pos 8 /*!< AES256 CMD: ABORT Position */
-#define AES256_CMD_ABORT_Msk (0x01UL << AES256_CMD_ABORT_Pos) /*!< AES256 CMD: ABORT Mask */
-#define AES256_CMD_WIPE_Pos 9 /*!< AES256 CMD: WIPE Position */
-#define AES256_CMD_WIPE_Msk (0x01UL << AES256_CMD_WIPE_Pos) /*!< AES256 CMD: WIPE Mask */
-
-/* -------------------------------- u_aes256_STAT ------------------------------- */
-#define AES256_STAT_IDLE_Pos 0 /*!< AES256 STAT: IDLE Position */
-#define AES256_STAT_IDLE_Msk (0x01UL << AES256_STAT_IDLE_Pos) /*!< AES256 STAT: IDLE Mask */
-#define AES256_STAT_IN_READY_Pos 1 /*!< AES256 STAT: IN_READY Position */
-#define AES256_STAT_IN_READY_Msk (0x01UL << AES256_STAT_IN_READY_Pos) /*!< AES256 STAT: IN_READY Mask */
-#define AES256_STAT_OUT_READY_Pos 2 /*!< AES256 STAT: OUT_READY Position */
-#define AES256_STAT_OUT_READY_Msk (0x01UL << AES256_STAT_OUT_READY_Pos) /*!< AES256 STAT: OUT_READY Mask */
-#define AES256_STAT_REVERSE_Pos 4 /*!< AES256 STAT: REVERSE Position */
-#define AES256_STAT_REVERSE_Msk (0x01UL << AES256_STAT_REVERSE_Pos) /*!< AES256 STAT: REVERSE Mask */
-#define AES256_STAT_KEY_VALID_Pos 5 /*!< AES256 STAT: KEY_VALID Position */
-#define AES256_STAT_KEY_VALID_Msk (0x01UL << AES256_STAT_KEY_VALID_Pos) /*!< AES256 STAT: KEY_VALID Mask */
-
-/* ------------------------------ u_aes256_CTR_INCR ----------------------------- */
-#define AES256_CTR_INCR_CTR_INCR_Pos 0 /*!< AES256 CTR_INCR: CTR_INCR Position */
-#define AES256_CTR_INCR_CTR_INCR_Msk (0xffffffffUL << AES256_CTR_INCR_CTR_INCR_Pos) /*!< AES256 CTR_INCR: CTR_INCR Mask */
-
-/* -------------------------------- u_aes256_KEY0 ------------------------------- */
-#define AES256_KEY0_KEY0_Pos 0 /*!< AES256 KEY0: KEY0 Position */
-#define AES256_KEY0_KEY0_Msk (0xffffffffUL << AES256_KEY0_KEY0_Pos) /*!< AES256 KEY0: KEY0 Mask */
-
-/* -------------------------------- u_aes256_KEY1 ------------------------------- */
-#define AES256_KEY1_KEY1_Pos 0 /*!< AES256 KEY1: KEY1 Position */
-#define AES256_KEY1_KEY1_Msk (0xffffffffUL << AES256_KEY1_KEY1_Pos) /*!< AES256 KEY1: KEY1 Mask */
-
-/* -------------------------------- u_aes256_KEY2 ------------------------------- */
-#define AES256_KEY2_KEY2_Pos 0 /*!< AES256 KEY2: KEY2 Position */
-#define AES256_KEY2_KEY2_Msk (0xffffffffUL << AES256_KEY2_KEY2_Pos) /*!< AES256 KEY2: KEY2 Mask */
-
-/* -------------------------------- u_aes256_KEY3 ------------------------------- */
-#define AES256_KEY3_KEY3_Pos 0 /*!< AES256 KEY3: KEY3 Position */
-#define AES256_KEY3_KEY3_Msk (0xffffffffUL << AES256_KEY3_KEY3_Pos) /*!< AES256 KEY3: KEY3 Mask */
-
-/* -------------------------------- u_aes256_KEY4 ------------------------------- */
-#define AES256_KEY4_KEY4_Pos 0 /*!< AES256 KEY4: KEY4 Position */
-#define AES256_KEY4_KEY4_Msk (0xffffffffUL << AES256_KEY4_KEY4_Pos) /*!< AES256 KEY4: KEY4 Mask */
-
-/* -------------------------------- u_aes256_KEY5 ------------------------------- */
-#define AES256_KEY5_KEY5_Pos 0 /*!< AES256 KEY5: KEY5 Position */
-#define AES256_KEY5_KEY5_Msk (0xffffffffUL << AES256_KEY5_KEY5_Pos) /*!< AES256 KEY5: KEY5 Mask */
-
-/* -------------------------------- u_aes256_KEY6 ------------------------------- */
-#define AES256_KEY6_KEY6_Pos 0 /*!< AES256 KEY6: KEY6 Position */
-#define AES256_KEY6_KEY6_Msk (0xffffffffUL << AES256_KEY6_KEY6_Pos) /*!< AES256 KEY6: KEY6 Mask */
-
-/* -------------------------------- u_aes256_KEY7 ------------------------------- */
-#define AES256_KEY7_KEY7_Pos 0 /*!< AES256 KEY7: KEY7 Position */
-#define AES256_KEY7_KEY7_Msk (0xffffffffUL << AES256_KEY7_KEY7_Pos) /*!< AES256 KEY7: KEY7 Mask */
-
-/* -------------------------------- u_aes256_IN0 -------------------------------- */
-#define AES256_IN0_IN0_Pos 0 /*!< AES256 IN0: IN0 Position */
-#define AES256_IN0_IN0_Msk (0xffffffffUL << AES256_IN0_IN0_Pos) /*!< AES256 IN0: IN0 Mask */
-
-/* -------------------------------- u_aes256_IN1 -------------------------------- */
-#define AES256_IN1_IN1_Pos 0 /*!< AES256 IN1: IN1 Position */
-#define AES256_IN1_IN1_Msk (0xffffffffUL << AES256_IN1_IN1_Pos) /*!< AES256 IN1: IN1 Mask */
-
-/* -------------------------------- u_aes256_IN2 -------------------------------- */
-#define AES256_IN2_IN2_Pos 0 /*!< AES256 IN2: IN2 Position */
-#define AES256_IN2_IN2_Msk (0xffffffffUL << AES256_IN2_IN2_Pos) /*!< AES256 IN2: IN2 Mask */
-
-/* -------------------------------- u_aes256_IN3 -------------------------------- */
-#define AES256_IN3_IN3_Pos 0 /*!< AES256 IN3: IN3 Position */
-#define AES256_IN3_IN3_Msk (0xffffffffUL << AES256_IN3_IN3_Pos) /*!< AES256 IN3: IN3 Mask */
-
-/* ------------------------------ u_aes256_HOLDING0 ----------------------------- */
-#define AES256_HOLDING0_HOLDING0_Pos 0 /*!< AES256 HOLDING0: HOLDING0 Position */
-#define AES256_HOLDING0_HOLDING0_Msk (0xffffffffUL << AES256_HOLDING0_HOLDING0_Pos) /*!< AES256 HOLDING0: HOLDING0 Mask */
-
-/* ------------------------------ u_aes256_HOLDING1 ----------------------------- */
-#define AES256_HOLDING1_HOLDING1_Pos 0 /*!< AES256 HOLDING1: HOLDING1 Position */
-#define AES256_HOLDING1_HOLDING1_Msk (0xffffffffUL << AES256_HOLDING1_HOLDING1_Pos) /*!< AES256 HOLDING1: HOLDING1 Mask */
-
-/* ------------------------------ u_aes256_HOLDING2 ----------------------------- */
-#define AES256_HOLDING2_HOLDING2_Pos 0 /*!< AES256 HOLDING2: HOLDING2 Position */
-#define AES256_HOLDING2_HOLDING2_Msk (0xffffffffUL << AES256_HOLDING2_HOLDING2_Pos) /*!< AES256 HOLDING2: HOLDING2 Mask */
-
-/* ------------------------------ u_aes256_HOLDING3 ----------------------------- */
-#define AES256_HOLDING3_HOLDING3_Pos 0 /*!< AES256 HOLDING3: HOLDING3 Position */
-#define AES256_HOLDING3_HOLDING3_Msk (0xffffffffUL << AES256_HOLDING3_HOLDING3_Pos) /*!< AES256 HOLDING3: HOLDING3 Mask */
-
-/* -------------------------------- u_aes256_OUT0 ------------------------------- */
-#define AES256_OUT0_OUT0_Pos 0 /*!< AES256 OUT0: OUT0 Position */
-#define AES256_OUT0_OUT0_Msk (0xffffffffUL << AES256_OUT0_OUT0_Pos) /*!< AES256 OUT0: OUT0 Mask */
-
-/* -------------------------------- u_aes256_OUT1 ------------------------------- */
-#define AES256_OUT1_OUT1_Pos 0 /*!< AES256 OUT1: OUT1 Position */
-#define AES256_OUT1_OUT1_Msk (0xffffffffUL << AES256_OUT1_OUT1_Pos) /*!< AES256 OUT1: OUT1 Mask */
-
-/* -------------------------------- u_aes256_OUT2 ------------------------------- */
-#define AES256_OUT2_OUT2_Pos 0 /*!< AES256 OUT2: OUT2 Position */
-#define AES256_OUT2_OUT2_Msk (0xffffffffUL << AES256_OUT2_OUT2_Pos) /*!< AES256 OUT2: OUT2 Mask */
-
-/* -------------------------------- u_aes256_OUT3 ------------------------------- */
-#define AES256_OUT3_OUT3_Pos 0 /*!< AES256 OUT3: OUT3 Position */
-#define AES256_OUT3_OUT3_Msk (0xffffffffUL << AES256_OUT3_OUT3_Pos) /*!< AES256 OUT3: OUT3 Mask */
-
-/* ------------------------------ u_aes256_GF128_Y0 ----------------------------- */
-#define AES256_GF128_Y0_GF128_Y0_Pos 0 /*!< AES256 GF128_Y0: GF128_Y0 Position */
-#define AES256_GF128_Y0_GF128_Y0_Msk (0xffffffffUL << AES256_GF128_Y0_GF128_Y0_Pos) /*!< AES256 GF128_Y0: GF128_Y0 Mask */
-
-/* ------------------------------ u_aes256_GF128_Y1 ----------------------------- */
-#define AES256_GF128_Y1_GF128_Y1_Pos 0 /*!< AES256 GF128_Y1: GF128_Y1 Position */
-#define AES256_GF128_Y1_GF128_Y1_Msk (0xffffffffUL << AES256_GF128_Y1_GF128_Y1_Pos) /*!< AES256 GF128_Y1: GF128_Y1 Mask */
-
-/* ------------------------------ u_aes256_GF128_Y2 ----------------------------- */
-#define AES256_GF128_Y2_GF128_Y2_Pos 0 /*!< AES256 GF128_Y2: GF128_Y2 Position */
-#define AES256_GF128_Y2_GF128_Y2_Msk (0xffffffffUL << AES256_GF128_Y2_GF128_Y2_Pos) /*!< AES256 GF128_Y2: GF128_Y2 Mask */
-
-/* ------------------------------ u_aes256_GF128_Y3 ----------------------------- */
-#define AES256_GF128_Y3_GF128_Y3_Pos 0 /*!< AES256 GF128_Y3: GF128_Y3 Position */
-#define AES256_GF128_Y3_GF128_Y3_Msk (0xffffffffUL << AES256_GF128_Y3_GF128_Y3_Pos) /*!< AES256 GF128_Y3: GF128_Y3 Mask */
-
-/* ------------------------------ u_aes256_GF128_Z0 ----------------------------- */
-#define AES256_GF128_Z0_GF128_Z0_Pos 0 /*!< AES256 GF128_Z0: GF128_Z0 Position */
-#define AES256_GF128_Z0_GF128_Z0_Msk (0xffffffffUL << AES256_GF128_Z0_GF128_Z0_Pos) /*!< AES256 GF128_Z0: GF128_Z0 Mask */
-
-/* ------------------------------ u_aes256_GF128_Z1 ----------------------------- */
-#define AES256_GF128_Z1_GF128_Z1_Pos 0 /*!< AES256 GF128_Z1: GF128_Z1 Position */
-#define AES256_GF128_Z1_GF128_Z1_Msk (0xffffffffUL << AES256_GF128_Z1_GF128_Z1_Pos) /*!< AES256 GF128_Z1: GF128_Z1 Mask */
-
-/* ------------------------------ u_aes256_GF128_Z2 ----------------------------- */
-#define AES256_GF128_Z2_GF128_Z2_Pos 0 /*!< AES256 GF128_Z2: GF128_Z2 Position */
-#define AES256_GF128_Z2_GF128_Z2_Msk (0xffffffffUL << AES256_GF128_Z2_GF128_Z2_Pos) /*!< AES256 GF128_Z2: GF128_Z2 Mask */
-
-/* ------------------------------ u_aes256_GF128_Z3 ----------------------------- */
-#define AES256_GF128_Z3_GF128_Z3_Pos 0 /*!< AES256 GF128_Z3: GF128_Z3 Position */
-#define AES256_GF128_Z3_GF128_Z3_Msk (0xffffffffUL << AES256_GF128_Z3_GF128_Z3_Pos) /*!< AES256 GF128_Z3: GF128_Z3 Mask */
-
-/* ------------------------------ u_aes256_GCM_TAG0 ----------------------------- */
-#define AES256_GCM_TAG0_GCM_TAG0_Pos 0 /*!< AES256 GCM_TAG0: GCM_TAG0 Position */
-#define AES256_GCM_TAG0_GCM_TAG0_Msk (0xffffffffUL << AES256_GCM_TAG0_GCM_TAG0_Pos) /*!< AES256 GCM_TAG0: GCM_TAG0 Mask */
-
-/* ------------------------------ u_aes256_GCM_TAG1 ----------------------------- */
-#define AES256_GCM_TAG1_GCM_TAG1_Pos 0 /*!< AES256 GCM_TAG1: GCM_TAG1 Position */
-#define AES256_GCM_TAG1_GCM_TAG1_Msk (0xffffffffUL << AES256_GCM_TAG1_GCM_TAG1_Pos) /*!< AES256 GCM_TAG1: GCM_TAG1 Mask */
-
-/* ------------------------------ u_aes256_GCM_TAG2 ----------------------------- */
-#define AES256_GCM_TAG2_GCM_TAG2_Pos 0 /*!< AES256 GCM_TAG2: GCM_TAG2 Position */
-#define AES256_GCM_TAG2_GCM_TAG2_Msk (0xffffffffUL << AES256_GCM_TAG2_GCM_TAG2_Pos) /*!< AES256 GCM_TAG2: GCM_TAG2 Mask */
-
-/* ------------------------------ u_aes256_GCM_TAG3 ----------------------------- */
-#define AES256_GCM_TAG3_GCM_TAG3_Pos 0 /*!< AES256 GCM_TAG3: GCM_TAG3 Position */
-#define AES256_GCM_TAG3_GCM_TAG3_Msk (0xffffffffUL << AES256_GCM_TAG3_GCM_TAG3_Pos) /*!< AES256 GCM_TAG3: GCM_TAG3 Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u_mailbox' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* ------------------------------- u_mailbox_IRQ0 ------------------------------- */
-#define MAILBOX_IRQ0_INTREQ0_Pos 0 /*!< MAILBOX IRQ0: INTREQ0 Position */
-#define MAILBOX_IRQ0_INTREQ0_Msk (0x01UL << MAILBOX_IRQ0_INTREQ0_Pos) /*!< MAILBOX IRQ0: INTREQ0 Mask */
-#define MAILBOX_IRQ0_INTREQ1_Pos 1 /*!< MAILBOX IRQ0: INTREQ1 Position */
-#define MAILBOX_IRQ0_INTREQ1_Msk (0x01UL << MAILBOX_IRQ0_INTREQ1_Pos) /*!< MAILBOX IRQ0: INTREQ1 Mask */
-#define MAILBOX_IRQ0_INTREQ2_Pos 2 /*!< MAILBOX IRQ0: INTREQ2 Position */
-#define MAILBOX_IRQ0_INTREQ2_Msk (0x01UL << MAILBOX_IRQ0_INTREQ2_Pos) /*!< MAILBOX IRQ0: INTREQ2 Mask */
-#define MAILBOX_IRQ0_INTREQ3_Pos 3 /*!< MAILBOX IRQ0: INTREQ3 Position */
-#define MAILBOX_IRQ0_INTREQ3_Msk (0x01UL << MAILBOX_IRQ0_INTREQ3_Pos) /*!< MAILBOX IRQ0: INTREQ3 Mask */
-#define MAILBOX_IRQ0_INTREQ4_Pos 4 /*!< MAILBOX IRQ0: INTREQ4 Position */
-#define MAILBOX_IRQ0_INTREQ4_Msk (0x01UL << MAILBOX_IRQ0_INTREQ4_Pos) /*!< MAILBOX IRQ0: INTREQ4 Mask */
-#define MAILBOX_IRQ0_INTREQ5_Pos 5 /*!< MAILBOX IRQ0: INTREQ5 Position */
-#define MAILBOX_IRQ0_INTREQ5_Msk (0x01UL << MAILBOX_IRQ0_INTREQ5_Pos) /*!< MAILBOX IRQ0: INTREQ5 Mask */
-#define MAILBOX_IRQ0_INTREQ6_Pos 6 /*!< MAILBOX IRQ0: INTREQ6 Position */
-#define MAILBOX_IRQ0_INTREQ6_Msk (0x01UL << MAILBOX_IRQ0_INTREQ6_Pos) /*!< MAILBOX IRQ0: INTREQ6 Mask */
-#define MAILBOX_IRQ0_INTREQ7_Pos 7 /*!< MAILBOX IRQ0: INTREQ7 Position */
-#define MAILBOX_IRQ0_INTREQ7_Msk (0x01UL << MAILBOX_IRQ0_INTREQ7_Pos) /*!< MAILBOX IRQ0: INTREQ7 Mask */
-#define MAILBOX_IRQ0_INTREQ8_Pos 8 /*!< MAILBOX IRQ0: INTREQ8 Position */
-#define MAILBOX_IRQ0_INTREQ8_Msk (0x01UL << MAILBOX_IRQ0_INTREQ8_Pos) /*!< MAILBOX IRQ0: INTREQ8 Mask */
-#define MAILBOX_IRQ0_INTREQ9_Pos 9 /*!< MAILBOX IRQ0: INTREQ9 Position */
-#define MAILBOX_IRQ0_INTREQ9_Msk (0x01UL << MAILBOX_IRQ0_INTREQ9_Pos) /*!< MAILBOX IRQ0: INTREQ9 Mask */
-#define MAILBOX_IRQ0_INTREQ10_Pos 10 /*!< MAILBOX IRQ0: INTREQ10 Position */
-#define MAILBOX_IRQ0_INTREQ10_Msk (0x01UL << MAILBOX_IRQ0_INTREQ10_Pos) /*!< MAILBOX IRQ0: INTREQ10 Mask */
-#define MAILBOX_IRQ0_INTREQ11_Pos 11 /*!< MAILBOX IRQ0: INTREQ11 Position */
-#define MAILBOX_IRQ0_INTREQ11_Msk (0x01UL << MAILBOX_IRQ0_INTREQ11_Pos) /*!< MAILBOX IRQ0: INTREQ11 Mask */
-#define MAILBOX_IRQ0_INTREQ12_Pos 12 /*!< MAILBOX IRQ0: INTREQ12 Position */
-#define MAILBOX_IRQ0_INTREQ12_Msk (0x01UL << MAILBOX_IRQ0_INTREQ12_Pos) /*!< MAILBOX IRQ0: INTREQ12 Mask */
-#define MAILBOX_IRQ0_INTREQ13_Pos 13 /*!< MAILBOX IRQ0: INTREQ13 Position */
-#define MAILBOX_IRQ0_INTREQ13_Msk (0x01UL << MAILBOX_IRQ0_INTREQ13_Pos) /*!< MAILBOX IRQ0: INTREQ13 Mask */
-#define MAILBOX_IRQ0_INTREQ14_Pos 14 /*!< MAILBOX IRQ0: INTREQ14 Position */
-#define MAILBOX_IRQ0_INTREQ14_Msk (0x01UL << MAILBOX_IRQ0_INTREQ14_Pos) /*!< MAILBOX IRQ0: INTREQ14 Mask */
-#define MAILBOX_IRQ0_INTREQ15_Pos 15 /*!< MAILBOX IRQ0: INTREQ15 Position */
-#define MAILBOX_IRQ0_INTREQ15_Msk (0x01UL << MAILBOX_IRQ0_INTREQ15_Pos) /*!< MAILBOX IRQ0: INTREQ15 Mask */
-#define MAILBOX_IRQ0_INTREQ16_Pos 16 /*!< MAILBOX IRQ0: INTREQ16 Position */
-#define MAILBOX_IRQ0_INTREQ16_Msk (0x01UL << MAILBOX_IRQ0_INTREQ16_Pos) /*!< MAILBOX IRQ0: INTREQ16 Mask */
-#define MAILBOX_IRQ0_INTREQ17_Pos 17 /*!< MAILBOX IRQ0: INTREQ17 Position */
-#define MAILBOX_IRQ0_INTREQ17_Msk (0x01UL << MAILBOX_IRQ0_INTREQ17_Pos) /*!< MAILBOX IRQ0: INTREQ17 Mask */
-#define MAILBOX_IRQ0_INTREQ18_Pos 18 /*!< MAILBOX IRQ0: INTREQ18 Position */
-#define MAILBOX_IRQ0_INTREQ18_Msk (0x01UL << MAILBOX_IRQ0_INTREQ18_Pos) /*!< MAILBOX IRQ0: INTREQ18 Mask */
-#define MAILBOX_IRQ0_INTREQ19_Pos 19 /*!< MAILBOX IRQ0: INTREQ19 Position */
-#define MAILBOX_IRQ0_INTREQ19_Msk (0x01UL << MAILBOX_IRQ0_INTREQ19_Pos) /*!< MAILBOX IRQ0: INTREQ19 Mask */
-#define MAILBOX_IRQ0_INTREQ20_Pos 20 /*!< MAILBOX IRQ0: INTREQ20 Position */
-#define MAILBOX_IRQ0_INTREQ20_Msk (0x01UL << MAILBOX_IRQ0_INTREQ20_Pos) /*!< MAILBOX IRQ0: INTREQ20 Mask */
-#define MAILBOX_IRQ0_INTREQ21_Pos 21 /*!< MAILBOX IRQ0: INTREQ21 Position */
-#define MAILBOX_IRQ0_INTREQ21_Msk (0x01UL << MAILBOX_IRQ0_INTREQ21_Pos) /*!< MAILBOX IRQ0: INTREQ21 Mask */
-#define MAILBOX_IRQ0_INTREQ22_Pos 22 /*!< MAILBOX IRQ0: INTREQ22 Position */
-#define MAILBOX_IRQ0_INTREQ22_Msk (0x01UL << MAILBOX_IRQ0_INTREQ22_Pos) /*!< MAILBOX IRQ0: INTREQ22 Mask */
-#define MAILBOX_IRQ0_INTREQ23_Pos 23 /*!< MAILBOX IRQ0: INTREQ23 Position */
-#define MAILBOX_IRQ0_INTREQ23_Msk (0x01UL << MAILBOX_IRQ0_INTREQ23_Pos) /*!< MAILBOX IRQ0: INTREQ23 Mask */
-#define MAILBOX_IRQ0_INTREQ24_Pos 24 /*!< MAILBOX IRQ0: INTREQ24 Position */
-#define MAILBOX_IRQ0_INTREQ24_Msk (0x01UL << MAILBOX_IRQ0_INTREQ24_Pos) /*!< MAILBOX IRQ0: INTREQ24 Mask */
-#define MAILBOX_IRQ0_INTREQ25_Pos 25 /*!< MAILBOX IRQ0: INTREQ25 Position */
-#define MAILBOX_IRQ0_INTREQ25_Msk (0x01UL << MAILBOX_IRQ0_INTREQ25_Pos) /*!< MAILBOX IRQ0: INTREQ25 Mask */
-#define MAILBOX_IRQ0_INTREQ26_Pos 26 /*!< MAILBOX IRQ0: INTREQ26 Position */
-#define MAILBOX_IRQ0_INTREQ26_Msk (0x01UL << MAILBOX_IRQ0_INTREQ26_Pos) /*!< MAILBOX IRQ0: INTREQ26 Mask */
-#define MAILBOX_IRQ0_INTREQ27_Pos 27 /*!< MAILBOX IRQ0: INTREQ27 Position */
-#define MAILBOX_IRQ0_INTREQ27_Msk (0x01UL << MAILBOX_IRQ0_INTREQ27_Pos) /*!< MAILBOX IRQ0: INTREQ27 Mask */
-#define MAILBOX_IRQ0_INTREQ28_Pos 28 /*!< MAILBOX IRQ0: INTREQ28 Position */
-#define MAILBOX_IRQ0_INTREQ28_Msk (0x01UL << MAILBOX_IRQ0_INTREQ28_Pos) /*!< MAILBOX IRQ0: INTREQ28 Mask */
-#define MAILBOX_IRQ0_INTREQ29_Pos 29 /*!< MAILBOX IRQ0: INTREQ29 Position */
-#define MAILBOX_IRQ0_INTREQ29_Msk (0x01UL << MAILBOX_IRQ0_INTREQ29_Pos) /*!< MAILBOX IRQ0: INTREQ29 Mask */
-#define MAILBOX_IRQ0_INTREQ30_Pos 30 /*!< MAILBOX IRQ0: INTREQ30 Position */
-#define MAILBOX_IRQ0_INTREQ30_Msk (0x01UL << MAILBOX_IRQ0_INTREQ30_Pos) /*!< MAILBOX IRQ0: INTREQ30 Mask */
-#define MAILBOX_IRQ0_INTREQ31_Pos 31 /*!< MAILBOX IRQ0: INTREQ31 Position */
-#define MAILBOX_IRQ0_INTREQ31_Msk (0x01UL << MAILBOX_IRQ0_INTREQ31_Pos) /*!< MAILBOX IRQ0: INTREQ31 Mask */
-
-/* ------------------------------ u_mailbox_IRQ0SET ----------------------------- */
-#define MAILBOX_IRQ0SET_INTREQSET0_Pos 0 /*!< MAILBOX IRQ0SET: INTREQSET0 Position */
-#define MAILBOX_IRQ0SET_INTREQSET0_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET0_Pos) /*!< MAILBOX IRQ0SET: INTREQSET0 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET1_Pos 1 /*!< MAILBOX IRQ0SET: INTREQSET1 Position */
-#define MAILBOX_IRQ0SET_INTREQSET1_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET1_Pos) /*!< MAILBOX IRQ0SET: INTREQSET1 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET2_Pos 2 /*!< MAILBOX IRQ0SET: INTREQSET2 Position */
-#define MAILBOX_IRQ0SET_INTREQSET2_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET2_Pos) /*!< MAILBOX IRQ0SET: INTREQSET2 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET3_Pos 3 /*!< MAILBOX IRQ0SET: INTREQSET3 Position */
-#define MAILBOX_IRQ0SET_INTREQSET3_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET3_Pos) /*!< MAILBOX IRQ0SET: INTREQSET3 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET4_Pos 4 /*!< MAILBOX IRQ0SET: INTREQSET4 Position */
-#define MAILBOX_IRQ0SET_INTREQSET4_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET4_Pos) /*!< MAILBOX IRQ0SET: INTREQSET4 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET5_Pos 5 /*!< MAILBOX IRQ0SET: INTREQSET5 Position */
-#define MAILBOX_IRQ0SET_INTREQSET5_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET5_Pos) /*!< MAILBOX IRQ0SET: INTREQSET5 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET6_Pos 6 /*!< MAILBOX IRQ0SET: INTREQSET6 Position */
-#define MAILBOX_IRQ0SET_INTREQSET6_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET6_Pos) /*!< MAILBOX IRQ0SET: INTREQSET6 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET7_Pos 7 /*!< MAILBOX IRQ0SET: INTREQSET7 Position */
-#define MAILBOX_IRQ0SET_INTREQSET7_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET7_Pos) /*!< MAILBOX IRQ0SET: INTREQSET7 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET8_Pos 8 /*!< MAILBOX IRQ0SET: INTREQSET8 Position */
-#define MAILBOX_IRQ0SET_INTREQSET8_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET8_Pos) /*!< MAILBOX IRQ0SET: INTREQSET8 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET9_Pos 9 /*!< MAILBOX IRQ0SET: INTREQSET9 Position */
-#define MAILBOX_IRQ0SET_INTREQSET9_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET9_Pos) /*!< MAILBOX IRQ0SET: INTREQSET9 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET10_Pos 10 /*!< MAILBOX IRQ0SET: INTREQSET10 Position */
-#define MAILBOX_IRQ0SET_INTREQSET10_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET10_Pos) /*!< MAILBOX IRQ0SET: INTREQSET10 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET11_Pos 11 /*!< MAILBOX IRQ0SET: INTREQSET11 Position */
-#define MAILBOX_IRQ0SET_INTREQSET11_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET11_Pos) /*!< MAILBOX IRQ0SET: INTREQSET11 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET12_Pos 12 /*!< MAILBOX IRQ0SET: INTREQSET12 Position */
-#define MAILBOX_IRQ0SET_INTREQSET12_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET12_Pos) /*!< MAILBOX IRQ0SET: INTREQSET12 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET13_Pos 13 /*!< MAILBOX IRQ0SET: INTREQSET13 Position */
-#define MAILBOX_IRQ0SET_INTREQSET13_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET13_Pos) /*!< MAILBOX IRQ0SET: INTREQSET13 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET14_Pos 14 /*!< MAILBOX IRQ0SET: INTREQSET14 Position */
-#define MAILBOX_IRQ0SET_INTREQSET14_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET14_Pos) /*!< MAILBOX IRQ0SET: INTREQSET14 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET15_Pos 15 /*!< MAILBOX IRQ0SET: INTREQSET15 Position */
-#define MAILBOX_IRQ0SET_INTREQSET15_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET15_Pos) /*!< MAILBOX IRQ0SET: INTREQSET15 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET16_Pos 16 /*!< MAILBOX IRQ0SET: INTREQSET16 Position */
-#define MAILBOX_IRQ0SET_INTREQSET16_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET16_Pos) /*!< MAILBOX IRQ0SET: INTREQSET16 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET17_Pos 17 /*!< MAILBOX IRQ0SET: INTREQSET17 Position */
-#define MAILBOX_IRQ0SET_INTREQSET17_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET17_Pos) /*!< MAILBOX IRQ0SET: INTREQSET17 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET18_Pos 18 /*!< MAILBOX IRQ0SET: INTREQSET18 Position */
-#define MAILBOX_IRQ0SET_INTREQSET18_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET18_Pos) /*!< MAILBOX IRQ0SET: INTREQSET18 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET19_Pos 19 /*!< MAILBOX IRQ0SET: INTREQSET19 Position */
-#define MAILBOX_IRQ0SET_INTREQSET19_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET19_Pos) /*!< MAILBOX IRQ0SET: INTREQSET19 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET20_Pos 20 /*!< MAILBOX IRQ0SET: INTREQSET20 Position */
-#define MAILBOX_IRQ0SET_INTREQSET20_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET20_Pos) /*!< MAILBOX IRQ0SET: INTREQSET20 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET21_Pos 21 /*!< MAILBOX IRQ0SET: INTREQSET21 Position */
-#define MAILBOX_IRQ0SET_INTREQSET21_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET21_Pos) /*!< MAILBOX IRQ0SET: INTREQSET21 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET22_Pos 22 /*!< MAILBOX IRQ0SET: INTREQSET22 Position */
-#define MAILBOX_IRQ0SET_INTREQSET22_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET22_Pos) /*!< MAILBOX IRQ0SET: INTREQSET22 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET23_Pos 23 /*!< MAILBOX IRQ0SET: INTREQSET23 Position */
-#define MAILBOX_IRQ0SET_INTREQSET23_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET23_Pos) /*!< MAILBOX IRQ0SET: INTREQSET23 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET24_Pos 24 /*!< MAILBOX IRQ0SET: INTREQSET24 Position */
-#define MAILBOX_IRQ0SET_INTREQSET24_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET24_Pos) /*!< MAILBOX IRQ0SET: INTREQSET24 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET25_Pos 25 /*!< MAILBOX IRQ0SET: INTREQSET25 Position */
-#define MAILBOX_IRQ0SET_INTREQSET25_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET25_Pos) /*!< MAILBOX IRQ0SET: INTREQSET25 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET26_Pos 26 /*!< MAILBOX IRQ0SET: INTREQSET26 Position */
-#define MAILBOX_IRQ0SET_INTREQSET26_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET26_Pos) /*!< MAILBOX IRQ0SET: INTREQSET26 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET27_Pos 27 /*!< MAILBOX IRQ0SET: INTREQSET27 Position */
-#define MAILBOX_IRQ0SET_INTREQSET27_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET27_Pos) /*!< MAILBOX IRQ0SET: INTREQSET27 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET28_Pos 28 /*!< MAILBOX IRQ0SET: INTREQSET28 Position */
-#define MAILBOX_IRQ0SET_INTREQSET28_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET28_Pos) /*!< MAILBOX IRQ0SET: INTREQSET28 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET29_Pos 29 /*!< MAILBOX IRQ0SET: INTREQSET29 Position */
-#define MAILBOX_IRQ0SET_INTREQSET29_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET29_Pos) /*!< MAILBOX IRQ0SET: INTREQSET29 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET30_Pos 30 /*!< MAILBOX IRQ0SET: INTREQSET30 Position */
-#define MAILBOX_IRQ0SET_INTREQSET30_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET30_Pos) /*!< MAILBOX IRQ0SET: INTREQSET30 Mask */
-#define MAILBOX_IRQ0SET_INTREQSET31_Pos 31 /*!< MAILBOX IRQ0SET: INTREQSET31 Position */
-#define MAILBOX_IRQ0SET_INTREQSET31_Msk (0x01UL << MAILBOX_IRQ0SET_INTREQSET31_Pos) /*!< MAILBOX IRQ0SET: INTREQSET31 Mask */
-
-/* ------------------------------ u_mailbox_IRQ0CLR ----------------------------- */
-#define MAILBOX_IRQ0CLR_INTREQCLR0_Pos 0 /*!< MAILBOX IRQ0CLR: INTREQCLR0 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR0_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR0_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR0 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR1_Pos 1 /*!< MAILBOX IRQ0CLR: INTREQCLR1 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR1_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR1_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR1 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR2_Pos 2 /*!< MAILBOX IRQ0CLR: INTREQCLR2 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR2_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR2_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR2 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR3_Pos 3 /*!< MAILBOX IRQ0CLR: INTREQCLR3 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR3_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR3_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR3 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR4_Pos 4 /*!< MAILBOX IRQ0CLR: INTREQCLR4 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR4_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR4_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR4 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR5_Pos 5 /*!< MAILBOX IRQ0CLR: INTREQCLR5 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR5_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR5_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR5 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR6_Pos 6 /*!< MAILBOX IRQ0CLR: INTREQCLR6 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR6_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR6_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR6 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR7_Pos 7 /*!< MAILBOX IRQ0CLR: INTREQCLR7 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR7_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR7_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR7 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR8_Pos 8 /*!< MAILBOX IRQ0CLR: INTREQCLR8 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR8_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR8_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR8 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR9_Pos 9 /*!< MAILBOX IRQ0CLR: INTREQCLR9 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR9_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR9_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR9 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR10_Pos 10 /*!< MAILBOX IRQ0CLR: INTREQCLR10 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR10_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR10_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR10 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR11_Pos 11 /*!< MAILBOX IRQ0CLR: INTREQCLR11 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR11_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR11_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR11 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR12_Pos 12 /*!< MAILBOX IRQ0CLR: INTREQCLR12 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR12_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR12_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR12 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR13_Pos 13 /*!< MAILBOX IRQ0CLR: INTREQCLR13 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR13_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR13_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR13 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR14_Pos 14 /*!< MAILBOX IRQ0CLR: INTREQCLR14 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR14_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR14_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR14 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR15_Pos 15 /*!< MAILBOX IRQ0CLR: INTREQCLR15 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR15_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR15_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR15 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR16_Pos 16 /*!< MAILBOX IRQ0CLR: INTREQCLR16 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR16_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR16_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR16 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR17_Pos 17 /*!< MAILBOX IRQ0CLR: INTREQCLR17 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR17_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR17_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR17 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR18_Pos 18 /*!< MAILBOX IRQ0CLR: INTREQCLR18 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR18_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR18_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR18 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR19_Pos 19 /*!< MAILBOX IRQ0CLR: INTREQCLR19 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR19_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR19_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR19 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR20_Pos 20 /*!< MAILBOX IRQ0CLR: INTREQCLR20 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR20_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR20_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR20 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR21_Pos 21 /*!< MAILBOX IRQ0CLR: INTREQCLR21 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR21_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR21_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR21 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR22_Pos 22 /*!< MAILBOX IRQ0CLR: INTREQCLR22 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR22_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR22_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR22 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR23_Pos 23 /*!< MAILBOX IRQ0CLR: INTREQCLR23 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR23_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR23_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR23 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR24_Pos 24 /*!< MAILBOX IRQ0CLR: INTREQCLR24 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR24_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR24_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR24 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR25_Pos 25 /*!< MAILBOX IRQ0CLR: INTREQCLR25 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR25_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR25_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR25 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR26_Pos 26 /*!< MAILBOX IRQ0CLR: INTREQCLR26 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR26_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR26_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR26 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR27_Pos 27 /*!< MAILBOX IRQ0CLR: INTREQCLR27 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR27_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR27_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR27 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR28_Pos 28 /*!< MAILBOX IRQ0CLR: INTREQCLR28 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR28_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR28_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR28 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR29_Pos 29 /*!< MAILBOX IRQ0CLR: INTREQCLR29 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR29_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR29_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR29 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR30_Pos 30 /*!< MAILBOX IRQ0CLR: INTREQCLR30 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR30_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR30_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR30 Mask */
-#define MAILBOX_IRQ0CLR_INTREQCLR31_Pos 31 /*!< MAILBOX IRQ0CLR: INTREQCLR31 Position */
-#define MAILBOX_IRQ0CLR_INTREQCLR31_Msk (0x01UL << MAILBOX_IRQ0CLR_INTREQCLR31_Pos) /*!< MAILBOX IRQ0CLR: INTREQCLR31 Mask */
-
-/* ------------------------------- u_mailbox_IRQ1 ------------------------------- */
-#define MAILBOX_IRQ1_INTREQ0_Pos 0 /*!< MAILBOX IRQ1: INTREQ0 Position */
-#define MAILBOX_IRQ1_INTREQ0_Msk (0x01UL << MAILBOX_IRQ1_INTREQ0_Pos) /*!< MAILBOX IRQ1: INTREQ0 Mask */
-#define MAILBOX_IRQ1_INTREQ1_Pos 1 /*!< MAILBOX IRQ1: INTREQ1 Position */
-#define MAILBOX_IRQ1_INTREQ1_Msk (0x01UL << MAILBOX_IRQ1_INTREQ1_Pos) /*!< MAILBOX IRQ1: INTREQ1 Mask */
-#define MAILBOX_IRQ1_INTREQ2_Pos 2 /*!< MAILBOX IRQ1: INTREQ2 Position */
-#define MAILBOX_IRQ1_INTREQ2_Msk (0x01UL << MAILBOX_IRQ1_INTREQ2_Pos) /*!< MAILBOX IRQ1: INTREQ2 Mask */
-#define MAILBOX_IRQ1_INTREQ3_Pos 3 /*!< MAILBOX IRQ1: INTREQ3 Position */
-#define MAILBOX_IRQ1_INTREQ3_Msk (0x01UL << MAILBOX_IRQ1_INTREQ3_Pos) /*!< MAILBOX IRQ1: INTREQ3 Mask */
-#define MAILBOX_IRQ1_INTREQ4_Pos 4 /*!< MAILBOX IRQ1: INTREQ4 Position */
-#define MAILBOX_IRQ1_INTREQ4_Msk (0x01UL << MAILBOX_IRQ1_INTREQ4_Pos) /*!< MAILBOX IRQ1: INTREQ4 Mask */
-#define MAILBOX_IRQ1_INTREQ5_Pos 5 /*!< MAILBOX IRQ1: INTREQ5 Position */
-#define MAILBOX_IRQ1_INTREQ5_Msk (0x01UL << MAILBOX_IRQ1_INTREQ5_Pos) /*!< MAILBOX IRQ1: INTREQ5 Mask */
-#define MAILBOX_IRQ1_INTREQ6_Pos 6 /*!< MAILBOX IRQ1: INTREQ6 Position */
-#define MAILBOX_IRQ1_INTREQ6_Msk (0x01UL << MAILBOX_IRQ1_INTREQ6_Pos) /*!< MAILBOX IRQ1: INTREQ6 Mask */
-#define MAILBOX_IRQ1_INTREQ7_Pos 7 /*!< MAILBOX IRQ1: INTREQ7 Position */
-#define MAILBOX_IRQ1_INTREQ7_Msk (0x01UL << MAILBOX_IRQ1_INTREQ7_Pos) /*!< MAILBOX IRQ1: INTREQ7 Mask */
-#define MAILBOX_IRQ1_INTREQ8_Pos 8 /*!< MAILBOX IRQ1: INTREQ8 Position */
-#define MAILBOX_IRQ1_INTREQ8_Msk (0x01UL << MAILBOX_IRQ1_INTREQ8_Pos) /*!< MAILBOX IRQ1: INTREQ8 Mask */
-#define MAILBOX_IRQ1_INTREQ9_Pos 9 /*!< MAILBOX IRQ1: INTREQ9 Position */
-#define MAILBOX_IRQ1_INTREQ9_Msk (0x01UL << MAILBOX_IRQ1_INTREQ9_Pos) /*!< MAILBOX IRQ1: INTREQ9 Mask */
-#define MAILBOX_IRQ1_INTREQ10_Pos 10 /*!< MAILBOX IRQ1: INTREQ10 Position */
-#define MAILBOX_IRQ1_INTREQ10_Msk (0x01UL << MAILBOX_IRQ1_INTREQ10_Pos) /*!< MAILBOX IRQ1: INTREQ10 Mask */
-#define MAILBOX_IRQ1_INTREQ11_Pos 11 /*!< MAILBOX IRQ1: INTREQ11 Position */
-#define MAILBOX_IRQ1_INTREQ11_Msk (0x01UL << MAILBOX_IRQ1_INTREQ11_Pos) /*!< MAILBOX IRQ1: INTREQ11 Mask */
-#define MAILBOX_IRQ1_INTREQ12_Pos 12 /*!< MAILBOX IRQ1: INTREQ12 Position */
-#define MAILBOX_IRQ1_INTREQ12_Msk (0x01UL << MAILBOX_IRQ1_INTREQ12_Pos) /*!< MAILBOX IRQ1: INTREQ12 Mask */
-#define MAILBOX_IRQ1_INTREQ13_Pos 13 /*!< MAILBOX IRQ1: INTREQ13 Position */
-#define MAILBOX_IRQ1_INTREQ13_Msk (0x01UL << MAILBOX_IRQ1_INTREQ13_Pos) /*!< MAILBOX IRQ1: INTREQ13 Mask */
-#define MAILBOX_IRQ1_INTREQ14_Pos 14 /*!< MAILBOX IRQ1: INTREQ14 Position */
-#define MAILBOX_IRQ1_INTREQ14_Msk (0x01UL << MAILBOX_IRQ1_INTREQ14_Pos) /*!< MAILBOX IRQ1: INTREQ14 Mask */
-#define MAILBOX_IRQ1_INTREQ15_Pos 15 /*!< MAILBOX IRQ1: INTREQ15 Position */
-#define MAILBOX_IRQ1_INTREQ15_Msk (0x01UL << MAILBOX_IRQ1_INTREQ15_Pos) /*!< MAILBOX IRQ1: INTREQ15 Mask */
-#define MAILBOX_IRQ1_INTREQ16_Pos 16 /*!< MAILBOX IRQ1: INTREQ16 Position */
-#define MAILBOX_IRQ1_INTREQ16_Msk (0x01UL << MAILBOX_IRQ1_INTREQ16_Pos) /*!< MAILBOX IRQ1: INTREQ16 Mask */
-#define MAILBOX_IRQ1_INTREQ17_Pos 17 /*!< MAILBOX IRQ1: INTREQ17 Position */
-#define MAILBOX_IRQ1_INTREQ17_Msk (0x01UL << MAILBOX_IRQ1_INTREQ17_Pos) /*!< MAILBOX IRQ1: INTREQ17 Mask */
-#define MAILBOX_IRQ1_INTREQ18_Pos 18 /*!< MAILBOX IRQ1: INTREQ18 Position */
-#define MAILBOX_IRQ1_INTREQ18_Msk (0x01UL << MAILBOX_IRQ1_INTREQ18_Pos) /*!< MAILBOX IRQ1: INTREQ18 Mask */
-#define MAILBOX_IRQ1_INTREQ19_Pos 19 /*!< MAILBOX IRQ1: INTREQ19 Position */
-#define MAILBOX_IRQ1_INTREQ19_Msk (0x01UL << MAILBOX_IRQ1_INTREQ19_Pos) /*!< MAILBOX IRQ1: INTREQ19 Mask */
-#define MAILBOX_IRQ1_INTREQ20_Pos 20 /*!< MAILBOX IRQ1: INTREQ20 Position */
-#define MAILBOX_IRQ1_INTREQ20_Msk (0x01UL << MAILBOX_IRQ1_INTREQ20_Pos) /*!< MAILBOX IRQ1: INTREQ20 Mask */
-#define MAILBOX_IRQ1_INTREQ21_Pos 21 /*!< MAILBOX IRQ1: INTREQ21 Position */
-#define MAILBOX_IRQ1_INTREQ21_Msk (0x01UL << MAILBOX_IRQ1_INTREQ21_Pos) /*!< MAILBOX IRQ1: INTREQ21 Mask */
-#define MAILBOX_IRQ1_INTREQ22_Pos 22 /*!< MAILBOX IRQ1: INTREQ22 Position */
-#define MAILBOX_IRQ1_INTREQ22_Msk (0x01UL << MAILBOX_IRQ1_INTREQ22_Pos) /*!< MAILBOX IRQ1: INTREQ22 Mask */
-#define MAILBOX_IRQ1_INTREQ23_Pos 23 /*!< MAILBOX IRQ1: INTREQ23 Position */
-#define MAILBOX_IRQ1_INTREQ23_Msk (0x01UL << MAILBOX_IRQ1_INTREQ23_Pos) /*!< MAILBOX IRQ1: INTREQ23 Mask */
-#define MAILBOX_IRQ1_INTREQ24_Pos 24 /*!< MAILBOX IRQ1: INTREQ24 Position */
-#define MAILBOX_IRQ1_INTREQ24_Msk (0x01UL << MAILBOX_IRQ1_INTREQ24_Pos) /*!< MAILBOX IRQ1: INTREQ24 Mask */
-#define MAILBOX_IRQ1_INTREQ25_Pos 25 /*!< MAILBOX IRQ1: INTREQ25 Position */
-#define MAILBOX_IRQ1_INTREQ25_Msk (0x01UL << MAILBOX_IRQ1_INTREQ25_Pos) /*!< MAILBOX IRQ1: INTREQ25 Mask */
-#define MAILBOX_IRQ1_INTREQ26_Pos 26 /*!< MAILBOX IRQ1: INTREQ26 Position */
-#define MAILBOX_IRQ1_INTREQ26_Msk (0x01UL << MAILBOX_IRQ1_INTREQ26_Pos) /*!< MAILBOX IRQ1: INTREQ26 Mask */
-#define MAILBOX_IRQ1_INTREQ27_Pos 27 /*!< MAILBOX IRQ1: INTREQ27 Position */
-#define MAILBOX_IRQ1_INTREQ27_Msk (0x01UL << MAILBOX_IRQ1_INTREQ27_Pos) /*!< MAILBOX IRQ1: INTREQ27 Mask */
-#define MAILBOX_IRQ1_INTREQ28_Pos 28 /*!< MAILBOX IRQ1: INTREQ28 Position */
-#define MAILBOX_IRQ1_INTREQ28_Msk (0x01UL << MAILBOX_IRQ1_INTREQ28_Pos) /*!< MAILBOX IRQ1: INTREQ28 Mask */
-#define MAILBOX_IRQ1_INTREQ29_Pos 29 /*!< MAILBOX IRQ1: INTREQ29 Position */
-#define MAILBOX_IRQ1_INTREQ29_Msk (0x01UL << MAILBOX_IRQ1_INTREQ29_Pos) /*!< MAILBOX IRQ1: INTREQ29 Mask */
-#define MAILBOX_IRQ1_INTREQ30_Pos 30 /*!< MAILBOX IRQ1: INTREQ30 Position */
-#define MAILBOX_IRQ1_INTREQ30_Msk (0x01UL << MAILBOX_IRQ1_INTREQ30_Pos) /*!< MAILBOX IRQ1: INTREQ30 Mask */
-#define MAILBOX_IRQ1_INTREQ31_Pos 31 /*!< MAILBOX IRQ1: INTREQ31 Position */
-#define MAILBOX_IRQ1_INTREQ31_Msk (0x01UL << MAILBOX_IRQ1_INTREQ31_Pos) /*!< MAILBOX IRQ1: INTREQ31 Mask */
-
-/* ------------------------------ u_mailbox_IRQ1SET ----------------------------- */
-#define MAILBOX_IRQ1SET_INTREQSET0_Pos 0 /*!< MAILBOX IRQ1SET: INTREQSET0 Position */
-#define MAILBOX_IRQ1SET_INTREQSET0_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET0_Pos) /*!< MAILBOX IRQ1SET: INTREQSET0 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET1_Pos 1 /*!< MAILBOX IRQ1SET: INTREQSET1 Position */
-#define MAILBOX_IRQ1SET_INTREQSET1_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET1_Pos) /*!< MAILBOX IRQ1SET: INTREQSET1 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET2_Pos 2 /*!< MAILBOX IRQ1SET: INTREQSET2 Position */
-#define MAILBOX_IRQ1SET_INTREQSET2_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET2_Pos) /*!< MAILBOX IRQ1SET: INTREQSET2 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET3_Pos 3 /*!< MAILBOX IRQ1SET: INTREQSET3 Position */
-#define MAILBOX_IRQ1SET_INTREQSET3_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET3_Pos) /*!< MAILBOX IRQ1SET: INTREQSET3 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET4_Pos 4 /*!< MAILBOX IRQ1SET: INTREQSET4 Position */
-#define MAILBOX_IRQ1SET_INTREQSET4_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET4_Pos) /*!< MAILBOX IRQ1SET: INTREQSET4 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET5_Pos 5 /*!< MAILBOX IRQ1SET: INTREQSET5 Position */
-#define MAILBOX_IRQ1SET_INTREQSET5_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET5_Pos) /*!< MAILBOX IRQ1SET: INTREQSET5 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET6_Pos 6 /*!< MAILBOX IRQ1SET: INTREQSET6 Position */
-#define MAILBOX_IRQ1SET_INTREQSET6_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET6_Pos) /*!< MAILBOX IRQ1SET: INTREQSET6 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET7_Pos 7 /*!< MAILBOX IRQ1SET: INTREQSET7 Position */
-#define MAILBOX_IRQ1SET_INTREQSET7_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET7_Pos) /*!< MAILBOX IRQ1SET: INTREQSET7 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET8_Pos 8 /*!< MAILBOX IRQ1SET: INTREQSET8 Position */
-#define MAILBOX_IRQ1SET_INTREQSET8_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET8_Pos) /*!< MAILBOX IRQ1SET: INTREQSET8 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET9_Pos 9 /*!< MAILBOX IRQ1SET: INTREQSET9 Position */
-#define MAILBOX_IRQ1SET_INTREQSET9_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET9_Pos) /*!< MAILBOX IRQ1SET: INTREQSET9 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET10_Pos 10 /*!< MAILBOX IRQ1SET: INTREQSET10 Position */
-#define MAILBOX_IRQ1SET_INTREQSET10_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET10_Pos) /*!< MAILBOX IRQ1SET: INTREQSET10 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET11_Pos 11 /*!< MAILBOX IRQ1SET: INTREQSET11 Position */
-#define MAILBOX_IRQ1SET_INTREQSET11_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET11_Pos) /*!< MAILBOX IRQ1SET: INTREQSET11 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET12_Pos 12 /*!< MAILBOX IRQ1SET: INTREQSET12 Position */
-#define MAILBOX_IRQ1SET_INTREQSET12_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET12_Pos) /*!< MAILBOX IRQ1SET: INTREQSET12 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET13_Pos 13 /*!< MAILBOX IRQ1SET: INTREQSET13 Position */
-#define MAILBOX_IRQ1SET_INTREQSET13_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET13_Pos) /*!< MAILBOX IRQ1SET: INTREQSET13 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET14_Pos 14 /*!< MAILBOX IRQ1SET: INTREQSET14 Position */
-#define MAILBOX_IRQ1SET_INTREQSET14_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET14_Pos) /*!< MAILBOX IRQ1SET: INTREQSET14 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET15_Pos 15 /*!< MAILBOX IRQ1SET: INTREQSET15 Position */
-#define MAILBOX_IRQ1SET_INTREQSET15_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET15_Pos) /*!< MAILBOX IRQ1SET: INTREQSET15 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET16_Pos 16 /*!< MAILBOX IRQ1SET: INTREQSET16 Position */
-#define MAILBOX_IRQ1SET_INTREQSET16_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET16_Pos) /*!< MAILBOX IRQ1SET: INTREQSET16 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET17_Pos 17 /*!< MAILBOX IRQ1SET: INTREQSET17 Position */
-#define MAILBOX_IRQ1SET_INTREQSET17_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET17_Pos) /*!< MAILBOX IRQ1SET: INTREQSET17 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET18_Pos 18 /*!< MAILBOX IRQ1SET: INTREQSET18 Position */
-#define MAILBOX_IRQ1SET_INTREQSET18_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET18_Pos) /*!< MAILBOX IRQ1SET: INTREQSET18 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET19_Pos 19 /*!< MAILBOX IRQ1SET: INTREQSET19 Position */
-#define MAILBOX_IRQ1SET_INTREQSET19_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET19_Pos) /*!< MAILBOX IRQ1SET: INTREQSET19 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET20_Pos 20 /*!< MAILBOX IRQ1SET: INTREQSET20 Position */
-#define MAILBOX_IRQ1SET_INTREQSET20_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET20_Pos) /*!< MAILBOX IRQ1SET: INTREQSET20 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET21_Pos 21 /*!< MAILBOX IRQ1SET: INTREQSET21 Position */
-#define MAILBOX_IRQ1SET_INTREQSET21_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET21_Pos) /*!< MAILBOX IRQ1SET: INTREQSET21 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET22_Pos 22 /*!< MAILBOX IRQ1SET: INTREQSET22 Position */
-#define MAILBOX_IRQ1SET_INTREQSET22_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET22_Pos) /*!< MAILBOX IRQ1SET: INTREQSET22 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET23_Pos 23 /*!< MAILBOX IRQ1SET: INTREQSET23 Position */
-#define MAILBOX_IRQ1SET_INTREQSET23_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET23_Pos) /*!< MAILBOX IRQ1SET: INTREQSET23 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET24_Pos 24 /*!< MAILBOX IRQ1SET: INTREQSET24 Position */
-#define MAILBOX_IRQ1SET_INTREQSET24_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET24_Pos) /*!< MAILBOX IRQ1SET: INTREQSET24 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET25_Pos 25 /*!< MAILBOX IRQ1SET: INTREQSET25 Position */
-#define MAILBOX_IRQ1SET_INTREQSET25_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET25_Pos) /*!< MAILBOX IRQ1SET: INTREQSET25 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET26_Pos 26 /*!< MAILBOX IRQ1SET: INTREQSET26 Position */
-#define MAILBOX_IRQ1SET_INTREQSET26_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET26_Pos) /*!< MAILBOX IRQ1SET: INTREQSET26 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET27_Pos 27 /*!< MAILBOX IRQ1SET: INTREQSET27 Position */
-#define MAILBOX_IRQ1SET_INTREQSET27_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET27_Pos) /*!< MAILBOX IRQ1SET: INTREQSET27 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET28_Pos 28 /*!< MAILBOX IRQ1SET: INTREQSET28 Position */
-#define MAILBOX_IRQ1SET_INTREQSET28_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET28_Pos) /*!< MAILBOX IRQ1SET: INTREQSET28 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET29_Pos 29 /*!< MAILBOX IRQ1SET: INTREQSET29 Position */
-#define MAILBOX_IRQ1SET_INTREQSET29_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET29_Pos) /*!< MAILBOX IRQ1SET: INTREQSET29 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET30_Pos 30 /*!< MAILBOX IRQ1SET: INTREQSET30 Position */
-#define MAILBOX_IRQ1SET_INTREQSET30_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET30_Pos) /*!< MAILBOX IRQ1SET: INTREQSET30 Mask */
-#define MAILBOX_IRQ1SET_INTREQSET31_Pos 31 /*!< MAILBOX IRQ1SET: INTREQSET31 Position */
-#define MAILBOX_IRQ1SET_INTREQSET31_Msk (0x01UL << MAILBOX_IRQ1SET_INTREQSET31_Pos) /*!< MAILBOX IRQ1SET: INTREQSET31 Mask */
-
-/* ------------------------------ u_mailbox_IRQ1CLR ----------------------------- */
-#define MAILBOX_IRQ1CLR_INTREQCLR0_Pos 0 /*!< MAILBOX IRQ1CLR: INTREQCLR0 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR0_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR0_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR0 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR1_Pos 1 /*!< MAILBOX IRQ1CLR: INTREQCLR1 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR1_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR1_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR1 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR2_Pos 2 /*!< MAILBOX IRQ1CLR: INTREQCLR2 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR2_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR2_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR2 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR3_Pos 3 /*!< MAILBOX IRQ1CLR: INTREQCLR3 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR3_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR3_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR3 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR4_Pos 4 /*!< MAILBOX IRQ1CLR: INTREQCLR4 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR4_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR4_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR4 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR5_Pos 5 /*!< MAILBOX IRQ1CLR: INTREQCLR5 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR5_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR5_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR5 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR6_Pos 6 /*!< MAILBOX IRQ1CLR: INTREQCLR6 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR6_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR6_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR6 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR7_Pos 7 /*!< MAILBOX IRQ1CLR: INTREQCLR7 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR7_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR7_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR7 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR8_Pos 8 /*!< MAILBOX IRQ1CLR: INTREQCLR8 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR8_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR8_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR8 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR9_Pos 9 /*!< MAILBOX IRQ1CLR: INTREQCLR9 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR9_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR9_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR9 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR10_Pos 10 /*!< MAILBOX IRQ1CLR: INTREQCLR10 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR10_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR10_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR10 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR11_Pos 11 /*!< MAILBOX IRQ1CLR: INTREQCLR11 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR11_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR11_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR11 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR12_Pos 12 /*!< MAILBOX IRQ1CLR: INTREQCLR12 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR12_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR12_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR12 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR13_Pos 13 /*!< MAILBOX IRQ1CLR: INTREQCLR13 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR13_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR13_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR13 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR14_Pos 14 /*!< MAILBOX IRQ1CLR: INTREQCLR14 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR14_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR14_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR14 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR15_Pos 15 /*!< MAILBOX IRQ1CLR: INTREQCLR15 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR15_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR15_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR15 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR16_Pos 16 /*!< MAILBOX IRQ1CLR: INTREQCLR16 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR16_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR16_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR16 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR17_Pos 17 /*!< MAILBOX IRQ1CLR: INTREQCLR17 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR17_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR17_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR17 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR18_Pos 18 /*!< MAILBOX IRQ1CLR: INTREQCLR18 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR18_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR18_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR18 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR19_Pos 19 /*!< MAILBOX IRQ1CLR: INTREQCLR19 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR19_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR19_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR19 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR20_Pos 20 /*!< MAILBOX IRQ1CLR: INTREQCLR20 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR20_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR20_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR20 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR21_Pos 21 /*!< MAILBOX IRQ1CLR: INTREQCLR21 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR21_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR21_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR21 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR22_Pos 22 /*!< MAILBOX IRQ1CLR: INTREQCLR22 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR22_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR22_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR22 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR23_Pos 23 /*!< MAILBOX IRQ1CLR: INTREQCLR23 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR23_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR23_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR23 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR24_Pos 24 /*!< MAILBOX IRQ1CLR: INTREQCLR24 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR24_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR24_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR24 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR25_Pos 25 /*!< MAILBOX IRQ1CLR: INTREQCLR25 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR25_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR25_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR25 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR26_Pos 26 /*!< MAILBOX IRQ1CLR: INTREQCLR26 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR26_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR26_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR26 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR27_Pos 27 /*!< MAILBOX IRQ1CLR: INTREQCLR27 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR27_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR27_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR27 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR28_Pos 28 /*!< MAILBOX IRQ1CLR: INTREQCLR28 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR28_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR28_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR28 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR29_Pos 29 /*!< MAILBOX IRQ1CLR: INTREQCLR29 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR29_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR29_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR29 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR30_Pos 30 /*!< MAILBOX IRQ1CLR: INTREQCLR30 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR30_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR30_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR30 Mask */
-#define MAILBOX_IRQ1CLR_INTREQCLR31_Pos 31 /*!< MAILBOX IRQ1CLR: INTREQCLR31 Position */
-#define MAILBOX_IRQ1CLR_INTREQCLR31_Msk (0x01UL << MAILBOX_IRQ1CLR_INTREQCLR31_Pos) /*!< MAILBOX IRQ1CLR: INTREQCLR31 Mask */
-
-/* ------------------------------- u_mailbox_MUTEX ------------------------------ */
-#define MAILBOX_MUTEX_EX_Pos 0 /*!< MAILBOX MUTEX: EX Position */
-#define MAILBOX_MUTEX_EX_Msk (0x01UL << MAILBOX_MUTEX_EX_Pos) /*!< MAILBOX MUTEX: EX Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u_adc' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* --------------------------------- u_adc_CTRL --------------------------------- */
-#define ADC_CTRL_CLKDIV_Pos 0 /*!< ADC CTRL: CLKDIV Position */
-#define ADC_CTRL_CLKDIV_Msk (0x000000ffUL << ADC_CTRL_CLKDIV_Pos) /*!< ADC CTRL: CLKDIV Mask */
-#define ADC_CTRL_ASYNMODE_Pos 8 /*!< ADC CTRL: ASYNMODE Position */
-#define ADC_CTRL_ASYNMODE_Msk (0x01UL << ADC_CTRL_ASYNMODE_Pos) /*!< ADC CTRL: ASYNMODE Mask */
-#define ADC_CTRL_RESOL_Pos 9 /*!< ADC CTRL: RESOL Position */
-#define ADC_CTRL_RESOL_Msk (0x03UL << ADC_CTRL_RESOL_Pos) /*!< ADC CTRL: RESOL Mask */
-#define ADC_CTRL_RESOL_MASK_DIS_Pos 11 /*!< ADC CTRL: RESOL_MASK_DIS Position */
-#define ADC_CTRL_RESOL_MASK_DIS_Msk (0x01UL << ADC_CTRL_RESOL_MASK_DIS_Pos) /*!< ADC CTRL: RESOL_MASK_DIS Mask */
-#define ADC_CTRL_TSAMP_Pos 12 /*!< ADC CTRL: TSAMP Position */
-#define ADC_CTRL_TSAMP_Msk (0x07UL << ADC_CTRL_TSAMP_Pos) /*!< ADC CTRL: TSAMP Mask */
-
-/* --------------------------------- u_adc_INSEL -------------------------------- */
-#define ADC_INSEL_INSEL_Pos 0 /*!< ADC INSEL: INSEL Position */
-#define ADC_INSEL_INSEL_Msk (0xffffffffUL << ADC_INSEL_INSEL_Pos) /*!< ADC INSEL: INSEL Mask */
-
-/* ------------------------------- u_adc_SEQA_CTRL ------------------------------ */
-#define ADC_SEQA_CTRL_CHANNELS_Pos 0 /*!< ADC SEQA_CTRL: CHANNELS Position */
-#define ADC_SEQA_CTRL_CHANNELS_Msk (0x000000ffUL << ADC_SEQA_CTRL_CHANNELS_Pos) /*!< ADC SEQA_CTRL: CHANNELS Mask */
-#define ADC_SEQA_CTRL_TRIGGER_Pos 12 /*!< ADC SEQA_CTRL: TRIGGER Position */
-#define ADC_SEQA_CTRL_TRIGGER_Msk (0x3fUL << ADC_SEQA_CTRL_TRIGGER_Pos) /*!< ADC SEQA_CTRL: TRIGGER Mask */
-#define ADC_SEQA_CTRL_TRIGPOL_Pos 18 /*!< ADC SEQA_CTRL: TRIGPOL Position */
-#define ADC_SEQA_CTRL_TRIGPOL_Msk (0x01UL << ADC_SEQA_CTRL_TRIGPOL_Pos) /*!< ADC SEQA_CTRL: TRIGPOL Mask */
-#define ADC_SEQA_CTRL_SYNCBYPASS_Pos 19 /*!< ADC SEQA_CTRL: SYNCBYPASS Position */
-#define ADC_SEQA_CTRL_SYNCBYPASS_Msk (0x01UL << ADC_SEQA_CTRL_SYNCBYPASS_Pos) /*!< ADC SEQA_CTRL: SYNCBYPASS Mask */
-#define ADC_SEQA_CTRL_START_BEHAVIOUR_Pos 25 /*!< ADC SEQA_CTRL: START_BEHAVIOUR Position */
-#define ADC_SEQA_CTRL_START_BEHAVIOUR_Msk (0x01UL << ADC_SEQA_CTRL_START_BEHAVIOUR_Pos) /*!< ADC SEQA_CTRL: START_BEHAVIOUR Mask */
-#define ADC_SEQA_CTRL_START_Pos 26 /*!< ADC SEQA_CTRL: START Position */
-#define ADC_SEQA_CTRL_START_Msk (0x01UL << ADC_SEQA_CTRL_START_Pos) /*!< ADC SEQA_CTRL: START Mask */
-#define ADC_SEQA_CTRL_BURST_Pos 27 /*!< ADC SEQA_CTRL: BURST Position */
-#define ADC_SEQA_CTRL_BURST_Msk (0x01UL << ADC_SEQA_CTRL_BURST_Pos) /*!< ADC SEQA_CTRL: BURST Mask */
-#define ADC_SEQA_CTRL_SINGLESTEP_Pos 28 /*!< ADC SEQA_CTRL: SINGLESTEP Position */
-#define ADC_SEQA_CTRL_SINGLESTEP_Msk (0x01UL << ADC_SEQA_CTRL_SINGLESTEP_Pos) /*!< ADC SEQA_CTRL: SINGLESTEP Mask */
-#define ADC_SEQA_CTRL_LOWPRIO_Pos 29 /*!< ADC SEQA_CTRL: LOWPRIO Position */
-#define ADC_SEQA_CTRL_LOWPRIO_Msk (0x01UL << ADC_SEQA_CTRL_LOWPRIO_Pos) /*!< ADC SEQA_CTRL: LOWPRIO Mask */
-#define ADC_SEQA_CTRL_MODE_Pos 30 /*!< ADC SEQA_CTRL: MODE Position */
-#define ADC_SEQA_CTRL_MODE_Msk (0x01UL << ADC_SEQA_CTRL_MODE_Pos) /*!< ADC SEQA_CTRL: MODE Mask */
-#define ADC_SEQA_CTRL_SEQA_ENA_Pos 31 /*!< ADC SEQA_CTRL: SEQA_ENA Position */
-#define ADC_SEQA_CTRL_SEQA_ENA_Msk (0x01UL << ADC_SEQA_CTRL_SEQA_ENA_Pos) /*!< ADC SEQA_CTRL: SEQA_ENA Mask */
-
-/* ------------------------------- u_adc_SEQB_CTRL ------------------------------ */
-#define ADC_SEQB_CTRL_CHANNELS_Pos 0 /*!< ADC SEQB_CTRL: CHANNELS Position */
-#define ADC_SEQB_CTRL_CHANNELS_Msk (0x000000ffUL << ADC_SEQB_CTRL_CHANNELS_Pos) /*!< ADC SEQB_CTRL: CHANNELS Mask */
-#define ADC_SEQB_CTRL_TRIGGER_Pos 12 /*!< ADC SEQB_CTRL: TRIGGER Position */
-#define ADC_SEQB_CTRL_TRIGGER_Msk (0x3fUL << ADC_SEQB_CTRL_TRIGGER_Pos) /*!< ADC SEQB_CTRL: TRIGGER Mask */
-#define ADC_SEQB_CTRL_TRIGPOL_Pos 18 /*!< ADC SEQB_CTRL: TRIGPOL Position */
-#define ADC_SEQB_CTRL_TRIGPOL_Msk (0x01UL << ADC_SEQB_CTRL_TRIGPOL_Pos) /*!< ADC SEQB_CTRL: TRIGPOL Mask */
-#define ADC_SEQB_CTRL_SYNCBYPASS_Pos 19 /*!< ADC SEQB_CTRL: SYNCBYPASS Position */
-#define ADC_SEQB_CTRL_SYNCBYPASS_Msk (0x01UL << ADC_SEQB_CTRL_SYNCBYPASS_Pos) /*!< ADC SEQB_CTRL: SYNCBYPASS Mask */
-#define ADC_SEQB_CTRL_START_BEHAVIOUR_Pos 25 /*!< ADC SEQB_CTRL: START_BEHAVIOUR Position */
-#define ADC_SEQB_CTRL_START_BEHAVIOUR_Msk (0x01UL << ADC_SEQB_CTRL_START_BEHAVIOUR_Pos) /*!< ADC SEQB_CTRL: START_BEHAVIOUR Mask */
-#define ADC_SEQB_CTRL_START_Pos 26 /*!< ADC SEQB_CTRL: START Position */
-#define ADC_SEQB_CTRL_START_Msk (0x01UL << ADC_SEQB_CTRL_START_Pos) /*!< ADC SEQB_CTRL: START Mask */
-#define ADC_SEQB_CTRL_BURST_Pos 27 /*!< ADC SEQB_CTRL: BURST Position */
-#define ADC_SEQB_CTRL_BURST_Msk (0x01UL << ADC_SEQB_CTRL_BURST_Pos) /*!< ADC SEQB_CTRL: BURST Mask */
-#define ADC_SEQB_CTRL_SINGLESTEP_Pos 28 /*!< ADC SEQB_CTRL: SINGLESTEP Position */
-#define ADC_SEQB_CTRL_SINGLESTEP_Msk (0x01UL << ADC_SEQB_CTRL_SINGLESTEP_Pos) /*!< ADC SEQB_CTRL: SINGLESTEP Mask */
-#define ADC_SEQB_CTRL_MODE_Pos 30 /*!< ADC SEQB_CTRL: MODE Position */
-#define ADC_SEQB_CTRL_MODE_Msk (0x01UL << ADC_SEQB_CTRL_MODE_Pos) /*!< ADC SEQB_CTRL: MODE Mask */
-#define ADC_SEQB_CTRL_SEQB_ENA_Pos 31 /*!< ADC SEQB_CTRL: SEQB_ENA Position */
-#define ADC_SEQB_CTRL_SEQB_ENA_Msk (0x01UL << ADC_SEQB_CTRL_SEQB_ENA_Pos) /*!< ADC SEQB_CTRL: SEQB_ENA Mask */
-
-/* ------------------------------- u_adc_SEQA_GDAT ------------------------------ */
-#define ADC_SEQA_GDAT_RESULT_Pos 4 /*!< ADC SEQA_GDAT: RESULT Position */
-#define ADC_SEQA_GDAT_RESULT_Msk (0x00000fffUL << ADC_SEQA_GDAT_RESULT_Pos) /*!< ADC SEQA_GDAT: RESULT Mask */
-#define ADC_SEQA_GDAT_THCMPRANGE_Pos 16 /*!< ADC SEQA_GDAT: THCMPRANGE Position */
-#define ADC_SEQA_GDAT_THCMPRANGE_Msk (0x03UL << ADC_SEQA_GDAT_THCMPRANGE_Pos) /*!< ADC SEQA_GDAT: THCMPRANGE Mask */
-#define ADC_SEQA_GDAT_THCMPCROSS_Pos 18 /*!< ADC SEQA_GDAT: THCMPCROSS Position */
-#define ADC_SEQA_GDAT_THCMPCROSS_Msk (0x03UL << ADC_SEQA_GDAT_THCMPCROSS_Pos) /*!< ADC SEQA_GDAT: THCMPCROSS Mask */
-#define ADC_SEQA_GDAT_CHN_Pos 26 /*!< ADC SEQA_GDAT: CHN Position */
-#define ADC_SEQA_GDAT_CHN_Msk (0x0fUL << ADC_SEQA_GDAT_CHN_Pos) /*!< ADC SEQA_GDAT: CHN Mask */
-#define ADC_SEQA_GDAT_OVERRUN_Pos 30 /*!< ADC SEQA_GDAT: OVERRUN Position */
-#define ADC_SEQA_GDAT_OVERRUN_Msk (0x01UL << ADC_SEQA_GDAT_OVERRUN_Pos) /*!< ADC SEQA_GDAT: OVERRUN Mask */
-#define ADC_SEQA_GDAT_DATAVALID_Pos 31 /*!< ADC SEQA_GDAT: DATAVALID Position */
-#define ADC_SEQA_GDAT_DATAVALID_Msk (0x01UL << ADC_SEQA_GDAT_DATAVALID_Pos) /*!< ADC SEQA_GDAT: DATAVALID Mask */
-
-/* ------------------------------- u_adc_SEQB_GDAT ------------------------------ */
-#define ADC_SEQB_GDAT_RESULT_Pos 4 /*!< ADC SEQB_GDAT: RESULT Position */
-#define ADC_SEQB_GDAT_RESULT_Msk (0x00000fffUL << ADC_SEQB_GDAT_RESULT_Pos) /*!< ADC SEQB_GDAT: RESULT Mask */
-#define ADC_SEQB_GDAT_THCMPRANGE_Pos 16 /*!< ADC SEQB_GDAT: THCMPRANGE Position */
-#define ADC_SEQB_GDAT_THCMPRANGE_Msk (0x03UL << ADC_SEQB_GDAT_THCMPRANGE_Pos) /*!< ADC SEQB_GDAT: THCMPRANGE Mask */
-#define ADC_SEQB_GDAT_THCMPCROSS_Pos 18 /*!< ADC SEQB_GDAT: THCMPCROSS Position */
-#define ADC_SEQB_GDAT_THCMPCROSS_Msk (0x03UL << ADC_SEQB_GDAT_THCMPCROSS_Pos) /*!< ADC SEQB_GDAT: THCMPCROSS Mask */
-#define ADC_SEQB_GDAT_CHN_Pos 26 /*!< ADC SEQB_GDAT: CHN Position */
-#define ADC_SEQB_GDAT_CHN_Msk (0x0fUL << ADC_SEQB_GDAT_CHN_Pos) /*!< ADC SEQB_GDAT: CHN Mask */
-#define ADC_SEQB_GDAT_OVERRUN_Pos 30 /*!< ADC SEQB_GDAT: OVERRUN Position */
-#define ADC_SEQB_GDAT_OVERRUN_Msk (0x01UL << ADC_SEQB_GDAT_OVERRUN_Pos) /*!< ADC SEQB_GDAT: OVERRUN Mask */
-#define ADC_SEQB_GDAT_DATAVALID_Pos 31 /*!< ADC SEQB_GDAT: DATAVALID Position */
-#define ADC_SEQB_GDAT_DATAVALID_Msk (0x01UL << ADC_SEQB_GDAT_DATAVALID_Pos) /*!< ADC SEQB_GDAT: DATAVALID Mask */
-
-/* ---------------------------------- u_adc_DAT --------------------------------- */
-#define ADC_DAT_RESULT_Pos 4 /*!< ADC DAT: RESULT Position */
-#define ADC_DAT_RESULT_Msk (0x00000fffUL << ADC_DAT_RESULT_Pos) /*!< ADC DAT: RESULT Mask */
-#define ADC_DAT_THCMPRANGE_Pos 16 /*!< ADC DAT: THCMPRANGE Position */
-#define ADC_DAT_THCMPRANGE_Msk (0x03UL << ADC_DAT_THCMPRANGE_Pos) /*!< ADC DAT: THCMPRANGE Mask */
-#define ADC_DAT_THCMPCROSS_Pos 18 /*!< ADC DAT: THCMPCROSS Position */
-#define ADC_DAT_THCMPCROSS_Msk (0x03UL << ADC_DAT_THCMPCROSS_Pos) /*!< ADC DAT: THCMPCROSS Mask */
-#define ADC_DAT_CHN_Pos 26 /*!< ADC DAT: CHN Position */
-#define ADC_DAT_CHN_Msk (0x0fUL << ADC_DAT_CHN_Pos) /*!< ADC DAT: CHN Mask */
-#define ADC_DAT_OVERRUN_Pos 30 /*!< ADC DAT: OVERRUN Position */
-#define ADC_DAT_OVERRUN_Msk (0x01UL << ADC_DAT_OVERRUN_Pos) /*!< ADC DAT: OVERRUN Mask */
-#define ADC_DAT_DATAVALID_Pos 31 /*!< ADC DAT: DATAVALID Position */
-#define ADC_DAT_DATAVALID_Msk (0x01UL << ADC_DAT_DATAVALID_Pos) /*!< ADC DAT: DATAVALID Mask */
-
-/* ------------------------------- u_adc_THR0_LOW ------------------------------- */
-#define ADC_THR0_LOW_THRLOW_Pos 4 /*!< ADC THR0_LOW: THRLOW Position */
-#define ADC_THR0_LOW_THRLOW_Msk (0x00000fffUL << ADC_THR0_LOW_THRLOW_Pos) /*!< ADC THR0_LOW: THRLOW Mask */
-
-/* ------------------------------- u_adc_THR1_LOW ------------------------------- */
-#define ADC_THR1_LOW_THRLOW_Pos 4 /*!< ADC THR1_LOW: THRLOW Position */
-#define ADC_THR1_LOW_THRLOW_Msk (0x00000fffUL << ADC_THR1_LOW_THRLOW_Pos) /*!< ADC THR1_LOW: THRLOW Mask */
-
-/* ------------------------------- u_adc_THR0_HIGH ------------------------------ */
-#define ADC_THR0_HIGH_THRHIGH_Pos 4 /*!< ADC THR0_HIGH: THRHIGH Position */
-#define ADC_THR0_HIGH_THRHIGH_Msk (0x00000fffUL << ADC_THR0_HIGH_THRHIGH_Pos) /*!< ADC THR0_HIGH: THRHIGH Mask */
-
-/* ------------------------------- u_adc_THR1_HIGH ------------------------------ */
-#define ADC_THR1_HIGH_THRHIGH_Pos 4 /*!< ADC THR1_HIGH: THRHIGH Position */
-#define ADC_THR1_HIGH_THRHIGH_Msk (0x00000fffUL << ADC_THR1_HIGH_THRHIGH_Pos) /*!< ADC THR1_HIGH: THRHIGH Mask */
-
-/* ------------------------------ u_adc_CHAN_THRSEL ----------------------------- */
-#define ADC_CHAN_THRSEL_CH0_THRSEL_Pos 0 /*!< ADC CHAN_THRSEL: CH0_THRSEL Position */
-#define ADC_CHAN_THRSEL_CH0_THRSEL_Msk (0x01UL << ADC_CHAN_THRSEL_CH0_THRSEL_Pos) /*!< ADC CHAN_THRSEL: CH0_THRSEL Mask */
-#define ADC_CHAN_THRSEL_CH1_THRSEL_Pos 1 /*!< ADC CHAN_THRSEL: CH1_THRSEL Position */
-#define ADC_CHAN_THRSEL_CH1_THRSEL_Msk (0x01UL << ADC_CHAN_THRSEL_CH1_THRSEL_Pos) /*!< ADC CHAN_THRSEL: CH1_THRSEL Mask */
-#define ADC_CHAN_THRSEL_CH2_THRSEL_Pos 2 /*!< ADC CHAN_THRSEL: CH2_THRSEL Position */
-#define ADC_CHAN_THRSEL_CH2_THRSEL_Msk (0x01UL << ADC_CHAN_THRSEL_CH2_THRSEL_Pos) /*!< ADC CHAN_THRSEL: CH2_THRSEL Mask */
-#define ADC_CHAN_THRSEL_CH3_THRSEL_Pos 3 /*!< ADC CHAN_THRSEL: CH3_THRSEL Position */
-#define ADC_CHAN_THRSEL_CH3_THRSEL_Msk (0x01UL << ADC_CHAN_THRSEL_CH3_THRSEL_Pos) /*!< ADC CHAN_THRSEL: CH3_THRSEL Mask */
-#define ADC_CHAN_THRSEL_CH4_THRSEL_Pos 4 /*!< ADC CHAN_THRSEL: CH4_THRSEL Position */
-#define ADC_CHAN_THRSEL_CH4_THRSEL_Msk (0x01UL << ADC_CHAN_THRSEL_CH4_THRSEL_Pos) /*!< ADC CHAN_THRSEL: CH4_THRSEL Mask */
-#define ADC_CHAN_THRSEL_CH5_THRSEL_Pos 5 /*!< ADC CHAN_THRSEL: CH5_THRSEL Position */
-#define ADC_CHAN_THRSEL_CH5_THRSEL_Msk (0x01UL << ADC_CHAN_THRSEL_CH5_THRSEL_Pos) /*!< ADC CHAN_THRSEL: CH5_THRSEL Mask */
-#define ADC_CHAN_THRSEL_CH6_THRSEL_Pos 6 /*!< ADC CHAN_THRSEL: CH6_THRSEL Position */
-#define ADC_CHAN_THRSEL_CH6_THRSEL_Msk (0x01UL << ADC_CHAN_THRSEL_CH6_THRSEL_Pos) /*!< ADC CHAN_THRSEL: CH6_THRSEL Mask */
-#define ADC_CHAN_THRSEL_CH7_THRSEL_Pos 7 /*!< ADC CHAN_THRSEL: CH7_THRSEL Position */
-#define ADC_CHAN_THRSEL_CH7_THRSEL_Msk (0x01UL << ADC_CHAN_THRSEL_CH7_THRSEL_Pos) /*!< ADC CHAN_THRSEL: CH7_THRSEL Mask */
-
-/* --------------------------------- u_adc_INTEN -------------------------------- */
-#define ADC_INTEN_SEQA_INTEN_Pos 0 /*!< ADC INTEN: SEQA_INTEN Position */
-#define ADC_INTEN_SEQA_INTEN_Msk (0x01UL << ADC_INTEN_SEQA_INTEN_Pos) /*!< ADC INTEN: SEQA_INTEN Mask */
-#define ADC_INTEN_SEQB_INTEN_Pos 1 /*!< ADC INTEN: SEQB_INTEN Position */
-#define ADC_INTEN_SEQB_INTEN_Msk (0x01UL << ADC_INTEN_SEQB_INTEN_Pos) /*!< ADC INTEN: SEQB_INTEN Mask */
-#define ADC_INTEN_OVR_INTEN_Pos 2 /*!< ADC INTEN: OVR_INTEN Position */
-#define ADC_INTEN_OVR_INTEN_Msk (0x01UL << ADC_INTEN_OVR_INTEN_Pos) /*!< ADC INTEN: OVR_INTEN Mask */
-#define ADC_INTEN_ADCMPINTEN0_Pos 3 /*!< ADC INTEN: ADCMPINTEN0 Position */
-#define ADC_INTEN_ADCMPINTEN0_Msk (0x03UL << ADC_INTEN_ADCMPINTEN0_Pos) /*!< ADC INTEN: ADCMPINTEN0 Mask */
-#define ADC_INTEN_ADCMPINTEN1_Pos 5 /*!< ADC INTEN: ADCMPINTEN1 Position */
-#define ADC_INTEN_ADCMPINTEN1_Msk (0x03UL << ADC_INTEN_ADCMPINTEN1_Pos) /*!< ADC INTEN: ADCMPINTEN1 Mask */
-#define ADC_INTEN_ADCMPINTEN2_Pos 7 /*!< ADC INTEN: ADCMPINTEN2 Position */
-#define ADC_INTEN_ADCMPINTEN2_Msk (0x03UL << ADC_INTEN_ADCMPINTEN2_Pos) /*!< ADC INTEN: ADCMPINTEN2 Mask */
-#define ADC_INTEN_ADCMPINTEN3_Pos 9 /*!< ADC INTEN: ADCMPINTEN3 Position */
-#define ADC_INTEN_ADCMPINTEN3_Msk (0x03UL << ADC_INTEN_ADCMPINTEN3_Pos) /*!< ADC INTEN: ADCMPINTEN3 Mask */
-#define ADC_INTEN_ADCMPINTEN4_Pos 11 /*!< ADC INTEN: ADCMPINTEN4 Position */
-#define ADC_INTEN_ADCMPINTEN4_Msk (0x03UL << ADC_INTEN_ADCMPINTEN4_Pos) /*!< ADC INTEN: ADCMPINTEN4 Mask */
-#define ADC_INTEN_ADCMPINTEN5_Pos 13 /*!< ADC INTEN: ADCMPINTEN5 Position */
-#define ADC_INTEN_ADCMPINTEN5_Msk (0x03UL << ADC_INTEN_ADCMPINTEN5_Pos) /*!< ADC INTEN: ADCMPINTEN5 Mask */
-#define ADC_INTEN_ADCMPINTEN6_Pos 15 /*!< ADC INTEN: ADCMPINTEN6 Position */
-#define ADC_INTEN_ADCMPINTEN6_Msk (0x03UL << ADC_INTEN_ADCMPINTEN6_Pos) /*!< ADC INTEN: ADCMPINTEN6 Mask */
-#define ADC_INTEN_ADCMPINTEN7_Pos 17 /*!< ADC INTEN: ADCMPINTEN7 Position */
-#define ADC_INTEN_ADCMPINTEN7_Msk (0x03UL << ADC_INTEN_ADCMPINTEN7_Pos) /*!< ADC INTEN: ADCMPINTEN7 Mask */
-
-/* --------------------------------- u_adc_FLAGS -------------------------------- */
-#define ADC_FLAGS_THCMP0_Pos 0 /*!< ADC FLAGS: THCMP0 Position */
-#define ADC_FLAGS_THCMP0_Msk (0x01UL << ADC_FLAGS_THCMP0_Pos) /*!< ADC FLAGS: THCMP0 Mask */
-#define ADC_FLAGS_THCMP1_Pos 1 /*!< ADC FLAGS: THCMP1 Position */
-#define ADC_FLAGS_THCMP1_Msk (0x01UL << ADC_FLAGS_THCMP1_Pos) /*!< ADC FLAGS: THCMP1 Mask */
-#define ADC_FLAGS_THCMP2_Pos 2 /*!< ADC FLAGS: THCMP2 Position */
-#define ADC_FLAGS_THCMP2_Msk (0x01UL << ADC_FLAGS_THCMP2_Pos) /*!< ADC FLAGS: THCMP2 Mask */
-#define ADC_FLAGS_THCMP3_Pos 3 /*!< ADC FLAGS: THCMP3 Position */
-#define ADC_FLAGS_THCMP3_Msk (0x01UL << ADC_FLAGS_THCMP3_Pos) /*!< ADC FLAGS: THCMP3 Mask */
-#define ADC_FLAGS_THCMP4_Pos 4 /*!< ADC FLAGS: THCMP4 Position */
-#define ADC_FLAGS_THCMP4_Msk (0x01UL << ADC_FLAGS_THCMP4_Pos) /*!< ADC FLAGS: THCMP4 Mask */
-#define ADC_FLAGS_THCMP5_Pos 5 /*!< ADC FLAGS: THCMP5 Position */
-#define ADC_FLAGS_THCMP5_Msk (0x01UL << ADC_FLAGS_THCMP5_Pos) /*!< ADC FLAGS: THCMP5 Mask */
-#define ADC_FLAGS_THCMP6_Pos 6 /*!< ADC FLAGS: THCMP6 Position */
-#define ADC_FLAGS_THCMP6_Msk (0x01UL << ADC_FLAGS_THCMP6_Pos) /*!< ADC FLAGS: THCMP6 Mask */
-#define ADC_FLAGS_THCMP7_Pos 7 /*!< ADC FLAGS: THCMP7 Position */
-#define ADC_FLAGS_THCMP7_Msk (0x01UL << ADC_FLAGS_THCMP7_Pos) /*!< ADC FLAGS: THCMP7 Mask */
-#define ADC_FLAGS_OVERRUN0_Pos 12 /*!< ADC FLAGS: OVERRUN0 Position */
-#define ADC_FLAGS_OVERRUN0_Msk (0x01UL << ADC_FLAGS_OVERRUN0_Pos) /*!< ADC FLAGS: OVERRUN0 Mask */
-#define ADC_FLAGS_OVERRUN1_Pos 13 /*!< ADC FLAGS: OVERRUN1 Position */
-#define ADC_FLAGS_OVERRUN1_Msk (0x01UL << ADC_FLAGS_OVERRUN1_Pos) /*!< ADC FLAGS: OVERRUN1 Mask */
-#define ADC_FLAGS_OVERRUN2_Pos 14 /*!< ADC FLAGS: OVERRUN2 Position */
-#define ADC_FLAGS_OVERRUN2_Msk (0x01UL << ADC_FLAGS_OVERRUN2_Pos) /*!< ADC FLAGS: OVERRUN2 Mask */
-#define ADC_FLAGS_OVERRUN3_Pos 15 /*!< ADC FLAGS: OVERRUN3 Position */
-#define ADC_FLAGS_OVERRUN3_Msk (0x01UL << ADC_FLAGS_OVERRUN3_Pos) /*!< ADC FLAGS: OVERRUN3 Mask */
-#define ADC_FLAGS_OVERRUN4_Pos 16 /*!< ADC FLAGS: OVERRUN4 Position */
-#define ADC_FLAGS_OVERRUN4_Msk (0x01UL << ADC_FLAGS_OVERRUN4_Pos) /*!< ADC FLAGS: OVERRUN4 Mask */
-#define ADC_FLAGS_OVERRUN5_Pos 17 /*!< ADC FLAGS: OVERRUN5 Position */
-#define ADC_FLAGS_OVERRUN5_Msk (0x01UL << ADC_FLAGS_OVERRUN5_Pos) /*!< ADC FLAGS: OVERRUN5 Mask */
-#define ADC_FLAGS_OVERRUN6_Pos 18 /*!< ADC FLAGS: OVERRUN6 Position */
-#define ADC_FLAGS_OVERRUN6_Msk (0x01UL << ADC_FLAGS_OVERRUN6_Pos) /*!< ADC FLAGS: OVERRUN6 Mask */
-#define ADC_FLAGS_OVERRUN7_Pos 19 /*!< ADC FLAGS: OVERRUN7 Position */
-#define ADC_FLAGS_OVERRUN7_Msk (0x01UL << ADC_FLAGS_OVERRUN7_Pos) /*!< ADC FLAGS: OVERRUN7 Mask */
-#define ADC_FLAGS_SEQA_OVR_Pos 24 /*!< ADC FLAGS: SEQA_OVR Position */
-#define ADC_FLAGS_SEQA_OVR_Msk (0x01UL << ADC_FLAGS_SEQA_OVR_Pos) /*!< ADC FLAGS: SEQA_OVR Mask */
-#define ADC_FLAGS_SEQB_OVR_Pos 25 /*!< ADC FLAGS: SEQB_OVR Position */
-#define ADC_FLAGS_SEQB_OVR_Msk (0x01UL << ADC_FLAGS_SEQB_OVR_Pos) /*!< ADC FLAGS: SEQB_OVR Mask */
-#define ADC_FLAGS_SEQA_INT_Pos 28 /*!< ADC FLAGS: SEQA_INT Position */
-#define ADC_FLAGS_SEQA_INT_Msk (0x01UL << ADC_FLAGS_SEQA_INT_Pos) /*!< ADC FLAGS: SEQA_INT Mask */
-#define ADC_FLAGS_SEQB_INT_Pos 29 /*!< ADC FLAGS: SEQB_INT Position */
-#define ADC_FLAGS_SEQB_INT_Msk (0x01UL << ADC_FLAGS_SEQB_INT_Pos) /*!< ADC FLAGS: SEQB_INT Mask */
-#define ADC_FLAGS_THCMP_INT_Pos 30 /*!< ADC FLAGS: THCMP_INT Position */
-#define ADC_FLAGS_THCMP_INT_Msk (0x01UL << ADC_FLAGS_THCMP_INT_Pos) /*!< ADC FLAGS: THCMP_INT Mask */
-#define ADC_FLAGS_OVR_INT_Pos 31 /*!< ADC FLAGS: OVR_INT Position */
-#define ADC_FLAGS_OVR_INT_Msk (0x01UL << ADC_FLAGS_OVR_INT_Pos) /*!< ADC FLAGS: OVR_INT Mask */
-
-/* -------------------------------- u_adc_STARTUP ------------------------------- */
-#define ADC_STARTUP_ADC_ENA_Pos 0 /*!< ADC STARTUP: ADC_ENA Position */
-#define ADC_STARTUP_ADC_ENA_Msk (0x01UL << ADC_STARTUP_ADC_ENA_Pos) /*!< ADC STARTUP: ADC_ENA Mask */
-
-/* ------------------------------ u_adc_GPADC_CTRL0 ----------------------------- */
-#define ADC_GPADC_CTRL0_LDO_POWER_EN_Pos 0 /*!< ADC GPADC_CTRL0: LDO_POWER_EN Position */
-#define ADC_GPADC_CTRL0_LDO_POWER_EN_Msk (0x01UL << ADC_GPADC_CTRL0_LDO_POWER_EN_Pos) /*!< ADC GPADC_CTRL0: LDO_POWER_EN Mask */
-#define ADC_GPADC_CTRL0_LDO_SEL_OUT_Pos 3 /*!< ADC GPADC_CTRL0: LDO_SEL_OUT Position */
-#define ADC_GPADC_CTRL0_LDO_SEL_OUT_Msk (0x1fUL << ADC_GPADC_CTRL0_LDO_SEL_OUT_Pos) /*!< ADC GPADC_CTRL0: LDO_SEL_OUT Mask */
-#define ADC_GPADC_CTRL0_PASS_ENABLE_Pos 8 /*!< ADC GPADC_CTRL0: PASS_ENABLE Position */
-#define ADC_GPADC_CTRL0_PASS_ENABLE_Msk (0x01UL << ADC_GPADC_CTRL0_PASS_ENABLE_Pos) /*!< ADC GPADC_CTRL0: PASS_ENABLE Mask */
-#define ADC_GPADC_CTRL0_GPADC_TSAMP_Pos 9 /*!< ADC GPADC_CTRL0: GPADC_TSAMP Position */
-#define ADC_GPADC_CTRL0_GPADC_TSAMP_Msk (0x1fUL << ADC_GPADC_CTRL0_GPADC_TSAMP_Pos) /*!< ADC GPADC_CTRL0: GPADC_TSAMP Mask */
-#define ADC_GPADC_CTRL0_TEST_Pos 14 /*!< ADC GPADC_CTRL0: TEST Position */
-#define ADC_GPADC_CTRL0_TEST_Msk (0x03UL << ADC_GPADC_CTRL0_TEST_Pos) /*!< ADC GPADC_CTRL0: TEST Mask */
-#define ADC_GPADC_CTRL0_SEL_ATB_Pos 16 /*!< ADC GPADC_CTRL0: SEL_ATB Position */
-#define ADC_GPADC_CTRL0_SEL_ATB_Msk (0x03UL << ADC_GPADC_CTRL0_SEL_ATB_Pos) /*!< ADC GPADC_CTRL0: SEL_ATB Mask */
-
-/* ------------------------------ u_adc_GPADC_CTRL1 ----------------------------- */
-#define ADC_GPADC_CTRL1_OFFSET_CAL_Pos 0 /*!< ADC GPADC_CTRL1: OFFSET_CAL Position */
-#define ADC_GPADC_CTRL1_OFFSET_CAL_Msk (0x000003ffUL << ADC_GPADC_CTRL1_OFFSET_CAL_Pos) /*!< ADC GPADC_CTRL1: OFFSET_CAL Mask */
-#define ADC_GPADC_CTRL1_GAIN_CAL_Pos 10 /*!< ADC GPADC_CTRL1: GAIN_CAL Position */
-#define ADC_GPADC_CTRL1_GAIN_CAL_Msk (0x000003ffUL << ADC_GPADC_CTRL1_GAIN_CAL_Pos) /*!< ADC GPADC_CTRL1: GAIN_CAL Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u_dmic' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* --------------------------------- u_dmic_OSR0 -------------------------------- */
-#define DMIC_OSR0_OSR_Pos 0 /*!< DMIC OSR0: OSR Position */
-#define DMIC_OSR0_OSR_Msk (0x000000ffUL << DMIC_OSR0_OSR_Pos) /*!< DMIC OSR0: OSR Mask */
-
-/* ------------------------------ u_dmic_DIVHFCLK0 ------------------------------ */
-#define DMIC_DIVHFCLK0_PDMDIV_Pos 0 /*!< DMIC DIVHFCLK0: PDMDIV Position */
-#define DMIC_DIVHFCLK0_PDMDIV_Msk (0x0fUL << DMIC_DIVHFCLK0_PDMDIV_Pos) /*!< DMIC DIVHFCLK0: PDMDIV Mask */
-
-/* ---------------------------- u_dmic_PREAC2FSCOEF0 ---------------------------- */
-#define DMIC_PREAC2FSCOEF0_COMP_Pos 0 /*!< DMIC PREAC2FSCOEF0: COMP Position */
-#define DMIC_PREAC2FSCOEF0_COMP_Msk (0x03UL << DMIC_PREAC2FSCOEF0_COMP_Pos) /*!< DMIC PREAC2FSCOEF0: COMP Mask */
-
-/* ---------------------------- u_dmic_PREAC4FSCOEF0 ---------------------------- */
-#define DMIC_PREAC4FSCOEF0_COMP_Pos 0 /*!< DMIC PREAC4FSCOEF0: COMP Position */
-#define DMIC_PREAC4FSCOEF0_COMP_Msk (0x03UL << DMIC_PREAC4FSCOEF0_COMP_Pos) /*!< DMIC PREAC4FSCOEF0: COMP Mask */
-
-/* ------------------------------ u_dmic_GAINSHIFT0 ----------------------------- */
-#define DMIC_GAINSHIFT0_GAIN_Pos 0 /*!< DMIC GAINSHIFT0: GAIN Position */
-#define DMIC_GAINSHIFT0_GAIN_Msk (0x3fUL << DMIC_GAINSHIFT0_GAIN_Pos) /*!< DMIC GAINSHIFT0: GAIN Mask */
-
-/* ------------------------------ u_dmic_FIFOCTRL0 ------------------------------ */
-#define DMIC_FIFOCTRL0_ENABLE_Pos 0 /*!< DMIC FIFOCTRL0: ENABLE Position */
-#define DMIC_FIFOCTRL0_ENABLE_Msk (0x01UL << DMIC_FIFOCTRL0_ENABLE_Pos) /*!< DMIC FIFOCTRL0: ENABLE Mask */
-#define DMIC_FIFOCTRL0_RESET_Pos 1 /*!< DMIC FIFOCTRL0: RESET Position */
-#define DMIC_FIFOCTRL0_RESET_Msk (0x01UL << DMIC_FIFOCTRL0_RESET_Pos) /*!< DMIC FIFOCTRL0: RESET Mask */
-#define DMIC_FIFOCTRL0_INTEN_Pos 2 /*!< DMIC FIFOCTRL0: INTEN Position */
-#define DMIC_FIFOCTRL0_INTEN_Msk (0x01UL << DMIC_FIFOCTRL0_INTEN_Pos) /*!< DMIC FIFOCTRL0: INTEN Mask */
-#define DMIC_FIFOCTRL0_DMAEN_Pos 3 /*!< DMIC FIFOCTRL0: DMAEN Position */
-#define DMIC_FIFOCTRL0_DMAEN_Msk (0x01UL << DMIC_FIFOCTRL0_DMAEN_Pos) /*!< DMIC FIFOCTRL0: DMAEN Mask */
-#define DMIC_FIFOCTRL0_TRIGLVL_Pos 16 /*!< DMIC FIFOCTRL0: TRIGLVL Position */
-#define DMIC_FIFOCTRL0_TRIGLVL_Msk (0x1fUL << DMIC_FIFOCTRL0_TRIGLVL_Pos) /*!< DMIC FIFOCTRL0: TRIGLVL Mask */
-
-/* ------------------------------ u_dmic_FIFOSTAT0 ------------------------------ */
-#define DMIC_FIFOSTAT0_INT_Pos 0 /*!< DMIC FIFOSTAT0: INT Position */
-#define DMIC_FIFOSTAT0_INT_Msk (0x01UL << DMIC_FIFOSTAT0_INT_Pos) /*!< DMIC FIFOSTAT0: INT Mask */
-#define DMIC_FIFOSTAT0_OVERRUN_Pos 1 /*!< DMIC FIFOSTAT0: OVERRUN Position */
-#define DMIC_FIFOSTAT0_OVERRUN_Msk (0x01UL << DMIC_FIFOSTAT0_OVERRUN_Pos) /*!< DMIC FIFOSTAT0: OVERRUN Mask */
-#define DMIC_FIFOSTAT0_UNDERRUN_Pos 2 /*!< DMIC FIFOSTAT0: UNDERRUN Position */
-#define DMIC_FIFOSTAT0_UNDERRUN_Msk (0x01UL << DMIC_FIFOSTAT0_UNDERRUN_Pos) /*!< DMIC FIFOSTAT0: UNDERRUN Mask */
-
-/* ------------------------------ u_dmic_FIFODATA0 ------------------------------ */
-#define DMIC_FIFODATA0_DATA_Pos 0 /*!< DMIC FIFODATA0: DATA Position */
-#define DMIC_FIFODATA0_DATA_Msk (0x00ffffffUL << DMIC_FIFODATA0_DATA_Pos) /*!< DMIC FIFODATA0: DATA Mask */
-
-/* ------------------------------ u_dmic_PDMSRCCFG0 ----------------------------- */
-#define DMIC_PDMSRCCFG0_PHY_FALL_Pos 0 /*!< DMIC PDMSRCCFG0: PHY_FALL Position */
-#define DMIC_PDMSRCCFG0_PHY_FALL_Msk (0x01UL << DMIC_PDMSRCCFG0_PHY_FALL_Pos) /*!< DMIC PDMSRCCFG0: PHY_FALL Mask */
-#define DMIC_PDMSRCCFG0_PHY_HALF_Pos 1 /*!< DMIC PDMSRCCFG0: PHY_HALF Position */
-#define DMIC_PDMSRCCFG0_PHY_HALF_Msk (0x01UL << DMIC_PDMSRCCFG0_PHY_HALF_Pos) /*!< DMIC PDMSRCCFG0: PHY_HALF Mask */
-
-/* ------------------------------- u_dmic_DCCTRL0 ------------------------------- */
-#define DMIC_DCCTRL0_DCPOLE_Pos 0 /*!< DMIC DCCTRL0: DCPOLE Position */
-#define DMIC_DCCTRL0_DCPOLE_Msk (0x03UL << DMIC_DCCTRL0_DCPOLE_Pos) /*!< DMIC DCCTRL0: DCPOLE Mask */
-#define DMIC_DCCTRL0_DCGAIN_Pos 4 /*!< DMIC DCCTRL0: DCGAIN Position */
-#define DMIC_DCCTRL0_DCGAIN_Msk (0x0fUL << DMIC_DCCTRL0_DCGAIN_Pos) /*!< DMIC DCCTRL0: DCGAIN Mask */
-#define DMIC_DCCTRL0_SATURATEAT16BIT_Pos 8 /*!< DMIC DCCTRL0: SATURATEAT16BIT Position */
-#define DMIC_DCCTRL0_SATURATEAT16BIT_Msk (0x01UL << DMIC_DCCTRL0_SATURATEAT16BIT_Pos) /*!< DMIC DCCTRL0: SATURATEAT16BIT Mask */
-
-/* --------------------------------- u_dmic_OSR1 -------------------------------- */
-#define DMIC_OSR1_OSR_Pos 0 /*!< DMIC OSR1: OSR Position */
-#define DMIC_OSR1_OSR_Msk (0x000000ffUL << DMIC_OSR1_OSR_Pos) /*!< DMIC OSR1: OSR Mask */
-
-/* ------------------------------ u_dmic_DIVHFCLK1 ------------------------------ */
-#define DMIC_DIVHFCLK1_PDMDIV_Pos 0 /*!< DMIC DIVHFCLK1: PDMDIV Position */
-#define DMIC_DIVHFCLK1_PDMDIV_Msk (0x0fUL << DMIC_DIVHFCLK1_PDMDIV_Pos) /*!< DMIC DIVHFCLK1: PDMDIV Mask */
-
-/* ---------------------------- u_dmic_PREAC2FSCOEF1 ---------------------------- */
-#define DMIC_PREAC2FSCOEF1_COMP_Pos 0 /*!< DMIC PREAC2FSCOEF1: COMP Position */
-#define DMIC_PREAC2FSCOEF1_COMP_Msk (0x03UL << DMIC_PREAC2FSCOEF1_COMP_Pos) /*!< DMIC PREAC2FSCOEF1: COMP Mask */
-
-/* ---------------------------- u_dmic_PREAC4FSCOEF1 ---------------------------- */
-#define DMIC_PREAC4FSCOEF1_COMP_Pos 0 /*!< DMIC PREAC4FSCOEF1: COMP Position */
-#define DMIC_PREAC4FSCOEF1_COMP_Msk (0x03UL << DMIC_PREAC4FSCOEF1_COMP_Pos) /*!< DMIC PREAC4FSCOEF1: COMP Mask */
-
-/* ------------------------------ u_dmic_GAINSHIFT1 ----------------------------- */
-#define DMIC_GAINSHIFT1_GAIN_Pos 0 /*!< DMIC GAINSHIFT1: GAIN Position */
-#define DMIC_GAINSHIFT1_GAIN_Msk (0x3fUL << DMIC_GAINSHIFT1_GAIN_Pos) /*!< DMIC GAINSHIFT1: GAIN Mask */
-
-/* ------------------------------ u_dmic_FIFOCTRL1 ------------------------------ */
-#define DMIC_FIFOCTRL1_ENABLE_Pos 0 /*!< DMIC FIFOCTRL1: ENABLE Position */
-#define DMIC_FIFOCTRL1_ENABLE_Msk (0x01UL << DMIC_FIFOCTRL1_ENABLE_Pos) /*!< DMIC FIFOCTRL1: ENABLE Mask */
-#define DMIC_FIFOCTRL1_RESET_Pos 1 /*!< DMIC FIFOCTRL1: RESET Position */
-#define DMIC_FIFOCTRL1_RESET_Msk (0x01UL << DMIC_FIFOCTRL1_RESET_Pos) /*!< DMIC FIFOCTRL1: RESET Mask */
-#define DMIC_FIFOCTRL1_INTEN_Pos 2 /*!< DMIC FIFOCTRL1: INTEN Position */
-#define DMIC_FIFOCTRL1_INTEN_Msk (0x01UL << DMIC_FIFOCTRL1_INTEN_Pos) /*!< DMIC FIFOCTRL1: INTEN Mask */
-#define DMIC_FIFOCTRL1_DMAEN_Pos 3 /*!< DMIC FIFOCTRL1: DMAEN Position */
-#define DMIC_FIFOCTRL1_DMAEN_Msk (0x01UL << DMIC_FIFOCTRL1_DMAEN_Pos) /*!< DMIC FIFOCTRL1: DMAEN Mask */
-#define DMIC_FIFOCTRL1_TRIGLVL_Pos 16 /*!< DMIC FIFOCTRL1: TRIGLVL Position */
-#define DMIC_FIFOCTRL1_TRIGLVL_Msk (0x1fUL << DMIC_FIFOCTRL1_TRIGLVL_Pos) /*!< DMIC FIFOCTRL1: TRIGLVL Mask */
-
-/* ------------------------------ u_dmic_FIFOSTAT1 ------------------------------ */
-#define DMIC_FIFOSTAT1_INT_Pos 0 /*!< DMIC FIFOSTAT1: INT Position */
-#define DMIC_FIFOSTAT1_INT_Msk (0x01UL << DMIC_FIFOSTAT1_INT_Pos) /*!< DMIC FIFOSTAT1: INT Mask */
-#define DMIC_FIFOSTAT1_OVERRUN_Pos 1 /*!< DMIC FIFOSTAT1: OVERRUN Position */
-#define DMIC_FIFOSTAT1_OVERRUN_Msk (0x01UL << DMIC_FIFOSTAT1_OVERRUN_Pos) /*!< DMIC FIFOSTAT1: OVERRUN Mask */
-#define DMIC_FIFOSTAT1_UNDERRUN_Pos 2 /*!< DMIC FIFOSTAT1: UNDERRUN Position */
-#define DMIC_FIFOSTAT1_UNDERRUN_Msk (0x01UL << DMIC_FIFOSTAT1_UNDERRUN_Pos) /*!< DMIC FIFOSTAT1: UNDERRUN Mask */
-
-/* ------------------------------ u_dmic_FIFODATA1 ------------------------------ */
-#define DMIC_FIFODATA1_DATA_Pos 0 /*!< DMIC FIFODATA1: DATA Position */
-#define DMIC_FIFODATA1_DATA_Msk (0x00ffffffUL << DMIC_FIFODATA1_DATA_Pos) /*!< DMIC FIFODATA1: DATA Mask */
-
-/* ------------------------------ u_dmic_PDMSRCCFG1 ----------------------------- */
-#define DMIC_PDMSRCCFG1_PHY_FALL_Pos 0 /*!< DMIC PDMSRCCFG1: PHY_FALL Position */
-#define DMIC_PDMSRCCFG1_PHY_FALL_Msk (0x01UL << DMIC_PDMSRCCFG1_PHY_FALL_Pos) /*!< DMIC PDMSRCCFG1: PHY_FALL Mask */
-#define DMIC_PDMSRCCFG1_PHY_HALF_Pos 1 /*!< DMIC PDMSRCCFG1: PHY_HALF Position */
-#define DMIC_PDMSRCCFG1_PHY_HALF_Msk (0x01UL << DMIC_PDMSRCCFG1_PHY_HALF_Pos) /*!< DMIC PDMSRCCFG1: PHY_HALF Mask */
-
-/* ------------------------------- u_dmic_DCCTRL1 ------------------------------- */
-#define DMIC_DCCTRL1_DCPOLE_Pos 0 /*!< DMIC DCCTRL1: DCPOLE Position */
-#define DMIC_DCCTRL1_DCPOLE_Msk (0x03UL << DMIC_DCCTRL1_DCPOLE_Pos) /*!< DMIC DCCTRL1: DCPOLE Mask */
-#define DMIC_DCCTRL1_DCGAIN_Pos 4 /*!< DMIC DCCTRL1: DCGAIN Position */
-#define DMIC_DCCTRL1_DCGAIN_Msk (0x0fUL << DMIC_DCCTRL1_DCGAIN_Pos) /*!< DMIC DCCTRL1: DCGAIN Mask */
-#define DMIC_DCCTRL1_SATURATEAT16BIT_Pos 8 /*!< DMIC DCCTRL1: SATURATEAT16BIT Position */
-#define DMIC_DCCTRL1_SATURATEAT16BIT_Msk (0x01UL << DMIC_DCCTRL1_SATURATEAT16BIT_Pos) /*!< DMIC DCCTRL1: SATURATEAT16BIT Mask */
-
-/* -------------------------------- u_dmic_CHANEN ------------------------------- */
-#define DMIC_CHANEN_EN_CH0_Pos 0 /*!< DMIC CHANEN: EN_CH0 Position */
-#define DMIC_CHANEN_EN_CH0_Msk (0x01UL << DMIC_CHANEN_EN_CH0_Pos) /*!< DMIC CHANEN: EN_CH0 Mask */
-#define DMIC_CHANEN_EN_CH1_Pos 1 /*!< DMIC CHANEN: EN_CH1 Position */
-#define DMIC_CHANEN_EN_CH1_Msk (0x01UL << DMIC_CHANEN_EN_CH1_Pos) /*!< DMIC CHANEN: EN_CH1 Mask */
-
-/* -------------------------------- u_dmic_IOCFG -------------------------------- */
-#define DMIC_IOCFG_CLK_BYPASS0_Pos 0 /*!< DMIC IOCFG: CLK_BYPASS0 Position */
-#define DMIC_IOCFG_CLK_BYPASS0_Msk (0x01UL << DMIC_IOCFG_CLK_BYPASS0_Pos) /*!< DMIC IOCFG: CLK_BYPASS0 Mask */
-#define DMIC_IOCFG_CLK_BYPASS1_Pos 1 /*!< DMIC IOCFG: CLK_BYPASS1 Position */
-#define DMIC_IOCFG_CLK_BYPASS1_Msk (0x01UL << DMIC_IOCFG_CLK_BYPASS1_Pos) /*!< DMIC IOCFG: CLK_BYPASS1 Mask */
-#define DMIC_IOCFG_STEREO_DATA0_Pos 2 /*!< DMIC IOCFG: STEREO_DATA0 Position */
-#define DMIC_IOCFG_STEREO_DATA0_Msk (0x01UL << DMIC_IOCFG_STEREO_DATA0_Pos) /*!< DMIC IOCFG: STEREO_DATA0 Mask */
-
-/* -------------------------------- u_dmic_USE2FS ------------------------------- */
-#define DMIC_USE2FS_USE2FS_Pos 0 /*!< DMIC USE2FS: USE2FS Position */
-#define DMIC_USE2FS_USE2FS_Msk (0x01UL << DMIC_USE2FS_USE2FS_Pos) /*!< DMIC USE2FS: USE2FS Mask */
-
-/* ------------------------------ u_dmic_HWVADGAIN ------------------------------ */
-#define DMIC_HWVADGAIN_INPUTGAIN_Pos 0 /*!< DMIC HWVADGAIN: INPUTGAIN Position */
-#define DMIC_HWVADGAIN_INPUTGAIN_Msk (0x0fUL << DMIC_HWVADGAIN_INPUTGAIN_Pos) /*!< DMIC HWVADGAIN: INPUTGAIN Mask */
-
-/* ------------------------------ u_dmic_HWVADHPFS ------------------------------ */
-#define DMIC_HWVADHPFS_HPFS_Pos 0 /*!< DMIC HWVADHPFS: HPFS Position */
-#define DMIC_HWVADHPFS_HPFS_Msk (0x03UL << DMIC_HWVADHPFS_HPFS_Pos) /*!< DMIC HWVADHPFS: HPFS Mask */
-
-/* ------------------------------ u_dmic_HWVADST10 ------------------------------ */
-#define DMIC_HWVADST10_ST10_Pos 0 /*!< DMIC HWVADST10: ST10 Position */
-#define DMIC_HWVADST10_ST10_Msk (0x01UL << DMIC_HWVADST10_ST10_Pos) /*!< DMIC HWVADST10: ST10 Mask */
-
-/* ------------------------------ u_dmic_HWVADRSTT ------------------------------ */
-#define DMIC_HWVADRSTT_RSTT_Pos 0 /*!< DMIC HWVADRSTT: RSTT Position */
-#define DMIC_HWVADRSTT_RSTT_Msk (0x01UL << DMIC_HWVADRSTT_RSTT_Pos) /*!< DMIC HWVADRSTT: RSTT Mask */
-
-/* ------------------------------ u_dmic_HWVADTHGN ------------------------------ */
-#define DMIC_HWVADTHGN_THGN_Pos 0 /*!< DMIC HWVADTHGN: THGN Position */
-#define DMIC_HWVADTHGN_THGN_Msk (0x0fUL << DMIC_HWVADTHGN_THGN_Pos) /*!< DMIC HWVADTHGN: THGN Mask */
-
-/* ------------------------------ u_dmic_HWVADTHGS ------------------------------ */
-#define DMIC_HWVADTHGS_THGS_Pos 0 /*!< DMIC HWVADTHGS: THGS Position */
-#define DMIC_HWVADTHGS_THGS_Msk (0x0fUL << DMIC_HWVADTHGS_THGS_Pos) /*!< DMIC HWVADTHGS: THGS Mask */
-
-/* ------------------------------ u_dmic_HWVADLOWZ ------------------------------ */
-#define DMIC_HWVADLOWZ_LOWZ_Pos 0 /*!< DMIC HWVADLOWZ: LOWZ Position */
-#define DMIC_HWVADLOWZ_LOWZ_Msk (0x0000ffffUL << DMIC_HWVADLOWZ_LOWZ_Pos) /*!< DMIC HWVADLOWZ: LOWZ Mask */
-
-/* ---------------------------------- u_dmic_ID --------------------------------- */
-#define DMIC_ID_ID_Pos 0 /*!< DMIC ID: ID Position */
-#define DMIC_ID_ID_Msk (0xffffffffUL << DMIC_ID_ID_Pos) /*!< DMIC ID: ID Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u0_usart' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* -------------------------------- u0_usart_CFG -------------------------------- */
-#define USART0_CFG_ENABLE_Pos 0 /*!< USART0 CFG: ENABLE Position */
-#define USART0_CFG_ENABLE_Msk (0x01UL << USART0_CFG_ENABLE_Pos) /*!< USART0 CFG: ENABLE Mask */
-#define USART0_CFG_DATALEN_Pos 2 /*!< USART0 CFG: DATALEN Position */
-#define USART0_CFG_DATALEN_Msk (0x03UL << USART0_CFG_DATALEN_Pos) /*!< USART0 CFG: DATALEN Mask */
-#define USART0_CFG_PARITYSEL_Pos 4 /*!< USART0 CFG: PARITYSEL Position */
-#define USART0_CFG_PARITYSEL_Msk (0x03UL << USART0_CFG_PARITYSEL_Pos) /*!< USART0 CFG: PARITYSEL Mask */
-#define USART0_CFG_STOPLEN_Pos 6 /*!< USART0 CFG: STOPLEN Position */
-#define USART0_CFG_STOPLEN_Msk (0x01UL << USART0_CFG_STOPLEN_Pos) /*!< USART0 CFG: STOPLEN Mask */
-#define USART0_CFG_MODE32K_Pos 7 /*!< USART0 CFG: MODE32K Position */
-#define USART0_CFG_MODE32K_Msk (0x01UL << USART0_CFG_MODE32K_Pos) /*!< USART0 CFG: MODE32K Mask */
-#define USART0_CFG_LINMODE_Pos 8 /*!< USART0 CFG: LINMODE Position */
-#define USART0_CFG_LINMODE_Msk (0x01UL << USART0_CFG_LINMODE_Pos) /*!< USART0 CFG: LINMODE Mask */
-#define USART0_CFG_CTSEN_Pos 9 /*!< USART0 CFG: CTSEN Position */
-#define USART0_CFG_CTSEN_Msk (0x01UL << USART0_CFG_CTSEN_Pos) /*!< USART0 CFG: CTSEN Mask */
-#define USART0_CFG_SYNCEN_Pos 11 /*!< USART0 CFG: SYNCEN Position */
-#define USART0_CFG_SYNCEN_Msk (0x01UL << USART0_CFG_SYNCEN_Pos) /*!< USART0 CFG: SYNCEN Mask */
-#define USART0_CFG_CLKPOL_Pos 12 /*!< USART0 CFG: CLKPOL Position */
-#define USART0_CFG_CLKPOL_Msk (0x01UL << USART0_CFG_CLKPOL_Pos) /*!< USART0 CFG: CLKPOL Mask */
-#define USART0_CFG_SYNCMST_Pos 14 /*!< USART0 CFG: SYNCMST Position */
-#define USART0_CFG_SYNCMST_Msk (0x01UL << USART0_CFG_SYNCMST_Pos) /*!< USART0 CFG: SYNCMST Mask */
-#define USART0_CFG_LOOP_Pos 15 /*!< USART0 CFG: LOOP Position */
-#define USART0_CFG_LOOP_Msk (0x01UL << USART0_CFG_LOOP_Pos) /*!< USART0 CFG: LOOP Mask */
-#define USART0_CFG_IOMODE_Pos 16 /*!< USART0 CFG: IOMODE Position */
-#define USART0_CFG_IOMODE_Msk (0x01UL << USART0_CFG_IOMODE_Pos) /*!< USART0 CFG: IOMODE Mask */
-#define USART0_CFG_OETA_Pos 18 /*!< USART0 CFG: OETA Position */
-#define USART0_CFG_OETA_Msk (0x01UL << USART0_CFG_OETA_Pos) /*!< USART0 CFG: OETA Mask */
-#define USART0_CFG_AUTOADDR_Pos 19 /*!< USART0 CFG: AUTOADDR Position */
-#define USART0_CFG_AUTOADDR_Msk (0x01UL << USART0_CFG_AUTOADDR_Pos) /*!< USART0 CFG: AUTOADDR Mask */
-#define USART0_CFG_OESEL_Pos 20 /*!< USART0 CFG: OESEL Position */
-#define USART0_CFG_OESEL_Msk (0x01UL << USART0_CFG_OESEL_Pos) /*!< USART0 CFG: OESEL Mask */
-#define USART0_CFG_OEPOL_Pos 21 /*!< USART0 CFG: OEPOL Position */
-#define USART0_CFG_OEPOL_Msk (0x01UL << USART0_CFG_OEPOL_Pos) /*!< USART0 CFG: OEPOL Mask */
-#define USART0_CFG_RXPOL_Pos 22 /*!< USART0 CFG: RXPOL Position */
-#define USART0_CFG_RXPOL_Msk (0x01UL << USART0_CFG_RXPOL_Pos) /*!< USART0 CFG: RXPOL Mask */
-#define USART0_CFG_TXPOL_Pos 23 /*!< USART0 CFG: TXPOL Position */
-#define USART0_CFG_TXPOL_Msk (0x01UL << USART0_CFG_TXPOL_Pos) /*!< USART0 CFG: TXPOL Mask */
-
-/* -------------------------------- u0_usart_CTL -------------------------------- */
-#define USART0_CTL_TXBRKEN_Pos 1 /*!< USART0 CTL: TXBRKEN Position */
-#define USART0_CTL_TXBRKEN_Msk (0x01UL << USART0_CTL_TXBRKEN_Pos) /*!< USART0 CTL: TXBRKEN Mask */
-#define USART0_CTL_ADDRDET_Pos 2 /*!< USART0 CTL: ADDRDET Position */
-#define USART0_CTL_ADDRDET_Msk (0x01UL << USART0_CTL_ADDRDET_Pos) /*!< USART0 CTL: ADDRDET Mask */
-#define USART0_CTL_TXDIS_Pos 6 /*!< USART0 CTL: TXDIS Position */
-#define USART0_CTL_TXDIS_Msk (0x01UL << USART0_CTL_TXDIS_Pos) /*!< USART0 CTL: TXDIS Mask */
-#define USART0_CTL_CC_Pos 8 /*!< USART0 CTL: CC Position */
-#define USART0_CTL_CC_Msk (0x01UL << USART0_CTL_CC_Pos) /*!< USART0 CTL: CC Mask */
-#define USART0_CTL_CLRCCONRX_Pos 9 /*!< USART0 CTL: CLRCCONRX Position */
-#define USART0_CTL_CLRCCONRX_Msk (0x01UL << USART0_CTL_CLRCCONRX_Pos) /*!< USART0 CTL: CLRCCONRX Mask */
-#define USART0_CTL_AUTOBAUD_Pos 16 /*!< USART0 CTL: AUTOBAUD Position */
-#define USART0_CTL_AUTOBAUD_Msk (0x01UL << USART0_CTL_AUTOBAUD_Pos) /*!< USART0 CTL: AUTOBAUD Mask */
-
-/* -------------------------------- u0_usart_STAT ------------------------------- */
-#define USART0_STAT_RXIDLE_Pos 1 /*!< USART0 STAT: RXIDLE Position */
-#define USART0_STAT_RXIDLE_Msk (0x01UL << USART0_STAT_RXIDLE_Pos) /*!< USART0 STAT: RXIDLE Mask */
-#define USART0_STAT_TXIDLE_Pos 3 /*!< USART0 STAT: TXIDLE Position */
-#define USART0_STAT_TXIDLE_Msk (0x01UL << USART0_STAT_TXIDLE_Pos) /*!< USART0 STAT: TXIDLE Mask */
-#define USART0_STAT_CTS_Pos 4 /*!< USART0 STAT: CTS Position */
-#define USART0_STAT_CTS_Msk (0x01UL << USART0_STAT_CTS_Pos) /*!< USART0 STAT: CTS Mask */
-#define USART0_STAT_DELTACTS_Pos 5 /*!< USART0 STAT: DELTACTS Position */
-#define USART0_STAT_DELTACTS_Msk (0x01UL << USART0_STAT_DELTACTS_Pos) /*!< USART0 STAT: DELTACTS Mask */
-#define USART0_STAT_TXDISSTAT_Pos 6 /*!< USART0 STAT: TXDISSTAT Position */
-#define USART0_STAT_TXDISSTAT_Msk (0x01UL << USART0_STAT_TXDISSTAT_Pos) /*!< USART0 STAT: TXDISSTAT Mask */
-#define USART0_STAT_OVERRUNINT_Pos 8 /*!< USART0 STAT: OVERRUNINT Position */
-#define USART0_STAT_OVERRUNINT_Msk (0x01UL << USART0_STAT_OVERRUNINT_Pos) /*!< USART0 STAT: OVERRUNINT Mask */
-#define USART0_STAT_RXBRK_Pos 10 /*!< USART0 STAT: RXBRK Position */
-#define USART0_STAT_RXBRK_Msk (0x01UL << USART0_STAT_RXBRK_Pos) /*!< USART0 STAT: RXBRK Mask */
-#define USART0_STAT_DELTARXBRK_Pos 11 /*!< USART0 STAT: DELTARXBRK Position */
-#define USART0_STAT_DELTARXBRK_Msk (0x01UL << USART0_STAT_DELTARXBRK_Pos) /*!< USART0 STAT: DELTARXBRK Mask */
-#define USART0_STAT_START_Pos 12 /*!< USART0 STAT: START Position */
-#define USART0_STAT_START_Msk (0x01UL << USART0_STAT_START_Pos) /*!< USART0 STAT: START Mask */
-#define USART0_STAT_FRAMERRINT_Pos 13 /*!< USART0 STAT: FRAMERRINT Position */
-#define USART0_STAT_FRAMERRINT_Msk (0x01UL << USART0_STAT_FRAMERRINT_Pos) /*!< USART0 STAT: FRAMERRINT Mask */
-#define USART0_STAT_PARITYERRINT_Pos 14 /*!< USART0 STAT: PARITYERRINT Position */
-#define USART0_STAT_PARITYERRINT_Msk (0x01UL << USART0_STAT_PARITYERRINT_Pos) /*!< USART0 STAT: PARITYERRINT Mask */
-#define USART0_STAT_RXNOISEINT_Pos 15 /*!< USART0 STAT: RXNOISEINT Position */
-#define USART0_STAT_RXNOISEINT_Msk (0x01UL << USART0_STAT_RXNOISEINT_Pos) /*!< USART0 STAT: RXNOISEINT Mask */
-#define USART0_STAT_ABERR_Pos 16 /*!< USART0 STAT: ABERR Position */
-#define USART0_STAT_ABERR_Msk (0x01UL << USART0_STAT_ABERR_Pos) /*!< USART0 STAT: ABERR Mask */
-
-/* ------------------------------ u0_usart_INTENSET ----------------------------- */
-#define USART0_INTENSET_RXRDYEN_Pos 0 /*!< USART0 INTENSET: RXRDYEN Position */
-#define USART0_INTENSET_RXRDYEN_Msk (0x01UL << USART0_INTENSET_RXRDYEN_Pos) /*!< USART0 INTENSET: RXRDYEN Mask */
-#define USART0_INTENSET_TXRDTEN_Pos 2 /*!< USART0 INTENSET: TXRDTEN Position */
-#define USART0_INTENSET_TXRDTEN_Msk (0x01UL << USART0_INTENSET_TXRDTEN_Pos) /*!< USART0 INTENSET: TXRDTEN Mask */
-#define USART0_INTENSET_TXIDLEEN_Pos 3 /*!< USART0 INTENSET: TXIDLEEN Position */
-#define USART0_INTENSET_TXIDLEEN_Msk (0x01UL << USART0_INTENSET_TXIDLEEN_Pos) /*!< USART0 INTENSET: TXIDLEEN Mask */
-#define USART0_INTENSET_DELTACTSEN_Pos 5 /*!< USART0 INTENSET: DELTACTSEN Position */
-#define USART0_INTENSET_DELTACTSEN_Msk (0x01UL << USART0_INTENSET_DELTACTSEN_Pos) /*!< USART0 INTENSET: DELTACTSEN Mask */
-#define USART0_INTENSET_TXDISEN_Pos 6 /*!< USART0 INTENSET: TXDISEN Position */
-#define USART0_INTENSET_TXDISEN_Msk (0x01UL << USART0_INTENSET_TXDISEN_Pos) /*!< USART0 INTENSET: TXDISEN Mask */
-#define USART0_INTENSET_OVERRUNEN_Pos 8 /*!< USART0 INTENSET: OVERRUNEN Position */
-#define USART0_INTENSET_OVERRUNEN_Msk (0x01UL << USART0_INTENSET_OVERRUNEN_Pos) /*!< USART0 INTENSET: OVERRUNEN Mask */
-#define USART0_INTENSET_DELTARXBRKEN_Pos 11 /*!< USART0 INTENSET: DELTARXBRKEN Position */
-#define USART0_INTENSET_DELTARXBRKEN_Msk (0x01UL << USART0_INTENSET_DELTARXBRKEN_Pos) /*!< USART0 INTENSET: DELTARXBRKEN Mask */
-#define USART0_INTENSET_STARTEN_Pos 12 /*!< USART0 INTENSET: STARTEN Position */
-#define USART0_INTENSET_STARTEN_Msk (0x01UL << USART0_INTENSET_STARTEN_Pos) /*!< USART0 INTENSET: STARTEN Mask */
-#define USART0_INTENSET_FRAMERREN_Pos 13 /*!< USART0 INTENSET: FRAMERREN Position */
-#define USART0_INTENSET_FRAMERREN_Msk (0x01UL << USART0_INTENSET_FRAMERREN_Pos) /*!< USART0 INTENSET: FRAMERREN Mask */
-#define USART0_INTENSET_PARITYERREN_Pos 14 /*!< USART0 INTENSET: PARITYERREN Position */
-#define USART0_INTENSET_PARITYERREN_Msk (0x01UL << USART0_INTENSET_PARITYERREN_Pos) /*!< USART0 INTENSET: PARITYERREN Mask */
-#define USART0_INTENSET_RXNOISEEN_Pos 15 /*!< USART0 INTENSET: RXNOISEEN Position */
-#define USART0_INTENSET_RXNOISEEN_Msk (0x01UL << USART0_INTENSET_RXNOISEEN_Pos) /*!< USART0 INTENSET: RXNOISEEN Mask */
-#define USART0_INTENSET_ABERREN_Pos 16 /*!< USART0 INTENSET: ABERREN Position */
-#define USART0_INTENSET_ABERREN_Msk (0x01UL << USART0_INTENSET_ABERREN_Pos) /*!< USART0 INTENSET: ABERREN Mask */
-
-/* ------------------------------ u0_usart_INTENCLR ----------------------------- */
-#define USART0_INTENCLR_RXRDYCLR_Pos 0 /*!< USART0 INTENCLR: RXRDYCLR Position */
-#define USART0_INTENCLR_RXRDYCLR_Msk (0x01UL << USART0_INTENCLR_RXRDYCLR_Pos) /*!< USART0 INTENCLR: RXRDYCLR Mask */
-#define USART0_INTENCLR_TXRDYCLR_Pos 2 /*!< USART0 INTENCLR: TXRDYCLR Position */
-#define USART0_INTENCLR_TXRDYCLR_Msk (0x01UL << USART0_INTENCLR_TXRDYCLR_Pos) /*!< USART0 INTENCLR: TXRDYCLR Mask */
-#define USART0_INTENCLR_TXIDLECLR_Pos 3 /*!< USART0 INTENCLR: TXIDLECLR Position */
-#define USART0_INTENCLR_TXIDLECLR_Msk (0x01UL << USART0_INTENCLR_TXIDLECLR_Pos) /*!< USART0 INTENCLR: TXIDLECLR Mask */
-#define USART0_INTENCLR_DELTACTSCLR_Pos 5 /*!< USART0 INTENCLR: DELTACTSCLR Position */
-#define USART0_INTENCLR_DELTACTSCLR_Msk (0x01UL << USART0_INTENCLR_DELTACTSCLR_Pos) /*!< USART0 INTENCLR: DELTACTSCLR Mask */
-#define USART0_INTENCLR_TXDISCLR_Pos 6 /*!< USART0 INTENCLR: TXDISCLR Position */
-#define USART0_INTENCLR_TXDISCLR_Msk (0x01UL << USART0_INTENCLR_TXDISCLR_Pos) /*!< USART0 INTENCLR: TXDISCLR Mask */
-#define USART0_INTENCLR_OVERRUNCLR_Pos 8 /*!< USART0 INTENCLR: OVERRUNCLR Position */
-#define USART0_INTENCLR_OVERRUNCLR_Msk (0x01UL << USART0_INTENCLR_OVERRUNCLR_Pos) /*!< USART0 INTENCLR: OVERRUNCLR Mask */
-#define USART0_INTENCLR_DELTARXBRKCLR_Pos 11 /*!< USART0 INTENCLR: DELTARXBRKCLR Position */
-#define USART0_INTENCLR_DELTARXBRKCLR_Msk (0x01UL << USART0_INTENCLR_DELTARXBRKCLR_Pos) /*!< USART0 INTENCLR: DELTARXBRKCLR Mask */
-#define USART0_INTENCLR_STARTCLR_Pos 12 /*!< USART0 INTENCLR: STARTCLR Position */
-#define USART0_INTENCLR_STARTCLR_Msk (0x01UL << USART0_INTENCLR_STARTCLR_Pos) /*!< USART0 INTENCLR: STARTCLR Mask */
-#define USART0_INTENCLR_FRAMERRCLR_Pos 13 /*!< USART0 INTENCLR: FRAMERRCLR Position */
-#define USART0_INTENCLR_FRAMERRCLR_Msk (0x01UL << USART0_INTENCLR_FRAMERRCLR_Pos) /*!< USART0 INTENCLR: FRAMERRCLR Mask */
-#define USART0_INTENCLR_PARITYERRCLR_Pos 14 /*!< USART0 INTENCLR: PARITYERRCLR Position */
-#define USART0_INTENCLR_PARITYERRCLR_Msk (0x01UL << USART0_INTENCLR_PARITYERRCLR_Pos) /*!< USART0 INTENCLR: PARITYERRCLR Mask */
-#define USART0_INTENCLR_RXNOISECLR_Pos 15 /*!< USART0 INTENCLR: RXNOISECLR Position */
-#define USART0_INTENCLR_RXNOISECLR_Msk (0x01UL << USART0_INTENCLR_RXNOISECLR_Pos) /*!< USART0 INTENCLR: RXNOISECLR Mask */
-#define USART0_INTENCLR_ABERRCLR_Pos 16 /*!< USART0 INTENCLR: ABERRCLR Position */
-#define USART0_INTENCLR_ABERRCLR_Msk (0x01UL << USART0_INTENCLR_ABERRCLR_Pos) /*!< USART0 INTENCLR: ABERRCLR Mask */
-
-/* -------------------------------- u0_usart_BRG -------------------------------- */
-#define USART0_BRG_BRGVAL_Pos 0 /*!< USART0 BRG: BRGVAL Position */
-#define USART0_BRG_BRGVAL_Msk (0x0000ffffUL << USART0_BRG_BRGVAL_Pos) /*!< USART0 BRG: BRGVAL Mask */
-
-/* ------------------------------ u0_usart_INTSTAT ------------------------------ */
-#define USART0_INTSTAT_RX_RDY_Pos 0 /*!< USART0 INTSTAT: RX_RDY Position */
-#define USART0_INTSTAT_RX_RDY_Msk (0x01UL << USART0_INTSTAT_RX_RDY_Pos) /*!< USART0 INTSTAT: RX_RDY Mask */
-#define USART0_INTSTAT_RXIDLE_Pos 1 /*!< USART0 INTSTAT: RXIDLE Position */
-#define USART0_INTSTAT_RXIDLE_Msk (0x01UL << USART0_INTSTAT_RXIDLE_Pos) /*!< USART0 INTSTAT: RXIDLE Mask */
-#define USART0_INTSTAT_TX_RDY_Pos 2 /*!< USART0 INTSTAT: TX_RDY Position */
-#define USART0_INTSTAT_TX_RDY_Msk (0x01UL << USART0_INTSTAT_TX_RDY_Pos) /*!< USART0 INTSTAT: TX_RDY Mask */
-#define USART0_INTSTAT_TXIDLE_Pos 3 /*!< USART0 INTSTAT: TXIDLE Position */
-#define USART0_INTSTAT_TXIDLE_Msk (0x01UL << USART0_INTSTAT_TXIDLE_Pos) /*!< USART0 INTSTAT: TXIDLE Mask */
-#define USART0_INTSTAT_DELTACTS_Pos 5 /*!< USART0 INTSTAT: DELTACTS Position */
-#define USART0_INTSTAT_DELTACTS_Msk (0x01UL << USART0_INTSTAT_DELTACTS_Pos) /*!< USART0 INTSTAT: DELTACTS Mask */
-#define USART0_INTSTAT_TXDIS_Pos 6 /*!< USART0 INTSTAT: TXDIS Position */
-#define USART0_INTSTAT_TXDIS_Msk (0x01UL << USART0_INTSTAT_TXDIS_Pos) /*!< USART0 INTSTAT: TXDIS Mask */
-#define USART0_INTSTAT_OVERRUN_Pos 8 /*!< USART0 INTSTAT: OVERRUN Position */
-#define USART0_INTSTAT_OVERRUN_Msk (0x01UL << USART0_INTSTAT_OVERRUN_Pos) /*!< USART0 INTSTAT: OVERRUN Mask */
-#define USART0_INTSTAT_DELTARXBRK_Pos 11 /*!< USART0 INTSTAT: DELTARXBRK Position */
-#define USART0_INTSTAT_DELTARXBRK_Msk (0x01UL << USART0_INTSTAT_DELTARXBRK_Pos) /*!< USART0 INTSTAT: DELTARXBRK Mask */
-#define USART0_INTSTAT_START_Pos 12 /*!< USART0 INTSTAT: START Position */
-#define USART0_INTSTAT_START_Msk (0x01UL << USART0_INTSTAT_START_Pos) /*!< USART0 INTSTAT: START Mask */
-#define USART0_INTSTAT_FRAMERR_Pos 13 /*!< USART0 INTSTAT: FRAMERR Position */
-#define USART0_INTSTAT_FRAMERR_Msk (0x01UL << USART0_INTSTAT_FRAMERR_Pos) /*!< USART0 INTSTAT: FRAMERR Mask */
-#define USART0_INTSTAT_PARITYERR_Pos 14 /*!< USART0 INTSTAT: PARITYERR Position */
-#define USART0_INTSTAT_PARITYERR_Msk (0x01UL << USART0_INTSTAT_PARITYERR_Pos) /*!< USART0 INTSTAT: PARITYERR Mask */
-#define USART0_INTSTAT_RXNOISE_Pos 15 /*!< USART0 INTSTAT: RXNOISE Position */
-#define USART0_INTSTAT_RXNOISE_Msk (0x01UL << USART0_INTSTAT_RXNOISE_Pos) /*!< USART0 INTSTAT: RXNOISE Mask */
-#define USART0_INTSTAT_ABERR_Pos 16 /*!< USART0 INTSTAT: ABERR Position */
-#define USART0_INTSTAT_ABERR_Msk (0x01UL << USART0_INTSTAT_ABERR_Pos) /*!< USART0 INTSTAT: ABERR Mask */
-
-/* -------------------------------- u0_usart_OSR -------------------------------- */
-#define USART0_OSR_OSRVAL_Pos 0 /*!< USART0 OSR: OSRVAL Position */
-#define USART0_OSR_OSRVAL_Msk (0x0fUL << USART0_OSR_OSRVAL_Pos) /*!< USART0 OSR: OSRVAL Mask */
-
-/* -------------------------------- u0_usart_ADDR ------------------------------- */
-#define USART0_ADDR_ADDRESS_Pos 0 /*!< USART0 ADDR: ADDRESS Position */
-#define USART0_ADDR_ADDRESS_Msk (0x000000ffUL << USART0_ADDR_ADDRESS_Pos) /*!< USART0 ADDR: ADDRESS Mask */
-
-/* ------------------------------ u0_usart_FIFOCFG ------------------------------ */
-#define USART0_FIFOCFG_ENABLETX_Pos 0 /*!< USART0 FIFOCFG: ENABLETX Position */
-#define USART0_FIFOCFG_ENABLETX_Msk (0x01UL << USART0_FIFOCFG_ENABLETX_Pos) /*!< USART0 FIFOCFG: ENABLETX Mask */
-#define USART0_FIFOCFG_ENABLERX_Pos 1 /*!< USART0 FIFOCFG: ENABLERX Position */
-#define USART0_FIFOCFG_ENABLERX_Msk (0x01UL << USART0_FIFOCFG_ENABLERX_Pos) /*!< USART0 FIFOCFG: ENABLERX Mask */
-#define USART0_FIFOCFG_SIZE_Pos 4 /*!< USART0 FIFOCFG: SIZE Position */
-#define USART0_FIFOCFG_SIZE_Msk (0x03UL << USART0_FIFOCFG_SIZE_Pos) /*!< USART0 FIFOCFG: SIZE Mask */
-#define USART0_FIFOCFG_DMATX_Pos 12 /*!< USART0 FIFOCFG: DMATX Position */
-#define USART0_FIFOCFG_DMATX_Msk (0x01UL << USART0_FIFOCFG_DMATX_Pos) /*!< USART0 FIFOCFG: DMATX Mask */
-#define USART0_FIFOCFG_DMARX_Pos 13 /*!< USART0 FIFOCFG: DMARX Position */
-#define USART0_FIFOCFG_DMARX_Msk (0x01UL << USART0_FIFOCFG_DMARX_Pos) /*!< USART0 FIFOCFG: DMARX Mask */
-#define USART0_FIFOCFG_WAKETX_Pos 14 /*!< USART0 FIFOCFG: WAKETX Position */
-#define USART0_FIFOCFG_WAKETX_Msk (0x01UL << USART0_FIFOCFG_WAKETX_Pos) /*!< USART0 FIFOCFG: WAKETX Mask */
-#define USART0_FIFOCFG_WAKERX_Pos 15 /*!< USART0 FIFOCFG: WAKERX Position */
-#define USART0_FIFOCFG_WAKERX_Msk (0x01UL << USART0_FIFOCFG_WAKERX_Pos) /*!< USART0 FIFOCFG: WAKERX Mask */
-#define USART0_FIFOCFG_EMPTYTX_Pos 16 /*!< USART0 FIFOCFG: EMPTYTX Position */
-#define USART0_FIFOCFG_EMPTYTX_Msk (0x01UL << USART0_FIFOCFG_EMPTYTX_Pos) /*!< USART0 FIFOCFG: EMPTYTX Mask */
-#define USART0_FIFOCFG_EMPTYRX_Pos 17 /*!< USART0 FIFOCFG: EMPTYRX Position */
-#define USART0_FIFOCFG_EMPTYRX_Msk (0x01UL << USART0_FIFOCFG_EMPTYRX_Pos) /*!< USART0 FIFOCFG: EMPTYRX Mask */
-#define USART0_FIFOCFG_POPDBG_Pos 18 /*!< USART0 FIFOCFG: POPDBG Position */
-#define USART0_FIFOCFG_POPDBG_Msk (0x01UL << USART0_FIFOCFG_POPDBG_Pos) /*!< USART0 FIFOCFG: POPDBG Mask */
-
-/* ------------------------------ u0_usart_FIFOSTAT ----------------------------- */
-#define USART0_FIFOSTAT_TXERR_Pos 0 /*!< USART0 FIFOSTAT: TXERR Position */
-#define USART0_FIFOSTAT_TXERR_Msk (0x01UL << USART0_FIFOSTAT_TXERR_Pos) /*!< USART0 FIFOSTAT: TXERR Mask */
-#define USART0_FIFOSTAT_RXERR_Pos 1 /*!< USART0 FIFOSTAT: RXERR Position */
-#define USART0_FIFOSTAT_RXERR_Msk (0x01UL << USART0_FIFOSTAT_RXERR_Pos) /*!< USART0 FIFOSTAT: RXERR Mask */
-#define USART0_FIFOSTAT_PERINT_Pos 3 /*!< USART0 FIFOSTAT: PERINT Position */
-#define USART0_FIFOSTAT_PERINT_Msk (0x01UL << USART0_FIFOSTAT_PERINT_Pos) /*!< USART0 FIFOSTAT: PERINT Mask */
-#define USART0_FIFOSTAT_TXEMPTY_Pos 4 /*!< USART0 FIFOSTAT: TXEMPTY Position */
-#define USART0_FIFOSTAT_TXEMPTY_Msk (0x01UL << USART0_FIFOSTAT_TXEMPTY_Pos) /*!< USART0 FIFOSTAT: TXEMPTY Mask */
-#define USART0_FIFOSTAT_TXNOTFULL_Pos 5 /*!< USART0 FIFOSTAT: TXNOTFULL Position */
-#define USART0_FIFOSTAT_TXNOTFULL_Msk (0x01UL << USART0_FIFOSTAT_TXNOTFULL_Pos) /*!< USART0 FIFOSTAT: TXNOTFULL Mask */
-#define USART0_FIFOSTAT_RXNOTEMPTY_Pos 6 /*!< USART0 FIFOSTAT: RXNOTEMPTY Position */
-#define USART0_FIFOSTAT_RXNOTEMPTY_Msk (0x01UL << USART0_FIFOSTAT_RXNOTEMPTY_Pos) /*!< USART0 FIFOSTAT: RXNOTEMPTY Mask */
-#define USART0_FIFOSTAT_RXFULL_Pos 7 /*!< USART0 FIFOSTAT: RXFULL Position */
-#define USART0_FIFOSTAT_RXFULL_Msk (0x01UL << USART0_FIFOSTAT_RXFULL_Pos) /*!< USART0 FIFOSTAT: RXFULL Mask */
-#define USART0_FIFOSTAT_TXLVL_Pos 8 /*!< USART0 FIFOSTAT: TXLVL Position */
-#define USART0_FIFOSTAT_TXLVL_Msk (0x1fUL << USART0_FIFOSTAT_TXLVL_Pos) /*!< USART0 FIFOSTAT: TXLVL Mask */
-#define USART0_FIFOSTAT_RXLVL_Pos 16 /*!< USART0 FIFOSTAT: RXLVL Position */
-#define USART0_FIFOSTAT_RXLVL_Msk (0x1fUL << USART0_FIFOSTAT_RXLVL_Pos) /*!< USART0 FIFOSTAT: RXLVL Mask */
-
-/* ------------------------------ u0_usart_FIFOTRIG ----------------------------- */
-#define USART0_FIFOTRIG_TXLVLENA_Pos 0 /*!< USART0 FIFOTRIG: TXLVLENA Position */
-#define USART0_FIFOTRIG_TXLVLENA_Msk (0x01UL << USART0_FIFOTRIG_TXLVLENA_Pos) /*!< USART0 FIFOTRIG: TXLVLENA Mask */
-#define USART0_FIFOTRIG_RXLVLENA_Pos 1 /*!< USART0 FIFOTRIG: RXLVLENA Position */
-#define USART0_FIFOTRIG_RXLVLENA_Msk (0x01UL << USART0_FIFOTRIG_RXLVLENA_Pos) /*!< USART0 FIFOTRIG: RXLVLENA Mask */
-#define USART0_FIFOTRIG_TXLVL_Pos 8 /*!< USART0 FIFOTRIG: TXLVL Position */
-#define USART0_FIFOTRIG_TXLVL_Msk (0x0fUL << USART0_FIFOTRIG_TXLVL_Pos) /*!< USART0 FIFOTRIG: TXLVL Mask */
-#define USART0_FIFOTRIG_RXLVL_Pos 16 /*!< USART0 FIFOTRIG: RXLVL Position */
-#define USART0_FIFOTRIG_RXLVL_Msk (0x0fUL << USART0_FIFOTRIG_RXLVL_Pos) /*!< USART0 FIFOTRIG: RXLVL Mask */
-
-/* ---------------------------- u0_usart_FIFOINTENSET --------------------------- */
-#define USART0_FIFOINTENSET_TXERR_Pos 0 /*!< USART0 FIFOINTENSET: TXERR Position */
-#define USART0_FIFOINTENSET_TXERR_Msk (0x01UL << USART0_FIFOINTENSET_TXERR_Pos) /*!< USART0 FIFOINTENSET: TXERR Mask */
-#define USART0_FIFOINTENSET_RXERR_Pos 1 /*!< USART0 FIFOINTENSET: RXERR Position */
-#define USART0_FIFOINTENSET_RXERR_Msk (0x01UL << USART0_FIFOINTENSET_RXERR_Pos) /*!< USART0 FIFOINTENSET: RXERR Mask */
-#define USART0_FIFOINTENSET_TXLVL_Pos 2 /*!< USART0 FIFOINTENSET: TXLVL Position */
-#define USART0_FIFOINTENSET_TXLVL_Msk (0x01UL << USART0_FIFOINTENSET_TXLVL_Pos) /*!< USART0 FIFOINTENSET: TXLVL Mask */
-#define USART0_FIFOINTENSET_RXLVL_Pos 3 /*!< USART0 FIFOINTENSET: RXLVL Position */
-#define USART0_FIFOINTENSET_RXLVL_Msk (0x01UL << USART0_FIFOINTENSET_RXLVL_Pos) /*!< USART0 FIFOINTENSET: RXLVL Mask */
-
-/* ---------------------------- u0_usart_FIFOINTENCLR --------------------------- */
-#define USART0_FIFOINTENCLR_TXERR_Pos 0 /*!< USART0 FIFOINTENCLR: TXERR Position */
-#define USART0_FIFOINTENCLR_TXERR_Msk (0x01UL << USART0_FIFOINTENCLR_TXERR_Pos) /*!< USART0 FIFOINTENCLR: TXERR Mask */
-#define USART0_FIFOINTENCLR_RXERR_Pos 1 /*!< USART0 FIFOINTENCLR: RXERR Position */
-#define USART0_FIFOINTENCLR_RXERR_Msk (0x01UL << USART0_FIFOINTENCLR_RXERR_Pos) /*!< USART0 FIFOINTENCLR: RXERR Mask */
-#define USART0_FIFOINTENCLR_TXLVL_Pos 2 /*!< USART0 FIFOINTENCLR: TXLVL Position */
-#define USART0_FIFOINTENCLR_TXLVL_Msk (0x01UL << USART0_FIFOINTENCLR_TXLVL_Pos) /*!< USART0 FIFOINTENCLR: TXLVL Mask */
-#define USART0_FIFOINTENCLR_RXLVL_Pos 3 /*!< USART0 FIFOINTENCLR: RXLVL Position */
-#define USART0_FIFOINTENCLR_RXLVL_Msk (0x01UL << USART0_FIFOINTENCLR_RXLVL_Pos) /*!< USART0 FIFOINTENCLR: RXLVL Mask */
-
-/* ---------------------------- u0_usart_FIFOINTSTAT ---------------------------- */
-#define USART0_FIFOINTSTAT_TXERR_Pos 0 /*!< USART0 FIFOINTSTAT: TXERR Position */
-#define USART0_FIFOINTSTAT_TXERR_Msk (0x01UL << USART0_FIFOINTSTAT_TXERR_Pos) /*!< USART0 FIFOINTSTAT: TXERR Mask */
-#define USART0_FIFOINTSTAT_RXERR_Pos 1 /*!< USART0 FIFOINTSTAT: RXERR Position */
-#define USART0_FIFOINTSTAT_RXERR_Msk (0x01UL << USART0_FIFOINTSTAT_RXERR_Pos) /*!< USART0 FIFOINTSTAT: RXERR Mask */
-#define USART0_FIFOINTSTAT_TXLVL_Pos 2 /*!< USART0 FIFOINTSTAT: TXLVL Position */
-#define USART0_FIFOINTSTAT_TXLVL_Msk (0x01UL << USART0_FIFOINTSTAT_TXLVL_Pos) /*!< USART0 FIFOINTSTAT: TXLVL Mask */
-#define USART0_FIFOINTSTAT_RXLVL_Pos 3 /*!< USART0 FIFOINTSTAT: RXLVL Position */
-#define USART0_FIFOINTSTAT_RXLVL_Msk (0x01UL << USART0_FIFOINTSTAT_RXLVL_Pos) /*!< USART0 FIFOINTSTAT: RXLVL Mask */
-#define USART0_FIFOINTSTAT_PERINT_Pos 4 /*!< USART0 FIFOINTSTAT: PERINT Position */
-#define USART0_FIFOINTSTAT_PERINT_Msk (0x01UL << USART0_FIFOINTSTAT_PERINT_Pos) /*!< USART0 FIFOINTSTAT: PERINT Mask */
-
-/* ------------------------------- u0_usart_FIFOWR ------------------------------ */
-#define USART0_FIFOWR_TXDATA_Pos 0 /*!< USART0 FIFOWR: TXDATA Position */
-#define USART0_FIFOWR_TXDATA_Msk (0x000000ffUL << USART0_FIFOWR_TXDATA_Pos) /*!< USART0 FIFOWR: TXDATA Mask */
-
-/* ------------------------------- u0_usart_FIFORD ------------------------------ */
-#define USART0_FIFORD_RXDATA_Pos 0 /*!< USART0 FIFORD: RXDATA Position */
-#define USART0_FIFORD_RXDATA_Msk (0x000001ffUL << USART0_FIFORD_RXDATA_Pos) /*!< USART0 FIFORD: RXDATA Mask */
-#define USART0_FIFORD_FRAMERR_Pos 13 /*!< USART0 FIFORD: FRAMERR Position */
-#define USART0_FIFORD_FRAMERR_Msk (0x01UL << USART0_FIFORD_FRAMERR_Pos) /*!< USART0 FIFORD: FRAMERR Mask */
-#define USART0_FIFORD_PARITYERR_Pos 14 /*!< USART0 FIFORD: PARITYERR Position */
-#define USART0_FIFORD_PARITYERR_Msk (0x01UL << USART0_FIFORD_PARITYERR_Pos) /*!< USART0 FIFORD: PARITYERR Mask */
-#define USART0_FIFORD_RXNOISE_Pos 15 /*!< USART0 FIFORD: RXNOISE Position */
-#define USART0_FIFORD_RXNOISE_Msk (0x01UL << USART0_FIFORD_RXNOISE_Pos) /*!< USART0 FIFORD: RXNOISE Mask */
-
-/* ---------------------------- u0_usart_FIFORDNOPOP ---------------------------- */
-#define USART0_FIFORDNOPOP_RXDATA_Pos 0 /*!< USART0 FIFORDNOPOP: RXDATA Position */
-#define USART0_FIFORDNOPOP_RXDATA_Msk (0x000001ffUL << USART0_FIFORDNOPOP_RXDATA_Pos) /*!< USART0 FIFORDNOPOP: RXDATA Mask */
-#define USART0_FIFORDNOPOP_FRAMERR_Pos 13 /*!< USART0 FIFORDNOPOP: FRAMERR Position */
-#define USART0_FIFORDNOPOP_FRAMERR_Msk (0x01UL << USART0_FIFORDNOPOP_FRAMERR_Pos) /*!< USART0 FIFORDNOPOP: FRAMERR Mask */
-#define USART0_FIFORDNOPOP_PARITYERR_Pos 14 /*!< USART0 FIFORDNOPOP: PARITYERR Position */
-#define USART0_FIFORDNOPOP_PARITYERR_Msk (0x01UL << USART0_FIFORDNOPOP_PARITYERR_Pos) /*!< USART0 FIFORDNOPOP: PARITYERR Mask */
-#define USART0_FIFORDNOPOP_RXNOISE_Pos 15 /*!< USART0 FIFORDNOPOP: RXNOISE Position */
-#define USART0_FIFORDNOPOP_RXNOISE_Msk (0x01UL << USART0_FIFORDNOPOP_RXNOISE_Pos) /*!< USART0 FIFORDNOPOP: RXNOISE Mask */
-
-/* ------------------------------- u0_usart_PSELID ------------------------------ */
-#define USART0_PSELID_PERSEL_Pos 0 /*!< USART0 PSELID: PERSEL Position */
-#define USART0_PSELID_PERSEL_Msk (0x07UL << USART0_PSELID_PERSEL_Pos) /*!< USART0 PSELID: PERSEL Mask */
-#define USART0_PSELID_LOCK_Pos 3 /*!< USART0 PSELID: LOCK Position */
-#define USART0_PSELID_LOCK_Msk (0x01UL << USART0_PSELID_LOCK_Pos) /*!< USART0 PSELID: LOCK Mask */
-#define USART0_PSELID_USARTPRESENT_Pos 4 /*!< USART0 PSELID: USARTPRESENT Position */
-#define USART0_PSELID_USARTPRESENT_Msk (0x01UL << USART0_PSELID_USARTPRESENT_Pos) /*!< USART0 PSELID: USARTPRESENT Mask */
-#define USART0_PSELID_ID_Pos 12 /*!< USART0 PSELID: ID Position */
-#define USART0_PSELID_ID_Msk (0x000fffffUL << USART0_PSELID_ID_Pos) /*!< USART0 PSELID: ID Mask */
-
-/* --------------------------------- u0_usart_ID -------------------------------- */
-#define USART0_ID_APERTURE_Pos 0 /*!< USART0 ID: APERTURE Position */
-#define USART0_ID_APERTURE_Msk (0x000000ffUL << USART0_ID_APERTURE_Pos) /*!< USART0 ID: APERTURE Mask */
-#define USART0_ID_MIN_REV_Pos 8 /*!< USART0 ID: MIN_REV Position */
-#define USART0_ID_MIN_REV_Msk (0x0fUL << USART0_ID_MIN_REV_Pos) /*!< USART0 ID: MIN_REV Mask */
-#define USART0_ID_MAJ_REV_Pos 12 /*!< USART0 ID: MAJ_REV Position */
-#define USART0_ID_MAJ_REV_Msk (0x0fUL << USART0_ID_MAJ_REV_Pos) /*!< USART0 ID: MAJ_REV Mask */
-#define USART0_ID_ID_Pos 16 /*!< USART0 ID: ID Position */
-#define USART0_ID_ID_Msk (0x0000ffffUL << USART0_ID_ID_Pos) /*!< USART0 ID: ID Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u1_usart' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* -------------------------------- u1_usart_CFG -------------------------------- */
-#define USART1_CFG_ENABLE_Pos 0 /*!< USART1 CFG: ENABLE Position */
-#define USART1_CFG_ENABLE_Msk (0x01UL << USART1_CFG_ENABLE_Pos) /*!< USART1 CFG: ENABLE Mask */
-#define USART1_CFG_DATALEN_Pos 2 /*!< USART1 CFG: DATALEN Position */
-#define USART1_CFG_DATALEN_Msk (0x03UL << USART1_CFG_DATALEN_Pos) /*!< USART1 CFG: DATALEN Mask */
-#define USART1_CFG_PARITYSEL_Pos 4 /*!< USART1 CFG: PARITYSEL Position */
-#define USART1_CFG_PARITYSEL_Msk (0x03UL << USART1_CFG_PARITYSEL_Pos) /*!< USART1 CFG: PARITYSEL Mask */
-#define USART1_CFG_STOPLEN_Pos 6 /*!< USART1 CFG: STOPLEN Position */
-#define USART1_CFG_STOPLEN_Msk (0x01UL << USART1_CFG_STOPLEN_Pos) /*!< USART1 CFG: STOPLEN Mask */
-#define USART1_CFG_MODE32K_Pos 7 /*!< USART1 CFG: MODE32K Position */
-#define USART1_CFG_MODE32K_Msk (0x01UL << USART1_CFG_MODE32K_Pos) /*!< USART1 CFG: MODE32K Mask */
-#define USART1_CFG_LINMODE_Pos 8 /*!< USART1 CFG: LINMODE Position */
-#define USART1_CFG_LINMODE_Msk (0x01UL << USART1_CFG_LINMODE_Pos) /*!< USART1 CFG: LINMODE Mask */
-#define USART1_CFG_CTSEN_Pos 9 /*!< USART1 CFG: CTSEN Position */
-#define USART1_CFG_CTSEN_Msk (0x01UL << USART1_CFG_CTSEN_Pos) /*!< USART1 CFG: CTSEN Mask */
-#define USART1_CFG_SYNCEN_Pos 11 /*!< USART1 CFG: SYNCEN Position */
-#define USART1_CFG_SYNCEN_Msk (0x01UL << USART1_CFG_SYNCEN_Pos) /*!< USART1 CFG: SYNCEN Mask */
-#define USART1_CFG_CLKPOL_Pos 12 /*!< USART1 CFG: CLKPOL Position */
-#define USART1_CFG_CLKPOL_Msk (0x01UL << USART1_CFG_CLKPOL_Pos) /*!< USART1 CFG: CLKPOL Mask */
-#define USART1_CFG_SYNCMST_Pos 14 /*!< USART1 CFG: SYNCMST Position */
-#define USART1_CFG_SYNCMST_Msk (0x01UL << USART1_CFG_SYNCMST_Pos) /*!< USART1 CFG: SYNCMST Mask */
-#define USART1_CFG_LOOP_Pos 15 /*!< USART1 CFG: LOOP Position */
-#define USART1_CFG_LOOP_Msk (0x01UL << USART1_CFG_LOOP_Pos) /*!< USART1 CFG: LOOP Mask */
-#define USART1_CFG_IOMODE_Pos 16 /*!< USART1 CFG: IOMODE Position */
-#define USART1_CFG_IOMODE_Msk (0x01UL << USART1_CFG_IOMODE_Pos) /*!< USART1 CFG: IOMODE Mask */
-#define USART1_CFG_OETA_Pos 18 /*!< USART1 CFG: OETA Position */
-#define USART1_CFG_OETA_Msk (0x01UL << USART1_CFG_OETA_Pos) /*!< USART1 CFG: OETA Mask */
-#define USART1_CFG_AUTOADDR_Pos 19 /*!< USART1 CFG: AUTOADDR Position */
-#define USART1_CFG_AUTOADDR_Msk (0x01UL << USART1_CFG_AUTOADDR_Pos) /*!< USART1 CFG: AUTOADDR Mask */
-#define USART1_CFG_OESEL_Pos 20 /*!< USART1 CFG: OESEL Position */
-#define USART1_CFG_OESEL_Msk (0x01UL << USART1_CFG_OESEL_Pos) /*!< USART1 CFG: OESEL Mask */
-#define USART1_CFG_OEPOL_Pos 21 /*!< USART1 CFG: OEPOL Position */
-#define USART1_CFG_OEPOL_Msk (0x01UL << USART1_CFG_OEPOL_Pos) /*!< USART1 CFG: OEPOL Mask */
-#define USART1_CFG_RXPOL_Pos 22 /*!< USART1 CFG: RXPOL Position */
-#define USART1_CFG_RXPOL_Msk (0x01UL << USART1_CFG_RXPOL_Pos) /*!< USART1 CFG: RXPOL Mask */
-#define USART1_CFG_TXPOL_Pos 23 /*!< USART1 CFG: TXPOL Position */
-#define USART1_CFG_TXPOL_Msk (0x01UL << USART1_CFG_TXPOL_Pos) /*!< USART1 CFG: TXPOL Mask */
-
-/* -------------------------------- u1_usart_CTL -------------------------------- */
-#define USART1_CTL_TXBRKEN_Pos 1 /*!< USART1 CTL: TXBRKEN Position */
-#define USART1_CTL_TXBRKEN_Msk (0x01UL << USART1_CTL_TXBRKEN_Pos) /*!< USART1 CTL: TXBRKEN Mask */
-#define USART1_CTL_ADDRDET_Pos 2 /*!< USART1 CTL: ADDRDET Position */
-#define USART1_CTL_ADDRDET_Msk (0x01UL << USART1_CTL_ADDRDET_Pos) /*!< USART1 CTL: ADDRDET Mask */
-#define USART1_CTL_TXDIS_Pos 6 /*!< USART1 CTL: TXDIS Position */
-#define USART1_CTL_TXDIS_Msk (0x01UL << USART1_CTL_TXDIS_Pos) /*!< USART1 CTL: TXDIS Mask */
-#define USART1_CTL_CC_Pos 8 /*!< USART1 CTL: CC Position */
-#define USART1_CTL_CC_Msk (0x01UL << USART1_CTL_CC_Pos) /*!< USART1 CTL: CC Mask */
-#define USART1_CTL_CLRCCONRX_Pos 9 /*!< USART1 CTL: CLRCCONRX Position */
-#define USART1_CTL_CLRCCONRX_Msk (0x01UL << USART1_CTL_CLRCCONRX_Pos) /*!< USART1 CTL: CLRCCONRX Mask */
-#define USART1_CTL_AUTOBAUD_Pos 16 /*!< USART1 CTL: AUTOBAUD Position */
-#define USART1_CTL_AUTOBAUD_Msk (0x01UL << USART1_CTL_AUTOBAUD_Pos) /*!< USART1 CTL: AUTOBAUD Mask */
-
-/* -------------------------------- u1_usart_STAT ------------------------------- */
-#define USART1_STAT_RXIDLE_Pos 1 /*!< USART1 STAT: RXIDLE Position */
-#define USART1_STAT_RXIDLE_Msk (0x01UL << USART1_STAT_RXIDLE_Pos) /*!< USART1 STAT: RXIDLE Mask */
-#define USART1_STAT_TXIDLE_Pos 3 /*!< USART1 STAT: TXIDLE Position */
-#define USART1_STAT_TXIDLE_Msk (0x01UL << USART1_STAT_TXIDLE_Pos) /*!< USART1 STAT: TXIDLE Mask */
-#define USART1_STAT_CTS_Pos 4 /*!< USART1 STAT: CTS Position */
-#define USART1_STAT_CTS_Msk (0x01UL << USART1_STAT_CTS_Pos) /*!< USART1 STAT: CTS Mask */
-#define USART1_STAT_DELTACTS_Pos 5 /*!< USART1 STAT: DELTACTS Position */
-#define USART1_STAT_DELTACTS_Msk (0x01UL << USART1_STAT_DELTACTS_Pos) /*!< USART1 STAT: DELTACTS Mask */
-#define USART1_STAT_TXDISSTAT_Pos 6 /*!< USART1 STAT: TXDISSTAT Position */
-#define USART1_STAT_TXDISSTAT_Msk (0x01UL << USART1_STAT_TXDISSTAT_Pos) /*!< USART1 STAT: TXDISSTAT Mask */
-#define USART1_STAT_OVERRUNINT_Pos 8 /*!< USART1 STAT: OVERRUNINT Position */
-#define USART1_STAT_OVERRUNINT_Msk (0x01UL << USART1_STAT_OVERRUNINT_Pos) /*!< USART1 STAT: OVERRUNINT Mask */
-#define USART1_STAT_RXBRK_Pos 10 /*!< USART1 STAT: RXBRK Position */
-#define USART1_STAT_RXBRK_Msk (0x01UL << USART1_STAT_RXBRK_Pos) /*!< USART1 STAT: RXBRK Mask */
-#define USART1_STAT_DELTARXBRK_Pos 11 /*!< USART1 STAT: DELTARXBRK Position */
-#define USART1_STAT_DELTARXBRK_Msk (0x01UL << USART1_STAT_DELTARXBRK_Pos) /*!< USART1 STAT: DELTARXBRK Mask */
-#define USART1_STAT_START_Pos 12 /*!< USART1 STAT: START Position */
-#define USART1_STAT_START_Msk (0x01UL << USART1_STAT_START_Pos) /*!< USART1 STAT: START Mask */
-#define USART1_STAT_FRAMERRINT_Pos 13 /*!< USART1 STAT: FRAMERRINT Position */
-#define USART1_STAT_FRAMERRINT_Msk (0x01UL << USART1_STAT_FRAMERRINT_Pos) /*!< USART1 STAT: FRAMERRINT Mask */
-#define USART1_STAT_PARITYERRINT_Pos 14 /*!< USART1 STAT: PARITYERRINT Position */
-#define USART1_STAT_PARITYERRINT_Msk (0x01UL << USART1_STAT_PARITYERRINT_Pos) /*!< USART1 STAT: PARITYERRINT Mask */
-#define USART1_STAT_RXNOISEINT_Pos 15 /*!< USART1 STAT: RXNOISEINT Position */
-#define USART1_STAT_RXNOISEINT_Msk (0x01UL << USART1_STAT_RXNOISEINT_Pos) /*!< USART1 STAT: RXNOISEINT Mask */
-#define USART1_STAT_ABERR_Pos 16 /*!< USART1 STAT: ABERR Position */
-#define USART1_STAT_ABERR_Msk (0x01UL << USART1_STAT_ABERR_Pos) /*!< USART1 STAT: ABERR Mask */
-
-/* ------------------------------ u1_usart_INTENSET ----------------------------- */
-#define USART1_INTENSET_RXRDYEN_Pos 0 /*!< USART1 INTENSET: RXRDYEN Position */
-#define USART1_INTENSET_RXRDYEN_Msk (0x01UL << USART1_INTENSET_RXRDYEN_Pos) /*!< USART1 INTENSET: RXRDYEN Mask */
-#define USART1_INTENSET_TXRDTEN_Pos 2 /*!< USART1 INTENSET: TXRDTEN Position */
-#define USART1_INTENSET_TXRDTEN_Msk (0x01UL << USART1_INTENSET_TXRDTEN_Pos) /*!< USART1 INTENSET: TXRDTEN Mask */
-#define USART1_INTENSET_TXIDLEEN_Pos 3 /*!< USART1 INTENSET: TXIDLEEN Position */
-#define USART1_INTENSET_TXIDLEEN_Msk (0x01UL << USART1_INTENSET_TXIDLEEN_Pos) /*!< USART1 INTENSET: TXIDLEEN Mask */
-#define USART1_INTENSET_DELTACTSEN_Pos 5 /*!< USART1 INTENSET: DELTACTSEN Position */
-#define USART1_INTENSET_DELTACTSEN_Msk (0x01UL << USART1_INTENSET_DELTACTSEN_Pos) /*!< USART1 INTENSET: DELTACTSEN Mask */
-#define USART1_INTENSET_TXDISEN_Pos 6 /*!< USART1 INTENSET: TXDISEN Position */
-#define USART1_INTENSET_TXDISEN_Msk (0x01UL << USART1_INTENSET_TXDISEN_Pos) /*!< USART1 INTENSET: TXDISEN Mask */
-#define USART1_INTENSET_OVERRUNEN_Pos 8 /*!< USART1 INTENSET: OVERRUNEN Position */
-#define USART1_INTENSET_OVERRUNEN_Msk (0x01UL << USART1_INTENSET_OVERRUNEN_Pos) /*!< USART1 INTENSET: OVERRUNEN Mask */
-#define USART1_INTENSET_DELTARXBRKEN_Pos 11 /*!< USART1 INTENSET: DELTARXBRKEN Position */
-#define USART1_INTENSET_DELTARXBRKEN_Msk (0x01UL << USART1_INTENSET_DELTARXBRKEN_Pos) /*!< USART1 INTENSET: DELTARXBRKEN Mask */
-#define USART1_INTENSET_STARTEN_Pos 12 /*!< USART1 INTENSET: STARTEN Position */
-#define USART1_INTENSET_STARTEN_Msk (0x01UL << USART1_INTENSET_STARTEN_Pos) /*!< USART1 INTENSET: STARTEN Mask */
-#define USART1_INTENSET_FRAMERREN_Pos 13 /*!< USART1 INTENSET: FRAMERREN Position */
-#define USART1_INTENSET_FRAMERREN_Msk (0x01UL << USART1_INTENSET_FRAMERREN_Pos) /*!< USART1 INTENSET: FRAMERREN Mask */
-#define USART1_INTENSET_PARITYERREN_Pos 14 /*!< USART1 INTENSET: PARITYERREN Position */
-#define USART1_INTENSET_PARITYERREN_Msk (0x01UL << USART1_INTENSET_PARITYERREN_Pos) /*!< USART1 INTENSET: PARITYERREN Mask */
-#define USART1_INTENSET_RXNOISEEN_Pos 15 /*!< USART1 INTENSET: RXNOISEEN Position */
-#define USART1_INTENSET_RXNOISEEN_Msk (0x01UL << USART1_INTENSET_RXNOISEEN_Pos) /*!< USART1 INTENSET: RXNOISEEN Mask */
-#define USART1_INTENSET_ABERREN_Pos 16 /*!< USART1 INTENSET: ABERREN Position */
-#define USART1_INTENSET_ABERREN_Msk (0x01UL << USART1_INTENSET_ABERREN_Pos) /*!< USART1 INTENSET: ABERREN Mask */
-
-/* ------------------------------ u1_usart_INTENCLR ----------------------------- */
-#define USART1_INTENCLR_RXRDYCLR_Pos 0 /*!< USART1 INTENCLR: RXRDYCLR Position */
-#define USART1_INTENCLR_RXRDYCLR_Msk (0x01UL << USART1_INTENCLR_RXRDYCLR_Pos) /*!< USART1 INTENCLR: RXRDYCLR Mask */
-#define USART1_INTENCLR_TXRDYCLR_Pos 2 /*!< USART1 INTENCLR: TXRDYCLR Position */
-#define USART1_INTENCLR_TXRDYCLR_Msk (0x01UL << USART1_INTENCLR_TXRDYCLR_Pos) /*!< USART1 INTENCLR: TXRDYCLR Mask */
-#define USART1_INTENCLR_TXIDLECLR_Pos 3 /*!< USART1 INTENCLR: TXIDLECLR Position */
-#define USART1_INTENCLR_TXIDLECLR_Msk (0x01UL << USART1_INTENCLR_TXIDLECLR_Pos) /*!< USART1 INTENCLR: TXIDLECLR Mask */
-#define USART1_INTENCLR_DELTACTSCLR_Pos 5 /*!< USART1 INTENCLR: DELTACTSCLR Position */
-#define USART1_INTENCLR_DELTACTSCLR_Msk (0x01UL << USART1_INTENCLR_DELTACTSCLR_Pos) /*!< USART1 INTENCLR: DELTACTSCLR Mask */
-#define USART1_INTENCLR_TXDISCLR_Pos 6 /*!< USART1 INTENCLR: TXDISCLR Position */
-#define USART1_INTENCLR_TXDISCLR_Msk (0x01UL << USART1_INTENCLR_TXDISCLR_Pos) /*!< USART1 INTENCLR: TXDISCLR Mask */
-#define USART1_INTENCLR_OVERRUNCLR_Pos 8 /*!< USART1 INTENCLR: OVERRUNCLR Position */
-#define USART1_INTENCLR_OVERRUNCLR_Msk (0x01UL << USART1_INTENCLR_OVERRUNCLR_Pos) /*!< USART1 INTENCLR: OVERRUNCLR Mask */
-#define USART1_INTENCLR_DELTARXBRKCLR_Pos 11 /*!< USART1 INTENCLR: DELTARXBRKCLR Position */
-#define USART1_INTENCLR_DELTARXBRKCLR_Msk (0x01UL << USART1_INTENCLR_DELTARXBRKCLR_Pos) /*!< USART1 INTENCLR: DELTARXBRKCLR Mask */
-#define USART1_INTENCLR_STARTCLR_Pos 12 /*!< USART1 INTENCLR: STARTCLR Position */
-#define USART1_INTENCLR_STARTCLR_Msk (0x01UL << USART1_INTENCLR_STARTCLR_Pos) /*!< USART1 INTENCLR: STARTCLR Mask */
-#define USART1_INTENCLR_FRAMERRCLR_Pos 13 /*!< USART1 INTENCLR: FRAMERRCLR Position */
-#define USART1_INTENCLR_FRAMERRCLR_Msk (0x01UL << USART1_INTENCLR_FRAMERRCLR_Pos) /*!< USART1 INTENCLR: FRAMERRCLR Mask */
-#define USART1_INTENCLR_PARITYERRCLR_Pos 14 /*!< USART1 INTENCLR: PARITYERRCLR Position */
-#define USART1_INTENCLR_PARITYERRCLR_Msk (0x01UL << USART1_INTENCLR_PARITYERRCLR_Pos) /*!< USART1 INTENCLR: PARITYERRCLR Mask */
-#define USART1_INTENCLR_RXNOISECLR_Pos 15 /*!< USART1 INTENCLR: RXNOISECLR Position */
-#define USART1_INTENCLR_RXNOISECLR_Msk (0x01UL << USART1_INTENCLR_RXNOISECLR_Pos) /*!< USART1 INTENCLR: RXNOISECLR Mask */
-#define USART1_INTENCLR_ABERRCLR_Pos 16 /*!< USART1 INTENCLR: ABERRCLR Position */
-#define USART1_INTENCLR_ABERRCLR_Msk (0x01UL << USART1_INTENCLR_ABERRCLR_Pos) /*!< USART1 INTENCLR: ABERRCLR Mask */
-
-/* -------------------------------- u1_usart_BRG -------------------------------- */
-#define USART1_BRG_BRGVAL_Pos 0 /*!< USART1 BRG: BRGVAL Position */
-#define USART1_BRG_BRGVAL_Msk (0x0000ffffUL << USART1_BRG_BRGVAL_Pos) /*!< USART1 BRG: BRGVAL Mask */
-
-/* ------------------------------ u1_usart_INTSTAT ------------------------------ */
-#define USART1_INTSTAT_RX_RDY_Pos 0 /*!< USART1 INTSTAT: RX_RDY Position */
-#define USART1_INTSTAT_RX_RDY_Msk (0x01UL << USART1_INTSTAT_RX_RDY_Pos) /*!< USART1 INTSTAT: RX_RDY Mask */
-#define USART1_INTSTAT_RXIDLE_Pos 1 /*!< USART1 INTSTAT: RXIDLE Position */
-#define USART1_INTSTAT_RXIDLE_Msk (0x01UL << USART1_INTSTAT_RXIDLE_Pos) /*!< USART1 INTSTAT: RXIDLE Mask */
-#define USART1_INTSTAT_TX_RDY_Pos 2 /*!< USART1 INTSTAT: TX_RDY Position */
-#define USART1_INTSTAT_TX_RDY_Msk (0x01UL << USART1_INTSTAT_TX_RDY_Pos) /*!< USART1 INTSTAT: TX_RDY Mask */
-#define USART1_INTSTAT_TXIDLE_Pos 3 /*!< USART1 INTSTAT: TXIDLE Position */
-#define USART1_INTSTAT_TXIDLE_Msk (0x01UL << USART1_INTSTAT_TXIDLE_Pos) /*!< USART1 INTSTAT: TXIDLE Mask */
-#define USART1_INTSTAT_DELTACTS_Pos 5 /*!< USART1 INTSTAT: DELTACTS Position */
-#define USART1_INTSTAT_DELTACTS_Msk (0x01UL << USART1_INTSTAT_DELTACTS_Pos) /*!< USART1 INTSTAT: DELTACTS Mask */
-#define USART1_INTSTAT_TXDIS_Pos 6 /*!< USART1 INTSTAT: TXDIS Position */
-#define USART1_INTSTAT_TXDIS_Msk (0x01UL << USART1_INTSTAT_TXDIS_Pos) /*!< USART1 INTSTAT: TXDIS Mask */
-#define USART1_INTSTAT_OVERRUN_Pos 8 /*!< USART1 INTSTAT: OVERRUN Position */
-#define USART1_INTSTAT_OVERRUN_Msk (0x01UL << USART1_INTSTAT_OVERRUN_Pos) /*!< USART1 INTSTAT: OVERRUN Mask */
-#define USART1_INTSTAT_DELTARXBRK_Pos 11 /*!< USART1 INTSTAT: DELTARXBRK Position */
-#define USART1_INTSTAT_DELTARXBRK_Msk (0x01UL << USART1_INTSTAT_DELTARXBRK_Pos) /*!< USART1 INTSTAT: DELTARXBRK Mask */
-#define USART1_INTSTAT_START_Pos 12 /*!< USART1 INTSTAT: START Position */
-#define USART1_INTSTAT_START_Msk (0x01UL << USART1_INTSTAT_START_Pos) /*!< USART1 INTSTAT: START Mask */
-#define USART1_INTSTAT_FRAMERR_Pos 13 /*!< USART1 INTSTAT: FRAMERR Position */
-#define USART1_INTSTAT_FRAMERR_Msk (0x01UL << USART1_INTSTAT_FRAMERR_Pos) /*!< USART1 INTSTAT: FRAMERR Mask */
-#define USART1_INTSTAT_PARITYERR_Pos 14 /*!< USART1 INTSTAT: PARITYERR Position */
-#define USART1_INTSTAT_PARITYERR_Msk (0x01UL << USART1_INTSTAT_PARITYERR_Pos) /*!< USART1 INTSTAT: PARITYERR Mask */
-#define USART1_INTSTAT_RXNOISE_Pos 15 /*!< USART1 INTSTAT: RXNOISE Position */
-#define USART1_INTSTAT_RXNOISE_Msk (0x01UL << USART1_INTSTAT_RXNOISE_Pos) /*!< USART1 INTSTAT: RXNOISE Mask */
-#define USART1_INTSTAT_ABERR_Pos 16 /*!< USART1 INTSTAT: ABERR Position */
-#define USART1_INTSTAT_ABERR_Msk (0x01UL << USART1_INTSTAT_ABERR_Pos) /*!< USART1 INTSTAT: ABERR Mask */
-
-/* -------------------------------- u1_usart_OSR -------------------------------- */
-#define USART1_OSR_OSRVAL_Pos 0 /*!< USART1 OSR: OSRVAL Position */
-#define USART1_OSR_OSRVAL_Msk (0x0fUL << USART1_OSR_OSRVAL_Pos) /*!< USART1 OSR: OSRVAL Mask */
-
-/* -------------------------------- u1_usart_ADDR ------------------------------- */
-#define USART1_ADDR_ADDRESS_Pos 0 /*!< USART1 ADDR: ADDRESS Position */
-#define USART1_ADDR_ADDRESS_Msk (0x000000ffUL << USART1_ADDR_ADDRESS_Pos) /*!< USART1 ADDR: ADDRESS Mask */
-
-/* ------------------------------ u1_usart_FIFOCFG ------------------------------ */
-#define USART1_FIFOCFG_ENABLETX_Pos 0 /*!< USART1 FIFOCFG: ENABLETX Position */
-#define USART1_FIFOCFG_ENABLETX_Msk (0x01UL << USART1_FIFOCFG_ENABLETX_Pos) /*!< USART1 FIFOCFG: ENABLETX Mask */
-#define USART1_FIFOCFG_ENABLERX_Pos 1 /*!< USART1 FIFOCFG: ENABLERX Position */
-#define USART1_FIFOCFG_ENABLERX_Msk (0x01UL << USART1_FIFOCFG_ENABLERX_Pos) /*!< USART1 FIFOCFG: ENABLERX Mask */
-#define USART1_FIFOCFG_SIZE_Pos 4 /*!< USART1 FIFOCFG: SIZE Position */
-#define USART1_FIFOCFG_SIZE_Msk (0x03UL << USART1_FIFOCFG_SIZE_Pos) /*!< USART1 FIFOCFG: SIZE Mask */
-#define USART1_FIFOCFG_DMATX_Pos 12 /*!< USART1 FIFOCFG: DMATX Position */
-#define USART1_FIFOCFG_DMATX_Msk (0x01UL << USART1_FIFOCFG_DMATX_Pos) /*!< USART1 FIFOCFG: DMATX Mask */
-#define USART1_FIFOCFG_DMARX_Pos 13 /*!< USART1 FIFOCFG: DMARX Position */
-#define USART1_FIFOCFG_DMARX_Msk (0x01UL << USART1_FIFOCFG_DMARX_Pos) /*!< USART1 FIFOCFG: DMARX Mask */
-#define USART1_FIFOCFG_WAKETX_Pos 14 /*!< USART1 FIFOCFG: WAKETX Position */
-#define USART1_FIFOCFG_WAKETX_Msk (0x01UL << USART1_FIFOCFG_WAKETX_Pos) /*!< USART1 FIFOCFG: WAKETX Mask */
-#define USART1_FIFOCFG_WAKERX_Pos 15 /*!< USART1 FIFOCFG: WAKERX Position */
-#define USART1_FIFOCFG_WAKERX_Msk (0x01UL << USART1_FIFOCFG_WAKERX_Pos) /*!< USART1 FIFOCFG: WAKERX Mask */
-#define USART1_FIFOCFG_EMPTYTX_Pos 16 /*!< USART1 FIFOCFG: EMPTYTX Position */
-#define USART1_FIFOCFG_EMPTYTX_Msk (0x01UL << USART1_FIFOCFG_EMPTYTX_Pos) /*!< USART1 FIFOCFG: EMPTYTX Mask */
-#define USART1_FIFOCFG_EMPTYRX_Pos 17 /*!< USART1 FIFOCFG: EMPTYRX Position */
-#define USART1_FIFOCFG_EMPTYRX_Msk (0x01UL << USART1_FIFOCFG_EMPTYRX_Pos) /*!< USART1 FIFOCFG: EMPTYRX Mask */
-#define USART1_FIFOCFG_POPDBG_Pos 18 /*!< USART1 FIFOCFG: POPDBG Position */
-#define USART1_FIFOCFG_POPDBG_Msk (0x01UL << USART1_FIFOCFG_POPDBG_Pos) /*!< USART1 FIFOCFG: POPDBG Mask */
-
-/* ------------------------------ u1_usart_FIFOSTAT ----------------------------- */
-#define USART1_FIFOSTAT_TXERR_Pos 0 /*!< USART1 FIFOSTAT: TXERR Position */
-#define USART1_FIFOSTAT_TXERR_Msk (0x01UL << USART1_FIFOSTAT_TXERR_Pos) /*!< USART1 FIFOSTAT: TXERR Mask */
-#define USART1_FIFOSTAT_RXERR_Pos 1 /*!< USART1 FIFOSTAT: RXERR Position */
-#define USART1_FIFOSTAT_RXERR_Msk (0x01UL << USART1_FIFOSTAT_RXERR_Pos) /*!< USART1 FIFOSTAT: RXERR Mask */
-#define USART1_FIFOSTAT_PERINT_Pos 3 /*!< USART1 FIFOSTAT: PERINT Position */
-#define USART1_FIFOSTAT_PERINT_Msk (0x01UL << USART1_FIFOSTAT_PERINT_Pos) /*!< USART1 FIFOSTAT: PERINT Mask */
-#define USART1_FIFOSTAT_TXEMPTY_Pos 4 /*!< USART1 FIFOSTAT: TXEMPTY Position */
-#define USART1_FIFOSTAT_TXEMPTY_Msk (0x01UL << USART1_FIFOSTAT_TXEMPTY_Pos) /*!< USART1 FIFOSTAT: TXEMPTY Mask */
-#define USART1_FIFOSTAT_TXNOTFULL_Pos 5 /*!< USART1 FIFOSTAT: TXNOTFULL Position */
-#define USART1_FIFOSTAT_TXNOTFULL_Msk (0x01UL << USART1_FIFOSTAT_TXNOTFULL_Pos) /*!< USART1 FIFOSTAT: TXNOTFULL Mask */
-#define USART1_FIFOSTAT_RXNOTEMPTY_Pos 6 /*!< USART1 FIFOSTAT: RXNOTEMPTY Position */
-#define USART1_FIFOSTAT_RXNOTEMPTY_Msk (0x01UL << USART1_FIFOSTAT_RXNOTEMPTY_Pos) /*!< USART1 FIFOSTAT: RXNOTEMPTY Mask */
-#define USART1_FIFOSTAT_RXFULL_Pos 7 /*!< USART1 FIFOSTAT: RXFULL Position */
-#define USART1_FIFOSTAT_RXFULL_Msk (0x01UL << USART1_FIFOSTAT_RXFULL_Pos) /*!< USART1 FIFOSTAT: RXFULL Mask */
-#define USART1_FIFOSTAT_TXLVL_Pos 8 /*!< USART1 FIFOSTAT: TXLVL Position */
-#define USART1_FIFOSTAT_TXLVL_Msk (0x1fUL << USART1_FIFOSTAT_TXLVL_Pos) /*!< USART1 FIFOSTAT: TXLVL Mask */
-#define USART1_FIFOSTAT_RXLVL_Pos 16 /*!< USART1 FIFOSTAT: RXLVL Position */
-#define USART1_FIFOSTAT_RXLVL_Msk (0x1fUL << USART1_FIFOSTAT_RXLVL_Pos) /*!< USART1 FIFOSTAT: RXLVL Mask */
-
-/* ------------------------------ u1_usart_FIFOTRIG ----------------------------- */
-#define USART1_FIFOTRIG_TXLVLENA_Pos 0 /*!< USART1 FIFOTRIG: TXLVLENA Position */
-#define USART1_FIFOTRIG_TXLVLENA_Msk (0x01UL << USART1_FIFOTRIG_TXLVLENA_Pos) /*!< USART1 FIFOTRIG: TXLVLENA Mask */
-#define USART1_FIFOTRIG_RXLVLENA_Pos 1 /*!< USART1 FIFOTRIG: RXLVLENA Position */
-#define USART1_FIFOTRIG_RXLVLENA_Msk (0x01UL << USART1_FIFOTRIG_RXLVLENA_Pos) /*!< USART1 FIFOTRIG: RXLVLENA Mask */
-#define USART1_FIFOTRIG_TXLVL_Pos 8 /*!< USART1 FIFOTRIG: TXLVL Position */
-#define USART1_FIFOTRIG_TXLVL_Msk (0x0fUL << USART1_FIFOTRIG_TXLVL_Pos) /*!< USART1 FIFOTRIG: TXLVL Mask */
-#define USART1_FIFOTRIG_RXLVL_Pos 16 /*!< USART1 FIFOTRIG: RXLVL Position */
-#define USART1_FIFOTRIG_RXLVL_Msk (0x0fUL << USART1_FIFOTRIG_RXLVL_Pos) /*!< USART1 FIFOTRIG: RXLVL Mask */
-
-/* ---------------------------- u1_usart_FIFOINTENSET --------------------------- */
-#define USART1_FIFOINTENSET_TXERR_Pos 0 /*!< USART1 FIFOINTENSET: TXERR Position */
-#define USART1_FIFOINTENSET_TXERR_Msk (0x01UL << USART1_FIFOINTENSET_TXERR_Pos) /*!< USART1 FIFOINTENSET: TXERR Mask */
-#define USART1_FIFOINTENSET_RXERR_Pos 1 /*!< USART1 FIFOINTENSET: RXERR Position */
-#define USART1_FIFOINTENSET_RXERR_Msk (0x01UL << USART1_FIFOINTENSET_RXERR_Pos) /*!< USART1 FIFOINTENSET: RXERR Mask */
-#define USART1_FIFOINTENSET_TXLVL_Pos 2 /*!< USART1 FIFOINTENSET: TXLVL Position */
-#define USART1_FIFOINTENSET_TXLVL_Msk (0x01UL << USART1_FIFOINTENSET_TXLVL_Pos) /*!< USART1 FIFOINTENSET: TXLVL Mask */
-#define USART1_FIFOINTENSET_RXLVL_Pos 3 /*!< USART1 FIFOINTENSET: RXLVL Position */
-#define USART1_FIFOINTENSET_RXLVL_Msk (0x01UL << USART1_FIFOINTENSET_RXLVL_Pos) /*!< USART1 FIFOINTENSET: RXLVL Mask */
-
-/* ---------------------------- u1_usart_FIFOINTENCLR --------------------------- */
-#define USART1_FIFOINTENCLR_TXERR_Pos 0 /*!< USART1 FIFOINTENCLR: TXERR Position */
-#define USART1_FIFOINTENCLR_TXERR_Msk (0x01UL << USART1_FIFOINTENCLR_TXERR_Pos) /*!< USART1 FIFOINTENCLR: TXERR Mask */
-#define USART1_FIFOINTENCLR_RXERR_Pos 1 /*!< USART1 FIFOINTENCLR: RXERR Position */
-#define USART1_FIFOINTENCLR_RXERR_Msk (0x01UL << USART1_FIFOINTENCLR_RXERR_Pos) /*!< USART1 FIFOINTENCLR: RXERR Mask */
-#define USART1_FIFOINTENCLR_TXLVL_Pos 2 /*!< USART1 FIFOINTENCLR: TXLVL Position */
-#define USART1_FIFOINTENCLR_TXLVL_Msk (0x01UL << USART1_FIFOINTENCLR_TXLVL_Pos) /*!< USART1 FIFOINTENCLR: TXLVL Mask */
-#define USART1_FIFOINTENCLR_RXLVL_Pos 3 /*!< USART1 FIFOINTENCLR: RXLVL Position */
-#define USART1_FIFOINTENCLR_RXLVL_Msk (0x01UL << USART1_FIFOINTENCLR_RXLVL_Pos) /*!< USART1 FIFOINTENCLR: RXLVL Mask */
-
-/* ---------------------------- u1_usart_FIFOINTSTAT ---------------------------- */
-#define USART1_FIFOINTSTAT_TXERR_Pos 0 /*!< USART1 FIFOINTSTAT: TXERR Position */
-#define USART1_FIFOINTSTAT_TXERR_Msk (0x01UL << USART1_FIFOINTSTAT_TXERR_Pos) /*!< USART1 FIFOINTSTAT: TXERR Mask */
-#define USART1_FIFOINTSTAT_RXERR_Pos 1 /*!< USART1 FIFOINTSTAT: RXERR Position */
-#define USART1_FIFOINTSTAT_RXERR_Msk (0x01UL << USART1_FIFOINTSTAT_RXERR_Pos) /*!< USART1 FIFOINTSTAT: RXERR Mask */
-#define USART1_FIFOINTSTAT_TXLVL_Pos 2 /*!< USART1 FIFOINTSTAT: TXLVL Position */
-#define USART1_FIFOINTSTAT_TXLVL_Msk (0x01UL << USART1_FIFOINTSTAT_TXLVL_Pos) /*!< USART1 FIFOINTSTAT: TXLVL Mask */
-#define USART1_FIFOINTSTAT_RXLVL_Pos 3 /*!< USART1 FIFOINTSTAT: RXLVL Position */
-#define USART1_FIFOINTSTAT_RXLVL_Msk (0x01UL << USART1_FIFOINTSTAT_RXLVL_Pos) /*!< USART1 FIFOINTSTAT: RXLVL Mask */
-#define USART1_FIFOINTSTAT_PERINT_Pos 4 /*!< USART1 FIFOINTSTAT: PERINT Position */
-#define USART1_FIFOINTSTAT_PERINT_Msk (0x01UL << USART1_FIFOINTSTAT_PERINT_Pos) /*!< USART1 FIFOINTSTAT: PERINT Mask */
-
-/* ------------------------------- u1_usart_FIFOWR ------------------------------ */
-#define USART1_FIFOWR_TXDATA_Pos 0 /*!< USART1 FIFOWR: TXDATA Position */
-#define USART1_FIFOWR_TXDATA_Msk (0x000000ffUL << USART1_FIFOWR_TXDATA_Pos) /*!< USART1 FIFOWR: TXDATA Mask */
-
-/* ------------------------------- u1_usart_FIFORD ------------------------------ */
-#define USART1_FIFORD_RXDATA_Pos 0 /*!< USART1 FIFORD: RXDATA Position */
-#define USART1_FIFORD_RXDATA_Msk (0x000001ffUL << USART1_FIFORD_RXDATA_Pos) /*!< USART1 FIFORD: RXDATA Mask */
-#define USART1_FIFORD_FRAMERR_Pos 13 /*!< USART1 FIFORD: FRAMERR Position */
-#define USART1_FIFORD_FRAMERR_Msk (0x01UL << USART1_FIFORD_FRAMERR_Pos) /*!< USART1 FIFORD: FRAMERR Mask */
-#define USART1_FIFORD_PARITYERR_Pos 14 /*!< USART1 FIFORD: PARITYERR Position */
-#define USART1_FIFORD_PARITYERR_Msk (0x01UL << USART1_FIFORD_PARITYERR_Pos) /*!< USART1 FIFORD: PARITYERR Mask */
-#define USART1_FIFORD_RXNOISE_Pos 15 /*!< USART1 FIFORD: RXNOISE Position */
-#define USART1_FIFORD_RXNOISE_Msk (0x01UL << USART1_FIFORD_RXNOISE_Pos) /*!< USART1 FIFORD: RXNOISE Mask */
-
-/* ---------------------------- u1_usart_FIFORDNOPOP ---------------------------- */
-#define USART1_FIFORDNOPOP_RXDATA_Pos 0 /*!< USART1 FIFORDNOPOP: RXDATA Position */
-#define USART1_FIFORDNOPOP_RXDATA_Msk (0x000001ffUL << USART1_FIFORDNOPOP_RXDATA_Pos) /*!< USART1 FIFORDNOPOP: RXDATA Mask */
-#define USART1_FIFORDNOPOP_FRAMERR_Pos 13 /*!< USART1 FIFORDNOPOP: FRAMERR Position */
-#define USART1_FIFORDNOPOP_FRAMERR_Msk (0x01UL << USART1_FIFORDNOPOP_FRAMERR_Pos) /*!< USART1 FIFORDNOPOP: FRAMERR Mask */
-#define USART1_FIFORDNOPOP_PARITYERR_Pos 14 /*!< USART1 FIFORDNOPOP: PARITYERR Position */
-#define USART1_FIFORDNOPOP_PARITYERR_Msk (0x01UL << USART1_FIFORDNOPOP_PARITYERR_Pos) /*!< USART1 FIFORDNOPOP: PARITYERR Mask */
-#define USART1_FIFORDNOPOP_RXNOISE_Pos 15 /*!< USART1 FIFORDNOPOP: RXNOISE Position */
-#define USART1_FIFORDNOPOP_RXNOISE_Msk (0x01UL << USART1_FIFORDNOPOP_RXNOISE_Pos) /*!< USART1 FIFORDNOPOP: RXNOISE Mask */
-
-/* ------------------------------- u1_usart_PSELID ------------------------------ */
-#define USART1_PSELID_PERSEL_Pos 0 /*!< USART1 PSELID: PERSEL Position */
-#define USART1_PSELID_PERSEL_Msk (0x07UL << USART1_PSELID_PERSEL_Pos) /*!< USART1 PSELID: PERSEL Mask */
-#define USART1_PSELID_LOCK_Pos 3 /*!< USART1 PSELID: LOCK Position */
-#define USART1_PSELID_LOCK_Msk (0x01UL << USART1_PSELID_LOCK_Pos) /*!< USART1 PSELID: LOCK Mask */
-#define USART1_PSELID_USARTPRESENT_Pos 4 /*!< USART1 PSELID: USARTPRESENT Position */
-#define USART1_PSELID_USARTPRESENT_Msk (0x01UL << USART1_PSELID_USARTPRESENT_Pos) /*!< USART1 PSELID: USARTPRESENT Mask */
-#define USART1_PSELID_ID_Pos 12 /*!< USART1 PSELID: ID Position */
-#define USART1_PSELID_ID_Msk (0x000fffffUL << USART1_PSELID_ID_Pos) /*!< USART1 PSELID: ID Mask */
-
-/* --------------------------------- u1_usart_ID -------------------------------- */
-#define USART1_ID_APERTURE_Pos 0 /*!< USART1 ID: APERTURE Position */
-#define USART1_ID_APERTURE_Msk (0x000000ffUL << USART1_ID_APERTURE_Pos) /*!< USART1 ID: APERTURE Mask */
-#define USART1_ID_MIN_REV_Pos 8 /*!< USART1 ID: MIN_REV Position */
-#define USART1_ID_MIN_REV_Msk (0x0fUL << USART1_ID_MIN_REV_Pos) /*!< USART1 ID: MIN_REV Mask */
-#define USART1_ID_MAJ_REV_Pos 12 /*!< USART1 ID: MAJ_REV Position */
-#define USART1_ID_MAJ_REV_Msk (0x0fUL << USART1_ID_MAJ_REV_Pos) /*!< USART1 ID: MAJ_REV Mask */
-#define USART1_ID_ID_Pos 16 /*!< USART1 ID: ID Position */
-#define USART1_ID_ID_Msk (0x0000ffffUL << USART1_ID_ID_Pos) /*!< USART1 ID: ID Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u0_spi' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* --------------------------------- u0_spi_CFG --------------------------------- */
-#define SPI0_CFG_ENABLE_Pos 0 /*!< SPI0 CFG: ENABLE Position */
-#define SPI0_CFG_ENABLE_Msk (0x01UL << SPI0_CFG_ENABLE_Pos) /*!< SPI0 CFG: ENABLE Mask */
-#define SPI0_CFG_MASTER_Pos 2 /*!< SPI0 CFG: MASTER Position */
-#define SPI0_CFG_MASTER_Msk (0x01UL << SPI0_CFG_MASTER_Pos) /*!< SPI0 CFG: MASTER Mask */
-#define SPI0_CFG_LSBF_Pos 3 /*!< SPI0 CFG: LSBF Position */
-#define SPI0_CFG_LSBF_Msk (0x01UL << SPI0_CFG_LSBF_Pos) /*!< SPI0 CFG: LSBF Mask */
-#define SPI0_CFG_CPHA_Pos 4 /*!< SPI0 CFG: CPHA Position */
-#define SPI0_CFG_CPHA_Msk (0x01UL << SPI0_CFG_CPHA_Pos) /*!< SPI0 CFG: CPHA Mask */
-#define SPI0_CFG_CPOL_Pos 5 /*!< SPI0 CFG: CPOL Position */
-#define SPI0_CFG_CPOL_Msk (0x01UL << SPI0_CFG_CPOL_Pos) /*!< SPI0 CFG: CPOL Mask */
-#define SPI0_CFG_LOOP_Pos 7 /*!< SPI0 CFG: LOOP Position */
-#define SPI0_CFG_LOOP_Msk (0x01UL << SPI0_CFG_LOOP_Pos) /*!< SPI0 CFG: LOOP Mask */
-#define SPI0_CFG_SPOL0_Pos 8 /*!< SPI0 CFG: SPOL0 Position */
-#define SPI0_CFG_SPOL0_Msk (0x01UL << SPI0_CFG_SPOL0_Pos) /*!< SPI0 CFG: SPOL0 Mask */
-#define SPI0_CFG_SPOL1_Pos 9 /*!< SPI0 CFG: SPOL1 Position */
-#define SPI0_CFG_SPOL1_Msk (0x01UL << SPI0_CFG_SPOL1_Pos) /*!< SPI0 CFG: SPOL1 Mask */
-#define SPI0_CFG_SPOL2_Pos 10 /*!< SPI0 CFG: SPOL2 Position */
-#define SPI0_CFG_SPOL2_Msk (0x01UL << SPI0_CFG_SPOL2_Pos) /*!< SPI0 CFG: SPOL2 Mask */
-#define SPI0_CFG_SPOL3_Pos 11 /*!< SPI0 CFG: SPOL3 Position */
-#define SPI0_CFG_SPOL3_Msk (0x01UL << SPI0_CFG_SPOL3_Pos) /*!< SPI0 CFG: SPOL3 Mask */
-
-/* --------------------------------- u0_spi_DLY --------------------------------- */
-#define SPI0_DLY_PRE_DELAY_Pos 0 /*!< SPI0 DLY: PRE_DELAY Position */
-#define SPI0_DLY_PRE_DELAY_Msk (0x0fUL << SPI0_DLY_PRE_DELAY_Pos) /*!< SPI0 DLY: PRE_DELAY Mask */
-#define SPI0_DLY_POST_DELAY_Pos 4 /*!< SPI0 DLY: POST_DELAY Position */
-#define SPI0_DLY_POST_DELAY_Msk (0x0fUL << SPI0_DLY_POST_DELAY_Pos) /*!< SPI0 DLY: POST_DELAY Mask */
-#define SPI0_DLY_FRAME_DELAY_Pos 8 /*!< SPI0 DLY: FRAME_DELAY Position */
-#define SPI0_DLY_FRAME_DELAY_Msk (0x0fUL << SPI0_DLY_FRAME_DELAY_Pos) /*!< SPI0 DLY: FRAME_DELAY Mask */
-#define SPI0_DLY_TRANSFER_DELAY_Pos 12 /*!< SPI0 DLY: TRANSFER_DELAY Position */
-#define SPI0_DLY_TRANSFER_DELAY_Msk (0x0fUL << SPI0_DLY_TRANSFER_DELAY_Pos) /*!< SPI0 DLY: TRANSFER_DELAY Mask */
-
-/* --------------------------------- u0_spi_STAT -------------------------------- */
-#define SPI0_STAT_RXOV_Pos 2 /*!< SPI0 STAT: RXOV Position */
-#define SPI0_STAT_RXOV_Msk (0x01UL << SPI0_STAT_RXOV_Pos) /*!< SPI0 STAT: RXOV Mask */
-#define SPI0_STAT_TXUR_Pos 3 /*!< SPI0 STAT: TXUR Position */
-#define SPI0_STAT_TXUR_Msk (0x01UL << SPI0_STAT_TXUR_Pos) /*!< SPI0 STAT: TXUR Mask */
-#define SPI0_STAT_SSA_Pos 4 /*!< SPI0 STAT: SSA Position */
-#define SPI0_STAT_SSA_Msk (0x01UL << SPI0_STAT_SSA_Pos) /*!< SPI0 STAT: SSA Mask */
-#define SPI0_STAT_SSD_Pos 5 /*!< SPI0 STAT: SSD Position */
-#define SPI0_STAT_SSD_Msk (0x01UL << SPI0_STAT_SSD_Pos) /*!< SPI0 STAT: SSD Mask */
-#define SPI0_STAT_STALLED_Pos 6 /*!< SPI0 STAT: STALLED Position */
-#define SPI0_STAT_STALLED_Msk (0x01UL << SPI0_STAT_STALLED_Pos) /*!< SPI0 STAT: STALLED Mask */
-#define SPI0_STAT_ENDTRANSFER_Pos 7 /*!< SPI0 STAT: ENDTRANSFER Position */
-#define SPI0_STAT_ENDTRANSFER_Msk (0x01UL << SPI0_STAT_ENDTRANSFER_Pos) /*!< SPI0 STAT: ENDTRANSFER Mask */
-#define SPI0_STAT_MSTIDLE_Pos 8 /*!< SPI0 STAT: MSTIDLE Position */
-#define SPI0_STAT_MSTIDLE_Msk (0x01UL << SPI0_STAT_MSTIDLE_Pos) /*!< SPI0 STAT: MSTIDLE Mask */
-
-/* ------------------------------- u0_spi_INTENSET ------------------------------ */
-#define SPI0_INTENSET_RXOVEN_Pos 2 /*!< SPI0 INTENSET: RXOVEN Position */
-#define SPI0_INTENSET_RXOVEN_Msk (0x01UL << SPI0_INTENSET_RXOVEN_Pos) /*!< SPI0 INTENSET: RXOVEN Mask */
-#define SPI0_INTENSET_TXUREN_Pos 3 /*!< SPI0 INTENSET: TXUREN Position */
-#define SPI0_INTENSET_TXUREN_Msk (0x01UL << SPI0_INTENSET_TXUREN_Pos) /*!< SPI0 INTENSET: TXUREN Mask */
-#define SPI0_INTENSET_SSAEN_Pos 4 /*!< SPI0 INTENSET: SSAEN Position */
-#define SPI0_INTENSET_SSAEN_Msk (0x01UL << SPI0_INTENSET_SSAEN_Pos) /*!< SPI0 INTENSET: SSAEN Mask */
-#define SPI0_INTENSET_SSDEN_Pos 5 /*!< SPI0 INTENSET: SSDEN Position */
-#define SPI0_INTENSET_SSDEN_Msk (0x01UL << SPI0_INTENSET_SSDEN_Pos) /*!< SPI0 INTENSET: SSDEN Mask */
-#define SPI0_INTENSET_MSTIDLEEN_Pos 8 /*!< SPI0 INTENSET: MSTIDLEEN Position */
-#define SPI0_INTENSET_MSTIDLEEN_Msk (0x01UL << SPI0_INTENSET_MSTIDLEEN_Pos) /*!< SPI0 INTENSET: MSTIDLEEN Mask */
-
-/* ------------------------------- u0_spi_INTENCLR ------------------------------ */
-#define SPI0_INTENCLR_RXOVCLR_Pos 2 /*!< SPI0 INTENCLR: RXOVCLR Position */
-#define SPI0_INTENCLR_RXOVCLR_Msk (0x01UL << SPI0_INTENCLR_RXOVCLR_Pos) /*!< SPI0 INTENCLR: RXOVCLR Mask */
-#define SPI0_INTENCLR_TXURCLR_Pos 3 /*!< SPI0 INTENCLR: TXURCLR Position */
-#define SPI0_INTENCLR_TXURCLR_Msk (0x01UL << SPI0_INTENCLR_TXURCLR_Pos) /*!< SPI0 INTENCLR: TXURCLR Mask */
-#define SPI0_INTENCLR_SSACLR_Pos 4 /*!< SPI0 INTENCLR: SSACLR Position */
-#define SPI0_INTENCLR_SSACLR_Msk (0x01UL << SPI0_INTENCLR_SSACLR_Pos) /*!< SPI0 INTENCLR: SSACLR Mask */
-#define SPI0_INTENCLR_SSDCLR_Pos 5 /*!< SPI0 INTENCLR: SSDCLR Position */
-#define SPI0_INTENCLR_SSDCLR_Msk (0x01UL << SPI0_INTENCLR_SSDCLR_Pos) /*!< SPI0 INTENCLR: SSDCLR Mask */
-#define SPI0_INTENCLR_MSTIDLECLR_Pos 8 /*!< SPI0 INTENCLR: MSTIDLECLR Position */
-#define SPI0_INTENCLR_MSTIDLECLR_Msk (0x01UL << SPI0_INTENCLR_MSTIDLECLR_Pos) /*!< SPI0 INTENCLR: MSTIDLECLR Mask */
-
-/* -------------------------------- u0_spi_TXCTL -------------------------------- */
-#define SPI0_TXCTL_TXSSEL0_N_Pos 16 /*!< SPI0 TXCTL: TXSSEL0_N Position */
-#define SPI0_TXCTL_TXSSEL0_N_Msk (0x01UL << SPI0_TXCTL_TXSSEL0_N_Pos) /*!< SPI0 TXCTL: TXSSEL0_N Mask */
-#define SPI0_TXCTL_TXSSEL1_N_Pos 17 /*!< SPI0 TXCTL: TXSSEL1_N Position */
-#define SPI0_TXCTL_TXSSEL1_N_Msk (0x01UL << SPI0_TXCTL_TXSSEL1_N_Pos) /*!< SPI0 TXCTL: TXSSEL1_N Mask */
-#define SPI0_TXCTL_TXSSEL2_N_Pos 18 /*!< SPI0 TXCTL: TXSSEL2_N Position */
-#define SPI0_TXCTL_TXSSEL2_N_Msk (0x01UL << SPI0_TXCTL_TXSSEL2_N_Pos) /*!< SPI0 TXCTL: TXSSEL2_N Mask */
-#define SPI0_TXCTL_TXSSEL3_N_Pos 19 /*!< SPI0 TXCTL: TXSSEL3_N Position */
-#define SPI0_TXCTL_TXSSEL3_N_Msk (0x01UL << SPI0_TXCTL_TXSSEL3_N_Pos) /*!< SPI0 TXCTL: TXSSEL3_N Mask */
-#define SPI0_TXCTL_EOTR_Pos 20 /*!< SPI0 TXCTL: EOTR Position */
-#define SPI0_TXCTL_EOTR_Msk (0x01UL << SPI0_TXCTL_EOTR_Pos) /*!< SPI0 TXCTL: EOTR Mask */
-#define SPI0_TXCTL_EOFR_Pos 21 /*!< SPI0 TXCTL: EOFR Position */
-#define SPI0_TXCTL_EOFR_Msk (0x01UL << SPI0_TXCTL_EOFR_Pos) /*!< SPI0 TXCTL: EOFR Mask */
-#define SPI0_TXCTL_RXIGNORE_Pos 22 /*!< SPI0 TXCTL: RXIGNORE Position */
-#define SPI0_TXCTL_RXIGNORE_Msk (0x01UL << SPI0_TXCTL_RXIGNORE_Pos) /*!< SPI0 TXCTL: RXIGNORE Mask */
-#define SPI0_TXCTL_LEN_Pos 24 /*!< SPI0 TXCTL: LEN Position */
-#define SPI0_TXCTL_LEN_Msk (0x0fUL << SPI0_TXCTL_LEN_Pos) /*!< SPI0 TXCTL: LEN Mask */
-
-/* --------------------------------- u0_spi_DIV --------------------------------- */
-#define SPI0_DIV_DIVVAL_Pos 0 /*!< SPI0 DIV: DIVVAL Position */
-#define SPI0_DIV_DIVVAL_Msk (0x0000ffffUL << SPI0_DIV_DIVVAL_Pos) /*!< SPI0 DIV: DIVVAL Mask */
-
-/* ------------------------------- u0_spi_INTSTAT ------------------------------- */
-#define SPI0_INTSTAT_RXOV_Pos 2 /*!< SPI0 INTSTAT: RXOV Position */
-#define SPI0_INTSTAT_RXOV_Msk (0x01UL << SPI0_INTSTAT_RXOV_Pos) /*!< SPI0 INTSTAT: RXOV Mask */
-#define SPI0_INTSTAT_TXUR_Pos 3 /*!< SPI0 INTSTAT: TXUR Position */
-#define SPI0_INTSTAT_TXUR_Msk (0x01UL << SPI0_INTSTAT_TXUR_Pos) /*!< SPI0 INTSTAT: TXUR Mask */
-#define SPI0_INTSTAT_SSA_Pos 4 /*!< SPI0 INTSTAT: SSA Position */
-#define SPI0_INTSTAT_SSA_Msk (0x01UL << SPI0_INTSTAT_SSA_Pos) /*!< SPI0 INTSTAT: SSA Mask */
-#define SPI0_INTSTAT_SSD_Pos 5 /*!< SPI0 INTSTAT: SSD Position */
-#define SPI0_INTSTAT_SSD_Msk (0x01UL << SPI0_INTSTAT_SSD_Pos) /*!< SPI0 INTSTAT: SSD Mask */
-#define SPI0_INTSTAT_MSTIDLE_Pos 8 /*!< SPI0 INTSTAT: MSTIDLE Position */
-#define SPI0_INTSTAT_MSTIDLE_Msk (0x01UL << SPI0_INTSTAT_MSTIDLE_Pos) /*!< SPI0 INTSTAT: MSTIDLE Mask */
-
-/* ------------------------------- u0_spi_FIFOCFG ------------------------------- */
-#define SPI0_FIFOCFG_ENABLETX_Pos 0 /*!< SPI0 FIFOCFG: ENABLETX Position */
-#define SPI0_FIFOCFG_ENABLETX_Msk (0x01UL << SPI0_FIFOCFG_ENABLETX_Pos) /*!< SPI0 FIFOCFG: ENABLETX Mask */
-#define SPI0_FIFOCFG_ENABLERX_Pos 1 /*!< SPI0 FIFOCFG: ENABLERX Position */
-#define SPI0_FIFOCFG_ENABLERX_Msk (0x01UL << SPI0_FIFOCFG_ENABLERX_Pos) /*!< SPI0 FIFOCFG: ENABLERX Mask */
-#define SPI0_FIFOCFG_SIZE_Pos 4 /*!< SPI0 FIFOCFG: SIZE Position */
-#define SPI0_FIFOCFG_SIZE_Msk (0x03UL << SPI0_FIFOCFG_SIZE_Pos) /*!< SPI0 FIFOCFG: SIZE Mask */
-#define SPI0_FIFOCFG_DMATX_Pos 12 /*!< SPI0 FIFOCFG: DMATX Position */
-#define SPI0_FIFOCFG_DMATX_Msk (0x01UL << SPI0_FIFOCFG_DMATX_Pos) /*!< SPI0 FIFOCFG: DMATX Mask */
-#define SPI0_FIFOCFG_DMARX_Pos 13 /*!< SPI0 FIFOCFG: DMARX Position */
-#define SPI0_FIFOCFG_DMARX_Msk (0x01UL << SPI0_FIFOCFG_DMARX_Pos) /*!< SPI0 FIFOCFG: DMARX Mask */
-#define SPI0_FIFOCFG_WAKETX_Pos 14 /*!< SPI0 FIFOCFG: WAKETX Position */
-#define SPI0_FIFOCFG_WAKETX_Msk (0x01UL << SPI0_FIFOCFG_WAKETX_Pos) /*!< SPI0 FIFOCFG: WAKETX Mask */
-#define SPI0_FIFOCFG_WAKERX_Pos 15 /*!< SPI0 FIFOCFG: WAKERX Position */
-#define SPI0_FIFOCFG_WAKERX_Msk (0x01UL << SPI0_FIFOCFG_WAKERX_Pos) /*!< SPI0 FIFOCFG: WAKERX Mask */
-#define SPI0_FIFOCFG_EMPTYTX_Pos 16 /*!< SPI0 FIFOCFG: EMPTYTX Position */
-#define SPI0_FIFOCFG_EMPTYTX_Msk (0x01UL << SPI0_FIFOCFG_EMPTYTX_Pos) /*!< SPI0 FIFOCFG: EMPTYTX Mask */
-#define SPI0_FIFOCFG_EMPTYRX_Pos 17 /*!< SPI0 FIFOCFG: EMPTYRX Position */
-#define SPI0_FIFOCFG_EMPTYRX_Msk (0x01UL << SPI0_FIFOCFG_EMPTYRX_Pos) /*!< SPI0 FIFOCFG: EMPTYRX Mask */
-#define SPI0_FIFOCFG_POPDBG_Pos 18 /*!< SPI0 FIFOCFG: POPDBG Position */
-#define SPI0_FIFOCFG_POPDBG_Msk (0x01UL << SPI0_FIFOCFG_POPDBG_Pos) /*!< SPI0 FIFOCFG: POPDBG Mask */
-
-/* ------------------------------- u0_spi_FIFOSTAT ------------------------------ */
-#define SPI0_FIFOSTAT_TXERR_Pos 0 /*!< SPI0 FIFOSTAT: TXERR Position */
-#define SPI0_FIFOSTAT_TXERR_Msk (0x01UL << SPI0_FIFOSTAT_TXERR_Pos) /*!< SPI0 FIFOSTAT: TXERR Mask */
-#define SPI0_FIFOSTAT_RXERR_Pos 1 /*!< SPI0 FIFOSTAT: RXERR Position */
-#define SPI0_FIFOSTAT_RXERR_Msk (0x01UL << SPI0_FIFOSTAT_RXERR_Pos) /*!< SPI0 FIFOSTAT: RXERR Mask */
-#define SPI0_FIFOSTAT_PERINT_Pos 3 /*!< SPI0 FIFOSTAT: PERINT Position */
-#define SPI0_FIFOSTAT_PERINT_Msk (0x01UL << SPI0_FIFOSTAT_PERINT_Pos) /*!< SPI0 FIFOSTAT: PERINT Mask */
-#define SPI0_FIFOSTAT_TXEMPTY_Pos 4 /*!< SPI0 FIFOSTAT: TXEMPTY Position */
-#define SPI0_FIFOSTAT_TXEMPTY_Msk (0x01UL << SPI0_FIFOSTAT_TXEMPTY_Pos) /*!< SPI0 FIFOSTAT: TXEMPTY Mask */
-#define SPI0_FIFOSTAT_TXNOTFULL_Pos 5 /*!< SPI0 FIFOSTAT: TXNOTFULL Position */
-#define SPI0_FIFOSTAT_TXNOTFULL_Msk (0x01UL << SPI0_FIFOSTAT_TXNOTFULL_Pos) /*!< SPI0 FIFOSTAT: TXNOTFULL Mask */
-#define SPI0_FIFOSTAT_RXNOTEMPTY_Pos 6 /*!< SPI0 FIFOSTAT: RXNOTEMPTY Position */
-#define SPI0_FIFOSTAT_RXNOTEMPTY_Msk (0x01UL << SPI0_FIFOSTAT_RXNOTEMPTY_Pos) /*!< SPI0 FIFOSTAT: RXNOTEMPTY Mask */
-#define SPI0_FIFOSTAT_RXFULL_Pos 7 /*!< SPI0 FIFOSTAT: RXFULL Position */
-#define SPI0_FIFOSTAT_RXFULL_Msk (0x01UL << SPI0_FIFOSTAT_RXFULL_Pos) /*!< SPI0 FIFOSTAT: RXFULL Mask */
-#define SPI0_FIFOSTAT_TXLVL_Pos 8 /*!< SPI0 FIFOSTAT: TXLVL Position */
-#define SPI0_FIFOSTAT_TXLVL_Msk (0x1fUL << SPI0_FIFOSTAT_TXLVL_Pos) /*!< SPI0 FIFOSTAT: TXLVL Mask */
-#define SPI0_FIFOSTAT_RXLVL_Pos 16 /*!< SPI0 FIFOSTAT: RXLVL Position */
-#define SPI0_FIFOSTAT_RXLVL_Msk (0x1fUL << SPI0_FIFOSTAT_RXLVL_Pos) /*!< SPI0 FIFOSTAT: RXLVL Mask */
-
-/* ------------------------------- u0_spi_FIFOTRIG ------------------------------ */
-#define SPI0_FIFOTRIG_TXLVLENA_Pos 0 /*!< SPI0 FIFOTRIG: TXLVLENA Position */
-#define SPI0_FIFOTRIG_TXLVLENA_Msk (0x01UL << SPI0_FIFOTRIG_TXLVLENA_Pos) /*!< SPI0 FIFOTRIG: TXLVLENA Mask */
-#define SPI0_FIFOTRIG_RXLVLENA_Pos 1 /*!< SPI0 FIFOTRIG: RXLVLENA Position */
-#define SPI0_FIFOTRIG_RXLVLENA_Msk (0x01UL << SPI0_FIFOTRIG_RXLVLENA_Pos) /*!< SPI0 FIFOTRIG: RXLVLENA Mask */
-#define SPI0_FIFOTRIG_TXLVL_Pos 8 /*!< SPI0 FIFOTRIG: TXLVL Position */
-#define SPI0_FIFOTRIG_TXLVL_Msk (0x0fUL << SPI0_FIFOTRIG_TXLVL_Pos) /*!< SPI0 FIFOTRIG: TXLVL Mask */
-#define SPI0_FIFOTRIG_RXLVL_Pos 16 /*!< SPI0 FIFOTRIG: RXLVL Position */
-#define SPI0_FIFOTRIG_RXLVL_Msk (0x0fUL << SPI0_FIFOTRIG_RXLVL_Pos) /*!< SPI0 FIFOTRIG: RXLVL Mask */
-
-/* ----------------------------- u0_spi_FIFOINTENSET ---------------------------- */
-#define SPI0_FIFOINTENSET_TXERR_Pos 0 /*!< SPI0 FIFOINTENSET: TXERR Position */
-#define SPI0_FIFOINTENSET_TXERR_Msk (0x01UL << SPI0_FIFOINTENSET_TXERR_Pos) /*!< SPI0 FIFOINTENSET: TXERR Mask */
-#define SPI0_FIFOINTENSET_RXERR_Pos 1 /*!< SPI0 FIFOINTENSET: RXERR Position */
-#define SPI0_FIFOINTENSET_RXERR_Msk (0x01UL << SPI0_FIFOINTENSET_RXERR_Pos) /*!< SPI0 FIFOINTENSET: RXERR Mask */
-#define SPI0_FIFOINTENSET_TXLVL_Pos 2 /*!< SPI0 FIFOINTENSET: TXLVL Position */
-#define SPI0_FIFOINTENSET_TXLVL_Msk (0x01UL << SPI0_FIFOINTENSET_TXLVL_Pos) /*!< SPI0 FIFOINTENSET: TXLVL Mask */
-#define SPI0_FIFOINTENSET_RXLVL_Pos 3 /*!< SPI0 FIFOINTENSET: RXLVL Position */
-#define SPI0_FIFOINTENSET_RXLVL_Msk (0x01UL << SPI0_FIFOINTENSET_RXLVL_Pos) /*!< SPI0 FIFOINTENSET: RXLVL Mask */
-
-/* ----------------------------- u0_spi_FIFOINTENCLR ---------------------------- */
-#define SPI0_FIFOINTENCLR_TXERR_Pos 0 /*!< SPI0 FIFOINTENCLR: TXERR Position */
-#define SPI0_FIFOINTENCLR_TXERR_Msk (0x01UL << SPI0_FIFOINTENCLR_TXERR_Pos) /*!< SPI0 FIFOINTENCLR: TXERR Mask */
-#define SPI0_FIFOINTENCLR_RXERR_Pos 1 /*!< SPI0 FIFOINTENCLR: RXERR Position */
-#define SPI0_FIFOINTENCLR_RXERR_Msk (0x01UL << SPI0_FIFOINTENCLR_RXERR_Pos) /*!< SPI0 FIFOINTENCLR: RXERR Mask */
-#define SPI0_FIFOINTENCLR_TXLVL_Pos 2 /*!< SPI0 FIFOINTENCLR: TXLVL Position */
-#define SPI0_FIFOINTENCLR_TXLVL_Msk (0x01UL << SPI0_FIFOINTENCLR_TXLVL_Pos) /*!< SPI0 FIFOINTENCLR: TXLVL Mask */
-#define SPI0_FIFOINTENCLR_RXLVL_Pos 3 /*!< SPI0 FIFOINTENCLR: RXLVL Position */
-#define SPI0_FIFOINTENCLR_RXLVL_Msk (0x01UL << SPI0_FIFOINTENCLR_RXLVL_Pos) /*!< SPI0 FIFOINTENCLR: RXLVL Mask */
-
-/* ----------------------------- u0_spi_FIFOINTSTAT ----------------------------- */
-#define SPI0_FIFOINTSTAT_TXERR_Pos 0 /*!< SPI0 FIFOINTSTAT: TXERR Position */
-#define SPI0_FIFOINTSTAT_TXERR_Msk (0x01UL << SPI0_FIFOINTSTAT_TXERR_Pos) /*!< SPI0 FIFOINTSTAT: TXERR Mask */
-#define SPI0_FIFOINTSTAT_RXERR_Pos 1 /*!< SPI0 FIFOINTSTAT: RXERR Position */
-#define SPI0_FIFOINTSTAT_RXERR_Msk (0x01UL << SPI0_FIFOINTSTAT_RXERR_Pos) /*!< SPI0 FIFOINTSTAT: RXERR Mask */
-#define SPI0_FIFOINTSTAT_TXLVL_Pos 2 /*!< SPI0 FIFOINTSTAT: TXLVL Position */
-#define SPI0_FIFOINTSTAT_TXLVL_Msk (0x01UL << SPI0_FIFOINTSTAT_TXLVL_Pos) /*!< SPI0 FIFOINTSTAT: TXLVL Mask */
-#define SPI0_FIFOINTSTAT_RXLVL_Pos 3 /*!< SPI0 FIFOINTSTAT: RXLVL Position */
-#define SPI0_FIFOINTSTAT_RXLVL_Msk (0x01UL << SPI0_FIFOINTSTAT_RXLVL_Pos) /*!< SPI0 FIFOINTSTAT: RXLVL Mask */
-#define SPI0_FIFOINTSTAT_PERINT_Pos 4 /*!< SPI0 FIFOINTSTAT: PERINT Position */
-#define SPI0_FIFOINTSTAT_PERINT_Msk (0x01UL << SPI0_FIFOINTSTAT_PERINT_Pos) /*!< SPI0 FIFOINTSTAT: PERINT Mask */
-
-/* -------------------------------- u0_spi_FIFOWR ------------------------------- */
-#define SPI0_FIFOWR_TXDATA_Pos 0 /*!< SPI0 FIFOWR: TXDATA Position */
-#define SPI0_FIFOWR_TXDATA_Msk (0x0000ffffUL << SPI0_FIFOWR_TXDATA_Pos) /*!< SPI0 FIFOWR: TXDATA Mask */
-#define SPI0_FIFOWR_TXSSEL0_N_Pos 16 /*!< SPI0 FIFOWR: TXSSEL0_N Position */
-#define SPI0_FIFOWR_TXSSEL0_N_Msk (0x01UL << SPI0_FIFOWR_TXSSEL0_N_Pos) /*!< SPI0 FIFOWR: TXSSEL0_N Mask */
-#define SPI0_FIFOWR_TXSSEL1_N_Pos 17 /*!< SPI0 FIFOWR: TXSSEL1_N Position */
-#define SPI0_FIFOWR_TXSSEL1_N_Msk (0x01UL << SPI0_FIFOWR_TXSSEL1_N_Pos) /*!< SPI0 FIFOWR: TXSSEL1_N Mask */
-#define SPI0_FIFOWR_TXSSEL2_N_Pos 18 /*!< SPI0 FIFOWR: TXSSEL2_N Position */
-#define SPI0_FIFOWR_TXSSEL2_N_Msk (0x01UL << SPI0_FIFOWR_TXSSEL2_N_Pos) /*!< SPI0 FIFOWR: TXSSEL2_N Mask */
-#define SPI0_FIFOWR_TXSSEL3_N_Pos 19 /*!< SPI0 FIFOWR: TXSSEL3_N Position */
-#define SPI0_FIFOWR_TXSSEL3_N_Msk (0x01UL << SPI0_FIFOWR_TXSSEL3_N_Pos) /*!< SPI0 FIFOWR: TXSSEL3_N Mask */
-#define SPI0_FIFOWR_EOTR_Pos 20 /*!< SPI0 FIFOWR: EOTR Position */
-#define SPI0_FIFOWR_EOTR_Msk (0x01UL << SPI0_FIFOWR_EOTR_Pos) /*!< SPI0 FIFOWR: EOTR Mask */
-#define SPI0_FIFOWR_EOFR_Pos 21 /*!< SPI0 FIFOWR: EOFR Position */
-#define SPI0_FIFOWR_EOFR_Msk (0x01UL << SPI0_FIFOWR_EOFR_Pos) /*!< SPI0 FIFOWR: EOFR Mask */
-#define SPI0_FIFOWR_RXIGNORE_Pos 22 /*!< SPI0 FIFOWR: RXIGNORE Position */
-#define SPI0_FIFOWR_RXIGNORE_Msk (0x01UL << SPI0_FIFOWR_RXIGNORE_Pos) /*!< SPI0 FIFOWR: RXIGNORE Mask */
-#define SPI0_FIFOWR_LEN_Pos 24 /*!< SPI0 FIFOWR: LEN Position */
-#define SPI0_FIFOWR_LEN_Msk (0x0fUL << SPI0_FIFOWR_LEN_Pos) /*!< SPI0 FIFOWR: LEN Mask */
-
-/* -------------------------------- u0_spi_FIFORD ------------------------------- */
-#define SPI0_FIFORD_RXDATA_Pos 0 /*!< SPI0 FIFORD: RXDATA Position */
-#define SPI0_FIFORD_RXDATA_Msk (0x0000ffffUL << SPI0_FIFORD_RXDATA_Pos) /*!< SPI0 FIFORD: RXDATA Mask */
-#define SPI0_FIFORD_RXSSEL0_N_Pos 16 /*!< SPI0 FIFORD: RXSSEL0_N Position */
-#define SPI0_FIFORD_RXSSEL0_N_Msk (0x01UL << SPI0_FIFORD_RXSSEL0_N_Pos) /*!< SPI0 FIFORD: RXSSEL0_N Mask */
-#define SPI0_FIFORD_RXSSEL1_N_Pos 17 /*!< SPI0 FIFORD: RXSSEL1_N Position */
-#define SPI0_FIFORD_RXSSEL1_N_Msk (0x01UL << SPI0_FIFORD_RXSSEL1_N_Pos) /*!< SPI0 FIFORD: RXSSEL1_N Mask */
-#define SPI0_FIFORD_RXSSEL2_N_Pos 18 /*!< SPI0 FIFORD: RXSSEL2_N Position */
-#define SPI0_FIFORD_RXSSEL2_N_Msk (0x01UL << SPI0_FIFORD_RXSSEL2_N_Pos) /*!< SPI0 FIFORD: RXSSEL2_N Mask */
-#define SPI0_FIFORD_RXSSEL3_N_Pos 19 /*!< SPI0 FIFORD: RXSSEL3_N Position */
-#define SPI0_FIFORD_RXSSEL3_N_Msk (0x01UL << SPI0_FIFORD_RXSSEL3_N_Pos) /*!< SPI0 FIFORD: RXSSEL3_N Mask */
-#define SPI0_FIFORD_SOT_Pos 20 /*!< SPI0 FIFORD: SOT Position */
-#define SPI0_FIFORD_SOT_Msk (0x01UL << SPI0_FIFORD_SOT_Pos) /*!< SPI0 FIFORD: SOT Mask */
-
-/* ----------------------------- u0_spi_FIFORDNOPOP ----------------------------- */
-#define SPI0_FIFORDNOPOP_RXDATA_Pos 0 /*!< SPI0 FIFORDNOPOP: RXDATA Position */
-#define SPI0_FIFORDNOPOP_RXDATA_Msk (0x0000ffffUL << SPI0_FIFORDNOPOP_RXDATA_Pos) /*!< SPI0 FIFORDNOPOP: RXDATA Mask */
-#define SPI0_FIFORDNOPOP_RXSSEL0_N_Pos 16 /*!< SPI0 FIFORDNOPOP: RXSSEL0_N Position */
-#define SPI0_FIFORDNOPOP_RXSSEL0_N_Msk (0x01UL << SPI0_FIFORDNOPOP_RXSSEL0_N_Pos) /*!< SPI0 FIFORDNOPOP: RXSSEL0_N Mask */
-#define SPI0_FIFORDNOPOP_RXSSEL1_N_Pos 17 /*!< SPI0 FIFORDNOPOP: RXSSEL1_N Position */
-#define SPI0_FIFORDNOPOP_RXSSEL1_N_Msk (0x01UL << SPI0_FIFORDNOPOP_RXSSEL1_N_Pos) /*!< SPI0 FIFORDNOPOP: RXSSEL1_N Mask */
-#define SPI0_FIFORDNOPOP_RXSSEL2_N_Pos 18 /*!< SPI0 FIFORDNOPOP: RXSSEL2_N Position */
-#define SPI0_FIFORDNOPOP_RXSSEL2_N_Msk (0x01UL << SPI0_FIFORDNOPOP_RXSSEL2_N_Pos) /*!< SPI0 FIFORDNOPOP: RXSSEL2_N Mask */
-#define SPI0_FIFORDNOPOP_RXSSEL3_N_Pos 19 /*!< SPI0 FIFORDNOPOP: RXSSEL3_N Position */
-#define SPI0_FIFORDNOPOP_RXSSEL3_N_Msk (0x01UL << SPI0_FIFORDNOPOP_RXSSEL3_N_Pos) /*!< SPI0 FIFORDNOPOP: RXSSEL3_N Mask */
-#define SPI0_FIFORDNOPOP_SOT_Pos 20 /*!< SPI0 FIFORDNOPOP: SOT Position */
-#define SPI0_FIFORDNOPOP_SOT_Msk (0x01UL << SPI0_FIFORDNOPOP_SOT_Pos) /*!< SPI0 FIFORDNOPOP: SOT Mask */
-
-/* -------------------------------- u0_spi_PSELID ------------------------------- */
-#define SPI0_PSELID_PERSEL_Pos 0 /*!< SPI0 PSELID: PERSEL Position */
-#define SPI0_PSELID_PERSEL_Msk (0x07UL << SPI0_PSELID_PERSEL_Pos) /*!< SPI0 PSELID: PERSEL Mask */
-#define SPI0_PSELID_LOCK_Pos 3 /*!< SPI0 PSELID: LOCK Position */
-#define SPI0_PSELID_LOCK_Msk (0x01UL << SPI0_PSELID_LOCK_Pos) /*!< SPI0 PSELID: LOCK Mask */
-#define SPI0_PSELID_SPIPRESENT_Pos 5 /*!< SPI0 PSELID: SPIPRESENT Position */
-#define SPI0_PSELID_SPIPRESENT_Msk (0x01UL << SPI0_PSELID_SPIPRESENT_Pos) /*!< SPI0 PSELID: SPIPRESENT Mask */
-#define SPI0_PSELID_ID_Pos 12 /*!< SPI0 PSELID: ID Position */
-#define SPI0_PSELID_ID_Msk (0x000fffffUL << SPI0_PSELID_ID_Pos) /*!< SPI0 PSELID: ID Mask */
-
-/* ---------------------------------- u0_spi_ID --------------------------------- */
-#define SPI0_ID_APERTURE_Pos 0 /*!< SPI0 ID: APERTURE Position */
-#define SPI0_ID_APERTURE_Msk (0x000000ffUL << SPI0_ID_APERTURE_Pos) /*!< SPI0 ID: APERTURE Mask */
-#define SPI0_ID_MIN_REV_Pos 8 /*!< SPI0 ID: MIN_REV Position */
-#define SPI0_ID_MIN_REV_Msk (0x0fUL << SPI0_ID_MIN_REV_Pos) /*!< SPI0 ID: MIN_REV Mask */
-#define SPI0_ID_MAJ_REV_Pos 12 /*!< SPI0 ID: MAJ_REV Position */
-#define SPI0_ID_MAJ_REV_Msk (0x0fUL << SPI0_ID_MAJ_REV_Pos) /*!< SPI0 ID: MAJ_REV Mask */
-#define SPI0_ID_ID_Pos 16 /*!< SPI0 ID: ID Position */
-#define SPI0_ID_ID_Msk (0x0000ffffUL << SPI0_ID_ID_Pos) /*!< SPI0 ID: ID Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u1_spi' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* --------------------------------- u1_spi_CFG --------------------------------- */
-#define SPI1_CFG_ENABLE_Pos 0 /*!< SPI1 CFG: ENABLE Position */
-#define SPI1_CFG_ENABLE_Msk (0x01UL << SPI1_CFG_ENABLE_Pos) /*!< SPI1 CFG: ENABLE Mask */
-#define SPI1_CFG_MASTER_Pos 2 /*!< SPI1 CFG: MASTER Position */
-#define SPI1_CFG_MASTER_Msk (0x01UL << SPI1_CFG_MASTER_Pos) /*!< SPI1 CFG: MASTER Mask */
-#define SPI1_CFG_LSBF_Pos 3 /*!< SPI1 CFG: LSBF Position */
-#define SPI1_CFG_LSBF_Msk (0x01UL << SPI1_CFG_LSBF_Pos) /*!< SPI1 CFG: LSBF Mask */
-#define SPI1_CFG_CPHA_Pos 4 /*!< SPI1 CFG: CPHA Position */
-#define SPI1_CFG_CPHA_Msk (0x01UL << SPI1_CFG_CPHA_Pos) /*!< SPI1 CFG: CPHA Mask */
-#define SPI1_CFG_CPOL_Pos 5 /*!< SPI1 CFG: CPOL Position */
-#define SPI1_CFG_CPOL_Msk (0x01UL << SPI1_CFG_CPOL_Pos) /*!< SPI1 CFG: CPOL Mask */
-#define SPI1_CFG_LOOP_Pos 7 /*!< SPI1 CFG: LOOP Position */
-#define SPI1_CFG_LOOP_Msk (0x01UL << SPI1_CFG_LOOP_Pos) /*!< SPI1 CFG: LOOP Mask */
-#define SPI1_CFG_SPOL0_Pos 8 /*!< SPI1 CFG: SPOL0 Position */
-#define SPI1_CFG_SPOL0_Msk (0x01UL << SPI1_CFG_SPOL0_Pos) /*!< SPI1 CFG: SPOL0 Mask */
-#define SPI1_CFG_SPOL1_Pos 9 /*!< SPI1 CFG: SPOL1 Position */
-#define SPI1_CFG_SPOL1_Msk (0x01UL << SPI1_CFG_SPOL1_Pos) /*!< SPI1 CFG: SPOL1 Mask */
-#define SPI1_CFG_SPOL2_Pos 10 /*!< SPI1 CFG: SPOL2 Position */
-#define SPI1_CFG_SPOL2_Msk (0x01UL << SPI1_CFG_SPOL2_Pos) /*!< SPI1 CFG: SPOL2 Mask */
-#define SPI1_CFG_SPOL3_Pos 11 /*!< SPI1 CFG: SPOL3 Position */
-#define SPI1_CFG_SPOL3_Msk (0x01UL << SPI1_CFG_SPOL3_Pos) /*!< SPI1 CFG: SPOL3 Mask */
-
-/* --------------------------------- u1_spi_DLY --------------------------------- */
-#define SPI1_DLY_PRE_DELAY_Pos 0 /*!< SPI1 DLY: PRE_DELAY Position */
-#define SPI1_DLY_PRE_DELAY_Msk (0x0fUL << SPI1_DLY_PRE_DELAY_Pos) /*!< SPI1 DLY: PRE_DELAY Mask */
-#define SPI1_DLY_POST_DELAY_Pos 4 /*!< SPI1 DLY: POST_DELAY Position */
-#define SPI1_DLY_POST_DELAY_Msk (0x0fUL << SPI1_DLY_POST_DELAY_Pos) /*!< SPI1 DLY: POST_DELAY Mask */
-#define SPI1_DLY_FRAME_DELAY_Pos 8 /*!< SPI1 DLY: FRAME_DELAY Position */
-#define SPI1_DLY_FRAME_DELAY_Msk (0x0fUL << SPI1_DLY_FRAME_DELAY_Pos) /*!< SPI1 DLY: FRAME_DELAY Mask */
-#define SPI1_DLY_TRANSFER_DELAY_Pos 12 /*!< SPI1 DLY: TRANSFER_DELAY Position */
-#define SPI1_DLY_TRANSFER_DELAY_Msk (0x0fUL << SPI1_DLY_TRANSFER_DELAY_Pos) /*!< SPI1 DLY: TRANSFER_DELAY Mask */
-
-/* --------------------------------- u1_spi_STAT -------------------------------- */
-#define SPI1_STAT_RXOV_Pos 2 /*!< SPI1 STAT: RXOV Position */
-#define SPI1_STAT_RXOV_Msk (0x01UL << SPI1_STAT_RXOV_Pos) /*!< SPI1 STAT: RXOV Mask */
-#define SPI1_STAT_TXUR_Pos 3 /*!< SPI1 STAT: TXUR Position */
-#define SPI1_STAT_TXUR_Msk (0x01UL << SPI1_STAT_TXUR_Pos) /*!< SPI1 STAT: TXUR Mask */
-#define SPI1_STAT_SSA_Pos 4 /*!< SPI1 STAT: SSA Position */
-#define SPI1_STAT_SSA_Msk (0x01UL << SPI1_STAT_SSA_Pos) /*!< SPI1 STAT: SSA Mask */
-#define SPI1_STAT_SSD_Pos 5 /*!< SPI1 STAT: SSD Position */
-#define SPI1_STAT_SSD_Msk (0x01UL << SPI1_STAT_SSD_Pos) /*!< SPI1 STAT: SSD Mask */
-#define SPI1_STAT_STALLED_Pos 6 /*!< SPI1 STAT: STALLED Position */
-#define SPI1_STAT_STALLED_Msk (0x01UL << SPI1_STAT_STALLED_Pos) /*!< SPI1 STAT: STALLED Mask */
-#define SPI1_STAT_ENDTRANSFER_Pos 7 /*!< SPI1 STAT: ENDTRANSFER Position */
-#define SPI1_STAT_ENDTRANSFER_Msk (0x01UL << SPI1_STAT_ENDTRANSFER_Pos) /*!< SPI1 STAT: ENDTRANSFER Mask */
-#define SPI1_STAT_MSTIDLE_Pos 8 /*!< SPI1 STAT: MSTIDLE Position */
-#define SPI1_STAT_MSTIDLE_Msk (0x01UL << SPI1_STAT_MSTIDLE_Pos) /*!< SPI1 STAT: MSTIDLE Mask */
-
-/* ------------------------------- u1_spi_INTENSET ------------------------------ */
-#define SPI1_INTENSET_RXOVEN_Pos 2 /*!< SPI1 INTENSET: RXOVEN Position */
-#define SPI1_INTENSET_RXOVEN_Msk (0x01UL << SPI1_INTENSET_RXOVEN_Pos) /*!< SPI1 INTENSET: RXOVEN Mask */
-#define SPI1_INTENSET_TXUREN_Pos 3 /*!< SPI1 INTENSET: TXUREN Position */
-#define SPI1_INTENSET_TXUREN_Msk (0x01UL << SPI1_INTENSET_TXUREN_Pos) /*!< SPI1 INTENSET: TXUREN Mask */
-#define SPI1_INTENSET_SSAEN_Pos 4 /*!< SPI1 INTENSET: SSAEN Position */
-#define SPI1_INTENSET_SSAEN_Msk (0x01UL << SPI1_INTENSET_SSAEN_Pos) /*!< SPI1 INTENSET: SSAEN Mask */
-#define SPI1_INTENSET_SSDEN_Pos 5 /*!< SPI1 INTENSET: SSDEN Position */
-#define SPI1_INTENSET_SSDEN_Msk (0x01UL << SPI1_INTENSET_SSDEN_Pos) /*!< SPI1 INTENSET: SSDEN Mask */
-#define SPI1_INTENSET_MSTIDLEEN_Pos 8 /*!< SPI1 INTENSET: MSTIDLEEN Position */
-#define SPI1_INTENSET_MSTIDLEEN_Msk (0x01UL << SPI1_INTENSET_MSTIDLEEN_Pos) /*!< SPI1 INTENSET: MSTIDLEEN Mask */
-
-/* ------------------------------- u1_spi_INTENCLR ------------------------------ */
-#define SPI1_INTENCLR_RXOVCLR_Pos 2 /*!< SPI1 INTENCLR: RXOVCLR Position */
-#define SPI1_INTENCLR_RXOVCLR_Msk (0x01UL << SPI1_INTENCLR_RXOVCLR_Pos) /*!< SPI1 INTENCLR: RXOVCLR Mask */
-#define SPI1_INTENCLR_TXURCLR_Pos 3 /*!< SPI1 INTENCLR: TXURCLR Position */
-#define SPI1_INTENCLR_TXURCLR_Msk (0x01UL << SPI1_INTENCLR_TXURCLR_Pos) /*!< SPI1 INTENCLR: TXURCLR Mask */
-#define SPI1_INTENCLR_SSACLR_Pos 4 /*!< SPI1 INTENCLR: SSACLR Position */
-#define SPI1_INTENCLR_SSACLR_Msk (0x01UL << SPI1_INTENCLR_SSACLR_Pos) /*!< SPI1 INTENCLR: SSACLR Mask */
-#define SPI1_INTENCLR_SSDCLR_Pos 5 /*!< SPI1 INTENCLR: SSDCLR Position */
-#define SPI1_INTENCLR_SSDCLR_Msk (0x01UL << SPI1_INTENCLR_SSDCLR_Pos) /*!< SPI1 INTENCLR: SSDCLR Mask */
-#define SPI1_INTENCLR_MSTIDLECLR_Pos 8 /*!< SPI1 INTENCLR: MSTIDLECLR Position */
-#define SPI1_INTENCLR_MSTIDLECLR_Msk (0x01UL << SPI1_INTENCLR_MSTIDLECLR_Pos) /*!< SPI1 INTENCLR: MSTIDLECLR Mask */
-
-/* -------------------------------- u1_spi_TXCTL -------------------------------- */
-#define SPI1_TXCTL_TXSSEL0_N_Pos 16 /*!< SPI1 TXCTL: TXSSEL0_N Position */
-#define SPI1_TXCTL_TXSSEL0_N_Msk (0x01UL << SPI1_TXCTL_TXSSEL0_N_Pos) /*!< SPI1 TXCTL: TXSSEL0_N Mask */
-#define SPI1_TXCTL_TXSSEL1_N_Pos 17 /*!< SPI1 TXCTL: TXSSEL1_N Position */
-#define SPI1_TXCTL_TXSSEL1_N_Msk (0x01UL << SPI1_TXCTL_TXSSEL1_N_Pos) /*!< SPI1 TXCTL: TXSSEL1_N Mask */
-#define SPI1_TXCTL_TXSSEL2_N_Pos 18 /*!< SPI1 TXCTL: TXSSEL2_N Position */
-#define SPI1_TXCTL_TXSSEL2_N_Msk (0x01UL << SPI1_TXCTL_TXSSEL2_N_Pos) /*!< SPI1 TXCTL: TXSSEL2_N Mask */
-#define SPI1_TXCTL_TXSSEL3_N_Pos 19 /*!< SPI1 TXCTL: TXSSEL3_N Position */
-#define SPI1_TXCTL_TXSSEL3_N_Msk (0x01UL << SPI1_TXCTL_TXSSEL3_N_Pos) /*!< SPI1 TXCTL: TXSSEL3_N Mask */
-#define SPI1_TXCTL_EOTR_Pos 20 /*!< SPI1 TXCTL: EOTR Position */
-#define SPI1_TXCTL_EOTR_Msk (0x01UL << SPI1_TXCTL_EOTR_Pos) /*!< SPI1 TXCTL: EOTR Mask */
-#define SPI1_TXCTL_EOFR_Pos 21 /*!< SPI1 TXCTL: EOFR Position */
-#define SPI1_TXCTL_EOFR_Msk (0x01UL << SPI1_TXCTL_EOFR_Pos) /*!< SPI1 TXCTL: EOFR Mask */
-#define SPI1_TXCTL_RXIGNORE_Pos 22 /*!< SPI1 TXCTL: RXIGNORE Position */
-#define SPI1_TXCTL_RXIGNORE_Msk (0x01UL << SPI1_TXCTL_RXIGNORE_Pos) /*!< SPI1 TXCTL: RXIGNORE Mask */
-#define SPI1_TXCTL_LEN_Pos 24 /*!< SPI1 TXCTL: LEN Position */
-#define SPI1_TXCTL_LEN_Msk (0x0fUL << SPI1_TXCTL_LEN_Pos) /*!< SPI1 TXCTL: LEN Mask */
-
-/* --------------------------------- u1_spi_DIV --------------------------------- */
-#define SPI1_DIV_DIVVAL_Pos 0 /*!< SPI1 DIV: DIVVAL Position */
-#define SPI1_DIV_DIVVAL_Msk (0x0000ffffUL << SPI1_DIV_DIVVAL_Pos) /*!< SPI1 DIV: DIVVAL Mask */
-
-/* ------------------------------- u1_spi_INTSTAT ------------------------------- */
-#define SPI1_INTSTAT_RXOV_Pos 2 /*!< SPI1 INTSTAT: RXOV Position */
-#define SPI1_INTSTAT_RXOV_Msk (0x01UL << SPI1_INTSTAT_RXOV_Pos) /*!< SPI1 INTSTAT: RXOV Mask */
-#define SPI1_INTSTAT_TXUR_Pos 3 /*!< SPI1 INTSTAT: TXUR Position */
-#define SPI1_INTSTAT_TXUR_Msk (0x01UL << SPI1_INTSTAT_TXUR_Pos) /*!< SPI1 INTSTAT: TXUR Mask */
-#define SPI1_INTSTAT_SSA_Pos 4 /*!< SPI1 INTSTAT: SSA Position */
-#define SPI1_INTSTAT_SSA_Msk (0x01UL << SPI1_INTSTAT_SSA_Pos) /*!< SPI1 INTSTAT: SSA Mask */
-#define SPI1_INTSTAT_SSD_Pos 5 /*!< SPI1 INTSTAT: SSD Position */
-#define SPI1_INTSTAT_SSD_Msk (0x01UL << SPI1_INTSTAT_SSD_Pos) /*!< SPI1 INTSTAT: SSD Mask */
-#define SPI1_INTSTAT_MSTIDLE_Pos 8 /*!< SPI1 INTSTAT: MSTIDLE Position */
-#define SPI1_INTSTAT_MSTIDLE_Msk (0x01UL << SPI1_INTSTAT_MSTIDLE_Pos) /*!< SPI1 INTSTAT: MSTIDLE Mask */
-
-/* ------------------------------- u1_spi_FIFOCFG ------------------------------- */
-#define SPI1_FIFOCFG_ENABLETX_Pos 0 /*!< SPI1 FIFOCFG: ENABLETX Position */
-#define SPI1_FIFOCFG_ENABLETX_Msk (0x01UL << SPI1_FIFOCFG_ENABLETX_Pos) /*!< SPI1 FIFOCFG: ENABLETX Mask */
-#define SPI1_FIFOCFG_ENABLERX_Pos 1 /*!< SPI1 FIFOCFG: ENABLERX Position */
-#define SPI1_FIFOCFG_ENABLERX_Msk (0x01UL << SPI1_FIFOCFG_ENABLERX_Pos) /*!< SPI1 FIFOCFG: ENABLERX Mask */
-#define SPI1_FIFOCFG_SIZE_Pos 4 /*!< SPI1 FIFOCFG: SIZE Position */
-#define SPI1_FIFOCFG_SIZE_Msk (0x03UL << SPI1_FIFOCFG_SIZE_Pos) /*!< SPI1 FIFOCFG: SIZE Mask */
-#define SPI1_FIFOCFG_DMATX_Pos 12 /*!< SPI1 FIFOCFG: DMATX Position */
-#define SPI1_FIFOCFG_DMATX_Msk (0x01UL << SPI1_FIFOCFG_DMATX_Pos) /*!< SPI1 FIFOCFG: DMATX Mask */
-#define SPI1_FIFOCFG_DMARX_Pos 13 /*!< SPI1 FIFOCFG: DMARX Position */
-#define SPI1_FIFOCFG_DMARX_Msk (0x01UL << SPI1_FIFOCFG_DMARX_Pos) /*!< SPI1 FIFOCFG: DMARX Mask */
-#define SPI1_FIFOCFG_WAKETX_Pos 14 /*!< SPI1 FIFOCFG: WAKETX Position */
-#define SPI1_FIFOCFG_WAKETX_Msk (0x01UL << SPI1_FIFOCFG_WAKETX_Pos) /*!< SPI1 FIFOCFG: WAKETX Mask */
-#define SPI1_FIFOCFG_WAKERX_Pos 15 /*!< SPI1 FIFOCFG: WAKERX Position */
-#define SPI1_FIFOCFG_WAKERX_Msk (0x01UL << SPI1_FIFOCFG_WAKERX_Pos) /*!< SPI1 FIFOCFG: WAKERX Mask */
-#define SPI1_FIFOCFG_EMPTYTX_Pos 16 /*!< SPI1 FIFOCFG: EMPTYTX Position */
-#define SPI1_FIFOCFG_EMPTYTX_Msk (0x01UL << SPI1_FIFOCFG_EMPTYTX_Pos) /*!< SPI1 FIFOCFG: EMPTYTX Mask */
-#define SPI1_FIFOCFG_EMPTYRX_Pos 17 /*!< SPI1 FIFOCFG: EMPTYRX Position */
-#define SPI1_FIFOCFG_EMPTYRX_Msk (0x01UL << SPI1_FIFOCFG_EMPTYRX_Pos) /*!< SPI1 FIFOCFG: EMPTYRX Mask */
-#define SPI1_FIFOCFG_POPDBG_Pos 18 /*!< SPI1 FIFOCFG: POPDBG Position */
-#define SPI1_FIFOCFG_POPDBG_Msk (0x01UL << SPI1_FIFOCFG_POPDBG_Pos) /*!< SPI1 FIFOCFG: POPDBG Mask */
-
-/* ------------------------------- u1_spi_FIFOSTAT ------------------------------ */
-#define SPI1_FIFOSTAT_TXERR_Pos 0 /*!< SPI1 FIFOSTAT: TXERR Position */
-#define SPI1_FIFOSTAT_TXERR_Msk (0x01UL << SPI1_FIFOSTAT_TXERR_Pos) /*!< SPI1 FIFOSTAT: TXERR Mask */
-#define SPI1_FIFOSTAT_RXERR_Pos 1 /*!< SPI1 FIFOSTAT: RXERR Position */
-#define SPI1_FIFOSTAT_RXERR_Msk (0x01UL << SPI1_FIFOSTAT_RXERR_Pos) /*!< SPI1 FIFOSTAT: RXERR Mask */
-#define SPI1_FIFOSTAT_PERINT_Pos 3 /*!< SPI1 FIFOSTAT: PERINT Position */
-#define SPI1_FIFOSTAT_PERINT_Msk (0x01UL << SPI1_FIFOSTAT_PERINT_Pos) /*!< SPI1 FIFOSTAT: PERINT Mask */
-#define SPI1_FIFOSTAT_TXEMPTY_Pos 4 /*!< SPI1 FIFOSTAT: TXEMPTY Position */
-#define SPI1_FIFOSTAT_TXEMPTY_Msk (0x01UL << SPI1_FIFOSTAT_TXEMPTY_Pos) /*!< SPI1 FIFOSTAT: TXEMPTY Mask */
-#define SPI1_FIFOSTAT_TXNOTFULL_Pos 5 /*!< SPI1 FIFOSTAT: TXNOTFULL Position */
-#define SPI1_FIFOSTAT_TXNOTFULL_Msk (0x01UL << SPI1_FIFOSTAT_TXNOTFULL_Pos) /*!< SPI1 FIFOSTAT: TXNOTFULL Mask */
-#define SPI1_FIFOSTAT_RXNOTEMPTY_Pos 6 /*!< SPI1 FIFOSTAT: RXNOTEMPTY Position */
-#define SPI1_FIFOSTAT_RXNOTEMPTY_Msk (0x01UL << SPI1_FIFOSTAT_RXNOTEMPTY_Pos) /*!< SPI1 FIFOSTAT: RXNOTEMPTY Mask */
-#define SPI1_FIFOSTAT_RXFULL_Pos 7 /*!< SPI1 FIFOSTAT: RXFULL Position */
-#define SPI1_FIFOSTAT_RXFULL_Msk (0x01UL << SPI1_FIFOSTAT_RXFULL_Pos) /*!< SPI1 FIFOSTAT: RXFULL Mask */
-#define SPI1_FIFOSTAT_TXLVL_Pos 8 /*!< SPI1 FIFOSTAT: TXLVL Position */
-#define SPI1_FIFOSTAT_TXLVL_Msk (0x1fUL << SPI1_FIFOSTAT_TXLVL_Pos) /*!< SPI1 FIFOSTAT: TXLVL Mask */
-#define SPI1_FIFOSTAT_RXLVL_Pos 16 /*!< SPI1 FIFOSTAT: RXLVL Position */
-#define SPI1_FIFOSTAT_RXLVL_Msk (0x1fUL << SPI1_FIFOSTAT_RXLVL_Pos) /*!< SPI1 FIFOSTAT: RXLVL Mask */
-
-/* ------------------------------- u1_spi_FIFOTRIG ------------------------------ */
-#define SPI1_FIFOTRIG_TXLVLENA_Pos 0 /*!< SPI1 FIFOTRIG: TXLVLENA Position */
-#define SPI1_FIFOTRIG_TXLVLENA_Msk (0x01UL << SPI1_FIFOTRIG_TXLVLENA_Pos) /*!< SPI1 FIFOTRIG: TXLVLENA Mask */
-#define SPI1_FIFOTRIG_RXLVLENA_Pos 1 /*!< SPI1 FIFOTRIG: RXLVLENA Position */
-#define SPI1_FIFOTRIG_RXLVLENA_Msk (0x01UL << SPI1_FIFOTRIG_RXLVLENA_Pos) /*!< SPI1 FIFOTRIG: RXLVLENA Mask */
-#define SPI1_FIFOTRIG_TXLVL_Pos 8 /*!< SPI1 FIFOTRIG: TXLVL Position */
-#define SPI1_FIFOTRIG_TXLVL_Msk (0x0fUL << SPI1_FIFOTRIG_TXLVL_Pos) /*!< SPI1 FIFOTRIG: TXLVL Mask */
-#define SPI1_FIFOTRIG_RXLVL_Pos 16 /*!< SPI1 FIFOTRIG: RXLVL Position */
-#define SPI1_FIFOTRIG_RXLVL_Msk (0x0fUL << SPI1_FIFOTRIG_RXLVL_Pos) /*!< SPI1 FIFOTRIG: RXLVL Mask */
-
-/* ----------------------------- u1_spi_FIFOINTENSET ---------------------------- */
-#define SPI1_FIFOINTENSET_TXERR_Pos 0 /*!< SPI1 FIFOINTENSET: TXERR Position */
-#define SPI1_FIFOINTENSET_TXERR_Msk (0x01UL << SPI1_FIFOINTENSET_TXERR_Pos) /*!< SPI1 FIFOINTENSET: TXERR Mask */
-#define SPI1_FIFOINTENSET_RXERR_Pos 1 /*!< SPI1 FIFOINTENSET: RXERR Position */
-#define SPI1_FIFOINTENSET_RXERR_Msk (0x01UL << SPI1_FIFOINTENSET_RXERR_Pos) /*!< SPI1 FIFOINTENSET: RXERR Mask */
-#define SPI1_FIFOINTENSET_TXLVL_Pos 2 /*!< SPI1 FIFOINTENSET: TXLVL Position */
-#define SPI1_FIFOINTENSET_TXLVL_Msk (0x01UL << SPI1_FIFOINTENSET_TXLVL_Pos) /*!< SPI1 FIFOINTENSET: TXLVL Mask */
-#define SPI1_FIFOINTENSET_RXLVL_Pos 3 /*!< SPI1 FIFOINTENSET: RXLVL Position */
-#define SPI1_FIFOINTENSET_RXLVL_Msk (0x01UL << SPI1_FIFOINTENSET_RXLVL_Pos) /*!< SPI1 FIFOINTENSET: RXLVL Mask */
-
-/* ----------------------------- u1_spi_FIFOINTENCLR ---------------------------- */
-#define SPI1_FIFOINTENCLR_TXERR_Pos 0 /*!< SPI1 FIFOINTENCLR: TXERR Position */
-#define SPI1_FIFOINTENCLR_TXERR_Msk (0x01UL << SPI1_FIFOINTENCLR_TXERR_Pos) /*!< SPI1 FIFOINTENCLR: TXERR Mask */
-#define SPI1_FIFOINTENCLR_RXERR_Pos 1 /*!< SPI1 FIFOINTENCLR: RXERR Position */
-#define SPI1_FIFOINTENCLR_RXERR_Msk (0x01UL << SPI1_FIFOINTENCLR_RXERR_Pos) /*!< SPI1 FIFOINTENCLR: RXERR Mask */
-#define SPI1_FIFOINTENCLR_TXLVL_Pos 2 /*!< SPI1 FIFOINTENCLR: TXLVL Position */
-#define SPI1_FIFOINTENCLR_TXLVL_Msk (0x01UL << SPI1_FIFOINTENCLR_TXLVL_Pos) /*!< SPI1 FIFOINTENCLR: TXLVL Mask */
-#define SPI1_FIFOINTENCLR_RXLVL_Pos 3 /*!< SPI1 FIFOINTENCLR: RXLVL Position */
-#define SPI1_FIFOINTENCLR_RXLVL_Msk (0x01UL << SPI1_FIFOINTENCLR_RXLVL_Pos) /*!< SPI1 FIFOINTENCLR: RXLVL Mask */
-
-/* ----------------------------- u1_spi_FIFOINTSTAT ----------------------------- */
-#define SPI1_FIFOINTSTAT_TXERR_Pos 0 /*!< SPI1 FIFOINTSTAT: TXERR Position */
-#define SPI1_FIFOINTSTAT_TXERR_Msk (0x01UL << SPI1_FIFOINTSTAT_TXERR_Pos) /*!< SPI1 FIFOINTSTAT: TXERR Mask */
-#define SPI1_FIFOINTSTAT_RXERR_Pos 1 /*!< SPI1 FIFOINTSTAT: RXERR Position */
-#define SPI1_FIFOINTSTAT_RXERR_Msk (0x01UL << SPI1_FIFOINTSTAT_RXERR_Pos) /*!< SPI1 FIFOINTSTAT: RXERR Mask */
-#define SPI1_FIFOINTSTAT_TXLVL_Pos 2 /*!< SPI1 FIFOINTSTAT: TXLVL Position */
-#define SPI1_FIFOINTSTAT_TXLVL_Msk (0x01UL << SPI1_FIFOINTSTAT_TXLVL_Pos) /*!< SPI1 FIFOINTSTAT: TXLVL Mask */
-#define SPI1_FIFOINTSTAT_RXLVL_Pos 3 /*!< SPI1 FIFOINTSTAT: RXLVL Position */
-#define SPI1_FIFOINTSTAT_RXLVL_Msk (0x01UL << SPI1_FIFOINTSTAT_RXLVL_Pos) /*!< SPI1 FIFOINTSTAT: RXLVL Mask */
-#define SPI1_FIFOINTSTAT_PERINT_Pos 4 /*!< SPI1 FIFOINTSTAT: PERINT Position */
-#define SPI1_FIFOINTSTAT_PERINT_Msk (0x01UL << SPI1_FIFOINTSTAT_PERINT_Pos) /*!< SPI1 FIFOINTSTAT: PERINT Mask */
-
-/* -------------------------------- u1_spi_FIFOWR ------------------------------- */
-#define SPI1_FIFOWR_TXDATA_Pos 0 /*!< SPI1 FIFOWR: TXDATA Position */
-#define SPI1_FIFOWR_TXDATA_Msk (0x0000ffffUL << SPI1_FIFOWR_TXDATA_Pos) /*!< SPI1 FIFOWR: TXDATA Mask */
-#define SPI1_FIFOWR_TXSSEL0_N_Pos 16 /*!< SPI1 FIFOWR: TXSSEL0_N Position */
-#define SPI1_FIFOWR_TXSSEL0_N_Msk (0x01UL << SPI1_FIFOWR_TXSSEL0_N_Pos) /*!< SPI1 FIFOWR: TXSSEL0_N Mask */
-#define SPI1_FIFOWR_TXSSEL1_N_Pos 17 /*!< SPI1 FIFOWR: TXSSEL1_N Position */
-#define SPI1_FIFOWR_TXSSEL1_N_Msk (0x01UL << SPI1_FIFOWR_TXSSEL1_N_Pos) /*!< SPI1 FIFOWR: TXSSEL1_N Mask */
-#define SPI1_FIFOWR_TXSSEL2_N_Pos 18 /*!< SPI1 FIFOWR: TXSSEL2_N Position */
-#define SPI1_FIFOWR_TXSSEL2_N_Msk (0x01UL << SPI1_FIFOWR_TXSSEL2_N_Pos) /*!< SPI1 FIFOWR: TXSSEL2_N Mask */
-#define SPI1_FIFOWR_TXSSEL3_N_Pos 19 /*!< SPI1 FIFOWR: TXSSEL3_N Position */
-#define SPI1_FIFOWR_TXSSEL3_N_Msk (0x01UL << SPI1_FIFOWR_TXSSEL3_N_Pos) /*!< SPI1 FIFOWR: TXSSEL3_N Mask */
-#define SPI1_FIFOWR_EOTR_Pos 20 /*!< SPI1 FIFOWR: EOTR Position */
-#define SPI1_FIFOWR_EOTR_Msk (0x01UL << SPI1_FIFOWR_EOTR_Pos) /*!< SPI1 FIFOWR: EOTR Mask */
-#define SPI1_FIFOWR_EOFR_Pos 21 /*!< SPI1 FIFOWR: EOFR Position */
-#define SPI1_FIFOWR_EOFR_Msk (0x01UL << SPI1_FIFOWR_EOFR_Pos) /*!< SPI1 FIFOWR: EOFR Mask */
-#define SPI1_FIFOWR_RXIGNORE_Pos 22 /*!< SPI1 FIFOWR: RXIGNORE Position */
-#define SPI1_FIFOWR_RXIGNORE_Msk (0x01UL << SPI1_FIFOWR_RXIGNORE_Pos) /*!< SPI1 FIFOWR: RXIGNORE Mask */
-#define SPI1_FIFOWR_LEN_Pos 24 /*!< SPI1 FIFOWR: LEN Position */
-#define SPI1_FIFOWR_LEN_Msk (0x0fUL << SPI1_FIFOWR_LEN_Pos) /*!< SPI1 FIFOWR: LEN Mask */
-
-/* -------------------------------- u1_spi_FIFORD ------------------------------- */
-#define SPI1_FIFORD_RXDATA_Pos 0 /*!< SPI1 FIFORD: RXDATA Position */
-#define SPI1_FIFORD_RXDATA_Msk (0x0000ffffUL << SPI1_FIFORD_RXDATA_Pos) /*!< SPI1 FIFORD: RXDATA Mask */
-#define SPI1_FIFORD_RXSSEL0_N_Pos 16 /*!< SPI1 FIFORD: RXSSEL0_N Position */
-#define SPI1_FIFORD_RXSSEL0_N_Msk (0x01UL << SPI1_FIFORD_RXSSEL0_N_Pos) /*!< SPI1 FIFORD: RXSSEL0_N Mask */
-#define SPI1_FIFORD_RXSSEL1_N_Pos 17 /*!< SPI1 FIFORD: RXSSEL1_N Position */
-#define SPI1_FIFORD_RXSSEL1_N_Msk (0x01UL << SPI1_FIFORD_RXSSEL1_N_Pos) /*!< SPI1 FIFORD: RXSSEL1_N Mask */
-#define SPI1_FIFORD_RXSSEL2_N_Pos 18 /*!< SPI1 FIFORD: RXSSEL2_N Position */
-#define SPI1_FIFORD_RXSSEL2_N_Msk (0x01UL << SPI1_FIFORD_RXSSEL2_N_Pos) /*!< SPI1 FIFORD: RXSSEL2_N Mask */
-#define SPI1_FIFORD_RXSSEL3_N_Pos 19 /*!< SPI1 FIFORD: RXSSEL3_N Position */
-#define SPI1_FIFORD_RXSSEL3_N_Msk (0x01UL << SPI1_FIFORD_RXSSEL3_N_Pos) /*!< SPI1 FIFORD: RXSSEL3_N Mask */
-#define SPI1_FIFORD_SOT_Pos 20 /*!< SPI1 FIFORD: SOT Position */
-#define SPI1_FIFORD_SOT_Msk (0x01UL << SPI1_FIFORD_SOT_Pos) /*!< SPI1 FIFORD: SOT Mask */
-
-/* ----------------------------- u1_spi_FIFORDNOPOP ----------------------------- */
-#define SPI1_FIFORDNOPOP_RXDATA_Pos 0 /*!< SPI1 FIFORDNOPOP: RXDATA Position */
-#define SPI1_FIFORDNOPOP_RXDATA_Msk (0x0000ffffUL << SPI1_FIFORDNOPOP_RXDATA_Pos) /*!< SPI1 FIFORDNOPOP: RXDATA Mask */
-#define SPI1_FIFORDNOPOP_RXSSEL0_N_Pos 16 /*!< SPI1 FIFORDNOPOP: RXSSEL0_N Position */
-#define SPI1_FIFORDNOPOP_RXSSEL0_N_Msk (0x01UL << SPI1_FIFORDNOPOP_RXSSEL0_N_Pos) /*!< SPI1 FIFORDNOPOP: RXSSEL0_N Mask */
-#define SPI1_FIFORDNOPOP_RXSSEL1_N_Pos 17 /*!< SPI1 FIFORDNOPOP: RXSSEL1_N Position */
-#define SPI1_FIFORDNOPOP_RXSSEL1_N_Msk (0x01UL << SPI1_FIFORDNOPOP_RXSSEL1_N_Pos) /*!< SPI1 FIFORDNOPOP: RXSSEL1_N Mask */
-#define SPI1_FIFORDNOPOP_RXSSEL2_N_Pos 18 /*!< SPI1 FIFORDNOPOP: RXSSEL2_N Position */
-#define SPI1_FIFORDNOPOP_RXSSEL2_N_Msk (0x01UL << SPI1_FIFORDNOPOP_RXSSEL2_N_Pos) /*!< SPI1 FIFORDNOPOP: RXSSEL2_N Mask */
-#define SPI1_FIFORDNOPOP_RXSSEL3_N_Pos 19 /*!< SPI1 FIFORDNOPOP: RXSSEL3_N Position */
-#define SPI1_FIFORDNOPOP_RXSSEL3_N_Msk (0x01UL << SPI1_FIFORDNOPOP_RXSSEL3_N_Pos) /*!< SPI1 FIFORDNOPOP: RXSSEL3_N Mask */
-#define SPI1_FIFORDNOPOP_SOT_Pos 20 /*!< SPI1 FIFORDNOPOP: SOT Position */
-#define SPI1_FIFORDNOPOP_SOT_Msk (0x01UL << SPI1_FIFORDNOPOP_SOT_Pos) /*!< SPI1 FIFORDNOPOP: SOT Mask */
-
-/* -------------------------------- u1_spi_PSELID ------------------------------- */
-#define SPI1_PSELID_PERSEL_Pos 0 /*!< SPI1 PSELID: PERSEL Position */
-#define SPI1_PSELID_PERSEL_Msk (0x07UL << SPI1_PSELID_PERSEL_Pos) /*!< SPI1 PSELID: PERSEL Mask */
-#define SPI1_PSELID_LOCK_Pos 3 /*!< SPI1 PSELID: LOCK Position */
-#define SPI1_PSELID_LOCK_Msk (0x01UL << SPI1_PSELID_LOCK_Pos) /*!< SPI1 PSELID: LOCK Mask */
-#define SPI1_PSELID_SPIPRESENT_Pos 5 /*!< SPI1 PSELID: SPIPRESENT Position */
-#define SPI1_PSELID_SPIPRESENT_Msk (0x01UL << SPI1_PSELID_SPIPRESENT_Pos) /*!< SPI1 PSELID: SPIPRESENT Mask */
-#define SPI1_PSELID_ID_Pos 12 /*!< SPI1 PSELID: ID Position */
-#define SPI1_PSELID_ID_Msk (0x000fffffUL << SPI1_PSELID_ID_Pos) /*!< SPI1 PSELID: ID Mask */
-
-/* ---------------------------------- u1_spi_ID --------------------------------- */
-#define SPI1_ID_APERTURE_Pos 0 /*!< SPI1 ID: APERTURE Position */
-#define SPI1_ID_APERTURE_Msk (0x000000ffUL << SPI1_ID_APERTURE_Pos) /*!< SPI1 ID: APERTURE Mask */
-#define SPI1_ID_MIN_REV_Pos 8 /*!< SPI1 ID: MIN_REV Position */
-#define SPI1_ID_MIN_REV_Msk (0x0fUL << SPI1_ID_MIN_REV_Pos) /*!< SPI1 ID: MIN_REV Mask */
-#define SPI1_ID_MAJ_REV_Pos 12 /*!< SPI1 ID: MAJ_REV Position */
-#define SPI1_ID_MAJ_REV_Msk (0x0fUL << SPI1_ID_MAJ_REV_Pos) /*!< SPI1 ID: MAJ_REV Mask */
-#define SPI1_ID_ID_Pos 16 /*!< SPI1 ID: ID Position */
-#define SPI1_ID_ID_Msk (0x0000ffffUL << SPI1_ID_ID_Pos) /*!< SPI1 ID: ID Mask */
-
-
-/* ================================================================================ */
-/* ================ struct 'u_hash' Position & Mask ================ */
-/* ================================================================================ */
-
-
-/* --------------------------------- u_hash_CTRL -------------------------------- */
-#define HASH_CTRL_CTRL_Pos 0 /*!< HASH CTRL: CTRL Position */
-#define HASH_CTRL_CTRL_Msk (0xffffffffUL << HASH_CTRL_CTRL_Pos) /*!< HASH CTRL: CTRL Mask */
-
-/* --------------------------------- u_hash_STAT -------------------------------- */
-#define HASH_STAT_STAT_Pos 0 /*!< HASH STAT: STAT Position */
-#define HASH_STAT_STAT_Msk (0xffffffffUL << HASH_STAT_STAT_Pos) /*!< HASH STAT: STAT Mask */
-
-/* -------------------------------- u_hash_INTEN -------------------------------- */
-#define HASH_INTEN_INTEN_Pos 0 /*!< HASH INTEN: INTEN Position */
-#define HASH_INTEN_INTEN_Msk (0xffffffffUL << HASH_INTEN_INTEN_Pos) /*!< HASH INTEN: INTEN Mask */
-
-/* -------------------------------- u_hash_INTCLR ------------------------------- */
-#define HASH_INTCLR_INTCLR_Pos 0 /*!< HASH INTCLR: INTCLR Position */
-#define HASH_INTCLR_INTCLR_Msk (0xffffffffUL << HASH_INTCLR_INTCLR_Pos) /*!< HASH INTCLR: INTCLR Mask */
-
-/* ------------------------------- u_hash_MEMCTRL ------------------------------- */
-#define HASH_MEMCTRL_MEMCTRL_Pos 0 /*!< HASH MEMCTRL: MEMCTRL Position */
-#define HASH_MEMCTRL_MEMCTRL_Msk (0xffffffffUL << HASH_MEMCTRL_MEMCTRL_Pos) /*!< HASH MEMCTRL: MEMCTRL Mask */
-
-/* ------------------------------- u_hash_MEMADDR ------------------------------- */
-#define HASH_MEMADDR_MEMADDR_Pos 0 /*!< HASH MEMADDR: MEMADDR Position */
-#define HASH_MEMADDR_MEMADDR_Msk (0xffffffffUL << HASH_MEMADDR_MEMADDR_Pos) /*!< HASH MEMADDR: MEMADDR Mask */
-
-/* -------------------------------- u_hash_INDATA ------------------------------- */
-#define HASH_INDATA_INDATA_Pos 0 /*!< HASH INDATA: INDATA Position */
-#define HASH_INDATA_INDATA_Msk (0xffffffffUL << HASH_INDATA_INDATA_Pos) /*!< HASH INDATA: INDATA Mask */
-
-/* -------------------------------- u_hash_DIGEST ------------------------------- */
-#define HASH_DIGEST_DIGEST_Pos 0 /*!< HASH DIGEST: DIGEST Position */
-#define HASH_DIGEST_DIGEST_Msk (0xffffffffUL << HASH_DIGEST_DIGEST_Pos) /*!< HASH DIGEST: DIGEST Mask */
-
-/* -------------------------------- u_hash_OUTD2 -------------------------------- */
-#define HASH_OUTD2_OUTD2_Pos 0 /*!< HASH OUTD2: OUTD2 Position */
-#define HASH_OUTD2_OUTD2_Msk (0xffffffffUL << HASH_OUTD2_OUTD2_Pos) /*!< HASH OUTD2: OUTD2 Mask */
-
-/* -------------------------------- u_hash_CRYPT -------------------------------- */
-#define HASH_CRYPT_CRYPT_Pos 0 /*!< HASH CRYPT: CRYPT Position */
-#define HASH_CRYPT_CRYPT_Msk (0xffffffffUL << HASH_CRYPT_CRYPT_Pos) /*!< HASH CRYPT: CRYPT Mask */
-
-/* -------------------------------- u_hash_CONFIG ------------------------------- */
-#define HASH_CONFIG_CONFIG_Pos 0 /*!< HASH CONFIG: CONFIG Position */
-#define HASH_CONFIG_CONFIG_Msk (0xffffffffUL << HASH_CONFIG_CONFIG_Pos) /*!< HASH CONFIG: CONFIG Mask */
-
-/* --------------------------------- u_hash_MASK -------------------------------- */
-#define HASH_MASK_MASK_Pos 0 /*!< HASH MASK: MASK Position */
-#define HASH_MASK_MASK_Msk (0xffffffffUL << HASH_MASK_MASK_Pos) /*!< HASH MASK: MASK Mask */
-
-/* ---------------------------------- u_hash_ID --------------------------------- */
-#define HASH_ID_APERTURE_Pos 0 /*!< HASH ID: APERTURE Position */
-#define HASH_ID_APERTURE_Msk (0x000000ffUL << HASH_ID_APERTURE_Pos) /*!< HASH ID: APERTURE Mask */
-#define HASH_ID_MIN_REV_Pos 8 /*!< HASH ID: MIN_REV Position */
-#define HASH_ID_MIN_REV_Msk (0x0fUL << HASH_ID_MIN_REV_Pos) /*!< HASH ID: MIN_REV Mask */
-#define HASH_ID_MAJ_REV_Pos 12 /*!< HASH ID: MAJ_REV Position */
-#define HASH_ID_MAJ_REV_Msk (0x0fUL << HASH_ID_MAJ_REV_Pos) /*!< HASH ID: MAJ_REV Mask */
-#define HASH_ID_ID_Pos 16 /*!< HASH ID: ID Position */
-#define HASH_ID_ID_Msk (0x0000ffffUL << HASH_ID_ID_Pos) /*!< HASH ID: ID Mask */
-
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-
-#define u_syscon_BASE 0x40000000UL
-#define u_otpc_BASE 0x40002000UL
-#define u0_i2c_BASE 0x40003000UL
-#define u1_i2c_BASE 0x40004000UL
-#define u2_i2c_BASE 0x40005000UL
-#define u_iso7816_BASE 0x40006000UL
-#define u_cic_irb_BASE 0x40007000UL
-#define u_codepatch_BASE 0x40008000UL
-#define u_flash_BASE 0x40009000UL
-#define u_wwdt_BASE 0x4000A000UL
-#define u_rtc_BASE 0x4000B000UL
-#define u_pwm_BASE 0x4000C000UL
-#define u_rng_BASE 0x4000D000UL
-#define u_inmux_BASE 0x4000E000UL
-#define u_iocon_BASE 0x4000F000UL
-#define u_pint_BASE 0x40010000UL
-#define u_gint_BASE 0x40011000UL
-#define u_pmc_BASE 0x40012000UL
-#define u_ble_dp_top_BASE 0x40014000UL
-#define u_pvt_BASE 0x40015000UL
-#define u_async_syscon_BASE 0x40020000UL
-#define u0_timer_BASE 0x40021000UL
-#define u1_timer_BASE 0x40022000UL
-#define u_gpio_BASE 0x40080000UL
-#define u_spifi_BASE 0x40084000UL
-#define u_dma_BASE 0x40085000UL
-#define u_aes256_BASE 0x40086000UL
-#define u_mailbox_BASE 0x40087000UL
-#define u_adc_BASE 0x40089000UL
-#define u_dmic_BASE 0x4008A000UL
-#define u0_usart_BASE 0x4008B000UL
-#define u1_usart_BASE 0x4008C000UL
-#define u0_spi_BASE 0x4008D000UL
-#define u1_spi_BASE 0x4008E000UL
-#define u_hash_BASE 0x4008F000UL
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-
-#define JN518X_SYSCON ((u_syscon_Type *) u_syscon_BASE)
-#define JN518X_OTPC ((u_otpc_Type *) u_otpc_BASE)
-#define JN518X_I2C0 ((u0_i2c_Type *) u0_i2c_BASE)
-#define JN518X_I2C1 ((u1_i2c_Type *) u1_i2c_BASE)
-#define JN518X_I2C2 ((u2_i2c_Type *) u2_i2c_BASE)
-#define JN518X_ISO7816 ((u_iso7816_Type *) u_iso7816_BASE)
-#define JN518X_IRB ((u_cic_irb_Type *) u_cic_irb_BASE)
-#define JN518X_CODEPATCH ((u_codepatch_Type *) u_codepatch_BASE)
-#define JN518X_FLASH ((u_flash_Type *) u_flash_BASE)
-#define JN518X_WWDT ((u_wwdt_Type *) u_wwdt_BASE)
-#define JN518X_RTC ((u_rtc_Type *) u_rtc_BASE)
-#define JN518X_PWM ((u_pwm_Type *) u_pwm_BASE)
-#define JN518X_RNG ((u_rng_Type *) u_rng_BASE)
-#define JN518X_INMUX ((u_inmux_Type *) u_inmux_BASE)
-#define JN518X_IOCON ((u_iocon_Type *) u_iocon_BASE)
-#define JN518X_PININT ((u_pint_Type *) u_pint_BASE)
-#define JN518X_GPIOINT ((u_gint_Type *) u_gint_BASE)
-#define JN518X_PMC ((u_pmc_Type *) u_pmc_BASE)
-#define JN518X_BLEMODEM ((u_ble_dp_top_Type *) u_ble_dp_top_BASE)
-#define JN518X_PVT ((u_pvt_Type *) u_pvt_BASE)
-#define JN518X_ASYSCON ((u_async_syscon_Type *) u_async_syscon_BASE)
-#define JN518X_CTIMER0 ((u0_timer_Type *) u0_timer_BASE)
-#define JN518X_CTIMER1 ((u1_timer_Type *) u1_timer_BASE)
-#define JN518X_GPIO ((u_gpio_Type *) u_gpio_BASE)
-#define JN518X_SPIFI ((u_spifi_Type *) u_spifi_BASE)
-#define JN518X_DMA ((u_dma_Type *) u_dma_BASE)
-#define JN518X_AES256 ((u_aes256_Type *) u_aes256_BASE)
-#define JN518X_MAILBOX ((u_mailbox_Type *) u_mailbox_BASE)
-#define JN518X_ADC ((u_adc_Type *) u_adc_BASE)
-#define JN518X_DMIC ((u_dmic_Type *) u_dmic_BASE)
-#define JN518X_USART0 ((u0_usart_Type *) u0_usart_BASE)
-#define JN518X_USART1 ((u1_usart_Type *) u1_usart_BASE)
-#define JN518X_SPI0 ((u0_spi_Type *) u0_spi_BASE)
-#define JN518X_SPI1 ((u1_spi_Type *) u1_spi_BASE)
-#define JN518X_HASH ((u_hash_Type *) u_hash_BASE)
-
-
-#define u_ble_link__0x400A0000_BASE 0x400A0000UL
-#define u_zb_modem__0x400B0000_BASE 0x400B0000UL
-#define u_zb_mac__0x400B1000_BASE 0x400B1000UL
-#define u_rfp_modem_0x40013000_BASE 0x40013000UL
-
-#define JN518X_BLELNK ((BLE_LINK_IF_Type*) u_ble_link__0x400A0000_BASE)
-#define JN518X_ZBMODEM ((ZB_MODEM_IF_Type*) u_zb_modem__0x400B0000_BASE)
-#define JN518X_ZBMAC ((ZB_MAC_IF_Type*) u_zb_mac__0x400B1000_BASE)
-#define JN518X_RFPMODEM ((t_extapb_regfile*) u_rfp_modem_0x40013000_BASE)
-
-/** @} */ /* End of group Device_Peripheral_Registers */
-/** @} */ /* End of group jn518x */
-/** @} */ /* End of group nxp.com */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* _JN518XHW_H_ */
diff --git a/third_party/nxp/JN5189/Radio_JN5189/Include/jn518x_ble_link.h b/third_party/nxp/JN5189/Radio_JN5189/Include/jn518x_ble_link.h
deleted file mode 100755
index bf49a1f..0000000
--- a/third_party/nxp/JN5189/Radio_JN5189/Include/jn518x_ble_link.h
+++ /dev/null
@@ -1,870 +0,0 @@
-/*
-* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
-* Copyright 2016-2019 NXP
-* All rights reserved.
-*
-* SPDX-License-Identifier: BSD-3-Clause
-*/
-
-#ifndef __BLE_LINK_IF_H__
-#define __BLE_LINK_IF_H__
-
- typedef struct {
- /* Address 0x000 */
- union {
- __IO uint32_t RW_BLE_RWBLECNTL;
-
- struct {
- __IO uint32_t rw_ble_rwblecntl : 32;
- } RW_BLE_RWBLECNTL_b;
- };
- /* Address 0x004 */
- union {
- __IO uint32_t RW_BLE_VERSION;
-
- struct {
- __IO uint32_t rw_ble_version : 32;
- } RW_BLE_VERSION_b;
- };
- /* Address 0x008 */
- union {
- __IO uint32_t RW_BLE_RWBLECONF;
-
- struct {
- __IO uint32_t rw_ble_rwbleconf : 32;
- } RW_BLE_RWBLECONF_b;
- };
- /* Address 0x00C */
- union {
- __IO uint32_t RW_BLE_INTCNTL;
-
- struct {
- __IO uint32_t rw_ble_intcntl : 32;
- } RW_BLE_INTCNTL_b;
- };
- /* Address 0x010 */
- union {
- __IO uint32_t RW_BLE_INTSTAT;
-
- struct {
- __IO uint32_t rw_ble_intstat : 32;
- } RW_BLE_INTSTAT_b;
- };
- /* Address 0x014 */
- union {
- __IO uint32_t RW_BLE_INTRAWSTAT;
-
- struct {
- __IO uint32_t rw_ble_intrawstat : 32;
- } RW_BLE_INTRAWSTAT_b;
- };
- /* Address 0x018 */
- union {
- __IO uint32_t RW_BLE_INTACK;
-
- struct {
- __IO uint32_t rw_ble_intack : 32;
- } RW_BLE_INTACK_b;
- };
- /* Address 0x01C */
- union {
- __IO uint32_t RW_BLE_BASETIMECNT;
-
- struct {
- __IO uint32_t rw_ble_basetimecnt : 32;
- } RW_BLE_BASETIMECNT_b;
- };
- /* Address 0x020 */
- union {
- __IO uint32_t RW_BLE_FINETIMECNT;
-
- struct {
- __IO uint32_t rw_ble_finetimecnt : 32;
- } RW_BLE_FINETIMECNT_b;
- };
- /* Address 0x024 */
- union {
- __IO uint32_t RW_BLE_BDADDRL;
-
- struct {
- __IO uint32_t rw_ble_bdaddrl : 32;
- } RW_BLE_BDADDRL_b;
- };
- /* Address 0x028 */
- union {
- __IO uint32_t RW_BLE_BDADDRU;
-
- struct {
- __IO uint32_t rw_ble_bdaddru : 32;
- } RW_BLE_BDADDRU_b;
- };
- /* Address 0x02C */
- union {
- __IO uint32_t RW_BLE_ET_CURRENTRXDESCPTR;
-
- struct {
- __IO uint32_t rw_ble_et_currentrxdescptr : 32;
- } RW_BLE_ET_CURRENTRXDESCPTR_b;
- };
- /* Address 0x030 */
- union {
- __IO uint32_t RW_BLE_DEEPSLCNTL;
-
- struct {
- __IO uint32_t rw_ble_deepslcntl : 32;
- } RW_BLE_DEEPSLCNTL_b;
- };
- /* Address 0x034 */
- union {
- __IO uint32_t RW_BLE_DEEPSLWKUP;
-
- struct {
- __IO uint32_t rw_ble_deepslwkup : 32;
- } RW_BLE_DEEPSLWKUP_b;
- };
- /* Address 0x038 */
- union {
- __IO uint32_t RW_BLE_DEEPSLSTAT;
-
- struct {
- __IO uint32_t rw_ble_deepslstat : 32;
- } RW_BLE_DEEPSLSTAT_b;
- };
- /* Address 0x03C */
- union {
- __IO uint32_t RW_BLE_ENBPRESET;
-
- struct {
- __IO uint32_t rw_ble_enbpreset : 32;
- } RW_BLE_ENBPRESET_b;
- };
- /* Address 0x040 */
- union {
- __IO uint32_t RW_BLE_FINECNTCORR;
-
- struct {
- __IO uint32_t rw_ble_finecntcorr : 32;
- } RW_BLE_FINECNTCORR_b;
- };
- /* Address 0x044 */
- union {
- __IO uint32_t RW_BLE_BASETIMECNTCORR;
-
- struct {
- __IO uint32_t rw_ble_basetimecntcorr : 32;
- } RW_BLE_BASETIMECNTCORR_b;
- };
- /* Addresses 0x048 - 0x04C */
- __O uint32_t RESERVED048[2];
- /* Address 0x050 */
- union {
- __IO uint32_t RW_BLE_DIAGCNTL;
-
- struct {
- __IO uint32_t rw_ble_diagcntl : 32;
- } RW_BLE_DIAGCNTL_b;
- };
- /* Address 0x054 */
- union {
- __IO uint32_t RW_BLE_DIAGSTAT;
-
- struct {
- __IO uint32_t rw_ble_diagstat : 32;
- } RW_BLE_DIAGSTAT_b;
- };
- /* Address 0x058 */
- union {
- __IO uint32_t RW_BLE_DEBUGADDMAX;
-
- struct {
- __IO uint32_t rw_ble_debugaddmax : 32;
- } RW_BLE_DEBUGADDMAX_b;
- };
- /* Address 0x05C */
- union {
- __IO uint32_t RW_BLE_DEBUGADDMIN;
-
- struct {
- __IO uint32_t rw_ble_debugaddmin : 32;
- } RW_BLE_DEBUGADDMIN_b;
- };
- /* Address 0x060 */
- union {
- __IO uint32_t RW_BLE_ERRORTYPESTAT;
-
- struct {
- __IO uint32_t rw_ble_errortypestat : 32;
- } RW_BLE_ERRORTYPESTAT_b;
- };
- /* Address 0x064 */
- union {
- __IO uint32_t RW_BLE_SWPROFILING;
-
- struct {
- __IO uint32_t rw_ble_swprofiling : 32;
- } RW_BLE_SWPROFILING_b;
- };
- /* Addresses 0x068 - 0x06C */
- __O uint32_t RESERVED068[2];
- /* Address 0x070 */
- union {
- __IO uint32_t RW_BLE_RADIOCNTL0;
-
- struct {
- __IO uint32_t rw_ble_radiocntl0 : 32;
- } RW_BLE_RADIOCNTL0_b;
- };
- /* Address 0x074 */
- union {
- __IO uint32_t RW_BLE_RADIOCNTL1;
-
- struct {
- __IO uint32_t rw_ble_radiocntl1 : 32;
- } RW_BLE_RADIOCNTL1_b;
- };
- /* Address 0x078 */
- union {
- __IO uint32_t RW_BLE_RADIOCNTL2;
-
- struct {
- __IO uint32_t rw_ble_radiocntl2 : 32;
- } RW_BLE_RADIOCNTL2_b;
- };
- /* Address 0x07C */
- union {
- __IO uint32_t RW_BLE_RADIOCNTL3;
-
- struct {
- __IO uint32_t rw_ble_radiocntl3 : 32;
- } RW_BLE_RADIOCNTL3_b;
- };
- /* Address 0x080 */
- union {
- __IO uint32_t RW_BLE_RADIOPWRUPDN;
-
- struct {
- __IO uint32_t rw_ble_radiopwrupdn : 32;
- } RW_BLE_RADIOPWRUPDN_b;
- };
- /* Address 0x084 */
- union {
- __IO uint32_t RW_BLE_SPIPTRCNTL0;
-
- struct {
- __IO uint32_t rw_ble_spiptrcntl0 : 32;
- } RW_BLE_SPIPTRCNTL0_b;
- };
- /* Address 0x088 */
- union {
- __IO uint32_t RW_BLE_SPIPTRCNTL1;
-
- struct {
- __IO uint32_t rw_ble_spiptrcntl1 : 32;
- } RW_BLE_SPIPTRCNTL1_b;
- };
- /* Address 0x08C */
- union {
- __IO uint32_t RW_BLE_SPIPTRCNTL2;
-
- struct {
- __IO uint32_t rw_ble_spiptrcntl2 : 32;
- } RW_BLE_SPIPTRCNTL2_b;
- };
- /* Address 0x090 */
- union {
- __IO uint32_t RW_BLE_ADVCHMAP;
-
- struct {
- __IO uint32_t rw_ble_advchmap : 32;
- } RW_BLE_ADVCHMAP_b;
- };
- /* Addresses 0x094 - 0x09C */
- __O uint32_t RESERVED094[3];
- /* Address 0x0A0 */
- union {
- __IO uint32_t RW_BLE_ADVTIM;
-
- struct {
- __IO uint32_t rw_ble_advtim : 32;
- } RW_BLE_ADVTIM_b;
- };
- /* Address 0x0A4 */
- union {
- __IO uint32_t RW_BLE_ACTSCANSTAT;
-
- struct {
- __IO uint32_t rw_ble_actscanstat : 32;
- } RW_BLE_ACTSCANSTAT_b;
- };
- /* Addresses 0x0A8 - 0x0AC */
- __O uint32_t RESERVED0A8[2];
- /* Address 0x0B0 */
- union {
- __IO uint32_t RW_BLE_WLPUBADDPTR;
-
- struct {
- __IO uint32_t rw_ble_wlpubaddptr : 32;
- } RW_BLE_WLPUBADDPTR_b;
- };
- /* Address 0x0B4 */
- union {
- __IO uint32_t RW_BLE_WLPRIVADDPTR;
-
- struct {
- __IO uint32_t rw_ble_wlprivaddptr : 32;
- } RW_BLE_WLPRIVADDPTR_b;
- };
- /* Address 0x0B8 */
- union {
- __IO uint32_t RW_BLE_WLNBDEV;
-
- struct {
- __IO uint32_t rw_ble_wlnbdev : 32;
- } RW_BLE_WLNBDEV_b;
- };
- /* Address 0x0BC */
- __O uint32_t RESERVED0BC[1];
- /* Address 0x0C0 */
- union {
- __IO uint32_t RW_BLE_AESCNTL;
-
- struct {
- __IO uint32_t rw_ble_aescntl : 32;
- } RW_BLE_AESCNTL_b;
- };
- /* Address 0x0C4 */
- union {
- __IO uint32_t RW_BLE_AESKEY31_0;
-
- struct {
- __IO uint32_t rw_ble_aeskey31_0 : 32;
- } RW_BLE_AESKEY31_0_b;
- };
- /* Address 0x0C8 */
- union {
- __IO uint32_t RW_BLE_AESKEY63_32;
-
- struct {
- __IO uint32_t rw_ble_aeskey63_32 : 32;
- } RW_BLE_AESKEY63_32_b;
- };
- /* Address 0x0CC */
- union {
- __IO uint32_t RW_BLE_AESKEY95_64;
-
- struct {
- __IO uint32_t rw_ble_aeskey95_64 : 32;
- } RW_BLE_AESKEY95_64_b;
- };
- /* Address 0x0D0 */
- union {
- __IO uint32_t RW_BLE_AESKEY127_96;
-
- struct {
- __IO uint32_t rw_ble_aeskey127_96 : 32;
- } RW_BLE_AESKEY127_96_b;
- };
- /* Address 0x0D4 */
- union {
- __IO uint32_t RW_BLE_AESPTR;
-
- struct {
- __IO uint32_t rw_ble_aesptr : 32;
- } RW_BLE_AESPTR_b;
- };
- /* Address 0x0D8 */
- union {
- __IO uint32_t RW_BLE_TXMICVAL;
-
- struct {
- __IO uint32_t rw_ble_txmicval : 32;
- } RW_BLE_TXMICVAL_b;
- };
- /* Address 0x0DC */
- union {
- __IO uint32_t RW_BLE_RXMICVAL;
-
- struct {
- __IO uint32_t rw_ble_rxmicval : 32;
- } RW_BLE_RXMICVAL_b;
- };
- /* Address 0x0E0 */
- union {
- __IO uint32_t RW_BLE_RFTESTCNTL;
-
- struct {
- __IO uint32_t rw_ble_rftestcntl : 32;
- } RW_BLE_RFTESTCNTL_b;
- };
- /* Address 0x0E4 */
- union {
- __IO uint32_t RW_BLE_RFTESTTXSTAT;
-
- struct {
- __IO uint32_t rw_ble_rftesttxstat : 32;
- } RW_BLE_RFTESTTXSTAT_b;
- };
- /* Address 0x0E8 */
- union {
- __IO uint32_t RW_BLE_RFTESTRXSTAT;
-
- struct {
- __IO uint32_t rw_ble_rftestrxstat : 32;
- } RW_BLE_RFTESTRXSTAT_b;
- };
- /* Address 0x0EC */
- __O uint32_t RESERVED0EC[1];
- /* Address 0x0F0 */
- union {
- __IO uint32_t RW_BLE_TIMGENCNTL;
-
- struct {
- __IO uint32_t rw_ble_timgencntl : 32;
- } RW_BLE_TIMGENCNTL_b;
- };
- /* Address 0x0F4 */
- union {
- __IO uint32_t RW_BLE_GROSSTIMTGT;
-
- struct {
- __IO uint32_t rw_ble_grosstimtgt : 32;
- } RW_BLE_GROSSTIMTGT_b;
- };
- /* Address 0x0F8 */
- union {
- __IO uint32_t RW_BLE_FINETIMTGT;
-
- struct {
- __IO uint32_t rw_ble_finetimtgt : 32;
- } RW_BLE_FINETIMTGT_b;
- };
- /* Address 0x0FC */
- __O uint32_t RESERVED0FC[1];
- /* Address 0x100 */
- union {
- __IO uint32_t RW_BLE_COEXIFCNTL0;
-
- struct {
- __IO uint32_t rw_ble_coexifcntl0 : 32;
- } RW_BLE_COEXIFCNTL0_b;
- };
- /* Address 0x104 */
- union {
- __IO uint32_t RW_BLE_COEXIFCNTL1;
-
- struct {
- __IO uint32_t rw_ble_coexifcntl1 : 32;
- } RW_BLE_COEXIFCNTL1_b;
- };
- /* Address 0x108 */
- union {
- __IO uint32_t RW_BLE_COEXIFCNTL2;
-
- struct {
- __IO uint32_t rw_ble_coexifcntl2 : 32;
- } RW_BLE_COEXIFCNTL2_b;
- };
- /* Address 0x10C */
- union {
- __IO uint32_t RW_BLE_BLEMPRIO0;
-
- struct {
- __IO uint32_t rw_ble_blemprio0 : 32;
- } RW_BLE_BLEMPRIO0_b;
- };
- /* Address 0x110 */
- union {
- __IO uint32_t RW_BLE_BLEMPRIO1;
-
- struct {
- __IO uint32_t rw_ble_blemprio1 : 32;
- } RW_BLE_BLEMPRIO1_b;
- };
- /* Addresses 0x114 - 0x11C */
- __O uint32_t RESERVED114[3];
- /* Address 0x120 */
- union {
- __IO uint32_t RW_BLE_RALPTR;
-
- struct {
- __IO uint32_t rw_ble_ralptr : 32;
- } RW_BLE_RALPTR_b;
- };
- /* Address 0x124 */
- union {
- __IO uint32_t RW_BLE_RALNBDEV;
-
- struct {
- __IO uint32_t rw_ble_ralnbdev : 32;
- } RW_BLE_RALNBDEV_b;
- };
- /* Address 0x128 */
- union {
- __IO uint32_t RW_BLE_RAL_LOCAL_RND;
-
- struct {
- __IO uint32_t rw_ble_ral_local_rnd : 32;
- } RW_BLE_RAL_LOCAL_RND_b;
- };
- /* Address 0x12C */
- union {
- __IO uint32_t RW_BLE_RAL_PEER_RND;
-
- struct {
- __IO uint32_t rw_ble_ral_peer_rnd : 32;
- } RW_BLE_RAL_PEER_RND_b;
- };
- /* Address 0x130 */
- union {
- __IO uint32_t RW_BLE_ISOCHANCNTL0;
-
- struct {
- __IO uint32_t rw_ble_isochancntl0 : 32;
- } RW_BLE_ISOCHANCNTL0_b;
- };
- /* Address 0x134 */
- union {
- __IO uint32_t RW_BLE_ISOMUTECNTL0;
-
- struct {
- __IO uint32_t rw_ble_isomutecntl0 : 32;
- } RW_BLE_ISOMUTECNTL0_b;
- };
- /* Address 0x138 */
- union {
- __IO uint32_t RW_BLE_ISOCURRENTTXPTR0;
-
- struct {
- __IO uint32_t rw_ble_isocurrenttxptr0 : 32;
- } RW_BLE_ISOCURRENTTXPTR0_b;
- };
- /* Address 0x13C */
- union {
- __IO uint32_t RW_BLE_ISOCURRENTRXPTR0;
-
- struct {
- __IO uint32_t rw_ble_isocurrentrxptr0 : 32;
- } RW_BLE_ISOCURRENTRXPTR0_b;
- };
- /* Address 0x140 */
- union {
- __IO uint32_t RW_BLE_ISOTRCNL0;
-
- struct {
- __IO uint32_t rw_ble_isotrcnl0 : 32;
- } RW_BLE_ISOTRCNL0_b;
- };
- /* Address 0x144 */
- union {
- __IO uint32_t RW_BLE_ISOEVTCNTLOFFSETL0;
-
- struct {
- __IO uint32_t rw_ble_isoevtcntloffsetl0 : 32;
- } RW_BLE_ISOEVTCNTLOFFSETL0_b;
- };
- /* Address 0x148 */
- union {
- __IO uint32_t RW_BLE_ISOEVTCNTLOFFSETU0;
-
- struct {
- __IO uint32_t rw_ble_isoevtcntloffsetu0 : 32;
- } RW_BLE_ISOEVTCNTLOFFSETU0_b;
- };
- /* Address 0x14C */
- __O uint32_t RESERVED14C[1];
- /* Address 0x150 */
- union {
- __IO uint32_t RW_BLE_ISOCHANCNTL1;
-
- struct {
- __IO uint32_t rw_ble_isochancntl1 : 32;
- } RW_BLE_ISOCHANCNTL1_b;
- };
- /* Address 0x154 */
- union {
- __IO uint32_t RW_BLE_ISOMUTECNTL1;
-
- struct {
- __IO uint32_t rw_ble_isomutecntl1 : 32;
- } RW_BLE_ISOMUTECNTL1_b;
- };
- /* Address 0x158 */
- union {
- __IO uint32_t RW_BLE_ISOCURRENTTXPTR1;
-
- struct {
- __IO uint32_t rw_ble_isocurrenttxptr1 : 32;
- } RW_BLE_ISOCURRENTTXPTR1_b;
- };
- /* Address 0x15C */
- union {
- __IO uint32_t RW_BLE_ISOCURRENTRXPTR1;
-
- struct {
- __IO uint32_t rw_ble_isocurrentrxptr1 : 32;
- } RW_BLE_ISOCURRENTRXPTR1_b;
- };
- /* Address 0x160 */
- union {
- __IO uint32_t RW_BLE_ISOTRCNL1;
-
- struct {
- __IO uint32_t rw_ble_isotrcnl1 : 32;
- } RW_BLE_ISOTRCNL1_b;
- };
- /* Address 0x164 */
- union {
- __IO uint32_t RW_BLE_ISOEVTCNTLOFFSETL1;
-
- struct {
- __IO uint32_t rw_ble_isoevtcntloffsetl1 : 32;
- } RW_BLE_ISOEVTCNTLOFFSETL1_b;
- };
- /* Address 0x168 */
- union {
- __IO uint32_t RW_BLE_ISOEVTCNTLOFFSETU1;
-
- struct {
- __IO uint32_t rw_ble_isoevtcntloffsetu1 : 32;
- } RW_BLE_ISOEVTCNTLOFFSETU1_b;
- };
- /* Address 0x16C */
- __O uint32_t RESERVED16C[1];
- /* Address 0x170 */
- union {
- __IO uint32_t RW_BLE_ISOCHANCNTL2;
-
- struct {
- __IO uint32_t rw_ble_isochancntl2 : 32;
- } RW_BLE_ISOCHANCNTL2_b;
- };
- /* Address 0x174 */
- union {
- __IO uint32_t RW_BLE_ISOMUTECNTL2;
-
- struct {
- __IO uint32_t rw_ble_isomutecntl2 : 32;
- } RW_BLE_ISOMUTECNTL2_b;
- };
- /* Address 0x178 */
- union {
- __IO uint32_t RW_BLE_ISOCURRENTTXPTR2;
-
- struct {
- __IO uint32_t rw_ble_isocurrenttxptr2 : 32;
- } RW_BLE_ISOCURRENTTXPTR2_b;
- };
- /* Address 0x17C */
- union {
- __IO uint32_t RW_BLE_ISOCURRENTRXPTR2;
-
- struct {
- __IO uint32_t rw_ble_isocurrentrxptr2 : 32;
- } RW_BLE_ISOCURRENTRXPTR2_b;
- };
- /* Address 0x180 */
- union {
- __IO uint32_t RW_BLE_ISOTRCNL2;
-
- struct {
- __IO uint32_t rw_ble_isotrcnl2 : 32;
- } RW_BLE_ISOTRCNL2_b;
- };
- /* Address 0x184 */
- union {
- __IO uint32_t RW_BLE_ISOEVTCNTLOFFSETL2;
-
- struct {
- __IO uint32_t rw_ble_isoevtcntloffsetl2 : 32;
- } RW_BLE_ISOEVTCNTLOFFSETL2_b;
- };
- /* Address 0x188 */
- union {
- __IO uint32_t RW_BLE_ISOEVTCNTLOFFSETU2;
-
- struct {
- __IO uint32_t rw_ble_isoevtcntloffsetu2 : 32;
- } RW_BLE_ISOEVTCNTLOFFSETU2_b;
- };
- /* Address 0x18C */
- __O uint32_t RESERVED18C[1];
- /* Address 0x190 */
- union {
- __IO uint32_t RW_BLE_BLEPRIOSCHARB;
-
- struct {
- __IO uint32_t rw_ble_bleprioscharb : 32;
- } RW_BLE_BLEPRIOSCHARB_b;
- };
- /* Addresses 0x194 - 0xFF0 */
- __O uint32_t RESERVED194[920];
- } BLE_LINK_IF_Type;
-
- #define BLELNK_RW_BLE_RWBLECNTL_RW_BLE_RWBLECNTL_Pos 0
- #define BLELNK_RW_BLE_RWBLECNTL_RW_BLE_RWBLECNTL_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_VERSION_RW_BLE_VERSION_Pos 0
- #define BLELNK_RW_BLE_VERSION_RW_BLE_VERSION_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_RWBLECONF_RW_BLE_RWBLECONF_Pos 0
- #define BLELNK_RW_BLE_RWBLECONF_RW_BLE_RWBLECONF_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_INTCNTL_RW_BLE_INTCNTL_Pos 0
- #define BLELNK_RW_BLE_INTCNTL_RW_BLE_INTCNTL_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_INTSTAT_RW_BLE_INTSTAT_Pos 0
- #define BLELNK_RW_BLE_INTSTAT_RW_BLE_INTSTAT_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_INTRAWSTAT_RW_BLE_INTRAWSTAT_Pos 0
- #define BLELNK_RW_BLE_INTRAWSTAT_RW_BLE_INTRAWSTAT_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_INTACK_RW_BLE_INTACK_Pos 0
- #define BLELNK_RW_BLE_INTACK_RW_BLE_INTACK_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_BASETIMECNT_RW_BLE_BASETIMECNT_Pos 0
- #define BLELNK_RW_BLE_BASETIMECNT_RW_BLE_BASETIMECNT_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_FINETIMECNT_RW_BLE_FINETIMECNT_Pos 0
- #define BLELNK_RW_BLE_FINETIMECNT_RW_BLE_FINETIMECNT_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_BDADDRL_RW_BLE_BDADDRL_Pos 0
- #define BLELNK_RW_BLE_BDADDRL_RW_BLE_BDADDRL_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_BDADDRU_RW_BLE_BDADDRU_Pos 0
- #define BLELNK_RW_BLE_BDADDRU_RW_BLE_BDADDRU_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_ET_CURRENTRXDESCPTR_RW_BLE_ET_CURRENTRXDESCPTR_Pos 0
- #define BLELNK_RW_BLE_ET_CURRENTRXDESCPTR_RW_BLE_ET_CURRENTRXDESCPTR_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_DEEPSLCNTL_RW_BLE_DEEPSLCNTL_Pos 0
- #define BLELNK_RW_BLE_DEEPSLCNTL_RW_BLE_DEEPSLCNTL_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_DEEPSLWKUP_RW_BLE_DEEPSLWKUP_Pos 0
- #define BLELNK_RW_BLE_DEEPSLWKUP_RW_BLE_DEEPSLWKUP_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_DEEPSLSTAT_RW_BLE_DEEPSLSTAT_Pos 0
- #define BLELNK_RW_BLE_DEEPSLSTAT_RW_BLE_DEEPSLSTAT_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_ENBPRESET_RW_BLE_ENBPRESET_Pos 0
- #define BLELNK_RW_BLE_ENBPRESET_RW_BLE_ENBPRESET_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_FINECNTCORR_RW_BLE_FINECNTCORR_Pos 0
- #define BLELNK_RW_BLE_FINECNTCORR_RW_BLE_FINECNTCORR_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_BASETIMECNTCORR_RW_BLE_BASETIMECNTCORR_Pos 0
- #define BLELNK_RW_BLE_BASETIMECNTCORR_RW_BLE_BASETIMECNTCORR_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_DIAGCNTL_RW_BLE_DIAGCNTL_Pos 0
- #define BLELNK_RW_BLE_DIAGCNTL_RW_BLE_DIAGCNTL_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_DIAGSTAT_RW_BLE_DIAGSTAT_Pos 0
- #define BLELNK_RW_BLE_DIAGSTAT_RW_BLE_DIAGSTAT_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_DEBUGADDMAX_RW_BLE_DEBUGADDMAX_Pos 0
- #define BLELNK_RW_BLE_DEBUGADDMAX_RW_BLE_DEBUGADDMAX_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_DEBUGADDMIN_RW_BLE_DEBUGADDMIN_Pos 0
- #define BLELNK_RW_BLE_DEBUGADDMIN_RW_BLE_DEBUGADDMIN_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_ERRORTYPESTAT_RW_BLE_ERRORTYPESTAT_Pos 0
- #define BLELNK_RW_BLE_ERRORTYPESTAT_RW_BLE_ERRORTYPESTAT_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_SWPROFILING_RW_BLE_SWPROFILING_Pos 0
- #define BLELNK_RW_BLE_SWPROFILING_RW_BLE_SWPROFILING_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_RADIOCNTL0_RW_BLE_RADIOCNTL0_Pos 0
- #define BLELNK_RW_BLE_RADIOCNTL0_RW_BLE_RADIOCNTL0_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_RADIOCNTL1_RW_BLE_RADIOCNTL1_Pos 0
- #define BLELNK_RW_BLE_RADIOCNTL1_RW_BLE_RADIOCNTL1_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_RADIOCNTL2_RW_BLE_RADIOCNTL2_Pos 0
- #define BLELNK_RW_BLE_RADIOCNTL2_RW_BLE_RADIOCNTL2_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_RADIOCNTL3_RW_BLE_RADIOCNTL3_Pos 0
- #define BLELNK_RW_BLE_RADIOCNTL3_RW_BLE_RADIOCNTL3_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_RADIOPWRUPDN_RW_BLE_RADIOPWRUPDN_Pos 0
- #define BLELNK_RW_BLE_RADIOPWRUPDN_RW_BLE_RADIOPWRUPDN_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_SPIPTRCNTL0_RW_BLE_SPIPTRCNTL0_Pos 0
- #define BLELNK_RW_BLE_SPIPTRCNTL0_RW_BLE_SPIPTRCNTL0_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_SPIPTRCNTL1_RW_BLE_SPIPTRCNTL1_Pos 0
- #define BLELNK_RW_BLE_SPIPTRCNTL1_RW_BLE_SPIPTRCNTL1_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_SPIPTRCNTL2_RW_BLE_SPIPTRCNTL2_Pos 0
- #define BLELNK_RW_BLE_SPIPTRCNTL2_RW_BLE_SPIPTRCNTL2_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_ADVCHMAP_RW_BLE_ADVCHMAP_Pos 0
- #define BLELNK_RW_BLE_ADVCHMAP_RW_BLE_ADVCHMAP_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_ADVTIM_RW_BLE_ADVTIM_Pos 0
- #define BLELNK_RW_BLE_ADVTIM_RW_BLE_ADVTIM_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_ACTSCANSTAT_RW_BLE_ACTSCANSTAT_Pos 0
- #define BLELNK_RW_BLE_ACTSCANSTAT_RW_BLE_ACTSCANSTAT_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_WLPUBADDPTR_RW_BLE_WLPUBADDPTR_Pos 0
- #define BLELNK_RW_BLE_WLPUBADDPTR_RW_BLE_WLPUBADDPTR_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_WLPRIVADDPTR_RW_BLE_WLPRIVADDPTR_Pos 0
- #define BLELNK_RW_BLE_WLPRIVADDPTR_RW_BLE_WLPRIVADDPTR_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_WLNBDEV_RW_BLE_WLNBDEV_Pos 0
- #define BLELNK_RW_BLE_WLNBDEV_RW_BLE_WLNBDEV_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_AESCNTL_RW_BLE_AESCNTL_Pos 0
- #define BLELNK_RW_BLE_AESCNTL_RW_BLE_AESCNTL_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_AESKEY31_0_RW_BLE_AESKEY31_0_Pos 0
- #define BLELNK_RW_BLE_AESKEY31_0_RW_BLE_AESKEY31_0_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_AESKEY63_32_RW_BLE_AESKEY63_32_Pos 0
- #define BLELNK_RW_BLE_AESKEY63_32_RW_BLE_AESKEY63_32_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_AESKEY95_64_RW_BLE_AESKEY95_64_Pos 0
- #define BLELNK_RW_BLE_AESKEY95_64_RW_BLE_AESKEY95_64_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_AESKEY127_96_RW_BLE_AESKEY127_96_Pos 0
- #define BLELNK_RW_BLE_AESKEY127_96_RW_BLE_AESKEY127_96_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_AESPTR_RW_BLE_AESPTR_Pos 0
- #define BLELNK_RW_BLE_AESPTR_RW_BLE_AESPTR_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_TXMICVAL_RW_BLE_TXMICVAL_Pos 0
- #define BLELNK_RW_BLE_TXMICVAL_RW_BLE_TXMICVAL_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_RXMICVAL_RW_BLE_RXMICVAL_Pos 0
- #define BLELNK_RW_BLE_RXMICVAL_RW_BLE_RXMICVAL_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_RFTESTCNTL_RW_BLE_RFTESTCNTL_Pos 0
- #define BLELNK_RW_BLE_RFTESTCNTL_RW_BLE_RFTESTCNTL_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_RFTESTTXSTAT_RW_BLE_RFTESTTXSTAT_Pos 0
- #define BLELNK_RW_BLE_RFTESTTXSTAT_RW_BLE_RFTESTTXSTAT_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_RFTESTRXSTAT_RW_BLE_RFTESTRXSTAT_Pos 0
- #define BLELNK_RW_BLE_RFTESTRXSTAT_RW_BLE_RFTESTRXSTAT_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_TIMGENCNTL_RW_BLE_TIMGENCNTL_Pos 0
- #define BLELNK_RW_BLE_TIMGENCNTL_RW_BLE_TIMGENCNTL_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_GROSSTIMTGT_RW_BLE_GROSSTIMTGT_Pos 0
- #define BLELNK_RW_BLE_GROSSTIMTGT_RW_BLE_GROSSTIMTGT_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_FINETIMTGT_RW_BLE_FINETIMTGT_Pos 0
- #define BLELNK_RW_BLE_FINETIMTGT_RW_BLE_FINETIMTGT_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_COEXIFCNTL0_RW_BLE_COEXIFCNTL0_Pos 0
- #define BLELNK_RW_BLE_COEXIFCNTL0_RW_BLE_COEXIFCNTL0_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_COEXIFCNTL1_RW_BLE_COEXIFCNTL1_Pos 0
- #define BLELNK_RW_BLE_COEXIFCNTL1_RW_BLE_COEXIFCNTL1_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_COEXIFCNTL2_RW_BLE_COEXIFCNTL2_Pos 0
- #define BLELNK_RW_BLE_COEXIFCNTL2_RW_BLE_COEXIFCNTL2_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_BLEMPRIO0_RW_BLE_BLEMPRIO0_Pos 0
- #define BLELNK_RW_BLE_BLEMPRIO0_RW_BLE_BLEMPRIO0_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_BLEMPRIO1_RW_BLE_BLEMPRIO1_Pos 0
- #define BLELNK_RW_BLE_BLEMPRIO1_RW_BLE_BLEMPRIO1_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_RALPTR_RW_BLE_RALPTR_Pos 0
- #define BLELNK_RW_BLE_RALPTR_RW_BLE_RALPTR_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_RALNBDEV_RW_BLE_RALNBDEV_Pos 0
- #define BLELNK_RW_BLE_RALNBDEV_RW_BLE_RALNBDEV_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_RAL_LOCAL_RND_RW_BLE_RAL_LOCAL_RND_Pos 0
- #define BLELNK_RW_BLE_RAL_LOCAL_RND_RW_BLE_RAL_LOCAL_RND_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_RAL_PEER_RND_RW_BLE_RAL_PEER_RND_Pos 0
- #define BLELNK_RW_BLE_RAL_PEER_RND_RW_BLE_RAL_PEER_RND_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_ISOCHANCNTL0_RW_BLE_ISOCHANCNTL0_Pos 0
- #define BLELNK_RW_BLE_ISOCHANCNTL0_RW_BLE_ISOCHANCNTL0_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_ISOMUTECNTL0_RW_BLE_ISOMUTECNTL0_Pos 0
- #define BLELNK_RW_BLE_ISOMUTECNTL0_RW_BLE_ISOMUTECNTL0_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_ISOCURRENTTXPTR0_RW_BLE_ISOCURRENTTXPTR0_Pos 0
- #define BLELNK_RW_BLE_ISOCURRENTTXPTR0_RW_BLE_ISOCURRENTTXPTR0_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_ISOCURRENTRXPTR0_RW_BLE_ISOCURRENTRXPTR0_Pos 0
- #define BLELNK_RW_BLE_ISOCURRENTRXPTR0_RW_BLE_ISOCURRENTRXPTR0_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_ISOTRCNL0_RW_BLE_ISOTRCNL0_Pos 0
- #define BLELNK_RW_BLE_ISOTRCNL0_RW_BLE_ISOTRCNL0_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_ISOEVTCNTLOFFSETL0_RW_BLE_ISOEVTCNTLOFFSETL0_Pos 0
- #define BLELNK_RW_BLE_ISOEVTCNTLOFFSETL0_RW_BLE_ISOEVTCNTLOFFSETL0_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_ISOEVTCNTLOFFSETU0_RW_BLE_ISOEVTCNTLOFFSETU0_Pos 0
- #define BLELNK_RW_BLE_ISOEVTCNTLOFFSETU0_RW_BLE_ISOEVTCNTLOFFSETU0_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_ISOCHANCNTL1_RW_BLE_ISOCHANCNTL1_Pos 0
- #define BLELNK_RW_BLE_ISOCHANCNTL1_RW_BLE_ISOCHANCNTL1_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_ISOMUTECNTL1_RW_BLE_ISOMUTECNTL1_Pos 0
- #define BLELNK_RW_BLE_ISOMUTECNTL1_RW_BLE_ISOMUTECNTL1_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_ISOCURRENTTXPTR1_RW_BLE_ISOCURRENTTXPTR1_Pos 0
- #define BLELNK_RW_BLE_ISOCURRENTTXPTR1_RW_BLE_ISOCURRENTTXPTR1_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_ISOCURRENTRXPTR1_RW_BLE_ISOCURRENTRXPTR1_Pos 0
- #define BLELNK_RW_BLE_ISOCURRENTRXPTR1_RW_BLE_ISOCURRENTRXPTR1_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_ISOTRCNL1_RW_BLE_ISOTRCNL1_Pos 0
- #define BLELNK_RW_BLE_ISOTRCNL1_RW_BLE_ISOTRCNL1_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_ISOEVTCNTLOFFSETL1_RW_BLE_ISOEVTCNTLOFFSETL1_Pos 0
- #define BLELNK_RW_BLE_ISOEVTCNTLOFFSETL1_RW_BLE_ISOEVTCNTLOFFSETL1_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_ISOEVTCNTLOFFSETU1_RW_BLE_ISOEVTCNTLOFFSETU1_Pos 0
- #define BLELNK_RW_BLE_ISOEVTCNTLOFFSETU1_RW_BLE_ISOEVTCNTLOFFSETU1_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_ISOCHANCNTL2_RW_BLE_ISOCHANCNTL2_Pos 0
- #define BLELNK_RW_BLE_ISOCHANCNTL2_RW_BLE_ISOCHANCNTL2_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_ISOMUTECNTL2_RW_BLE_ISOMUTECNTL2_Pos 0
- #define BLELNK_RW_BLE_ISOMUTECNTL2_RW_BLE_ISOMUTECNTL2_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_ISOCURRENTTXPTR2_RW_BLE_ISOCURRENTTXPTR2_Pos 0
- #define BLELNK_RW_BLE_ISOCURRENTTXPTR2_RW_BLE_ISOCURRENTTXPTR2_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_ISOCURRENTRXPTR2_RW_BLE_ISOCURRENTRXPTR2_Pos 0
- #define BLELNK_RW_BLE_ISOCURRENTRXPTR2_RW_BLE_ISOCURRENTRXPTR2_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_ISOTRCNL2_RW_BLE_ISOTRCNL2_Pos 0
- #define BLELNK_RW_BLE_ISOTRCNL2_RW_BLE_ISOTRCNL2_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_ISOEVTCNTLOFFSETL2_RW_BLE_ISOEVTCNTLOFFSETL2_Pos 0
- #define BLELNK_RW_BLE_ISOEVTCNTLOFFSETL2_RW_BLE_ISOEVTCNTLOFFSETL2_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_ISOEVTCNTLOFFSETU2_RW_BLE_ISOEVTCNTLOFFSETU2_Pos 0
- #define BLELNK_RW_BLE_ISOEVTCNTLOFFSETU2_RW_BLE_ISOEVTCNTLOFFSETU2_Msk 0x0ffffffffUL
- #define BLELNK_RW_BLE_BLEPRIOSCHARB_RW_BLE_BLEPRIOSCHARB_Pos 0
- #define BLELNK_RW_BLE_BLEPRIOSCHARB_RW_BLE_BLEPRIOSCHARB_Msk 0x0ffffffffUL
-
-#endif // __BLE_LINK_IF_H__
diff --git a/third_party/nxp/JN5189/Radio_JN5189/Include/jn518x_rfp_modem.h b/third_party/nxp/JN5189/Radio_JN5189/Include/jn518x_rfp_modem.h
deleted file mode 100755
index ebd24bb..0000000
--- a/third_party/nxp/JN5189/Radio_JN5189/Include/jn518x_rfp_modem.h
+++ /dev/null
@@ -1,21556 +0,0 @@
-/*
-* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
-* Copyright 2016-2019 NXP
-* All rights reserved.
-*
-* SPDX-License-Identifier: BSD-3-Clause
-*/
-
-#ifndef JN518X_RFP_MODEM_H
-#define JN518X_RFP_MODEM_H
-
-
-/* extapb module */
-/*-------------------------*/
-
-
-/* regfile module */
-/*-------------------------*/
-
-
-/* test module */
-/*-------------------------*/
-
-
-/* dummy register */
-/*----------------------*/
-/* dummy register: this register can be written/read back to test the SPI interface. WARNING: after power-up, the very first SPI access will be rejected to synchronize the SPI interface! WARNING: through APB and SPI (so not accessible through the PIF, 4 more register are available; set_snap (address 0x1), reset_snap (address 0x2), and status (address 0x3) For snapshotting registers with the snapshot functionality, write the set_snap register followed by a write to the reset_snap register. */
-/* data : dummy */
-#define EXTAPB_REGFILE_TEST_DUMMY_DATA_MASK 0xffff
-#define EXTAPB_REGFILE_TEST_DUMMY_DATA_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int data : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_test_dummy;
-#define EXTAPB_REGFILE_TEST_DUMMY_RST 0x0
-#define EXTAPB_REGFILE_TEST_DUMMY_ADDR 0x4001d000
-
-
-/* version_set_snap register */
-/*----------------------*/
-/* Read access : read version register. Write access : assert snap towards regfile (only applicable for SPI and APB interfaces). */
-/* version : Version of IP2001. */
-#define EXTAPB_REGFILE_TEST_VERSION_SET_SNAP_VERSION_MASK 0xffff
-#define EXTAPB_REGFILE_TEST_VERSION_SET_SNAP_VERSION_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int version : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_test_version_set_snap;
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_TEST_VERSION_SET_SNAP_RST 0x1
-#else
-#define EXTAPB_REGFILE_TEST_VERSION_SET_SNAP_RST 0x2
-#endif
-#define EXTAPB_REGFILE_TEST_VERSION_SET_SNAP_ADDR 0x4001d004
-
-
-/* reset_snap register */
-/*----------------------*/
-/* When this register is written, the snap towards the regfile is de-asserted. Only applicable for SPI and APB interfaces. */
-/* reset_snap : See register description. */
-#define EXTAPB_REGFILE_TEST_RESET_SNAP_RESET_SNAP_MASK 0x0001
-#define EXTAPB_REGFILE_TEST_RESET_SNAP_RESET_SNAP_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int reset_snap : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_test_reset_snap;
-#define EXTAPB_REGFILE_TEST_RESET_SNAP_RST 0x0
-#define EXTAPB_REGFILE_TEST_RESET_SNAP_ADDR 0x4001d008
-
-
-/* status register */
-/*----------------------*/
-/* Access status register. Only applicable for SPI and APB interfaces. */
-/* snack : Value of snack line */
-/* wr_busy : Returns 1 whether a previous write access is still in process by the regfile */
-#define EXTAPB_REGFILE_TEST_STATUS_SNACK_MASK 0x0001
-#define EXTAPB_REGFILE_TEST_STATUS_SNACK_POS 0
-#define EXTAPB_REGFILE_TEST_STATUS_WR_BUSY_MASK 0x0002
-#define EXTAPB_REGFILE_TEST_STATUS_WR_BUSY_POS 1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int snack : 1;
- unsigned int wr_busy : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_test_status;
-#define EXTAPB_REGFILE_TEST_STATUS_RST 0x0
-#define EXTAPB_REGFILE_TEST_STATUS_ADDR 0x4001d00c
-
-
-typedef struct{
- t_extapb_regfile_test_dummy dummy;
- t_extapb_regfile_test_version_set_snap version_set_snap;
- t_extapb_regfile_test_reset_snap reset_snap;
- t_extapb_regfile_test_status status;
-} t_extapb_regfile_test;
-#define EXTAPB_REGFILE_TEST_ADDR 0x4001d000
-#define EXTAPB_REGFILE_TEST ((t_extapb_regfile_test *)EXTAPB_REGFILE_TEST_ADDR)
-
-
-/* clockshop module */
-/*-------------------------*/
-
-
-/* ref_clk_cfg register */
-/*----------------------*/
-/* Reference clock input (16 MHz) configuration */
-/* sel : Selects the source for the 16 MHz reference clock */
-#define EXTAPB_REGFILE_CLOCKSHOP_REF_CLK_CFG_SEL_MASK 0x0003
-#define EXTAPB_REGFILE_CLOCKSHOP_REF_CLK_CFG_SEL_POS 0
-#define EXTAPB_REGFILE_CLOCKSHOP_REF_CLK_CFG_SEL_INTERNAL 0
-#define EXTAPB_REGFILE_CLOCKSHOP_REF_CLK_CFG_SEL_INTERNAL_MASK 0x0
-#define EXTAPB_REGFILE_CLOCKSHOP_REF_CLK_CFG_SEL_EXTERNAL 1
-#define EXTAPB_REGFILE_CLOCKSHOP_REF_CLK_CFG_SEL_EXTERNAL_MASK 0x1
-#define EXTAPB_REGFILE_CLOCKSHOP_REF_CLK_CFG_SEL_RC_0 2
-#define EXTAPB_REGFILE_CLOCKSHOP_REF_CLK_CFG_SEL_RC_0_MASK 0x2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int sel : 2;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_clockshop_ref_clk_cfg;
-#define EXTAPB_REGFILE_CLOCKSHOP_REF_CLK_CFG_RST 0x0
-#define EXTAPB_REGFILE_CLOCKSHOP_REF_CLK_CFG_ADDR 0x4001d014
-
-
-/* tx_clk_cfg register */
-/*----------------------*/
-/* Clockgate control of the tx datapath, overriding the clockgate control of the tmu. */
-/* bb_clk_divisor : */
-/* bb_clk_en : Enables the Tx Datapath BB clock. */
-#define EXTAPB_REGFILE_CLOCKSHOP_TX_CLK_CFG_BB_CLK_DIVISOR_MASK 0x003f
-#define EXTAPB_REGFILE_CLOCKSHOP_TX_CLK_CFG_BB_CLK_DIVISOR_POS 0
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#else
-#define EXTAPB_REGFILE_CLOCKSHOP_TX_CLK_CFG_BB_CLK_DIVISOR_ZB_2 8
-#define EXTAPB_REGFILE_CLOCKSHOP_TX_CLK_CFG_BB_CLK_DIVISOR_ZB_2_MASK 0x8
-#define EXTAPB_REGFILE_CLOCKSHOP_TX_CLK_CFG_BB_CLK_DIVISOR_BLE_1 8
-#define EXTAPB_REGFILE_CLOCKSHOP_TX_CLK_CFG_BB_CLK_DIVISOR_BLE_1_MASK 0x8
-#define EXTAPB_REGFILE_CLOCKSHOP_TX_CLK_CFG_BB_CLK_DIVISOR_BLE_2 8
-#define EXTAPB_REGFILE_CLOCKSHOP_TX_CLK_CFG_BB_CLK_DIVISOR_BLE_2_MASK 0x8
-#endif
-#define EXTAPB_REGFILE_CLOCKSHOP_TX_CLK_CFG_BB_CLK_EN_MASK 0x0100
-#define EXTAPB_REGFILE_CLOCKSHOP_TX_CLK_CFG_BB_CLK_EN_POS 8
-#define EXTAPB_REGFILE_CLOCKSHOP_TX_CLK_CFG_BB_CLK_EN_EN 1
-#define EXTAPB_REGFILE_CLOCKSHOP_TX_CLK_CFG_BB_CLK_EN_EN_MASK 0x100
-#define EXTAPB_REGFILE_CLOCKSHOP_TX_CLK_CFG_BB_CLK_EN_DIS 0
-#define EXTAPB_REGFILE_CLOCKSHOP_TX_CLK_CFG_BB_CLK_EN_DIS_MASK 0x0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int bb_clk_divisor : 6;
- unsigned int : 2;
- unsigned int bb_clk_en : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_clockshop_tx_clk_cfg;
-#define EXTAPB_REGFILE_CLOCKSHOP_TX_CLK_CFG_RST 0x8
-#define EXTAPB_REGFILE_CLOCKSHOP_TX_CLK_CFG_ADDR 0x4001d018
-
-
-/* rx_clk_cfg register */
-/*----------------------*/
-/* Clockgate control of the rx datapath, overriding the clockgate control of the tmu. */
-/* bb_clk_divisor : */
-/* bb_clk_en : Enables the Rx Datapath BB clock. */
-#define EXTAPB_REGFILE_CLOCKSHOP_RX_CLK_CFG_BB_CLK_DIVISOR_MASK 0x003f
-#define EXTAPB_REGFILE_CLOCKSHOP_RX_CLK_CFG_BB_CLK_DIVISOR_POS 0
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#else
-#define EXTAPB_REGFILE_CLOCKSHOP_RX_CLK_CFG_BB_CLK_DIVISOR_ZB_2 8
-#define EXTAPB_REGFILE_CLOCKSHOP_RX_CLK_CFG_BB_CLK_DIVISOR_ZB_2_MASK 0x8
-#define EXTAPB_REGFILE_CLOCKSHOP_RX_CLK_CFG_BB_CLK_DIVISOR_BLE_1 8
-#define EXTAPB_REGFILE_CLOCKSHOP_RX_CLK_CFG_BB_CLK_DIVISOR_BLE_1_MASK 0x8
-#define EXTAPB_REGFILE_CLOCKSHOP_RX_CLK_CFG_BB_CLK_DIVISOR_BLE_2 8
-#define EXTAPB_REGFILE_CLOCKSHOP_RX_CLK_CFG_BB_CLK_DIVISOR_BLE_2_MASK 0x8
-#endif
-#define EXTAPB_REGFILE_CLOCKSHOP_RX_CLK_CFG_BB_CLK_EN_MASK 0x0100
-#define EXTAPB_REGFILE_CLOCKSHOP_RX_CLK_CFG_BB_CLK_EN_POS 8
-#define EXTAPB_REGFILE_CLOCKSHOP_RX_CLK_CFG_BB_CLK_EN_EN 1
-#define EXTAPB_REGFILE_CLOCKSHOP_RX_CLK_CFG_BB_CLK_EN_EN_MASK 0x100
-#define EXTAPB_REGFILE_CLOCKSHOP_RX_CLK_CFG_BB_CLK_EN_DIS 0
-#define EXTAPB_REGFILE_CLOCKSHOP_RX_CLK_CFG_BB_CLK_EN_DIS_MASK 0x0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int bb_clk_divisor : 6;
- unsigned int : 2;
- unsigned int bb_clk_en : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_clockshop_rx_clk_cfg;
-#define EXTAPB_REGFILE_CLOCKSHOP_RX_CLK_CFG_RST 0x8
-#define EXTAPB_REGFILE_CLOCKSHOP_RX_CLK_CFG_ADDR 0x4001d01c
-
-
-/* synth_clk_cfg register */
-/*----------------------*/
-/* Digital synthesizer clock configuration */
-/* sel : Selects the source for the digital synthesizer clock */
-#define EXTAPB_REGFILE_CLOCKSHOP_SYNTH_CLK_CFG_SEL_MASK 0x0003
-#define EXTAPB_REGFILE_CLOCKSHOP_SYNTH_CLK_CFG_SEL_POS 0
-#define EXTAPB_REGFILE_CLOCKSHOP_SYNTH_CLK_CFG_SEL_PLL_DIVN_FO_SDM 0
-#define EXTAPB_REGFILE_CLOCKSHOP_SYNTH_CLK_CFG_SEL_PLL_DIVN_FO_SDM_MASK 0x0
-#define EXTAPB_REGFILE_CLOCKSHOP_SYNTH_CLK_CFG_SEL_REF_CLK 1
-#define EXTAPB_REGFILE_CLOCKSHOP_SYNTH_CLK_CFG_SEL_REF_CLK_MASK 0x1
-#define EXTAPB_REGFILE_CLOCKSHOP_SYNTH_CLK_CFG_SEL_EXTERNAL 2
-#define EXTAPB_REGFILE_CLOCKSHOP_SYNTH_CLK_CFG_SEL_EXTERNAL_MASK 0x2
-#define EXTAPB_REGFILE_CLOCKSHOP_SYNTH_CLK_CFG_SEL_RC_0 3
-#define EXTAPB_REGFILE_CLOCKSHOP_SYNTH_CLK_CFG_SEL_RC_0_MASK 0x3
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int sel : 2;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_clockshop_synth_clk_cfg;
-#define EXTAPB_REGFILE_CLOCKSHOP_SYNTH_CLK_CFG_RST 0x0
-#define EXTAPB_REGFILE_CLOCKSHOP_SYNTH_CLK_CFG_ADDR 0x4001d020
-
-
-typedef struct{
- t_extapb_regfile_clockshop_ref_clk_cfg ref_clk_cfg;
- t_extapb_regfile_clockshop_tx_clk_cfg tx_clk_cfg;
- t_extapb_regfile_clockshop_rx_clk_cfg rx_clk_cfg;
- t_extapb_regfile_clockshop_synth_clk_cfg synth_clk_cfg;
-} t_extapb_regfile_clockshop;
-#define EXTAPB_REGFILE_CLOCKSHOP_ADDR 0x4001d014
-#define EXTAPB_REGFILE_CLOCKSHOP ((t_extapb_regfile_clockshop *)EXTAPB_REGFILE_CLOCKSHOP_ADDR)
-
-
-/* ip2001_global module */
-/*-------------------------*/
-
-
-/* cfg register */
-/*----------------------*/
-/* IP2001 global configuration */
-/* spi_sel : SPI interface selection */
-/* ant_switch : External antenna switch */
-#define EXTAPB_REGFILE_IP2001_GLOBAL_CFG_SPI_SEL_MASK 0x0001
-#define EXTAPB_REGFILE_IP2001_GLOBAL_CFG_SPI_SEL_POS 0
-#define EXTAPB_REGFILE_IP2001_GLOBAL_CFG_SPI_SEL_DEDICATED_IF 0
-#define EXTAPB_REGFILE_IP2001_GLOBAL_CFG_SPI_SEL_DEDICATED_IF_MASK 0x0
-#define EXTAPB_REGFILE_IP2001_GLOBAL_CFG_SPI_SEL_SWM_IF 1
-#define EXTAPB_REGFILE_IP2001_GLOBAL_CFG_SPI_SEL_SWM_IF_MASK 0x1
-#define EXTAPB_REGFILE_IP2001_GLOBAL_CFG_ANT_SWITCH_MASK 0x0004
-#define EXTAPB_REGFILE_IP2001_GLOBAL_CFG_ANT_SWITCH_POS 2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int spi_sel : 1;
- unsigned int : 1;
- unsigned int ant_switch : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_ip2001_global_cfg;
-#define EXTAPB_REGFILE_IP2001_GLOBAL_CFG_RST 0x0
-#define EXTAPB_REGFILE_IP2001_GLOBAL_CFG_ADDR 0x4001d030
-
-
-typedef struct{
- unsigned int reserved0[2];
- t_extapb_regfile_ip2001_global_cfg cfg;
-} t_extapb_regfile_ip2001_global;
-#define EXTAPB_REGFILE_IP2001_GLOBAL_ADDR 0x4001d028
-#define EXTAPB_REGFILE_IP2001_GLOBAL ((t_extapb_regfile_ip2001_global *)EXTAPB_REGFILE_IP2001_GLOBAL_ADDR)
-
-
-/* rx_datapath module */
-/*-------------------------*/
-
-
-/* global register */
-/*----------------------*/
-/* Global configuration of the Rx Datapath */
-/* rx_bank : Bank selection of Rx Datapath */
-/* adc_sample_edge : Sampling edge for the data coming from the ADC. */
-/* adc_en : Enable bit for the ADC-Rx Datapath interface. */
-/* iq_swap_en : enable for IQ swapping at input of DC offset */
-/* rx_data_range_sel : Data range selection towards ZB modem. 0 for the 10 middle bits, 1 for the 10 LSBs */
-/* adc_2s_complement_en : When 1, data from ADC is considered as 2s complement format. */
-#define EXTAPB_REGFILE_RX_DP_GLOBAL_RX_BANK_MASK 0x0003
-#define EXTAPB_REGFILE_RX_DP_GLOBAL_RX_BANK_POS 0
-#define EXTAPB_REGFILE_RX_DP_GLOBAL_ADC_SAMPLE_EDGE_MASK 0x0004
-#define EXTAPB_REGFILE_RX_DP_GLOBAL_ADC_SAMPLE_EDGE_POS 2
-#define EXTAPB_REGFILE_RX_DP_GLOBAL_ADC_SAMPLE_EDGE_RISING_EDGE 0
-#define EXTAPB_REGFILE_RX_DP_GLOBAL_ADC_SAMPLE_EDGE_RISING_EDGE_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_GLOBAL_ADC_SAMPLE_EDGE_FALLING_EDGE 1
-#define EXTAPB_REGFILE_RX_DP_GLOBAL_ADC_SAMPLE_EDGE_FALLING_EDGE_MASK 0x4
-#define EXTAPB_REGFILE_RX_DP_GLOBAL_ADC_EN_MASK 0x0008
-#define EXTAPB_REGFILE_RX_DP_GLOBAL_ADC_EN_POS 3
-#define EXTAPB_REGFILE_RX_DP_GLOBAL_ADC_EN_DIS 0
-#define EXTAPB_REGFILE_RX_DP_GLOBAL_ADC_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_GLOBAL_ADC_EN_EN 1
-#define EXTAPB_REGFILE_RX_DP_GLOBAL_ADC_EN_EN_MASK 0x8
-#define EXTAPB_REGFILE_RX_DP_GLOBAL_IQ_SWAP_EN_MASK 0x0010
-#define EXTAPB_REGFILE_RX_DP_GLOBAL_IQ_SWAP_EN_POS 4
-#define EXTAPB_REGFILE_RX_DP_GLOBAL_IQ_SWAP_EN_DIS 0
-#define EXTAPB_REGFILE_RX_DP_GLOBAL_IQ_SWAP_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_GLOBAL_IQ_SWAP_EN_EN 1
-#define EXTAPB_REGFILE_RX_DP_GLOBAL_IQ_SWAP_EN_EN_MASK 0x10
-#define EXTAPB_REGFILE_RX_DP_GLOBAL_RX_DATA_RANGE_SEL_MASK 0x0060
-#define EXTAPB_REGFILE_RX_DP_GLOBAL_RX_DATA_RANGE_SEL_POS 5
-#define EXTAPB_REGFILE_RX_DP_GLOBAL_ADC_2S_COMPLEMENT_EN_MASK 0x0080
-#define EXTAPB_REGFILE_RX_DP_GLOBAL_ADC_2S_COMPLEMENT_EN_POS 7
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_bank : 2;
- unsigned int adc_sample_edge : 1;
- unsigned int adc_en : 1;
- unsigned int iq_swap_en : 1;
- unsigned int rx_data_range_sel : 2;
- unsigned int adc_2s_complement_en : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_global;
-#define EXTAPB_REGFILE_RX_DP_GLOBAL_RST 0xa0
-#define EXTAPB_REGFILE_RX_DP_GLOBAL_ADDR 0x4001d040
-
-
-/* cfg register */
-/*----------------------*/
-/* Group of context configuration settings (part 1) (Stored in configuration bank) */
-/* dec_en : Enable bit for the decimation filter. */
-/* link_active : Link or scan mode configuration bit. */
-#define EXTAPB_REGFILE_RX_DP_CFG_DEC_EN_MASK 0x0001
-#define EXTAPB_REGFILE_RX_DP_CFG_DEC_EN_POS 0
-#define EXTAPB_REGFILE_RX_DP_CFG_DEC_EN_EN 1
-#define EXTAPB_REGFILE_RX_DP_CFG_DEC_EN_EN_MASK 0x1
-#define EXTAPB_REGFILE_RX_DP_CFG_DEC_EN_DIS 0
-#define EXTAPB_REGFILE_RX_DP_CFG_DEC_EN_DIS_MASK 0x0
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_CFG_DEC_EN_BT_LE_1 1
-#define EXTAPB_REGFILE_RX_DP_CFG_DEC_EN_BT_LE_1_MASK 0x1
-#define EXTAPB_REGFILE_RX_DP_CFG_DEC_EN_BT_LE_2 0
-#define EXTAPB_REGFILE_RX_DP_CFG_DEC_EN_BT_LE_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_CFG_DEC_EN_NORDIC_250 1
-#define EXTAPB_REGFILE_RX_DP_CFG_DEC_EN_NORDIC_250_MASK 0x1
-#define EXTAPB_REGFILE_RX_DP_CFG_DEC_EN_NORDIC_2 0
-#define EXTAPB_REGFILE_RX_DP_CFG_DEC_EN_NORDIC_2_MASK 0x0
-#else
-#define EXTAPB_REGFILE_RX_DP_CFG_DEC_EN_ZB_2 1
-#define EXTAPB_REGFILE_RX_DP_CFG_DEC_EN_ZB_2_MASK 0x1
-#define EXTAPB_REGFILE_RX_DP_CFG_DEC_EN_BLE_1 1
-#define EXTAPB_REGFILE_RX_DP_CFG_DEC_EN_BLE_1_MASK 0x1
-#define EXTAPB_REGFILE_RX_DP_CFG_DEC_EN_BLE_2 1
-#define EXTAPB_REGFILE_RX_DP_CFG_DEC_EN_BLE_2_MASK 0x1
-#endif
-
-#define EXTAPB_REGFILE_RX_DP_CFG_LINK_ACTIVE_MASK 0x0002
-#define EXTAPB_REGFILE_RX_DP_CFG_LINK_ACTIVE_POS 1
-#define EXTAPB_REGFILE_RX_DP_CFG_LINK_ACTIVE_INACTIVE 0
-#define EXTAPB_REGFILE_RX_DP_CFG_LINK_ACTIVE_INACTIVE_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_CFG_LINK_ACTIVE_ACTIVE 1
-#define EXTAPB_REGFILE_RX_DP_CFG_LINK_ACTIVE_ACTIVE_MASK 0x2
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#else
-#define EXTAPB_REGFILE_RX_DP_CFG_LINK_ACTIVE_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_CFG_LINK_ACTIVE_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_CFG_LINK_ACTIVE_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_CFG_LINK_ACTIVE_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_CFG_LINK_ACTIVE_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_CFG_LINK_ACTIVE_BLE_2_MASK 0x0
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int dec_en : 1;
- unsigned int link_active : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_cfg;
-#define EXTAPB_REGFILE_RX_DP_CFG_RST 0x1
-#define EXTAPB_REGFILE_RX_DP_CFG_ADDR 0x4001d044
-
-
-/* bank_cfg1 register */
-/*----------------------*/
-/* Group of context configuration settings (part 2) (Stored in configuration bank) */
-/* enable_min_ifamp_gain_settings : TBD */
-/* enable_min_aaf_gain_settings : TBD */
-/* symbols_per_bit : Define whether nb of symbols per bit is 1 or 4 */
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_ENABLE_MIN_IFAMP_GAIN_SETTINGS_MASK 0x0001
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_ENABLE_MIN_IFAMP_GAIN_SETTINGS_POS 0
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#else
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_ENABLE_MIN_IFAMP_GAIN_SETTINGS_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_ENABLE_MIN_IFAMP_GAIN_SETTINGS_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_ENABLE_MIN_IFAMP_GAIN_SETTINGS_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_ENABLE_MIN_IFAMP_GAIN_SETTINGS_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_ENABLE_MIN_IFAMP_GAIN_SETTINGS_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_ENABLE_MIN_IFAMP_GAIN_SETTINGS_BLE_2_MASK 0x0
-#endif
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_ENABLE_MIN_AAF_GAIN_SETTINGS_MASK 0x0002
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_ENABLE_MIN_AAF_GAIN_SETTINGS_POS 1
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#else
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_ENABLE_MIN_AAF_GAIN_SETTINGS_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_ENABLE_MIN_AAF_GAIN_SETTINGS_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_ENABLE_MIN_AAF_GAIN_SETTINGS_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_ENABLE_MIN_AAF_GAIN_SETTINGS_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_ENABLE_MIN_AAF_GAIN_SETTINGS_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_ENABLE_MIN_AAF_GAIN_SETTINGS_BLE_2_MASK 0x0
-#endif
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_SYMBOLS_PER_BIT_MASK 0x0004
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_SYMBOLS_PER_BIT_POS 2
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_SYMBOLS_PER_BIT_ONE 1
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_SYMBOLS_PER_BIT_ONE_MASK 0x4
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_SYMBOLS_PER_BIT_FOUR 0
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_SYMBOLS_PER_BIT_FOUR_MASK 0x0
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_SYMBOLS_PER_BIT_BT_LE_1 1
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_SYMBOLS_PER_BIT_BT_LE_1_MASK 0x4
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_SYMBOLS_PER_BIT_BT_LE_2 1
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_SYMBOLS_PER_BIT_BT_LE_2_MASK 0x4
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_SYMBOLS_PER_BIT_NORDIC_250 0
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_SYMBOLS_PER_BIT_NORDIC_250_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_SYMBOLS_PER_BIT_NORDIC_2 1
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_SYMBOLS_PER_BIT_NORDIC_2_MASK 0x4
-#else
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_SYMBOLS_PER_BIT_ZB_2 1
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_SYMBOLS_PER_BIT_ZB_2_MASK 0x4
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_SYMBOLS_PER_BIT_BLE_1 1
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_SYMBOLS_PER_BIT_BLE_1_MASK 0x4
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_SYMBOLS_PER_BIT_BLE_2 1
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_SYMBOLS_PER_BIT_BLE_2_MASK 0x4
-#endif
-
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int enable_min_ifamp_gain_settings : 1;
- unsigned int enable_min_aaf_gain_settings : 1;
- unsigned int symbols_per_bit : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_bank_cfg1;
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_RST 0x4
-#define EXTAPB_REGFILE_RX_DP_BANK_CFG1_ADDR 0x4001d048
-
-
-/* dc_offset_cfg register */
-/*----------------------*/
-/* DC offset compensation configuration (Stored in configuration bank) */
-/* dc_comp_en : DC offset compensation enable */
-/* dc_comp_filter_en : DC offset compensation filter enable */
-/* alpha : alpha towards the DC offset compensation module. */
-/* dc_comp_filter_flush_en : When 1, the DC compensation HP/LP filter is flushed upon a change of the gain setting. */
-/* dc_offset_upd_on_eop_en : When 1, the DC offset compensation value is updated based on the output of the DC offset compensation LP filter output at the end of the packet. */
-/* dc_offset_init_decfilter_en : Configures if the Decimation filter must be initialized (at start of packet) with the DC offset value */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_EN_MASK 0x0001
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_EN_POS 0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_EN_DIS 0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_EN_EN 1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_EN_EN_MASK 0x1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_EN_MASK 0x0002
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_EN_POS 1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_EN_DIS 0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_EN_EN 1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_EN_EN_MASK 0x2
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_ALPHA_MASK 0x007c
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_ALPHA_POS 2
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_FLUSH_EN_MASK 0x0080
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_FLUSH_EN_POS 7
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_FLUSH_EN_DIS 0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_FLUSH_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_FLUSH_EN_EN 1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_FLUSH_EN_EN_MASK 0x80
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_UPD_ON_EOP_EN_MASK 0x0100
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_UPD_ON_EOP_EN_POS 8
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_UPD_ON_EOP_EN_DIS 0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_UPD_ON_EOP_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_UPD_ON_EOP_EN_EN 1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_UPD_ON_EOP_EN_EN_MASK 0x100
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_INIT_DECFILTER_EN_MASK 0x0200
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_INIT_DECFILTER_EN_POS 9
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_INIT_DECFILTER_EN_DIS 0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_INIT_DECFILTER_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_INIT_DECFILTER_EN_EN 1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_INIT_DECFILTER_EN_EN_MASK 0x200
-#else
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_EN_MASK 0x0001
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_EN_POS 0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_EN_DIS 0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_EN_EN 1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_EN_EN_MASK 0x1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_EN_ZB_2 1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_EN_ZB_2_MASK 0x1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_EN_BLE_1 1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_EN_BLE_1_MASK 0x1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_EN_BLE_2 1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_EN_BLE_2_MASK 0x1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_EN_MASK 0x0002
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_EN_POS 1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_EN_DIS 0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_EN_EN 1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_EN_EN_MASK 0x2
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_EN_ZB_2 1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_EN_ZB_2_MASK 0x2
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_EN_BLE_1 1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_EN_BLE_1_MASK 0x2
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_EN_BLE_2 1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_EN_BLE_2_MASK 0x2
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_ALPHA_MASK 0x007c
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_ALPHA_POS 2
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_ALPHA_ZB_2 4
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_ALPHA_ZB_2_MASK 0x10
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_ALPHA_BLE_1 4
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_ALPHA_BLE_1_MASK 0x10
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_ALPHA_BLE_2 4
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_ALPHA_BLE_2_MASK 0x10
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_FLUSH_EN_MASK 0x0080
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_FLUSH_EN_POS 7
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_FLUSH_EN_DIS 0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_FLUSH_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_FLUSH_EN_EN 1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_FLUSH_EN_EN_MASK 0x80
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_FLUSH_EN_ZB_2 1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_FLUSH_EN_ZB_2_MASK 0x80
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_FLUSH_EN_BLE_1 1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_FLUSH_EN_BLE_1_MASK 0x80
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_FLUSH_EN_BLE_2 1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_COMP_FILTER_FLUSH_EN_BLE_2_MASK 0x80
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_UPD_ON_EOP_EN_MASK 0x0100
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_UPD_ON_EOP_EN_POS 8
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_UPD_ON_EOP_EN_DIS 0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_UPD_ON_EOP_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_UPD_ON_EOP_EN_EN 1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_UPD_ON_EOP_EN_EN_MASK 0x100
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_UPD_ON_EOP_EN_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_UPD_ON_EOP_EN_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_UPD_ON_EOP_EN_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_UPD_ON_EOP_EN_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_UPD_ON_EOP_EN_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_UPD_ON_EOP_EN_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_INIT_DECFILTER_EN_MASK 0x0200
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_INIT_DECFILTER_EN_POS 9
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_INIT_DECFILTER_EN_DIS 0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_INIT_DECFILTER_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_INIT_DECFILTER_EN_EN 1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_INIT_DECFILTER_EN_EN_MASK 0x200
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_INIT_DECFILTER_EN_ZB_2 1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_INIT_DECFILTER_EN_ZB_2_MASK 0x200
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_INIT_DECFILTER_EN_BLE_1 1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_INIT_DECFILTER_EN_BLE_1_MASK 0x200
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_INIT_DECFILTER_EN_BLE_2 1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_DC_OFFSET_INIT_DECFILTER_EN_BLE_2_MASK 0x200
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int dc_comp_en : 1;
- unsigned int dc_comp_filter_en : 1;
- unsigned int alpha : 5;
- unsigned int dc_comp_filter_flush_en : 1;
- unsigned int dc_offset_upd_on_eop_en : 1;
- unsigned int dc_offset_init_decfilter_en : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_dc_offset_cfg;
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_RST 0x293
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_CFG_ADDR 0x4001d04c
-
-
-/* clip_det_1_lev_sel register */
-/*----------------------*/
-/* Clip detector 1 (RF): detection level select */
-/* clip_det_1_lev_sel : Clip detector 1 (RF): detection level select */
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_LEV_SEL_CLIP_DET_1_LEV_SEL_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_LEV_SEL_CLIP_DET_1_LEV_SEL_POS 0
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_LEV_SEL_CLIP_DET_1_LEV_SEL_HUNDRED 0
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_LEV_SEL_CLIP_DET_1_LEV_SEL_HUNDRED_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_LEV_SEL_CLIP_DET_1_LEV_SEL_HUNDRED_FIFTY 1
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_LEV_SEL_CLIP_DET_1_LEV_SEL_HUNDRED_FIFTY_MASK 0x1
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_LEV_SEL_CLIP_DET_1_LEV_SEL_TWO_HUNDRED 2
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_LEV_SEL_CLIP_DET_1_LEV_SEL_TWO_HUNDRED_MASK 0x2
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_LEV_SEL_CLIP_DET_1_LEV_SEL_TWO_HUNDRED_FIFTY 3
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_LEV_SEL_CLIP_DET_1_LEV_SEL_TWO_HUNDRED_FIFTY_MASK 0x3
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int clip_det_1_lev_sel : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_clip_det_1_lev_sel;
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_LEV_SEL_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_LEV_SEL_ADDR 0x4001d050
-
-
-/* clip_det_1_ana_agc_bypass register */
-/*----------------------*/
-/* clip detector 1 controls in case of analogue agc bypass */
-/* clip_det_1_reset_ana_agc_bypass : clip detector 1 reset control in case of analogue agc bypass */
-/* clip_det_1_en_ana_agc_bypass : clip detector 1 enable control in case of analogue agc bypass */
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_ANA_AGC_BYPASS_CLIP_DET_1_RESET_ANA_AGC_BYPASS_MASK 0x0001
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_ANA_AGC_BYPASS_CLIP_DET_1_RESET_ANA_AGC_BYPASS_POS 0
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_ANA_AGC_BYPASS_CLIP_DET_1_EN_ANA_AGC_BYPASS_MASK 0x0002
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_ANA_AGC_BYPASS_CLIP_DET_1_EN_ANA_AGC_BYPASS_POS 1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int clip_det_1_reset_ana_agc_bypass : 1;
- unsigned int clip_det_1_en_ana_agc_bypass : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_clip_det_1_ana_agc_bypass;
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_ANA_AGC_BYPASS_RST 0x1
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_ANA_AGC_BYPASS_ADDR 0x4001d054
-
-
-/* clip_det_1_timeout_up register */
-/*----------------------*/
-/* Timeout following a clipping detection or gain increase during which no attempt can be made to increase the gain again */
-/* clip_det_1_timeout_up : Timeout following a clipping detection or gain increase during which no attempt can be made to increase the gain again */
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_TIMEOUT_UP_CLIP_DET_1_TIMEOUT_UP_MASK 0xffff
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_TIMEOUT_UP_CLIP_DET_1_TIMEOUT_UP_POS 0
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#else
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_TIMEOUT_UP_CLIP_DET_1_TIMEOUT_UP_ZB_2 768
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_TIMEOUT_UP_CLIP_DET_1_TIMEOUT_UP_ZB_2_MASK 0x300
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_TIMEOUT_UP_CLIP_DET_1_TIMEOUT_UP_BLE_1 768
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_TIMEOUT_UP_CLIP_DET_1_TIMEOUT_UP_BLE_1_MASK 0x300
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_TIMEOUT_UP_CLIP_DET_1_TIMEOUT_UP_BLE_2 768
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_TIMEOUT_UP_CLIP_DET_1_TIMEOUT_UP_BLE_2_MASK 0x300
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int clip_det_1_timeout_up : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_clip_det_1_timeout_up;
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_TIMEOUT_UP_RST 0x300
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_TIMEOUT_UP_ADDR 0x4001d058
-
-
-/* lna_setting register */
-/*----------------------*/
-/* Additional gain in case of low gain setting <4,2> */
-/* lna_offset_gain_db : Additional gain in case of low gain setting <4,2> */
-/* lna_iadj_set : Additional gain in case of low gain setting <4,2> */
-#define EXTAPB_REGFILE_RX_DP_LNA_SETTING_LNA_OFFSET_GAIN_DB_MASK 0x007f
-#define EXTAPB_REGFILE_RX_DP_LNA_SETTING_LNA_OFFSET_GAIN_DB_POS 0
-#define EXTAPB_REGFILE_RX_DP_LNA_SETTING_LNA_IADJ_SET_MASK 0x0380
-#define EXTAPB_REGFILE_RX_DP_LNA_SETTING_LNA_IADJ_SET_POS 7
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int lna_offset_gain_db : 7;
- unsigned int lna_iadj_set : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_lna_setting;
-#define EXTAPB_REGFILE_RX_DP_LNA_SETTING_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_LNA_SETTING_ADDR 0x4001d060
-
-
-/* lna_gain_setting_ana_agc_bypass register */
-/*----------------------*/
-/* lna gain in case agc is bypassed */
-/* lna_gain_setting_ana_agc_bypass : lna gain in case agc is bypassed */
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_SETTING_ANA_AGC_BYPASS_LNA_GAIN_SETTING_ANA_AGC_BYPASS_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_SETTING_ANA_AGC_BYPASS_LNA_GAIN_SETTING_ANA_AGC_BYPASS_POS 0
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_SETTING_ANA_AGC_BYPASS_LNA_GAIN_SETTING_ANA_AGC_BYPASS_M21_DB 0
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_SETTING_ANA_AGC_BYPASS_LNA_GAIN_SETTING_ANA_AGC_BYPASS_M21_DB_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_SETTING_ANA_AGC_BYPASS_LNA_GAIN_SETTING_ANA_AGC_BYPASS_M9_DB 1
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_SETTING_ANA_AGC_BYPASS_LNA_GAIN_SETTING_ANA_AGC_BYPASS_M9_DB_MASK 0x1
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_SETTING_ANA_AGC_BYPASS_LNA_GAIN_SETTING_ANA_AGC_BYPASS_M3_DB 2
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_SETTING_ANA_AGC_BYPASS_LNA_GAIN_SETTING_ANA_AGC_BYPASS_M3_DB_MASK 0x2
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_SETTING_ANA_AGC_BYPASS_LNA_GAIN_SETTING_ANA_AGC_BYPASS_3_DB 3
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_SETTING_ANA_AGC_BYPASS_LNA_GAIN_SETTING_ANA_AGC_BYPASS_3_DB_MASK 0x3
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_SETTING_ANA_AGC_BYPASS_LNA_GAIN_SETTING_ANA_AGC_BYPASS_15_DB 4
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_SETTING_ANA_AGC_BYPASS_LNA_GAIN_SETTING_ANA_AGC_BYPASS_15_DB_MASK 0x4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int lna_gain_setting_ana_agc_bypass : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_lna_gain_setting_ana_agc_bypass;
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_SETTING_ANA_AGC_BYPASS_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_SETTING_ANA_AGC_BYPASS_ADDR 0x4001d064
-
-
-/* clip_det_2_lev_sel register */
-/*----------------------*/
-/* Clip detector 2 (IF): detection level select */
-/* clip_det_2_lev_sel : Clip detector 2 (IF): detection level select */
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_LEV_SEL_CLIP_DET_2_LEV_SEL_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_LEV_SEL_CLIP_DET_2_LEV_SEL_POS 0
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_LEV_SEL_CLIP_DET_2_LEV_SEL_HUNDRED_FIFTY 0
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_LEV_SEL_CLIP_DET_2_LEV_SEL_HUNDRED_FIFTY_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_LEV_SEL_CLIP_DET_2_LEV_SEL_HUNDRED_SEVENTY_FIVE 1
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_LEV_SEL_CLIP_DET_2_LEV_SEL_HUNDRED_SEVENTY_FIVE_MASK 0x1
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_LEV_SEL_CLIP_DET_2_LEV_SEL_TWO_HUNDRED 2
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_LEV_SEL_CLIP_DET_2_LEV_SEL_TWO_HUNDRED_MASK 0x2
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_LEV_SEL_CLIP_DET_2_LEV_SEL_TWO_HUNDRED_TWENTY_FIVE 3
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_LEV_SEL_CLIP_DET_2_LEV_SEL_TWO_HUNDRED_TWENTY_FIVE_MASK 0x3
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_LEV_SEL_CLIP_DET_2_LEV_SEL_TWO_HUNDRED_FIFTY 4
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_LEV_SEL_CLIP_DET_2_LEV_SEL_TWO_HUNDRED_FIFTY_MASK 0x4
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_LEV_SEL_CLIP_DET_2_LEV_SEL_TWO_HUNDRED_SEVENTY_FIVE 5
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_LEV_SEL_CLIP_DET_2_LEV_SEL_TWO_HUNDRED_SEVENTY_FIVE_MASK 0x5
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_LEV_SEL_CLIP_DET_2_LEV_SEL_THREE_HUNDRED 6
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_LEV_SEL_CLIP_DET_2_LEV_SEL_THREE_HUNDRED_MASK 0x6
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_LEV_SEL_CLIP_DET_2_LEV_SEL_THREE_HUNDRED_TWENTY_FIVE 7
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_LEV_SEL_CLIP_DET_2_LEV_SEL_THREE_HUNDRED_TWENTY_FIVE_MASK 0x7
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int clip_det_2_lev_sel : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_clip_det_2_lev_sel;
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_LEV_SEL_RST 0x3
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_LEV_SEL_ADDR 0x4001d068
-
-
-/* clip_det_2_ana_agc_bypass register */
-/*----------------------*/
-/* clip detector 1 controls in case of analogue agc bypass */
-/* clip_det_2_reset_ana_agc_bypass : clip detector 2 reset control in case of analogue agc bypass */
-/* clip_det_2_en_ana_agc_bypass : clip detector 2 enable control in case of analogue agc bypass */
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_ANA_AGC_BYPASS_CLIP_DET_2_RESET_ANA_AGC_BYPASS_MASK 0x0001
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_ANA_AGC_BYPASS_CLIP_DET_2_RESET_ANA_AGC_BYPASS_POS 0
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_ANA_AGC_BYPASS_CLIP_DET_2_EN_ANA_AGC_BYPASS_MASK 0x0002
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_ANA_AGC_BYPASS_CLIP_DET_2_EN_ANA_AGC_BYPASS_POS 1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int clip_det_2_reset_ana_agc_bypass : 1;
- unsigned int clip_det_2_en_ana_agc_bypass : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_clip_det_2_ana_agc_bypass;
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_ANA_AGC_BYPASS_RST 0x1
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_ANA_AGC_BYPASS_ADDR 0x4001d06c
-
-
-/* clip_det_2_bucket_decr register */
-/*----------------------*/
-/* Leaky bucket decrement (clip detector 2) */
-/* clip_det_2_bucket_decr : Leaky bucket decrement (clip detector 2) */
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_BUCKET_DECR_CLIP_DET_2_BUCKET_DECR_MASK 0x000f
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_BUCKET_DECR_CLIP_DET_2_BUCKET_DECR_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int clip_det_2_bucket_decr : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_clip_det_2_bucket_decr;
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_BUCKET_DECR_RST 0x1
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_BUCKET_DECR_ADDR 0x4001d070
-
-
-/* clip_det_2_bucket_incr register */
-/*----------------------*/
-/* Leaky bucket increment (clip detector 2) */
-/* clip_det_2_bucket_incr : Leaky bucket increment in case of overload detection (clip detector 2) */
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_BUCKET_INCR_CLIP_DET_2_BUCKET_INCR_MASK 0x003f
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_BUCKET_INCR_CLIP_DET_2_BUCKET_INCR_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int clip_det_2_bucket_incr : 6;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_clip_det_2_bucket_incr;
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_BUCKET_INCR_RST 0xc
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_BUCKET_INCR_ADDR 0x4001d074
-
-
-/* clip_det_2_bucket_threshold register */
-/*----------------------*/
-/* Leaky bucket threshold (clip detector 2) */
-/* clip_det_2_bucket_threshold : Leaky bucket threshold (clip detector 2) */
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_BUCKET_THRESHOLD_CLIP_DET_2_BUCKET_THRESHOLD_MASK 0x007f
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_BUCKET_THRESHOLD_CLIP_DET_2_BUCKET_THRESHOLD_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int clip_det_2_bucket_threshold : 7;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_clip_det_2_bucket_threshold;
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_BUCKET_THRESHOLD_RST 0x10
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_BUCKET_THRESHOLD_ADDR 0x4001d078
-
-
-/* clip_det_2_timeout register */
-/*----------------------*/
-/* Timeout following a clipping detection during which clipping events are ignored and further gain reduction of the IFAMP is blocked */
-/* clip_det_2_timeout : Timeout following a clipping detection during which clipping events are ignored and further gain reduction of the IFAMP is blocked */
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_TIMEOUT_CLIP_DET_2_TIMEOUT_MASK 0x003f
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_TIMEOUT_CLIP_DET_2_TIMEOUT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int clip_det_2_timeout : 6;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_clip_det_2_timeout;
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_TIMEOUT_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_2_TIMEOUT_ADDR 0x4001d07c
-
-
-/* clip_det_3_window_size register */
-/*----------------------*/
-/* Window (16 MHz samples) during which saturated samples are counted */
-/* clip_det_3_window_size : Window (16 MHz samples) during which saturated samples are counted */
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_3_WINDOW_SIZE_CLIP_DET_3_WINDOW_SIZE_MASK 0x001f
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_3_WINDOW_SIZE_CLIP_DET_3_WINDOW_SIZE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int clip_det_3_window_size : 5;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_clip_det_3_window_size;
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_3_WINDOW_SIZE_RST 0x10
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_3_WINDOW_SIZE_ADDR 0x4001d080
-
-
-/* clip_det_3_thr_1 register */
-/*----------------------*/
-/* If number of saturated samples > 0 and < clip_det_3_thr_1, AAF gain is reduced with 3 dB */
-/* clip_det_3_thr_1 : If number of saturated samples > 0 and < clip_det_3_thr_1, AAF gain is reduced with 3 dB */
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_3_THR_1_CLIP_DET_3_THR_1_MASK 0x001f
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_3_THR_1_CLIP_DET_3_THR_1_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int clip_det_3_thr_1 : 5;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_clip_det_3_thr_1;
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_3_THR_1_RST 0x3
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_3_THR_1_ADDR 0x4001d084
-
-
-/* clip_det_3_thr_2 register */
-/*----------------------*/
-/* If number of saturated samples >= clip_det_3_thr_1 and < clip_det_3_thr_2, AAF gain is reduced with 6 dB. If number of saturated samples >= clip_det_3_thr_2, AAF gain is reduced with 9 dB. */
-/* clip_det_3_thr_2 : If number of saturated samples >= clip_det_3_thr_1 and < clip_det_3_thr_2, AAF gain is reduced with 6 dB. If number of saturated samples >= clip_det_3_thr_2, AAF gain is reduced with 9 dB. */
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_3_THR_2_CLIP_DET_3_THR_2_MASK 0x001f
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_3_THR_2_CLIP_DET_3_THR_2_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int clip_det_3_thr_2 : 5;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_clip_det_3_thr_2;
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_3_THR_2_RST 0x5
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_3_THR_2_ADDR 0x4001d088
-
-
-/* clip_det_3_timeout register */
-/*----------------------*/
-/* Timeout following a clipping detection during which clipping events are ignored and further gain reduction of the AAF is blocked */
-/* clip_det_3_timeout : Timeout following a clipping detection during which clipping events are ignored and further gain reduction of the AAF is blocked */
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_3_TIMEOUT_CLIP_DET_3_TIMEOUT_MASK 0x003f
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_3_TIMEOUT_CLIP_DET_3_TIMEOUT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int clip_det_3_timeout : 6;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_clip_det_3_timeout;
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_3_TIMEOUT_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_3_TIMEOUT_ADDR 0x4001d08c
-
-
-/* ifamp_gain_setting_ana_agc_bypass register */
-/*----------------------*/
-/* IFAMP gain in case agc is bypassed */
-/* ifamp_gain_setting_ana_agc_bypass : IFAMP gain in case agc is bypassed */
-#define EXTAPB_REGFILE_RX_DP_IFAMP_GAIN_SETTING_ANA_AGC_BYPASS_IFAMP_GAIN_SETTING_ANA_AGC_BYPASS_MASK 0x0003
-#define EXTAPB_REGFILE_RX_DP_IFAMP_GAIN_SETTING_ANA_AGC_BYPASS_IFAMP_GAIN_SETTING_ANA_AGC_BYPASS_POS 0
-#define EXTAPB_REGFILE_RX_DP_IFAMP_GAIN_SETTING_ANA_AGC_BYPASS_IFAMP_GAIN_SETTING_ANA_AGC_BYPASS_0_DB 0
-#define EXTAPB_REGFILE_RX_DP_IFAMP_GAIN_SETTING_ANA_AGC_BYPASS_IFAMP_GAIN_SETTING_ANA_AGC_BYPASS_0_DB_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_IFAMP_GAIN_SETTING_ANA_AGC_BYPASS_IFAMP_GAIN_SETTING_ANA_AGC_BYPASS_15_DB 1
-#define EXTAPB_REGFILE_RX_DP_IFAMP_GAIN_SETTING_ANA_AGC_BYPASS_IFAMP_GAIN_SETTING_ANA_AGC_BYPASS_15_DB_MASK 0x1
-#define EXTAPB_REGFILE_RX_DP_IFAMP_GAIN_SETTING_ANA_AGC_BYPASS_IFAMP_GAIN_SETTING_ANA_AGC_BYPASS_26_DB 2
-#define EXTAPB_REGFILE_RX_DP_IFAMP_GAIN_SETTING_ANA_AGC_BYPASS_IFAMP_GAIN_SETTING_ANA_AGC_BYPASS_26_DB_MASK 0x2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int ifamp_gain_setting_ana_agc_bypass : 2;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_ifamp_gain_setting_ana_agc_bypass;
-#define EXTAPB_REGFILE_RX_DP_IFAMP_GAIN_SETTING_ANA_AGC_BYPASS_RST 0x2
-#define EXTAPB_REGFILE_RX_DP_IFAMP_GAIN_SETTING_ANA_AGC_BYPASS_ADDR 0x4001d090
-
-
-/* ifamp_fc_set register */
-/*----------------------*/
-/* IFAMP cut-off frequency */
-/* ifamp_fc_set : Column 2 */
-#define EXTAPB_REGFILE_RX_DP_IFAMP_FC_SET_IFAMP_FC_SET_MASK 0x0003
-#define EXTAPB_REGFILE_RX_DP_IFAMP_FC_SET_IFAMP_FC_SET_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int ifamp_fc_set : 2;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_ifamp_fc_set;
-#define EXTAPB_REGFILE_RX_DP_IFAMP_FC_SET_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_IFAMP_FC_SET_ADDR 0x4001d094
-
-
-/* ifamp_ibias_set register */
-/*----------------------*/
-/* IFAMP ibias control signal; dependent on gain setting, desired bandwidth and current budget. Column selector is ifamp_gain_setting or ifamp_gain_setting_ana_agc_bypass. */
-/* ifamp_ibias_set0 : Column 0 */
-/* ifamp_ibias_set1 : Column 1 */
-/* ifamp_ibias_set2 : Column 2 */
-#define EXTAPB_REGFILE_RX_DP_IFAMP_IBIAS_SET_IFAMP_IBIAS_SET0_MASK 0x001f
-#define EXTAPB_REGFILE_RX_DP_IFAMP_IBIAS_SET_IFAMP_IBIAS_SET0_POS 0
-#define EXTAPB_REGFILE_RX_DP_IFAMP_IBIAS_SET_IFAMP_IBIAS_SET1_MASK 0x03e0
-#define EXTAPB_REGFILE_RX_DP_IFAMP_IBIAS_SET_IFAMP_IBIAS_SET1_POS 5
-#define EXTAPB_REGFILE_RX_DP_IFAMP_IBIAS_SET_IFAMP_IBIAS_SET2_MASK 0x7c00
-#define EXTAPB_REGFILE_RX_DP_IFAMP_IBIAS_SET_IFAMP_IBIAS_SET2_POS 10
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int ifamp_ibias_set0 : 5;
- unsigned int ifamp_ibias_set1 : 5;
- unsigned int ifamp_ibias_set2 : 5;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_ifamp_ibias_set;
-#define EXTAPB_REGFILE_RX_DP_IFAMP_IBIAS_SET_RST 0x28a1
-#define EXTAPB_REGFILE_RX_DP_IFAMP_IBIAS_SET_ADDR 0x4001d098
-
-
-/* ifamp_bypass_set_ana_agc_bypass register */
-/*----------------------*/
-/* ifamp_bypass_set control signal in case agc state machine is bypassed */
-/* ifamp_bypass_set_ana_agc_bypass : ifamp_bypass_set control signal in case agc state machine is bypassed */
-#define EXTAPB_REGFILE_RX_DP_IFAMP_BYPASS_SET_ANA_AGC_BYPASS_IFAMP_BYPASS_SET_ANA_AGC_BYPASS_MASK 0x0001
-#define EXTAPB_REGFILE_RX_DP_IFAMP_BYPASS_SET_ANA_AGC_BYPASS_IFAMP_BYPASS_SET_ANA_AGC_BYPASS_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int ifamp_bypass_set_ana_agc_bypass : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_ifamp_bypass_set_ana_agc_bypass;
-#define EXTAPB_REGFILE_RX_DP_IFAMP_BYPASS_SET_ANA_AGC_BYPASS_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_IFAMP_BYPASS_SET_ANA_AGC_BYPASS_ADDR 0x4001d09c
-
-
-/* aaf_gain_setting_ana_agc_bypass register */
-/*----------------------*/
-/* AAF gain in case agc is bypassed */
-/* aaf_gain_setting_ana_agc_bypass : AAF gain in case agc is bypassed */
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_SETTING_ANA_AGC_BYPASS_AAF_GAIN_SETTING_ANA_AGC_BYPASS_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_SETTING_ANA_AGC_BYPASS_AAF_GAIN_SETTING_ANA_AGC_BYPASS_POS 0
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_SETTING_ANA_AGC_BYPASS_AAF_GAIN_SETTING_ANA_AGC_BYPASS_0_DB 0
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_SETTING_ANA_AGC_BYPASS_AAF_GAIN_SETTING_ANA_AGC_BYPASS_0_DB_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_SETTING_ANA_AGC_BYPASS_AAF_GAIN_SETTING_ANA_AGC_BYPASS_3_DB 1
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_SETTING_ANA_AGC_BYPASS_AAF_GAIN_SETTING_ANA_AGC_BYPASS_3_DB_MASK 0x1
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_SETTING_ANA_AGC_BYPASS_AAF_GAIN_SETTING_ANA_AGC_BYPASS_6_DB 2
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_SETTING_ANA_AGC_BYPASS_AAF_GAIN_SETTING_ANA_AGC_BYPASS_6_DB_MASK 0x2
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_SETTING_ANA_AGC_BYPASS_AAF_GAIN_SETTING_ANA_AGC_BYPASS_9_DB 3
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_SETTING_ANA_AGC_BYPASS_AAF_GAIN_SETTING_ANA_AGC_BYPASS_9_DB_MASK 0x3
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_SETTING_ANA_AGC_BYPASS_AAF_GAIN_SETTING_ANA_AGC_BYPASS_12_DB 4
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_SETTING_ANA_AGC_BYPASS_AAF_GAIN_SETTING_ANA_AGC_BYPASS_12_DB_MASK 0x4
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_SETTING_ANA_AGC_BYPASS_AAF_GAIN_SETTING_ANA_AGC_BYPASS_15_DB 5
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_SETTING_ANA_AGC_BYPASS_AAF_GAIN_SETTING_ANA_AGC_BYPASS_15_DB_MASK 0x5
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_SETTING_ANA_AGC_BYPASS_AAF_GAIN_SETTING_ANA_AGC_BYPASS_18_DB 6
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_SETTING_ANA_AGC_BYPASS_AAF_GAIN_SETTING_ANA_AGC_BYPASS_18_DB_MASK 0x6
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aaf_gain_setting_ana_agc_bypass : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_aaf_gain_setting_ana_agc_bypass;
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_SETTING_ANA_AGC_BYPASS_RST 0x6
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_SETTING_ANA_AGC_BYPASS_ADDR 0x4001d0a0
-
-
-/* aaf_fc_set register */
-/*----------------------*/
-/* AAF cut-off frequency (Stored in configuration bank) */
-/* aaf_fc_set : AAF cut-off frequency */
-#define EXTAPB_REGFILE_RX_DP_AAF_FC_SET_AAF_FC_SET_MASK 0x0003
-#define EXTAPB_REGFILE_RX_DP_AAF_FC_SET_AAF_FC_SET_POS 0
-#define EXTAPB_REGFILE_RX_DP_AAF_FC_SET_AAF_FC_SET_2_5_MHZ 0
-#define EXTAPB_REGFILE_RX_DP_AAF_FC_SET_AAF_FC_SET_2_5_MHZ_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_AAF_FC_SET_AAF_FC_SET_1_4_MHZ 1
-#define EXTAPB_REGFILE_RX_DP_AAF_FC_SET_AAF_FC_SET_1_4_MHZ_MASK 0x1
-#define EXTAPB_REGFILE_RX_DP_AAF_FC_SET_AAF_FC_SET_1_1_MHZ 3
-#define EXTAPB_REGFILE_RX_DP_AAF_FC_SET_AAF_FC_SET_1_1_MHZ_MASK 0x3
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#else
-#define EXTAPB_REGFILE_RX_DP_AAF_FC_SET_AAF_FC_SET_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_AAF_FC_SET_AAF_FC_SET_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_AAF_FC_SET_AAF_FC_SET_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_AAF_FC_SET_AAF_FC_SET_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_AAF_FC_SET_AAF_FC_SET_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_AAF_FC_SET_AAF_FC_SET_BLE_2_MASK 0x0
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aaf_fc_set : 2;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_aaf_fc_set;
-#define EXTAPB_REGFILE_RX_DP_AAF_FC_SET_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_AAF_FC_SET_ADDR 0x4001d0a4
-
-
-/* aaf_q_set register */
-/*----------------------*/
-/* AAF Q factor. Column selector is based on aaf_fc_set. Values: 0..2 */
-/* aaf_q_set0 : Column 0 */
-/* aaf_q_set1 : Column 1 */
-/* aaf_q_set2 : Column 2 */
-#define EXTAPB_REGFILE_RX_DP_AAF_Q_SET_AAF_Q_SET0_MASK 0x0003
-#define EXTAPB_REGFILE_RX_DP_AAF_Q_SET_AAF_Q_SET0_POS 0
-#define EXTAPB_REGFILE_RX_DP_AAF_Q_SET_AAF_Q_SET1_MASK 0x000c
-#define EXTAPB_REGFILE_RX_DP_AAF_Q_SET_AAF_Q_SET1_POS 2
-#define EXTAPB_REGFILE_RX_DP_AAF_Q_SET_AAF_Q_SET2_MASK 0x0030
-#define EXTAPB_REGFILE_RX_DP_AAF_Q_SET_AAF_Q_SET2_POS 4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aaf_q_set0 : 2;
- unsigned int aaf_q_set1 : 2;
- unsigned int aaf_q_set2 : 2;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_aaf_q_set;
-#define EXTAPB_REGFILE_RX_DP_AAF_Q_SET_RST 0x3a
-#define EXTAPB_REGFILE_RX_DP_AAF_Q_SET_ADDR 0x4001d0a8
-
-
-/* aaf_opam1i_set0 register */
-/*----------------------*/
-/* AAF tail current of OTA stage 1. Row selector is based on aaf_fc_set. Column selector is aaf_gain_setting or aaf_gain_setting_ana_agc_bypass. */
-/* aaf_opam1i_set0 : Row 0 */
-/* aaf_opam1i_set1 : Row 1 */
-/* aaf_opam1i_set2 : Row 2 */
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET0_AAF_OPAM1I_SET0_MASK 0x000f
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET0_AAF_OPAM1I_SET0_POS 0
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET0_AAF_OPAM1I_SET1_MASK 0x00f0
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET0_AAF_OPAM1I_SET1_POS 4
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET0_AAF_OPAM1I_SET2_MASK 0x0f00
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET0_AAF_OPAM1I_SET2_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aaf_opam1i_set0 : 4;
- unsigned int aaf_opam1i_set1 : 4;
- unsigned int aaf_opam1i_set2 : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_aaf_opam1i_set0;
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET0_RST 0x666
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET0_ADDR 0x4001d0ac
-
-
-/* aaf_opam1i_set1 register */
-/*----------------------*/
-/* AAF tail current of OTA stage 1. Row selector is based on aaf_fc_set. Column selector is aaf_gain_setting or aaf_gain_setting_ana_agc_bypass. */
-/* aaf_opam1i_set0 : Row 0 */
-/* aaf_opam1i_set1 : Row 1 */
-/* aaf_opam1i_set2 : Row 2 */
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET1_AAF_OPAM1I_SET0_MASK 0x000f
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET1_AAF_OPAM1I_SET0_POS 0
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET1_AAF_OPAM1I_SET1_MASK 0x00f0
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET1_AAF_OPAM1I_SET1_POS 4
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET1_AAF_OPAM1I_SET2_MASK 0x0f00
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET1_AAF_OPAM1I_SET2_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aaf_opam1i_set0 : 4;
- unsigned int aaf_opam1i_set1 : 4;
- unsigned int aaf_opam1i_set2 : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_aaf_opam1i_set1;
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET1_RST 0x666
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET1_ADDR 0x4001d0b0
-
-
-/* aaf_opam1i_set2 register */
-/*----------------------*/
-/* AAF tail current of OTA stage 1. Row selector is based on aaf_fc_set. Column selector is aaf_gain_setting or aaf_gain_setting_ana_agc_bypass. */
-/* aaf_opam1i_set0 : Row 0 */
-/* aaf_opam1i_set1 : Row 1 */
-/* aaf_opam1i_set2 : Row 2 */
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET2_AAF_OPAM1I_SET0_MASK 0x000f
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET2_AAF_OPAM1I_SET0_POS 0
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET2_AAF_OPAM1I_SET1_MASK 0x00f0
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET2_AAF_OPAM1I_SET1_POS 4
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET2_AAF_OPAM1I_SET2_MASK 0x0f00
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET2_AAF_OPAM1I_SET2_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aaf_opam1i_set0 : 4;
- unsigned int aaf_opam1i_set1 : 4;
- unsigned int aaf_opam1i_set2 : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_aaf_opam1i_set2;
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET2_RST 0x666
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET2_ADDR 0x4001d0b4
-
-
-/* aaf_opam1i_set3 register */
-/*----------------------*/
-/* AAF tail current of OTA stage 1. Row selector is based on aaf_fc_set. Column selector is aaf_gain_setting or aaf_gain_setting_ana_agc_bypass. */
-/* aaf_opam1i_set0 : Row 0 */
-/* aaf_opam1i_set1 : Row 1 */
-/* aaf_opam1i_set2 : Row 2 */
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET3_AAF_OPAM1I_SET0_MASK 0x000f
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET3_AAF_OPAM1I_SET0_POS 0
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET3_AAF_OPAM1I_SET1_MASK 0x00f0
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET3_AAF_OPAM1I_SET1_POS 4
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET3_AAF_OPAM1I_SET2_MASK 0x0f00
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET3_AAF_OPAM1I_SET2_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aaf_opam1i_set0 : 4;
- unsigned int aaf_opam1i_set1 : 4;
- unsigned int aaf_opam1i_set2 : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_aaf_opam1i_set3;
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET3_RST 0x666
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET3_ADDR 0x4001d0b8
-
-
-/* aaf_opam1i_set4 register */
-/*----------------------*/
-/* AAF tail current of OTA stage 1. Row selector is based on aaf_fc_set. Column selector is aaf_gain_setting or aaf_gain_setting_ana_agc_bypass. */
-/* aaf_opam1i_set0 : Row 0 */
-/* aaf_opam1i_set1 : Row 1 */
-/* aaf_opam1i_set2 : Row 2 */
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET4_AAF_OPAM1I_SET0_MASK 0x000f
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET4_AAF_OPAM1I_SET0_POS 0
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET4_AAF_OPAM1I_SET1_MASK 0x00f0
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET4_AAF_OPAM1I_SET1_POS 4
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET4_AAF_OPAM1I_SET2_MASK 0x0f00
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET4_AAF_OPAM1I_SET2_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aaf_opam1i_set0 : 4;
- unsigned int aaf_opam1i_set1 : 4;
- unsigned int aaf_opam1i_set2 : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_aaf_opam1i_set4;
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET4_RST 0x866
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET4_ADDR 0x4001d0bc
-
-
-/* aaf_opam1i_set5 register */
-/*----------------------*/
-/* AAF tail current of OTA stage 1. Row selector is based on aaf_fc_set. Column selector is aaf_gain_setting or aaf_gain_setting_ana_agc_bypass. */
-/* aaf_opam1i_set0 : Row 0 */
-/* aaf_opam1i_set1 : Row 1 */
-/* aaf_opam1i_set2 : Row 2 */
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET5_AAF_OPAM1I_SET0_MASK 0x000f
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET5_AAF_OPAM1I_SET0_POS 0
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET5_AAF_OPAM1I_SET1_MASK 0x00f0
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET5_AAF_OPAM1I_SET1_POS 4
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET5_AAF_OPAM1I_SET2_MASK 0x0f00
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET5_AAF_OPAM1I_SET2_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aaf_opam1i_set0 : 4;
- unsigned int aaf_opam1i_set1 : 4;
- unsigned int aaf_opam1i_set2 : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_aaf_opam1i_set5;
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET5_RST 0x866
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET5_ADDR 0x4001d0c0
-
-
-/* aaf_opam1i_set6 register */
-/*----------------------*/
-/* AAF tail current of OTA stage 1. Row selector is based on aaf_fc_set. Column selector is aaf_gain_setting or aaf_gain_setting_ana_agc_bypass. */
-/* aaf_opam1i_set0 : Row 0 */
-/* aaf_opam1i_set1 : Row 1 */
-/* aaf_opam1i_set2 : Row 2 */
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET6_AAF_OPAM1I_SET0_MASK 0x000f
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET6_AAF_OPAM1I_SET0_POS 0
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET6_AAF_OPAM1I_SET1_MASK 0x00f0
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET6_AAF_OPAM1I_SET1_POS 4
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET6_AAF_OPAM1I_SET2_MASK 0x0f00
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET6_AAF_OPAM1I_SET2_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aaf_opam1i_set0 : 4;
- unsigned int aaf_opam1i_set1 : 4;
- unsigned int aaf_opam1i_set2 : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_aaf_opam1i_set6;
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET6_RST 0xa88
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM1I_SET6_ADDR 0x4001d0c4
-
-
-/* aaf_opam2i_set0 register */
-/*----------------------*/
-/* AAF tail current of OTA stage 2. Row selector is based on aaf_fc_set. Column selector is aaf_gain_setting or aaf_gain_setting_ana_agc_bypass. */
-/* aaf_opam2i_set0 : Row 0 */
-/* aaf_opam2i_set1 : Row 1 */
-/* aaf_opam2i_set2 : Row 2 */
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET0_AAF_OPAM2I_SET0_MASK 0x000f
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET0_AAF_OPAM2I_SET0_POS 0
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET0_AAF_OPAM2I_SET1_MASK 0x00f0
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET0_AAF_OPAM2I_SET1_POS 4
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET0_AAF_OPAM2I_SET2_MASK 0x0f00
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET0_AAF_OPAM2I_SET2_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aaf_opam2i_set0 : 4;
- unsigned int aaf_opam2i_set1 : 4;
- unsigned int aaf_opam2i_set2 : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_aaf_opam2i_set0;
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET0_RST 0x888
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET0_ADDR 0x4001d0c8
-
-
-/* aaf_opam2i_set1 register */
-/*----------------------*/
-/* AAF tail current of OTA stage 2. Row selector is based on aaf_fc_set. Column selector is aaf_gain_setting or aaf_gain_setting_ana_agc_bypass. */
-/* aaf_opam2i_set0 : Row 0 */
-/* aaf_opam2i_set1 : Row 1 */
-/* aaf_opam2i_set2 : Row 2 */
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET1_AAF_OPAM2I_SET0_MASK 0x000f
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET1_AAF_OPAM2I_SET0_POS 0
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET1_AAF_OPAM2I_SET1_MASK 0x00f0
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET1_AAF_OPAM2I_SET1_POS 4
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET1_AAF_OPAM2I_SET2_MASK 0x0f00
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET1_AAF_OPAM2I_SET2_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aaf_opam2i_set0 : 4;
- unsigned int aaf_opam2i_set1 : 4;
- unsigned int aaf_opam2i_set2 : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_aaf_opam2i_set1;
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET1_RST 0x888
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET1_ADDR 0x4001d0cc
-
-
-/* aaf_opam2i_set2 register */
-/*----------------------*/
-/* AAF tail current of OTA stage 2. Row selector is based on aaf_fc_set. Column selector is aaf_gain_setting or aaf_gain_setting_ana_agc_bypass. */
-/* aaf_opam2i_set0 : Row 0 */
-/* aaf_opam2i_set1 : Row 1 */
-/* aaf_opam2i_set2 : Row 2 */
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET2_AAF_OPAM2I_SET0_MASK 0x000f
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET2_AAF_OPAM2I_SET0_POS 0
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET2_AAF_OPAM2I_SET1_MASK 0x00f0
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET2_AAF_OPAM2I_SET1_POS 4
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET2_AAF_OPAM2I_SET2_MASK 0x0f00
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET2_AAF_OPAM2I_SET2_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aaf_opam2i_set0 : 4;
- unsigned int aaf_opam2i_set1 : 4;
- unsigned int aaf_opam2i_set2 : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_aaf_opam2i_set2;
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET2_RST 0x888
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET2_ADDR 0x4001d0d0
-
-
-/* aaf_opam2i_set3 register */
-/*----------------------*/
-/* AAF tail current of OTA stage 2. Row selector is based on aaf_fc_set. Column selector is aaf_gain_setting or aaf_gain_setting_ana_agc_bypass. */
-/* aaf_opam2i_set0 : Row 0 */
-/* aaf_opam2i_set1 : Row 1 */
-/* aaf_opam2i_set2 : Row 2 */
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET3_AAF_OPAM2I_SET0_MASK 0x000f
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET3_AAF_OPAM2I_SET0_POS 0
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET3_AAF_OPAM2I_SET1_MASK 0x00f0
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET3_AAF_OPAM2I_SET1_POS 4
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET3_AAF_OPAM2I_SET2_MASK 0x0f00
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET3_AAF_OPAM2I_SET2_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aaf_opam2i_set0 : 4;
- unsigned int aaf_opam2i_set1 : 4;
- unsigned int aaf_opam2i_set2 : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_aaf_opam2i_set3;
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET3_RST 0x888
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET3_ADDR 0x4001d0d4
-
-
-/* aaf_opam2i_set4 register */
-/*----------------------*/
-/* AAF tail current of OTA stage 2. Row selector is based on aaf_fc_set. Column selector is aaf_gain_setting or aaf_gain_setting_ana_agc_bypass. */
-/* aaf_opam2i_set0 : Row 0 */
-/* aaf_opam2i_set1 : Row 1 */
-/* aaf_opam2i_set2 : Row 2 */
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET4_AAF_OPAM2I_SET0_MASK 0x000f
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET4_AAF_OPAM2I_SET0_POS 0
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET4_AAF_OPAM2I_SET1_MASK 0x00f0
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET4_AAF_OPAM2I_SET1_POS 4
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET4_AAF_OPAM2I_SET2_MASK 0x0f00
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET4_AAF_OPAM2I_SET2_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aaf_opam2i_set0 : 4;
- unsigned int aaf_opam2i_set1 : 4;
- unsigned int aaf_opam2i_set2 : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_aaf_opam2i_set4;
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET4_RST 0xa88
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET4_ADDR 0x4001d0d8
-
-
-/* aaf_opam2i_set5 register */
-/*----------------------*/
-/* AAF tail current of OTA stage 2. Row selector is based on aaf_fc_set. Column selector is aaf_gain_setting or aaf_gain_setting_ana_agc_bypass. */
-/* aaf_opam2i_set0 : Row 0 */
-/* aaf_opam2i_set1 : Row 1 */
-/* aaf_opam2i_set2 : Row 2 */
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET5_AAF_OPAM2I_SET0_MASK 0x000f
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET5_AAF_OPAM2I_SET0_POS 0
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET5_AAF_OPAM2I_SET1_MASK 0x00f0
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET5_AAF_OPAM2I_SET1_POS 4
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET5_AAF_OPAM2I_SET2_MASK 0x0f00
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET5_AAF_OPAM2I_SET2_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aaf_opam2i_set0 : 4;
- unsigned int aaf_opam2i_set1 : 4;
- unsigned int aaf_opam2i_set2 : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_aaf_opam2i_set5;
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET5_RST 0xa88
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET5_ADDR 0x4001d0dc
-
-
-/* aaf_opam2i_set6 register */
-/*----------------------*/
-/* AAF tail current of OTA stage 2. Row selector is based on aaf_fc_set. Column selector is aaf_gain_setting or aaf_gain_setting_ana_agc_bypass. */
-/* aaf_opam2i_set0 : Row 0 */
-/* aaf_opam2i_set1 : Row 1 */
-/* aaf_opam2i_set2 : Row 2 */
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET6_AAF_OPAM2I_SET0_MASK 0x000f
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET6_AAF_OPAM2I_SET0_POS 0
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET6_AAF_OPAM2I_SET1_MASK 0x00f0
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET6_AAF_OPAM2I_SET1_POS 4
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET6_AAF_OPAM2I_SET2_MASK 0x0f00
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET6_AAF_OPAM2I_SET2_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aaf_opam2i_set0 : 4;
- unsigned int aaf_opam2i_set1 : 4;
- unsigned int aaf_opam2i_set2 : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_aaf_opam2i_set6;
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET6_RST 0xaaa
-#define EXTAPB_REGFILE_RX_DP_AAF_OPAM2I_SET6_ADDR 0x4001d0e0
-
-
-/* aaf_gain_delay register */
-/*----------------------*/
-/* Delay in applying a gain setting change to the anti-aliasing filter. Used to introduce delay between simultaneous IFAMP and AAF gain adjustments. (Stored in configuration bank) */
-/* aaf_gain_delay : Delay in applying a gain setting change to the anti-aliasing filter. Used to introduce delay between simultaneous IFAMP and AAF gain adjustments. */
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_DELAY_AAF_GAIN_DELAY_MASK 0x003f
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_DELAY_AAF_GAIN_DELAY_POS 0
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#else
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_DELAY_AAF_GAIN_DELAY_ZB_2 3
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_DELAY_AAF_GAIN_DELAY_ZB_2_MASK 0x3
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_DELAY_AAF_GAIN_DELAY_BLE_1 3
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_DELAY_AAF_GAIN_DELAY_BLE_1_MASK 0x3
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_DELAY_AAF_GAIN_DELAY_BLE_2 3
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_DELAY_AAF_GAIN_DELAY_BLE_2_MASK 0x3
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aaf_gain_delay : 6;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_aaf_gain_delay;
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_DELAY_RST 0x3
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_DELAY_ADDR 0x4001d0e4
-
-
-/* nb_rssi_correction_db register */
-/*----------------------*/
-/* Programmable offset which can be given to the measured narrowband RSSI as entry to the gain setting lookup table. Values: -32..31 (Stored in configuration bank) */
-/* nb_rssi_correction_db : Programmable offset which can be given to the measured narrowband RSSI as entry to the gain setting lookup table. Values: -32..31 */
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CORRECTION_DB_NB_RSSI_CORRECTION_DB_MASK 0x003f
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CORRECTION_DB_NB_RSSI_CORRECTION_DB_POS 0
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CORRECTION_DB_NB_RSSI_CORRECTION_DB_BT_LE_1 0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CORRECTION_DB_NB_RSSI_CORRECTION_DB_BT_LE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CORRECTION_DB_NB_RSSI_CORRECTION_DB_BT_LE_2 8
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CORRECTION_DB_NB_RSSI_CORRECTION_DB_BT_LE_2_MASK 0x8
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CORRECTION_DB_NB_RSSI_CORRECTION_DB_NORDIC_250 2
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CORRECTION_DB_NB_RSSI_CORRECTION_DB_NORDIC_250_MASK 0x2
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CORRECTION_DB_NB_RSSI_CORRECTION_DB_NORDIC_2 8
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CORRECTION_DB_NB_RSSI_CORRECTION_DB_NORDIC_2_MASK 0x8
-#else
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CORRECTION_DB_NB_RSSI_CORRECTION_DB_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CORRECTION_DB_NB_RSSI_CORRECTION_DB_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CORRECTION_DB_NB_RSSI_CORRECTION_DB_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CORRECTION_DB_NB_RSSI_CORRECTION_DB_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CORRECTION_DB_NB_RSSI_CORRECTION_DB_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CORRECTION_DB_NB_RSSI_CORRECTION_DB_BLE_2_MASK 0x0
-#endif
-
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nb_rssi_correction_db : 6;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_nb_rssi_correction_db;
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CORRECTION_DB_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CORRECTION_DB_ADDR 0x4001d0e8
-
-
-/* nb_rssi_hysteresis register */
-/*----------------------*/
-/* Hysteresis on subsequent narrowband RSSI measurements input to the gain setting lookup table. (Stored in configuration bank) */
-/* nb_rssi_hysteresis : Hysteresis on subsequent narrowband RSSI measurements input to the gain setting lookup table */
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_HYSTERESIS_NB_RSSI_HYSTERESIS_MASK 0x000f
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_HYSTERESIS_NB_RSSI_HYSTERESIS_POS 0
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#else
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_HYSTERESIS_NB_RSSI_HYSTERESIS_ZB_2 4
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_HYSTERESIS_NB_RSSI_HYSTERESIS_ZB_2_MASK 0x4
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_HYSTERESIS_NB_RSSI_HYSTERESIS_BLE_1 4
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_HYSTERESIS_NB_RSSI_HYSTERESIS_BLE_1_MASK 0x4
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_HYSTERESIS_NB_RSSI_HYSTERESIS_BLE_2 4
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_HYSTERESIS_NB_RSSI_HYSTERESIS_BLE_2_MASK 0x4
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nb_rssi_hysteresis : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_nb_rssi_hysteresis;
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_HYSTERESIS_RST 0x4
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_HYSTERESIS_ADDR 0x4001d0ec
-
-
-/* rssi_lna_gain_lut1 register */
-/*----------------------*/
-/* lna gain lookup table part 1; entry is narrowband RSSI (Stored in configuration bank) */
-/* rssi_lna_gain_lut4 : m86 dBm */
-/* rssi_lna_gain_lut5 : m83 dBm */
-/* rssi_lna_gain_lut6 : m80 dBm */
-/* rssi_lna_gain_lut7 : m77 dBm */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT4_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT4_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT5_MASK 0x0038
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT5_POS 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT6_MASK 0x01c0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT6_POS 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT7_MASK 0x0e00
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT7_POS 9
-#else
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT4_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT4_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT4_ZB_2 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT4_ZB_2_MASK 0x3
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT4_BLE_1 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT4_BLE_1_MASK 0x3
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT4_BLE_2 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT4_BLE_2_MASK 0x3
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT5_MASK 0x0038
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT5_POS 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT5_ZB_2 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT5_ZB_2_MASK 0x18
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT5_BLE_1 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT5_BLE_1_MASK 0x18
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT5_BLE_2 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT5_BLE_2_MASK 0x18
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT6_MASK 0x01c0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT6_POS 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT6_ZB_2 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT6_ZB_2_MASK 0xc0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT6_BLE_1 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT6_BLE_1_MASK 0xc0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT6_BLE_2 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT6_BLE_2_MASK 0xc0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT7_MASK 0x0e00
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT7_POS 9
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT7_ZB_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT7_ZB_2_MASK 0x400
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT7_BLE_1 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT7_BLE_1_MASK 0x400
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT7_BLE_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RSSI_LNA_GAIN_LUT7_BLE_2_MASK 0x400
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rssi_lna_gain_lut4 : 3;
- unsigned int rssi_lna_gain_lut5 : 3;
- unsigned int rssi_lna_gain_lut6 : 3;
- unsigned int rssi_lna_gain_lut7 : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_rssi_lna_gain_lut1;
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_RST 0x4db
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT1_ADDR 0x4001d0f0
-
-
-/* rssi_lna_gain_lut2 register */
-/*----------------------*/
-/* lna gain lookup table part 2; entry is narrowband RSSI (Stored in configuration bank) */
-/* rssi_lna_gain_lut8 : m74 dBm */
-/* rssi_lna_gain_lut9 : m71 dBm */
-/* rssi_lna_gain_lut10 : m68 dBm */
-/* rssi_lna_gain_lut11 : m65 dBm */
-/* rssi_lna_gain_lut12 : m62 dBm */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT8_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT8_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT9_MASK 0x0038
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT9_POS 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT10_MASK 0x01c0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT10_POS 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT11_MASK 0x0e00
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT11_POS 9
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT12_MASK 0x7000
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT12_POS 12
-#else
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT8_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT8_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT8_ZB_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT8_ZB_2_MASK 0x2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT8_BLE_1 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT8_BLE_1_MASK 0x2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT8_BLE_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT8_BLE_2_MASK 0x2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT9_MASK 0x0038
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT9_POS 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT9_ZB_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT9_ZB_2_MASK 0x10
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT9_BLE_1 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT9_BLE_1_MASK 0x10
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT9_BLE_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT9_BLE_2_MASK 0x10
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT10_MASK 0x01c0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT10_POS 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT10_ZB_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT10_ZB_2_MASK 0x80
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT10_BLE_1 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT10_BLE_1_MASK 0x80
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT10_BLE_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT10_BLE_2_MASK 0x80
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT11_MASK 0x0e00
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT11_POS 9
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT11_ZB_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT11_ZB_2_MASK 0x400
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT11_BLE_1 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT11_BLE_1_MASK 0x400
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT11_BLE_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT11_BLE_2_MASK 0x400
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT12_MASK 0x7000
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT12_POS 12
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT12_ZB_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT12_ZB_2_MASK 0x2000
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT12_BLE_1 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT12_BLE_1_MASK 0x2000
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT12_BLE_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RSSI_LNA_GAIN_LUT12_BLE_2_MASK 0x2000
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rssi_lna_gain_lut8 : 3;
- unsigned int rssi_lna_gain_lut9 : 3;
- unsigned int rssi_lna_gain_lut10 : 3;
- unsigned int rssi_lna_gain_lut11 : 3;
- unsigned int rssi_lna_gain_lut12 : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_rssi_lna_gain_lut2;
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_RST 0x2492
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT2_ADDR 0x4001d0f4
-
-
-/* rssi_lna_gain_lut3 register */
-/*----------------------*/
-/* lna gain lookup table part 3; entry is narrowband RSSI (Stored in configuration bank) */
-/* rssi_lna_gain_lut13 : m59 dBm */
-/* rssi_lna_gain_lut14 : m56 dBm */
-/* rssi_lna_gain_lut15 : m53 dBm */
-/* rssi_lna_gain_lut16 : m50 dBm */
-/* rssi_lna_gain_lut17 : m47 dBm */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT13_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT13_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT14_MASK 0x0038
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT14_POS 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT15_MASK 0x01c0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT15_POS 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT16_MASK 0x0e00
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT16_POS 9
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT17_MASK 0x7000
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT17_POS 12
-#else
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT13_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT13_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT13_ZB_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT13_ZB_2_MASK 0x2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT13_BLE_1 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT13_BLE_1_MASK 0x2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT13_BLE_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT13_BLE_2_MASK 0x2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT14_MASK 0x0038
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT14_POS 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT14_ZB_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT14_ZB_2_MASK 0x10
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT14_BLE_1 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT14_BLE_1_MASK 0x10
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT14_BLE_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT14_BLE_2_MASK 0x10
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT15_MASK 0x01c0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT15_POS 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT15_ZB_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT15_ZB_2_MASK 0x80
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT15_BLE_1 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT15_BLE_1_MASK 0x80
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT15_BLE_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT15_BLE_2_MASK 0x80
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT16_MASK 0x0e00
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT16_POS 9
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT16_ZB_2 1
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT16_ZB_2_MASK 0x200
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT16_BLE_1 1
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT16_BLE_1_MASK 0x200
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT16_BLE_2 1
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT16_BLE_2_MASK 0x200
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT17_MASK 0x7000
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT17_POS 12
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT17_ZB_2 1
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT17_ZB_2_MASK 0x1000
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT17_BLE_1 1
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT17_BLE_1_MASK 0x1000
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT17_BLE_2 1
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RSSI_LNA_GAIN_LUT17_BLE_2_MASK 0x1000
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rssi_lna_gain_lut13 : 3;
- unsigned int rssi_lna_gain_lut14 : 3;
- unsigned int rssi_lna_gain_lut15 : 3;
- unsigned int rssi_lna_gain_lut16 : 3;
- unsigned int rssi_lna_gain_lut17 : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_rssi_lna_gain_lut3;
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_RST 0x1292
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT3_ADDR 0x4001d0f8
-
-
-/* rssi_lna_gain_lut4 register */
-/*----------------------*/
-/* lna gain lookup table part 4; entry is narrowband RSSI (Stored in configuration bank) */
-/* rssi_lna_gain_lut18 : m44 dBm */
-/* rssi_lna_gain_lut19 : m41 dBm */
-/* rssi_lna_gain_lut20 : m38 dBm */
-/* rssi_lna_gain_lut21 : m35 dBm */
-/* rssi_lna_gain_lut22 : m33 dBm */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT18_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT18_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT19_MASK 0x0038
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT19_POS 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT20_MASK 0x01c0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT20_POS 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT21_MASK 0x0e00
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT21_POS 9
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT22_MASK 0x7000
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT22_POS 12
-#else
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT18_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT18_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT18_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT18_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT18_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT18_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT18_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT18_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT19_MASK 0x0038
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT19_POS 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT19_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT19_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT19_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT19_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT19_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT19_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT20_MASK 0x01c0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT20_POS 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT20_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT20_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT20_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT20_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT20_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT20_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT21_MASK 0x0e00
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT21_POS 9
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT21_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT21_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT21_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT21_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT21_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT21_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT22_MASK 0x7000
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT22_POS 12
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT22_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT22_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT22_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT22_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT22_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RSSI_LNA_GAIN_LUT22_BLE_2_MASK 0x0
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rssi_lna_gain_lut18 : 3;
- unsigned int rssi_lna_gain_lut19 : 3;
- unsigned int rssi_lna_gain_lut20 : 3;
- unsigned int rssi_lna_gain_lut21 : 3;
- unsigned int rssi_lna_gain_lut22 : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_rssi_lna_gain_lut4;
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT4_ADDR 0x4001d0fc
-
-
-/* rssi_ifamp_gain_lut0 register */
-/*----------------------*/
-/* IFAMP gain lookup table part 0; entry is narrowband RSSI (Stored in configuration bank) */
-/* rssi_ifamp_gain_lut0 : m98 dBm */
-/* rssi_ifamp_gain_lut1 : m95 dBm */
-/* rssi_ifamp_gain_lut2 : m92 dBm */
-/* rssi_ifamp_gain_lut3 : m89 dBm */
-/* rssi_ifamp_gain_lut4 : m86 dBm */
-/* rssi_ifamp_gain_lut5 : m83 dBm */
-/* rssi_ifamp_gain_lut6 : m80 dBm */
-/* rssi_ifamp_gain_lut7 : m77 dBm */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT0_MASK 0x0003
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT0_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT1_MASK 0x000c
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT1_POS 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT2_MASK 0x0030
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT2_POS 4
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT3_MASK 0x00c0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT3_POS 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT4_MASK 0x0300
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT4_POS 8
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT5_MASK 0x0c00
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT5_POS 10
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT6_MASK 0x3000
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT6_POS 12
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT7_MASK 0xc000
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT7_POS 14
-#else
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT0_MASK 0x0003
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT0_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT0_ZB_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT0_ZB_2_MASK 0x2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT0_BLE_1 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT0_BLE_1_MASK 0x2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT0_BLE_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT0_BLE_2_MASK 0x2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT1_MASK 0x000c
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT1_POS 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT1_ZB_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT1_ZB_2_MASK 0x8
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT1_BLE_1 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT1_BLE_1_MASK 0x8
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT1_BLE_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT1_BLE_2_MASK 0x8
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT2_MASK 0x0030
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT2_POS 4
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT2_ZB_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT2_ZB_2_MASK 0x20
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT2_BLE_1 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT2_BLE_1_MASK 0x20
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT2_BLE_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT2_BLE_2_MASK 0x20
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT3_MASK 0x00c0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT3_POS 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT3_ZB_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT3_ZB_2_MASK 0x80
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT3_BLE_1 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT3_BLE_1_MASK 0x80
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT3_BLE_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT3_BLE_2_MASK 0x80
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT4_MASK 0x0300
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT4_POS 8
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT4_ZB_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT4_ZB_2_MASK 0x200
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT4_BLE_1 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT4_BLE_1_MASK 0x200
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT4_BLE_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT4_BLE_2_MASK 0x200
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT5_MASK 0x0c00
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT5_POS 10
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT5_ZB_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT5_ZB_2_MASK 0x800
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT5_BLE_1 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT5_BLE_1_MASK 0x800
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT5_BLE_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT5_BLE_2_MASK 0x800
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT6_MASK 0x3000
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT6_POS 12
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT6_ZB_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT6_ZB_2_MASK 0x2000
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT6_BLE_1 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT6_BLE_1_MASK 0x2000
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT6_BLE_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT6_BLE_2_MASK 0x2000
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT7_MASK 0xc000
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT7_POS 14
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT7_ZB_2 1
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT7_ZB_2_MASK 0x4000
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT7_BLE_1 1
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT7_BLE_1_MASK 0x4000
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT7_BLE_2 1
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RSSI_IFAMP_GAIN_LUT7_BLE_2_MASK 0x4000
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rssi_ifamp_gain_lut0 : 2;
- unsigned int rssi_ifamp_gain_lut1 : 2;
- unsigned int rssi_ifamp_gain_lut2 : 2;
- unsigned int rssi_ifamp_gain_lut3 : 2;
- unsigned int rssi_ifamp_gain_lut4 : 2;
- unsigned int rssi_ifamp_gain_lut5 : 2;
- unsigned int rssi_ifamp_gain_lut6 : 2;
- unsigned int rssi_ifamp_gain_lut7 : 2;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_rssi_ifamp_gain_lut0;
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_RST 0x6aaa
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT0_ADDR 0x4001d100
-
-
-/* rssi_ifamp_gain_lut1 register */
-/*----------------------*/
-/* IFAMP gain lookup table part 1; entry is narrowband RSSI (Stored in configuration bank) */
-/* rssi_ifamp_gain_lut8 : m74 dBm */
-/* rssi_ifamp_gain_lut9 : m71 dBm */
-/* rssi_ifamp_gain_lut10 : m68 dBm */
-/* rssi_ifamp_gain_lut11 : m65 dBm */
-/* rssi_ifamp_gain_lut12 : m62 dBm */
-/* rssi_ifamp_gain_lut13 : m59 dBm */
-/* rssi_ifamp_gain_lut14 : m56 dBm */
-/* rssi_ifamp_gain_lut15 : m53 dBm */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT8_MASK 0x0003
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT8_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT9_MASK 0x000c
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT9_POS 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT10_MASK 0x0030
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT10_POS 4
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT11_MASK 0x00c0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT11_POS 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT12_MASK 0x0300
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT12_POS 8
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT13_MASK 0x0c00
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT13_POS 10
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT14_MASK 0x3000
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT14_POS 12
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT15_MASK 0xc000
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT15_POS 14
-#else
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT8_MASK 0x0003
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT8_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT8_ZB_2 1
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT8_ZB_2_MASK 0x1
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT8_BLE_1 1
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT8_BLE_1_MASK 0x1
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT8_BLE_2 1
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT8_BLE_2_MASK 0x1
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT9_MASK 0x000c
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT9_POS 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT9_ZB_2 1
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT9_ZB_2_MASK 0x4
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT9_BLE_1 1
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT9_BLE_1_MASK 0x4
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT9_BLE_2 1
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT9_BLE_2_MASK 0x4
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT10_MASK 0x0030
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT10_POS 4
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT10_ZB_2 1
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT10_ZB_2_MASK 0x10
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT10_BLE_1 1
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT10_BLE_1_MASK 0x10
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT10_BLE_2 1
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT10_BLE_2_MASK 0x10
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT11_MASK 0x00c0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT11_POS 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT11_ZB_2 1
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT11_ZB_2_MASK 0x40
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT11_BLE_1 1
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT11_BLE_1_MASK 0x40
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT11_BLE_2 1
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT11_BLE_2_MASK 0x40
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT12_MASK 0x0300
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT12_POS 8
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT12_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT12_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT12_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT12_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT12_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT12_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT13_MASK 0x0c00
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT13_POS 10
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT13_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT13_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT13_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT13_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT13_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT13_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT14_MASK 0x3000
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT14_POS 12
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT14_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT14_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT14_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT14_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT14_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT14_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT15_MASK 0xc000
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT15_POS 14
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT15_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT15_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT15_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT15_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT15_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RSSI_IFAMP_GAIN_LUT15_BLE_2_MASK 0x0
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rssi_ifamp_gain_lut8 : 2;
- unsigned int rssi_ifamp_gain_lut9 : 2;
- unsigned int rssi_ifamp_gain_lut10 : 2;
- unsigned int rssi_ifamp_gain_lut11 : 2;
- unsigned int rssi_ifamp_gain_lut12 : 2;
- unsigned int rssi_ifamp_gain_lut13 : 2;
- unsigned int rssi_ifamp_gain_lut14 : 2;
- unsigned int rssi_ifamp_gain_lut15 : 2;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_rssi_ifamp_gain_lut1;
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_RST 0x55
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT1_ADDR 0x4001d104
-
-
-/* rssi_ifamp_gain_lut2 register */
-/*----------------------*/
-/* IFAMP gain lookup table part 2; entry is narrowband RSSI (Stored in configuration bank) */
-/* rssi_ifamp_gain_lut16 : m50 dBm */
-/* rssi_ifamp_gain_lut17 : m47 dBm */
-/* rssi_ifamp_gain_lut18 : m44 dBm */
-/* rssi_ifamp_gain_lut19 : m41 dBm */
-/* rssi_ifamp_gain_lut20 : m38 dBm */
-/* rssi_ifamp_gain_lut21 : m35 dBm */
-/* rssi_ifamp_gain_lut22 : m33 dBm */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT16_MASK 0x0003
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT16_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT17_MASK 0x000c
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT17_POS 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT18_MASK 0x0030
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT18_POS 4
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT19_MASK 0x00c0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT19_POS 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT20_MASK 0x0300
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT20_POS 8
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT21_MASK 0x0c00
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT21_POS 10
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT22_MASK 0x3000
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT22_POS 12
-#else
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT16_MASK 0x0003
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT16_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT16_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT16_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT16_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT16_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT16_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT16_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT17_MASK 0x000c
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT17_POS 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT17_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT17_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT17_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT17_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT17_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT17_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT18_MASK 0x0030
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT18_POS 4
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT18_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT18_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT18_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT18_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT18_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT18_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT19_MASK 0x00c0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT19_POS 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT19_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT19_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT19_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT19_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT19_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT19_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT20_MASK 0x0300
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT20_POS 8
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT20_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT20_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT20_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT20_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT20_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT20_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT21_MASK 0x0c00
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT21_POS 10
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT21_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT21_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT21_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT21_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT21_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT21_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT22_MASK 0x3000
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT22_POS 12
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT22_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT22_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT22_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT22_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT22_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RSSI_IFAMP_GAIN_LUT22_BLE_2_MASK 0x0
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rssi_ifamp_gain_lut16 : 2;
- unsigned int rssi_ifamp_gain_lut17 : 2;
- unsigned int rssi_ifamp_gain_lut18 : 2;
- unsigned int rssi_ifamp_gain_lut19 : 2;
- unsigned int rssi_ifamp_gain_lut20 : 2;
- unsigned int rssi_ifamp_gain_lut21 : 2;
- unsigned int rssi_ifamp_gain_lut22 : 2;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_rssi_ifamp_gain_lut2;
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT2_ADDR 0x4001d108
-
-
-/* rssi_aaf_gain_lut0 register */
-/*----------------------*/
-/* AAF gain lookup table part 0; entry is narrowband RSSI (Stored in configuration bank) */
-/* rssi_aaf_gain_lut0 : m98 dBm */
-/* rssi_aaf_gain_lut1 : m95 dBm */
-/* rssi_aaf_gain_lut2 : m92 dBm */
-/* rssi_aaf_gain_lut3 : m89 dBm */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT0_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT0_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT1_MASK 0x0038
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT1_POS 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT2_MASK 0x01c0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT2_POS 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT3_MASK 0x0e00
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT3_POS 9
-#else
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT0_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT0_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT0_ZB_2 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT0_ZB_2_MASK 0x6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT0_BLE_1 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT0_BLE_1_MASK 0x6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT0_BLE_2 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT0_BLE_2_MASK 0x6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT1_MASK 0x0038
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT1_POS 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT1_ZB_2 5
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT1_ZB_2_MASK 0x28
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT1_BLE_1 5
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT1_BLE_1_MASK 0x28
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT1_BLE_2 5
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT1_BLE_2_MASK 0x28
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT2_MASK 0x01c0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT2_POS 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT2_ZB_2 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT2_ZB_2_MASK 0xc0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT2_BLE_1 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT2_BLE_1_MASK 0xc0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT2_BLE_2 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT2_BLE_2_MASK 0xc0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT3_MASK 0x0e00
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT3_POS 9
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT3_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT3_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT3_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT3_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT3_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RSSI_AAF_GAIN_LUT3_BLE_2_MASK 0x0
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rssi_aaf_gain_lut0 : 3;
- unsigned int rssi_aaf_gain_lut1 : 3;
- unsigned int rssi_aaf_gain_lut2 : 3;
- unsigned int rssi_aaf_gain_lut3 : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_rssi_aaf_gain_lut0;
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_RST 0xee
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT0_ADDR 0x4001d10c
-
-
-/* rssi_aaf_gain_lut1 register */
-/*----------------------*/
-/* AAF gain lookup table part 1; entry is narrowband RSSI (Stored in configuration bank) */
-/* rssi_aaf_gain_lut4 : m86 dBm */
-/* rssi_aaf_gain_lut5 : m83 dBm */
-/* rssi_aaf_gain_lut6 : m80 dBm */
-/* rssi_aaf_gain_lut7 : m77 dBm */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT4_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT4_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT5_MASK 0x0038
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT5_POS 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT6_MASK 0x01c0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT6_POS 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT7_MASK 0x0e00
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT7_POS 9
-#else
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT4_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT4_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT4_ZB_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT4_ZB_2_MASK 0x2
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT4_BLE_1 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT4_BLE_1_MASK 0x2
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT4_BLE_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT4_BLE_2_MASK 0x2
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT5_MASK 0x0038
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT5_POS 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT5_ZB_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT5_ZB_2_MASK 0x10
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT5_BLE_1 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT5_BLE_1_MASK 0x10
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT5_BLE_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT5_BLE_2_MASK 0x10
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT6_MASK 0x01c0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT6_POS 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT6_ZB_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT6_ZB_2_MASK 0x80
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT6_BLE_1 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT6_BLE_1_MASK 0x80
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT6_BLE_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT6_BLE_2_MASK 0x80
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT7_MASK 0x0e00
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT7_POS 9
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT7_ZB_2 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT7_ZB_2_MASK 0xc00
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT7_BLE_1 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT7_BLE_1_MASK 0xc00
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT7_BLE_2 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RSSI_AAF_GAIN_LUT7_BLE_2_MASK 0xc00
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rssi_aaf_gain_lut4 : 3;
- unsigned int rssi_aaf_gain_lut5 : 3;
- unsigned int rssi_aaf_gain_lut6 : 3;
- unsigned int rssi_aaf_gain_lut7 : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_rssi_aaf_gain_lut1;
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_RST 0xc92
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT1_ADDR 0x4001d130
-
-
-/* rssi_aaf_gain_lut2 register */
-/*----------------------*/
-/* AAF gain lookup table part 2; entry is narrowband RSSI (Stored in configuration bank) */
-/* rssi_aaf_gain_lut8 : m74 dBm */
-/* rssi_aaf_gain_lut9 : m71 dBm */
-/* rssi_aaf_gain_lut10 : m68 dBm */
-/* rssi_aaf_gain_lut11 : m65 dBm */
-/* rssi_aaf_gain_lut12 : m62 dBm */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT8_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT8_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT9_MASK 0x0038
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT9_POS 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT10_MASK 0x01c0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT10_POS 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT11_MASK 0x0e00
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT11_POS 9
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT12_MASK 0x7000
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT12_POS 12
-#else
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT8_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT8_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT8_ZB_2 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT8_ZB_2_MASK 0x6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT8_BLE_1 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT8_BLE_1_MASK 0x6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT8_BLE_2 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT8_BLE_2_MASK 0x6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT9_MASK 0x0038
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT9_POS 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT9_ZB_2 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT9_ZB_2_MASK 0x30
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT9_BLE_1 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT9_BLE_1_MASK 0x30
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT9_BLE_2 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT9_BLE_2_MASK 0x30
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT10_MASK 0x01c0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT10_POS 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT10_ZB_2 4
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT10_ZB_2_MASK 0x100
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT10_BLE_1 4
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT10_BLE_1_MASK 0x100
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT10_BLE_2 4
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT10_BLE_2_MASK 0x100
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT11_MASK 0x0e00
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT11_POS 9
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT11_ZB_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT11_ZB_2_MASK 0x400
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT11_BLE_1 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT11_BLE_1_MASK 0x400
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT11_BLE_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT11_BLE_2_MASK 0x400
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT12_MASK 0x7000
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT12_POS 12
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT12_ZB_2 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT12_ZB_2_MASK 0x6000
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT12_BLE_1 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT12_BLE_1_MASK 0x6000
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT12_BLE_2 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RSSI_AAF_GAIN_LUT12_BLE_2_MASK 0x6000
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rssi_aaf_gain_lut8 : 3;
- unsigned int rssi_aaf_gain_lut9 : 3;
- unsigned int rssi_aaf_gain_lut10 : 3;
- unsigned int rssi_aaf_gain_lut11 : 3;
- unsigned int rssi_aaf_gain_lut12 : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_rssi_aaf_gain_lut2;
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_RST 0x6536
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT2_ADDR 0x4001d134
-
-
-/* rssi_aaf_gain_lut3 register */
-/*----------------------*/
-/* AAF gain lookup table part 3; entry is narrowband RSSI (Stored in configuration bank) */
-/* rssi_aaf_gain_lut13 : m59 dBm */
-/* rssi_aaf_gain_lut14 : m56 dBm */
-/* rssi_aaf_gain_lut15 : m53 dBm */
-/* rssi_aaf_gain_lut16 : m50 dBm */
-/* rssi_aaf_gain_lut17 : m47 dBm */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT13_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT13_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT14_MASK 0x0038
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT14_POS 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT15_MASK 0x01c0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT15_POS 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT16_MASK 0x0e00
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT16_POS 9
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT17_MASK 0x7000
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT17_POS 12
-#else
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT13_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT13_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT13_ZB_2 4
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT13_ZB_2_MASK 0x4
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT13_BLE_1 4
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT13_BLE_1_MASK 0x4
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT13_BLE_2 4
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT13_BLE_2_MASK 0x4
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT14_MASK 0x0038
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT14_POS 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT14_ZB_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT14_ZB_2_MASK 0x10
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT14_BLE_1 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT14_BLE_1_MASK 0x10
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT14_BLE_2 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT14_BLE_2_MASK 0x10
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT15_MASK 0x01c0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT15_POS 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT15_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT15_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT15_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT15_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT15_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT15_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT16_MASK 0x0e00
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT16_POS 9
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT16_ZB_2 1
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT16_ZB_2_MASK 0x200
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT16_BLE_1 1
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT16_BLE_1_MASK 0x200
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT16_BLE_2 1
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT16_BLE_2_MASK 0x200
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT17_MASK 0x7000
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT17_POS 12
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT17_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT17_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT17_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT17_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT17_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RSSI_AAF_GAIN_LUT17_BLE_2_MASK 0x0
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rssi_aaf_gain_lut13 : 3;
- unsigned int rssi_aaf_gain_lut14 : 3;
- unsigned int rssi_aaf_gain_lut15 : 3;
- unsigned int rssi_aaf_gain_lut16 : 3;
- unsigned int rssi_aaf_gain_lut17 : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_rssi_aaf_gain_lut3;
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_RST 0x214
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT3_ADDR 0x4001d138
-
-
-/* rssi_aaf_gain_lut4 register */
-/*----------------------*/
-/* AAF gain lookup table part 4; entry is narrowband RSSI (Stored in configuration bank) */
-/* rssi_aaf_gain_lut18 : m44 dBm */
-/* rssi_aaf_gain_lut19 : m41 dBm */
-/* rssi_aaf_gain_lut20 : m38 dBm */
-/* rssi_aaf_gain_lut21 : m35 dBm */
-/* rssi_aaf_gain_lut22 : m33 dBm */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT18_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT18_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT19_MASK 0x0038
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT19_POS 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT20_MASK 0x01c0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT20_POS 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT21_MASK 0x0e00
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT21_POS 9
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT22_MASK 0x7000
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT22_POS 12
-#else
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT18_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT18_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT18_ZB_2 5
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT18_ZB_2_MASK 0x5
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT18_BLE_1 5
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT18_BLE_1_MASK 0x5
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT18_BLE_2 5
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT18_BLE_2_MASK 0x5
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT19_MASK 0x0038
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT19_POS 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT19_ZB_2 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT19_ZB_2_MASK 0x18
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT19_BLE_1 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT19_BLE_1_MASK 0x18
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT19_BLE_2 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT19_BLE_2_MASK 0x18
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT20_MASK 0x01c0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT20_POS 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT20_ZB_2 1
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT20_ZB_2_MASK 0x40
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT20_BLE_1 1
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT20_BLE_1_MASK 0x40
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT20_BLE_2 1
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT20_BLE_2_MASK 0x40
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT21_MASK 0x0e00
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT21_POS 9
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT21_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT21_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT21_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT21_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT21_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT21_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT22_MASK 0x7000
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT22_POS 12
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT22_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT22_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT22_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT22_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT22_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RSSI_AAF_GAIN_LUT22_BLE_2_MASK 0x0
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rssi_aaf_gain_lut18 : 3;
- unsigned int rssi_aaf_gain_lut19 : 3;
- unsigned int rssi_aaf_gain_lut20 : 3;
- unsigned int rssi_aaf_gain_lut21 : 3;
- unsigned int rssi_aaf_gain_lut22 : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_rssi_aaf_gain_lut4;
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_RST 0x5d
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT4_ADDR 0x4001d13c
-
-
-/* lna_gain_lut0 register */
-/*----------------------*/
-/* LNA Gain0 */
-/* lna_gain_lut : LNA gain0 */
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_LUT0_LNA_GAIN_LUT_MASK 0x00ff
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_LUT0_LNA_GAIN_LUT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int lna_gain_lut : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_lna_gain_lut0;
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_LUT0_RST 0xac
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_LUT0_ADDR 0x4001d140
-
-
-/* lna_gain_lut1 register */
-/*----------------------*/
-/* LNA Gain1 */
-/* lna_gain_lut : LNA gain1 */
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_LUT1_LNA_GAIN_LUT_MASK 0x00ff
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_LUT1_LNA_GAIN_LUT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int lna_gain_lut : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_lna_gain_lut1;
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_LUT1_RST 0xdc
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_LUT1_ADDR 0x4001d144
-
-
-/* lna_gain_lut2 register */
-/*----------------------*/
-/* LNA Gain2 */
-/* lna_gain_lut : LNA gain2 */
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_LUT2_LNA_GAIN_LUT_MASK 0x00ff
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_LUT2_LNA_GAIN_LUT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int lna_gain_lut : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_lna_gain_lut2;
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_LUT2_RST 0xf4
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_LUT2_ADDR 0x4001d148
-
-
-/* lna_gain_lut3 register */
-/*----------------------*/
-/* LNA Gain3 */
-/* lna_gain_lut : LNA gain3 */
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_LUT3_LNA_GAIN_LUT_MASK 0x00ff
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_LUT3_LNA_GAIN_LUT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int lna_gain_lut : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_lna_gain_lut3;
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_LUT3_RST 0xc
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_LUT3_ADDR 0x4001d14c
-
-
-/* lna_gain_lut4 register */
-/*----------------------*/
-/* LNA Gain4 */
-/* lna_gain_lut : LNA gain4 */
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_LUT4_LNA_GAIN_LUT_MASK 0x00ff
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_LUT4_LNA_GAIN_LUT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int lna_gain_lut : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_lna_gain_lut4;
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_LUT4_RST 0x3c
-#define EXTAPB_REGFILE_RX_DP_LNA_GAIN_LUT4_ADDR 0x4001d150
-
-
-/* ifamp_gain_lut0 register */
-/*----------------------*/
-/* IFAMP gain values, required for RSSI calculation; column selector is ifamp_gain_setting. Values: 0..31.75 in steps of 0.25 dB */
-/* ifamp_gain_lut : IFAMP gain values, required for RSSI calculation; column selector is ifamp_gain_setting. Values: 0..31.75 in steps of 0.25 dB */
-#define EXTAPB_REGFILE_RX_DP_IFAMP_GAIN_LUT0_IFAMP_GAIN_LUT_MASK 0x007f
-#define EXTAPB_REGFILE_RX_DP_IFAMP_GAIN_LUT0_IFAMP_GAIN_LUT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int ifamp_gain_lut : 7;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_ifamp_gain_lut0;
-#define EXTAPB_REGFILE_RX_DP_IFAMP_GAIN_LUT0_RST 0x2
-#define EXTAPB_REGFILE_RX_DP_IFAMP_GAIN_LUT0_ADDR 0x4001d154
-
-
-/* ifamp_gain_lut1 register */
-/*----------------------*/
-/* IFAMP gain values, required for RSSI calculation; column selector is ifamp_gain_setting. Values: 0..31.75 in steps of 0.25 dB */
-/* ifamp_gain_lut : IFAMP gain values, required for RSSI calculation; column selector is ifamp_gain_setting. Values: 0..31.75 in steps of 0.25 dB */
-#define EXTAPB_REGFILE_RX_DP_IFAMP_GAIN_LUT1_IFAMP_GAIN_LUT_MASK 0x007f
-#define EXTAPB_REGFILE_RX_DP_IFAMP_GAIN_LUT1_IFAMP_GAIN_LUT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int ifamp_gain_lut : 7;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_ifamp_gain_lut1;
-#define EXTAPB_REGFILE_RX_DP_IFAMP_GAIN_LUT1_RST 0x32
-#define EXTAPB_REGFILE_RX_DP_IFAMP_GAIN_LUT1_ADDR 0x4001d158
-
-
-/* ifamp_gain_lut2 register */
-/*----------------------*/
-/* IFAMP gain values, required for RSSI calculation; column selector is ifamp_gain_setting. Values: 0..31.75 in steps of 0.25 dB */
-/* ifamp_gain_lut : IFAMP gain values, required for RSSI calculation; column selector is ifamp_gain_setting. Values: 0..31.75 in steps of 0.25 dB */
-#define EXTAPB_REGFILE_RX_DP_IFAMP_GAIN_LUT2_IFAMP_GAIN_LUT_MASK 0x007f
-#define EXTAPB_REGFILE_RX_DP_IFAMP_GAIN_LUT2_IFAMP_GAIN_LUT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int ifamp_gain_lut : 7;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_ifamp_gain_lut2;
-#define EXTAPB_REGFILE_RX_DP_IFAMP_GAIN_LUT2_RST 0x58
-#define EXTAPB_REGFILE_RX_DP_IFAMP_GAIN_LUT2_ADDR 0x4001d15c
-
-
-/* aaf_gain_lut0 register */
-/*----------------------*/
-/* AAF gain values, required for RSSI calculation; column selector is aaf_gain_setting (can be delayed with aaf_gain_delay). Values: 0..31.75 in steps of 0.25 dB */
-/* aaf_gain_lut : AAF gain values, required for RSSI calculation; column selector is aaf_gain_setting (can be delayed with aaf_gain_delay) Values: 0..31.75 in steps of 0.25 dB */
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_LUT0_AAF_GAIN_LUT_MASK 0x007f
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_LUT0_AAF_GAIN_LUT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aaf_gain_lut : 7;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_aaf_gain_lut0;
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_LUT0_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_LUT0_ADDR 0x4001d160
-
-
-/* aaf_gain_lut1 register */
-/*----------------------*/
-/* AAF gain values, required for RSSI calculation; column selector is aaf_gain_setting (can be delayed with aaf_gain_delay). Values: 0..31.75 in steps of 0.25 dB */
-/* aaf_gain_lut : AAF gain values, required for RSSI calculation; column selector is aaf_gain_setting (can be delayed with aaf_gain_delay) Values: 0..31.75 in steps of 0.25 dB */
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_LUT1_AAF_GAIN_LUT_MASK 0x007f
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_LUT1_AAF_GAIN_LUT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aaf_gain_lut : 7;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_aaf_gain_lut1;
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_LUT1_RST 0xc
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_LUT1_ADDR 0x4001d164
-
-
-/* aaf_gain_lut2 register */
-/*----------------------*/
-/* AAF gain values, required for RSSI calculation; column selector is aaf_gain_setting (can be delayed with aaf_gain_delay). Values: 0..31.75 in steps of 0.25 dB */
-/* aaf_gain_lut : AAF gain values, required for RSSI calculation; column selector is aaf_gain_setting (can be delayed with aaf_gain_delay) Values: 0..31.75 in steps of 0.25 dB */
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_LUT2_AAF_GAIN_LUT_MASK 0x007f
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_LUT2_AAF_GAIN_LUT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aaf_gain_lut : 7;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_aaf_gain_lut2;
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_LUT2_RST 0x18
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_LUT2_ADDR 0x4001d168
-
-
-/* aaf_gain_lut3 register */
-/*----------------------*/
-/* AAF gain values, required for RSSI calculation; column selector is aaf_gain_setting (can be delayed with aaf_gain_delay). Values: 0..31.75 in steps of 0.25 dB */
-/* aaf_gain_lut : AAF gain values, required for RSSI calculation; column selector is aaf_gain_setting (can be delayed with aaf_gain_delay) Values: 0..31.75 in steps of 0.25 dB */
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_LUT3_AAF_GAIN_LUT_MASK 0x007f
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_LUT3_AAF_GAIN_LUT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aaf_gain_lut : 7;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_aaf_gain_lut3;
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_LUT3_RST 0x24
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_LUT3_ADDR 0x4001d16c
-
-
-/* aaf_gain_lut4 register */
-/*----------------------*/
-/* AAF gain values, required for RSSI calculation; column selector is aaf_gain_setting (can be delayed with aaf_gain_delay). Values: 0..31.75 in steps of 0.25 dB */
-/* aaf_gain_lut : AAF gain values, required for RSSI calculation; column selector is aaf_gain_setting (can be delayed with aaf_gain_delay) Values: 0..31.75 in steps of 0.25 dB */
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_LUT4_AAF_GAIN_LUT_MASK 0x007f
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_LUT4_AAF_GAIN_LUT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aaf_gain_lut : 7;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_aaf_gain_lut4;
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_LUT4_RST 0x30
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_LUT4_ADDR 0x4001d170
-
-
-/* aaf_gain_lut5 register */
-/*----------------------*/
-/* AAF gain values, required for RSSI calculation; column selector is aaf_gain_setting (can be delayed with aaf_gain_delay). Values: 0..31.75 in steps of 0.25 dB */
-/* aaf_gain_lut : AAF gain values, required for RSSI calculation; column selector is aaf_gain_setting (can be delayed with aaf_gain_delay) Values: 0..31.75 in steps of 0.25 dB */
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_LUT5_AAF_GAIN_LUT_MASK 0x007f
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_LUT5_AAF_GAIN_LUT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aaf_gain_lut : 7;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_aaf_gain_lut5;
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_LUT5_RST 0x3c
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_LUT5_ADDR 0x4001d174
-
-
-/* aaf_gain_lut6 register */
-/*----------------------*/
-/* AAF gain values, required for RSSI calculation; column selector is aaf_gain_setting (can be delayed with aaf_gain_delay). Values: 0..31.75 in steps of 0.25 dB */
-/* aaf_gain_lut : AAF gain values, required for RSSI calculation; column selector is aaf_gain_setting (can be delayed with aaf_gain_delay) Values: 0..31.75 in steps of 0.25 dB */
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_LUT6_AAF_GAIN_LUT_MASK 0x007f
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_LUT6_AAF_GAIN_LUT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aaf_gain_lut : 7;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_aaf_gain_lut6;
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_LUT6_RST 0x48
-#define EXTAPB_REGFILE_RX_DP_AAF_GAIN_LUT6_ADDR 0x4001d178
-
-
-/* nb_rssi_conv_to_dbm register */
-/*----------------------*/
-/* Conversion factor for narrowband RSSI (including ADC gain, digital gain, conversion from dBV to dBm, systematic error introduced by truncations) Values: -128..0 in steps of 0.25 dB (Stored in configuration bank) */
-/* nb_rssi_conv_to_dbm : Conversion factor for narrowband RSSI (including ADC gain, digital gain, conversion from dBV to dBm, systematic error introduced by truncations) Values: -128..0 in steps of 0.25 dB */
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CONV_TO_DBM_NB_RSSI_CONV_TO_DBM_MASK 0x03ff
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CONV_TO_DBM_NB_RSSI_CONV_TO_DBM_POS 0
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#else
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CONV_TO_DBM_NB_RSSI_CONV_TO_DBM_ZB_2 712
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CONV_TO_DBM_NB_RSSI_CONV_TO_DBM_ZB_2_MASK 0x2c8
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CONV_TO_DBM_NB_RSSI_CONV_TO_DBM_BLE_1 712
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CONV_TO_DBM_NB_RSSI_CONV_TO_DBM_BLE_1_MASK 0x2c8
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CONV_TO_DBM_NB_RSSI_CONV_TO_DBM_BLE_2 712
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CONV_TO_DBM_NB_RSSI_CONV_TO_DBM_BLE_2_MASK 0x2c8
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nb_rssi_conv_to_dbm : 10;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_nb_rssi_conv_to_dbm;
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CONV_TO_DBM_RST 0x2c8
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CONV_TO_DBM_ADDR 0x4001d17c
-
-
-/* wb_rssi_conv_to_dbm register */
-/*----------------------*/
-/* Conversion factor for wideband RSSI (including ADC gain, digital gain, conversion from dBV to dBm, systematic error introduced by truncations) Values: -128..0 in steps of 0.5 dB (Stored in configuration bank) */
-/* wb_rssi_conv_to_dbm : Conversion factor for wideband RSSI (including ADC gain, digital gain, conversion from dBV to dBm, systematic error introduced by truncations) Values: -128..0 in steps of 0.5 dB */
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CONV_TO_DBM_WB_RSSI_CONV_TO_DBM_MASK 0x01ff
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CONV_TO_DBM_WB_RSSI_CONV_TO_DBM_POS 0
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#else
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CONV_TO_DBM_WB_RSSI_CONV_TO_DBM_ZB_2 387
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CONV_TO_DBM_WB_RSSI_CONV_TO_DBM_ZB_2_MASK 0x183
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CONV_TO_DBM_WB_RSSI_CONV_TO_DBM_BLE_1 387
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CONV_TO_DBM_WB_RSSI_CONV_TO_DBM_BLE_1_MASK 0x183
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CONV_TO_DBM_WB_RSSI_CONV_TO_DBM_BLE_2 387
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CONV_TO_DBM_WB_RSSI_CONV_TO_DBM_BLE_2_MASK 0x183
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int wb_rssi_conv_to_dbm : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_wb_rssi_conv_to_dbm;
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CONV_TO_DBM_RST 0x183
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CONV_TO_DBM_ADDR 0x4001d180
-
-
-/* wb_rssi_ctrl register */
-/*----------------------*/
-/* Wideband rssi settings (Stored in configuration bank) */
-/* alpha_wb_rssi : Wideband rssi lowpass filter constant. Value map: 4..10 -> 2**4..2**10 */
-/* wb_rssi_window : Window for wideband rssi averaging. Values: 0..1023 */
-/* wb_rssi_always_on : Enable wideband rssi measurement */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_ALPHA_WB_RSSI_MASK 0x000f
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_ALPHA_WB_RSSI_POS 0
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_WB_RSSI_WINDOW_MASK 0x3ff0
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_WB_RSSI_WINDOW_POS 4
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_WB_RSSI_ALWAYS_ON_MASK 0x4000
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_WB_RSSI_ALWAYS_ON_POS 14
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_WB_RSSI_ALWAYS_ON_OFF 0
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_WB_RSSI_ALWAYS_ON_OFF_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_WB_RSSI_ALWAYS_ON_ON 1
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_WB_RSSI_ALWAYS_ON_ON_MASK 0x4000
-#else
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_ALPHA_WB_RSSI_MASK 0x000f
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_ALPHA_WB_RSSI_POS 0
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_ALPHA_WB_RSSI_ZB_2 7
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_ALPHA_WB_RSSI_ZB_2_MASK 0x7
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_ALPHA_WB_RSSI_BLE_1 7
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_ALPHA_WB_RSSI_BLE_1_MASK 0x7
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_ALPHA_WB_RSSI_BLE_2 7
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_ALPHA_WB_RSSI_BLE_2_MASK 0x7
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_WB_RSSI_WINDOW_MASK 0x3ff0
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_WB_RSSI_WINDOW_POS 4
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_WB_RSSI_WINDOW_ZB_2 512
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_WB_RSSI_WINDOW_ZB_2_MASK 0x2000
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_WB_RSSI_WINDOW_BLE_1 512
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_WB_RSSI_WINDOW_BLE_1_MASK 0x2000
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_WB_RSSI_WINDOW_BLE_2 512
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_WB_RSSI_WINDOW_BLE_2_MASK 0x2000
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_WB_RSSI_ALWAYS_ON_MASK 0x4000
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_WB_RSSI_ALWAYS_ON_POS 14
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_WB_RSSI_ALWAYS_ON_OFF 0
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_WB_RSSI_ALWAYS_ON_OFF_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_WB_RSSI_ALWAYS_ON_ON 1
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_WB_RSSI_ALWAYS_ON_ON_MASK 0x4000
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_WB_RSSI_ALWAYS_ON_ZB_2 1
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_WB_RSSI_ALWAYS_ON_ZB_2_MASK 0x4000
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_WB_RSSI_ALWAYS_ON_BLE_1 1
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_WB_RSSI_ALWAYS_ON_BLE_1_MASK 0x4000
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_WB_RSSI_ALWAYS_ON_BLE_2 1
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_WB_RSSI_ALWAYS_ON_BLE_2_MASK 0x4000
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int alpha_wb_rssi : 4;
- unsigned int wb_rssi_window : 10;
- unsigned int wb_rssi_always_on : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_wb_rssi_ctrl;
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_RST 0x6007
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_CTRL_ADDR 0x4001d184
-
-
-/* wb_rssi_wakeup register */
-/*----------------------*/
-/* Wideband rssi wakeup. (Stored in configuration bank) */
-/* wb_rssi_wakeup : Threshold for wideband rssi wakeup Signed values: -128..0 [dBm] */
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_WAKEUP_WB_RSSI_WAKEUP_MASK 0x01ff
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_WAKEUP_WB_RSSI_WAKEUP_POS 0
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#else
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_WAKEUP_WB_RSSI_WAKEUP_ZB_2 412
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_WAKEUP_WB_RSSI_WAKEUP_ZB_2_MASK 0x19c
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_WAKEUP_WB_RSSI_WAKEUP_BLE_1 412
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_WAKEUP_WB_RSSI_WAKEUP_BLE_1_MASK 0x19c
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_WAKEUP_WB_RSSI_WAKEUP_BLE_2 412
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_WAKEUP_WB_RSSI_WAKEUP_BLE_2_MASK 0x19c
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int wb_rssi_wakeup : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_wb_rssi_wakeup;
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_WAKEUP_RST 0x19c
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_WAKEUP_ADDR 0x4001d188
-
-
-/* nb_rssi_wakeup register */
-/*----------------------*/
-/* Narrowband rssi wakeup. (Stored in configuration bank) */
-/* nb_rssi_wakeup : Threshold for narrowband rssi wakeup Signed values: -128..0 [dBm] */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_WAKEUP_NB_RSSI_WAKEUP_MASK 0x01ff
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_WAKEUP_NB_RSSI_WAKEUP_POS 0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_WAKEUP_NB_RSSI_WAKEUP_BT_LE_1 414
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_WAKEUP_NB_RSSI_WAKEUP_BT_LE_1_MASK 0x19e
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_WAKEUP_NB_RSSI_WAKEUP_BT_LE_2 416
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_WAKEUP_NB_RSSI_WAKEUP_BT_LE_2_MASK 0x1a0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_WAKEUP_NB_RSSI_WAKEUP_NORDIC_250 414
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_WAKEUP_NB_RSSI_WAKEUP_NORDIC_250_MASK 0x19e
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_WAKEUP_NB_RSSI_WAKEUP_NORDIC_2 416
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_WAKEUP_NB_RSSI_WAKEUP_NORDIC_2_MASK 0x1a0
-#else
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_WAKEUP_NB_RSSI_WAKEUP_MASK 0x01ff
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_WAKEUP_NB_RSSI_WAKEUP_POS 0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_WAKEUP_NB_RSSI_WAKEUP_ZB_2 412
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_WAKEUP_NB_RSSI_WAKEUP_ZB_2_MASK 0x19c
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_WAKEUP_NB_RSSI_WAKEUP_BLE_1 412
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_WAKEUP_NB_RSSI_WAKEUP_BLE_1_MASK 0x19c
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_WAKEUP_NB_RSSI_WAKEUP_BLE_2 412
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_WAKEUP_NB_RSSI_WAKEUP_BLE_2_MASK 0x19c
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nb_rssi_wakeup : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_nb_rssi_wakeup;
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_WAKEUP_RST 0x19c
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_WAKEUP_ADDR 0x4001d18c
-
-
-/* nb_rssi_ctrl1 register */
-/*----------------------*/
-/* Narrowband rssi control (timeout) (Stored in configuration bank) */
-/* alpha1_nb_rssi : Narrowband rssi lowpass filter timeout constant. Value map: 0..6 -> 2**0..2**6 */
-/* nb_rssi_timeout : Narrowband rssi lowpass filter timeout. Values: 0..8191 */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_ALPHA1_NB_RSSI_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_ALPHA1_NB_RSSI_POS 0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_NB_RSSI_TIMEOUT_MASK 0xfff8
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_NB_RSSI_TIMEOUT_POS 3
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_NB_RSSI_TIMEOUT_BT_LE_1 28
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_NB_RSSI_TIMEOUT_BT_LE_1_MASK 0xe0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_NB_RSSI_TIMEOUT_BT_LE_2 56
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_NB_RSSI_TIMEOUT_BT_LE_2_MASK 0x1c0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_NB_RSSI_TIMEOUT_NORDIC_250 28
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_NB_RSSI_TIMEOUT_NORDIC_250_MASK 0xe0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_NB_RSSI_TIMEOUT_NORDIC_2 56
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_NB_RSSI_TIMEOUT_NORDIC_2_MASK 0x1c0
-#else
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_ALPHA1_NB_RSSI_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_ALPHA1_NB_RSSI_POS 0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_ALPHA1_NB_RSSI_ZB_2 1
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_ALPHA1_NB_RSSI_ZB_2_MASK 0x1
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_ALPHA1_NB_RSSI_BLE_1 1
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_ALPHA1_NB_RSSI_BLE_1_MASK 0x1
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_ALPHA1_NB_RSSI_BLE_2 1
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_ALPHA1_NB_RSSI_BLE_2_MASK 0x1
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_NB_RSSI_TIMEOUT_MASK 0xfff8
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_NB_RSSI_TIMEOUT_POS 3
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_NB_RSSI_TIMEOUT_ZB_2 64
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_NB_RSSI_TIMEOUT_ZB_2_MASK 0x200
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_NB_RSSI_TIMEOUT_BLE_1 64
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_NB_RSSI_TIMEOUT_BLE_1_MASK 0x200
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_NB_RSSI_TIMEOUT_BLE_2 64
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_NB_RSSI_TIMEOUT_BLE_2_MASK 0x200
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int alpha1_nb_rssi : 3;
- unsigned int nb_rssi_timeout : 13;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_nb_rssi_ctrl1;
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_RST 0x201
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL1_ADDR 0x4001d190
-
-
-/* nb_rssi_ctrl2 register */
-/*----------------------*/
-/* Narrowband rssi control (window) (Stored in configuration bank) */
-/* nb_rssi_window : Narrowband rssi lowpass filter window. Values: 0..8191 */
-/* reset_nb_rssi_counter : Keep nb_RSSI_counter at zero before wakeup is detected. When this bit is low, the AGC and RSSI is backwards compatible with MRA1 */
-/* nb_rssi_wakeup_disable_sync_peak_search_en : Enable bit to disable the sync peak detection when the nb_rssi_wakeup drops below its detection threshold during sync peak detection. */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WINDOW_MASK 0x1fff
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WINDOW_POS 0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WINDOW_BT_LE_1 16
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WINDOW_BT_LE_1_MASK 0x10
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WINDOW_BT_LE_2 24
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WINDOW_BT_LE_2_MASK 0x18
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WINDOW_NORDIC_250 16
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WINDOW_NORDIC_250_MASK 0x10
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WINDOW_NORDIC_2 24
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WINDOW_NORDIC_2_MASK 0x18
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_RESET_NB_RSSI_COUNTER_MASK 0x2000
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_RESET_NB_RSSI_COUNTER_POS 13
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_RESET_NB_RSSI_COUNTER_DIS 0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_RESET_NB_RSSI_COUNTER_DIS_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_RESET_NB_RSSI_COUNTER_EN 1
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_RESET_NB_RSSI_COUNTER_EN_MASK 0x2000
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WAKEUP_DISABLE_SYNC_PEAK_SEARCH_EN_MASK 0x4000
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WAKEUP_DISABLE_SYNC_PEAK_SEARCH_EN_POS 14
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WAKEUP_DISABLE_SYNC_PEAK_SEARCH_EN_DIS 0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WAKEUP_DISABLE_SYNC_PEAK_SEARCH_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WAKEUP_DISABLE_SYNC_PEAK_SEARCH_EN_EN 1
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WAKEUP_DISABLE_SYNC_PEAK_SEARCH_EN_EN_MASK 0x4000
-#else
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WINDOW_MASK 0x1fff
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WINDOW_POS 0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WINDOW_ZB_2 16
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WINDOW_ZB_2_MASK 0x10
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WINDOW_BLE_1 16
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WINDOW_BLE_1_MASK 0x10
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WINDOW_BLE_2 16
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WINDOW_BLE_2_MASK 0x10
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_RESET_NB_RSSI_COUNTER_MASK 0x2000
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_RESET_NB_RSSI_COUNTER_POS 13
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_RESET_NB_RSSI_COUNTER_DIS 0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_RESET_NB_RSSI_COUNTER_DIS_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_RESET_NB_RSSI_COUNTER_EN 1
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_RESET_NB_RSSI_COUNTER_EN_MASK 0x2000
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_RESET_NB_RSSI_COUNTER_ZB_2 1
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_RESET_NB_RSSI_COUNTER_ZB_2_MASK 0x2000
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_RESET_NB_RSSI_COUNTER_BLE_1 1
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_RESET_NB_RSSI_COUNTER_BLE_1_MASK 0x2000
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_RESET_NB_RSSI_COUNTER_BLE_2 1
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_RESET_NB_RSSI_COUNTER_BLE_2_MASK 0x2000
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WAKEUP_DISABLE_SYNC_PEAK_SEARCH_EN_MASK 0x4000
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WAKEUP_DISABLE_SYNC_PEAK_SEARCH_EN_POS 14
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WAKEUP_DISABLE_SYNC_PEAK_SEARCH_EN_DIS 0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WAKEUP_DISABLE_SYNC_PEAK_SEARCH_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WAKEUP_DISABLE_SYNC_PEAK_SEARCH_EN_EN 1
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WAKEUP_DISABLE_SYNC_PEAK_SEARCH_EN_EN_MASK 0x4000
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WAKEUP_DISABLE_SYNC_PEAK_SEARCH_EN_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WAKEUP_DISABLE_SYNC_PEAK_SEARCH_EN_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WAKEUP_DISABLE_SYNC_PEAK_SEARCH_EN_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WAKEUP_DISABLE_SYNC_PEAK_SEARCH_EN_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WAKEUP_DISABLE_SYNC_PEAK_SEARCH_EN_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_NB_RSSI_WAKEUP_DISABLE_SYNC_PEAK_SEARCH_EN_BLE_2_MASK 0x0
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nb_rssi_window : 13;
- unsigned int reset_nb_rssi_counter : 1;
- unsigned int nb_rssi_wakeup_disable_sync_peak_search_en : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_nb_rssi_ctrl2;
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_RST 0x2010
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL2_ADDR 0x4001d194
-
-
-/* nb_rssi_ctrl3 register */
-/*----------------------*/
-/* Narrowband rssi control (scan mode) (Stored in configuration bank) */
-/* alpha2_nb_rssi : Narrowband rssi lowpass filter window constant. Value map: 3..9 -> 2**3..2**9 */
-/* alpha3_nb_rssi : Narrowband rssi lowpass filter (for scan mode) window constant. Value map: 3..7 => 2**3..2**7 */
-/* nb_rssi_wakeup_limit_en : Enable bit for slope limited wakeup RSSI. When this bit is low, the AGC and RSSI is backwards compatible with MRA1 */
-/* rssi_syncf_cordic_wakeup_limit : Slope limited wakeup RSSI */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ALPHA2_NB_RSSI_MASK 0x000f
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ALPHA2_NB_RSSI_POS 0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ALPHA2_NB_RSSI_BT_LE_1 3
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ALPHA2_NB_RSSI_BT_LE_1_MASK 0x3
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ALPHA2_NB_RSSI_BT_LE_2 2
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ALPHA2_NB_RSSI_BT_LE_2_MASK 0x2
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ALPHA2_NB_RSSI_NORDIC_250 3
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ALPHA2_NB_RSSI_NORDIC_250_MASK 0x3
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ALPHA2_NB_RSSI_NORDIC_2 2
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ALPHA2_NB_RSSI_NORDIC_2_MASK 0x2
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ALPHA3_NB_RSSI_MASK 0x0070
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ALPHA3_NB_RSSI_POS 4
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_NB_RSSI_WAKEUP_LIMIT_EN_MASK 0x0080
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_NB_RSSI_WAKEUP_LIMIT_EN_POS 7
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_NB_RSSI_WAKEUP_LIMIT_EN_DIS 0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_NB_RSSI_WAKEUP_LIMIT_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_NB_RSSI_WAKEUP_LIMIT_EN_EN 1
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_NB_RSSI_WAKEUP_LIMIT_EN_EN_MASK 0x80
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_RSSI_SYNCF_CORDIC_WAKEUP_LIMIT_MASK 0xff00
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_RSSI_SYNCF_CORDIC_WAKEUP_LIMIT_POS 8
-#else
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ALPHA2_NB_RSSI_MASK 0x000f
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ALPHA2_NB_RSSI_POS 0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ALPHA2_NB_RSSI_ZB_2 5
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ALPHA2_NB_RSSI_ZB_2_MASK 0x5
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ALPHA2_NB_RSSI_BLE_1 5
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ALPHA2_NB_RSSI_BLE_1_MASK 0x5
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ALPHA2_NB_RSSI_BLE_2 5
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ALPHA2_NB_RSSI_BLE_2_MASK 0x5
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ALPHA3_NB_RSSI_MASK 0x0070
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ALPHA3_NB_RSSI_POS 4
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ALPHA3_NB_RSSI_ZB_2 3
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ALPHA3_NB_RSSI_ZB_2_MASK 0x30
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ALPHA3_NB_RSSI_BLE_1 3
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ALPHA3_NB_RSSI_BLE_1_MASK 0x30
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ALPHA3_NB_RSSI_BLE_2 3
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ALPHA3_NB_RSSI_BLE_2_MASK 0x30
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_NB_RSSI_WAKEUP_LIMIT_EN_MASK 0x0080
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_NB_RSSI_WAKEUP_LIMIT_EN_POS 7
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_NB_RSSI_WAKEUP_LIMIT_EN_DIS 0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_NB_RSSI_WAKEUP_LIMIT_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_NB_RSSI_WAKEUP_LIMIT_EN_EN 1
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_NB_RSSI_WAKEUP_LIMIT_EN_EN_MASK 0x80
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_NB_RSSI_WAKEUP_LIMIT_EN_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_NB_RSSI_WAKEUP_LIMIT_EN_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_NB_RSSI_WAKEUP_LIMIT_EN_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_NB_RSSI_WAKEUP_LIMIT_EN_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_NB_RSSI_WAKEUP_LIMIT_EN_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_NB_RSSI_WAKEUP_LIMIT_EN_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_RSSI_SYNCF_CORDIC_WAKEUP_LIMIT_MASK 0xff00
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_RSSI_SYNCF_CORDIC_WAKEUP_LIMIT_POS 8
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_RSSI_SYNCF_CORDIC_WAKEUP_LIMIT_ZB_2 50
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_RSSI_SYNCF_CORDIC_WAKEUP_LIMIT_ZB_2_MASK 0x3200
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_RSSI_SYNCF_CORDIC_WAKEUP_LIMIT_BLE_1 50
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_RSSI_SYNCF_CORDIC_WAKEUP_LIMIT_BLE_1_MASK 0x3200
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_RSSI_SYNCF_CORDIC_WAKEUP_LIMIT_BLE_2 50
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_RSSI_SYNCF_CORDIC_WAKEUP_LIMIT_BLE_2_MASK 0x3200
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int alpha2_nb_rssi : 4;
- unsigned int alpha3_nb_rssi : 3;
- unsigned int nb_rssi_wakeup_limit_en : 1;
- unsigned int rssi_syncf_cordic_wakeup_limit : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_nb_rssi_ctrl3;
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_RST 0x3235
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_CTRL3_ADDR 0x4001d198
-
-
-/* nb_rssi_payload_ctrl register */
-/*----------------------*/
-/* Narrowband rssi payload control (Stored in configuration bank) */
-/* alpha_nb_rssi_payload : Narrowband rssi payload lowpass filter constant. Value map: 2..8 -> 2**2..2**8 */
-/* alpha_nb_rssi_pa_cal : Narrowband rssi payload lowpass filter constant during PA calibration. Value map: 2..8 -> 2**2..2**8 */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_PAYLOAD_CTRL_ALPHA_NB_RSSI_PAYLOAD_MASK 0x000f
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_PAYLOAD_CTRL_ALPHA_NB_RSSI_PAYLOAD_POS 0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_PAYLOAD_CTRL_ALPHA_NB_RSSI_PA_CAL_MASK 0x00f0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_PAYLOAD_CTRL_ALPHA_NB_RSSI_PA_CAL_POS 4
-#else
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_PAYLOAD_CTRL_ALPHA_NB_RSSI_PAYLOAD_MASK 0x000f
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_PAYLOAD_CTRL_ALPHA_NB_RSSI_PAYLOAD_POS 0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_PAYLOAD_CTRL_ALPHA_NB_RSSI_PAYLOAD_ZB_2 5
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_PAYLOAD_CTRL_ALPHA_NB_RSSI_PAYLOAD_ZB_2_MASK 0x5
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_PAYLOAD_CTRL_ALPHA_NB_RSSI_PAYLOAD_BLE_1 5
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_PAYLOAD_CTRL_ALPHA_NB_RSSI_PAYLOAD_BLE_1_MASK 0x5
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_PAYLOAD_CTRL_ALPHA_NB_RSSI_PAYLOAD_BLE_2 5
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_PAYLOAD_CTRL_ALPHA_NB_RSSI_PAYLOAD_BLE_2_MASK 0x5
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_PAYLOAD_CTRL_ALPHA_NB_RSSI_PA_CAL_MASK 0x00f0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_PAYLOAD_CTRL_ALPHA_NB_RSSI_PA_CAL_POS 4
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_PAYLOAD_CTRL_ALPHA_NB_RSSI_PA_CAL_ZB_2 4
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_PAYLOAD_CTRL_ALPHA_NB_RSSI_PA_CAL_ZB_2_MASK 0x40
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_PAYLOAD_CTRL_ALPHA_NB_RSSI_PA_CAL_BLE_1 4
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_PAYLOAD_CTRL_ALPHA_NB_RSSI_PA_CAL_BLE_1_MASK 0x40
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_PAYLOAD_CTRL_ALPHA_NB_RSSI_PA_CAL_BLE_2 4
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_PAYLOAD_CTRL_ALPHA_NB_RSSI_PA_CAL_BLE_2_MASK 0x40
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int alpha_nb_rssi_payload : 4;
- unsigned int alpha_nb_rssi_pa_cal : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_nb_rssi_payload_ctrl;
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_PAYLOAD_CTRL_RST 0x45
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_PAYLOAD_CTRL_ADDR 0x4001d19c
-
-
-/* nb_rssi_modem_ctrl register */
-/*----------------------*/
-/* Narrowband rssi modem control */
-/* nb_rssi_timeout : Narrowband rssi settling window. Values : 0?8191 */
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_MODEM_CTRL_NB_RSSI_TIMEOUT_MASK 0x1fff
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_MODEM_CTRL_NB_RSSI_TIMEOUT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nb_rssi_timeout : 13;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_nb_rssi_modem_ctrl;
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_MODEM_CTRL_RST 0x10
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_MODEM_CTRL_ADDR 0x4001d1a0
-
-
-/* mute_ctrl1 register */
-/*----------------------*/
-/* mute control (ADC output) (Stored in configuration bank) */
-/* mn_mute_enable : Control signal that enables muting the ADC output and/or correlator input following a change in mn_low_gain_setting */
-/* ifamp_mute_enable : Control signal that enables muting the ADC output and/or correlator input following an IFAMP gain change */
-/* mn_ifamp_adc_mute_time : Number of muted ADC samples following an IFAMP gain change or change in mn_low_gain_setting */
-/* aaf_mute_enable : Control signal that enables muting the ADC output following an AAF gain change */
-/* aaf_adc_mute_time : Number of muted ADC samples following an AAF gain change */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_MN_MUTE_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_MN_MUTE_ENABLE_POS 0
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_IFAMP_MUTE_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_IFAMP_MUTE_ENABLE_POS 1
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_MN_IFAMP_ADC_MUTE_TIME_MASK 0x00fc
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_MN_IFAMP_ADC_MUTE_TIME_POS 2
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_AAF_MUTE_ENABLE_MASK 0x0100
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_AAF_MUTE_ENABLE_POS 8
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_AAF_ADC_MUTE_TIME_MASK 0x7e00
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_AAF_ADC_MUTE_TIME_POS 9
-#else
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_MN_MUTE_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_MN_MUTE_ENABLE_POS 0
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_MN_MUTE_ENABLE_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_MN_MUTE_ENABLE_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_MN_MUTE_ENABLE_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_MN_MUTE_ENABLE_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_MN_MUTE_ENABLE_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_MN_MUTE_ENABLE_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_IFAMP_MUTE_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_IFAMP_MUTE_ENABLE_POS 1
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_IFAMP_MUTE_ENABLE_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_IFAMP_MUTE_ENABLE_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_IFAMP_MUTE_ENABLE_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_IFAMP_MUTE_ENABLE_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_IFAMP_MUTE_ENABLE_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_IFAMP_MUTE_ENABLE_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_MN_IFAMP_ADC_MUTE_TIME_MASK 0x00fc
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_MN_IFAMP_ADC_MUTE_TIME_POS 2
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_MN_IFAMP_ADC_MUTE_TIME_ZB_2 4
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_MN_IFAMP_ADC_MUTE_TIME_ZB_2_MASK 0x10
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_MN_IFAMP_ADC_MUTE_TIME_BLE_1 4
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_MN_IFAMP_ADC_MUTE_TIME_BLE_1_MASK 0x10
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_MN_IFAMP_ADC_MUTE_TIME_BLE_2 4
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_MN_IFAMP_ADC_MUTE_TIME_BLE_2_MASK 0x10
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_AAF_MUTE_ENABLE_MASK 0x0100
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_AAF_MUTE_ENABLE_POS 8
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_AAF_MUTE_ENABLE_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_AAF_MUTE_ENABLE_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_AAF_MUTE_ENABLE_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_AAF_MUTE_ENABLE_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_AAF_MUTE_ENABLE_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_AAF_MUTE_ENABLE_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_AAF_ADC_MUTE_TIME_MASK 0x7e00
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_AAF_ADC_MUTE_TIME_POS 9
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_AAF_ADC_MUTE_TIME_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_AAF_ADC_MUTE_TIME_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_AAF_ADC_MUTE_TIME_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_AAF_ADC_MUTE_TIME_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_AAF_ADC_MUTE_TIME_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_AAF_ADC_MUTE_TIME_BLE_2_MASK 0x0
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mn_mute_enable : 1;
- unsigned int ifamp_mute_enable : 1;
- unsigned int mn_ifamp_adc_mute_time : 6;
- unsigned int aaf_mute_enable : 1;
- unsigned int aaf_adc_mute_time : 6;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_mute_ctrl1;
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_RST 0x10
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL1_ADDR 0x4001d1a4
-
-
-/* mute_ctrl2 register */
-/*----------------------*/
-/* mute control (correlator input) (Stored in configuration bank) */
-/* corr_mute_enable : Control signal that enables muting the correlator input */
-/* corr_mute_delay : Delay for correlator input mute start */
-/* corr_mute_window_1 : Duration (number of (decimated) samples) of correlator input muting if IFAMP gain change is 1 step */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_ENABLE_POS 0
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_DELAY_MASK 0x007e
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_DELAY_POS 1
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_WINDOW_1_MASK 0x7f80
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_WINDOW_1_POS 7
-#else
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_ENABLE_POS 0
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_ENABLE_ZB_2 1
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_ENABLE_ZB_2_MASK 0x1
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_ENABLE_BLE_1 1
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_ENABLE_BLE_1_MASK 0x1
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_ENABLE_BLE_2 1
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_ENABLE_BLE_2_MASK 0x1
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_DELAY_MASK 0x007e
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_DELAY_POS 1
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_DELAY_ZB_2 10
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_DELAY_ZB_2_MASK 0x14
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_DELAY_BLE_1 10
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_DELAY_BLE_1_MASK 0x14
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_DELAY_BLE_2 10
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_DELAY_BLE_2_MASK 0x14
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_WINDOW_1_MASK 0x7f80
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_WINDOW_1_POS 7
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_WINDOW_1_ZB_2 24
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_WINDOW_1_ZB_2_MASK 0xc00
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_WINDOW_1_BLE_1 24
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_WINDOW_1_BLE_1_MASK 0xc00
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_WINDOW_1_BLE_2 24
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_CORR_MUTE_WINDOW_1_BLE_2_MASK 0xc00
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int corr_mute_enable : 1;
- unsigned int corr_mute_delay : 6;
- unsigned int corr_mute_window_1 : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_mute_ctrl2;
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_RST 0xc15
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL2_ADDR 0x4001d1a8
-
-
-/* mute_ctrl3 register */
-/*----------------------*/
-/* mute control (correlator input) (Stored in configuration bank) */
-/* corr_mute_window_2 : Duration (number of (decimated) samples) of correlator input muting if IFAMP gain change is 2 steps */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL3_CORR_MUTE_WINDOW_2_MASK 0x01ff
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL3_CORR_MUTE_WINDOW_2_POS 0
-#else
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL3_CORR_MUTE_WINDOW_2_MASK 0x01ff
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL3_CORR_MUTE_WINDOW_2_POS 0
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL3_CORR_MUTE_WINDOW_2_ZB_2 40
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL3_CORR_MUTE_WINDOW_2_ZB_2_MASK 0x28
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL3_CORR_MUTE_WINDOW_2_BLE_1 40
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL3_CORR_MUTE_WINDOW_2_BLE_1_MASK 0x28
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL3_CORR_MUTE_WINDOW_2_BLE_2 40
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL3_CORR_MUTE_WINDOW_2_BLE_2_MASK 0x28
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int corr_mute_window_2 : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_mute_ctrl3;
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL3_RST 0x28
-#define EXTAPB_REGFILE_RX_DP_MUTE_CTRL3_ADDR 0x4001d1ac
-
-
-/* ana_agc_bypass register */
-/*----------------------*/
-/* Control signals to bypass different parts of the analogue agc and use register values */
-/* clip_det_1 : Control signal to bypass clip detector 1 part of the analogue agc and use register values */
-/* clip_det_1_clip_override_enable : Enable bit to override ip_a2d_clipdet_hs_clip */
-/* clip_det_1_clip_override_value : Override value for ip_a2d_clipdet_hs_clip */
-/* clip_det_2 : Control signal to bypass clip detector 2 part of the analogue agc and use register values */
-/* clip_det_2_clip_override_enable : Enable bit to override ip_a2d_clipdet_ls_clip */
-/* clip_det_2_clip_override_value : Override value for ip_a2d_clipdet_ls_clip */
-/* clip_det_3 : Control signal to bypass clip detector 3 part of the analogue agc and use register values */
-/* ifamp : Control signal to bypass ifamp part of the analogue agc and use register values */
-/* aaf : Control signal to bypass aaf part of the analogue agc and use register values */
-/* rssi_wakeup : Control signal to bypass rssi wakeup part of the analogue agc and use register values */
-/* nb_rssi_lut : Control signal to bypass nb rssi lut part of the analogue agc and use register values */
-/* lna : Control signal to bypass lna part of the analogue agc and use register values */
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_CLIP_DET_1_MASK 0x0001
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_CLIP_DET_1_POS 0
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_CLIP_DET_1_DIS 0
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_CLIP_DET_1_DIS_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_CLIP_DET_1_EN 1
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_CLIP_DET_1_EN_MASK 0x1
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_CLIP_DET_1_CLIP_OVERRIDE_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_CLIP_DET_1_CLIP_OVERRIDE_ENABLE_POS 1
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_CLIP_DET_1_CLIP_OVERRIDE_VALUE_MASK 0x0004
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_CLIP_DET_1_CLIP_OVERRIDE_VALUE_POS 2
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_CLIP_DET_2_MASK 0x0008
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_CLIP_DET_2_POS 3
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_CLIP_DET_2_DIS 0
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_CLIP_DET_2_DIS_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_CLIP_DET_2_EN 1
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_CLIP_DET_2_EN_MASK 0x8
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_CLIP_DET_2_CLIP_OVERRIDE_ENABLE_MASK 0x0010
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_CLIP_DET_2_CLIP_OVERRIDE_ENABLE_POS 4
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_CLIP_DET_2_CLIP_OVERRIDE_VALUE_MASK 0x0020
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_CLIP_DET_2_CLIP_OVERRIDE_VALUE_POS 5
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_CLIP_DET_3_MASK 0x0040
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_CLIP_DET_3_POS 6
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_CLIP_DET_3_DIS 0
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_CLIP_DET_3_DIS_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_CLIP_DET_3_EN 1
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_CLIP_DET_3_EN_MASK 0x40
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_IFAMP_MASK 0x0080
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_IFAMP_POS 7
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_IFAMP_DIS 0
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_IFAMP_DIS_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_IFAMP_EN 1
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_IFAMP_EN_MASK 0x80
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_AAF_MASK 0x0100
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_AAF_POS 8
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_AAF_DIS 0
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_AAF_DIS_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_AAF_EN 1
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_AAF_EN_MASK 0x100
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_RSSI_WAKEUP_MASK 0x0200
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_RSSI_WAKEUP_POS 9
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_RSSI_WAKEUP_DIS 0
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_RSSI_WAKEUP_DIS_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_RSSI_WAKEUP_EN 1
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_RSSI_WAKEUP_EN_MASK 0x200
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_NB_RSSI_LUT_MASK 0x0400
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_NB_RSSI_LUT_POS 10
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_NB_RSSI_LUT_DIS 0
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_NB_RSSI_LUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_NB_RSSI_LUT_EN 1
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_NB_RSSI_LUT_EN_MASK 0x400
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_LNA_MASK 0x0800
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_LNA_POS 11
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_LNA_DIS 0
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_LNA_DIS_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_LNA_EN 1
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_LNA_EN_MASK 0x800
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int clip_det_1 : 1;
- unsigned int clip_det_1_clip_override_enable : 1;
- unsigned int clip_det_1_clip_override_value : 1;
- unsigned int clip_det_2 : 1;
- unsigned int clip_det_2_clip_override_enable : 1;
- unsigned int clip_det_2_clip_override_value : 1;
- unsigned int clip_det_3 : 1;
- unsigned int ifamp : 1;
- unsigned int aaf : 1;
- unsigned int rssi_wakeup : 1;
- unsigned int nb_rssi_lut : 1;
- unsigned int lna : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_ana_agc_bypass;
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_ANA_AGC_BYPASS_ADDR 0x4001d1b0
-
-
-/* agc_freeze_offset register */
-/*----------------------*/
-/* Number of symbols after the correlation start, to freeze the actual gain settings calculated by the agc state machine, in order to avoid transitions during the payload reception. Values: -16..15 */
-/* agc_link_freeze_offset : In link mode, number of symbols after the correlation start, to freeze the actual gain settings calculated by the agc state machine, in order to avoid transitions during the payload reception. Values: -16..15 */
-/* agc_scan_freeze_offset : In scan mode, number of symbols after the correlation start, to freeze the actual gain settings calculated by the agc state machine, in order to avoid transitions during the payload reception. Values: -16..15 */
-/* agc_scan_freeze_en : Enable bit for the agc_scan_freeze_offset. When this bit is low, the AGC is backwards compatible with MRA1 */
-#define EXTAPB_REGFILE_RX_DP_AGC_FREEZE_OFFSET_AGC_LINK_FREEZE_OFFSET_MASK 0x001f
-#define EXTAPB_REGFILE_RX_DP_AGC_FREEZE_OFFSET_AGC_LINK_FREEZE_OFFSET_POS 0
-#define EXTAPB_REGFILE_RX_DP_AGC_FREEZE_OFFSET_AGC_SCAN_FREEZE_OFFSET_MASK 0x03e0
-#define EXTAPB_REGFILE_RX_DP_AGC_FREEZE_OFFSET_AGC_SCAN_FREEZE_OFFSET_POS 5
-#define EXTAPB_REGFILE_RX_DP_AGC_FREEZE_OFFSET_AGC_SCAN_FREEZE_EN_MASK 0x0400
-#define EXTAPB_REGFILE_RX_DP_AGC_FREEZE_OFFSET_AGC_SCAN_FREEZE_EN_POS 10
-#define EXTAPB_REGFILE_RX_DP_AGC_FREEZE_OFFSET_AGC_SCAN_FREEZE_EN_DIS 0
-#define EXTAPB_REGFILE_RX_DP_AGC_FREEZE_OFFSET_AGC_SCAN_FREEZE_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_AGC_FREEZE_OFFSET_AGC_SCAN_FREEZE_EN_EN 1
-#define EXTAPB_REGFILE_RX_DP_AGC_FREEZE_OFFSET_AGC_SCAN_FREEZE_EN_EN_MASK 0x400
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int agc_link_freeze_offset : 5;
- unsigned int agc_scan_freeze_offset : 5;
- unsigned int agc_scan_freeze_en : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_agc_freeze_offset;
-#define EXTAPB_REGFILE_RX_DP_AGC_FREEZE_OFFSET_RST 0x42
-#define EXTAPB_REGFILE_RX_DP_AGC_FREEZE_OFFSET_ADDR 0x4001d1b4
-
-
-/* wb_rssi_dbm_run register */
-/*----------------------*/
-/* WB RSSI value readable when packet is received. (Snapshot register) */
-/* wb_rssi_dbm : Snapshot value */
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_DBM_RUN_WB_RSSI_DBM_MASK 0x01ff
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_DBM_RUN_WB_RSSI_DBM_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int wb_rssi_dbm : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_wb_rssi_dbm_run;
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_DBM_RUN_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_DBM_RUN_DYNAMIC true
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_DBM_RUN_SNAPCLOCK 1
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_DBM_RUN_ADDR 0x4001d1b8
-
-
-/* wb_rssi_dbm_sync register */
-/*----------------------*/
-/* WB RSSI value latched at end of sync phase */
-/* wb_rssi_dbm : See register description */
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_DBM_SYNC_WB_RSSI_DBM_MASK 0x01ff
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_DBM_SYNC_WB_RSSI_DBM_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int wb_rssi_dbm : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_wb_rssi_dbm_sync;
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_DBM_SYNC_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_DBM_SYNC_DYNAMIC true
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_DBM_SYNC_SNAPCLOCK 1
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_DBM_SYNC_ADDR 0x4001d1c0
-
-
-/* wb_rssi_dbm_packet register */
-/*----------------------*/
-/* WB RSSI value readable when packet is received */
-/* wb_rssi_dbm : See register description */
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_DBM_PACKET_WB_RSSI_DBM_MASK 0x01ff
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_DBM_PACKET_WB_RSSI_DBM_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int wb_rssi_dbm : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_wb_rssi_dbm_packet;
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_DBM_PACKET_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_DBM_PACKET_DYNAMIC true
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_DBM_PACKET_SNAPCLOCK 1
-#define EXTAPB_REGFILE_RX_DP_WB_RSSI_DBM_PACKET_ADDR 0x4001d1c4
-
-
-/* nb_rssi_dbm_run register */
-/*----------------------*/
-/* NB RSSI value readable when sync phase is still ongoing. (Snapshot register) */
-/* nb_rssi_dbm : Snapshot value of the NB RSSI */
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_DBM_RUN_NB_RSSI_DBM_MASK 0x03ff
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_DBM_RUN_NB_RSSI_DBM_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nb_rssi_dbm : 10;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_nb_rssi_dbm_run;
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_DBM_RUN_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_DBM_RUN_DYNAMIC true
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_DBM_RUN_SNAPCLOCK 1
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_DBM_RUN_ADDR 0x4001d1c8
-
-
-/* nb_rssi_agc_dbm_run register */
-/*----------------------*/
-/* NB RSSI value used by AGC readable when sync phase is still ongoing. (Snapshot register) */
-/* nb_rssi_dbm : Snapshot value of the NB RSSI */
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_AGC_DBM_RUN_NB_RSSI_DBM_MASK 0x03ff
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_AGC_DBM_RUN_NB_RSSI_DBM_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nb_rssi_dbm : 10;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_nb_rssi_agc_dbm_run;
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_AGC_DBM_RUN_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_AGC_DBM_RUN_DYNAMIC true
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_AGC_DBM_RUN_SNAPCLOCK 1
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_AGC_DBM_RUN_ADDR 0x4001d1cc
-
-
-/* nb_rssi_dbm_sync register */
-/*----------------------*/
-/* NB RSSI value latched at end of sync phase */
-/* nb_rssi_dbm : Latched value */
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_DBM_SYNC_NB_RSSI_DBM_MASK 0x03ff
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_DBM_SYNC_NB_RSSI_DBM_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nb_rssi_dbm : 10;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_nb_rssi_dbm_sync;
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_DBM_SYNC_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_DBM_SYNC_DYNAMIC true
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_DBM_SYNC_SNAPCLOCK 1
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_DBM_SYNC_ADDR 0x4001d1d0
-
-
-/* nb_rssi_agc_dbm_sync register */
-/*----------------------*/
-/* NB RSSI value used by AGC latched at end of sync phase */
-/* nb_rssi_dbm : Latched value */
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_AGC_DBM_SYNC_NB_RSSI_DBM_MASK 0x03ff
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_AGC_DBM_SYNC_NB_RSSI_DBM_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nb_rssi_dbm : 10;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_nb_rssi_agc_dbm_sync;
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_AGC_DBM_SYNC_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_AGC_DBM_SYNC_DYNAMIC true
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_AGC_DBM_SYNC_SNAPCLOCK 1
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_AGC_DBM_SYNC_ADDR 0x4001d1d4
-
-
-/* mf_rssi_dbm_run register */
-/*----------------------*/
-/* Matched Filter RSSI readable when data phase still ongoing. (Snapshot register) */
-/* mf_rssi_dbm : Snapshot value */
-#define EXTAPB_REGFILE_RX_DP_MF_RSSI_DBM_RUN_MF_RSSI_DBM_MASK 0x03ff
-#define EXTAPB_REGFILE_RX_DP_MF_RSSI_DBM_RUN_MF_RSSI_DBM_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mf_rssi_dbm : 10;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_mf_rssi_dbm_run;
-#define EXTAPB_REGFILE_RX_DP_MF_RSSI_DBM_RUN_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_MF_RSSI_DBM_RUN_DYNAMIC true
-#define EXTAPB_REGFILE_RX_DP_MF_RSSI_DBM_RUN_SNAPCLOCK 1
-#define EXTAPB_REGFILE_RX_DP_MF_RSSI_DBM_RUN_ADDR 0x4001d1d8
-
-
-/* mf_rssi_dbm_packet register */
-/*----------------------*/
-/* Matched Filter RSSI latched at the packet EOP */
-/* mf_rssi_dbm : Latched value */
-#define EXTAPB_REGFILE_RX_DP_MF_RSSI_DBM_PACKET_MF_RSSI_DBM_MASK 0x03ff
-#define EXTAPB_REGFILE_RX_DP_MF_RSSI_DBM_PACKET_MF_RSSI_DBM_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mf_rssi_dbm : 10;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_mf_rssi_dbm_packet;
-#define EXTAPB_REGFILE_RX_DP_MF_RSSI_DBM_PACKET_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_MF_RSSI_DBM_PACKET_DYNAMIC true
-#define EXTAPB_REGFILE_RX_DP_MF_RSSI_DBM_PACKET_SNAPCLOCK 1
-#define EXTAPB_REGFILE_RX_DP_MF_RSSI_DBM_PACKET_ADDR 0x4001d1dc
-
-
-/* dc_offset_i_packet register */
-/*----------------------*/
-/* DC offset compensation LP filter output at end of the packet. (I chain) */
-/* dc_offset_i : See register description. */
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_I_PACKET_DC_OFFSET_I_MASK 0x0fff
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_I_PACKET_DC_OFFSET_I_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int dc_offset_i : 12;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_dc_offset_i_packet;
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_I_PACKET_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_I_PACKET_DYNAMIC true
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_I_PACKET_SNAPCLOCK 1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_I_PACKET_ADDR 0x4001d1e0
-
-
-/* dc_offset_q_packet register */
-/*----------------------*/
-/* DC offset compensation LP filter output at end of the packet. (Q chain). */
-/* dc_offset_q : See register description. */
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_Q_PACKET_DC_OFFSET_Q_MASK 0x0fff
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_Q_PACKET_DC_OFFSET_Q_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int dc_offset_q : 12;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_dc_offset_q_packet;
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_Q_PACKET_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_Q_PACKET_DYNAMIC true
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_Q_PACKET_SNAPCLOCK 1
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_Q_PACKET_ADDR 0x4001d1e4
-
-
-/* agc_bypass_nb_rssi register */
-/*----------------------*/
-/* The measured nb rssi value (= input of the AGC) can optionally be bypassed by a register value */
-/* enable : Enable bit to bypass the measured nb rssi value (= input of the AGC) by a register value */
-/* value : Register value used when the measured nb rssi value (= input of the AGC) is bypassed */
-#define EXTAPB_REGFILE_RX_DP_AGC_BYPASS_NB_RSSI_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_RX_DP_AGC_BYPASS_NB_RSSI_ENABLE_POS 0
-#define EXTAPB_REGFILE_RX_DP_AGC_BYPASS_NB_RSSI_VALUE_MASK 0x07fe
-#define EXTAPB_REGFILE_RX_DP_AGC_BYPASS_NB_RSSI_VALUE_POS 1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int enable : 1;
- unsigned int value : 10;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_agc_bypass_nb_rssi;
-#define EXTAPB_REGFILE_RX_DP_AGC_BYPASS_NB_RSSI_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_AGC_BYPASS_NB_RSSI_ADDR 0x4001d1e8
-
-
-/* agc_out_run register */
-/*----------------------*/
-/* AGC outputs readable when sync phase is still ongoing. (Snapshot register) */
-/* ifamp_gain_set : IFAMP gain settings in operation. Snapshot value */
-/* aaf_gain_set : AAF gain settings in operation. Snapshot value */
-/* gain_lna : LNA gain settings in operation. Snapshot value */
-#define EXTAPB_REGFILE_RX_DP_AGC_OUT_RUN_IFAMP_GAIN_SET_MASK 0x0003
-#define EXTAPB_REGFILE_RX_DP_AGC_OUT_RUN_IFAMP_GAIN_SET_POS 0
-#define EXTAPB_REGFILE_RX_DP_AGC_OUT_RUN_AAF_GAIN_SET_MASK 0x001c
-#define EXTAPB_REGFILE_RX_DP_AGC_OUT_RUN_AAF_GAIN_SET_POS 2
-#define EXTAPB_REGFILE_RX_DP_AGC_OUT_RUN_GAIN_LNA_MASK 0x00e0
-#define EXTAPB_REGFILE_RX_DP_AGC_OUT_RUN_GAIN_LNA_POS 5
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int ifamp_gain_set : 2;
- unsigned int aaf_gain_set : 3;
- unsigned int gain_lna : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_agc_out_run;
-#define EXTAPB_REGFILE_RX_DP_AGC_OUT_RUN_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_AGC_OUT_RUN_DYNAMIC true
-#define EXTAPB_REGFILE_RX_DP_AGC_OUT_RUN_SNAPCLOCK 1
-#define EXTAPB_REGFILE_RX_DP_AGC_OUT_RUN_ADDR 0x4001d1ec
-
-
-/* agc_out_sync register */
-/*----------------------*/
-/* AGC outputs latched at end of sync phase */
-/* ifamp_gain_set : IFAMP gain settings at end of AGC operation. Latched value */
-/* aaf_gain_set : AAF gain settings at end of AGC operation. Latched value */
-/* gain_lna : LNA gain settins at end of AGC operation. Latched value */
-#define EXTAPB_REGFILE_RX_DP_AGC_OUT_SYNC_IFAMP_GAIN_SET_MASK 0x0003
-#define EXTAPB_REGFILE_RX_DP_AGC_OUT_SYNC_IFAMP_GAIN_SET_POS 0
-#define EXTAPB_REGFILE_RX_DP_AGC_OUT_SYNC_AAF_GAIN_SET_MASK 0x001c
-#define EXTAPB_REGFILE_RX_DP_AGC_OUT_SYNC_AAF_GAIN_SET_POS 2
-#define EXTAPB_REGFILE_RX_DP_AGC_OUT_SYNC_GAIN_LNA_MASK 0x00e0
-#define EXTAPB_REGFILE_RX_DP_AGC_OUT_SYNC_GAIN_LNA_POS 5
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int ifamp_gain_set : 2;
- unsigned int aaf_gain_set : 3;
- unsigned int gain_lna : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_agc_out_sync;
-#define EXTAPB_REGFILE_RX_DP_AGC_OUT_SYNC_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_AGC_OUT_SYNC_DYNAMIC true
-#define EXTAPB_REGFILE_RX_DP_AGC_OUT_SYNC_SNAPCLOCK 1
-#define EXTAPB_REGFILE_RX_DP_AGC_OUT_SYNC_ADDR 0x4001d1f0
-
-
-/* dc_offset_delay register */
-/*----------------------*/
-/* Delay (16 MHz cycles) between gain update from AGC and reset of DC offset compensation filter (Stored in configuration bank) */
-/* dc_offset_delay : Delay between gain update from AGC and reset of DC offset compensation filter */
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_DELAY_DC_OFFSET_DELAY_MASK 0x003f
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_DELAY_DC_OFFSET_DELAY_POS 0
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#else
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_DELAY_DC_OFFSET_DELAY_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_DELAY_DC_OFFSET_DELAY_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_DELAY_DC_OFFSET_DELAY_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_DELAY_DC_OFFSET_DELAY_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_DELAY_DC_OFFSET_DELAY_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_DELAY_DC_OFFSET_DELAY_BLE_2_MASK 0x0
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int dc_offset_delay : 6;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_dc_offset_delay;
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_DELAY_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_DC_OFFSET_DELAY_ADDR 0x4001d1f4
-
-
-/* wakeup_timeout register */
-/*----------------------*/
-/* Wakeup timeout (Stored in configuration bank) */
-/* wakeup_timeout : Wakeup timeout */
-#define EXTAPB_REGFILE_RX_DP_WAKEUP_TIMEOUT_WAKEUP_TIMEOUT_MASK 0x03ff
-#define EXTAPB_REGFILE_RX_DP_WAKEUP_TIMEOUT_WAKEUP_TIMEOUT_POS 0
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#else
-#define EXTAPB_REGFILE_RX_DP_WAKEUP_TIMEOUT_WAKEUP_TIMEOUT_ZB_2 160
-#define EXTAPB_REGFILE_RX_DP_WAKEUP_TIMEOUT_WAKEUP_TIMEOUT_ZB_2_MASK 0xa0
-#define EXTAPB_REGFILE_RX_DP_WAKEUP_TIMEOUT_WAKEUP_TIMEOUT_BLE_1 160
-#define EXTAPB_REGFILE_RX_DP_WAKEUP_TIMEOUT_WAKEUP_TIMEOUT_BLE_1_MASK 0xa0
-#define EXTAPB_REGFILE_RX_DP_WAKEUP_TIMEOUT_WAKEUP_TIMEOUT_BLE_2 160
-#define EXTAPB_REGFILE_RX_DP_WAKEUP_TIMEOUT_WAKEUP_TIMEOUT_BLE_2_MASK 0xa0
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int wakeup_timeout : 10;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_wakeup_timeout;
-#define EXTAPB_REGFILE_RX_DP_WAKEUP_TIMEOUT_RST 0xa0
-#define EXTAPB_REGFILE_RX_DP_WAKEUP_TIMEOUT_ADDR 0x4001d1f8
-
-
-/* nb_rssi_init_timeout register */
-/*----------------------*/
-/* NB RSSI timeout at start of packet (Stored in configuration bank) */
-/* nb_rssi_init_timeout : NB RSSI timeout at start of packet */
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_INIT_TIMEOUT_NB_RSSI_INIT_TIMEOUT_MASK 0x03ff
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_INIT_TIMEOUT_NB_RSSI_INIT_TIMEOUT_POS 0
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#else
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_INIT_TIMEOUT_NB_RSSI_INIT_TIMEOUT_ZB_2 160
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_INIT_TIMEOUT_NB_RSSI_INIT_TIMEOUT_ZB_2_MASK 0xa0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_INIT_TIMEOUT_NB_RSSI_INIT_TIMEOUT_BLE_1 160
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_INIT_TIMEOUT_NB_RSSI_INIT_TIMEOUT_BLE_1_MASK 0xa0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_INIT_TIMEOUT_NB_RSSI_INIT_TIMEOUT_BLE_2 160
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_INIT_TIMEOUT_NB_RSSI_INIT_TIMEOUT_BLE_2_MASK 0xa0
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nb_rssi_init_timeout : 10;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_nb_rssi_init_timeout;
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_INIT_TIMEOUT_RST 0xa0
-#define EXTAPB_REGFILE_RX_DP_NB_RSSI_INIT_TIMEOUT_ADDR 0x4001d1fc
-
-
-/* if_freq_norm register */
-/*----------------------*/
-/* Normalized IF frequency used in the frequency offset compensator - signed (3.5) (Stored in configuration bank) */
-/* if_freq_norm : Normalized IF frequency used in the frequency offset compensator - signed (3.5) */
-/* if_freq_norm_extended : Extension IF frequency to create signed (3.13) */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_IF_FREQ_NORM_IF_FREQ_NORM_MASK 0x00ff
-#define EXTAPB_REGFILE_RX_DP_IF_FREQ_NORM_IF_FREQ_NORM_POS 0
-#define EXTAPB_REGFILE_RX_DP_IF_FREQ_NORM_IF_FREQ_NORM_BT_LE_1 32
-#define EXTAPB_REGFILE_RX_DP_IF_FREQ_NORM_IF_FREQ_NORM_BT_LE_1_MASK 0x20
-#define EXTAPB_REGFILE_RX_DP_IF_FREQ_NORM_IF_FREQ_NORM_BT_LE_2 24
-#define EXTAPB_REGFILE_RX_DP_IF_FREQ_NORM_IF_FREQ_NORM_BT_LE_2_MASK 0x18
-#define EXTAPB_REGFILE_RX_DP_IF_FREQ_NORM_IF_FREQ_NORM_NORDIC_250 16
-#define EXTAPB_REGFILE_RX_DP_IF_FREQ_NORM_IF_FREQ_NORM_NORDIC_250_MASK 0x10
-#define EXTAPB_REGFILE_RX_DP_IF_FREQ_NORM_IF_FREQ_NORM_NORDIC_2 24
-#define EXTAPB_REGFILE_RX_DP_IF_FREQ_NORM_IF_FREQ_NORM_NORDIC_2_MASK 0x18
-#else
-#define EXTAPB_REGFILE_RX_DP_IF_FREQ_NORM_IF_FREQ_NORM_MASK 0x00ff
-#define EXTAPB_REGFILE_RX_DP_IF_FREQ_NORM_IF_FREQ_NORM_POS 0
-#define EXTAPB_REGFILE_RX_DP_IF_FREQ_NORM_IF_FREQ_NORM_ZB_2 240
-#define EXTAPB_REGFILE_RX_DP_IF_FREQ_NORM_IF_FREQ_NORM_ZB_2_MASK 0xf0
-#define EXTAPB_REGFILE_RX_DP_IF_FREQ_NORM_IF_FREQ_NORM_BLE_1 240
-#define EXTAPB_REGFILE_RX_DP_IF_FREQ_NORM_IF_FREQ_NORM_BLE_1_MASK 0xf0
-#define EXTAPB_REGFILE_RX_DP_IF_FREQ_NORM_IF_FREQ_NORM_BLE_2 240
-#define EXTAPB_REGFILE_RX_DP_IF_FREQ_NORM_IF_FREQ_NORM_BLE_2_MASK 0xf0
-#define EXTAPB_REGFILE_RX_DP_IF_FREQ_NORM_IF_FREQ_NORM_EXTENDED_MASK 0xff00
-#define EXTAPB_REGFILE_RX_DP_IF_FREQ_NORM_IF_FREQ_NORM_EXTENDED_POS 8
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int if_freq_norm : 8;
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
- /* ES1 if explicitly configured */
-#else
- /* ES2 default */
- unsigned int if_freq_norm_extended : 8;
-#endif
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_if_freq_norm;
-#define EXTAPB_REGFILE_RX_DP_IF_FREQ_NORM_RST 0xf0
-#define EXTAPB_REGFILE_RX_DP_IF_FREQ_NORM_ADDR 0x4001d200
-
-
-/* correlator_start_link register */
-/*----------------------*/
-/* Number of symbols at the beginning of a packet for which the correlator does not calculate the result (Stored in configuration bank) */
-/* correlator_start_link : Number of symbols at the beginning of a packet for which the correlator does not calculate the result */
-#define EXTAPB_REGFILE_RX_DP_CORRELATOR_START_LINK_CORRELATOR_START_LINK_MASK 0xffff
-#define EXTAPB_REGFILE_RX_DP_CORRELATOR_START_LINK_CORRELATOR_START_LINK_POS 0
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#else
-#define EXTAPB_REGFILE_RX_DP_CORRELATOR_START_LINK_CORRELATOR_START_LINK_ZB_2 35
-#define EXTAPB_REGFILE_RX_DP_CORRELATOR_START_LINK_CORRELATOR_START_LINK_ZB_2_MASK 0x23
-#define EXTAPB_REGFILE_RX_DP_CORRELATOR_START_LINK_CORRELATOR_START_LINK_BLE_1 35
-#define EXTAPB_REGFILE_RX_DP_CORRELATOR_START_LINK_CORRELATOR_START_LINK_BLE_1_MASK 0x23
-#define EXTAPB_REGFILE_RX_DP_CORRELATOR_START_LINK_CORRELATOR_START_LINK_BLE_2 35
-#define EXTAPB_REGFILE_RX_DP_CORRELATOR_START_LINK_CORRELATOR_START_LINK_BLE_2_MASK 0x23
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int correlator_start_link : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_correlator_start_link;
-#define EXTAPB_REGFILE_RX_DP_CORRELATOR_START_LINK_RST 0x23
-#define EXTAPB_REGFILE_RX_DP_CORRELATOR_START_LINK_ADDR 0x4001d204
-
-
-/* correlator_start_scan register */
-/*----------------------*/
-/* Number of symbols at the beginning of a packet for which the correlator does not calculate the result (Stored in configuration bank) */
-/* correlator_start_scan : Number of symbols at the beginning of a packet for which the correlator does not calculate the result */
-#define EXTAPB_REGFILE_RX_DP_CORRELATOR_START_SCAN_CORRELATOR_START_SCAN_MASK 0xffff
-#define EXTAPB_REGFILE_RX_DP_CORRELATOR_START_SCAN_CORRELATOR_START_SCAN_POS 0
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#else
-#define EXTAPB_REGFILE_RX_DP_CORRELATOR_START_SCAN_CORRELATOR_START_SCAN_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_CORRELATOR_START_SCAN_CORRELATOR_START_SCAN_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_CORRELATOR_START_SCAN_CORRELATOR_START_SCAN_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_CORRELATOR_START_SCAN_CORRELATOR_START_SCAN_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_CORRELATOR_START_SCAN_CORRELATOR_START_SCAN_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_CORRELATOR_START_SCAN_CORRELATOR_START_SCAN_BLE_2_MASK 0x0
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int correlator_start_scan : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_correlator_start_scan;
-#define EXTAPB_REGFILE_RX_DP_CORRELATOR_START_SCAN_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_CORRELATOR_START_SCAN_ADDR 0x4001d208
-
-
-/* rssi_lna_gain_lut0 register */
-/*----------------------*/
-/* lna gain lookup table part 0; entry is narrowband RSSI (Stored in configuration bank) */
-/* rssi_lna_gain_lut0 : m98 dBm */
-/* rssi_lna_gain_lut1 : m95 dBm */
-/* rssi_lna_gain_lut2 : m92 dBm */
-/* rssi_lna_gain_lut3 : m89 dBm */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT0_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT0_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT1_MASK 0x0038
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT1_POS 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT2_MASK 0x01c0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT2_POS 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT3_MASK 0x0e00
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT3_POS 9
-#else
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT0_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT0_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT0_ZB_2 4
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT0_ZB_2_MASK 0x4
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT0_BLE_1 4
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT0_BLE_1_MASK 0x4
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT0_BLE_2 4
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT0_BLE_2_MASK 0x4
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT1_MASK 0x0038
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT1_POS 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT1_ZB_2 4
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT1_ZB_2_MASK 0x20
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT1_BLE_1 4
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT1_BLE_1_MASK 0x20
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT1_BLE_2 4
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT1_BLE_2_MASK 0x20
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT2_MASK 0x01c0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT2_POS 6
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT2_ZB_2 4
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT2_ZB_2_MASK 0x100
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT2_BLE_1 4
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT2_BLE_1_MASK 0x100
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT2_BLE_2 4
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT2_BLE_2_MASK 0x100
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT3_MASK 0x0e00
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT3_POS 9
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT3_ZB_2 4
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT3_ZB_2_MASK 0x800
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT3_BLE_1 4
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT3_BLE_1_MASK 0x800
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT3_BLE_2 4
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RSSI_LNA_GAIN_LUT3_BLE_2_MASK 0x800
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rssi_lna_gain_lut0 : 3;
- unsigned int rssi_lna_gain_lut1 : 3;
- unsigned int rssi_lna_gain_lut2 : 3;
- unsigned int rssi_lna_gain_lut3 : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_rssi_lna_gain_lut0;
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_RST 0x924
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT0_ADDR 0x4001d210
-
-
-/* clip_det_1_timeout register */
-/*----------------------*/
-/* Timeout following a clipping detection during which clipping events are ignored and further gain reduction of the LNA is blocked. (Stored in configuration bank) */
-/* clip_det_1_timeout : Timeout following a clipping detection during which clipping events are ignored and further gain reduction of the LNA is blocked */
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_TIMEOUT_CLIP_DET_1_TIMEOUT_MASK 0x003f
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_TIMEOUT_CLIP_DET_1_TIMEOUT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int clip_det_1_timeout : 6;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_clip_det_1_timeout;
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_TIMEOUT_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_CLIP_DET_1_TIMEOUT_ADDR 0x4001d220
-
-
-/* agc_ctrl1 register */
-/*----------------------*/
-/* AGC control 1 */
-/* compifaaf_det2 : When Ifamp gain is too low to decrease with det2, then increase AAF gain instead */
-/* compifaaf_det3 : When AAF gain is too low to decrease with det3, then decrease Ifamp gain instead */
-/* thres_rfp : threshold on gains to select middle or msb after rfp */
-/* scale_rfp : enable autorescale output data from rfp for BLE */
-/* offset_max_adc : offset from max adc to detect the cliping det 3 */
-/* restrict_lut : restrict lut table management when set to 1, else gains only driven with clippng detectors */
-/* enable_lut : enable lut table management when set to 1, else gains only driven with clippng detectors */
-/* en_clip_rst_on_gfreeze : enable the possibility to reset cliping hs and ls when agc_freeze during 1 clock 16 Mhz */
-/* en_clip_rst_on_timeout : enable the possibility to reset cliping hs and ls during timeout_clip1 or 2 instead of waiting rising_edge cliping detection */
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL1_COMPIFAAF_DET2_MASK 0x0001
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL1_COMPIFAAF_DET2_POS 0
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL1_COMPIFAAF_DET3_MASK 0x0002
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL1_COMPIFAAF_DET3_POS 1
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL1_THRES_RFP_MASK 0x003c
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL1_THRES_RFP_POS 2
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL1_SCALE_RFP_MASK 0x0040
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL1_SCALE_RFP_POS 6
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL1_OFFSET_MAX_ADC_MASK 0x0780
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL1_OFFSET_MAX_ADC_POS 7
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL1_RESTRICT_LUT_MASK 0x1800
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL1_RESTRICT_LUT_POS 11
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL1_ENABLE_LUT_MASK 0x2000
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL1_ENABLE_LUT_POS 13
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL1_EN_CLIP_RST_ON_GFREEZE_MASK 0x4000
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL1_EN_CLIP_RST_ON_GFREEZE_POS 14
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#else
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL1_EN_CLIP_RST_ON_TIMEOUT_MASK 0x8000
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL1_EN_CLIP_RST_ON_TIMEOUT_POS 15
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int compifaaf_det2 : 1;
- unsigned int compifaaf_det3 : 1;
- unsigned int thres_rfp : 4;
- unsigned int scale_rfp : 1;
- unsigned int offset_max_adc : 4;
- unsigned int restrict_lut : 2;
- unsigned int enable_lut : 1;
- unsigned int en_clip_rst_on_gfreeze : 1;
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#else
- unsigned int en_clip_rst_on_timeout : 1;
-#endif
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_agc_ctrl1;
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL1_RST 0x2028
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL1_ADDR 0x4001d224
-
-
-/* agc_ctrl2 register */
-/*----------------------*/
-/* AGC control 2 */
-/* cliphs_end : When Ifamp gain is too low to decrease with det2, then increase AAF gain instead */
-/* clipls_end : When Ifamp gain is too low to decrease with det2, then increase AAF gain instead */
-/* reinit_on_clip : During clipping sequence lna,if,aaf, if a previous clip occur, then reset all gain to max */
-/* window_mode_clip3 : When set to '2' change aaf gain based on window new method (all gains in one step), when set to '1' change aaf change aaf gain based on window method, else change step by step on each ADC saturationgain based on window method */
-/* extend_nbrssi : enable possibility to recompute rssi when agc just freeze and apply lut */
-/* clipone_nbrssi : enable possibility to compute rssi only once after clipping */
-/* extend_time1up : enable possibility to activate timer1_up to allow max gains when gains changes , not only clip hs */
-/* en_aaf_always_lsclip : enable the possibility to modify ifamp gains even if hs_clip always happens and lna_gain=0 */
-/* en_if_always_hsclip : enable the possibility to modify aaf gains even if ls_clip always happens and if_gain=0 */
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL2_CLIPHS_END_MASK 0x000f
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL2_CLIPHS_END_POS 0
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL2_CLIPLS_END_MASK 0x00f0
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL2_CLIPLS_END_POS 4
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL2_REINIT_ON_CLIP_MASK 0x0100
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL2_REINIT_ON_CLIP_POS 8
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL2_WINDOW_MODE_CLIP3_MASK 0x0600
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL2_WINDOW_MODE_CLIP3_POS 9
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL2_EXTEND_NBRSSI_MASK 0x0800
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL2_EXTEND_NBRSSI_POS 11
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL2_CLIPONE_NBRSSI_MASK 0x1000
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL2_CLIPONE_NBRSSI_POS 12
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL2_EXTEND_TIME1UP_MASK 0x2000
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL2_EXTEND_TIME1UP_POS 13
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL2_EN_AAF_ALWAYS_LSCLIP_MASK 0x4000
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL2_EN_AAF_ALWAYS_LSCLIP_POS 14
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL2_EN_IF_ALWAYS_HSCLIP_MASK 0x8000
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL2_EN_IF_ALWAYS_HSCLIP_POS 15
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int cliphs_end : 4;
- unsigned int clipls_end : 4;
- unsigned int reinit_on_clip : 1;
- unsigned int window_mode_clip3 : 2;
- unsigned int extend_nbrssi : 1;
- unsigned int clipone_nbrssi : 1;
- unsigned int extend_time1up : 1;
- unsigned int en_aaf_always_lsclip : 1;
- unsigned int en_if_always_hsclip : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_agc_ctrl2;
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL2_RST 0x155
-#define EXTAPB_REGFILE_RX_DP_AGC_CTRL2_ADDR 0x4001d228
-
-
-/* agc_reset register */
-/*----------------------*/
-/* agc_wificm_reset */
-/* reinit_cpt_wificm : wifi stats, reinit gain counters each time reg_nb_measure is reached and gain is still forced */
-/* rst_wificm : reset wifi detectors counter gains and gain_lna is released */
-#define EXTAPB_REGFILE_RX_DP_AGC_RESET_REINIT_CPT_WIFICM_MASK 0x0001
-#define EXTAPB_REGFILE_RX_DP_AGC_RESET_REINIT_CPT_WIFICM_POS 0
-#define EXTAPB_REGFILE_RX_DP_AGC_RESET_RST_WIFICM_MASK 0x0002
-#define EXTAPB_REGFILE_RX_DP_AGC_RESET_RST_WIFICM_POS 1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int reinit_cpt_wificm : 1;
- unsigned int rst_wificm : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_agc_reset;
-#define EXTAPB_REGFILE_RX_DP_AGC_RESET_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_AGC_RESET_ADDR 0x4001d22c
-
-
-/* agc_wificm_conf register */
-/*----------------------*/
-/* agc_wificm_conf */
-/* keep_prev_gain : keep gain from previous packet in retetion flop for lna, if, aaf */
-/* nb_measure : number of measures needed (2**(nb_measure+2)) to computed the optimum gain */
-/* mode_agcvalid : in wifi stats, counter is based on agc_valid info, when set to 1 else on timeout_wificm when set to 0 */
-/* en_prot_lna : apply gain result from wifi_stats algo to analog lna gain */
-/* en_prot_ifamp : apply gain result from wifi_stats algo to analog ifamp gain */
-/* en_wificm : enable wifi detector bloc */
-/* dis_init_cpt_ret : disable wifi retention flop initialisation */
-/* dis_init_ret : disable wifi gain counter retention flop initialisation */
-/* dis_gupdate : disable update forced gain during all measures , only applied first measure */
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_CONF_KEEP_PREV_GAIN_MASK 0x0001
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_CONF_KEEP_PREV_GAIN_POS 0
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_CONF_NB_MEASURE_MASK 0x001e
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_CONF_NB_MEASURE_POS 1
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_CONF_MODE_AGCVALID_MASK 0x0020
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_CONF_MODE_AGCVALID_POS 5
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_CONF_EN_PROT_LNA_MASK 0x0040
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_CONF_EN_PROT_LNA_POS 6
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_CONF_EN_PROT_IFAMP_MASK 0x0080
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_CONF_EN_PROT_IFAMP_POS 7
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_CONF_EN_WIFICM_MASK 0x0100
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_CONF_EN_WIFICM_POS 8
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_CONF_DIS_INIT_CPT_RET_MASK 0x0200
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_CONF_DIS_INIT_CPT_RET_POS 9
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_CONF_DIS_INIT_RET_MASK 0x0400
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_CONF_DIS_INIT_RET_POS 10
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_CONF_DIS_GUPDATE_MASK 0x0800
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_CONF_DIS_GUPDATE_POS 11
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int keep_prev_gain : 1;
- unsigned int nb_measure : 4;
- unsigned int mode_agcvalid : 1;
- unsigned int en_prot_lna : 1;
- unsigned int en_prot_ifamp : 1;
- unsigned int en_wificm : 1;
- unsigned int dis_init_cpt_ret : 1;
- unsigned int dis_init_ret : 1;
- unsigned int dis_gupdate : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_agc_wificm_conf;
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_CONF_RST 0x22
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_CONF_ADDR 0x4001d230
-
-
-/* agc_wificm_gain register */
-/*----------------------*/
-/* agc_wificm_gain */
-/* set_soft_gain : force lna gain and ifamp gain with soft_glna and soft_gifamp_when set to 1 */
-/* soft_glna : reg_soft_glna */
-/* soft_gifamp : reg_soft_gifamp */
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_GAIN_SET_SOFT_GAIN_MASK 0x0001
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_GAIN_SET_SOFT_GAIN_POS 0
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_GAIN_SOFT_GLNA_MASK 0x000e
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_GAIN_SOFT_GLNA_POS 1
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_GAIN_SOFT_GIFAMP_MASK 0x0030
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_GAIN_SOFT_GIFAMP_POS 4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int set_soft_gain : 1;
- unsigned int soft_glna : 3;
- unsigned int soft_gifamp : 2;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_agc_wificm_gain;
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_GAIN_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_GAIN_ADDR 0x4001d234
-
-
-/* agc_wificm_tout register */
-/*----------------------*/
-/* agc_wificm_tout */
-/* timeout_wificm : maximum time in multiple of 62.5 ns to do one measure when reg_mode_agcvalid = 0 */
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_TOUT_TIMEOUT_WIFICM_MASK 0xffff
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_TOUT_TIMEOUT_WIFICM_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int timeout_wificm : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_agc_wificm_tout;
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_TOUT_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_TOUT_ADDR 0x4001d238
-
-
-/* agc_wificm_fgain register */
-/*----------------------*/
-/* agc_wificm number of forced gains consecutively applied */
-/* nb_forced_gain : maximum time in multiple of 62.5 ns to do one measure when reg_mode_agcvalid = 0 */
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_FGAIN_NB_FORCED_GAIN_MASK 0x00ff
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_FGAIN_NB_FORCED_GAIN_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nb_forced_gain : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_agc_wificm_fgain;
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_FGAIN_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_FGAIN_ADDR 0x4001d23c
-
-
-/* agc_wificm_th register */
-/*----------------------*/
-/* agc_wificm_th */
-/* thres_glna : threshold value used */
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_TH_THRES_GLNA_MASK 0x01ff
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_TH_THRES_GLNA_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int thres_glna : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_agc_wificm_th;
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_TH_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_AGC_WIFICM_TH_ADDR 0x4001d240
-
-
-/* agc_obs register */
-/*----------------------*/
-/* agc_obs */
-/* clip_hs_ana : HS clip form radio */
-/* clip_ls_ana : LS clip from radio */
-/* clip_hs_dig : HS clip after resync */
-/* clip_ls_dig : LS clip after resync */
-#define EXTAPB_REGFILE_RX_DP_AGC_OBS_CLIP_HS_ANA_MASK 0x0001
-#define EXTAPB_REGFILE_RX_DP_AGC_OBS_CLIP_HS_ANA_POS 0
-#define EXTAPB_REGFILE_RX_DP_AGC_OBS_CLIP_LS_ANA_MASK 0x0002
-#define EXTAPB_REGFILE_RX_DP_AGC_OBS_CLIP_LS_ANA_POS 1
-#define EXTAPB_REGFILE_RX_DP_AGC_OBS_CLIP_HS_DIG_MASK 0x0004
-#define EXTAPB_REGFILE_RX_DP_AGC_OBS_CLIP_HS_DIG_POS 2
-#define EXTAPB_REGFILE_RX_DP_AGC_OBS_CLIP_LS_DIG_MASK 0x0008
-#define EXTAPB_REGFILE_RX_DP_AGC_OBS_CLIP_LS_DIG_POS 3
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int clip_hs_ana : 1;
- unsigned int clip_ls_ana : 1;
- unsigned int clip_hs_dig : 1;
- unsigned int clip_ls_dig : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_agc_obs;
-#define EXTAPB_REGFILE_RX_DP_AGC_OBS_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_AGC_OBS_DYNAMIC true
-#define EXTAPB_REGFILE_RX_DP_AGC_OBS_SNAPCLOCK 1
-#define EXTAPB_REGFILE_RX_DP_AGC_OBS_ADDR 0x4001d244
-
-
-/* wificm_glna0 register */
-/*----------------------*/
-/* Result of retention gain_lna = 0 */
-/* cpt_glna0 : result of retention gain_lna=0 */
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA0_CPT_GLNA0_MASK 0x01ff
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA0_CPT_GLNA0_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int cpt_glna0 : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_wificm_glna0;
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA0_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA0_DYNAMIC true
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA0_SNAPCLOCK 1
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA0_ADDR 0x4001d248
-
-
-/* wificm_glna1 register */
-/*----------------------*/
-/* Result of retention gain_lna = 1 */
-/* cpt_glna1 : result of retention gain_lna=1 */
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA1_CPT_GLNA1_MASK 0x01ff
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA1_CPT_GLNA1_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int cpt_glna1 : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_wificm_glna1;
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA1_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA1_DYNAMIC true
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA1_SNAPCLOCK 1
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA1_ADDR 0x4001d24c
-
-
-/* wificm_glna2 register */
-/*----------------------*/
-/* Result of retention gain_lna = 2 */
-/* cpt_glna2 : result of retention gain_lna=2 */
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA2_CPT_GLNA2_MASK 0x01ff
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA2_CPT_GLNA2_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int cpt_glna2 : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_wificm_glna2;
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA2_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA2_DYNAMIC true
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA2_SNAPCLOCK 1
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA2_ADDR 0x4001d250
-
-
-/* wificm_glna3 register */
-/*----------------------*/
-/* Result of retention gain_lna = 3 */
-/* cpt_glna3 : result of retention gain_lna=3 */
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA3_CPT_GLNA3_MASK 0x01ff
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA3_CPT_GLNA3_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int cpt_glna3 : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_wificm_glna3;
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA3_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA3_DYNAMIC true
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA3_SNAPCLOCK 1
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA3_ADDR 0x4001d254
-
-
-/* wificm_glna4 register */
-/*----------------------*/
-/* Result of retention gain_lna = 4 */
-/* cpt_glna4 : result of retention gain_lna=4 */
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA4_CPT_GLNA4_MASK 0x01ff
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA4_CPT_GLNA4_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int cpt_glna4 : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_wificm_glna4;
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA4_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA4_DYNAMIC true
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA4_SNAPCLOCK 1
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GLNA4_ADDR 0x4001d258
-
-
-/* wificm_gifamp register */
-/*----------------------*/
-/* Result of retention gain_lna */
-/* cpt_gifamp : result of retention gain_ifamp */
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GIFAMP_CPT_GIFAMP_MASK 0x01ff
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GIFAMP_CPT_GIFAMP_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int cpt_gifamp : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_wificm_gifamp;
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GIFAMP_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GIFAMP_DYNAMIC true
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GIFAMP_SNAPCLOCK 1
-#define EXTAPB_REGFILE_RX_DP_WIFICM_GIFAMP_ADDR 0x4001d25c
-
-
-/* agc_bt_conf register */
-/*----------------------*/
-/* BT gain offset for AGC */
-/* gain_offset : Add offset gain to gain calc in AGC for BT */
-/* rssi_mux : mux to select bt rssi filter */
-/* rfagc_fsync_det_dis : TBD */
-/* rfagc_direction_freeze : TBD */
-/* rf_gain_sw : TBD */
-/* agc_sat_flag : TBD */
-#define EXTAPB_REGFILE_RX_DP_AGC_BT_CONF_GAIN_OFFSET_MASK 0x007f
-#define EXTAPB_REGFILE_RX_DP_AGC_BT_CONF_GAIN_OFFSET_POS 0
-#define EXTAPB_REGFILE_RX_DP_AGC_BT_CONF_RSSI_MUX_MASK 0x0080
-#define EXTAPB_REGFILE_RX_DP_AGC_BT_CONF_RSSI_MUX_POS 7
-#define EXTAPB_REGFILE_RX_DP_AGC_BT_CONF_RFAGC_FSYNC_DET_DIS_MASK 0x0100
-#define EXTAPB_REGFILE_RX_DP_AGC_BT_CONF_RFAGC_FSYNC_DET_DIS_POS 8
-#define EXTAPB_REGFILE_RX_DP_AGC_BT_CONF_RFAGC_DIRECTION_FREEZE_MASK 0x0200
-#define EXTAPB_REGFILE_RX_DP_AGC_BT_CONF_RFAGC_DIRECTION_FREEZE_POS 9
-#define EXTAPB_REGFILE_RX_DP_AGC_BT_CONF_RF_GAIN_SW_MASK 0x0400
-#define EXTAPB_REGFILE_RX_DP_AGC_BT_CONF_RF_GAIN_SW_POS 10
-#define EXTAPB_REGFILE_RX_DP_AGC_BT_CONF_AGC_SAT_FLAG_MASK 0x0800
-#define EXTAPB_REGFILE_RX_DP_AGC_BT_CONF_AGC_SAT_FLAG_POS 11
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int gain_offset : 7;
- unsigned int rssi_mux : 1;
- unsigned int rfagc_fsync_det_dis : 1;
- unsigned int rfagc_direction_freeze : 1;
- unsigned int rf_gain_sw : 1;
- unsigned int agc_sat_flag : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_agc_bt_conf;
-#define EXTAPB_REGFILE_RX_DP_AGC_BT_CONF_RST 0xa14
-#define EXTAPB_REGFILE_RX_DP_AGC_BT_CONF_ADDR 0x4001d260
-
-
-/* rx_pwrup_cnt_th register */
-/*----------------------*/
-/* */
-/* rx_pwrup_cnt_th1m : Delay to start correlating in BLE 1 Mbps mode */
-/* rx_pwrup_cnt_th2m : Delay to start correlating in BLE 2 Mbps mode */
-#define EXTAPB_REGFILE_RX_DP_RX_PWRUP_CNT_TH_RX_PWRUP_CNT_TH1M_MASK 0x00ff
-#define EXTAPB_REGFILE_RX_DP_RX_PWRUP_CNT_TH_RX_PWRUP_CNT_TH1M_POS 0
-#define EXTAPB_REGFILE_RX_DP_RX_PWRUP_CNT_TH_RX_PWRUP_CNT_TH2M_MASK 0xff00
-#define EXTAPB_REGFILE_RX_DP_RX_PWRUP_CNT_TH_RX_PWRUP_CNT_TH2M_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_pwrup_cnt_th1m : 8;
- unsigned int rx_pwrup_cnt_th2m : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_rx_pwrup_cnt_th;
-#define EXTAPB_REGFILE_RX_DP_RX_PWRUP_CNT_TH_RST 0x3646
-#define EXTAPB_REGFILE_RX_DP_RX_PWRUP_CNT_TH_ADDR 0x4001d264
-
-
-/* rssi_lna_gain_lut5 register */
-/*----------------------*/
-/* lna gain lookup table part 5; entry is narrowband RSSI (Stored in configuration bank) */
-/* rssi_lna_gain_lut23 : m30 dBm */
-/* rssi_lna_gain_lut24 : m27 dBm */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT5_RSSI_LNA_GAIN_LUT23_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT5_RSSI_LNA_GAIN_LUT23_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT5_RSSI_LNA_GAIN_LUT24_MASK 0x0038
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT5_RSSI_LNA_GAIN_LUT24_POS 3
-#else
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT5_RSSI_LNA_GAIN_LUT23_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT5_RSSI_LNA_GAIN_LUT23_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT5_RSSI_LNA_GAIN_LUT23_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT5_RSSI_LNA_GAIN_LUT23_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT5_RSSI_LNA_GAIN_LUT23_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT5_RSSI_LNA_GAIN_LUT23_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT5_RSSI_LNA_GAIN_LUT23_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT5_RSSI_LNA_GAIN_LUT23_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT5_RSSI_LNA_GAIN_LUT24_MASK 0x0038
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT5_RSSI_LNA_GAIN_LUT24_POS 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT5_RSSI_LNA_GAIN_LUT24_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT5_RSSI_LNA_GAIN_LUT24_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT5_RSSI_LNA_GAIN_LUT24_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT5_RSSI_LNA_GAIN_LUT24_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT5_RSSI_LNA_GAIN_LUT24_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT5_RSSI_LNA_GAIN_LUT24_BLE_2_MASK 0x0
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rssi_lna_gain_lut23 : 3;
- unsigned int rssi_lna_gain_lut24 : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_rssi_lna_gain_lut5;
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT5_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_LNA_GAIN_LUT5_ADDR 0x4001d268
-
-
-/* rssi_ifamp_gain_lut3 register */
-/*----------------------*/
-/* IFAMP gain lookup table part 3; entry is narrowband RSSI (Stored in configuration bank) */
-/* rssi_ifamp_gain_lut23 : m30 dBm */
-/* rssi_ifamp_gain_lut24 : m27 dBm */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT3_RSSI_IFAMP_GAIN_LUT23_MASK 0x0003
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT3_RSSI_IFAMP_GAIN_LUT23_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT3_RSSI_IFAMP_GAIN_LUT24_MASK 0x000c
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT3_RSSI_IFAMP_GAIN_LUT24_POS 2
-#else
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT3_RSSI_IFAMP_GAIN_LUT23_MASK 0x0003
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT3_RSSI_IFAMP_GAIN_LUT23_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT3_RSSI_IFAMP_GAIN_LUT23_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT3_RSSI_IFAMP_GAIN_LUT23_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT3_RSSI_IFAMP_GAIN_LUT23_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT3_RSSI_IFAMP_GAIN_LUT23_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT3_RSSI_IFAMP_GAIN_LUT23_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT3_RSSI_IFAMP_GAIN_LUT23_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT3_RSSI_IFAMP_GAIN_LUT24_MASK 0x000c
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT3_RSSI_IFAMP_GAIN_LUT24_POS 2
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT3_RSSI_IFAMP_GAIN_LUT24_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT3_RSSI_IFAMP_GAIN_LUT24_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT3_RSSI_IFAMP_GAIN_LUT24_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT3_RSSI_IFAMP_GAIN_LUT24_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT3_RSSI_IFAMP_GAIN_LUT24_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT3_RSSI_IFAMP_GAIN_LUT24_BLE_2_MASK 0x0
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rssi_ifamp_gain_lut23 : 2;
- unsigned int rssi_ifamp_gain_lut24 : 2;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_rssi_ifamp_gain_lut3;
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT3_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_IFAMP_GAIN_LUT3_ADDR 0x4001d26c
-
-
-/* rssi_aaf_gain_lut5 register */
-/*----------------------*/
-/* AAF gain lookup table part 5; entry is narrowband RSSI (Stored in configuration bank) */
-/* rssi_aaf_gain_lut23 : m30 dBm */
-/* rssi_aaf_gain_lut24 : m27 dBm */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT5_RSSI_AAF_GAIN_LUT23_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT5_RSSI_AAF_GAIN_LUT23_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT5_RSSI_AAF_GAIN_LUT24_MASK 0x0038
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT5_RSSI_AAF_GAIN_LUT24_POS 3
-#else
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT5_RSSI_AAF_GAIN_LUT23_MASK 0x0007
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT5_RSSI_AAF_GAIN_LUT23_POS 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT5_RSSI_AAF_GAIN_LUT23_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT5_RSSI_AAF_GAIN_LUT23_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT5_RSSI_AAF_GAIN_LUT23_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT5_RSSI_AAF_GAIN_LUT23_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT5_RSSI_AAF_GAIN_LUT23_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT5_RSSI_AAF_GAIN_LUT23_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT5_RSSI_AAF_GAIN_LUT24_MASK 0x0038
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT5_RSSI_AAF_GAIN_LUT24_POS 3
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT5_RSSI_AAF_GAIN_LUT24_ZB_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT5_RSSI_AAF_GAIN_LUT24_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT5_RSSI_AAF_GAIN_LUT24_BLE_1 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT5_RSSI_AAF_GAIN_LUT24_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT5_RSSI_AAF_GAIN_LUT24_BLE_2 0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT5_RSSI_AAF_GAIN_LUT24_BLE_2_MASK 0x0
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rssi_aaf_gain_lut23 : 3;
- unsigned int rssi_aaf_gain_lut24 : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rx_dp_rssi_aaf_gain_lut5;
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT5_RST 0x0
-#define EXTAPB_REGFILE_RX_DP_RSSI_AAF_GAIN_LUT5_ADDR 0x4001d270
-
-
-typedef struct{
- t_extapb_regfile_rx_dp_global global;
- t_extapb_regfile_rx_dp_cfg cfg;
- t_extapb_regfile_rx_dp_bank_cfg1 bank_cfg1;
- t_extapb_regfile_rx_dp_dc_offset_cfg dc_offset_cfg;
- t_extapb_regfile_rx_dp_clip_det_1_lev_sel clip_det_1_lev_sel;
- t_extapb_regfile_rx_dp_clip_det_1_ana_agc_bypass clip_det_1_ana_agc_bypass;
- t_extapb_regfile_rx_dp_clip_det_1_timeout_up clip_det_1_timeout_up;
- unsigned int reserved0[1];
- t_extapb_regfile_rx_dp_lna_setting lna_setting;
- t_extapb_regfile_rx_dp_lna_gain_setting_ana_agc_bypass lna_gain_setting_ana_agc_bypass;
- t_extapb_regfile_rx_dp_clip_det_2_lev_sel clip_det_2_lev_sel;
- t_extapb_regfile_rx_dp_clip_det_2_ana_agc_bypass clip_det_2_ana_agc_bypass;
- t_extapb_regfile_rx_dp_clip_det_2_bucket_decr clip_det_2_bucket_decr;
- t_extapb_regfile_rx_dp_clip_det_2_bucket_incr clip_det_2_bucket_incr;
- t_extapb_regfile_rx_dp_clip_det_2_bucket_threshold clip_det_2_bucket_threshold;
- t_extapb_regfile_rx_dp_clip_det_2_timeout clip_det_2_timeout;
- t_extapb_regfile_rx_dp_clip_det_3_window_size clip_det_3_window_size;
- t_extapb_regfile_rx_dp_clip_det_3_thr_1 clip_det_3_thr_1;
- t_extapb_regfile_rx_dp_clip_det_3_thr_2 clip_det_3_thr_2;
- t_extapb_regfile_rx_dp_clip_det_3_timeout clip_det_3_timeout;
- t_extapb_regfile_rx_dp_ifamp_gain_setting_ana_agc_bypass ifamp_gain_setting_ana_agc_bypass;
- t_extapb_regfile_rx_dp_ifamp_fc_set ifamp_fc_set;
- t_extapb_regfile_rx_dp_ifamp_ibias_set ifamp_ibias_set;
- t_extapb_regfile_rx_dp_ifamp_bypass_set_ana_agc_bypass ifamp_bypass_set_ana_agc_bypass;
- t_extapb_regfile_rx_dp_aaf_gain_setting_ana_agc_bypass aaf_gain_setting_ana_agc_bypass;
- t_extapb_regfile_rx_dp_aaf_fc_set aaf_fc_set;
- t_extapb_regfile_rx_dp_aaf_q_set aaf_q_set;
- t_extapb_regfile_rx_dp_aaf_opam1i_set0 aaf_opam1i_set0;
- t_extapb_regfile_rx_dp_aaf_opam1i_set1 aaf_opam1i_set1;
- t_extapb_regfile_rx_dp_aaf_opam1i_set2 aaf_opam1i_set2;
- t_extapb_regfile_rx_dp_aaf_opam1i_set3 aaf_opam1i_set3;
- t_extapb_regfile_rx_dp_aaf_opam1i_set4 aaf_opam1i_set4;
- t_extapb_regfile_rx_dp_aaf_opam1i_set5 aaf_opam1i_set5;
- t_extapb_regfile_rx_dp_aaf_opam1i_set6 aaf_opam1i_set6;
- t_extapb_regfile_rx_dp_aaf_opam2i_set0 aaf_opam2i_set0;
- t_extapb_regfile_rx_dp_aaf_opam2i_set1 aaf_opam2i_set1;
- t_extapb_regfile_rx_dp_aaf_opam2i_set2 aaf_opam2i_set2;
- t_extapb_regfile_rx_dp_aaf_opam2i_set3 aaf_opam2i_set3;
- t_extapb_regfile_rx_dp_aaf_opam2i_set4 aaf_opam2i_set4;
- t_extapb_regfile_rx_dp_aaf_opam2i_set5 aaf_opam2i_set5;
- t_extapb_regfile_rx_dp_aaf_opam2i_set6 aaf_opam2i_set6;
- t_extapb_regfile_rx_dp_aaf_gain_delay aaf_gain_delay;
- t_extapb_regfile_rx_dp_nb_rssi_correction_db nb_rssi_correction_db;
- t_extapb_regfile_rx_dp_nb_rssi_hysteresis nb_rssi_hysteresis;
- t_extapb_regfile_rx_dp_rssi_lna_gain_lut1 rssi_lna_gain_lut1;
- t_extapb_regfile_rx_dp_rssi_lna_gain_lut2 rssi_lna_gain_lut2;
- t_extapb_regfile_rx_dp_rssi_lna_gain_lut3 rssi_lna_gain_lut3;
- t_extapb_regfile_rx_dp_rssi_lna_gain_lut4 rssi_lna_gain_lut4;
- t_extapb_regfile_rx_dp_rssi_ifamp_gain_lut0 rssi_ifamp_gain_lut0;
- t_extapb_regfile_rx_dp_rssi_ifamp_gain_lut1 rssi_ifamp_gain_lut1;
- t_extapb_regfile_rx_dp_rssi_ifamp_gain_lut2 rssi_ifamp_gain_lut2;
- t_extapb_regfile_rx_dp_rssi_aaf_gain_lut0 rssi_aaf_gain_lut0;
- unsigned int reserved1[8];
- t_extapb_regfile_rx_dp_rssi_aaf_gain_lut1 rssi_aaf_gain_lut1;
- t_extapb_regfile_rx_dp_rssi_aaf_gain_lut2 rssi_aaf_gain_lut2;
- t_extapb_regfile_rx_dp_rssi_aaf_gain_lut3 rssi_aaf_gain_lut3;
- t_extapb_regfile_rx_dp_rssi_aaf_gain_lut4 rssi_aaf_gain_lut4;
- t_extapb_regfile_rx_dp_lna_gain_lut0 lna_gain_lut0;
- t_extapb_regfile_rx_dp_lna_gain_lut1 lna_gain_lut1;
- t_extapb_regfile_rx_dp_lna_gain_lut2 lna_gain_lut2;
- t_extapb_regfile_rx_dp_lna_gain_lut3 lna_gain_lut3;
- t_extapb_regfile_rx_dp_lna_gain_lut4 lna_gain_lut4;
- t_extapb_regfile_rx_dp_ifamp_gain_lut0 ifamp_gain_lut0;
- t_extapb_regfile_rx_dp_ifamp_gain_lut1 ifamp_gain_lut1;
- t_extapb_regfile_rx_dp_ifamp_gain_lut2 ifamp_gain_lut2;
- t_extapb_regfile_rx_dp_aaf_gain_lut0 aaf_gain_lut0;
- t_extapb_regfile_rx_dp_aaf_gain_lut1 aaf_gain_lut1;
- t_extapb_regfile_rx_dp_aaf_gain_lut2 aaf_gain_lut2;
- t_extapb_regfile_rx_dp_aaf_gain_lut3 aaf_gain_lut3;
- t_extapb_regfile_rx_dp_aaf_gain_lut4 aaf_gain_lut4;
- t_extapb_regfile_rx_dp_aaf_gain_lut5 aaf_gain_lut5;
- t_extapb_regfile_rx_dp_aaf_gain_lut6 aaf_gain_lut6;
- t_extapb_regfile_rx_dp_nb_rssi_conv_to_dbm nb_rssi_conv_to_dbm;
- t_extapb_regfile_rx_dp_wb_rssi_conv_to_dbm wb_rssi_conv_to_dbm;
- t_extapb_regfile_rx_dp_wb_rssi_ctrl wb_rssi_ctrl;
- t_extapb_regfile_rx_dp_wb_rssi_wakeup wb_rssi_wakeup;
- t_extapb_regfile_rx_dp_nb_rssi_wakeup nb_rssi_wakeup;
- t_extapb_regfile_rx_dp_nb_rssi_ctrl1 nb_rssi_ctrl1;
- t_extapb_regfile_rx_dp_nb_rssi_ctrl2 nb_rssi_ctrl2;
- t_extapb_regfile_rx_dp_nb_rssi_ctrl3 nb_rssi_ctrl3;
- t_extapb_regfile_rx_dp_nb_rssi_payload_ctrl nb_rssi_payload_ctrl;
- t_extapb_regfile_rx_dp_nb_rssi_modem_ctrl nb_rssi_modem_ctrl;
- t_extapb_regfile_rx_dp_mute_ctrl1 mute_ctrl1;
- t_extapb_regfile_rx_dp_mute_ctrl2 mute_ctrl2;
- t_extapb_regfile_rx_dp_mute_ctrl3 mute_ctrl3;
- t_extapb_regfile_rx_dp_ana_agc_bypass ana_agc_bypass;
- t_extapb_regfile_rx_dp_agc_freeze_offset agc_freeze_offset;
- t_extapb_regfile_rx_dp_wb_rssi_dbm_run wb_rssi_dbm_run;
- unsigned int reserved2[1];
- t_extapb_regfile_rx_dp_wb_rssi_dbm_sync wb_rssi_dbm_sync;
- t_extapb_regfile_rx_dp_wb_rssi_dbm_packet wb_rssi_dbm_packet;
- t_extapb_regfile_rx_dp_nb_rssi_dbm_run nb_rssi_dbm_run;
- t_extapb_regfile_rx_dp_nb_rssi_agc_dbm_run nb_rssi_agc_dbm_run;
- t_extapb_regfile_rx_dp_nb_rssi_dbm_sync nb_rssi_dbm_sync;
- t_extapb_regfile_rx_dp_nb_rssi_agc_dbm_sync nb_rssi_agc_dbm_sync;
- t_extapb_regfile_rx_dp_mf_rssi_dbm_run mf_rssi_dbm_run;
- t_extapb_regfile_rx_dp_mf_rssi_dbm_packet mf_rssi_dbm_packet;
- t_extapb_regfile_rx_dp_dc_offset_i_packet dc_offset_i_packet;
- t_extapb_regfile_rx_dp_dc_offset_q_packet dc_offset_q_packet;
- t_extapb_regfile_rx_dp_agc_bypass_nb_rssi agc_bypass_nb_rssi;
- t_extapb_regfile_rx_dp_agc_out_run agc_out_run;
- t_extapb_regfile_rx_dp_agc_out_sync agc_out_sync;
- t_extapb_regfile_rx_dp_dc_offset_delay dc_offset_delay;
- t_extapb_regfile_rx_dp_wakeup_timeout wakeup_timeout;
- t_extapb_regfile_rx_dp_nb_rssi_init_timeout nb_rssi_init_timeout;
- t_extapb_regfile_rx_dp_if_freq_norm if_freq_norm;
- t_extapb_regfile_rx_dp_correlator_start_link correlator_start_link;
- t_extapb_regfile_rx_dp_correlator_start_scan correlator_start_scan;
- unsigned int reserved3[1];
- t_extapb_regfile_rx_dp_rssi_lna_gain_lut0 rssi_lna_gain_lut0;
- unsigned int reserved4[3];
- t_extapb_regfile_rx_dp_clip_det_1_timeout clip_det_1_timeout;
- t_extapb_regfile_rx_dp_agc_ctrl1 agc_ctrl1;
- t_extapb_regfile_rx_dp_agc_ctrl2 agc_ctrl2;
- t_extapb_regfile_rx_dp_agc_reset agc_reset;
- t_extapb_regfile_rx_dp_agc_wificm_conf agc_wificm_conf;
- t_extapb_regfile_rx_dp_agc_wificm_gain agc_wificm_gain;
- t_extapb_regfile_rx_dp_agc_wificm_tout agc_wificm_tout;
- t_extapb_regfile_rx_dp_agc_wificm_fgain agc_wificm_fgain;
- t_extapb_regfile_rx_dp_agc_wificm_th agc_wificm_th;
- t_extapb_regfile_rx_dp_agc_obs agc_obs;
- t_extapb_regfile_rx_dp_wificm_glna0 wificm_glna0;
- t_extapb_regfile_rx_dp_wificm_glna1 wificm_glna1;
- t_extapb_regfile_rx_dp_wificm_glna2 wificm_glna2;
- t_extapb_regfile_rx_dp_wificm_glna3 wificm_glna3;
- t_extapb_regfile_rx_dp_wificm_glna4 wificm_glna4;
- t_extapb_regfile_rx_dp_wificm_gifamp wificm_gifamp;
- t_extapb_regfile_rx_dp_agc_bt_conf agc_bt_conf;
- t_extapb_regfile_rx_dp_rx_pwrup_cnt_th rx_pwrup_cnt_th;
- t_extapb_regfile_rx_dp_rssi_lna_gain_lut5 rssi_lna_gain_lut5;
- t_extapb_regfile_rx_dp_rssi_ifamp_gain_lut3 rssi_ifamp_gain_lut3;
- t_extapb_regfile_rx_dp_rssi_aaf_gain_lut5 rssi_aaf_gain_lut5;
-} t_extapb_regfile_rx_datapath;
-#define EXTAPB_REGFILE_RX_DATAPATH_ADDR 0x4001d040
-#define EXTAPB_REGFILE_RX_DATAPATH ((t_extapb_regfile_rx_datapath *)EXTAPB_REGFILE_RX_DATAPATH_ADDR)
-
-
-/* transceiver module */
-/*-------------------------*/
-
-
-/* clipdet_d2r_if_val register */
-/*----------------------*/
-/* Clip Detector RF interface : regfile value */
-/* rx_clipdet_hs_enable : Clip Detector HS enable */
-/* rx_clipdet_ls_enable : Clip Detector LS enable */
-/* rx_clipdet_hs_amp_set : Programmable clip amplitude level */
-/* rx_clipdet_hs_reset : Reset signal for the SR output latch */
-/* rx_clipdet_ls_amp_set : Programmable clip amplitude level */
-/* rx_clipdet_ls_reset : Reset signal to the SR output latch */
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_VAL_RX_CLIPDET_HS_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_VAL_RX_CLIPDET_HS_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_VAL_RX_CLIPDET_LS_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_VAL_RX_CLIPDET_LS_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_VAL_RX_CLIPDET_HS_AMP_SET_MASK 0x001c
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_VAL_RX_CLIPDET_HS_AMP_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_VAL_RX_CLIPDET_HS_RESET_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_VAL_RX_CLIPDET_HS_RESET_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_VAL_RX_CLIPDET_LS_AMP_SET_MASK 0x01c0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_VAL_RX_CLIPDET_LS_AMP_SET_POS 6
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_VAL_RX_CLIPDET_LS_RESET_MASK 0x0200
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_VAL_RX_CLIPDET_LS_RESET_POS 9
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_clipdet_hs_enable : 1;
- unsigned int rx_clipdet_ls_enable : 1;
- unsigned int rx_clipdet_hs_amp_set : 3;
- unsigned int rx_clipdet_hs_reset : 1;
- unsigned int rx_clipdet_ls_amp_set : 3;
- unsigned int rx_clipdet_ls_reset : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_clipdet_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_VAL_ADDR 0x4001d280
-
-
-/* clipdet_d2r_if_src_sel register */
-/*----------------------*/
-/* Clip Detector RF interface : source selection */
-/* rx_clipdet_hs_enable : Source selection for rx_clipdet_hs_enable */
-/* rx_clipdet_ls_enable : Source selection for rx_clipdet_ls_enable */
-/* rx_clipdet_hs_amp_set : Source selection for rx_clipdet_hs_amp_set */
-/* rx_clipdet_hs_reset : Source selection for rx_clipdet_hs_reset */
-/* rx_clipdet_ls_amp_set : Source selection for rx_clipdet_ls_amp_set */
-/* rx_clipdet_ls_reset : Source selection for rx_clipdet_ls_reset */
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_HS_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_HS_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_HS_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_HS_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_HS_ENABLE_AGC 1
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_HS_ENABLE_AGC_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_LS_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_LS_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_LS_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_LS_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_LS_ENABLE_AGC 1
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_LS_ENABLE_AGC_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_HS_AMP_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_HS_AMP_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_HS_AMP_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_HS_AMP_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_HS_AMP_SET_AGC 1
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_HS_AMP_SET_AGC_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_HS_RESET_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_HS_RESET_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_HS_RESET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_HS_RESET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_HS_RESET_AGC 1
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_HS_RESET_AGC_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_LS_AMP_SET_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_LS_AMP_SET_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_LS_AMP_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_LS_AMP_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_LS_AMP_SET_AGC 1
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_LS_AMP_SET_AGC_MASK 0x10
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_LS_RESET_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_LS_RESET_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_LS_RESET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_LS_RESET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_LS_RESET_AGC 1
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RX_CLIPDET_LS_RESET_AGC_MASK 0x20
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_clipdet_hs_enable : 1;
- unsigned int rx_clipdet_ls_enable : 1;
- unsigned int rx_clipdet_hs_amp_set : 1;
- unsigned int rx_clipdet_hs_reset : 1;
- unsigned int rx_clipdet_ls_amp_set : 1;
- unsigned int rx_clipdet_ls_reset : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_clipdet_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_RST 0x3f
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_SRC_SEL_ADDR 0x4001d284
-
-
-/* clipdet_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* Clip detector RF interface : polarity invert control */
-/* rx_clipdet_hs_enable : Polarity invert control for rx_clipdet_hs_enable */
-/* rx_clipdet_ls_enable : Polarity invert control for rx_clipdet_ls_enable */
-/* rx_clipdet_hs_reset : Polarity invert control for rx_clipdet_hs_reset */
-/* rx_clipdet_ls_reset : Polarity invert control for rx_clipdet_ls_reset */
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_POL_INVERT_EN_RX_CLIPDET_HS_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_POL_INVERT_EN_RX_CLIPDET_HS_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_POL_INVERT_EN_RX_CLIPDET_HS_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_POL_INVERT_EN_RX_CLIPDET_HS_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_POL_INVERT_EN_RX_CLIPDET_HS_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_POL_INVERT_EN_RX_CLIPDET_HS_ENABLE_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_POL_INVERT_EN_RX_CLIPDET_LS_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_POL_INVERT_EN_RX_CLIPDET_LS_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_POL_INVERT_EN_RX_CLIPDET_LS_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_POL_INVERT_EN_RX_CLIPDET_LS_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_POL_INVERT_EN_RX_CLIPDET_LS_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_POL_INVERT_EN_RX_CLIPDET_LS_ENABLE_EN_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_POL_INVERT_EN_RX_CLIPDET_HS_RESET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_POL_INVERT_EN_RX_CLIPDET_HS_RESET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_POL_INVERT_EN_RX_CLIPDET_HS_RESET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_POL_INVERT_EN_RX_CLIPDET_HS_RESET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_POL_INVERT_EN_RX_CLIPDET_HS_RESET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_POL_INVERT_EN_RX_CLIPDET_HS_RESET_EN_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_POL_INVERT_EN_RX_CLIPDET_LS_RESET_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_POL_INVERT_EN_RX_CLIPDET_LS_RESET_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_POL_INVERT_EN_RX_CLIPDET_LS_RESET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_POL_INVERT_EN_RX_CLIPDET_LS_RESET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_POL_INVERT_EN_RX_CLIPDET_LS_RESET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_POL_INVERT_EN_RX_CLIPDET_LS_RESET_EN_MASK 0x8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_clipdet_hs_enable : 1;
- unsigned int rx_clipdet_ls_enable : 1;
- unsigned int rx_clipdet_hs_reset : 1;
- unsigned int rx_clipdet_ls_reset : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_clipdet_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_D2R_IF_POL_INVERT_EN_ADDR 0x4001d288
-
-
-/* clipdet_r2d_if_val register */
-/*----------------------*/
-/* Clip Detector RF interface : regfile value */
-/* rx_clipdet_hs_clip : Clip det HS block output (0.8V) */
-/* rx_clipdet_ls_clip : Clip det LS block output (0.8V) */
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_R2D_IF_VAL_RX_CLIPDET_HS_CLIP_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_R2D_IF_VAL_RX_CLIPDET_HS_CLIP_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_R2D_IF_VAL_RX_CLIPDET_LS_CLIP_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_R2D_IF_VAL_RX_CLIPDET_LS_CLIP_POS 1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_clipdet_hs_clip : 1;
- unsigned int rx_clipdet_ls_clip : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_clipdet_r2d_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_R2D_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_R2D_IF_VAL_DYNAMIC true
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_R2D_IF_VAL_SNAPCLOCK 0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_R2D_IF_VAL_ADDR 0x4001d28c
-
-
-/* clipdet_r2d_if_pol_invert_en register */
-/*----------------------*/
-/* Clip Detector RF interface : polarity invert control */
-/* rx_clipdet_hs_clip : Polarity invert control for rx_clipdet_hs_clip */
-/* rx_clipdet_ls_clip : Polarity invert control for rx_clipdet_ls_clip */
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_R2D_IF_POL_INVERT_EN_RX_CLIPDET_HS_CLIP_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_R2D_IF_POL_INVERT_EN_RX_CLIPDET_HS_CLIP_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_R2D_IF_POL_INVERT_EN_RX_CLIPDET_HS_CLIP_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_R2D_IF_POL_INVERT_EN_RX_CLIPDET_HS_CLIP_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_R2D_IF_POL_INVERT_EN_RX_CLIPDET_HS_CLIP_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_R2D_IF_POL_INVERT_EN_RX_CLIPDET_HS_CLIP_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_R2D_IF_POL_INVERT_EN_RX_CLIPDET_LS_CLIP_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_R2D_IF_POL_INVERT_EN_RX_CLIPDET_LS_CLIP_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_R2D_IF_POL_INVERT_EN_RX_CLIPDET_LS_CLIP_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_R2D_IF_POL_INVERT_EN_RX_CLIPDET_LS_CLIP_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_R2D_IF_POL_INVERT_EN_RX_CLIPDET_LS_CLIP_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_R2D_IF_POL_INVERT_EN_RX_CLIPDET_LS_CLIP_EN_MASK 0x2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_clipdet_hs_clip : 1;
- unsigned int rx_clipdet_ls_clip : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_clipdet_r2d_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_R2D_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_CLIPDET_R2D_IF_POL_INVERT_EN_ADDR 0x4001d290
-
-
-/* aaf_d2r_if_val register */
-/*----------------------*/
-/* Rx AAF RF interface : regfile value */
-/* rx_aaf_i_enable : Anti-aliasing filter enable (I side) */
-/* rx_aaf_q_enable : Anti-aliasing filter enable (Q/DAC filter side) */
-/* rx_aaf_gain_set : DC Gain selection */
-/* rx_aaf_opamp1i_set : Tail current of 1st stage opamp. Can be incremented in steps of 2uA */
-/* rx_aaf_q_set : Q factor selection */
-/* rx_aaf_opamp2i_set : Tail current of 2nd stage opamp. Can be incremented in steps of 2 uA. */
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_VAL_RX_AAF_I_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_VAL_RX_AAF_I_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_VAL_RX_AAF_Q_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_VAL_RX_AAF_Q_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_VAL_RX_AAF_GAIN_SET_MASK 0x001c
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_VAL_RX_AAF_GAIN_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_VAL_RX_AAF_OPAMP1I_SET_MASK 0x01e0
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_VAL_RX_AAF_OPAMP1I_SET_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_VAL_RX_AAF_Q_SET_MASK 0x0600
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_VAL_RX_AAF_Q_SET_POS 9
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_VAL_RX_AAF_OPAMP2I_SET_MASK 0x7800
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_VAL_RX_AAF_OPAMP2I_SET_POS 11
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_aaf_i_enable : 1;
- unsigned int rx_aaf_q_enable : 1;
- unsigned int rx_aaf_gain_set : 3;
- unsigned int rx_aaf_opamp1i_set : 4;
- unsigned int rx_aaf_q_set : 2;
- unsigned int rx_aaf_opamp2i_set : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_aaf_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_VAL_ADDR 0x4001d294
-
-
-/* aaf_d2r_if_src_sel register */
-/*----------------------*/
-/* Rx AAF RF Interface : source selection */
-/* rx_aaf_i_enable : Source selection for rx_aaf_i_enable */
-/* rx_aaf_q_enable : Source selection for rx_aaf_q_enable */
-/* rx_aaf_gain_set : Source selectoin for rx_aaf_gain_set */
-/* rx_aaf_opamp1i_set : Source selection for rx_aaf_opamp1i_set */
-/* rx_aaf_q_set : Source selection for rx_aaf_q_set */
-/* rx_aaf_opamp2i_set : Source selection for rx_aaf_opamp2i_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_I_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_I_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_I_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_I_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_I_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_I_ENABLE_TMU_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_Q_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_Q_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_Q_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_Q_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_Q_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_Q_ENABLE_TMU_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_GAIN_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_GAIN_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_GAIN_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_GAIN_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_GAIN_SET_AGC 1
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_GAIN_SET_AGC_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_OPAMP1I_SET_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_OPAMP1I_SET_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_OPAMP1I_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_OPAMP1I_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_OPAMP1I_SET_AGC 1
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_OPAMP1I_SET_AGC_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_Q_SET_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_Q_SET_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_Q_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_Q_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_Q_SET_AGC 1
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_Q_SET_AGC_MASK 0x10
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_OPAMP2I_SET_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_OPAMP2I_SET_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_OPAMP2I_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_OPAMP2I_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_OPAMP2I_SET_AGC 1
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RX_AAF_OPAMP2I_SET_AGC_MASK 0x20
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_aaf_i_enable : 1;
- unsigned int rx_aaf_q_enable : 1;
- unsigned int rx_aaf_gain_set : 1;
- unsigned int rx_aaf_opamp1i_set : 1;
- unsigned int rx_aaf_q_set : 1;
- unsigned int rx_aaf_opamp2i_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_aaf_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_RST 0x3f
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_SRC_SEL_ADDR 0x4001d298
-
-
-/* aaf_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* Rx AAFF RF Interface : polarity invert control */
-/* rx_aaf_i_enable : Polarity invert control for rx_aaf_i_enable */
-/* rx_aaf_q_enable : Polarity invert control for rx_aaf_q_enable */
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_POL_INVERT_EN_RX_AAF_I_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_POL_INVERT_EN_RX_AAF_I_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_POL_INVERT_EN_RX_AAF_I_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_POL_INVERT_EN_RX_AAF_I_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_POL_INVERT_EN_RX_AAF_I_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_POL_INVERT_EN_RX_AAF_I_ENABLE_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_POL_INVERT_EN_RX_AAF_Q_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_POL_INVERT_EN_RX_AAF_Q_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_POL_INVERT_EN_RX_AAF_Q_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_POL_INVERT_EN_RX_AAF_Q_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_POL_INVERT_EN_RX_AAF_Q_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_POL_INVERT_EN_RX_AAF_Q_ENABLE_EN_MASK 0x2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_aaf_i_enable : 1;
- unsigned int rx_aaf_q_enable : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_aaf_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_D2R_IF_POL_INVERT_EN_ADDR 0x4001d29c
-
-
-/* aaf_1_d2r_if_val register */
-/*----------------------*/
-/* Rx AAF RF interface : regfile value */
-/* rx_aaf_fc_set : Anti-aliasing filter cut-off frequency config */
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_1_D2R_IF_VAL_RX_AAF_FC_SET_MASK 0x0003
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_1_D2R_IF_VAL_RX_AAF_FC_SET_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_aaf_fc_set : 2;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_aaf_1_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_1_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_1_D2R_IF_VAL_ADDR 0x4001d2a0
-
-
-/* aaf_1_d2r_if_src_sel register */
-/*----------------------*/
-/* Rx AAF RF Interface : source selection */
-/* rx_aaf_fc_set : Soruce selection for rx_aaf_fc_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_1_D2R_IF_SRC_SEL_RX_AAF_FC_SET_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_1_D2R_IF_SRC_SEL_RX_AAF_FC_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_1_D2R_IF_SRC_SEL_RX_AAF_FC_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_1_D2R_IF_SRC_SEL_RX_AAF_FC_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_1_D2R_IF_SRC_SEL_RX_AAF_FC_SET_AGC 1
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_1_D2R_IF_SRC_SEL_RX_AAF_FC_SET_AGC_MASK 0x1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_aaf_fc_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_aaf_1_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_1_D2R_IF_SRC_SEL_RST 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_AAF_1_D2R_IF_SRC_SEL_ADDR 0x4001d2a4
-
-
-/* ifamp_d2r_if_val register */
-/*----------------------*/
-/* IFamp RF interface : regfile value */
-/* ifamp_enable_1v1 : IF amplifier enable */
-/* ifamp_ibias_i_1v1_set : Bias current selection */
-/* ifamp_gain_i_1v1_set : Ifamp gain */
-/* ifamp_fc_i_1v1_set : Ifamp fc set */
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_VAL_IFAMP_ENABLE_1V1_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_VAL_IFAMP_ENABLE_1V1_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_VAL_IFAMP_IBIAS_I_1V1_SET_MASK 0x003e
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_VAL_IFAMP_IBIAS_I_1V1_SET_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_VAL_IFAMP_GAIN_I_1V1_SET_MASK 0x00c0
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_VAL_IFAMP_GAIN_I_1V1_SET_POS 6
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_VAL_IFAMP_FC_I_1V1_SET_MASK 0x0300
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_VAL_IFAMP_FC_I_1V1_SET_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int ifamp_enable_1v1 : 1;
- unsigned int ifamp_ibias_i_1v1_set : 5;
- unsigned int ifamp_gain_i_1v1_set : 2;
- unsigned int ifamp_fc_i_1v1_set : 2;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_ifamp_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_VAL_RST 0x1e
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_VAL_ADDR 0x4001d2a8
-
-
-/* ifamp_d2r_if_src_sel register */
-/*----------------------*/
-/* IFamp RF interface : source selection */
-/* ifamp_enable_1v1 : Source selection for ifamp_enable_1v1 */
-/* ifamp_ibias_i_1v1_set : Source selection for ifamp_ibias_i_1v1_set */
-/* ifamp_gain_i_1v1_set : Source selection for ifamp_gain_1v1_set */
-/* ifamp_fc_i_1v1_set : Source selection for ifamp_fc_i_1v1_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_SRC_SEL_IFAMP_ENABLE_1V1_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_SRC_SEL_IFAMP_ENABLE_1V1_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_SRC_SEL_IFAMP_ENABLE_1V1_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_SRC_SEL_IFAMP_ENABLE_1V1_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_SRC_SEL_IFAMP_ENABLE_1V1_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_SRC_SEL_IFAMP_ENABLE_1V1_TMU_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_SRC_SEL_IFAMP_IBIAS_I_1V1_SET_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_SRC_SEL_IFAMP_IBIAS_I_1V1_SET_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_SRC_SEL_IFAMP_IBIAS_I_1V1_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_SRC_SEL_IFAMP_IBIAS_I_1V1_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_SRC_SEL_IFAMP_IBIAS_I_1V1_SET_AGC 1
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_SRC_SEL_IFAMP_IBIAS_I_1V1_SET_AGC_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_SRC_SEL_IFAMP_GAIN_I_1V1_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_SRC_SEL_IFAMP_GAIN_I_1V1_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_SRC_SEL_IFAMP_GAIN_I_1V1_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_SRC_SEL_IFAMP_GAIN_I_1V1_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_SRC_SEL_IFAMP_GAIN_I_1V1_SET_AGC 1
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_SRC_SEL_IFAMP_GAIN_I_1V1_SET_AGC_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_SRC_SEL_IFAMP_FC_I_1V1_SET_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_SRC_SEL_IFAMP_FC_I_1V1_SET_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_SRC_SEL_IFAMP_FC_I_1V1_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_SRC_SEL_IFAMP_FC_I_1V1_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_SRC_SEL_IFAMP_FC_I_1V1_SET_AGC 1
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_SRC_SEL_IFAMP_FC_I_1V1_SET_AGC_MASK 0x8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int ifamp_enable_1v1 : 1;
- unsigned int ifamp_ibias_i_1v1_set : 1;
- unsigned int ifamp_gain_i_1v1_set : 1;
- unsigned int ifamp_fc_i_1v1_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_ifamp_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_SRC_SEL_RST 0xf
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_SRC_SEL_ADDR 0x4001d2ac
-
-
-/* ifamp_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* IFamp RF interface : polarity invert control */
-/* ifamp_enable_1v1 : Polarity invert control for ifamp_enable_1v1 */
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_POL_INVERT_EN_IFAMP_ENABLE_1V1_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_POL_INVERT_EN_IFAMP_ENABLE_1V1_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_POL_INVERT_EN_IFAMP_ENABLE_1V1_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_POL_INVERT_EN_IFAMP_ENABLE_1V1_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_POL_INVERT_EN_IFAMP_ENABLE_1V1_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_POL_INVERT_EN_IFAMP_ENABLE_1V1_EN_MASK 0x1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int ifamp_enable_1v1 : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_ifamp_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_IFAMP_D2R_IF_POL_INVERT_EN_ADDR 0x4001d2b0
-
-
-/* lna_d2r_if_val register */
-/*----------------------*/
-/* Rx LNA Interface : regfile value */
-/* lna_gain_i_1v1_set : LNA gain */
-/* lna_iadj_i_1v1_set : LNA adj */
-/* lna_enable_1v1 : TBD */
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_VAL_LNA_GAIN_I_1V1_SET_MASK 0x0007
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_VAL_LNA_GAIN_I_1V1_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_VAL_LNA_IADJ_I_1V1_SET_MASK 0x0038
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_VAL_LNA_IADJ_I_1V1_SET_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_VAL_LNA_ENABLE_1V1_MASK 0x0040
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_VAL_LNA_ENABLE_1V1_POS 6
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int lna_gain_i_1v1_set : 3;
- unsigned int lna_iadj_i_1v1_set : 3;
- unsigned int lna_enable_1v1 : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_lna_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_VAL_RST 0x20
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_VAL_ADDR 0x4001d2b4
-
-
-/* lna_d2r_if_src_sel register */
-/*----------------------*/
-/* Rx LNA Interface : source selection */
-/* lna_gain_i_1v1_set : Source selection for lna_gain_i_1v1_set */
-/* lna_enable_1v1 : Source selection for lna_enable_1v1 */
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_SRC_SEL_LNA_GAIN_I_1V1_SET_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_SRC_SEL_LNA_GAIN_I_1V1_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_SRC_SEL_LNA_GAIN_I_1V1_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_SRC_SEL_LNA_GAIN_I_1V1_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_SRC_SEL_LNA_GAIN_I_1V1_SET_AGC 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_SRC_SEL_LNA_GAIN_I_1V1_SET_AGC_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_SRC_SEL_LNA_ENABLE_1V1_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_SRC_SEL_LNA_ENABLE_1V1_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_SRC_SEL_LNA_ENABLE_1V1_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_SRC_SEL_LNA_ENABLE_1V1_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_SRC_SEL_LNA_ENABLE_1V1_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_SRC_SEL_LNA_ENABLE_1V1_TMU_MASK 0x2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int lna_gain_i_1v1_set : 1;
- unsigned int lna_enable_1v1 : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_lna_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_SRC_SEL_RST 0x3
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_SRC_SEL_ADDR 0x4001d2b8
-
-
-/* lna_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* Rx LNA interface: polarity invert control */
-/* lna_enable_1v1 : Polarity invert control for pa_core_enable_1v1 */
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_POL_INVERT_EN_LNA_ENABLE_1V1_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_POL_INVERT_EN_LNA_ENABLE_1V1_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_POL_INVERT_EN_LNA_ENABLE_1V1_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_POL_INVERT_EN_LNA_ENABLE_1V1_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_POL_INVERT_EN_LNA_ENABLE_1V1_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_POL_INVERT_EN_LNA_ENABLE_1V1_EN_MASK 0x1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int lna_enable_1v1 : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_lna_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LNA_D2R_IF_POL_INVERT_EN_ADDR 0x4001d2bc
-
-
-/* pll_dac_0_d2r_if_val register */
-/*----------------------*/
-/* PLL DAC RF interface : regfile value */
-/* pll_dac_aaf_out_enable : Enable DAC output to AAF. And AAF to Vmod */
-/* pll_dac_aafbias_enable : Bias enable for AAF */
-/* pll_dac_c_set : Output capacitor set. Default value 10 */
-/* pll_dac_mode2_enable : 2Mbps mode ON */
-/* dac_test_1v1_set : sets if_vcm_vo (350 mV if 1; 400mV if 0) + enable path from dac to aaf */
-/* pll_dac_enable : DAC enable */
-/* pll_dac_in_set : DAC data in (8 bits). NXP to detail. */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_VAL_PLL_DAC_AAF_OUT_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_VAL_PLL_DAC_AAF_OUT_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_VAL_PLL_DAC_AAFBIAS_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_VAL_PLL_DAC_AAFBIAS_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_VAL_PLL_DAC_C_SET_MASK 0x000c
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_VAL_PLL_DAC_C_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_VAL_PLL_DAC_MODE2_ENABLE_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_VAL_PLL_DAC_MODE2_ENABLE_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_VAL_DAC_TEST_1V1_SET_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_VAL_DAC_TEST_1V1_SET_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_VAL_PLL_DAC_ENABLE_MASK 0x0040
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_VAL_PLL_DAC_ENABLE_POS 6
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_VAL_PLL_DAC_IN_SET_MASK 0x7f80
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_VAL_PLL_DAC_IN_SET_POS 7
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_dac_aaf_out_enable : 1;
- unsigned int pll_dac_aafbias_enable : 1;
- unsigned int pll_dac_c_set : 2;
- unsigned int pll_dac_mode2_enable : 1;
- unsigned int dac_test_1v1_set : 1;
- unsigned int pll_dac_enable : 1;
- unsigned int pll_dac_in_set : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_dac_0_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_VAL_RST 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_VAL_ADDR 0x4001d2c0
-
-
-/* pll_dac_0_d2r_if_src_sel register */
-/*----------------------*/
-/* PLL DAC RF interface : source selection */
-/* pll_dac_aaf_out_enable : Source selection for pll_dac_aaf_out_enable */
-/* pll_dac_aafbias_enable : Source selection for pll_dac_aafbias_enable */
-/* dac_test_1v1_set : Source selection for dac_test_1v1_set */
-/* pll_dac_enable : Source selection for pll_dac_enable */
-/* pll_dac_in_set : Source selection for pll_dac_in_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_PLL_DAC_AAF_OUT_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_PLL_DAC_AAF_OUT_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_PLL_DAC_AAF_OUT_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_PLL_DAC_AAF_OUT_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_PLL_DAC_AAF_OUT_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_PLL_DAC_AAF_OUT_ENABLE_TMU_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_PLL_DAC_AAFBIAS_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_PLL_DAC_AAFBIAS_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_PLL_DAC_AAFBIAS_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_PLL_DAC_AAFBIAS_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_PLL_DAC_AAFBIAS_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_PLL_DAC_AAFBIAS_ENABLE_TMU_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_DAC_TEST_1V1_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_DAC_TEST_1V1_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_DAC_TEST_1V1_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_DAC_TEST_1V1_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_DAC_TEST_1V1_SET_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_DAC_TEST_1V1_SET_TMU_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_PLL_DAC_ENABLE_MASK 0x0018
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_PLL_DAC_ENABLE_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_PLL_DAC_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_PLL_DAC_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_PLL_DAC_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_PLL_DAC_ENABLE_TMU_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_PLL_DAC_ENABLE_SYNTHESIZER 2
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_PLL_DAC_ENABLE_SYNTHESIZER_MASK 0x10
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_PLL_DAC_IN_SET_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_PLL_DAC_IN_SET_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_PLL_DAC_IN_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_PLL_DAC_IN_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_PLL_DAC_IN_SET_TX_DP 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_PLL_DAC_IN_SET_TX_DP_MASK 0x20
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_dac_aaf_out_enable : 1;
- unsigned int pll_dac_aafbias_enable : 1;
- unsigned int dac_test_1v1_set : 1;
- unsigned int pll_dac_enable : 2;
- unsigned int pll_dac_in_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_dac_0_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_RST 0x2a
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_SRC_SEL_ADDR 0x4001d2c4
-
-
-/* pll_dac_0_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* PLL DAC RF interface : polarity invert control */
-/* pll_dac_aaf_out_enable : Polarity invert control for pll_dac_aaf_out_enable */
-/* pll_dac_aafbias_enable : Polarity invert control for pll_dac_aafbias_enable */
-/* pll_dac_mode2_enable : Polarity invert control for pll_dac_mode2_enable */
-/* dac_test_1v1_set : Polarity invert control for dac_test_1v1_set */
-/* pll_dac_enable : Polarity invert control for pll_dac_enable */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_PLL_DAC_AAF_OUT_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_PLL_DAC_AAF_OUT_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_PLL_DAC_AAF_OUT_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_PLL_DAC_AAF_OUT_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_PLL_DAC_AAF_OUT_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_PLL_DAC_AAF_OUT_ENABLE_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_PLL_DAC_AAFBIAS_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_PLL_DAC_AAFBIAS_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_PLL_DAC_AAFBIAS_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_PLL_DAC_AAFBIAS_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_PLL_DAC_AAFBIAS_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_PLL_DAC_AAFBIAS_ENABLE_EN_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_PLL_DAC_MODE2_ENABLE_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_PLL_DAC_MODE2_ENABLE_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_PLL_DAC_MODE2_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_PLL_DAC_MODE2_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_PLL_DAC_MODE2_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_PLL_DAC_MODE2_ENABLE_EN_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_DAC_TEST_1V1_SET_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_DAC_TEST_1V1_SET_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_DAC_TEST_1V1_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_DAC_TEST_1V1_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_DAC_TEST_1V1_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_DAC_TEST_1V1_SET_EN_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_PLL_DAC_ENABLE_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_PLL_DAC_ENABLE_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_PLL_DAC_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_PLL_DAC_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_PLL_DAC_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_PLL_DAC_ENABLE_EN_MASK 0x10
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_dac_aaf_out_enable : 1;
- unsigned int pll_dac_aafbias_enable : 1;
- unsigned int pll_dac_mode2_enable : 1;
- unsigned int dac_test_1v1_set : 1;
- unsigned int pll_dac_enable : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_dac_0_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_0_D2R_IF_POL_INVERT_EN_ADDR 0x4001d2c8
-
-
-/* pll_dac_1_d2r_if_val register */
-/*----------------------*/
-/* PLL DAC RF interface : regfile value */
-/* pll_dac_dccur_set : Output voltage trimming. Default value 1000. NXP to detail. */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_1_D2R_IF_VAL_PLL_DAC_DCCUR_SET_MASK 0x000f
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_1_D2R_IF_VAL_PLL_DAC_DCCUR_SET_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_dac_dccur_set : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_dac_1_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_1_D2R_IF_VAL_RST 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DAC_1_D2R_IF_VAL_ADDR 0x4001d2cc
-
-
-/* adc_d2r_if_val register */
-/*----------------------*/
-/* Rx ADC RF interface : regfile value */
-/* rx_adc_samptime_set : ADC control. NXP to expand table. */
-/* rx_adc_enable : ADC enable signal */
-#define EXTAPB_REGFILE_TRANSCEIVER_ADC_D2R_IF_VAL_RX_ADC_SAMPTIME_SET_MASK 0x0003
-#define EXTAPB_REGFILE_TRANSCEIVER_ADC_D2R_IF_VAL_RX_ADC_SAMPTIME_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_ADC_D2R_IF_VAL_RX_ADC_ENABLE_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_ADC_D2R_IF_VAL_RX_ADC_ENABLE_POS 2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_adc_samptime_set : 2;
- unsigned int rx_adc_enable : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_adc_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_ADC_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_ADC_D2R_IF_VAL_ADDR 0x4001d2d0
-
-
-/* adc_d2r_if_src_sel register */
-/*----------------------*/
-/* Rx ADC RF interface : source selection */
-/* rx_adc_enable : Source selection for rx_adc_enable */
-#define EXTAPB_REGFILE_TRANSCEIVER_ADC_D2R_IF_SRC_SEL_RX_ADC_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_ADC_D2R_IF_SRC_SEL_RX_ADC_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_ADC_D2R_IF_SRC_SEL_RX_ADC_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_ADC_D2R_IF_SRC_SEL_RX_ADC_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_ADC_D2R_IF_SRC_SEL_RX_ADC_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_ADC_D2R_IF_SRC_SEL_RX_ADC_ENABLE_TMU_MASK 0x1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_adc_enable : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_adc_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_ADC_D2R_IF_SRC_SEL_RST 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_ADC_D2R_IF_SRC_SEL_ADDR 0x4001d2d4
-
-
-/* adc_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* Rx ADC RF interface : polarity invert control */
-/* rx_adc_enable : Polarity invert control for rx_adc_enable */
-#define EXTAPB_REGFILE_TRANSCEIVER_ADC_D2R_IF_POL_INVERT_EN_RX_ADC_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_ADC_D2R_IF_POL_INVERT_EN_RX_ADC_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_ADC_D2R_IF_POL_INVERT_EN_RX_ADC_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_ADC_D2R_IF_POL_INVERT_EN_RX_ADC_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_ADC_D2R_IF_POL_INVERT_EN_RX_ADC_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_ADC_D2R_IF_POL_INVERT_EN_RX_ADC_ENABLE_EN_MASK 0x1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_adc_enable : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_adc_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_ADC_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_ADC_D2R_IF_POL_INVERT_EN_ADDR 0x4001d2d8
-
-
-/* bgr_d2r_if_val register */
-/*----------------------*/
-/* Rx Bandgap RF interface : regfile value */
-/* rx_bgr_enable : BGR enable */
-/* rx_bgr_trim_enable : Enable bypass RF bandgap trimming */
-/* rx_bgr_cur5ua_1v8_set : 5uA Main mirror N trimming. 3.4uA to 8.3uA */
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_VAL_RX_BGR_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_VAL_RX_BGR_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_VAL_RX_BGR_TRIM_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_VAL_RX_BGR_TRIM_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_VAL_RX_BGR_CUR5UA_1V8_SET_MASK 0x007c
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_VAL_RX_BGR_CUR5UA_1V8_SET_POS 2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_bgr_enable : 1;
- unsigned int rx_bgr_trim_enable : 1;
- unsigned int rx_bgr_cur5ua_1v8_set : 5;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_bgr_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_VAL_ADDR 0x4001d2dc
-
-
-/* bgr_d2r_if_src_sel register */
-/*----------------------*/
-/* Rx Bandgap RF interface : source selection */
-/* rx_bgr_enable : Source selection for rx_bgr_enable */
-/* rx_bgr_trim_enable : Source selection for rx_bgr_trim_enable */
-/* rx_bgr_cur5ua_1v8_set : Source selection for rx_bgr_cur5ua_1v8_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_SRC_SEL_RX_BGR_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_SRC_SEL_RX_BGR_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_SRC_SEL_RX_BGR_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_SRC_SEL_RX_BGR_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_SRC_SEL_RX_BGR_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_SRC_SEL_RX_BGR_ENABLE_TMU_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_SRC_SEL_RX_BGR_TRIM_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_SRC_SEL_RX_BGR_TRIM_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_SRC_SEL_RX_BGR_TRIM_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_SRC_SEL_RX_BGR_TRIM_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_SRC_SEL_RX_BGR_TRIM_ENABLE_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_SRC_SEL_RX_BGR_TRIM_ENABLE_CALIBRATION_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_SRC_SEL_RX_BGR_CUR5UA_1V8_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_SRC_SEL_RX_BGR_CUR5UA_1V8_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_SRC_SEL_RX_BGR_CUR5UA_1V8_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_SRC_SEL_RX_BGR_CUR5UA_1V8_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_SRC_SEL_RX_BGR_CUR5UA_1V8_SET_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_SRC_SEL_RX_BGR_CUR5UA_1V8_SET_CALIBRATION_MASK 0x4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_bgr_enable : 1;
- unsigned int rx_bgr_trim_enable : 1;
- unsigned int rx_bgr_cur5ua_1v8_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_bgr_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_SRC_SEL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_SRC_SEL_ADDR 0x4001d2e0
-
-
-/* bgr_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* Rx Bandgap RF interface : polarity invert control */
-/* rx_bgr_enable : Polarity invert control for rx_bgr_enable */
-/* rx_bgr_trim_enable : Polarity invert control for rx_bgr_trim_enable */
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_POL_INVERT_EN_RX_BGR_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_POL_INVERT_EN_RX_BGR_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_POL_INVERT_EN_RX_BGR_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_POL_INVERT_EN_RX_BGR_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_POL_INVERT_EN_RX_BGR_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_POL_INVERT_EN_RX_BGR_ENABLE_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_POL_INVERT_EN_RX_BGR_TRIM_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_POL_INVERT_EN_RX_BGR_TRIM_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_POL_INVERT_EN_RX_BGR_TRIM_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_POL_INVERT_EN_RX_BGR_TRIM_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_POL_INVERT_EN_RX_BGR_TRIM_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_POL_INVERT_EN_RX_BGR_TRIM_ENABLE_EN_MASK 0x2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_bgr_enable : 1;
- unsigned int rx_bgr_trim_enable : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_bgr_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_D2R_IF_POL_INVERT_EN_ADDR 0x4001d2e4
-
-
-/* bgr_r2d_if_val register */
-/*----------------------*/
-/* Rx Bandgap RF interface : regfile value */
-/* rx_bgr_comp_out : Bandgap comparator output */
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_R2D_IF_VAL_RX_BGR_COMP_OUT_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_R2D_IF_VAL_RX_BGR_COMP_OUT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_bgr_comp_out : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_bgr_r2d_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_R2D_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_R2D_IF_VAL_DYNAMIC true
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_R2D_IF_VAL_SNAPCLOCK 0
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_R2D_IF_VAL_ADDR 0x4001d2e8
-
-
-/* bgr_r2d_if_pol_invert_en register */
-/*----------------------*/
-/* Rx Bandgap RF interface : polarity invert control */
-/* rx_bgr_comp_out : Polarity invert control for rx_bgr_comp_out */
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_R2D_IF_POL_INVERT_EN_RX_BGR_COMP_OUT_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_R2D_IF_POL_INVERT_EN_RX_BGR_COMP_OUT_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_R2D_IF_POL_INVERT_EN_RX_BGR_COMP_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_R2D_IF_POL_INVERT_EN_RX_BGR_COMP_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_R2D_IF_POL_INVERT_EN_RX_BGR_COMP_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_R2D_IF_POL_INVERT_EN_RX_BGR_COMP_OUT_EN_MASK 0x1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_bgr_comp_out : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_bgr_r2d_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_R2D_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_BGR_R2D_IF_POL_INVERT_EN_ADDR 0x4001d2ec
-
-
-/* mixer_d2r_if_val register */
-/*----------------------*/
-/* Mixer RF interface : regfile value */
-/* enable_1v1 : NXP to detail */
-/* mixer_vgadjust_i_1v1_set : NXP to detail */
-/* dummy_mixer_enable : Mixer enable */
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_VAL_ENABLE_1V1_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_VAL_ENABLE_1V1_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_VAL_MIXER_VGADJUST_I_1V1_SET_MASK 0x000e
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_VAL_MIXER_VGADJUST_I_1V1_SET_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_VAL_DUMMY_MIXER_ENABLE_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_VAL_DUMMY_MIXER_ENABLE_POS 4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int enable_1v1 : 1;
- unsigned int mixer_vgadjust_i_1v1_set : 3;
- unsigned int dummy_mixer_enable : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_mixer_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_VAL_ADDR 0x4001d2f0
-
-
-/* mixer_d2r_if_src_sel register */
-/*----------------------*/
-/* Mixer RF interface : source selection */
-/* enable_1v1 : Source selection for enable_1v1 */
-/* dummy_mixer_enable : Source selection for dummy_mixer_enable */
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_SRC_SEL_ENABLE_1V1_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_SRC_SEL_ENABLE_1V1_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_SRC_SEL_ENABLE_1V1_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_SRC_SEL_ENABLE_1V1_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_SRC_SEL_ENABLE_1V1_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_SRC_SEL_ENABLE_1V1_TMU_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_SRC_SEL_DUMMY_MIXER_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_SRC_SEL_DUMMY_MIXER_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_SRC_SEL_DUMMY_MIXER_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_SRC_SEL_DUMMY_MIXER_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_SRC_SEL_DUMMY_MIXER_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_SRC_SEL_DUMMY_MIXER_ENABLE_TMU_MASK 0x2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int enable_1v1 : 1;
- unsigned int dummy_mixer_enable : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_mixer_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_SRC_SEL_RST 0x3
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_SRC_SEL_ADDR 0x4001d2f4
-
-
-/* mixer_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* Mixer RF interface : polarity invert control */
-/* enable_1v1 : Polarity invert control for enable_1v1 */
-/* dummy_mixer_enable : Polarity invert control for dummy_mixer_en */
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_POL_INVERT_EN_ENABLE_1V1_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_POL_INVERT_EN_ENABLE_1V1_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_POL_INVERT_EN_ENABLE_1V1_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_POL_INVERT_EN_ENABLE_1V1_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_POL_INVERT_EN_ENABLE_1V1_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_POL_INVERT_EN_ENABLE_1V1_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_POL_INVERT_EN_DUMMY_MIXER_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_POL_INVERT_EN_DUMMY_MIXER_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_POL_INVERT_EN_DUMMY_MIXER_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_POL_INVERT_EN_DUMMY_MIXER_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_POL_INVERT_EN_DUMMY_MIXER_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_POL_INVERT_EN_DUMMY_MIXER_ENABLE_EN_MASK 0x2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int enable_1v1 : 1;
- unsigned int dummy_mixer_enable : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_mixer_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_MIXER_D2R_IF_POL_INVERT_EN_ADDR 0x4001d2f8
-
-
-/* tone_0_d2r_if_val register */
-/*----------------------*/
-/* Tone Generator RF interface : regfile value */
-/* tone_buffer_enable : Used in PA calibration */
-/* tone_att_n_enable : Attenuator n enable */
-/* tone_att_p_enable : Attenuator p enable */
-/* tone_cco_drv_enable : CCO and CCO driver enable */
-/* tone_cp_slice_enable : Charge pump enable */
-/* tone_cp_slice_test_enable : Charge pump test slice enable */
-/* tone_cp_bias_cor_enable : Charge pump bias correction enable */
-/* tone_cp_offcur_set : Set charge pump offset current */
-/* tone_cp_bias_enable : Charge pump bias enable */
-/* tone_divn_fo_test_enable : Test frequency out enable */
-/* tone_pfd_enable : Enable signal for PFD */
-/* tone_att_set : Attenuation selection */
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_BUFFER_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_BUFFER_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_ATT_N_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_ATT_N_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_ATT_P_ENABLE_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_ATT_P_ENABLE_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_CCO_DRV_ENABLE_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_CCO_DRV_ENABLE_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_CP_SLICE_ENABLE_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_CP_SLICE_ENABLE_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_CP_SLICE_TEST_ENABLE_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_CP_SLICE_TEST_ENABLE_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_CP_BIAS_COR_ENABLE_MASK 0x0040
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_CP_BIAS_COR_ENABLE_POS 6
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_CP_OFFCUR_SET_MASK 0x0380
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_CP_OFFCUR_SET_POS 7
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_CP_BIAS_ENABLE_MASK 0x0400
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_CP_BIAS_ENABLE_POS 10
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_DIVN_FO_TEST_ENABLE_MASK 0x0800
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_DIVN_FO_TEST_ENABLE_POS 11
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_PFD_ENABLE_MASK 0x1000
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_PFD_ENABLE_POS 12
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_ATT_SET_MASK 0x6000
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_ATT_SET_POS 13
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_ATT_SET_E_32DB 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_ATT_SET_E_32DB_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_ATT_SET_E_38DB 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_ATT_SET_E_38DB_MASK 0x2000
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_ATT_SET_E_44DB 2
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_ATT_SET_E_44DB_MASK 0x4000
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_ATT_SET_E_50DB 3
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_TONE_ATT_SET_E_50DB_MASK 0x6000
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int tone_buffer_enable : 1;
- unsigned int tone_att_n_enable : 1;
- unsigned int tone_att_p_enable : 1;
- unsigned int tone_cco_drv_enable : 1;
- unsigned int tone_cp_slice_enable : 1;
- unsigned int tone_cp_slice_test_enable : 1;
- unsigned int tone_cp_bias_cor_enable : 1;
- unsigned int tone_cp_offcur_set : 3;
- unsigned int tone_cp_bias_enable : 1;
- unsigned int tone_divn_fo_test_enable : 1;
- unsigned int tone_pfd_enable : 1;
- unsigned int tone_att_set : 2;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_tone_0_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_VAL_ADDR 0x4001d2fc
-
-
-/* tone_0_d2r_if_src_sel register */
-/*----------------------*/
-/* Tone Generator RF interface : source selection */
-/* tone_buffer_enable : Source selection for tone_buffer_enable */
-/* tone_att_n_enable : Source selection for tone_att_n_enable */
-/* tone_att_p_enable : Source selection for tone_att_p_enable */
-/* tone_cco_drv_enable : Source selection for tone_cco_drv_enable */
-/* tone_cp_slice_enable : Source selection for tone_cp_slice_enable */
-/* tone_cp_slice_test_enable : Source selection for tone_cp_slice_test_enable */
-/* tone_cp_bias_cor_enable : Source selection for tone_cp_bias_cor_enable */
-/* tone_cp_bias_enable : Source selection for tone_cp_bias_enable */
-/* tone_divn_fo_test_enable : Source selection for tone_divn_fo_test_enable */
-/* tone_pfd_enable : Source selection for tone_pfd_enable */
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_BUFFER_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_BUFFER_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_BUFFER_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_BUFFER_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_BUFFER_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_BUFFER_ENABLE_TMU_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_ATT_N_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_ATT_N_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_ATT_N_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_ATT_N_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_ATT_N_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_ATT_N_ENABLE_TMU_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_ATT_P_ENABLE_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_ATT_P_ENABLE_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_ATT_P_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_ATT_P_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_ATT_P_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_ATT_P_ENABLE_TMU_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CCO_DRV_ENABLE_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CCO_DRV_ENABLE_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CCO_DRV_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CCO_DRV_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CCO_DRV_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CCO_DRV_ENABLE_TMU_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CP_SLICE_ENABLE_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CP_SLICE_ENABLE_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CP_SLICE_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CP_SLICE_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CP_SLICE_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CP_SLICE_ENABLE_TMU_MASK 0x10
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CP_SLICE_TEST_ENABLE_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CP_SLICE_TEST_ENABLE_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CP_SLICE_TEST_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CP_SLICE_TEST_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CP_SLICE_TEST_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CP_SLICE_TEST_ENABLE_TMU_MASK 0x20
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CP_BIAS_COR_ENABLE_MASK 0x0040
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CP_BIAS_COR_ENABLE_POS 6
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CP_BIAS_COR_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CP_BIAS_COR_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CP_BIAS_COR_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CP_BIAS_COR_ENABLE_TMU_MASK 0x40
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CP_BIAS_ENABLE_MASK 0x0080
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CP_BIAS_ENABLE_POS 7
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CP_BIAS_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CP_BIAS_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CP_BIAS_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_CP_BIAS_ENABLE_TMU_MASK 0x80
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_DIVN_FO_TEST_ENABLE_MASK 0x0100
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_DIVN_FO_TEST_ENABLE_POS 8
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_DIVN_FO_TEST_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_DIVN_FO_TEST_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_DIVN_FO_TEST_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_DIVN_FO_TEST_ENABLE_TMU_MASK 0x100
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_PFD_ENABLE_MASK 0x0200
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_PFD_ENABLE_POS 9
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_PFD_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_PFD_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_PFD_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_TONE_PFD_ENABLE_TMU_MASK 0x200
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int tone_buffer_enable : 1;
- unsigned int tone_att_n_enable : 1;
- unsigned int tone_att_p_enable : 1;
- unsigned int tone_cco_drv_enable : 1;
- unsigned int tone_cp_slice_enable : 1;
- unsigned int tone_cp_slice_test_enable : 1;
- unsigned int tone_cp_bias_cor_enable : 1;
- unsigned int tone_cp_bias_enable : 1;
- unsigned int tone_divn_fo_test_enable : 1;
- unsigned int tone_pfd_enable : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_tone_0_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_RST 0x3ff
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_SRC_SEL_ADDR 0x4001d300
-
-
-/* tone_1_d2r_if_val register */
-/*----------------------*/
-/* Tone Generator RF interface : regfile value */
-/* tone_divn_p_set : Fixed division ration for div2_divn block */
-/* tone_pfd_del_ctrl_set : Delay control signal. 0 : no delay, 3 : delay by 3 cycles */
-/* tone_lf_prech_set : Pre charge loop filter to start at mid value */
-/* tone_cp_prech_set : Pre charge for charge pump */
-/* tone_pfd_force_up_set : force UP signal to always high */
-/* tone_pfd_force_dn_set : force DOWN signal to always high */
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_VAL_TONE_DIVN_P_SET_MASK 0x007f
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_VAL_TONE_DIVN_P_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_VAL_TONE_PFD_DEL_CTRL_SET_MASK 0x0180
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_VAL_TONE_PFD_DEL_CTRL_SET_POS 7
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_VAL_TONE_LF_PRECH_SET_MASK 0x0200
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_VAL_TONE_LF_PRECH_SET_POS 9
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_VAL_TONE_CP_PRECH_SET_MASK 0x0400
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_VAL_TONE_CP_PRECH_SET_POS 10
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_VAL_TONE_PFD_FORCE_UP_SET_MASK 0x0800
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_VAL_TONE_PFD_FORCE_UP_SET_POS 11
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_VAL_TONE_PFD_FORCE_DN_SET_MASK 0x1000
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_VAL_TONE_PFD_FORCE_DN_SET_POS 12
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int tone_divn_p_set : 7;
- unsigned int tone_pfd_del_ctrl_set : 2;
- unsigned int tone_lf_prech_set : 1;
- unsigned int tone_cp_prech_set : 1;
- unsigned int tone_pfd_force_up_set : 1;
- unsigned int tone_pfd_force_dn_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_tone_1_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_VAL_ADDR 0x4001d304
-
-
-/* tone_1_d2r_if_src_sel register */
-/*----------------------*/
-/* Tone Generator RF interface : source selection */
-/* tone_divn_p_set : Source selection for tone_divn_p_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_SRC_SEL_TONE_DIVN_P_SET_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_SRC_SEL_TONE_DIVN_P_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_SRC_SEL_TONE_DIVN_P_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_SRC_SEL_TONE_DIVN_P_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_SRC_SEL_TONE_DIVN_P_SET_TX_DP 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_SRC_SEL_TONE_DIVN_P_SET_TX_DP_MASK 0x1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int tone_divn_p_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_tone_1_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_SRC_SEL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_SRC_SEL_ADDR 0x4001d308
-
-
-/* tone_0_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* Tone Generator RF interface : polarity invert control */
-/* tone_att_n_enable : Polarity invert control for tone_att_n_enable */
-/* tone_att_p_enable : Polarity invert control for tone_att_p_enable */
-/* tone_cco_drv_enable : Polarity invert control for tone_cco_drv_enable */
-/* tone_cp_slice_enable : Polarity invert control for tone_cp_slice_enable */
-/* tone_cp_slice_test_enable : Polarity invert control for tone_cp_slice_test_enable */
-/* tone_cp_bias_cor_enable : Polarity invert control for tone_cp_bias_cor_enable */
-/* tone_cp_bias_enable : Polarity invert control for tone_cp_bias_enable */
-/* tone_divn_fo_test_enable : Polarity invert control for tone_divn_fo_test_enable */
-/* tone_pfd_enable : Polarity invert control for tone_pfd_enable */
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_ATT_N_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_ATT_N_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_ATT_N_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_ATT_N_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_ATT_N_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_ATT_N_ENABLE_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_ATT_P_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_ATT_P_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_ATT_P_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_ATT_P_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_ATT_P_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_ATT_P_ENABLE_EN_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CCO_DRV_ENABLE_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CCO_DRV_ENABLE_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CCO_DRV_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CCO_DRV_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CCO_DRV_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CCO_DRV_ENABLE_EN_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CP_SLICE_ENABLE_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CP_SLICE_ENABLE_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CP_SLICE_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CP_SLICE_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CP_SLICE_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CP_SLICE_ENABLE_EN_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CP_SLICE_TEST_ENABLE_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CP_SLICE_TEST_ENABLE_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CP_SLICE_TEST_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CP_SLICE_TEST_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CP_SLICE_TEST_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CP_SLICE_TEST_ENABLE_EN_MASK 0x10
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CP_BIAS_COR_ENABLE_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CP_BIAS_COR_ENABLE_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CP_BIAS_COR_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CP_BIAS_COR_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CP_BIAS_COR_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CP_BIAS_COR_ENABLE_EN_MASK 0x20
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CP_BIAS_ENABLE_MASK 0x0040
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CP_BIAS_ENABLE_POS 6
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CP_BIAS_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CP_BIAS_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CP_BIAS_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_CP_BIAS_ENABLE_EN_MASK 0x40
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_DIVN_FO_TEST_ENABLE_MASK 0x0080
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_DIVN_FO_TEST_ENABLE_POS 7
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_DIVN_FO_TEST_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_DIVN_FO_TEST_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_DIVN_FO_TEST_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_DIVN_FO_TEST_ENABLE_EN_MASK 0x80
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_PFD_ENABLE_MASK 0x0100
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_PFD_ENABLE_POS 8
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_PFD_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_PFD_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_PFD_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_TONE_PFD_ENABLE_EN_MASK 0x100
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int tone_att_n_enable : 1;
- unsigned int tone_att_p_enable : 1;
- unsigned int tone_cco_drv_enable : 1;
- unsigned int tone_cp_slice_enable : 1;
- unsigned int tone_cp_slice_test_enable : 1;
- unsigned int tone_cp_bias_cor_enable : 1;
- unsigned int tone_cp_bias_enable : 1;
- unsigned int tone_divn_fo_test_enable : 1;
- unsigned int tone_pfd_enable : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_tone_0_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_0_D2R_IF_POL_INVERT_EN_ADDR 0x4001d30c
-
-
-/* tone_1_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* Tone Generator RF Interface : Polarity invert control */
-/* tone_lf_prech_set : Polarity invert control for tone_lf_prech_set */
-/* tone_cp_prech_set : Polarity invert control for tone_cp_prech_set */
-/* tone_pfd_force_up_set : Polarity invert control for tone_pfd_force_up_set */
-/* tone_pfd_force_dn_set : Polarity invert control for tone_pfd_force_dn_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_POL_INVERT_EN_TONE_LF_PRECH_SET_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_POL_INVERT_EN_TONE_LF_PRECH_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_POL_INVERT_EN_TONE_LF_PRECH_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_POL_INVERT_EN_TONE_LF_PRECH_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_POL_INVERT_EN_TONE_LF_PRECH_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_POL_INVERT_EN_TONE_LF_PRECH_SET_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_POL_INVERT_EN_TONE_CP_PRECH_SET_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_POL_INVERT_EN_TONE_CP_PRECH_SET_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_POL_INVERT_EN_TONE_CP_PRECH_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_POL_INVERT_EN_TONE_CP_PRECH_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_POL_INVERT_EN_TONE_CP_PRECH_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_POL_INVERT_EN_TONE_CP_PRECH_SET_EN_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_POL_INVERT_EN_TONE_PFD_FORCE_UP_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_POL_INVERT_EN_TONE_PFD_FORCE_UP_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_POL_INVERT_EN_TONE_PFD_FORCE_UP_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_POL_INVERT_EN_TONE_PFD_FORCE_UP_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_POL_INVERT_EN_TONE_PFD_FORCE_UP_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_POL_INVERT_EN_TONE_PFD_FORCE_UP_SET_EN_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_POL_INVERT_EN_TONE_PFD_FORCE_DN_SET_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_POL_INVERT_EN_TONE_PFD_FORCE_DN_SET_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_POL_INVERT_EN_TONE_PFD_FORCE_DN_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_POL_INVERT_EN_TONE_PFD_FORCE_DN_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_POL_INVERT_EN_TONE_PFD_FORCE_DN_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_POL_INVERT_EN_TONE_PFD_FORCE_DN_SET_EN_MASK 0x8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int tone_lf_prech_set : 1;
- unsigned int tone_cp_prech_set : 1;
- unsigned int tone_pfd_force_up_set : 1;
- unsigned int tone_pfd_force_dn_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_tone_1_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_1_D2R_IF_POL_INVERT_EN_ADDR 0x4001d310
-
-
-/* pll_cp_d2r_if_val register */
-/*----------------------*/
-/* PLL charge pump RF interface : regfile value */
-/* pll_cp_enable : Enable signal for charge pump */
-/* pll_cp_bias_cor_enable : Enable signal for bias correction */
-/* pll_cp_offcur_set : Enable signal for charge pump offset */
-/* pll_cp_offcur_pol_set : Enable PMOS (default) or NMOS sources in the CP */
-/* pll_cp_slice_test_enable : Enable signal for test slice cp */
-/* pll_cp_slice_set : enable signal for slices cp */
-/* pll_cp_pch_enable : Enable signal for precharge cp */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_VAL_PLL_CP_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_VAL_PLL_CP_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_VAL_PLL_CP_BIAS_COR_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_VAL_PLL_CP_BIAS_COR_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_VAL_PLL_CP_OFFCUR_SET_MASK 0x003c
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_VAL_PLL_CP_OFFCUR_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_VAL_PLL_CP_OFFCUR_POL_SET_MASK 0x0040
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_VAL_PLL_CP_OFFCUR_POL_SET_POS 6
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_VAL_PLL_CP_SLICE_TEST_ENABLE_MASK 0x0080
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_VAL_PLL_CP_SLICE_TEST_ENABLE_POS 7
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_VAL_PLL_CP_SLICE_SET_MASK 0x1f00
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_VAL_PLL_CP_SLICE_SET_POS 8
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_VAL_PLL_CP_PCH_ENABLE_MASK 0x2000
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_VAL_PLL_CP_PCH_ENABLE_POS 13
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_cp_enable : 1;
- unsigned int pll_cp_bias_cor_enable : 1;
- unsigned int pll_cp_offcur_set : 4;
- unsigned int pll_cp_offcur_pol_set : 1;
- unsigned int pll_cp_slice_test_enable : 1;
- unsigned int pll_cp_slice_set : 5;
- unsigned int pll_cp_pch_enable : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_cp_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_VAL_ADDR 0x4001d314
-
-
-/* pll_cp_d2r_if_src_sel register */
-/*----------------------*/
-/* PLL charge pump RF interface : source selection */
-/* pll_cp_enable : Source selection for pll_cp_enable */
-/* pll_cp_bias_cor_enable : Source selection for pll_cp_bias_cor_enable */
-/* pll_cp_offcur_set : Source selection for pll_cp_offcur_set */
-/* pll_cp_slice_set : Source selection for pll_cp_slice_set */
-/* pll_cp_pch_enable : cd */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_ENABLE_TMU_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_BIAS_COR_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_BIAS_COR_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_BIAS_COR_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_BIAS_COR_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_BIAS_COR_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_BIAS_COR_ENABLE_TMU_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_OFFCUR_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_OFFCUR_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_OFFCUR_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_OFFCUR_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_OFFCUR_SET_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_OFFCUR_SET_CALIBRATION_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_SLICE_SET_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_SLICE_SET_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_SLICE_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_SLICE_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_SLICE_SET_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_SLICE_SET_CALIBRATION_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_PCH_ENABLE_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_PCH_ENABLE_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_PCH_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_PCH_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_PCH_ENABLE_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_PLL_CP_PCH_ENABLE_CALIBRATION_MASK 0x10
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_cp_enable : 1;
- unsigned int pll_cp_bias_cor_enable : 1;
- unsigned int pll_cp_offcur_set : 1;
- unsigned int pll_cp_slice_set : 1;
- unsigned int pll_cp_pch_enable : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_cp_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_RST 0x13
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_SRC_SEL_ADDR 0x4001d318
-
-
-/* pll_cp_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* PLL charge pump RF interface : polarity invert control */
-/* pll_cp_enable : Polarity invert control for pll_cp_enable */
-/* pll_cp_bias_cor_enable : Polarity invert control for pll_cp_bias_cor_enable */
-/* pll_cp_offcur_pol_set : Polarity invert control for pll_cp_offcur_pol_set */
-/* pll_cp_slice_test_enable : Polarity invert control for pll_cp_slice_test_enable */
-/* pll_cp_pch_enable : Polarity invert control for pll_cp_pch_enable */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_ENABLE_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_BIAS_COR_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_BIAS_COR_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_BIAS_COR_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_BIAS_COR_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_BIAS_COR_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_BIAS_COR_ENABLE_EN_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_OFFCUR_POL_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_OFFCUR_POL_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_OFFCUR_POL_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_OFFCUR_POL_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_OFFCUR_POL_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_OFFCUR_POL_SET_EN_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_SLICE_TEST_ENABLE_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_SLICE_TEST_ENABLE_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_SLICE_TEST_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_SLICE_TEST_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_SLICE_TEST_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_SLICE_TEST_ENABLE_EN_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_PCH_ENABLE_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_PCH_ENABLE_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_PCH_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_PCH_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_PCH_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_PLL_CP_PCH_ENABLE_EN_MASK 0x10
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_cp_enable : 1;
- unsigned int pll_cp_bias_cor_enable : 1;
- unsigned int pll_cp_offcur_pol_set : 1;
- unsigned int pll_cp_slice_test_enable : 1;
- unsigned int pll_cp_pch_enable : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_cp_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CP_D2R_IF_POL_INVERT_EN_ADDR 0x4001d31c
-
-
-/* pll_xo_d2r_if_val register */
-/*----------------------*/
-/* PLL XO RF interface : regfile value */
-/* pll_xo_captest_start_set : Start test */
-/* pll_xo_captest_enable : Enable signal for cap test */
-/* pll_xo_captest_osc_in_set : Select the input for test, 0 : osc_out, 1: osc_in */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_D2R_IF_VAL_PLL_XO_CAPTEST_START_SET_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_D2R_IF_VAL_PLL_XO_CAPTEST_START_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_D2R_IF_VAL_PLL_XO_CAPTEST_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_D2R_IF_VAL_PLL_XO_CAPTEST_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_D2R_IF_VAL_PLL_XO_CAPTEST_OSC_IN_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_D2R_IF_VAL_PLL_XO_CAPTEST_OSC_IN_SET_POS 2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_xo_captest_start_set : 1;
- unsigned int pll_xo_captest_enable : 1;
- unsigned int pll_xo_captest_osc_in_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_xo_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_D2R_IF_VAL_ADDR 0x4001d320
-
-
-/* pll_xo_d2r_if_src_sel register */
-/*----------------------*/
-/* PLL XO RF Interface : source selection */
-/* pll_xo_captest_start_set : Source selection for pll_xo_captest_start_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_D2R_IF_SRC_SEL_PLL_XO_CAPTEST_START_SET_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_D2R_IF_SRC_SEL_PLL_XO_CAPTEST_START_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_D2R_IF_SRC_SEL_PLL_XO_CAPTEST_START_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_D2R_IF_SRC_SEL_PLL_XO_CAPTEST_START_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_D2R_IF_SRC_SEL_PLL_XO_CAPTEST_START_SET_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_D2R_IF_SRC_SEL_PLL_XO_CAPTEST_START_SET_CALIBRATION_MASK 0x1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_xo_captest_start_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_xo_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_D2R_IF_SRC_SEL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_D2R_IF_SRC_SEL_ADDR 0x4001d324
-
-
-/* pll_xo_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* PLL XO RF Interface : polarity invert control */
-/* pll_xo_captest_start_set : Polarity invert control for pll_xo_captest_start_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_D2R_IF_POL_INVERT_EN_PLL_XO_CAPTEST_START_SET_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_D2R_IF_POL_INVERT_EN_PLL_XO_CAPTEST_START_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_D2R_IF_POL_INVERT_EN_PLL_XO_CAPTEST_START_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_D2R_IF_POL_INVERT_EN_PLL_XO_CAPTEST_START_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_D2R_IF_POL_INVERT_EN_PLL_XO_CAPTEST_START_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_D2R_IF_POL_INVERT_EN_PLL_XO_CAPTEST_START_SET_EN_MASK 0x1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_xo_captest_start_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_xo_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_D2R_IF_POL_INVERT_EN_ADDR 0x4001d328
-
-
-/* pll_xo_r2d_if_val register */
-/*----------------------*/
-/* PLL XO RF interface : regfile value */
-/* pll_xo_captest_stop : Output XO cap test. */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_R2D_IF_VAL_PLL_XO_CAPTEST_STOP_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_R2D_IF_VAL_PLL_XO_CAPTEST_STOP_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_xo_captest_stop : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_xo_r2d_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_R2D_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_R2D_IF_VAL_DYNAMIC true
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_R2D_IF_VAL_SNAPCLOCK 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_R2D_IF_VAL_ADDR 0x4001d32c
-
-
-/* pll_xo_r2d_if_pol_invert_en register */
-/*----------------------*/
-/* PLL XO RF Interface : polarity invert control */
-/* pll_xo_captest_stop : Polarity invert control for pll_xo_captest_stop */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_R2D_IF_POL_INVERT_EN_PLL_XO_CAPTEST_STOP_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_R2D_IF_POL_INVERT_EN_PLL_XO_CAPTEST_STOP_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_R2D_IF_POL_INVERT_EN_PLL_XO_CAPTEST_STOP_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_R2D_IF_POL_INVERT_EN_PLL_XO_CAPTEST_STOP_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_R2D_IF_POL_INVERT_EN_PLL_XO_CAPTEST_STOP_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_R2D_IF_POL_INVERT_EN_PLL_XO_CAPTEST_STOP_EN_MASK 0x1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_xo_captest_stop : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_xo_r2d_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_R2D_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_XO_R2D_IF_POL_INVERT_EN_ADDR 0x4001d330
-
-
-/* xo32k_d2r_if_val register */
-/*----------------------*/
-/* 32 kHz XO RF interface : regfile value */
-/* xo32k_captest_start_ao_set : Start test */
-/* xo32k_captest_enable_ao : Enable signal for cap test */
-/* xo32k_captest_osc_in_sel_ao_set : Select the input for test, 0 : osc_out, 1 : osc_in */
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_D2R_IF_VAL_XO32K_CAPTEST_START_AO_SET_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_D2R_IF_VAL_XO32K_CAPTEST_START_AO_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_D2R_IF_VAL_XO32K_CAPTEST_ENABLE_AO_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_D2R_IF_VAL_XO32K_CAPTEST_ENABLE_AO_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_D2R_IF_VAL_XO32K_CAPTEST_OSC_IN_SEL_AO_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_D2R_IF_VAL_XO32K_CAPTEST_OSC_IN_SEL_AO_SET_POS 2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int xo32k_captest_start_ao_set : 1;
- unsigned int xo32k_captest_enable_ao : 1;
- unsigned int xo32k_captest_osc_in_sel_ao_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_xo32k_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_D2R_IF_VAL_ADDR 0x4001d334
-
-
-/* xo32k_d2r_if_src_sel register */
-/*----------------------*/
-/* 32 kHz XO RF interface : source selection */
-/* xo32k_captest_start_ao_set : Source selection for xo32k_captest_start_ao_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_D2R_IF_SRC_SEL_XO32K_CAPTEST_START_AO_SET_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_D2R_IF_SRC_SEL_XO32K_CAPTEST_START_AO_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_D2R_IF_SRC_SEL_XO32K_CAPTEST_START_AO_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_D2R_IF_SRC_SEL_XO32K_CAPTEST_START_AO_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_D2R_IF_SRC_SEL_XO32K_CAPTEST_START_AO_SET_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_D2R_IF_SRC_SEL_XO32K_CAPTEST_START_AO_SET_CALIBRATION_MASK 0x1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int xo32k_captest_start_ao_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_xo32k_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_D2R_IF_SRC_SEL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_D2R_IF_SRC_SEL_ADDR 0x4001d338
-
-
-/* xo32k_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* 32 kHz XO RF interface : polarity invert control */
-/* xo32k_captest_start_ao_set : Polarity invert control for xo32k_captest_start_ao_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_D2R_IF_POL_INVERT_EN_XO32K_CAPTEST_START_AO_SET_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_D2R_IF_POL_INVERT_EN_XO32K_CAPTEST_START_AO_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_D2R_IF_POL_INVERT_EN_XO32K_CAPTEST_START_AO_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_D2R_IF_POL_INVERT_EN_XO32K_CAPTEST_START_AO_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_D2R_IF_POL_INVERT_EN_XO32K_CAPTEST_START_AO_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_D2R_IF_POL_INVERT_EN_XO32K_CAPTEST_START_AO_SET_EN_MASK 0x1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int xo32k_captest_start_ao_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_xo32k_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_D2R_IF_POL_INVERT_EN_ADDR 0x4001d33c
-
-
-/* xo32k_r2d_if_val register */
-/*----------------------*/
-/* 32 kHz XO RF interface : regfile value */
-/* xo32k_captest_stop_ao : Output XO cap test */
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_R2D_IF_VAL_XO32K_CAPTEST_STOP_AO_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_R2D_IF_VAL_XO32K_CAPTEST_STOP_AO_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int xo32k_captest_stop_ao : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_xo32k_r2d_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_R2D_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_R2D_IF_VAL_DYNAMIC true
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_R2D_IF_VAL_SNAPCLOCK 0
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_R2D_IF_VAL_ADDR 0x4001d340
-
-
-/* xo32k_r2d_if_pol_invert_en register */
-/*----------------------*/
-/* 32 kHz XO RF interface : polarity invert control */
-/* xo32k_captest_stop_ao : Polarity invert control for xo32k_captest_stop_ao */
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_R2D_IF_POL_INVERT_EN_XO32K_CAPTEST_STOP_AO_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_R2D_IF_POL_INVERT_EN_XO32K_CAPTEST_STOP_AO_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_R2D_IF_POL_INVERT_EN_XO32K_CAPTEST_STOP_AO_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_R2D_IF_POL_INVERT_EN_XO32K_CAPTEST_STOP_AO_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_R2D_IF_POL_INVERT_EN_XO32K_CAPTEST_STOP_AO_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_R2D_IF_POL_INVERT_EN_XO32K_CAPTEST_STOP_AO_EN_MASK 0x1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int xo32k_captest_stop_ao : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_xo32k_r2d_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_R2D_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_XO32K_R2D_IF_POL_INVERT_EN_ADDR 0x4001d344
-
-
-/* ldo_lo_d2r_if_val register */
-/*----------------------*/
-/* PLL LDO RF Interface : regfile value */
-/* enable_1v8 : Enable signal for LO */
-/* bypass_i_1v8_set : Enable bypass signal */
-/* highz_i_1v8_set : TBD */
-/* vout_i_1v8_set : TBD */
-/* ibias_i_1v8_set : TBD */
-/* stabmode_i_1v8_set : TBD */
-/* vout_i_1v8_set_rx : TBD */
-/* vout_i_1v8_set_tx : TBD */
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_VAL_ENABLE_1V8_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_VAL_ENABLE_1V8_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_VAL_BYPASS_I_1V8_SET_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_VAL_BYPASS_I_1V8_SET_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_VAL_HIGHZ_I_1V8_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_VAL_HIGHZ_I_1V8_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_VAL_VOUT_I_1V8_SET_MASK 0x0038
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_VAL_VOUT_I_1V8_SET_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_VAL_IBIAS_I_1V8_SET_MASK 0x00c0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_VAL_IBIAS_I_1V8_SET_POS 6
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_VAL_STABMODE_I_1V8_SET_MASK 0x0300
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_VAL_STABMODE_I_1V8_SET_POS 8
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_VAL_VOUT_I_1V8_SET_RX_MASK 0x1c00
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_VAL_VOUT_I_1V8_SET_RX_POS 10
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_VAL_VOUT_I_1V8_SET_TX_MASK 0xe000
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_VAL_VOUT_I_1V8_SET_TX_POS 13
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int enable_1v8 : 1;
- unsigned int bypass_i_1v8_set : 1;
- unsigned int highz_i_1v8_set : 1;
- unsigned int vout_i_1v8_set : 3;
- unsigned int ibias_i_1v8_set : 2;
- unsigned int stabmode_i_1v8_set : 2;
- unsigned int vout_i_1v8_set_rx : 3;
- unsigned int vout_i_1v8_set_tx : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_ldo_lo_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_VAL_RST 0xb568
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_VAL_ADDR 0x4001d348
-
-
-/* ldo_lo_d2r_if_src_sel register */
-/*----------------------*/
-/* PLL LDO RF Interface : source selection */
-/* enable_1v8 : Source selection for enable_1v8 */
-/* vout_i_1v8_set : Source selection for vout_i_1v8 */
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_SRC_SEL_ENABLE_1V8_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_SRC_SEL_ENABLE_1V8_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_SRC_SEL_ENABLE_1V8_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_SRC_SEL_ENABLE_1V8_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_SRC_SEL_ENABLE_1V8_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_SRC_SEL_ENABLE_1V8_TMU_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_SRC_SEL_VOUT_I_1V8_SET_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_SRC_SEL_VOUT_I_1V8_SET_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_SRC_SEL_VOUT_I_1V8_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_SRC_SEL_VOUT_I_1V8_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_SRC_SEL_VOUT_I_1V8_SET_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_SRC_SEL_VOUT_I_1V8_SET_TMU_MASK 0x2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int enable_1v8 : 1;
- unsigned int vout_i_1v8_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_ldo_lo_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_SRC_SEL_RST 0x3
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_SRC_SEL_ADDR 0x4001d34c
-
-
-/* ldo_lo_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* PLL LDO RF interface : polarity invert control */
-/* bypass_i_1v8_set : Polarity invert control for bypass_i_1v8_set */
-/* enable_1v8 : Polarity invert control for enable_1v8 */
-/* highz_i_1v8_set : Polarity invert control for highz_i_1v8_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_POL_INVERT_EN_BYPASS_I_1V8_SET_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_POL_INVERT_EN_BYPASS_I_1V8_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_POL_INVERT_EN_BYPASS_I_1V8_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_POL_INVERT_EN_BYPASS_I_1V8_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_POL_INVERT_EN_BYPASS_I_1V8_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_POL_INVERT_EN_BYPASS_I_1V8_SET_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_POL_INVERT_EN_ENABLE_1V8_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_POL_INVERT_EN_ENABLE_1V8_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_POL_INVERT_EN_ENABLE_1V8_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_POL_INVERT_EN_ENABLE_1V8_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_POL_INVERT_EN_ENABLE_1V8_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_POL_INVERT_EN_ENABLE_1V8_EN_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_POL_INVERT_EN_HIGHZ_I_1V8_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_POL_INVERT_EN_HIGHZ_I_1V8_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_POL_INVERT_EN_HIGHZ_I_1V8_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_POL_INVERT_EN_HIGHZ_I_1V8_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_POL_INVERT_EN_HIGHZ_I_1V8_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_POL_INVERT_EN_HIGHZ_I_1V8_SET_EN_MASK 0x4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int bypass_i_1v8_set : 1;
- unsigned int enable_1v8 : 1;
- unsigned int highz_i_1v8_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_ldo_lo_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_LO_D2R_IF_POL_INVERT_EN_ADDR 0x4001d350
-
-
-/* pll_pfd_d2r_if_val register */
-/*----------------------*/
-/* PLL PFD RF interface : regfile value */
-/* pll_pfdcp_enable : Enable signal for pfdcp */
-/* pll_pfd_del_ctrl_set : Tune delay in the pfd. Default 00. NXP to detail */
-/* pll_pfd_force_up_set : Force Up signal */
-/* pll_pfd_force_dn_set : Force Down signal */
-/* pll_pfd_rst_set : Reset pfd active high */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_VAL_PLL_PFDCP_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_VAL_PLL_PFDCP_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_VAL_PLL_PFD_DEL_CTRL_SET_MASK 0x0006
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_VAL_PLL_PFD_DEL_CTRL_SET_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_VAL_PLL_PFD_FORCE_UP_SET_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_VAL_PLL_PFD_FORCE_UP_SET_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_VAL_PLL_PFD_FORCE_DN_SET_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_VAL_PLL_PFD_FORCE_DN_SET_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_VAL_PLL_PFD_RST_SET_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_VAL_PLL_PFD_RST_SET_POS 5
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_pfdcp_enable : 1;
- unsigned int pll_pfd_del_ctrl_set : 2;
- unsigned int pll_pfd_force_up_set : 1;
- unsigned int pll_pfd_force_dn_set : 1;
- unsigned int pll_pfd_rst_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_pfd_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_VAL_ADDR 0x4001d354
-
-
-/* pll_pfd_d2r_if_src_sel register */
-/*----------------------*/
-/* PLL PFD RF Interface : source selection */
-/* pll_pfdcp_enable : Source selection for pll_pfdcp_enable */
-/* pll_pfd_rst_set : Source selection for pll_pfd_rst_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_SRC_SEL_PLL_PFDCP_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_SRC_SEL_PLL_PFDCP_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_SRC_SEL_PLL_PFDCP_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_SRC_SEL_PLL_PFDCP_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_SRC_SEL_PLL_PFDCP_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_SRC_SEL_PLL_PFDCP_ENABLE_TMU_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_SRC_SEL_PLL_PFD_RST_SET_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_SRC_SEL_PLL_PFD_RST_SET_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_SRC_SEL_PLL_PFD_RST_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_SRC_SEL_PLL_PFD_RST_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_SRC_SEL_PLL_PFD_RST_SET_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_SRC_SEL_PLL_PFD_RST_SET_CALIBRATION_MASK 0x2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_pfdcp_enable : 1;
- unsigned int pll_pfd_rst_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_pfd_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_SRC_SEL_RST 0x3
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_SRC_SEL_ADDR 0x4001d358
-
-
-/* pll_pfd_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* PLL PFD RF interface : polarity invert control */
-/* pll_pfdcp_enable : Polarity invert control for pll_pfdcp_enable */
-/* pll_pfd_force_up_set : Polarity invert control for pll_pfd_force_up_set */
-/* pll_pfd_force_dn_set : Polarity Invert control for pll_pfd_force_dn_set */
-/* pll_pfd_rst_set : Polarity invert control for pll_pfd_rst_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_POL_INVERT_EN_PLL_PFDCP_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_POL_INVERT_EN_PLL_PFDCP_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_POL_INVERT_EN_PLL_PFDCP_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_POL_INVERT_EN_PLL_PFDCP_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_POL_INVERT_EN_PLL_PFDCP_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_POL_INVERT_EN_PLL_PFDCP_ENABLE_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_POL_INVERT_EN_PLL_PFD_FORCE_UP_SET_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_POL_INVERT_EN_PLL_PFD_FORCE_UP_SET_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_POL_INVERT_EN_PLL_PFD_FORCE_UP_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_POL_INVERT_EN_PLL_PFD_FORCE_UP_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_POL_INVERT_EN_PLL_PFD_FORCE_UP_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_POL_INVERT_EN_PLL_PFD_FORCE_UP_SET_EN_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_POL_INVERT_EN_PLL_PFD_FORCE_DN_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_POL_INVERT_EN_PLL_PFD_FORCE_DN_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_POL_INVERT_EN_PLL_PFD_FORCE_DN_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_POL_INVERT_EN_PLL_PFD_FORCE_DN_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_POL_INVERT_EN_PLL_PFD_FORCE_DN_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_POL_INVERT_EN_PLL_PFD_FORCE_DN_SET_EN_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_POL_INVERT_EN_PLL_PFD_RST_SET_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_POL_INVERT_EN_PLL_PFD_RST_SET_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_POL_INVERT_EN_PLL_PFD_RST_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_POL_INVERT_EN_PLL_PFD_RST_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_POL_INVERT_EN_PLL_PFD_RST_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_POL_INVERT_EN_PLL_PFD_RST_SET_EN_MASK 0x8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_pfdcp_enable : 1;
- unsigned int pll_pfd_force_up_set : 1;
- unsigned int pll_pfd_force_dn_set : 1;
- unsigned int pll_pfd_rst_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_pfd_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_PFD_D2R_IF_POL_INVERT_EN_ADDR 0x4001d35c
-
-
-/* pll_lock_d2r_if_val register */
-/*----------------------*/
-/* PLL Lock RF interface : regfile value */
-/* pll_lock_det_enable : Enable signal for the lock detector */
-/* pll_lock_det_force_rst_set : Force reset lock detector */
-/* pll_lock_det_mode_ctrl_set : Mode select for lock detector. Default : 00000 */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_VAL_PLL_LOCK_DET_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_VAL_PLL_LOCK_DET_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_VAL_PLL_LOCK_DET_FORCE_RST_SET_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_VAL_PLL_LOCK_DET_FORCE_RST_SET_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_VAL_PLL_LOCK_DET_MODE_CTRL_SET_MASK 0x007c
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_VAL_PLL_LOCK_DET_MODE_CTRL_SET_POS 2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_lock_det_enable : 1;
- unsigned int pll_lock_det_force_rst_set : 1;
- unsigned int pll_lock_det_mode_ctrl_set : 5;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_lock_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_VAL_ADDR 0x4001d360
-
-
-/* pll_lock_d2r_if_src_sel register */
-/*----------------------*/
-/* PLL Lock RF interface : source selection */
-/* pll_lock_det_enable : Source selection for pll_lock_det_enable */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_SRC_SEL_PLL_LOCK_DET_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_SRC_SEL_PLL_LOCK_DET_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_SRC_SEL_PLL_LOCK_DET_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_SRC_SEL_PLL_LOCK_DET_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_SRC_SEL_PLL_LOCK_DET_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_SRC_SEL_PLL_LOCK_DET_ENABLE_TMU_MASK 0x1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_lock_det_enable : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_lock_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_SRC_SEL_RST 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_SRC_SEL_ADDR 0x4001d364
-
-
-/* pll_lock_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* PLL Lock RF interface : polarity invert control */
-/* pll_lock_det_enable : Polarity invert control for pll_lock_det_enable */
-/* pll_lock_det_force_rst_set : Polarity invert control for pll_lock_det_force_rst_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_POL_INVERT_EN_PLL_LOCK_DET_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_POL_INVERT_EN_PLL_LOCK_DET_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_POL_INVERT_EN_PLL_LOCK_DET_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_POL_INVERT_EN_PLL_LOCK_DET_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_POL_INVERT_EN_PLL_LOCK_DET_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_POL_INVERT_EN_PLL_LOCK_DET_ENABLE_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_POL_INVERT_EN_PLL_LOCK_DET_FORCE_RST_SET_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_POL_INVERT_EN_PLL_LOCK_DET_FORCE_RST_SET_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_POL_INVERT_EN_PLL_LOCK_DET_FORCE_RST_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_POL_INVERT_EN_PLL_LOCK_DET_FORCE_RST_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_POL_INVERT_EN_PLL_LOCK_DET_FORCE_RST_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_POL_INVERT_EN_PLL_LOCK_DET_FORCE_RST_SET_EN_MASK 0x2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_lock_det_enable : 1;
- unsigned int pll_lock_det_force_rst_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_lock_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_D2R_IF_POL_INVERT_EN_ADDR 0x4001d368
-
-
-/* pll_lock_r2d_if_val register */
-/*----------------------*/
-/* PLL Lock RF interface : regfile value */
-/* pll_lock_out : PLL lock detect signal */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_R2D_IF_VAL_PLL_LOCK_OUT_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_R2D_IF_VAL_PLL_LOCK_OUT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_lock_out : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_lock_r2d_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_R2D_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_R2D_IF_VAL_DYNAMIC true
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_R2D_IF_VAL_SNAPCLOCK 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_R2D_IF_VAL_ADDR 0x4001d36c
-
-
-/* pll_lock_r2d_if_pol_invert_en register */
-/*----------------------*/
-/* PLL Lock RF interface : polarity invert control */
-/* pll_lock_out : Polarity invert control for pll_lock_out */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_R2D_IF_POL_INVERT_EN_PLL_LOCK_OUT_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_R2D_IF_POL_INVERT_EN_PLL_LOCK_OUT_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_R2D_IF_POL_INVERT_EN_PLL_LOCK_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_R2D_IF_POL_INVERT_EN_PLL_LOCK_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_R2D_IF_POL_INVERT_EN_PLL_LOCK_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_R2D_IF_POL_INVERT_EN_PLL_LOCK_OUT_EN_MASK 0x1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_lock_out : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_lock_r2d_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_R2D_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LOCK_R2D_IF_POL_INVERT_EN_ADDR 0x4001d370
-
-
-/* pll_vco_0_d2r_if_val register */
-/*----------------------*/
-/* PLL VCO RF Interface : regfile value */
-/* pll_vco_comp_enable : Enable signal for peak detector */
-/* pll_vco_enable : Enable signal for vco */
-/* pll_vco_fctrl_bin_set : Binary cap settings for vco. NXP to detail */
-/* pll_vco_comp_amp_set : Vref setting for peak detector VCO. NXP to detail */
-/* pll_vco_icore_bin_enable : Enable signal for */
-/* pll_vco_vtune_enable : Enable switch vtune */
-/* pll_vco_vtail_enable : Enable VCO tail resistor */
-/* pll_vco_tx_notrx : VCO settings selector */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_VAL_PLL_VCO_COMP_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_VAL_PLL_VCO_COMP_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_VAL_PLL_VCO_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_VAL_PLL_VCO_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_VAL_PLL_VCO_FCTRL_BIN_SET_MASK 0x003c
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_VAL_PLL_VCO_FCTRL_BIN_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_VAL_PLL_VCO_COMP_AMP_SET_MASK 0x07c0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_VAL_PLL_VCO_COMP_AMP_SET_POS 6
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_VAL_PLL_VCO_ICORE_BIN_ENABLE_MASK 0x0800
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_VAL_PLL_VCO_ICORE_BIN_ENABLE_POS 11
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_VAL_PLL_VCO_VTUNE_ENABLE_MASK 0x1000
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_VAL_PLL_VCO_VTUNE_ENABLE_POS 12
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_VAL_PLL_VCO_VTAIL_ENABLE_MASK 0x2000
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_VAL_PLL_VCO_VTAIL_ENABLE_POS 13
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_VAL_PLL_VCO_TX_NOTRX_MASK 0x4000
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_VAL_PLL_VCO_TX_NOTRX_POS 14
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_vco_comp_enable : 1;
- unsigned int pll_vco_enable : 1;
- unsigned int pll_vco_fctrl_bin_set : 4;
- unsigned int pll_vco_comp_amp_set : 5;
- unsigned int pll_vco_icore_bin_enable : 1;
- unsigned int pll_vco_vtune_enable : 1;
- unsigned int pll_vco_vtail_enable : 1;
- unsigned int pll_vco_tx_notrx : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_vco_0_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_VAL_ADDR 0x4001d374
-
-
-/* pll_vco_0_d2r_if_src_sel register */
-/*----------------------*/
-/* PLL VCO RF Interface : source selection */
-/* pll_vco_comp_enable : Source selection for pll_vco_comp_enable */
-/* pll_vco_enable : Source selection for pll_vco_enable */
-/* pll_vco_fctrl_bin_set : Source selection for pll_vco_fctrl_bin_set */
-/* pll_vco_comp_amp_set : Source selection for pll_vco_comp_amp_set */
-/* pll_vco_tx_notrx : Source selection for pll_vco_tx_notrx */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_COMP_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_COMP_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_COMP_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_COMP_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_COMP_ENABLE_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_COMP_ENABLE_CALIBRATION_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_ENABLE_TMU_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_FCTRL_BIN_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_FCTRL_BIN_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_FCTRL_BIN_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_FCTRL_BIN_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_FCTRL_BIN_SET_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_FCTRL_BIN_SET_CALIBRATION_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_COMP_AMP_SET_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_COMP_AMP_SET_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_COMP_AMP_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_COMP_AMP_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_COMP_AMP_SET_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_COMP_AMP_SET_CALIBRATION_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_TX_NOTRX_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_TX_NOTRX_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_TX_NOTRX_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_TX_NOTRX_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_TX_NOTRX_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_PLL_VCO_TX_NOTRX_TMU_MASK 0x10
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_vco_comp_enable : 1;
- unsigned int pll_vco_enable : 1;
- unsigned int pll_vco_fctrl_bin_set : 1;
- unsigned int pll_vco_comp_amp_set : 1;
- unsigned int pll_vco_tx_notrx : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_vco_0_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_RST 0x16
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_SRC_SEL_ADDR 0x4001d378
-
-
-/* pll_vco_0_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* PLL VCO RF Interface : polarity invert control */
-/* pll_vco_comp_enable : Polarity invert control for pll_vco_comp_enable */
-/* pll_vco_enable : Polarity invert control for pll_vco_enable */
-/* pll_vco_icore_bin_enable : Polarity invert control for pll_vco_icore_bin_enable */
-/* pll_vco_vtune_enable : Polarity invert control for pll_vco_vtune_enable */
-/* pll_vco_vtail_enable : Polarity invert control for pll_vco_vtail_enable */
-/* pll_vco_tx_notrx : Polarity invert control for pll_vco_tx_notrx */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_COMP_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_COMP_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_COMP_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_COMP_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_COMP_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_COMP_ENABLE_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_ENABLE_EN_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_ICORE_BIN_ENABLE_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_ICORE_BIN_ENABLE_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_ICORE_BIN_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_ICORE_BIN_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_ICORE_BIN_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_ICORE_BIN_ENABLE_EN_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_VTUNE_ENABLE_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_VTUNE_ENABLE_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_VTUNE_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_VTUNE_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_VTUNE_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_VTUNE_ENABLE_EN_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_VTAIL_ENABLE_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_VTAIL_ENABLE_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_VTAIL_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_VTAIL_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_VTAIL_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_VTAIL_ENABLE_EN_MASK 0x10
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_TX_NOTRX_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_TX_NOTRX_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_TX_NOTRX_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_TX_NOTRX_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_TX_NOTRX_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_PLL_VCO_TX_NOTRX_EN_MASK 0x20
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_vco_comp_enable : 1;
- unsigned int pll_vco_enable : 1;
- unsigned int pll_vco_icore_bin_enable : 1;
- unsigned int pll_vco_vtune_enable : 1;
- unsigned int pll_vco_vtail_enable : 1;
- unsigned int pll_vco_tx_notrx : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_vco_0_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_0_D2R_IF_POL_INVERT_EN_ADDR 0x4001d37c
-
-
-/* pll_vco_1_d2r_if_val register */
-/*----------------------*/
-/* PLL VCO RF interface : regfile value */
-/* pll_vco_fctrl_therm_set : Thermo cap settings for vco. NXP to detail. */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_1_D2R_IF_VAL_PLL_VCO_FCTRL_THERM_SET_MASK 0x7fff
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_1_D2R_IF_VAL_PLL_VCO_FCTRL_THERM_SET_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_vco_fctrl_therm_set : 15;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_vco_1_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_1_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_1_D2R_IF_VAL_ADDR 0x4001d380
-
-
-/* pll_vco_1_d2r_if_src_sel register */
-/*----------------------*/
-/* PLL VCO RF interface : source selection */
-/* pll_vco_fctrl_therm_set : Source selection for pll_vco_fctrl_therm_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_1_D2R_IF_SRC_SEL_PLL_VCO_FCTRL_THERM_SET_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_1_D2R_IF_SRC_SEL_PLL_VCO_FCTRL_THERM_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_1_D2R_IF_SRC_SEL_PLL_VCO_FCTRL_THERM_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_1_D2R_IF_SRC_SEL_PLL_VCO_FCTRL_THERM_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_1_D2R_IF_SRC_SEL_PLL_VCO_FCTRL_THERM_SET_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_1_D2R_IF_SRC_SEL_PLL_VCO_FCTRL_THERM_SET_CALIBRATION_MASK 0x1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_vco_fctrl_therm_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_vco_1_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_1_D2R_IF_SRC_SEL_RST 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_1_D2R_IF_SRC_SEL_ADDR 0x4001d384
-
-
-/* pll_vco_curset_d2r_if_val register */
-/*----------------------*/
-/* PLL VCO curset interface : regfile value */
-/* pll_vco_curset_rx : Current settings VCO */
-/* pll_vco_curset_tx : Current settings VCO */
-/* pll_vco_curset_set : Current settings vco */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_CURSET_D2R_IF_VAL_PLL_VCO_CURSET_RX_MASK 0x001f
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_CURSET_D2R_IF_VAL_PLL_VCO_CURSET_RX_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_CURSET_D2R_IF_VAL_PLL_VCO_CURSET_TX_MASK 0x03e0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_CURSET_D2R_IF_VAL_PLL_VCO_CURSET_TX_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_CURSET_D2R_IF_VAL_PLL_VCO_CURSET_SET_MASK 0x7c00
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_CURSET_D2R_IF_VAL_PLL_VCO_CURSET_SET_POS 10
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_vco_curset_rx : 5;
- unsigned int pll_vco_curset_tx : 5;
- unsigned int pll_vco_curset_set : 5;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_vco_curset_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_CURSET_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_CURSET_D2R_IF_VAL_ADDR 0x4001d388
-
-
-/* pll_vco_curset_d2r_if_src_sel register */
-/*----------------------*/
-/* PLL VCO curset Interface : source selection */
-/* pll_vco_curset_rx : Source selection for pll_vco_curset_rx */
-/* pll_vco_curset_tx : Source selection for pll_vco_curset_tx */
-/* pll_vco_curset_set : Source selection for pll_vco_curset_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_CURSET_D2R_IF_SRC_SEL_PLL_VCO_CURSET_RX_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_CURSET_D2R_IF_SRC_SEL_PLL_VCO_CURSET_RX_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_CURSET_D2R_IF_SRC_SEL_PLL_VCO_CURSET_RX_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_CURSET_D2R_IF_SRC_SEL_PLL_VCO_CURSET_RX_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_CURSET_D2R_IF_SRC_SEL_PLL_VCO_CURSET_RX_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_CURSET_D2R_IF_SRC_SEL_PLL_VCO_CURSET_RX_CALIBRATION_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_CURSET_D2R_IF_SRC_SEL_PLL_VCO_CURSET_TX_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_CURSET_D2R_IF_SRC_SEL_PLL_VCO_CURSET_TX_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_CURSET_D2R_IF_SRC_SEL_PLL_VCO_CURSET_TX_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_CURSET_D2R_IF_SRC_SEL_PLL_VCO_CURSET_TX_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_CURSET_D2R_IF_SRC_SEL_PLL_VCO_CURSET_TX_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_CURSET_D2R_IF_SRC_SEL_PLL_VCO_CURSET_TX_CALIBRATION_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_CURSET_D2R_IF_SRC_SEL_PLL_VCO_CURSET_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_CURSET_D2R_IF_SRC_SEL_PLL_VCO_CURSET_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_CURSET_D2R_IF_SRC_SEL_PLL_VCO_CURSET_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_CURSET_D2R_IF_SRC_SEL_PLL_VCO_CURSET_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_CURSET_D2R_IF_SRC_SEL_PLL_VCO_CURSET_SET_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_CURSET_D2R_IF_SRC_SEL_PLL_VCO_CURSET_SET_CALIBRATION_MASK 0x4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_vco_curset_rx : 1;
- unsigned int pll_vco_curset_tx : 1;
- unsigned int pll_vco_curset_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_vco_curset_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_CURSET_D2R_IF_SRC_SEL_RST 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_CURSET_D2R_IF_SRC_SEL_ADDR 0x4001d38c
-
-
-/* pll_lf_d2r_if_val register */
-/*----------------------*/
-/* PLL LF RF interface : regfile value */
-/* pll_lf_open_set : LF Open */
-/* pll_lf_pch_n_set : Precharge settings. 0x0 : disabled. Xxx : enable resistor from supply to Vtune. */
-/* pll_lf_pch_p_set : Precharge settings. 0x0 : disabled. Xxx : enable resisotr from supply to Vtune. */
-/* pll_lf_lock_boost_enable : Enable signal for boost mode LF */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_VAL_PLL_LF_OPEN_SET_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_VAL_PLL_LF_OPEN_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_VAL_PLL_LF_PCH_N_SET_MASK 0x000e
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_VAL_PLL_LF_PCH_N_SET_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_VAL_PLL_LF_PCH_P_SET_MASK 0x0070
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_VAL_PLL_LF_PCH_P_SET_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_VAL_PLL_LF_LOCK_BOOST_ENABLE_MASK 0x0080
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_VAL_PLL_LF_LOCK_BOOST_ENABLE_POS 7
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_lf_open_set : 1;
- unsigned int pll_lf_pch_n_set : 3;
- unsigned int pll_lf_pch_p_set : 3;
- unsigned int pll_lf_lock_boost_enable : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_lf_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_VAL_ADDR 0x4001d390
-
-
-/* pll_lf_d2r_if_src_sel register */
-/*----------------------*/
-/* PLL LF RF interface : source selection */
-/* pll_lf_open_set : Source selection for pll_lf_open_set */
-/* pll_lf_pch_n_set : Source selection for pll_lf_pch_n_set */
-/* pll_lf_pch_p_set : Source selection for pll_lf_pch_p_set */
-/* pll_lf_lock_boost_enable : Source selection for pll_lf_lock_boost_enable */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_SRC_SEL_PLL_LF_OPEN_SET_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_SRC_SEL_PLL_LF_OPEN_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_SRC_SEL_PLL_LF_OPEN_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_SRC_SEL_PLL_LF_OPEN_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_SRC_SEL_PLL_LF_OPEN_SET_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_SRC_SEL_PLL_LF_OPEN_SET_CALIBRATION_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_SRC_SEL_PLL_LF_PCH_N_SET_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_SRC_SEL_PLL_LF_PCH_N_SET_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_SRC_SEL_PLL_LF_PCH_N_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_SRC_SEL_PLL_LF_PCH_N_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_SRC_SEL_PLL_LF_PCH_N_SET_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_SRC_SEL_PLL_LF_PCH_N_SET_CALIBRATION_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_SRC_SEL_PLL_LF_PCH_P_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_SRC_SEL_PLL_LF_PCH_P_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_SRC_SEL_PLL_LF_PCH_P_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_SRC_SEL_PLL_LF_PCH_P_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_SRC_SEL_PLL_LF_PCH_P_SET_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_SRC_SEL_PLL_LF_PCH_P_SET_CALIBRATION_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_SRC_SEL_PLL_LF_LOCK_BOOST_ENABLE_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_SRC_SEL_PLL_LF_LOCK_BOOST_ENABLE_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_SRC_SEL_PLL_LF_LOCK_BOOST_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_SRC_SEL_PLL_LF_LOCK_BOOST_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_SRC_SEL_PLL_LF_LOCK_BOOST_ENABLE_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_SRC_SEL_PLL_LF_LOCK_BOOST_ENABLE_CALIBRATION_MASK 0x8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_lf_open_set : 1;
- unsigned int pll_lf_pch_n_set : 1;
- unsigned int pll_lf_pch_p_set : 1;
- unsigned int pll_lf_lock_boost_enable : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_lf_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_SRC_SEL_RST 0x6
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_SRC_SEL_ADDR 0x4001d394
-
-
-/* pll_lf_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* PLL LF RF interface : polarity invert control */
-/* pll_lf_open_set : Polarity invert control for pll_lf_open_set */
-/* pll_lf_lock_boost_enable : Polarity invert control for pll_lf_lock_boost_enable */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_POL_INVERT_EN_PLL_LF_OPEN_SET_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_POL_INVERT_EN_PLL_LF_OPEN_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_POL_INVERT_EN_PLL_LF_OPEN_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_POL_INVERT_EN_PLL_LF_OPEN_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_POL_INVERT_EN_PLL_LF_OPEN_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_POL_INVERT_EN_PLL_LF_OPEN_SET_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_POL_INVERT_EN_PLL_LF_LOCK_BOOST_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_POL_INVERT_EN_PLL_LF_LOCK_BOOST_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_POL_INVERT_EN_PLL_LF_LOCK_BOOST_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_POL_INVERT_EN_PLL_LF_LOCK_BOOST_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_POL_INVERT_EN_PLL_LF_LOCK_BOOST_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_POL_INVERT_EN_PLL_LF_LOCK_BOOST_ENABLE_EN_MASK 0x2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_lf_open_set : 1;
- unsigned int pll_lf_lock_boost_enable : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_lf_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_LF_D2R_IF_POL_INVERT_EN_ADDR 0x4001d398
-
-
-/* pll_divn_d2r_if_val register */
-/*----------------------*/
-/* PLL Divider RF interface : regfile value */
-/* pll_divn_fo_test_enable : Enable divider N feedback test */
-/* pll_divn_set : Settings divider N. N = code in decimal */
-/* pll_divn_sdm_pol_set : PLL SDM clock polarity w.r.t. pfd feedback clock */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_VAL_PLL_DIVN_FO_TEST_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_VAL_PLL_DIVN_FO_TEST_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_VAL_PLL_DIVN_SET_MASK 0x00fe
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_VAL_PLL_DIVN_SET_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_VAL_PLL_DIVN_SDM_POL_SET_MASK 0x0100
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_VAL_PLL_DIVN_SDM_POL_SET_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_divn_fo_test_enable : 1;
- unsigned int pll_divn_set : 7;
- unsigned int pll_divn_sdm_pol_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_divn_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_VAL_ADDR 0x4001d39c
-
-
-/* pll_divn_d2r_if_src_sel register */
-/*----------------------*/
-/* PLL Divider RF interface : source selection */
-/* pll_divn_set : Source selection for pll_divn_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_SRC_SEL_PLL_DIVN_SET_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_SRC_SEL_PLL_DIVN_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_SRC_SEL_PLL_DIVN_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_SRC_SEL_PLL_DIVN_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_SRC_SEL_PLL_DIVN_SET_SYNTHESIZER 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_SRC_SEL_PLL_DIVN_SET_SYNTHESIZER_MASK 0x1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_divn_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_divn_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_SRC_SEL_RST 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_SRC_SEL_ADDR 0x4001d3a0
-
-
-/* pll_divn_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* PLL Divider RF interface : polarity invert control */
-/* pll_divn_fo_test_enable : Polarity invert control for pll_divn_fo_test_enable */
-/* pll_divn_sdm_pol_set : Polarity invert control for pll_divn_sdm_pol_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_POL_INVERT_EN_PLL_DIVN_FO_TEST_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_POL_INVERT_EN_PLL_DIVN_FO_TEST_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_POL_INVERT_EN_PLL_DIVN_FO_TEST_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_POL_INVERT_EN_PLL_DIVN_FO_TEST_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_POL_INVERT_EN_PLL_DIVN_FO_TEST_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_POL_INVERT_EN_PLL_DIVN_FO_TEST_ENABLE_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_POL_INVERT_EN_PLL_DIVN_SDM_POL_SET_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_POL_INVERT_EN_PLL_DIVN_SDM_POL_SET_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_POL_INVERT_EN_PLL_DIVN_SDM_POL_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_POL_INVERT_EN_PLL_DIVN_SDM_POL_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_POL_INVERT_EN_PLL_DIVN_SDM_POL_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_POL_INVERT_EN_PLL_DIVN_SDM_POL_SET_EN_MASK 0x2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_divn_fo_test_enable : 1;
- unsigned int pll_divn_sdm_pol_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_divn_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVN_D2R_IF_POL_INVERT_EN_ADDR 0x4001d3a4
-
-
-/* pll_cal_d2r_if_val register */
-/*----------------------*/
-/* PLL Calibration RF Interface : regfile value */
-/* pll_cal_enable : Enable calibration counter */
-/* pll_cal_ip_aac_fref_set : AAC calibration reference */
-/* pll_cal_ip_aafc_enable : AAFC enable */
-/* pll_cal_ip_afc_fref_set : AFC calibration reference */
-/* pll_cal_ip_det_fref_set : DET calibration reference */
-/* pll_cal_ip_test_enable : Test enable calibration */
-/* pll_cal_ip_vco_rst_set : Reset calibration */
-/* pll_cal_div_set : Pll cal divset */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_VAL_PLL_CAL_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_VAL_PLL_CAL_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_VAL_PLL_CAL_IP_AAC_FREF_SET_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_VAL_PLL_CAL_IP_AAC_FREF_SET_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_VAL_PLL_CAL_IP_AAFC_ENABLE_MASK 0x0040
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_VAL_PLL_CAL_IP_AAFC_ENABLE_POS 6
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_VAL_PLL_CAL_IP_AFC_FREF_SET_MASK 0x0080
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_VAL_PLL_CAL_IP_AFC_FREF_SET_POS 7
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_VAL_PLL_CAL_IP_DET_FREF_SET_MASK 0x0100
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_VAL_PLL_CAL_IP_DET_FREF_SET_POS 8
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_VAL_PLL_CAL_IP_TEST_ENABLE_MASK 0x0200
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_VAL_PLL_CAL_IP_TEST_ENABLE_POS 9
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_VAL_PLL_CAL_IP_VCO_RST_SET_MASK 0x0400
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_VAL_PLL_CAL_IP_VCO_RST_SET_POS 10
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_VAL_PLL_CAL_DIV_SET_MASK 0x7800
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_VAL_PLL_CAL_DIV_SET_POS 11
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_cal_enable : 1;
- unsigned int : 4;
- unsigned int pll_cal_ip_aac_fref_set : 1;
- unsigned int pll_cal_ip_aafc_enable : 1;
- unsigned int pll_cal_ip_afc_fref_set : 1;
- unsigned int pll_cal_ip_det_fref_set : 1;
- unsigned int pll_cal_ip_test_enable : 1;
- unsigned int pll_cal_ip_vco_rst_set : 1;
- unsigned int pll_cal_div_set : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_cal_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_VAL_ADDR 0x4001d3a8
-
-
-/* pll_cal_d2r_if_src_sel register */
-/*----------------------*/
-/* PLL calibration RF interface : source selection */
-/* pll_cal_enable : Source selection for pll_cal_enable */
-/* pll_cal_ip_aac_fref_set : Source selection for pll_cal_ip_aac_fref_set */
-/* pll_cal_ip_aafc_enable : Source selection for pll_cal_if_aafc_enable */
-/* pll_cal_ip_afc_fref_set : Source selection for pll_cal_ip_afc_fref_set */
-/* pll_cal_ip_det_fref_set : Source selection for pll_cal_ip_det_fref_set */
-/* pll_cal_ip_vco_rst_set : Source selection for pll_cal_ip_vco_rst_set */
-/* pll_cal_div_set : Source selection for pll_cal_div_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_ENABLE_TMU_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_AAC_FREF_SET_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_AAC_FREF_SET_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_AAC_FREF_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_AAC_FREF_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_AAC_FREF_SET_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_AAC_FREF_SET_CALIBRATION_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_AAFC_ENABLE_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_AAFC_ENABLE_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_AAFC_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_AAFC_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_AAFC_ENABLE_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_AAFC_ENABLE_CALIBRATION_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_AFC_FREF_SET_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_AFC_FREF_SET_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_AFC_FREF_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_AFC_FREF_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_AFC_FREF_SET_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_AFC_FREF_SET_CALIBRATION_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_DET_FREF_SET_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_DET_FREF_SET_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_DET_FREF_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_DET_FREF_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_DET_FREF_SET_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_DET_FREF_SET_CALIBRATION_MASK 0x10
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_VCO_RST_SET_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_VCO_RST_SET_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_VCO_RST_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_VCO_RST_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_VCO_RST_SET_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_IP_VCO_RST_SET_CALIBRATION_MASK 0x20
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_DIV_SET_MASK 0x0040
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_DIV_SET_POS 6
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_DIV_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_DIV_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_DIV_SET_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_PLL_CAL_DIV_SET_CALIBRATION_MASK 0x40
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_cal_enable : 1;
- unsigned int pll_cal_ip_aac_fref_set : 1;
- unsigned int pll_cal_ip_aafc_enable : 1;
- unsigned int pll_cal_ip_afc_fref_set : 1;
- unsigned int pll_cal_ip_det_fref_set : 1;
- unsigned int pll_cal_ip_vco_rst_set : 1;
- unsigned int pll_cal_div_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_cal_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_RST 0x7f
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_SRC_SEL_ADDR 0x4001d3ac
-
-
-/* pll_cal_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* PLL calibration RF interface : polarity invert control */
-/* pll_cal_enable : Polarity invert control for pll_cal_enable */
-/* pll_cal_ip_aac_fref_set : Polarity invert control for pll_cal_ip_aac_fref_set */
-/* pll_cal_ip_aafc_enable : Polarity invert control for pll_cal_ip_aafc_enable */
-/* pll_cal_ip_afc_fref_set : Polarity invert control for pll_cal_ip_afc_fref_set */
-/* pll_cal_ip_det_fref_set : Polarity invert control for pll_cal_ip_det_fref_set */
-/* pll_cal_ip_test_enable : Polarity invert control for pll_cal_ip_test_enable */
-/* pll_cal_ip_vco_rst_set : Polarity invert control for pll_cal_ip_vco_rst_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_ENABLE_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_AAC_FREF_SET_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_AAC_FREF_SET_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_AAC_FREF_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_AAC_FREF_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_AAC_FREF_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_AAC_FREF_SET_EN_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_AAFC_ENABLE_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_AAFC_ENABLE_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_AAFC_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_AAFC_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_AAFC_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_AAFC_ENABLE_EN_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_AFC_FREF_SET_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_AFC_FREF_SET_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_AFC_FREF_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_AFC_FREF_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_AFC_FREF_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_AFC_FREF_SET_EN_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_DET_FREF_SET_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_DET_FREF_SET_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_DET_FREF_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_DET_FREF_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_DET_FREF_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_DET_FREF_SET_EN_MASK 0x10
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_TEST_ENABLE_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_TEST_ENABLE_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_TEST_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_TEST_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_TEST_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_TEST_ENABLE_EN_MASK 0x20
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_VCO_RST_SET_MASK 0x0040
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_VCO_RST_SET_POS 6
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_VCO_RST_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_VCO_RST_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_VCO_RST_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_PLL_CAL_IP_VCO_RST_SET_EN_MASK 0x40
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_cal_enable : 1;
- unsigned int pll_cal_ip_aac_fref_set : 1;
- unsigned int pll_cal_ip_aafc_enable : 1;
- unsigned int pll_cal_ip_afc_fref_set : 1;
- unsigned int pll_cal_ip_det_fref_set : 1;
- unsigned int pll_cal_ip_test_enable : 1;
- unsigned int pll_cal_ip_vco_rst_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_cal_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_D2R_IF_POL_INVERT_EN_ADDR 0x4001d3b0
-
-
-/* pll_cal_0_r2d_if_val register */
-/*----------------------*/
-/* PLL calibration RF interface : regfile value */
-/* pll_cal_op_det_toggle : DET (out of range) toggle */
-/* pll_cal_op_det_m : DET (out of range) counter value */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_0_R2D_IF_VAL_PLL_CAL_OP_DET_TOGGLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_0_R2D_IF_VAL_PLL_CAL_OP_DET_TOGGLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_0_R2D_IF_VAL_PLL_CAL_OP_DET_M_MASK 0x03fe
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_0_R2D_IF_VAL_PLL_CAL_OP_DET_M_POS 1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_cal_op_det_toggle : 1;
- unsigned int pll_cal_op_det_m : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_cal_0_r2d_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_0_R2D_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_0_R2D_IF_VAL_DYNAMIC true
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_0_R2D_IF_VAL_SNAPCLOCK 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_0_R2D_IF_VAL_ADDR 0x4001d3b4
-
-
-/* pll_cal_0_r2d_if_pol_invert_en register */
-/*----------------------*/
-/* PLL calibration RF interface : polarity invert control */
-/* pll_cal_op_det_toggle : Polarity invert control for pll_cal_op_det_toggle */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_0_R2D_IF_POL_INVERT_EN_PLL_CAL_OP_DET_TOGGLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_0_R2D_IF_POL_INVERT_EN_PLL_CAL_OP_DET_TOGGLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_0_R2D_IF_POL_INVERT_EN_PLL_CAL_OP_DET_TOGGLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_0_R2D_IF_POL_INVERT_EN_PLL_CAL_OP_DET_TOGGLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_0_R2D_IF_POL_INVERT_EN_PLL_CAL_OP_DET_TOGGLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_0_R2D_IF_POL_INVERT_EN_PLL_CAL_OP_DET_TOGGLE_EN_MASK 0x1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_cal_op_det_toggle : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_cal_0_r2d_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_0_R2D_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_0_R2D_IF_POL_INVERT_EN_ADDR 0x4001d3b8
-
-
-/* pll_cal_1_r2d_if_val register */
-/*----------------------*/
-/* PLL calibration RF interface : regfile value */
-/* pll_cal_op_afc_m : AFC counter value */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_1_R2D_IF_VAL_PLL_CAL_OP_AFC_M_MASK 0x0fff
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_1_R2D_IF_VAL_PLL_CAL_OP_AFC_M_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_cal_op_afc_m : 12;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_cal_1_r2d_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_1_R2D_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_1_R2D_IF_VAL_DYNAMIC true
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_1_R2D_IF_VAL_SNAPCLOCK 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CAL_1_R2D_IF_VAL_ADDR 0x4001d3bc
-
-
-/* various_d2r_if_val register */
-/*----------------------*/
-/* Various RF interface : regfile value */
-/* pll_vsw_delay_set : Delay settings switch LF. NXP to detail. */
-/* pll_vsw_enable : Enable signal for switch LF */
-/* rx_pacal_set : Drives multiplexor at input of I_aaf filter ot select mixer output */
-/* xo16m_to_rfp_enable : Enable the 16MHz clock to RFP */
-/* rx_iqswap_ipath_set : Invert pn on ipath */
-/* rx_iqswap_qpath_set : Invert pn on qpath */
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_VAL_PLL_VSW_DELAY_SET_MASK 0x0003
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_VAL_PLL_VSW_DELAY_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_VAL_PLL_VSW_ENABLE_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_VAL_PLL_VSW_ENABLE_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_VAL_RX_PACAL_SET_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_VAL_RX_PACAL_SET_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_VAL_RX_PACAL_SET_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_VAL_RX_PACAL_SET_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_VAL_RX_PACAL_SET_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_VAL_RX_PACAL_SET_HIGH_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_VAL_XO16M_TO_RFP_ENABLE_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_VAL_XO16M_TO_RFP_ENABLE_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_VAL_RX_IQSWAP_IPATH_SET_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_VAL_RX_IQSWAP_IPATH_SET_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_VAL_RX_IQSWAP_QPATH_SET_MASK 0x0040
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_VAL_RX_IQSWAP_QPATH_SET_POS 6
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_vsw_delay_set : 2;
- unsigned int pll_vsw_enable : 1;
- unsigned int rx_pacal_set : 1;
- unsigned int xo16m_to_rfp_enable : 1;
- unsigned int rx_iqswap_ipath_set : 1;
- unsigned int rx_iqswap_qpath_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_various_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_VAL_ADDR 0x4001d3c0
-
-
-/* various_d2r_if_src_sel register */
-/*----------------------*/
-/* Various RF interface : source selection */
-/* pll_vsw_delay_set : Source selection for pll_vsw_delay */
-/* pll_vsw_enable : Source selection for pll_vsw_enable */
-/* rx_pacal_set : Source selection for rx_pacal_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_SRC_SEL_PLL_VSW_DELAY_SET_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_SRC_SEL_PLL_VSW_DELAY_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_SRC_SEL_PLL_VSW_DELAY_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_SRC_SEL_PLL_VSW_DELAY_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_SRC_SEL_PLL_VSW_DELAY_SET_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_SRC_SEL_PLL_VSW_DELAY_SET_CALIBRATION_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_SRC_SEL_PLL_VSW_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_SRC_SEL_PLL_VSW_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_SRC_SEL_PLL_VSW_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_SRC_SEL_PLL_VSW_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_SRC_SEL_PLL_VSW_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_SRC_SEL_PLL_VSW_ENABLE_TMU_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_SRC_SEL_RX_PACAL_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_SRC_SEL_RX_PACAL_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_SRC_SEL_RX_PACAL_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_SRC_SEL_RX_PACAL_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_SRC_SEL_RX_PACAL_SET_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_SRC_SEL_RX_PACAL_SET_TMU_MASK 0x4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_vsw_delay_set : 1;
- unsigned int pll_vsw_enable : 1;
- unsigned int rx_pacal_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_various_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_SRC_SEL_RST 0x6
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_SRC_SEL_ADDR 0x4001d3c4
-
-
-/* various_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* Various RF interface : polarity invert control */
-/* pll_vsw_enable : Polarity invert control for pll_vsw_enable */
-/* rx_pacal_set : Polarity invert control for rx_pacal_set */
-/* xo16m_to_rfp_enable : Polarity invert control for xo16m_to_rfp_enable */
-/* rx_iqswap_ipath_set : Polarity invert control for rx_iqswap_ipath_set */
-/* rx_iqswap_qpath_set : Polarity invert control for rx_iqswap_qpath_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_PLL_VSW_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_PLL_VSW_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_PLL_VSW_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_PLL_VSW_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_PLL_VSW_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_PLL_VSW_ENABLE_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_RX_PACAL_SET_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_RX_PACAL_SET_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_RX_PACAL_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_RX_PACAL_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_RX_PACAL_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_RX_PACAL_SET_EN_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_XO16M_TO_RFP_ENABLE_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_XO16M_TO_RFP_ENABLE_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_XO16M_TO_RFP_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_XO16M_TO_RFP_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_XO16M_TO_RFP_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_XO16M_TO_RFP_ENABLE_EN_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_RX_IQSWAP_IPATH_SET_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_RX_IQSWAP_IPATH_SET_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_RX_IQSWAP_IPATH_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_RX_IQSWAP_IPATH_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_RX_IQSWAP_IPATH_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_RX_IQSWAP_IPATH_SET_EN_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_RX_IQSWAP_QPATH_SET_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_RX_IQSWAP_QPATH_SET_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_RX_IQSWAP_QPATH_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_RX_IQSWAP_QPATH_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_RX_IQSWAP_QPATH_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_RX_IQSWAP_QPATH_SET_EN_MASK 0x10
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_vsw_enable : 1;
- unsigned int rx_pacal_set : 1;
- unsigned int xo16m_to_rfp_enable : 1;
- unsigned int rx_iqswap_ipath_set : 1;
- unsigned int rx_iqswap_qpath_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_various_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_VARIOUS_D2R_IF_POL_INVERT_EN_ADDR 0x4001d3c8
-
-
-/* radio_ctrl_d2r_if_val register */
-/*----------------------*/
-/* Radio Control RF interface : regfile value */
-/* ref_div2_enable : Reference divider control */
-#define EXTAPB_REGFILE_TRANSCEIVER_RADIO_CTRL_D2R_IF_VAL_REF_DIV2_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_RADIO_CTRL_D2R_IF_VAL_REF_DIV2_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RADIO_CTRL_D2R_IF_VAL_REF_DIV2_ENABLE_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RADIO_CTRL_D2R_IF_VAL_REF_DIV2_ENABLE_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RADIO_CTRL_D2R_IF_VAL_REF_DIV2_ENABLE_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RADIO_CTRL_D2R_IF_VAL_REF_DIV2_ENABLE_HIGH_MASK 0x1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int ref_div2_enable : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_radio_ctrl_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_RADIO_CTRL_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RADIO_CTRL_D2R_IF_VAL_ADDR 0x4001d3cc
-
-
-/* r_rc_cal_d2r_if_val register */
-/*----------------------*/
-/* R and RC Calibration RF interface : regfile value */
-/* rx_r_cal_enable : R calibration enable */
-/* rx_rccal_enable : RC calibration enable */
-/* rx_r_cal_trimr_halflsb_set : R cal 1 percent resistance control bit. */
-/* rx_rccal_trig : RC transient release trigger */
-/* trimr_set : R Calibration trim value */
-/* trimc_set : RC calibration trim value */
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_VAL_RX_R_CAL_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_VAL_RX_R_CAL_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_VAL_RX_R_CAL_ENABLE_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_VAL_RX_R_CAL_ENABLE_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_VAL_RX_R_CAL_ENABLE_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_VAL_RX_R_CAL_ENABLE_HIGH_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_VAL_RX_RCCAL_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_VAL_RX_RCCAL_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_VAL_RX_RCCAL_ENABLE_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_VAL_RX_RCCAL_ENABLE_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_VAL_RX_RCCAL_ENABLE_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_VAL_RX_RCCAL_ENABLE_HIGH_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_VAL_RX_R_CAL_TRIMR_HALFLSB_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_VAL_RX_R_CAL_TRIMR_HALFLSB_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_VAL_RX_RCCAL_TRIG_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_VAL_RX_RCCAL_TRIG_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_VAL_RX_RCCAL_TRIG_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_VAL_RX_RCCAL_TRIG_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_VAL_RX_RCCAL_TRIG_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_VAL_RX_RCCAL_TRIG_HIGH_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_VAL_TRIMR_SET_MASK 0x01f0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_VAL_TRIMR_SET_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_VAL_TRIMC_SET_MASK 0x0e00
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_VAL_TRIMC_SET_POS 9
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_r_cal_enable : 1;
- unsigned int rx_rccal_enable : 1;
- unsigned int rx_r_cal_trimr_halflsb_set : 1;
- unsigned int rx_rccal_trig : 1;
- unsigned int trimr_set : 5;
- unsigned int trimc_set : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_r_rc_cal_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_VAL_RST 0x6a0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_VAL_ADDR 0x4001d3d0
-
-
-/* r_rc_cal_d2r_if_src_sel register */
-/*----------------------*/
-/* R and RC Calibration RF interface : source selection */
-/* rx_r_cal_enable : Source selection for rx_r_cal_enable */
-/* rx_rccal_enable : Source selection for rx_rccal_enable */
-/* rx_r_cal_trimr_halflsb_set : Source selection for rx_r_cal_trimr_halflsb_set */
-/* rx_rccal_trig : Source selection for rx_rccal_trig */
-/* trimr_set : Source selection for rx_trimr_set */
-/* trimc_set : Source selection for rx_trimc_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_RX_R_CAL_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_RX_R_CAL_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_RX_R_CAL_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_RX_R_CAL_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_RX_R_CAL_ENABLE_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_RX_R_CAL_ENABLE_CALIBRATION_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_RX_RCCAL_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_RX_RCCAL_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_RX_RCCAL_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_RX_RCCAL_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_RX_RCCAL_ENABLE_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_RX_RCCAL_ENABLE_CALIBRATION_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_RX_R_CAL_TRIMR_HALFLSB_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_RX_R_CAL_TRIMR_HALFLSB_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_RX_R_CAL_TRIMR_HALFLSB_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_RX_R_CAL_TRIMR_HALFLSB_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_RX_R_CAL_TRIMR_HALFLSB_SET_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_RX_R_CAL_TRIMR_HALFLSB_SET_CALIBRATION_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_RX_RCCAL_TRIG_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_RX_RCCAL_TRIG_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_RX_RCCAL_TRIG_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_RX_RCCAL_TRIG_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_RX_RCCAL_TRIG_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_RX_RCCAL_TRIG_CALIBRATION_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_TRIMR_SET_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_TRIMR_SET_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_TRIMR_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_TRIMR_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_TRIMR_SET_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_TRIMR_SET_CALIBRATION_MASK 0x10
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_TRIMC_SET_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_TRIMC_SET_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_TRIMC_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_TRIMC_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_TRIMC_SET_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_TRIMC_SET_CALIBRATION_MASK 0x20
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_r_cal_enable : 1;
- unsigned int rx_rccal_enable : 1;
- unsigned int rx_r_cal_trimr_halflsb_set : 1;
- unsigned int rx_rccal_trig : 1;
- unsigned int trimr_set : 1;
- unsigned int trimc_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_r_rc_cal_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_SRC_SEL_ADDR 0x4001d3d4
-
-
-/* r_rc_cal_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* R and RC Calibration RF interface : polarity invert control */
-/* rx_r_cal_enable : Polarity invert control for rx_r_cal_enable */
-/* rx_rccal_enable : Polarity invert control for rx_rccal_enable */
-/* rx_r_cal_trimr_halflsb_set : Polarity invert control for rx_rx_cal_trimr_halflsb_set */
-/* rx_rccal_trig : Polarity invert control for rx_rccal_trig */
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_POL_INVERT_EN_RX_R_CAL_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_POL_INVERT_EN_RX_R_CAL_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_POL_INVERT_EN_RX_R_CAL_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_POL_INVERT_EN_RX_R_CAL_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_POL_INVERT_EN_RX_R_CAL_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_POL_INVERT_EN_RX_R_CAL_ENABLE_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_POL_INVERT_EN_RX_RCCAL_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_POL_INVERT_EN_RX_RCCAL_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_POL_INVERT_EN_RX_RCCAL_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_POL_INVERT_EN_RX_RCCAL_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_POL_INVERT_EN_RX_RCCAL_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_POL_INVERT_EN_RX_RCCAL_ENABLE_EN_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_POL_INVERT_EN_RX_R_CAL_TRIMR_HALFLSB_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_POL_INVERT_EN_RX_R_CAL_TRIMR_HALFLSB_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_POL_INVERT_EN_RX_R_CAL_TRIMR_HALFLSB_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_POL_INVERT_EN_RX_R_CAL_TRIMR_HALFLSB_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_POL_INVERT_EN_RX_R_CAL_TRIMR_HALFLSB_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_POL_INVERT_EN_RX_R_CAL_TRIMR_HALFLSB_SET_EN_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_POL_INVERT_EN_RX_RCCAL_TRIG_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_POL_INVERT_EN_RX_RCCAL_TRIG_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_POL_INVERT_EN_RX_RCCAL_TRIG_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_POL_INVERT_EN_RX_RCCAL_TRIG_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_POL_INVERT_EN_RX_RCCAL_TRIG_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_POL_INVERT_EN_RX_RCCAL_TRIG_EN_MASK 0x8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_r_cal_enable : 1;
- unsigned int rx_rccal_enable : 1;
- unsigned int rx_r_cal_trimr_halflsb_set : 1;
- unsigned int rx_rccal_trig : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_r_rc_cal_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_D2R_IF_POL_INVERT_EN_ADDR 0x4001d3d8
-
-
-/* r_rc_cal_r2d_if_val register */
-/*----------------------*/
-/* R and RC calibration RF interface : regfile value */
-/* rx_r_cal_fb : R cal buffered comparator output (0.8V) */
-/* rx_rccal_fb : RC Cal buffere comparator output (0.8V) */
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_R2D_IF_VAL_RX_R_CAL_FB_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_R2D_IF_VAL_RX_R_CAL_FB_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_R2D_IF_VAL_RX_RCCAL_FB_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_R2D_IF_VAL_RX_RCCAL_FB_POS 1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_r_cal_fb : 1;
- unsigned int rx_rccal_fb : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_r_rc_cal_r2d_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_R2D_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_R2D_IF_VAL_DYNAMIC true
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_R2D_IF_VAL_SNAPCLOCK 0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_R2D_IF_VAL_ADDR 0x4001d3dc
-
-
-/* r_rc_cal_r2d_if_pol_invert_en register */
-/*----------------------*/
-/* R and RC Calibration RF interface : polarity invert control */
-/* rx_r_cal_fb : Polarity invert control for rx_r_cal_fb */
-/* rx_rccal_fb : Polarity invert contro for rx_rccal_fb */
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_R2D_IF_POL_INVERT_EN_RX_R_CAL_FB_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_R2D_IF_POL_INVERT_EN_RX_R_CAL_FB_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_R2D_IF_POL_INVERT_EN_RX_R_CAL_FB_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_R2D_IF_POL_INVERT_EN_RX_R_CAL_FB_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_R2D_IF_POL_INVERT_EN_RX_R_CAL_FB_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_R2D_IF_POL_INVERT_EN_RX_R_CAL_FB_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_R2D_IF_POL_INVERT_EN_RX_RCCAL_FB_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_R2D_IF_POL_INVERT_EN_RX_RCCAL_FB_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_R2D_IF_POL_INVERT_EN_RX_RCCAL_FB_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_R2D_IF_POL_INVERT_EN_RX_RCCAL_FB_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_R2D_IF_POL_INVERT_EN_RX_RCCAL_FB_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_R2D_IF_POL_INVERT_EN_RX_RCCAL_FB_EN_MASK 0x2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_r_cal_fb : 1;
- unsigned int rx_rccal_fb : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_r_rc_cal_r2d_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_R2D_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_R_RC_CAL_R2D_IF_POL_INVERT_EN_ADDR 0x4001d3e0
-
-
-/* dcoff_d2r_if_val register */
-/*----------------------*/
-/* DC offset RF interface : regfile value */
-/* rx_dcoff_i_enable : DC Offset enable I channel */
-/* rx_dcoff_q_enable : DC Offset enable Q channel */
-/* rx_dcoff_i_set : Programmable offset current control word 4-bits. Positive offset creates negative voltage shift. */
-/* rx_dcoff_q_set : Programmable offset current control word 4-bits. Positive offset creates negative voltage shift. */
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_VAL_RX_DCOFF_I_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_VAL_RX_DCOFF_I_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_VAL_RX_DCOFF_I_ENABLE_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_VAL_RX_DCOFF_I_ENABLE_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_VAL_RX_DCOFF_I_ENABLE_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_VAL_RX_DCOFF_I_ENABLE_HIGH_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_VAL_RX_DCOFF_Q_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_VAL_RX_DCOFF_Q_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_VAL_RX_DCOFF_Q_ENABLE_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_VAL_RX_DCOFF_Q_ENABLE_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_VAL_RX_DCOFF_Q_ENABLE_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_VAL_RX_DCOFF_Q_ENABLE_HIGH_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_VAL_RX_DCOFF_I_SET_MASK 0x003c
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_VAL_RX_DCOFF_I_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_VAL_RX_DCOFF_Q_SET_MASK 0x03c0
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_VAL_RX_DCOFF_Q_SET_POS 6
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_dcoff_i_enable : 1;
- unsigned int rx_dcoff_q_enable : 1;
- unsigned int rx_dcoff_i_set : 4;
- unsigned int rx_dcoff_q_set : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_dcoff_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_VAL_ADDR 0x4001d3e4
-
-
-/* dcoff_d2r_if_src_sel register */
-/*----------------------*/
-/* DC Offset RF interface : source selection */
-/* rx_dcoff_i_enable : Source selection for rx_dcoff_i_enable */
-/* rx_dcoff_q_enable : Source selection for rx_dcoff_q_enable */
-/* rx_dcoff_i_set : Source selection for rx_dcoff_i_set */
-/* rx_dcoff_q_set : Source selection for rx_dcoff_q_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_SRC_SEL_RX_DCOFF_I_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_SRC_SEL_RX_DCOFF_I_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_SRC_SEL_RX_DCOFF_I_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_SRC_SEL_RX_DCOFF_I_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_SRC_SEL_RX_DCOFF_I_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_SRC_SEL_RX_DCOFF_I_ENABLE_TMU_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_SRC_SEL_RX_DCOFF_Q_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_SRC_SEL_RX_DCOFF_Q_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_SRC_SEL_RX_DCOFF_Q_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_SRC_SEL_RX_DCOFF_Q_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_SRC_SEL_RX_DCOFF_Q_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_SRC_SEL_RX_DCOFF_Q_ENABLE_TMU_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_SRC_SEL_RX_DCOFF_I_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_SRC_SEL_RX_DCOFF_I_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_SRC_SEL_RX_DCOFF_I_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_SRC_SEL_RX_DCOFF_I_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_SRC_SEL_RX_DCOFF_I_SET_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_SRC_SEL_RX_DCOFF_I_SET_CALIBRATION_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_SRC_SEL_RX_DCOFF_Q_SET_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_SRC_SEL_RX_DCOFF_Q_SET_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_SRC_SEL_RX_DCOFF_Q_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_SRC_SEL_RX_DCOFF_Q_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_SRC_SEL_RX_DCOFF_Q_SET_CALIBRATION 1
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_SRC_SEL_RX_DCOFF_Q_SET_CALIBRATION_MASK 0x8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_dcoff_i_enable : 1;
- unsigned int rx_dcoff_q_enable : 1;
- unsigned int rx_dcoff_i_set : 1;
- unsigned int rx_dcoff_q_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_dcoff_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_SRC_SEL_RST 0x3
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_SRC_SEL_ADDR 0x4001d3e8
-
-
-/* dcoff_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* DC Offset RF interface : polarity invert control */
-/* rx_dcoff_i_enable : Polarity invert control for rx_dcoff_i_enable */
-/* rx_dcoff_q_enable : Polarity invert control for rx_dcoff_q_enable */
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_POL_INVERT_EN_RX_DCOFF_I_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_POL_INVERT_EN_RX_DCOFF_I_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_POL_INVERT_EN_RX_DCOFF_I_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_POL_INVERT_EN_RX_DCOFF_I_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_POL_INVERT_EN_RX_DCOFF_I_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_POL_INVERT_EN_RX_DCOFF_I_ENABLE_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_POL_INVERT_EN_RX_DCOFF_Q_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_POL_INVERT_EN_RX_DCOFF_Q_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_POL_INVERT_EN_RX_DCOFF_Q_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_POL_INVERT_EN_RX_DCOFF_Q_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_POL_INVERT_EN_RX_DCOFF_Q_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_POL_INVERT_EN_RX_DCOFF_Q_ENABLE_EN_MASK 0x2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_dcoff_i_enable : 1;
- unsigned int rx_dcoff_q_enable : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_dcoff_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_DCOFF_D2R_IF_POL_INVERT_EN_ADDR 0x4001d3ec
-
-
-/* dummy_output_d2r_if_val register */
-/*----------------------*/
-/* Reserved outputs RF interface : regfile value */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-/* dummy_output : Reserved outputs */
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_OUTPUT_D2R_IF_VAL_DUMMY_OUTPUT_MASK 0xffff
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_OUTPUT_D2R_IF_VAL_DUMMY_OUTPUT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int dummy_output : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_dummy_output_d2r_if_val;
-#else
-/* pll_lf_rlf2_set_1v1_set : Programmable Post Filter cut-off frequency (ES1 last minute change) - Allows Trade-Off Between PLL Phase Margin and Spurs ans SDM Noise Rejection - Trimm the Rlf2 resistor value of this RC Low-pass filter (constant 4.81pF capacitor value) Rlf2 = 21k + 21k * rlf2_set<0> + 42k * rlf2_set<1> with rlf2_set<1:0>=0 default */
-/* rx_dcoffset_dac_dis_1v1_set : DC-offset compensation DAC disabling (ES2 change) - 0: DC-offset compensation DAC enabled (default) -1: DC-offset compensation DAC disabled */
-/* pll_xoflag_dcy_1v1_set : Selection of the XO flag input triggering duty cycle range (ES2 change) - 0x01 (default): [0.25, 0.75] duty cycle range for flag output rising edge, [0.17, 0.83] duty cycle range for flag output falling edge. */
-/* vco_gain_adj : Coarse trimming of the VCO gain in analog domain (ES2 change) 0x00: Nominal value (default), 0x01: +30%, 0x11: -30% */
-/* pre_const_len_tie : drives the bit [7:5] of the setting tx_datapath.pre_const_len, since they are not driven by the original register now.(expected to be set to 0) */
-/* ll_agc_rssi_ready_ignore : When set AGC_RSSI_READY is ignored during link layer state machine radio switch off */
-/* ad_double_zero_detect : Antenna diversity false ?0? symbols detection improvement enable - 0: Antenna switching stopped after one ?0? symbol detected - 1: Antenna switching stopped after two ?0? symbols detected */
-/* ad_timer_only : disable antenna diversity rssi_valid - 0: Switching will be based on rssi_valid signal [ES2 behaviour] - 1: Switching will be based on a timer only */
-/* g1_grp_forced : Radio group G1 is forced on when this bit is set */
-/* g2_grp_forced : Radio group G2 is forced on when this bit is set. */
-/* pll_grp_forced : Radio group PLL is forced on when this bit is set. */
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_OUTPUT_D2R_IF_VAL_PLL_LF_RLF2_SET_1V1_SET_MASK 0x0003
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_OUTPUT_D2R_IF_VAL_PLL_LF_RLF2_SET_1V1_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_OUTPUT_D2R_IF_VAL_RX_DCOFFSET_DAC_DIS_1V1_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_OUTPUT_D2R_IF_VAL_RX_DCOFFSET_DAC_DIS_1V1_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_OUTPUT_D2R_IF_VAL_PLL_XOFLAG_DCY_1V1_SET_MASK 0x0018
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_OUTPUT_D2R_IF_VAL_PLL_XOFLAG_DCY_1V1_SET_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_OUTPUT_D2R_IF_VAL_VCO_GAIN_ADJ_MASK 0x0060
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_OUTPUT_D2R_IF_VAL_VCO_GAIN_ADJ_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_OUTPUT_D2R_IF_VAL_PRE_CONST_LEN_TIE_MASK 0x0100
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_OUTPUT_D2R_IF_VAL_PRE_CONST_LEN_TIE_POS 8
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_OUTPUT_D2R_IF_VAL_LL_AGC_RSSI_READY_IGNORE_MASK 0x0200
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_OUTPUT_D2R_IF_VAL_LL_AGC_RSSI_READY_IGNORE_POS 9
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_OUTPUT_D2R_IF_VAL_AD_DOUBLE_ZERO_DETECT_MASK 0x0400
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_OUTPUT_D2R_IF_VAL_AD_DOUBLE_ZERO_DETECT_POS 10
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_OUTPUT_D2R_IF_VAL_AD_TIMER_ONLY_MASK 0x0800
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_OUTPUT_D2R_IF_VAL_AD_TIMER_ONLY_POS 11
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_OUTPUT_D2R_IF_VAL_G1_GRP_FORCED_MASK 0x1000
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_OUTPUT_D2R_IF_VAL_G1_GRP_FORCED_POS 12
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_OUTPUT_D2R_IF_VAL_G2_GRP_FORCED_MASK 0x2000
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_OUTPUT_D2R_IF_VAL_G2_GRP_FORCED_POS 13
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_OUTPUT_D2R_IF_VAL_PLL_GRP_FORCED_MASK 0x4000
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_OUTPUT_D2R_IF_VAL_PLL_GRP_FORCED_POS 14
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_lf_rlf2_set_1v1_set : 2;
- unsigned int rx_dcoffset_dac_dis_1v1_set : 1;
- unsigned int pll_xoflag_dcy_1v1_set : 2;
- unsigned int vco_gain_adj : 2;
- unsigned int : 1;
- unsigned int pre_const_len_tie : 1;
- unsigned int ll_agc_rssi_ready_ignore : 1;
- unsigned int ad_double_zero_detect : 1;
- unsigned int ad_timer_only : 1;
- unsigned int g1_grp_forced : 1;
- unsigned int g2_grp_forced : 1;
- unsigned int pll_grp_forced : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_dummy_output_d2r_if_val;
-#endif
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_OUTPUT_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_OUTPUT_D2R_IF_VAL_ADDR 0x4001d3f0
-
-
-/* dummy_input_r2d_if_val register */
-/*----------------------*/
-/* Reserved inputs RF interface : regfile value */
-/* dummy_input : Reserved inputs */
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_INPUT_R2D_IF_VAL_DUMMY_INPUT_MASK 0x00ff
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_INPUT_R2D_IF_VAL_DUMMY_INPUT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int dummy_input : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_dummy_input_r2d_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_INPUT_R2D_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_INPUT_R2D_IF_VAL_DYNAMIC true
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_INPUT_R2D_IF_VAL_SNAPCLOCK 0
-#define EXTAPB_REGFILE_TRANSCEIVER_DUMMY_INPUT_R2D_IF_VAL_ADDR 0x4001d3f4
-
-
-/* tmu_grp_g_d2r_if_val register */
-/*----------------------*/
-/* TMU Global Power Sequencing RF interface : regfile value */
-/* tmu_grp_g1_sig_0_out : TMU Global Power Sequencing G1 wire 0 value */
-/* tmu_grp_g1_sig_1_out : TMU Global Power Sequencing G1 wire 1 value */
-/* tmu_grp_g1_sig_2_out : TMU Global Power Sequencing G1 wire 2 value */
-/* tmu_grp_g1_sig_3_out : TMU Global Power Sequencing G1 wire 3 value */
-/* tmu_grp_g2_sig_0_out : TMU Global Power Sequencing G2 wire 0 value */
-/* tmu_grp_g2_sig_1_out : TMU Global Power Sequencing G2 wire 1 value */
-/* tmu_grp_g2_sig_2_out : TMU Global Power Sequencing G2 wire 2 value */
-/* tmu_grp_g2_sig_3_out : TMU Global Power Sequencing G2 wire 3 value */
-/* tmu_grp_pll_sig_out : TMU Global Power Sequencing PLL wire value */
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G1_SIG_0_OUT_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G1_SIG_0_OUT_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G1_SIG_0_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G1_SIG_0_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G1_SIG_0_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G1_SIG_0_OUT_HIGH_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G1_SIG_1_OUT_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G1_SIG_1_OUT_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G1_SIG_1_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G1_SIG_1_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G1_SIG_1_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G1_SIG_1_OUT_HIGH_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G1_SIG_2_OUT_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G1_SIG_2_OUT_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G1_SIG_2_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G1_SIG_2_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G1_SIG_2_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G1_SIG_2_OUT_HIGH_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G1_SIG_3_OUT_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G1_SIG_3_OUT_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G1_SIG_3_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G1_SIG_3_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G1_SIG_3_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G1_SIG_3_OUT_HIGH_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G2_SIG_0_OUT_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G2_SIG_0_OUT_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G2_SIG_0_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G2_SIG_0_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G2_SIG_0_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G2_SIG_0_OUT_HIGH_MASK 0x10
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G2_SIG_1_OUT_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G2_SIG_1_OUT_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G2_SIG_1_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G2_SIG_1_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G2_SIG_1_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G2_SIG_1_OUT_HIGH_MASK 0x20
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G2_SIG_2_OUT_MASK 0x0040
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G2_SIG_2_OUT_POS 6
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G2_SIG_2_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G2_SIG_2_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G2_SIG_2_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G2_SIG_2_OUT_HIGH_MASK 0x40
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G2_SIG_3_OUT_MASK 0x0080
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G2_SIG_3_OUT_POS 7
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G2_SIG_3_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G2_SIG_3_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G2_SIG_3_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_G2_SIG_3_OUT_HIGH_MASK 0x80
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_PLL_SIG_OUT_MASK 0x0100
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_PLL_SIG_OUT_POS 8
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_PLL_SIG_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_PLL_SIG_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_PLL_SIG_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_TMU_GRP_PLL_SIG_OUT_HIGH_MASK 0x100
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int tmu_grp_g1_sig_0_out : 1;
- unsigned int tmu_grp_g1_sig_1_out : 1;
- unsigned int tmu_grp_g1_sig_2_out : 1;
- unsigned int tmu_grp_g1_sig_3_out : 1;
- unsigned int tmu_grp_g2_sig_0_out : 1;
- unsigned int tmu_grp_g2_sig_1_out : 1;
- unsigned int tmu_grp_g2_sig_2_out : 1;
- unsigned int tmu_grp_g2_sig_3_out : 1;
- unsigned int tmu_grp_pll_sig_out : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_tmu_grp_g_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_VAL_ADDR 0x4001d3f8
-
-
-/* tmu_grp_g_d2r_if_src_sel register */
-/*----------------------*/
-/* TMU Global Power Sequencing RF Interface : source selection */
-/* tmu_grp_g1_sig_0_out : Source selection for tmu_grp_g1_sig_0_out */
-/* tmu_grp_g1_sig_1_out : Source selection for tmu_grp_g1_sig_1_out */
-/* tmu_grp_g1_sig_2_out : Source selection for tmu_grp_g1_sig_2_out */
-/* tmu_grp_g1_sig_3_out : Source selection for tmu_grp_g1_sig_3_out */
-/* tmu_grp_g2_sig_0_out : Source selection for tmu_grp_g2_sig_0_out */
-/* tmu_grp_g2_sig_1_out : Source selection for tmu_grp_g2_sig_1_out */
-/* tmu_grp_g2_sig_2_out : Source selection for tmu_grp_g2_sig_2_out */
-/* tmu_grp_g2_sig_3_out : Source selection for tmu_grp_g2_sig_3_out */
-/* tmu_grp_pll_sig_out : Source selection for tmu_grp_pll_sig_out */
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G1_SIG_0_OUT_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G1_SIG_0_OUT_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G1_SIG_0_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G1_SIG_0_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G1_SIG_0_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G1_SIG_0_OUT_TMU_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G1_SIG_1_OUT_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G1_SIG_1_OUT_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G1_SIG_1_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G1_SIG_1_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G1_SIG_1_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G1_SIG_1_OUT_TMU_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G1_SIG_2_OUT_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G1_SIG_2_OUT_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G1_SIG_2_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G1_SIG_2_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G1_SIG_2_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G1_SIG_2_OUT_TMU_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G1_SIG_3_OUT_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G1_SIG_3_OUT_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G1_SIG_3_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G1_SIG_3_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G1_SIG_3_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G1_SIG_3_OUT_TMU_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G2_SIG_0_OUT_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G2_SIG_0_OUT_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G2_SIG_0_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G2_SIG_0_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G2_SIG_0_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G2_SIG_0_OUT_TMU_MASK 0x10
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G2_SIG_1_OUT_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G2_SIG_1_OUT_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G2_SIG_1_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G2_SIG_1_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G2_SIG_1_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G2_SIG_1_OUT_TMU_MASK 0x20
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G2_SIG_2_OUT_MASK 0x0040
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G2_SIG_2_OUT_POS 6
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G2_SIG_2_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G2_SIG_2_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G2_SIG_2_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G2_SIG_2_OUT_TMU_MASK 0x40
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G2_SIG_3_OUT_MASK 0x0080
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G2_SIG_3_OUT_POS 7
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G2_SIG_3_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G2_SIG_3_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G2_SIG_3_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_G2_SIG_3_OUT_TMU_MASK 0x80
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_PLL_SIG_OUT_MASK 0x0100
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_PLL_SIG_OUT_POS 8
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_PLL_SIG_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_PLL_SIG_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_PLL_SIG_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_TMU_GRP_PLL_SIG_OUT_TMU_MASK 0x100
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int tmu_grp_g1_sig_0_out : 1;
- unsigned int tmu_grp_g1_sig_1_out : 1;
- unsigned int tmu_grp_g1_sig_2_out : 1;
- unsigned int tmu_grp_g1_sig_3_out : 1;
- unsigned int tmu_grp_g2_sig_0_out : 1;
- unsigned int tmu_grp_g2_sig_1_out : 1;
- unsigned int tmu_grp_g2_sig_2_out : 1;
- unsigned int tmu_grp_g2_sig_3_out : 1;
- unsigned int tmu_grp_pll_sig_out : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_tmu_grp_g_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_RST 0x1ff
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_SRC_SEL_ADDR 0x4001d3fc
-
-
-/* tmu_grp_g_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* TMU Global Power Sequencing RF Interface : polarity invert control */
-/* tmu_grp_g1_sig_0_out : Polarity invert control for tmu_grp_g1_sig_0_out */
-/* tmu_grp_g1_sig_1_out : Polarity invert control for tmu_grp_g1_sig_1_out */
-/* tmu_grp_g1_sig_2_out : Polarity invert control for tmu_grp_g1_sig_2_out */
-/* tmu_grp_g1_sig_3_out : Polarity invert control for tmu_grp_g1_sig_3_out */
-/* tmu_grp_g2_sig_0_out : Polarity invert control for tmu_grp_g2_sig_0_out */
-/* tmu_grp_g2_sig_1_out : Polarity invert control for tmu_grp_g2_sig_1_out */
-/* tmu_grp_g2_sig_2_out : Polarity invert control for tmu_grp_g2_sig_2_out */
-/* tmu_grp_g2_sig_3_out : Polarity invert control for tmu_grp_g2_sig_3_out */
-/* tmu_grp_pll_sig_out : Polarity invert control for tmu_grp_pll_sig_out */
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G1_SIG_0_OUT_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G1_SIG_0_OUT_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G1_SIG_0_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G1_SIG_0_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G1_SIG_0_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G1_SIG_0_OUT_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G1_SIG_1_OUT_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G1_SIG_1_OUT_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G1_SIG_1_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G1_SIG_1_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G1_SIG_1_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G1_SIG_1_OUT_EN_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G1_SIG_2_OUT_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G1_SIG_2_OUT_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G1_SIG_2_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G1_SIG_2_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G1_SIG_2_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G1_SIG_2_OUT_EN_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G1_SIG_3_OUT_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G1_SIG_3_OUT_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G1_SIG_3_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G1_SIG_3_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G1_SIG_3_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G1_SIG_3_OUT_EN_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G2_SIG_0_OUT_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G2_SIG_0_OUT_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G2_SIG_0_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G2_SIG_0_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G2_SIG_0_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G2_SIG_0_OUT_EN_MASK 0x10
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G2_SIG_1_OUT_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G2_SIG_1_OUT_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G2_SIG_1_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G2_SIG_1_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G2_SIG_1_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G2_SIG_1_OUT_EN_MASK 0x20
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G2_SIG_2_OUT_MASK 0x0040
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G2_SIG_2_OUT_POS 6
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G2_SIG_2_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G2_SIG_2_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G2_SIG_2_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G2_SIG_2_OUT_EN_MASK 0x40
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G2_SIG_3_OUT_MASK 0x0080
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G2_SIG_3_OUT_POS 7
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G2_SIG_3_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G2_SIG_3_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G2_SIG_3_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_G2_SIG_3_OUT_EN_MASK 0x80
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_PLL_SIG_OUT_MASK 0x0100
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_PLL_SIG_OUT_POS 8
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_PLL_SIG_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_PLL_SIG_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_PLL_SIG_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_TMU_GRP_PLL_SIG_OUT_EN_MASK 0x100
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int tmu_grp_g1_sig_0_out : 1;
- unsigned int tmu_grp_g1_sig_1_out : 1;
- unsigned int tmu_grp_g1_sig_2_out : 1;
- unsigned int tmu_grp_g1_sig_3_out : 1;
- unsigned int tmu_grp_g2_sig_0_out : 1;
- unsigned int tmu_grp_g2_sig_1_out : 1;
- unsigned int tmu_grp_g2_sig_2_out : 1;
- unsigned int tmu_grp_g2_sig_3_out : 1;
- unsigned int tmu_grp_pll_sig_out : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_tmu_grp_g_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_G_D2R_IF_POL_INVERT_EN_ADDR 0x4001d400
-
-
-/* tmu_grp_tx_d2r_if_val register */
-/*----------------------*/
-/* TMU TX Power Sequencing RF Interface : regfile value */
-/* tmu_grp_tx1_sig_0_out : TMU Tx Power Sequencing TX1 wire 0 value */
-/* tmu_grp_tx1_sig_1_out : TMU Tx Power Sequencing TX1 wire 1 value */
-/* tmu_grp_tx1_sig_2_out : TMU Tx Power Sequencing TX1 wire 2 value */
-/* tmu_grp_tx1_sig_3_out : TMU Tx Power Sequencing TX1 wire 3 value */
-/* tmu_grp_tx2_sig_0_out : TMU Tx Power Sequencing TX2 wire 0 value */
-/* tmu_grp_tx2_sig_1_out : TMU Tx Power Sequencing TX2 wire 1 value */
-/* tmu_grp_tx2_sig_2_out : TMU Tx Power Sequencing TX2 wire 2 value */
-/* tmu_grp_tx2_sig_3_out : TMU Tx Power Sequencing TX2 wire 3 value */
-/* tmu_grp_tx3_sig_0_out : TMU Tx Power Sequencing TX3 wire 0 value */
-/* tmu_grp_tx3_sig_1_out : TMU Tx Power Sequencing TX3 wire 1 value */
-/* tmu_grp_tx3_sig_2_out : TMU Tx Power Sequencing TX3 wire 2 value */
-/* tmu_grp_tx3_sig_3_out : TMU Tx Power Sequencing TX3 wire 3 value */
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX1_SIG_0_OUT_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX1_SIG_0_OUT_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX1_SIG_0_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX1_SIG_0_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX1_SIG_0_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX1_SIG_0_OUT_HIGH_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX1_SIG_1_OUT_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX1_SIG_1_OUT_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX1_SIG_1_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX1_SIG_1_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX1_SIG_1_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX1_SIG_1_OUT_HIGH_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX1_SIG_2_OUT_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX1_SIG_2_OUT_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX1_SIG_2_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX1_SIG_2_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX1_SIG_2_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX1_SIG_2_OUT_HIGH_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX1_SIG_3_OUT_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX1_SIG_3_OUT_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX1_SIG_3_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX1_SIG_3_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX1_SIG_3_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX1_SIG_3_OUT_HIGH_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX2_SIG_0_OUT_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX2_SIG_0_OUT_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX2_SIG_0_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX2_SIG_0_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX2_SIG_0_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX2_SIG_0_OUT_HIGH_MASK 0x10
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX2_SIG_1_OUT_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX2_SIG_1_OUT_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX2_SIG_1_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX2_SIG_1_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX2_SIG_1_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX2_SIG_1_OUT_HIGH_MASK 0x20
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX2_SIG_2_OUT_MASK 0x0040
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX2_SIG_2_OUT_POS 6
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX2_SIG_2_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX2_SIG_2_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX2_SIG_2_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX2_SIG_2_OUT_HIGH_MASK 0x40
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX2_SIG_3_OUT_MASK 0x0080
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX2_SIG_3_OUT_POS 7
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX2_SIG_3_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX2_SIG_3_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX2_SIG_3_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX2_SIG_3_OUT_HIGH_MASK 0x80
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX3_SIG_0_OUT_MASK 0x0100
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX3_SIG_0_OUT_POS 8
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX3_SIG_0_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX3_SIG_0_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX3_SIG_0_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX3_SIG_0_OUT_HIGH_MASK 0x100
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX3_SIG_1_OUT_MASK 0x0200
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX3_SIG_1_OUT_POS 9
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX3_SIG_1_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX3_SIG_1_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX3_SIG_1_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX3_SIG_1_OUT_HIGH_MASK 0x200
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX3_SIG_2_OUT_MASK 0x0400
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX3_SIG_2_OUT_POS 10
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX3_SIG_2_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX3_SIG_2_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX3_SIG_2_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX3_SIG_2_OUT_HIGH_MASK 0x400
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX3_SIG_3_OUT_MASK 0x0800
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX3_SIG_3_OUT_POS 11
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX3_SIG_3_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX3_SIG_3_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX3_SIG_3_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_TMU_GRP_TX3_SIG_3_OUT_HIGH_MASK 0x800
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int tmu_grp_tx1_sig_0_out : 1;
- unsigned int tmu_grp_tx1_sig_1_out : 1;
- unsigned int tmu_grp_tx1_sig_2_out : 1;
- unsigned int tmu_grp_tx1_sig_3_out : 1;
- unsigned int tmu_grp_tx2_sig_0_out : 1;
- unsigned int tmu_grp_tx2_sig_1_out : 1;
- unsigned int tmu_grp_tx2_sig_2_out : 1;
- unsigned int tmu_grp_tx2_sig_3_out : 1;
- unsigned int tmu_grp_tx3_sig_0_out : 1;
- unsigned int tmu_grp_tx3_sig_1_out : 1;
- unsigned int tmu_grp_tx3_sig_2_out : 1;
- unsigned int tmu_grp_tx3_sig_3_out : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_tmu_grp_tx_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_VAL_ADDR 0x4001d404
-
-
-/* tmu_grp_tx_d2r_if_src_sel register */
-/*----------------------*/
-/* TMU TX Power sequencing RF interface : source selection */
-/* tmu_grp_tx1_sig_0_out : Source selection for tmu_grp_tx1_sig_0_out */
-/* tmu_grp_tx1_sig_1_out : Source selection for tmu_grp_tx1_sig_1_out */
-/* tmu_grp_tx1_sig_2_out : Source selectoin for tmu_grp_tx1_sig_2_out */
-/* tmu_grp_tx1_sig_3_out : Source selection for tmu_grp_tx1_sig_3_out */
-/* tmu_grp_tx2_sig_0_out : Source selection for tmu_grp_tx2_sig_0_out */
-/* tmu_grp_tx2_sig_1_out : Source selection for tmu_grp_tx2_sig_1_out */
-/* tmu_grp_tx2_sig_2_out : Source selection for tmu_grp_tx2_sig_2_out */
-/* tmu_grp_tx2_sig_3_out : Source selection for tmu_grp_tx2_sig_3_out */
-/* tmu_grp_tx3_sig_0_out : Source selection for tmu_grp_tx3_sig_0_out */
-/* tmu_grp_tx3_sig_1_out : Source selection for tmu_grp_tx3_sig_1_out */
-/* tmu_grp_tx3_sig_2_out : Source selection for tmu_grp_tx3_sig_2_out */
-/* tmu_grp_tx3_sig_3_out : Source selection for tmu_grp_tx3_sig_3_out */
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX1_SIG_0_OUT_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX1_SIG_0_OUT_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX1_SIG_0_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX1_SIG_0_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX1_SIG_0_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX1_SIG_0_OUT_TMU_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX1_SIG_1_OUT_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX1_SIG_1_OUT_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX1_SIG_1_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX1_SIG_1_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX1_SIG_1_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX1_SIG_1_OUT_TMU_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX1_SIG_2_OUT_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX1_SIG_2_OUT_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX1_SIG_2_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX1_SIG_2_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX1_SIG_2_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX1_SIG_2_OUT_TMU_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX1_SIG_3_OUT_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX1_SIG_3_OUT_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX1_SIG_3_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX1_SIG_3_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX1_SIG_3_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX1_SIG_3_OUT_TMU_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX2_SIG_0_OUT_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX2_SIG_0_OUT_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX2_SIG_0_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX2_SIG_0_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX2_SIG_0_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX2_SIG_0_OUT_TMU_MASK 0x10
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX2_SIG_1_OUT_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX2_SIG_1_OUT_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX2_SIG_1_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX2_SIG_1_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX2_SIG_1_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX2_SIG_1_OUT_TMU_MASK 0x20
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX2_SIG_2_OUT_MASK 0x0040
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX2_SIG_2_OUT_POS 6
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX2_SIG_2_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX2_SIG_2_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX2_SIG_2_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX2_SIG_2_OUT_TMU_MASK 0x40
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX2_SIG_3_OUT_MASK 0x0080
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX2_SIG_3_OUT_POS 7
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX2_SIG_3_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX2_SIG_3_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX2_SIG_3_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX2_SIG_3_OUT_TMU_MASK 0x80
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX3_SIG_0_OUT_MASK 0x0100
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX3_SIG_0_OUT_POS 8
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX3_SIG_0_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX3_SIG_0_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX3_SIG_0_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX3_SIG_0_OUT_TMU_MASK 0x100
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX3_SIG_1_OUT_MASK 0x0200
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX3_SIG_1_OUT_POS 9
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX3_SIG_1_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX3_SIG_1_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX3_SIG_1_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX3_SIG_1_OUT_TMU_MASK 0x200
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX3_SIG_2_OUT_MASK 0x0400
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX3_SIG_2_OUT_POS 10
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX3_SIG_2_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX3_SIG_2_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX3_SIG_2_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX3_SIG_2_OUT_TMU_MASK 0x400
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX3_SIG_3_OUT_MASK 0x0800
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX3_SIG_3_OUT_POS 11
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX3_SIG_3_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX3_SIG_3_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX3_SIG_3_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_TMU_GRP_TX3_SIG_3_OUT_TMU_MASK 0x800
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int tmu_grp_tx1_sig_0_out : 1;
- unsigned int tmu_grp_tx1_sig_1_out : 1;
- unsigned int tmu_grp_tx1_sig_2_out : 1;
- unsigned int tmu_grp_tx1_sig_3_out : 1;
- unsigned int tmu_grp_tx2_sig_0_out : 1;
- unsigned int tmu_grp_tx2_sig_1_out : 1;
- unsigned int tmu_grp_tx2_sig_2_out : 1;
- unsigned int tmu_grp_tx2_sig_3_out : 1;
- unsigned int tmu_grp_tx3_sig_0_out : 1;
- unsigned int tmu_grp_tx3_sig_1_out : 1;
- unsigned int tmu_grp_tx3_sig_2_out : 1;
- unsigned int tmu_grp_tx3_sig_3_out : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_tmu_grp_tx_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_RST 0xfff
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_SRC_SEL_ADDR 0x4001d408
-
-
-/* tmu_grp_tx_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* TMU Tx Power Sequencing RF Interface : polarity invert control */
-/* tmu_grp_tx1_sig_0_out : Polarity invert control for tmu_grp_tx1_sig_0_out */
-/* tmu_grp_tx1_sig_1_out : Polarity invert control for tmu_grp_tx1_sig_1_out */
-/* tmu_grp_tx1_sig_2_out : Polarity invert control for tmu_grp_tx1_sig_2_out */
-/* tmu_grp_tx1_sig_3_out : Polarity invert control for tmu_grp_tx1_sig_3_out */
-/* tmu_grp_tx2_sig_0_out : Polarity invert control for tmu_grp_tx2_sig_0_out */
-/* tmu_grp_tx2_sig_1_out : Polarity invert control for tmu_grp_tx2_sig_1_out */
-/* tmu_grp_tx2_sig_2_out : Polarity invert control for tmu_grp_tx2_sig_2_out */
-/* tmu_grp_tx2_sig_3_out : Polarity invert control for tmu_grp_tx2_sig_3_out */
-/* tmu_grp_tx3_sig_0_out : Polarity invert control for tmu_grp_tx3_sig_0_out */
-/* tmu_grp_tx3_sig_1_out : Polarity invert control for tmu_grp_tx3_sig_1_out */
-/* tmu_grp_tx3_sig_2_out : Polarity invert control for tmu_grp_tx3_sig_2_out */
-/* tmu_grp_tx3_sig_3_out : Polarity invert control for tmu_grp_tx3_sig_3_out */
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX1_SIG_0_OUT_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX1_SIG_0_OUT_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX1_SIG_0_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX1_SIG_0_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX1_SIG_0_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX1_SIG_0_OUT_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX1_SIG_1_OUT_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX1_SIG_1_OUT_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX1_SIG_1_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX1_SIG_1_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX1_SIG_1_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX1_SIG_1_OUT_EN_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX1_SIG_2_OUT_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX1_SIG_2_OUT_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX1_SIG_2_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX1_SIG_2_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX1_SIG_2_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX1_SIG_2_OUT_EN_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX1_SIG_3_OUT_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX1_SIG_3_OUT_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX1_SIG_3_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX1_SIG_3_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX1_SIG_3_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX1_SIG_3_OUT_EN_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX2_SIG_0_OUT_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX2_SIG_0_OUT_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX2_SIG_0_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX2_SIG_0_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX2_SIG_0_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX2_SIG_0_OUT_EN_MASK 0x10
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX2_SIG_1_OUT_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX2_SIG_1_OUT_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX2_SIG_1_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX2_SIG_1_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX2_SIG_1_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX2_SIG_1_OUT_EN_MASK 0x20
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX2_SIG_2_OUT_MASK 0x0040
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX2_SIG_2_OUT_POS 6
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX2_SIG_2_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX2_SIG_2_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX2_SIG_2_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX2_SIG_2_OUT_EN_MASK 0x40
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX2_SIG_3_OUT_MASK 0x0080
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX2_SIG_3_OUT_POS 7
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX2_SIG_3_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX2_SIG_3_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX2_SIG_3_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX2_SIG_3_OUT_EN_MASK 0x80
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX3_SIG_0_OUT_MASK 0x0100
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX3_SIG_0_OUT_POS 8
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX3_SIG_0_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX3_SIG_0_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX3_SIG_0_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX3_SIG_0_OUT_EN_MASK 0x100
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX3_SIG_1_OUT_MASK 0x0200
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX3_SIG_1_OUT_POS 9
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX3_SIG_1_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX3_SIG_1_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX3_SIG_1_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX3_SIG_1_OUT_EN_MASK 0x200
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX3_SIG_2_OUT_MASK 0x0400
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX3_SIG_2_OUT_POS 10
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX3_SIG_2_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX3_SIG_2_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX3_SIG_2_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX3_SIG_2_OUT_EN_MASK 0x400
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX3_SIG_3_OUT_MASK 0x0800
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX3_SIG_3_OUT_POS 11
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX3_SIG_3_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX3_SIG_3_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX3_SIG_3_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_TMU_GRP_TX3_SIG_3_OUT_EN_MASK 0x800
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int tmu_grp_tx1_sig_0_out : 1;
- unsigned int tmu_grp_tx1_sig_1_out : 1;
- unsigned int tmu_grp_tx1_sig_2_out : 1;
- unsigned int tmu_grp_tx1_sig_3_out : 1;
- unsigned int tmu_grp_tx2_sig_0_out : 1;
- unsigned int tmu_grp_tx2_sig_1_out : 1;
- unsigned int tmu_grp_tx2_sig_2_out : 1;
- unsigned int tmu_grp_tx2_sig_3_out : 1;
- unsigned int tmu_grp_tx3_sig_0_out : 1;
- unsigned int tmu_grp_tx3_sig_1_out : 1;
- unsigned int tmu_grp_tx3_sig_2_out : 1;
- unsigned int tmu_grp_tx3_sig_3_out : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_tmu_grp_tx_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_TX_D2R_IF_POL_INVERT_EN_ADDR 0x4001d40c
-
-
-/* tmu_grp_rx_d2r_if_val register */
-/*----------------------*/
-/* TMU RX Power sequencing RF interface : regfile value */
-/* tmu_grp_rx1_sig_0_out : TMU Rx Power Sequencing RX1 wire 0 value */
-/* tmu_grp_rx1_sig_1_out : TMU Rx Power Sequencing RX1 wire 1 value */
-/* tmu_grp_rx1_sig_2_out : TMU Rx Power Sequencing RX1 wire 2 value */
-/* tmu_grp_rx1_sig_3_out : TMU Rx Power Sequencing RX1 wire 3 value */
-/* tmu_grp_rx2_sig_0_out : TMU Rx Power Sequencing RX2 wire 0 value */
-/* tmu_grp_rx2_sig_1_out : TMU Rx Power sequencing RX2 wire 1 value */
-/* tmu_grp_rx2_sig_2_out : TMU Rx Power Sequencing RX2 wire 2 value */
-/* tmu_grp_rx2_sig_3_out : TMU Rx Power Sequencing RX2 wire 3 value */
-/* tmu_grp_rx3_sig_0_out : TMU Rx Power Sequencing RX3 wire 0 value */
-/* tmu_grp_rx3_sig_1_out : TMU Rx Power Sequencing RX3 wire 1 value */
-/* tmu_grp_rx3_sig_2_out : TMU Rx Power Sequencing RX3 wire 2 value */
-/* tmu_grp_rx3_sig_3_out : TMU Rx Power Sequencing RX3 wire 3 value */
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX1_SIG_0_OUT_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX1_SIG_0_OUT_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX1_SIG_0_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX1_SIG_0_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX1_SIG_0_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX1_SIG_0_OUT_HIGH_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX1_SIG_1_OUT_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX1_SIG_1_OUT_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX1_SIG_1_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX1_SIG_1_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX1_SIG_1_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX1_SIG_1_OUT_HIGH_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX1_SIG_2_OUT_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX1_SIG_2_OUT_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX1_SIG_2_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX1_SIG_2_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX1_SIG_2_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX1_SIG_2_OUT_HIGH_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX1_SIG_3_OUT_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX1_SIG_3_OUT_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX1_SIG_3_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX1_SIG_3_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX1_SIG_3_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX1_SIG_3_OUT_HIGH_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX2_SIG_0_OUT_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX2_SIG_0_OUT_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX2_SIG_0_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX2_SIG_0_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX2_SIG_0_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX2_SIG_0_OUT_HIGH_MASK 0x10
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX2_SIG_1_OUT_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX2_SIG_1_OUT_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX2_SIG_1_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX2_SIG_1_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX2_SIG_1_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX2_SIG_1_OUT_HIGH_MASK 0x20
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX2_SIG_2_OUT_MASK 0x0040
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX2_SIG_2_OUT_POS 6
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX2_SIG_2_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX2_SIG_2_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX2_SIG_2_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX2_SIG_2_OUT_HIGH_MASK 0x40
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX2_SIG_3_OUT_MASK 0x0080
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX2_SIG_3_OUT_POS 7
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX2_SIG_3_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX2_SIG_3_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX2_SIG_3_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX2_SIG_3_OUT_HIGH_MASK 0x80
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX3_SIG_0_OUT_MASK 0x0100
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX3_SIG_0_OUT_POS 8
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX3_SIG_0_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX3_SIG_0_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX3_SIG_0_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX3_SIG_0_OUT_HIGH_MASK 0x100
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX3_SIG_1_OUT_MASK 0x0200
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX3_SIG_1_OUT_POS 9
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX3_SIG_1_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX3_SIG_1_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX3_SIG_1_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX3_SIG_1_OUT_HIGH_MASK 0x200
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX3_SIG_2_OUT_MASK 0x0400
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX3_SIG_2_OUT_POS 10
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX3_SIG_2_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX3_SIG_2_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX3_SIG_2_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX3_SIG_2_OUT_HIGH_MASK 0x400
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX3_SIG_3_OUT_MASK 0x0800
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX3_SIG_3_OUT_POS 11
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX3_SIG_3_OUT_LOW 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX3_SIG_3_OUT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX3_SIG_3_OUT_HIGH 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_TMU_GRP_RX3_SIG_3_OUT_HIGH_MASK 0x800
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int tmu_grp_rx1_sig_0_out : 1;
- unsigned int tmu_grp_rx1_sig_1_out : 1;
- unsigned int tmu_grp_rx1_sig_2_out : 1;
- unsigned int tmu_grp_rx1_sig_3_out : 1;
- unsigned int tmu_grp_rx2_sig_0_out : 1;
- unsigned int tmu_grp_rx2_sig_1_out : 1;
- unsigned int tmu_grp_rx2_sig_2_out : 1;
- unsigned int tmu_grp_rx2_sig_3_out : 1;
- unsigned int tmu_grp_rx3_sig_0_out : 1;
- unsigned int tmu_grp_rx3_sig_1_out : 1;
- unsigned int tmu_grp_rx3_sig_2_out : 1;
- unsigned int tmu_grp_rx3_sig_3_out : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_tmu_grp_rx_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_VAL_ADDR 0x4001d410
-
-
-/* tmu_grp_rx_d2r_if_src_sel register */
-/*----------------------*/
-/* TMU RX Power Sequencing RF Interface : source selection */
-/* tmu_grp_rx1_sig_0_out : Source selection for tmu_grp_rx1_sig_0_out */
-/* tmu_grp_rx1_sig_1_out : Source selection for tmu_grp_rx1_sig_1_out */
-/* tmu_grp_rx1_sig_2_out : Source selection for tmu_grp_rx1_sig_2_out */
-/* tmu_grp_rx1_sig_3_out : Source selection for tmu_grp_rx1_sig_3_out */
-/* tmu_grp_rx2_sig_0_out : Source selection for tmu_grp_rx2_sig_0_out */
-/* tmu_grp_rx2_sig_1_out : Source selection for tmu_grp_rx2_sig_1_out */
-/* tmu_grp_rx2_sig_2_out : Source selection for tmu_grp_rx2_sig_2_out */
-/* tmu_grp_rx2_sig_3_out : Source selection for tmu_grp_rx2_sig_3_out */
-/* tmu_grp_rx3_sig_0_out : Source selection for tmu_grp_rx3_sig_0_out */
-/* tmu_grp_rx3_sig_1_out : Source selection for tmu_grp_rx3_sig_1_out */
-/* tmu_grp_rx3_sig_2_out : Source selection for tmu_grp_rx3_sig_2_out */
-/* tmu_grp_rx3_sig_3_out : Source selection for tmu_grp_rx3_sig_3_out */
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX1_SIG_0_OUT_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX1_SIG_0_OUT_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX1_SIG_0_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX1_SIG_0_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX1_SIG_0_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX1_SIG_0_OUT_TMU_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX1_SIG_1_OUT_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX1_SIG_1_OUT_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX1_SIG_1_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX1_SIG_1_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX1_SIG_1_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX1_SIG_1_OUT_TMU_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX1_SIG_2_OUT_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX1_SIG_2_OUT_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX1_SIG_2_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX1_SIG_2_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX1_SIG_2_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX1_SIG_2_OUT_TMU_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX1_SIG_3_OUT_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX1_SIG_3_OUT_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX1_SIG_3_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX1_SIG_3_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX1_SIG_3_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX1_SIG_3_OUT_TMU_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX2_SIG_0_OUT_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX2_SIG_0_OUT_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX2_SIG_0_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX2_SIG_0_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX2_SIG_0_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX2_SIG_0_OUT_TMU_MASK 0x10
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX2_SIG_1_OUT_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX2_SIG_1_OUT_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX2_SIG_1_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX2_SIG_1_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX2_SIG_1_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX2_SIG_1_OUT_TMU_MASK 0x20
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX2_SIG_2_OUT_MASK 0x0040
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX2_SIG_2_OUT_POS 6
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX2_SIG_2_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX2_SIG_2_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX2_SIG_2_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX2_SIG_2_OUT_TMU_MASK 0x40
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX2_SIG_3_OUT_MASK 0x0080
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX2_SIG_3_OUT_POS 7
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX2_SIG_3_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX2_SIG_3_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX2_SIG_3_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX2_SIG_3_OUT_TMU_MASK 0x80
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX3_SIG_0_OUT_MASK 0x0100
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX3_SIG_0_OUT_POS 8
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX3_SIG_0_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX3_SIG_0_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX3_SIG_0_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX3_SIG_0_OUT_TMU_MASK 0x100
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX3_SIG_1_OUT_MASK 0x0200
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX3_SIG_1_OUT_POS 9
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX3_SIG_1_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX3_SIG_1_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX3_SIG_1_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX3_SIG_1_OUT_TMU_MASK 0x200
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX3_SIG_2_OUT_MASK 0x0400
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX3_SIG_2_OUT_POS 10
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX3_SIG_2_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX3_SIG_2_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX3_SIG_2_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX3_SIG_2_OUT_TMU_MASK 0x400
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX3_SIG_3_OUT_MASK 0x0800
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX3_SIG_3_OUT_POS 11
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX3_SIG_3_OUT_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX3_SIG_3_OUT_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX3_SIG_3_OUT_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_TMU_GRP_RX3_SIG_3_OUT_TMU_MASK 0x800
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int tmu_grp_rx1_sig_0_out : 1;
- unsigned int tmu_grp_rx1_sig_1_out : 1;
- unsigned int tmu_grp_rx1_sig_2_out : 1;
- unsigned int tmu_grp_rx1_sig_3_out : 1;
- unsigned int tmu_grp_rx2_sig_0_out : 1;
- unsigned int tmu_grp_rx2_sig_1_out : 1;
- unsigned int tmu_grp_rx2_sig_2_out : 1;
- unsigned int tmu_grp_rx2_sig_3_out : 1;
- unsigned int tmu_grp_rx3_sig_0_out : 1;
- unsigned int tmu_grp_rx3_sig_1_out : 1;
- unsigned int tmu_grp_rx3_sig_2_out : 1;
- unsigned int tmu_grp_rx3_sig_3_out : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_tmu_grp_rx_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_RST 0xfff
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_SRC_SEL_ADDR 0x4001d414
-
-
-/* tmu_grp_rx_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* TMU Rx Power sequencing RX interface : polarity invert control */
-/* tmu_grp_rx1_sig_0_out : Polarity invert control for tmu_grp_rx1_sig_0_out */
-/* tmu_grp_rx1_sig_1_out : Polarity invert control for tmu_grp_rx1_sig_1_out */
-/* tmu_grp_rx1_sig_2_out : Polarity invert control for tmu_grp_rx1_sig_2_out */
-/* tmu_grp_rx1_sig_3_out : Polarity invert control for tmu_grp_rx1_sig_3_out */
-/* tmu_grp_rx2_sig_0_out : Polarity invert control for tmu_grp_rx2_sig_0_out */
-/* tmu_grp_rx2_sig_1_out : Polarity invert control for tmu_grp_rx2_sig_1_out */
-/* tmu_grp_rx2_sig_2_out : Polarity invert control for tmu_grp_rx2_sig_2_out */
-/* tmu_grp_rx2_sig_3_out : Polarity invert control for tmu_grp_rx2_sig_3_out */
-/* tmu_grp_rx3_sig_0_out : Polarity invert control for tmu_grp_rx3_sig_0_out */
-/* tmu_grp_rx3_sig_1_out : Polarity invert control for tmu_grp_rx3_sig_1_out */
-/* tmu_grp_rx3_sig_2_out : Polarity invert control for tmu_grp_rx3_sig_2_out */
-/* tmu_grp_rx3_sig_3_out : Polarity invert control for tmu_grp_rx3_sig_3_out */
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX1_SIG_0_OUT_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX1_SIG_0_OUT_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX1_SIG_0_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX1_SIG_0_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX1_SIG_0_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX1_SIG_0_OUT_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX1_SIG_1_OUT_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX1_SIG_1_OUT_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX1_SIG_1_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX1_SIG_1_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX1_SIG_1_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX1_SIG_1_OUT_EN_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX1_SIG_2_OUT_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX1_SIG_2_OUT_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX1_SIG_2_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX1_SIG_2_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX1_SIG_2_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX1_SIG_2_OUT_EN_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX1_SIG_3_OUT_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX1_SIG_3_OUT_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX1_SIG_3_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX1_SIG_3_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX1_SIG_3_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX1_SIG_3_OUT_EN_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX2_SIG_0_OUT_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX2_SIG_0_OUT_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX2_SIG_0_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX2_SIG_0_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX2_SIG_0_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX2_SIG_0_OUT_EN_MASK 0x10
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX2_SIG_1_OUT_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX2_SIG_1_OUT_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX2_SIG_1_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX2_SIG_1_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX2_SIG_1_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX2_SIG_1_OUT_EN_MASK 0x20
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX2_SIG_2_OUT_MASK 0x0040
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX2_SIG_2_OUT_POS 6
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX2_SIG_2_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX2_SIG_2_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX2_SIG_2_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX2_SIG_2_OUT_EN_MASK 0x40
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX2_SIG_3_OUT_MASK 0x0080
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX2_SIG_3_OUT_POS 7
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX2_SIG_3_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX2_SIG_3_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX2_SIG_3_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX2_SIG_3_OUT_EN_MASK 0x80
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX3_SIG_0_OUT_MASK 0x0100
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX3_SIG_0_OUT_POS 8
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX3_SIG_0_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX3_SIG_0_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX3_SIG_0_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX3_SIG_0_OUT_EN_MASK 0x100
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX3_SIG_1_OUT_MASK 0x0200
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX3_SIG_1_OUT_POS 9
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX3_SIG_1_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX3_SIG_1_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX3_SIG_1_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX3_SIG_1_OUT_EN_MASK 0x200
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX3_SIG_2_OUT_MASK 0x0400
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX3_SIG_2_OUT_POS 10
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX3_SIG_2_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX3_SIG_2_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX3_SIG_2_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX3_SIG_2_OUT_EN_MASK 0x400
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX3_SIG_3_OUT_MASK 0x0800
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX3_SIG_3_OUT_POS 11
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX3_SIG_3_OUT_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX3_SIG_3_OUT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX3_SIG_3_OUT_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_TMU_GRP_RX3_SIG_3_OUT_EN_MASK 0x800
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int tmu_grp_rx1_sig_0_out : 1;
- unsigned int tmu_grp_rx1_sig_1_out : 1;
- unsigned int tmu_grp_rx1_sig_2_out : 1;
- unsigned int tmu_grp_rx1_sig_3_out : 1;
- unsigned int tmu_grp_rx2_sig_0_out : 1;
- unsigned int tmu_grp_rx2_sig_1_out : 1;
- unsigned int tmu_grp_rx2_sig_2_out : 1;
- unsigned int tmu_grp_rx2_sig_3_out : 1;
- unsigned int tmu_grp_rx3_sig_0_out : 1;
- unsigned int tmu_grp_rx3_sig_1_out : 1;
- unsigned int tmu_grp_rx3_sig_2_out : 1;
- unsigned int tmu_grp_rx3_sig_3_out : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_tmu_grp_rx_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TMU_GRP_RX_D2R_IF_POL_INVERT_EN_ADDR 0x4001d418
-
-
-/* rx_ldo_d2r_if_val register */
-/*----------------------*/
-/* Rx LDO RF interface : regfile value */
-/* rx_ldo_adc_enable : LDO adc enable */
-/* rx_ldo_adc_pass_set : Set to 1 to enable bypass mode */
-/* rx_ldo_adc_fbres_set : NXP to detail */
-/* rx_ldo_control_0v8_pass : Set to 1 to enable bypass mode */
-/* rx_ldo_control_0v8_ref_sel : Selects between PMU and RF bandgap reference */
-/* rx_ldo_1v4_enable : LDO_1v4 enable */
-/* rx_ldo_1v4_pass_set : Set to 1 to enable bypass mode */
-/* rx_ldo_1v2_vout_set : Flexibility to change the 1.2V output from 1V to 1.2V */
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_VAL_RX_LDO_ADC_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_VAL_RX_LDO_ADC_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_VAL_RX_LDO_ADC_PASS_SET_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_VAL_RX_LDO_ADC_PASS_SET_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_VAL_RX_LDO_ADC_FBRES_SET_MASK 0x007c
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_VAL_RX_LDO_ADC_FBRES_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_VAL_RX_LDO_CONTROL_0V8_PASS_MASK 0x0080
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_VAL_RX_LDO_CONTROL_0V8_PASS_POS 7
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_VAL_RX_LDO_CONTROL_0V8_REF_SEL_MASK 0x0100
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_VAL_RX_LDO_CONTROL_0V8_REF_SEL_POS 8
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_VAL_RX_LDO_1V4_ENABLE_MASK 0x0200
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_VAL_RX_LDO_1V4_ENABLE_POS 9
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_VAL_RX_LDO_1V4_PASS_SET_MASK 0x0400
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_VAL_RX_LDO_1V4_PASS_SET_POS 10
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_VAL_RX_LDO_1V2_VOUT_SET_MASK 0x3800
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_VAL_RX_LDO_1V2_VOUT_SET_POS 11
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_ldo_adc_enable : 1;
- unsigned int rx_ldo_adc_pass_set : 1;
- unsigned int rx_ldo_adc_fbres_set : 5;
- unsigned int rx_ldo_control_0v8_pass : 1;
- unsigned int rx_ldo_control_0v8_ref_sel : 1;
- unsigned int rx_ldo_1v4_enable : 1;
- unsigned int rx_ldo_1v4_pass_set : 1;
- unsigned int rx_ldo_1v2_vout_set : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_rx_ldo_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_VAL_ADDR 0x4001d41c
-
-
-/* rx_ldo_d2r_if_src_sel register */
-/*----------------------*/
-/* Rx LDO RF interace : source selection */
-/* rx_ldo_adc_enable : Source selection for rx_ldo_adc_enable */
-/* rx_ldo_1v4_enable : Source selection for rx_ldo_1v4_enable */
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_SRC_SEL_RX_LDO_ADC_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_SRC_SEL_RX_LDO_ADC_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_SRC_SEL_RX_LDO_ADC_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_SRC_SEL_RX_LDO_ADC_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_SRC_SEL_RX_LDO_ADC_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_SRC_SEL_RX_LDO_ADC_ENABLE_TMU_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_SRC_SEL_RX_LDO_1V4_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_SRC_SEL_RX_LDO_1V4_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_SRC_SEL_RX_LDO_1V4_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_SRC_SEL_RX_LDO_1V4_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_SRC_SEL_RX_LDO_1V4_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_SRC_SEL_RX_LDO_1V4_ENABLE_TMU_MASK 0x2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_ldo_adc_enable : 1;
- unsigned int rx_ldo_1v4_enable : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_rx_ldo_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_SRC_SEL_RST 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_SRC_SEL_ADDR 0x4001d420
-
-
-/* rx_ldo_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* Rx LDO RF Interface : polarity invert control */
-/* rx_ldo_adc_enable : Polarity invert control for rx_ldo_adc_enable */
-/* rx_ldo_adc_pass_set : Polarity invert control for rx_ldo_adc_pass_set */
-/* rx_ldo_control_0v8_pass : Polarity invert ocntrol for rx_ldo_control_0v8_pass */
-/* rx_ldo_control_0v8_ref_sel : Polarity invert control for rx_ldo_control_0v8_ref_sel */
-/* rx_ldo_1v4_enable : Polarity invert control for rx_ldo_1v4_enable */
-/* rx_ldo_1v4_pass_set : Polarity invert control for rx_ldo_1v4_pass_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_ADC_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_ADC_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_ADC_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_ADC_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_ADC_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_ADC_ENABLE_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_ADC_PASS_SET_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_ADC_PASS_SET_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_ADC_PASS_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_ADC_PASS_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_ADC_PASS_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_ADC_PASS_SET_EN_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_CONTROL_0V8_PASS_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_CONTROL_0V8_PASS_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_CONTROL_0V8_PASS_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_CONTROL_0V8_PASS_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_CONTROL_0V8_PASS_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_CONTROL_0V8_PASS_EN_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_CONTROL_0V8_REF_SEL_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_CONTROL_0V8_REF_SEL_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_CONTROL_0V8_REF_SEL_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_CONTROL_0V8_REF_SEL_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_CONTROL_0V8_REF_SEL_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_CONTROL_0V8_REF_SEL_EN_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_1V4_ENABLE_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_1V4_ENABLE_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_1V4_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_1V4_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_1V4_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_1V4_ENABLE_EN_MASK 0x10
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_1V4_PASS_SET_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_1V4_PASS_SET_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_1V4_PASS_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_1V4_PASS_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_1V4_PASS_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RX_LDO_1V4_PASS_SET_EN_MASK 0x20
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_ldo_adc_enable : 1;
- unsigned int rx_ldo_adc_pass_set : 1;
- unsigned int rx_ldo_control_0v8_pass : 1;
- unsigned int rx_ldo_control_0v8_ref_sel : 1;
- unsigned int rx_ldo_1v4_enable : 1;
- unsigned int rx_ldo_1v4_pass_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_rx_ldo_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_LDO_D2R_IF_POL_INVERT_EN_ADDR 0x4001d424
-
-
-/* rx_iftest_d2r_if_val register */
-/*----------------------*/
-/* Rx IFtest RF interface : regfile value */
-/* rx_iftest_enable : To be done */
-/* rx_iftest_1_set : Select signal on ACB wire 1 */
-/* rx_iftest_2_set : Select signal on ACB wire 2 */
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_IFTEST_D2R_IF_VAL_RX_IFTEST_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_IFTEST_D2R_IF_VAL_RX_IFTEST_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_IFTEST_D2R_IF_VAL_RX_IFTEST_1_SET_MASK 0x000e
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_IFTEST_D2R_IF_VAL_RX_IFTEST_1_SET_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_IFTEST_D2R_IF_VAL_RX_IFTEST_2_SET_MASK 0x0070
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_IFTEST_D2R_IF_VAL_RX_IFTEST_2_SET_POS 4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_iftest_enable : 1;
- unsigned int rx_iftest_1_set : 3;
- unsigned int rx_iftest_2_set : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_rx_iftest_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_IFTEST_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_IFTEST_D2R_IF_VAL_ADDR 0x4001d428
-
-
-/* rx_ifbuf_d2r_if_val register */
-/*----------------------*/
-/* RX IFbuf RF interface : regfile value */
-/* rx_ifbuf_rz_set : Set to 0 in case of large load capacitance (20 pF). 1 in case of small load capacitance (2 pF). */
-/* rx_ifbuf_enable : IF buffer enable */
-/* rx_ifbuf_pass_set : Set to 1 to enable bypass mode */
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_IFBUF_D2R_IF_VAL_RX_IFBUF_RZ_SET_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_IFBUF_D2R_IF_VAL_RX_IFBUF_RZ_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_IFBUF_D2R_IF_VAL_RX_IFBUF_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_IFBUF_D2R_IF_VAL_RX_IFBUF_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_IFBUF_D2R_IF_VAL_RX_IFBUF_PASS_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_IFBUF_D2R_IF_VAL_RX_IFBUF_PASS_SET_POS 2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_ifbuf_rz_set : 1;
- unsigned int rx_ifbuf_enable : 1;
- unsigned int rx_ifbuf_pass_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_rx_ifbuf_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_IFBUF_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_IFBUF_D2R_IF_VAL_ADDR 0x4001d42c
-
-
-/* pll_vco_boost_d2r_if_val register */
-/*----------------------*/
-/* PLL VCO boost interface : regfile value */
-/* pll_vco_boost_en_rx : Boost settings VCO */
-/* pll_vco_boost_en_tx : Boost settings VCO */
-/* pll_vco_boost_set : Boost VCO tail current */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_BOOST_D2R_IF_VAL_PLL_VCO_BOOST_EN_RX_MASK 0x0007
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_BOOST_D2R_IF_VAL_PLL_VCO_BOOST_EN_RX_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_BOOST_D2R_IF_VAL_PLL_VCO_BOOST_EN_TX_MASK 0x0038
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_BOOST_D2R_IF_VAL_PLL_VCO_BOOST_EN_TX_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_BOOST_D2R_IF_VAL_PLL_VCO_BOOST_SET_MASK 0x01c0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_BOOST_D2R_IF_VAL_PLL_VCO_BOOST_SET_POS 6
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_vco_boost_en_rx : 3;
- unsigned int pll_vco_boost_en_tx : 3;
- unsigned int pll_vco_boost_set : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_vco_boost_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_BOOST_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_BOOST_D2R_IF_VAL_ADDR 0x4001d430
-
-
-/* pll_vco_boost_d2r_if_src_sel register */
-/*----------------------*/
-/* PLL VCO boost interface : source selection */
-/* pll_vco_boost_set : Source selection for pll_vco_boost_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_BOOST_D2R_IF_SRC_SEL_PLL_VCO_BOOST_SET_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_BOOST_D2R_IF_SRC_SEL_PLL_VCO_BOOST_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_BOOST_D2R_IF_SRC_SEL_PLL_VCO_BOOST_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_BOOST_D2R_IF_SRC_SEL_PLL_VCO_BOOST_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_BOOST_D2R_IF_SRC_SEL_PLL_VCO_BOOST_SET_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_BOOST_D2R_IF_SRC_SEL_PLL_VCO_BOOST_SET_TMU_MASK 0x1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_vco_boost_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_vco_boost_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_BOOST_D2R_IF_SRC_SEL_RST 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_VCO_BOOST_D2R_IF_SRC_SEL_ADDR 0x4001d434
-
-
-/* pa_0_d2r_if_val register */
-/*----------------------*/
-/* PA interface : regfile value (part 0) */
-/* pa_core_enable_1v1 : TBD */
-/* pa_powerstage_enable_1v1 : TBD */
-/* pa_slices_i_1v1_set : TBD */
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_VAL_PA_CORE_ENABLE_1V1_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_VAL_PA_CORE_ENABLE_1V1_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_VAL_PA_POWERSTAGE_ENABLE_1V1_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_VAL_PA_POWERSTAGE_ENABLE_1V1_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_VAL_PA_SLICES_I_1V1_SET_MASK 0x07fc
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_VAL_PA_SLICES_I_1V1_SET_POS 2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pa_core_enable_1v1 : 1;
- unsigned int pa_powerstage_enable_1v1 : 1;
- unsigned int pa_slices_i_1v1_set : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pa_0_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_VAL_RST 0x3fc
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_VAL_ADDR 0x4001d438
-
-
-/* pa_0_d2r_if_src_sel register */
-/*----------------------*/
-/* PA interface : source selection (part0) */
-/* pa_core_enable_1v1 : Source selection for pa_core_enable_1v1 */
-/* pa_powerstage_enable_1v1 : Source selection for pa_core_enable_1v1 */
-/* pa_slices_i_1v1_set : Source selection for pa_core_enable_1v1 */
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_SRC_SEL_PA_CORE_ENABLE_1V1_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_SRC_SEL_PA_CORE_ENABLE_1V1_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_SRC_SEL_PA_CORE_ENABLE_1V1_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_SRC_SEL_PA_CORE_ENABLE_1V1_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_SRC_SEL_PA_CORE_ENABLE_1V1_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_SRC_SEL_PA_CORE_ENABLE_1V1_TMU_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_SRC_SEL_PA_POWERSTAGE_ENABLE_1V1_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_SRC_SEL_PA_POWERSTAGE_ENABLE_1V1_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_SRC_SEL_PA_POWERSTAGE_ENABLE_1V1_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_SRC_SEL_PA_POWERSTAGE_ENABLE_1V1_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_SRC_SEL_PA_POWERSTAGE_ENABLE_1V1_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_SRC_SEL_PA_POWERSTAGE_ENABLE_1V1_TMU_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_SRC_SEL_PA_SLICES_I_1V1_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_SRC_SEL_PA_SLICES_I_1V1_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_SRC_SEL_PA_SLICES_I_1V1_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_SRC_SEL_PA_SLICES_I_1V1_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_SRC_SEL_PA_SLICES_I_1V1_SET_PA_CONTROL 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_SRC_SEL_PA_SLICES_I_1V1_SET_PA_CONTROL_MASK 0x4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pa_core_enable_1v1 : 1;
- unsigned int pa_powerstage_enable_1v1 : 1;
- unsigned int pa_slices_i_1v1_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pa_0_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_SRC_SEL_RST 0x7
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_SRC_SEL_ADDR 0x4001d43c
-
-
-/* pa_0_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* PA interface : polarity invert control (part0) */
-/* pa_core_enable_1v1 : Polarity invert control for pa_core_enable_1v1 */
-/* pa_powerstage_enable_1v1 : Polarity invert control for pa_powerstage_enable_1v1 */
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_POL_INVERT_EN_PA_CORE_ENABLE_1V1_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_POL_INVERT_EN_PA_CORE_ENABLE_1V1_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_POL_INVERT_EN_PA_CORE_ENABLE_1V1_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_POL_INVERT_EN_PA_CORE_ENABLE_1V1_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_POL_INVERT_EN_PA_CORE_ENABLE_1V1_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_POL_INVERT_EN_PA_CORE_ENABLE_1V1_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_POL_INVERT_EN_PA_POWERSTAGE_ENABLE_1V1_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_POL_INVERT_EN_PA_POWERSTAGE_ENABLE_1V1_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_POL_INVERT_EN_PA_POWERSTAGE_ENABLE_1V1_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_POL_INVERT_EN_PA_POWERSTAGE_ENABLE_1V1_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_POL_INVERT_EN_PA_POWERSTAGE_ENABLE_1V1_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_POL_INVERT_EN_PA_POWERSTAGE_ENABLE_1V1_EN_MASK 0x2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pa_core_enable_1v1 : 1;
- unsigned int pa_powerstage_enable_1v1 : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pa_0_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_0_D2R_IF_POL_INVERT_EN_ADDR 0x4001d440
-
-
-/* pa_1_d2r_if_val register */
-/*----------------------*/
-/* PA interface : regfile value (part 1) */
-/* pa_nmosgate_i_1v1_set : TBD */
-/* pa_pmosgate_i_1v1_set : TBD */
-/* pa_dcc_i_1v1_set : TBD */
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_1_D2R_IF_VAL_PA_NMOSGATE_I_1V1_SET_MASK 0x0007
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_1_D2R_IF_VAL_PA_NMOSGATE_I_1V1_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_1_D2R_IF_VAL_PA_PMOSGATE_I_1V1_SET_MASK 0x0038
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_1_D2R_IF_VAL_PA_PMOSGATE_I_1V1_SET_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_1_D2R_IF_VAL_PA_DCC_I_1V1_SET_MASK 0x03c0
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_1_D2R_IF_VAL_PA_DCC_I_1V1_SET_POS 6
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pa_nmosgate_i_1v1_set : 3;
- unsigned int pa_pmosgate_i_1v1_set : 3;
- unsigned int pa_dcc_i_1v1_set : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pa_1_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_1_D2R_IF_VAL_RST 0x124
-#define EXTAPB_REGFILE_TRANSCEIVER_PA_1_D2R_IF_VAL_ADDR 0x4001d444
-
-
-/* transfo_d2r_if_val register */
-/*----------------------*/
-/* transfo interface: regfile value */
-/* transfo_cap_sec_tx_i_1v1_set : TBD */
-/* transfo_cap_prim_tune_i_1v1_set : TBD */
-/* transfo_cap_filter_tune_i_1v1_set : TBD */
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_D2R_IF_VAL_TRANSFO_CAP_SEC_TX_I_1V1_SET_MASK 0x0007
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_D2R_IF_VAL_TRANSFO_CAP_SEC_TX_I_1V1_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_D2R_IF_VAL_TRANSFO_CAP_PRIM_TUNE_I_1V1_SET_MASK 0x0038
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_D2R_IF_VAL_TRANSFO_CAP_PRIM_TUNE_I_1V1_SET_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_D2R_IF_VAL_TRANSFO_CAP_FILTER_TUNE_I_1V1_SET_MASK 0x01c0
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_D2R_IF_VAL_TRANSFO_CAP_FILTER_TUNE_I_1V1_SET_POS 6
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int transfo_cap_sec_tx_i_1v1_set : 3;
- unsigned int transfo_cap_prim_tune_i_1v1_set : 3;
- unsigned int transfo_cap_filter_tune_i_1v1_set : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_transfo_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_D2R_IF_VAL_RST 0x124
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_D2R_IF_VAL_ADDR 0x4001d448
-
-
-/* transfo_d2r_if_src_sel register */
-/*----------------------*/
-/* transfo interface : source selection */
-/* transfo_cap_sec_tx_i_1v1_set : TBD */
-/* transfo_cap_prim_tune_i_1v1_set : TBD */
-/* transfo_cap_filter_tune_i_1v1_set : TBD */
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_D2R_IF_SRC_SEL_TRANSFO_CAP_SEC_TX_I_1V1_SET_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_D2R_IF_SRC_SEL_TRANSFO_CAP_SEC_TX_I_1V1_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_D2R_IF_SRC_SEL_TRANSFO_CAP_SEC_TX_I_1V1_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_D2R_IF_SRC_SEL_TRANSFO_CAP_SEC_TX_I_1V1_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_D2R_IF_SRC_SEL_TRANSFO_CAP_SEC_TX_I_1V1_SET_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_D2R_IF_SRC_SEL_TRANSFO_CAP_SEC_TX_I_1V1_SET_TMU_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_D2R_IF_SRC_SEL_TRANSFO_CAP_PRIM_TUNE_I_1V1_SET_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_D2R_IF_SRC_SEL_TRANSFO_CAP_PRIM_TUNE_I_1V1_SET_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_D2R_IF_SRC_SEL_TRANSFO_CAP_PRIM_TUNE_I_1V1_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_D2R_IF_SRC_SEL_TRANSFO_CAP_PRIM_TUNE_I_1V1_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_D2R_IF_SRC_SEL_TRANSFO_CAP_PRIM_TUNE_I_1V1_SET_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_D2R_IF_SRC_SEL_TRANSFO_CAP_PRIM_TUNE_I_1V1_SET_TMU_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_D2R_IF_SRC_SEL_TRANSFO_CAP_FILTER_TUNE_I_1V1_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_D2R_IF_SRC_SEL_TRANSFO_CAP_FILTER_TUNE_I_1V1_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_D2R_IF_SRC_SEL_TRANSFO_CAP_FILTER_TUNE_I_1V1_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_D2R_IF_SRC_SEL_TRANSFO_CAP_FILTER_TUNE_I_1V1_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_D2R_IF_SRC_SEL_TRANSFO_CAP_FILTER_TUNE_I_1V1_SET_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_D2R_IF_SRC_SEL_TRANSFO_CAP_FILTER_TUNE_I_1V1_SET_TMU_MASK 0x4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int transfo_cap_sec_tx_i_1v1_set : 1;
- unsigned int transfo_cap_prim_tune_i_1v1_set : 1;
- unsigned int transfo_cap_filter_tune_i_1v1_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_transfo_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_D2R_IF_SRC_SEL_RST 0x7
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_D2R_IF_SRC_SEL_ADDR 0x4001d44c
-
-
-/* transfo_rx_d2r_if_val register */
-/*----------------------*/
-/* transfo interface : regfile RX value */
-/* transfo_cap_sec_tx_i_1v1_set : TBD */
-/* transfo_cap_prim_tune_i_1v1_set : TBD */
-/* transfo_cap_filter_tune_i_1v1_set : TBD */
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_RX_D2R_IF_VAL_TRANSFO_CAP_SEC_TX_I_1V1_SET_MASK 0x0007
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_RX_D2R_IF_VAL_TRANSFO_CAP_SEC_TX_I_1V1_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_RX_D2R_IF_VAL_TRANSFO_CAP_PRIM_TUNE_I_1V1_SET_MASK 0x0038
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_RX_D2R_IF_VAL_TRANSFO_CAP_PRIM_TUNE_I_1V1_SET_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_RX_D2R_IF_VAL_TRANSFO_CAP_FILTER_TUNE_I_1V1_SET_MASK 0x01c0
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_RX_D2R_IF_VAL_TRANSFO_CAP_FILTER_TUNE_I_1V1_SET_POS 6
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int transfo_cap_sec_tx_i_1v1_set : 3;
- unsigned int transfo_cap_prim_tune_i_1v1_set : 3;
- unsigned int transfo_cap_filter_tune_i_1v1_set : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_transfo_rx_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_RX_D2R_IF_VAL_RST 0x124
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_RX_D2R_IF_VAL_ADDR 0x4001d450
-
-
-/* transfo_tx_d2r_if_val register */
-/*----------------------*/
-/* transfo interface : regfile TX value */
-/* transfo_cap_sec_tx_i_1v1_set : TBD */
-/* transfo_cap_prim_tune_i_1v1_set : TBD */
-/* transfo_cap_filter_tune_i_1v1_set : TBD */
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_TX_D2R_IF_VAL_TRANSFO_CAP_SEC_TX_I_1V1_SET_MASK 0x0007
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_TX_D2R_IF_VAL_TRANSFO_CAP_SEC_TX_I_1V1_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_TX_D2R_IF_VAL_TRANSFO_CAP_PRIM_TUNE_I_1V1_SET_MASK 0x0038
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_TX_D2R_IF_VAL_TRANSFO_CAP_PRIM_TUNE_I_1V1_SET_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_TX_D2R_IF_VAL_TRANSFO_CAP_FILTER_TUNE_I_1V1_SET_MASK 0x01c0
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_TX_D2R_IF_VAL_TRANSFO_CAP_FILTER_TUNE_I_1V1_SET_POS 6
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int transfo_cap_sec_tx_i_1v1_set : 3;
- unsigned int transfo_cap_prim_tune_i_1v1_set : 3;
- unsigned int transfo_cap_filter_tune_i_1v1_set : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_transfo_tx_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_TX_D2R_IF_VAL_RST 0x124
-#define EXTAPB_REGFILE_TRANSCEIVER_TRANSFO_TX_D2R_IF_VAL_ADDR 0x4001d454
-
-
-/* lo_d2r_if_val register */
-/*----------------------*/
-/* LO interface: regfile value */
-/* rx_enable_1v1 : TBD */
-/* tx_enable_1v1 : TBD */
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_VAL_RX_ENABLE_1V1_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_VAL_RX_ENABLE_1V1_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_VAL_TX_ENABLE_1V1_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_VAL_TX_ENABLE_1V1_POS 1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_enable_1v1 : 1;
- unsigned int tx_enable_1v1 : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_lo_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_VAL_ADDR 0x4001d458
-
-
-/* lo_d2r_if_src_sel register */
-/*----------------------*/
-/* LO interface: source selection */
-/* rx_enable_1v1 : Source selection for rx_enable_1v1 */
-/* tx_enable_1v1 : Source selection for tx_enable_1v1 */
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_SRC_SEL_RX_ENABLE_1V1_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_SRC_SEL_RX_ENABLE_1V1_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_SRC_SEL_RX_ENABLE_1V1_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_SRC_SEL_RX_ENABLE_1V1_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_SRC_SEL_RX_ENABLE_1V1_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_SRC_SEL_RX_ENABLE_1V1_TMU_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_SRC_SEL_TX_ENABLE_1V1_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_SRC_SEL_TX_ENABLE_1V1_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_SRC_SEL_TX_ENABLE_1V1_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_SRC_SEL_TX_ENABLE_1V1_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_SRC_SEL_TX_ENABLE_1V1_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_SRC_SEL_TX_ENABLE_1V1_TMU_MASK 0x2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_enable_1v1 : 1;
- unsigned int tx_enable_1v1 : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_lo_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_SRC_SEL_RST 0x3
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_SRC_SEL_ADDR 0x4001d45c
-
-
-/* lo_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* LO interface: polarity invert control */
-/* rx_enable_1v1 : Polarity invert control for rx_enable_1v1 */
-/* tx_enable_1v1 : Polarity invert control for tx_enable_1v1 */
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_POL_INVERT_EN_RX_ENABLE_1V1_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_POL_INVERT_EN_RX_ENABLE_1V1_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_POL_INVERT_EN_RX_ENABLE_1V1_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_POL_INVERT_EN_RX_ENABLE_1V1_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_POL_INVERT_EN_RX_ENABLE_1V1_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_POL_INVERT_EN_RX_ENABLE_1V1_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_POL_INVERT_EN_TX_ENABLE_1V1_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_POL_INVERT_EN_TX_ENABLE_1V1_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_POL_INVERT_EN_TX_ENABLE_1V1_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_POL_INVERT_EN_TX_ENABLE_1V1_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_POL_INVERT_EN_TX_ENABLE_1V1_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_POL_INVERT_EN_TX_ENABLE_1V1_EN_MASK 0x2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_enable_1v1 : 1;
- unsigned int tx_enable_1v1 : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_lo_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LO_D2R_IF_POL_INVERT_EN_ADDR 0x4001d460
-
-
-/* ldo_pa_d2r_if_val register */
-/*----------------------*/
-/* LDO_PA interface: regfile value */
-/* powerstage_enable_1v8 : Enable the Powerstage PA LDO output */
-/* powerstage_vadj_i_1v8_set : Output Voltage adjustment for powerstage voltage */
-/* powerstage_bypass_i_1v8_set : Activate LDO powerstage bypass */
-/* powerstage_highz_i_1v8_set : Put the output in high impedance state */
-/* powerstage_ibias_i_1v8_set : Adjust the biasing current */
-/* powerstage_enable_1v8_rx : Enable the Powerstage PA LDO output (RX mode value) */
-/* powerstage_enable_1v8_tx : Enable the Powerstage PA LDO output (TX mode value) */
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_VAL_POWERSTAGE_ENABLE_1V8_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_VAL_POWERSTAGE_ENABLE_1V8_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_VAL_POWERSTAGE_VADJ_I_1V8_SET_MASK 0x003e
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_VAL_POWERSTAGE_VADJ_I_1V8_SET_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_VAL_POWERSTAGE_BYPASS_I_1V8_SET_MASK 0x0040
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_VAL_POWERSTAGE_BYPASS_I_1V8_SET_POS 6
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_VAL_POWERSTAGE_HIGHZ_I_1V8_SET_MASK 0x0080
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_VAL_POWERSTAGE_HIGHZ_I_1V8_SET_POS 7
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_VAL_POWERSTAGE_IBIAS_I_1V8_SET_MASK 0x0300
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_VAL_POWERSTAGE_IBIAS_I_1V8_SET_POS 8
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_VAL_POWERSTAGE_ENABLE_1V8_RX_MASK 0x0400
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_VAL_POWERSTAGE_ENABLE_1V8_RX_POS 10
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_VAL_POWERSTAGE_ENABLE_1V8_TX_MASK 0x0800
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_VAL_POWERSTAGE_ENABLE_1V8_TX_POS 11
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int powerstage_enable_1v8 : 1;
- unsigned int powerstage_vadj_i_1v8_set : 5;
- unsigned int powerstage_bypass_i_1v8_set : 1;
- unsigned int powerstage_highz_i_1v8_set : 1;
- unsigned int powerstage_ibias_i_1v8_set : 2;
- unsigned int powerstage_enable_1v8_rx : 1;
- unsigned int powerstage_enable_1v8_tx : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_ldo_pa_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_VAL_RST 0x16
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_VAL_ADDR 0x4001d464
-
-
-/* ldo_pa_d2r_if_src_sel register */
-/*----------------------*/
-/* LDO_PA interface: source selection */
-/* powerstage_enable_1v8 : Source selection for powerstage_enable_1v8 */
-/* powerstage_enable_1v8_rx : Source selection for powerstage_enable_1v8_rx */
-/* powerstage_enable_1v8_tx : Source selection for powerstage_enable_1v8_tx */
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_SRC_SEL_POWERSTAGE_ENABLE_1V8_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_SRC_SEL_POWERSTAGE_ENABLE_1V8_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_SRC_SEL_POWERSTAGE_ENABLE_1V8_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_SRC_SEL_POWERSTAGE_ENABLE_1V8_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_SRC_SEL_POWERSTAGE_ENABLE_1V8_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_SRC_SEL_POWERSTAGE_ENABLE_1V8_TMU_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_SRC_SEL_POWERSTAGE_ENABLE_1V8_RX_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_SRC_SEL_POWERSTAGE_ENABLE_1V8_RX_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_SRC_SEL_POWERSTAGE_ENABLE_1V8_RX_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_SRC_SEL_POWERSTAGE_ENABLE_1V8_RX_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_SRC_SEL_POWERSTAGE_ENABLE_1V8_RX_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_SRC_SEL_POWERSTAGE_ENABLE_1V8_RX_TMU_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_SRC_SEL_POWERSTAGE_ENABLE_1V8_TX_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_SRC_SEL_POWERSTAGE_ENABLE_1V8_TX_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_SRC_SEL_POWERSTAGE_ENABLE_1V8_TX_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_SRC_SEL_POWERSTAGE_ENABLE_1V8_TX_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_SRC_SEL_POWERSTAGE_ENABLE_1V8_TX_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_SRC_SEL_POWERSTAGE_ENABLE_1V8_TX_TMU_MASK 0x4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int powerstage_enable_1v8 : 1;
- unsigned int powerstage_enable_1v8_rx : 1;
- unsigned int powerstage_enable_1v8_tx : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_ldo_pa_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_SRC_SEL_RST 0x5
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_SRC_SEL_ADDR 0x4001d468
-
-
-/* ldo_pa_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* LDO_PA interface: polarity invert control */
-/* powerstage_enable_1v8 : Polarity invert control for powerstage_enable_1v8 */
-/* powerstage_bypass_i_1v8_set : Polarity invert control for powerstage_bypass_i_1v8_pass */
-/* powerstage_highz_i_1v8_set : Polarity invert control for powerstage_highz_i_1v8_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_POL_INVERT_EN_POWERSTAGE_ENABLE_1V8_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_POL_INVERT_EN_POWERSTAGE_ENABLE_1V8_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_POL_INVERT_EN_POWERSTAGE_ENABLE_1V8_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_POL_INVERT_EN_POWERSTAGE_ENABLE_1V8_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_POL_INVERT_EN_POWERSTAGE_ENABLE_1V8_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_POL_INVERT_EN_POWERSTAGE_ENABLE_1V8_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_POL_INVERT_EN_POWERSTAGE_BYPASS_I_1V8_SET_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_POL_INVERT_EN_POWERSTAGE_BYPASS_I_1V8_SET_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_POL_INVERT_EN_POWERSTAGE_BYPASS_I_1V8_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_POL_INVERT_EN_POWERSTAGE_BYPASS_I_1V8_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_POL_INVERT_EN_POWERSTAGE_BYPASS_I_1V8_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_POL_INVERT_EN_POWERSTAGE_BYPASS_I_1V8_SET_EN_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_POL_INVERT_EN_POWERSTAGE_HIGHZ_I_1V8_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_POL_INVERT_EN_POWERSTAGE_HIGHZ_I_1V8_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_POL_INVERT_EN_POWERSTAGE_HIGHZ_I_1V8_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_POL_INVERT_EN_POWERSTAGE_HIGHZ_I_1V8_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_POL_INVERT_EN_POWERSTAGE_HIGHZ_I_1V8_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_POL_INVERT_EN_POWERSTAGE_HIGHZ_I_1V8_SET_EN_MASK 0x4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int powerstage_enable_1v8 : 1;
- unsigned int powerstage_bypass_i_1v8_set : 1;
- unsigned int powerstage_highz_i_1v8_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_ldo_pa_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_PA_D2R_IF_POL_INVERT_EN_ADDR 0x4001d46c
-
-
-/* ldo_if_d2r_if_val register */
-/*----------------------*/
-/* LDO_IF interface: regfile value */
-/* bypass_i_1v8_set : TBD */
-/* enable_1v8 : TBD */
-/* highz_i_1v8_set : TBD */
-/* vout_i_1v8_set : TBD */
-/* ibias_i_1v8_set : TBD */
-/* stabmode_i_1v8_set : TBD */
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_VAL_BYPASS_I_1V8_SET_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_VAL_BYPASS_I_1V8_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_VAL_ENABLE_1V8_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_VAL_ENABLE_1V8_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_VAL_HIGHZ_I_1V8_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_VAL_HIGHZ_I_1V8_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_VAL_VOUT_I_1V8_SET_MASK 0x0038
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_VAL_VOUT_I_1V8_SET_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_VAL_IBIAS_I_1V8_SET_MASK 0x00c0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_VAL_IBIAS_I_1V8_SET_POS 6
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_VAL_STABMODE_I_1V8_SET_MASK 0x0300
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_VAL_STABMODE_I_1V8_SET_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int bypass_i_1v8_set : 1;
- unsigned int enable_1v8 : 1;
- unsigned int highz_i_1v8_set : 1;
- unsigned int vout_i_1v8_set : 3;
- unsigned int ibias_i_1v8_set : 2;
- unsigned int stabmode_i_1v8_set : 2;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_ldo_if_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_VAL_RST 0x168
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_VAL_ADDR 0x4001d470
-
-
-/* ldo_if_d2r_if_src_sel register */
-/*----------------------*/
-/* LDO_IF interface: source selection */
-/* enable_1v8 : Source selection for enable_1v8 */
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_SRC_SEL_ENABLE_1V8_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_SRC_SEL_ENABLE_1V8_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_SRC_SEL_ENABLE_1V8_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_SRC_SEL_ENABLE_1V8_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_SRC_SEL_ENABLE_1V8_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_SRC_SEL_ENABLE_1V8_TMU_MASK 0x1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int enable_1v8 : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_ldo_if_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_SRC_SEL_RST 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_SRC_SEL_ADDR 0x4001d474
-
-
-/* ldo_if_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* LDO_IF interface: polarity invert control */
-/* bypass_i_1v8_set : Polarity invert control for bypass_i_1v8_set */
-/* enable_1v8 : Polarity invert control for enable_1v8 */
-/* highz_i_1v8_set : Polarity invert control for highz_i_1v8_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_POL_INVERT_EN_BYPASS_I_1V8_SET_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_POL_INVERT_EN_BYPASS_I_1V8_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_POL_INVERT_EN_BYPASS_I_1V8_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_POL_INVERT_EN_BYPASS_I_1V8_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_POL_INVERT_EN_BYPASS_I_1V8_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_POL_INVERT_EN_BYPASS_I_1V8_SET_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_POL_INVERT_EN_ENABLE_1V8_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_POL_INVERT_EN_ENABLE_1V8_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_POL_INVERT_EN_ENABLE_1V8_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_POL_INVERT_EN_ENABLE_1V8_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_POL_INVERT_EN_ENABLE_1V8_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_POL_INVERT_EN_ENABLE_1V8_EN_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_POL_INVERT_EN_HIGHZ_I_1V8_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_POL_INVERT_EN_HIGHZ_I_1V8_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_POL_INVERT_EN_HIGHZ_I_1V8_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_POL_INVERT_EN_HIGHZ_I_1V8_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_POL_INVERT_EN_HIGHZ_I_1V8_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_POL_INVERT_EN_HIGHZ_I_1V8_SET_EN_MASK 0x4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int bypass_i_1v8_set : 1;
- unsigned int enable_1v8 : 1;
- unsigned int highz_i_1v8_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_ldo_if_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_IF_D2R_IF_POL_INVERT_EN_ADDR 0x4001d478
-
-
-/* ldo_synth_d2r_if_val register */
-/*----------------------*/
-/* LDO_synth interface: regfile value */
-/* bypass_i_1v8_set : TBD */
-/* enable_1v8 : TBD */
-/* highz_i_1v8_set : TBD */
-/* vout_i_1v8_set : TBD */
-/* ibias_i_1v8_set : TBD */
-/* stabmode_i_1v8_set : TBD */
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_VAL_BYPASS_I_1V8_SET_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_VAL_BYPASS_I_1V8_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_VAL_ENABLE_1V8_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_VAL_ENABLE_1V8_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_VAL_HIGHZ_I_1V8_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_VAL_HIGHZ_I_1V8_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_VAL_VOUT_I_1V8_SET_MASK 0x0038
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_VAL_VOUT_I_1V8_SET_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_VAL_IBIAS_I_1V8_SET_MASK 0x00c0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_VAL_IBIAS_I_1V8_SET_POS 6
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_VAL_STABMODE_I_1V8_SET_MASK 0x0300
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_VAL_STABMODE_I_1V8_SET_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int bypass_i_1v8_set : 1;
- unsigned int enable_1v8 : 1;
- unsigned int highz_i_1v8_set : 1;
- unsigned int vout_i_1v8_set : 3;
- unsigned int ibias_i_1v8_set : 2;
- unsigned int stabmode_i_1v8_set : 2;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_ldo_synth_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_VAL_RST 0x168
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_VAL_ADDR 0x4001d47c
-
-
-/* ldo_synth_d2r_if_src_sel register */
-/*----------------------*/
-/* LDO_synth interface: source selection */
-/* enable_1v8 : Source selection for enable_1v8 */
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_SRC_SEL_ENABLE_1V8_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_SRC_SEL_ENABLE_1V8_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_SRC_SEL_ENABLE_1V8_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_SRC_SEL_ENABLE_1V8_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_SRC_SEL_ENABLE_1V8_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_SRC_SEL_ENABLE_1V8_TMU_MASK 0x1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int enable_1v8 : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_ldo_synth_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_SRC_SEL_RST 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_SRC_SEL_ADDR 0x4001d480
-
-
-/* ldo_synth_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* LDO_synth interface: polarity invert control */
-/* bypass_i_1v8_set : Polarity invert control for bypass_i_1v8_set */
-/* enable_1v8 : Polarity invert control for enable_1v8 */
-/* highz_i_1v8_set : Polarity invert control for highz_i_1v8_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_POL_INVERT_EN_BYPASS_I_1V8_SET_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_POL_INVERT_EN_BYPASS_I_1V8_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_POL_INVERT_EN_BYPASS_I_1V8_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_POL_INVERT_EN_BYPASS_I_1V8_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_POL_INVERT_EN_BYPASS_I_1V8_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_POL_INVERT_EN_BYPASS_I_1V8_SET_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_POL_INVERT_EN_ENABLE_1V8_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_POL_INVERT_EN_ENABLE_1V8_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_POL_INVERT_EN_ENABLE_1V8_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_POL_INVERT_EN_ENABLE_1V8_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_POL_INVERT_EN_ENABLE_1V8_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_POL_INVERT_EN_ENABLE_1V8_EN_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_POL_INVERT_EN_HIGHZ_I_1V8_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_POL_INVERT_EN_HIGHZ_I_1V8_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_POL_INVERT_EN_HIGHZ_I_1V8_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_POL_INVERT_EN_HIGHZ_I_1V8_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_POL_INVERT_EN_HIGHZ_I_1V8_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_POL_INVERT_EN_HIGHZ_I_1V8_SET_EN_MASK 0x4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int bypass_i_1v8_set : 1;
- unsigned int enable_1v8 : 1;
- unsigned int highz_i_1v8_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_ldo_synth_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_SYNTH_D2R_IF_POL_INVERT_EN_ADDR 0x4001d484
-
-
-/* ldo_vco_d2r_if_val register */
-/*----------------------*/
-/* LDO_PLL interface: regfile value */
-/* bypass_i_1v8_set : TBD */
-/* enable_1v8 : TBD */
-/* highz_i_1v8_set : TBD */
-/* vout_i_1v8_set : TBD */
-/* ibias_i_1v8_set : TBD */
-/* stabmode_i_1v8_set : TBD */
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_VAL_BYPASS_I_1V8_SET_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_VAL_BYPASS_I_1V8_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_VAL_ENABLE_1V8_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_VAL_ENABLE_1V8_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_VAL_HIGHZ_I_1V8_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_VAL_HIGHZ_I_1V8_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_VAL_VOUT_I_1V8_SET_MASK 0x0038
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_VAL_VOUT_I_1V8_SET_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_VAL_IBIAS_I_1V8_SET_MASK 0x00c0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_VAL_IBIAS_I_1V8_SET_POS 6
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_VAL_STABMODE_I_1V8_SET_MASK 0x0300
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_VAL_STABMODE_I_1V8_SET_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int bypass_i_1v8_set : 1;
- unsigned int enable_1v8 : 1;
- unsigned int highz_i_1v8_set : 1;
- unsigned int vout_i_1v8_set : 3;
- unsigned int ibias_i_1v8_set : 2;
- unsigned int stabmode_i_1v8_set : 2;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_ldo_vco_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_VAL_RST 0x168
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_VAL_ADDR 0x4001d488
-
-
-/* ldo_vco_d2r_if_src_sel register */
-/*----------------------*/
-/* LDO_PLL interface: source selection */
-/* enable_1v8 : Source selection for enable_1v8 */
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_SRC_SEL_ENABLE_1V8_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_SRC_SEL_ENABLE_1V8_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_SRC_SEL_ENABLE_1V8_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_SRC_SEL_ENABLE_1V8_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_SRC_SEL_ENABLE_1V8_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_SRC_SEL_ENABLE_1V8_TMU_MASK 0x1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int enable_1v8 : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_ldo_vco_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_SRC_SEL_RST 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_SRC_SEL_ADDR 0x4001d48c
-
-
-/* ldo_vco_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* LDO_PLL interface: polarity invert control */
-/* bypass_i_1v8_set : Polarity invert control for bypass_i_1v8_set */
-/* enable_1v8 : Polarity invert control for enable_1v8 */
-/* highz_i_1v8_set : Polarity invert control for highz_i_1v8_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_POL_INVERT_EN_BYPASS_I_1V8_SET_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_POL_INVERT_EN_BYPASS_I_1V8_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_POL_INVERT_EN_BYPASS_I_1V8_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_POL_INVERT_EN_BYPASS_I_1V8_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_POL_INVERT_EN_BYPASS_I_1V8_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_POL_INVERT_EN_BYPASS_I_1V8_SET_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_POL_INVERT_EN_ENABLE_1V8_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_POL_INVERT_EN_ENABLE_1V8_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_POL_INVERT_EN_ENABLE_1V8_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_POL_INVERT_EN_ENABLE_1V8_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_POL_INVERT_EN_ENABLE_1V8_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_POL_INVERT_EN_ENABLE_1V8_EN_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_POL_INVERT_EN_HIGHZ_I_1V8_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_POL_INVERT_EN_HIGHZ_I_1V8_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_POL_INVERT_EN_HIGHZ_I_1V8_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_POL_INVERT_EN_HIGHZ_I_1V8_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_POL_INVERT_EN_HIGHZ_I_1V8_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_POL_INVERT_EN_HIGHZ_I_1V8_SET_EN_MASK 0x4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int bypass_i_1v8_set : 1;
- unsigned int enable_1v8 : 1;
- unsigned int highz_i_1v8_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_ldo_vco_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_VCO_D2R_IF_POL_INVERT_EN_ADDR 0x4001d490
-
-
-/* tone_pll_d2r_if_val register */
-/*----------------------*/
-/* Tone PLL interface: regfile value */
-/* tone_pll_bypass_set : TBD */
-/* tone_pll_ldo_enable : TBD */
-/* tone_pll_ldo_fbres_set : TBD */
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_VAL_TONE_PLL_BYPASS_SET_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_VAL_TONE_PLL_BYPASS_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_VAL_TONE_PLL_LDO_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_VAL_TONE_PLL_LDO_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_VAL_TONE_PLL_LDO_FBRES_SET_MASK 0x007c
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_VAL_TONE_PLL_LDO_FBRES_SET_POS 2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int tone_pll_bypass_set : 1;
- unsigned int tone_pll_ldo_enable : 1;
- unsigned int tone_pll_ldo_fbres_set : 5;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_tone_pll_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_VAL_ADDR 0x4001d494
-
-
-/* tone_pll_d2r_if_src_sel register */
-/*----------------------*/
-/* Tone PLL interface : source selection */
-/* tone_pll_ldo_enable : Source selection for tone_pll_ldo_enable */
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_SRC_SEL_TONE_PLL_LDO_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_SRC_SEL_TONE_PLL_LDO_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_SRC_SEL_TONE_PLL_LDO_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_SRC_SEL_TONE_PLL_LDO_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_SRC_SEL_TONE_PLL_LDO_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_SRC_SEL_TONE_PLL_LDO_ENABLE_TMU_MASK 0x1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int tone_pll_ldo_enable : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_tone_pll_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_SRC_SEL_RST 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_SRC_SEL_ADDR 0x4001d498
-
-
-/* tone_pll_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* Tone PLL interface: polarity invert control */
-/* tone_pll_bypass_set : Polarity invert control for tone_pll_bypass_set */
-/* tone_pll_ldo_enable : Polarity invert control for tone_pll_ldo_enable */
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_POL_INVERT_EN_TONE_PLL_BYPASS_SET_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_POL_INVERT_EN_TONE_PLL_BYPASS_SET_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_POL_INVERT_EN_TONE_PLL_BYPASS_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_POL_INVERT_EN_TONE_PLL_BYPASS_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_POL_INVERT_EN_TONE_PLL_BYPASS_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_POL_INVERT_EN_TONE_PLL_BYPASS_SET_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_POL_INVERT_EN_TONE_PLL_LDO_ENABLE_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_POL_INVERT_EN_TONE_PLL_LDO_ENABLE_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_POL_INVERT_EN_TONE_PLL_LDO_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_POL_INVERT_EN_TONE_PLL_LDO_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_POL_INVERT_EN_TONE_PLL_LDO_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_POL_INVERT_EN_TONE_PLL_LDO_ENABLE_EN_MASK 0x2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int tone_pll_bypass_set : 1;
- unsigned int tone_pll_ldo_enable : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_tone_pll_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TONE_PLL_D2R_IF_POL_INVERT_EN_ADDR 0x4001d49c
-
-
-/* radio_id_r2d_if_val register */
-/*----------------------*/
-/* Radio ID interface: regfile value */
-/* radio_id : Radio version ID */
-#define EXTAPB_REGFILE_TRANSCEIVER_RADIO_ID_R2D_IF_VAL_RADIO_ID_MASK 0x003f
-#define EXTAPB_REGFILE_TRANSCEIVER_RADIO_ID_R2D_IF_VAL_RADIO_ID_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int radio_id : 6;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_radio_id_r2d_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_RADIO_ID_R2D_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RADIO_ID_R2D_IF_VAL_DYNAMIC true
-#define EXTAPB_REGFILE_TRANSCEIVER_RADIO_ID_R2D_IF_VAL_SNAPCLOCK 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RADIO_ID_R2D_IF_VAL_ADDR 0x4001d4a0
-
-
-/* pll_cur_mir_d2r_if_val register */
-/*----------------------*/
-/* PLL current mirror interface: regfile value */
-/* pll_cur_mir_enable : Enable signal for current mirror */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CUR_MIR_D2R_IF_VAL_PLL_CUR_MIR_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CUR_MIR_D2R_IF_VAL_PLL_CUR_MIR_ENABLE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_cur_mir_enable : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_cur_mir_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CUR_MIR_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CUR_MIR_D2R_IF_VAL_ADDR 0x4001d4a4
-
-
-/* pll_cur_mir_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* PLL current mirror interface: polarity invert control */
-/* pll_cur_mir_enable : Polarity invert control for pll_cur_mir_enable */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CUR_MIR_D2R_IF_POL_INVERT_EN_PLL_CUR_MIR_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CUR_MIR_D2R_IF_POL_INVERT_EN_PLL_CUR_MIR_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CUR_MIR_D2R_IF_POL_INVERT_EN_PLL_CUR_MIR_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CUR_MIR_D2R_IF_POL_INVERT_EN_PLL_CUR_MIR_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CUR_MIR_D2R_IF_POL_INVERT_EN_PLL_CUR_MIR_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CUR_MIR_D2R_IF_POL_INVERT_EN_PLL_CUR_MIR_ENABLE_EN_MASK 0x1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_cur_mir_enable : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_cur_mir_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CUR_MIR_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_CUR_MIR_D2R_IF_POL_INVERT_EN_ADDR 0x4001d4a8
-
-
-/* pll_divlo_d2r_if_val register */
-/*----------------------*/
-/* LO Divider interface: regfile value */
-/* pll_divlo_divn_enable : Enable LO divider core */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVLO_D2R_IF_VAL_PLL_DIVLO_DIVN_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVLO_D2R_IF_VAL_PLL_DIVLO_DIVN_ENABLE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_divlo_divn_enable : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_divlo_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVLO_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVLO_D2R_IF_VAL_ADDR 0x4001d4ac
-
-
-/* pll_divlo_d2r_if_src_sel register */
-/*----------------------*/
-/* LO Divider interface : source selection */
-/* pll_divlo_divn_enable : Source selection for pll_divlo_divn_enable */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVLO_D2R_IF_SRC_SEL_PLL_DIVLO_DIVN_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVLO_D2R_IF_SRC_SEL_PLL_DIVLO_DIVN_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVLO_D2R_IF_SRC_SEL_PLL_DIVLO_DIVN_ENABLE_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVLO_D2R_IF_SRC_SEL_PLL_DIVLO_DIVN_ENABLE_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVLO_D2R_IF_SRC_SEL_PLL_DIVLO_DIVN_ENABLE_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVLO_D2R_IF_SRC_SEL_PLL_DIVLO_DIVN_ENABLE_TMU_MASK 0x1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_divlo_divn_enable : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_divlo_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVLO_D2R_IF_SRC_SEL_RST 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVLO_D2R_IF_SRC_SEL_ADDR 0x4001d4b0
-
-
-/* pll_divlo_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* LO Divider interface: polarity invert control */
-/* pll_divlo_divn_enable : Polarity invert control for pll_divlo_divn_enable */
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVLO_D2R_IF_POL_INVERT_EN_PLL_DIVLO_DIVN_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVLO_D2R_IF_POL_INVERT_EN_PLL_DIVLO_DIVN_ENABLE_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVLO_D2R_IF_POL_INVERT_EN_PLL_DIVLO_DIVN_ENABLE_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVLO_D2R_IF_POL_INVERT_EN_PLL_DIVLO_DIVN_ENABLE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVLO_D2R_IF_POL_INVERT_EN_PLL_DIVLO_DIVN_ENABLE_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVLO_D2R_IF_POL_INVERT_EN_PLL_DIVLO_DIVN_ENABLE_EN_MASK 0x1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_divlo_divn_enable : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_pll_divlo_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVLO_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_PLL_DIVLO_D2R_IF_POL_INVERT_EN_ADDR 0x4001d4b4
-
-
-/* ldo_rf_d2r_if_val register */
-/*----------------------*/
-/* LDO RF interface : regfile value */
-/* core_enable_1v8 : Enable the Core PA LDO output */
-/* core_vadj_i_1v8_set : Output Voltage adjustment for core voltage */
-/* core_bypass_i_1v8_set : Activate LDO core bypass */
-/* core_highz_i_1v8_set : Put the output in high impedance state */
-/* core_ibias_i_1v8_set : Adjust the biasing current */
-/* core_vadj_i_1v8_set_rx : Rx output voltage adjustment for core voltage */
-/* core_vadj_i_1v8_set_tx : TX output voltage adjustment for core voltage */
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_VAL_CORE_ENABLE_1V8_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_VAL_CORE_ENABLE_1V8_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_VAL_CORE_VADJ_I_1V8_SET_MASK 0x000e
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_VAL_CORE_VADJ_I_1V8_SET_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_VAL_CORE_BYPASS_I_1V8_SET_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_VAL_CORE_BYPASS_I_1V8_SET_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_VAL_CORE_HIGHZ_I_1V8_SET_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_VAL_CORE_HIGHZ_I_1V8_SET_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_VAL_CORE_IBIAS_I_1V8_SET_MASK 0x00c0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_VAL_CORE_IBIAS_I_1V8_SET_POS 6
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_VAL_CORE_VADJ_I_1V8_SET_RX_MASK 0x0700
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_VAL_CORE_VADJ_I_1V8_SET_RX_POS 8
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_VAL_CORE_VADJ_I_1V8_SET_TX_MASK 0x3800
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_VAL_CORE_VADJ_I_1V8_SET_TX_POS 11
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int core_enable_1v8 : 1;
- unsigned int core_vadj_i_1v8_set : 3;
- unsigned int core_bypass_i_1v8_set : 1;
- unsigned int core_highz_i_1v8_set : 1;
- unsigned int core_ibias_i_1v8_set : 2;
- unsigned int core_vadj_i_1v8_set_rx : 3;
- unsigned int core_vadj_i_1v8_set_tx : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_ldo_rf_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_VAL_ADDR 0x4001d4b8
-
-
-/* ldo_rf_d2r_if_src_sel register */
-/*----------------------*/
-/* LDO RF interface : source selection */
-/* core_enable_1v8 : Source selection for core_enable_1v8 */
-/* core_vadj_i_1v8_set : Source selection for core_vadj_i_1v8_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_SRC_SEL_CORE_ENABLE_1V8_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_SRC_SEL_CORE_ENABLE_1V8_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_SRC_SEL_CORE_ENABLE_1V8_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_SRC_SEL_CORE_ENABLE_1V8_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_SRC_SEL_CORE_ENABLE_1V8_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_SRC_SEL_CORE_ENABLE_1V8_TMU_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_SRC_SEL_CORE_VADJ_I_1V8_SET_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_SRC_SEL_CORE_VADJ_I_1V8_SET_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_SRC_SEL_CORE_VADJ_I_1V8_SET_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_SRC_SEL_CORE_VADJ_I_1V8_SET_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_SRC_SEL_CORE_VADJ_I_1V8_SET_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_SRC_SEL_CORE_VADJ_I_1V8_SET_TMU_MASK 0x2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int core_enable_1v8 : 1;
- unsigned int core_vadj_i_1v8_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_ldo_rf_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_SRC_SEL_RST 0x3
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_SRC_SEL_ADDR 0x4001d4bc
-
-
-/* ldo_rf_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* LDO RF interface : polarity invert control */
-/* core_enable_1v8 : Polarity invert control for core_enable_1v8 */
-/* core_bypass_i_1v8_set : Polarity invert control for core_bypass_i_1v8_set */
-/* core_highz_i_1v8_set : Polarity invert control for core_highz_i_1v8_set */
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_POL_INVERT_EN_CORE_ENABLE_1V8_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_POL_INVERT_EN_CORE_ENABLE_1V8_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_POL_INVERT_EN_CORE_ENABLE_1V8_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_POL_INVERT_EN_CORE_ENABLE_1V8_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_POL_INVERT_EN_CORE_ENABLE_1V8_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_POL_INVERT_EN_CORE_ENABLE_1V8_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_POL_INVERT_EN_CORE_BYPASS_I_1V8_SET_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_POL_INVERT_EN_CORE_BYPASS_I_1V8_SET_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_POL_INVERT_EN_CORE_BYPASS_I_1V8_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_POL_INVERT_EN_CORE_BYPASS_I_1V8_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_POL_INVERT_EN_CORE_BYPASS_I_1V8_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_POL_INVERT_EN_CORE_BYPASS_I_1V8_SET_EN_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_POL_INVERT_EN_CORE_HIGHZ_I_1V8_SET_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_POL_INVERT_EN_CORE_HIGHZ_I_1V8_SET_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_POL_INVERT_EN_CORE_HIGHZ_I_1V8_SET_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_POL_INVERT_EN_CORE_HIGHZ_I_1V8_SET_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_POL_INVERT_EN_CORE_HIGHZ_I_1V8_SET_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_POL_INVERT_EN_CORE_HIGHZ_I_1V8_SET_EN_MASK 0x4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int core_enable_1v8 : 1;
- unsigned int core_bypass_i_1v8_set : 1;
- unsigned int core_highz_i_1v8_set : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_ldo_rf_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_LDO_RF_D2R_IF_POL_INVERT_EN_ADDR 0x4001d4c0
-
-
-/* global_spare_d2r_if_val register */
-/*----------------------*/
-/* Global group sequence spare : regfile value */
-/* g1_spare_0 : G1 group sequence spare */
-/* g1_spare_1 : G1 group sequence spare */
-/* g2_spare_0 : G2 group sequence spare */
-/* g2_spare_1 : G2 group sequence spare */
-/* pll_spare_0 : PLL group sequence spare */
-/* pll_spare_1 : PLL group sequence spare */
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_VAL_G1_SPARE_0_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_VAL_G1_SPARE_0_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_VAL_G1_SPARE_1_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_VAL_G1_SPARE_1_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_VAL_G2_SPARE_0_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_VAL_G2_SPARE_0_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_VAL_G2_SPARE_1_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_VAL_G2_SPARE_1_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_VAL_PLL_SPARE_0_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_VAL_PLL_SPARE_0_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_VAL_PLL_SPARE_1_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_VAL_PLL_SPARE_1_POS 5
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int g1_spare_0 : 1;
- unsigned int g1_spare_1 : 1;
- unsigned int g2_spare_0 : 1;
- unsigned int g2_spare_1 : 1;
- unsigned int pll_spare_0 : 1;
- unsigned int pll_spare_1 : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_global_spare_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_VAL_ADDR 0x4001d4c4
-
-
-/* global_spare_d2r_if_src_sel register */
-/*----------------------*/
-/* Global group sequence spare : source selection */
-/* g1_spare_0 : Source selection for g1_spare_0 */
-/* g1_spare_1 : Source selection for g1_spare_1 */
-/* g2_spare_0 : Source selection for g2_spare_0 */
-/* g2_spare_1 : Source selection for g2_spare_1 */
-/* pll_spare_0 : Source selection for pll_spare_0 */
-/* pll_spare_1 : Source selection for pll_spare_1 */
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_G1_SPARE_0_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_G1_SPARE_0_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_G1_SPARE_0_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_G1_SPARE_0_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_G1_SPARE_0_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_G1_SPARE_0_TMU_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_G1_SPARE_1_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_G1_SPARE_1_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_G1_SPARE_1_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_G1_SPARE_1_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_G1_SPARE_1_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_G1_SPARE_1_TMU_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_G2_SPARE_0_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_G2_SPARE_0_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_G2_SPARE_0_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_G2_SPARE_0_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_G2_SPARE_0_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_G2_SPARE_0_TMU_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_G2_SPARE_1_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_G2_SPARE_1_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_G2_SPARE_1_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_G2_SPARE_1_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_G2_SPARE_1_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_G2_SPARE_1_TMU_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_PLL_SPARE_0_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_PLL_SPARE_0_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_PLL_SPARE_0_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_PLL_SPARE_0_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_PLL_SPARE_0_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_PLL_SPARE_0_TMU_MASK 0x10
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_PLL_SPARE_1_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_PLL_SPARE_1_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_PLL_SPARE_1_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_PLL_SPARE_1_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_PLL_SPARE_1_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_PLL_SPARE_1_TMU_MASK 0x20
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int g1_spare_0 : 1;
- unsigned int g1_spare_1 : 1;
- unsigned int g2_spare_0 : 1;
- unsigned int g2_spare_1 : 1;
- unsigned int pll_spare_0 : 1;
- unsigned int pll_spare_1 : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_global_spare_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_RST 0x3f
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_SRC_SEL_ADDR 0x4001d4c8
-
-
-/* global_spare_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* Global group sequence spare : polarity invert control */
-/* g1_spare_0 : Polarity invert control for g1_spare_0 */
-/* g1_spare_1 : Polarity invert control for g1_spare_1 */
-/* g2_spare_0 : Polarity invert control for g2_spare_0 */
-/* g2_spare_1 : Polarity invert control for g2_spare_1 */
-/* pll_spare_0 : Polarity invert control for pll_spare_0 */
-/* pll_spare_1 : Polarity invert control for pll_spare_1 */
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_G1_SPARE_0_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_G1_SPARE_0_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_G1_SPARE_0_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_G1_SPARE_0_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_G1_SPARE_0_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_G1_SPARE_0_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_G1_SPARE_1_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_G1_SPARE_1_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_G1_SPARE_1_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_G1_SPARE_1_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_G1_SPARE_1_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_G1_SPARE_1_EN_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_G2_SPARE_0_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_G2_SPARE_0_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_G2_SPARE_0_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_G2_SPARE_0_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_G2_SPARE_0_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_G2_SPARE_0_EN_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_G2_SPARE_1_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_G2_SPARE_1_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_G2_SPARE_1_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_G2_SPARE_1_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_G2_SPARE_1_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_G2_SPARE_1_EN_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_PLL_SPARE_0_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_PLL_SPARE_0_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_PLL_SPARE_0_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_PLL_SPARE_0_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_PLL_SPARE_0_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_PLL_SPARE_0_EN_MASK 0x10
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_PLL_SPARE_1_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_PLL_SPARE_1_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_PLL_SPARE_1_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_PLL_SPARE_1_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_PLL_SPARE_1_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_PLL_SPARE_1_EN_MASK 0x20
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int g1_spare_0 : 1;
- unsigned int g1_spare_1 : 1;
- unsigned int g2_spare_0 : 1;
- unsigned int g2_spare_1 : 1;
- unsigned int pll_spare_0 : 1;
- unsigned int pll_spare_1 : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_global_spare_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_GLOBAL_SPARE_D2R_IF_POL_INVERT_EN_ADDR 0x4001d4cc
-
-
-/* rx_spare_d2r_if_val register */
-/*----------------------*/
-/* Rx group sequence spare : regfile value */
-/* rx1_spare_0 : RX1 group sequence spare */
-/* rx1_spare_1 : RX1 group sequence spare */
-/* rx2_spare_0 : RX2 group sequence spare */
-/* rx2_spare_1 : RX2 group sequence spare */
-/* rx3_spare_0 : RX3 group sequence spare */
-/* rx3_spare_1 : RX3 group sequence spare */
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_VAL_RX1_SPARE_0_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_VAL_RX1_SPARE_0_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_VAL_RX1_SPARE_1_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_VAL_RX1_SPARE_1_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_VAL_RX2_SPARE_0_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_VAL_RX2_SPARE_0_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_VAL_RX2_SPARE_1_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_VAL_RX2_SPARE_1_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_VAL_RX3_SPARE_0_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_VAL_RX3_SPARE_0_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_VAL_RX3_SPARE_1_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_VAL_RX3_SPARE_1_POS 5
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx1_spare_0 : 1;
- unsigned int rx1_spare_1 : 1;
- unsigned int rx2_spare_0 : 1;
- unsigned int rx2_spare_1 : 1;
- unsigned int rx3_spare_0 : 1;
- unsigned int rx3_spare_1 : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_rx_spare_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_VAL_ADDR 0x4001d4d0
-
-
-/* rx_spare_d2r_if_src_sel register */
-/*----------------------*/
-/* Rx group sequence spare : source selection */
-/* rx1_spare_0 : Source selection for rx1_spare_0 */
-/* rx1_spare_1 : Source selection for rx1_spare_1 */
-/* rx2_spare_0 : Source selection for rx2_spare_0 */
-/* rx2_spare_1 : Source selection for rx2_spare_1 */
-/* rx3_spare_0 : Source selection for rx3_spare_0 */
-/* rx3_spare_1 : Source selection for rx3_spare_1 */
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX1_SPARE_0_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX1_SPARE_0_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX1_SPARE_0_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX1_SPARE_0_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX1_SPARE_0_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX1_SPARE_0_TMU_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX1_SPARE_1_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX1_SPARE_1_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX1_SPARE_1_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX1_SPARE_1_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX1_SPARE_1_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX1_SPARE_1_TMU_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX2_SPARE_0_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX2_SPARE_0_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX2_SPARE_0_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX2_SPARE_0_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX2_SPARE_0_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX2_SPARE_0_TMU_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX2_SPARE_1_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX2_SPARE_1_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX2_SPARE_1_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX2_SPARE_1_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX2_SPARE_1_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX2_SPARE_1_TMU_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX3_SPARE_0_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX3_SPARE_0_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX3_SPARE_0_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX3_SPARE_0_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX3_SPARE_0_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX3_SPARE_0_TMU_MASK 0x10
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX3_SPARE_1_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX3_SPARE_1_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX3_SPARE_1_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX3_SPARE_1_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX3_SPARE_1_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RX3_SPARE_1_TMU_MASK 0x20
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx1_spare_0 : 1;
- unsigned int rx1_spare_1 : 1;
- unsigned int rx2_spare_0 : 1;
- unsigned int rx2_spare_1 : 1;
- unsigned int rx3_spare_0 : 1;
- unsigned int rx3_spare_1 : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_rx_spare_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_RST 0x3f
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_SRC_SEL_ADDR 0x4001d4d4
-
-
-/* rx_spare_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* Rx group sequence spare : polarity invert control */
-/* rx1_spare_0 : Polarity invert control for rx1_spare_0 */
-/* rx1_spare_1 : Polarity invert control for rx1_spare_1 */
-/* rx2_spare_0 : Polarity invert control for rx2_spare_0 */
-/* rx2_spare_1 : Polarity invert control for rx2_spare_1 */
-/* rx3_spare_0 : Polarity invert control for rx3_spare_0 */
-/* rx3_spare_1 : Polarity invert control for rx3_spare_1 */
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX1_SPARE_0_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX1_SPARE_0_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX1_SPARE_0_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX1_SPARE_0_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX1_SPARE_0_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX1_SPARE_0_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX1_SPARE_1_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX1_SPARE_1_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX1_SPARE_1_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX1_SPARE_1_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX1_SPARE_1_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX1_SPARE_1_EN_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX2_SPARE_0_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX2_SPARE_0_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX2_SPARE_0_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX2_SPARE_0_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX2_SPARE_0_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX2_SPARE_0_EN_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX2_SPARE_1_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX2_SPARE_1_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX2_SPARE_1_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX2_SPARE_1_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX2_SPARE_1_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX2_SPARE_1_EN_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX3_SPARE_0_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX3_SPARE_0_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX3_SPARE_0_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX3_SPARE_0_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX3_SPARE_0_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX3_SPARE_0_EN_MASK 0x10
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX3_SPARE_1_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX3_SPARE_1_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX3_SPARE_1_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX3_SPARE_1_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX3_SPARE_1_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RX3_SPARE_1_EN_MASK 0x20
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx1_spare_0 : 1;
- unsigned int rx1_spare_1 : 1;
- unsigned int rx2_spare_0 : 1;
- unsigned int rx2_spare_1 : 1;
- unsigned int rx3_spare_0 : 1;
- unsigned int rx3_spare_1 : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_rx_spare_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RX_SPARE_D2R_IF_POL_INVERT_EN_ADDR 0x4001d4d8
-
-
-/* tx_spare_d2r_if_val register */
-/*----------------------*/
-/* Tx group sequence spare : regfile value */
-/* tx1_spare_0 : TX1 group sequence spare */
-/* tx1_spare_1 : TX1 group sequence spare */
-/* tx2_spare_0 : TX2 group sequence spare */
-/* tx2_spare_1 : TX2 group sequence spare */
-/* tx3_spare_0 : TX3 group sequence spare */
-/* tx3_spare_1 : TX3 group sequence spare */
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_VAL_TX1_SPARE_0_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_VAL_TX1_SPARE_0_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_VAL_TX1_SPARE_1_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_VAL_TX1_SPARE_1_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_VAL_TX2_SPARE_0_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_VAL_TX2_SPARE_0_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_VAL_TX2_SPARE_1_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_VAL_TX2_SPARE_1_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_VAL_TX3_SPARE_0_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_VAL_TX3_SPARE_0_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_VAL_TX3_SPARE_1_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_VAL_TX3_SPARE_1_POS 5
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int tx1_spare_0 : 1;
- unsigned int tx1_spare_1 : 1;
- unsigned int tx2_spare_0 : 1;
- unsigned int tx2_spare_1 : 1;
- unsigned int tx3_spare_0 : 1;
- unsigned int tx3_spare_1 : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_tx_spare_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_VAL_ADDR 0x4001d4dc
-
-
-/* tx_spare_d2r_if_src_sel register */
-/*----------------------*/
-/* Tx group sequence spare : source selection */
-/* tx1_spare_0 : Source selection for tx1_spare_0 */
-/* tx1_spare_1 : Source selection for tx1_spare_1 */
-/* tx2_spare_0 : Source selection for tx2_spare_0 */
-/* tx2_spare_1 : Source selection for tx2_spare_1 */
-/* tx3_spare_0 : Source selection for tx3_spare_0 */
-/* tx3_spare_1 : Source selection for tx3_spare_1 */
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX1_SPARE_0_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX1_SPARE_0_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX1_SPARE_0_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX1_SPARE_0_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX1_SPARE_0_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX1_SPARE_0_TMU_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX1_SPARE_1_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX1_SPARE_1_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX1_SPARE_1_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX1_SPARE_1_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX1_SPARE_1_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX1_SPARE_1_TMU_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX2_SPARE_0_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX2_SPARE_0_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX2_SPARE_0_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX2_SPARE_0_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX2_SPARE_0_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX2_SPARE_0_TMU_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX2_SPARE_1_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX2_SPARE_1_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX2_SPARE_1_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX2_SPARE_1_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX2_SPARE_1_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX2_SPARE_1_TMU_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX3_SPARE_0_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX3_SPARE_0_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX3_SPARE_0_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX3_SPARE_0_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX3_SPARE_0_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX3_SPARE_0_TMU_MASK 0x10
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX3_SPARE_1_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX3_SPARE_1_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX3_SPARE_1_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX3_SPARE_1_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX3_SPARE_1_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_TX3_SPARE_1_TMU_MASK 0x20
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int tx1_spare_0 : 1;
- unsigned int tx1_spare_1 : 1;
- unsigned int tx2_spare_0 : 1;
- unsigned int tx2_spare_1 : 1;
- unsigned int tx3_spare_0 : 1;
- unsigned int tx3_spare_1 : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_tx_spare_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_RST 0x3f
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_SRC_SEL_ADDR 0x4001d4e0
-
-
-/* tx_spare_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* Tx group sequence spare : polarity invert control */
-/* tx1_spare_0 : Polarity invert control for tx1_spare_0 */
-/* tx1_spare_1 : Polarity invert control for tx1_spare_1 */
-/* tx2_spare_0 : Polarity invert control for tx2_spare_0 */
-/* tx2_spare_1 : Polarity invert control for tx2_spare_1 */
-/* tx3_spare_0 : Polarity invert control for tx3_spare_0 */
-/* tx3_spare_1 : Polarity invert control for tx3_spare_1 */
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX1_SPARE_0_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX1_SPARE_0_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX1_SPARE_0_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX1_SPARE_0_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX1_SPARE_0_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX1_SPARE_0_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX1_SPARE_1_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX1_SPARE_1_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX1_SPARE_1_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX1_SPARE_1_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX1_SPARE_1_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX1_SPARE_1_EN_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX2_SPARE_0_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX2_SPARE_0_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX2_SPARE_0_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX2_SPARE_0_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX2_SPARE_0_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX2_SPARE_0_EN_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX2_SPARE_1_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX2_SPARE_1_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX2_SPARE_1_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX2_SPARE_1_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX2_SPARE_1_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX2_SPARE_1_EN_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX3_SPARE_0_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX3_SPARE_0_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX3_SPARE_0_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX3_SPARE_0_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX3_SPARE_0_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX3_SPARE_0_EN_MASK 0x10
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX3_SPARE_1_MASK 0x0020
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX3_SPARE_1_POS 5
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX3_SPARE_1_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX3_SPARE_1_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX3_SPARE_1_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_TX3_SPARE_1_EN_MASK 0x20
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int tx1_spare_0 : 1;
- unsigned int tx1_spare_1 : 1;
- unsigned int tx2_spare_0 : 1;
- unsigned int tx2_spare_1 : 1;
- unsigned int tx3_spare_0 : 1;
- unsigned int tx3_spare_1 : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_tx_spare_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_TX_SPARE_D2R_IF_POL_INVERT_EN_ADDR 0x4001d4e4
-
-
-/* rf_txrx_d2r_if_val register */
-/*----------------------*/
-/* High power module output enable : regfile value */
-/* rfrx : High power module support enable for RX */
-/* rftx : High power module support enable for TX */
-/* flicker_rx : Flicker RX */
-/* flicker_tx : Flicker TX */
-/* flicker : Flicker */
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_VAL_RFRX_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_VAL_RFRX_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_VAL_RFTX_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_VAL_RFTX_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_VAL_FLICKER_RX_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_VAL_FLICKER_RX_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_VAL_FLICKER_TX_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_VAL_FLICKER_TX_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_VAL_FLICKER_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_VAL_FLICKER_POS 4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rfrx : 1;
- unsigned int rftx : 1;
- unsigned int flicker_rx : 1;
- unsigned int flicker_tx : 1;
- unsigned int flicker : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_rf_txrx_d2r_if_val;
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_VAL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_VAL_ADDR 0x4001d4e8
-
-
-/* rf_txrx_d2r_if_src_sel register */
-/*----------------------*/
-/* High power module output enable : source selection */
-/* rfrx : Source selection for rfrx */
-/* rftx : Source selection for rftx */
-/* flicker_rx : Source selection for flicker_rx */
-/* flicker_tx : Source selection for flicker_tx */
-/* flicker : Source selection for flicker */
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_RFRX_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_RFRX_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_RFRX_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_RFRX_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_RFRX_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_RFRX_TMU_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_RFTX_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_RFTX_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_RFTX_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_RFTX_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_RFTX_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_RFTX_TMU_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_FLICKER_RX_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_FLICKER_RX_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_FLICKER_RX_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_FLICKER_RX_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_FLICKER_RX_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_FLICKER_RX_TMU_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_FLICKER_TX_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_FLICKER_TX_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_FLICKER_TX_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_FLICKER_TX_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_FLICKER_TX_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_FLICKER_TX_TMU_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_FLICKER_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_FLICKER_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_FLICKER_REGFILE 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_FLICKER_REGFILE_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_FLICKER_TMU 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_FLICKER_TMU_MASK 0x10
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rfrx : 1;
- unsigned int rftx : 1;
- unsigned int flicker_rx : 1;
- unsigned int flicker_tx : 1;
- unsigned int flicker : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_rf_txrx_d2r_if_src_sel;
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_SRC_SEL_ADDR 0x4001d4ec
-
-
-/* rf_txrx_d2r_if_pol_invert_en register */
-/*----------------------*/
-/* High power module output enable : polarity invert control */
-/* rfrx : Polarity invert control for rfrx */
-/* rftx : Polarity invert control for rftx */
-/* flicker_rx : Polarity invert control for flicker_rx */
-/* flicker_tx : Polarity invert control for flicker_tx */
-/* flicker : Polarity invert control for flicker */
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_RFRX_MASK 0x0001
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_RFRX_POS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_RFRX_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_RFRX_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_RFRX_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_RFRX_EN_MASK 0x1
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_RFTX_MASK 0x0002
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_RFTX_POS 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_RFTX_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_RFTX_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_RFTX_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_RFTX_EN_MASK 0x2
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_FLICKER_RX_MASK 0x0004
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_FLICKER_RX_POS 2
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_FLICKER_RX_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_FLICKER_RX_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_FLICKER_RX_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_FLICKER_RX_EN_MASK 0x4
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_FLICKER_TX_MASK 0x0008
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_FLICKER_TX_POS 3
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_FLICKER_TX_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_FLICKER_TX_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_FLICKER_TX_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_FLICKER_TX_EN_MASK 0x8
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_FLICKER_MASK 0x0010
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_FLICKER_POS 4
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_FLICKER_DIS 0
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_FLICKER_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_FLICKER_EN 1
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_FLICKER_EN_MASK 0x10
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rfrx : 1;
- unsigned int rftx : 1;
- unsigned int flicker_rx : 1;
- unsigned int flicker_tx : 1;
- unsigned int flicker : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_transceiver_rf_txrx_d2r_if_pol_invert_en;
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_RST 0x0
-#define EXTAPB_REGFILE_TRANSCEIVER_RF_TXRX_D2R_IF_POL_INVERT_EN_ADDR 0x4001d4f0
-
-
-typedef struct{
- t_extapb_regfile_transceiver_clipdet_d2r_if_val clipdet_d2r_if_val;
- t_extapb_regfile_transceiver_clipdet_d2r_if_src_sel clipdet_d2r_if_src_sel;
- t_extapb_regfile_transceiver_clipdet_d2r_if_pol_invert_en clipdet_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_clipdet_r2d_if_val clipdet_r2d_if_val;
- t_extapb_regfile_transceiver_clipdet_r2d_if_pol_invert_en clipdet_r2d_if_pol_invert_en;
- t_extapb_regfile_transceiver_aaf_d2r_if_val aaf_d2r_if_val;
- t_extapb_regfile_transceiver_aaf_d2r_if_src_sel aaf_d2r_if_src_sel;
- t_extapb_regfile_transceiver_aaf_d2r_if_pol_invert_en aaf_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_aaf_1_d2r_if_val aaf_1_d2r_if_val;
- t_extapb_regfile_transceiver_aaf_1_d2r_if_src_sel aaf_1_d2r_if_src_sel;
- t_extapb_regfile_transceiver_ifamp_d2r_if_val ifamp_d2r_if_val;
- t_extapb_regfile_transceiver_ifamp_d2r_if_src_sel ifamp_d2r_if_src_sel;
- t_extapb_regfile_transceiver_ifamp_d2r_if_pol_invert_en ifamp_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_lna_d2r_if_val lna_d2r_if_val;
- t_extapb_regfile_transceiver_lna_d2r_if_src_sel lna_d2r_if_src_sel;
- t_extapb_regfile_transceiver_lna_d2r_if_pol_invert_en lna_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_pll_dac_0_d2r_if_val pll_dac_0_d2r_if_val;
- t_extapb_regfile_transceiver_pll_dac_0_d2r_if_src_sel pll_dac_0_d2r_if_src_sel;
- t_extapb_regfile_transceiver_pll_dac_0_d2r_if_pol_invert_en pll_dac_0_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_pll_dac_1_d2r_if_val pll_dac_1_d2r_if_val;
- t_extapb_regfile_transceiver_adc_d2r_if_val adc_d2r_if_val;
- t_extapb_regfile_transceiver_adc_d2r_if_src_sel adc_d2r_if_src_sel;
- t_extapb_regfile_transceiver_adc_d2r_if_pol_invert_en adc_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_bgr_d2r_if_val bgr_d2r_if_val;
- t_extapb_regfile_transceiver_bgr_d2r_if_src_sel bgr_d2r_if_src_sel;
- t_extapb_regfile_transceiver_bgr_d2r_if_pol_invert_en bgr_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_bgr_r2d_if_val bgr_r2d_if_val;
- t_extapb_regfile_transceiver_bgr_r2d_if_pol_invert_en bgr_r2d_if_pol_invert_en;
- t_extapb_regfile_transceiver_mixer_d2r_if_val mixer_d2r_if_val;
- t_extapb_regfile_transceiver_mixer_d2r_if_src_sel mixer_d2r_if_src_sel;
- t_extapb_regfile_transceiver_mixer_d2r_if_pol_invert_en mixer_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_tone_0_d2r_if_val tone_0_d2r_if_val;
- t_extapb_regfile_transceiver_tone_0_d2r_if_src_sel tone_0_d2r_if_src_sel;
- t_extapb_regfile_transceiver_tone_1_d2r_if_val tone_1_d2r_if_val;
- t_extapb_regfile_transceiver_tone_1_d2r_if_src_sel tone_1_d2r_if_src_sel;
- t_extapb_regfile_transceiver_tone_0_d2r_if_pol_invert_en tone_0_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_tone_1_d2r_if_pol_invert_en tone_1_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_pll_cp_d2r_if_val pll_cp_d2r_if_val;
- t_extapb_regfile_transceiver_pll_cp_d2r_if_src_sel pll_cp_d2r_if_src_sel;
- t_extapb_regfile_transceiver_pll_cp_d2r_if_pol_invert_en pll_cp_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_pll_xo_d2r_if_val pll_xo_d2r_if_val;
- t_extapb_regfile_transceiver_pll_xo_d2r_if_src_sel pll_xo_d2r_if_src_sel;
- t_extapb_regfile_transceiver_pll_xo_d2r_if_pol_invert_en pll_xo_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_pll_xo_r2d_if_val pll_xo_r2d_if_val;
- t_extapb_regfile_transceiver_pll_xo_r2d_if_pol_invert_en pll_xo_r2d_if_pol_invert_en;
- t_extapb_regfile_transceiver_xo32k_d2r_if_val xo32k_d2r_if_val;
- t_extapb_regfile_transceiver_xo32k_d2r_if_src_sel xo32k_d2r_if_src_sel;
- t_extapb_regfile_transceiver_xo32k_d2r_if_pol_invert_en xo32k_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_xo32k_r2d_if_val xo32k_r2d_if_val;
- t_extapb_regfile_transceiver_xo32k_r2d_if_pol_invert_en xo32k_r2d_if_pol_invert_en;
- t_extapb_regfile_transceiver_ldo_lo_d2r_if_val ldo_lo_d2r_if_val;
- t_extapb_regfile_transceiver_ldo_lo_d2r_if_src_sel ldo_lo_d2r_if_src_sel;
- t_extapb_regfile_transceiver_ldo_lo_d2r_if_pol_invert_en ldo_lo_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_pll_pfd_d2r_if_val pll_pfd_d2r_if_val;
- t_extapb_regfile_transceiver_pll_pfd_d2r_if_src_sel pll_pfd_d2r_if_src_sel;
- t_extapb_regfile_transceiver_pll_pfd_d2r_if_pol_invert_en pll_pfd_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_pll_lock_d2r_if_val pll_lock_d2r_if_val;
- t_extapb_regfile_transceiver_pll_lock_d2r_if_src_sel pll_lock_d2r_if_src_sel;
- t_extapb_regfile_transceiver_pll_lock_d2r_if_pol_invert_en pll_lock_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_pll_lock_r2d_if_val pll_lock_r2d_if_val;
- t_extapb_regfile_transceiver_pll_lock_r2d_if_pol_invert_en pll_lock_r2d_if_pol_invert_en;
- t_extapb_regfile_transceiver_pll_vco_0_d2r_if_val pll_vco_0_d2r_if_val;
- t_extapb_regfile_transceiver_pll_vco_0_d2r_if_src_sel pll_vco_0_d2r_if_src_sel;
- t_extapb_regfile_transceiver_pll_vco_0_d2r_if_pol_invert_en pll_vco_0_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_pll_vco_1_d2r_if_val pll_vco_1_d2r_if_val;
- t_extapb_regfile_transceiver_pll_vco_1_d2r_if_src_sel pll_vco_1_d2r_if_src_sel;
- t_extapb_regfile_transceiver_pll_vco_curset_d2r_if_val pll_vco_curset_d2r_if_val;
- t_extapb_regfile_transceiver_pll_vco_curset_d2r_if_src_sel pll_vco_curset_d2r_if_src_sel;
- t_extapb_regfile_transceiver_pll_lf_d2r_if_val pll_lf_d2r_if_val;
- t_extapb_regfile_transceiver_pll_lf_d2r_if_src_sel pll_lf_d2r_if_src_sel;
- t_extapb_regfile_transceiver_pll_lf_d2r_if_pol_invert_en pll_lf_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_pll_divn_d2r_if_val pll_divn_d2r_if_val;
- t_extapb_regfile_transceiver_pll_divn_d2r_if_src_sel pll_divn_d2r_if_src_sel;
- t_extapb_regfile_transceiver_pll_divn_d2r_if_pol_invert_en pll_divn_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_pll_cal_d2r_if_val pll_cal_d2r_if_val;
- t_extapb_regfile_transceiver_pll_cal_d2r_if_src_sel pll_cal_d2r_if_src_sel;
- t_extapb_regfile_transceiver_pll_cal_d2r_if_pol_invert_en pll_cal_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_pll_cal_0_r2d_if_val pll_cal_0_r2d_if_val;
- t_extapb_regfile_transceiver_pll_cal_0_r2d_if_pol_invert_en pll_cal_0_r2d_if_pol_invert_en;
- t_extapb_regfile_transceiver_pll_cal_1_r2d_if_val pll_cal_1_r2d_if_val;
- t_extapb_regfile_transceiver_various_d2r_if_val various_d2r_if_val;
- t_extapb_regfile_transceiver_various_d2r_if_src_sel various_d2r_if_src_sel;
- t_extapb_regfile_transceiver_various_d2r_if_pol_invert_en various_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_radio_ctrl_d2r_if_val radio_ctrl_d2r_if_val;
- t_extapb_regfile_transceiver_r_rc_cal_d2r_if_val r_rc_cal_d2r_if_val;
- t_extapb_regfile_transceiver_r_rc_cal_d2r_if_src_sel r_rc_cal_d2r_if_src_sel;
- t_extapb_regfile_transceiver_r_rc_cal_d2r_if_pol_invert_en r_rc_cal_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_r_rc_cal_r2d_if_val r_rc_cal_r2d_if_val;
- t_extapb_regfile_transceiver_r_rc_cal_r2d_if_pol_invert_en r_rc_cal_r2d_if_pol_invert_en;
- t_extapb_regfile_transceiver_dcoff_d2r_if_val dcoff_d2r_if_val;
- t_extapb_regfile_transceiver_dcoff_d2r_if_src_sel dcoff_d2r_if_src_sel;
- t_extapb_regfile_transceiver_dcoff_d2r_if_pol_invert_en dcoff_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_dummy_output_d2r_if_val dummy_output_d2r_if_val;
- t_extapb_regfile_transceiver_dummy_input_r2d_if_val dummy_input_r2d_if_val;
- t_extapb_regfile_transceiver_tmu_grp_g_d2r_if_val tmu_grp_g_d2r_if_val;
- t_extapb_regfile_transceiver_tmu_grp_g_d2r_if_src_sel tmu_grp_g_d2r_if_src_sel;
- t_extapb_regfile_transceiver_tmu_grp_g_d2r_if_pol_invert_en tmu_grp_g_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_tmu_grp_tx_d2r_if_val tmu_grp_tx_d2r_if_val;
- t_extapb_regfile_transceiver_tmu_grp_tx_d2r_if_src_sel tmu_grp_tx_d2r_if_src_sel;
- t_extapb_regfile_transceiver_tmu_grp_tx_d2r_if_pol_invert_en tmu_grp_tx_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_tmu_grp_rx_d2r_if_val tmu_grp_rx_d2r_if_val;
- t_extapb_regfile_transceiver_tmu_grp_rx_d2r_if_src_sel tmu_grp_rx_d2r_if_src_sel;
- t_extapb_regfile_transceiver_tmu_grp_rx_d2r_if_pol_invert_en tmu_grp_rx_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_rx_ldo_d2r_if_val rx_ldo_d2r_if_val;
- t_extapb_regfile_transceiver_rx_ldo_d2r_if_src_sel rx_ldo_d2r_if_src_sel;
- t_extapb_regfile_transceiver_rx_ldo_d2r_if_pol_invert_en rx_ldo_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_rx_iftest_d2r_if_val rx_iftest_d2r_if_val;
- t_extapb_regfile_transceiver_rx_ifbuf_d2r_if_val rx_ifbuf_d2r_if_val;
- t_extapb_regfile_transceiver_pll_vco_boost_d2r_if_val pll_vco_boost_d2r_if_val;
- t_extapb_regfile_transceiver_pll_vco_boost_d2r_if_src_sel pll_vco_boost_d2r_if_src_sel;
- t_extapb_regfile_transceiver_pa_0_d2r_if_val pa_0_d2r_if_val;
- t_extapb_regfile_transceiver_pa_0_d2r_if_src_sel pa_0_d2r_if_src_sel;
- t_extapb_regfile_transceiver_pa_0_d2r_if_pol_invert_en pa_0_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_pa_1_d2r_if_val pa_1_d2r_if_val;
- t_extapb_regfile_transceiver_transfo_d2r_if_val transfo_d2r_if_val;
- t_extapb_regfile_transceiver_transfo_d2r_if_src_sel transfo_d2r_if_src_sel;
- t_extapb_regfile_transceiver_transfo_rx_d2r_if_val transfo_rx_d2r_if_val;
- t_extapb_regfile_transceiver_transfo_tx_d2r_if_val transfo_tx_d2r_if_val;
- t_extapb_regfile_transceiver_lo_d2r_if_val lo_d2r_if_val;
- t_extapb_regfile_transceiver_lo_d2r_if_src_sel lo_d2r_if_src_sel;
- t_extapb_regfile_transceiver_lo_d2r_if_pol_invert_en lo_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_ldo_pa_d2r_if_val ldo_pa_d2r_if_val;
- t_extapb_regfile_transceiver_ldo_pa_d2r_if_src_sel ldo_pa_d2r_if_src_sel;
- t_extapb_regfile_transceiver_ldo_pa_d2r_if_pol_invert_en ldo_pa_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_ldo_if_d2r_if_val ldo_if_d2r_if_val;
- t_extapb_regfile_transceiver_ldo_if_d2r_if_src_sel ldo_if_d2r_if_src_sel;
- t_extapb_regfile_transceiver_ldo_if_d2r_if_pol_invert_en ldo_if_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_ldo_synth_d2r_if_val ldo_synth_d2r_if_val;
- t_extapb_regfile_transceiver_ldo_synth_d2r_if_src_sel ldo_synth_d2r_if_src_sel;
- t_extapb_regfile_transceiver_ldo_synth_d2r_if_pol_invert_en ldo_synth_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_ldo_vco_d2r_if_val ldo_vco_d2r_if_val;
- t_extapb_regfile_transceiver_ldo_vco_d2r_if_src_sel ldo_vco_d2r_if_src_sel;
- t_extapb_regfile_transceiver_ldo_vco_d2r_if_pol_invert_en ldo_vco_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_tone_pll_d2r_if_val tone_pll_d2r_if_val;
- t_extapb_regfile_transceiver_tone_pll_d2r_if_src_sel tone_pll_d2r_if_src_sel;
- t_extapb_regfile_transceiver_tone_pll_d2r_if_pol_invert_en tone_pll_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_radio_id_r2d_if_val radio_id_r2d_if_val;
- t_extapb_regfile_transceiver_pll_cur_mir_d2r_if_val pll_cur_mir_d2r_if_val;
- t_extapb_regfile_transceiver_pll_cur_mir_d2r_if_pol_invert_en pll_cur_mir_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_pll_divlo_d2r_if_val pll_divlo_d2r_if_val;
- t_extapb_regfile_transceiver_pll_divlo_d2r_if_src_sel pll_divlo_d2r_if_src_sel;
- t_extapb_regfile_transceiver_pll_divlo_d2r_if_pol_invert_en pll_divlo_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_ldo_rf_d2r_if_val ldo_rf_d2r_if_val;
- t_extapb_regfile_transceiver_ldo_rf_d2r_if_src_sel ldo_rf_d2r_if_src_sel;
- t_extapb_regfile_transceiver_ldo_rf_d2r_if_pol_invert_en ldo_rf_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_global_spare_d2r_if_val global_spare_d2r_if_val;
- t_extapb_regfile_transceiver_global_spare_d2r_if_src_sel global_spare_d2r_if_src_sel;
- t_extapb_regfile_transceiver_global_spare_d2r_if_pol_invert_en global_spare_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_rx_spare_d2r_if_val rx_spare_d2r_if_val;
- t_extapb_regfile_transceiver_rx_spare_d2r_if_src_sel rx_spare_d2r_if_src_sel;
- t_extapb_regfile_transceiver_rx_spare_d2r_if_pol_invert_en rx_spare_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_tx_spare_d2r_if_val tx_spare_d2r_if_val;
- t_extapb_regfile_transceiver_tx_spare_d2r_if_src_sel tx_spare_d2r_if_src_sel;
- t_extapb_regfile_transceiver_tx_spare_d2r_if_pol_invert_en tx_spare_d2r_if_pol_invert_en;
- t_extapb_regfile_transceiver_rf_txrx_d2r_if_val rf_txrx_d2r_if_val;
- t_extapb_regfile_transceiver_rf_txrx_d2r_if_src_sel rf_txrx_d2r_if_src_sel;
- t_extapb_regfile_transceiver_rf_txrx_d2r_if_pol_invert_en rf_txrx_d2r_if_pol_invert_en;
-} t_extapb_regfile_transceiver;
-#define EXTAPB_REGFILE_TRANSCEIVER_ADDR 0x4001d280
-#define EXTAPB_REGFILE_TRANSCEIVER ((t_extapb_regfile_transceiver *)EXTAPB_REGFILE_TRANSCEIVER_ADDR)
-
-
-/* calibration module */
-/*-------------------------*/
-
-
-/* vco_cal_afc_cfg0 register */
-/*----------------------*/
-/* VCO calibration : AFC configuration part 1 */
-/* afc_mdes : Desired counter value M_afc=Fvco_div/Fref_afc (0-4095). (Fvco_div=Fvco/8 or Fvco/12 by means of fixed divider) */
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_CFG0_AFC_MDES_MASK 0x0fff
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_CFG0_AFC_MDES_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int afc_mdes : 12;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_vco_cal_afc_cfg0;
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_CFG0_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_CFG0_ADDR 0x4001d5c0
-
-
-/* vco_cal_afc_cfg1 register */
-/*----------------------*/
-/* VCO calibration : AFC configuration part 2 */
-/* afc_fref_sel : Divider ratio N_afc. Divide-by-2(0), 4(1), 8(2), 16(3), 32(4), 64(5), 128(6), 256(7). Frequeny measurement frequency Fref_afc=Fxo/N_afc */
-/* afc_ki : Frequency gain integrator ki_f=0.5(7), 0.25(6), 0.125(5), 0.0625(4), 1/32(3)...etc */
-/* afc_lock_ctrl1 : Lock criterion AFC-loop 1 */
-/* afc_lock_ctrl2 : Lock criterion AFC-loop 2 */
-/* afc_manual : Manual control AFC. Set frequency loop in manual mode afc_fsel_out = afc_init. The time needed to make afc_fsel_out=afc_init is equal to (N_afc+1)/Fxo, with N_afc=2,4,8,16,31,64,128,256 depending on afc_fref_fsel */
-/* afc_skip_loop1 : When set to 1, the first AFC loop is skipped */
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_CFG1_AFC_FREF_SEL_MASK 0x0007
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_CFG1_AFC_FREF_SEL_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_CFG1_AFC_KI_MASK 0x0038
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_CFG1_AFC_KI_POS 3
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_CFG1_AFC_LOCK_CTRL1_MASK 0x01c0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_CFG1_AFC_LOCK_CTRL1_POS 6
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_CFG1_AFC_LOCK_CTRL2_MASK 0x0e00
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_CFG1_AFC_LOCK_CTRL2_POS 9
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_CFG1_AFC_MANUAL_MASK 0x1000
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_CFG1_AFC_MANUAL_POS 12
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_CFG1_AFC_SKIP_LOOP1_MASK 0x2000
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_CFG1_AFC_SKIP_LOOP1_POS 13
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int afc_fref_sel : 3;
- unsigned int afc_ki : 3;
- unsigned int afc_lock_ctrl1 : 3;
- unsigned int afc_lock_ctrl2 : 3;
- unsigned int afc_manual : 1;
- unsigned int afc_skip_loop1 : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_vco_cal_afc_cfg1;
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_CFG1_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_CFG1_ADDR 0x4001d5c4
-
-
-/* vco_cal_afc_cfg2 register */
-/*----------------------*/
-/* VCO calibration : AFC configuration part 3 */
-/* afc_fsel_init : Initial value for fsel (value on capacitor bank) during manual mode (0-255). 0 = maximum VCO frequency, 255 = minimum VCO frequency. Without using manual mode, the initial value of fsel=128 */
-/* afc_fsel_min : Minimal value for fsel (value on capacitor bank) */
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_CFG2_AFC_FSEL_INIT_MASK 0x00ff
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_CFG2_AFC_FSEL_INIT_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_CFG2_AFC_FSEL_MIN_MASK 0xff00
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_CFG2_AFC_FSEL_MIN_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int afc_fsel_init : 8;
- unsigned int afc_fsel_min : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_vco_cal_afc_cfg2;
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_CFG2_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_CFG2_ADDR 0x4001d5c8
-
-
-/* vco_cal_aac_cfg0 register */
-/*----------------------*/
-/* VCO calibration : AAC configuration part 1 */
-/* aac_ades_in : Desired amplitude setting. Desired amplitude setting also depends on aac_iref_ctrl_in */
-/* aac_ki : Amplitude gain integrator ki_a */
-/* aac_lock_ctrl : Lock criterion */
-/* aac_manual : Manual control AAC. Set amplitude loop in manual mode ( make aac_ictrl_out = aac_ictrl_init). The time needed to make aac_ictrl_out = aac_ictrl_init is equal to: 5/Fxo~0.19us. */
-/* aac_ictrl_correction : Static correction value for aac_ictrl_out */
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_CFG0_AAC_ADES_IN_MASK 0x001f
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_CFG0_AAC_ADES_IN_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_CFG0_AAC_KI_MASK 0x00e0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_CFG0_AAC_KI_POS 5
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_CFG0_AAC_LOCK_CTRL_MASK 0x0700
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_CFG0_AAC_LOCK_CTRL_POS 8
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_CFG0_AAC_MANUAL_MASK 0x0800
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_CFG0_AAC_MANUAL_POS 11
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_CFG0_AAC_ICTRL_CORRECTION_MASK 0x7000
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_CFG0_AAC_ICTRL_CORRECTION_POS 12
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aac_ades_in : 5;
- unsigned int aac_ki : 3;
- unsigned int aac_lock_ctrl : 3;
- unsigned int aac_manual : 1;
- unsigned int aac_ictrl_correction : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_vco_cal_aac_cfg0;
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_CFG0_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_CFG0_ADDR 0x4001d5cc
-
-
-/* vco_cal_aac_cfg1 register */
-/*----------------------*/
-/* VCO calibration : AAC configuration part 2 */
-/* aac_ictrl_init : Initial value for VCO current (aac_ictrl_out) during manual mode. Initial VCO current ~ 45u*24+360u=1440uA Without manual mode the initial value is 31, to ensure fast startup. */
-/* aac_ictrl_min : Minimum value for VCO current (aac_ictrl_out) Minimum current ~ 45u*0+360u=360uA */
-/* aac_iref_ctrl_in : Reference current control input for the Amplitude Voltage Reference (in analog). */
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_CFG1_AAC_ICTRL_INIT_MASK 0x001f
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_CFG1_AAC_ICTRL_INIT_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_CFG1_AAC_ICTRL_MIN_MASK 0x03e0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_CFG1_AAC_ICTRL_MIN_POS 5
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_CFG1_AAC_IREF_CTRL_IN_MASK 0x7c00
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_CFG1_AAC_IREF_CTRL_IN_POS 10
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aac_ictrl_init : 5;
- unsigned int aac_ictrl_min : 5;
- unsigned int aac_iref_ctrl_in : 5;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_vco_cal_aac_cfg1;
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_CFG1_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_CFG1_ADDR 0x4001d5d0
-
-
-/* vco_cal_det_cfg0 register */
-/*----------------------*/
-/* VCO calibration : DET configuration part 1 */
-/* det_kmin : Minimum counter value kmin */
-/* det_kmin_runin : Minimum counter value during VCO run-in period kmin_runin */
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_DET_CFG0_DET_KMIN_MASK 0x00ff
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_DET_CFG0_DET_KMIN_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_DET_CFG0_DET_KMIN_RUNIN_MASK 0xff00
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_DET_CFG0_DET_KMIN_RUNIN_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int det_kmin : 8;
- unsigned int det_kmin_runin : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_vco_cal_det_cfg0;
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_DET_CFG0_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_DET_CFG0_ADDR 0x4001d5d4
-
-
-/* vco_cal_det_cfg1 register */
-/*----------------------*/
-/* VCO calibration : DET configuration part 2 */
-/* det_fref_sel : Divider ratio N_det �?�? divide-by-4(0), 8(1), 16(2), 32(3) �??Out-of-range�?� measurement frequency Fref_det=Fxo/N_det Oscillator frequency Fxo=27MHz */
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_DET_CFG1_DET_FREF_SEL_MASK 0x0003
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_DET_CFG1_DET_FREF_SEL_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int det_fref_sel : 2;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_vco_cal_det_cfg1;
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_DET_CFG1_RST 0x2
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_DET_CFG1_ADDR 0x4001d5d8
-
-
-/* vco_cal_afc_stat0 register */
-/*----------------------*/
-/* VCO calibration AFC status 0 */
-/* afc_m : Frequency counter value (for test purposes) */
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_STAT0_AFC_M_MASK 0x0fff
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_STAT0_AFC_M_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int afc_m : 12;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_vco_cal_afc_stat0;
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_STAT0_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_STAT0_DYNAMIC true
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_STAT0_SNAPCLOCK 0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_STAT0_ADDR 0x4001d5dc
-
-
-/* vco_cal_afc_stat1 register */
-/*----------------------*/
-/* VCO calibration AFC status 1 */
-/* afc_fsel_out : Binary representation of value on capacitor bank (for test purposes) afc_fsel_out=128 (Fvco~3.5GHz) after de-asserting the reset. afc_fsel_out[7:4]= afc_fsel_bin. afc_fsel_out[3:0]~afc_fsel_therm */
-/* afc_fsel_bin : Binary cap bank settings for vco. */
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_STAT1_AFC_FSEL_OUT_MASK 0x00ff
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_STAT1_AFC_FSEL_OUT_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_STAT1_AFC_FSEL_BIN_MASK 0x0f00
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_STAT1_AFC_FSEL_BIN_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int afc_fsel_out : 8;
- unsigned int afc_fsel_bin : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_vco_cal_afc_stat1;
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_STAT1_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_STAT1_DYNAMIC true
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_STAT1_SNAPCLOCK 0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_STAT1_ADDR 0x4001d5e0
-
-
-/* vco_cal_afc_stat2 register */
-/*----------------------*/
-/* VCO calibration AFDCstatus 2 */
-/* afc_fsel_therm : Thermo cap bank settings for vco. */
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_STAT2_AFC_FSEL_THERM_MASK 0x7fff
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_STAT2_AFC_FSEL_THERM_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int afc_fsel_therm : 15;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_vco_cal_afc_stat2;
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_STAT2_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_STAT2_DYNAMIC true
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_STAT2_SNAPCLOCK 0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AFC_STAT2_ADDR 0x4001d5e4
-
-
-/* vco_cal_aac_stat0 register */
-/*----------------------*/
-/* VCO calibration : AAC status part 1 */
-/* aac_ades_out : Adjusted desired amplitude setting for the Amplitude Reference Circuit in analog.If the setting of aac_ades_in is not too low (see 2. Design of Out-Of-Range detector). Then aac_ades_out is equal to Ow5aac_ades_in. */
-/* aac_toolarge_out : Just a feed through from I2aac_toolarge_in */
-/* aac_icomp_ctrl : To activate the bias Current for Bang-Bang Amplitude Detektor (in analog) If ac_enable=1 and aac_lock=0 and IwAsyncReset_a=0 then Owaac_icomp_ctrl=1, else */
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_STAT0_AAC_ADES_OUT_MASK 0x001f
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_STAT0_AAC_ADES_OUT_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_STAT0_AAC_TOOLARGE_OUT_MASK 0x0020
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_STAT0_AAC_TOOLARGE_OUT_POS 5
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_STAT0_AAC_ICOMP_CTRL_MASK 0x0040
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_STAT0_AAC_ICOMP_CTRL_POS 6
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aac_ades_out : 5;
- unsigned int aac_toolarge_out : 1;
- unsigned int aac_icomp_ctrl : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_vco_cal_aac_stat0;
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_STAT0_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_STAT0_DYNAMIC true
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_STAT0_SNAPCLOCK 0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_STAT0_ADDR 0x4001d5e8
-
-
-/* vco_cal_aac_stat1 register */
-/*----------------------*/
-/* VCO calibration : AAC status part 2 */
-/* aac_ictrl_out : Amplitude control for VCO */
-/* aac_iref_ctrl_out : Reference current control output for the Amplitude Voltage Reference (in analog). To adjust the temperature coefficient of the amplitude. If aac_enable=1 and aac_lock=0 and IwAsyncReset_a=0 then aac_ictrl_out=aac_ictrl_in, else */
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_STAT1_AAC_ICTRL_OUT_MASK 0x001f
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_STAT1_AAC_ICTRL_OUT_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_STAT1_AAC_IREF_CTRL_OUT_MASK 0x03e0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_STAT1_AAC_IREF_CTRL_OUT_POS 5
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aac_ictrl_out : 5;
- unsigned int aac_iref_ctrl_out : 5;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_vco_cal_aac_stat1;
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_STAT1_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_STAT1_DYNAMIC true
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_STAT1_SNAPCLOCK 0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_AAC_STAT1_ADDR 0x4001d5ec
-
-
-/* vco_cal_lock_stat register */
-/*----------------------*/
-/* VCO calibration lock status */
-/* afc_lock : Indication if the frequency loop is in lock. The condition to become in lock depends on the setting afc_lock_ctrl1, this setting determines the amount of samples that Fsel should be stable. An Fsel sample is seen as stable as: It did not change more than 1 compared to the previous value. If it is not equal to the maximum or minimum value. As the course part of Fsel does not changes (jump detector) */
-/* aac_lock : Indication if the AAC-loop is in lock */
-/* aafc_lock : Indication that the AAFC (frequency and amplitude) are in lock */
-/* det_out_of_range : Indication if the frequency Fvco_div is out of the range Fvco_div smaller than Fvco_div_min_runin during run_in Fvco_div smaller than Fvco_div_min during calibration The out-of-range detection is active as long: (aafc_lock+afc_manual+aac_manual) =1 */
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_LOCK_STAT_AFC_LOCK_MASK 0x0001
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_LOCK_STAT_AFC_LOCK_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_LOCK_STAT_AAC_LOCK_MASK 0x0002
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_LOCK_STAT_AAC_LOCK_POS 1
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_LOCK_STAT_AAFC_LOCK_MASK 0x0004
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_LOCK_STAT_AAFC_LOCK_POS 2
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_LOCK_STAT_DET_OUT_OF_RANGE_MASK 0x0008
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_LOCK_STAT_DET_OUT_OF_RANGE_POS 3
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int afc_lock : 1;
- unsigned int aac_lock : 1;
- unsigned int aafc_lock : 1;
- unsigned int det_out_of_range : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_vco_cal_lock_stat;
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_LOCK_STAT_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_LOCK_STAT_DYNAMIC true
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_LOCK_STAT_SNAPCLOCK 0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_LOCK_STAT_ADDR 0x4001d5f0
-
-
-/* vco_cal_sync_delay register */
-/*----------------------*/
-/* VCO calibration sync delay for det_fref and afc_fref synchronization in XO clock domain */
-/* aac_fref_sync_delay : AAC Fsel sync delay */
-/* afc_fref_sync_delay : AFC Fsel sync delay */
-/* det_fref_sync_delay : Det Fsel sync delay */
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_SYNC_DELAY_AAC_FREF_SYNC_DELAY_MASK 0x0007
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_SYNC_DELAY_AAC_FREF_SYNC_DELAY_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_SYNC_DELAY_AFC_FREF_SYNC_DELAY_MASK 0x0070
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_SYNC_DELAY_AFC_FREF_SYNC_DELAY_POS 4
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_SYNC_DELAY_DET_FREF_SYNC_DELAY_MASK 0x0700
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_SYNC_DELAY_DET_FREF_SYNC_DELAY_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aac_fref_sync_delay : 3;
- unsigned int : 1;
- unsigned int afc_fref_sync_delay : 3;
- unsigned int : 1;
- unsigned int det_fref_sync_delay : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_vco_cal_sync_delay;
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_SYNC_DELAY_RST 0x10
-#define EXTAPB_REGFILE_CALIBRATION_VCO_CAL_SYNC_DELAY_ADDR 0x4001d5f4
-
-
-/* dco_cal_gain_en_low register */
-/*----------------------*/
-/* DCO calibration gain enable */
-/* gain_en : DCO calibration gain enable, This means ifamp 0/1 for aaf 0-6 and ifamp 2 aaf 0/1 */
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_GAIN_EN_LOW_GAIN_EN_MASK 0xffff
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_GAIN_EN_LOW_GAIN_EN_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int gain_en : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_dco_cal_gain_en_low;
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_GAIN_EN_LOW_RST 0x1
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_GAIN_EN_LOW_ADDR 0x4001d5f8
-
-
-/* dco_cal_gain_en_high register */
-/*----------------------*/
-/* DCO calibration gain enable */
-/* gain_en : DCO calibration gain enable, This means aaf 2-6 and ifamp 2 aaf 0/1 */
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_GAIN_EN_HIGH_GAIN_EN_MASK 0x001f
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_GAIN_EN_HIGH_GAIN_EN_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int gain_en : 5;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_dco_cal_gain_en_high;
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_GAIN_EN_HIGH_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_GAIN_EN_HIGH_ADDR 0x4001d5fc
-
-
-/* dco_cal_cfg register */
-/*----------------------*/
-/* DCO calibration configuration. (Loop enable and lna gain) */
-/* loop_en : Enable bits for the loops of the DC Offset calibration. A one-hot encoding is used. When loop_en[i] = 1, loop i is enabled. */
-/* coarse_tables : */
-/* lna_gain : LNA gain used for DC offset calibration */
-/* lna_gain_val_upd_on_cal_en : When 1, dc offset value related to lna_gain is updated on cal */
-/* lna_gain_val_en : When 1, dc offset value related to lna gain is used */
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_CFG_LOOP_EN_MASK 0x000f
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_CFG_LOOP_EN_POS 0
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
- /* ES1 if explicitly configured */
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_CFG_LNA_GAIN_MASK 0x0070
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_CFG_LNA_GAIN_POS 4
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_CFG_LNA_GAIN_VAL_UPD_ON_CAL_EN_MASK 0x0080
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_CFG_LNA_GAIN_VAL_UPD_ON_CAL_EN_POS 7
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_CFG_LNA_GAIN_VAL_EN_MASK 0x0100
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_CFG_LNA_GAIN_VAL_EN_POS 8
-#else
- /* ES2 default */
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_CFG_COARSE_TABLES_MASK 0x0030
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_CFG_COARSE_TABLES_POS 4
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_CFG_LNA_GAIN_MASK 0x01c0
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_CFG_LNA_GAIN_POS 6
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_CFG_LNA_GAIN_VAL_UPD_ON_CAL_EN_MASK 0x0200
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_CFG_LNA_GAIN_VAL_UPD_ON_CAL_EN_POS 9
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_CFG_LNA_GAIN_VAL_EN_MASK 0x0400
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_CFG_LNA_GAIN_VAL_EN_POS 10
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int loop_en : 4;
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
- /* ES1 if explicitly configured */
-#else
- /* ES2 default */
- unsigned int coarse_tables : 2;
-#endif
- unsigned int lna_gain : 3;
- unsigned int lna_gain_val_upd_on_cal_en : 1;
- unsigned int lna_gain_val_en : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_dco_cal_cfg;
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_CFG_RST 0x17
-#else
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_CFG_RST 0x47
-#endif
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_CFG_ADDR 0x4001d600
-
-
-/* dco_cal_alpha_cfg0 register */
-/*----------------------*/
-/* Alpha parameters applied towards the DC offset compensation module during DC offset calibration for loop 0 and 1 */
-/* alpha_loop0 : Alpha parameter applied towards the DC offset compensation module during loop 0 of the DC offset calibration */
-/* alpha_loop1 : Alpha parameter applied towards the DC offset compensation module during loop 1 of the DC offset calibration */
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_ALPHA_CFG0_ALPHA_LOOP0_MASK 0x001f
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_ALPHA_CFG0_ALPHA_LOOP0_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_ALPHA_CFG0_ALPHA_LOOP1_MASK 0x1f00
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_ALPHA_CFG0_ALPHA_LOOP1_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int alpha_loop0 : 5;
- unsigned int : 3;
- unsigned int alpha_loop1 : 5;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_dco_cal_alpha_cfg0;
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_ALPHA_CFG0_RST 0xc0b
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_ALPHA_CFG0_ADDR 0x4001d604
-
-
-/* dco_cal_alpha_cfg1 register */
-/*----------------------*/
-/* Alpha parameters applied towards the DC offset compensation module during DC offset calibration for loop 2 and 3 */
-/* alpha_loop2 : Alpha parameter applied towards the DC offset compensation module during loop 2 of the DC offset calibration */
-/* alpha_loop3 : Alpha parameter applied towards the DC offset compensation module during loop 3 of the DC offset calibration */
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_ALPHA_CFG1_ALPHA_LOOP2_MASK 0x001f
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_ALPHA_CFG1_ALPHA_LOOP2_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_ALPHA_CFG1_ALPHA_LOOP3_MASK 0x1f00
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_ALPHA_CFG1_ALPHA_LOOP3_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int alpha_loop2 : 5;
- unsigned int : 3;
- unsigned int alpha_loop3 : 5;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_dco_cal_alpha_cfg1;
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_ALPHA_CFG1_RST 0xc0e
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_ALPHA_CFG1_ADDR 0x4001d608
-
-
-/* dco_cal_meas_period register */
-/*----------------------*/
-/* Specifies the measurement period for each loop of the DC offset calibration, being the amount of 16 samples (= 1 us) processed by the DC offset compensation HP/LP filter */
-/* meas_period : Identical to register description */
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_MEAS_PERIOD_MEAS_PERIOD_MASK 0xffff
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_MEAS_PERIOD_MEAS_PERIOD_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int meas_period : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_dco_cal_meas_period;
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_MEAS_PERIOD_RST 0x271
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_MEAS_PERIOD0_ADDR 0x4001d60c
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_MEAS_PERIOD0 ((t_extapb_regfile_calibration_dco_cal_meas_period *)EXTAPB_REGFILE_CALIBRATION_DCO_CAL_MEAS_PERIOD0_ADDR)
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_MEAS_PERIOD1_ADDR 0x4001d610
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_MEAS_PERIOD1 ((t_extapb_regfile_calibration_dco_cal_meas_period *)EXTAPB_REGFILE_CALIBRATION_DCO_CAL_MEAS_PERIOD1_ADDR)
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_MEAS_PERIOD2_ADDR 0x4001d614
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_MEAS_PERIOD2 ((t_extapb_regfile_calibration_dco_cal_meas_period *)EXTAPB_REGFILE_CALIBRATION_DCO_CAL_MEAS_PERIOD2_ADDR)
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_MEAS_PERIOD3_ADDR 0x4001d618
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_MEAS_PERIOD3 ((t_extapb_regfile_calibration_dco_cal_meas_period *)EXTAPB_REGFILE_CALIBRATION_DCO_CAL_MEAS_PERIOD3_ADDR)
-
-
-/* dco_cal_dc_offset_gain_index register */
-/*----------------------*/
-/* The fine DC offset compensation values are stored in HW as an array of 21 values for both I and Q chain. (One entry for each possible gain value) which is indirect accessible by SW. The gain index in this register specifies the gain index for which the SW accesses the fine DC offset compensation values. */
-/* index : See register description */
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_OFFSET_GAIN_INDEX_INDEX_MASK 0x001f
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_OFFSET_GAIN_INDEX_INDEX_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int index : 5;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_dco_cal_dc_offset_gain_index;
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_OFFSET_GAIN_INDEX_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_OFFSET_GAIN_INDEX_ADDR 0x4001d61c
-
-
-/* dco_cal_dc_offset_i register */
-/*----------------------*/
-/* Fine DC offset compensation value (I chain). The gain index for which this register is accessed is set by dco_cal_dc_offset_gain_index. */
-/* fine_dc_offset_i : See register description. */
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_OFFSET_I_FINE_DC_OFFSET_I_MASK 0x0fff
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_OFFSET_I_FINE_DC_OFFSET_I_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int fine_dc_offset_i : 12;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_dco_cal_dc_offset_i;
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_OFFSET_I_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_OFFSET_I_ADDR 0x4001d620
-
-
-/* dco_cal_dc_offset_q register */
-/*----------------------*/
-/* Fine DC offset compensation value (Q chain). The gain index for which this register is accessed is set by dco_cal_dc_offset_gain_index. */
-/* fine_dc_offset_q : See register description. */
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_OFFSET_Q_FINE_DC_OFFSET_Q_MASK 0x0fff
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_OFFSET_Q_FINE_DC_OFFSET_Q_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int fine_dc_offset_q : 12;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_dco_cal_dc_offset_q;
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_OFFSET_Q_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_OFFSET_Q_ADDR 0x4001d624
-
-
-/* iq_cal_alpha_cfg0 register */
-/*----------------------*/
-/* Alpha parameters applied towards the DC offset compensation module during IQ mismatch calibration */
-/* alpha_dc_offset_phase : Alpha parameter applied towards the DC offset compensation module during the IQ mismatch phase calibration. */
-/* alpha_dc_offset_mag : Alpha parameter applied towards the DC offset compensation module during the IQ mismatch magnitude calibration. */
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_ALPHA_CFG0_ALPHA_DC_OFFSET_PHASE_MASK 0x001f
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_ALPHA_CFG0_ALPHA_DC_OFFSET_PHASE_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_ALPHA_CFG0_ALPHA_DC_OFFSET_MAG_MASK 0x03e0
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_ALPHA_CFG0_ALPHA_DC_OFFSET_MAG_POS 5
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int alpha_dc_offset_phase : 5;
- unsigned int alpha_dc_offset_mag : 5;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_iq_cal_alpha_cfg0;
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_ALPHA_CFG0_RST 0xa8
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_ALPHA_CFG0_ADDR 0x4001d628
-
-
-/* iq_cal_alpha_cfg1 register */
-/*----------------------*/
-/* Alpha parameters applied towards the IQ mismatch rectifier module during loop 0 and 1 of the IQ mismatch magnitude calibration. */
-/* alpha_mag_loop0 : Alpha parameter applied towards the IQ mismatch rectifier module during loop 0 of the IQ mismatch magnitude calibration. */
-/* alpha_mag_loop1 : Alpha parameter applied towards the IQ mismatch rectifier module during loop 1 of the IQ mismatch magnitude calibration. */
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_ALPHA_CFG1_ALPHA_MAG_LOOP0_MASK 0x001f
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_ALPHA_CFG1_ALPHA_MAG_LOOP0_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_ALPHA_CFG1_ALPHA_MAG_LOOP1_MASK 0x1f00
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_ALPHA_CFG1_ALPHA_MAG_LOOP1_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int alpha_mag_loop0 : 5;
- unsigned int : 3;
- unsigned int alpha_mag_loop1 : 5;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_iq_cal_alpha_cfg1;
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_ALPHA_CFG1_RST 0xe0b
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_ALPHA_CFG1_ADDR 0x4001d62c
-
-
-/* iq_cal_alpha_cfg2 register */
-/*----------------------*/
-/* Alpha parameters applied towards the IQ mismatch rectifier module during loop 2 and 3 of the IQ mismatch magnitude calibration. */
-/* alpha_mag_loop2 : Alpha parameter applied towards the IQ mismatch rectifier module during loop 2 of the IQ mismatch magnitude calibration. */
-/* alpha_mag_loop3 : Alpha parameter applied towards the IQ mismatch rectifier module during loop 3 of the IQ mismatch magnitude calibration. */
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_ALPHA_CFG2_ALPHA_MAG_LOOP2_MASK 0x001f
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_ALPHA_CFG2_ALPHA_MAG_LOOP2_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_ALPHA_CFG2_ALPHA_MAG_LOOP3_MASK 0x1f00
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_ALPHA_CFG2_ALPHA_MAG_LOOP3_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int alpha_mag_loop2 : 5;
- unsigned int : 3;
- unsigned int alpha_mag_loop3 : 5;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_iq_cal_alpha_cfg2;
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_ALPHA_CFG2_RST 0x1010
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_ALPHA_CFG2_ADDR 0x4001d630
-
-
-/* iq_cal_k_i_cfg register */
-/*----------------------*/
-/* K_i parameters used by the IQ mismatch phase calibration during the different loops. */
-/* k_i_loop0 : K_i parameter used by the IQ mismatch phase calibration during loop 0 */
-/* k_i_loop1 : K_i parameter used by the IQ mismatch phase calibration during loop 1 */
-/* k_i_loop2 : K_i parameter used by the IQ mismatch phase calibration during loop 2 */
-/* k_i_loop3 : K_i parameter used by the IQ mismatch phase calibration during loop 3 */
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_K_I_CFG_K_I_LOOP0_MASK 0x000f
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_K_I_CFG_K_I_LOOP0_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_K_I_CFG_K_I_LOOP1_MASK 0x00f0
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_K_I_CFG_K_I_LOOP1_POS 4
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_K_I_CFG_K_I_LOOP2_MASK 0x0f00
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_K_I_CFG_K_I_LOOP2_POS 8
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_K_I_CFG_K_I_LOOP3_MASK 0xf000
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_K_I_CFG_K_I_LOOP3_POS 12
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int k_i_loop0 : 4;
- unsigned int k_i_loop1 : 4;
- unsigned int k_i_loop2 : 4;
- unsigned int k_i_loop3 : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_iq_cal_k_i_cfg;
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_K_I_CFG_RST 0x9964
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_K_I_CFG_ADDR 0x4001d634
-
-
-/* iq_cal_loop_en register */
-/*----------------------*/
-/* Enable bits for the loops of the IQ mismatch calibration. A one-hot encoding is used. */
-/* phase_loop_en : Enable bits for the loops of the IQ mismatch phase calibration. */
-/* mag_loop_en : Enable bits for the loops of teh IQ mismatch magnitude calibration. */
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_LOOP_EN_PHASE_LOOP_EN_MASK 0x000f
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_LOOP_EN_PHASE_LOOP_EN_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_LOOP_EN_MAG_LOOP_EN_MASK 0x00f0
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_LOOP_EN_MAG_LOOP_EN_POS 4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int phase_loop_en : 4;
- unsigned int mag_loop_en : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_iq_cal_loop_en;
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_LOOP_EN_RST 0x77
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_LOOP_EN_ADDR 0x4001d638
-
-
-/* iq_cal_phase_meas_period register */
-/*----------------------*/
-/* Specifies the measurement period for each loop of the IQ mismatch phase calibration, being the amount of samples processed by the IQ mismatch compensation module. */
-/* meas_period : See register description. */
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_PHASE_MEAS_PERIOD_MEAS_PERIOD_MASK 0xffff
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_PHASE_MEAS_PERIOD_MEAS_PERIOD_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int meas_period : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_iq_cal_phase_meas_period;
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_PHASE_MEAS_PERIOD_RST 0x1
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_PHASE_MEAS_PERIOD0_ADDR 0x4001d63c
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_PHASE_MEAS_PERIOD0 ((t_extapb_regfile_calibration_iq_cal_phase_meas_period *)EXTAPB_REGFILE_CALIBRATION_IQ_CAL_PHASE_MEAS_PERIOD0_ADDR)
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_PHASE_MEAS_PERIOD1_ADDR 0x4001d640
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_PHASE_MEAS_PERIOD1 ((t_extapb_regfile_calibration_iq_cal_phase_meas_period *)EXTAPB_REGFILE_CALIBRATION_IQ_CAL_PHASE_MEAS_PERIOD1_ADDR)
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_PHASE_MEAS_PERIOD2_ADDR 0x4001d644
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_PHASE_MEAS_PERIOD2 ((t_extapb_regfile_calibration_iq_cal_phase_meas_period *)EXTAPB_REGFILE_CALIBRATION_IQ_CAL_PHASE_MEAS_PERIOD2_ADDR)
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_PHASE_MEAS_PERIOD3_ADDR 0x4001d648
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_PHASE_MEAS_PERIOD3 ((t_extapb_regfile_calibration_iq_cal_phase_meas_period *)EXTAPB_REGFILE_CALIBRATION_IQ_CAL_PHASE_MEAS_PERIOD3_ADDR)
-
-
-/* iq_cal_mag_meas_period register */
-/*----------------------*/
-/* Specifies the measurement period for each loop of the IQ mismatch magnitude calibration, being the amount of samples processed by the IQ mismatch compensation module. */
-/* meas_period : See register description */
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_MAG_MEAS_PERIOD_MEAS_PERIOD_MASK 0xffff
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_MAG_MEAS_PERIOD_MEAS_PERIOD_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int meas_period : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_iq_cal_mag_meas_period;
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_MAG_MEAS_PERIOD_RST 0x1
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_MAG_MEAS_PERIOD0_ADDR 0x4001d64c
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_MAG_MEAS_PERIOD0 ((t_extapb_regfile_calibration_iq_cal_mag_meas_period *)EXTAPB_REGFILE_CALIBRATION_IQ_CAL_MAG_MEAS_PERIOD0_ADDR)
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_MAG_MEAS_PERIOD1_ADDR 0x4001d650
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_MAG_MEAS_PERIOD1 ((t_extapb_regfile_calibration_iq_cal_mag_meas_period *)EXTAPB_REGFILE_CALIBRATION_IQ_CAL_MAG_MEAS_PERIOD1_ADDR)
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_MAG_MEAS_PERIOD2_ADDR 0x4001d654
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_MAG_MEAS_PERIOD2 ((t_extapb_regfile_calibration_iq_cal_mag_meas_period *)EXTAPB_REGFILE_CALIBRATION_IQ_CAL_MAG_MEAS_PERIOD2_ADDR)
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_MAG_MEAS_PERIOD3_ADDR 0x4001d658
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_MAG_MEAS_PERIOD3 ((t_extapb_regfile_calibration_iq_cal_mag_meas_period *)EXTAPB_REGFILE_CALIBRATION_IQ_CAL_MAG_MEAS_PERIOD3_ADDR)
-
-
-/* iq_cal_scale_factor register */
-/*----------------------*/
-/* IQ mismatch scale factor */
-/* iq_mismatch_scale_factor : See register description. */
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_SCALE_FACTOR_IQ_MISMATCH_SCALE_FACTOR_MASK 0x01ff
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_SCALE_FACTOR_IQ_MISMATCH_SCALE_FACTOR_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int iq_mismatch_scale_factor : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_iq_cal_scale_factor;
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_SCALE_FACTOR_RST 0x100
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_SCALE_FACTOR_ADDR 0x4001d65c
-
-
-/* iq_cal_cross_factor register */
-/*----------------------*/
-/* IQ mismatch cross factor. */
-/* iq_mismatch_cross_factor : See register description. */
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_CROSS_FACTOR_IQ_MISMATCH_CROSS_FACTOR_MASK 0x03ff
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_CROSS_FACTOR_IQ_MISMATCH_CROSS_FACTOR_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int iq_mismatch_cross_factor : 10;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_iq_cal_cross_factor;
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_CROSS_FACTOR_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_IQ_CAL_CROSS_FACTOR_ADDR 0x4001d660
-
-
-/* r_cal_cfg register */
-/*----------------------*/
-/* Parameters applicable for the R calibration */
-/* power_up_time : Specifies the R calibration power up time above 20 us (expressed in us). */
-/* comp_delay : Specifies the comparator window period above 500 ns (expressed in 16 MHz clock cycles). */
-#define EXTAPB_REGFILE_CALIBRATION_R_CAL_CFG_POWER_UP_TIME_MASK 0x000f
-#define EXTAPB_REGFILE_CALIBRATION_R_CAL_CFG_POWER_UP_TIME_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_R_CAL_CFG_COMP_DELAY_MASK 0x00f0
-#define EXTAPB_REGFILE_CALIBRATION_R_CAL_CFG_COMP_DELAY_POS 4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int power_up_time : 4;
- unsigned int comp_delay : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_r_cal_cfg;
-#define EXTAPB_REGFILE_CALIBRATION_R_CAL_CFG_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_R_CAL_CFG_ADDR 0x4001d664
-
-
-/* r_cal_status register */
-/*----------------------*/
-/* Result of the R calibration */
-/* trimr_set : R trim value */
-/* error : Error flag from the R calibration. */
-#define EXTAPB_REGFILE_CALIBRATION_R_CAL_STATUS_TRIMR_SET_MASK 0x001f
-#define EXTAPB_REGFILE_CALIBRATION_R_CAL_STATUS_TRIMR_SET_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_R_CAL_STATUS_ERROR_MASK 0x0020
-#define EXTAPB_REGFILE_CALIBRATION_R_CAL_STATUS_ERROR_POS 5
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int trimr_set : 5;
- unsigned int error : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_r_cal_status;
-#define EXTAPB_REGFILE_CALIBRATION_R_CAL_STATUS_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_R_CAL_STATUS_DYNAMIC true
-#define EXTAPB_REGFILE_CALIBRATION_R_CAL_STATUS_SNAPCLOCK 0
-#define EXTAPB_REGFILE_CALIBRATION_R_CAL_STATUS_ADDR 0x4001d668
-
-
-/* rc_cal_transient_period register */
-/*----------------------*/
-/* RC calibration delay (expressed in 16 MHz clock cycles) used to let the analog settle after an update of the trimc_set value. */
-/* transient_period : See register description. */
-#define EXTAPB_REGFILE_CALIBRATION_RC_CAL_TRANSIENT_PERIOD_TRANSIENT_PERIOD_MASK 0xffff
-#define EXTAPB_REGFILE_CALIBRATION_RC_CAL_TRANSIENT_PERIOD_TRANSIENT_PERIOD_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int transient_period : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_rc_cal_transient_period;
-#define EXTAPB_REGFILE_CALIBRATION_RC_CAL_TRANSIENT_PERIOD_RST 0x140
-#define EXTAPB_REGFILE_CALIBRATION_RC_CAL_TRANSIENT_PERIOD_ADDR 0x4001d66c
-
-
-/* rc_cal_discharge_period register */
-/*----------------------*/
-/* RC calibration discharge delay time above 46 us (expressed in us) */
-/* discharge_period : See register description */
-#define EXTAPB_REGFILE_CALIBRATION_RC_CAL_DISCHARGE_PERIOD_DISCHARGE_PERIOD_MASK 0x000f
-#define EXTAPB_REGFILE_CALIBRATION_RC_CAL_DISCHARGE_PERIOD_DISCHARGE_PERIOD_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int discharge_period : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_rc_cal_discharge_period;
-#define EXTAPB_REGFILE_CALIBRATION_RC_CAL_DISCHARGE_PERIOD_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_RC_CAL_DISCHARGE_PERIOD_ADDR 0x4001d670
-
-
-/* rc_cal_treshold_period register */
-/*----------------------*/
-/* RC calibration threshold time expressed in 16 MHz clock cycles. */
-/* treshold_period : See register description. */
-#define EXTAPB_REGFILE_CALIBRATION_RC_CAL_TRESHOLD_PERIOD_TRESHOLD_PERIOD_MASK 0xffff
-#define EXTAPB_REGFILE_CALIBRATION_RC_CAL_TRESHOLD_PERIOD_TRESHOLD_PERIOD_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int treshold_period : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_rc_cal_treshold_period;
-#define EXTAPB_REGFILE_CALIBRATION_RC_CAL_TRESHOLD_PERIOD_RST 0x64
-#define EXTAPB_REGFILE_CALIBRATION_RC_CAL_TRESHOLD_PERIOD_ADDR 0x4001d674
-
-
-/* rc_cal_status register */
-/*----------------------*/
-/* Result of the RC calibration */
-/* trimc_set : RC trim value */
-/* error : Error flag from the RC calibration. */
-#define EXTAPB_REGFILE_CALIBRATION_RC_CAL_STATUS_TRIMC_SET_MASK 0x0007
-#define EXTAPB_REGFILE_CALIBRATION_RC_CAL_STATUS_TRIMC_SET_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_RC_CAL_STATUS_ERROR_MASK 0x0008
-#define EXTAPB_REGFILE_CALIBRATION_RC_CAL_STATUS_ERROR_POS 3
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int trimc_set : 3;
- unsigned int error : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_rc_cal_status;
-#define EXTAPB_REGFILE_CALIBRATION_RC_CAL_STATUS_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_RC_CAL_STATUS_DYNAMIC true
-#define EXTAPB_REGFILE_CALIBRATION_RC_CAL_STATUS_SNAPCLOCK 0
-#define EXTAPB_REGFILE_CALIBRATION_RC_CAL_STATUS_ADDR 0x4001d678
-
-
-/* kmod_band_cal_cfg register */
-/*----------------------*/
-/* KMod band calibration parameters */
-/* calib_code_exp : Specifies the negative and positive code applied to the DAC input during KMod band calibration as a power of 2. The positive code is 2**calib_code_exp. The negative code is -2**calib_code_exp. */
-/* fref_kmod_calib_sel : Configures the AFC counter integration window in terms of divided reference (XO) clocks. */
-/* kmod_precision_factor : Specifies the KMod precision factor. */
-/* startup_transient : Speificies the timeout period to avoid transient effects after the DAC code changes. (Expressed in XO clock periods). */
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_CFG_CALIB_CODE_EXP_MASK 0x0007
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_CFG_CALIB_CODE_EXP_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_CFG_FREF_KMOD_CALIB_SEL_MASK 0x0018
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_CFG_FREF_KMOD_CALIB_SEL_POS 3
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_CFG_KMOD_PRECISION_FACTOR_MASK 0x0060
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_CFG_KMOD_PRECISION_FACTOR_POS 5
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_CFG_STARTUP_TRANSIENT_MASK 0x7f80
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_CFG_STARTUP_TRANSIENT_POS 7
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int calib_code_exp : 3;
- unsigned int fref_kmod_calib_sel : 2;
- unsigned int kmod_precision_factor : 2;
- unsigned int startup_transient : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_kmod_band_cal_cfg;
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_CFG_RST 0xa2e
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_CFG_ADDR 0x4001d67c
-
-
-/* kmod_band_cal_count_1_lsb register */
-/*----------------------*/
-/* LSB part of the integrated AFC value resulting from the KMod band calibration with the negative DAC code. */
-/* count_1_lsb : See register description. */
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_COUNT_1_LSB_COUNT_1_LSB_MASK 0xffff
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_COUNT_1_LSB_COUNT_1_LSB_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int count_1_lsb : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_kmod_band_cal_count_1_lsb;
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_COUNT_1_LSB_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_COUNT_1_LSB_ADDR 0x4001d680
-
-
-/* kmod_band_cal_count_1_msb register */
-/*----------------------*/
-/* MSB part of the integrated AFC value resulting from the KMod band calibration with the negative DAC code. */
-/* count_1_msb : See register description. */
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_COUNT_1_MSB_COUNT_1_MSB_MASK 0x003f
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_COUNT_1_MSB_COUNT_1_MSB_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int count_1_msb : 6;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_kmod_band_cal_count_1_msb;
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_COUNT_1_MSB_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_COUNT_1_MSB_ADDR 0x4001d684
-
-
-/* kmod_band_cal_count_2_lsb register */
-/*----------------------*/
-/* LSB part of the integrated AFC value resulting from the KMod band calibration with the positive DAC code. */
-/* count_2_lsb : See register description. */
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_COUNT_2_LSB_COUNT_2_LSB_MASK 0xffff
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_COUNT_2_LSB_COUNT_2_LSB_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int count_2_lsb : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_kmod_band_cal_count_2_lsb;
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_COUNT_2_LSB_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_COUNT_2_LSB_ADDR 0x4001d688
-
-
-/* kmod_band_cal_count_2_msb register */
-/*----------------------*/
-/* MSB part of the integrated AFC value resulting from the KMod band calibration with the positive DAC code. */
-/* count_2_msb : See register description */
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_COUNT_2_MSB_COUNT_2_MSB_MASK 0x003f
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_COUNT_2_MSB_COUNT_2_MSB_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int count_2_msb : 6;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_kmod_band_cal_count_2_msb;
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_COUNT_2_MSB_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_COUNT_2_MSB_ADDR 0x4001d68c
-
-
-/* kmod_band_cal_corr_1 register */
-/*----------------------*/
-/* KMod band correction factor */
-/* corr_1 : See register description */
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_CORR_1_CORR_1_MASK 0x07ff
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_CORR_1_CORR_1_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int corr_1 : 11;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_kmod_band_cal_corr_1;
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_CORR_1_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_BAND_CAL_CORR_1_ADDR 0x4001d690
-
-
-/* kmod_chan_cal_corr_2 register */
-/*----------------------*/
-/* KMod channel correction factor */
-/* corr_2 : See register description */
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_CHAN_CAL_CORR_2_CORR_2_MASK 0x07ff
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_CHAN_CAL_CORR_2_CORR_2_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int corr_2 : 11;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_kmod_chan_cal_corr_2;
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_CHAN_CAL_CORR_2_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_KMOD_CHAN_CAL_CORR_2_ADDR 0x4001d694
-
-
-/* synth_cal_startup_afc_ctrl_bin register */
-/*----------------------*/
-/* Override value for binary cap bank settings for VCO during synthesizer startup calibration. */
-/* afc_ctrl_bin : See register description. */
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_CTRL_BIN_AFC_CTRL_BIN_MASK 0x000f
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_CTRL_BIN_AFC_CTRL_BIN_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int afc_ctrl_bin : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_synth_cal_startup_afc_ctrl_bin;
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_CTRL_BIN_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_CTRL_BIN_ADDR 0x4001d698
-
-
-/* synth_cal_startup_afc_ctrl_therm register */
-/*----------------------*/
-/* Override value for thermo cap bank settings for VCO during synthesizer startup calibration. */
-/* afc_ctrl_therm : See register description. */
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_CTRL_THERM_AFC_CTRL_THERM_MASK 0x7fff
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_CTRL_THERM_AFC_CTRL_THERM_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int afc_ctrl_therm : 15;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_synth_cal_startup_afc_ctrl_therm;
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_CTRL_THERM_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_CTRL_THERM_ADDR 0x4001d69c
-
-
-/* synth_cal_startup_aac_ictrl_out_store register */
-/*----------------------*/
-/* Resulting aac_iref_ctrl_out from AAC calibration during synthesizer startup calibration. */
-/* aac_ictrl_out_store : See register description. */
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AAC_ICTRL_OUT_STORE_AAC_ICTRL_OUT_STORE_MASK 0x001f
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AAC_ICTRL_OUT_STORE_AAC_ICTRL_OUT_STORE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aac_ictrl_out_store : 5;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_synth_cal_startup_aac_ictrl_out_store;
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AAC_ICTRL_OUT_STORE_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AAC_ICTRL_OUT_STORE_ADDR 0x4001d6a0
-
-
-/* synth_cal_startup_afc_fsel_out register */
-/*----------------------*/
-/* Resulting afc_fsel_out values from AFC calibration during synthesizer startup calibration. */
-/* afc_fsel_out1 : Resulting afc_fsel_out value from AFC calibration for FCW1 during synthesizer startup calibration. */
-/* afc_fsel_out2 : Resulting afc_fsel_out value from AFC calibration for FCW2 during synthesizer startup calibration */
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_FSEL_OUT_AFC_FSEL_OUT1_MASK 0x00ff
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_FSEL_OUT_AFC_FSEL_OUT1_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_FSEL_OUT_AFC_FSEL_OUT2_MASK 0xff00
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_FSEL_OUT_AFC_FSEL_OUT2_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int afc_fsel_out1 : 8;
- unsigned int afc_fsel_out2 : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_synth_cal_startup_afc_fsel_out;
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_FSEL_OUT_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_FSEL_OUT_ADDR 0x4001d6a4
-
-
-/* synth_cal_cfg register */
-/*----------------------*/
-/* Synthesizer calibration parameters */
-/* fcw_sel : Selection for FCW1 and FCW2 pair */
-/* high_side_injection : For Rx mode, selects between high side injection (LO frequency higher than carrier frequency), and low side injection (LO frequency lower than carrier frequency */
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_CFG_FCW_SEL_MASK 0x0001
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_CFG_FCW_SEL_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_CFG_FCW_SEL_FCW12_151_155 0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_CFG_FCW_SEL_FCW12_151_155_MASK 0x0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_CFG_FCW_SEL_FCW12_152_154 1
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_CFG_FCW_SEL_FCW12_152_154_MASK 0x1
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_CFG_HIGH_SIDE_INJECTION_MASK 0x0002
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_CFG_HIGH_SIDE_INJECTION_POS 1
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_CFG_HIGH_SIDE_INJECTION_HIGH_SIDE 1
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_CFG_HIGH_SIDE_INJECTION_HIGH_SIDE_MASK 0x2
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_CFG_HIGH_SIDE_INJECTION_LOW_SIDE 0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_CFG_HIGH_SIDE_INJECTION_LOW_SIDE_MASK 0x0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int fcw_sel : 1;
- unsigned int high_side_injection : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_synth_cal_cfg;
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_CFG_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_CFG_ADDR 0x4001d6a8
-
-
-/* synth_cal_startup_afc_2_rx register */
-/*----------------------*/
-/* Resulting afc_2 value from AFC calibration during synthesizer startup calibration. Input for cap bank calculation during Rx mode. */
-/* afc_2 : Resulting afc_2 value from AFC calibration during synthesizer startup calibration */
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_2_RX_AFC_2_MASK 0x01ff
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_2_RX_AFC_2_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int afc_2 : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_synth_cal_startup_afc_2_rx;
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_2_RX_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_2_RX_ADDR 0x4001d6ac
-
-
-/* synth_cal_startup_afc_diff_rx register */
-/*----------------------*/
-/* Resulting afc_diff value from AFC calibration during synthesizer startup calibration. Input for cap bank calculation during Rx mode. */
-/* afc_diff : Resulting afc_diff value from AFC calibration during synthesizer startup calibration */
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_DIFF_RX_AFC_DIFF_MASK 0x00ff
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_DIFF_RX_AFC_DIFF_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int afc_diff : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_synth_cal_startup_afc_diff_rx;
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_DIFF_RX_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_DIFF_RX_ADDR 0x4001d6b0
-
-
-/* synth_cal_pll_lock_init_cfg register */
-/*----------------------*/
-/* Output values applied at PLL locking sequence */
-/* pll_cp_slice_en : Output value for pll_cp_slice_en at start of PLL locking sequence */
-/* pll_cp_offcur_en : Output value for pll_cp_offcur_en at start of PLL locking sequence */
-/* pll_lf_lock_boost_en : Output value for pll_lf_lock_boost_en at start of PLL locking sequence */
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_INIT_CFG_PLL_CP_SLICE_EN_MASK 0x001f
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_INIT_CFG_PLL_CP_SLICE_EN_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_INIT_CFG_PLL_CP_OFFCUR_EN_MASK 0x01e0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_INIT_CFG_PLL_CP_OFFCUR_EN_POS 5
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_INIT_CFG_PLL_LF_LOCK_BOOST_EN_MASK 0x0400
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_INIT_CFG_PLL_LF_LOCK_BOOST_EN_POS 10
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_cp_slice_en : 5;
- unsigned int pll_cp_offcur_en : 4;
- unsigned int : 1;
- unsigned int pll_lf_lock_boost_en : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_synth_cal_pll_lock_init_cfg;
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_INIT_CFG_RST 0x49e
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_INIT_CFG_ADDR 0x4001d6b4
-
-
-/* synth_cal_pre_charge_period register */
-/*----------------------*/
-/* Synthesizer calibration pre_charge period (expressed in 16 MHz clock cycles) */
-/* pre_charge_period : See register description. */
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PRE_CHARGE_PERIOD_PRE_CHARGE_PERIOD_MASK 0x00ff
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PRE_CHARGE_PERIOD_PRE_CHARGE_PERIOD_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pre_charge_period : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_synth_cal_pre_charge_period;
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PRE_CHARGE_PERIOD_RST 0x20
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PRE_CHARGE_PERIOD_ADDR 0x4001d6b8
-
-
-/* synth_cal_pre_charge_pll_lf_pch register */
-/*----------------------*/
-/* Several output value set during synthesizer calibration pre_charge */
-/* pll_lf_pch_p : Output value for pll_lf_pch_p during synthesizer calibration pre_charge */
-/* pll_lf_pch_n : Output value for pll_lf_pch_n during synthesizer calibration pre_charge */
-/* pll_lf_pch_p_hold : Output hold value for pll_lf_pch_p during AFC phases of synthesizer calibration for startup */
-/* pll_lf_pch_n_hold : Output hold value for pll_lf_pch_n during AFC phases of synthesizer calibration for startup */
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PRE_CHARGE_PLL_LF_PCH_PLL_LF_PCH_P_MASK 0x0007
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PRE_CHARGE_PLL_LF_PCH_PLL_LF_PCH_P_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PRE_CHARGE_PLL_LF_PCH_PLL_LF_PCH_N_MASK 0x0038
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PRE_CHARGE_PLL_LF_PCH_PLL_LF_PCH_N_POS 3
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PRE_CHARGE_PLL_LF_PCH_PLL_LF_PCH_P_HOLD_MASK 0x01c0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PRE_CHARGE_PLL_LF_PCH_PLL_LF_PCH_P_HOLD_POS 6
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PRE_CHARGE_PLL_LF_PCH_PLL_LF_PCH_N_HOLD_MASK 0x0e00
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PRE_CHARGE_PLL_LF_PCH_PLL_LF_PCH_N_HOLD_POS 9
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_lf_pch_p : 3;
- unsigned int pll_lf_pch_n : 3;
- unsigned int pll_lf_pch_p_hold : 3;
- unsigned int pll_lf_pch_n_hold : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_synth_cal_pre_charge_pll_lf_pch;
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PRE_CHARGE_PLL_LF_PCH_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PRE_CHARGE_PLL_LF_PCH_ADDR 0x4001d6bc
-
-
-/* synth_cal_pll_lock_loop1_cfg register */
-/*----------------------*/
-/* Output values applied during the first PLL lock loop */
-/* pll_cp_slice_en : Output value for pll_cp_slice_en during the first PLL lock loop */
-/* pll_cp_offcur_en : Output value for pll_cp_offcur_en during the first PLL lock loop. */
-/* pll_lf_lock_boost_en : Output value for pll_lf_lock_boost_en during the first PLL lock loop. */
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_LOOP1_CFG_PLL_CP_SLICE_EN_MASK 0x001f
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_LOOP1_CFG_PLL_CP_SLICE_EN_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_LOOP1_CFG_PLL_CP_OFFCUR_EN_MASK 0x01e0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_LOOP1_CFG_PLL_CP_OFFCUR_EN_POS 5
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_LOOP1_CFG_PLL_LF_LOCK_BOOST_EN_MASK 0x0200
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_LOOP1_CFG_PLL_LF_LOCK_BOOST_EN_POS 9
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_cp_slice_en : 5;
- unsigned int pll_cp_offcur_en : 4;
- unsigned int pll_lf_lock_boost_en : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_synth_cal_pll_lock_loop1_cfg;
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_LOOP1_CFG_RST 0x41
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_LOOP1_CFG_ADDR 0x4001d6c0
-
-
-/* synth_cal_pll_lock_loop2_cfg register */
-/*----------------------*/
-/* Output values applied during the second PLL lock loop */
-/* pll_cp_slice_en : Output value for pll_cp_slice_en during the second PLL lock loop */
-/* pll_cp_offcur_en : Output value for pll_cp_offcur_en during the second PLL lock loop. */
-/* pll_lf_lock_boost_en : Output value for pll_lf_lock_boost_en during the second PLL lock loop. */
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_LOOP2_CFG_PLL_CP_SLICE_EN_MASK 0x001f
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_LOOP2_CFG_PLL_CP_SLICE_EN_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_LOOP2_CFG_PLL_CP_OFFCUR_EN_MASK 0x01e0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_LOOP2_CFG_PLL_CP_OFFCUR_EN_POS 5
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_LOOP2_CFG_PLL_LF_LOCK_BOOST_EN_MASK 0x0200
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_LOOP2_CFG_PLL_LF_LOCK_BOOST_EN_POS 9
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_cp_slice_en : 5;
- unsigned int pll_cp_offcur_en : 4;
- unsigned int pll_lf_lock_boost_en : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_synth_cal_pll_lock_loop2_cfg;
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_LOOP2_CFG_RST 0x83
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_LOOP2_CFG_ADDR 0x4001d6c4
-
-
-/* synth_cal_pll_lock_loop3_cfg register */
-/*----------------------*/
-/* Output values applied during the third PLL lock loop. */
-/* pll_cp_slice_en : Output values for pll_cp_slice_en during the third PLL lock loop. */
-/* pll_cp_offcur_en : Output values for pll_cp_offcur_en during the third PLL lock loop. */
-/* pll_lf_lock_boost_en : Output values for pll_lf_lock_boost_en during the third PLL lock loop. */
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_LOOP3_CFG_PLL_CP_SLICE_EN_MASK 0x001f
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_LOOP3_CFG_PLL_CP_SLICE_EN_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_LOOP3_CFG_PLL_CP_OFFCUR_EN_MASK 0x01e0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_LOOP3_CFG_PLL_CP_OFFCUR_EN_POS 5
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_LOOP3_CFG_PLL_LF_LOCK_BOOST_EN_MASK 0x0200
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_LOOP3_CFG_PLL_LF_LOCK_BOOST_EN_POS 9
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_cp_slice_en : 5;
- unsigned int pll_cp_offcur_en : 4;
- unsigned int pll_lf_lock_boost_en : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_synth_cal_pll_lock_loop3_cfg;
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_LOOP3_CFG_RST 0xc5
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_LOCK_LOOP3_CFG_ADDR 0x4001d6c8
-
-
-/* synth_cal_pll_cal_div_set register */
-/*----------------------*/
-/* VCO clock divider used during synthesizer calibration. */
-/* pll_cal_div_set : See register description. */
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_CAL_DIV_SET_PLL_CAL_DIV_SET_MASK 0x000f
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_CAL_DIV_SET_PLL_CAL_DIV_SET_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_cal_div_set : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_synth_cal_pll_cal_div_set;
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_CAL_DIV_SET_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_PLL_CAL_DIV_SET_ADDR 0x4001d6cc
-
-
-/* synth_cal_startup_afc_2_tx register */
-/*----------------------*/
-/* Input for cap bank calculation during Tx mode. */
-/* afc_2 : Resulting afc_2 value from AFC calibration during synthesizer startup calibration */
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_2_TX_AFC_2_MASK 0x01ff
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_2_TX_AFC_2_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int afc_2 : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_synth_cal_startup_afc_2_tx;
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_2_TX_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_2_TX_ADDR 0x4001d6d0
-
-
-/* dco_cal_dc_ana_offset_i register */
-/*----------------------*/
-/* Coarse DC offset compensation parameters (I chain) */
-/* coarse_dc_offset_i : Coarse (analog) DC offset compensation value (I chain) */
-/* coarse_dc_offset_i_en : Enable bit for the coarse (analog) DC offset compensation (I chain) */
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_I_COARSE_DC_OFFSET_I_MASK 0x000f
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_I_COARSE_DC_OFFSET_I_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_I_COARSE_DC_OFFSET_I_EN_MASK 0x0010
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_I_COARSE_DC_OFFSET_I_EN_POS 4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int coarse_dc_offset_i : 4;
- unsigned int coarse_dc_offset_i_en : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_dco_cal_dc_ana_offset_i;
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_I_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_I_ADDR 0x4001d6d4
-
-
-/* dco_cal_dc_ana_offset_q register */
-/*----------------------*/
-/* Coarse DC offset compensation parameters (Q chain) */
-/* coarse_dc_offset_q : Coarse (analog) DC offset compensation value (Q chain) */
-/* coarse_dc_offset_q_en : Enable bit for the coarse (analog) DC offset compensation (Q chain) */
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_Q_COARSE_DC_OFFSET_Q_MASK 0x000f
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_Q_COARSE_DC_OFFSET_Q_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_Q_COARSE_DC_OFFSET_Q_EN_MASK 0x0010
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_Q_COARSE_DC_OFFSET_Q_EN_POS 4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int coarse_dc_offset_q : 4;
- unsigned int coarse_dc_offset_q_en : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_dco_cal_dc_ana_offset_q;
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_Q_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_Q_ADDR 0x4001d6d8
-
-
-/* dco_cal_dc_ana_offset_lna_gain_i register */
-/*----------------------*/
-/* Coarse DC offset compensation parameters coupled with LNA gain (I chain) */
-/* coarse_dc_offset_i : Coarse (analog) DC offset compensation value (I chain) */
-/* coarse_dc_offset_i_en : Enable bit for the coarse (analog) DC offset compensation (I chain) */
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_I_COARSE_DC_OFFSET_I_MASK 0x000f
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_I_COARSE_DC_OFFSET_I_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_I_COARSE_DC_OFFSET_I_EN_MASK 0x0010
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_I_COARSE_DC_OFFSET_I_EN_POS 4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int coarse_dc_offset_i : 4;
- unsigned int coarse_dc_offset_i_en : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_dco_cal_dc_ana_offset_lna_gain_i;
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_I_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_I0_ADDR 0x4001d6dc
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_I0 ((t_extapb_regfile_calibration_dco_cal_dc_ana_offset_lna_gain_i *)EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_I0_ADDR)
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_I1_ADDR 0x4001d6e0
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_I1 ((t_extapb_regfile_calibration_dco_cal_dc_ana_offset_lna_gain_i *)EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_I1_ADDR)
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_I2_ADDR 0x4001d6e4
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_I2 ((t_extapb_regfile_calibration_dco_cal_dc_ana_offset_lna_gain_i *)EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_I2_ADDR)
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_I3_ADDR 0x4001d6e8
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_I3 ((t_extapb_regfile_calibration_dco_cal_dc_ana_offset_lna_gain_i *)EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_I3_ADDR)
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_I4_ADDR 0x4001d6ec
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_I4 ((t_extapb_regfile_calibration_dco_cal_dc_ana_offset_lna_gain_i *)EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_I4_ADDR)
-
-
-/* dco_cal_dc_ana_offset_lna_gain_q register */
-/*----------------------*/
-/* Coarse DC offset compensation parameters coupled with LNA gain (Q chain) */
-/* coarse_dc_offset_q : Coarse (analog) DC offset compensation value (Q chain) */
-/* coarse_dc_offset_q_en : Enable bit for the coarse (analog) DC offset compensation (Q chain) */
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_Q_COARSE_DC_OFFSET_Q_MASK 0x000f
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_Q_COARSE_DC_OFFSET_Q_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_Q_COARSE_DC_OFFSET_Q_EN_MASK 0x0010
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_Q_COARSE_DC_OFFSET_Q_EN_POS 4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int coarse_dc_offset_q : 4;
- unsigned int coarse_dc_offset_q_en : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_dco_cal_dc_ana_offset_lna_gain_q;
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_Q_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_Q0_ADDR 0x4001d6f0
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_Q0 ((t_extapb_regfile_calibration_dco_cal_dc_ana_offset_lna_gain_q *)EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_Q0_ADDR)
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_Q1_ADDR 0x4001d6f4
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_Q1 ((t_extapb_regfile_calibration_dco_cal_dc_ana_offset_lna_gain_q *)EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_Q1_ADDR)
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_Q2_ADDR 0x4001d6f8
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_Q2 ((t_extapb_regfile_calibration_dco_cal_dc_ana_offset_lna_gain_q *)EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_Q2_ADDR)
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_Q3_ADDR 0x4001d6fc
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_Q3 ((t_extapb_regfile_calibration_dco_cal_dc_ana_offset_lna_gain_q *)EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_Q3_ADDR)
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_Q4_ADDR 0x4001d700
-#define EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_Q4 ((t_extapb_regfile_calibration_dco_cal_dc_ana_offset_lna_gain_q *)EXTAPB_REGFILE_CALIBRATION_DCO_CAL_DC_ANA_OFFSET_LNA_GAIN_Q4_ADDR)
-
-
-/* synth_cal_operation_fcw_frac register */
-/*----------------------*/
-/* Fractional part of the FCW used for synthesizer calibration during operation. */
-/* fcw_frac : See register description. */
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_FCW_FRAC_FCW_FRAC_MASK 0xffff
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_FCW_FRAC_FCW_FRAC_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int fcw_frac : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_synth_cal_operation_fcw_frac;
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_FCW_FRAC_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_FCW_FRAC_DYNAMIC true
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_FCW_FRAC_SNAPCLOCK 0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_FCW_FRAC_ADDR 0x4001d704
-
-
-/* synth_cal_operation_fcw_int register */
-/*----------------------*/
-/* Integer part of the FCW used for synthesizer calibration during operation. */
-/* fcw_int : See register description. */
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_FCW_INT_FCW_INT_MASK 0x00ff
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_FCW_INT_FCW_INT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int fcw_int : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_synth_cal_operation_fcw_int;
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_FCW_INT_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_FCW_INT_DYNAMIC true
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_FCW_INT_SNAPCLOCK 0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_FCW_INT_ADDR 0x4001d708
-
-
-/* synth_cal_operation_afc_fsel_bin register */
-/*----------------------*/
-/* Calculated binary cap bank value for VCO during synthesizer calibration during operation. */
-/* afc_fsel_bin : See register description. */
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_AFC_FSEL_BIN_AFC_FSEL_BIN_MASK 0x000f
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_AFC_FSEL_BIN_AFC_FSEL_BIN_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int afc_fsel_bin : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_synth_cal_operation_afc_fsel_bin;
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_AFC_FSEL_BIN_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_AFC_FSEL_BIN_DYNAMIC true
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_AFC_FSEL_BIN_SNAPCLOCK 0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_AFC_FSEL_BIN_ADDR 0x4001d70c
-
-
-/* synth_cal_operation_afc_fsel_therm register */
-/*----------------------*/
-/* Calculated thermo cap bank settings for VCO during synthesizer calibration during operation. */
-/* afc_fsel_therm : See register description. */
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_AFC_FSEL_THERM_AFC_FSEL_THERM_MASK 0x7fff
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_AFC_FSEL_THERM_AFC_FSEL_THERM_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int afc_fsel_therm : 15;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_synth_cal_operation_afc_fsel_therm;
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_AFC_FSEL_THERM_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_AFC_FSEL_THERM_DYNAMIC true
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_AFC_FSEL_THERM_SNAPCLOCK 0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_AFC_FSEL_THERM_ADDR 0x4001d710
-
-
-/* synth_cal_operation_aac_ictrl_out register */
-/*----------------------*/
-/* Resulting aac_iref_ctrl_out from AAC calibration during synthesizer calibration during operation. */
-/* aac_ictrl_out : See register description. */
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_AAC_ICTRL_OUT_AAC_ICTRL_OUT_MASK 0x001f
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_AAC_ICTRL_OUT_AAC_ICTRL_OUT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aac_ictrl_out : 5;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_synth_cal_operation_aac_ictrl_out;
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_AAC_ICTRL_OUT_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_AAC_ICTRL_OUT_DYNAMIC true
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_AAC_ICTRL_OUT_SNAPCLOCK 0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_OPERATION_AAC_ICTRL_OUT_ADDR 0x4001d714
-
-
-/* synth_cal_startup_ratio_bin_thermo register */
-/*----------------------*/
-/* Ratio bin thermo value used to calculate afc_diff and afc_2. */
-/* ratio_bin_thermo : Ratio bin thermo value used to calculate afc_diff and afc_2 */
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_RATIO_BIN_THERMO_RATIO_BIN_THERMO_MASK 0x000f
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_RATIO_BIN_THERMO_RATIO_BIN_THERMO_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int ratio_bin_thermo : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_synth_cal_startup_ratio_bin_thermo;
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_RATIO_BIN_THERMO_RST 0xb
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_RATIO_BIN_THERMO_ADDR 0x4001d718
-
-
-/* synth_cal_startup_afc_diff_tx register */
-/*----------------------*/
-/* Input for cap bank calculation during Tx mode. */
-/* afc_diff : Resulting afc_diff value from AFC calibration during synthesizer startup calibration */
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_DIFF_TX_AFC_DIFF_MASK 0x00ff
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_DIFF_TX_AFC_DIFF_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int afc_diff : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_synth_cal_startup_afc_diff_tx;
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_DIFF_TX_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_SYNTH_CAL_STARTUP_AFC_DIFF_TX_ADDR 0x4001d71c
-
-
-/* pa_cal_cfg0 register */
-/*----------------------*/
-/* PA calibration parameters */
-/* pa_cal_phase_en : Each bit will enable one of the calibration phases whet set with LSB enabling the first phase */
-/* pa_cal_rssi_offset : Signed value in 6.2 format to add to the measured RSSI value to account for offsets in the calibration path */
-/* pa_cal_ate_en : When set PA calibration radio settings specific to ATE calibration will be applied, and calibration will stop at the end of phase one. */
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_CFG0_PA_CAL_PHASE_EN_MASK 0x000f
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_CFG0_PA_CAL_PHASE_EN_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_CFG0_PA_CAL_RSSI_OFFSET_MASK 0x0ff0
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_CFG0_PA_CAL_RSSI_OFFSET_POS 4
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_CFG0_PA_CAL_ATE_EN_MASK 0x1000
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_CFG0_PA_CAL_ATE_EN_POS 12
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pa_cal_phase_en : 4;
- unsigned int pa_cal_rssi_offset : 8;
- unsigned int pa_cal_ate_en : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_pa_cal_cfg0;
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_CFG0_RST 0xf
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_CFG0_ADDR 0x4001d720
-
-
-/* pa_cal_rcal register */
-/*----------------------*/
-/* PA calibration Rcal */
-/* rcal : Calibration results giving power measured for the pcal settings. Signed value in 8.2 format */
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_RCAL_RCAL_MASK 0x03ff
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_RCAL_RCAL_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rcal : 10;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_pa_cal_rcal;
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_RCAL_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_RCAL0_ADDR 0x4001d724
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_RCAL0 ((t_extapb_regfile_calibration_pa_cal_rcal *)EXTAPB_REGFILE_CALIBRATION_PA_CAL_RCAL0_ADDR)
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_RCAL1_ADDR 0x4001d728
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_RCAL1 ((t_extapb_regfile_calibration_pa_cal_rcal *)EXTAPB_REGFILE_CALIBRATION_PA_CAL_RCAL1_ADDR)
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_RCAL2_ADDR 0x4001d72c
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_RCAL2 ((t_extapb_regfile_calibration_pa_cal_rcal *)EXTAPB_REGFILE_CALIBRATION_PA_CAL_RCAL2_ADDR)
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_RCAL3_ADDR 0x4001d730
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_RCAL3 ((t_extapb_regfile_calibration_pa_cal_rcal *)EXTAPB_REGFILE_CALIBRATION_PA_CAL_RCAL3_ADDR)
-
-
-/* pa_cal_pcal0 register */
-/*----------------------*/
-/* PA calibration Pcal 0 */
-/* pcal : Power setting for PA calibration phase 0. Signed value in 6.0 format */
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_PCAL0_PCAL_MASK 0x003f
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_PCAL0_PCAL_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pcal : 6;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_pa_cal_pcal0;
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_PCAL0_RST 0x32
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_PCAL0_ADDR 0x4001d734
-
-
-/* pa_cal_pcal1 register */
-/*----------------------*/
-/* PA calibration Pcal 1 */
-/* pcal : Power setting for PA calibration phase 1. Signed value in 6.0 format */
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_PCAL1_PCAL_MASK 0x003f
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_PCAL1_PCAL_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pcal : 6;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_pa_cal_pcal1;
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_PCAL1_RST 0x2
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_PCAL1_ADDR 0x4001d738
-
-
-/* pa_cal_pcal2 register */
-/*----------------------*/
-/* PA calibration Pcal 2 */
-/* pcal : Power setting for PA calibration phase 2. Signed value in 6.0 format */
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_PCAL2_PCAL_MASK 0x003f
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_PCAL2_PCAL_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pcal : 6;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_pa_cal_pcal2;
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_PCAL2_RST 0x6
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_PCAL2_ADDR 0x4001d73c
-
-
-/* pa_cal_pcal3 register */
-/*----------------------*/
-/* PA calibration Pcal 3 */
-/* pcal : Power setting for PA calibration phase 3. Signed value in 6.0 format */
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_PCAL3_PCAL_MASK 0x003f
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_PCAL3_PCAL_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pcal : 6;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_pa_cal_pcal3;
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_PCAL3_RST 0xa
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_PCAL3_ADDR 0x4001d740
-
-
-/* pa_cal_abval register */
-/*----------------------*/
-/* PA calibration Aval and Bval */
-/* aval : Gradient delta array (a coefficients) in format 1.6 */
-/* bval : Calibration offset arreay (b coefficients) in format 4.3 */
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_ABVAL_AVAL_MASK 0x007f
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_ABVAL_AVAL_POS 0
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_ABVAL_BVAL_MASK 0x3f80
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_ABVAL_BVAL_POS 7
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aval : 7;
- unsigned int bval : 7;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_calibration_pa_cal_abval;
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_ABVAL_RST 0x0
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_ABVAL0_ADDR 0x4001d744
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_ABVAL0 ((t_extapb_regfile_calibration_pa_cal_abval *)EXTAPB_REGFILE_CALIBRATION_PA_CAL_ABVAL0_ADDR)
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_ABVAL1_ADDR 0x4001d748
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_ABVAL1 ((t_extapb_regfile_calibration_pa_cal_abval *)EXTAPB_REGFILE_CALIBRATION_PA_CAL_ABVAL1_ADDR)
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_ABVAL2_ADDR 0x4001d74c
-#define EXTAPB_REGFILE_CALIBRATION_PA_CAL_ABVAL2 ((t_extapb_regfile_calibration_pa_cal_abval *)EXTAPB_REGFILE_CALIBRATION_PA_CAL_ABVAL2_ADDR)
-
-
-typedef struct{
- t_extapb_regfile_calibration_vco_cal_afc_cfg0 vco_cal_afc_cfg0;
- t_extapb_regfile_calibration_vco_cal_afc_cfg1 vco_cal_afc_cfg1;
- t_extapb_regfile_calibration_vco_cal_afc_cfg2 vco_cal_afc_cfg2;
- t_extapb_regfile_calibration_vco_cal_aac_cfg0 vco_cal_aac_cfg0;
- t_extapb_regfile_calibration_vco_cal_aac_cfg1 vco_cal_aac_cfg1;
- t_extapb_regfile_calibration_vco_cal_det_cfg0 vco_cal_det_cfg0;
- t_extapb_regfile_calibration_vco_cal_det_cfg1 vco_cal_det_cfg1;
- t_extapb_regfile_calibration_vco_cal_afc_stat0 vco_cal_afc_stat0;
- t_extapb_regfile_calibration_vco_cal_afc_stat1 vco_cal_afc_stat1;
- t_extapb_regfile_calibration_vco_cal_afc_stat2 vco_cal_afc_stat2;
- t_extapb_regfile_calibration_vco_cal_aac_stat0 vco_cal_aac_stat0;
- t_extapb_regfile_calibration_vco_cal_aac_stat1 vco_cal_aac_stat1;
- t_extapb_regfile_calibration_vco_cal_lock_stat vco_cal_lock_stat;
- t_extapb_regfile_calibration_vco_cal_sync_delay vco_cal_sync_delay;
- t_extapb_regfile_calibration_dco_cal_gain_en_low dco_cal_gain_en_low;
- t_extapb_regfile_calibration_dco_cal_gain_en_high dco_cal_gain_en_high;
- t_extapb_regfile_calibration_dco_cal_cfg dco_cal_cfg;
- t_extapb_regfile_calibration_dco_cal_alpha_cfg0 dco_cal_alpha_cfg0;
- t_extapb_regfile_calibration_dco_cal_alpha_cfg1 dco_cal_alpha_cfg1;
- t_extapb_regfile_calibration_dco_cal_meas_period dco_cal_meas_period[4];
- t_extapb_regfile_calibration_dco_cal_dc_offset_gain_index dco_cal_dc_offset_gain_index;
- t_extapb_regfile_calibration_dco_cal_dc_offset_i dco_cal_dc_offset_i;
- t_extapb_regfile_calibration_dco_cal_dc_offset_q dco_cal_dc_offset_q;
- t_extapb_regfile_calibration_iq_cal_alpha_cfg0 iq_cal_alpha_cfg0;
- t_extapb_regfile_calibration_iq_cal_alpha_cfg1 iq_cal_alpha_cfg1;
- t_extapb_regfile_calibration_iq_cal_alpha_cfg2 iq_cal_alpha_cfg2;
- t_extapb_regfile_calibration_iq_cal_k_i_cfg iq_cal_k_i_cfg;
- t_extapb_regfile_calibration_iq_cal_loop_en iq_cal_loop_en;
- t_extapb_regfile_calibration_iq_cal_phase_meas_period iq_cal_phase_meas_period[4];
- t_extapb_regfile_calibration_iq_cal_mag_meas_period iq_cal_mag_meas_period[4];
- t_extapb_regfile_calibration_iq_cal_scale_factor iq_cal_scale_factor;
- t_extapb_regfile_calibration_iq_cal_cross_factor iq_cal_cross_factor;
- t_extapb_regfile_calibration_r_cal_cfg r_cal_cfg;
- t_extapb_regfile_calibration_r_cal_status r_cal_status;
- t_extapb_regfile_calibration_rc_cal_transient_period rc_cal_transient_period;
- t_extapb_regfile_calibration_rc_cal_discharge_period rc_cal_discharge_period;
- t_extapb_regfile_calibration_rc_cal_treshold_period rc_cal_treshold_period;
- t_extapb_regfile_calibration_rc_cal_status rc_cal_status;
- t_extapb_regfile_calibration_kmod_band_cal_cfg kmod_band_cal_cfg;
- t_extapb_regfile_calibration_kmod_band_cal_count_1_lsb kmod_band_cal_count_1_lsb;
- t_extapb_regfile_calibration_kmod_band_cal_count_1_msb kmod_band_cal_count_1_msb;
- t_extapb_regfile_calibration_kmod_band_cal_count_2_lsb kmod_band_cal_count_2_lsb;
- t_extapb_regfile_calibration_kmod_band_cal_count_2_msb kmod_band_cal_count_2_msb;
- t_extapb_regfile_calibration_kmod_band_cal_corr_1 kmod_band_cal_corr_1;
- t_extapb_regfile_calibration_kmod_chan_cal_corr_2 kmod_chan_cal_corr_2;
- t_extapb_regfile_calibration_synth_cal_startup_afc_ctrl_bin synth_cal_startup_afc_ctrl_bin;
- t_extapb_regfile_calibration_synth_cal_startup_afc_ctrl_therm synth_cal_startup_afc_ctrl_therm;
- t_extapb_regfile_calibration_synth_cal_startup_aac_ictrl_out_store synth_cal_startup_aac_ictrl_out_store;
- t_extapb_regfile_calibration_synth_cal_startup_afc_fsel_out synth_cal_startup_afc_fsel_out;
- t_extapb_regfile_calibration_synth_cal_cfg synth_cal_cfg;
- t_extapb_regfile_calibration_synth_cal_startup_afc_2_rx synth_cal_startup_afc_2_rx;
- t_extapb_regfile_calibration_synth_cal_startup_afc_diff_rx synth_cal_startup_afc_diff_rx;
- t_extapb_regfile_calibration_synth_cal_pll_lock_init_cfg synth_cal_pll_lock_init_cfg;
- t_extapb_regfile_calibration_synth_cal_pre_charge_period synth_cal_pre_charge_period;
- t_extapb_regfile_calibration_synth_cal_pre_charge_pll_lf_pch synth_cal_pre_charge_pll_lf_pch;
- t_extapb_regfile_calibration_synth_cal_pll_lock_loop1_cfg synth_cal_pll_lock_loop1_cfg;
- t_extapb_regfile_calibration_synth_cal_pll_lock_loop2_cfg synth_cal_pll_lock_loop2_cfg;
- t_extapb_regfile_calibration_synth_cal_pll_lock_loop3_cfg synth_cal_pll_lock_loop3_cfg;
- t_extapb_regfile_calibration_synth_cal_pll_cal_div_set synth_cal_pll_cal_div_set;
- t_extapb_regfile_calibration_synth_cal_startup_afc_2_tx synth_cal_startup_afc_2_tx;
- t_extapb_regfile_calibration_dco_cal_dc_ana_offset_i dco_cal_dc_ana_offset_i;
- t_extapb_regfile_calibration_dco_cal_dc_ana_offset_q dco_cal_dc_ana_offset_q;
- t_extapb_regfile_calibration_dco_cal_dc_ana_offset_lna_gain_i dco_cal_dc_ana_offset_lna_gain_i[5];
- t_extapb_regfile_calibration_dco_cal_dc_ana_offset_lna_gain_q dco_cal_dc_ana_offset_lna_gain_q[5];
- t_extapb_regfile_calibration_synth_cal_operation_fcw_frac synth_cal_operation_fcw_frac;
- t_extapb_regfile_calibration_synth_cal_operation_fcw_int synth_cal_operation_fcw_int;
- t_extapb_regfile_calibration_synth_cal_operation_afc_fsel_bin synth_cal_operation_afc_fsel_bin;
- t_extapb_regfile_calibration_synth_cal_operation_afc_fsel_therm synth_cal_operation_afc_fsel_therm;
- t_extapb_regfile_calibration_synth_cal_operation_aac_ictrl_out synth_cal_operation_aac_ictrl_out;
- t_extapb_regfile_calibration_synth_cal_startup_ratio_bin_thermo synth_cal_startup_ratio_bin_thermo;
- t_extapb_regfile_calibration_synth_cal_startup_afc_diff_tx synth_cal_startup_afc_diff_tx;
- t_extapb_regfile_calibration_pa_cal_cfg0 pa_cal_cfg0;
- t_extapb_regfile_calibration_pa_cal_rcal pa_cal_rcal[4];
- t_extapb_regfile_calibration_pa_cal_pcal0 pa_cal_pcal0;
- t_extapb_regfile_calibration_pa_cal_pcal1 pa_cal_pcal1;
- t_extapb_regfile_calibration_pa_cal_pcal2 pa_cal_pcal2;
- t_extapb_regfile_calibration_pa_cal_pcal3 pa_cal_pcal3;
- t_extapb_regfile_calibration_pa_cal_abval pa_cal_abval[3];
-} t_extapb_regfile_calibration;
-#define EXTAPB_REGFILE_CALIBRATION_ADDR 0x4001d5c0
-#define EXTAPB_REGFILE_CALIBRATION ((t_extapb_regfile_calibration *)EXTAPB_REGFILE_CALIBRATION_ADDR)
-
-
-/* tx_datapath module */
-/*-------------------------*/
-
-
-/* global register */
-/*----------------------*/
-/* Global configuration of the Tx Datapath */
-/* tx_bank : Bank selection of Tx datapath */
-/* dac_output_edge : Selects at which edge of the Tx symbol clock data is output towards DAC */
-/* pll_output_edge : Selects at which edge of the Tx Reference clock data is output towards the PLL */
-/* kmod_band_corr_1_upd_on_cal_en : When enabled, the KMod band correction result after KMod band calibration is copied to the KMod band corr 1 factor of the Tx Datapath. */
-/* kmod_chan_corr_2_upd_on_cal_en : When enabled, the KMod channel correction result after KMod channel calibration is copied to the KMod channel corr 2 factor of the Tx Datapath. */
-/* modem_data_valid_mode : Modem data valid mode. */
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_TX_BANK_MASK 0x0003
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_TX_BANK_POS 0
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_DAC_OUTPUT_EDGE_MASK 0x0004
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_DAC_OUTPUT_EDGE_POS 2
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_DAC_OUTPUT_EDGE_RISING_EDGE 0
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_DAC_OUTPUT_EDGE_RISING_EDGE_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_DAC_OUTPUT_EDGE_FALLING_EDGE 1
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_DAC_OUTPUT_EDGE_FALLING_EDGE_MASK 0x4
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_PLL_OUTPUT_EDGE_MASK 0x0008
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_PLL_OUTPUT_EDGE_POS 3
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_PLL_OUTPUT_EDGE_RISING_EDGE 0
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_PLL_OUTPUT_EDGE_RISING_EDGE_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_PLL_OUTPUT_EDGE_FALLING_EDGE 1
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_PLL_OUTPUT_EDGE_FALLING_EDGE_MASK 0x8
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_KMOD_BAND_CORR_1_UPD_ON_CAL_EN_MASK 0x0010
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_KMOD_BAND_CORR_1_UPD_ON_CAL_EN_POS 4
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_KMOD_BAND_CORR_1_UPD_ON_CAL_EN_DIS 0
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_KMOD_BAND_CORR_1_UPD_ON_CAL_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_KMOD_BAND_CORR_1_UPD_ON_CAL_EN_EN 1
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_KMOD_BAND_CORR_1_UPD_ON_CAL_EN_EN_MASK 0x10
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_KMOD_CHAN_CORR_2_UPD_ON_CAL_EN_MASK 0x0020
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_KMOD_CHAN_CORR_2_UPD_ON_CAL_EN_POS 5
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_KMOD_CHAN_CORR_2_UPD_ON_CAL_EN_DIS 0
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_KMOD_CHAN_CORR_2_UPD_ON_CAL_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_KMOD_CHAN_CORR_2_UPD_ON_CAL_EN_EN 1
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_KMOD_CHAN_CORR_2_UPD_ON_CAL_EN_EN_MASK 0x20
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_MODEM_DATA_VALID_MODE_MASK 0x0040
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_MODEM_DATA_VALID_MODE_POS 6
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_MODEM_DATA_VALID_MODE_PULSE 0
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_MODEM_DATA_VALID_MODE_PULSE_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_MODEM_DATA_VALID_MODE_TOGGLE 1
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_MODEM_DATA_VALID_MODE_TOGGLE_MASK 0x40
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int tx_bank : 2;
- unsigned int dac_output_edge : 1;
- unsigned int pll_output_edge : 1;
- unsigned int kmod_band_corr_1_upd_on_cal_en : 1;
- unsigned int kmod_chan_corr_2_upd_on_cal_en : 1;
- unsigned int modem_data_valid_mode : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tx_datapath_global;
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_RST 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_GLOBAL_ADDR 0x4001d780
-
-
-/* cfg register */
-/*----------------------*/
-/* Bank configuration (Stored in configuration bank) */
-/* cic_active : Enable bit for CIC filter */
-/* gaussian_mode : Mode settings for the gaussian (shape) filter and upsampling */
-/* flush_cnt : Flush counter for upsample gauss filter in clock cycles */
-/* zoh_shift : Position shift */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_CIC_ACTIVE_MASK 0x0001
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_CIC_ACTIVE_POS 0
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_CIC_ACTIVE_LOW 0
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_CIC_ACTIVE_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_CIC_ACTIVE_HIGH 1
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_CIC_ACTIVE_HIGH_MASK 0x1
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_GAUSSIAN_MODE_MASK 0x0006
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_GAUSSIAN_MODE_POS 1
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_GAUSSIAN_MODE_GAUSSIAN_0_50 0
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_GAUSSIAN_MODE_GAUSSIAN_0_50_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_GAUSSIAN_MODE_GAUSSIAN_0_95 1
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_GAUSSIAN_MODE_GAUSSIAN_0_95_MASK 0x2
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_GAUSSIAN_MODE_ZOH 2
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_GAUSSIAN_MODE_ZOH_MASK 0x4
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_FLUSH_CNT_MASK 0x07f8
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_FLUSH_CNT_POS 3
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_ZOH_SHIFT_MASK 0x3800
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_ZOH_SHIFT_POS 11
-#else
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_CIC_ACTIVE_MASK 0x0001
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_CIC_ACTIVE_POS 0
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_CIC_ACTIVE_LOW 0
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_CIC_ACTIVE_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_CIC_ACTIVE_HIGH 1
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_CIC_ACTIVE_HIGH_MASK 0x1
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_CIC_ACTIVE_ZB_2 0
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_CIC_ACTIVE_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_CIC_ACTIVE_BLE_1 0
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_CIC_ACTIVE_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_CIC_ACTIVE_BLE_2 0
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_CIC_ACTIVE_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_GAUSSIAN_MODE_MASK 0x0006
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_GAUSSIAN_MODE_POS 1
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_GAUSSIAN_MODE_GAUSSIAN_0_50 0
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_GAUSSIAN_MODE_GAUSSIAN_0_50_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_GAUSSIAN_MODE_GAUSSIAN_0_95 1
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_GAUSSIAN_MODE_GAUSSIAN_0_95_MASK 0x2
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_GAUSSIAN_MODE_ZOH 2
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_GAUSSIAN_MODE_ZOH_MASK 0x4
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_GAUSSIAN_MODE_ZB_2 0
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_GAUSSIAN_MODE_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_GAUSSIAN_MODE_BLE_1 0
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_GAUSSIAN_MODE_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_GAUSSIAN_MODE_BLE_2 0
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_GAUSSIAN_MODE_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_FLUSH_CNT_MASK 0x07f8
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_FLUSH_CNT_POS 3
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_FLUSH_CNT_ZB_2 21
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_FLUSH_CNT_ZB_2_MASK 0xa8
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_FLUSH_CNT_BLE_1 21
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_FLUSH_CNT_BLE_1_MASK 0xa8
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_FLUSH_CNT_BLE_2 21
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_FLUSH_CNT_BLE_2_MASK 0xa8
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_ZOH_SHIFT_MASK 0x3800
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_ZOH_SHIFT_POS 11
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_ZOH_SHIFT_ZB_2 6
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_ZOH_SHIFT_ZB_2_MASK 0x3000
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_ZOH_SHIFT_BLE_1 6
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_ZOH_SHIFT_BLE_1_MASK 0x3000
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_ZOH_SHIFT_BLE_2 6
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_ZOH_SHIFT_BLE_2_MASK 0x3000
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int cic_active : 1;
- unsigned int gaussian_mode : 2;
- unsigned int flush_cnt : 8;
- unsigned int zoh_shift : 3;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tx_datapath_cfg;
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_RST 0x30a8
-#define EXTAPB_REGFILE_TX_DATAPATH_CFG_ADDR 0x4001d784
-
-
-/* delay register */
-/*----------------------*/
-/* Sample delay compensation (Stored in configuration bank) */
-/* first_point_coarse : Sample delay first point, coarse */
-/* first_point_fine : Sample delay first point, fine */
-/* second_point : Sample delay second point */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_FIRST_POINT_COARSE_MASK 0x000f
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_FIRST_POINT_COARSE_POS 0
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_FIRST_POINT_FINE_MASK 0x0030
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_FIRST_POINT_FINE_POS 4
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_SECOND_POINT_MASK 0x03c0
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_SECOND_POINT_POS 6
-#else
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_FIRST_POINT_COARSE_MASK 0x000f
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_FIRST_POINT_COARSE_POS 0
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_FIRST_POINT_COARSE_ZB_2 0
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_FIRST_POINT_COARSE_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_FIRST_POINT_COARSE_BLE_1 0
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_FIRST_POINT_COARSE_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_FIRST_POINT_COARSE_BLE_2 0
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_FIRST_POINT_COARSE_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_FIRST_POINT_FINE_MASK 0x0030
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_FIRST_POINT_FINE_POS 4
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_FIRST_POINT_FINE_ZB_2 0
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_FIRST_POINT_FINE_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_FIRST_POINT_FINE_BLE_1 0
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_FIRST_POINT_FINE_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_FIRST_POINT_FINE_BLE_2 0
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_FIRST_POINT_FINE_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_SECOND_POINT_MASK 0x03c0
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_SECOND_POINT_POS 6
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_SECOND_POINT_ZB_2 0
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_SECOND_POINT_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_SECOND_POINT_BLE_1 0
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_SECOND_POINT_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_SECOND_POINT_BLE_2 0
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_SECOND_POINT_BLE_2_MASK 0x0
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int first_point_coarse : 4;
- unsigned int first_point_fine : 2;
- unsigned int second_point : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tx_datapath_delay;
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_RST 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_DELAY_ADDR 0x4001d788
-
-
-/* gain_first_point register */
-/*----------------------*/
-/* Tx Datapath : Gain first point (Stored in configuration bank) */
-/* gain_first_point : Gain first point */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_FIRST_POINT_GAIN_FIRST_POINT_MASK 0x07ff
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_FIRST_POINT_GAIN_FIRST_POINT_POS 0
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_FIRST_POINT_GAIN_FIRST_POINT_BT_LE_1 1924
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_FIRST_POINT_GAIN_FIRST_POINT_BT_LE_1_MASK 0x784
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_FIRST_POINT_GAIN_FIRST_POINT_BT_LE_2 1806
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_FIRST_POINT_GAIN_FIRST_POINT_BT_LE_2_MASK 0x70e
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_FIRST_POINT_GAIN_FIRST_POINT_NORDIC_250 2004
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_FIRST_POINT_GAIN_FIRST_POINT_NORDIC_250_MASK 0x7d4
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_FIRST_POINT_GAIN_FIRST_POINT_NORDIC_2 1893
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_FIRST_POINT_GAIN_FIRST_POINT_NORDIC_2_MASK 0x765
-#else
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_FIRST_POINT_GAIN_FIRST_POINT_MASK 0x07ff
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_FIRST_POINT_GAIN_FIRST_POINT_POS 0
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_FIRST_POINT_GAIN_FIRST_POINT_ZB_2 0
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_FIRST_POINT_GAIN_FIRST_POINT_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_FIRST_POINT_GAIN_FIRST_POINT_BLE_1 0
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_FIRST_POINT_GAIN_FIRST_POINT_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_FIRST_POINT_GAIN_FIRST_POINT_BLE_2 0
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_FIRST_POINT_GAIN_FIRST_POINT_BLE_2_MASK 0x0
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int gain_first_point : 11;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tx_datapath_gain_first_point;
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_FIRST_POINT_RST 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_FIRST_POINT_ADDR 0x4001d78c
-
-
-/* gain_second_point register */
-/*----------------------*/
-/* Tx Datapath : Gain second point (Stored in configuration bank) */
-/* gain_second_point : Gain second point */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_SECOND_POINT_GAIN_SECOND_POINT_MASK 0x00ff
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_SECOND_POINT_GAIN_SECOND_POINT_POS 0
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_SECOND_POINT_GAIN_SECOND_POINT_BT_LE_1 31
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_SECOND_POINT_GAIN_SECOND_POINT_BT_LE_1_MASK 0x1f
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_SECOND_POINT_GAIN_SECOND_POINT_BT_LE_2 60
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_SECOND_POINT_GAIN_SECOND_POINT_BT_LE_2_MASK 0x3c
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_SECOND_POINT_GAIN_SECOND_POINT_NORDIC_250 11
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_SECOND_POINT_GAIN_SECOND_POINT_NORDIC_250_MASK 0xb
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_SECOND_POINT_GAIN_SECOND_POINT_NORDIC_2 39
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_SECOND_POINT_GAIN_SECOND_POINT_NORDIC_2_MASK 0x27
-#else
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_SECOND_POINT_GAIN_SECOND_POINT_MASK 0x00ff
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_SECOND_POINT_GAIN_SECOND_POINT_POS 0
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_SECOND_POINT_GAIN_SECOND_POINT_ZB_2 0
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_SECOND_POINT_GAIN_SECOND_POINT_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_SECOND_POINT_GAIN_SECOND_POINT_BLE_1 0
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_SECOND_POINT_GAIN_SECOND_POINT_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_SECOND_POINT_GAIN_SECOND_POINT_BLE_2 0
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_SECOND_POINT_GAIN_SECOND_POINT_BLE_2_MASK 0x0
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int gain_second_point : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tx_datapath_gain_second_point;
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_SECOND_POINT_RST 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_GAIN_SECOND_POINT_ADDR 0x4001d790
-
-
-/* kmod_band_corr_1 register */
-/*----------------------*/
-/* KMod band correction factor */
-/* corr_1 : See register description. */
-#define EXTAPB_REGFILE_TX_DATAPATH_KMOD_BAND_CORR_1_CORR_1_MASK 0x07ff
-#define EXTAPB_REGFILE_TX_DATAPATH_KMOD_BAND_CORR_1_CORR_1_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int corr_1 : 11;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tx_datapath_kmod_band_corr_1;
-#define EXTAPB_REGFILE_TX_DATAPATH_KMOD_BAND_CORR_1_RST 0x400
-#define EXTAPB_REGFILE_TX_DATAPATH_KMOD_BAND_CORR_1_ADDR 0x4001d794
-
-
-/* kmod_chan_corr_2 register */
-/*----------------------*/
-/* KMod channel correction factor */
-/* corr_2 : See register description. */
-#define EXTAPB_REGFILE_TX_DATAPATH_KMOD_CHAN_CORR_2_CORR_2_MASK 0x07ff
-#define EXTAPB_REGFILE_TX_DATAPATH_KMOD_CHAN_CORR_2_CORR_2_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int corr_2 : 11;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tx_datapath_kmod_chan_corr_2;
-#define EXTAPB_REGFILE_TX_DATAPATH_KMOD_CHAN_CORR_2_RST 0x400
-#define EXTAPB_REGFILE_TX_DATAPATH_KMOD_CHAN_CORR_2_ADDR 0x4001d798
-
-
-/* pre_const register */
-/*----------------------*/
-/* Constant value to be prepended before packet (Stored in configuration bank) */
-/* len : Length of pre constant value, only bits 4:0 are used */
-/* val : Constant value for prepend: -1, 0, +1 */
-/* en : Configures whether constant value is prepended before packet */
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_LEN_MASK 0x00ff
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_LEN_POS 0
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_VAL_MASK 0x0300
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_VAL_POS 8
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_EN_MASK 0x0400
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_EN_POS 10
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_EN_DIS 0
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_EN_DIS_MASK 0x0
-#else
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_LEN_MASK 0x00ff
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_LEN_POS 0
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_LEN_ZB_2 0
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_LEN_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_LEN_BLE_1 0
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_LEN_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_LEN_BLE_2 0
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_LEN_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_VAL_MASK 0x0300
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_VAL_POS 8
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_VAL_ZB_2 0
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_VAL_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_VAL_BLE_1 0
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_VAL_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_VAL_BLE_2 0
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_VAL_BLE_2_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_EN_MASK 0x0400
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_EN_POS 10
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_EN_DIS 0
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_EN_EN 1
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_EN_EN_MASK 0x400
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_EN_ZB_2 0
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_EN_ZB_2_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_EN_BLE_1 0
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_EN_BLE_1_MASK 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_EN_BLE_2 0
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_EN_BLE_2_MASK 0x0
-#endif
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int len : 8;
- unsigned int val : 2;
- unsigned int en : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tx_datapath_pre_const;
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_RST 0x0
-#define EXTAPB_REGFILE_TX_DATAPATH_PRE_CONST_ADDR 0x4001d79c
-
-
-typedef struct{
- t_extapb_regfile_tx_datapath_global global;
- t_extapb_regfile_tx_datapath_cfg cfg;
- t_extapb_regfile_tx_datapath_delay delay;
- t_extapb_regfile_tx_datapath_gain_first_point gain_first_point;
- t_extapb_regfile_tx_datapath_gain_second_point gain_second_point;
- t_extapb_regfile_tx_datapath_kmod_band_corr_1 kmod_band_corr_1;
- t_extapb_regfile_tx_datapath_kmod_chan_corr_2 kmod_chan_corr_2;
- t_extapb_regfile_tx_datapath_pre_const pre_const;
-} t_extapb_regfile_tx_datapath;
-#define EXTAPB_REGFILE_TX_DATAPATH_ADDR 0x4001d780
-#define EXTAPB_REGFILE_TX_DATAPATH ((t_extapb_regfile_tx_datapath *)EXTAPB_REGFILE_TX_DATAPATH_ADDR)
-
-
-/* tmu module */
-/*-------------------------*/
-
-
-/* mode_ctrl register */
-/*----------------------*/
-/* Operation mode control register. Cannot be written without reference clock: any next write will hang. */
-/* tx_notrx : Transfer direction selection. */
-/* tx_order : Register file tx_order value */
-/* rx_order : Register file rx_order value */
-/* pll_mode : TBD */
-/* packet_start_mode : Specifies which packet_start is used. */
-/* rx_false_sync_mode : Specifies the behaviour when a false sync is detected in scan mode */
-/* ble_mode : Specifies the BLE mode */
-/* ble_sync_mode : Specifies the BLE synchronization mode (select which BLE sync wire is used to freeze the AGC) */
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_TX_NOTRX_MASK 0x0001
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_TX_NOTRX_POS 0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_TX_NOTRX_RX 0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_TX_NOTRX_RX_MASK 0x0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_TX_NOTRX_TX 1
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_TX_NOTRX_TX_MASK 0x1
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_TX_ORDER_MASK 0x0006
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_TX_ORDER_POS 1
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_RX_ORDER_MASK 0x0018
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_RX_ORDER_POS 3
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_PLL_MODE_MASK 0x00e0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_PLL_MODE_POS 5
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_PLL_MODE_PLL_SKIP 0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_PLL_MODE_PLL_SKIP_MASK 0x0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_PLL_MODE_PLL_STARTUP 1
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_PLL_MODE_PLL_STARTUP_MASK 0x20
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_PLL_MODE_PLL_OPERATION 2
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_PLL_MODE_PLL_OPERATION_MASK 0x40
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_PLL_MODE_PLL_STARTUP_OPERATION 3
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_PLL_MODE_PLL_STARTUP_OPERATION_MASK 0x60
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_PLL_MODE_PLL_SW_CONTROLLED 4
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_PLL_MODE_PLL_SW_CONTROLLED_MASK 0x80
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_PACKET_START_MODE_MASK 0x0100
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_PACKET_START_MODE_POS 8
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_PACKET_START_MODE_PACKET_START_EXTERNAL 0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_PACKET_START_MODE_PACKET_START_EXTERNAL_MASK 0x0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_PACKET_START_MODE_PACKET_START_INTERNAL 1
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_PACKET_START_MODE_PACKET_START_INTERNAL_MASK 0x100
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_RX_FALSE_SYNC_MODE_MASK 0x0200
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_RX_FALSE_SYNC_MODE_POS 9
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_RX_FALSE_SYNC_MODE_RETRY_MODE 0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_RX_FALSE_SYNC_MODE_RETRY_MODE_MASK 0x0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_RX_FALSE_SYNC_MODE_ABORT_MODE 1
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_RX_FALSE_SYNC_MODE_ABORT_MODE_MASK 0x200
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_BLE_MODE_MASK 0x0400
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_BLE_MODE_POS 10
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_BLE_MODE_ZB 0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_BLE_MODE_ZB_MASK 0x0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_BLE_MODE_BLE 1
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_BLE_MODE_BLE_MASK 0x400
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_BLE_SYNC_MODE_MASK 0x1800
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_BLE_SYNC_MODE_POS 11
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int tx_notrx : 1;
- unsigned int tx_order : 2;
- unsigned int rx_order : 2;
- unsigned int pll_mode : 3;
- unsigned int packet_start_mode : 1;
- unsigned int rx_false_sync_mode : 1;
- unsigned int ble_mode : 1;
- unsigned int ble_sync_mode : 2;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_mode_ctrl;
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_RST 0x100
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_ADDR 0x4001d800
-
-
-/* mode_ctrl_2 register */
-/*----------------------*/
-/* Operation mode control register. Cannot be written without reference clock: any next write will hang. */
-/* mra2_mode_ctrl_en : MRA2 mode control enable. */
-/* pll_phase_skip_en : Specifies whether the PLL phase is skipped in between consecutive packets in the same power cycle */
-/* trx_powerup_en : Specifies whether the TMU initiates the power up for the selected mode during the PLL phase. */
-/* trx_powerdown_en : Specifies whether the TMU initiates the power down for the selected mode after a transfer is finished. */
-/* global_powerdown_en : Specifies whether the TMU initiates the global power down after all transfers are finished. */
-/* kmod_band_cal_en : Specifies whether the TMU initiates the KMod band calibration during the PLL phase. */
-/* kmod_chan_cal_en : Specifies whether the TMU initiates the KMod channel calibration during the PLL phase. */
-/* synth_cal_startup_en : Specifies whether the TMU initiates the synthesizer calibration for startup during the PLL phase. */
-/* synth_cal_operation_en : Specifies whether the TMU initiates the synthesizer calibration for operation during the PLL phase. */
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_MRA2_MODE_CTRL_EN_MASK 0x0001
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_MRA2_MODE_CTRL_EN_POS 0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_MRA2_MODE_CTRL_EN_DIS 0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_MRA2_MODE_CTRL_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_MRA2_MODE_CTRL_EN_EN 1
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_MRA2_MODE_CTRL_EN_EN_MASK 0x1
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_PLL_PHASE_SKIP_EN_MASK 0x0002
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_PLL_PHASE_SKIP_EN_POS 1
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_PLL_PHASE_SKIP_EN_DIS 0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_PLL_PHASE_SKIP_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_PLL_PHASE_SKIP_EN_EN 1
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_PLL_PHASE_SKIP_EN_EN_MASK 0x2
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_TRX_POWERUP_EN_MASK 0x0004
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_TRX_POWERUP_EN_POS 2
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_TRX_POWERUP_EN_DIS 0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_TRX_POWERUP_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_TRX_POWERUP_EN_EN 1
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_TRX_POWERUP_EN_EN_MASK 0x4
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_TRX_POWERDOWN_EN_MASK 0x0008
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_TRX_POWERDOWN_EN_POS 3
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_TRX_POWERDOWN_EN_DIS 0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_TRX_POWERDOWN_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_TRX_POWERDOWN_EN_EN 1
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_TRX_POWERDOWN_EN_EN_MASK 0x8
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_GLOBAL_POWERDOWN_EN_MASK 0x0010
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_GLOBAL_POWERDOWN_EN_POS 4
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_GLOBAL_POWERDOWN_EN_DIS 0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_GLOBAL_POWERDOWN_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_GLOBAL_POWERDOWN_EN_EN 1
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_GLOBAL_POWERDOWN_EN_EN_MASK 0x10
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_KMOD_BAND_CAL_EN_MASK 0x0020
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_KMOD_BAND_CAL_EN_POS 5
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_KMOD_BAND_CAL_EN_DIS 0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_KMOD_BAND_CAL_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_KMOD_BAND_CAL_EN_EN 1
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_KMOD_BAND_CAL_EN_EN_MASK 0x20
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_KMOD_CHAN_CAL_EN_MASK 0x0040
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_KMOD_CHAN_CAL_EN_POS 6
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_KMOD_CHAN_CAL_EN_DIS 0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_KMOD_CHAN_CAL_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_KMOD_CHAN_CAL_EN_EN 1
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_KMOD_CHAN_CAL_EN_EN_MASK 0x40
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_SYNTH_CAL_STARTUP_EN_MASK 0x0080
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_SYNTH_CAL_STARTUP_EN_POS 7
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_SYNTH_CAL_STARTUP_EN_DIS 0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_SYNTH_CAL_STARTUP_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_SYNTH_CAL_STARTUP_EN_EN 1
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_SYNTH_CAL_STARTUP_EN_EN_MASK 0x80
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_SYNTH_CAL_OPERATION_EN_MASK 0x0100
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_SYNTH_CAL_OPERATION_EN_POS 8
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_SYNTH_CAL_OPERATION_EN_DIS 0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_SYNTH_CAL_OPERATION_EN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_SYNTH_CAL_OPERATION_EN_EN 1
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_SYNTH_CAL_OPERATION_EN_EN_MASK 0x100
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mra2_mode_ctrl_en : 1;
- unsigned int pll_phase_skip_en : 1;
- unsigned int trx_powerup_en : 1;
- unsigned int trx_powerdown_en : 1;
- unsigned int global_powerdown_en : 1;
- unsigned int kmod_band_cal_en : 1;
- unsigned int kmod_chan_cal_en : 1;
- unsigned int synth_cal_startup_en : 1;
- unsigned int synth_cal_operation_en : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_mode_ctrl_2;
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_RST 0x1d
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_2_ADDR 0x4001d804
-
-
-/* mode_ctrl_3 register */
-/*----------------------*/
-/* Operation mode control register. Cannot be written without reference clock: any next write will hang. */
-/* p_wanted : TBD */
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_3_P_WANTED_MASK 0x00ff
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_3_P_WANTED_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int p_wanted : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_mode_ctrl_3;
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_3_RST 0x0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_3_ADDR 0x4001d808
-
-
-/* mode_ctrl_src register */
-/*----------------------*/
-/* Mode control source register */
-/* tx_notrx_src : Selects the tx_norx source */
-/* ble_mode_src : Selects the ble_mode source */
-/* p_wanted_src : Selects the p_wanted source */
-/* tx_order_src : Selects the tx_order source */
-/* rx_order_src : Selects the rx_order source */
-/* rf_carrier_freq_int_src : Selects the rf_carrier_freq_int source */
-/* rf_carrier_freq_frac_src : Selects the rf_carrier_freq_frac source */
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_TX_NOTRX_SRC_MASK 0x0003
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_TX_NOTRX_SRC_POS 0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_TX_NOTRX_SRC_PRE_START_SRC 0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_TX_NOTRX_SRC_PRE_START_SRC_MASK 0x0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_TX_NOTRX_SRC_REGFILE 1
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_TX_NOTRX_SRC_REGFILE_MASK 0x1
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_TX_NOTRX_SRC_LINKLAYER 2
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_TX_NOTRX_SRC_LINKLAYER_MASK 0x2
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_BLE_MODE_SRC_MASK 0x0004
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_BLE_MODE_SRC_POS 2
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_BLE_MODE_SRC_PRE_START_SRC 0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_BLE_MODE_SRC_PRE_START_SRC_MASK 0x0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_BLE_MODE_SRC_REGFILE 1
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_BLE_MODE_SRC_REGFILE_MASK 0x4
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_P_WANTED_SRC_MASK 0x0018
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_P_WANTED_SRC_POS 3
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_P_WANTED_SRC_PRE_START_SRC 0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_P_WANTED_SRC_PRE_START_SRC_MASK 0x0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_P_WANTED_SRC_REGFILE 1
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_P_WANTED_SRC_REGFILE_MASK 0x8
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_P_WANTED_SRC_LINKLAYER 2
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_P_WANTED_SRC_LINKLAYER_MASK 0x10
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_TX_ORDER_SRC_MASK 0x0060
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_TX_ORDER_SRC_POS 5
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_TX_ORDER_SRC_PRE_START_SRC 0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_TX_ORDER_SRC_PRE_START_SRC_MASK 0x0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_TX_ORDER_SRC_REGFILE 1
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_TX_ORDER_SRC_REGFILE_MASK 0x20
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_TX_ORDER_SRC_LINKLAYER 2
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_TX_ORDER_SRC_LINKLAYER_MASK 0x40
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_RX_ORDER_SRC_MASK 0x0180
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_RX_ORDER_SRC_POS 7
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_RX_ORDER_SRC_PRE_START_SRC 0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_RX_ORDER_SRC_PRE_START_SRC_MASK 0x0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_RX_ORDER_SRC_REGFILE 1
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_RX_ORDER_SRC_REGFILE_MASK 0x80
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_RX_ORDER_SRC_LINKLAYER 2
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_RX_ORDER_SRC_LINKLAYER_MASK 0x100
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_RF_CARRIER_FREQ_INT_SRC_MASK 0x0600
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_RF_CARRIER_FREQ_INT_SRC_POS 9
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_RF_CARRIER_FREQ_INT_SRC_PRE_START_SRC 0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_RF_CARRIER_FREQ_INT_SRC_PRE_START_SRC_MASK 0x0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_RF_CARRIER_FREQ_INT_SRC_REGFILE 1
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_RF_CARRIER_FREQ_INT_SRC_REGFILE_MASK 0x200
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_RF_CARRIER_FREQ_INT_SRC_LINKLAYER 2
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_RF_CARRIER_FREQ_INT_SRC_LINKLAYER_MASK 0x400
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_RF_CARRIER_FREQ_FRAC_SRC_MASK 0x1800
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_RF_CARRIER_FREQ_FRAC_SRC_POS 11
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_RF_CARRIER_FREQ_FRAC_SRC_PRE_START_SRC 0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_RF_CARRIER_FREQ_FRAC_SRC_PRE_START_SRC_MASK 0x0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_RF_CARRIER_FREQ_FRAC_SRC_REGFILE 1
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_RF_CARRIER_FREQ_FRAC_SRC_REGFILE_MASK 0x800
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_RF_CARRIER_FREQ_FRAC_SRC_LINKLAYER 2
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_RF_CARRIER_FREQ_FRAC_SRC_LINKLAYER_MASK 0x1000
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int tx_notrx_src : 2;
- unsigned int ble_mode_src : 1;
- unsigned int p_wanted_src : 2;
- unsigned int tx_order_src : 2;
- unsigned int rx_order_src : 2;
- unsigned int rf_carrier_freq_int_src : 2;
- unsigned int rf_carrier_freq_frac_src : 2;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_mode_ctrl_src;
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_RST 0xa0
-#define EXTAPB_REGFILE_TMU_MODE_CTRL_SRC_ADDR 0x4001d80c
-
-
-/* pre_tx register */
-/*----------------------*/
-/* TX startup time register */
-/* cnt : TX startup time: time in baseband clock cycles between rising edge of START (TX analog modules enable) and TX datapath enable */
-#define EXTAPB_REGFILE_TMU_PRE_TX_CNT_MASK 0x00ff
-#define EXTAPB_REGFILE_TMU_PRE_TX_CNT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int cnt : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_pre_tx;
-#define EXTAPB_REGFILE_TMU_PRE_TX_RST 0x0
-#define EXTAPB_REGFILE_TMU_PRE_TX_ADDR 0x4001d810
-
-
-/* post_tx register */
-/*----------------------*/
-/* TX closing time register */
-/* cnt : TX closing time: time in baseband clock cycles between TX datapath finished (EOP) and TX analog modules disable. Smallest value allowed is 3. */
-#define EXTAPB_REGFILE_TMU_POST_TX_CNT_MASK 0x00ff
-#define EXTAPB_REGFILE_TMU_POST_TX_CNT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int cnt : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_post_tx;
-#define EXTAPB_REGFILE_TMU_POST_TX_RST 0x5
-#define EXTAPB_REGFILE_TMU_POST_TX_ADDR 0x4001d814
-
-
-/* pre_rx register */
-/*----------------------*/
-/* RX startup time register */
-/* cnt : RX startup time: time in baseband clock cycles between rising edge of START (RX analog modules enable) and RX datapath enable */
-#define EXTAPB_REGFILE_TMU_PRE_RX_CNT_MASK 0x00ff
-#define EXTAPB_REGFILE_TMU_PRE_RX_CNT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int cnt : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_pre_rx;
-#define EXTAPB_REGFILE_TMU_PRE_RX_RST 0x0
-#define EXTAPB_REGFILE_TMU_PRE_RX_ADDR 0x4001d818
-
-
-/* post_rx register */
-/*----------------------*/
-/* RX closing time register */
-/* cnt : RX closing time: time in baseband clock cycles between RX datapath finished (EOP) and RX analog modules disable */
-#define EXTAPB_REGFILE_TMU_POST_RX_CNT_MASK 0x00ff
-#define EXTAPB_REGFILE_TMU_POST_RX_CNT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int cnt : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_post_rx;
-#define EXTAPB_REGFILE_TMU_POST_RX_RST 0x0
-#define EXTAPB_REGFILE_TMU_POST_RX_ADDR 0x4001d81c
-
-
-/* status register */
-/*----------------------*/
-/* RX and TX Status. (Snapshot register) */
-/* tx_state : */
-/* rx_state : */
-/* tx_ready : */
-/* rx_ready : */
-#define EXTAPB_REGFILE_TMU_STATUS_TX_STATE_MASK 0x000f
-#define EXTAPB_REGFILE_TMU_STATUS_TX_STATE_POS 0
-#define EXTAPB_REGFILE_TMU_STATUS_RX_STATE_MASK 0x00f0
-#define EXTAPB_REGFILE_TMU_STATUS_RX_STATE_POS 4
-#define EXTAPB_REGFILE_TMU_STATUS_TX_READY_MASK 0x0100
-#define EXTAPB_REGFILE_TMU_STATUS_TX_READY_POS 8
-#define EXTAPB_REGFILE_TMU_STATUS_RX_READY_MASK 0x0200
-#define EXTAPB_REGFILE_TMU_STATUS_RX_READY_POS 9
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int tx_state : 4;
- unsigned int rx_state : 4;
- unsigned int tx_ready : 1;
- unsigned int rx_ready : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_status;
-#define EXTAPB_REGFILE_TMU_STATUS_RST 0x0
-#define EXTAPB_REGFILE_TMU_STATUS_DYNAMIC true
-#define EXTAPB_REGFILE_TMU_STATUS_SNAPCLOCK 0
-#define EXTAPB_REGFILE_TMU_STATUS_ADDR 0x4001d820
-
-
-/* cal_status register */
-/*----------------------*/
-/* Calibration status. (Snapshot register) */
-/* cal_state : */
-#define EXTAPB_REGFILE_TMU_CAL_STATUS_CAL_STATE_MASK 0xffff
-#define EXTAPB_REGFILE_TMU_CAL_STATUS_CAL_STATE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int cal_state : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_cal_status;
-#define EXTAPB_REGFILE_TMU_CAL_STATUS_RST 0x0
-#define EXTAPB_REGFILE_TMU_CAL_STATUS_DYNAMIC true
-#define EXTAPB_REGFILE_TMU_CAL_STATUS_SNAPCLOCK 0
-#define EXTAPB_REGFILE_TMU_CAL_STATUS_ADDR 0x4001d824
-
-
-/* cal_status1 register */
-/*----------------------*/
-/* Calibration status (part2) (Snapshot register) */
-/* cal_state : */
-#define EXTAPB_REGFILE_TMU_CAL_STATUS1_CAL_STATE_MASK 0xffff
-#define EXTAPB_REGFILE_TMU_CAL_STATUS1_CAL_STATE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int cal_state : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_cal_status1;
-#define EXTAPB_REGFILE_TMU_CAL_STATUS1_RST 0x0
-#define EXTAPB_REGFILE_TMU_CAL_STATUS1_DYNAMIC true
-#define EXTAPB_REGFILE_TMU_CAL_STATUS1_SNAPCLOCK 0
-#define EXTAPB_REGFILE_TMU_CAL_STATUS1_ADDR 0x4001d828
-
-
-/* cal_status2 register */
-/*----------------------*/
-/* Calibration status (part3) (Snapshot register) */
-/* cal_state : */
-#define EXTAPB_REGFILE_TMU_CAL_STATUS2_CAL_STATE_MASK 0xffff
-#define EXTAPB_REGFILE_TMU_CAL_STATUS2_CAL_STATE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int cal_state : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_cal_status2;
-#define EXTAPB_REGFILE_TMU_CAL_STATUS2_RST 0x0
-#define EXTAPB_REGFILE_TMU_CAL_STATUS2_DYNAMIC true
-#define EXTAPB_REGFILE_TMU_CAL_STATUS2_SNAPCLOCK 0
-#define EXTAPB_REGFILE_TMU_CAL_STATUS2_ADDR 0x4001d82c
-
-
-/* global_status register */
-/*----------------------*/
-/* Global TMU status. (Snapshot register) */
-/* global_state : */
-#define EXTAPB_REGFILE_TMU_GLOBAL_STATUS_GLOBAL_STATE_MASK 0x03ff
-#define EXTAPB_REGFILE_TMU_GLOBAL_STATUS_GLOBAL_STATE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int global_state : 10;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_global_status;
-#define EXTAPB_REGFILE_TMU_GLOBAL_STATUS_RST 0x0
-#define EXTAPB_REGFILE_TMU_GLOBAL_STATUS_DYNAMIC true
-#define EXTAPB_REGFILE_TMU_GLOBAL_STATUS_SNAPCLOCK 0
-#define EXTAPB_REGFILE_TMU_GLOBAL_STATUS_ADDR 0x4001d830
-
-
-/* clk_override register */
-/*----------------------*/
-/* Snap/Snack will hang if a clock is missing. This register allows to enable the clock for specific clock domains. */
-/* ref_clk : The register value is OR-ed with op_tx_tmu_ref_clk_en */
-/* rx_bb_clk : The register value is OR-ed with op_rx_tmu_bb_clk_en */
-#define EXTAPB_REGFILE_TMU_CLK_OVERRIDE_REF_CLK_MASK 0x0001
-#define EXTAPB_REGFILE_TMU_CLK_OVERRIDE_REF_CLK_POS 0
-#define EXTAPB_REGFILE_TMU_CLK_OVERRIDE_RX_BB_CLK_MASK 0x0002
-#define EXTAPB_REGFILE_TMU_CLK_OVERRIDE_RX_BB_CLK_POS 1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int ref_clk : 1;
- unsigned int rx_bb_clk : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_clk_override;
-#define EXTAPB_REGFILE_TMU_CLK_OVERRIDE_RST 0x0
-#define EXTAPB_REGFILE_TMU_CLK_OVERRIDE_ADDR 0x4001d834
-
-
-/* rx_sync_found_timeout register */
-/*----------------------*/
-/* Rx sync period before timeout */
-/* cnt : RX sync period before timeout. Zero means unlimited sync period (so no synchronization timeout). */
-#define EXTAPB_REGFILE_TMU_RX_SYNC_FOUND_TIMEOUT_CNT_MASK 0xffff
-#define EXTAPB_REGFILE_TMU_RX_SYNC_FOUND_TIMEOUT_CNT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int cnt : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_rx_sync_found_timeout;
-#define EXTAPB_REGFILE_TMU_RX_SYNC_FOUND_TIMEOUT_RST 0x0
-#define EXTAPB_REGFILE_TMU_RX_SYNC_FOUND_TIMEOUT_ADDR 0x4001d838
-
-
-/* rfp_tmu_intstat register */
-/*----------------------*/
-/* RFP TMU Interrupt status */
-/* rx_sync_found : Rx Sync found detected */
-/* rx_sync_found_timeout : Rx Sync found timeout detected */
-/* tx_eop : Tx EOP detected */
-/* pll_not_locked_rx : PLL not locked when entering RX. Measurement moment : assertion of RX3 */
-/* pll_not_locked_tx : PLL not locked when entering TX. Measurement moment : assertion of TX3 (in front of PA rampup) */
-/* pll_not_locked_pa_cal : PLL not locked at the end of PA_delay1 stage of PA calibration */
-/* pll_state_start : Asserted when entering PLL state */
-/* rx_state_start : Asserted when entering RX state */
-/* rx_state_end : Asserted when leaving RX state */
-/* tx_state_start : Asserted when entering TX state */
-/* tx_state_end : Asserted when leaving TX state */
-/* zb_lost : If set ZB MAC lost modem when it was active */
-/* zb_denied : If set ZB MAC attempted to use radio but was blocked due to higher priority BLE */
-/* ble_lost : If set BLE link layer lost modem when it was active */
-/* ble_denied : If set BLE link layer attempted to use radio but was blocked due to higher priority ZB */
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_RX_SYNC_FOUND_MASK 0x0001
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_RX_SYNC_FOUND_POS 0
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_RX_SYNC_FOUND_TIMEOUT_MASK 0x0002
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_RX_SYNC_FOUND_TIMEOUT_POS 1
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_TX_EOP_MASK 0x0004
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_TX_EOP_POS 2
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_PLL_NOT_LOCKED_RX_MASK 0x0008
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_PLL_NOT_LOCKED_RX_POS 3
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_PLL_NOT_LOCKED_TX_MASK 0x0010
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_PLL_NOT_LOCKED_TX_POS 4
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_PLL_NOT_LOCKED_PA_CAL_MASK 0x0020
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_PLL_NOT_LOCKED_PA_CAL_POS 5
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_PLL_STATE_START_MASK 0x0040
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_PLL_STATE_START_POS 6
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_RX_STATE_START_MASK 0x0080
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_RX_STATE_START_POS 7
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_RX_STATE_END_MASK 0x0100
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_RX_STATE_END_POS 8
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_TX_STATE_START_MASK 0x0200
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_TX_STATE_START_POS 9
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_TX_STATE_END_MASK 0x0400
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_TX_STATE_END_POS 10
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_ZB_LOST_MASK 0x0800
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_ZB_LOST_POS 11
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_ZB_DENIED_MASK 0x1000
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_ZB_DENIED_POS 12
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_BLE_LOST_MASK 0x2000
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_BLE_LOST_POS 13
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_BLE_DENIED_MASK 0x4000
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_BLE_DENIED_POS 14
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_sync_found : 1;
- unsigned int rx_sync_found_timeout : 1;
- unsigned int tx_eop : 1;
- unsigned int pll_not_locked_rx : 1;
- unsigned int pll_not_locked_tx : 1;
- unsigned int pll_not_locked_pa_cal : 1;
- unsigned int pll_state_start : 1;
- unsigned int rx_state_start : 1;
- unsigned int rx_state_end : 1;
- unsigned int tx_state_start : 1;
- unsigned int tx_state_end : 1;
- unsigned int zb_lost : 1;
- unsigned int zb_denied : 1;
- unsigned int ble_lost : 1;
- unsigned int ble_denied : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_rfp_tmu_intstat;
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_RST 0x0
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSTAT_ADDR 0x4001d83c
-
-
-/* rfp_tmu_intsetstat register */
-/*----------------------*/
-/* RFP TMU Interrupt Set. Cannot be written without RX reference clock. Any next write will hang */
-/* rx_sync_found : Set event for rx_sync_found */
-/* rx_sync_found_timeout : Set event for rx_sync_found_timeout */
-/* tx_eop : Set event for tx_eop */
-/* pll_not_locked_rx : Set event for pll_not_locked_rx */
-/* pll_not_locked_tx : Set event for pll_not_locked_tx */
-/* pll_not_locked_pa_cal : Set event for pll_not_locked_pa_cal */
-/* pll_state_start : Set event for pll_state_start */
-/* rx_state_start : Set event for rx_state_start */
-/* rx_state_end : Set event for rx_state_end */
-/* tx_state_start : Set event for tx_state_start */
-/* tx_state_end : Set event for tx_state_end */
-/* zb_lost : Set event for zb_lost */
-/* zb_denied : Set event for zb_denied */
-/* ble_lost : Set event for ble_lost */
-/* ble_denied : Set event for ble_denied */
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_RX_SYNC_FOUND_MASK 0x0001
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_RX_SYNC_FOUND_POS 0
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_RX_SYNC_FOUND_TIMEOUT_MASK 0x0002
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_RX_SYNC_FOUND_TIMEOUT_POS 1
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_TX_EOP_MASK 0x0004
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_TX_EOP_POS 2
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_PLL_NOT_LOCKED_RX_MASK 0x0008
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_PLL_NOT_LOCKED_RX_POS 3
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_PLL_NOT_LOCKED_TX_MASK 0x0010
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_PLL_NOT_LOCKED_TX_POS 4
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_PLL_NOT_LOCKED_PA_CAL_MASK 0x0020
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_PLL_NOT_LOCKED_PA_CAL_POS 5
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_PLL_STATE_START_MASK 0x0040
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_PLL_STATE_START_POS 6
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_RX_STATE_START_MASK 0x0080
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_RX_STATE_START_POS 7
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_RX_STATE_END_MASK 0x0100
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_RX_STATE_END_POS 8
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_TX_STATE_START_MASK 0x0200
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_TX_STATE_START_POS 9
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_TX_STATE_END_MASK 0x0400
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_TX_STATE_END_POS 10
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_ZB_LOST_MASK 0x0800
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_ZB_LOST_POS 11
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_ZB_DENIED_MASK 0x1000
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_ZB_DENIED_POS 12
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_BLE_LOST_MASK 0x2000
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_BLE_LOST_POS 13
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_BLE_DENIED_MASK 0x4000
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_BLE_DENIED_POS 14
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_sync_found : 1;
- unsigned int rx_sync_found_timeout : 1;
- unsigned int tx_eop : 1;
- unsigned int pll_not_locked_rx : 1;
- unsigned int pll_not_locked_tx : 1;
- unsigned int pll_not_locked_pa_cal : 1;
- unsigned int pll_state_start : 1;
- unsigned int rx_state_start : 1;
- unsigned int rx_state_end : 1;
- unsigned int tx_state_start : 1;
- unsigned int tx_state_end : 1;
- unsigned int zb_lost : 1;
- unsigned int zb_denied : 1;
- unsigned int ble_lost : 1;
- unsigned int ble_denied : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_rfp_tmu_intsetstat;
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_RST 0x0
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTSETSTAT_ADDR 0x4001d840
-
-
-/* rfp_tmu_intclrstat register */
-/*----------------------*/
-/* RFP TMU Interrupt clear. Cannot be written without RX reference clock. Any next write will hang */
-/* rx_sync_found : Clear event for rx_sync_found */
-/* rx_sync_found_timeout : Clear event for rx_sync_found_timeout */
-/* tx_eop : Clear event for tx_eop */
-/* pll_not_locked_rx : Clear event for pll_not_locked_rx */
-/* pll_not_locked_tx : Clear event for pll_not_locked_tx */
-/* pll_not_locked_pa_cal : Clear event for pll_not_locked_pa_cal */
-/* pll_state_start : Clear event for pll_state_start */
-/* rx_state_start : Clear event for rx_state_start */
-/* rx_state_end : Clear event for rx_state_end */
-/* tx_state_start : Clear event for tx_state_start */
-/* tx_state_end : Clear event for tx_state_end */
-/* zb_lost : Clear event for zb_lost */
-/* zb_denied : Clear event for zb_denied */
-/* ble_lost : Clear event for ble_lost */
-/* ble_denied : Clear event for ble_denied */
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_RX_SYNC_FOUND_MASK 0x0001
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_RX_SYNC_FOUND_POS 0
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_RX_SYNC_FOUND_TIMEOUT_MASK 0x0002
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_RX_SYNC_FOUND_TIMEOUT_POS 1
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_TX_EOP_MASK 0x0004
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_TX_EOP_POS 2
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_PLL_NOT_LOCKED_RX_MASK 0x0008
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_PLL_NOT_LOCKED_RX_POS 3
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_PLL_NOT_LOCKED_TX_MASK 0x0010
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_PLL_NOT_LOCKED_TX_POS 4
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_PLL_NOT_LOCKED_PA_CAL_MASK 0x0020
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_PLL_NOT_LOCKED_PA_CAL_POS 5
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_PLL_STATE_START_MASK 0x0040
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_PLL_STATE_START_POS 6
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_RX_STATE_START_MASK 0x0080
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_RX_STATE_START_POS 7
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_RX_STATE_END_MASK 0x0100
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_RX_STATE_END_POS 8
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_TX_STATE_START_MASK 0x0200
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_TX_STATE_START_POS 9
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_TX_STATE_END_MASK 0x0400
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_TX_STATE_END_POS 10
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_ZB_LOST_MASK 0x0800
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_ZB_LOST_POS 11
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_ZB_DENIED_MASK 0x1000
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_ZB_DENIED_POS 12
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_BLE_LOST_MASK 0x2000
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_BLE_LOST_POS 13
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_BLE_DENIED_MASK 0x4000
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_BLE_DENIED_POS 14
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_sync_found : 1;
- unsigned int rx_sync_found_timeout : 1;
- unsigned int tx_eop : 1;
- unsigned int pll_not_locked_rx : 1;
- unsigned int pll_not_locked_tx : 1;
- unsigned int pll_not_locked_pa_cal : 1;
- unsigned int pll_state_start : 1;
- unsigned int rx_state_start : 1;
- unsigned int rx_state_end : 1;
- unsigned int tx_state_start : 1;
- unsigned int tx_state_end : 1;
- unsigned int zb_lost : 1;
- unsigned int zb_denied : 1;
- unsigned int ble_lost : 1;
- unsigned int ble_denied : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_rfp_tmu_intclrstat;
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_RST 0x0
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTCLRSTAT_ADDR 0x4001d844
-
-
-/* rfp_tmu_inten register */
-/*----------------------*/
-/* RFP TMU Interrupt enable */
-/* rx_sync_found : Interrupt enable for rx_sync_found */
-/* rx_sync_found_timeout : Interrupt enable for rx_sync_found_timeout */
-/* tx_eop : Interrupt enable for tx_eop */
-/* pll_not_locked_rx : Interrupt enable for pll_not_locked_rx */
-/* pll_not_locked_tx : Interrupt enable for pll_not_locked_tx */
-/* pll_not_locked_pa_cal : Interrupt enable for pll_not_locked_pa_cal */
-/* pll_state_start : Interrupt enable for pll_state_start */
-/* rx_state_start : Interrupt enable for rx_state_start */
-/* rx_state_end : Interrupt enable for rx_state_end */
-/* tx_state_start : Interrupt enable for tx_state_start */
-/* tx_state_end : Interrupt enable for tx_state_end */
-/* zb_lost : Interrupt enable for zb_lost */
-/* zb_denied : Interrupt enable for zb_denied */
-/* ble_lost : Interrupt enable for ble_lost */
-/* ble_denied : Interrupt enable for ble_denied */
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_RX_SYNC_FOUND_MASK 0x0001
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_RX_SYNC_FOUND_POS 0
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_RX_SYNC_FOUND_TIMEOUT_MASK 0x0002
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_RX_SYNC_FOUND_TIMEOUT_POS 1
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_TX_EOP_MASK 0x0004
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_TX_EOP_POS 2
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_PLL_NOT_LOCKED_RX_MASK 0x0008
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_PLL_NOT_LOCKED_RX_POS 3
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_PLL_NOT_LOCKED_TX_MASK 0x0010
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_PLL_NOT_LOCKED_TX_POS 4
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_PLL_NOT_LOCKED_PA_CAL_MASK 0x0020
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_PLL_NOT_LOCKED_PA_CAL_POS 5
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_PLL_STATE_START_MASK 0x0040
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_PLL_STATE_START_POS 6
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_RX_STATE_START_MASK 0x0080
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_RX_STATE_START_POS 7
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_RX_STATE_END_MASK 0x0100
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_RX_STATE_END_POS 8
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_TX_STATE_START_MASK 0x0200
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_TX_STATE_START_POS 9
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_TX_STATE_END_MASK 0x0400
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_TX_STATE_END_POS 10
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_ZB_LOST_MASK 0x0800
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_ZB_LOST_POS 11
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_ZB_DENIED_MASK 0x1000
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_ZB_DENIED_POS 12
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_BLE_LOST_MASK 0x2000
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_BLE_LOST_POS 13
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_BLE_DENIED_MASK 0x4000
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_BLE_DENIED_POS 14
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rx_sync_found : 1;
- unsigned int rx_sync_found_timeout : 1;
- unsigned int tx_eop : 1;
- unsigned int pll_not_locked_rx : 1;
- unsigned int pll_not_locked_tx : 1;
- unsigned int pll_not_locked_pa_cal : 1;
- unsigned int pll_state_start : 1;
- unsigned int rx_state_start : 1;
- unsigned int rx_state_end : 1;
- unsigned int tx_state_start : 1;
- unsigned int tx_state_end : 1;
- unsigned int zb_lost : 1;
- unsigned int zb_denied : 1;
- unsigned int ble_lost : 1;
- unsigned int ble_denied : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_rfp_tmu_inten;
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_RST 0x0
-#define EXTAPB_REGFILE_TMU_RFP_TMU_INTEN_ADDR 0x4001d848
-
-
-/* rfp_tmu_power_intstat register */
-/*----------------------*/
-/* RFP TMU Power Interrupt status */
-/* power_up_tx_end : Asserted when TX power up is finished */
-/* power_up_rx_end : Asserted when RX power up is finished */
-/* power_down_tx_end : Asserted when TX power down is finished */
-/* power_down_rx_end : Asserted when RX power down is finished */
-/* power_down_end : Asserted when global power down is finished */
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTSTAT_POWER_UP_TX_END_MASK 0x0001
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTSTAT_POWER_UP_TX_END_POS 0
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTSTAT_POWER_UP_RX_END_MASK 0x0002
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTSTAT_POWER_UP_RX_END_POS 1
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTSTAT_POWER_DOWN_TX_END_MASK 0x0004
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTSTAT_POWER_DOWN_TX_END_POS 2
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTSTAT_POWER_DOWN_RX_END_MASK 0x0008
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTSTAT_POWER_DOWN_RX_END_POS 3
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTSTAT_POWER_DOWN_END_MASK 0x0010
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTSTAT_POWER_DOWN_END_POS 4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int power_up_tx_end : 1;
- unsigned int power_up_rx_end : 1;
- unsigned int power_down_tx_end : 1;
- unsigned int power_down_rx_end : 1;
- unsigned int power_down_end : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_rfp_tmu_power_intstat;
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTSTAT_RST 0x0
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTSTAT_ADDR 0x4001d84c
-
-
-/* rfp_tmu_power_intsetstat register */
-/*----------------------*/
-/* RFP TMU Power Interrupt Set. Cannot be written without RX reference clock. Any next write will hang */
-/* power_up_tx_end : Set event for power_up_tx_end */
-/* power_up_rx_end : Set event for power_up_rx_end */
-/* power_down_tx_end : Set event for power_down_tx_end */
-/* power_down_rx_end : Set event for power_down_rx_end */
-/* power_down_end : Set event for power_down_end */
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTSETSTAT_POWER_UP_TX_END_MASK 0x0001
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTSETSTAT_POWER_UP_TX_END_POS 0
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTSETSTAT_POWER_UP_RX_END_MASK 0x0002
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTSETSTAT_POWER_UP_RX_END_POS 1
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTSETSTAT_POWER_DOWN_TX_END_MASK 0x0004
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTSETSTAT_POWER_DOWN_TX_END_POS 2
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTSETSTAT_POWER_DOWN_RX_END_MASK 0x0008
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTSETSTAT_POWER_DOWN_RX_END_POS 3
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTSETSTAT_POWER_DOWN_END_MASK 0x0010
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTSETSTAT_POWER_DOWN_END_POS 4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int power_up_tx_end : 1;
- unsigned int power_up_rx_end : 1;
- unsigned int power_down_tx_end : 1;
- unsigned int power_down_rx_end : 1;
- unsigned int power_down_end : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_rfp_tmu_power_intsetstat;
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTSETSTAT_RST 0x0
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTSETSTAT_ADDR 0x4001d850
-
-
-/* rfp_tmu_power_intclrstat register */
-/*----------------------*/
-/* RFP TMU Power Interrupt Clear. Cannot be written without RX reference clock. Any next write will hang */
-/* power_up_tx_end : Clear event for power_up_tx_end */
-/* power_up_rx_end : Clear event for power_up_rx_end */
-/* power_down_tx_end : Clear event for power_down_tx_end */
-/* power_down_rx_end : Clear event for power_down_rx_end */
-/* power_down_end : Clear event for power_down_end */
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTCLRSTAT_POWER_UP_TX_END_MASK 0x0001
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTCLRSTAT_POWER_UP_TX_END_POS 0
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTCLRSTAT_POWER_UP_RX_END_MASK 0x0002
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTCLRSTAT_POWER_UP_RX_END_POS 1
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTCLRSTAT_POWER_DOWN_TX_END_MASK 0x0004
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTCLRSTAT_POWER_DOWN_TX_END_POS 2
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTCLRSTAT_POWER_DOWN_RX_END_MASK 0x0008
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTCLRSTAT_POWER_DOWN_RX_END_POS 3
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTCLRSTAT_POWER_DOWN_END_MASK 0x0010
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTCLRSTAT_POWER_DOWN_END_POS 4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int power_up_tx_end : 1;
- unsigned int power_up_rx_end : 1;
- unsigned int power_down_tx_end : 1;
- unsigned int power_down_rx_end : 1;
- unsigned int power_down_end : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_rfp_tmu_power_intclrstat;
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTCLRSTAT_RST 0x0
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTCLRSTAT_ADDR 0x4001d854
-
-
-/* rfp_tmu_power_inten register */
-/*----------------------*/
-/* RFP TMU Power Interrupt enable. */
-/* power_up_tx_end : Interrupt enable for power_up_tx_end */
-/* power_up_rx_end : Interrupt enable for power_up_rx_end */
-/* power_down_tx_end : Interrupt enable for power_down_tx_end */
-/* power_down_rx_end : Interrupt enable for power_down_rx_end */
-/* power_down_end : Interrrupt enable for power_down_end */
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTEN_POWER_UP_TX_END_MASK 0x0001
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTEN_POWER_UP_TX_END_POS 0
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTEN_POWER_UP_RX_END_MASK 0x0002
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTEN_POWER_UP_RX_END_POS 1
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTEN_POWER_DOWN_TX_END_MASK 0x0004
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTEN_POWER_DOWN_TX_END_POS 2
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTEN_POWER_DOWN_RX_END_MASK 0x0008
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTEN_POWER_DOWN_RX_END_POS 3
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTEN_POWER_DOWN_END_MASK 0x0010
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTEN_POWER_DOWN_END_POS 4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int power_up_tx_end : 1;
- unsigned int power_up_rx_end : 1;
- unsigned int power_down_tx_end : 1;
- unsigned int power_down_rx_end : 1;
- unsigned int power_down_end : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_rfp_tmu_power_inten;
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTEN_RST 0x0
-#define EXTAPB_REGFILE_TMU_RFP_TMU_POWER_INTEN_ADDR 0x4001d858
-
-
-/* rfp_tmu_cal_intstat register */
-/*----------------------*/
-/* RFP TMU Calibration Interrupt status */
-/* dco_cal_done : Asserted when DC Offset calibration is finished */
-/* iq_cal_done : Asserted when IQ mismatch calibration is finished */
-/* r_cal_done : Asserted when R Calibration is finished */
-/* rc_cal_done : Asserted when RC Calibration is finished */
-/* kmod_band_cal_done : Asserted when Kmod band calibration is finished */
-/* kmod_chan_cal_done : Asserted when Kmod channel calibration is finished */
-/* vco_cal_aac_done : Asserted when VCO AAC calibration is finished */
-/* vco_cal_afc_done : Asserted when VCO AFC calibration is finished */
-/* vco_cal_det_done : Asserted when VCO DET calibration is finished */
-/* pa_cal_done : Asserted when PA calibration is finished. */
-/* synth_cal_startup_done : Asserted when Synthesizer calibration for startup is finished */
-/* synth_cal_operation_done : Asserted when Synthesizer calibration for operation is finished */
-/* rf_bgp_cal_done : Asserted when RF bandgap calibration is finished */
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSTAT_DCO_CAL_DONE_MASK 0x0001
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSTAT_DCO_CAL_DONE_POS 0
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSTAT_IQ_CAL_DONE_MASK 0x0002
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSTAT_IQ_CAL_DONE_POS 1
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSTAT_R_CAL_DONE_MASK 0x0004
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSTAT_R_CAL_DONE_POS 2
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSTAT_RC_CAL_DONE_MASK 0x0008
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSTAT_RC_CAL_DONE_POS 3
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSTAT_KMOD_BAND_CAL_DONE_MASK 0x0010
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSTAT_KMOD_BAND_CAL_DONE_POS 4
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSTAT_KMOD_CHAN_CAL_DONE_MASK 0x0020
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSTAT_KMOD_CHAN_CAL_DONE_POS 5
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSTAT_VCO_CAL_AAC_DONE_MASK 0x0040
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSTAT_VCO_CAL_AAC_DONE_POS 6
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSTAT_VCO_CAL_AFC_DONE_MASK 0x0080
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSTAT_VCO_CAL_AFC_DONE_POS 7
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSTAT_VCO_CAL_DET_DONE_MASK 0x0100
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSTAT_VCO_CAL_DET_DONE_POS 8
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSTAT_PA_CAL_DONE_MASK 0x0200
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSTAT_PA_CAL_DONE_POS 9
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSTAT_SYNTH_CAL_STARTUP_DONE_MASK 0x0400
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSTAT_SYNTH_CAL_STARTUP_DONE_POS 10
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSTAT_SYNTH_CAL_OPERATION_DONE_MASK 0x0800
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSTAT_SYNTH_CAL_OPERATION_DONE_POS 11
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSTAT_RF_BGP_CAL_DONE_MASK 0x1000
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSTAT_RF_BGP_CAL_DONE_POS 12
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int dco_cal_done : 1;
- unsigned int iq_cal_done : 1;
- unsigned int r_cal_done : 1;
- unsigned int rc_cal_done : 1;
- unsigned int kmod_band_cal_done : 1;
- unsigned int kmod_chan_cal_done : 1;
- unsigned int vco_cal_aac_done : 1;
- unsigned int vco_cal_afc_done : 1;
- unsigned int vco_cal_det_done : 1;
- unsigned int pa_cal_done : 1;
- unsigned int synth_cal_startup_done : 1;
- unsigned int synth_cal_operation_done : 1;
- unsigned int rf_bgp_cal_done : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_rfp_tmu_cal_intstat;
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSTAT_RST 0x0
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSTAT_ADDR 0x4001d85c
-
-
-/* rfp_tmu_cal_intsetstat register */
-/*----------------------*/
-/* RFP TMU Calibration Interrupt Set. Cannot be written without RX reference clock. Any next write will hang */
-/* dco_cal_done : Set event for dco_cal_done */
-/* iq_cal_done : Set event for iq_cal_done */
-/* r_cal_done : Set event for r_cal_done */
-/* rc_cal_done : Set event for rc_cal_done */
-/* kmod_band_cal_done : Set event for kmod_band_cal_done */
-/* kmod_chan_cal_done : Set event for kmod_chan_cal_done */
-/* vco_cal_aac_done : Set event for vco_cal_aac_done */
-/* vco_cal_afc_done : Set event for vco_cal_afc_done */
-/* vco_cal_det_done : Set event for vco_cal_det_done */
-/* pa_cal_done : Set event for pa_cal_done */
-/* synth_cal_startup_done : Set event for synth_cal_startup_done */
-/* synth_cal_operation_done : Set event for synth_cal_operation_done */
-/* rf_bgp_cal_done : Set event for rf_bgp_cal_done */
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSETSTAT_DCO_CAL_DONE_MASK 0x0001
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSETSTAT_DCO_CAL_DONE_POS 0
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSETSTAT_IQ_CAL_DONE_MASK 0x0002
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSETSTAT_IQ_CAL_DONE_POS 1
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSETSTAT_R_CAL_DONE_MASK 0x0004
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSETSTAT_R_CAL_DONE_POS 2
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSETSTAT_RC_CAL_DONE_MASK 0x0008
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSETSTAT_RC_CAL_DONE_POS 3
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSETSTAT_KMOD_BAND_CAL_DONE_MASK 0x0010
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSETSTAT_KMOD_BAND_CAL_DONE_POS 4
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSETSTAT_KMOD_CHAN_CAL_DONE_MASK 0x0020
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSETSTAT_KMOD_CHAN_CAL_DONE_POS 5
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSETSTAT_VCO_CAL_AAC_DONE_MASK 0x0040
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSETSTAT_VCO_CAL_AAC_DONE_POS 6
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSETSTAT_VCO_CAL_AFC_DONE_MASK 0x0080
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSETSTAT_VCO_CAL_AFC_DONE_POS 7
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSETSTAT_VCO_CAL_DET_DONE_MASK 0x0100
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSETSTAT_VCO_CAL_DET_DONE_POS 8
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSETSTAT_PA_CAL_DONE_MASK 0x0200
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSETSTAT_PA_CAL_DONE_POS 9
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSETSTAT_SYNTH_CAL_STARTUP_DONE_MASK 0x0400
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSETSTAT_SYNTH_CAL_STARTUP_DONE_POS 10
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSETSTAT_SYNTH_CAL_OPERATION_DONE_MASK 0x0800
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSETSTAT_SYNTH_CAL_OPERATION_DONE_POS 11
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSETSTAT_RF_BGP_CAL_DONE_MASK 0x1000
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSETSTAT_RF_BGP_CAL_DONE_POS 12
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int dco_cal_done : 1;
- unsigned int iq_cal_done : 1;
- unsigned int r_cal_done : 1;
- unsigned int rc_cal_done : 1;
- unsigned int kmod_band_cal_done : 1;
- unsigned int kmod_chan_cal_done : 1;
- unsigned int vco_cal_aac_done : 1;
- unsigned int vco_cal_afc_done : 1;
- unsigned int vco_cal_det_done : 1;
- unsigned int pa_cal_done : 1;
- unsigned int synth_cal_startup_done : 1;
- unsigned int synth_cal_operation_done : 1;
- unsigned int rf_bgp_cal_done : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_rfp_tmu_cal_intsetstat;
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSETSTAT_RST 0x0
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTSETSTAT_ADDR 0x4001d860
-
-
-/* rfp_tmu_cal_intclrstat register */
-/*----------------------*/
-/* RFP TMU Calibration Interrupt clear. Cannot be written without RX reference clock. Any next write will hang */
-/* dco_cal_done : Clear event for dco_cal_done */
-/* iq_cal_done : Clear event for iq_cal_done */
-/* r_cal_done : Clear event for r_cal_done */
-/* rc_cal_done : Clear event for rc_cal_done */
-/* kmod_band_cal_done : Clear event for kmod_band_cal_done */
-/* kmod_chan_cal_done : Clear event for kmod_chan_cal_done */
-/* vco_cal_aac_done : Clear event for vco_cal_aac_done */
-/* vco_cal_afc_done : Clear event for vco_cal_afc_done */
-/* vco_cal_det_done : Clear event for vco_cal_det_done */
-/* pa_cal_done : Clear event for pa_cal_done */
-/* synth_cal_startup_done : Clear event for synth_cal_startup_done */
-/* synth_cal_operation_done : Clear event for synth_cal_operation_done */
-/* rf_bgp_cal_done : Clear event for rf_bgp_cal_done */
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTCLRSTAT_DCO_CAL_DONE_MASK 0x0001
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTCLRSTAT_DCO_CAL_DONE_POS 0
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTCLRSTAT_IQ_CAL_DONE_MASK 0x0002
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTCLRSTAT_IQ_CAL_DONE_POS 1
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTCLRSTAT_R_CAL_DONE_MASK 0x0004
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTCLRSTAT_R_CAL_DONE_POS 2
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTCLRSTAT_RC_CAL_DONE_MASK 0x0008
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTCLRSTAT_RC_CAL_DONE_POS 3
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTCLRSTAT_KMOD_BAND_CAL_DONE_MASK 0x0010
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTCLRSTAT_KMOD_BAND_CAL_DONE_POS 4
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTCLRSTAT_KMOD_CHAN_CAL_DONE_MASK 0x0020
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTCLRSTAT_KMOD_CHAN_CAL_DONE_POS 5
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTCLRSTAT_VCO_CAL_AAC_DONE_MASK 0x0040
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTCLRSTAT_VCO_CAL_AAC_DONE_POS 6
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTCLRSTAT_VCO_CAL_AFC_DONE_MASK 0x0080
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTCLRSTAT_VCO_CAL_AFC_DONE_POS 7
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTCLRSTAT_VCO_CAL_DET_DONE_MASK 0x0100
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTCLRSTAT_VCO_CAL_DET_DONE_POS 8
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTCLRSTAT_PA_CAL_DONE_MASK 0x0200
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTCLRSTAT_PA_CAL_DONE_POS 9
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTCLRSTAT_SYNTH_CAL_STARTUP_DONE_MASK 0x0400
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTCLRSTAT_SYNTH_CAL_STARTUP_DONE_POS 10
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTCLRSTAT_SYNTH_CAL_OPERATION_DONE_MASK 0x0800
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTCLRSTAT_SYNTH_CAL_OPERATION_DONE_POS 11
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTCLRSTAT_RF_BGP_CAL_DONE_MASK 0x1000
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTCLRSTAT_RF_BGP_CAL_DONE_POS 12
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int dco_cal_done : 1;
- unsigned int iq_cal_done : 1;
- unsigned int r_cal_done : 1;
- unsigned int rc_cal_done : 1;
- unsigned int kmod_band_cal_done : 1;
- unsigned int kmod_chan_cal_done : 1;
- unsigned int vco_cal_aac_done : 1;
- unsigned int vco_cal_afc_done : 1;
- unsigned int vco_cal_det_done : 1;
- unsigned int pa_cal_done : 1;
- unsigned int synth_cal_startup_done : 1;
- unsigned int synth_cal_operation_done : 1;
- unsigned int rf_bgp_cal_done : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_rfp_tmu_cal_intclrstat;
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTCLRSTAT_RST 0x0
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTCLRSTAT_ADDR 0x4001d864
-
-
-/* rfp_tmu_cal_inten register */
-/*----------------------*/
-/* RFP TMU Calibration Interrupt enable */
-/* dco_cal_done : Interrupt enable for dco_cal_done */
-/* iq_cal_done : Interrupt enable for iq_cal_done */
-/* r_cal_done : Interrupt enable for r_cal_done */
-/* rc_cal_done : Interrupt enable for rc_cal_done */
-/* kmod_band_cal_done : Interrupt enable for kmod_band_cal_done */
-/* kmod_chan_cal_done : Interrupt enable for kmod_chan_cal_done */
-/* vco_cal_aac_done : Interrupt enable for vco_cal_aac_done */
-/* vco_cal_afc_done : Interrupt enable for vco_cal_afc_done */
-/* vco_cal_det_done : Interrupt enable for vco_cal_det_done */
-/* pa_cal_done : Interrupt enable for pa_cal_done */
-/* synth_cal_startup_done : Interrupt enable for synth_cal_startup_done */
-/* synth_cal_operation_done : Interrupt enable for synth_cal_operation_done */
-/* rf_bgp_cal_done : Interrupt enable for rf_bgp_cal_done */
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTEN_DCO_CAL_DONE_MASK 0x0001
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTEN_DCO_CAL_DONE_POS 0
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTEN_IQ_CAL_DONE_MASK 0x0002
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTEN_IQ_CAL_DONE_POS 1
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTEN_R_CAL_DONE_MASK 0x0004
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTEN_R_CAL_DONE_POS 2
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTEN_RC_CAL_DONE_MASK 0x0008
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTEN_RC_CAL_DONE_POS 3
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTEN_KMOD_BAND_CAL_DONE_MASK 0x0010
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTEN_KMOD_BAND_CAL_DONE_POS 4
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTEN_KMOD_CHAN_CAL_DONE_MASK 0x0020
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTEN_KMOD_CHAN_CAL_DONE_POS 5
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTEN_VCO_CAL_AAC_DONE_MASK 0x0040
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTEN_VCO_CAL_AAC_DONE_POS 6
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTEN_VCO_CAL_AFC_DONE_MASK 0x0080
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTEN_VCO_CAL_AFC_DONE_POS 7
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTEN_VCO_CAL_DET_DONE_MASK 0x0100
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTEN_VCO_CAL_DET_DONE_POS 8
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTEN_PA_CAL_DONE_MASK 0x0200
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTEN_PA_CAL_DONE_POS 9
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTEN_SYNTH_CAL_STARTUP_DONE_MASK 0x0400
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTEN_SYNTH_CAL_STARTUP_DONE_POS 10
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTEN_SYNTH_CAL_OPERATION_DONE_MASK 0x0800
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTEN_SYNTH_CAL_OPERATION_DONE_POS 11
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTEN_RF_BGP_CAL_DONE_MASK 0x1000
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTEN_RF_BGP_CAL_DONE_POS 12
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int dco_cal_done : 1;
- unsigned int iq_cal_done : 1;
- unsigned int r_cal_done : 1;
- unsigned int rc_cal_done : 1;
- unsigned int kmod_band_cal_done : 1;
- unsigned int kmod_chan_cal_done : 1;
- unsigned int vco_cal_aac_done : 1;
- unsigned int vco_cal_afc_done : 1;
- unsigned int vco_cal_det_done : 1;
- unsigned int pa_cal_done : 1;
- unsigned int synth_cal_startup_done : 1;
- unsigned int synth_cal_operation_done : 1;
- unsigned int rf_bgp_cal_done : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_rfp_tmu_cal_inten;
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTEN_RST 0x0
-#define EXTAPB_REGFILE_TMU_RFP_TMU_CAL_INTEN_ADDR 0x4001d868
-
-
-/* triggers register */
-/*----------------------*/
-/* Triggers timing critical signals */
-/* pre_start : Register access to generate an equivalent rising edge of the phyon input signal. */
-/* packet_start : Register access to generate an equivalent rising edge of the packet_start input signal. */
-/* abort : Register access to generate an equivalent rising edge of the ABORT input signal. */
-/* power_down : Register access to trigger the power down sequence from the TMU. */
-/* power_up_tx : Register access to trigger the power up sequence of the grp_tx_sig_out signals */
-/* power_down_tx : Register access to trigger the power down sequence of the grp_tx_sig_out signals */
-/* power_up_rx : Register access to trigger the power up sequence of the grp_rx_sig_out signals */
-/* power_down_rx : Register access to trigger the power down sequence of the grp_rx_sig_out signals */
-/* packet_done : Register access to generate an equivalent falling edge of the phyon input signal. */
-/* pa_start : Register access to start the PA. */
-/* pa_end : Register access to end the PA. */
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PRE_START_MASK 0x0001
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PRE_START_POS 0
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PRE_START_EN 1
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PRE_START_EN_MASK 0x1
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PRE_START_DIS 0
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PRE_START_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PACKET_START_MASK 0x0002
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PACKET_START_POS 1
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PACKET_START_EN 1
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PACKET_START_EN_MASK 0x2
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PACKET_START_DIS 0
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PACKET_START_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TMU_TRIGGERS_ABORT_MASK 0x0004
-#define EXTAPB_REGFILE_TMU_TRIGGERS_ABORT_POS 2
-#define EXTAPB_REGFILE_TMU_TRIGGERS_ABORT_EN 1
-#define EXTAPB_REGFILE_TMU_TRIGGERS_ABORT_EN_MASK 0x4
-#define EXTAPB_REGFILE_TMU_TRIGGERS_ABORT_DIS 0
-#define EXTAPB_REGFILE_TMU_TRIGGERS_ABORT_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_DOWN_MASK 0x0008
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_DOWN_POS 3
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_DOWN_EN 1
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_DOWN_EN_MASK 0x8
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_DOWN_DIS 0
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_DOWN_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_UP_TX_MASK 0x0010
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_UP_TX_POS 4
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_UP_TX_EN 1
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_UP_TX_EN_MASK 0x10
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_UP_TX_DIS 0
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_UP_TX_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_DOWN_TX_MASK 0x0020
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_DOWN_TX_POS 5
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_DOWN_TX_EN 1
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_DOWN_TX_EN_MASK 0x20
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_DOWN_TX_DIS 0
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_DOWN_TX_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_UP_RX_MASK 0x0040
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_UP_RX_POS 6
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_UP_RX_EN 1
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_UP_RX_EN_MASK 0x40
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_UP_RX_DIS 0
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_UP_RX_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_DOWN_RX_MASK 0x0080
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_DOWN_RX_POS 7
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_DOWN_RX_EN 1
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_DOWN_RX_EN_MASK 0x80
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_DOWN_RX_DIS 0
-#define EXTAPB_REGFILE_TMU_TRIGGERS_POWER_DOWN_RX_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PACKET_DONE_MASK 0x0100
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PACKET_DONE_POS 8
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PACKET_DONE_EN 1
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PACKET_DONE_EN_MASK 0x100
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PACKET_DONE_DIS 0
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PACKET_DONE_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PA_START_MASK 0x0200
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PA_START_POS 9
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PA_START_EN 1
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PA_START_EN_MASK 0x200
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PA_START_DIS 0
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PA_START_DIS_MASK 0x0
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PA_END_MASK 0x0400
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PA_END_POS 10
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PA_END_EN 1
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PA_END_EN_MASK 0x400
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PA_END_DIS 0
-#define EXTAPB_REGFILE_TMU_TRIGGERS_PA_END_DIS_MASK 0x0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pre_start : 1;
- unsigned int packet_start : 1;
- unsigned int abort : 1;
- unsigned int power_down : 1;
- unsigned int power_up_tx : 1;
- unsigned int power_down_tx : 1;
- unsigned int power_up_rx : 1;
- unsigned int power_down_rx : 1;
- unsigned int packet_done : 1;
- unsigned int pa_start : 1;
- unsigned int pa_end : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_triggers;
-#define EXTAPB_REGFILE_TMU_TRIGGERS_RST 0x0
-#define EXTAPB_REGFILE_TMU_TRIGGERS_ADDR 0x4001d86c
-
-
-/* cal_triggers register */
-/*----------------------*/
-/* Triggers calibration enable signals */
-/* vco_cal_afc_en : Enable automatic frequency calibration (AFC) */
-/* vco_cal_afc_abort : Disable automatic frequency calibration (AFC) */
-/* vco_cal_aac_en : Enable amplitude loop */
-/* vco_cal_aac_abort : Disable amplitude loop */
-/* vco_cal_det_en : Enable out-of-range measurement */
-/* vco_cal_det_abort : Disable out-of-range measurement */
-/* dco_cal_en : Enable DC Offset calibration */
-/* iq_cal_en : Enable IQ Mismatch calibration */
-/* r_cal_en : Enable R Calibration */
-/* r_cal_abort : Disable R Calibration */
-/* rc_cal_en : Enable RC Calibration */
-/* rc_cal_abort : Disable RC Calibration */
-/* pa_cal_en : Enable PA calibration */
-/* pa_cal_abort : Disable PA calibration */
-/* pa_cal_coeff_calc_en : Enable PA calibration coefficient calculation */
-/* rf_bgp_cal_en : Enable RF bandbap calibration */
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_AFC_EN_MASK 0x0001
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_AFC_EN_POS 0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_AFC_EN_HIGH 1
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_AFC_EN_HIGH_MASK 0x1
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_AFC_EN_LOW 0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_AFC_EN_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_AFC_ABORT_MASK 0x0002
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_AFC_ABORT_POS 1
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_AFC_ABORT_HIGH 1
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_AFC_ABORT_HIGH_MASK 0x2
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_AFC_ABORT_LOW 0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_AFC_ABORT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_AAC_EN_MASK 0x0004
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_AAC_EN_POS 2
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_AAC_EN_HIGH 1
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_AAC_EN_HIGH_MASK 0x4
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_AAC_EN_LOW 0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_AAC_EN_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_AAC_ABORT_MASK 0x0008
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_AAC_ABORT_POS 3
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_AAC_ABORT_HIGH 1
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_AAC_ABORT_HIGH_MASK 0x8
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_AAC_ABORT_LOW 0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_AAC_ABORT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_DET_EN_MASK 0x0010
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_DET_EN_POS 4
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_DET_EN_HIGH 1
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_DET_EN_HIGH_MASK 0x10
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_DET_EN_LOW 0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_DET_EN_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_DET_ABORT_MASK 0x0020
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_DET_ABORT_POS 5
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_DET_ABORT_HIGH 1
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_DET_ABORT_HIGH_MASK 0x20
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_DET_ABORT_LOW 0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_VCO_CAL_DET_ABORT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_DCO_CAL_EN_MASK 0x0040
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_DCO_CAL_EN_POS 6
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_DCO_CAL_EN_HIGH 1
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_DCO_CAL_EN_HIGH_MASK 0x40
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_DCO_CAL_EN_LOW 0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_DCO_CAL_EN_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_IQ_CAL_EN_MASK 0x0080
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_IQ_CAL_EN_POS 7
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_IQ_CAL_EN_HIGH 1
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_IQ_CAL_EN_HIGH_MASK 0x80
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_IQ_CAL_EN_LOW 0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_IQ_CAL_EN_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_R_CAL_EN_MASK 0x0100
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_R_CAL_EN_POS 8
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_R_CAL_EN_HIGH 1
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_R_CAL_EN_HIGH_MASK 0x100
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_R_CAL_EN_LOW 0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_R_CAL_EN_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_R_CAL_ABORT_MASK 0x0200
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_R_CAL_ABORT_POS 9
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_R_CAL_ABORT_HIGH 1
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_R_CAL_ABORT_HIGH_MASK 0x200
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_R_CAL_ABORT_LOW 0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_R_CAL_ABORT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_RC_CAL_EN_MASK 0x0400
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_RC_CAL_EN_POS 10
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_RC_CAL_EN_HIGH 1
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_RC_CAL_EN_HIGH_MASK 0x400
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_RC_CAL_EN_LOW 0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_RC_CAL_EN_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_RC_CAL_ABORT_MASK 0x0800
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_RC_CAL_ABORT_POS 11
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_RC_CAL_ABORT_HIGH 1
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_RC_CAL_ABORT_HIGH_MASK 0x800
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_RC_CAL_ABORT_LOW 0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_RC_CAL_ABORT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_PA_CAL_EN_MASK 0x1000
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_PA_CAL_EN_POS 12
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_PA_CAL_EN_HIGH 1
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_PA_CAL_EN_HIGH_MASK 0x1000
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_PA_CAL_EN_LOW 0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_PA_CAL_EN_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_PA_CAL_ABORT_MASK 0x2000
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_PA_CAL_ABORT_POS 13
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_PA_CAL_ABORT_HIGH 1
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_PA_CAL_ABORT_HIGH_MASK 0x2000
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_PA_CAL_ABORT_LOW 0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_PA_CAL_ABORT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_PA_CAL_COEFF_CALC_EN_MASK 0x4000
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_PA_CAL_COEFF_CALC_EN_POS 14
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_PA_CAL_COEFF_CALC_EN_HIGH 1
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_PA_CAL_COEFF_CALC_EN_HIGH_MASK 0x4000
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_PA_CAL_COEFF_CALC_EN_LOW 0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_PA_CAL_COEFF_CALC_EN_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_RF_BGP_CAL_EN_MASK 0x8000
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_RF_BGP_CAL_EN_POS 15
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_RF_BGP_CAL_EN_HIGH 1
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_RF_BGP_CAL_EN_HIGH_MASK 0x8000
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_RF_BGP_CAL_EN_LOW 0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_RF_BGP_CAL_EN_LOW_MASK 0x0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int vco_cal_afc_en : 1;
- unsigned int vco_cal_afc_abort : 1;
- unsigned int vco_cal_aac_en : 1;
- unsigned int vco_cal_aac_abort : 1;
- unsigned int vco_cal_det_en : 1;
- unsigned int vco_cal_det_abort : 1;
- unsigned int dco_cal_en : 1;
- unsigned int iq_cal_en : 1;
- unsigned int r_cal_en : 1;
- unsigned int r_cal_abort : 1;
- unsigned int rc_cal_en : 1;
- unsigned int rc_cal_abort : 1;
- unsigned int pa_cal_en : 1;
- unsigned int pa_cal_abort : 1;
- unsigned int pa_cal_coeff_calc_en : 1;
- unsigned int rf_bgp_cal_en : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_cal_triggers;
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_RST 0x0
-#define EXTAPB_REGFILE_TMU_CAL_TRIGGERS_ADDR 0x4001d870
-
-
-/* kmod_cal_triggers register */
-/*----------------------*/
-/* Triggers KMod calibration */
-/* kmod_band_cal_en : Enable KMod pre calibration */
-/* kmod_band_cal_abort : Disable KMod pre calibration */
-/* kmod_chan_cal_en : Enable KMod post calibration */
-/* kmod_chan_cal_abort : Disable KMod post calibration */
-#define EXTAPB_REGFILE_TMU_KMOD_CAL_TRIGGERS_KMOD_BAND_CAL_EN_MASK 0x0001
-#define EXTAPB_REGFILE_TMU_KMOD_CAL_TRIGGERS_KMOD_BAND_CAL_EN_POS 0
-#define EXTAPB_REGFILE_TMU_KMOD_CAL_TRIGGERS_KMOD_BAND_CAL_EN_HIGH 1
-#define EXTAPB_REGFILE_TMU_KMOD_CAL_TRIGGERS_KMOD_BAND_CAL_EN_HIGH_MASK 0x1
-#define EXTAPB_REGFILE_TMU_KMOD_CAL_TRIGGERS_KMOD_BAND_CAL_EN_LOW 0
-#define EXTAPB_REGFILE_TMU_KMOD_CAL_TRIGGERS_KMOD_BAND_CAL_EN_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TMU_KMOD_CAL_TRIGGERS_KMOD_BAND_CAL_ABORT_MASK 0x0002
-#define EXTAPB_REGFILE_TMU_KMOD_CAL_TRIGGERS_KMOD_BAND_CAL_ABORT_POS 1
-#define EXTAPB_REGFILE_TMU_KMOD_CAL_TRIGGERS_KMOD_BAND_CAL_ABORT_HIGH 1
-#define EXTAPB_REGFILE_TMU_KMOD_CAL_TRIGGERS_KMOD_BAND_CAL_ABORT_HIGH_MASK 0x2
-#define EXTAPB_REGFILE_TMU_KMOD_CAL_TRIGGERS_KMOD_BAND_CAL_ABORT_LOW 0
-#define EXTAPB_REGFILE_TMU_KMOD_CAL_TRIGGERS_KMOD_BAND_CAL_ABORT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TMU_KMOD_CAL_TRIGGERS_KMOD_CHAN_CAL_EN_MASK 0x0004
-#define EXTAPB_REGFILE_TMU_KMOD_CAL_TRIGGERS_KMOD_CHAN_CAL_EN_POS 2
-#define EXTAPB_REGFILE_TMU_KMOD_CAL_TRIGGERS_KMOD_CHAN_CAL_EN_HIGH 1
-#define EXTAPB_REGFILE_TMU_KMOD_CAL_TRIGGERS_KMOD_CHAN_CAL_EN_HIGH_MASK 0x4
-#define EXTAPB_REGFILE_TMU_KMOD_CAL_TRIGGERS_KMOD_CHAN_CAL_EN_LOW 0
-#define EXTAPB_REGFILE_TMU_KMOD_CAL_TRIGGERS_KMOD_CHAN_CAL_EN_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TMU_KMOD_CAL_TRIGGERS_KMOD_CHAN_CAL_ABORT_MASK 0x0008
-#define EXTAPB_REGFILE_TMU_KMOD_CAL_TRIGGERS_KMOD_CHAN_CAL_ABORT_POS 3
-#define EXTAPB_REGFILE_TMU_KMOD_CAL_TRIGGERS_KMOD_CHAN_CAL_ABORT_HIGH 1
-#define EXTAPB_REGFILE_TMU_KMOD_CAL_TRIGGERS_KMOD_CHAN_CAL_ABORT_HIGH_MASK 0x8
-#define EXTAPB_REGFILE_TMU_KMOD_CAL_TRIGGERS_KMOD_CHAN_CAL_ABORT_LOW 0
-#define EXTAPB_REGFILE_TMU_KMOD_CAL_TRIGGERS_KMOD_CHAN_CAL_ABORT_LOW_MASK 0x0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int kmod_band_cal_en : 1;
- unsigned int kmod_band_cal_abort : 1;
- unsigned int kmod_chan_cal_en : 1;
- unsigned int kmod_chan_cal_abort : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_kmod_cal_triggers;
-#define EXTAPB_REGFILE_TMU_KMOD_CAL_TRIGGERS_RST 0x0
-#define EXTAPB_REGFILE_TMU_KMOD_CAL_TRIGGERS_ADDR 0x4001d874
-
-
-/* synth_cal_triggers register */
-/*----------------------*/
-/* Triggers for synthesizer calibration */
-/* synth_cal_startup_start : Triggers the start of the synthesizer calibration for startup */
-/* synth_cal_startup_abort : Aborts (ongoing) synthesizer calibration for startup. */
-/* synth_cal_operation_start : Triggers the start of the synthesizer calibration during operation. */
-/* synth_cal_operation_abort : Aborts (ongoing) synthesizer calibration during operation. */
-/* synth_cal_locking_sequence_start : Triggers the start of the locking sequence (independent from the synth calibration for operation */
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_STARTUP_START_MASK 0x0001
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_STARTUP_START_POS 0
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_STARTUP_START_HIGH 1
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_STARTUP_START_HIGH_MASK 0x1
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_STARTUP_START_LOW 0
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_STARTUP_START_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_STARTUP_ABORT_MASK 0x0002
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_STARTUP_ABORT_POS 1
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_STARTUP_ABORT_HIGH 1
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_STARTUP_ABORT_HIGH_MASK 0x2
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_STARTUP_ABORT_LOW 0
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_STARTUP_ABORT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_OPERATION_START_MASK 0x0004
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_OPERATION_START_POS 2
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_OPERATION_START_HIGH 1
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_OPERATION_START_HIGH_MASK 0x4
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_OPERATION_START_LOW 0
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_OPERATION_START_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_OPERATION_ABORT_MASK 0x0008
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_OPERATION_ABORT_POS 3
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_OPERATION_ABORT_HIGH 1
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_OPERATION_ABORT_HIGH_MASK 0x8
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_OPERATION_ABORT_LOW 0
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_OPERATION_ABORT_LOW_MASK 0x0
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_LOCKING_SEQUENCE_START_MASK 0x0010
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_LOCKING_SEQUENCE_START_POS 4
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_LOCKING_SEQUENCE_START_HIGH 1
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_LOCKING_SEQUENCE_START_HIGH_MASK 0x10
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_LOCKING_SEQUENCE_START_LOW 0
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_SYNTH_CAL_LOCKING_SEQUENCE_START_LOW_MASK 0x0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int synth_cal_startup_start : 1;
- unsigned int synth_cal_startup_abort : 1;
- unsigned int synth_cal_operation_start : 1;
- unsigned int synth_cal_operation_abort : 1;
- unsigned int synth_cal_locking_sequence_start : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_synth_cal_triggers;
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_RST 0x0
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_TRIGGERS_ADDR 0x4001d878
-
-
-/* synth_cal_cfg register */
-/*----------------------*/
-/* Parameters for syntesizer calibration. */
-/* pll_vco_ff_amp_cor : When 1, the feedforward amplitude correction is enabled. */
-/* redo_aafc : When 1, the AAFC is re-run during synthesizer calibration during operation. */
-/* aac_active : When 1, the AAC is re-run after pre-charge (when redo_aafc = 0 and pll_vco_ff_amp_cor = 0) */
-/* pll_lock_aac_pch_active : When 1, pre-chare during PLL locking sequence is enabled. */
-/* pll_lock_aac_lock_active : When 1, AAC during pll locking sequence is enabled. */
-/* pll_lock_pa_rampup_active : When 1, PLL locking sequence is launched at start PA rampup */
-/* pll_lock_tx3_active : When 1, PLL locking sequence is launched at assertion TX3 group signal */
-/* pll_vtune_hold_en : When 1,during VCO coarse calibration the hold value for the PLL vtune settings are extended till the end of the VCO coarse calibration. When 0, the PLL vtune settings are reset after the AFC2 loop is finished */
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_CFG_PLL_VCO_FF_AMP_COR_MASK 0x0001
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_CFG_PLL_VCO_FF_AMP_COR_POS 0
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_CFG_REDO_AAFC_MASK 0x0002
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_CFG_REDO_AAFC_POS 1
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_CFG_AAC_ACTIVE_MASK 0x0004
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_CFG_AAC_ACTIVE_POS 2
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_CFG_PLL_LOCK_AAC_PCH_ACTIVE_MASK 0x0008
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_CFG_PLL_LOCK_AAC_PCH_ACTIVE_POS 3
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_CFG_PLL_LOCK_AAC_LOCK_ACTIVE_MASK 0x0010
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_CFG_PLL_LOCK_AAC_LOCK_ACTIVE_POS 4
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_CFG_PLL_LOCK_PA_RAMPUP_ACTIVE_MASK 0x0020
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_CFG_PLL_LOCK_PA_RAMPUP_ACTIVE_POS 5
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_CFG_PLL_LOCK_TX3_ACTIVE_MASK 0x0040
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_CFG_PLL_LOCK_TX3_ACTIVE_POS 6
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_CFG_PLL_VTUNE_HOLD_EN_MASK 0x0080
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_CFG_PLL_VTUNE_HOLD_EN_POS 7
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_vco_ff_amp_cor : 1;
- unsigned int redo_aafc : 1;
- unsigned int aac_active : 1;
- unsigned int pll_lock_aac_pch_active : 1;
- unsigned int pll_lock_aac_lock_active : 1;
- unsigned int pll_lock_pa_rampup_active : 1;
- unsigned int pll_lock_tx3_active : 1;
- unsigned int pll_vtune_hold_en : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_synth_cal_cfg;
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_CFG_RST 0x40
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_CFG_ADDR 0x4001d87c
-
-
-/* cal_mode register */
-/*----------------------*/
-/* Specifies calibration modes */
-/* dco_cal_mode : DC Offset calibration mode */
-/* iq_cal_mode : IQ mismatch calibration mode */
-#define EXTAPB_REGFILE_TMU_CAL_MODE_DCO_CAL_MODE_MASK 0x0003
-#define EXTAPB_REGFILE_TMU_CAL_MODE_DCO_CAL_MODE_POS 0
-#define EXTAPB_REGFILE_TMU_CAL_MODE_DCO_CAL_MODE_COARSE_ONLY 0
-#define EXTAPB_REGFILE_TMU_CAL_MODE_DCO_CAL_MODE_COARSE_ONLY_MASK 0x0
-#define EXTAPB_REGFILE_TMU_CAL_MODE_DCO_CAL_MODE_FINE_ONLY 1
-#define EXTAPB_REGFILE_TMU_CAL_MODE_DCO_CAL_MODE_FINE_ONLY_MASK 0x1
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#define EXTAPB_REGFILE_TMU_CAL_MODE_DCO_CAL_MODE_COARSE_FINE 2
-#define EXTAPB_REGFILE_TMU_CAL_MODE_DCO_CAL_MODE_COARSE_FINE_MASK 0x2
-#else
-#define EXTAPB_REGFILE_TMU_CAL_MODE_DCO_CAL_MODE_0 2
-#define EXTAPB_REGFILE_TMU_CAL_MODE_DCO_CAL_MODE_0_MASK 0x2
-#endif
-#define EXTAPB_REGFILE_TMU_CAL_MODE_IQ_CAL_MODE_MASK 0x000c
-#define EXTAPB_REGFILE_TMU_CAL_MODE_IQ_CAL_MODE_POS 2
-#define EXTAPB_REGFILE_TMU_CAL_MODE_IQ_CAL_MODE_PHASE_ONLY 0
-#define EXTAPB_REGFILE_TMU_CAL_MODE_IQ_CAL_MODE_PHASE_ONLY_MASK 0x0
-#define EXTAPB_REGFILE_TMU_CAL_MODE_IQ_CAL_MODE_MAG_ONLY 1
-#define EXTAPB_REGFILE_TMU_CAL_MODE_IQ_CAL_MODE_MAG_ONLY_MASK 0x4
-#define EXTAPB_REGFILE_TMU_CAL_MODE_IQ_CAL_MODE_PHASE_MAG 2
-#define EXTAPB_REGFILE_TMU_CAL_MODE_IQ_CAL_MODE_PHASE_MAG_MASK 0x8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int dco_cal_mode : 2;
- unsigned int iq_cal_mode : 2;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_cal_mode;
-#define EXTAPB_REGFILE_TMU_CAL_MODE_RST 0x0
-#define EXTAPB_REGFILE_TMU_CAL_MODE_ADDR 0x4001d880
-
-
-/* synth_cal_pll_vco_rst_window register */
-/*----------------------*/
-/* Duration of the PLL VCO reset pulse at the start of the synthesizer calibration for startup (expressed in 0.5 us) */
-/* pll_vco_rst_window : See register description */
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_PLL_VCO_RST_WINDOW_PLL_VCO_RST_WINDOW_MASK 0x03ff
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_PLL_VCO_RST_WINDOW_PLL_VCO_RST_WINDOW_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pll_vco_rst_window : 10;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_synth_cal_pll_vco_rst_window;
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_PLL_VCO_RST_WINDOW_RST 0x2
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_PLL_VCO_RST_WINDOW_ADDR 0x4001d884
-
-
-/* synth_cal_pll_lock_aac_pch_treshold register */
-/*----------------------*/
-/* Timer value to start the pre charge during the PLL locking sequence (expressed in 0.5 us) */
-/* aac_pch_treshold : See register description. */
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_PLL_LOCK_AAC_PCH_TRESHOLD_AAC_PCH_TRESHOLD_MASK 0x03ff
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_PLL_LOCK_AAC_PCH_TRESHOLD_AAC_PCH_TRESHOLD_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aac_pch_treshold : 10;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_synth_cal_pll_lock_aac_pch_treshold;
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_PLL_LOCK_AAC_PCH_TRESHOLD_RST 0x0
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_PLL_LOCK_AAC_PCH_TRESHOLD_ADDR 0x4001d888
-
-
-/* synth_cal_pll_lock_aac_lock_treshold register */
-/*----------------------*/
-/* Timer value to start the AAC during the PLL locking sequence (expressed in 0.5 us) */
-/* aac_lock_treshold : See register description. */
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_PLL_LOCK_AAC_LOCK_TRESHOLD_AAC_LOCK_TRESHOLD_MASK 0x03ff
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_PLL_LOCK_AAC_LOCK_TRESHOLD_AAC_LOCK_TRESHOLD_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int aac_lock_treshold : 10;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_synth_cal_pll_lock_aac_lock_treshold;
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_PLL_LOCK_AAC_LOCK_TRESHOLD_RST 0x0
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_PLL_LOCK_AAC_LOCK_TRESHOLD_ADDR 0x4001d88c
-
-
-/* synth_cal_pll_lock_treshold_1 register */
-/*----------------------*/
-/* Timer value to start first loop of PLL locking sequence (Expressed in 0.5 us) */
-/* lock_treshold_1 : See register description. */
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_PLL_LOCK_TRESHOLD_1_LOCK_TRESHOLD_1_MASK 0x03ff
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_PLL_LOCK_TRESHOLD_1_LOCK_TRESHOLD_1_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int lock_treshold_1 : 10;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_synth_cal_pll_lock_treshold_1;
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_PLL_LOCK_TRESHOLD_1_RST 0x14
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_PLL_LOCK_TRESHOLD_1_ADDR 0x4001d890
-
-
-/* synth_cal_pll_lock_treshold_2 register */
-/*----------------------*/
-/* Timer value to start second loop of PLL locking sequence (Expressed in 0.5 us) */
-/* lock_treshold_2 : See register description. */
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_PLL_LOCK_TRESHOLD_2_LOCK_TRESHOLD_2_MASK 0x03ff
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_PLL_LOCK_TRESHOLD_2_LOCK_TRESHOLD_2_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int lock_treshold_2 : 10;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_synth_cal_pll_lock_treshold_2;
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_PLL_LOCK_TRESHOLD_2_RST 0x28
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_PLL_LOCK_TRESHOLD_2_ADDR 0x4001d894
-
-
-/* synth_cal_pll_lock_treshold_3 register */
-/*----------------------*/
-/* Timer value to start third loop of PLL locking sequence (Expressed in 0.5 us) */
-/* lock_treshold_3 : See register description. */
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_PLL_LOCK_TRESHOLD_3_LOCK_TRESHOLD_3_MASK 0x03ff
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_PLL_LOCK_TRESHOLD_3_LOCK_TRESHOLD_3_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int lock_treshold_3 : 10;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_synth_cal_pll_lock_treshold_3;
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_PLL_LOCK_TRESHOLD_3_RST 0x3c
-#define EXTAPB_REGFILE_TMU_SYNTH_CAL_PLL_LOCK_TRESHOLD_3_ADDR 0x4001d898
-
-
-/* dco_cal_gain_switch_settling_time register */
-/*----------------------*/
-/* During dc-offset calibration the analog gain is switched in between every measurement. The analog circuits are allowed to switch and settle before actualy measuring the dco offset. Unit is 16 MHz clock cycle (62.5 ns) */
-/* dco_cal_settling_time : See register description */
-#define EXTAPB_REGFILE_TMU_DCO_CAL_GAIN_SWITCH_SETTLING_TIME_DCO_CAL_SETTLING_TIME_MASK 0xffff
-#define EXTAPB_REGFILE_TMU_DCO_CAL_GAIN_SWITCH_SETTLING_TIME_DCO_CAL_SETTLING_TIME_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int dco_cal_settling_time : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_dco_cal_gain_switch_settling_time;
-#define EXTAPB_REGFILE_TMU_DCO_CAL_GAIN_SWITCH_SETTLING_TIME_RST 0x1
-#define EXTAPB_REGFILE_TMU_DCO_CAL_GAIN_SWITCH_SETTLING_TIME_ADDR 0x4001d89c
-
-
-/* dco_cal_fine_cal_pause register */
-/*----------------------*/
-/* Delay between coarse and fine DC offset calibration to allow the applied coarse offset to have its effect. Unit is 0.5 us */
-/* dc_fine_cal_pause : See register description */
-#define EXTAPB_REGFILE_TMU_DCO_CAL_FINE_CAL_PAUSE_DC_FINE_CAL_PAUSE_MASK 0xffff
-#define EXTAPB_REGFILE_TMU_DCO_CAL_FINE_CAL_PAUSE_DC_FINE_CAL_PAUSE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int dc_fine_cal_pause : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_dco_cal_fine_cal_pause;
-#define EXTAPB_REGFILE_TMU_DCO_CAL_FINE_CAL_PAUSE_RST 0xa
-#define EXTAPB_REGFILE_TMU_DCO_CAL_FINE_CAL_PAUSE_ADDR 0x4001d8a0
-
-
-/* comparator_pre_g1 register */
-/*----------------------*/
-/* Time window between the assertion of the G1 group signals and G2 group signals. Unit = 0.5 us */
-/* comparator_pre : See register description. */
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_G1_COMPARATOR_PRE_MASK 0x07ff
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_G1_COMPARATOR_PRE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int comparator_pre : 11;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_comparator_pre_g1;
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_G1_RST 0x28
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_G1_ADDR 0x4001d8a4
-
-
-/* comparator_post_g1 register */
-/*----------------------*/
-/* Time window between the start of the power-down sequence and the de-assertion of the G1 group signals. Unit = 0.5 us */
-/* comparator_post : See register description. */
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_G1_COMPARATOR_POST_MASK 0x07ff
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_G1_COMPARATOR_POST_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int comparator_post : 11;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_comparator_post_g1;
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_G1_RST 0x14
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_G1_ADDR 0x4001d8a8
-
-
-/* comparator_pre_g2 register */
-/*----------------------*/
-/* Time window between the assertion of the G1 group signals and the start of the PLL phase. Unit = 0.5 us */
-/* comparator_pre : See register description */
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_G2_COMPARATOR_PRE_MASK 0x07ff
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_G2_COMPARATOR_PRE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int comparator_pre : 11;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_comparator_pre_g2;
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_G2_RST 0x50
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_G2_ADDR 0x4001d8ac
-
-
-/* comparator_post_g2 register */
-/*----------------------*/
-/* Time window between the start of the power-down sequence and the de-assertion of the G2 group signals. Unit = 0.5 us */
-/* comparator_post : See register description. */
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_G2_COMPARATOR_POST_MASK 0x07ff
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_G2_COMPARATOR_POST_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int comparator_post : 11;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_comparator_post_g2;
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_G2_RST 0xa
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_G2_ADDR 0x4001d8b0
-
-
-/* comparator_pre_tx1 register */
-/*----------------------*/
-/* Time window between the start of the PLL phase and the assertion of the TX1 group signals. Unit = 0.5 us */
-/* comparator_pre : See register description. */
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_TX1_COMPARATOR_PRE_MASK 0x07ff
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_TX1_COMPARATOR_PRE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int comparator_pre : 11;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_comparator_pre_tx1;
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_TX1_RST 0x28
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_TX1_ADDR 0x4001d8b4
-
-
-/* comparator_post_tx1 register */
-/*----------------------*/
-/* Time window between the end of the TX phase and the de-assertion of the TX1 group signals. Unit = 0.5 us */
-/* comparator_post : See register description. */
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_TX1_COMPARATOR_POST_MASK 0x07ff
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_TX1_COMPARATOR_POST_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int comparator_post : 11;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_comparator_post_tx1;
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_TX1_RST 0x8
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_TX1_ADDR 0x4001d8b8
-
-
-/* comparator_pre_tx2 register */
-/*----------------------*/
-/* Time window between the start of the PLL phase and the assertion of the TX2 group signals. Unit = 0.5 us */
-/* comparator_pre : See register description. */
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_TX2_COMPARATOR_PRE_MASK 0x07ff
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_TX2_COMPARATOR_PRE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int comparator_pre : 11;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_comparator_pre_tx2;
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_TX2_RST 0x2a
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_TX2_ADDR 0x4001d8bc
-
-
-/* comparator_post_tx2 register */
-/*----------------------*/
-/* Time window between the end of the TX phase and the de-assertion of the TX2 group signals. Unit = 0.5 us */
-/* comparator_post : See register description. */
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_TX2_COMPARATOR_POST_MASK 0x07ff
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_TX2_COMPARATOR_POST_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int comparator_post : 11;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_comparator_post_tx2;
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_TX2_RST 0x6
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_TX2_ADDR 0x4001d8c0
-
-
-/* comparator_pre_tx3 register */
-/*----------------------*/
-/* Time window between the start of the PLL phase and the assertion of the TX3 group signals. Unit = 0.5 us */
-/* comparator_pre : See register description. */
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_TX3_COMPARATOR_PRE_MASK 0x07ff
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_TX3_COMPARATOR_PRE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int comparator_pre : 11;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_comparator_pre_tx3;
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_TX3_RST 0x2c
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_TX3_ADDR 0x4001d8c4
-
-
-/* comparator_post_tx3 register */
-/*----------------------*/
-/* Time window between the end of the TX phase and the de-assertion of the TX3 group signals. Unit = 0.5 us */
-/* comparator_post : See register description */
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_TX3_COMPARATOR_POST_MASK 0x07ff
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_TX3_COMPARATOR_POST_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int comparator_post : 11;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_comparator_post_tx3;
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_TX3_RST 0x4
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_TX3_ADDR 0x4001d8c8
-
-
-/* comparator_pre_rx1 register */
-/*----------------------*/
-/* Time window between the start of the PLL phase and the assertion of the RX1 group signals. Unit = 0.5 us */
-/* comparator_pre : See register description. */
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_RX1_COMPARATOR_PRE_MASK 0x07ff
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_RX1_COMPARATOR_PRE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int comparator_pre : 11;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_comparator_pre_rx1;
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_RX1_RST 0x28
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_RX1_ADDR 0x4001d8cc
-
-
-/* comparator_post_rx1 register */
-/*----------------------*/
-/* Time window between the end of the RX phase and the de-assertion of the RX1 group signals. Unit = 0.5 us */
-/* comparator_post : See register description */
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_RX1_COMPARATOR_POST_MASK 0x07ff
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_RX1_COMPARATOR_POST_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int comparator_post : 11;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_comparator_post_rx1;
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_RX1_RST 0x8
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_RX1_ADDR 0x4001d8d0
-
-
-/* comparator_pre_rx2 register */
-/*----------------------*/
-/* Time window between the start of the PLL phase and the assertion of the RX2 group signals. Unit = 0.5 us */
-/* comparator_pre : See register description. */
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_RX2_COMPARATOR_PRE_MASK 0x07ff
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_RX2_COMPARATOR_PRE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int comparator_pre : 11;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_comparator_pre_rx2;
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_RX2_RST 0x2a
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_RX2_ADDR 0x4001d8d4
-
-
-/* comparator_post_rx2 register */
-/*----------------------*/
-/* Time window between the end of the RX phase and the de-assertion of the RX2 group signals. Unit = 0.5 us */
-/* comparator_post : See register description. */
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_RX2_COMPARATOR_POST_MASK 0x07ff
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_RX2_COMPARATOR_POST_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int comparator_post : 11;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_comparator_post_rx2;
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_RX2_RST 0x6
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_RX2_ADDR 0x4001d8d8
-
-
-/* comparator_pre_rx3 register */
-/*----------------------*/
-/* Time window between the start of the PLL phase and the assertion of the RX3 group signals. Unit = 0.5 us */
-/* comparator_pre : See register description. */
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_RX3_COMPARATOR_PRE_MASK 0x07ff
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_RX3_COMPARATOR_PRE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int comparator_pre : 11;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_comparator_pre_rx3;
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_RX3_RST 0x2c
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_RX3_ADDR 0x4001d8dc
-
-
-/* comparator_post_rx3 register */
-/*----------------------*/
-/* Time window between the end of the RX phase and the de-assertion of the RX3 group signals. Unit = 0.5 us */
-/* comparator_post : See register description. */
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_RX3_COMPARATOR_POST_MASK 0x07ff
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_RX3_COMPARATOR_POST_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int comparator_post : 11;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_comparator_post_rx3;
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_RX3_RST 0x4
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_RX3_ADDR 0x4001d8e0
-
-
-/* comparator_packet_start register */
-/*----------------------*/
-/* Time window between the start of the PLL phase and the generation of the internal packet start. (If enabled). Unit = 0.5 us */
-/* comparator : See register description. */
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PACKET_START_COMPARATOR_MASK 0x07ff
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PACKET_START_COMPARATOR_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int comparator : 11;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_comparator_packet_start;
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PACKET_START_RST 0x32
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PACKET_START_ADDR 0x4001d8e4
-
-
-/* comparator_pre_dp_reset register */
-/*----------------------*/
-/* Time window between the assertion of the G1 group signals and the de-assertion of the reset signal towards the datapath. */
-/* comparator_pre : See register description. */
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_DP_RESET_COMPARATOR_PRE_MASK 0x07ff
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_DP_RESET_COMPARATOR_PRE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int comparator_pre : 11;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_comparator_pre_dp_reset;
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_DP_RESET_RST 0x28
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PRE_DP_RESET_ADDR 0x4001d8e8
-
-
-/* comparator_post_dp_reset register */
-/*----------------------*/
-/* Time window between the start of the power down sequence and the assertion of the reset signal towards the datapath. */
-/* comparator_post : See register description. */
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_DP_RESET_COMPARATOR_POST_MASK 0x07ff
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_DP_RESET_COMPARATOR_POST_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int comparator_post : 11;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_comparator_post_dp_reset;
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_DP_RESET_RST 0xf
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_DP_RESET_ADDR 0x4001d8ec
-
-
-/* comparator_pa_rampup register */
-/*----------------------*/
-/* Time window between the assertion of the TX3 group signals and the start of the PA power ramp-up. Unit = 1 us */
-/* comparator : See register description */
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PA_RAMPUP_COMPARATOR_MASK 0x001f
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PA_RAMPUP_COMPARATOR_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int comparator : 5;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_comparator_pa_rampup;
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PA_RAMPUP_RST 0x1
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PA_RAMPUP_ADDR 0x4001d8f0
-
-
-/* comparator_pll_on register */
-/*----------------------*/
-/* Time window between the end of the RX/TX phase and the restart of the PLL phase. Unit 0.5 us */
-/* comparator_pll_on : See register description */
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PLL_ON_COMPARATOR_PLL_ON_MASK 0x07ff
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PLL_ON_COMPARATOR_PLL_ON_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int comparator_pll_on : 11;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_comparator_pll_on;
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PLL_ON_RST 0x14
-#define EXTAPB_REGFILE_TMU_COMPARATOR_PLL_ON_ADDR 0x4001d8f4
-
-
-/* reset_mask register */
-/*----------------------*/
-/* Disable mask for the generated resets. */
-/* dp_reset_dis : When 1, the reset scheme towards the datapath in the power sequence is disabled. */
-/* dp_reset_force : When 1, the dp_reset is forced to 1 */
-/* synth_reset_force : When 1, the synth_reset is forced to 1 */
-/* synth_reset_dp_rst_dis : When 0, the synth_reset is enabled by dp_reset */
-/* synth_reset_fcw_upd_dis : When 0, the synth_reset is enabled at update of FCW */
-/* synth_reset_pll_lock_dis : When 0, the synth_reset is enabled till the PLL lockin sequence is started */
-/* synth_reset_power_down_dis : When 0, the synth_reset is enabled as soon the global TMU enters the power_down state */
-/* tone_reset_force : When 1, the tone_reset is forced to 1 */
-/* tone_reset_dp_rst_dis : When 0, the synth_reset is enabled by dp_reset */
-/* tone_reset_fcw_upd_dis : When 0, the tone_reset is enabled at update of FCW */
-#define EXTAPB_REGFILE_TMU_RESET_MASK_DP_RESET_DIS_MASK 0x0001
-#define EXTAPB_REGFILE_TMU_RESET_MASK_DP_RESET_DIS_POS 0
-#define EXTAPB_REGFILE_TMU_RESET_MASK_DP_RESET_FORCE_MASK 0x0002
-#define EXTAPB_REGFILE_TMU_RESET_MASK_DP_RESET_FORCE_POS 1
-#define EXTAPB_REGFILE_TMU_RESET_MASK_SYNTH_RESET_FORCE_MASK 0x0004
-#define EXTAPB_REGFILE_TMU_RESET_MASK_SYNTH_RESET_FORCE_POS 2
-#define EXTAPB_REGFILE_TMU_RESET_MASK_SYNTH_RESET_DP_RST_DIS_MASK 0x0008
-#define EXTAPB_REGFILE_TMU_RESET_MASK_SYNTH_RESET_DP_RST_DIS_POS 3
-#define EXTAPB_REGFILE_TMU_RESET_MASK_SYNTH_RESET_FCW_UPD_DIS_MASK 0x0010
-#define EXTAPB_REGFILE_TMU_RESET_MASK_SYNTH_RESET_FCW_UPD_DIS_POS 4
-#define EXTAPB_REGFILE_TMU_RESET_MASK_SYNTH_RESET_PLL_LOCK_DIS_MASK 0x0020
-#define EXTAPB_REGFILE_TMU_RESET_MASK_SYNTH_RESET_PLL_LOCK_DIS_POS 5
-#define EXTAPB_REGFILE_TMU_RESET_MASK_SYNTH_RESET_POWER_DOWN_DIS_MASK 0x0040
-#define EXTAPB_REGFILE_TMU_RESET_MASK_SYNTH_RESET_POWER_DOWN_DIS_POS 6
-#define EXTAPB_REGFILE_TMU_RESET_MASK_TONE_RESET_FORCE_MASK 0x0080
-#define EXTAPB_REGFILE_TMU_RESET_MASK_TONE_RESET_FORCE_POS 7
-#define EXTAPB_REGFILE_TMU_RESET_MASK_TONE_RESET_DP_RST_DIS_MASK 0x0100
-#define EXTAPB_REGFILE_TMU_RESET_MASK_TONE_RESET_DP_RST_DIS_POS 8
-#define EXTAPB_REGFILE_TMU_RESET_MASK_TONE_RESET_FCW_UPD_DIS_MASK 0x0200
-#define EXTAPB_REGFILE_TMU_RESET_MASK_TONE_RESET_FCW_UPD_DIS_POS 9
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int dp_reset_dis : 1;
- unsigned int dp_reset_force : 1;
- unsigned int synth_reset_force : 1;
- unsigned int synth_reset_dp_rst_dis : 1;
- unsigned int synth_reset_fcw_upd_dis : 1;
- unsigned int synth_reset_pll_lock_dis : 1;
- unsigned int synth_reset_power_down_dis : 1;
- unsigned int tone_reset_force : 1;
- unsigned int tone_reset_dp_rst_dis : 1;
- unsigned int tone_reset_fcw_upd_dis : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_reset_mask;
-#define EXTAPB_REGFILE_TMU_RESET_MASK_RST 0x0
-#define EXTAPB_REGFILE_TMU_RESET_MASK_ADDR 0x4001d8f8
-
-
-/* pa_mask register */
-/*----------------------*/
-/* PA enable mask */
-/* tmu_pa_start_dis : When 1, the coupling between TMU and the PA start is disabled */
-/* tmu_pa_end_dis : When 1, the coupling between TMU and the PA end is disabled */
-#define EXTAPB_REGFILE_TMU_PA_MASK_TMU_PA_START_DIS_MASK 0x0001
-#define EXTAPB_REGFILE_TMU_PA_MASK_TMU_PA_START_DIS_POS 0
-#define EXTAPB_REGFILE_TMU_PA_MASK_TMU_PA_END_DIS_MASK 0x0002
-#define EXTAPB_REGFILE_TMU_PA_MASK_TMU_PA_END_DIS_POS 1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int tmu_pa_start_dis : 1;
- unsigned int tmu_pa_end_dis : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_pa_mask;
-#define EXTAPB_REGFILE_TMU_PA_MASK_RST 0x0
-#define EXTAPB_REGFILE_TMU_PA_MASK_ADDR 0x4001d8fc
-
-
-/* rfp_agc_intstat register */
-/*----------------------*/
-/* RFP AGC Interrupt status */
-/* int_agc : AGC interrupt detected */
-#define EXTAPB_REGFILE_TMU_RFP_AGC_INTSTAT_INT_AGC_MASK 0x000f
-#define EXTAPB_REGFILE_TMU_RFP_AGC_INTSTAT_INT_AGC_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int int_agc : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_rfp_agc_intstat;
-#define EXTAPB_REGFILE_TMU_RFP_AGC_INTSTAT_RST 0x0
-#define EXTAPB_REGFILE_TMU_RFP_AGC_INTSTAT_DYNAMIC true
-#define EXTAPB_REGFILE_TMU_RFP_AGC_INTSTAT_SNAPCLOCK 0
-#define EXTAPB_REGFILE_TMU_RFP_AGC_INTSTAT_ADDR 0x4001d900
-
-
-/* rfp_agc_intsetstat register */
-/*----------------------*/
-/* RFP AGC Interrupt Set. Cannot be written without RX reference clock. Any next write will hang */
-/* int_agc : Set event for AGC interrupt */
-#define EXTAPB_REGFILE_TMU_RFP_AGC_INTSETSTAT_INT_AGC_MASK 0x000f
-#define EXTAPB_REGFILE_TMU_RFP_AGC_INTSETSTAT_INT_AGC_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int int_agc : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_rfp_agc_intsetstat;
-#define EXTAPB_REGFILE_TMU_RFP_AGC_INTSETSTAT_RST 0x0
-#define EXTAPB_REGFILE_TMU_RFP_AGC_INTSETSTAT_ADDR 0x4001d904
-
-
-/* rfp_agc_intclrstat register */
-/*----------------------*/
-/* RFP AGC Interrupt clear. Cannot be written without RX reference clock. Any next write will hang */
-/* int_agc : Clear event for AGC interrupt */
-#define EXTAPB_REGFILE_TMU_RFP_AGC_INTCLRSTAT_INT_AGC_MASK 0x000f
-#define EXTAPB_REGFILE_TMU_RFP_AGC_INTCLRSTAT_INT_AGC_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int int_agc : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_rfp_agc_intclrstat;
-#define EXTAPB_REGFILE_TMU_RFP_AGC_INTCLRSTAT_RST 0x0
-#define EXTAPB_REGFILE_TMU_RFP_AGC_INTCLRSTAT_ADDR 0x4001d908
-
-
-/* rfp_agc_inten register */
-/*----------------------*/
-/* RFP AGC Interrupt enable */
-/* int_agc : Interrupt enable for AGC interrupt */
-#define EXTAPB_REGFILE_TMU_RFP_AGC_INTEN_INT_AGC_MASK 0x000f
-#define EXTAPB_REGFILE_TMU_RFP_AGC_INTEN_INT_AGC_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int int_agc : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_rfp_agc_inten;
-#define EXTAPB_REGFILE_TMU_RFP_AGC_INTEN_RST 0x0
-#define EXTAPB_REGFILE_TMU_RFP_AGC_INTEN_ADDR 0x4001d90c
-
-
-/* pa_cal_delay1 register */
-/*----------------------*/
-/* TBD */
-/* value : TBD */
-#define EXTAPB_REGFILE_TMU_PA_CAL_DELAY1_VALUE_MASK 0x03ff
-#define EXTAPB_REGFILE_TMU_PA_CAL_DELAY1_VALUE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int value : 10;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_pa_cal_delay1;
-#define EXTAPB_REGFILE_TMU_PA_CAL_DELAY1_RST 0x8
-#define EXTAPB_REGFILE_TMU_PA_CAL_DELAY1_ADDR 0x4001d910
-
-
-/* pa_cal_delay2 register */
-/*----------------------*/
-/* TBD */
-/* value : TBD */
-#define EXTAPB_REGFILE_TMU_PA_CAL_DELAY2_VALUE_MASK 0x03ff
-#define EXTAPB_REGFILE_TMU_PA_CAL_DELAY2_VALUE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int value : 10;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_pa_cal_delay2;
-#define EXTAPB_REGFILE_TMU_PA_CAL_DELAY2_RST 0x8
-#define EXTAPB_REGFILE_TMU_PA_CAL_DELAY2_ADDR 0x4001d914
-
-
-/* pa_cal_delay3 register */
-/*----------------------*/
-/* TBD */
-/* value : TBD */
-#define EXTAPB_REGFILE_TMU_PA_CAL_DELAY3_VALUE_MASK 0x03ff
-#define EXTAPB_REGFILE_TMU_PA_CAL_DELAY3_VALUE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int value : 10;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_pa_cal_delay3;
-#define EXTAPB_REGFILE_TMU_PA_CAL_DELAY3_RST 0x8
-#define EXTAPB_REGFILE_TMU_PA_CAL_DELAY3_ADDR 0x4001d918
-
-
-/* pa_cal_meas_window register */
-/*----------------------*/
-/* TBD */
-/* value : TBD */
-#define EXTAPB_REGFILE_TMU_PA_CAL_MEAS_WINDOW_VALUE_MASK 0xffff
-#define EXTAPB_REGFILE_TMU_PA_CAL_MEAS_WINDOW_VALUE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int value : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_pa_cal_meas_window;
-#define EXTAPB_REGFILE_TMU_PA_CAL_MEAS_WINDOW_RST 0x10
-#define EXTAPB_REGFILE_TMU_PA_CAL_MEAS_WINDOW_ADDR 0x4001d91c
-
-
-/* arbitration_cfg register */
-/*----------------------*/
-/* TBD */
-/* auto_zb_hp : For auto arbitration. If set ZB has highest priority, if clear BLE has highest priority */
-/* man_arb_en : If set manual arbitration is enabled. If clear automatic arbitration is enabled. */
-/* man_zb : If using manual mode, and this bit is set radio will be allocated to ZB, otherwise allocated to BLE */
-#define EXTAPB_REGFILE_TMU_ARBITRATION_CFG_AUTO_ZB_HP_MASK 0x0001
-#define EXTAPB_REGFILE_TMU_ARBITRATION_CFG_AUTO_ZB_HP_POS 0
-#define EXTAPB_REGFILE_TMU_ARBITRATION_CFG_MAN_ARB_EN_MASK 0x0002
-#define EXTAPB_REGFILE_TMU_ARBITRATION_CFG_MAN_ARB_EN_POS 1
-#define EXTAPB_REGFILE_TMU_ARBITRATION_CFG_MAN_ZB_MASK 0x0004
-#define EXTAPB_REGFILE_TMU_ARBITRATION_CFG_MAN_ZB_POS 2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int auto_zb_hp : 1;
- unsigned int man_arb_en : 1;
- unsigned int man_zb : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_arbitration_cfg;
-#define EXTAPB_REGFILE_TMU_ARBITRATION_CFG_RST 0x1
-#define EXTAPB_REGFILE_TMU_ARBITRATION_CFG_ADDR 0x4001d920
-
-
-/* rf_carrier_freq_int register */
-/*----------------------*/
-/* TBD */
-/* rf_carrier_freq_int : TBD */
-#define EXTAPB_REGFILE_TMU_RF_CARRIER_FREQ_INT_RF_CARRIER_FREQ_INT_MASK 0x0fff
-#define EXTAPB_REGFILE_TMU_RF_CARRIER_FREQ_INT_RF_CARRIER_FREQ_INT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rf_carrier_freq_int : 12;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_rf_carrier_freq_int;
-#define EXTAPB_REGFILE_TMU_RF_CARRIER_FREQ_INT_RST 0x0
-#define EXTAPB_REGFILE_TMU_RF_CARRIER_FREQ_INT_ADDR 0x4001d924
-
-
-/* rf_carrier_freq_frac register */
-/*----------------------*/
-/* TBD */
-/* rf_carrier_freq_frac : TBD */
-#define EXTAPB_REGFILE_TMU_RF_CARRIER_FREQ_FRAC_RF_CARRIER_FREQ_FRAC_MASK 0x3fff
-#define EXTAPB_REGFILE_TMU_RF_CARRIER_FREQ_FRAC_RF_CARRIER_FREQ_FRAC_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rf_carrier_freq_frac : 14;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_rf_carrier_freq_frac;
-#define EXTAPB_REGFILE_TMU_RF_CARRIER_FREQ_FRAC_RST 0x0
-#define EXTAPB_REGFILE_TMU_RF_CARRIER_FREQ_FRAC_ADDR 0x4001d928
-
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
- /* ES1 if explicitly configured */
-#else
- /* ES2 default */
-/* comparator_post_pll register */
-/*----------------------*/
-/* [ES2] Time window between the start of the power-down sequence and the de-assertion of the PLL group signals. Unit = 0.5 us */
-/* comparator_post : See register description. */
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_PLL_COMPARATOR_POST_MASK 0x07ff
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_PLL_COMPARATOR_POST_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int comparator_post : 11;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tmu_comparator_post_pll;
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_PLL_RST 0x0
-#define EXTAPB_REGFILE_TMU_COMPARATOR_POST_PLL_ADDR 0x4001d92c
-#endif
-
-typedef struct{
- t_extapb_regfile_tmu_mode_ctrl mode_ctrl;
- t_extapb_regfile_tmu_mode_ctrl_2 mode_ctrl_2;
- t_extapb_regfile_tmu_mode_ctrl_3 mode_ctrl_3;
- t_extapb_regfile_tmu_mode_ctrl_src mode_ctrl_src;
- t_extapb_regfile_tmu_pre_tx pre_tx;
- t_extapb_regfile_tmu_post_tx post_tx;
- t_extapb_regfile_tmu_pre_rx pre_rx;
- t_extapb_regfile_tmu_post_rx post_rx;
- t_extapb_regfile_tmu_status status;
- t_extapb_regfile_tmu_cal_status cal_status;
- t_extapb_regfile_tmu_cal_status1 cal_status1;
- t_extapb_regfile_tmu_cal_status2 cal_status2;
- t_extapb_regfile_tmu_global_status global_status;
- t_extapb_regfile_tmu_clk_override clk_override;
- t_extapb_regfile_tmu_rx_sync_found_timeout rx_sync_found_timeout;
- t_extapb_regfile_tmu_rfp_tmu_intstat rfp_tmu_intstat;
- t_extapb_regfile_tmu_rfp_tmu_intsetstat rfp_tmu_intsetstat;
- t_extapb_regfile_tmu_rfp_tmu_intclrstat rfp_tmu_intclrstat;
- t_extapb_regfile_tmu_rfp_tmu_inten rfp_tmu_inten;
- t_extapb_regfile_tmu_rfp_tmu_power_intstat rfp_tmu_power_intstat;
- t_extapb_regfile_tmu_rfp_tmu_power_intsetstat rfp_tmu_power_intsetstat;
- t_extapb_regfile_tmu_rfp_tmu_power_intclrstat rfp_tmu_power_intclrstat;
- t_extapb_regfile_tmu_rfp_tmu_power_inten rfp_tmu_power_inten;
- t_extapb_regfile_tmu_rfp_tmu_cal_intstat rfp_tmu_cal_intstat;
- t_extapb_regfile_tmu_rfp_tmu_cal_intsetstat rfp_tmu_cal_intsetstat;
- t_extapb_regfile_tmu_rfp_tmu_cal_intclrstat rfp_tmu_cal_intclrstat;
- t_extapb_regfile_tmu_rfp_tmu_cal_inten rfp_tmu_cal_inten;
- t_extapb_regfile_tmu_triggers triggers;
- t_extapb_regfile_tmu_cal_triggers cal_triggers;
- t_extapb_regfile_tmu_kmod_cal_triggers kmod_cal_triggers;
- t_extapb_regfile_tmu_synth_cal_triggers synth_cal_triggers;
- t_extapb_regfile_tmu_synth_cal_cfg synth_cal_cfg;
- t_extapb_regfile_tmu_cal_mode cal_mode;
- t_extapb_regfile_tmu_synth_cal_pll_vco_rst_window synth_cal_pll_vco_rst_window;
- t_extapb_regfile_tmu_synth_cal_pll_lock_aac_pch_treshold synth_cal_pll_lock_aac_pch_treshold;
- t_extapb_regfile_tmu_synth_cal_pll_lock_aac_lock_treshold synth_cal_pll_lock_aac_lock_treshold;
- t_extapb_regfile_tmu_synth_cal_pll_lock_treshold_1 synth_cal_pll_lock_treshold_1;
- t_extapb_regfile_tmu_synth_cal_pll_lock_treshold_2 synth_cal_pll_lock_treshold_2;
- t_extapb_regfile_tmu_synth_cal_pll_lock_treshold_3 synth_cal_pll_lock_treshold_3;
- t_extapb_regfile_tmu_dco_cal_gain_switch_settling_time dco_cal_gain_switch_settling_time;
- t_extapb_regfile_tmu_dco_cal_fine_cal_pause dco_cal_fine_cal_pause;
- t_extapb_regfile_tmu_comparator_pre_g1 comparator_pre_g1;
- t_extapb_regfile_tmu_comparator_post_g1 comparator_post_g1;
- t_extapb_regfile_tmu_comparator_pre_g2 comparator_pre_g2;
- t_extapb_regfile_tmu_comparator_post_g2 comparator_post_g2;
- t_extapb_regfile_tmu_comparator_pre_tx1 comparator_pre_tx1;
- t_extapb_regfile_tmu_comparator_post_tx1 comparator_post_tx1;
- t_extapb_regfile_tmu_comparator_pre_tx2 comparator_pre_tx2;
- t_extapb_regfile_tmu_comparator_post_tx2 comparator_post_tx2;
- t_extapb_regfile_tmu_comparator_pre_tx3 comparator_pre_tx3;
- t_extapb_regfile_tmu_comparator_post_tx3 comparator_post_tx3;
- t_extapb_regfile_tmu_comparator_pre_rx1 comparator_pre_rx1;
- t_extapb_regfile_tmu_comparator_post_rx1 comparator_post_rx1;
- t_extapb_regfile_tmu_comparator_pre_rx2 comparator_pre_rx2;
- t_extapb_regfile_tmu_comparator_post_rx2 comparator_post_rx2;
- t_extapb_regfile_tmu_comparator_pre_rx3 comparator_pre_rx3;
- t_extapb_regfile_tmu_comparator_post_rx3 comparator_post_rx3;
- t_extapb_regfile_tmu_comparator_packet_start comparator_packet_start;
- t_extapb_regfile_tmu_comparator_pre_dp_reset comparator_pre_dp_reset;
- t_extapb_regfile_tmu_comparator_post_dp_reset comparator_post_dp_reset;
- t_extapb_regfile_tmu_comparator_pa_rampup comparator_pa_rampup;
- t_extapb_regfile_tmu_comparator_pll_on comparator_pll_on;
- t_extapb_regfile_tmu_reset_mask reset_mask;
- t_extapb_regfile_tmu_pa_mask pa_mask;
- t_extapb_regfile_tmu_rfp_agc_intstat rfp_agc_intstat;
- t_extapb_regfile_tmu_rfp_agc_intsetstat rfp_agc_intsetstat;
- t_extapb_regfile_tmu_rfp_agc_intclrstat rfp_agc_intclrstat;
- t_extapb_regfile_tmu_rfp_agc_inten rfp_agc_inten;
- t_extapb_regfile_tmu_pa_cal_delay1 pa_cal_delay1;
- t_extapb_regfile_tmu_pa_cal_delay2 pa_cal_delay2;
- t_extapb_regfile_tmu_pa_cal_delay3 pa_cal_delay3;
- t_extapb_regfile_tmu_pa_cal_meas_window pa_cal_meas_window;
- t_extapb_regfile_tmu_arbitration_cfg arbitration_cfg;
- t_extapb_regfile_tmu_rf_carrier_freq_int rf_carrier_freq_int;
- t_extapb_regfile_tmu_rf_carrier_freq_frac rf_carrier_freq_frac;
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
- /* ES1 if explicitly configured */
-#else
- /* ES2 default */
- t_extapb_regfile_tmu_comparator_post_pll comparator_post_pll;
-#endif
-} t_extapb_regfile_tmu;
-#define EXTAPB_REGFILE_TMU_ADDR 0x4001d800
-#define EXTAPB_REGFILE_TMU ((t_extapb_regfile_tmu *)EXTAPB_REGFILE_TMU_ADDR)
-
-
-/* synth_control module */
-/*-------------------------*/
-
-
-/* cfg register */
-/*----------------------*/
-/* Configuration */
-/* cw_mode : Configures the CW mode for the synthesizer */
-/* output_edge : Configures the output edge of the samples towards the PLL divider. */
-/* zoh_en : Configures whether the ZOH is enabled at the CDC (to deal with the 32 MHz synthesizer clock) */
-/* div_second_point : Control for second point divider function */
-/* delay_second_point_super_fine : Control for second point fine delay */
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_CW_MODE_MASK 0x0001
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_CW_MODE_POS 0
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_CW_MODE_INPUT_VAL 0
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_CW_MODE_INPUT_VAL_MASK 0x0
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_CW_MODE_FIXED_VAL 1
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_CW_MODE_FIXED_VAL_MASK 0x1
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_OUTPUT_EDGE_MASK 0x0002
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_OUTPUT_EDGE_POS 1
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_OUTPUT_EDGE_RISING_EDGE 0
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_OUTPUT_EDGE_RISING_EDGE_MASK 0x0
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_OUTPUT_EDGE_FALLING_EDGE 1
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_OUTPUT_EDGE_FALLING_EDGE_MASK 0x2
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_ZOH_EN_MASK 0x0004
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_ZOH_EN_POS 2
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_DIV_SECOND_POINT_MASK 0x0018
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_DIV_SECOND_POINT_POS 3
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_DIV_SECOND_POINT_DIV0 0
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_DIV_SECOND_POINT_DIV0_MASK 0x0
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_DIV_SECOND_POINT_DIV1 1
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_DIV_SECOND_POINT_DIV1_MASK 0x8
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_DIV_SECOND_POINT_DIV2 2
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_DIV_SECOND_POINT_DIV2_MASK 0x10
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_DIV_SECOND_POINT_DIV3 3
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_DIV_SECOND_POINT_DIV3_MASK 0x18
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_DELAY_SECOND_POINT_SUPER_FINE_MASK 0x0060
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_DELAY_SECOND_POINT_SUPER_FINE_POS 5
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_DELAY_SECOND_POINT_SUPER_FINE_DELAY0 0
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_DELAY_SECOND_POINT_SUPER_FINE_DELAY0_MASK 0x0
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_DELAY_SECOND_POINT_SUPER_FINE_DELAY1 1
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_DELAY_SECOND_POINT_SUPER_FINE_DELAY1_MASK 0x20
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_DELAY_SECOND_POINT_SUPER_FINE_DELAY2 2
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_DELAY_SECOND_POINT_SUPER_FINE_DELAY2_MASK 0x40
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_DELAY_SECOND_POINT_SUPER_FINE_DELAY3 3
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_DELAY_SECOND_POINT_SUPER_FINE_DELAY3_MASK 0x60
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int cw_mode : 1;
- unsigned int output_edge : 1;
- unsigned int zoh_en : 1;
- unsigned int div_second_point : 2;
- unsigned int delay_second_point_super_fine : 2;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_synth_control_cfg;
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_RST 0x8
-#define EXTAPB_REGFILE_SYNTH_CONTROL_CFG_ADDR 0x4001d980
-
-
-/* fcw_frac register */
-/*----------------------*/
-/* Frequency control word : fractional bits */
-/* fcw_frac : Fractional bits (16) of frequency control word */
-#define EXTAPB_REGFILE_SYNTH_CONTROL_FCW_FRAC_FCW_FRAC_MASK 0xffff
-#define EXTAPB_REGFILE_SYNTH_CONTROL_FCW_FRAC_FCW_FRAC_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int fcw_frac : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_synth_control_fcw_frac;
-#define EXTAPB_REGFILE_SYNTH_CONTROL_FCW_FRAC_RST 0x0
-#define EXTAPB_REGFILE_SYNTH_CONTROL_FCW_FRAC_ADDR 0x4001d984
-
-
-/* fcw_int register */
-/*----------------------*/
-/* Frequency control word: integer bits */
-/* fcw_int : Integer bits (8) of frequency control word */
-#define EXTAPB_REGFILE_SYNTH_CONTROL_FCW_INT_FCW_INT_MASK 0x00ff
-#define EXTAPB_REGFILE_SYNTH_CONTROL_FCW_INT_FCW_INT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int fcw_int : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_synth_control_fcw_int;
-#define EXTAPB_REGFILE_SYNTH_CONTROL_FCW_INT_RST 0x2
-#define EXTAPB_REGFILE_SYNTH_CONTROL_FCW_INT_ADDR 0x4001d988
-
-
-typedef struct{
- t_extapb_regfile_synth_control_cfg cfg;
- t_extapb_regfile_synth_control_fcw_frac fcw_frac;
- t_extapb_regfile_synth_control_fcw_int fcw_int;
-} t_extapb_regfile_synth_control;
-#define EXTAPB_REGFILE_SYNTH_CONTROL_ADDR 0x4001d980
-#define EXTAPB_REGFILE_SYNTH_CONTROL ((t_extapb_regfile_synth_control *)EXTAPB_REGFILE_SYNTH_CONTROL_ADDR)
-
-
-/* tone_control module */
-/*-------------------------*/
-
-
-/* cfg register */
-/*----------------------*/
-/* Configuration */
-/* cw_mode : Configures the CW mode for the tone generator */
-/* output_edge : Configures the output edge of the samples towards the PLL divider. */
-/* zoh_en : Configures whether the ZOH is enabled at the CDC (to deal with the 32 MHz synthesizer clock) */
-/* div_second_point : Control for second point divider function */
-/* delay_second_point_super_fine : Control for second point fine delay */
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_CW_MODE_MASK 0x0001
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_CW_MODE_POS 0
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_CW_MODE_INPUT_VAL 0
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_CW_MODE_INPUT_VAL_MASK 0x0
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_CW_MODE_FIXED_VAL 1
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_CW_MODE_FIXED_VAL_MASK 0x1
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_OUTPUT_EDGE_MASK 0x0002
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_OUTPUT_EDGE_POS 1
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_OUTPUT_EDGE_RISING_EDGE 0
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_OUTPUT_EDGE_RISING_EDGE_MASK 0x0
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_OUTPUT_EDGE_FALLING_EDGE 1
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_OUTPUT_EDGE_FALLING_EDGE_MASK 0x2
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_ZOH_EN_MASK 0x0004
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_ZOH_EN_POS 2
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_DIV_SECOND_POINT_MASK 0x0018
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_DIV_SECOND_POINT_POS 3
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_DIV_SECOND_POINT_DIV0 0
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_DIV_SECOND_POINT_DIV0_MASK 0x0
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_DIV_SECOND_POINT_DIV1 1
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_DIV_SECOND_POINT_DIV1_MASK 0x8
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_DIV_SECOND_POINT_DIV2 2
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_DIV_SECOND_POINT_DIV2_MASK 0x10
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_DIV_SECOND_POINT_DIV3 3
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_DIV_SECOND_POINT_DIV3_MASK 0x18
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_DELAY_SECOND_POINT_SUPER_FINE_MASK 0x0060
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_DELAY_SECOND_POINT_SUPER_FINE_POS 5
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_DELAY_SECOND_POINT_SUPER_FINE_DELAY0 0
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_DELAY_SECOND_POINT_SUPER_FINE_DELAY0_MASK 0x0
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_DELAY_SECOND_POINT_SUPER_FINE_DELAY1 1
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_DELAY_SECOND_POINT_SUPER_FINE_DELAY1_MASK 0x20
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_DELAY_SECOND_POINT_SUPER_FINE_DELAY2 2
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_DELAY_SECOND_POINT_SUPER_FINE_DELAY2_MASK 0x40
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_DELAY_SECOND_POINT_SUPER_FINE_DELAY3 3
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_DELAY_SECOND_POINT_SUPER_FINE_DELAY3_MASK 0x60
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int cw_mode : 1;
- unsigned int output_edge : 1;
- unsigned int zoh_en : 1;
- unsigned int div_second_point : 2;
- unsigned int delay_second_point_super_fine : 2;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tone_control_cfg;
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_RST 0x8
-#define EXTAPB_REGFILE_TONE_CONTROL_CFG_ADDR 0x4001d9c0
-
-
-/* fcw_frac register */
-/*----------------------*/
-/* Frequency control word : fractional bits */
-/* fcw_frac : Fractional bits (16) of frequency control word */
-#define EXTAPB_REGFILE_TONE_CONTROL_FCW_FRAC_FCW_FRAC_MASK 0xffff
-#define EXTAPB_REGFILE_TONE_CONTROL_FCW_FRAC_FCW_FRAC_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int fcw_frac : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tone_control_fcw_frac;
-#define EXTAPB_REGFILE_TONE_CONTROL_FCW_FRAC_RST 0x0
-#define EXTAPB_REGFILE_TONE_CONTROL_FCW_FRAC_ADDR 0x4001d9c4
-
-
-/* fcw_int register */
-/*----------------------*/
-/* Frequency control word: integer bits */
-/* fcw_int : Integer bits (8) of frequency control word */
-#define EXTAPB_REGFILE_TONE_CONTROL_FCW_INT_FCW_INT_MASK 0x00ff
-#define EXTAPB_REGFILE_TONE_CONTROL_FCW_INT_FCW_INT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int fcw_int : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_tone_control_fcw_int;
-#define EXTAPB_REGFILE_TONE_CONTROL_FCW_INT_RST 0x2
-#define EXTAPB_REGFILE_TONE_CONTROL_FCW_INT_ADDR 0x4001d9c8
-
-
-typedef struct{
- t_extapb_regfile_tone_control_cfg cfg;
- t_extapb_regfile_tone_control_fcw_frac fcw_frac;
- t_extapb_regfile_tone_control_fcw_int fcw_int;
-} t_extapb_regfile_tone_control;
-#define EXTAPB_REGFILE_TONE_CONTROL_ADDR 0x4001d9c0
-#define EXTAPB_REGFILE_TONE_CONTROL ((t_extapb_regfile_tone_control *)EXTAPB_REGFILE_TONE_CONTROL_ADDR)
-
-
-/* snap module */
-/*-------------------------*/
-
-
-/* disable_mask register */
-/*----------------------*/
-/* Snap/Snack will hang if a clock is missing. This register allows to disable Snap/Snack for specific clock domains. */
-/* ref_clk : Ref clock */
-/* rx_bb_clk : Rx BB clock */
-#define EXTAPB_REGFILE_SNAP_DISABLE_MASK_REF_CLK_MASK 0x0001
-#define EXTAPB_REGFILE_SNAP_DISABLE_MASK_REF_CLK_POS 0
-#define EXTAPB_REGFILE_SNAP_DISABLE_MASK_RX_BB_CLK_MASK 0x0002
-#define EXTAPB_REGFILE_SNAP_DISABLE_MASK_RX_BB_CLK_POS 1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int ref_clk : 1;
- unsigned int rx_bb_clk : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_snap_disable_mask;
-#define EXTAPB_REGFILE_SNAP_DISABLE_MASK_RST 0x2
-#define EXTAPB_REGFILE_SNAP_DISABLE_MASK_ADDR 0x4001da00
-
-
-typedef struct{
- t_extapb_regfile_snap_disable_mask disable_mask;
-} t_extapb_regfile_snap;
-#define EXTAPB_REGFILE_SNAP_ADDR 0x4001da00
-#define EXTAPB_REGFILE_SNAP ((t_extapb_regfile_snap *)EXTAPB_REGFILE_SNAP_ADDR)
-
-
-/* apbm module */
-/*-------------------------*/
-
-
-/* address_lsb register */
-/*----------------------*/
-/* APB master address (LSB) */
-/* address_lsb : Address value (LSB) */
-#define EXTAPB_REGFILE_APBM_ADDRESS_LSB_ADDRESS_LSB_MASK 0xffff
-#define EXTAPB_REGFILE_APBM_ADDRESS_LSB_ADDRESS_LSB_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int address_lsb : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_apbm_address_lsb;
-#define EXTAPB_REGFILE_APBM_ADDRESS_LSB_RST 0x0
-#define EXTAPB_REGFILE_APBM_ADDRESS_LSB_ADDR 0x4001da20
-
-
-/* address_msb register */
-/*----------------------*/
-/* APB master address (MSB) */
-/* address_msb : Address value (MSB) */
-#define EXTAPB_REGFILE_APBM_ADDRESS_MSB_ADDRESS_MSB_MASK 0x0003
-#define EXTAPB_REGFILE_APBM_ADDRESS_MSB_ADDRESS_MSB_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int address_msb : 2;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_apbm_address_msb;
-#define EXTAPB_REGFILE_APBM_ADDRESS_MSB_RST 0x0
-#define EXTAPB_REGFILE_APBM_ADDRESS_MSB_ADDR 0x4001da24
-
-
-/* access_cfg register */
-/*----------------------*/
-/* APB master access configuration */
-/* clock_enable : Clock enable */
-/* cmd_t : Command toggle */
-/* write_en : Write enable */
-#define EXTAPB_REGFILE_APBM_ACCESS_CFG_CLOCK_ENABLE_MASK 0x0001
-#define EXTAPB_REGFILE_APBM_ACCESS_CFG_CLOCK_ENABLE_POS 0
-#define EXTAPB_REGFILE_APBM_ACCESS_CFG_CMD_T_MASK 0x0002
-#define EXTAPB_REGFILE_APBM_ACCESS_CFG_CMD_T_POS 1
-#define EXTAPB_REGFILE_APBM_ACCESS_CFG_WRITE_EN_MASK 0x0004
-#define EXTAPB_REGFILE_APBM_ACCESS_CFG_WRITE_EN_POS 2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int clock_enable : 1;
- unsigned int cmd_t : 1;
- unsigned int write_en : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_apbm_access_cfg;
-#define EXTAPB_REGFILE_APBM_ACCESS_CFG_RST 0x0
-#define EXTAPB_REGFILE_APBM_ACCESS_CFG_ADDR 0x4001da28
-
-
-/* wdata_lsb register */
-/*----------------------*/
-/* Write data (LSB part) */
-/* wdata_lsb : Write data (LSB part) */
-#define EXTAPB_REGFILE_APBM_WDATA_LSB_WDATA_LSB_MASK 0xffff
-#define EXTAPB_REGFILE_APBM_WDATA_LSB_WDATA_LSB_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int wdata_lsb : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_apbm_wdata_lsb;
-#define EXTAPB_REGFILE_APBM_WDATA_LSB_RST 0x0
-#define EXTAPB_REGFILE_APBM_WDATA_LSB_ADDR 0x4001da2c
-
-
-/* wdata_msb register */
-/*----------------------*/
-/* Write data (MSB part) */
-/* wdata_msb : Write data (MSB part) */
-#define EXTAPB_REGFILE_APBM_WDATA_MSB_WDATA_MSB_MASK 0xffff
-#define EXTAPB_REGFILE_APBM_WDATA_MSB_WDATA_MSB_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int wdata_msb : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_apbm_wdata_msb;
-#define EXTAPB_REGFILE_APBM_WDATA_MSB_RST 0x0
-#define EXTAPB_REGFILE_APBM_WDATA_MSB_ADDR 0x4001da30
-
-
-/* rdata_lsb register */
-/*----------------------*/
-/* Read data (LSB part) */
-/* rdata_lsb : Read data (LSB part) */
-#define EXTAPB_REGFILE_APBM_RDATA_LSB_RDATA_LSB_MASK 0xffff
-#define EXTAPB_REGFILE_APBM_RDATA_LSB_RDATA_LSB_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rdata_lsb : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_apbm_rdata_lsb;
-#define EXTAPB_REGFILE_APBM_RDATA_LSB_RST 0x0
-#define EXTAPB_REGFILE_APBM_RDATA_LSB_DYNAMIC true
-#define EXTAPB_REGFILE_APBM_RDATA_LSB_SNAPCLOCK 0
-#define EXTAPB_REGFILE_APBM_RDATA_LSB_ADDR 0x4001da34
-
-
-/* rdata_msb register */
-/*----------------------*/
-/* Read data (MSB part) */
-/* rdata_msb : Read data (MSB part) */
-#define EXTAPB_REGFILE_APBM_RDATA_MSB_RDATA_MSB_MASK 0xffff
-#define EXTAPB_REGFILE_APBM_RDATA_MSB_RDATA_MSB_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rdata_msb : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_apbm_rdata_msb;
-#define EXTAPB_REGFILE_APBM_RDATA_MSB_RST 0x0
-#define EXTAPB_REGFILE_APBM_RDATA_MSB_DYNAMIC true
-#define EXTAPB_REGFILE_APBM_RDATA_MSB_SNAPCLOCK 0
-#define EXTAPB_REGFILE_APBM_RDATA_MSB_ADDR 0x4001da38
-
-
-/* access_status register */
-/*----------------------*/
-/* APB master access status */
-/* ack_t : Acknowledge toggle */
-#define EXTAPB_REGFILE_APBM_ACCESS_STATUS_ACK_T_MASK 0x0001
-#define EXTAPB_REGFILE_APBM_ACCESS_STATUS_ACK_T_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int ack_t : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_apbm_access_status;
-#define EXTAPB_REGFILE_APBM_ACCESS_STATUS_RST 0x0
-#define EXTAPB_REGFILE_APBM_ACCESS_STATUS_DYNAMIC true
-#define EXTAPB_REGFILE_APBM_ACCESS_STATUS_SNAPCLOCK 0
-#define EXTAPB_REGFILE_APBM_ACCESS_STATUS_ADDR 0x4001da3c
-
-
-typedef struct{
- t_extapb_regfile_apbm_address_lsb address_lsb;
- t_extapb_regfile_apbm_address_msb address_msb;
- t_extapb_regfile_apbm_access_cfg access_cfg;
- t_extapb_regfile_apbm_wdata_lsb wdata_lsb;
- t_extapb_regfile_apbm_wdata_msb wdata_msb;
- t_extapb_regfile_apbm_rdata_lsb rdata_lsb;
- t_extapb_regfile_apbm_rdata_msb rdata_msb;
- t_extapb_regfile_apbm_access_status access_status;
-} t_extapb_regfile_apbm;
-#define EXTAPB_REGFILE_APBM_ADDR 0x4001da20
-#define EXTAPB_REGFILE_APBM ((t_extapb_regfile_apbm *)EXTAPB_REGFILE_APBM_ADDR)
-
-
-/* switch_matrix module */
-/*-------------------------*/
-
-
-/* pad_cfg0 register */
-/*----------------------*/
-/* SWM Pad 0 configuration */
-/* mode : Mode configuration for SWM pad */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG0_MODE_MASK 0x00ff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG0_MODE_POS 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG0_MODE_FIXED_0 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG0_MODE_FIXED_0_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG0_MODE_FIXED_1 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG0_MODE_FIXED_1_MASK 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG0_MODE_SWM_XOT_DONE 10
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG0_MODE_SWM_XOT_DONE_MASK 0xa
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG0_MODE_SWM_REF_CLK 15
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG0_MODE_SWM_REF_CLK_MASK 0xf
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG0_MODE_GPIO_0 22
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG0_MODE_GPIO_0_MASK 0x16
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG0_MODE_SWM_TMU_GRP_G1_OUT 23
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG0_MODE_SWM_TMU_GRP_G1_OUT_MASK 0x17
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG0_MODE_SWM_ANT_SWITCH 26
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG0_MODE_SWM_ANT_SWITCH_MASK 0x1a
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG0_MODE_SWM_VCO_LOCK 27
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG0_MODE_SWM_VCO_LOCK_MASK 0x1b
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG0_MODE_SWM_PLL_DIVN_FO_SDM 32
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG0_MODE_SWM_PLL_DIVN_FO_SDM_MASK 0x20
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG0_MODE_SWM_TMU_GRP_PLL_OUT 33
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG0_MODE_SWM_TMU_GRP_PLL_OUT_MASK 0x21
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mode : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_pad_cfg0;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG0_RST 0x16
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG0_ADDR 0x4001da40
-
-
-/* pad_cfg1 register */
-/*----------------------*/
-/* SWM Pad 1 configuration */
-/* mode : Mode configuration for SWM pad */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG1_MODE_MASK 0x00ff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG1_MODE_POS 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG1_MODE_FIXED_0 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG1_MODE_FIXED_0_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG1_MODE_FIXED_1 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG1_MODE_FIXED_1_MASK 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG1_MODE_SWM_REF_CLK 15
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG1_MODE_SWM_REF_CLK_MASK 0xf
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG1_MODE_GPIO_1 22
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG1_MODE_GPIO_1_MASK 0x16
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG1_MODE_SWM_TMU_GRP_G2_OUT 23
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG1_MODE_SWM_TMU_GRP_G2_OUT_MASK 0x17
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG1_MODE_SWM_R_CAL_DONE_CLX 24
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG1_MODE_SWM_R_CAL_DONE_CLX_MASK 0x18
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG1_MODE_SWM_ANT_SWITCH 26
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG1_MODE_SWM_ANT_SWITCH_MASK 0x1a
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG1_MODE_SWM_VCO_LOCK 27
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG1_MODE_SWM_VCO_LOCK_MASK 0x1b
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG1_MODE_SWM_PLL_DIVN_FO_SDM 32
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG1_MODE_SWM_PLL_DIVN_FO_SDM_MASK 0x20
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG1_MODE_SWM_TMU_GRP_PLL_OUT 33
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG1_MODE_SWM_TMU_GRP_PLL_OUT_MASK 0x21
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mode : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_pad_cfg1;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG1_RST 0x16
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG1_ADDR 0x4001da44
-
-
-/* pad_cfg2 register */
-/*----------------------*/
-/* SWM Pad 2 configuration */
-/* mode : Mode configuration for SWM pad */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_MASK 0x00ff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_POS 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_FIXED_0 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_FIXED_0_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_FIXED_1 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_FIXED_1_MASK 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_SWM_SPI_MISO 2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_SWM_SPI_MISO_MASK 0x2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_SWM_DBG_SER_RX_DATA_3 11
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_SWM_DBG_SER_RX_DATA_3_MASK 0xb
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_SWM_DBG_SER_CALIB_DATA_3 12
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_SWM_DBG_SER_CALIB_DATA_3_MASK 0xc
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_SWM_REF_CLK 15
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_SWM_REF_CLK_MASK 0xf
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_SWM_ADC_FS_SER_FRAME 17
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_SWM_ADC_FS_SER_FRAME_MASK 0x11
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_SWM_ADC_HS_SER_DATA_MSB 18
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_SWM_ADC_HS_SER_DATA_MSB_MASK 0x12
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_GPIO_2 22
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_GPIO_2_MASK 0x16
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_SWM_TMU_GRP_RX1_OUT 23
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_SWM_TMU_GRP_RX1_OUT_MASK 0x17
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_SWM_ANT_SWITCH 26
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_SWM_ANT_SWITCH_MASK 0x1a
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_SWM_VCO_LOCK 27
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_SWM_VCO_LOCK_MASK 0x1b
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_SWM_PLL_DIVN_FO_SDM 32
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_SWM_PLL_DIVN_FO_SDM_MASK 0x20
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_SWM_TMU_GRP_PLL_OUT 33
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_MODE_SWM_TMU_GRP_PLL_OUT_MASK 0x21
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mode : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_pad_cfg2;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_RST 0x16
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG2_ADDR 0x4001da48
-
-
-/* pad_cfg3 register */
-/*----------------------*/
-/* SWM Pad 3 configuration */
-/* mode : Mode configuration for SWM pad */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_MODE_MASK 0x00ff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_MODE_POS 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_MODE_FIXED_0 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_MODE_FIXED_0_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_MODE_FIXED_1 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_MODE_FIXED_1_MASK 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_MODE_IP_SWM_DBG_SER_RX_DATA_2 11
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_MODE_IP_SWM_DBG_SER_RX_DATA_2_MASK 0xb
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_MODE_IP_SWM_DBG_SER_CALIB_DATA_2 12
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_MODE_IP_SWM_DBG_SER_CALIB_DATA_2_MASK 0xc
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_MODE_IP_SWM_REF_CLK 15
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_MODE_IP_SWM_REF_CLK_MASK 0xf
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_MODE_IP_SWM_ADC_FS_SER_DATA_4 17
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_MODE_IP_SWM_ADC_FS_SER_DATA_4_MASK 0x11
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_MODE_IP_SWM_ADC_HS_SER_DATA_4 18
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_MODE_IP_SWM_ADC_HS_SER_DATA_4_MASK 0x12
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_MODE_IP_GPIO_3 22
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_MODE_IP_GPIO_3_MASK 0x16
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_MODE_IP_SWM_TMU_GRP_RX2_OUT 23
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_MODE_IP_SWM_TMU_GRP_RX2_OUT_MASK 0x17
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_MODE_IP_SWM_ANT_SWITCH 26
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_MODE_IP_SWM_ANT_SWITCH_MASK 0x1a
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_MODE_IP_SWM_VCO_LOCK 27
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_MODE_IP_SWM_VCO_LOCK_MASK 0x1b
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_MODE_SWM_PLL_DIVN_FO_SDM 32
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_MODE_SWM_PLL_DIVN_FO_SDM_MASK 0x20
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_MODE_SWM_TMU_GRP_PLL_OUT 33
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_MODE_SWM_TMU_GRP_PLL_OUT_MASK 0x21
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mode : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_pad_cfg3;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_RST 0x16
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG3_ADDR 0x4001da4c
-
-
-/* pad_cfg4 register */
-/*----------------------*/
-/* SWM Pad 4 configuration */
-/* mode : Mode configuration for SWM pad */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG4_MODE_MASK 0x00ff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG4_MODE_POS 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG4_MODE_FIXED_0 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG4_MODE_FIXED_0_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG4_MODE_FIXED_1 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG4_MODE_FIXED_1_MASK 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG4_MODE_SWM_SPI_MISO 3
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG4_MODE_SWM_SPI_MISO_MASK 0x3
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG4_MODE_SWM_REF_CLK 15
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG4_MODE_SWM_REF_CLK_MASK 0xf
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG4_MODE_GPIO_4 22
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG4_MODE_GPIO_4_MASK 0x16
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG4_MODE_SWM_ANT_SWITCH 26
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG4_MODE_SWM_ANT_SWITCH_MASK 0x1a
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG4_MODE_SWM_VCO_LOCK 27
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG4_MODE_SWM_VCO_LOCK_MASK 0x1b
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG4_MODE_SWM_PLL_DIVN_FO_SDM 32
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG4_MODE_SWM_PLL_DIVN_FO_SDM_MASK 0x20
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG4_MODE_SWM_TMU_GRP_PLL_OUT 33
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG4_MODE_SWM_TMU_GRP_PLL_OUT_MASK 0x21
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mode : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_pad_cfg4;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG4_RST 0x16
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG4_ADDR 0x4001da50
-
-
-/* pad_cfg5 register */
-/*----------------------*/
-/* SWM Pad 5 configuration */
-/* mode : Mode configuration for SWM pad */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG5_MODE_MASK 0x00ff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG5_MODE_POS 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG5_MODE_FIXED_0 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG5_MODE_FIXED_0_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG5_MODE_FIXED_1 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG5_MODE_FIXED_1_MASK 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG5_MODE_SWM_REF_CLK 15
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG5_MODE_SWM_REF_CLK_MASK 0xf
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG5_MODE_GPIO_5 22
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG5_MODE_GPIO_5_MASK 0x16
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG5_MODE_SWM_ANT_SWITCH 26
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG5_MODE_SWM_ANT_SWITCH_MASK 0x1a
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG5_MODE_SWM_VCO_LOCK 27
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG5_MODE_SWM_VCO_LOCK_MASK 0x1b
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG5_MODE_SWM_PLL_DIVN_FO_SDM 32
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG5_MODE_SWM_PLL_DIVN_FO_SDM_MASK 0x20
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG5_MODE_SWM_TMU_GRP_PLL_OUT 33
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG5_MODE_SWM_TMU_GRP_PLL_OUT_MASK 0x21
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mode : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_pad_cfg5;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG5_RST 0x16
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG5_ADDR 0x4001da54
-
-
-/* pad_cfg6 register */
-/*----------------------*/
-/* SWM Pad 6 configuration */
-/* mode : Mode configuration for SWM pad */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_MASK 0x00ff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_POS 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_FIXED_0 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_FIXED_0_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_FIXED_1 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_FIXED_1_MASK 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_SWM_SPI_MISO 4
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_SWM_SPI_MISO_MASK 0x4
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_SWM_RX_DATA 6
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_SWM_RX_DATA_MASK 0x6
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_SWM_DBG_SER_RX_DATA_1 11
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_SWM_DBG_SER_RX_DATA_1_MASK 0xb
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_SWM_DBG_SER_CALIB_DATA_1 12
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_SWM_DBG_SER_CALIB_DATA_1_MASK 0xc
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_SWM_REF_CLK 15
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_SWM_REF_CLK_MASK 0xf
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_SWM_ADC_FS_SER_DATA_3 17
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_SWM_ADC_FS_SER_DATA_3_MASK 0x11
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_SWM_ADC_HS_SER_DATA_3 18
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_SWM_ADC_HS_SER_DATA_3_MASK 0x12
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_GPIO_6 22
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_GPIO_6_MASK 0x16
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_SWM_TMU_GRP_RX3_OUT 23
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_SWM_TMU_GRP_RX3_OUT_MASK 0x17
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_SWM_ANT_SWITCH 26
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_SWM_ANT_SWITCH_MASK 0x1a
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_SWM_VCO_LOCK 27
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_SWM_VCO_LOCK_MASK 0x1b
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_SWM_PLL_DIVN_FO_SDM 32
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_SWM_PLL_DIVN_FO_SDM_MASK 0x20
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_SWM_TMU_GRP_PLL_OUT 33
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_MODE_SWM_TMU_GRP_PLL_OUT_MASK 0x21
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mode : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_pad_cfg6;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_RST 0x16
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG6_ADDR 0x4001da58
-
-
-/* pad_cfg7 register */
-/*----------------------*/
-/* SWM Pad 7 configuration */
-/* mode : Mode configuration for SWM pad */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_MODE_MASK 0x00ff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_MODE_POS 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_MODE_FIXED_0 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_MODE_FIXED_0_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_MODE_FIXED_1 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_MODE_FIXED_1_MASK 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_MODE_SWM_DBG_SER_RX_DATA_0 11
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_MODE_SWM_DBG_SER_RX_DATA_0_MASK 0xb
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_MODE_SWM_DBG_SER_CALIB_DATA_0 12
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_MODE_SWM_DBG_SER_CALIB_DATA_0_MASK 0xc
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_MODE_SWM_REF_CLK 15
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_MODE_SWM_REF_CLK_MASK 0xf
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_MODE_SWM_ADC_FS_SER_DATA_2 17
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_MODE_SWM_ADC_FS_SER_DATA_2_MASK 0x11
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_MODE_SWM_ADC_HS_SER_DATA_2 18
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_MODE_SWM_ADC_HS_SER_DATA_2_MASK 0x12
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_MODE_GPIO_7 22
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_MODE_GPIO_7_MASK 0x16
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_MODE_SWM_TMU_GRP_TX1_OUT 23
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_MODE_SWM_TMU_GRP_TX1_OUT_MASK 0x17
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_MODE_SWM_ANT_SWITCH 26
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_MODE_SWM_ANT_SWITCH_MASK 0x1a
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_MODE_SWM_VCO_LOCK 27
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_MODE_SWM_VCO_LOCK_MASK 0x1b
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_MODE_SWM_PLL_DIVN_FO_SDM 32
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_MODE_SWM_PLL_DIVN_FO_SDM_MASK 0x20
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_MODE_SWM_TMU_GRP_PLL_OUT 33
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_MODE_SWM_TMU_GRP_PLL_OUT_MASK 0x21
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mode : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_pad_cfg7;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_RST 0x16
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG7_ADDR 0x4001da5c
-
-
-/* pad_cfg8 register */
-/*----------------------*/
-/* SWM Pad 8 configuration */
-/* mode : Mode configuration for SWM pad */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_MASK 0x00ff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_POS 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_FIXED_0 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_FIXED_0_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_FIXED_1 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_FIXED_1_MASK 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_SWM_TX_SYNC_CLX 6
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_SWM_TX_SYNC_CLX_MASK 0x6
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_SWM_XOT_DONE 9
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_SWM_XOT_DONE_MASK 0x9
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_SWM_DBG_SER_RX_FRAME 11
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_SWM_DBG_SER_RX_FRAME_MASK 0xb
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_SWM_DBG_SER_CALIB_FRAME 12
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_SWM_DBG_SER_CALIB_FRAME_MASK 0xc
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_SWM_REF_CLK 15
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_SWM_REF_CLK_MASK 0xf
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_SWM_ADC_FS_SER_DATA_1 17
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_SWM_ADC_FS_SER_DATA_1_MASK 0x11
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_SWM_ADC_HS_SER_DATA_1 18
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_SWM_ADC_HS_SER_DATA_1_MASK 0x12
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_GPIO_8 22
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_GPIO_8_MASK 0x16
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_SWM_TMU_GRP_TX2_OUT 23
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_SWM_TMU_GRP_TX2_OUT_MASK 0x17
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_SWM_ANT_SWITCH 26
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_SWM_ANT_SWITCH_MASK 0x1a
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_SWM_VCO_LOCK 27
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_SWM_VCO_LOCK_MASK 0x1b
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_SWM_PLL_DIVN_FO_SDM 32
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_SWM_PLL_DIVN_FO_SDM_MASK 0x20
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_SWM_TMU_GRP_PLL_OUT 33
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_MODE_SWM_TMU_GRP_PLL_OUT_MASK 0x21
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mode : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_pad_cfg8;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_RST 0x16
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG8_ADDR 0x4001da60
-
-
-/* pad_cfg9 register */
-/*----------------------*/
-/* SWM Pad 9 configuration */
-/* mode : Mode configuration for SWM pad */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_MODE_MASK 0x00ff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_MODE_POS 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_MODE_FIXED_0 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_MODE_FIXED_0_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_MODE_FIXED_1 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_MODE_FIXED_1_MASK 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_MODE_SWM_DBG_SER_RX_CLK 11
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_MODE_SWM_DBG_SER_RX_CLK_MASK 0xb
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_MODE_SWM_DBG_SER_CALIB_CLK 12
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_MODE_SWM_DBG_SER_CALIB_CLK_MASK 0xc
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_MODE_SWM_REF_CLK 15
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_MODE_SWM_REF_CLK_MASK 0xf
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_MODE_SWM_ADC_FS_SER_DATA_0 17
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_MODE_SWM_ADC_FS_SER_DATA_0_MASK 0x11
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_MODE_SWM_ADC_HS_SER_DATA_0 18
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_MODE_SWM_ADC_HS_SER_DATA_0_MASK 0x12
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_MODE_GPIO_9 22
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_MODE_GPIO_9_MASK 0x16
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_MODE_SWM_TMU_GRP_TX3_OUT 23
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_MODE_SWM_TMU_GRP_TX3_OUT_MASK 0x17
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_MODE_SWM_ANT_SWITCH 26
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_MODE_SWM_ANT_SWITCH_MASK 0x1a
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_MODE_SWM_VCO_LOCK 27
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_MODE_SWM_VCO_LOCK_MASK 0x1b
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_MODE_SWM_PLL_DIVN_FO_SDM 32
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_MODE_SWM_PLL_DIVN_FO_SDM_MASK 0x20
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_MODE_SWM_TMU_GRP_PLL_OUT 33
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_MODE_SWM_TMU_GRP_PLL_OUT_MASK 0x21
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mode : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_pad_cfg9;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_RST 0x16
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG9_ADDR 0x4001da64
-
-
-/* pad_cfg10 register */
-/*----------------------*/
-/* SWM Pad 10 configuration */
-/* mode : Mode configuration for SWM pad */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG10_MODE_MASK 0x00ff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG10_MODE_POS 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG10_MODE_FIXED_0 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG10_MODE_FIXED_0_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG10_MODE_FIXED_1 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG10_MODE_FIXED_1_MASK 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG10_MODE_SWM_REF_CLK 15
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG10_MODE_SWM_REF_CLK_MASK 0xf
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG10_MODE_GPIO_10 22
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG10_MODE_GPIO_10_MASK 0x16
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG10_MODE_SWM_ANT_SWITCH 26
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG10_MODE_SWM_ANT_SWITCH_MASK 0x1a
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG10_MODE_SWM_VCO_LOCK 27
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG10_MODE_SWM_VCO_LOCK_MASK 0x1b
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG10_MODE_SWM_PLL_DIVN_FO_SDM 32
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG10_MODE_SWM_PLL_DIVN_FO_SDM_MASK 0x20
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG10_MODE_SWM_TMU_GRP_PLL_OUT 33
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG10_MODE_SWM_TMU_GRP_PLL_OUT_MASK 0x21
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mode : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_pad_cfg10;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG10_RST 0x16
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG10_ADDR 0x4001da68
-
-
-/* pad_cfg11 register */
-/*----------------------*/
-/* SWM Pad 11 configuration */
-/* mode : Mode configuration for SWM pad */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG11_MODE_MASK 0x00ff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG11_MODE_POS 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG11_MODE_FIXED_0 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG11_MODE_FIXED_0_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG11_MODE_FIXED_1 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG11_MODE_FIXED_1_MASK 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG11_MODE_SWM_REF_CLK 15
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG11_MODE_SWM_REF_CLK_MASK 0xf
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG11_MODE_GPIO_11 22
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG11_MODE_GPIO_11_MASK 0x16
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG11_MODE_SWM_ANT_SWITCH 26
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG11_MODE_SWM_ANT_SWITCH_MASK 0x1a
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG11_MODE_SWM_VCO_LOCK 27
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG11_MODE_SWM_VCO_LOCK_MASK 0x1b
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG11_MODE_SWM_PLL_DIVN_FO_SDM 32
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG11_MODE_SWM_PLL_DIVN_FO_SDM_MASK 0x20
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG11_MODE_SWM_TMU_GRP_PLL_OUT 33
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG11_MODE_SWM_TMU_GRP_PLL_OUT_MASK 0x21
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mode : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_pad_cfg11;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG11_RST 0x16
-#define EXTAPB_REGFILE_SWITCH_MATRIX_PAD_CFG11_ADDR 0x4001da6c
-
-
-/* sig_cfg0 register */
-/*----------------------*/
-/* SWM Internal signal configuration - op_swm_spi_clk */
-/* mode : Mode configuration for SWM internal signal */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_MASK 0x00ff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_POS 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_FIXED_0 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_FIXED_0_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_FIXED_1 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_FIXED_1_MASK 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_SWM_00 2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_SWM_00_MASK 0x2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_SWM_01 3
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_SWM_01_MASK 0x3
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_SWM_02 4
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_SWM_02_MASK 0x4
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_SWM_03 5
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_SWM_03_MASK 0x5
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_SWM_04 6
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_SWM_04_MASK 0x6
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_SWM_05 7
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_SWM_05_MASK 0x7
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_SWM_06 8
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_SWM_06_MASK 0x8
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_SWM_07 9
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_SWM_07_MASK 0x9
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_SWM_08 10
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_SWM_08_MASK 0xa
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_SWM_09 11
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_SWM_09_MASK 0xb
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_SWM_10 12
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_SWM_10_MASK 0xc
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_SWM_11 13
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_MODE_SWM_11_MASK 0xd
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mode : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_sig_cfg0;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_RST 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG0_ADDR 0x4001da70
-
-
-/* sig_cfg1 register */
-/*----------------------*/
-/* SWM Internal signal configuration - op_swm_spi_cs_n */
-/* mode : Mode configuration for SWM internal signal */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_MASK 0x00ff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_POS 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_FIXED_0 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_FIXED_0_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_FIXED_1 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_FIXED_1_MASK 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_SWM_00 2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_SWM_00_MASK 0x2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_SWM_01 3
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_SWM_01_MASK 0x3
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_SWM_02 4
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_SWM_02_MASK 0x4
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_SWM_03 5
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_SWM_03_MASK 0x5
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_SWM_04 6
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_SWM_04_MASK 0x6
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_SWM_05 7
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_SWM_05_MASK 0x7
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_SWM_06 8
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_SWM_06_MASK 0x8
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_SWM_07 9
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_SWM_07_MASK 0x9
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_SWM_08 10
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_SWM_08_MASK 0xa
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_SWM_09 11
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_SWM_09_MASK 0xb
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_SWM_10 12
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_SWM_10_MASK 0xc
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_SWM_11 13
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_MODE_SWM_11_MASK 0xd
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mode : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_sig_cfg1;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_RST 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG1_ADDR 0x4001da74
-
-
-/* sig_cfg2 register */
-/*----------------------*/
-/* SWM Internal signal configuration - op_swm_spi_mosi */
-/* mode : Mode configuration for SWM internal signal */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_MASK 0x00ff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_POS 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_FIXED_0 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_FIXED_0_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_FIXED_1 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_FIXED_1_MASK 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_SWM_00 2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_SWM_00_MASK 0x2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_SWM_01 3
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_SWM_01_MASK 0x3
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_SWM_02 4
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_SWM_02_MASK 0x4
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_SWM_03 5
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_SWM_03_MASK 0x5
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_SWM_04 6
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_SWM_04_MASK 0x6
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_SWM_05 7
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_SWM_05_MASK 0x7
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_SWM_06 8
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_SWM_06_MASK 0x8
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_SWM_07 9
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_SWM_07_MASK 0x9
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_SWM_08 10
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_SWM_08_MASK 0xa
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_SWM_09 11
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_SWM_09_MASK 0xb
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_SWM_10 12
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_SWM_10_MASK 0xc
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_SWM_11 13
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_MODE_SWM_11_MASK 0xd
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mode : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_sig_cfg2;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_RST 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG2_ADDR 0x4001da78
-
-
-/* sig_cfg4 register */
-/*----------------------*/
-/* SWM Internal signal configuration - op_swm_ref_clk */
-/* mode : Mode configuration for SWM internal signal */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_MASK 0x00ff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_POS 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_FIXED_0 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_FIXED_0_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_FIXED_1 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_FIXED_1_MASK 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_SWM_00 2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_SWM_00_MASK 0x2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_SWM_01 3
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_SWM_01_MASK 0x3
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_SWM_02 4
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_SWM_02_MASK 0x4
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_SWM_03 5
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_SWM_03_MASK 0x5
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_SWM_04 6
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_SWM_04_MASK 0x6
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_SWM_05 7
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_SWM_05_MASK 0x7
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_SWM_06 8
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_SWM_06_MASK 0x8
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_SWM_07 9
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_SWM_07_MASK 0x9
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_SWM_08 10
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_SWM_08_MASK 0xa
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_SWM_09 11
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_SWM_09_MASK 0xb
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_SWM_10 12
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_SWM_10_MASK 0xc
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_SWM_11 13
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_MODE_SWM_11_MASK 0xd
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mode : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_sig_cfg4;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_RST 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG4_ADDR 0x4001da80
-
-
-/* sig_cfg5 register */
-/*----------------------*/
-/* SWM Internal signal configuration - op_swm_dbg_clk */
-/* mode : Mode configuration for SWM internal signal */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_MASK 0x00ff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_POS 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_FIXED_0 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_FIXED_0_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_FIXED_1 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_FIXED_1_MASK 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_SWM_00 2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_SWM_00_MASK 0x2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_SWM_01 3
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_SWM_01_MASK 0x3
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_SWM_02 4
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_SWM_02_MASK 0x4
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_SWM_03 5
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_SWM_03_MASK 0x5
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_SWM_04 6
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_SWM_04_MASK 0x6
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_SWM_05 7
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_SWM_05_MASK 0x7
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_SWM_06 8
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_SWM_06_MASK 0x8
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_SWM_07 9
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_SWM_07_MASK 0x9
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_SWM_08 10
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_SWM_08_MASK 0xa
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_SWM_09 11
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_SWM_09_MASK 0xb
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_SWM_10 12
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_SWM_10_MASK 0xc
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_SWM_11 13
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_MODE_SWM_11_MASK 0xd
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mode : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_sig_cfg5;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_RST 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG5_ADDR 0x4001da84
-
-
-/* sig_cfg6 register */
-/*----------------------*/
-/* SWM Internal signal configuration - op_swm_hsp_clk */
-/* mode : Mode configuration for SWM internal signal */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_MASK 0x00ff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_POS 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_FIXED_0 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_FIXED_0_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_FIXED_1 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_FIXED_1_MASK 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_SWM_00 2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_SWM_00_MASK 0x2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_SWM_01 3
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_SWM_01_MASK 0x3
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_SWM_02 4
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_SWM_02_MASK 0x4
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_SWM_03 5
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_SWM_03_MASK 0x5
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_SWM_04 6
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_SWM_04_MASK 0x6
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_SWM_05 7
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_SWM_05_MASK 0x7
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_SWM_06 8
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_SWM_06_MASK 0x8
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_SWM_07 9
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_SWM_07_MASK 0x9
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_SWM_08 10
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_SWM_08_MASK 0xa
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_SWM_09 11
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_SWM_09_MASK 0xb
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_SWM_10 12
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_SWM_10_MASK 0xc
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_SWM_11 13
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_MODE_SWM_11_MASK 0xd
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mode : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_sig_cfg6;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_RST 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG6_ADDR 0x4001da88
-
-
-/* sig_cfg7 register */
-/*----------------------*/
-/* SWM Internal signal configuration - op_gpio(11...0) */
-/* mode : Mode configuration for SWM internal signal */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG7_MODE_MASK 0x00ff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG7_MODE_POS 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG7_MODE_FIXED_0 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG7_MODE_FIXED_0_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG7_MODE_FIXED_1 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG7_MODE_FIXED_1_MASK 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG7_MODE_SWM 2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG7_MODE_SWM_MASK 0x2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mode : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_sig_cfg7;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG7_RST 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG7_ADDR 0x4001da8c
-
-
-/* sig_cfg8 register */
-/*----------------------*/
-/* SWM Internal signal configuration - op_swm_r_cal_start_clx */
-/* mode : Mode configuration for SWM internal signal */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_MASK 0x00ff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_POS 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_FIXED_0 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_FIXED_0_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_FIXED_1 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_FIXED_1_MASK 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_SWM_00 2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_SWM_00_MASK 0x2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_SWM_01 3
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_SWM_01_MASK 0x3
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_SWM_02 4
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_SWM_02_MASK 0x4
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_SWM_03 5
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_SWM_03_MASK 0x5
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_SWM_04 6
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_SWM_04_MASK 0x6
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_SWM_05 7
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_SWM_05_MASK 0x7
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_SWM_06 8
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_SWM_06_MASK 0x8
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_SWM_07 9
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_SWM_07_MASK 0x9
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_SWM_08 10
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_SWM_08_MASK 0xa
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_SWM_09 11
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_SWM_09_MASK 0xb
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_SWM_10 12
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_SWM_10_MASK 0xc
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_SWM_11 13
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_MODE_SWM_11_MASK 0xd
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mode : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_sig_cfg8;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_RST 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG8_ADDR 0x4001da90
-
-
-/* sig_cfg11 register */
-/*----------------------*/
-/* SWM Internal signal configuration - op_swm_dac_par(7...0) */
-/* mode : Mode configuration for SWM internal signal */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG11_MODE_MASK 0x00ff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG11_MODE_POS 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG11_MODE_FIXED_0 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG11_MODE_FIXED_0_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG11_MODE_FIXED_1 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG11_MODE_FIXED_1_MASK 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG11_MODE_SWM 2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG11_MODE_SWM_MASK 0x2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mode : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_sig_cfg11;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG11_RST 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG11_ADDR 0x4001da9c
-
-
-/* sig_cfg12 register */
-/*----------------------*/
-/* SWM Internal signal configuration - op_swm_par_pll_divn(7...0) */
-/* mode : Mode configuration for SWM internal signal */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG12_MODE_MASK 0x00ff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG12_MODE_POS 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG12_MODE_FIXED_0 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG12_MODE_FIXED_0_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG12_MODE_FIXED_1 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG12_MODE_FIXED_1_MASK 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG12_MODE_SWM 2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG12_MODE_SWM_MASK 0x2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mode : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_sig_cfg12;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG12_RST 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG12_ADDR 0x4001daa0
-
-
-/* sig_cfg13 register */
-/*----------------------*/
-/* SWM Internal signal configuration - op_swm_xot_start */
-/* mode : Mode configuration for SWM internal signal */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_MASK 0x00ff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_POS 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_FIXED_0 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_FIXED_0_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_FIXED_1 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_FIXED_1_MASK 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_SWM_00 2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_SWM_00_MASK 0x2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_SWM_01 3
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_SWM_01_MASK 0x3
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_SWM_02 4
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_SWM_02_MASK 0x4
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_SWM_03 5
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_SWM_03_MASK 0x5
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_SWM_04 6
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_SWM_04_MASK 0x6
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_SWM_05 7
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_SWM_05_MASK 0x7
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_SWM_06 8
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_SWM_06_MASK 0x8
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_SWM_07 9
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_SWM_07_MASK 0x9
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_SWM_08 10
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_SWM_08_MASK 0xa
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_SWM_09 11
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_SWM_09_MASK 0xb
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_SWM_10 12
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_SWM_10_MASK 0xc
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_SWM_11 13
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_MODE_SWM_11_MASK 0xd
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mode : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_sig_cfg13;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_RST 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG13_ADDR 0x4001daa4
-
-
-/* sig_cfg14 register */
-/*----------------------*/
-/* SWM Internal signal configuration - op_swm_dac_ser_frame */
-/* mode : Mode configuration for SWM internal signal */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_MASK 0x00ff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_POS 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_FIXED_0 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_FIXED_0_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_FIXED_1 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_FIXED_1_MASK 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_SWM_00 2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_SWM_00_MASK 0x2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_SWM_01 3
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_SWM_01_MASK 0x3
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_SWM_02 4
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_SWM_02_MASK 0x4
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_SWM_03 5
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_SWM_03_MASK 0x5
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_SWM_04 6
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_SWM_04_MASK 0x6
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_SWM_05 7
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_SWM_05_MASK 0x7
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_SWM_06 8
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_SWM_06_MASK 0x8
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_SWM_07 9
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_SWM_07_MASK 0x9
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_SWM_08 10
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_SWM_08_MASK 0xa
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_SWM_09 11
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_SWM_09_MASK 0xb
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_SWM_10 12
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_SWM_10_MASK 0xc
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_SWM_11 13
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_MODE_SWM_11_MASK 0xd
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mode : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_sig_cfg14;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_RST 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG14_ADDR 0x4001daa8
-
-
-/* sig_cfg17 register */
-/*----------------------*/
-/* SWM Internal signal configuration - op_swm_xot_clk */
-/* mode : Mode configuration for SWM internal signal */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_MASK 0x00ff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_POS 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_FIXED_0 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_FIXED_0_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_FIXED_1 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_FIXED_1_MASK 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_SWM_00 2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_SWM_00_MASK 0x2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_SWM_01 3
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_SWM_01_MASK 0x3
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_SWM_02 4
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_SWM_02_MASK 0x4
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_SWM_03 5
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_SWM_03_MASK 0x5
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_SWM_04 6
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_SWM_04_MASK 0x6
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_SWM_05 7
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_SWM_05_MASK 0x7
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_SWM_06 8
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_SWM_06_MASK 0x8
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_SWM_07 9
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_SWM_07_MASK 0x9
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_SWM_08 10
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_SWM_08_MASK 0xa
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_SWM_09 11
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_SWM_09_MASK 0xb
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_SWM_10 12
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_SWM_10_MASK 0xc
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_SWM_11 13
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_MODE_SWM_11_MASK 0xd
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mode : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_sig_cfg17;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_RST 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG17_ADDR 0x4001dab4
-
-
-/* sig_cfg18 register */
-/*----------------------*/
-/* SWM Internal signal configuration - op_swm_dac_ser_data(3...0) */
-/* mode : Mode configuration for SWM internal signal */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG18_MODE_MASK 0x00ff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG18_MODE_POS 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG18_MODE_FIXED_0 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG18_MODE_FIXED_0_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG18_MODE_FIXED_1 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG18_MODE_FIXED_1_MASK 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG18_MODE_SWM 2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG18_MODE_SWM_MASK 0x2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int mode : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_sig_cfg18;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG18_RST 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SIG_CFG18_ADDR 0x4001dab8
-
-
-/* dcb_cfg register */
-/*----------------------*/
-/* DCB configuration */
-/* rf_dcb0 : Enable RF DCB0 */
-/* rf_dcb1 : Enable RF DCB1 */
-/* pmu_dcb0 : Enable PMU DCB0 */
-/* pmu_dcb1 : Enable PMU DCB1 */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_DCB_CFG_RF_DCB0_MASK 0x0001
-#define EXTAPB_REGFILE_SWITCH_MATRIX_DCB_CFG_RF_DCB0_POS 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_DCB_CFG_RF_DCB0_DISABLE 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_DCB_CFG_RF_DCB0_DISABLE_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_DCB_CFG_RF_DCB0_ENABLE 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_DCB_CFG_RF_DCB0_ENABLE_MASK 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_DCB_CFG_RF_DCB1_MASK 0x0002
-#define EXTAPB_REGFILE_SWITCH_MATRIX_DCB_CFG_RF_DCB1_POS 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_DCB_CFG_RF_DCB1_DISABLE 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_DCB_CFG_RF_DCB1_DISABLE_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_DCB_CFG_RF_DCB1_ENABLE 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_DCB_CFG_RF_DCB1_ENABLE_MASK 0x2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_DCB_CFG_PMU_DCB0_MASK 0x0004
-#define EXTAPB_REGFILE_SWITCH_MATRIX_DCB_CFG_PMU_DCB0_POS 2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_DCB_CFG_PMU_DCB0_DISABLE 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_DCB_CFG_PMU_DCB0_DISABLE_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_DCB_CFG_PMU_DCB0_ENABLE 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_DCB_CFG_PMU_DCB0_ENABLE_MASK 0x4
-#define EXTAPB_REGFILE_SWITCH_MATRIX_DCB_CFG_PMU_DCB1_MASK 0x0008
-#define EXTAPB_REGFILE_SWITCH_MATRIX_DCB_CFG_PMU_DCB1_POS 3
-#define EXTAPB_REGFILE_SWITCH_MATRIX_DCB_CFG_PMU_DCB1_DISABLE 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_DCB_CFG_PMU_DCB1_DISABLE_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_DCB_CFG_PMU_DCB1_ENABLE 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_DCB_CFG_PMU_DCB1_ENABLE_MASK 0x8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int rf_dcb0 : 1;
- unsigned int rf_dcb1 : 1;
- unsigned int pmu_dcb0 : 1;
- unsigned int pmu_dcb1 : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_dcb_cfg;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_DCB_CFG_RST 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_DCB_CFG_ADDR 0x4001dac8
-
-
-/* reserved_out register */
-/*----------------------*/
-/* Reserved OUT */
-/* value : reserved vector */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_RESERVED_OUT_VALUE_MASK 0xffff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_RESERVED_OUT_VALUE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int value : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_reserved_out;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_RESERVED_OUT_RST 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_RESERVED_OUT_ADDR 0x4001dacc
-
-
-/* reserved_in register */
-/*----------------------*/
-/* Reserved IN */
-/* value : reserved vector */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_RESERVED_IN_VALUE_MASK 0xffff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_RESERVED_IN_VALUE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int value : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_reserved_in;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_RESERVED_IN_RST 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_RESERVED_IN_DYNAMIC true
-#define EXTAPB_REGFILE_SWITCH_MATRIX_RESERVED_IN_SNAPCLOCK 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_RESERVED_IN_ADDR 0x4001dad0
-
-
-/* override_out register */
-/*----------------------*/
-/* This register represents an override for each SWM output pin in the toplevel switch matrix. When the corresponding bit in this register has been set to '1', the corresponding configuration will be forced upon the toplevel switch matrix. */
-/* value : empty */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_OVERRIDE_OUT_VALUE_MASK 0x0fff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_OVERRIDE_OUT_VALUE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int value : 12;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_override_out;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_OVERRIDE_OUT_RST 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_OVERRIDE_OUT_ADDR 0x4001dad4
-
-
-/* spi_location register */
-/*----------------------*/
-/* empty */
-/* value : empty */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SPI_LOCATION_VALUE_MASK 0x0003
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SPI_LOCATION_VALUE_POS 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SPI_LOCATION_VALUE_SPI_LOC_0 0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SPI_LOCATION_VALUE_SPI_LOC_0_MASK 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SPI_LOCATION_VALUE_SPI_LOC_1 1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SPI_LOCATION_VALUE_SPI_LOC_1_MASK 0x1
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SPI_LOCATION_VALUE_SPI_LOC_2 2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SPI_LOCATION_VALUE_SPI_LOC_2_MASK 0x2
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SPI_LOCATION_VALUE_SPI_LOC_3 3
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SPI_LOCATION_VALUE_SPI_LOC_3_MASK 0x3
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int value : 2;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_spi_location;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SPI_LOCATION_RST 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_SPI_LOCATION_ADDR 0x4001dad8
-
-
-/* ana_enable register */
-/*----------------------*/
-/* empty */
-/* value : empty */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_ANA_ENABLE_VALUE_MASK 0x000f
-#define EXTAPB_REGFILE_SWITCH_MATRIX_ANA_ENABLE_VALUE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int value : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_ana_enable;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_ANA_ENABLE_RST 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_ANA_ENABLE_ADDR 0x4001dadc
-
-
-/* ehs0 register */
-/*----------------------*/
-/* Enable PAD low speed. To be used in conjunction with EHS1. Low speed: EHS1='0',EHS0='1'. Nominal speed: EHS1='0',EHS0='0'. High speed: EHS1='1'. */
-/* value : empty */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_EHS0_VALUE_MASK 0x0fff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_EHS0_VALUE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int value : 12;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_ehs0;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_EHS0_RST 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_EHS0_ADDR 0x4001dae0
-
-
-/* ehs1 register */
-/*----------------------*/
-/* Enable PAD high speed. To be used in conjunction with EHS0. Low speed: EHS1='0',EHS0='1'. Nominal speed: EHS1='0',EHS0='0'. High speed: EHS1='1'. */
-/* value : empty */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_EHS1_VALUE_MASK 0x0fff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_EHS1_VALUE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int value : 12;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_ehs1;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_EHS1_RST 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_EHS1_ADDR 0x4001dae4
-
-
-/* override_in register */
-/*----------------------*/
-/* This register represents an override for each SWM input pin in the toplevel switch matrix. When the corresponding bit in this register has been set to '1', the corresponding configuration will be forced upon the toplevel switch matrix. */
-/* value : empty */
-#define EXTAPB_REGFILE_SWITCH_MATRIX_OVERRIDE_IN_VALUE_MASK 0x0fff
-#define EXTAPB_REGFILE_SWITCH_MATRIX_OVERRIDE_IN_VALUE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int value : 12;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_switch_matrix_override_in;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_OVERRIDE_IN_RST 0x0
-#define EXTAPB_REGFILE_SWITCH_MATRIX_OVERRIDE_IN_ADDR 0x4001dae8
-
-
-typedef struct{
- t_extapb_regfile_switch_matrix_pad_cfg0 pad_cfg0;
- t_extapb_regfile_switch_matrix_pad_cfg1 pad_cfg1;
- t_extapb_regfile_switch_matrix_pad_cfg2 pad_cfg2;
- t_extapb_regfile_switch_matrix_pad_cfg3 pad_cfg3;
- t_extapb_regfile_switch_matrix_pad_cfg4 pad_cfg4;
- t_extapb_regfile_switch_matrix_pad_cfg5 pad_cfg5;
- t_extapb_regfile_switch_matrix_pad_cfg6 pad_cfg6;
- t_extapb_regfile_switch_matrix_pad_cfg7 pad_cfg7;
- t_extapb_regfile_switch_matrix_pad_cfg8 pad_cfg8;
- t_extapb_regfile_switch_matrix_pad_cfg9 pad_cfg9;
- t_extapb_regfile_switch_matrix_pad_cfg10 pad_cfg10;
- t_extapb_regfile_switch_matrix_pad_cfg11 pad_cfg11;
- t_extapb_regfile_switch_matrix_sig_cfg0 sig_cfg0;
- t_extapb_regfile_switch_matrix_sig_cfg1 sig_cfg1;
- t_extapb_regfile_switch_matrix_sig_cfg2 sig_cfg2;
- unsigned int reserved0[1];
- t_extapb_regfile_switch_matrix_sig_cfg4 sig_cfg4;
- t_extapb_regfile_switch_matrix_sig_cfg5 sig_cfg5;
- t_extapb_regfile_switch_matrix_sig_cfg6 sig_cfg6;
- t_extapb_regfile_switch_matrix_sig_cfg7 sig_cfg7;
- t_extapb_regfile_switch_matrix_sig_cfg8 sig_cfg8;
- unsigned int reserved1[2];
- t_extapb_regfile_switch_matrix_sig_cfg11 sig_cfg11;
- t_extapb_regfile_switch_matrix_sig_cfg12 sig_cfg12;
- t_extapb_regfile_switch_matrix_sig_cfg13 sig_cfg13;
- t_extapb_regfile_switch_matrix_sig_cfg14 sig_cfg14;
- unsigned int reserved2[2];
- t_extapb_regfile_switch_matrix_sig_cfg17 sig_cfg17;
- t_extapb_regfile_switch_matrix_sig_cfg18 sig_cfg18;
- unsigned int reserved3[3];
- t_extapb_regfile_switch_matrix_dcb_cfg dcb_cfg;
- t_extapb_regfile_switch_matrix_reserved_out reserved_out;
- t_extapb_regfile_switch_matrix_reserved_in reserved_in;
- t_extapb_regfile_switch_matrix_override_out override_out;
- t_extapb_regfile_switch_matrix_spi_location spi_location;
- t_extapb_regfile_switch_matrix_ana_enable ana_enable;
- t_extapb_regfile_switch_matrix_ehs0 ehs0;
- t_extapb_regfile_switch_matrix_ehs1 ehs1;
- t_extapb_regfile_switch_matrix_override_in override_in;
-} t_extapb_regfile_switch_matrix;
-#define EXTAPB_REGFILE_SWITCH_MATRIX_ADDR 0x4001da40
-#define EXTAPB_REGFILE_SWITCH_MATRIX ((t_extapb_regfile_switch_matrix *)EXTAPB_REGFILE_SWITCH_MATRIX_ADDR)
-
-
-/* debug_adc module */
-/*-------------------------*/
-
-
-/* enable register */
-/*----------------------*/
-/* Enabling of the clocks. */
-/* gen : Enabling of the SAR-ADC debug. */
-/* ref : Enabling of the reference clock. */
-/* dbg : Enabling of the externally applied debug clock. */
-#define EXTAPB_REGFILE_DEBUG_ADC_ENABLE_GEN_MASK 0x0001
-#define EXTAPB_REGFILE_DEBUG_ADC_ENABLE_GEN_POS 0
-#define EXTAPB_REGFILE_DEBUG_ADC_ENABLE_REF_MASK 0x0002
-#define EXTAPB_REGFILE_DEBUG_ADC_ENABLE_REF_POS 1
-#define EXTAPB_REGFILE_DEBUG_ADC_ENABLE_DBG_MASK 0x0004
-#define EXTAPB_REGFILE_DEBUG_ADC_ENABLE_DBG_POS 2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int gen : 1;
- unsigned int ref : 1;
- unsigned int dbg : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_debug_adc_enable;
-#define EXTAPB_REGFILE_DEBUG_ADC_ENABLE_RST 0x0
-#define EXTAPB_REGFILE_DEBUG_ADC_ENABLE_ADDR 0x4001db00
-
-
-/* cfg register */
-/*----------------------*/
-/* Configuration. */
-/* half_speed : Select half or full speed ADC debugging. */
-/* select_q : In half speed, select I or Q ADC. */
-#define EXTAPB_REGFILE_DEBUG_ADC_CFG_HALF_SPEED_MASK 0x0001
-#define EXTAPB_REGFILE_DEBUG_ADC_CFG_HALF_SPEED_POS 0
-#define EXTAPB_REGFILE_DEBUG_ADC_CFG_SELECT_Q_MASK 0x0002
-#define EXTAPB_REGFILE_DEBUG_ADC_CFG_SELECT_Q_POS 1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int half_speed : 1;
- unsigned int select_q : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_debug_adc_cfg;
-#define EXTAPB_REGFILE_DEBUG_ADC_CFG_RST 0x0
-#define EXTAPB_REGFILE_DEBUG_ADC_CFG_ADDR 0x4001db04
-
-
-/* snap_cmd register */
-/*----------------------*/
-/* Snap command */
-/* trigger_t : trigger toggle to trigger the snap process */
-/* done_t : Done toggle indicating that the snap process has been completed. */
-#define EXTAPB_REGFILE_DEBUG_ADC_SNAP_CMD_TRIGGER_T_MASK 0x0001
-#define EXTAPB_REGFILE_DEBUG_ADC_SNAP_CMD_TRIGGER_T_POS 0
-#define EXTAPB_REGFILE_DEBUG_ADC_SNAP_CMD_DONE_T_MASK 0x8000
-#define EXTAPB_REGFILE_DEBUG_ADC_SNAP_CMD_DONE_T_POS 15
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int trigger_t : 1;
- unsigned int : 14;
- unsigned int done_t : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_debug_adc_snap_cmd;
-#define EXTAPB_REGFILE_DEBUG_ADC_SNAP_CMD_RST 0x0
-#define EXTAPB_REGFILE_DEBUG_ADC_SNAP_CMD_ADDR 0x4001db08
-
-
-/* snap_i register */
-/*----------------------*/
-/* Snapshot of the SAR ADC I */
-/* value : Snapshot value of the SAR ADC I. */
-#define EXTAPB_REGFILE_DEBUG_ADC_SNAP_I_VALUE_MASK 0x03ff
-#define EXTAPB_REGFILE_DEBUG_ADC_SNAP_I_VALUE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int value : 10;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_debug_adc_snap_i;
-#define EXTAPB_REGFILE_DEBUG_ADC_SNAP_I_RST 0x0
-#define EXTAPB_REGFILE_DEBUG_ADC_SNAP_I_DYNAMIC true
-#define EXTAPB_REGFILE_DEBUG_ADC_SNAP_I_SNAPCLOCK 0
-#define EXTAPB_REGFILE_DEBUG_ADC_SNAP_I_ADDR 0x4001db0c
-
-
-/* snap_q register */
-/*----------------------*/
-/* Snapshot of the SAR ADC Q */
-/* value : Snapshot value of the SAR ADC Q. */
-#define EXTAPB_REGFILE_DEBUG_ADC_SNAP_Q_VALUE_MASK 0x03ff
-#define EXTAPB_REGFILE_DEBUG_ADC_SNAP_Q_VALUE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int value : 10;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_debug_adc_snap_q;
-#define EXTAPB_REGFILE_DEBUG_ADC_SNAP_Q_RST 0x0
-#define EXTAPB_REGFILE_DEBUG_ADC_SNAP_Q_DYNAMIC true
-#define EXTAPB_REGFILE_DEBUG_ADC_SNAP_Q_SNAPCLOCK 0
-#define EXTAPB_REGFILE_DEBUG_ADC_SNAP_Q_ADDR 0x4001db10
-
-
-typedef struct{
- t_extapb_regfile_debug_adc_enable enable;
- t_extapb_regfile_debug_adc_cfg cfg;
- t_extapb_regfile_debug_adc_snap_cmd snap_cmd;
- t_extapb_regfile_debug_adc_snap_i snap_i;
- t_extapb_regfile_debug_adc_snap_q snap_q;
-} t_extapb_regfile_debug_adc;
-#define EXTAPB_REGFILE_DEBUG_ADC_ADDR 0x4001db00
-#define EXTAPB_REGFILE_DEBUG_ADC ((t_extapb_regfile_debug_adc *)EXTAPB_REGFILE_DEBUG_ADC_ADDR)
-
-
-/* gpio module */
-/*-------------------------*/
-
-
-/* gpio_out register */
-/*----------------------*/
-/* GPIO output */
-/* gpio_out : GPIO out value */
-#define EXTAPB_REGFILE_GPIO_GPIO_OUT_GPIO_OUT_MASK 0x0fff
-#define EXTAPB_REGFILE_GPIO_GPIO_OUT_GPIO_OUT_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int gpio_out : 12;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_gpio_gpio_out;
-#define EXTAPB_REGFILE_GPIO_GPIO_OUT_RST 0x0
-#define EXTAPB_REGFILE_GPIO_GPIO_OUT_ADDR 0x4001db20
-
-
-/* gpio_out_en register */
-/*----------------------*/
-/* GPIO output enable */
-/* gpio_out_en : GPIO out enable value */
-#define EXTAPB_REGFILE_GPIO_GPIO_OUT_EN_GPIO_OUT_EN_MASK 0x0fff
-#define EXTAPB_REGFILE_GPIO_GPIO_OUT_EN_GPIO_OUT_EN_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int gpio_out_en : 12;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_gpio_gpio_out_en;
-#define EXTAPB_REGFILE_GPIO_GPIO_OUT_EN_RST 0x0
-#define EXTAPB_REGFILE_GPIO_GPIO_OUT_EN_ADDR 0x4001db24
-
-
-/* gpio_in register */
-/*----------------------*/
-/* GPIO input */
-/* gpio_in : GPIO input value */
-#define EXTAPB_REGFILE_GPIO_GPIO_IN_GPIO_IN_MASK 0x0fff
-#define EXTAPB_REGFILE_GPIO_GPIO_IN_GPIO_IN_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int gpio_in : 12;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_gpio_gpio_in;
-#define EXTAPB_REGFILE_GPIO_GPIO_IN_RST 0x0
-#define EXTAPB_REGFILE_GPIO_GPIO_IN_DYNAMIC true
-#define EXTAPB_REGFILE_GPIO_GPIO_IN_SNAPCLOCK 0
-#define EXTAPB_REGFILE_GPIO_GPIO_IN_ADDR 0x4001db28
-
-
-typedef struct{
- t_extapb_regfile_gpio_gpio_out gpio_out;
- t_extapb_regfile_gpio_gpio_out_en gpio_out_en;
- t_extapb_regfile_gpio_gpio_in gpio_in;
-} t_extapb_regfile_gpio;
-#define EXTAPB_REGFILE_GPIO_ADDR 0x4001db20
-#define EXTAPB_REGFILE_GPIO ((t_extapb_regfile_gpio *)EXTAPB_REGFILE_GPIO_ADDR)
-
-
-/* debug_dac module */
-/*-------------------------*/
-
-
-/* enable register */
-/*----------------------*/
-/* Enabling of the clocks. */
-/* gen : Enabling of the SAR-ADC debug. */
-/* ref : Enabling of the reference clock. */
-/* dbg : Enabling of the externally applied debug clock. */
-/* dac_ovr : DAC override enable */
-/* pll_divn_ovr : PLL DIVN override enable */
-#define EXTAPB_REGFILE_DEBUG_DAC_ENABLE_GEN_MASK 0x0001
-#define EXTAPB_REGFILE_DEBUG_DAC_ENABLE_GEN_POS 0
-#define EXTAPB_REGFILE_DEBUG_DAC_ENABLE_REF_MASK 0x0002
-#define EXTAPB_REGFILE_DEBUG_DAC_ENABLE_REF_POS 1
-#define EXTAPB_REGFILE_DEBUG_DAC_ENABLE_DBG_MASK 0x0004
-#define EXTAPB_REGFILE_DEBUG_DAC_ENABLE_DBG_POS 2
-#define EXTAPB_REGFILE_DEBUG_DAC_ENABLE_DAC_OVR_MASK 0x0008
-#define EXTAPB_REGFILE_DEBUG_DAC_ENABLE_DAC_OVR_POS 3
-#define EXTAPB_REGFILE_DEBUG_DAC_ENABLE_PLL_DIVN_OVR_MASK 0x0010
-#define EXTAPB_REGFILE_DEBUG_DAC_ENABLE_PLL_DIVN_OVR_POS 4
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int gen : 1;
- unsigned int ref : 1;
- unsigned int dbg : 1;
- unsigned int dac_ovr : 1;
- unsigned int pll_divn_ovr : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_debug_dac_enable;
-#define EXTAPB_REGFILE_DEBUG_DAC_ENABLE_RST 0x0
-#define EXTAPB_REGFILE_DEBUG_DAC_ENABLE_ADDR 0x4001db40
-
-
-/* src register */
-/*----------------------*/
-/* Data source of the DACs. */
-/* dac : Data source for the DAC. */
-/* pll_divn : Data source for the PLL DIVN. */
-#define EXTAPB_REGFILE_DEBUG_DAC_SRC_DAC_MASK 0x0003
-#define EXTAPB_REGFILE_DEBUG_DAC_SRC_DAC_POS 0
-#define EXTAPB_REGFILE_DEBUG_DAC_SRC_PLL_DIVN_MASK 0x000c
-#define EXTAPB_REGFILE_DEBUG_DAC_SRC_PLL_DIVN_POS 2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int dac : 2;
- unsigned int pll_divn : 2;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_debug_dac_src;
-#define EXTAPB_REGFILE_DEBUG_DAC_SRC_RST 0x0
-#define EXTAPB_REGFILE_DEBUG_DAC_SRC_ADDR 0x4001db44
-
-
-/* dac_pll_divn register */
-/*----------------------*/
-/* Writing to this register sets the DAC and PLL DIVN values simultaneously */
-/* dac : Value of the DAC. */
-/* pll_divn : Value of the PLL DIVN. */
-#define EXTAPB_REGFILE_DEBUG_DAC_DAC_PLL_DIVN_DAC_MASK 0x00ff
-#define EXTAPB_REGFILE_DEBUG_DAC_DAC_PLL_DIVN_DAC_POS 0
-#define EXTAPB_REGFILE_DEBUG_DAC_DAC_PLL_DIVN_PLL_DIVN_MASK 0x7f00
-#define EXTAPB_REGFILE_DEBUG_DAC_DAC_PLL_DIVN_PLL_DIVN_POS 8
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int dac : 8;
- unsigned int pll_divn : 7;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_debug_dac_dac_pll_divn;
-#define EXTAPB_REGFILE_DEBUG_DAC_DAC_PLL_DIVN_RST 0x0
-#define EXTAPB_REGFILE_DEBUG_DAC_DAC_PLL_DIVN_ADDR 0x4001db48
-
-
-typedef struct{
- t_extapb_regfile_debug_dac_enable enable;
- t_extapb_regfile_debug_dac_src src;
- t_extapb_regfile_debug_dac_dac_pll_divn dac_pll_divn;
-} t_extapb_regfile_debug_dac;
-#define EXTAPB_REGFILE_DEBUG_DAC_ADDR 0x4001db40
-#define EXTAPB_REGFILE_DEBUG_DAC ((t_extapb_regfile_debug_dac *)EXTAPB_REGFILE_DEBUG_DAC_ADDR)
-
-
-/* xo_cal module */
-/*-------------------------*/
-
-
-/* cfg register */
-/*----------------------*/
-/* Configuration of the Crystal Oscillator Calibration module. */
-/* start_inv : Polarity of the externally applied START signal. */
-/* start_ovr : Override of the START signal towards the RF. */
-/* start : Override value of the START signal towards the RF. */
-/* stop_inv : Polarity of the STOP signal from the RF. */
-/* stop_cntr_end : Generate the external DONE signal when the counter reaches its end. */
-/* xo32k_mode : When 0 : 32 MHz XO cal is used, when 1 : 32 kHz XO cal is used */
-#define EXTAPB_REGFILE_XO_CAL_CFG_START_INV_MASK 0x0001
-#define EXTAPB_REGFILE_XO_CAL_CFG_START_INV_POS 0
-#define EXTAPB_REGFILE_XO_CAL_CFG_START_OVR_MASK 0x0002
-#define EXTAPB_REGFILE_XO_CAL_CFG_START_OVR_POS 1
-#define EXTAPB_REGFILE_XO_CAL_CFG_START_MASK 0x0004
-#define EXTAPB_REGFILE_XO_CAL_CFG_START_POS 2
-#define EXTAPB_REGFILE_XO_CAL_CFG_STOP_INV_MASK 0x0008
-#define EXTAPB_REGFILE_XO_CAL_CFG_STOP_INV_POS 3
-#define EXTAPB_REGFILE_XO_CAL_CFG_STOP_CNTR_END_MASK 0x0010
-#define EXTAPB_REGFILE_XO_CAL_CFG_STOP_CNTR_END_POS 4
-#define EXTAPB_REGFILE_XO_CAL_CFG_XO32K_MODE_MASK 0x0020
-#define EXTAPB_REGFILE_XO_CAL_CFG_XO32K_MODE_POS 5
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int start_inv : 1;
- unsigned int start_ovr : 1;
- unsigned int start : 1;
- unsigned int stop_inv : 1;
- unsigned int stop_cntr_end : 1;
- unsigned int xo32k_mode : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_xo_cal_cfg;
-#define EXTAPB_REGFILE_XO_CAL_CFG_RST 0x0
-#define EXTAPB_REGFILE_XO_CAL_CFG_ADDR 0x4001db80
-
-
-/* cmd register */
-/*----------------------*/
-/* Command register */
-/* ovr : Override instructing the state machine to use the START/STOP signals from this register. */
-/* start : START signal for testing the state machine. */
-/* stop : STOP signal for testing the state machine. */
-#define EXTAPB_REGFILE_XO_CAL_CMD_OVR_MASK 0x0001
-#define EXTAPB_REGFILE_XO_CAL_CMD_OVR_POS 0
-#define EXTAPB_REGFILE_XO_CAL_CMD_START_MASK 0x0002
-#define EXTAPB_REGFILE_XO_CAL_CMD_START_POS 1
-#define EXTAPB_REGFILE_XO_CAL_CMD_STOP_MASK 0x0004
-#define EXTAPB_REGFILE_XO_CAL_CMD_STOP_POS 2
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int ovr : 1;
- unsigned int start : 1;
- unsigned int stop : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_xo_cal_cmd;
-#define EXTAPB_REGFILE_XO_CAL_CMD_RST 0x0
-#define EXTAPB_REGFILE_XO_CAL_CMD_ADDR 0x4001db84
-
-
-/* status register */
-/*----------------------*/
-/* Status register */
-/* done : Status of the calibration run. */
-#define EXTAPB_REGFILE_XO_CAL_STATUS_DONE_MASK 0x0001
-#define EXTAPB_REGFILE_XO_CAL_STATUS_DONE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int done : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_xo_cal_status;
-#define EXTAPB_REGFILE_XO_CAL_STATUS_RST 0x0
-#define EXTAPB_REGFILE_XO_CAL_STATUS_DYNAMIC true
-#define EXTAPB_REGFILE_XO_CAL_STATUS_SNAPCLOCK 0
-#define EXTAPB_REGFILE_XO_CAL_STATUS_ADDR 0x4001db88
-
-
-/* cntr register */
-/*----------------------*/
-/* Counter register */
-/* cntr : Result of the counter. */
-#define EXTAPB_REGFILE_XO_CAL_CNTR_CNTR_MASK 0xffff
-#define EXTAPB_REGFILE_XO_CAL_CNTR_CNTR_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int cntr : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_xo_cal_cntr;
-#define EXTAPB_REGFILE_XO_CAL_CNTR_RST 0x0
-#define EXTAPB_REGFILE_XO_CAL_CNTR_DYNAMIC true
-#define EXTAPB_REGFILE_XO_CAL_CNTR_SNAPCLOCK 0
-#define EXTAPB_REGFILE_XO_CAL_CNTR_ADDR 0x4001db8c
-
-
-typedef struct{
- t_extapb_regfile_xo_cal_cfg cfg;
- t_extapb_regfile_xo_cal_cmd cmd;
- t_extapb_regfile_xo_cal_status status;
- t_extapb_regfile_xo_cal_cntr cntr;
-} t_extapb_regfile_xo_cal;
-#define EXTAPB_REGFILE_XO_CAL_ADDR 0x4001db80
-#define EXTAPB_REGFILE_XO_CAL ((t_extapb_regfile_xo_cal *)EXTAPB_REGFILE_XO_CAL_ADDR)
-
-
-/* rf_bgp_cal module */
-/*-------------------------*/
-
-
-/* cfg register */
-/*----------------------*/
-/* Configuration of the RF Bandgap Calibration module. */
-/* pwr_delay : power delay setting */
-/* cmp_delay : comparator delay setting */
-#define EXTAPB_REGFILE_RF_BGP_CAL_CFG_PWR_DELAY_MASK 0x001f
-#define EXTAPB_REGFILE_RF_BGP_CAL_CFG_PWR_DELAY_POS 0
-#define EXTAPB_REGFILE_RF_BGP_CAL_CFG_CMP_DELAY_MASK 0x01e0
-#define EXTAPB_REGFILE_RF_BGP_CAL_CFG_CMP_DELAY_POS 5
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pwr_delay : 5;
- unsigned int cmp_delay : 4;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rf_bgp_cal_cfg;
-#define EXTAPB_REGFILE_RF_BGP_CAL_CFG_RST 0x0
-#define EXTAPB_REGFILE_RF_BGP_CAL_CFG_ADDR 0x4001db90
-
-
-/* iref register */
-/*----------------------*/
-/* Readable Reference Current output of the RF bandgap calibration */
-/* iref : Reference current */
-#define EXTAPB_REGFILE_RF_BGP_CAL_IREF_IREF_MASK 0x001f
-#define EXTAPB_REGFILE_RF_BGP_CAL_IREF_IREF_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int iref : 5;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rf_bgp_cal_iref;
-#define EXTAPB_REGFILE_RF_BGP_CAL_IREF_RST 0x0
-#define EXTAPB_REGFILE_RF_BGP_CAL_IREF_DYNAMIC true
-#define EXTAPB_REGFILE_RF_BGP_CAL_IREF_SNAPCLOCK 0
-#define EXTAPB_REGFILE_RF_BGP_CAL_IREF_ADDR 0x4001db94
-
-
-/* error register */
-/*----------------------*/
-/* RF Bandgap Calibration error register */
-/* error : error */
-/* error_status : error status */
-#define EXTAPB_REGFILE_RF_BGP_CAL_ERROR_ERROR_MASK 0x0001
-#define EXTAPB_REGFILE_RF_BGP_CAL_ERROR_ERROR_POS 0
-#define EXTAPB_REGFILE_RF_BGP_CAL_ERROR_ERROR_STATUS_MASK 0x0006
-#define EXTAPB_REGFILE_RF_BGP_CAL_ERROR_ERROR_STATUS_POS 1
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int error : 1;
- unsigned int error_status : 2;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_rf_bgp_cal_error;
-#define EXTAPB_REGFILE_RF_BGP_CAL_ERROR_RST 0x0
-#define EXTAPB_REGFILE_RF_BGP_CAL_ERROR_DYNAMIC true
-#define EXTAPB_REGFILE_RF_BGP_CAL_ERROR_SNAPCLOCK 0
-#define EXTAPB_REGFILE_RF_BGP_CAL_ERROR_ADDR 0x4001db98
-
-
-typedef struct{
- t_extapb_regfile_rf_bgp_cal_cfg cfg;
- t_extapb_regfile_rf_bgp_cal_iref iref;
- t_extapb_regfile_rf_bgp_cal_error error;
-} t_extapb_regfile_rf_bgp_cal;
-#define EXTAPB_REGFILE_RF_BGP_CAL_ADDR 0x4001db90
-#define EXTAPB_REGFILE_RF_BGP_CAL ((t_extapb_regfile_rf_bgp_cal *)EXTAPB_REGFILE_RF_BGP_CAL_ADDR)
-
-
-/* dummy module */
-/*-------------------------*/
-
-
-/* dummy_reg register */
-/*----------------------*/
-/* Dummy registers */
-/* dummy_val : Dummy value. */
-#define EXTAPB_REGFILE_DUMMY_DUMMY_REG_DUMMY_VAL_MASK 0xffff
-#define EXTAPB_REGFILE_DUMMY_DUMMY_REG_DUMMY_VAL_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int dummy_val : 16;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_dummy_dummy_reg;
-#define EXTAPB_REGFILE_DUMMY_DUMMY_REG_RST 0x0
-#define EXTAPB_REGFILE_DUMMY_DUMMY_REG0_ADDR 0x4001dc00
-#define EXTAPB_REGFILE_DUMMY_DUMMY_REG0 ((t_extapb_regfile_dummy_dummy_reg *)EXTAPB_REGFILE_DUMMY_DUMMY_REG0_ADDR)
-#define EXTAPB_REGFILE_DUMMY_DUMMY_REG1_ADDR 0x4001dc04
-#define EXTAPB_REGFILE_DUMMY_DUMMY_REG1 ((t_extapb_regfile_dummy_dummy_reg *)EXTAPB_REGFILE_DUMMY_DUMMY_REG1_ADDR)
-#define EXTAPB_REGFILE_DUMMY_DUMMY_REG2_ADDR 0x4001dc08
-#define EXTAPB_REGFILE_DUMMY_DUMMY_REG2 ((t_extapb_regfile_dummy_dummy_reg *)EXTAPB_REGFILE_DUMMY_DUMMY_REG2_ADDR)
-#define EXTAPB_REGFILE_DUMMY_DUMMY_REG3_ADDR 0x4001dc0c
-#define EXTAPB_REGFILE_DUMMY_DUMMY_REG3 ((t_extapb_regfile_dummy_dummy_reg *)EXTAPB_REGFILE_DUMMY_DUMMY_REG3_ADDR)
-#define EXTAPB_REGFILE_DUMMY_DUMMY_REG4_ADDR 0x4001dc10
-#define EXTAPB_REGFILE_DUMMY_DUMMY_REG4 ((t_extapb_regfile_dummy_dummy_reg *)EXTAPB_REGFILE_DUMMY_DUMMY_REG4_ADDR)
-#define EXTAPB_REGFILE_DUMMY_DUMMY_REG5_ADDR 0x4001dc14
-#define EXTAPB_REGFILE_DUMMY_DUMMY_REG5 ((t_extapb_regfile_dummy_dummy_reg *)EXTAPB_REGFILE_DUMMY_DUMMY_REG5_ADDR)
-#define EXTAPB_REGFILE_DUMMY_DUMMY_REG6_ADDR 0x4001dc18
-#define EXTAPB_REGFILE_DUMMY_DUMMY_REG6 ((t_extapb_regfile_dummy_dummy_reg *)EXTAPB_REGFILE_DUMMY_DUMMY_REG6_ADDR)
-#define EXTAPB_REGFILE_DUMMY_DUMMY_REG7_ADDR 0x4001dc1c
-#define EXTAPB_REGFILE_DUMMY_DUMMY_REG7 ((t_extapb_regfile_dummy_dummy_reg *)EXTAPB_REGFILE_DUMMY_DUMMY_REG7_ADDR)
-
-
-typedef struct{
- t_extapb_regfile_dummy_dummy_reg dummy_reg[8];
-} t_extapb_regfile_dummy;
-#define EXTAPB_REGFILE_DUMMY_ADDR 0x4001dc00
-#define EXTAPB_REGFILE_DUMMY ((t_extapb_regfile_dummy *)EXTAPB_REGFILE_DUMMY_ADDR)
-
-
-/* pa_control module */
-/*-------------------------*/
-
-
-/* pa_ramp_cfg register */
-/*----------------------*/
-/* TX PA ramp up and down configuration */
-/* tx_pa_ramp_init : Indicates point where ramping will start from or end at */
-/* tx_pa_slice_incr_delay : Step delay configed in terms of 16 MHz clock cycles. 0 corresponds to 1 clockcycle. 0x3F corresponds to 128 clock cycles */
-/* pa_slice_ramp_bypass_en : PA ramp bypass */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_RAMP_CFG_TX_PA_RAMP_INIT_MASK 0x000f
-#define EXTAPB_REGFILE_PA_CONTROL_PA_RAMP_CFG_TX_PA_RAMP_INIT_POS 0
-#define EXTAPB_REGFILE_PA_CONTROL_PA_RAMP_CFG_TX_PA_SLICE_INCR_DELAY_MASK 0x07f0
-#define EXTAPB_REGFILE_PA_CONTROL_PA_RAMP_CFG_TX_PA_SLICE_INCR_DELAY_POS 4
-#define EXTAPB_REGFILE_PA_CONTROL_PA_RAMP_CFG_PA_SLICE_RAMP_BYPASS_EN_MASK 0x0800
-#define EXTAPB_REGFILE_PA_CONTROL_PA_RAMP_CFG_PA_SLICE_RAMP_BYPASS_EN_POS 11
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int tx_pa_ramp_init : 4;
- unsigned int tx_pa_slice_incr_delay : 7;
- unsigned int pa_slice_ramp_bypass_en : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_ramp_cfg;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_RAMP_CFG_RST 0x140
-#define EXTAPB_REGFILE_PA_CONTROL_PA_RAMP_CFG_ADDR 0x4001dc40
-
-
-/* pa_cal_comp_cfg register */
-/*----------------------*/
-/* PA calibration compensation config */
-/* pa_cal_comp_bypass_en : Enable bit for PA calibration compensation bypass mux */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_CAL_COMP_CFG_PA_CAL_COMP_BYPASS_EN_MASK 0x0001
-#define EXTAPB_REGFILE_PA_CONTROL_PA_CAL_COMP_CFG_PA_CAL_COMP_BYPASS_EN_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pa_cal_comp_bypass_en : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_cal_comp_cfg;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_CAL_COMP_CFG_RST 0x1
-#define EXTAPB_REGFILE_PA_CONTROL_PA_CAL_COMP_CFG_ADDR 0x4001dc44
-
-
-/* man_pa_cfg register */
-/*----------------------*/
-/* Manual PA control */
-/* man_pa_setting : Manual register setting */
-/* man_pa_setting_en : Manual register setting enable */
-#define EXTAPB_REGFILE_PA_CONTROL_MAN_PA_CFG_MAN_PA_SETTING_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_MAN_PA_CFG_MAN_PA_SETTING_POS 0
-#define EXTAPB_REGFILE_PA_CONTROL_MAN_PA_CFG_MAN_PA_SETTING_EN_MASK 0x0200
-#define EXTAPB_REGFILE_PA_CONTROL_MAN_PA_CFG_MAN_PA_SETTING_EN_POS 9
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int man_pa_setting : 9;
- unsigned int man_pa_setting_en : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_man_pa_cfg;
-#define EXTAPB_REGFILE_PA_CONTROL_MAN_PA_CFG_RST 0x0
-#define EXTAPB_REGFILE_PA_CONTROL_MAN_PA_CFG_ADDR 0x4001dc48
-
-
-/* pa_lut0 register */
-/*----------------------*/
-/* PA LUT entry 0 */
-/* nslice : Power to nslice lookup table. Entry 0 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT0_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT0_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut0;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT0_RST 0x1
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT0_ADDR 0x4001dc4c
-
-
-/* pa_lut1 register */
-/*----------------------*/
-/* PA LUT entry 1 */
-/* nslice : Power to nslice lookup table. Entry 1 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT1_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT1_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut1;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT1_RST 0x1
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT1_ADDR 0x4001dc50
-
-
-/* pa_lut2 register */
-/*----------------------*/
-/* PA LUT entry 2 */
-/* nslice : Power to nslice lookup table. Entry 2 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT2_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT2_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut2;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT2_RST 0x1
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT2_ADDR 0x4001dc54
-
-
-/* pa_lut3 register */
-/*----------------------*/
-/* PA LUT entry 3 */
-/* nslice : Power to nslice lookup table. Entry 3 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT3_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT3_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut3;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT3_RST 0x1
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT3_ADDR 0x4001dc58
-
-
-/* pa_lut4 register */
-/*----------------------*/
-/* PA LUT entry 4 */
-/* nslice : Power to nslice lookup table. Entry 4 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT4_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT4_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut4;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT4_RST 0x1
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT4_ADDR 0x4001dc5c
-
-
-/* pa_lut5 register */
-/*----------------------*/
-/* PA LUT entry 5 */
-/* nslice : Power to nslice lookup table. Entry 5 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT5_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT5_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut5;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT5_RST 0x2
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT5_ADDR 0x4001dc60
-
-
-/* pa_lut6 register */
-/*----------------------*/
-/* PA LUT entry 6 */
-/* nslice : Power to nslice lokup table. Entry 6 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT6_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT6_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut6;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT6_RST 0x2
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT6_ADDR 0x4001dc64
-
-
-/* pa_lut7 register */
-/*----------------------*/
-/* PA LUT entry 7 */
-/* nslice : Power to nslice lookup table. Entry 7 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT7_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT7_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut7;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT7_RST 0x2
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT7_ADDR 0x4001dc68
-
-
-/* pa_lut8 register */
-/*----------------------*/
-/* PA LUT entry 8 */
-/* nslice : Power to nslice lookup table. Entry 8 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT8_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT8_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut8;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT8_RST 0x2
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT8_ADDR 0x4001dc6c
-
-
-/* pa_lut9 register */
-/*----------------------*/
-/* PA LUT entry 9 */
-/* nslice : Power to nslice lookup table. Entry 9 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT9_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT9_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut9;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT9_RST 0x3
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT9_ADDR 0x4001dc70
-
-
-/* pa_lut10 register */
-/*----------------------*/
-/* PA LUT entry 10 */
-/* nslice : Power to nslice lookup table. Entry 10 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT10_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT10_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut10;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT10_RST 0x3
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT10_ADDR 0x4001dc74
-
-
-/* pa_lut11 register */
-/*----------------------*/
-/* PA LUT entry 11 */
-/* nslice : Power to nslice lookup table. Entry 11 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT11_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT11_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut11;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT11_RST 0x3
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT11_ADDR 0x4001dc78
-
-
-/* pa_lut12 register */
-/*----------------------*/
-/* PA LUT entry 12 */
-/* nslice : Power to nslice lookup table. Entry 12 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT12_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT12_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut12;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT12_RST 0x4
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT12_ADDR 0x4001dc7c
-
-
-/* pa_lut13 register */
-/*----------------------*/
-/* PA LUT entry 13 */
-/* nslice : Power to nslice lookup table. Entry 13 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT13_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT13_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut13;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT13_RST 0x4
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT13_ADDR 0x4001dc80
-
-
-/* pa_lut14 register */
-/*----------------------*/
-/* PA LUT entry 14 */
-/* nslice : Power to nslice lookup table. Entry 14 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT14_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT14_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut14;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT14_RST 0x5
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT14_ADDR 0x4001dc84
-
-
-/* pa_lut15 register */
-/*----------------------*/
-/* PA LUT entry 15 */
-/* nslice : Power to nslice lookup table. Entry 15 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT15_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT15_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut15;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT15_RST 0x5
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT15_ADDR 0x4001dc88
-
-
-/* pa_lut16 register */
-/*----------------------*/
-/* PA LUT entry 16 */
-/* nslice : Power to nslice lookup table. Entry 16 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT16_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT16_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut16;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT16_RST 0x6
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT16_ADDR 0x4001dc8c
-
-
-/* pa_lut17 register */
-/*----------------------*/
-/* PA LUT entry 17 */
-/* nslice : Power to nslice lookup table. Entry 17 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT17_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT17_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut17;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT17_RST 0x7
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT17_ADDR 0x4001dc90
-
-
-/* pa_lut18 register */
-/*----------------------*/
-/* PA LUT entry 18 */
-/* nslice : Power to nslice lookup table. Entry 18 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT18_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT18_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut18;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT18_RST 0x8
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT18_ADDR 0x4001dc94
-
-
-/* pa_lut19 register */
-/*----------------------*/
-/* PA LUT entry 19 */
-/* nslice : Power to nslice lookup table. Entry 19 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT19_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT19_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut19;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT19_RST 0x8
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT19_ADDR 0x4001dc98
-
-
-/* pa_lut20 register */
-/*----------------------*/
-/* PA LUT entry 20 */
-/* nslice : Power to nslice lookup table. Entry 20 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT20_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT20_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut20;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT20_RST 0xa
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT20_ADDR 0x4001dc9c
-
-
-/* pa_lut21 register */
-/*----------------------*/
-/* PA LUT entry 21 */
-/* nslice : Power to nslice lookup table. Entry 21 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT21_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT21_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut21;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT21_RST 0xb
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT21_ADDR 0x4001dca0
-
-
-/* pa_lut22 register */
-/*----------------------*/
-/* PA LUT entry 22 */
-/* nslice : Power to nslice lookup table. Entry 22 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT22_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT22_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut22;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT22_RST 0xc
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT22_ADDR 0x4001dca4
-
-
-/* pa_lut23 register */
-/*----------------------*/
-/* PA LUT entry 23 */
-/* nslice : Power to nslice lookup table. Entry 23 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT23_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT23_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut23;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT23_RST 0xe
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT23_ADDR 0x4001dca8
-
-
-/* pa_lut24 register */
-/*----------------------*/
-/* PA LUT entry 24 */
-/* nslice : Power to nslice lookup table. Entry 24 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT24_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT24_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut24;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT24_RST 0x10
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT24_ADDR 0x4001dcac
-
-
-/* pa_lut25 register */
-/*----------------------*/
-/* PA LUT entry 25 */
-/* nslice : Power to nslice lookup table. Entry 25 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT25_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT25_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut25;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT25_RST 0x12
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT25_ADDR 0x4001dcb0
-
-
-/* pa_lut26 register */
-/*----------------------*/
-/* PA LUT entry 26 */
-/* nslice : Power to nslice lookup table. Entry 26 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT26_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT26_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut26;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT26_RST 0x14
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT26_ADDR 0x4001dcb4
-
-
-/* pa_lut27 register */
-/*----------------------*/
-/* PA LUT entry 27 */
-/* nslice : Power to nslice lookup table. Entry 27 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT27_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT27_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut27;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT27_RST 0x17
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT27_ADDR 0x4001dcb8
-
-
-/* pa_lut28 register */
-/*----------------------*/
-/* PA LUT entry 28 */
-/* nslice : Power to nslice lookup table. Entry 28 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT28_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT28_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut28;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT28_RST 0x1a
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT28_ADDR 0x4001dcbc
-
-
-/* pa_lut29 register */
-/*----------------------*/
-/* PA LUT entry 29 */
-/* nslice : Power to nslice lookup table. Entry 29 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT29_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT29_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut29;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT29_RST 0x1e
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT29_ADDR 0x4001dcc0
-
-
-/* pa_lut30 register */
-/*----------------------*/
-/* PA LUT entry 30 */
-/* nslice : Power to nslice lookup table. Entry 30 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT30_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT30_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut30;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT30_RST 0x22
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT30_ADDR 0x4001dcc4
-
-
-/* pa_lut31 register */
-/*----------------------*/
-/* PA LUT entry 31 */
-/* nslice : Power to nslice lookup table. Entry 31 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT31_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT31_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut31;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT31_RST 0x27
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT31_ADDR 0x4001dcc8
-
-
-/* pa_lut32 register */
-/*----------------------*/
-/* PA LUT entry 32 */
-/* nslice : Power to nslice lookup table. Entry 32 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT32_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT32_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut32;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT32_RST 0x2e
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT32_ADDR 0x4001dccc
-
-
-/* pa_lut33 register */
-/*----------------------*/
-/* PA LUT entry 33 */
-/* nslice : Power to nslice lookup table. Entry 33 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT33_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT33_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut33;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT33_RST 0x36
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT33_ADDR 0x4001dcd0
-
-
-/* pa_lut34 register */
-/*----------------------*/
-/* PA LUT entry 34 */
-/* nslice : Power to nslice lookup table. Entry 34 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT34_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT34_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut34;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT34_RST 0x3f
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT34_ADDR 0x4001dcd4
-
-
-/* pa_lut35 register */
-/*----------------------*/
-/* PA LUT entry 35 */
-/* nslice : Power to nslice lookup table. Entry 35 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT35_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT35_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut35;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT35_RST 0x4c
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT35_ADDR 0x4001dcd8
-
-
-/* pa_lut36 register */
-/*----------------------*/
-/* PA LUT entry 36 */
-/* nslice : Power to nslice lookup table. Entry 36 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT36_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT36_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut36;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT36_RST 0x5c
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT36_ADDR 0x4001dcdc
-
-
-/* pa_lut37 register */
-/*----------------------*/
-/* PA LUT entry 37 */
-/* nslice : Power to nslice lookup table. Entry 37 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT37_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT37_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut37;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT37_RST 0x73
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT37_ADDR 0x4001dce0
-
-
-/* pa_lut38 register */
-/*----------------------*/
-/* PA LUT entry 38 */
-/* nslice : Power to nslice lookup table. Entry 38 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT38_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT38_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut38;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT38_RST 0x96
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT38_ADDR 0x4001dce4
-
-
-/* pa_lut39 register */
-/*----------------------*/
-/* PA LUT entry 39 */
-/* nslice : Power to nslice lookup table. Entry 39 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT39_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT39_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut39;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT39_RST 0xd0
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT39_ADDR 0x4001dce8
-
-
-/* pa_lut40 register */
-/*----------------------*/
-/* PA LUT entry 40 */
-/* nslice : Power to nslice lookup table. Entry 40 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT40_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT40_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut40;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT40_RST 0x144
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT40_ADDR 0x4001dcec
-
-
-/* pa_lut41 register */
-/*----------------------*/
-/* PA LUT entry 41 */
-/* nslice : Power to nslice lookup table. Entry 41 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT41_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT41_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut41;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT41_RST 0x1ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT41_ADDR 0x4001dcf0
-
-
-/* pa_lut42 register */
-/*----------------------*/
-/* PA LUT entry 42 */
-/* nslice : Power to nslice lookup table. Entry 42 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT42_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT42_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut42;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT42_RST 0x1ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT42_ADDR 0x4001dcf4
-
-
-/* pa_lut43 register */
-/*----------------------*/
-/* PA LUT entry 43 */
-/* nslice : Power to nslice lookup table. Entry 43 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT43_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT43_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut43;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT43_RST 0x1ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT43_ADDR 0x4001dcf8
-
-
-/* pa_lut44 register */
-/*----------------------*/
-/* PA LUT entry 44 */
-/* nslice : Power to nslice lookup table. Entry 44 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT44_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT44_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut44;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT44_RST 0x1ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT44_ADDR 0x4001dcfc
-
-
-/* pa_lut45 register */
-/*----------------------*/
-/* PA LUT entry 45 */
-/* nslice : Power to nslice lookup table. Entry 45 */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT45_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT45_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut45;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT45_RST 0x1ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT45_ADDR 0x4001dd00
-
-
-/* pa_lut_interpolate_cfg register */
-/*----------------------*/
-/* TBD */
-/* lut_offset : Identifies LUT entry that corresponds to 0dBm */
-/* interpolate_en : Enable interpolation between LUT entries for 0.5dB steps when set */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT_INTERPOLATE_CFG_LUT_OFFSET_MASK 0x003f
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT_INTERPOLATE_CFG_LUT_OFFSET_POS 0
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT_INTERPOLATE_CFG_INTERPOLATE_EN_MASK 0x0040
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT_INTERPOLATE_CFG_INTERPOLATE_EN_POS 6
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int lut_offset : 6;
- unsigned int interpolate_en : 1;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_lut_interpolate_cfg;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT_INTERPOLATE_CFG_RST 0x5e
-#define EXTAPB_REGFILE_PA_CONTROL_PA_LUT_INTERPOLATE_CFG_ADDR 0x4001dd04
-
-
-/* pa_status_pcorr register */
-/*----------------------*/
-/* PA status Pcorr */
-/* pcorr : pcorr resulting from the power level adjustment */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_STATUS_PCORR_PCORR_MASK 0x00ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_STATUS_PCORR_PCORR_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int pcorr : 8;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_status_pcorr;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_STATUS_PCORR_RST 0x0
-#define EXTAPB_REGFILE_PA_CONTROL_PA_STATUS_PCORR_DYNAMIC true
-#define EXTAPB_REGFILE_PA_CONTROL_PA_STATUS_PCORR_SNAPCLOCK 0
-#define EXTAPB_REGFILE_PA_CONTROL_PA_STATUS_PCORR_ADDR 0x4001dd08
-
-
-/* pa_status_nslice register */
-/*----------------------*/
-/* PA status Nslice */
-/* nslice : nslice resulting from LUT and interpolation */
-#define EXTAPB_REGFILE_PA_CONTROL_PA_STATUS_NSLICE_NSLICE_MASK 0x01ff
-#define EXTAPB_REGFILE_PA_CONTROL_PA_STATUS_NSLICE_NSLICE_POS 0
-#ifdef APB_ALLOW_BITFIELDS
-typedef volatile union{
-#else
-typedef volatile struct{
-#endif /*APB_ALLOW_BITFIELDS*/
- unsigned int val;
-#ifdef APB_ALLOW_BITFIELDS
- struct{
- unsigned int nslice : 9;
- } fields;
-#endif /*APB_ALLOW_BITFIELDS*/
-} t_extapb_regfile_pa_control_pa_status_nslice;
-#define EXTAPB_REGFILE_PA_CONTROL_PA_STATUS_NSLICE_RST 0x0
-#define EXTAPB_REGFILE_PA_CONTROL_PA_STATUS_NSLICE_DYNAMIC true
-#define EXTAPB_REGFILE_PA_CONTROL_PA_STATUS_NSLICE_SNAPCLOCK 0
-#define EXTAPB_REGFILE_PA_CONTROL_PA_STATUS_NSLICE_ADDR 0x4001dd0c
-
-
-typedef struct{
- t_extapb_regfile_pa_control_pa_ramp_cfg pa_ramp_cfg;
- t_extapb_regfile_pa_control_pa_cal_comp_cfg pa_cal_comp_cfg;
- t_extapb_regfile_pa_control_man_pa_cfg man_pa_cfg;
- t_extapb_regfile_pa_control_pa_lut0 pa_lut0;
- t_extapb_regfile_pa_control_pa_lut1 pa_lut1;
- t_extapb_regfile_pa_control_pa_lut2 pa_lut2;
- t_extapb_regfile_pa_control_pa_lut3 pa_lut3;
- t_extapb_regfile_pa_control_pa_lut4 pa_lut4;
- t_extapb_regfile_pa_control_pa_lut5 pa_lut5;
- t_extapb_regfile_pa_control_pa_lut6 pa_lut6;
- t_extapb_regfile_pa_control_pa_lut7 pa_lut7;
- t_extapb_regfile_pa_control_pa_lut8 pa_lut8;
- t_extapb_regfile_pa_control_pa_lut9 pa_lut9;
- t_extapb_regfile_pa_control_pa_lut10 pa_lut10;
- t_extapb_regfile_pa_control_pa_lut11 pa_lut11;
- t_extapb_regfile_pa_control_pa_lut12 pa_lut12;
- t_extapb_regfile_pa_control_pa_lut13 pa_lut13;
- t_extapb_regfile_pa_control_pa_lut14 pa_lut14;
- t_extapb_regfile_pa_control_pa_lut15 pa_lut15;
- t_extapb_regfile_pa_control_pa_lut16 pa_lut16;
- t_extapb_regfile_pa_control_pa_lut17 pa_lut17;
- t_extapb_regfile_pa_control_pa_lut18 pa_lut18;
- t_extapb_regfile_pa_control_pa_lut19 pa_lut19;
- t_extapb_regfile_pa_control_pa_lut20 pa_lut20;
- t_extapb_regfile_pa_control_pa_lut21 pa_lut21;
- t_extapb_regfile_pa_control_pa_lut22 pa_lut22;
- t_extapb_regfile_pa_control_pa_lut23 pa_lut23;
- t_extapb_regfile_pa_control_pa_lut24 pa_lut24;
- t_extapb_regfile_pa_control_pa_lut25 pa_lut25;
- t_extapb_regfile_pa_control_pa_lut26 pa_lut26;
- t_extapb_regfile_pa_control_pa_lut27 pa_lut27;
- t_extapb_regfile_pa_control_pa_lut28 pa_lut28;
- t_extapb_regfile_pa_control_pa_lut29 pa_lut29;
- t_extapb_regfile_pa_control_pa_lut30 pa_lut30;
- t_extapb_regfile_pa_control_pa_lut31 pa_lut31;
- t_extapb_regfile_pa_control_pa_lut32 pa_lut32;
- t_extapb_regfile_pa_control_pa_lut33 pa_lut33;
- t_extapb_regfile_pa_control_pa_lut34 pa_lut34;
- t_extapb_regfile_pa_control_pa_lut35 pa_lut35;
- t_extapb_regfile_pa_control_pa_lut36 pa_lut36;
- t_extapb_regfile_pa_control_pa_lut37 pa_lut37;
- t_extapb_regfile_pa_control_pa_lut38 pa_lut38;
- t_extapb_regfile_pa_control_pa_lut39 pa_lut39;
- t_extapb_regfile_pa_control_pa_lut40 pa_lut40;
- t_extapb_regfile_pa_control_pa_lut41 pa_lut41;
- t_extapb_regfile_pa_control_pa_lut42 pa_lut42;
- t_extapb_regfile_pa_control_pa_lut43 pa_lut43;
- t_extapb_regfile_pa_control_pa_lut44 pa_lut44;
- t_extapb_regfile_pa_control_pa_lut45 pa_lut45;
- t_extapb_regfile_pa_control_pa_lut_interpolate_cfg pa_lut_interpolate_cfg;
- t_extapb_regfile_pa_control_pa_status_pcorr pa_status_pcorr;
- t_extapb_regfile_pa_control_pa_status_nslice pa_status_nslice;
-} t_extapb_regfile_pa_control;
-#define EXTAPB_REGFILE_PA_CONTROL_ADDR 0x4001dc40
-#define EXTAPB_REGFILE_PA_CONTROL ((t_extapb_regfile_pa_control *)EXTAPB_REGFILE_PA_CONTROL_ADDR)
-
-
-typedef struct{
- t_extapb_regfile_test test;
- unsigned int reserved0[1];
- t_extapb_regfile_clockshop clockshop;
- unsigned int reserved1[1];
- t_extapb_regfile_ip2001_global ip2001_global;
- unsigned int reserved2[3];
- t_extapb_regfile_rx_datapath rx_datapath;
- unsigned int reserved3[3];
- t_extapb_regfile_transceiver transceiver;
- unsigned int reserved4[51];
- t_extapb_regfile_calibration calibration;
- unsigned int reserved5[12];
- t_extapb_regfile_tx_datapath tx_datapath;
- unsigned int reserved6[24];
- t_extapb_regfile_tmu tmu;
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
- /* ES1 if explicitly configured */
- unsigned int reserved7[21];
-#else
- /* ES2 default */
- unsigned int reserved7[20];
-#endif
- t_extapb_regfile_synth_control synth_control;
- unsigned int reserved8[13];
- t_extapb_regfile_tone_control tone_control;
- unsigned int reserved9[13];
- t_extapb_regfile_snap snap;
- unsigned int reserved10[7];
- t_extapb_regfile_apbm apbm;
- t_extapb_regfile_switch_matrix switch_matrix;
- unsigned int reserved11[5];
- t_extapb_regfile_debug_adc debug_adc;
- unsigned int reserved12[3];
- t_extapb_regfile_gpio gpio;
- unsigned int reserved13[5];
- t_extapb_regfile_debug_dac debug_dac;
- unsigned int reserved14[13];
- t_extapb_regfile_xo_cal xo_cal;
- t_extapb_regfile_rf_bgp_cal rf_bgp_cal;
- unsigned int reserved15[25];
- t_extapb_regfile_dummy dummy;
- unsigned int reserved16[8];
- t_extapb_regfile_pa_control pa_control;
- unsigned int reserved17[188];
-} t_extapb_regfile;
-#define EXTAPB_REGFILE_ADDR 0x4001d000
-#define EXTAPB_REGFILE ((t_extapb_regfile *)EXTAPB_REGFILE_ADDR)
-
-
-typedef struct{
- unsigned int reserved0[268465152];
- t_extapb_regfile regfile;
-} t_extapb;
-#define EXTAPB_ADDR 0x0
-#define EXTAPB ((t_extapb *)EXTAPB_ADDR)
-
-#endif /*JN518X_RFP_MODEM_H*/
diff --git a/third_party/nxp/JN5189/Radio_JN5189/Include/jn518x_zb_mac.h b/third_party/nxp/JN5189/Radio_JN5189/Include/jn518x_zb_mac.h
deleted file mode 100755
index 608e251..0000000
--- a/third_party/nxp/JN5189/Radio_JN5189/Include/jn518x_zb_mac.h
+++ /dev/null
@@ -1,930 +0,0 @@
-/*
-* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
-* Copyright 2016-2019 NXP
-* All rights reserved.
-*
-* SPDX-License-Identifier: BSD-3-Clause
-*/
-
-#ifndef __ZB_MAC_IF_H__
-#define __ZB_MAC_IF_H__
-
- typedef struct {
- /* Address 0x000 */
- union {
- __IO uint32_t SCMR0;
-
- struct {
- __IO uint32_t scmr0 : 32;
- } SCMR0_b;
- };
- /* Address 0x004 */
- union {
- __IO uint32_t SCMR1;
-
- struct {
- __IO uint32_t scmr1 : 32;
- } SCMR1_b;
- };
- /* Address 0x008 */
- union {
- __IO uint32_t SCMR2;
-
- struct {
- __IO uint32_t scmr2 : 32;
- } SCMR2_b;
- };
- /* Address 0x00C */
- union {
- __IO uint32_t SCMR3;
-
- struct {
- __IO uint32_t scmr3 : 32;
- } SCMR3_b;
- };
- /* Address 0x010 */
- union {
- __IO uint32_t SCTR0;
-
- struct {
- __IO uint32_t sctr0 : 32;
- } SCTR0_b;
- };
- /* Address 0x014 */
- union {
- __IO uint32_t SCTR1;
-
- struct {
- __IO uint32_t sctr1 : 32;
- } SCTR1_b;
- };
- /* Addresses 0x018 - 0x01C */
- __O uint32_t RESERVED018[2];
- /* Address 0x020 */
- union {
- __IO uint32_t SCTCR;
-
- struct {
- __IO uint32_t sctcr : 2;
- __IO uint32_t reserved2 : 30;
- } SCTCR_b;
- };
- /* Address 0x024 */
- union {
- __IO uint32_t SCFRC;
-
- struct {
- __IO uint32_t scfrc : 32;
- } SCFRC_b;
- };
- /* Address 0x028 */
- union {
- __I uint32_t SCSSR;
-
- struct {
- __I uint32_t scssr : 32;
- } SCSSR_b;
- };
- /* Address 0x02C */
- union {
- __IO uint32_t SCESL;
-
- struct {
- __IO uint32_t scesl : 32;
- } SCESL_b;
- };
- /* Address 0x030 */
- union {
- __IO uint32_t RXETST;
-
- struct {
- __IO uint32_t rxetst : 32;
- } RXETST_b;
- };
- /* Address 0x034 */
- union {
- __I uint32_t RXTSTP;
-
- struct {
- __I uint32_t rxtstp : 32;
- } RXTSTP_b;
- };
- /* Address 0x038 */
- union {
- __IO uint32_t TXTSTP;
-
- struct {
- __IO uint32_t txtstp : 32;
- } TXTSTP_b;
- };
- /* Address 0x03C */
- union {
- __IO uint32_t IER;
-
- struct {
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
- __IO uint32_t ier : 10;
- __IO uint32_t reserved10 : 22;
-#else
- __IO uint32_t ier : 12;
- __IO uint32_t reserved12 : 20;
-#endif
- } IER_b;
- };
- /* Address 0x040 */
- union {
- __IO uint32_t ISR;
-
- struct {
- __IO uint32_t txint : 1;
- __IO uint32_t headerrxint : 1;
- __IO uint32_t rxint : 1;
- __IO uint32_t unused_3_3 : 1;
- __IO uint32_t match : 4;
- __IO uint32_t timeout : 2;
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
- __IO uint32_t reserved10 : 22;
-#else
- __IO uint32_t rxaddnomatch : 1;
- __IO uint32_t rxaddmatch : 1;
- __IO uint32_t reserved12 : 20;
-#endif
- } ISR_b;
- };
- /* Address 0x044 */
- union {
- __IO uint32_t SCTL;
-
- struct {
- __IO uint32_t sctl : 7;
- __IO uint32_t reserved7 : 25;
- } SCTL_b;
- };
- /* Address 0x048 */
- union {
- __IO uint32_t PHYTXTUNETIME;
-
- struct {
- __IO uint32_t phytxtunetime : 8;
- __IO uint32_t phyrx2txtime : 8;
- __IO uint32_t reserved16 : 16;
- } PHYTXTUNETIME_b;
- };
- /* Address 0x04C */
- union {
- __IO uint32_t PHYRXTUNETIME;
-
- struct {
- __IO uint32_t phyrxtunetime : 8;
- __IO uint32_t reserved8 : 24;
- } PHYRXTUNETIME_b;
- };
- /* Address 0x050 */
- __O uint32_t RESERVED050[1];
- /* Address 0x054 */
- union {
- __IO uint32_t TURNAROUNDTIME;
-
- struct {
- __IO uint32_t turnaroundtime : 8;
- __IO uint32_t reserved8 : 24;
- } TURNAROUNDTIME_b;
- };
- /* Address 0x058 */
- union {
- __IO uint32_t BACKOFFTIME;
-
- struct {
- __IO uint32_t backofftime : 8;
- __IO uint32_t reserved8 : 24;
- } BACKOFFTIME_b;
- };
- /* Addresses 0x05C - 0x06C */
- __O uint32_t RESERVED05C[5];
- /* Address 0x070 */
- union {
- __IO uint32_t PRBS_SEED;
-
- struct {
- __IO uint32_t prbs_seed : 15;
- __IO uint32_t reserved15 : 17;
- } PRBS_SEED_b;
- };
- /* Addresses 0x074 - 0x078 */
- __O uint32_t RESERVED074[2];
- /* Address 0x07C */
- union {
- __IO uint32_t SM_STATE;
-
- struct {
- __IO uint32_t sm_state : 7;
- __IO uint32_t reserved7 : 25;
- } SM_STATE_b;
- };
- /* Address 0x080 */
- union {
- __IO uint32_t LIFSTURNAROUNDTIME;
-
- struct {
- __IO uint32_t lifsturnaroundtime : 8;
- __IO uint32_t reserved8 : 24;
- } LIFSTURNAROUNDTIME_b;
- };
- /* Address 0x084 */
- union {
- __IO uint32_t HDR_CTRL;
-
- struct {
- __IO uint32_t hdr_ctrl : 2;
- __IO uint32_t reserved2 : 30;
- } HDR_CTRL_b;
- };
- /* Address 0x088 */
- union {
- __IO uint32_t MISR;
-
- struct {
- __IO uint32_t misr : 10;
- __IO uint32_t reserved10 : 22;
- } MISR_b;
- };
- /* Addresses 0x08C - 0x0F8 */
- __O uint32_t RESERVED08C[28];
- /* Address 0x0FC */
- union {
- __I uint32_t IDENTIFIER;
-
- struct {
- __I uint32_t identifier : 32;
- } IDENTIFIER_b;
- };
- /* Addresses 0x100 - 0x1BC */
- __O uint32_t RESERVED100[48];
- /* Address 0x1C0 */
- union {
- __IO uint32_t TXCTL;
-
- struct {
- __IO uint32_t sch : 1;
- __IO uint32_t ss : 1;
- __IO uint32_t slotack : 1;
- __IO uint32_t aa : 1;
- __IO uint32_t mode : 2;
- __IO uint32_t reserved6 : 26;
- } TXCTL_b;
- };
- /* Address 0x1C4 */
- union {
- __I uint32_t TXSTAT;
-
- struct {
- __I uint32_t txstat : 5;
- __I uint32_t txto : 1;
- __I uint32_t txpcto : 1;
- __I uint32_t reserved7 : 25;
- } TXSTAT_b;
- };
- /* Address 0x1C8 */
- union {
- __IO uint32_t TXMBEBT;
-
- struct {
- __IO uint32_t minbe : 4;
- __IO uint32_t maxbo : 3;
- __IO uint32_t ble : 1;
- __IO uint32_t maxbe : 4;
- __IO uint32_t frcdly : 1;
- __IO uint32_t hide : 4;
- __IO uint32_t reserved17 : 15;
- } TXMBEBT_b;
- };
- /* Address 0x1CC */
- union {
- __IO uint32_t TXCSMAC;
-
- struct {
- __IO uint32_t txcsmac : 18;
- __IO uint32_t reserved18 : 14;
- } TXCSMAC_b;
- };
- /* Address 0x1D0 */
- union {
- __IO uint32_t TXTRIES;
-
- struct {
- __IO uint32_t txtries : 4;
- __IO uint32_t reserved4 : 28;
- } TXTRIES_b;
- };
- /* Address 0x1D4 */
- union {
- __IO uint32_t TXPEND;
-
- struct {
- __IO uint32_t txpend : 1;
- __IO uint32_t reserved1 : 31;
- } TXPEND_b;
- };
- /* Address 0x1D8 */
- union {
- __IO uint32_t TXASC;
-
- struct {
- __IO uint32_t txasc : 1;
- __IO uint32_t reserved1 : 31;
- } TXASC_b;
- };
- /* Address 0x1DC */
- union {
- __IO uint32_t TXBUFAD;
-
- struct {
- __IO uint32_t txbufad : 32;
- } TXBUFAD_b;
- };
- /* Address 0x1E0 */
- union {
- __IO uint32_t TXTO;
-
- struct {
- __IO uint32_t tx_to_len : 7;
- __IO uint32_t tx_to_ena : 1;
- __IO uint32_t tx_topc_ena : 1;
- __IO uint32_t reserved9 : 23;
- } TXTO_b;
- };
- /* Addresses 0x1E4 - 0x2BC */
- __O uint32_t RESERVED1E4[55];
- /* Address 0x2C0 */
- union {
- __IO uint32_t RXCTL;
-
- struct {
- __IO uint32_t rxctl : 5;
- __IO uint32_t reserved5 : 27;
- } RXCTL_b;
- };
- /* Address 0x2C4 */
- union {
- __I uint32_t RXSTAT;
-
- struct {
- __I uint32_t fcs_error : 1;
- __I uint32_t abort : 1;
- __I uint32_t unused_2_2 : 1;
- __I uint32_t unused_3_3 : 1;
- __I uint32_t mod_in_packet : 1;
- __I uint32_t malformed : 1;
- __I uint32_t reserved6 : 26;
- } RXSTAT_b;
- };
- /* Address 0x2C8 */
- union {
- __IO uint32_t RXMPID;
-
- struct {
- __IO uint32_t rxmpid : 18;
- __IO uint32_t reserved18 : 14;
- } RXMPID_b;
- };
- /* Address 0x2CC */
- union {
- __IO uint32_t RXMSAD;
-
- struct {
- __IO uint32_t rxmsad : 16;
- __IO uint32_t reserved16 : 16;
- } RXMSAD_b;
- };
- /* Address 0x2D0 */
- union {
- __IO uint32_t RXMEADL;
-
- struct {
- __IO uint32_t rxmeadl : 32;
- } RXMEADL_b;
- };
- /* Address 0x2D4 */
- union {
- __IO uint32_t RXMEADH;
-
- struct {
- __IO uint32_t rxmeadh : 32;
- } RXMEADH_b;
- };
- /* Address 0x2D8 */
- __O uint32_t RESERVED2D8[1];
- /* Address 0x2DC */
- union {
- __IO uint32_t RXBUFAD;
-
- struct {
- __IO uint32_t rxbufad : 32;
- } RXBUFAD_b;
- };
- /* Address 0x2E0 */
- union {
- __IO uint32_t RXPROM;
-
- struct {
- __IO uint32_t rxprom : 2;
- __IO uint32_t reserved2 : 30;
- } RXPROM_b;
- };
- /* Address 0x2E4 */
- union {
- __IO uint32_t RXMPID_SEC;
-
- struct {
- __IO uint32_t rxmpid_sec : 19;
- __IO uint32_t reserved19 : 13;
- } RXMPID_SEC_b;
- };
- /* Address 0x2E8 */
- union {
- __IO uint32_t RXMSAD_SEC;
-
- struct {
- __IO uint32_t rxmsad_sec : 16;
- __IO uint32_t reserved16 : 16;
- } RXMSAD_SEC_b;
- };
- /* Address 0x2EC */
- union {
- __IO uint32_t RXMEADL_SEC;
-
- struct {
- __IO uint32_t rxmeadl_sec : 32;
- } RXMEADL_SEC_b;
- };
- /* Address 0x2F0 */
- union {
- __IO uint32_t RXMEADH_SEC;
-
- struct {
- __IO uint32_t rxmeadh_sec : 32;
- } RXMEADH_SEC_b;
- };
- /* Addresses 0x2F4 - 0x2FC */
- __O uint32_t RESERVED2F4[3];
- /* Address 0x300 */
- union {
- __IO uint32_t DMA_ADDR;
-
- struct {
- __IO uint32_t dma_addr : 32;
- } DMA_ADDR_b;
- };
- /* Address 0x304 */
- union {
- __I uint32_t DMA_RD_DATA;
-
- struct {
- __I uint32_t dma_rd_data : 32;
- } DMA_RD_DATA_b;
- };
- /* Address 0x308 */
- union {
- __IO uint32_t DMA_WR_DATA;
-
- struct {
- __IO uint32_t dma_wr_data : 32;
- } DMA_WR_DATA_b;
- };
- /* Address 0x30C */
- union {
- __IO uint32_t DMA_ADDR_OFFSET;
-
- struct {
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
- __IO uint32_t reserved0 : 15;
- __IO uint32_t dma_addr_offset : 17;
-#else
- __IO uint32_t reserved0 : 17;
- __IO uint32_t dma_addr_offset : 15;
-#endif
- } DMA_ADDR_OFFSET_b;
- };
- /* Addresses 0x310 - 0x3FC */
- __O uint32_t RESERVED310[60];
- /* Address 0x400 */
- union {
- __IO uint32_t DMA_FROM_ADC;
-
- struct {
- __IO uint32_t activate : 1;
- __IO uint32_t mode : 4;
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
- __IO uint32_t reserved5 : 27;
-#else
- __IO uint32_t safe : 1;
- __IO uint32_t reserved6 : 26;
-#endif
- } DMA_FROM_ADC_b;
- };
- /* Address 0x404 */
- union {
- __IO uint32_t PHY_MCTRL;
-
- struct {
- __IO uint32_t bbc_rmi_req : 1;
- __IO uint32_t reserved1 : 31;
- } PHY_MCTRL_b;
- };
- /* Address 0x408 */
- union {
- __I uint32_t PHY_MSTATUS;
-
- struct {
- __I uint32_t bbc_rmi_ack : 1;
- __I uint32_t reserved1 : 31;
- } PHY_MSTATUS_b;
- };
- /* Addresses 0x40C - 0xFF0 */
- __O uint32_t RESERVED40C[762];
- /* Address 0xFF4 */
- union {
- __IO uint32_t POWERDOWN;
-
- struct {
- __IO uint32_t soft_reset : 1;
- __IO uint32_t force_softreset : 1;
- __IO uint32_t enable_flags_with_core_bus : 1;
- __IO uint32_t reserved3 : 28;
- __IO uint32_t powerdown : 1;
- } POWERDOWN_b;
- };
- /* Address 0xFF8 */
- __O uint32_t RESERVEDFF8[1];
- /* Address 0xFFC */
- union {
- __I uint32_t MODULEID;
-
- struct {
- __I uint32_t aperture : 8;
- __I uint32_t minor_revision : 4;
- __I uint32_t major_revision : 4;
- __I uint32_t identifier : 16;
- } MODULEID_b;
- };
- } ZB_MAC_IF_Type;
-
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
- #define ZBMAC_SCMR0_SCMR0_Pos 0
- #define ZBMAC_SCMR0_SCMR0_Msk 0x0ffffffffUL
- #define ZBMAC_SCMR1_SCMR1_Pos 0
- #define ZBMAC_SCMR1_SCMR1_Msk 0x0ffffffffUL
- #define ZBMAC_SCMR2_SCMR2_Pos 0
- #define ZBMAC_SCMR2_SCMR2_Msk 0x0ffffffffUL
- #define ZBMAC_SCMR3_SCMR3_Pos 0
- #define ZBMAC_SCMR3_SCMR3_Msk 0x0ffffffffUL
- #define ZBMAC_SCTR0_SCTR0_Pos 0
- #define ZBMAC_SCTR0_SCTR0_Msk 0x0ffffffffUL
- #define ZBMAC_SCTR1_SCTR1_Pos 0
- #define ZBMAC_SCTR1_SCTR1_Msk 0x0ffffffffUL
- #define ZBMAC_SCTCR_SCTCR_Pos 0
- #define ZBMAC_SCTCR_SCTCR_Msk 0x03UL
- #define ZBMAC_SCFRC_SCFRC_Pos 0
- #define ZBMAC_SCFRC_SCFRC_Msk 0x0ffffffffUL
- #define ZBMAC_SCSSR_SCSSR_Pos 0
- #define ZBMAC_SCSSR_SCSSR_Msk 0x0ffffffffUL
- #define ZBMAC_SCESL_SCESL_Pos 0
- #define ZBMAC_SCESL_SCESL_Msk 0x0ffffffffUL
- #define ZBMAC_RXETST_RXETST_Pos 0
- #define ZBMAC_RXETST_RXETST_Msk 0x0ffffffffUL
- #define ZBMAC_RXTSTP_RXTSTP_Pos 0
- #define ZBMAC_RXTSTP_RXTSTP_Msk 0x0ffffffffUL
- #define ZBMAC_TXTSTP_TXTSTP_Pos 0
- #define ZBMAC_TXTSTP_TXTSTP_Msk 0x0ffffffffUL
- #define ZBMAC_IER_IER_Pos 0
- #define ZBMAC_IER_IER_Msk 0x03ffUL
- #define ZBMAC_ISR_TXINT_Pos 0
- #define ZBMAC_ISR_TXINT_Msk 0x01UL
- #define ZBMAC_ISR_HEADERRXINT_Pos 1
- #define ZBMAC_ISR_HEADERRXINT_Msk 0x02UL
- #define ZBMAC_ISR_RXINT_Pos 2
- #define ZBMAC_ISR_RXINT_Msk 0x04UL
- #define ZBMAC_ISR_UNUSED_3_3_Pos 3
- #define ZBMAC_ISR_UNUSED_3_3_Msk 0x08UL
- #define ZBMAC_ISR_MATCH_Pos 4
- #define ZBMAC_ISR_MATCH_Msk 0x0f0UL
- #define ZBMAC_ISR_TIMEOUT_Pos 8
- #define ZBMAC_ISR_TIMEOUT_Msk 0x0300UL
- #define ZBMAC_SCTL_SCTL_Pos 0
- #define ZBMAC_SCTL_SCTL_Msk 0x07fUL
- #define ZBMAC_PHYTXTUNETIME_PHYTXTUNETIME_Pos 0
- #define ZBMAC_PHYTXTUNETIME_PHYTXTUNETIME_Msk 0x0ffUL
- #define ZBMAC_PHYTXTUNETIME_PHYRX2TXTIME_Pos 8
- #define ZBMAC_PHYTXTUNETIME_PHYRX2TXTIME_Msk 0x0ff00UL
- #define ZBMAC_PHYRXTUNETIME_PHYRXTUNETIME_Pos 0
- #define ZBMAC_PHYRXTUNETIME_PHYRXTUNETIME_Msk 0x0ffUL
- #define ZBMAC_TURNAROUNDTIME_TURNAROUNDTIME_Pos 0
- #define ZBMAC_TURNAROUNDTIME_TURNAROUNDTIME_Msk 0x0ffUL
- #define ZBMAC_BACKOFFTIME_BACKOFFTIME_Pos 0
- #define ZBMAC_BACKOFFTIME_BACKOFFTIME_Msk 0x0ffUL
- #define ZBMAC_PRBS_SEED_PRBS_SEED_Pos 0
- #define ZBMAC_PRBS_SEED_PRBS_SEED_Msk 0x07fffUL
- #define ZBMAC_SM_STATE_SM_STATE_Pos 0
- #define ZBMAC_SM_STATE_SM_STATE_Msk 0x07fUL
- #define ZBMAC_LIFSTURNAROUNDTIME_LIFSTURNAROUNDTIME_Pos 0
- #define ZBMAC_LIFSTURNAROUNDTIME_LIFSTURNAROUNDTIME_Msk 0x0ffUL
- #define ZBMAC_HDR_CTRL_HDR_CTRL_Pos 0
- #define ZBMAC_HDR_CTRL_HDR_CTRL_Msk 0x03UL
- #define ZBMAC_MISR_MISR_Pos 0
- #define ZBMAC_MISR_MISR_Msk 0x03ffUL
- #define ZBMAC_IDENTIFIER_IDENTIFIER_Pos 0
- #define ZBMAC_IDENTIFIER_IDENTIFIER_Msk 0x0ffffffffUL
- #define ZBMAC_TXCTL_SCH_Pos 0
- #define ZBMAC_TXCTL_SCH_Msk 0x01UL
- #define ZBMAC_TXCTL_SS_Pos 1
- #define ZBMAC_TXCTL_SS_Msk 0x02UL
- #define ZBMAC_TXCTL_SLOTACK_Pos 2
- #define ZBMAC_TXCTL_SLOTACK_Msk 0x04UL
- #define ZBMAC_TXCTL_AA_Pos 3
- #define ZBMAC_TXCTL_AA_Msk 0x08UL
- #define ZBMAC_TXCTL_MODE_Pos 4
- #define ZBMAC_TXCTL_MODE_Msk 0x030UL
- #define ZBMAC_TXSTAT_TXSTAT_Pos 0
- #define ZBMAC_TXSTAT_TXSTAT_Msk 0x01fUL
- #define ZBMAC_TXSTAT_TXTO_Pos 5
- #define ZBMAC_TXSTAT_TXTO_Msk 0x020UL
- #define ZBMAC_TXSTAT_TXPCTO_Pos 6
- #define ZBMAC_TXSTAT_TXPCTO_Msk 0x040UL
- #define ZBMAC_TXMBEBT_MINBE_Pos 0
- #define ZBMAC_TXMBEBT_MINBE_Msk 0x0fUL
- #define ZBMAC_TXMBEBT_MAXBO_Pos 4
- #define ZBMAC_TXMBEBT_MAXBO_Msk 0x070UL
- #define ZBMAC_TXMBEBT_BLE_Pos 7
- #define ZBMAC_TXMBEBT_BLE_Msk 0x080UL
- #define ZBMAC_TXMBEBT_MAXBE_Pos 8
- #define ZBMAC_TXMBEBT_MAXBE_Msk 0x0f00UL
- #define ZBMAC_TXMBEBT_FRCDLY_Pos 12
- #define ZBMAC_TXMBEBT_FRCDLY_Msk 0x01000UL
- #define ZBMAC_TXMBEBT_HIDE_Pos 13
- #define ZBMAC_TXMBEBT_HIDE_Msk 0x01e000UL
- #define ZBMAC_TXCSMAC_TXCSMAC_Pos 0
- #define ZBMAC_TXCSMAC_TXCSMAC_Msk 0x03ffffUL
- #define ZBMAC_TXTRIES_TXTRIES_Pos 0
- #define ZBMAC_TXTRIES_TXTRIES_Msk 0x0fUL
- #define ZBMAC_TXPEND_TXPEND_Pos 0
- #define ZBMAC_TXPEND_TXPEND_Msk 0x01UL
- #define ZBMAC_TXASC_TXASC_Pos 0
- #define ZBMAC_TXASC_TXASC_Msk 0x01UL
- #define ZBMAC_TXBUFAD_TXBUFAD_Pos 0
- #define ZBMAC_TXBUFAD_TXBUFAD_Msk 0x0ffffffffUL
- #define ZBMAC_TXTO_TX_TO_LEN_Pos 0
- #define ZBMAC_TXTO_TX_TO_LEN_Msk 0x07fUL
- #define ZBMAC_TXTO_TX_TO_ENA_Pos 7
- #define ZBMAC_TXTO_TX_TO_ENA_Msk 0x080UL
- #define ZBMAC_TXTO_TX_TOPC_ENA_Pos 8
- #define ZBMAC_TXTO_TX_TOPC_ENA_Msk 0x0100UL
- #define ZBMAC_RXCTL_RXCTL_Pos 0
- #define ZBMAC_RXCTL_RXCTL_Msk 0x01fUL
- #define ZBMAC_RXSTAT_FCS_ERROR_Pos 0
- #define ZBMAC_RXSTAT_FCS_ERROR_Msk 0x01UL
- #define ZBMAC_RXSTAT_ABORT_Pos 1
- #define ZBMAC_RXSTAT_ABORT_Msk 0x02UL
- #define ZBMAC_RXSTAT_UNUSED_2_2_Pos 2
- #define ZBMAC_RXSTAT_UNUSED_2_2_Msk 0x04UL
- #define ZBMAC_RXSTAT_UNUSED_3_3_Pos 3
- #define ZBMAC_RXSTAT_UNUSED_3_3_Msk 0x08UL
- #define ZBMAC_RXSTAT_MOD_IN_PACKET_Pos 4
- #define ZBMAC_RXSTAT_MOD_IN_PACKET_Msk 0x010UL
- #define ZBMAC_RXSTAT_MALFORMED_Pos 5
- #define ZBMAC_RXSTAT_MALFORMED_Msk 0x020UL
- #define ZBMAC_RXMPID_RXMPID_Pos 0
- #define ZBMAC_RXMPID_RXMPID_Msk 0x03ffffUL
- #define ZBMAC_RXMSAD_RXMSAD_Pos 0
- #define ZBMAC_RXMSAD_RXMSAD_Msk 0x0ffffUL
- #define ZBMAC_RXMEADL_RXMEADL_Pos 0
- #define ZBMAC_RXMEADL_RXMEADL_Msk 0x0ffffffffUL
- #define ZBMAC_RXMEADH_RXMEADH_Pos 0
- #define ZBMAC_RXMEADH_RXMEADH_Msk 0x0ffffffffUL
- #define ZBMAC_RXBUFAD_RXBUFAD_Pos 0
- #define ZBMAC_RXBUFAD_RXBUFAD_Msk 0x0ffffffffUL
- #define ZBMAC_RXPROM_RXPROM_Pos 0
- #define ZBMAC_RXPROM_RXPROM_Msk 0x03UL
- #define ZBMAC_RXMPID_SEC_RXMPID_SEC_Pos 0
- #define ZBMAC_RXMPID_SEC_RXMPID_SEC_Msk 0x07ffffUL
- #define ZBMAC_RXMSAD_SEC_RXMSAD_SEC_Pos 0
- #define ZBMAC_RXMSAD_SEC_RXMSAD_SEC_Msk 0x0ffffUL
- #define ZBMAC_RXMEADL_SEC_RXMEADL_SEC_Pos 0
- #define ZBMAC_RXMEADL_SEC_RXMEADL_SEC_Msk 0x0ffffffffUL
- #define ZBMAC_RXMEADH_SEC_RXMEADH_SEC_Pos 0
- #define ZBMAC_RXMEADH_SEC_RXMEADH_SEC_Msk 0x0ffffffffUL
- #define ZBMAC_DMA_ADDR_DMA_ADDR_Pos 0
- #define ZBMAC_DMA_ADDR_DMA_ADDR_Msk 0x0ffffffffUL
- #define ZBMAC_DMA_RD_DATA_DMA_RD_DATA_Pos 0
- #define ZBMAC_DMA_RD_DATA_DMA_RD_DATA_Msk 0x0ffffffffUL
- #define ZBMAC_DMA_WR_DATA_DMA_WR_DATA_Pos 0
- #define ZBMAC_DMA_WR_DATA_DMA_WR_DATA_Msk 0x0ffffffffUL
- #define ZBMAC_DMA_ADDR_OFFSET_DMA_ADDR_OFFSET_Pos 15
- #define ZBMAC_DMA_ADDR_OFFSET_DMA_ADDR_OFFSET_Msk 0x0ffff8000UL
- #define ZBMAC_DMA_FROM_ADC_ACTIVATE_Pos 0
- #define ZBMAC_DMA_FROM_ADC_ACTIVATE_Msk 0x01UL
- #define ZBMAC_DMA_FROM_ADC_MODE_Pos 1
- #define ZBMAC_DMA_FROM_ADC_MODE_Msk 0x01eUL
- #define ZBMAC_PHY_MCTRL_BBC_RMI_REQ_Pos 0
- #define ZBMAC_PHY_MCTRL_BBC_RMI_REQ_Msk 0x01UL
- #define ZBMAC_PHY_MSTATUS_BBC_RMI_ACK_Pos 0
- #define ZBMAC_PHY_MSTATUS_BBC_RMI_ACK_Msk 0x01UL
- #define ZBMAC_POWERDOWN_SOFT_RESET_Pos 0
- #define ZBMAC_POWERDOWN_SOFT_RESET_Msk 0x01UL
- #define ZBMAC_POWERDOWN_FORCE_SOFTRESET_Pos 1
- #define ZBMAC_POWERDOWN_FORCE_SOFTRESET_Msk 0x02UL
- #define ZBMAC_POWERDOWN_ENABLE_FLAGS_WITH_CORE_BUS_Pos 2
- #define ZBMAC_POWERDOWN_ENABLE_FLAGS_WITH_CORE_BUS_Msk 0x04UL
- #define ZBMAC_POWERDOWN_POWERDOWN_Pos 31
- #define ZBMAC_POWERDOWN_POWERDOWN_Msk 0x080000000UL
- #define ZBMAC_MODULEID_APERTURE_Pos 0
- #define ZBMAC_MODULEID_APERTURE_Msk 0x0ffUL
- #define ZBMAC_MODULEID_MINOR_REVISION_Pos 8
- #define ZBMAC_MODULEID_MINOR_REVISION_Msk 0x0f00UL
- #define ZBMAC_MODULEID_MAJOR_REVISION_Pos 12
- #define ZBMAC_MODULEID_MAJOR_REVISION_Msk 0x0f000UL
- #define ZBMAC_MODULEID_IDENTIFIER_Pos 16
- #define ZBMAC_MODULEID_IDENTIFIER_Msk 0x0ffff0000UL
-#else
- #define ZB_MAC_SCMR0_SCMR0_Pos 0
- #define ZB_MAC_SCMR0_SCMR0_Msk 0x0ffffffffUL
- #define ZB_MAC_SCMR1_SCMR1_Pos 0
- #define ZB_MAC_SCMR1_SCMR1_Msk 0x0ffffffffUL
- #define ZB_MAC_SCMR2_SCMR2_Pos 0
- #define ZB_MAC_SCMR2_SCMR2_Msk 0x0ffffffffUL
- #define ZB_MAC_SCMR3_SCMR3_Pos 0
- #define ZB_MAC_SCMR3_SCMR3_Msk 0x0ffffffffUL
- #define ZB_MAC_SCTR0_SCTR0_Pos 0
- #define ZB_MAC_SCTR0_SCTR0_Msk 0x0ffffffffUL
- #define ZB_MAC_SCTR1_SCTR1_Pos 0
- #define ZB_MAC_SCTR1_SCTR1_Msk 0x0ffffffffUL
- #define ZB_MAC_SCTCR_SCTCR_Pos 0
- #define ZB_MAC_SCTCR_SCTCR_Msk 0x03UL
- #define ZB_MAC_SCFRC_SCFRC_Pos 0
- #define ZB_MAC_SCFRC_SCFRC_Msk 0x0ffffffffUL
- #define ZB_MAC_SCSSR_SCSSR_Pos 0
- #define ZB_MAC_SCSSR_SCSSR_Msk 0x0ffffffffUL
- #define ZB_MAC_SCESL_SCESL_Pos 0
- #define ZB_MAC_SCESL_SCESL_Msk 0x0ffffffffUL
- #define ZB_MAC_RXETST_RXETST_Pos 0
- #define ZB_MAC_RXETST_RXETST_Msk 0x0ffffffffUL
- #define ZB_MAC_RXTSTP_RXTSTP_Pos 0
- #define ZB_MAC_RXTSTP_RXTSTP_Msk 0x0ffffffffUL
- #define ZB_MAC_TXTSTP_TXTSTP_Pos 0
- #define ZB_MAC_TXTSTP_TXTSTP_Msk 0x0ffffffffUL
- #define ZB_MAC_IER_IER_Pos 0
- #define ZB_MAC_IER_IER_Msk 0x0fffUL
- #define ZB_MAC_ISR_TXINT_Pos 0
- #define ZB_MAC_ISR_TXINT_Msk 0x01UL
- #define ZB_MAC_ISR_HEADERRXINT_Pos 1
- #define ZB_MAC_ISR_HEADERRXINT_Msk 0x02UL
- #define ZB_MAC_ISR_RXINT_Pos 2
- #define ZB_MAC_ISR_RXINT_Msk 0x04UL
- #define ZB_MAC_ISR_UNUSED_3_3_Pos 3
- #define ZB_MAC_ISR_UNUSED_3_3_Msk 0x08UL
- #define ZB_MAC_ISR_MATCH_Pos 4
- #define ZB_MAC_ISR_MATCH_Msk 0x0f0UL
- #define ZB_MAC_ISR_TIMEOUT_Pos 8
- #define ZB_MAC_ISR_TIMEOUT_Msk 0x0300UL
- #define ZB_MAC_ISR_RXNOMATCH_Pos 10
- #define ZB_MAC_ISR_RXNOMATCH_Msk 0x0400UL
- #define ZB_MAC_ISR_RXMATCH_Pos 11
- #define ZB_MAC_ISR_RXMATCH_Msk 0x0800UL
- #define ZB_MAC_SCTL_SCTL_Pos 0
- #define ZB_MAC_SCTL_SCTL_Msk 0x07fUL
- #define ZB_MAC_PHYTXTUNETIME_PHYTXTUNETIME_Pos 0
- #define ZB_MAC_PHYTXTUNETIME_PHYTXTUNETIME_Msk 0x0ffUL
- #define ZB_MAC_PHYTXTUNETIME_PHYRX2TXTIME_Pos 8
- #define ZB_MAC_PHYTXTUNETIME_PHYRX2TXTIME_Msk 0x0ff00UL
- #define ZB_MAC_PHYRXTUNETIME_PHYRXTUNETIME_Pos 0
- #define ZB_MAC_PHYRXTUNETIME_PHYRXTUNETIME_Msk 0x0ffUL
- #define ZB_MAC_TURNAROUNDTIME_TURNAROUNDTIME_Pos 0
- #define ZB_MAC_TURNAROUNDTIME_TURNAROUNDTIME_Msk 0x0ffUL
- #define ZB_MAC_BACKOFFTIME_BACKOFFTIME_Pos 0
- #define ZB_MAC_BACKOFFTIME_BACKOFFTIME_Msk 0x0ffUL
- #define ZB_MAC_PRBS_SEED_PRBS_SEED_Pos 0
- #define ZB_MAC_PRBS_SEED_PRBS_SEED_Msk 0x07fffUL
- #define ZB_MAC_SM_STATE_SM_STATE_Pos 0
- #define ZB_MAC_SM_STATE_SM_STATE_Msk 0x07fUL
- #define ZB_MAC_LIFSTURNAROUNDTIME_LIFSTURNAROUNDTIME_Pos 0
- #define ZB_MAC_LIFSTURNAROUNDTIME_LIFSTURNAROUNDTIME_Msk 0x0ffUL
- #define ZB_MAC_HDR_CTRL_HDR_CTRL_Pos 0
- #define ZB_MAC_HDR_CTRL_HDR_CTRL_Msk 0x03UL
- #define ZB_MAC_MISR_MISR_Pos 0
- #define ZB_MAC_MISR_MISR_Msk 0x03ffUL
- #define ZB_MAC_IDENTIFIER_IDENTIFIER_Pos 0
- #define ZB_MAC_IDENTIFIER_IDENTIFIER_Msk 0x0ffffffffUL
- #define ZB_MAC_TXCTL_SCH_Pos 0
- #define ZB_MAC_TXCTL_SCH_Msk 0x01UL
- #define ZB_MAC_TXCTL_SS_Pos 1
- #define ZB_MAC_TXCTL_SS_Msk 0x02UL
- #define ZB_MAC_TXCTL_SLOTACK_Pos 2
- #define ZB_MAC_TXCTL_SLOTACK_Msk 0x04UL
- #define ZB_MAC_TXCTL_AA_Pos 3
- #define ZB_MAC_TXCTL_AA_Msk 0x08UL
- #define ZB_MAC_TXCTL_MODE_Pos 4
- #define ZB_MAC_TXCTL_MODE_Msk 0x030UL
- #define ZB_MAC_TXSTAT_TXSTAT_Pos 0
- #define ZB_MAC_TXSTAT_TXSTAT_Msk 0x01fUL
- #define ZB_MAC_TXSTAT_TXTO_Pos 5
- #define ZB_MAC_TXSTAT_TXTO_Msk 0x020UL
- #define ZB_MAC_TXSTAT_TXPCTO_Pos 6
- #define ZB_MAC_TXSTAT_TXPCTO_Msk 0x040UL
- #define ZB_MAC_TXMBEBT_MINBE_Pos 0
- #define ZB_MAC_TXMBEBT_MINBE_Msk 0x0fUL
- #define ZB_MAC_TXMBEBT_MAXBO_Pos 4
- #define ZB_MAC_TXMBEBT_MAXBO_Msk 0x070UL
- #define ZB_MAC_TXMBEBT_BLE_Pos 7
- #define ZB_MAC_TXMBEBT_BLE_Msk 0x080UL
- #define ZB_MAC_TXMBEBT_MAXBE_Pos 8
- #define ZB_MAC_TXMBEBT_MAXBE_Msk 0x0f00UL
- #define ZB_MAC_TXMBEBT_FRCDLY_Pos 12
- #define ZB_MAC_TXMBEBT_FRCDLY_Msk 0x01000UL
- #define ZB_MAC_TXMBEBT_HIDE_Pos 13
- #define ZB_MAC_TXMBEBT_HIDE_Msk 0x01e000UL
- #define ZB_MAC_TXCSMAC_TXCSMAC_Pos 0
- #define ZB_MAC_TXCSMAC_TXCSMAC_Msk 0x03ffffUL
- #define ZB_MAC_TXTRIES_TXTRIES_Pos 0
- #define ZB_MAC_TXTRIES_TXTRIES_Msk 0x0fUL
- #define ZB_MAC_TXPEND_TXPEND_Pos 0
- #define ZB_MAC_TXPEND_TXPEND_Msk 0x01UL
- #define ZB_MAC_TXASC_TXASC_Pos 0
- #define ZB_MAC_TXASC_TXASC_Msk 0x01UL
- #define ZB_MAC_TXBUFAD_TXBUFAD_Pos 0
- #define ZB_MAC_TXBUFAD_TXBUFAD_Msk 0x0ffffffffUL
- #define ZB_MAC_TXTO_TX_TO_LEN_Pos 0
- #define ZB_MAC_TXTO_TX_TO_LEN_Msk 0x07fUL
- #define ZB_MAC_TXTO_TX_TO_ENA_Pos 7
- #define ZB_MAC_TXTO_TX_TO_ENA_Msk 0x080UL
- #define ZB_MAC_TXTO_TX_TOPC_ENA_Pos 8
- #define ZB_MAC_TXTO_TX_TOPC_ENA_Msk 0x0100UL
- #define ZB_MAC_RXCTL_RXCTL_Pos 0
- #define ZB_MAC_RXCTL_RXCTL_Msk 0x01fUL
- #define ZB_MAC_RXSTAT_FCS_ERROR_Pos 0
- #define ZB_MAC_RXSTAT_FCS_ERROR_Msk 0x01UL
- #define ZB_MAC_RXSTAT_ABORT_Pos 1
- #define ZB_MAC_RXSTAT_ABORT_Msk 0x02UL
- #define ZB_MAC_RXSTAT_UNUSED_2_2_Pos 2
- #define ZB_MAC_RXSTAT_UNUSED_2_2_Msk 0x04UL
- #define ZB_MAC_RXSTAT_UNUSED_3_3_Pos 3
- #define ZB_MAC_RXSTAT_UNUSED_3_3_Msk 0x08UL
- #define ZB_MAC_RXSTAT_MOD_IN_PACKET_Pos 4
- #define ZB_MAC_RXSTAT_MOD_IN_PACKET_Msk 0x010UL
- #define ZB_MAC_RXSTAT_MALFORMED_Pos 5
- #define ZB_MAC_RXSTAT_MALFORMED_Msk 0x020UL
- #define ZB_MAC_RXMPID_RXMPID_Pos 0
- #define ZB_MAC_RXMPID_RXMPID_Msk 0x03ffffUL
- #define ZB_MAC_RXMSAD_RXMSAD_Pos 0
- #define ZB_MAC_RXMSAD_RXMSAD_Msk 0x0ffffUL
- #define ZB_MAC_RXMEADL_RXMEADL_Pos 0
- #define ZB_MAC_RXMEADL_RXMEADL_Msk 0x0ffffffffUL
- #define ZB_MAC_RXMEADH_RXMEADH_Pos 0
- #define ZB_MAC_RXMEADH_RXMEADH_Msk 0x0ffffffffUL
- #define ZB_MAC_RXBUFAD_RXBUFAD_Pos 0
- #define ZB_MAC_RXBUFAD_RXBUFAD_Msk 0x0ffffffffUL
- #define ZB_MAC_RXPROM_RXPROM_Pos 0
- #define ZB_MAC_RXPROM_RXPROM_Msk 0x03UL
- #define ZB_MAC_RXMPID_SEC_RXMPID_SEC_Pos 0
- #define ZB_MAC_RXMPID_SEC_RXMPID_SEC_Msk 0x07ffffUL
- #define ZB_MAC_RXMSAD_SEC_RXMSAD_SEC_Pos 0
- #define ZB_MAC_RXMSAD_SEC_RXMSAD_SEC_Msk 0x0ffffUL
- #define ZB_MAC_RXMEADL_SEC_RXMEADL_SEC_Pos 0
- #define ZB_MAC_RXMEADL_SEC_RXMEADL_SEC_Msk 0x0ffffffffUL
- #define ZB_MAC_RXMEADH_SEC_RXMEADH_SEC_Pos 0
- #define ZB_MAC_RXMEADH_SEC_RXMEADH_SEC_Msk 0x0ffffffffUL
- #define ZB_MAC_DMA_ADDR_DMA_ADDR_Pos 0
- #define ZB_MAC_DMA_ADDR_DMA_ADDR_Msk 0x0ffffffffUL
- #define ZB_MAC_DMA_RD_DATA_DMA_RD_DATA_Pos 0
- #define ZB_MAC_DMA_RD_DATA_DMA_RD_DATA_Msk 0x0ffffffffUL
- #define ZB_MAC_DMA_WR_DATA_DMA_WR_DATA_Pos 0
- #define ZB_MAC_DMA_WR_DATA_DMA_WR_DATA_Msk 0x0ffffffffUL
- #define ZB_MAC_DMA_ADDR_OFFSET_DMA_ADDR_OFFSET_Pos 17
- #define ZB_MAC_DMA_ADDR_OFFSET_DMA_ADDR_OFFSET_Msk 0x0fffe0000UL
- #define ZB_MAC_DMA_FROM_ADC_ACTIVATE_Pos 0
- #define ZB_MAC_DMA_FROM_ADC_ACTIVATE_Msk 0x01UL
- #define ZB_MAC_DMA_FROM_ADC_MODE_Pos 1
- #define ZB_MAC_DMA_FROM_ADC_MODE_Msk 0x01eUL
- #define ZB_MAC_DMA_FROM_ADC_SAFE_Pos 5
- #define ZB_MAC_DMA_FROM_ADC_SAFE_Msk 0x020UL
- #define ZB_MAC_PHY_MCTRL_BBC_RMI_REQ_Pos 0
- #define ZB_MAC_PHY_MCTRL_BBC_RMI_REQ_Msk 0x01UL
- #define ZB_MAC_PHY_MSTATUS_BBC_RMI_ACK_Pos 0
- #define ZB_MAC_PHY_MSTATUS_BBC_RMI_ACK_Msk 0x01UL
- #define ZB_MAC_POWERDOWN_SOFT_RESET_Pos 0
- #define ZB_MAC_POWERDOWN_SOFT_RESET_Msk 0x01UL
- #define ZB_MAC_POWERDOWN_FORCE_SOFTRESET_Pos 1
- #define ZB_MAC_POWERDOWN_FORCE_SOFTRESET_Msk 0x02UL
- #define ZB_MAC_POWERDOWN_ENABLE_FLAGS_WITH_CORE_BUS_Pos 2
- #define ZB_MAC_POWERDOWN_ENABLE_FLAGS_WITH_CORE_BUS_Msk 0x04UL
- #define ZB_MAC_POWERDOWN_POWERDOWN_Pos 31
- #define ZB_MAC_POWERDOWN_POWERDOWN_Msk 0x080000000UL
- #define ZB_MAC_MODULEID_APERTURE_Pos 0
- #define ZB_MAC_MODULEID_APERTURE_Msk 0x0ffUL
- #define ZB_MAC_MODULEID_MINOR_REVISION_Pos 8
- #define ZB_MAC_MODULEID_MINOR_REVISION_Msk 0x0f00UL
- #define ZB_MAC_MODULEID_MAJOR_REVISION_Pos 12
- #define ZB_MAC_MODULEID_MAJOR_REVISION_Msk 0x0f000UL
- #define ZB_MAC_MODULEID_IDENTIFIER_Pos 16
- #define ZB_MAC_MODULEID_IDENTIFIER_Msk 0x0ffff0000UL
-#endif
-
-#endif // __ZB_MAC_IF_H__
diff --git a/third_party/nxp/JN5189/Radio_JN5189/Include/jn518x_zb_modem.h b/third_party/nxp/JN5189/Radio_JN5189/Include/jn518x_zb_modem.h
deleted file mode 100755
index 891e45e..0000000
--- a/third_party/nxp/JN5189/Radio_JN5189/Include/jn518x_zb_modem.h
+++ /dev/null
@@ -1,405 +0,0 @@
-/*
-* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
-* Copyright 2016-2019 NXP
-* All rights reserved.
-*
-* SPDX-License-Identifier: BSD-3-Clause
-*/
-
-#ifndef __ZB_MODEM_IF_H__
-#define __ZB_MODEM_IF_H__
-
- typedef struct {
- /* Address 0x000 */
- union {
- __IO uint32_t MCCA_CTRL;
-
- struct {
- __IO uint32_t rx_cca_mode : 2;
- __IO uint32_t rx_cca_thresh : 10;
- __IO uint32_t rx_cca_or : 1;
- __IO uint32_t reserved13 : 19;
- } MCCA_CTRL_b;
- };
- /* Address 0x004 */
- union {
- __IO uint32_t MTX_CTRL;
-
- struct {
- __IO uint32_t tx_test_en : 1;
- __IO uint32_t tx_test_mode : 1;
- __IO uint32_t tx_pol : 1;
- __IO uint32_t tx_inframe_sync : 1;
- __IO uint32_t reserved4 : 28;
- } MTX_CTRL_b;
- };
- /* Address 0x008 */
- union {
- __IO uint32_t MTX_TST_SEQ;
-
- struct {
- __IO uint32_t tx_test_seq : 32;
- } MTX_TST_SEQ_b;
- };
- /* Address 0x00C */
- union {
- __IO uint32_t MRX_CTRL;
-
- struct {
- __IO uint32_t rx_cor_lo : 6;
- __IO uint32_t rx_cor_hi : 6;
- __IO uint32_t rx_sync_mode : 2;
- __IO uint32_t rx_pol : 2;
- __IO uint32_t rx_pre_num : 3;
- __IO uint32_t rx_early_eop : 2;
- __IO uint32_t rx_agc_rst_en : 1;
- __IO uint32_t rx_agc_rst_thr : 7;
- __IO uint32_t rx_rssi_avg_en : 1;
- __IO uint32_t rx_rssi_pulse_mode : 1;
- __IO uint32_t reserved31 : 1;
- } MRX_CTRL_b;
- };
- /* Address 0x010 */
- union {
- __I uint32_t MSTAT;
-
- struct {
- __I uint32_t rx_pre_state : 2;
- __I uint32_t rx_pre_cnt : 3;
- __I uint32_t rx_ad_ant : 1;
- __I uint32_t rx_rssi_avg : 10;
- __I uint32_t rx_sqi : 8;
- __I uint32_t rx_ccas : 1;
- __I uint32_t rx_ad_switch : 1;
- __I uint32_t reserved26 : 6;
- } MSTAT_b;
- };
- /* Address 0x014 */
- union {
- __IO uint32_t RXFE_CONFIG;
-
- struct {
- __IO uint32_t selfi : 4;
- __IO uint32_t specinv : 1;
- __IO uint32_t bypass_lpf : 1;
- __IO uint32_t bypass_adj : 1;
- __IO uint32_t selfe4demod : 1;
- __IO uint32_t selfe4agc : 1;
- __IO uint32_t loopback : 1;
- __IO uint32_t bitinv : 1;
- __IO uint32_t xcorr_mode : 1;
- __IO uint32_t reserved12 : 20;
- } RXFE_CONFIG_b;
- };
- /* Address 0x018 */
- union {
- __IO uint32_t PHY_MCTRL;
-
- struct {
- __IO uint32_t reserved0 : 1;
- __IO uint32_t miom : 1;
- __IO uint32_t mphyon : 1;
- __IO uint32_t mphydir : 1;
- __IO uint32_t mccat : 1;
- __IO uint32_t medt : 1;
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
- /* ES1 if explicitly configured */
- __IO uint32_t reserved6 : 26;
-#else
- /* ES2 default */
- __IO uint32_t aedt : 1;
- __IO uint32_t reserved7 : 25;
-#endif
- } PHY_MCTRL_b;
- };
- /* Address 0x01C */
- union {
- __IO uint32_t PHY_CHAN;
-
- struct {
- __IO uint32_t chan : 5;
- __IO uint32_t unused_6_5 : 2;
- __IO uint32_t man_freq_en : 1;
- __IO uint32_t man_freq : 8;
- __IO uint32_t reserved16 : 16;
- } PHY_CHAN_b;
- };
- /* Address 0x020 */
- union {
- __IO uint32_t PHY_PWR;
-
- struct {
- __IO uint32_t pwr : 8;
- __IO uint32_t reserved8 : 24;
- } PHY_PWR_b;
- };
- /* Address 0x024 */
- union {
- __I uint32_t RX_PP;
-
- struct {
- __I uint32_t rx_cpp : 10;
- __I uint32_t rx_ppp : 10;
- __I uint32_t rx_ipp : 10;
- __I uint32_t reserved30 : 2;
- } RX_PP_b;
- };
- /* Address 0x028 */
- union {
- __IO uint32_t ANT_DIV_P;
-
- struct {
- __IO uint32_t sw_toogle : 1;
- __IO uint32_t reserved1 : 31;
- } ANT_DIV_P_b;
- };
- /* Address 0x02C */
- union {
- __IO uint32_t ANT_DIV;
-
- struct {
- __IO uint32_t ad_rssi_thr : 10;
- __IO uint32_t rx_ad_en : 1;
- __IO uint32_t tx_ad_en : 1;
- __IO uint32_t rx_ad_timer : 4;
- __IO uint32_t reserved16 : 16;
- } ANT_DIV_b;
- };
- /* Addresses 0x030 - 0xFDC */
- __O uint32_t RESERVED030[1004];
- /* Address 0xFE0 */
- union {
- __I uint32_t ZB_EVENTS_STATUS;
-
- struct {
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
- __I uint32_t status : 13;
- __I uint32_t reserved13 : 19;
-#else
- __I uint32_t status : 15;
- __I uint32_t reserved15 : 17;
-#endif
- } ZB_EVENTS_STATUS_b;
- };
- /* Address 0xFE4 */
- union {
- __IO uint32_t ZB_EVENTS_ENABLE;
-
- struct {
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
- __IO uint32_t enable : 13;
- __IO uint32_t reserved13 : 19;
-#else
- __IO uint32_t enable : 15;
- __IO uint32_t reserved15 : 17;
-#endif
- } ZB_EVENTS_ENABLE_b;
- };
- /* Address 0xFE8 */
- union {
- __IO uint32_t ZB_EVENTS_CLEAR;
-
- struct {
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
- __IO uint32_t clear : 13;
- __IO uint32_t reserved13 : 19;
-#else
- __IO uint32_t clear : 15;
- __IO uint32_t reserved15 : 17;
-#endif
- } ZB_EVENTS_CLEAR_b;
- };
- /* Address 0xFEC */
- union {
- __IO uint32_t ZB_EVENTS_SET;
-
- struct {
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
- __IO uint32_t set : 13;
- __IO uint32_t reserved13 : 19;
-#else
- __IO uint32_t set : 15;
- __IO uint32_t reserved15 : 17;
-#endif
- } ZB_EVENTS_SET_b;
- };
- /* Address 0xFF0 */
- __O uint32_t RESERVEDFF0[1];
- /* Address 0xFF4 */
- union {
- __IO uint32_t POWERDOWN;
-
- struct {
- __IO uint32_t soft_reset : 1;
- __IO uint32_t force_softreset : 1;
- __IO uint32_t enable_flags_with_core_bus : 1;
- __IO uint32_t reserved3 : 28;
- __IO uint32_t powerdown : 1;
- } POWERDOWN_b;
- };
- /* Address 0xFF8 */
- __O uint32_t RESERVEDFF8[1];
- /* Address 0xFFC */
- union {
- __I uint32_t MODULEID;
-
- struct {
- __I uint32_t aperture : 8;
- __I uint32_t minor_revision : 4;
- __I uint32_t major_revision : 4;
- __I uint32_t identifier : 16;
- } MODULEID_b;
- };
- } ZB_MODEM_IF_Type;
-
- #define ZB_MODEM_MCCA_CTRL_RX_CCA_MODE_Pos 0
- #define ZB_MODEM_MCCA_CTRL_RX_CCA_MODE_Msk 0x03UL
- #define ZB_MODEM_MCCA_CTRL_RX_CCA_THRESH_Pos 2
- #define ZB_MODEM_MCCA_CTRL_RX_CCA_THRESH_Msk 0x0ffcUL
- #define ZB_MODEM_MCCA_CTRL_RX_CCA_OR_Pos 12
- #define ZB_MODEM_MCCA_CTRL_RX_CCA_OR_Msk 0x01000UL
- #define ZB_MODEM_MTX_CTRL_TX_TEST_EN_Pos 0
- #define ZB_MODEM_MTX_CTRL_TX_TEST_EN_Msk 0x01UL
- #define ZB_MODEM_MTX_CTRL_TX_TEST_MODE_Pos 1
- #define ZB_MODEM_MTX_CTRL_TX_TEST_MODE_Msk 0x02UL
- #define ZB_MODEM_MTX_CTRL_TX_POL_Pos 2
- #define ZB_MODEM_MTX_CTRL_TX_POL_Msk 0x04UL
- #define ZB_MODEM_MTX_CTRL_TX_INFRAME_SYNC_Pos 3
- #define ZB_MODEM_MTX_CTRL_TX_INFRAME_SYNC_Msk 0x08UL
- #define ZB_MODEM_MTX_TST_SEQ_TX_TEST_SEQ_Pos 0
- #define ZB_MODEM_MTX_TST_SEQ_TX_TEST_SEQ_Msk 0x0ffffffffUL
- #define ZB_MODEM_MRX_CTRL_RX_COR_LO_Pos 0
- #define ZB_MODEM_MRX_CTRL_RX_COR_LO_Msk 0x03fUL
- #define ZB_MODEM_MRX_CTRL_RX_COR_HI_Pos 6
- #define ZB_MODEM_MRX_CTRL_RX_COR_HI_Msk 0x0fc0UL
- #define ZB_MODEM_MRX_CTRL_RX_SYNC_MODE_Pos 12
- #define ZB_MODEM_MRX_CTRL_RX_SYNC_MODE_Msk 0x03000UL
- #define ZB_MODEM_MRX_CTRL_RX_POL_Pos 14
- #define ZB_MODEM_MRX_CTRL_RX_POL_Msk 0x0c000UL
- #define ZB_MODEM_MRX_CTRL_RX_PRE_NUM_Pos 16
- #define ZB_MODEM_MRX_CTRL_RX_PRE_NUM_Msk 0x070000UL
- #define ZB_MODEM_MRX_CTRL_RX_EARLY_EOP_Pos 19
- #define ZB_MODEM_MRX_CTRL_RX_EARLY_EOP_Msk 0x0180000UL
- #define ZB_MODEM_MRX_CTRL_RX_AGC_RST_EN_Pos 21
- #define ZB_MODEM_MRX_CTRL_RX_AGC_RST_EN_Msk 0x0200000UL
- #define ZB_MODEM_MRX_CTRL_RX_AGC_RST_THR_Pos 22
- #define ZB_MODEM_MRX_CTRL_RX_AGC_RST_THR_Msk 0x01fc00000UL
- #define ZB_MODEM_MRX_CTRL_RX_RSSI_AVG_EN_Pos 29
- #define ZB_MODEM_MRX_CTRL_RX_RSSI_AVG_EN_Msk 0x020000000UL
- #define ZB_MODEM_MRX_CTRL_RX_RSSI_PULSE_MODE_Pos 30
- #define ZB_MODEM_MRX_CTRL_RX_RSSI_PULSE_MODE_Msk 0x040000000UL
- #define ZB_MODEM_MSTAT_RX_PRE_STATE_Pos 0
- #define ZB_MODEM_MSTAT_RX_PRE_STATE_Msk 0x03UL
- #define ZB_MODEM_MSTAT_RX_PRE_CNT_Pos 2
- #define ZB_MODEM_MSTAT_RX_PRE_CNT_Msk 0x01cUL
- #define ZB_MODEM_MSTAT_RX_AD_ANT_Pos 5
- #define ZB_MODEM_MSTAT_RX_AD_ANT_Msk 0x020UL
- #define ZB_MODEM_MSTAT_RX_RSSI_AVG_Pos 6
- #define ZB_MODEM_MSTAT_RX_RSSI_AVG_Msk 0x0ffc0UL
- #define ZB_MODEM_MSTAT_RX_SQI_Pos 16
- #define ZB_MODEM_MSTAT_RX_SQI_Msk 0x0ff0000UL
- #define ZB_MODEM_MSTAT_RX_CCAS_Pos 24
- #define ZB_MODEM_MSTAT_RX_CCAS_Msk 0x01000000UL
- #define ZB_MODEM_MSTAT_RX_AD_SWITCH_Pos 25
- #define ZB_MODEM_MSTAT_RX_AD_SWITCH_Msk 0x02000000UL
- #define ZB_MODEM_RXFE_CONFIG_SELFI_Pos 0
- #define ZB_MODEM_RXFE_CONFIG_SELFI_Msk 0x0fUL
- #define ZB_MODEM_RXFE_CONFIG_SPECINV_Pos 4
- #define ZB_MODEM_RXFE_CONFIG_SPECINV_Msk 0x010UL
- #define ZB_MODEM_RXFE_CONFIG_BYPASS_LPF_Pos 5
- #define ZB_MODEM_RXFE_CONFIG_BYPASS_LPF_Msk 0x020UL
- #define ZB_MODEM_RXFE_CONFIG_BYPASS_ADJ_Pos 6
- #define ZB_MODEM_RXFE_CONFIG_BYPASS_ADJ_Msk 0x040UL
- #define ZB_MODEM_RXFE_CONFIG_SELFE4DEMOD_Pos 7
- #define ZB_MODEM_RXFE_CONFIG_SELFE4DEMOD_Msk 0x080UL
- #define ZB_MODEM_RXFE_CONFIG_SELFE4AGC_Pos 8
- #define ZB_MODEM_RXFE_CONFIG_SELFE4AGC_Msk 0x0100UL
- #define ZB_MODEM_RXFE_CONFIG_LOOPBACK_Pos 9
- #define ZB_MODEM_RXFE_CONFIG_LOOPBACK_Msk 0x0200UL
- #define ZB_MODEM_RXFE_CONFIG_BITINV_Pos 10
- #define ZB_MODEM_RXFE_CONFIG_BITINV_Msk 0x0400UL
- #define ZB_MODEM_RXFE_CONFIG_XCORR_MODE_Pos 11
- #define ZB_MODEM_RXFE_CONFIG_XCORR_MODE_Msk 0x0800UL
- #define ZB_MODEM_PHY_MCTRL_MIOM_Pos 1
- #define ZB_MODEM_PHY_MCTRL_MIOM_Msk 0x02UL
- #define ZB_MODEM_PHY_MCTRL_MPHYON_Pos 2
- #define ZB_MODEM_PHY_MCTRL_MPHYON_Msk 0x04UL
- #define ZB_MODEM_PHY_MCTRL_MPHYDIR_Pos 3
- #define ZB_MODEM_PHY_MCTRL_MPHYDIR_Msk 0x08UL
- #define ZB_MODEM_PHY_MCTRL_MCCAT_Pos 4
- #define ZB_MODEM_PHY_MCTRL_MCCAT_Msk 0x010UL
- #define ZB_MODEM_PHY_MCTRL_MEDT_Pos 5
- #define ZB_MODEM_PHY_MCTRL_MEDT_Msk 0x020UL
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
-#else
- #define ZB_MODEM_PHY_MCTRL_AEDT_Pos 6
- #define ZB_MODEM_PHY_MCTRL_AEDT_Msk 0x040UL
-#endif
- #define ZB_MODEM_PHY_CHAN_CHAN_Pos 0
- #define ZB_MODEM_PHY_CHAN_CHAN_Msk 0x01fUL
- #define ZB_MODEM_PHY_CHAN_UNUSED_6_5_Pos 5
- #define ZB_MODEM_PHY_CHAN_UNUSED_6_5_Msk 0x060UL
- #define ZB_MODEM_PHY_CHAN_MAN_FREQ_EN_Pos 7
- #define ZB_MODEM_PHY_CHAN_MAN_FREQ_EN_Msk 0x080UL
- #define ZB_MODEM_PHY_CHAN_MAN_FREQ_Pos 8
- #define ZB_MODEM_PHY_CHAN_MAN_FREQ_Msk 0x0ff00UL
- #define ZB_MODEM_PHY_PWR_PWR_Pos 0
- #define ZB_MODEM_PHY_PWR_PWR_Msk 0x0ffUL
- #define ZB_MODEM_RX_PP_RX_CPP_Pos 0
- #define ZB_MODEM_RX_PP_RX_CPP_Msk 0x03ffUL
- #define ZB_MODEM_RX_PP_RX_PPP_Pos 10
- #define ZB_MODEM_RX_PP_RX_PPP_Msk 0x0ffc00UL
- #define ZB_MODEM_RX_PP_RX_IPP_Pos 20
- #define ZB_MODEM_RX_PP_RX_IPP_Msk 0x03ff00000UL
- #define ZB_MODEM_ANT_DIV_P_SW_TOOGLE_Pos 0
- #define ZB_MODEM_ANT_DIV_P_SW_TOOGLE_Msk 0x01UL
- #define ZB_MODEM_ANT_DIV_AD_RSSI_THR_Pos 0
- #define ZB_MODEM_ANT_DIV_AD_RSSI_THR_Msk 0x03ffUL
- #define ZB_MODEM_ANT_DIV_RX_AD_EN_Pos 10
- #define ZB_MODEM_ANT_DIV_RX_AD_EN_Msk 0x0400UL
- #define ZB_MODEM_ANT_DIV_TX_AD_EN_Pos 11
- #define ZB_MODEM_ANT_DIV_TX_AD_EN_Msk 0x0800UL
- #define ZB_MODEM_ANT_DIV_RX_AD_TIMER_Pos 12
- #define ZB_MODEM_ANT_DIV_RX_AD_TIMER_Msk 0x0f000UL
- #define ZB_MODEM_ZB_EVENTS_STATUS_STATUS_Pos 0
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
- #define ZB_MODEM_ZB_EVENTS_STATUS_STATUS_Msk 0x01fffUL
-#else
- #define ZB_MODEM_ZB_EVENTS_STATUS_STATUS_Msk 0x07fffUL
-#endif
- #define ZB_MODEM_ZB_EVENTS_ENABLE_ENABLE_Pos 0
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
- #define ZB_MODEM_ZB_EVENTS_ENABLE_ENABLE_Msk 0x01fffUL
-#else
- #define ZB_MODEM_ZB_EVENTS_ENABLE_ENABLE_Msk 0x07fffUL
-#endif
- #define ZB_MODEM_ZB_EVENTS_CLEAR_CLEAR_Pos 0
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
- #define ZB_MODEM_ZB_EVENTS_CLEAR_CLEAR_Msk 0x01fffUL
-#else
- #define ZB_MODEM_ZB_EVENTS_CLEAR_CLEAR_Msk 0x07fffUL
-#endif
- #define ZB_MODEM_ZB_EVENTS_SET_SET_Pos 0
-#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
- #define ZB_MODEM_ZB_EVENTS_SET_SET_Msk 0x01fffUL
-#else
- #define ZB_MODEM_ZB_EVENTS_SET_SET_Msk 0x07fffUL
-#endif
- #define ZB_MODEM_POWERDOWN_SOFT_RESET_Pos 0
- #define ZB_MODEM_POWERDOWN_SOFT_RESET_Msk 0x01UL
- #define ZB_MODEM_POWERDOWN_FORCE_SOFTRESET_Pos 1
- #define ZB_MODEM_POWERDOWN_FORCE_SOFTRESET_Msk 0x02UL
- #define ZB_MODEM_POWERDOWN_ENABLE_FLAGS_WITH_CORE_BUS_Pos 2
- #define ZB_MODEM_POWERDOWN_ENABLE_FLAGS_WITH_CORE_BUS_Msk 0x04UL
- #define ZB_MODEM_POWERDOWN_POWERDOWN_Pos 31
- #define ZB_MODEM_POWERDOWN_POWERDOWN_Msk 0x080000000UL
- #define ZB_MODEM_MODULEID_APERTURE_Pos 0
- #define ZB_MODEM_MODULEID_APERTURE_Msk 0x0ffUL
- #define ZB_MODEM_MODULEID_MINOR_REVISION_Pos 8
- #define ZB_MODEM_MODULEID_MINOR_REVISION_Msk 0x0f00UL
- #define ZB_MODEM_MODULEID_MAJOR_REVISION_Pos 12
- #define ZB_MODEM_MODULEID_MAJOR_REVISION_Msk 0x0f000UL
- #define ZB_MODEM_MODULEID_IDENTIFIER_Pos 16
- #define ZB_MODEM_MODULEID_IDENTIFIER_Msk 0x0ffff0000UL
-
-#endif // __ZB_MODEM_IF_H__
diff --git a/third_party/nxp/JN5189/Radio_JN5189/Include/radio_jn518x.h b/third_party/nxp/JN5189/Radio_JN5189/Include/radio_jn518x.h
deleted file mode 100755
index e6d4c3b..0000000
--- a/third_party/nxp/JN5189/Radio_JN5189/Include/radio_jn518x.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
-* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
-* Copyright 2016-2019 NXP
- * All rights reserved.
- *
-* SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __RADIO_JN518X_H_
-#define __RADIO_JN518X_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "radio.h"
-
-/****************************************************************************/
-/*** Macro/Type Definitions ***/
-/****************************************************************************/
-
-#define RADIO_JN518X_VERSION RADIO_VERSION
-#define RADIO_JN5189_MAX_RSSI_REPORT RADIO_MAX_RSSI_REPORT
-#define RADIO_JN5189_MIN_RSSI_REPORT RADIO_MIN_RSSI_REPORT
-
-#define vRadio_Jn518x_RadioInit vRadio_RadioInit
-#define vRadio_Jn518x_RadioDeInit vRadio_RadioDeInit
-#define vRadio_Jn518x_Standard_Init vRadio_Standard_Init
-#define u8Radio_Jn518x_GetEDfromRSSI u8Radio_GetEDfromRSSI
-#define u32Radio_Jn518x_RadioModesAvailable u32Radio_RadioModesAvailable
-#define u32Radio_Jn518x_RadioGetVersion u32Radio_RadioGetVersion
-#define vRadio_JN518x_Temp_Update vRadio_Temp_Update
-#define vRadio_JN518x_ConfigCalFlashUsage vRadio_ConfigCalFlashUsage
-#define vRadio_jn518x_Save_ApplicationData_Retention vRadio_Save_ApplicationData_Retention
-#define vRadio_jn518x_Restore_Retention_ApplicationData vRadio_Restore_Retention_ApplicationData
-#define vRadio_JN518xRecal vRadio_Recal
-#define vRadio_Jn518x_RFT1778_bad_crc vRadio_RFT1778_bad_crc
-#define vRadio_Jn518x_LockupCheckAndAbortRadio vRadio_LockupCheckAndAbortRadio
-#define i16Radio_Jn518x_GetRSSI i16Radio_GetRSSI
-#define i16Radio_Jn518x_GetNbRSSISync i16Radio_GetNbRSSISync
-#define i16Radio_Jn518x_GetNbRSSISyncCor i16Radio_GetNbRSSISyncCor
-#define i8Radio_Jn518x_GetLastPacketRSSI i8Radio_GetLastPacketRSSI
-#define i16Radio_Jn518x_BoundRssiValue i16Radio_BoundRssiValue
-#define vRadio_Jn518x_BLE_ResetOn vRadio_BLE_ResetOn
-#define vRadio_Jn518x_BLE_ResetOff vRadio_BLE_ResetOff
-#define vRadio_Jn518x_remove_patch_ISR vRadio_remove_patch_ISR
-#define vRadio_Jn518x_SingleRX_AgcReadyPatch vRadio_SingleRX_AgcReadyPatch
-#define vRadio_Jn518x_MultiRX_AgcReadyPatch vRadio_MultiRX_AgcReadyPatch
-#define vRadio_Jn518x_Enable_AgcReadyPatch vRadio_Enable_AgcReadyPatch;
-#define vRadio_Jn518x_Disable_AgcReadyPatch vRadio_Disable_AgcReadyPatch
-#define vRadio_Jn518x_SkipXTALInit vRadio_SkipXTALInit
-#define vRadio_Jn518x_EnableXTALInit vRadio_EnableXTALInit
-#define vRadio_jn518x_ActivateXtal32MRadioBiasing vRadio_ActivateXtal32MRadioBiasing
-#define vRadio_jn518x_DisableZBRadio vRadio_DisableZBRadio
-#define vRadio_jn518x_DisableBLERadio vRadio_DisableBLERadio
-#define vRadio_jn518x_EnableBLEFastTX vRadio_EnableBLEFastTX
-#define vRadio_jn518x_DisableBLEFastTX vRadio_DisableBLEFastTX
-#define vRadio_jn518x_ZBtoBLE vRadio_ZBtoBLE
-#define vRadio_jn518x_BLEtoZB vRadio_BLEtoZB
-#define u32Radio_JN518x_Get_Next_Recal_Duration u32Radio_Get_Next_Recal_Duration
-#define vRadio_Jn518x_AntennaDiversityTxRxEnable vRadio_AntennaDiversityTxRxEnable
-#define vRadio_Jn518x_AntennaDiversityConfigure vRadio_AntennaDiversityConfigure
-#define vRadio_Jn518x_AntennaDiversitySwitch vRadio_AntennaDiversitySwitch
-#define u8Radio_Jn518x_AntennaDiversityStatus u8Radio_AntennaDiversityStatus
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __RADIO_JN518X_H_ */
diff --git a/third_party/nxp/JN5189/Radio_JN5189/Include/system_jn518x.h b/third_party/nxp/JN5189/Radio_JN5189/Include/system_jn518x.h
deleted file mode 100755
index 5d68696..0000000
--- a/third_party/nxp/JN5189/Radio_JN5189/Include/system_jn518x.h
+++ /dev/null
@@ -1,55 +0,0 @@
-#ifndef SYSTEM_JN518X_H
-#define SYSTEM_JN518X_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-
-
-/**
- * Initialize the system
- *
- * @param none
- * @return none
- *
- * @brief Setup the microcontroller system.
- * Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param none
- * @return none
- *
- * @brief Updates the SystemCoreClock with current core Clock
- * retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-
-
-/* *** JN518x *** */
-
-/** \brief Exceptions and Interrupts vectors structure.
- */
-
-typedef struct
-{
- uint32_t pExceptions[16]; /*!< System exceptions vectors */
- uint32_t pIsr[240]; /*!< User interrupt vectors */
-} VectorTable_Type;
-
-
-extern const uint32_t XSW_VTOR_BASE ;
-
-#define JN518X_ISR_TABLE ((VectorTable_Type *) XSW_VTOR_BASE)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SYSTEM_JN518X_H */
diff --git a/third_party/nxp/JN5189/drivers/fsl_debug_console.c b/third_party/nxp/JN5189/drivers/fsl_debug_console.c
deleted file mode 100755
index 0339843..0000000
--- a/third_party/nxp/JN5189/drivers/fsl_debug_console.c
+++ /dev/null
@@ -1,1907 +0,0 @@
-/*
-* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
-* Copyright 2016-2019 NXP
-* All rights reserved.
-*
-* SPDX-License-Identifier: BSD-3-Clause
-*/
-
-#include <stdarg.h>
-#include <stdlib.h>
-#if defined(__CC_ARM)
-#include <stdio.h>
-#endif
-#include <math.h>
-#include "fsl_debug_console.h"
-
-#if (defined(FSL_FEATURE_SOC_UART_COUNT) && (FSL_FEATURE_SOC_UART_COUNT > 0)) || \
- (defined(FSL_FEATURE_SOC_IUART_COUNT) && (FSL_FEATURE_SOC_IUART_COUNT > 0))
-#include "fsl_uart.h"
-#endif /* FSL_FEATURE_SOC_UART_COUNT || FSL_FEATURE_SOC_IUART_COUNT */
-
-#if defined(FSL_FEATURE_SOC_LPSCI_COUNT) && (FSL_FEATURE_SOC_LPSCI_COUNT > 0)
-#include "fsl_lpsci.h"
-#endif /* FSL_FEATURE_SOC_LPSCI_COUNT */
-
-#if defined(FSL_FEATURE_SOC_LPUART_COUNT) && (FSL_FEATURE_SOC_LPUART_COUNT > 0)
-#include "fsl_lpuart.h"
-#endif /* FSL_FEATURE_SOC_LPUART_COUNT */
-
-#if defined(FSL_FEATURE_SOC_USB_COUNT) && (FSL_FEATURE_SOC_USB_COUNT > 0) && defined(BOARD_USE_VIRTUALCOM)
-#include "usb_device_config.h"
-#include "usb.h"
-#include "usb_device_cdc_acm.h"
-#include "usb_device_ch9.h"
-#include "virtual_com.h"
-#endif
-
-#if defined(FSL_FEATURE_SOC_FLEXCOMM_COUNT) && (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 0)
-#include "fsl_usart.h"
-#endif /* FSL_FEATURE_SOC_FLEXCOMM_COUNT */
-
-/*! @brief Keil: suppress ellipsis warning in va_arg usage below. */
-#if defined(__CC_ARM)
-#pragma diag_suppress 1256
-#endif /* __CC_ARM */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @brief This definition is maximum line that debugconsole can scanf each time.*/
-#define IO_MAXLINE 20U
-
-/*! @brief The overflow value.*/
-#ifndef HUGE_VAL
-#define HUGE_VAL (99.e99)
-#endif /* HUGE_VAL */
-
-#if SCANF_FLOAT_ENABLE
-static double fnum = 0.0;
-#endif /* SCANF_FLOAT_ENABLE */
-
-/*! @brief Operation functions definitions for debug console. */
-typedef struct DebugConsoleOperationFunctions
-{
- union
- {
- void (*PutChar)(void *base, const uint8_t *buffer, size_t length);
-#if (defined(FSL_FEATURE_SOC_UART_COUNT) && (FSL_FEATURE_SOC_UART_COUNT > 0)) || \
- (defined(FSL_FEATURE_SOC_IUART_COUNT) && (FSL_FEATURE_SOC_IUART_COUNT > 0))
- void (*UART_PutChar)(UART_Type *base, const uint8_t *buffer, size_t length);
-#endif /* FSL_FEATURE_SOC_UART_COUNT || FSL_FEATURE_SOC_IUART_COUNT */
-#if defined(FSL_FEATURE_SOC_LPSCI_COUNT) && (FSL_FEATURE_SOC_LPSCI_COUNT > 0)
- void (*LPSCI_PutChar)(UART0_Type *base, const uint8_t *buffer, size_t length);
-#endif /* FSL_FEATURE_SOC_LPSCI_COUNT */
-#if defined(FSL_FEATURE_SOC_LPUART_COUNT) && (FSL_FEATURE_SOC_LPUART_COUNT > 0)
- void (*LPUART_PutChar)(LPUART_Type *base, const uint8_t *buffer, size_t length);
-#endif /* FSL_FEATURE_SOC_LPUART_COUNT */
-#if defined(FSL_FEATURE_SOC_USB_COUNT) && (FSL_FEATURE_SOC_USB_COUNT > 0) && defined(BOARD_USE_VIRTUALCOM)
- void (*USB_PutChar)(usb_device_handle base, const uint8_t *buf, size_t count);
-#endif /* FSL_FEATURE_SOC_USB_COUNT && BOARD_USE_VIRTUALCOM*/
-#if defined(FSL_FEATURE_SOC_FLEXCOMM_COUNT) && (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 0)
- void (*USART_PutChar)(USART_Type *base, const uint8_t *data, size_t length);
-#endif /* FSL_FEATURE_SOC_FLEXCOMM_COUNT */
- } tx_union;
- union
- {
- status_t (*GetChar)(void *base, const uint8_t *buffer, size_t length);
-#if (defined(FSL_FEATURE_SOC_UART_COUNT) && (FSL_FEATURE_SOC_UART_COUNT > 0)) || \
- (defined(FSL_FEATURE_SOC_IUART_COUNT) && (FSL_FEATURE_SOC_IUART_COUNT > 0))
- status_t (*UART_GetChar)(UART_Type *base, uint8_t *buffer, size_t length);
-#endif /* FSL_FEATURE_SOC_UART_COUNT || FSL_FEATURE_SOC_IUART_COUNT*/
-#if defined(FSL_FEATURE_SOC_LPSCI_COUNT) && (FSL_FEATURE_SOC_LPSCI_COUNT > 0)
- status_t (*LPSCI_GetChar)(UART0_Type *base, uint8_t *buffer, size_t length);
-#endif /* FSL_FEATURE_SOC_LPSCI_COUNT */
-#if defined(FSL_FEATURE_SOC_LPUART_COUNT) && (FSL_FEATURE_SOC_LPUART_COUNT > 0)
- status_t (*LPUART_GetChar)(LPUART_Type *base, uint8_t *buffer, size_t length);
-#endif /* FSL_FEATURE_SOC_LPUART_COUNT */
-#if defined(FSL_FEATURE_SOC_USB_COUNT) && (FSL_FEATURE_SOC_USB_COUNT > 0) && defined(BOARD_USE_VIRTUALCOM)
- status_t (*USB_GetChar)(usb_device_handle base, uint8_t *buf, size_t count);
-#endif /* FSL_FEATURE_SOC_USB_COUNT && BOARD_USE_VIRTUALCOM*/
-#if defined(FSL_FEATURE_SOC_FLEXCOMM_COUNT) && (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 0)
- status_t (*USART_GetChar)(USART_Type *base, uint8_t *data, size_t length);
-#endif
- } rx_union;
-} debug_console_ops_t;
-
-/*! @brief State structure storing debug console. */
-typedef struct DebugConsoleState
-{
- uint8_t type; /*!< Indicator telling whether the debug console is initialized. */
- void *base; /*!< Base of the IP register. */
- debug_console_ops_t ops; /*!< Operation function pointers for debug UART operations. */
-} debug_console_state_t;
-
-/*! @brief Type of KSDK printf function pointer. */
-typedef int (*PUTCHAR_FUNC)(int a);
-
-#if PRINTF_ADVANCED_ENABLE
-/*! @brief Specification modifier flags for printf. */
-enum _debugconsole_printf_flag
-{
- kPRINTF_Minus = 0x01U, /*!< Minus FLag. */
- kPRINTF_Plus = 0x02U, /*!< Plus Flag. */
- kPRINTF_Space = 0x04U, /*!< Space Flag. */
- kPRINTF_Zero = 0x08U, /*!< Zero Flag. */
- kPRINTF_Pound = 0x10U, /*!< Pound Flag. */
- kPRINTF_LengthChar = 0x20U, /*!< Length: Char Flag. */
- kPRINTF_LengthShortInt = 0x40U, /*!< Length: Short Int Flag. */
- kPRINTF_LengthLongInt = 0x80U, /*!< Length: Long Int Flag. */
- kPRINTF_LengthLongLongInt = 0x100U, /*!< Length: Long Long Int Flag. */
-};
-#endif /* PRINTF_ADVANCED_ENABLE */
-
-/*! @brief Specification modifier flags for scanf. */
-enum _debugconsole_scanf_flag
-{
- kSCANF_Suppress = 0x2U, /*!< Suppress Flag. */
- kSCANF_DestMask = 0x7cU, /*!< Destination Mask. */
- kSCANF_DestChar = 0x4U, /*!< Destination Char Flag. */
- kSCANF_DestString = 0x8U, /*!< Destination String FLag. */
- kSCANF_DestSet = 0x10U, /*!< Destination Set Flag. */
- kSCANF_DestInt = 0x20U, /*!< Destination Int Flag. */
- kSCANF_DestFloat = 0x30U, /*!< Destination Float Flag. */
- kSCANF_LengthMask = 0x1f00U, /*!< Length Mask Flag. */
-#if SCANF_ADVANCED_ENABLE
- kSCANF_LengthChar = 0x100U, /*!< Length Char Flag. */
- kSCANF_LengthShortInt = 0x200U, /*!< Length ShortInt Flag. */
- kSCANF_LengthLongInt = 0x400U, /*!< Length LongInt Flag. */
- kSCANF_LengthLongLongInt = 0x800U, /*!< Length LongLongInt Flag. */
-#endif /* SCANF_ADVANCED_ENABLE */
-#if PRINTF_FLOAT_ENABLE
- kSCANF_LengthLongLongDouble = 0x1000U, /*!< Length LongLongDuoble Flag. */
-#endif /*PRINTF_FLOAT_ENABLE */
- kSCANF_TypeSinged = 0x2000U, /*!< TypeSinged Flag. */
-};
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/*! @brief Debug UART state information. */
-static debug_console_state_t s_debugConsole = {.type = DEBUG_CONSOLE_DEVICE_TYPE_NONE, .base = NULL, .ops = {{0}, {0}}};
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-#if SDK_DEBUGCONSOLE
-static int DbgConsole_PrintfFormattedData(PUTCHAR_FUNC func_ptr, const char *fmt, va_list ap);
-static int DbgConsole_ScanfFormattedData(const char *line_ptr, char *format, va_list args_ptr);
-double modf(double input_dbl, double *intpart_ptr);
-#endif /* SDK_DEBUGCONSOLE */
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-/*************Code for DbgConsole Init, Deinit, Printf, Scanf *******************************/
-
-/* See fsl_debug_console.h for documentation of this function. */
-status_t DbgConsole_Init(uint32_t baseAddr, uint32_t baudRate, uint8_t device, uint32_t clkSrcFreq)
-{
- if (s_debugConsole.type != DEBUG_CONSOLE_DEVICE_TYPE_NONE)
- {
- return kStatus_Fail;
- }
-
- /* Set debug console to initialized to avoid duplicated initialized operation. */
- s_debugConsole.type = device;
-
- /* Switch between different device. */
- switch (device)
- {
-#if (defined(FSL_FEATURE_SOC_UART_COUNT) && (FSL_FEATURE_SOC_UART_COUNT > 0)) || \
- (defined(FSL_FEATURE_SOC_IUART_COUNT) && (FSL_FEATURE_SOC_IUART_COUNT > 0))
- case DEBUG_CONSOLE_DEVICE_TYPE_UART:
- case DEBUG_CONSOLE_DEVICE_TYPE_IUART:
- {
- uart_config_t uart_config;
- s_debugConsole.base = (UART_Type *)baseAddr;
- UART_GetDefaultConfig(&uart_config);
- uart_config.baudRate_Bps = baudRate;
- /* Enable clock and initial UART module follow user configure structure. */
- UART_Init(s_debugConsole.base, &uart_config, clkSrcFreq);
- UART_EnableTx(s_debugConsole.base, true);
- UART_EnableRx(s_debugConsole.base, true);
- /* Set the function pointer for send and receive for this kind of device. */
- s_debugConsole.ops.tx_union.UART_PutChar = UART_WriteBlocking;
- s_debugConsole.ops.rx_union.UART_GetChar = UART_ReadBlocking;
- }
- break;
-#endif /* FSL_FEATURE_SOC_UART_COUNT */
-#if defined(FSL_FEATURE_SOC_LPSCI_COUNT) && (FSL_FEATURE_SOC_LPSCI_COUNT > 0)
- case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI:
- {
- lpsci_config_t lpsci_config;
- s_debugConsole.base = (UART0_Type *)baseAddr;
- LPSCI_GetDefaultConfig(&lpsci_config);
- lpsci_config.baudRate_Bps = baudRate;
- /* Enable clock and initial UART module follow user configure structure. */
- LPSCI_Init(s_debugConsole.base, &lpsci_config, clkSrcFreq);
- LPSCI_EnableTx(s_debugConsole.base, true);
- LPSCI_EnableRx(s_debugConsole.base, true);
- /* Set the function pointer for send and receive for this kind of device. */
- s_debugConsole.ops.tx_union.LPSCI_PutChar = LPSCI_WriteBlocking;
- s_debugConsole.ops.rx_union.LPSCI_GetChar = LPSCI_ReadBlocking;
- }
- break;
-#endif /* FSL_FEATURE_SOC_LPSCI_COUNT */
-#if defined(FSL_FEATURE_SOC_LPUART_COUNT) && (FSL_FEATURE_SOC_LPUART_COUNT > 0)
- case DEBUG_CONSOLE_DEVICE_TYPE_LPUART:
- {
- lpuart_config_t lpuart_config;
- s_debugConsole.base = (LPUART_Type *)baseAddr;
- LPUART_GetDefaultConfig(&lpuart_config);
- lpuart_config.baudRate_Bps = baudRate;
- /* Enable clock and initial UART module follow user configure structure. */
- LPUART_Init(s_debugConsole.base, &lpuart_config, clkSrcFreq);
- LPUART_EnableTx(s_debugConsole.base, true);
- LPUART_EnableRx(s_debugConsole.base, true);
- /* Set the function pointer for send and receive for this kind of device. */
- s_debugConsole.ops.tx_union.LPUART_PutChar = LPUART_WriteBlocking;
- s_debugConsole.ops.rx_union.LPUART_GetChar = LPUART_ReadBlocking;
- }
- break;
-#endif /* FSL_FEATURE_SOC_LPUART_COUNT */
-#if defined(FSL_FEATURE_SOC_USB_COUNT) && (FSL_FEATURE_SOC_USB_COUNT > 0) && defined(BOARD_USE_VIRTUALCOM)
- case DEBUG_CONSOLE_DEVICE_TYPE_USBCDC:
- {
- s_debugConsole.base = USB_VcomInit();
- s_debugConsole.ops.tx_union.USB_PutChar = USB_VcomWriteBlocking;
- s_debugConsole.ops.rx_union.USB_GetChar = USB_VcomReadBlocking;
- }
- break;
-#endif /* FSL_FEATURE_SOC_USB_COUNT && BOARD_USE_VIRTUALCOM*/
-#if defined(FSL_FEATURE_SOC_FLEXCOMM_COUNT) && (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 0)
- case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM:
- {
- usart_config_t usart_config;
- s_debugConsole.base = (USART_Type *)baseAddr;
- USART_GetDefaultConfig(&usart_config);
- usart_config.baudRate_Bps = baudRate;
- /* Enable clock and initial UART module follow user configure structure. */
- USART_Init(s_debugConsole.base, &usart_config, clkSrcFreq);
- /* Set the function pointer for send and receive for this kind of device. */
- s_debugConsole.ops.tx_union.USART_PutChar = USART_WriteBlocking;
- s_debugConsole.ops.rx_union.USART_GetChar = USART_ReadBlocking;
- }
- break;
-#endif /* FSL_FEATURE_SOC_FLEXCOMM_COUNT*/
- /* If new device is required as the low level device for debug console,
- * Add the case branch and add the preprocessor macro to judge whether
- * this kind of device exist in this SOC. */
- default:
- /* Device identified is invalid, return invalid device error code. */
- return kStatus_InvalidArgument;
- }
-
- return kStatus_Success;
-}
-
-/* See fsl_debug_console.h for documentation of this function. */
-status_t DbgConsole_Deinit(void)
-{
- if (s_debugConsole.type == DEBUG_CONSOLE_DEVICE_TYPE_NONE)
- {
- return kStatus_Success;
- }
-
- switch (s_debugConsole.type)
- {
-#if (defined(FSL_FEATURE_SOC_UART_COUNT) && (FSL_FEATURE_SOC_UART_COUNT > 0)) || \
- (defined(FSL_FEATURE_SOC_IUART_COUNT) && (FSL_FEATURE_SOC_IUART_COUNT > 0))
- case DEBUG_CONSOLE_DEVICE_TYPE_UART:
- case DEBUG_CONSOLE_DEVICE_TYPE_IUART:
- /* Disable UART module. */
- UART_Deinit(s_debugConsole.base);
- break;
-#endif /* FSL_FEATURE_SOC_UART_COUNT */
-#if defined(FSL_FEATURE_SOC_LPSCI_COUNT) && (FSL_FEATURE_SOC_LPSCI_COUNT > 0)
- case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI:
- /* Disable LPSCI module. */
- LPSCI_Deinit(s_debugConsole.base);
- break;
-#endif /* FSL_FEATURE_SOC_LPSCI_COUNT */
-#if defined(FSL_FEATURE_SOC_LPUART_COUNT) && (FSL_FEATURE_SOC_LPUART_COUNT > 0)
- case DEBUG_CONSOLE_DEVICE_TYPE_LPUART:
- /* Disable LPUART module. */
- LPUART_Deinit(s_debugConsole.base);
- break;
-#endif /* FSL_FEATURE_SOC_LPUART_COUNT */
-#if defined(FSL_FEATURE_SOC_USB_COUNT) && (FSL_FEATURE_SOC_USB_COUNT > 0) && defined(BOARD_USE_VIRTUALCOM)
- case DEBUG_CONSOLE_DEVICE_TYPE_USBCDC:
- /* Disable USBCDC module. */
- USB_VcomDeinit(s_debugConsole.base);
- break;
-#endif /* FSL_FEATURE_SOC_USB_COUNT && BOARD_USE_VIRTUALCOM*/
-#if defined(FSL_FEATURE_SOC_FLEXCOMM_COUNT) && (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 0)
- case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM:
- {
- USART_Deinit((USART_Type *)s_debugConsole.base);
- }
- break;
-#endif /* FSL_FEATURE_SOC_FLEXCOMM_COUNT*/
- default:
- s_debugConsole.type = DEBUG_CONSOLE_DEVICE_TYPE_NONE;
- break;
- }
-
- /* Device identified is invalid, return invalid device error code. */
- if (s_debugConsole.type == DEBUG_CONSOLE_DEVICE_TYPE_NONE)
- {
- return kStatus_InvalidArgument;
- }
-
- s_debugConsole.type = DEBUG_CONSOLE_DEVICE_TYPE_NONE;
- return kStatus_Success;
-}
-
-#if SDK_DEBUGCONSOLE
-/* See fsl_debug_console.h for documentation of this function. */
-int DbgConsole_Printf(const char *fmt_s, ...)
-{
- va_list ap;
- int result;
-
- /* Do nothing if the debug UART is not initialized. */
- if (s_debugConsole.type == DEBUG_CONSOLE_DEVICE_TYPE_NONE)
- {
- return -1;
- }
- va_start(ap, fmt_s);
- result = DbgConsole_PrintfFormattedData(DbgConsole_Putchar, fmt_s, ap);
- va_end(ap);
-
- return result;
-}
-
-/* See fsl_debug_console.h for documentation of this function. */
-int DbgConsole_Putchar(int ch)
-{
- /* Do nothing if the debug UART is not initialized. */
- if (s_debugConsole.type == DEBUG_CONSOLE_DEVICE_TYPE_NONE)
- {
- return -1;
- }
- s_debugConsole.ops.tx_union.PutChar(s_debugConsole.base, (uint8_t *)(&ch), 1);
-
- return 1;
-}
-
-/* See fsl_debug_console.h for documentation of this function. */
-int DbgConsole_Scanf(char *fmt_ptr, ...)
-{
- /* Plus one to store end of string char */
- char temp_buf[IO_MAXLINE + 1];
- va_list ap;
- int32_t i;
- char result;
-
- /* Do nothing if the debug UART is not initialized. */
- if (s_debugConsole.type == DEBUG_CONSOLE_DEVICE_TYPE_NONE)
- {
- return -1;
- }
- va_start(ap, fmt_ptr);
- temp_buf[0] = '\0';
-
- for (i = 0; i < IO_MAXLINE; i++)
- {
- temp_buf[i] = result = DbgConsole_Getchar();
-
- if ((result == '\r') || (result == '\n'))
- {
- /* End of Line. */
- if (i == 0)
- {
- temp_buf[i] = '\0';
- i = -1;
- }
- else
- {
- break;
- }
- }
- }
-
- if ((i == IO_MAXLINE))
- {
- temp_buf[i] = '\0';
- }
- else
- {
- temp_buf[i + 1] = '\0';
- }
- result = DbgConsole_ScanfFormattedData(temp_buf, fmt_ptr, ap);
- va_end(ap);
-
- return result;
-}
-
-/* See fsl_debug_console.h for documentation of this function. */
-int DbgConsole_Getchar(void)
-{
- char ch;
- /* Do nothing if the debug UART is not initialized. */
- if (s_debugConsole.type == DEBUG_CONSOLE_DEVICE_TYPE_NONE)
- {
- return -1;
- }
- while (kStatus_Success != s_debugConsole.ops.rx_union.GetChar(s_debugConsole.base, (uint8_t *)(&ch), 1))
- {
- return -1;
- }
-
- return ch;
-}
-
-/*************Code for process formatted data*******************************/
-/*!
- * @brief Scanline function which ignores white spaces.
- *
- * @param[in] s The address of the string pointer to update.
- * @return String without white spaces.
- */
-static uint32_t DbgConsole_ScanIgnoreWhiteSpace(const char **s)
-{
- uint8_t count = 0;
- uint8_t c;
-
- c = **s;
- while ((c == ' ') || (c == '\t') || (c == '\n') || (c == '\r') || (c == '\v') || (c == '\f'))
- {
- count++;
- (*s)++;
- c = **s;
- }
- return count;
-}
-
-/*!
- * @brief This function puts padding character.
- *
- * @param[in] c Padding character.
- * @param[in] curlen Length of current formatted string .
- * @param[in] width Width of expected formatted string.
- * @param[in] count Number of characters.
- * @param[in] func_ptr Function to put character out.
- */
-static void DbgConsole_PrintfPaddingCharacter(
- char c, int32_t curlen, int32_t width, int32_t *count, PUTCHAR_FUNC func_ptr)
-{
- int32_t i;
-
- for (i = curlen; i < width; i++)
- {
- func_ptr(c);
- (*count)++;
- }
-}
-
-/*!
- * @brief Converts a radix number to a string and return its length.
- *
- * @param[in] numstr Converted string of the number.
- * @param[in] nump Pointer to the number.
- * @param[in] neg Polarity of the number.
- * @param[in] radix The radix to be converted to.
- * @param[in] use_caps Used to identify %x/X output format.
-
- * @return Length of the converted string.
- */
-static int32_t DbgConsole_ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps)
-{
-#if PRINTF_ADVANCED_ENABLE
- int64_t a;
- int64_t b;
- int64_t c;
-
- uint64_t ua;
- uint64_t ub;
- uint64_t uc;
-#else
- int32_t a;
- int32_t b;
- int32_t c;
-
- uint32_t ua;
- uint32_t ub;
- uint32_t uc;
-#endif /* PRINTF_ADVANCED_ENABLE */
-
- int32_t nlen;
- char *nstrp;
-
- nlen = 0;
- nstrp = numstr;
- *nstrp++ = '\0';
-
- if (neg)
- {
-#if PRINTF_ADVANCED_ENABLE
- a = *(int64_t *)nump;
-#else
- a = *(int32_t *)nump;
-#endif /* PRINTF_ADVANCED_ENABLE */
- if (a == 0)
- {
- *nstrp = '0';
- ++nlen;
- return nlen;
- }
- while (a != 0)
- {
-#if PRINTF_ADVANCED_ENABLE
- b = (int64_t)a / (int64_t)radix;
- c = (int64_t)a - ((int64_t)b * (int64_t)radix);
- if (c < 0)
- {
- uc = (uint64_t)c;
- c = (int64_t)(~uc) + 1 + '0';
- }
-#else
- b = a / radix;
- c = a - (b * radix);
- if (c < 0)
- {
- uc = (uint32_t)c;
- c = (uint32_t)(~uc) + 1 + '0';
- }
-#endif /* PRINTF_ADVANCED_ENABLE */
- else
- {
- c = c + '0';
- }
- a = b;
- *nstrp++ = (char)c;
- ++nlen;
- }
- }
- else
- {
-#if PRINTF_ADVANCED_ENABLE
- ua = *(uint64_t *)nump;
-#else
- ua = *(uint32_t *)nump;
-#endif /* PRINTF_ADVANCED_ENABLE */
- if (ua == 0)
- {
- *nstrp = '0';
- ++nlen;
- return nlen;
- }
- while (ua != 0)
- {
-#if PRINTF_ADVANCED_ENABLE
- ub = (uint64_t)ua / (uint64_t)radix;
- uc = (uint64_t)ua - ((uint64_t)ub * (uint64_t)radix);
-#else
- ub = ua / (uint32_t)radix;
- uc = ua - (ub * (uint32_t)radix);
-#endif /* PRINTF_ADVANCED_ENABLE */
-
- if (uc < 10)
- {
- uc = uc + '0';
- }
- else
- {
- uc = uc - 10 + (use_caps ? 'A' : 'a');
- }
- ua = ub;
- *nstrp++ = (char)uc;
- ++nlen;
- }
- }
- return nlen;
-}
-
-#if PRINTF_FLOAT_ENABLE
-/*!
- * @brief Converts a floating radix number to a string and return its length.
- *
- * @param[in] numstr Converted string of the number.
- * @param[in] nump Pointer to the number.
- * @param[in] radix The radix to be converted to.
- * @param[in] precision_width Specify the precision width.
-
- * @return Length of the converted string.
- */
-static int32_t DbgConsole_ConvertFloatRadixNumToString(char *numstr,
- void *nump,
- int32_t radix,
- uint32_t precision_width)
-{
- int32_t a;
- int32_t b;
- int32_t c;
- int32_t i;
- uint32_t uc;
- double fa;
- double dc;
- double fb;
- double r;
- double fractpart;
- double intpart;
-
- int32_t nlen;
- char *nstrp;
- nlen = 0;
- nstrp = numstr;
- *nstrp++ = '\0';
- r = *(double *)nump;
- if (!r)
- {
- *nstrp = '0';
- ++nlen;
- return nlen;
- }
- fractpart = modf((double)r, (double *)&intpart);
- /* Process fractional part. */
- for (i = 0; i < precision_width; i++)
- {
- fractpart *= radix;
- }
- if (r >= 0)
- {
- fa = fractpart + (double)0.5;
- if (fa >= pow(10, precision_width))
- {
- intpart++;
- }
- }
- else
- {
- fa = fractpart - (double)0.5;
- if (fa <= -pow(10, precision_width))
- {
- intpart--;
- }
- }
- for (i = 0; i < precision_width; i++)
- {
- fb = fa / (int32_t)radix;
- dc = (fa - (int64_t)fb * (int32_t)radix);
- c = (int32_t)dc;
- if (c < 0)
- {
- uc = (uint32_t)c;
- c = (int32_t)(~uc) + 1 + '0';
- }
- else
- {
- c = c + '0';
- }
- fa = fb;
- *nstrp++ = (char)c;
- ++nlen;
- }
- *nstrp++ = (char)'.';
- ++nlen;
- a = (int32_t)intpart;
- if (a == 0)
- {
- *nstrp++ = '0';
- ++nlen;
- }
- else
- {
- while (a != 0)
- {
- b = (int32_t)a / (int32_t)radix;
- c = (int32_t)a - ((int32_t)b * (int32_t)radix);
- if (c < 0)
- {
- uc = (uint32_t)c;
- c = (int32_t)(~uc) + 1 + '0';
- }
- else
- {
- c = c + '0';
- }
- a = b;
- *nstrp++ = (char)c;
- ++nlen;
- }
- }
- return nlen;
-}
-#endif /* PRINTF_FLOAT_ENABLE */
-
-/*!
- * @brief This function outputs its parameters according to a formatted string.
- *
- * @note I/O is performed by calling given function pointer using following
- * (*func_ptr)(c);
- *
- * @param[in] func_ptr Function to put character out.
- * @param[in] fmt_ptr Format string for printf.
- * @param[in] args_ptr Arguments to printf.
- *
- * @return Number of characters
- */
-static int DbgConsole_PrintfFormattedData(PUTCHAR_FUNC func_ptr, const char *fmt, va_list ap)
-{
- /* va_list ap; */
- char *p;
- int32_t c;
-
- char vstr[33];
- char *vstrp = NULL;
- int32_t vlen = 0;
-
- int32_t done;
- int32_t count = 0;
-
- uint32_t field_width;
- uint32_t precision_width;
- char *sval;
- int32_t cval;
- bool use_caps;
- uint8_t radix = 0;
-
-#if PRINTF_ADVANCED_ENABLE
- uint32_t flags_used;
- int32_t schar, dschar;
- int64_t ival;
- uint64_t uval = 0;
- bool valid_precision_width;
-#else
- int32_t ival;
- uint32_t uval = 0;
-#endif /* PRINTF_ADVANCED_ENABLE */
-
-#if PRINTF_FLOAT_ENABLE
- double fval;
-#endif /* PRINTF_FLOAT_ENABLE */
-
- /* Start parsing apart the format string and display appropriate formats and data. */
- for (p = (char *)fmt; (c = *p) != 0; p++)
- {
- /*
- * All formats begin with a '%' marker. Special chars like
- * '\n' or '\t' are normally converted to the appropriate
- * character by the __compiler__. Thus, no need for this
- * routine to account for the '\' character.
- */
- if (c != '%')
- {
- func_ptr(c);
- count++;
- /* By using 'continue', the next iteration of the loop is used, skipping the code that follows. */
- continue;
- }
-
- use_caps = true;
-
-#if PRINTF_ADVANCED_ENABLE
- /* First check for specification modifier flags. */
- flags_used = 0;
- done = false;
- while (!done)
- {
- switch (*++p)
- {
- case '-':
- flags_used |= kPRINTF_Minus;
- break;
- case '+':
- flags_used |= kPRINTF_Plus;
- break;
- case ' ':
- flags_used |= kPRINTF_Space;
- break;
- case '0':
- flags_used |= kPRINTF_Zero;
- break;
- case '#':
- flags_used |= kPRINTF_Pound;
- break;
- default:
- /* We've gone one char too far. */
- --p;
- done = true;
- break;
- }
- }
-#endif /* PRINTF_ADVANCED_ENABLE */
-
- /* Next check for minimum field width. */
- field_width = 0;
- done = false;
- while (!done)
- {
- c = *++p;
- if ((c >= '0') && (c <= '9'))
- {
- field_width = (field_width * 10) + (c - '0');
- }
-#if PRINTF_ADVANCED_ENABLE
- else if (c == '*')
- {
- field_width = (uint32_t)va_arg(ap, uint32_t);
- }
-#endif /* PRINTF_ADVANCED_ENABLE */
- else
- {
- /* We've gone one char too far. */
- --p;
- done = true;
- }
- }
- /* Next check for the width and precision field separator. */
- precision_width = 6;
-#if PRINTF_ADVANCED_ENABLE
- valid_precision_width = false;
-#endif /* PRINTF_ADVANCED_ENABLE */
- if (*++p == '.')
- {
- /* Must get precision field width, if present. */
- precision_width = 0;
- done = false;
- while (!done)
- {
- c = *++p;
- if ((c >= '0') && (c <= '9'))
- {
- precision_width = (precision_width * 10) + (c - '0');
-#if PRINTF_ADVANCED_ENABLE
- valid_precision_width = true;
-#endif /* PRINTF_ADVANCED_ENABLE */
- }
-#if PRINTF_ADVANCED_ENABLE
- else if (c == '*')
- {
- precision_width = (uint32_t)va_arg(ap, uint32_t);
- valid_precision_width = true;
- }
-#endif /* PRINTF_ADVANCED_ENABLE */
- else
- {
- /* We've gone one char too far. */
- --p;
- done = true;
- }
- }
- }
- else
- {
- /* We've gone one char too far. */
- --p;
- }
-#if PRINTF_ADVANCED_ENABLE
- /*
- * Check for the length modifier.
- */
- switch (/* c = */ *++p)
- {
- case 'h':
- if (*++p != 'h')
- {
- flags_used |= kPRINTF_LengthShortInt;
- --p;
- }
- else
- {
- flags_used |= kPRINTF_LengthChar;
- }
- break;
- case 'l':
- if (*++p != 'l')
- {
- flags_used |= kPRINTF_LengthLongInt;
- --p;
- }
- else
- {
- flags_used |= kPRINTF_LengthLongLongInt;
- }
- break;
- default:
- /* we've gone one char too far */
- --p;
- break;
- }
-#endif /* PRINTF_ADVANCED_ENABLE */
- /* Now we're ready to examine the format. */
- c = *++p;
- {
- if ((c == 'd') || (c == 'i') || (c == 'f') || (c == 'F') || (c == 'x') || (c == 'X') || (c == 'o') ||
- (c == 'b') || (c == 'p') || (c == 'u'))
- {
- if ((c == 'd') || (c == 'i'))
- {
-#if PRINTF_ADVANCED_ENABLE
- if (flags_used & kPRINTF_LengthLongLongInt)
- {
- ival = (int64_t)va_arg(ap, int64_t);
- }
- else
-#endif /* PRINTF_ADVANCED_ENABLE */
- {
- ival = (int32_t)va_arg(ap, int32_t);
- }
- vlen = DbgConsole_ConvertRadixNumToString(vstr, &ival, true, 10, use_caps);
- vstrp = &vstr[vlen];
-#if PRINTF_ADVANCED_ENABLE
- if (ival < 0)
- {
- schar = '-';
- ++vlen;
- }
- else
- {
- if (flags_used & kPRINTF_Plus)
- {
- schar = '+';
- ++vlen;
- }
- else
- {
- if (flags_used & kPRINTF_Space)
- {
- schar = ' ';
- ++vlen;
- }
- else
- {
- schar = 0;
- }
- }
- }
- dschar = false;
- /* Do the ZERO pad. */
- if (flags_used & kPRINTF_Zero)
- {
- if (schar)
- {
- func_ptr(schar);
- count++;
- }
- dschar = true;
-
- DbgConsole_PrintfPaddingCharacter('0', vlen, field_width, &count, func_ptr);
- vlen = field_width;
- }
- else
- {
- if (!(flags_used & kPRINTF_Minus))
- {
- DbgConsole_PrintfPaddingCharacter(' ', vlen, field_width, &count, func_ptr);
- if (schar)
- {
- func_ptr(schar);
- count++;
- }
- dschar = true;
- }
- }
- /* The string was built in reverse order, now display in correct order. */
- if ((!dschar) && schar)
- {
- func_ptr(schar);
- count++;
- }
-#endif /* PRINTF_ADVANCED_ENABLE */
- }
-
-#if PRINTF_FLOAT_ENABLE
- if ((c == 'f') || (c == 'F'))
- {
- fval = (double)va_arg(ap, double);
- vlen = DbgConsole_ConvertFloatRadixNumToString(vstr, &fval, 10, precision_width);
- vstrp = &vstr[vlen];
-
-#if PRINTF_ADVANCED_ENABLE
- if (fval < 0)
- {
- schar = '-';
- ++vlen;
- }
- else
- {
- if (flags_used & kPRINTF_Plus)
- {
- schar = '+';
- ++vlen;
- }
- else
- {
- if (flags_used & kPRINTF_Space)
- {
- schar = ' ';
- ++vlen;
- }
- else
- {
- schar = 0;
- }
- }
- }
- dschar = false;
- if (flags_used & kPRINTF_Zero)
- {
- if (schar)
- {
- func_ptr(schar);
- count++;
- }
- dschar = true;
- DbgConsole_PrintfPaddingCharacter('0', vlen, field_width, &count, func_ptr);
- vlen = field_width;
- }
- else
- {
- if (!(flags_used & kPRINTF_Minus))
- {
- DbgConsole_PrintfPaddingCharacter(' ', vlen, field_width, &count, func_ptr);
- if (schar)
- {
- func_ptr(schar);
- count++;
- }
- dschar = true;
- }
- }
- if ((!dschar) && schar)
- {
- func_ptr(schar);
- count++;
- }
-#endif /* PRINTF_ADVANCED_ENABLE */
- }
-#endif /* PRINTF_FLOAT_ENABLE */
- if ((c == 'X') || (c == 'x'))
- {
- if (c == 'x')
- {
- use_caps = false;
- }
-#if PRINTF_ADVANCED_ENABLE
- if (flags_used & kPRINTF_LengthLongLongInt)
- {
- uval = (uint64_t)va_arg(ap, uint64_t);
- }
- else
-#endif /* PRINTF_ADVANCED_ENABLE */
- {
- uval = (uint32_t)va_arg(ap, uint32_t);
- }
- vlen = DbgConsole_ConvertRadixNumToString(vstr, &uval, false, 16, use_caps);
- vstrp = &vstr[vlen];
-
-#if PRINTF_ADVANCED_ENABLE
- dschar = false;
- if (flags_used & kPRINTF_Zero)
- {
- if (flags_used & kPRINTF_Pound)
- {
- func_ptr('0');
- func_ptr((use_caps ? 'X' : 'x'));
- count += 2;
- /*vlen += 2;*/
- dschar = true;
- }
- DbgConsole_PrintfPaddingCharacter('0', vlen, field_width, &count, func_ptr);
- vlen = field_width;
- }
- else
- {
- if (!(flags_used & kPRINTF_Minus))
- {
- if (flags_used & kPRINTF_Pound)
- {
- vlen += 2;
- }
- DbgConsole_PrintfPaddingCharacter(' ', vlen, field_width, &count, func_ptr);
- if (flags_used & kPRINTF_Pound)
- {
- func_ptr('0');
- func_ptr(use_caps ? 'X' : 'x');
- count += 2;
-
- dschar = true;
- }
- }
- }
-
- if ((flags_used & kPRINTF_Pound) && (!dschar))
- {
- func_ptr('0');
- func_ptr(use_caps ? 'X' : 'x');
- count += 2;
- vlen += 2;
- }
-#endif /* PRINTF_ADVANCED_ENABLE */
- }
- if ((c == 'o') || (c == 'b') || (c == 'p') || (c == 'u'))
- {
-#if PRINTF_ADVANCED_ENABLE
- if (flags_used & kPRINTF_LengthLongLongInt)
- {
- uval = (uint64_t)va_arg(ap, uint64_t);
- }
- else
-#endif /* PRINTF_ADVANCED_ENABLE */
- {
- uval = (uint32_t)va_arg(ap, uint32_t);
- }
- switch (c)
- {
- case 'o':
- radix = 8;
- break;
- case 'b':
- radix = 2;
- break;
- case 'p':
- radix = 16;
- break;
- case 'u':
- radix = 10;
- break;
- default:
- break;
- }
- vlen = DbgConsole_ConvertRadixNumToString(vstr, &uval, false, radix, use_caps);
- vstrp = &vstr[vlen];
-#if PRINTF_ADVANCED_ENABLE
- if (flags_used & kPRINTF_Zero)
- {
- DbgConsole_PrintfPaddingCharacter('0', vlen, field_width, &count, func_ptr);
- vlen = field_width;
- }
- else
- {
- if (!(flags_used & kPRINTF_Minus))
- {
- DbgConsole_PrintfPaddingCharacter(' ', vlen, field_width, &count, func_ptr);
- }
- }
-#endif /* PRINTF_ADVANCED_ENABLE */
- }
-#if !PRINTF_ADVANCED_ENABLE
- DbgConsole_PrintfPaddingCharacter(' ', vlen, field_width, &count, func_ptr);
-#endif /* !PRINTF_ADVANCED_ENABLE */
- if (vstrp != NULL)
- {
- while (*vstrp)
- {
- func_ptr(*vstrp--);
- count++;
- }
- }
-#if PRINTF_ADVANCED_ENABLE
- if (flags_used & kPRINTF_Minus)
- {
- DbgConsole_PrintfPaddingCharacter(' ', vlen, field_width, &count, func_ptr);
- }
-#endif /* PRINTF_ADVANCED_ENABLE */
- }
- else if (c == 'c')
- {
- cval = (char)va_arg(ap, uint32_t);
- func_ptr(cval);
- count++;
- }
- else if (c == 's')
- {
- sval = (char *)va_arg(ap, char *);
- if (sval)
- {
-#if PRINTF_ADVANCED_ENABLE
- if (valid_precision_width)
- {
- vlen = precision_width;
- }
- else
- {
- vlen = strlen(sval);
- }
-#else
- vlen = strlen(sval);
-#endif /* PRINTF_ADVANCED_ENABLE */
-#if PRINTF_ADVANCED_ENABLE
- if (!(flags_used & kPRINTF_Minus))
-#endif /* PRINTF_ADVANCED_ENABLE */
- {
- DbgConsole_PrintfPaddingCharacter(' ', vlen, field_width, &count, func_ptr);
- }
-
-#if PRINTF_ADVANCED_ENABLE
- if (valid_precision_width)
- {
- while ((*sval) && (vlen > 0))
- {
- func_ptr(*sval++);
- count++;
- vlen--;
- }
- /* In case that vlen sval is shorter than vlen */
- vlen = precision_width - vlen;
- }
- else
- {
-#endif /* PRINTF_ADVANCED_ENABLE */
- while (*sval)
- {
- func_ptr(*sval++);
- count++;
- }
-#if PRINTF_ADVANCED_ENABLE
- }
-#endif /* PRINTF_ADVANCED_ENABLE */
-
-#if PRINTF_ADVANCED_ENABLE
- if (flags_used & kPRINTF_Minus)
- {
- DbgConsole_PrintfPaddingCharacter(' ', vlen, field_width, &count, func_ptr);
- }
-#endif /* PRINTF_ADVANCED_ENABLE */
- }
- }
- else
- {
- func_ptr(c);
- count++;
- }
- }
- }
- return count;
-}
-
-/*!
- * @brief Converts an input line of ASCII characters based upon a provided
- * string format.
- *
- * @param[in] line_ptr The input line of ASCII data.
- * @param[in] format Format first points to the format string.
- * @param[in] args_ptr The list of parameters.
- *
- * @return Number of input items converted and assigned.
- * @retval IO_EOF When line_ptr is empty string "".
- */
-static int DbgConsole_ScanfFormattedData(const char *line_ptr, char *format, va_list args_ptr)
-{
- uint8_t base;
- int8_t neg;
- /* Identifier for the format string. */
- char *c = format;
- char temp;
- char *buf;
- /* Flag telling the conversion specification. */
- uint32_t flag = 0;
- /* Filed width for the matching input streams. */
- uint32_t field_width;
- /* How many arguments are assigned except the suppress. */
- uint32_t nassigned = 0;
- /* How many characters are read from the input streams. */
- uint32_t n_decode = 0;
-
- int32_t val;
-
- const char *s;
- /* Identifier for the input string. */
- const char *p = line_ptr;
-
- /* Return EOF error before any conversion. */
- if (*p == '\0')
- {
- return -1;
- }
-
- /* Decode directives. */
- while ((*c) && (*p))
- {
- /* Ignore all white-spaces in the format strings. */
- if (DbgConsole_ScanIgnoreWhiteSpace((const char **)&c))
- {
- n_decode += DbgConsole_ScanIgnoreWhiteSpace(&p);
- }
- else if ((*c != '%') || ((*c == '%') && (*(c + 1) == '%')))
- {
- /* Ordinary characters. */
- c++;
- if (*p == *c)
- {
- n_decode++;
- p++;
- c++;
- }
- else
- {
- /* Match failure. Misalignment with C99, the unmatched characters need to be pushed back to stream.
- * However, it is deserted now. */
- break;
- }
- }
- else
- {
- /* convernsion specification */
- c++;
- /* Reset. */
- flag = 0;
- field_width = 0;
- base = 0;
-
- /* Loop to get full conversion specification. */
- while ((*c) && (!(flag & kSCANF_DestMask)))
- {
- switch (*c)
- {
-#if SCANF_ADVANCED_ENABLE
- case '*':
- if (flag & kSCANF_Suppress)
- {
- /* Match failure. */
- return nassigned;
- }
- flag |= kSCANF_Suppress;
- c++;
- break;
- case 'h':
- if (flag & kSCANF_LengthMask)
- {
- /* Match failure. */
- return nassigned;
- }
-
- if (c[1] == 'h')
- {
- flag |= kSCANF_LengthChar;
- c++;
- }
- else
- {
- flag |= kSCANF_LengthShortInt;
- }
- c++;
- break;
- case 'l':
- if (flag & kSCANF_LengthMask)
- {
- /* Match failure. */
- return nassigned;
- }
-
- if (c[1] == 'l')
- {
- flag |= kSCANF_LengthLongLongInt;
- c++;
- }
- else
- {
- flag |= kSCANF_LengthLongInt;
- }
- c++;
- break;
-#endif /* SCANF_ADVANCED_ENABLE */
-#if SCANF_FLOAT_ENABLE
- case 'L':
- if (flag & kSCANF_LengthMask)
- {
- /* Match failure. */
- return nassigned;
- }
- flag |= kSCANF_LengthLongLongDouble;
- c++;
- break;
-#endif /* SCANF_FLOAT_ENABLE */
- case '0':
- case '1':
- case '2':
- case '3':
- case '4':
- case '5':
- case '6':
- case '7':
- case '8':
- case '9':
- if (field_width)
- {
- /* Match failure. */
- return nassigned;
- }
- do
- {
- field_width = field_width * 10 + *c - '0';
- c++;
- } while ((*c >= '0') && (*c <= '9'));
- break;
- case 'd':
- base = 10;
- flag |= kSCANF_TypeSinged;
- flag |= kSCANF_DestInt;
- c++;
- break;
- case 'u':
- base = 10;
- flag |= kSCANF_DestInt;
- c++;
- break;
- case 'o':
- base = 8;
- flag |= kSCANF_DestInt;
- c++;
- break;
- case 'x':
- case 'X':
- base = 16;
- flag |= kSCANF_DestInt;
- c++;
- break;
- case 'i':
- base = 0;
- flag |= kSCANF_DestInt;
- c++;
- break;
-#if SCANF_FLOAT_ENABLE
- case 'a':
- case 'A':
- case 'e':
- case 'E':
- case 'f':
- case 'F':
- case 'g':
- case 'G':
- flag |= kSCANF_DestFloat;
- c++;
- break;
-#endif /* SCANF_FLOAT_ENABLE */
- case 'c':
- flag |= kSCANF_DestChar;
- if (!field_width)
- {
- field_width = 1;
- }
- c++;
- break;
- case 's':
- flag |= kSCANF_DestString;
- c++;
- break;
- default:
- return nassigned;
- }
- }
-
- if (!(flag & kSCANF_DestMask))
- {
- /* Format strings are exhausted. */
- return nassigned;
- }
-
- if (!field_width)
- {
- /* Large than length of a line. */
- field_width = 99;
- }
-
- /* Matching strings in input streams and assign to argument. */
- switch (flag & kSCANF_DestMask)
- {
- case kSCANF_DestChar:
- s = (const char *)p;
- buf = va_arg(args_ptr, char *);
- while ((field_width--) && (*p))
- {
- if (!(flag & kSCANF_Suppress))
- {
- *buf++ = *p++;
- }
- else
- {
- p++;
- }
- n_decode++;
- }
-
- if ((!(flag & kSCANF_Suppress)) && (s != p))
- {
- nassigned++;
- }
- break;
- case kSCANF_DestString:
- n_decode += DbgConsole_ScanIgnoreWhiteSpace(&p);
- s = p;
- buf = va_arg(args_ptr, char *);
- while ((field_width--) && (*p != '\0') && (*p != ' ') && (*p != '\t') && (*p != '\n') &&
- (*p != '\r') && (*p != '\v') && (*p != '\f'))
- {
- if (flag & kSCANF_Suppress)
- {
- p++;
- }
- else
- {
- *buf++ = *p++;
- }
- n_decode++;
- }
-
- if ((!(flag & kSCANF_Suppress)) && (s != p))
- {
- /* Add NULL to end of string. */
- *buf = '\0';
- nassigned++;
- }
- break;
- case kSCANF_DestInt:
- n_decode += DbgConsole_ScanIgnoreWhiteSpace(&p);
- s = p;
- val = 0;
- if ((base == 0) || (base == 16))
- {
- if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X')))
- {
- base = 16;
- if (field_width >= 1)
- {
- p += 2;
- n_decode += 2;
- field_width -= 2;
- }
- }
- }
-
- if (base == 0)
- {
- if (s[0] == '0')
- {
- base = 8;
- }
- else
- {
- base = 10;
- }
- }
-
- neg = 1;
- switch (*p)
- {
- case '-':
- neg = -1;
- n_decode++;
- p++;
- field_width--;
- break;
- case '+':
- neg = 1;
- n_decode++;
- p++;
- field_width--;
- break;
- default:
- break;
- }
-
- while ((*p) && (field_width--))
- {
- if ((*p <= '9') && (*p >= '0'))
- {
- temp = *p - '0';
- }
- else if ((*p <= 'f') && (*p >= 'a'))
- {
- temp = *p - 'a' + 10;
- }
- else if ((*p <= 'F') && (*p >= 'A'))
- {
- temp = *p - 'A' + 10;
- }
- else
- {
- temp = base;
- }
-
- if (temp >= base)
- {
- break;
- }
- else
- {
- val = base * val + temp;
- }
- p++;
- n_decode++;
- }
- val *= neg;
- if (!(flag & kSCANF_Suppress))
- {
-#if SCANF_ADVANCED_ENABLE
- switch (flag & kSCANF_LengthMask)
- {
- case kSCANF_LengthChar:
- if (flag & kSCANF_TypeSinged)
- {
- *va_arg(args_ptr, signed char *) = (signed char)val;
- }
- else
- {
- *va_arg(args_ptr, unsigned char *) = (unsigned char)val;
- }
- break;
- case kSCANF_LengthShortInt:
- if (flag & kSCANF_TypeSinged)
- {
- *va_arg(args_ptr, signed short *) = (signed short)val;
- }
- else
- {
- *va_arg(args_ptr, unsigned short *) = (unsigned short)val;
- }
- break;
- case kSCANF_LengthLongInt:
- if (flag & kSCANF_TypeSinged)
- {
- *va_arg(args_ptr, signed long int *) = (signed long int)val;
- }
- else
- {
- *va_arg(args_ptr, unsigned long int *) = (unsigned long int)val;
- }
- break;
- case kSCANF_LengthLongLongInt:
- if (flag & kSCANF_TypeSinged)
- {
- *va_arg(args_ptr, signed long long int *) = (signed long long int)val;
- }
- else
- {
- *va_arg(args_ptr, unsigned long long int *) = (unsigned long long int)val;
- }
- break;
- default:
- /* The default type is the type int. */
- if (flag & kSCANF_TypeSinged)
- {
- *va_arg(args_ptr, signed int *) = (signed int)val;
- }
- else
- {
- *va_arg(args_ptr, unsigned int *) = (unsigned int)val;
- }
- break;
- }
-#else
- /* The default type is the type int. */
- if (flag & kSCANF_TypeSinged)
- {
- *va_arg(args_ptr, signed int *) = (signed int)val;
- }
- else
- {
- *va_arg(args_ptr, unsigned int *) = (unsigned int)val;
- }
-#endif /* SCANF_ADVANCED_ENABLE */
- nassigned++;
- }
- break;
-#if SCANF_FLOAT_ENABLE
- case kSCANF_DestFloat:
- n_decode += DbgConsole_ScanIgnoreWhiteSpace(&p);
- fnum = strtod(p, (char **)&s);
-
- if ((fnum >= HUGE_VAL) || (fnum <= -HUGE_VAL))
- {
- break;
- }
-
- n_decode += (int)(s) - (int)(p);
- p = s;
- if (!(flag & kSCANF_Suppress))
- {
- if (flag & kSCANF_LengthLongLongDouble)
- {
- *va_arg(args_ptr, double *) = fnum;
- }
- else
- {
- *va_arg(args_ptr, float *) = (float)fnum;
- }
- nassigned++;
- }
- break;
-#endif /* SCANF_FLOAT_ENABLE */
- default:
- return nassigned;
- }
- }
- }
- return nassigned;
-}
-#endif /* SDK_DEBUGCONSOLE */
-/*************Code to support toolchain's printf, scanf *******************************/
-/* These function __write and __read is used to support IAR toolchain to printf and scanf*/
-#if (defined(__ICCARM__))
-#pragma weak __write
-size_t __write(int handle, const unsigned char *buffer, size_t size)
-{
- if (buffer == 0)
- {
- /*
- * This means that we should flush internal buffers. Since we don't we just return.
- * (Remember, "handle" == -1 means that all handles should be flushed.)
- */
- return 0;
- }
-
- /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
- if ((handle != 1) && (handle != 2))
- {
- return ((size_t)-1);
- }
-
- /* Do nothing if the debug UART is not initialized. */
- if (s_debugConsole.type == DEBUG_CONSOLE_DEVICE_TYPE_NONE)
- {
- return ((size_t)-1);
- }
-
- /* Send data. */
- s_debugConsole.ops.tx_union.PutChar(s_debugConsole.base, buffer, 1);
- return size;
-}
-
-#pragma weak __read
-size_t __read(int handle, unsigned char *buffer, size_t size)
-{
- /* This function only reads from "standard in", for all other file handles it returns failure. */
- if (handle != 0)
- {
- return ((size_t)-1);
- }
-
- /* Do nothing if the debug UART is not initialized. */
- if (s_debugConsole.type == DEBUG_CONSOLE_DEVICE_TYPE_NONE)
- {
- return ((size_t)-1);
- }
-
- /* Receive data. */
- s_debugConsole.ops.rx_union.GetChar(s_debugConsole.base, buffer, size);
-
- return size;
-}
-
-/* support LPC Xpresso with RedLib */
-#elif(defined(__REDLIB__))
-
-#if (!SDK_DEBUGCONSOLE) && (defined(SDK_DEBUGCONSOLE_UART))
-int __attribute__((weak)) __sys_write(int handle, char *buffer, int size)
-{
- if (buffer == 0)
- {
- /* return -1 if error. */
- return -1;
- }
-
- /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
- if ((handle != 1) && (handle != 2))
- {
- return -1;
- }
-
- /* Do nothing if the debug UART is not initialized. */
- if (s_debugConsole.type == DEBUG_CONSOLE_DEVICE_TYPE_NONE)
- {
- return -1;
- }
-
- /* Send data. */
- s_debugConsole.ops.tx_union.PutChar(s_debugConsole.base, (uint8_t *)buffer, size);
- return 0;
-}
-
-int __attribute__((weak)) __sys_readc(void)
-{
- char tmp;
- /* Do nothing if the debug UART is not initialized. */
- if (s_debugConsole.type == DEBUG_CONSOLE_DEVICE_TYPE_NONE)
- {
- return -1;
- }
-
- /* Receive data. */
- s_debugConsole.ops.rx_union.GetChar(s_debugConsole.base, (uint8_t *)&tmp, sizeof(tmp));
- return tmp;
-}
-#endif
-
-/* These function __write and __read is used to support ARM_GCC, KDS, Atollic toolchains to printf and scanf*/
-#elif(defined(__GNUC__))
-
-#if ((defined(__GNUC__) && (!defined(__MCUXPRESSO))) || \
- (defined(__MCUXPRESSO) && (!SDK_DEBUGCONSOLE) && (defined(SDK_DEBUGCONSOLE_UART))))
-
-int __attribute__((weak)) _write(int handle, char *buffer, int size)
-{
- if (buffer == 0)
- {
- /* return -1 if error. */
- return -1;
- }
-
- /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
- if ((handle != 1) && (handle != 2))
- {
- return -1;
- }
-
- /* Do nothing if the debug UART is not initialized. */
- if (s_debugConsole.type == DEBUG_CONSOLE_DEVICE_TYPE_NONE)
- {
- return -1;
- }
-
- /* Send data. */
- s_debugConsole.ops.tx_union.PutChar(s_debugConsole.base, (uint8_t *)buffer, size);
- return size;
-}
-
-int __attribute__((weak)) _read(int handle, char *buffer, int size)
-{
- /* This function only reads from "standard in", for all other file handles it returns failure. */
- if (handle != 0)
- {
- return -1;
- }
-
- /* Do nothing if the debug UART is not initialized. */
- if (s_debugConsole.type == DEBUG_CONSOLE_DEVICE_TYPE_NONE)
- {
- return -1;
- }
-
- /* Receive data. */
- s_debugConsole.ops.rx_union.GetChar(s_debugConsole.base, (uint8_t *)buffer, size);
- return size;
-}
-#endif
-
-/* These function fputc and fgetc is used to support KEIL toolchain to printf and scanf*/
-#elif defined(__CC_ARM)
-struct __FILE
-{
- int handle;
- /*
- * Whatever you require here. If the only file you are using is standard output using printf() for debugging,
- * no file handling is required.
- */
-};
-
-/* FILE is typedef in stdio.h. */
-#pragma weak __stdout
-#pragma weak __stdin
-FILE __stdout;
-FILE __stdin;
-
-#pragma weak fputc
-int fputc(int ch, FILE *f)
-{
- /* Do nothing if the debug UART is not initialized. */
- if (s_debugConsole.type == DEBUG_CONSOLE_DEVICE_TYPE_NONE)
- {
- return -1;
- }
-
- /* Send data. */
- s_debugConsole.ops.tx_union.PutChar(s_debugConsole.base, (uint8_t *)(&ch), 1);
- return 1;
-}
-
-#pragma weak fgetc
-int fgetc(FILE *f)
-{
- char ch;
- /* Do nothing if the debug UART is not initialized. */
- if (s_debugConsole.type == DEBUG_CONSOLE_DEVICE_TYPE_NONE)
- {
- return -1;
- }
-
- /* Receive data. */
- s_debugConsole.ops.rx_union.GetChar(s_debugConsole.base, (uint8_t *)(&ch), 1);
- return ch;
-}
-#endif /* __ICCARM__ */
diff --git a/third_party/nxp/JN5189/drivers/fsl_debug_console.h b/third_party/nxp/JN5189/drivers/fsl_debug_console.h
deleted file mode 100755
index 44c206a..0000000
--- a/third_party/nxp/JN5189/drivers/fsl_debug_console.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
-* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
-* Copyright 2016-2019 NXP
-* All rights reserved.
-*
-* SPDX-License-Identifier: BSD-3-Clause
-*/
-
-/*
- * Debug console shall provide input and output functions to scan and print formatted data.
- * o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier"
- * - [flags] :'-', '+', '#', ' ', '0'
- * - [width]: number (0,1...)
- * - [.precision]: number (0,1...)
- * - [length]: do not support
- * - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n'
- * o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier"
- * - [*]: is supported.
- * - [width]: number (0,1...)
- * - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t')
- * - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's'
- */
-
-#ifndef _FSL_DEBUGCONSOLE_H_
-#define _FSL_DEBUGCONSOLE_H_
-
-#include "fsl_common.h"
-
-/*
- * @addtogroup debugconsole
- * @{
- */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @brief Definition to select sdk or toolchain printf, scanf. */
-#ifndef SDK_DEBUGCONSOLE
-#define SDK_DEBUGCONSOLE 1U
-#endif
-
-#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE)
-#include <stdio.h>
-#endif
-
-/*! @brief Definition to printf the float number. */
-#ifndef PRINTF_FLOAT_ENABLE
-#define PRINTF_FLOAT_ENABLE 0U
-#endif /* PRINTF_FLOAT_ENABLE */
-
-/*! @brief Definition to scanf the float number. */
-#ifndef SCANF_FLOAT_ENABLE
-#define SCANF_FLOAT_ENABLE 0U
-#endif /* SCANF_FLOAT_ENABLE */
-
-/*! @brief Definition to support advanced format specifier for printf. */
-#ifndef PRINTF_ADVANCED_ENABLE
-#define PRINTF_ADVANCED_ENABLE 0U
-#endif /* PRINTF_ADVANCED_ENABLE */
-
-/*! @brief Definition to support advanced format specifier for scanf. */
-#ifndef SCANF_ADVANCED_ENABLE
-#define SCANF_ADVANCED_ENABLE 0U
-#endif /* SCANF_ADVANCED_ENABLE */
-
-#if SDK_DEBUGCONSOLE /* Select printf, scanf, putchar, getchar of SDK version. */
-#define PRINTF DbgConsole_Printf
-#define SCANF DbgConsole_Scanf
-#define PUTCHAR DbgConsole_Putchar
-#define GETCHAR DbgConsole_Getchar
-#else /* Select printf, scanf, putchar, getchar of toolchain. */
-#define PRINTF printf
-#define SCANF scanf
-#define PUTCHAR putchar
-#define GETCHAR getchar
-#endif /* SDK_DEBUGCONSOLE */
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus */
-
-/*! @name Initialization*/
-/* @{ */
-
-/*!
- * @brief Initializes the the peripheral used for debug messages.
- *
- * Call this function to enable debug log messages to be output via the specified peripheral,
- * frequency of peripheral source clock, and base address at the specified baud rate.
- * After this function has returned, stdout and stdin are connected to the selected peripheral.
- *
- * @param baseAddr Indicates the address of the peripheral used to send debug messages.
- * @param baudRate The desired baud rate in bits per second.
- * @param device Low level device type for the debug console, can be one of the following.
- * @arg DEBUG_CONSOLE_DEVICE_TYPE_UART,
- * @arg DEBUG_CONSOLE_DEVICE_TYPE_LPUART,
- * @arg DEBUG_CONSOLE_DEVICE_TYPE_LPSCI,
- * @arg DEBUG_CONSOLE_DEVICE_TYPE_USBCDC.
- * @param clkSrcFreq Frequency of peripheral source clock.
- *
- * @return Indicates whether initialization was successful or not.
- * @retval kStatus_Success Execution successfully
- * @retval kStatus_Fail Execution failure
- * @retval kStatus_InvalidArgument Invalid argument existed
- */
-status_t DbgConsole_Init(uint32_t baseAddr, uint32_t baudRate, uint8_t device, uint32_t clkSrcFreq);
-
-/*!
- * @brief De-initializes the peripheral used for debug messages.
- *
- * Call this function to disable debug log messages to be output via the specified peripheral
- * base address and at the specified baud rate.
- *
- * @return Indicates whether de-initialization was successful or not.
- */
-status_t DbgConsole_Deinit(void);
-
-#if SDK_DEBUGCONSOLE
-/*!
- * @brief Writes formatted output to the standard output stream.
- *
- * Call this function to write a formatted output to the standard output stream.
- *
- * @param fmt_s Format control string.
- * @return Returns the number of characters printed or a negative value if an error occurs.
- */
-int DbgConsole_Printf(const char *fmt_s, ...);
-
-/*!
- * @brief Writes a character to stdout.
- *
- * Call this function to write a character to stdout.
- *
- * @param ch Character to be written.
- * @return Returns the character written.
- */
-int DbgConsole_Putchar(int ch);
-
-/*!
- * @brief Reads formatted data from the standard input stream.
- *
- * Call this function to read formatted data from the standard input stream.
- *
- * @param fmt_ptr Format control string.
- * @return Returns the number of fields successfully converted and assigned.
- */
-int DbgConsole_Scanf(char *fmt_ptr, ...);
-
-/*!
- * @brief Reads a character from standard input.
- *
- * Call this function to read a character from standard input.
- *
- * @return Returns the character read.
- */
-int DbgConsole_Getchar(void);
-
-#endif /* SDK_DEBUGCONSOLE */
-
-/*! @} */
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus */
-
-/*! @} */
-
-#endif /* _FSL_DEBUGCONSOLE_H_ */
diff --git a/third_party/nxp/JN5189/libraries/libMicroSpecific_JN518x.a b/third_party/nxp/JN5189/libraries/libMicroSpecific_JN518x.a
deleted file mode 100755
index 2120b36..0000000
--- a/third_party/nxp/JN5189/libraries/libMicroSpecific_JN518x.a
+++ /dev/null
Binary files differ
diff --git a/third_party/nxp/JN5189/libraries/libMiniMac.a b/third_party/nxp/JN5189/libraries/libMiniMac.a
deleted file mode 100755
index ba35d12..0000000
--- a/third_party/nxp/JN5189/libraries/libMiniMac.a
+++ /dev/null
Binary files differ
diff --git a/third_party/nxp/JN5189/libraries/libRadio.a b/third_party/nxp/JN5189/libraries/libRadio.a
deleted file mode 100755
index e8a95ef..0000000
--- a/third_party/nxp/JN5189/libraries/libRadio.a
+++ /dev/null
Binary files differ
diff --git a/third_party/nxp/JN5189/system_JN5189.c b/third_party/nxp/JN5189/system_JN5189.c
deleted file mode 100755
index 43fdde2..0000000
--- a/third_party/nxp/JN5189/system_JN5189.c
+++ /dev/null
@@ -1,270 +0,0 @@
-/*
-** ###################################################################
-** Processors: JN5189HN
-** JN5189THN
-**
-** Compilers: Keil ARM C/C++ Compiler
-** GNU C Compiler
-** IAR ANSI C/C++ Compiler for ARM
-** MCUXpresso Compiler
-**
-** Reference manual: JN5189 User manual Rev0.1 27 July 2018
-** Version: rev. 1.0, 2018-07-31
-** Build: b180731
-**
-** Abstract:
-** Provides a system configuration function and a global variable that
-** contains the system frequency. It configures the device and initializes
-** the oscillator (PLL) that is part of the microcontroller device.
-**
-** Copyright 2016 Freescale Semiconductor, Inc.
-** Copyright 2016-2018 NXP
-**
-** SPDX-License-Identifier: BSD-3-Clause
-**
-** http: www.nxp.com
-** mail: support@nxp.com
-**
-** Revisions:
-** - rev. 1.0 (2018-07-31)
-** Initial version.
-**
-** ###################################################################
-*/
-
-/*!
- * @file JN5189
- * @version 1.0
- * @date 2018-07-31
- * @brief Device specific configuration file for JN5189 (implementation file)
- *
- * Provides a system configuration function and a global variable that contains
- * the system frequency. It configures the device and initializes the oscillator
- * (PLL) that is part of the microcontroller device.
- */
-
-#include <stdint.h>
-#include "fsl_device_registers.h"
-#include "rom_api.h"
-
-/**
- * Clock source selections for the Main Clock
- */
-typedef enum _main_clock_src
-{
- kCLOCK_MainFro12M = 0,
- kCLOCK_MainOsc32k = 1,
- kCLOCK_MainXtal32M = 2,
- kCLOCK_MainFro32M = 3,
- kCLOCK_MainFro48M = 4,
- kCLOCK_MainExtClk = 5,
- kCLOCK_MainFro1M = 6,
-} main_clock_src_t;
-
-
-/**
- * Clock source selections for CLKOUT
- */
-typedef enum _clkout_clock_src
-{
- kCLOCK_ClkoutMainClk = 0,
- kCLOCK_ClkoutXtal32k = 1,
- kCLOCK_ClkoutFro32k = 2,
- kCLOCK_ClkoutXtal32M = 3,
- kCLOCK_ClkoutDcDcTest= 4,
- kCLOCK_ClkoutFro48M = 5,
- kCLOCK_ClkoutFro1M = 6,
- kCLOCK_ClkoutNoClock = 7
-} clkout_clock_src_t;
-
-typedef enum
-{
- FRO12M_ENA = (1 << 0),
- FRO32M_ENA = (1 << 1),
- FRO48M_ENA = (1 << 2),
- FRO64M_ENA = (1 << 3),
- FRO96M_ENA = (1 << 4)
-} Fro_ClkSel_t;
-
-#define OSC32K_FREQ 32768UL
-#define FRO32K_FREQ 32768UL
-#define OSC32M_FREQ 32000000UL
-#define XTAL32M_FREQ 32000000UL
-#define FRO64M_FREQ 64000000UL
-#define FRO1M_FREQ 1000000UL
-#define FRO12M_FREQ 12000000UL
-#define FRO32M_FREQ 32000000UL
-#define FRO48M_FREQ 48000000UL
-
-static const uint32_t g_Ext_Clk_Freq = 0U;
-
-extern unsigned int __Vectors;
-extern WEAK void SystemInit(void);
-extern WEAK void WarmMain(void);
-
-static uint32_t CLOCK_GetXtal32kFreq(void)
-{
- uint32_t freq = 0;
-
- if (((PMC->PDRUNCFG & PMC_PDRUNCFG_ENA_XTAL32K_MASK)
- >> PMC_PDRUNCFG_ENA_XTAL32K_SHIFT) != 0)
- {
- freq = OSC32K_FREQ;
- }
-
- return freq;
-}
-
-static uint32_t CLOCK_GetXtal32MFreq(void)
-{
- return XTAL32M_FREQ;
-}
-
-static uint32_t CLOCK_GetFro32kFreq(void)
-{
- uint32_t freq = 0;
-
- if (((PMC->PDRUNCFG & PMC_PDRUNCFG_ENA_FRO32K_MASK)
- >> PMC_PDRUNCFG_ENA_FRO32K_SHIFT) != 0)
- {
- freq = FRO32K_FREQ;
- }
-
- return freq;
-}
-
-static uint32_t CLOCK_GetFro1MFreq(void)
-{
- return FRO1M_FREQ;
-}
-
-static uint32_t CLOCK_GetFro12MFreq(void)
-{
- uint32_t freq = 0;
-
- if (((PMC->FRO192M & PMC_FRO192M_DIVSEL_MASK) >>
- PMC_FRO192M_DIVSEL_SHIFT) & FRO12M_ENA)
- {
- freq = FRO12M_FREQ;
- }
-
- return freq;
-}
-
-static uint32_t CLOCK_GetFro32MFreq(void)
-{
- uint32_t freq = 0;
-
- if (((PMC->FRO192M & PMC_FRO192M_DIVSEL_MASK) >>
- PMC_FRO192M_DIVSEL_SHIFT) & FRO32M_ENA)
- {
- freq = FRO32M_FREQ;
- }
-
- return freq;
-}
-
-static uint32_t CLOCK_GetFro48MFreq(void)
-{
- uint32_t freq = 0;
-
- if (((PMC->FRO192M & PMC_FRO192M_DIVSEL_MASK) >>
- PMC_FRO192M_DIVSEL_SHIFT) & FRO48M_ENA)
- {
- freq = FRO48M_FREQ;
- }
-
- return freq;
-}
-
-static uint32_t CLOCK_GetOsc32kFreq(void)
-{
- uint32_t freq = 0;
- if ((SYSCON->OSC32CLKSEL & SYSCON_OSC32CLKSEL_SEL32KHZ_MASK) != 0)
- {
- freq = CLOCK_GetXtal32kFreq();
- }
- else
- {
- freq = CLOCK_GetFro32kFreq();
- }
- return freq;
-}
-
-/* Return main clock rate */
-static uint32_t CLOCK_GetMainClockRate(void)
-{
- uint32_t freq = 0;
-
- switch ((main_clock_src_t)((SYSCON->MAINCLKSEL & SYSCON_MAINCLKSEL_SEL_MASK)
- >> SYSCON_MAINCLKSEL_SEL_SHIFT))
- {
- case kCLOCK_MainFro12M:
- freq = CLOCK_GetFro12MFreq();
- break;
-
- case kCLOCK_MainOsc32k:
- freq = CLOCK_GetOsc32kFreq();
- break;
-
- case kCLOCK_MainXtal32M:
- freq = CLOCK_GetXtal32MFreq();
- break;
-
- case kCLOCK_MainFro32M:
- freq = CLOCK_GetFro32MFreq();
- break;
-
- case kCLOCK_MainFro48M:
- freq = CLOCK_GetFro48MFreq();
- break;
-
- case kCLOCK_MainExtClk:
- freq = g_Ext_Clk_Freq;
- break;
-
- case kCLOCK_MainFro1M:
- freq = CLOCK_GetFro1MFreq();
- break;
- }
-
- return freq;
-}
-
-
-
-/* ----------------------------------------------------------------------------
- -- Core clock
- ---------------------------------------------------------------------------- */
-
-uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
-
-/* ----------------------------------------------------------------------------
- -- SystemInit()
- ---------------------------------------------------------------------------- */
-
-void SystemInit (void) {
- uint32_t trim;
- /* Initialise SystemCoreClock value */
- SystemCoreClockUpdate();
-
- /* Initialise NVIC priority grouping value */
- NVIC_SetPriorityGrouping(4);
-
- /* Apply FRO1M trim value */
- trim = *(uint32_t*)(0x9FCD0U);
-
- if(trim & 0x1U)
- {
- PMC->FRO1M = (PMC->FRO1M & ~PMC_FRO1M_FREQSEL_MASK) | ((trim>>1) & PMC_FRO1M_FREQSEL_MASK);
- }
-}
-
-/* ----------------------------------------------------------------------------
- -- SystemCoreClockUpdate()
- ---------------------------------------------------------------------------- */
-
-void SystemCoreClockUpdate (void) {
- SystemCoreClock = (CLOCK_GetMainClockRate() / ((SYSCON->AHBCLKDIV & SYSCON_AHBCLKDIV_DIV_MASK) + 1U));
-}
-
diff --git a/third_party/nxp/JN5189DK6/CMSIS/Include/arm_common_tables.h b/third_party/nxp/JN5189DK6/CMSIS/Include/arm_common_tables.h
new file mode 100755
index 0000000..8742a56
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/CMSIS/Include/arm_common_tables.h
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. October 2015
+* $Revision: V.1.4.5 a
+*
+* Project: CMSIS DSP Library
+* Title: arm_common_tables.h
+*
+* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+/* extern const q31_t realCoefAQ31[1024]; */
+/* extern const q31_t realCoefBQ31[1024]; */
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /* ARM_COMMON_TABLES_H */
diff --git a/third_party/nxp/JN5189DK6/CMSIS/Include/arm_const_structs.h b/third_party/nxp/JN5189DK6/CMSIS/Include/arm_const_structs.h
new file mode 100755
index 0000000..726d06e
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/CMSIS/Include/arm_const_structs.h
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_const_structs.h
+*
+* Description: This file has constant structs that are initialized for
+* user convenience. For example, some can be given as
+* arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/third_party/nxp/JN5189DK6/CMSIS/Include/arm_math.h b/third_party/nxp/JN5189DK6/CMSIS/Include/arm_math.h
new file mode 100755
index 0000000..d33f8a9
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/CMSIS/Include/arm_math.h
@@ -0,0 +1,7154 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+*
+* $Date: 20. October 2015
+* $Revision: V1.4.5 b
+*
+* Project: CMSIS DSP Library
+* Title: arm_math.h
+*
+* Description: Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+ \mainpage CMSIS DSP Software Library
+ *
+ * Introduction
+ * ------------
+ *
+ * This user manual describes the CMSIS DSP software library,
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.
+ *
+ * The library is divided into a number of functions each covering a specific category:
+ * - Basic math functions
+ * - Fast math functions
+ * - Complex math functions
+ * - Filters
+ * - Matrix functions
+ * - Transforms
+ * - Motor control functions
+ * - Statistical functions
+ * - Support functions
+ * - Interpolation functions
+ *
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+ * 32-bit integer and 32-bit floating-point values.
+ *
+ * Using the Library
+ * ------------
+ *
+ * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+ * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)
+ * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)
+ * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+ * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+ * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+ * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+ * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)
+ * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)
+ *
+ * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+ * public header file <code> arm_math.h</code> for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+ * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
+ * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+ *
+ * Examples
+ * --------
+ *
+ * The library ships with a number of examples which demonstrate how to use the library functions.
+ *
+ * Toolchain Support
+ * ------------
+ *
+ * The library has been developed and tested with MDK-ARM version 5.14.0.0
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+ *
+ * Building the Library
+ * ------------
+ *
+ * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+ * - arm_cortexM_math.uvprojx
+ *
+ *
+ * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+ *
+ * Pre-processor Macros
+ * ------------
+ *
+ * Each library project have differant pre-processor macros.
+ *
+ * - UNALIGNED_SUPPORT_DISABLE:
+ *
+ * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+ *
+ * - ARM_MATH_BIG_ENDIAN:
+ *
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+ *
+ * - ARM_MATH_MATRIX_CHECK:
+ *
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+ *
+ * - ARM_MATH_ROUNDING:
+ *
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions
+ *
+ * - ARM_MATH_CMx:
+ *
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+ * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+ * ARM_MATH_CM7 for building the library on cortex-M7.
+ *
+ * - __FPU_PRESENT:
+ *
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+ *
+ * <hr>
+ * CMSIS-DSP in ARM::CMSIS Pack
+ * -----------------------------
+ *
+ * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+ * |File/Folder |Content |
+ * |------------------------------|------------------------------------------------------------------------|
+ * |\b CMSIS\\Documentation\\DSP | This documentation |
+ * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |
+ * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |
+ * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |
+ *
+ * <hr>
+ * Revision History of CMSIS-DSP
+ * ------------
+ * Please refer to \ref ChangeLog_pg.
+ *
+ * Copyright Notice
+ * ------------
+ *
+ * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+ */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures. For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ * typedef struct
+ * {
+ * uint16_t numRows; // number of rows of the matrix.
+ * uint16_t numCols; // number of columns of the matrix.
+ * float32_t *pData; // points to the data of the matrix.
+ * } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data. The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order. That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ * pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure. For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ * <pre>
+ * ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ * ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ * ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings. By default this macro is defined
+ * and size checking is enabled. By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster. With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+/* ignore some GCC warnings */
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+ #include "core_cm7.h"
+#elif defined (ARM_MATH_CM4)
+ #include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+ #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+ #include "core_cm0.h"
+ #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+ #include "core_cm0plus.h"
+ #define ARM_MATH_CM0_FAMILY
+#else
+ #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"
+#endif
+
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+ /**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31 (0x100)
+#define DELTA_Q15 0x5
+#define INDEX_MASK 0x0000003F
+#ifndef PI
+#define PI 3.14159265358979f
+#endif
+
+ /**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define FAST_MATH_TABLE_SIZE 512
+#define FAST_MATH_Q31_SHIFT (32 - 10)
+#define FAST_MATH_Q15_SHIFT (16 - 10)
+#define CONTROLLER_Q31_SHIFT (32 - 9)
+#define TABLE_SIZE 256
+#define TABLE_SPACING_Q31 0x400000
+#define TABLE_SPACING_Q15 0x80
+
+ /**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+ /* 1.31(q31) Fixed value of 2/360 */
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+ /**
+ * @brief Macro for Unaligned Support
+ */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+ #define ALIGN4
+#else
+ #if defined (__GNUC__)
+ #define ALIGN4 __attribute__((aligned(4)))
+ #else
+ #define ALIGN4 __align(4)
+ #endif
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /**
+ * @brief Error status returned by some functions in the library.
+ */
+
+ typedef enum
+ {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+ } arm_status;
+
+ /**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+ typedef int8_t q7_t;
+
+ /**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+ typedef int16_t q15_t;
+
+ /**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+ typedef int32_t q31_t;
+
+ /**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+ typedef int64_t q63_t;
+
+ /**
+ * @brief 32-bit floating-point type definition.
+ */
+ typedef float float32_t;
+
+ /**
+ * @brief 64-bit floating-point type definition.
+ */
+ typedef double float64_t;
+
+ /**
+ * @brief definition to read/write two 16 bit values.
+ */
+#if defined __CC_ARM
+ #define __SIMD32_TYPE int32_t __packed
+ #define CMSIS_UNUSED __attribute__((unused))
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+
+#elif defined __GNUC__
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+
+#elif defined __ICCARM__
+ #define __SIMD32_TYPE int32_t __packed
+ #define CMSIS_UNUSED
+
+#elif defined __CSMC__
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED
+
+#elif defined __TASKING__
+ #define __SIMD32_TYPE __unaligned int32_t
+ #define CMSIS_UNUSED
+
+#else
+ #error Unknown compiler
+#endif
+
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))
+#define __SIMD64(addr) (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+ /**
+ * @brief definition to pack two 16 bit values.
+ */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
+
+#endif
+
+
+ /**
+ * @brief definition to pack four 8 bit values.
+ */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+
+#endif
+
+
+ /**
+ * @brief Clips Q63 to Q31 values.
+ */
+ static __INLINE q31_t clip_q63_to_q31(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+ }
+
+ /**
+ * @brief Clips Q63 to Q15 values.
+ */
+ static __INLINE q15_t clip_q63_to_q15(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+ }
+
+ /**
+ * @brief Clips Q31 to Q7 values.
+ */
+ static __INLINE q7_t clip_q31_to_q7(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+ }
+
+ /**
+ * @brief Clips Q31 to Q15 values.
+ */
+ static __INLINE q15_t clip_q31_to_q15(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+ }
+
+ /**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+
+ static __INLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+ {
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y)));
+ }
+
+/*
+ #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM )
+ #define __CLZ __clz
+ #endif
+ */
+/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) )
+ static __INLINE uint32_t __CLZ(
+ q31_t data);
+
+ static __INLINE uint32_t __CLZ(
+ q31_t data)
+ {
+ uint32_t count = 0;
+ uint32_t mask = 0x80000000;
+
+ while((data & mask) == 0)
+ {
+ count += 1u;
+ mask = mask >> 1u;
+ }
+
+ return (count);
+ }
+#endif
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+
+ static __INLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t * dst,
+ q31_t * pRecipTable)
+ {
+ q31_t out;
+ uint32_t tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if(in > 0)
+ {
+ signBits = ((uint32_t) (__CLZ( in) - 1));
+ }
+ else
+ {
+ signBits = ((uint32_t) (__CLZ(-in) - 1));
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 24);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0u; i < 2u; i++)
+ {
+ tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+ tempVal = 0x7FFFFFFFu - tempVal;
+ /* 1.31 with exp 1 */
+ /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+ out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1u);
+ }
+
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+ static __INLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t * dst,
+ q15_t * pRecipTable)
+ {
+ q15_t out = 0;
+ uint32_t tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if(in > 0)
+ {
+ signBits = ((uint32_t)(__CLZ( in) - 17));
+ }
+ else
+ {
+ signBits = ((uint32_t)(__CLZ(-in) - 17));
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 8);
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0u; i < 2u; i++)
+ {
+ tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFFu - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+ }
+
+
+ /*
+ * @brief C custom defined intrinisic function for only M0 processors
+ */
+#if defined(ARM_MATH_CM0_FAMILY)
+ static __INLINE q31_t __SSAT(
+ q31_t x,
+ uint32_t y)
+ {
+ int32_t posMax, negMin;
+ uint32_t i;
+
+ posMax = 1;
+ for (i = 0; i < (y - 1); i++)
+ {
+ posMax = posMax * 2;
+ }
+
+ if(x > 0)
+ {
+ posMax = (posMax - 1);
+
+ if(x > posMax)
+ {
+ x = posMax;
+ }
+ }
+ else
+ {
+ negMin = -posMax;
+
+ if(x < negMin)
+ {
+ x = negMin;
+ }
+ }
+ return (x);
+ }
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+ /*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+ /*
+ * @brief C custom defined QADD8 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QADD8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB8 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QSUB8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */
+ q31_t r = 0, s = 0;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHADD16 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SHADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB16 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSUB16 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SHSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QASX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHASX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SHASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSAX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSAX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SHSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSDX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMUSDX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+ /*
+ * @brief C custom defined SMUADX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMUADX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined QADD for M3 and M0 processors
+ */
+ static __INLINE int32_t __QADD(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB for M3 and M0 processors
+ */
+ static __INLINE int32_t __QSUB(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined SMLAD for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMLAD(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLADX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMLADX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLSDX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMLSDX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALD for M3 and M0 processors
+ */
+ static __INLINE uint64_t __SMLALD(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALDX for M3 and M0 processors
+ */
+ static __INLINE uint64_t __SMLALDX(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUAD for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMUAD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSD for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMUSD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SXTB16 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SXTB16(
+ uint32_t x)
+ {
+ return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+ ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));
+ }
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+ /**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q7;
+
+ /**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] S points to an instance of the Q7 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ */
+ void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] S points to an instance of the Q15 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+ * <code>numTaps</code> is not a supported value.
+ */
+ arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] S points to an instance of the Q31 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] S points to an instance of the floating-point FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_f32(
+ const arm_fir_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q15;
+
+ /**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q31;
+
+ /**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_casd_df1_inst_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f32;
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float64_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f64;
+
+ /**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q31;
+
+
+ /**
+ * @brief Floating-point matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Q31, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+
+ /**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+
+ /**
+ * @brief Q31 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix scaling.
+ * @param[in] pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData);
+
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData);
+
+
+ /**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+ typedef struct
+ {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+ q15_t A1;
+ q15_t A2;
+#else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+ typedef struct
+ {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+ typedef struct
+ {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_f32;
+
+
+
+ /**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ */
+ void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S);
+
+
+ /**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ */
+
+ void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S);
+
+
+ /**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the q15 PID Control structure
+ */
+ void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S);
+
+
+ /**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+ typedef struct
+ {
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
+ float32_t *pYData; /**< pointer to the table of Y values */
+ } arm_linear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q7;
+
+
+ /**
+ * @brief Q7 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+ void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q15_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+ const arm_cfft_instance_q15 * S,
+ q15_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+ const arm_cfft_instance_q31 * S,
+ q31_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_f32;
+
+ void arm_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q15;
+
+ arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+ /**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q31;
+
+ arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_f32;
+
+ arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+typedef struct
+ {
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
+ } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+ arm_rfft_fast_instance_f32 * S,
+ uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+ arm_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut,
+ uint8_t ifftFlag);
+
+ /**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ float32_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+ */
+ arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+
+ /**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ q31_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q31;
+
+
+ /**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q31 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ q15_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q15 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+
+ /**
+ * @brief Floating-point vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_f32(
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q7(
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q15(
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q31(
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+
+ /**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+
+ /**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q7(
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q15(
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q31(
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_f32(
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q7(
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q15(
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q31(
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR decimator.
+ * @param[in,out] S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+ arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+ arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q31(
+ arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+ arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+ } arm_fir_interpolate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+ arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+ arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+ arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+ } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+ /**
+ * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f64;
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_stereo_df2T_f32(
+ const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f64(
+ const arm_biquad_cascade_df2T_instance_f64 * S,
+ float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_stereo_df2T_init_f32(
+ arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f64(
+ arm_biquad_cascade_df2T_instance_f64 * S,
+ uint8_t numStages,
+ float64_t * pCoeffs,
+ float64_t * pState);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ */
+ void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+ } arm_lms_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q15;
+
+
+ /**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+ void arm_correlate_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+ void arm_correlate_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+ void arm_correlate_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+ void arm_correlate_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_correlate_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q7;
+
+
+ /**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cos output.
+ */
+ void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCosVal);
+
+
+ /**
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cosine output.
+ */
+ void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal);
+
+
+ /**
+ * @brief Floating-point complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the PID control data structure. <code>in</code>
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ * <pre>
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ * A0 = Kp + Ki + Kd
+ * A1 = (-Kp ) - (2 * Kd )
+ * A2 = Kd </pre>
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ */
+ static __INLINE float32_t arm_pid_f32(
+ arm_pid_instance_f32 * S,
+ float32_t in)
+ {
+ float32_t out;
+
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = (S->A0 * in) +
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @brief Process function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+ static __INLINE q31_t arm_pid_q31(
+ arm_pid_instance_q31 * S,
+ q31_t in)
+ {
+ q63_t acc;
+ q31_t out;
+
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31u);
+
+ /* out += y[n-1] */
+ out += S->state[2];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+
+ /**
+ * @brief Process function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+ static __INLINE q15_t arm_pid_q15(
+ arm_pid_instance_q15 * S,
+ q15_t in)
+ {
+ q63_t acc;
+ q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+ __SIMD32_TYPE *vstate;
+
+ /* Implementation of PID controller */
+
+ /* acc = A0 * x[n] */
+ acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ vstate = __SIMD32_CONST(S->state);
+ acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);
+#else
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0) * in;
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0];
+ acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+
+ /* saturate the output */
+ out = (q15_t) (__SSAT((acc >> 15), 16));
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+ /**
+ * @} end of PID group
+ */
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32 * src,
+ arm_matrix_instance_f32 * dst);
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f64(
+ const arm_matrix_instance_f64 * src,
+ arm_matrix_instance_f64 * dst);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+ * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+ * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+ * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+ * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup clarke
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate <code>a</code>
+ * @param[in] Ib input three-phase coordinate <code>b</code>
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ */
+ static __INLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+ }
+
+
+ /**
+ * @brief Clarke transform for Q31 version
+ * @param[in] Ia input three-phase coordinate <code>a</code>
+ * @param[in] Ib input three-phase coordinate <code>b</code>
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+ static __INLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+ }
+
+ /**
+ * @} end of clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q31(
+ q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+ * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Clarke transform
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate <code>a</code>
+ * @param[out] pIb points to output three-phase coordinate <code>b</code>
+ */
+ static __INLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
+ {
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+ }
+
+
+ /**
+ * @brief Inverse Clarke transform for Q31 version
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate <code>a</code>
+ * @param[out] pIb points to output three-phase coordinate <code>b</code>
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+ static __INLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+ }
+
+ /**
+ * @} end of inv_clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q15(
+ q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+ * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+ static __INLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+ }
+
+
+ /**
+ * @brief Park transform for Q31 version
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+ static __INLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+ }
+
+ /**
+ * @} end of park group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q7_to_float(
+ q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+ * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Park transform
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ */
+ static __INLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+ }
+
+
+ /**
+ * @brief Inverse Park transform for Q31 version
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+ static __INLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+ }
+
+ /**
+ * @} end of Inverse park group
+ */
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_float(
+ q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ * <pre>
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ * where x0, x1 are nearest values of input x
+ * y0, y1 are nearest values to output y
+ * </pre>
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+ * <code>x</code> is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+ /**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+ static __INLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32 * S,
+ float32_t x)
+ {
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t *pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (int32_t) ((x - S->x1) / xSpacing);
+
+ if(i < 0)
+ {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ }
+ else if((uint32_t)i >= S->nValues)
+ {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues - 1];
+ }
+ else
+ {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i + 1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+ }
+
+ /* returns output value */
+ return (y);
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q31 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q31 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ static __INLINE q31_t arm_linear_interp_q31(
+ q31_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (q31_t)0xFFF00000) >> 20);
+
+ if(index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1u);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ static __INLINE q15_t arm_linear_interp_q15(
+ q15_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (int32_t)0xFFF00000) >> 20);
+
+ if(index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (q15_t) (y >> 20);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+ static __INLINE q7_t arm_linear_interp_q7(
+ q7_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ uint32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ if (x < 0)
+ {
+ return (pYData[0]);
+ }
+ index = (x >> 20) & 0xfff;
+
+ if(index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (q7_t) (y >> 20);
+ }
+ }
+
+ /**
+ * @} end of LinearInterpolate group
+ */
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+ float32_t arm_sin_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q31_t arm_sin_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q15_t arm_sin_q15(
+ q15_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+ float32_t arm_cos_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q31_t arm_cos_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q15_t arm_cos_q15(
+ q15_t x);
+
+
+ /**
+ * @ingroup groupFastMath
+ */
+
+
+ /**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ * <pre>
+ * x1 = x0 - f(x0)/f'(x0)
+ * </pre>
+ * where <code>x1</code> is the current estimate,
+ * <code>x0</code> is the previous estimate, and
+ * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+ * For the square root function, the algorithm reduces to:
+ * <pre>
+ * x0 = in/2 [initial guess]
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]
+ * </pre>
+ */
+
+
+ /**
+ * @addtogroup SQRT
+ * @{
+ */
+
+ /**
+ * @brief Floating-point square root function.
+ * @param[in] in input value.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+ static __INLINE arm_status arm_sqrt_f32(
+ float32_t in,
+ float32_t * pOut)
+ {
+ if(in >= 0.0f)
+ {
+
+#if (__FPU_USED == 1) && defined ( __CC_ARM )
+ *pOut = __sqrtf(in);
+#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+ *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined(__GNUC__)
+ *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
+ __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+#else
+ *pOut = sqrtf(in);
+#endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else
+ {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+ }
+
+
+ /**
+ * @brief Q31 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut);
+
+
+ /**
+ * @brief Q15 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut);
+
+ /**
+ * @} end of SQRT group
+ */
+
+
+ /**
+ * @brief floating-point Circular write function.
+ */
+ static __INLINE void arm_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+
+ /**
+ * @brief floating-point Circular Read function.
+ */
+ static __INLINE void arm_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (int32_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular write function.
+ */
+ static __INLINE void arm_circularWrite_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q15_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular Read function.
+ */
+ static __INLINE void arm_circularRead_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q15_t * dst,
+ q15_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q15_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular write function.
+ */
+ static __INLINE void arm_circularWrite_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q7_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular Read function.
+ */
+ static __INLINE void arm_circularRead_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q7_t * dst,
+ q7_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q7_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Floating-point complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+
+ /**
+ * @brief Q31 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+
+ /**
+ * @brief Floating-point complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+
+ /**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q15(
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q31(
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_f32(
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
+
+
+ /**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[in] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q31(
+ float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q15(
+ float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q7(
+ float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q15(
+ q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q7(
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_float(
+ q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q31(
+ q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q7(
+ q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * <b>Algorithm</b>
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ * <pre>
+ * typedef struct
+ * {
+ * uint16_t numRows;
+ * uint16_t numCols;
+ * float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ * </pre>
+ *
+ * \par
+ * where <code>numRows</code> specifies the number of rows in the table;
+ * <code>numCols</code> specifies the number of columns in the table;
+ * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+ * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+ *
+ * \par
+ * Let <code>(x, y)</code> specify the desired interpolation point. Then define:
+ * <pre>
+ * XF = floor(x)
+ * YF = floor(y)
+ * </pre>
+ * \par
+ * The interpolated output point is computed as:
+ * <pre>
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ * </pre>
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+ /**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+
+ /**
+ *
+ * @brief Floating-point bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate.
+ * @param[in] Y interpolation coordinate.
+ * @return out interpolated value.
+ */
+ static __INLINE float32_t arm_bilinear_interp_f32(
+ const arm_bilinear_interp_instance_f32 * S,
+ float32_t X,
+ float32_t Y)
+ {
+ float32_t out;
+ float32_t f00, f01, f10, f11;
+ float32_t *pData = S->pData;
+ int32_t xIndex, yIndex, index;
+ float32_t xdiff, ydiff;
+ float32_t b1, b2, b3, b4;
+
+ xIndex = (int32_t) X;
+ yIndex = (int32_t) Y;
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* Calculation of index for two nearest points in X-direction */
+ index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+ /* Read two nearest points in X-direction */
+ f00 = pData[index];
+ f01 = pData[index + 1];
+
+ /* Calculation of index for two nearest points in Y-direction */
+ index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+ /* Read two nearest points in Y-direction */
+ f10 = pData[index];
+ f11 = pData[index + 1];
+
+ /* Calculation of intermediate values */
+ b1 = f00;
+ b2 = f01 - f00;
+ b3 = f10 - f00;
+ b4 = f00 - f01 - f10 + f11;
+
+ /* Calculation of fractional part in X */
+ xdiff = X - xIndex;
+
+ /* Calculation of fractional part in Y */
+ ydiff = Y - yIndex;
+
+ /* Calculation of bi-linear interpolated output */
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+ /* return to application */
+ return (out);
+ }
+
+
+ /**
+ *
+ * @brief Q31 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ static __INLINE q31_t arm_bilinear_interp_q31(
+ arm_bilinear_interp_instance_q31 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q31_t out; /* Temporary output */
+ q31_t acc = 0; /* output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q31_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q31_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* shift left xfract by 11 to keep 1.31 format */
+ xfract = (X & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + (int32_t)nCols * (cI) ];
+ x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* shift left yfract by 11 to keep 1.31 format */
+ yfract = (Y & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];
+ y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* Convert acc to 1.31(q31) format */
+ return ((q31_t)(acc << 2));
+ }
+
+
+ /**
+ * @brief Q15 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ static __INLINE q15_t arm_bilinear_interp_q15(
+ arm_bilinear_interp_instance_q15 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q15_t x1, x2, y1, y2; /* Nearest output values */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ int32_t rI, cI; /* Row and column indices */
+ q15_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+ acc = ((q63_t) out * (0xFFFFF - yfract));
+
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+ acc += ((q63_t) out * (xfract));
+
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* acc is in 13.51 format and down shift acc by 36 times */
+ /* Convert out to 1.15 format */
+ return ((q15_t)(acc >> 36));
+ }
+
+
+ /**
+ * @brief Q7 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ static __INLINE q7_t arm_bilinear_interp_q7(
+ arm_bilinear_interp_instance_q7 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q7_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q7_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+ out = ((x1 * (0xFFFFF - xfract)));
+ acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
+ out = ((x2 * (0xFFFFF - yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y1 * (0xFFFFF - xfract)));
+ acc += (((q63_t) out * (yfract)));
+
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y2 * (yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+ return ((q7_t)(acc >> 40));
+ }
+
+ /**
+ * @} end of BilinearInterpolate group
+ */
+
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+ a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+ a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+ a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM )
+ /* Enter low optimization region - place directly above function definition */
+ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("push") \
+ _Pragma ("O1")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+ #define LOW_OPTIMIZATION_EXIT \
+ _Pragma ("pop")
+ #else
+ #define LOW_OPTIMIZATION_EXIT
+ #endif
+
+ /* Enter low optimization region - place directly above function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+ #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__)
+ /* Enter low optimization region - place directly above function definition */
+ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define LOW_OPTIMIZATION_EXIT
+
+ /* Enter low optimization region - place directly above function definition */
+ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__CSMC__)
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__TASKING__)
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/third_party/nxp/JN5189DK6/CMSIS/Include/cmsis_armcc.h b/third_party/nxp/JN5189DK6/CMSIS/Include/cmsis_armcc.h
new file mode 100755
index 0000000..74c49c6
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/CMSIS/Include/cmsis_armcc.h
@@ -0,0 +1,734 @@
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+
+#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() do {\
+ __schedule_barrier();\
+ __isb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+ __schedule_barrier();\
+ __dsb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXB(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXH(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXW(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
+
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
+
+#endif /* (__CORTEX_M >= 0x04) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/third_party/nxp/JN5189DK6/CMSIS/Include/cmsis_armcc_V6.h b/third_party/nxp/JN5189DK6/CMSIS/Include/cmsis_armcc_V6.h
new file mode 100755
index 0000000..cd13240
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/CMSIS/Include/cmsis_armcc_V6.h
@@ -0,0 +1,1800 @@
+/**************************************************************************//**
+ * @file cmsis_armcc_V6.h
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_ARMCC_V6_H
+#define __CMSIS_ARMCC_V6_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get IPSR Register (non-secure)
+ \details Returns the content of the non-secure IPSR Register when in secure state.
+ \return IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get APSR Register (non-secure)
+ \details Returns the content of the non-secure APSR Register when in secure state.
+ \return APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get xPSR Register (non-secure)
+ \details Returns the content of the non-secure xPSR Register when in secure state.
+ \return xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp");
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp");
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Base Priority with condition (non_secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value)
+{
+ __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+
+#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */
+
+
+#if (__ARM_ARCH_8M__ == 1U)
+
+/**
+ \brief Get Process Stack Pointer Limit
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* (__ARM_ARCH_8M__ == 1U) */
+
+
+#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */
+
+/**
+ \brief Get FPSCR
+ \details eturns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#define __get_FPSCR __builtin_arm_get_fpscr
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ uint32_t result;
+
+ __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+#endif
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get FPSCR (non-secure)
+ \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state.
+ \return Floating Point Status/Control register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ uint32_t result;
+
+ __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+#endif
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#define __set_FPSCR __builtin_arm_set_fpscr
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+#endif
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set FPSCR (non-secure)
+ \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+#endif
+
+#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF);
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF);
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF);
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __builtin_bswap32
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+ /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+ int32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+ /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return(result);
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __builtin_clz
+
+
+#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+/*#define __SSAT __builtin_arm_ssat*/
+#define __SSAT(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+#if 0
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+#endif
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */
+
+
+#if (__ARM_ARCH_8M__ == 1U)
+
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* (__ARM_ARCH_8M__ == 1U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1U) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_V6_H */
diff --git a/third_party/nxp/JN5189DK6/CMSIS/Include/cmsis_gcc.h b/third_party/nxp/JN5189DK6/CMSIS/Include/cmsis_gcc.h
new file mode 100755
index 0000000..bb89fbb
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/CMSIS/Include/cmsis_gcc.h
@@ -0,0 +1,1373 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (__CORTEX_M >= 0x03U)
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03U) */
+
+
+#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ uint32_t result;
+
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (short)__builtin_bswap16(value);
+#else
+ int32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return(result);
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __builtin_clz
+
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x04) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* __CMSIS_GCC_H */
diff --git a/third_party/nxp/JN5189DK6/CMSIS/Include/core_cm0.h b/third_party/nxp/JN5189DK6/CMSIS/Include/core_cm0.h
new file mode 100755
index 0000000..711dad5
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/CMSIS/Include/core_cm0.h
@@ -0,0 +1,798 @@
+/**************************************************************************//**
+ * @file core_cm0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M0
+ @{
+ */
+
+/* CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0_REV
+ #define __CM0_REV 0x0000U
+ #warning "__CM0_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/third_party/nxp/JN5189DK6/CMSIS/Include/core_cm0plus.h b/third_party/nxp/JN5189DK6/CMSIS/Include/core_cm0plus.h
new file mode 100755
index 0000000..b04aa39
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/CMSIS/Include/core_cm0plus.h
@@ -0,0 +1,914 @@
+/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex-M0+
+ @{
+ */
+
+/* CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+ __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0PLUS_REV
+ #define __CM0PLUS_REV 0x0000U
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0+ header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/third_party/nxp/JN5189DK6/CMSIS/Include/core_cm3.h b/third_party/nxp/JN5189DK6/CMSIS/Include/core_cm3.h
new file mode 100755
index 0000000..b4ac4c7
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/CMSIS/Include/core_cm3.h
@@ -0,0 +1,1763 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M3
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03U) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200U
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201U) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U))
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in NVIC and returns the active bit.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/third_party/nxp/JN5189DK6/CMSIS/Include/core_cm4.h b/third_party/nxp/JN5189DK6/CMSIS/Include/core_cm4.h
new file mode 100755
index 0000000..dc840eb
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/CMSIS/Include/core_cm4.h
@@ -0,0 +1,1937 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M4
+ @{
+ */
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x04U) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000U
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1U)
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in NVIC and returns the active bit.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/third_party/nxp/JN5189DK6/CMSIS/Include/core_cm7.h b/third_party/nxp/JN5189DK6/CMSIS/Include/core_cm7.h
new file mode 100755
index 0000000..3b7530a
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/CMSIS/Include/core_cm7.h
@@ -0,0 +1,2512 @@
+/**************************************************************************//**
+ * @file core_cm7.h
+ * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M7
+ @{
+ */
+
+/* CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+ __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x07U) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM7_REV
+ #define __CM7_REV 0x0000U
+ #warning "__CM7_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ICACHE_PRESENT
+ #define __ICACHE_PRESENT 0U
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DCACHE_PRESENT
+ #define __DCACHE_PRESENT 0U
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DTCM_PRESENT
+ #define __DTCM_PRESENT 0U
+ #warning "__DTCM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[1U];
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED3[93U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED3[981U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1U)
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in NVIC and returns the active bit.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = SCB->MVFR0;
+ if ((mvfr0 & 0x00000FF0UL) == 0x220UL)
+ {
+ return 2UL; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & 0x00000FF0UL) == 0x020UL)
+ {
+ return 1UL; /* Single precision FPU */
+ }
+ else
+ {
+ return 0UL; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## Cache functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions
+ \brief Functions that configure Instruction and Data cache.
+ @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
+
+
+/**
+ \brief Enable I-Cache
+ \details Turns on I-Cache
+ */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+ #if (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable I-Cache
+ \details Turns off I-Cache
+ */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+ #if (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate I-Cache
+ \details Invalidates I-Cache
+ */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+ #if (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL;
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Enable D-Cache
+ \details Turns on D-Cache
+ */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways--);
+ } while(sets--);
+ __DSB();
+
+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable D-Cache
+ \details Turns off D-Cache
+ */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate D-Cache
+ \details Invalidates D-Cache
+ */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean D-Cache
+ \details Cleans D-Cache
+ */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+ ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean & Invalidate D-Cache
+ \details Cleans and Invalidates D-Cache
+ */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Invalidate by address
+ \details Invalidates D-Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t)addr;
+ int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCIMVAC = op_addr;
+ op_addr += linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean by address
+ \details Cleans D-Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if (__DCACHE_PRESENT == 1)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t) addr;
+ int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCCMVAC = op_addr;
+ op_addr += linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean and Invalidate by address
+ \details Cleans and invalidates D_Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t) addr;
+ int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCCIMVAC = op_addr;
+ op_addr += linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/third_party/nxp/JN5189DK6/CMSIS/Include/core_cmFunc.h b/third_party/nxp/JN5189DK6/CMSIS/Include/core_cmFunc.h
new file mode 100755
index 0000000..652a48a
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/CMSIS/Include/core_cmFunc.h
@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+ #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+ #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+ #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/third_party/nxp/JN5189DK6/CMSIS/Include/core_cmInstr.h b/third_party/nxp/JN5189DK6/CMSIS/Include/core_cmInstr.h
new file mode 100755
index 0000000..f474b0e
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/CMSIS/Include/core_cmInstr.h
@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+ #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+ #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+ #include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/third_party/nxp/JN5189DK6/CMSIS/Include/core_cmSimd.h b/third_party/nxp/JN5189DK6/CMSIS/Include/core_cmSimd.h
new file mode 100755
index 0000000..66bf5c2
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/CMSIS/Include/core_cmSimd.h
@@ -0,0 +1,96 @@
+/**************************************************************************//**
+ * @file core_cmSimd.h
+ * @brief CMSIS Cortex-M SIMD Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+ #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+ #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+ #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */
diff --git a/third_party/nxp/JN5189DK6/CMSIS/Include/core_sc000.h b/third_party/nxp/JN5189DK6/CMSIS/Include/core_sc000.h
new file mode 100755
index 0000000..514dbd8
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/CMSIS/Include/core_sc000.h
@@ -0,0 +1,926 @@
+/**************************************************************************//**
+ * @file core_sc000.h
+ * @brief CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup SC000
+ @{
+ */
+
+/* CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+ __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC (000U) /*!< Cortex secure core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __SC000_REV
+ #define __SC000_REV 0x0000U
+ #warning "__SC000_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ uint32_t RESERVED1[154U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the SC000 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of SC000 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/third_party/nxp/JN5189DK6/CMSIS/Include/core_sc300.h b/third_party/nxp/JN5189DK6/CMSIS/Include/core_sc300.h
new file mode 100755
index 0000000..8bd18aa
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/CMSIS/Include/core_sc300.h
@@ -0,0 +1,1745 @@
+/**************************************************************************//**
+ * @file core_sc300.h
+ * @brief CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup SC3000
+ @{
+ */
+
+/* CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+ __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC (300U) /*!< Cortex secure core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __SC300_REV
+ #define __SC300_REV 0x0000U
+ #warning "__SC300_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED1[129U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ uint32_t RESERVED1[1U];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in NVIC and returns the active bit.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/third_party/nxp/JN5189/dk6_jn5180/board.c b/third_party/nxp/JN5189DK6/boards/jn5189dk6/wireless_examples/openthread/enablement/board.c
similarity index 100%
rename from third_party/nxp/JN5189/dk6_jn5180/board.c
rename to third_party/nxp/JN5189DK6/boards/jn5189dk6/wireless_examples/openthread/enablement/board.c
diff --git a/third_party/nxp/JN5189/dk6_jn5180/board.h b/third_party/nxp/JN5189DK6/boards/jn5189dk6/wireless_examples/openthread/enablement/board.h
similarity index 100%
rename from third_party/nxp/JN5189/dk6_jn5180/board.h
rename to third_party/nxp/JN5189DK6/boards/jn5189dk6/wireless_examples/openthread/enablement/board.h
diff --git a/third_party/nxp/JN5189/dk6_jn5180/clock_config.c b/third_party/nxp/JN5189DK6/boards/jn5189dk6/wireless_examples/openthread/enablement/clock_config.c
similarity index 98%
rename from third_party/nxp/JN5189/dk6_jn5180/clock_config.c
rename to third_party/nxp/JN5189DK6/boards/jn5189dk6/wireless_examples/openthread/enablement/clock_config.c
index b9dca12..1a4ca32 100755
--- a/third_party/nxp/JN5189/dk6_jn5180/clock_config.c
+++ b/third_party/nxp/JN5189DK6/boards/jn5189dk6/wireless_examples/openthread/enablement/clock_config.c
@@ -8,8 +8,6 @@
#include "fsl_common.h"
#include "clock_config.h"
-#include "system_JN5189.h"
-
/*******************************************************************************
* Definitions
******************************************************************************/
diff --git a/third_party/nxp/JN5189/dk6_jn5180/clock_config.h b/third_party/nxp/JN5189DK6/boards/jn5189dk6/wireless_examples/openthread/enablement/clock_config.h
similarity index 100%
rename from third_party/nxp/JN5189/dk6_jn5180/clock_config.h
rename to third_party/nxp/JN5189DK6/boards/jn5189dk6/wireless_examples/openthread/enablement/clock_config.h
diff --git a/third_party/nxp/JN5189/dk6_jn5180/pin_mux.c b/third_party/nxp/JN5189DK6/boards/jn5189dk6/wireless_examples/openthread/enablement/pin_mux.c
similarity index 100%
rename from third_party/nxp/JN5189/dk6_jn5180/pin_mux.c
rename to third_party/nxp/JN5189DK6/boards/jn5189dk6/wireless_examples/openthread/enablement/pin_mux.c
diff --git a/third_party/nxp/JN5189/dk6_jn5180/pin_mux.h b/third_party/nxp/JN5189DK6/boards/jn5189dk6/wireless_examples/openthread/enablement/pin_mux.h
similarity index 100%
rename from third_party/nxp/JN5189/dk6_jn5180/pin_mux.h
rename to third_party/nxp/JN5189DK6/boards/jn5189dk6/wireless_examples/openthread/enablement/pin_mux.h
diff --git a/third_party/nxp/JN5189DK6/components/serial_manager/serial_manager.c b/third_party/nxp/JN5189DK6/components/serial_manager/serial_manager.c
new file mode 100755
index 0000000..42dc0a4
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/components/serial_manager/serial_manager.c
@@ -0,0 +1,1326 @@
+/*
+ * Copyright 2018-2019 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include <string.h>
+
+#include "serial_manager.h"
+#include "serial_port_internal.h"
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+#include "generic_list.h"
+
+/*
+ * The OSA_USED macro can only be defined when the OSA component is used.
+ * If the source code of the OSA component does not exist, the OSA_USED cannot be defined.
+ * OR, If OSA component is not added into project event the OSA source code exists, the OSA_USED
+ * also cannot be defined.
+ * The source code path of the OSA component is <MCUXpresso_SDK>/components/osa.
+ *
+ */
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+#include "common_task.h"
+#else
+#include "fsl_os_abstraction.h"
+#endif
+
+#endif
+
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#ifndef NDEBUG
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
+#undef assert
+#define assert(n)
+#endif
+#endif
+
+#define SERIAL_EVENT_DATA_RECEIVED (1U << 0)
+#define SERIAL_EVENT_DATA_SENT (1U << 1)
+
+#define SERIAL_MANAGER_WRITE_TAG 0xAABB5754U
+#define SERIAL_MANAGER_READ_TAG 0xBBAA5244U
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+typedef enum _serial_manager_transmission_mode
+{
+ kSerialManager_TransmissionBlocking = 0x0U, /*!< Blocking transmission*/
+ kSerialManager_TransmissionNonBlocking = 0x1U, /*!< None blocking transmission*/
+} serial_manager_transmission_mode_t;
+
+/* TX transfer structure */
+typedef struct _serial_manager_transfer
+{
+ uint8_t *buffer;
+ volatile uint32_t length;
+ volatile uint32_t soFar;
+ serial_manager_transmission_mode_t mode;
+ serial_manager_status_t status;
+} serial_manager_transfer_t;
+#endif
+
+/* write handle structure */
+typedef struct _serial_manager_send_handle
+{
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ list_element_t link; /*!< list element of the link */
+ serial_manager_transfer_t transfer;
+#endif
+ struct _serial_manager_handle *serialManagerHandle;
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ serial_manager_callback_t callback;
+ void *callbackParam;
+ uint32_t tag;
+#endif
+} serial_manager_write_handle_t;
+
+typedef serial_manager_write_handle_t serial_manager_read_handle_t;
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+/* receive state structure */
+typedef struct _serial_manager_read_ring_buffer
+{
+ uint8_t *ringBuffer;
+ uint32_t ringBufferSize;
+ volatile uint32_t ringHead;
+ volatile uint32_t ringTail;
+} serial_manager_read_ring_buffer_t;
+#endif
+
+#if defined(__CC_ARM)
+#pragma anon_unions
+#endif
+/* The serial manager handle structure */
+typedef struct _serial_manager_handle
+{
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ list_label_t runningWriteHandleHead; /*!< The queue of running write handle */
+ list_label_t completedWriteHandleHead; /*!< The queue of completed write handle */
+#endif
+ serial_manager_read_handle_t *volatile openedReadHandleHead;
+ volatile uint32_t openedWriteHandleCount;
+ union
+ {
+ uint8_t lowLevelhandleBuffer[1];
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ uint8_t uartHandleBuffer[SERIAL_PORT_UART_HANDLE_SIZE];
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ uint8_t usbcdcHandleBuffer[SERIAL_PORT_USB_CDC_HANDLE_SIZE];
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ uint8_t swoHandleBuffer[SERIAL_PORT_SWO_HANDLE_SIZE];
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ uint8_t usbcdcVirtualHandleBuffer[SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE];
+#endif
+ };
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ serial_manager_read_ring_buffer_t ringBuffer;
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+ common_task_message_t commontaskMsg;
+#else
+ uint8_t event[OSA_EVENT_HANDLE_SIZE]; /*!< Event instance */
+ uint8_t taskId[OSA_TASK_HANDLE_SIZE]; /*!< Task handle */
+#endif
+
+#endif
+
+#endif
+
+ serial_port_type_t type;
+} serial_manager_handle_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+static void SerialManager_Task(void *param);
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+
+#else
+ /*
+ * \brief Defines the serial manager task's stack
+ */
+OSA_TASK_DEFINE(SerialManager_Task, SERIAL_MANAGER_TASK_PRIORITY, 1, SERIAL_MANAGER_TASK_STACK_SIZE, false);
+#endif
+
+#endif
+
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+static void SerialManager_AddTail(list_label_t *queue, serial_manager_write_handle_t *node)
+{
+ (void)LIST_AddTail(queue, &node->link);
+}
+
+static void SerialManager_RemoveHead(list_label_t *queue)
+{
+ (void)LIST_RemoveHead(queue);
+}
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_t *handle)
+{
+ serial_manager_status_t status = kStatus_SerialManager_Error;
+ serial_manager_write_handle_t *writeHandle =
+ (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->runningWriteHandleHead);
+
+ if (writeHandle != NULL)
+ {
+ switch (handle->type)
+ {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ case kSerialPort_Uart:
+ status = Serial_UartWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ writeHandle->transfer.buffer, writeHandle->transfer.length);
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ case kSerialPort_UsbCdc:
+ status = Serial_UsbCdcWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ writeHandle->transfer.buffer, writeHandle->transfer.length);
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ case kSerialPort_Swo:
+ status = Serial_SwoWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ writeHandle->transfer.buffer, writeHandle->transfer.length);
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ case kSerialPort_UsbCdcVirtual:
+ status = Serial_UsbCdcVirtualWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ writeHandle->transfer.buffer, writeHandle->transfer.length);
+ break;
+#endif
+ default:
+ status = kStatus_SerialManager_Error;
+ break;
+ }
+ }
+ return status;
+}
+
+static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_t *handle,
+ serial_manager_read_handle_t *readHandle,
+ uint8_t *buffer,
+ uint32_t length)
+{
+ serial_manager_status_t status = kStatus_SerialManager_Error;
+
+ if (readHandle != NULL)
+ {
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ if (handle->type == kSerialPort_UsbCdc)
+ {
+ status = Serial_UsbCdcRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ }
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ if (handle->type == kSerialPort_UsbCdcVirtual)
+ {
+ status = Serial_UsbCdcVirtualRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ }
+#endif
+ }
+ return status;
+}
+
+#else
+
+static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_t *handle,
+ serial_manager_write_handle_t *writeHandle,
+ uint8_t *buffer,
+ uint32_t length)
+{
+ serial_manager_status_t status = kStatus_SerialManager_Error;
+
+ if (writeHandle != NULL)
+ {
+ switch (handle->type)
+ {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ case kSerialPort_Uart:
+ status = Serial_UartWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ case kSerialPort_UsbCdc:
+ status = Serial_UsbCdcWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ case kSerialPort_Swo:
+ status = Serial_SwoWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ case kSerialPort_UsbCdcVirtual:
+ status = Serial_UsbCdcVirtualWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ break;
+#endif
+ default:
+ status = kStatus_SerialManager_Error;
+ break;
+ }
+ }
+ return status;
+}
+
+static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_t *handle,
+ serial_manager_read_handle_t *readHandle,
+ uint8_t *buffer,
+ uint32_t length)
+{
+ serial_manager_status_t status = kStatus_SerialManager_Error;
+
+ if (readHandle != NULL)
+ {
+ switch (handle->type)
+ {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ case kSerialPort_Uart:
+ status = Serial_UartRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ case kSerialPort_UsbCdc:
+ status = Serial_UsbCdcRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ case kSerialPort_Swo:
+ status = Serial_SwoRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ case kSerialPort_UsbCdcVirtual:
+ status = Serial_UsbCdcVirtualRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ break;
+#endif
+ default:
+ status = kStatus_SerialManager_Error;
+ break;
+ }
+ }
+ return status;
+}
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+static void SerialManager_IsrFunction(serial_manager_handle_t *handle)
+{
+ uint32_t regPrimask = DisableGlobalIRQ();
+ switch (handle->type)
+ {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ case kSerialPort_Uart:
+ Serial_UartIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ case kSerialPort_UsbCdc:
+ Serial_UsbCdcIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ case kSerialPort_Swo:
+ Serial_SwoIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ case kSerialPort_UsbCdcVirtual:
+ Serial_UsbCdcVirtualIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+ default:
+ /*MISRA rule 16.4*/
+ break;
+ }
+ EnableGlobalIRQ(regPrimask);
+}
+
+static void SerialManager_Task(void *param)
+{
+ serial_manager_handle_t *handle = (serial_manager_handle_t *)param;
+ serial_manager_write_handle_t *serialWriteHandle;
+ serial_manager_read_handle_t *serialReadHandle;
+ uint32_t primask;
+ serial_manager_callback_message_t msg;
+
+ if (NULL != handle)
+ {
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+#else
+ osa_event_flags_t ev = 0;
+
+ do
+ {
+ if (KOSA_StatusSuccess ==
+ OSA_EventWait((osa_event_handle_t)handle->event, osaEventFlagsAll_c, false, osaWaitForever_c, &ev))
+ {
+ if (ev & SERIAL_EVENT_DATA_SENT)
+#endif
+
+#endif
+ {
+ serialWriteHandle =
+ (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->completedWriteHandleHead);
+ while (NULL != serialWriteHandle)
+ {
+ SerialManager_RemoveHead(&handle->completedWriteHandleHead);
+ msg.buffer = serialWriteHandle->transfer.buffer;
+ msg.length = serialWriteHandle->transfer.soFar;
+ serialWriteHandle->transfer.buffer = NULL;
+ if (serialWriteHandle->callback != NULL)
+ {
+ serialWriteHandle->callback(serialWriteHandle->callbackParam, &msg,
+ serialWriteHandle->transfer.status);
+ }
+ serialWriteHandle =
+ (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->completedWriteHandleHead);
+ }
+ }
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+#else
+ if (ev & SERIAL_EVENT_DATA_RECEIVED)
+#endif
+
+#endif
+ {
+ primask = DisableGlobalIRQ();
+ serialReadHandle = handle->openedReadHandleHead;
+ EnableGlobalIRQ(primask);
+
+ if (serialReadHandle != NULL)
+ {
+ if (serialReadHandle->transfer.buffer != NULL)
+ {
+ if (serialReadHandle->transfer.soFar >= serialReadHandle->transfer.length)
+ {
+ msg.buffer = serialReadHandle->transfer.buffer;
+ msg.length = serialReadHandle->transfer.soFar;
+ serialReadHandle->transfer.buffer = NULL;
+ if (serialReadHandle->callback != NULL)
+ {
+ serialReadHandle->callback(serialReadHandle->callbackParam, &msg,
+ serialReadHandle->transfer.status);
+ }
+ }
+ }
+ }
+ }
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+#else
+ }
+ } while (gUseRtos_c);
+#endif
+
+#endif
+ }
+}
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+static void SerialManager_TxCallback(void *callbackParam,
+ serial_manager_callback_message_t *message,
+ serial_manager_status_t status)
+{
+ serial_manager_handle_t *handle;
+ serial_manager_write_handle_t *writeHandle;
+
+ assert(callbackParam);
+ assert(message);
+
+ handle = (serial_manager_handle_t *)callbackParam;
+
+ writeHandle = (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->runningWriteHandleHead);
+
+ if (NULL != writeHandle)
+ {
+ SerialManager_RemoveHead(&handle->runningWriteHandleHead);
+ (void)SerialManager_StartWriting(handle);
+ writeHandle->transfer.soFar = message->length;
+ writeHandle->transfer.status = status;
+ if (kSerialManager_TransmissionNonBlocking == writeHandle->transfer.mode)
+ {
+ SerialManager_AddTail(&handle->completedWriteHandleHead, writeHandle);
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+ handle->commontaskMsg.callback = SerialManager_Task;
+ handle->commontaskMsg.callbackParam = handle;
+ COMMON_TASK_post_message(&handle->commontaskMsg);
+#else
+ (void)OSA_EventSet((osa_event_handle_t)handle->event, SERIAL_EVENT_DATA_SENT);
+#endif
+
+#else
+ SerialManager_Task(handle);
+#endif
+ }
+ else
+ {
+ writeHandle->transfer.buffer = NULL;
+ }
+ }
+}
+
+static void SerialManager_RxCallback(void *callbackParam,
+ serial_manager_callback_message_t *message,
+ serial_manager_status_t status)
+{
+ serial_manager_handle_t *handle;
+ uint32_t ringBufferLength;
+ uint32_t primask;
+
+ assert(callbackParam);
+ assert(message);
+
+ handle = (serial_manager_handle_t *)callbackParam;
+
+ status = kStatus_SerialManager_Notify;
+
+ for (uint32_t i = 0; i < message->length; i++)
+ {
+ handle->ringBuffer.ringBuffer[handle->ringBuffer.ringHead++] = message->buffer[i];
+ if (handle->ringBuffer.ringHead >= handle->ringBuffer.ringBufferSize)
+ {
+ handle->ringBuffer.ringHead = 0U;
+ }
+ if (handle->ringBuffer.ringHead == handle->ringBuffer.ringTail)
+ {
+ status = kStatus_SerialManager_RingBufferOverflow;
+ handle->ringBuffer.ringTail++;
+ if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize)
+ {
+ handle->ringBuffer.ringTail = 0U;
+ }
+ }
+ }
+
+ ringBufferLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail;
+ ringBufferLength = ringBufferLength % handle->ringBuffer.ringBufferSize;
+
+ primask = DisableGlobalIRQ();
+ if ((handle->openedReadHandleHead != NULL) && (handle->openedReadHandleHead->transfer.buffer != NULL))
+ {
+ if (handle->openedReadHandleHead->transfer.length > handle->openedReadHandleHead->transfer.soFar)
+ {
+ uint32_t remainLength =
+ handle->openedReadHandleHead->transfer.length - handle->openedReadHandleHead->transfer.soFar;
+ for (uint32_t i = 0; i < MIN(ringBufferLength, remainLength); i++)
+ {
+ handle->openedReadHandleHead->transfer.buffer[handle->openedReadHandleHead->transfer.soFar] =
+ handle->ringBuffer.ringBuffer[handle->ringBuffer.ringTail];
+ handle->ringBuffer.ringTail++;
+ handle->openedReadHandleHead->transfer.soFar++;
+ if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize)
+ {
+ handle->ringBuffer.ringTail = 0U;
+ }
+ }
+ ringBufferLength = ringBufferLength - MIN(ringBufferLength, remainLength);
+ }
+
+ if (handle->openedReadHandleHead->transfer.length > handle->openedReadHandleHead->transfer.soFar)
+ {
+ }
+ else
+ {
+ if (kSerialManager_TransmissionBlocking == handle->openedReadHandleHead->transfer.mode)
+ {
+ handle->openedReadHandleHead->transfer.buffer = NULL;
+ }
+ else
+ {
+ handle->openedReadHandleHead->transfer.status = kStatus_SerialManager_Success;
+
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+ handle->commontaskMsg.callback = SerialManager_Task;
+ handle->commontaskMsg.callbackParam = handle;
+ COMMON_TASK_post_message(&handle->commontaskMsg);
+#else
+ (void)OSA_EventSet((osa_event_handle_t)handle->event, SERIAL_EVENT_DATA_RECEIVED);
+#endif
+
+#else
+ SerialManager_Task(handle);
+#endif
+ }
+ }
+ }
+
+ if (ringBufferLength != 0U)
+ {
+ message->buffer = NULL;
+ message->length = ringBufferLength;
+ if ((NULL != handle->openedReadHandleHead) && (NULL != handle->openedReadHandleHead->callback))
+ {
+ handle->openedReadHandleHead->callback(handle->openedReadHandleHead->callbackParam, message, status);
+ }
+ }
+
+ ringBufferLength = handle->ringBuffer.ringBufferSize - 1U - ringBufferLength;
+
+ if (NULL != handle->openedReadHandleHead)
+ {
+ (void)SerialManager_StartReading(handle, handle->openedReadHandleHead, NULL, ringBufferLength);
+ }
+ EnableGlobalIRQ(primask);
+}
+
+static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHandle,
+ uint8_t *buffer,
+ uint32_t length,
+ serial_manager_transmission_mode_t mode)
+{
+ serial_manager_write_handle_t *serialWriteHandle;
+ serial_manager_handle_t *handle;
+ serial_manager_status_t status = kStatus_SerialManager_Success;
+ uint32_t primask;
+ uint8_t isEmpty = 0U;
+
+ assert(writeHandle);
+ assert(buffer);
+ assert(length);
+
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
+ handle = serialWriteHandle->serialManagerHandle;
+
+ assert(handle);
+ assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag);
+ assert(!((kSerialManager_TransmissionNonBlocking == mode) && (NULL == serialWriteHandle->callback)));
+
+ primask = DisableGlobalIRQ();
+ if (serialWriteHandle->transfer.buffer != NULL)
+ {
+ EnableGlobalIRQ(primask);
+ return kStatus_SerialManager_Busy;
+ }
+ serialWriteHandle->transfer.buffer = buffer;
+ serialWriteHandle->transfer.length = length;
+ serialWriteHandle->transfer.soFar = 0U;
+ serialWriteHandle->transfer.mode = mode;
+
+ if (NULL == LIST_GetHead(&handle->runningWriteHandleHead))
+ {
+ isEmpty = 1U;
+ }
+ SerialManager_AddTail(&handle->runningWriteHandleHead, serialWriteHandle);
+ EnableGlobalIRQ(primask);
+
+ if (isEmpty != 0U)
+ {
+ status = SerialManager_StartWriting(handle);
+ if ((serial_manager_status_t)kStatus_SerialManager_Success != status)
+ {
+ return status;
+ }
+ }
+
+ if (kSerialManager_TransmissionBlocking == mode)
+ {
+ while (serialWriteHandle->transfer.length > serialWriteHandle->transfer.soFar)
+ {
+#if defined(__GIC_PRIO_BITS)
+ if ((__get_CPSR() & CPSR_M_Msk) == 0x13)
+#else
+ if (__get_IPSR() != 0U)
+#endif
+ {
+ SerialManager_IsrFunction(handle);
+ }
+ }
+ }
+ return kStatus_SerialManager_Success;
+}
+
+static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandle,
+ uint8_t *buffer,
+ uint32_t length,
+ serial_manager_transmission_mode_t mode,
+ uint32_t *receivedLength)
+{
+ serial_manager_read_handle_t *serialReadHandle;
+ serial_manager_handle_t *handle;
+ uint32_t dataLength;
+ uint32_t primask;
+
+ assert(readHandle);
+ assert(buffer);
+ assert(length);
+
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;
+ handle = serialReadHandle->serialManagerHandle;
+
+ assert(handle);
+ assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag);
+ assert(!((kSerialManager_TransmissionNonBlocking == mode) && (NULL == serialReadHandle->callback)));
+
+ primask = DisableGlobalIRQ();
+ if (serialReadHandle->transfer.buffer != NULL)
+ {
+ EnableGlobalIRQ(primask);
+ return kStatus_SerialManager_Busy;
+ }
+ serialReadHandle->transfer.buffer = buffer;
+ serialReadHandle->transfer.length = length;
+ serialReadHandle->transfer.soFar = 0U;
+ serialReadHandle->transfer.mode = mode;
+
+ dataLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail;
+ dataLength = dataLength % handle->ringBuffer.ringBufferSize;
+
+ for (serialReadHandle->transfer.soFar = 0U; serialReadHandle->transfer.soFar < MIN(dataLength, length);
+ serialReadHandle->transfer.soFar++)
+ {
+ buffer[serialReadHandle->transfer.soFar] = handle->ringBuffer.ringBuffer[handle->ringBuffer.ringTail];
+ handle->ringBuffer.ringTail++;
+ if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize)
+ {
+ handle->ringBuffer.ringTail = 0U;
+ }
+ }
+
+ dataLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail;
+ dataLength = dataLength % handle->ringBuffer.ringBufferSize;
+ dataLength = handle->ringBuffer.ringBufferSize - 1U - dataLength;
+
+ (void)SerialManager_StartReading(handle, readHandle, NULL, dataLength);
+
+ if (receivedLength != NULL)
+ {
+ *receivedLength = serialReadHandle->transfer.soFar;
+ serialReadHandle->transfer.buffer = NULL;
+ EnableGlobalIRQ(primask);
+ }
+ else
+ {
+ if (serialReadHandle->transfer.soFar >= serialReadHandle->transfer.length)
+ {
+ serialReadHandle->transfer.buffer = NULL;
+ EnableGlobalIRQ(primask);
+ if (kSerialManager_TransmissionNonBlocking == mode)
+ {
+ if (serialReadHandle->callback != NULL)
+ {
+ serial_manager_callback_message_t msg;
+ msg.buffer = buffer;
+ msg.length = serialReadHandle->transfer.soFar;
+ serialReadHandle->callback(serialReadHandle->callbackParam, &msg, kStatus_SerialManager_Success);
+ }
+ }
+ }
+ else
+ {
+ EnableGlobalIRQ(primask);
+ }
+
+ if (kSerialManager_TransmissionBlocking == mode)
+ {
+ while (serialReadHandle->transfer.length > serialReadHandle->transfer.soFar)
+ {
+ }
+ }
+ }
+
+ return kStatus_SerialManager_Success;
+}
+
+#else
+
+static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHandle, uint8_t *buffer, uint32_t length)
+{
+ serial_manager_write_handle_t *serialWriteHandle;
+ serial_manager_handle_t *handle;
+
+ assert(writeHandle);
+ assert(buffer);
+ assert(length);
+
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
+ handle = serialWriteHandle->serialManagerHandle;
+
+ assert(handle);
+
+ return SerialManager_StartWriting(handle, serialWriteHandle, buffer, length);
+}
+
+static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length)
+{
+ serial_manager_read_handle_t *serialReadHandle;
+ serial_manager_handle_t *handle;
+
+ assert(readHandle);
+ assert(buffer);
+ assert(length);
+
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;
+ handle = serialReadHandle->serialManagerHandle;
+
+ assert(handle);
+
+ return SerialManager_StartReading(handle, serialReadHandle, buffer, length);
+}
+#endif
+
+serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, serial_manager_config_t *config)
+{
+ serial_manager_handle_t *handle;
+ serial_manager_status_t status = kStatus_SerialManager_Error;
+
+ assert(config);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ assert(config->ringBuffer);
+ assert(config->ringBufferSize);
+#endif
+ assert(serialHandle);
+ assert(SERIAL_MANAGER_HANDLE_SIZE >= sizeof(serial_manager_handle_t));
+
+ handle = (serial_manager_handle_t *)serialHandle;
+
+ (void)memset(handle, 0, SERIAL_MANAGER_HANDLE_SIZE);
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+
+ COMMON_TASK_init();
+
+#else
+ if (KOSA_StatusSuccess != OSA_EventCreate((osa_event_handle_t)handle->event, true))
+ {
+ return kStatus_SerialManager_Error;
+ }
+
+ if (KOSA_StatusSuccess != OSA_TaskCreate((osa_task_handle_t)handle->taskId, OSA_TASK(SerialManager_Task), handle))
+ {
+ return kStatus_SerialManager_Error;
+ }
+#endif
+
+#endif
+
+#endif
+
+ handle->type = config->type;
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ handle->ringBuffer.ringBuffer = config->ringBuffer;
+ handle->ringBuffer.ringBufferSize = config->ringBufferSize;
+#endif
+
+ switch (config->type)
+ {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ case kSerialPort_Uart:
+ status = Serial_UartInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ if ((serial_manager_status_t)kStatus_SerialManager_Success == status)
+ {
+ status = Serial_UartInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ SerialManager_TxCallback, handle);
+ if ((serial_manager_status_t)kStatus_SerialManager_Success == status)
+ {
+ status = Serial_UartInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ SerialManager_RxCallback, handle);
+ }
+ }
+#endif
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ case kSerialPort_UsbCdc:
+ status = Serial_UsbCdcInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ if (kStatus_SerialManager_Success == status)
+ {
+ status = Serial_UsbCdcInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ SerialManager_TxCallback, handle);
+ if (kStatus_SerialManager_Success == status)
+ {
+ status = Serial_UsbCdcInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ SerialManager_RxCallback, handle);
+ }
+ }
+#endif
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ case kSerialPort_Swo:
+ status = Serial_SwoInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ if (kStatus_SerialManager_Success == status)
+ {
+ status = Serial_SwoInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ SerialManager_TxCallback, handle);
+ }
+#endif
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ case kSerialPort_UsbCdcVirtual:
+ status = Serial_UsbCdcVirtualInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ if (kStatus_SerialManager_Success == status)
+ {
+ status = Serial_UsbCdcVirtualInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ SerialManager_TxCallback, handle);
+ if (kStatus_SerialManager_Success == status)
+ {
+ status = Serial_UsbCdcVirtualInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ SerialManager_RxCallback, handle);
+ }
+ }
+#endif
+ break;
+#endif
+ default:
+ /*MISRA rule 16.4*/
+ break;
+ }
+
+ return status;
+}
+
+serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle)
+{
+ serial_manager_handle_t *handle;
+ uint32_t primask;
+
+ assert(serialHandle);
+
+ handle = (serial_manager_handle_t *)serialHandle;
+
+ primask = DisableGlobalIRQ();
+ if ((handle->openedReadHandleHead != NULL) || (handle->openedWriteHandleCount != 0U))
+ {
+ EnableGlobalIRQ(primask);
+ return kStatus_SerialManager_Busy;
+ }
+ EnableGlobalIRQ(primask);
+
+ switch (handle->type)
+ {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ case kSerialPort_Uart:
+ (void)Serial_UartDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ case kSerialPort_UsbCdc:
+ (void)Serial_UsbCdcDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ case kSerialPort_Swo:
+ (void)Serial_SwoDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ case kSerialPort_UsbCdcVirtual:
+ (void)Serial_UsbCdcVirtualDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+ default:
+ /*MISRA rule 16.4*/
+ break;
+ }
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+#else
+ OSA_EventDestroy((osa_event_handle_t)handle->event);
+ OSA_TaskDestroy((osa_task_handle_t)handle->taskId);
+#endif
+
+#endif
+
+#endif
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle)
+{
+ serial_manager_handle_t *handle;
+ serial_manager_write_handle_t *serialWriteHandle;
+ uint32_t primask;
+
+ assert(serialHandle);
+ assert(writeHandle);
+ assert(SERIAL_MANAGER_WRITE_HANDLE_SIZE >= sizeof(serial_manager_write_handle_t));
+
+ handle = (serial_manager_handle_t *)serialHandle;
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
+
+ (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_HANDLE_SIZE);
+
+ primask = DisableGlobalIRQ();
+ handle->openedWriteHandleCount++;
+ EnableGlobalIRQ(primask);
+
+ serialWriteHandle->serialManagerHandle = handle;
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ serialWriteHandle->tag = SERIAL_MANAGER_WRITE_TAG;
+#endif
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle)
+{
+ serial_manager_handle_t *handle;
+ serial_manager_write_handle_t *serialWriteHandle;
+ uint32_t primask;
+
+ assert(writeHandle);
+
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
+ handle = (serial_manager_handle_t *)(void *)serialWriteHandle->serialManagerHandle;
+
+ assert(handle);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag);
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ (void)SerialManager_CancelWriting(writeHandle);
+#endif
+ primask = DisableGlobalIRQ();
+ if (handle->openedWriteHandleCount > 0U)
+ {
+ handle->openedWriteHandleCount--;
+ }
+ EnableGlobalIRQ(primask);
+
+ (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_HANDLE_SIZE);
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle)
+{
+ serial_manager_handle_t *handle;
+ serial_manager_read_handle_t *serialReadHandle;
+ uint32_t primask;
+
+ assert(serialHandle);
+ assert(readHandle);
+ assert(SERIAL_MANAGER_READ_HANDLE_SIZE >= sizeof(serial_manager_read_handle_t));
+
+ handle = (serial_manager_handle_t *)serialHandle;
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;
+
+ primask = DisableGlobalIRQ();
+ if (handle->openedReadHandleHead != NULL)
+ {
+ EnableGlobalIRQ(primask);
+ return kStatus_SerialManager_Busy;
+ }
+ handle->openedReadHandleHead = serialReadHandle;
+ EnableGlobalIRQ(primask);
+
+ (void)memset(readHandle, 0, SERIAL_MANAGER_READ_HANDLE_SIZE);
+
+ serialReadHandle->serialManagerHandle = handle;
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ serialReadHandle->tag = SERIAL_MANAGER_READ_TAG;
+#endif
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle)
+{
+ serial_manager_handle_t *handle;
+ serial_manager_read_handle_t *serialReadHandle;
+ uint32_t primask;
+
+ assert(readHandle);
+
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;
+ handle = (serial_manager_handle_t *)(void *)serialReadHandle->serialManagerHandle;
+
+ assert(handle && (handle->openedReadHandleHead == serialReadHandle));
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag);
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ (void)SerialManager_CancelReading(readHandle);
+#endif
+
+ primask = DisableGlobalIRQ();
+ handle->openedReadHandleHead = NULL;
+ EnableGlobalIRQ(primask);
+
+ (void)memset(readHandle, 0, SERIAL_MANAGER_READ_HANDLE_SIZE);
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle, uint8_t *buffer, uint32_t length)
+{
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ return SerialManager_Write(writeHandle, buffer, length, kSerialManager_TransmissionBlocking);
+#else
+ return SerialManager_Write(writeHandle, buffer, length);
+#endif
+}
+
+serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length)
+{
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionBlocking, NULL);
+#else
+ return SerialManager_Read(readHandle, buffer, length);
+#endif
+}
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle,
+ uint8_t *buffer,
+ uint32_t length)
+{
+ return SerialManager_Write(writeHandle, buffer, length, kSerialManager_TransmissionNonBlocking);
+}
+
+serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length)
+{
+ return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionNonBlocking, NULL);
+}
+
+serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle)
+{
+ serial_manager_write_handle_t *serialWriteHandle;
+ uint32_t primask;
+ uint8_t isNotUsed = 0;
+
+ assert(writeHandle);
+
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
+
+ assert(serialWriteHandle->serialManagerHandle);
+ assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag);
+
+ if ((serialWriteHandle->transfer.buffer != NULL) &&
+ (kSerialManager_TransmissionBlocking == serialWriteHandle->transfer.mode))
+ {
+ return kStatus_SerialManager_Error;
+ }
+
+ primask = DisableGlobalIRQ();
+ if (serialWriteHandle != (serial_manager_write_handle_t *)(void *)LIST_GetHead(
+ &serialWriteHandle->serialManagerHandle->runningWriteHandleHead))
+ {
+ (void)LIST_RemoveElement(&serialWriteHandle->link);
+ isNotUsed = 1;
+ }
+ EnableGlobalIRQ(primask);
+
+ if (isNotUsed != 0U)
+ {
+ serialWriteHandle->transfer.soFar = 0;
+ serialWriteHandle->transfer.status = kStatus_SerialManager_Canceled;
+
+ SerialManager_AddTail(&serialWriteHandle->serialManagerHandle->completedWriteHandleHead, serialWriteHandle);
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+ serialWriteHandle->serialManagerHandle->commontaskMsg.callback = SerialManager_Task;
+ serialWriteHandle->serialManagerHandle->commontaskMsg.callbackParam = serialWriteHandle->serialManagerHandle;
+ COMMON_TASK_post_message(&serialWriteHandle->serialManagerHandle->commontaskMsg);
+#else
+ (void)OSA_EventSet((osa_event_handle_t)serialWriteHandle->serialManagerHandle->event, SERIAL_EVENT_DATA_SENT);
+#endif
+
+#else
+ SerialManager_Task(serialWriteHandle->serialManagerHandle);
+#endif
+ }
+ else
+ {
+ switch (serialWriteHandle->serialManagerHandle->type)
+ {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ case kSerialPort_Uart:
+ (void)Serial_UartCancelWrite(
+ ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ case kSerialPort_UsbCdc:
+ (void)Serial_UsbCdcCancelWrite(
+ ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ case kSerialPort_Swo:
+ (void)Serial_SwoCancelWrite(
+ ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ case kSerialPort_UsbCdcVirtual:
+ (void)Serial_UsbCdcVirtualCancelWrite(
+ ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+ default:
+ /*MISRA rule 16.4*/
+ break;
+ }
+ }
+
+ (void)SerialManager_StartWriting(serialWriteHandle->serialManagerHandle);
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle)
+{
+ serial_manager_read_handle_t *serialReadHandle;
+ serial_manager_callback_message_t msg;
+ uint8_t *buffer;
+ uint32_t primask;
+
+ assert(readHandle);
+
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;
+
+ assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag);
+
+ if ((serialReadHandle->transfer.buffer != NULL) &&
+ (kSerialManager_TransmissionBlocking == serialReadHandle->transfer.mode))
+ {
+ return kStatus_SerialManager_Error;
+ }
+
+ primask = DisableGlobalIRQ();
+ buffer = serialReadHandle->transfer.buffer;
+ serialReadHandle->transfer.buffer = NULL;
+ serialReadHandle->transfer.length = 0;
+ msg.buffer = buffer;
+ msg.length = serialReadHandle->transfer.soFar;
+ EnableGlobalIRQ(primask);
+
+ if (buffer != NULL)
+ {
+ if (serialReadHandle->callback != NULL)
+ {
+ serialReadHandle->callback(serialReadHandle->callbackParam, &msg, kStatus_SerialManager_Canceled);
+ }
+ }
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle,
+ uint8_t *buffer,
+ uint32_t length,
+ uint32_t *receivedLength)
+{
+ assert(receivedLength);
+
+ return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionBlocking, receivedLength);
+}
+
+serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam)
+{
+ serial_manager_write_handle_t *serialWriteHandle;
+
+ assert(writeHandle);
+
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
+
+ assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag);
+
+ serialWriteHandle->callbackParam = callbackParam;
+ serialWriteHandle->callback = callback;
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam)
+{
+ serial_manager_read_handle_t *serialReadHandle;
+
+ assert(readHandle);
+
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;
+
+ assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag);
+
+ serialReadHandle->callbackParam = callbackParam;
+ serialReadHandle->callback = callback;
+
+ return kStatus_SerialManager_Success;
+}
+#endif
+
+serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle)
+{
+ assert(serialHandle);
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle)
+{
+ assert(serialHandle);
+
+ return kStatus_SerialManager_Success;
+}
diff --git a/third_party/nxp/JN5189DK6/components/serial_manager/serial_manager.h b/third_party/nxp/JN5189DK6/components/serial_manager/serial_manager.h
new file mode 100755
index 0000000..0b4e334
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/components/serial_manager/serial_manager.h
@@ -0,0 +1,548 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SERIAL_MANAGER_H__
+#define __SERIAL_MANAGER_H__
+
+/*!
+ * @addtogroup serialmanager
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/*! @brief Enable or disable serial manager non-blocking mode (1 - enable, 0 - disable) */
+#define SERIAL_MANAGER_NON_BLOCKING_MODE (1U)
+#else
+#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE
+#define SERIAL_MANAGER_NON_BLOCKING_MODE (0U)
+#endif
+#endif
+
+/*! @brief Enable or disable uart port (1 - enable, 0 - disable) */
+#ifndef SERIAL_PORT_TYPE_UART
+#define SERIAL_PORT_TYPE_UART (1U)
+#endif
+
+/*! @brief Enable or disable USB CDC port (1 - enable, 0 - disable) */
+#ifndef SERIAL_PORT_TYPE_USBCDC
+#define SERIAL_PORT_TYPE_USBCDC (0U)
+#endif
+
+/*! @brief Enable or disable SWO port (1 - enable, 0 - disable) */
+#ifndef SERIAL_PORT_TYPE_SWO
+#define SERIAL_PORT_TYPE_SWO (0U)
+#endif
+
+/*! @brief Enable or disable USB CDC virtual port (1 - enable, 0 - disable) */
+#ifndef SERIAL_PORT_TYPE_USBCDC_VIRTUAL
+#define SERIAL_PORT_TYPE_USBCDC_VIRTUAL (0U)
+#endif
+
+/*! @brief Set serial manager write handle size */
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (44U)
+#define SERIAL_MANAGER_READ_HANDLE_SIZE (44U)
+#else
+#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (4U)
+#define SERIAL_MANAGER_READ_HANDLE_SIZE (4U)
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+#include "serial_port_uart.h"
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#error The serial manager blocking mode cannot be supported for USB CDC.
+#endif
+
+#include "serial_port_usb.h"
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+#include "serial_port_swo.h"
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#error The serial manager blocking mode cannot be supported for USB CDC.
+#endif
+
+#include "serial_port_usb_virtual.h"
+#endif
+
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP 0U
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+
+#if (SERIAL_PORT_UART_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_UART_HANDLE_SIZE
+#endif
+
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+
+#if (SERIAL_PORT_USB_CDC_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_CDC_HANDLE_SIZE
+#endif
+
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+
+#if (SERIAL_PORT_SWO_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_SWO_HANDLE_SIZE
+#endif
+
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+
+#if (SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE
+#endif
+
+#endif
+
+/*! @brief SERIAL_PORT_UART_HANDLE_SIZE/SERIAL_PORT_USB_CDC_HANDLE_SIZE + serial manager dedicated size */
+#if ((defined(SERIAL_MANAGER_HANDLE_SIZE_TEMP) && (SERIAL_MANAGER_HANDLE_SIZE_TEMP > 0U)))
+#else
+#error SERIAL_PORT_TYPE_UART, SERIAL_PORT_TYPE_USBCDC, SERIAL_PORT_TYPE_SWO and SERIAL_PORT_TYPE_USBCDC_VIRTUAL should not be cleared at same time.
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 120U)
+#else
+#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 12U)
+#endif
+
+#define SERIAL_MANAGER_USE_COMMON_TASK (1U)
+#define SERIAL_MANAGER_TASK_PRIORITY (2U)
+#define SERIAL_MANAGER_TASK_STACK_SIZE (1000U)
+
+typedef void *serial_handle_t;
+typedef void *serial_write_handle_t;
+typedef void *serial_read_handle_t;
+
+/*! @brief serial port type*/
+typedef enum _serial_port_type
+{
+ kSerialPort_Uart = 1U, /*!< Serial port UART */
+ kSerialPort_UsbCdc, /*!< Serial port USB CDC */
+ kSerialPort_Swo, /*!< Serial port SWO */
+ kSerialPort_UsbCdcVirtual, /*!< Serial port USB CDC Virtual */
+} serial_port_type_t;
+
+/*! @brief serial manager config structure*/
+typedef struct _serial_manager_config
+{
+ uint8_t *ringBuffer; /*!< Ring buffer address, it is used to buffer data received by the hardware.
+ Besides, the memory space cannot be free during the lifetime of the serial
+ manager module. */
+ uint32_t ringBufferSize; /*!< The size of the ring buffer */
+ serial_port_type_t type; /*!< Serial port type */
+ void *portConfig; /*!< Serial port configuration */
+} serial_manager_config_t;
+
+/*! @brief serial manager error code*/
+typedef enum _serial_manager_status
+{
+ kStatus_SerialManager_Success = kStatus_Success, /*!< Success */
+ kStatus_SerialManager_Error = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 1), /*!< Failed */
+ kStatus_SerialManager_Busy = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 2), /*!< Busy */
+ kStatus_SerialManager_Notify = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 3), /*!< Ring buffer is not empty */
+ kStatus_SerialManager_Canceled =
+ MAKE_STATUS(kStatusGroup_SERIALMANAGER, 4), /*!< the non-blocking request is canceled */
+ kStatus_SerialManager_HandleConflict = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 5), /*!< The handle is opened */
+ kStatus_SerialManager_RingBufferOverflow =
+ MAKE_STATUS(kStatusGroup_SERIALMANAGER, 6), /*!< The ring buffer is overflowed */
+} serial_manager_status_t;
+
+/*! @brief Callback message structure */
+typedef struct _serial_manager_callback_message
+{
+ uint8_t *buffer; /*!< Transferred buffer */
+ uint32_t length; /*!< Transferred data length */
+} serial_manager_callback_message_t;
+
+/*! @brief callback function */
+typedef void (*serial_manager_callback_t)(void *callbackParam,
+ serial_manager_callback_message_t *message,
+ serial_manager_status_t status);
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @brief Initializes a serial manager module with the serial manager handle and the user configuration structure.
+ *
+ * This function configures the Serial Manager module with user-defined settings. The user can configure the
+ * configuration
+ * structure. The parameter serialHandle is a pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE
+ * allocated by the caller.
+ * The Serial Manager module supports two types of serial port, UART (includes UART, USART, LPSCI, LPUART, etc) and USB
+ * CDC.
+ * Please refer to #serial_port_type_t for serial port setting. These two types can be set by using
+ * #serial_manager_config_t.
+ *
+ * Example below shows how to use this API to configure the Serial Manager.
+ * For UART,
+ * @code
+ * #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U)
+ * static uint8_t s_serialHandleBuffer[SERIAL_MANAGER_HANDLE_SIZE];
+ * static serial_handle_t s_serialHandle = &s_serialHandleBuffer[0];
+ * static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];
+ *
+ * serial_manager_config_t config;
+ * serial_port_uart_config_t uartConfig;
+ * config.type = kSerialPort_Uart;
+ * config.ringBuffer = &s_ringBuffer[0];
+ * config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;
+ * uartConfig.instance = 0;
+ * uartConfig.clockRate = 24000000;
+ * uartConfig.baudRate = 115200;
+ * uartConfig.parityMode = kSerialManager_UartParityDisabled;
+ * uartConfig.stopBitCount = kSerialManager_UartOneStopBit;
+ * uartConfig.enableRx = 1;
+ * uartConfig.enableTx = 1;
+ * config.portConfig = &uartConfig;
+ * SerialManager_Init(s_serialHandle, &config);
+ * @endcode
+ * For USB CDC,
+ * @code
+ * #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U)
+ * static uint8_t s_serialHandleBuffer[SERIAL_MANAGER_HANDLE_SIZE];
+ * static serial_handle_t s_serialHandle = &s_serialHandleBuffer[0];
+ * static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];
+ *
+ * serial_manager_config_t config;
+ * serial_port_usb_cdc_config_t usbCdcConfig;
+ * config.type = kSerialPort_UsbCdc;
+ * config.ringBuffer = &s_ringBuffer[0];
+ * config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;
+ * usbCdcConfig.controllerIndex = kSerialManager_UsbControllerKhci0;
+ * config.portConfig = &usbCdcConfig;
+ * SerialManager_Init(s_serialHandle, &config);
+ * @endcode
+ *
+ * @param serialHandle Pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE allocated by the caller.
+ * @param config Pointer to user-defined configuration structure.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ * @retval kStatus_SerialManager_Success The Serial Manager module initialization succeed.
+ */
+serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, serial_manager_config_t *config);
+
+/*!
+ * @brief De-initializes the serial manager module instance.
+ *
+ * This function de-initializes the serial manager module instance. If the opened writing or
+ * reading handle is not closed, the function will return kStatus_SerialManager_Busy.
+ *
+ * @param serialHandle The serial manager module handle pointer.
+ * @retval kStatus_SerialManager_Success The serial manager de-initialization succeed.
+ * @retval kStatus_SerialManager_Busy Opened reading or writing handle is not closed.
+ */
+serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle);
+
+/*!
+ * @brief Opens a writing handle for the serial manager module.
+ *
+ * This function Opens a writing handle for the serial manager module. If the serial manager needs to
+ * be used in different tasks, the task should open a dedicated write handle for itself by calling
+ * #SerialManager_OpenWriteHandle. Since there can only one buffer for transmission for the writing
+ * handle at the same time, multiple writing handles need to be opened when the multiple transmission
+ * is needed for a task.
+ *
+ * @param serialHandle The serial manager module handle pointer.
+ * @param writeHandle The serial manager module writing handle pointer.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ * @retval kStatus_SerialManager_HandleConflict The writing handle was opened.
+ * @retval kStatus_SerialManager_Success The writing handle is opened.
+ *
+ * Example below shows how to use this API to write data.
+ * For task 1,
+ * @code
+ * static uint8_t s_serialWriteHandleBuffer1[SERIAL_MANAGER_WRITE_HANDLE_SIZE];
+ * static serial_write_handle_t s_serialWriteHandle1 = &s_serialWriteHandleBuffer1[0];
+ * static uint8_t s_nonBlockingWelcome1[] = "This is non-blocking writing log for task1!\r\n";
+ * SerialManager_OpenWriteHandle(serialHandle, s_serialWriteHandle1);
+ * SerialManager_InstallTxCallback(s_serialWriteHandle1, Task1_SerialManagerTxCallback, s_serialWriteHandle1);
+ * SerialManager_WriteNonBlocking(s_serialWriteHandle1, s_nonBlockingWelcome1, sizeof(s_nonBlockingWelcome1) - 1);
+ * @endcode
+ * For task 2,
+ * @code
+ * static uint8_t s_serialWriteHandleBuffer2[SERIAL_MANAGER_WRITE_HANDLE_SIZE];
+ * static serial_write_handle_t s_serialWriteHandle2 = &s_serialWriteHandleBuffer2[0];
+ * static uint8_t s_nonBlockingWelcome2[] = "This is non-blocking writing log for task2!\r\n";
+ * SerialManager_OpenWriteHandle(serialHandle, s_serialWriteHandle2);
+ * SerialManager_InstallTxCallback(s_serialWriteHandle2, Task2_SerialManagerTxCallback, s_serialWriteHandle2);
+ * SerialManager_WriteNonBlocking(s_serialWriteHandle2, s_nonBlockingWelcome2, sizeof(s_nonBlockingWelcome2) - 1);
+ * @endcode
+ */
+serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle);
+
+/*!
+ * @brief Closes a writing handle for the serial manager module.
+ *
+ * This function Closes a writing handle for the serial manager module.
+ *
+ * @param writeHandle The serial manager module writing handle pointer.
+ * @retval kStatus_SerialManager_Success The writing handle is closed.
+ */
+serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle);
+
+/*!
+ * @brief Opens a reading handle for the serial manager module.
+ *
+ * This function Opens a reading handle for the serial manager module. The reading handle can not be
+ * opened multiple at the same time. The error code kStatus_SerialManager_Busy would be returned when
+ * the previous reading handle is not closed. And There can only be one buffer for receiving for the
+ * reading handle at the same time.
+ *
+ * @param serialHandle The serial manager module handle pointer.
+ * @param readHandle The serial manager module reading handle pointer.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ * @retval kStatus_SerialManager_Success The reading handle is opened.
+ * @retval kStatus_SerialManager_Busy Previous reading handle is not closed.
+ *
+ * Example below shows how to use this API to read data.
+ * @code
+ * static uint8_t s_serialReadHandleBuffer[SERIAL_MANAGER_READ_HANDLE_SIZE];
+ * static serial_read_handle_t s_serialReadHandle = &s_serialReadHandleBuffer[0];
+ * SerialManager_OpenReadHandle(serialHandle, s_serialReadHandle);
+ * static uint8_t s_nonBlockingBuffer[64];
+ * SerialManager_InstallRxCallback(s_serialReadHandle, APP_SerialManagerRxCallback, s_serialReadHandle);
+ * SerialManager_ReadNonBlocking(s_serialReadHandle, s_nonBlockingBuffer, sizeof(s_nonBlockingBuffer));
+ * @endcode
+ */
+serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle);
+
+/*!
+ * @brief Closes a reading for the serial manager module.
+ *
+ * This function Closes a reading for the serial manager module.
+ *
+ * @param readHandle The serial manager module reading handle pointer.
+ * @retval kStatus_SerialManager_Success The reading handle is closed.
+ */
+serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle);
+
+/*!
+ * @brief Transmits data with the blocking mode.
+ *
+ * This is a blocking function, which polls the sending queue, waits for the sending queue to be empty.
+ * This function sends data using an interrupt method. The interrupt of the hardware could not be disabled.
+ * And There can only one buffer for transmission for the writing handle at the same time.
+ *
+ * @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking
+ * cannot be used at the same time.
+ * And, the function #SerialManager_CancelWriting cannot be used to abort the transmission of this function.
+ *
+ * @param writeHandle The serial manager module handle pointer.
+ * @param buffer Start address of the data to write.
+ * @param length Length of the data to write.
+ * @retval kStatus_SerialManager_Success Successfully sent all data.
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle,
+ uint8_t *buffer,
+ uint32_t length);
+
+/*!
+ * @brief Reads data with the blocking mode.
+ *
+ * This is a blocking function, which polls the receiving buffer, waits for the receiving buffer to be full.
+ * This function receives data using an interrupt method. The interrupt of the hardware could not be disabled.
+ * And There can only one buffer for receiving for the reading handle at the same time.
+ *
+ * @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking
+ * cannot be used at the same time.
+ * And, the function #SerialManager_CancelReading cannot be used to abort the transmission of this function.
+ *
+ * @param readHandle The serial manager module handle pointer.
+ * @param buffer Start address of the data to store the received data.
+ * @param length The length of the data to be received.
+ * @retval kStatus_SerialManager_Success Successfully received all data.
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length);
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+/*!
+ * @brief Transmits data with the non-blocking mode.
+ *
+ * This is a non-blocking function, which returns directly without waiting for all data to be sent.
+ * When all data is sent, the module notifies the upper layer through a TX callback function and passes
+ * the status parameter @ref kStatus_SerialManager_Success.
+ * This function sends data using an interrupt method. The interrupt of the hardware could not be disabled.
+ * And There can only one buffer for transmission for the writing handle at the same time.
+ *
+ * @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking
+ * cannot be used at the same time. And, the TX callback is mandatory before the function could be used.
+ *
+ * @param writeHandle The serial manager module handle pointer.
+ * @param buffer Start address of the data to write.
+ * @param length Length of the data to write.
+ * @retval kStatus_SerialManager_Success Successfully sent all data.
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle,
+ uint8_t *buffer,
+ uint32_t length);
+
+/*!
+ * @brief Reads data with the non-blocking mode.
+ *
+ * This is a non-blocking function, which returns directly without waiting for all data to be received.
+ * When all data is received, the module driver notifies the upper layer
+ * through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Success.
+ * This function receives data using an interrupt method. The interrupt of the hardware could not be disabled.
+ * And There can only one buffer for receiving for the reading handle at the same time.
+ *
+ * @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking
+ * cannot be used at the same time. And, the RX callback is mandatory before the function could be used.
+ *
+ * @param readHandle The serial manager module handle pointer.
+ * @param buffer Start address of the data to store the received data.
+ * @param length The length of the data to be received.
+ * @retval kStatus_SerialManager_Success Successfully received all data.
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle,
+ uint8_t *buffer,
+ uint32_t length);
+
+/*!
+ * @brief Tries to read data.
+ *
+ * The function tries to read data from internal ring buffer. If the ring buffer is not empty, the data will be
+ * copied from ring buffer to up layer buffer. The copied length is the minimum of the ring buffer and up layer length.
+ * After the data is copied, the actual data length is passed by the parameter length.
+ * And There can only one buffer for receiving for the reading handle at the same time.
+ *
+ * @param readHandle The serial manager module handle pointer.
+ * @param buffer Start address of the data to store the received data.
+ * @param length The length of the data to be received.
+ * @param receivedLength Length received from the ring buffer directly.
+ * @retval kStatus_SerialManager_Success Successfully received all data.
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle,
+ uint8_t *buffer,
+ uint32_t length,
+ uint32_t *receivedLength);
+
+/*!
+ * @brief Cancels unfinished send transmission.
+ *
+ * The function cancels unfinished send transmission. When the transfer is canceled, the module notifies the upper layer
+ * through a TX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled.
+ *
+ * @note The function #SerialManager_CancelWriting cannot be used to abort the transmission of
+ * the function #SerialManager_WriteBlocking.
+ *
+ * @param writeHandle The serial manager module handle pointer.
+ * @retval kStatus_SerialManager_Success Get successfully abort the sending.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle);
+
+/*!
+ * @brief Cancels unfinished receive transmission.
+ *
+ * The function cancels unfinished receive transmission. When the transfer is canceled, the module notifies the upper
+ * layer
+ * through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled.
+ *
+ * @note The function #SerialManager_CancelReading cannot be used to abort the transmission of
+ * the function #SerialManager_ReadBlocking.
+ *
+ * @param readHandle The serial manager module handle pointer.
+ * @retval kStatus_SerialManager_Success Get successfully abort the receiving.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle);
+
+/*!
+ * @brief Installs a TX callback and callback parameter.
+ *
+ * This function is used to install the TX callback and callback parameter for the serial manager module.
+ * When any status of TX transmission changed, the driver will notify the upper layer by the installed callback
+ * function. And the status is also passed as status parameter when the callback is called.
+ *
+ * @param writeHandle The serial manager module handle pointer.
+ * @param callback The callback function.
+ * @param callbackParam The parameter of the callback function.
+ * @retval kStatus_SerialManager_Success Successfully install the callback.
+ */
+serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+
+/*!
+ * @brief Installs a RX callback and callback parameter.
+ *
+ * This function is used to install the RX callback and callback parameter for the serial manager module.
+ * When any status of RX transmission changed, the driver will notify the upper layer by the installed callback
+ * function. And the status is also passed as status parameter when the callback is called.
+ *
+ * @param readHandle The serial manager module handle pointer.
+ * @param callback The callback function.
+ * @param callbackParam The parameter of the callback function.
+ * @retval kStatus_SerialManager_Success Successfully install the callback.
+ */
+serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+
+#endif
+
+/*!
+ * @brief Prepares to enter low power consumption.
+ *
+ * This function is used to prepare to enter low power consumption.
+ *
+ * @param serialHandle The serial manager module handle pointer.
+ * @retval kStatus_SerialManager_Success Successful operation.
+ */
+serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle);
+
+/*!
+ * @brief Restores from low power consumption.
+ *
+ * This function is used to restore from low power consumption.
+ *
+ * @param serialHandle The serial manager module handle pointer.
+ * @retval kStatus_SerialManager_Success Successful operation.
+ */
+serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle);
+
+#if defined(__cplusplus)
+}
+#endif
+/*! @} */
+#endif /* __SERIAL_MANAGER_H__ */
diff --git a/third_party/nxp/JN5189DK6/components/serial_manager/serial_port_internal.h b/third_party/nxp/JN5189DK6/components/serial_manager/serial_port_internal.h
new file mode 100755
index 0000000..abccd47
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/components/serial_manager/serial_port_internal.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright 2019 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SERIAL_PORT_INTERNAL_H__
+#define __SERIAL_PORT_INTERNAL_H__
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig);
+serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+void Serial_UartIsrFunction(serial_handle_t serialHandle);
+#endif
+
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+serial_manager_status_t Serial_UsbCdcInit(serial_handle_t serialHandle, void *config);
+serial_manager_status_t Serial_UsbCdcDeinit(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UsbCdcWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_UsbCdcRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_UsbCdcCancelWrite(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UsbCdcInstallTxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+serial_manager_status_t Serial_UsbCdcInstallRxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+void Serial_UsbCdcIsrFunction(serial_handle_t serialHandle);
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+serial_manager_status_t Serial_SwoInit(serial_handle_t serialHandle, void *config);
+serial_manager_status_t Serial_SwoDeinit(serial_handle_t serialHandle);
+serial_manager_status_t Serial_SwoWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_SwoRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#endif
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_SwoCancelWrite(serial_handle_t serialHandle);
+serial_manager_status_t Serial_SwoInstallTxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+serial_manager_status_t Serial_SwoInstallRxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+void Serial_SwoIsrFunction(serial_handle_t serialHandle);
+#endif
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+serial_manager_status_t Serial_UsbCdcVirtualInit(serial_handle_t serialHandle, void *config);
+serial_manager_status_t Serial_UsbCdcVirtualDeinit(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UsbCdcVirtualWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_UsbCdcVirtualRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_UsbCdcVirtualCancelWrite(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UsbCdcVirtualInstallTxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+serial_manager_status_t Serial_UsbCdcVirtualInstallRxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+void Serial_UsbCdcVirtualIsrFunction(serial_handle_t serialHandle);
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __SERIAL_PORT_INTERNAL_H__ */
diff --git a/third_party/nxp/JN5189DK6/components/serial_manager/serial_port_uart.c b/third_party/nxp/JN5189DK6/components/serial_manager/serial_port_uart.c
new file mode 100755
index 0000000..f60320d
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/components/serial_manager/serial_port_uart.c
@@ -0,0 +1,371 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "serial_manager.h"
+#include "serial_port_internal.h"
+
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+#include "uart.h"
+
+#include "serial_port_uart.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#ifndef NDEBUG
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
+#undef assert
+#define assert(n)
+#endif
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#define SERIAL_PORT_UART_RECEIVE_DATA_LENGTH 1U
+
+typedef struct _serial_uart_send_state
+{
+ serial_manager_callback_t callback;
+ void *callbackParam;
+ uint8_t *buffer;
+ uint32_t length;
+ volatile uint8_t busy;
+} serial_uart_send_state_t;
+
+typedef struct _serial_uart_recv_state
+{
+ serial_manager_callback_t callback;
+ void *callbackParam;
+ volatile uint8_t busy;
+ uint8_t readBuffer[SERIAL_PORT_UART_RECEIVE_DATA_LENGTH];
+} serial_uart_recv_state_t;
+#endif
+
+typedef struct _serial_uart_state
+{
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ serial_uart_send_state_t tx;
+ serial_uart_recv_state_t rx;
+#endif
+ uint8_t usartHandleBuffer[HAL_UART_HANDLE_SIZE];
+} serial_uart_state_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+/* UART user callback */
+static void Serial_UartCallback(hal_uart_handle_t handle, hal_uart_status_t status, void *userData)
+{
+ serial_uart_state_t *serialUartHandle;
+ serial_manager_callback_message_t msg;
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ hal_uart_transfer_t transfer;
+#endif
+
+ if (NULL == userData)
+ {
+ return;
+ }
+
+ serialUartHandle = (serial_uart_state_t *)userData;
+
+ if ((hal_uart_status_t)kStatus_HAL_UartRxIdle == status)
+ {
+ if ((NULL != serialUartHandle->rx.callback))
+ {
+ msg.buffer = &serialUartHandle->rx.readBuffer[0];
+ msg.length = sizeof(serialUartHandle->rx.readBuffer);
+ serialUartHandle->rx.callback(serialUartHandle->rx.callbackParam, &msg, kStatus_SerialManager_Success);
+ }
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ transfer.data = &serialUartHandle->rx.readBuffer[0];
+ transfer.dataSize = sizeof(serialUartHandle->rx.readBuffer);
+ if (kStatus_HAL_UartSuccess ==
+ HAL_UartTransferReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer))
+#else
+ if ((hal_uart_status_t)kStatus_HAL_UartSuccess ==
+ HAL_UartReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
+ &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer)))
+#endif
+ {
+ serialUartHandle->rx.busy = 1U;
+ }
+ else
+ {
+ serialUartHandle->rx.busy = 0U;
+ }
+ }
+ else if ((hal_uart_status_t)kStatus_HAL_UartTxIdle == status)
+ {
+ if (serialUartHandle->tx.busy != 0U)
+ {
+ serialUartHandle->tx.busy = 0U;
+ if ((NULL != serialUartHandle->tx.callback))
+ {
+ msg.buffer = serialUartHandle->tx.buffer;
+ msg.length = serialUartHandle->tx.length;
+ serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &msg, kStatus_SerialManager_Success);
+ }
+ }
+ }
+ else
+ {
+ }
+}
+#endif
+
+serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig)
+{
+ serial_uart_state_t *serialUartHandle;
+ serial_port_uart_config_t *uartConfig;
+ hal_uart_config_t config;
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ hal_uart_transfer_t transfer;
+#endif
+#endif
+
+ assert(serialConfig);
+ assert(serialHandle);
+ assert(SERIAL_PORT_UART_HANDLE_SIZE >= sizeof(serial_uart_state_t));
+
+ uartConfig = (serial_port_uart_config_t *)serialConfig;
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+ config.baudRate_Bps = uartConfig->baudRate;
+ config.parityMode = (hal_uart_parity_mode_t)uartConfig->parityMode;
+ config.stopBitCount = (hal_uart_stop_bit_count_t)uartConfig->stopBitCount;
+ config.enableRx = uartConfig->enableRx;
+ config.enableTx = uartConfig->enableTx;
+ config.srcClock_Hz = uartConfig->clockRate;
+ config.instance = uartConfig->instance;
+
+ if (kStatus_HAL_UartSuccess != HAL_UartInit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &config))
+ {
+ return kStatus_SerialManager_Error;
+ }
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ if (kStatus_HAL_UartSuccess !=
+ HAL_UartTransferInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
+ Serial_UartCallback, serialUartHandle))
+#else
+ if (kStatus_HAL_UartSuccess != HAL_UartInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
+ Serial_UartCallback, serialUartHandle))
+#endif
+ {
+ return kStatus_SerialManager_Error;
+ }
+
+ if (uartConfig->enableRx != 0U)
+ {
+ serialUartHandle->rx.busy = 1U;
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ transfer.data = &serialUartHandle->rx.readBuffer[0];
+ transfer.dataSize = sizeof(serialUartHandle->rx.readBuffer);
+ if (kStatus_HAL_UartSuccess !=
+ HAL_UartTransferReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer))
+#else
+ if (kStatus_HAL_UartSuccess !=
+ HAL_UartReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
+ &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer)))
+#endif
+ {
+ serialUartHandle->rx.busy = 0U;
+ return kStatus_SerialManager_Error;
+ }
+ }
+#endif
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle)
+{
+ serial_uart_state_t *serialUartHandle;
+
+ assert(serialHandle);
+
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ (void)HAL_UartTransferAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+#else
+ (void)HAL_UartAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+#endif
+#endif
+ (void)HAL_UartDeinit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ serialUartHandle->tx.busy = 0U;
+ serialUartHandle->rx.busy = 0U;
+#endif
+
+ return kStatus_SerialManager_Success;
+}
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
+{
+ serial_uart_state_t *serialUartHandle;
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ hal_uart_transfer_t transfer;
+#endif
+
+ assert(serialHandle);
+ assert(buffer);
+ assert(length);
+
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+ if (serialUartHandle->tx.busy != 0U)
+ {
+ return kStatus_SerialManager_Busy;
+ }
+ serialUartHandle->tx.busy = 1U;
+
+ serialUartHandle->tx.buffer = buffer;
+ serialUartHandle->tx.length = length;
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ transfer.data = buffer;
+ transfer.dataSize = length;
+ if (kStatus_HAL_UartSuccess !=
+ HAL_UartTransferSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer))
+#else
+ if (kStatus_HAL_UartSuccess !=
+ HAL_UartSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length))
+#endif
+ {
+ serialUartHandle->tx.busy = 0U;
+ return kStatus_SerialManager_Error;
+ }
+ return kStatus_SerialManager_Success;
+}
+
+#else
+
+serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
+{
+ serial_uart_state_t *serialUartHandle;
+
+ assert(serialHandle);
+ assert(buffer);
+ assert(length);
+
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+ return (serial_manager_status_t)HAL_UartSendBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
+ buffer, length);
+}
+
+serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
+{
+ serial_uart_state_t *serialUartHandle;
+
+ assert(serialHandle);
+ assert(buffer);
+ assert(length);
+
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+ return (serial_manager_status_t)HAL_UartReceiveBlocking(
+ ((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length);
+}
+
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle)
+{
+ serial_uart_state_t *serialUartHandle;
+ serial_manager_callback_message_t msg;
+ uint32_t primask;
+ uint8_t isBusy = 0U;
+
+ assert(serialHandle);
+
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+ primask = DisableGlobalIRQ();
+ isBusy = serialUartHandle->tx.busy;
+ serialUartHandle->tx.busy = 0U;
+ EnableGlobalIRQ(primask);
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ (void)HAL_UartTransferAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+#else
+ (void)HAL_UartAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+#endif
+ if (isBusy != 0U)
+ {
+ if ((NULL != serialUartHandle->tx.callback))
+ {
+ msg.buffer = serialUartHandle->tx.buffer;
+ msg.length = serialUartHandle->tx.length;
+ serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &msg, kStatus_SerialManager_Canceled);
+ }
+ }
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam)
+{
+ serial_uart_state_t *serialUartHandle;
+
+ assert(serialHandle);
+
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+ serialUartHandle->tx.callback = callback;
+ serialUartHandle->tx.callbackParam = callbackParam;
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam)
+{
+ serial_uart_state_t *serialUartHandle;
+
+ assert(serialHandle);
+
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+ serialUartHandle->rx.callback = callback;
+ serialUartHandle->rx.callbackParam = callbackParam;
+
+ return kStatus_SerialManager_Success;
+}
+
+void Serial_UartIsrFunction(serial_handle_t serialHandle)
+{
+ serial_uart_state_t *serialUartHandle;
+
+ assert(serialHandle);
+
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+ HAL_UartIsrFunction(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+}
+#endif
+
+#endif
diff --git a/third_party/nxp/JN5189DK6/components/serial_manager/serial_port_uart.h b/third_party/nxp/JN5189DK6/components/serial_manager/serial_port_uart.h
new file mode 100755
index 0000000..2d5d21e
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/components/serial_manager/serial_port_uart.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SERIAL_PORT_UART_H__
+#define __SERIAL_PORT_UART_H__
+
+/*!
+ * @addtogroup serial_port_uart
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief serial port uart handle size*/
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#define SERIAL_PORT_UART_HANDLE_SIZE (166U)
+#else
+#define SERIAL_PORT_UART_HANDLE_SIZE (4U)
+#endif
+
+/*! @brief serial port uart parity mode*/
+typedef enum _serial_port_uart_parity_mode
+{
+ kSerialManager_UartParityDisabled = 0x0U, /*!< Parity disabled */
+ kSerialManager_UartParityEven = 0x1U, /*!< Parity even enabled */
+ kSerialManager_UartParityOdd = 0x2U, /*!< Parity odd enabled */
+} serial_port_uart_parity_mode_t;
+
+/*! @brief serial port uart stop bit count*/
+typedef enum _serial_port_uart_stop_bit_count
+{
+ kSerialManager_UartOneStopBit = 0U, /*!< One stop bit */
+ kSerialManager_UartTwoStopBit = 1U, /*!< Two stop bits */
+} serial_port_uart_stop_bit_count_t;
+
+/*! @brief serial port uart config struct*/
+typedef struct _serial_port_uart_config
+{
+ uint32_t clockRate; /*!< clock rate */
+ uint32_t baudRate; /*!< baud rate */
+ serial_port_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
+ serial_port_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
+ uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information
+ please refer to the SOC corresponding RM. */
+ uint8_t enableRx; /*!< Enable RX */
+ uint8_t enableTx; /*!< Enable TX */
+} serial_port_uart_config_t;
+/*! @} */
+#endif /* __SERIAL_PORT_UART_H__ */
diff --git a/third_party/nxp/JN5189DK6/components/uart/uart.h b/third_party/nxp/JN5189DK6/components/uart/uart.h
new file mode 100755
index 0000000..11db5c4
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/components/uart/uart.h
@@ -0,0 +1,475 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __HAL_UART_ADAPTER_H__
+#define __HAL_UART_ADAPTER_H__
+
+#if defined(FSL_RTOS_FREE_RTOS)
+#include "FreeRTOS.h"
+#endif
+
+/*!
+ * @addtogroup UART_Adapter
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Enable or disable UART adapter non-blocking mode (1 - enable, 0 - disable) */
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+#define UART_ADAPTER_NON_BLOCKING_MODE (1U)
+#else
+#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE
+#define UART_ADAPTER_NON_BLOCKING_MODE (0U)
+#else
+#define UART_ADAPTER_NON_BLOCKING_MODE SERIAL_MANAGER_NON_BLOCKING_MODE
+#endif
+#endif
+
+#if defined(__GIC_PRIO_BITS)
+#define HAL_UART_ISR_PRIORITY (25U)
+#else
+#if defined(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
+#define HAL_UART_ISR_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
+#else
+/* The default value 3 is used to support different ARM Core, such as CM0P, CM4, CM7, and CM33, etc.
+ * The minimum number of priority bits implemented in the NVIC is 2 on these SOCs. The value of mininum
+ * priority is 3 (2^2 - 1). So, the default value is 3.
+ */
+#define HAL_UART_ISR_PRIORITY (3U)
+#endif
+#endif
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+#define HAL_UART_HANDLE_SIZE (90U)
+#else
+#define HAL_UART_HANDLE_SIZE (4U)
+#endif
+
+/*! @brief Whether enable transactional function of the UART. (0 - disable, 1 - enable) */
+#define HAL_UART_TRANSFER_MODE (0U)
+
+typedef void *hal_uart_handle_t;
+
+/*! @brief UART status */
+typedef enum _hal_uart_status
+{
+ kStatus_HAL_UartSuccess = kStatus_Success, /*!< Successfully */
+ kStatus_HAL_UartTxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 1), /*!< TX busy */
+ kStatus_HAL_UartRxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 2), /*!< RX busy */
+ kStatus_HAL_UartTxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 3), /*!< HAL UART transmitter is idle. */
+ kStatus_HAL_UartRxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 4), /*!< HAL UART receiver is idle */
+ kStatus_HAL_UartBaudrateNotSupport =
+ MAKE_STATUS(kStatusGroup_HAL_UART, 5), /*!< Baudrate is not support in current clock source */
+ kStatus_HAL_UartProtocolError = MAKE_STATUS(
+ kStatusGroup_HAL_UART,
+ 6), /*!< Error occurs for Noise, Framing, Parity, etc.
+ For transactional transfer, The up layer needs to abort the transfer and then starts again */
+ kStatus_HAL_UartError = MAKE_STATUS(kStatusGroup_HAL_UART, 7), /*!< Error occurs on HAL UART */
+} hal_uart_status_t;
+
+/*! @brief UART parity mode. */
+typedef enum _hal_uart_parity_mode
+{
+ kHAL_UartParityDisabled = 0x0U, /*!< Parity disabled */
+ kHAL_UartParityEven = 0x1U, /*!< Parity even enabled */
+ kHAL_UartParityOdd = 0x2U, /*!< Parity odd enabled */
+} hal_uart_parity_mode_t;
+
+/*! @brief UART stop bit count. */
+typedef enum _hal_uart_stop_bit_count
+{
+ kHAL_UartOneStopBit = 0U, /*!< One stop bit */
+ kHAL_UartTwoStopBit = 1U, /*!< Two stop bits */
+} hal_uart_stop_bit_count_t;
+
+/*! @brief UART configuration structure. */
+typedef struct _hal_uart_config
+{
+ uint32_t srcClock_Hz; /*!< Source clock */
+ uint32_t baudRate_Bps; /*!< Baud rate */
+ hal_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
+ hal_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
+ uint8_t enableRx; /*!< Enable RX */
+ uint8_t enableTx; /*!< Enable TX */
+ uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information please refer to the
+ SOC corresponding RM.
+ Invalid instance value will cause initialization failure. */
+} hal_uart_config_t;
+
+/*! @brief UART transfer callback function. */
+typedef void (*hal_uart_transfer_callback_t)(hal_uart_handle_t handle, hal_uart_status_t status, void *callbackParam);
+
+/*! @brief UART transfer structure. */
+typedef struct _hal_uart_transfer
+{
+ uint8_t *data; /*!< The buffer of data to be transfer.*/
+ size_t dataSize; /*!< The byte count to be transfer. */
+} hal_uart_transfer_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes a UART instance with the UART handle and the user configuration structure.
+ *
+ * This function configures the UART module with user-defined settings. The user can configure the configuration
+ * structure. The parameter handle is a pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by
+ * the caller. Example below shows how to use this API to configure the UART.
+ * @code
+ * uint8_t g_UartHandleBuffer[HAL_UART_HANDLE_SIZE];
+ * hal_uart_handle_t g_UartHandle = &g_UartHandleBuffer[0];
+ * hal_uart_config_t config;
+ * config.srcClock_Hz = 48000000;
+ * config.baudRate_Bps = 115200U;
+ * config.parityMode = kHAL_UartParityDisabled;
+ * config.stopBitCount = kHAL_UartOneStopBit;
+ * config.enableRx = 1;
+ * config.enableTx = 1;
+ * config.instance = 0;
+ * HAL_UartInit(g_UartHandle, &config);
+ * @endcode
+ *
+ * @param handle Pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by the caller.
+ * @param config Pointer to user-defined configuration structure.
+ * @retval kStatus_HAL_UartBaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_HAL_UartSuccess UART initialization succeed
+ */
+hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, hal_uart_config_t *config);
+
+/*!
+ * @brief Deinitializes a UART instance.
+ *
+ * This function waits for TX complete, disables TX and RX, and disables the UART clock.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_HAL_UartSuccess UART de-initialization succeed
+ */
+hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle);
+
+/*! @}*/
+
+/*!
+ * @name Blocking bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Reads RX data register using a blocking method.
+ *
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
+ * have data, and reads data from the RX register.
+ *
+ * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking
+ * cannot be used at the same time.
+ * And, the function #HAL_UartTransferAbortReceive cannot be used to abort the transmission of this function.
+ *
+ * @param handle UART handle pointer.
+ * @param data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ * @retval kStatus_HAL_UartError An error occurred while receiving data.
+ * @retval kStatus_HAL_UartParityError A parity error occurred while receiving data.
+ * @retval kStatus_HAL_UartSuccess Successfully received all data.
+ */
+hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
+
+/*!
+ * @brief Writes to the TX register using a blocking method.
+ *
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
+ * to have room and writes data to the TX buffer.
+ *
+ * @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking
+ * cannot be used at the same time.
+ * And, the function #HAL_UartTransferAbortSend cannot be used to abort the transmission of this function.
+ *
+ * @param handle UART handle pointer.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_HAL_UartSuccess Successfully sent all data.
+ */
+hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length);
+
+/*! @}*/
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+
+/*!
+ * @name Transactional
+ * @note The transactional API and the functional API cannot be used at the same time. The macro
+ * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the
+ * functional API with non-blocking mode will be used. Otherwise, transactional API will be used.
+ * @{
+ */
+
+/*!
+ * @brief Installs a callback and callback parameter.
+ *
+ * This function is used to install the callback and callback parameter for UART module.
+ * When any status of the UART changed, the driver will notify the upper layer by the installed callback
+ * function. And the status is also passed as status parameter when the callback is called.
+ *
+ * @param handle UART handle pointer.
+ * @param callback The callback function.
+ * @param callbackParam The parameter of the callback function.
+ * @retval kStatus_HAL_UartSuccess Successfully install the callback.
+ */
+hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle,
+ hal_uart_transfer_callback_t callback,
+ void *callbackParam);
+
+/*!
+ * @brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be received.
+ * The receive request is saved by the UART driver.
+ * When the new data arrives, the receive request is serviced first.
+ * When all data is received, the UART driver notifies the upper layer
+ * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle.
+ *
+ * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking
+ * cannot be used at the same time.
+ *
+ * @param handle UART handle pointer.
+ * @param transfer UART transfer structure, see #hal_uart_transfer_t.
+ * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue.
+ * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer);
+
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the ISR, the UART driver calls the callback
+ * function and passes the @ref kStatus_UART_TxIdle as status parameter.
+ *
+ * @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking
+ * cannot be used at the same time.
+ *
+ * @param handle UART handle pointer.
+ * @param transfer UART transfer structure. See #hal_uart_transfer_t.
+ * @retval kStatus_HAL_UartSuccess Successfully start the data transmission.
+ * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer);
+
+/*!
+ * @brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param handle UART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_HAL_UartError An error occurred.
+ * @retval kStatus_Success Get successfully through the parameter \p count.
+ */
+hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count);
+
+/*!
+ * @brief Gets the number of bytes written to the UART TX register.
+ *
+ * This function gets the number of bytes written to the UART TX
+ * register by using the interrupt method.
+ *
+ * @param handle UART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_HAL_UartError An error occurred.
+ * @retval kStatus_Success Get successfully through the parameter \p count.
+ */
+hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
+ * how many bytes are not received yet.
+ *
+ * @note The function #HAL_UartTransferAbortReceive cannot be used to abort the transmission of
+ * the function #HAL_UartReceiveBlocking.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the receiving.
+ */
+hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle);
+
+/*!
+ * @brief Aborts the interrupt-driven data sending.
+ *
+ * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out
+ * how many bytes are not sent out.
+ *
+ * @note The function #HAL_UartTransferAbortSend cannot be used to abort the transmission of
+ * the function #HAL_UartSendBlocking.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the sending.
+ */
+hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle);
+
+/*! @}*/
+
+#else
+
+/*!
+ * @name Functional API with non-blocking mode.
+ * @note The functional API and the transactional API cannot be used at the same time. The macro
+ * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the
+ * functional API with non-blocking mode will be used. Otherwise, transactional API will be used.
+ * @{
+ */
+
+/*!
+ * @brief Installs a callback and callback parameter.
+ *
+ * This function is used to install the callback and callback parameter for UART module.
+ * When non-blocking sending or receiving finished, the adapter will notify the upper layer by the installed callback
+ * function. And the status is also passed as status parameter when the callback is called.
+ *
+ * @param handle UART handle pointer.
+ * @param callback The callback function.
+ * @param callbackParam The parameter of the callback function.
+ * @retval kStatus_HAL_UartSuccess Successfully install the callback.
+ */
+hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle,
+ hal_uart_transfer_callback_t callback,
+ void *callbackParam);
+
+/*!
+ * @brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be received.
+ * The receive request is saved by the UART adapter.
+ * When the new data arrives, the receive request is serviced first.
+ * When all data is received, the UART adapter notifies the upper layer
+ * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle.
+ *
+ * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartReceiveNonBlocking
+ * cannot be used at the same time.
+ *
+ * @param handle UART handle pointer.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue.
+ * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
+
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the ISR, the UART driver calls the callback
+ * function and passes the @ref kStatus_UART_TxIdle as status parameter.
+ *
+ * @note The function #HAL_UartSendBlocking and the function #HAL_UartSendNonBlocking
+ * cannot be used at the same time.
+ *
+ * @param handle UART handle pointer.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_HAL_UartSuccess Successfully start the data transmission.
+ * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
+
+/*!
+ * @brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param handle UART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_HAL_UartError An error occurred.
+ * @retval kStatus_Success Get successfully through the parameter \p count.
+ */
+hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount);
+
+/*!
+ * @brief Gets the number of bytes written to the UART TX register.
+ *
+ * This function gets the number of bytes written to the UART TX
+ * register by using the interrupt method.
+ *
+ * @param handle UART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_HAL_UartError An error occurred.
+ * @retval kStatus_Success Get successfully through the parameter \p count.
+ */
+hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
+ * how many bytes are not received yet.
+ *
+ * @note The function #HAL_UartAbortReceive cannot be used to abort the transmission of
+ * the function #HAL_UartReceiveBlocking.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the receiving.
+ */
+hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle);
+
+/*!
+ * @brief Aborts the interrupt-driven data sending.
+ *
+ * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out
+ * how many bytes are not sent out.
+ *
+ * @note The function #HAL_UartAbortSend cannot be used to abort the transmission of
+ * the function #HAL_UartSendBlocking.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the sending.
+ */
+hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle);
+
+/*! @}*/
+
+#endif
+#endif
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+/*!
+ * @brief UART IRQ handle function.
+ *
+ * This function handles the UART transmit and receive IRQ request.
+ *
+ * @param handle UART handle pointer.
+ */
+void HAL_UartIsrFunction(hal_uart_handle_t handle);
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+/*! @}*/
+#endif /* __HAL_UART_ADAPTER_H__ */
diff --git a/third_party/nxp/JN5189DK6/components/uart/usart_adapter.c b/third_party/nxp/JN5189DK6/components/uart/usart_adapter.c
new file mode 100755
index 0000000..9b04160
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/components/uart/usart_adapter.c
@@ -0,0 +1,629 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_usart.h"
+#include "fsl_flexcomm.h"
+
+#include "uart.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#ifndef NDEBUG
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
+#undef assert
+#define assert(n)
+#endif
+#endif
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+/*! @brief uart RX state structure. */
+typedef struct _hal_uart_receive_state
+{
+ volatile uint8_t *buffer;
+ volatile uint32_t bufferLength;
+ volatile uint32_t bufferSofar;
+} hal_uart_receive_state_t;
+
+/*! @brief uart TX state structure. */
+typedef struct _hal_uart_send_state
+{
+ volatile uint8_t *buffer;
+ volatile uint32_t bufferLength;
+ volatile uint32_t bufferSofar;
+} hal_uart_send_state_t;
+#endif
+/*! @brief uart state structure. */
+typedef struct _hal_uart_state
+{
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+ hal_uart_transfer_callback_t callback;
+ void *callbackParam;
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ usart_handle_t hardwareHandle;
+#endif
+ hal_uart_receive_state_t rx;
+ hal_uart_send_state_t tx;
+#endif
+ uint8_t instance;
+} hal_uart_state_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static USART_Type *const s_UsartAdapterBase[] = USART_BASE_PTRS;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+/* Array of USART IRQ number. */
+static const IRQn_Type s_UsartIRQ[] = USART_IRQS;
+#endif
+
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+static hal_uart_status_t HAL_UartGetStatus(status_t status)
+{
+ hal_uart_status_t uartStatus = kStatus_HAL_UartError;
+ switch (status)
+ {
+ case kStatus_Success:
+ uartStatus = kStatus_HAL_UartSuccess;
+ break;
+ case kStatus_USART_TxBusy:
+ uartStatus = kStatus_HAL_UartTxBusy;
+ break;
+ case kStatus_USART_RxBusy:
+ uartStatus = kStatus_HAL_UartRxBusy;
+ break;
+ case kStatus_USART_TxIdle:
+ uartStatus = kStatus_HAL_UartTxIdle;
+ break;
+ case kStatus_USART_RxIdle:
+ uartStatus = kStatus_HAL_UartRxIdle;
+ break;
+ case kStatus_USART_BaudrateNotSupport:
+ uartStatus = kStatus_HAL_UartBaudrateNotSupport;
+ break;
+ case kStatus_USART_NoiseError:
+ case kStatus_USART_FramingError:
+ case kStatus_USART_ParityError:
+ uartStatus = kStatus_HAL_UartProtocolError;
+ break;
+ default:
+ break;
+ }
+ return uartStatus;
+}
+#else
+static hal_uart_status_t HAL_UartGetStatus(status_t status)
+{
+ if (kStatus_Success == status)
+ {
+ return kStatus_HAL_UartSuccess;
+ }
+ else
+ {
+ return kStatus_HAL_UartError;
+ }
+}
+#endif
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+static void HAL_UartCallback(USART_Type *base, usart_handle_t *handle, status_t status, void *callbackParam)
+{
+ hal_uart_state_t *uartHandle;
+ hal_uart_status_t uartStatus = HAL_UartGetStatus(status);
+ assert(callbackParam);
+
+ uartHandle = (hal_uart_state_t *)callbackParam;
+
+ if (kStatus_HAL_UartProtocolError == uartStatus)
+ {
+ if (uartHandle->hardwareHandle.rxDataSize)
+ {
+ uartStatus = kStatus_HAL_UartError;
+ }
+ }
+
+ if (uartHandle->callback)
+ {
+ uartHandle->callback(uartHandle, uartStatus, uartHandle->callbackParam);
+ }
+}
+
+#else
+
+static void HAL_UartInterruptHandle(USART_Type *base, void *handle)
+{
+ hal_uart_state_t *uartHandle = (hal_uart_state_t *)handle;
+ uint32_t status;
+ uint8_t instance;
+
+ if (NULL == uartHandle)
+ {
+ return;
+ }
+ instance = uartHandle->instance;
+
+ status = USART_GetStatusFlags(s_UsartAdapterBase[instance]);
+
+ /* Receive data register full */
+ if ((USART_FIFOSTAT_RXNOTEMPTY_MASK & status) &&
+ (USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_RXLVL_MASK))
+ {
+ if (uartHandle->rx.buffer)
+ {
+ uartHandle->rx.buffer[uartHandle->rx.bufferSofar++] = USART_ReadByte(s_UsartAdapterBase[instance]);
+ if (uartHandle->rx.bufferSofar >= uartHandle->rx.bufferLength)
+ {
+ USART_DisableInterrupts(s_UsartAdapterBase[instance],
+ USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK);
+ uartHandle->rx.buffer = NULL;
+ if (uartHandle->callback)
+ {
+ uartHandle->callback(uartHandle, kStatus_HAL_UartRxIdle, uartHandle->callbackParam);
+ }
+ }
+ }
+ }
+
+ /* Send data register empty and the interrupt is enabled. */
+ if ((USART_FIFOSTAT_TXNOTFULL_MASK & status) &&
+ (USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_TXLVL_MASK))
+ {
+ if (uartHandle->tx.buffer)
+ {
+ USART_WriteByte(s_UsartAdapterBase[instance], uartHandle->tx.buffer[uartHandle->tx.bufferSofar++]);
+ if (uartHandle->tx.bufferSofar >= uartHandle->tx.bufferLength)
+ {
+ USART_DisableInterrupts(s_UsartAdapterBase[instance], USART_FIFOINTENCLR_TXLVL_MASK);
+ uartHandle->tx.buffer = NULL;
+ if (uartHandle->callback)
+ {
+ uartHandle->callback(uartHandle, kStatus_HAL_UartTxIdle, uartHandle->callbackParam);
+ }
+ }
+ }
+ }
+
+#if 1
+ USART_ClearStatusFlags(s_UsartAdapterBase[instance], status);
+#endif
+}
+#endif
+
+#endif
+
+hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, hal_uart_config_t *config)
+{
+ hal_uart_state_t *uartHandle;
+ usart_config_t usartConfig;
+ status_t status;
+ assert(handle);
+ assert(config);
+ assert(config->instance < (sizeof(s_UsartAdapterBase) / sizeof(USART_Type *)));
+ assert(s_UsartAdapterBase[config->instance]);
+
+ if (HAL_UART_HANDLE_SIZE < sizeof(hal_uart_state_t))
+ {
+ return kStatus_HAL_UartError;
+ }
+
+ USART_GetDefaultConfig(&usartConfig);
+ usartConfig.baudRate_Bps = config->baudRate_Bps;
+
+ if (kHAL_UartParityEven == config->parityMode)
+ {
+ usartConfig.parityMode = kUSART_ParityEven;
+ }
+ else if (kHAL_UartParityOdd == config->parityMode)
+ {
+ usartConfig.parityMode = kUSART_ParityOdd;
+ }
+ else
+ {
+ usartConfig.parityMode = kUSART_ParityDisabled;
+ }
+
+ if (kHAL_UartTwoStopBit == config->stopBitCount)
+ {
+ usartConfig.stopBitCount = kUSART_TwoStopBit;
+ }
+ else
+ {
+ usartConfig.stopBitCount = kUSART_OneStopBit;
+ }
+ usartConfig.enableRx = config->enableRx;
+ usartConfig.enableTx = config->enableTx;
+ usartConfig.txWatermark = kUSART_TxFifo0;
+ usartConfig.rxWatermark = kUSART_RxFifo1;
+
+ status = USART_Init(s_UsartAdapterBase[config->instance], &usartConfig, config->srcClock_Hz);
+
+ if (kStatus_Success != status)
+ {
+ return HAL_UartGetStatus(status);
+ }
+
+ uartHandle = (hal_uart_state_t *)handle;
+ uartHandle->instance = config->instance;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ USART_TransferCreateHandle(s_UsartAdapterBase[config->instance], &uartHandle->hardwareHandle,
+ (usart_transfer_callback_t)HAL_UartCallback, handle);
+#else
+ /* Enable interrupt in NVIC. */
+ FLEXCOMM_SetIRQHandler(s_UsartAdapterBase[config->instance], (flexcomm_irq_handler_t)HAL_UartInterruptHandle,
+ handle);
+ NVIC_SetPriority((IRQn_Type)s_UsartIRQ[config->instance], HAL_UART_ISR_PRIORITY);
+ EnableIRQ(s_UsartIRQ[config->instance]);
+#endif
+
+#endif
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+
+ assert(handle);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ USART_Deinit(s_UsartAdapterBase[uartHandle->instance]);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(data);
+ assert(length);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+ if (uartHandle->rx.buffer)
+ {
+ return kStatus_HAL_UartRxBusy;
+ }
+#endif
+
+ status = USART_ReadBlocking(s_UsartAdapterBase[uartHandle->instance], data, length);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(data);
+ assert(length);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+ if (uartHandle->tx.buffer)
+ {
+ return kStatus_HAL_UartTxBusy;
+ }
+#endif
+
+ USART_WriteBlocking(s_UsartAdapterBase[uartHandle->instance], data, length);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+
+hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle,
+ hal_uart_transfer_callback_t callback,
+ void *callbackParam)
+{
+ hal_uart_state_t *uartHandle;
+
+ assert(handle);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ uartHandle->callbackParam = callbackParam;
+ uartHandle->callback = callback;
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(transfer);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ status = USART_TransferReceiveNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle,
+ (usart_transfer_t *)transfer, NULL);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(transfer);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ status = USART_TransferSendNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle,
+ (usart_transfer_t *)transfer);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(count);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ status =
+ USART_TransferGetReceiveCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(count);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ status = USART_TransferGetSendCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ USART_TransferAbortReceive(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ USART_TransferAbortSend(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+#else
+
+/* None transactional API with non-blocking mode. */
+hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle,
+ hal_uart_transfer_callback_t callback,
+ void *callbackParam)
+{
+ hal_uart_state_t *uartHandle;
+
+ assert(handle);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ uartHandle->callbackParam = callbackParam;
+ uartHandle->callback = callback;
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(data);
+ assert(length);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (uartHandle->rx.buffer)
+ {
+ return kStatus_HAL_UartRxBusy;
+ }
+
+ uartHandle->rx.bufferLength = length;
+ uartHandle->rx.bufferSofar = 0;
+ uartHandle->rx.buffer = data;
+ USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_RXLVL_MASK);
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(data);
+ assert(length);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (uartHandle->tx.buffer)
+ {
+ return kStatus_HAL_UartTxBusy;
+ }
+ uartHandle->tx.bufferLength = length;
+ uartHandle->tx.bufferSofar = 0;
+ uartHandle->tx.buffer = (volatile uint8_t *)data;
+ USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_TXLVL_MASK);
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(reCount);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (uartHandle->rx.buffer)
+ {
+ *reCount = uartHandle->rx.bufferSofar;
+ return kStatus_HAL_UartSuccess;
+ }
+ return kStatus_HAL_UartError;
+}
+
+hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(seCount);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (uartHandle->tx.buffer)
+ {
+ *seCount = uartHandle->tx.bufferSofar;
+ return kStatus_HAL_UartSuccess;
+ }
+ return kStatus_HAL_UartError;
+}
+
+hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (uartHandle->rx.buffer)
+ {
+ USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance],
+ USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK);
+ uartHandle->rx.buffer = NULL;
+ }
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (uartHandle->tx.buffer)
+ {
+ USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENCLR_TXLVL_MASK);
+ uartHandle->tx.buffer = NULL;
+ }
+
+ return kStatus_HAL_UartSuccess;
+}
+
+#endif
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+
+void HAL_UartIsrFunction(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+#if 0
+ DisableIRQ(s_UsartIRQ[uartHandle->instance]);
+#endif
+ USART_TransferHandleIRQ(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
+#if 0
+ NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
+ EnableIRQ(s_UsartIRQ[uartHandle->instance]);
+#endif
+}
+
+#else
+
+void HAL_UartIsrFunction(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+#if 0
+ DisableIRQ(s_UsartIRQ[uartHandle->instance]);
+#endif
+ HAL_UartInterruptHandle(s_UsartAdapterBase[uartHandle->instance], (void *)uartHandle);
+#if 0
+ NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
+ EnableIRQ(s_UsartIRQ[uartHandle->instance]);
+#endif
+}
+
+#endif
+
+#endif
diff --git a/third_party/nxp/JN5189/JN5189.h b/third_party/nxp/JN5189DK6/devices/JN5189/JN5189.h
similarity index 95%
rename from third_party/nxp/JN5189/JN5189.h
rename to third_party/nxp/JN5189DK6/devices/JN5189/JN5189.h
index 8fff510..c171daa 100755
--- a/third_party/nxp/JN5189/JN5189.h
+++ b/third_party/nxp/JN5189DK6/devices/JN5189/JN5189.h
@@ -1,6 +1,8 @@
/*
** ###################################################################
-** Processors: JN5189HN
+** Processors: JN5188HN
+** JN5188THN
+** JN5189HN
** JN5189THN
**
** Compilers: GNU C Compiler
@@ -8,9 +10,9 @@
** Keil ARM C/C++ Compiler
** MCUXpresso Compiler
**
-** Reference manual: QN9090 User manual Rev.0.3 13 September 2018
+** Reference manual: JN5189UM_Rev.1.2 20 December 2018
** Version: rev. 1.0, 2018-07-31
-** Build: b190827
+** Build: b191225
**
** Abstract:
** CMSIS Peripheral Access Layer for JN5189
@@ -164,6 +166,63 @@
/* ----------------------------------------------------------------------------
+ -- Mapping Information
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*!
+ * @addtogroup dma_request
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the DMA hardware request
+ *
+ * Defines the structure for the DMA hardware request collections. The user can configure the
+ * hardware request to trigger the DMA transfer accordingly. The index
+ * of the hardware request varies according to the to SoC.
+ */
+typedef enum _dma_request_source
+{
+ kDmaRequestUsart0Rx = 0U, /**< USART 0 RX */
+ kDmaRequestUsart0Tx = 1U, /**< USART 0 TX */
+ kDmaRequestUsart1Rx = 2U, /**< USART 1 RX */
+ kDmaRequestUsart1Tx = 3U, /**< USART 1 TX */
+ kDmaRequestI2c0Slave = 4U, /**< I2C 0 Slave */
+ kDmaRequestI2c0Master = 5U, /**< I2C 0 Master */
+ kDmaRequestI2c1Slave = 6U, /**< I2C 1 Slave */
+ kDmaRequestI2c1Master = 7U, /**< I2C 1 Master */
+ kDmaRequestSpi0Rx = 8U, /**< SPI 0 RX */
+ kDmaRequestSpi0Tx = 9U, /**< SPI 0 TX */
+ kDmaRequestSpi1Rx = 10U, /**< SPI 1 RX */
+ kDmaRequestSpi1Tx = 11U, /**< SPI 1 TX */
+ kDmaRequestSPIFI = 12U, /**< SPIFI */
+ kDmaRequestI2c2Slave = 13U, /**< I2C 2 Slave */
+ kDmaRequestI2c2Master = 14U, /**< I2C 2 Master */
+ kDmaRequestDMIC0 = 15U, /**< DMIC Channel 0 */
+ kDmaRequestDMIC1 = 16U, /**< DMIC Channel 1 */
+ kDmaRequestHashRx = 17U, /**< Hash RX */
+ kDmaRequestHashTx = 18U, /**< Hash TX */
+} dma_request_source_t;
+
+/* @} */
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
+/* ----------------------------------------------------------------------------
-- Device Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -848,13 +907,6 @@
* damage the device. '11': Not used
*/
#define ADC_GPADC_CTRL0_TEST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GPADC_CTRL0_TEST_SHIFT)) & ADC_GPADC_CTRL0_TEST_MASK)
-#define ADC_GPADC_CTRL0_SEL_ATB_MASK (0x30000U)
-#define ADC_GPADC_CTRL0_SEL_ATB_SHIFT (16U)
-/*! SEL_ATB - Select analog test bus '00': normal mode '01': atb_p = out_ana(LDO_output) atb_n =
- * Vssa (LDO analog ground) '10': atb_p = out_ref (LDO output) atb_n = Vrefn (ADC negative
- * reference) '11': atb_p = out_ana (LDO output) atb_n = ADC (ADC analog ground)
- */
-#define ADC_GPADC_CTRL0_SEL_ATB(x) (((uint32_t)(((uint32_t)(x)) << ADC_GPADC_CTRL0_SEL_ATB_SHIFT)) & ADC_GPADC_CTRL0_SEL_ATB_MASK)
/*! @} */
/*! @name GPADC_CTRL1 - Third ADC Control register : ADC internal gain and offset */
@@ -906,22 +958,10 @@
/** AES - Register Layout Typedef */
typedef struct {
- union { /* offset: 0x0 */
- __IO uint32_t CFG; /**< AES Configuration register, offset: 0x0 */
- struct { /* offset: 0x0 */
- union { /* offset: 0x0 */
- __IO uint16_t CFG0_15; /**< AES Configuration register 0:15, offset: 0x0 */
- struct { /* offset: 0x0 */
- __IO uint8_t CFG0_7; /**< AES Configuration register 0:7, offset: 0x0 */
- __IO uint8_t CFG8_15; /**< AES Configuration register 8:15, offset: 0x1 */
- } CFGL;
- };
- __IO uint16_t CFG16_31; /**< AES Configuration register 16:31, offset: 0x2 */
- } CFG0_32;
- };
- __IO uint32_t CMD; /**< AES Command register, offset: 0x4 */
- __IO uint32_t STAT; /**< AES Status register, offset: 0x8 */
- __IO uint32_t CTR_INCR; /**< Counter Increment, offset: 0xC */
+ __IO uint32_t CFG; /**< Configuration, offset: 0x0 */
+ __IO uint32_t CMD; /**< Command, offset: 0x4 */
+ __IO uint32_t STAT; /**< Status, offset: 0x8 */
+ __IO uint32_t CTR_INCR; /**< Counter Increment. Increment value for HOLDING when in Counter modes, offset: 0xC */
uint8_t RESERVED_0[16];
__O uint32_t KEY[8]; /**< Bits of the AES key, array offset: 0x20, array step: 0x4 */
__O uint32_t INTEXT[4]; /**< Input text bits, array offset: 0x40, array step: 0x4 */
@@ -941,220 +981,127 @@
* @{
*/
-/*! @name CFG - AES Configuration register */
+/*! @name CFG - Configuration */
/*! @{ */
#define AES_CFG_PROC_EN_MASK (0x3U)
#define AES_CFG_PROC_EN_SHIFT (0U)
-/*! PROC_EN - Process type enable.
+/*! PROC_EN - Processing Mode Enable. 00: Reserved. 01: Encrypt/Decrypt Only. 10: GF128 Hash Only. 11: Encrypt/Decrypt and Hash.
*/
#define AES_CFG_PROC_EN(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_PROC_EN_SHIFT)) & AES_CFG_PROC_EN_MASK)
#define AES_CFG_GF128_SEL_MASK (0x4U)
#define AES_CFG_GF128_SEL_SHIFT (2U)
-/*! GF128_SEL - GF128 hash selection.
+/*! GF128_SEL - GF128 Select Mode. 0: GF128 Hash Input Text. 1: GF128 Hash Output Text.
*/
#define AES_CFG_GF128_SEL(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_GF128_SEL_SHIFT)) & AES_CFG_GF128_SEL_MASK)
#define AES_CFG_INTEXT_BSWAP_MASK (0x10U)
#define AES_CFG_INTEXT_BSWAP_SHIFT (4U)
-/*! INTEXT_BSWAP - Byte swap input text.
+/*! INTEXT_BSWAP - Input Text Byte Swap
*/
#define AES_CFG_INTEXT_BSWAP(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_INTEXT_BSWAP_SHIFT)) & AES_CFG_INTEXT_BSWAP_MASK)
#define AES_CFG_INTEXT_WSWAP_MASK (0x20U)
#define AES_CFG_INTEXT_WSWAP_SHIFT (5U)
-/*! INTEXT_WSWAP - Word swap input text.
+/*! INTEXT_WSWAP - Input Text Word Swap
*/
#define AES_CFG_INTEXT_WSWAP(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_INTEXT_WSWAP_SHIFT)) & AES_CFG_INTEXT_WSWAP_MASK)
#define AES_CFG_OUTTEXT_BSWAP_MASK (0x40U)
#define AES_CFG_OUTTEXT_BSWAP_SHIFT (6U)
-/*! OUTTEXT_BSWAP - Byte swap output text.
+/*! OUTTEXT_BSWAP - Output Text Byte Swap
*/
#define AES_CFG_OUTTEXT_BSWAP(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_OUTTEXT_BSWAP_SHIFT)) & AES_CFG_OUTTEXT_BSWAP_MASK)
#define AES_CFG_OUTTEXT_WSWAP_MASK (0x80U)
#define AES_CFG_OUTTEXT_WSWAP_SHIFT (7U)
-/*! OUTTEXT_WSWAP - Word swap output text.
+/*! OUTTEXT_WSWAP - Output Text Word Swap
*/
#define AES_CFG_OUTTEXT_WSWAP(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_OUTTEXT_WSWAP_SHIFT)) & AES_CFG_OUTTEXT_WSWAP_MASK)
#define AES_CFG_KEY_CFG_MASK (0x300U)
#define AES_CFG_KEY_CFG_SHIFT (8U)
-/*! KEY_CFG - Key Configuration.
+/*! KEY_CFG - Key Configuration. 00: 128 Bit Key. 01: 192 Bit Key. 10: 256 Bit Key. 11: Reserved.
*/
#define AES_CFG_KEY_CFG(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_KEY_CFG_SHIFT)) & AES_CFG_KEY_CFG_MASK)
#define AES_CFG_INBLK_SEL_MASK (0x30000U)
#define AES_CFG_INBLK_SEL_SHIFT (16U)
-/*! INBLK_SEL - Input block select.
+/*! INBLK_SEL - Input Block Selection From: 00: Reserved. 01: Input Text. 10: Holding. 11: Input Text XOR Holding.
*/
#define AES_CFG_INBLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_INBLK_SEL_SHIFT)) & AES_CFG_INBLK_SEL_MASK)
#define AES_CFG_HOLD_SEL_MASK (0x300000U)
#define AES_CFG_HOLD_SEL_SHIFT (20U)
-/*! HOLD_SEL - Holding register source select.
+/*! HOLD_SEL - Holding Select From: 00: Counter. 01: Input Text. 10: Output Block. 11: Input Text XOR Output Block.
*/
#define AES_CFG_HOLD_SEL(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_HOLD_SEL_SHIFT)) & AES_CFG_HOLD_SEL_MASK)
#define AES_CFG_OUTTEXT_SEL_MASK (0x3000000U)
#define AES_CFG_OUTTEXT_SEL_SHIFT (24U)
-/*! OUTTEXT_SEL - Output text source select.
+/*! OUTTEXT_SEL - Output Text Selection From: 00: Output Block. 01: Output Block XOR Input Text. 10:
+ * Output Block XOR Holding. 11: Reserved.
*/
#define AES_CFG_OUTTEXT_SEL(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_OUTTEXT_SEL_SHIFT)) & AES_CFG_OUTTEXT_SEL_MASK)
/*! @} */
-/*! @name CFG0_15 - AES Configuration register 0:15 */
+/*! @name CMD - Command */
/*! @{ */
-#define AES_CFG0_15_PROC_EN_MASK (0x3U)
-#define AES_CFG0_15_PROC_EN_SHIFT (0U)
-/*! PROC_EN - Process type enable.
+#define AES_CMD_COPY_SKEY_MASK (0x1U)
+#define AES_CMD_COPY_SKEY_SHIFT (0U)
+/*! COPY_SKEY - Copies Secret Key and enables cipher. Secret key is typically held in OTP or other secure memory.
*/
-#define AES_CFG0_15_PROC_EN(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_PROC_EN_SHIFT)) & AES_CFG0_15_PROC_EN_MASK)
-#define AES_CFG0_15_GF128_SEL_MASK (0x4U)
-#define AES_CFG0_15_GF128_SEL_SHIFT (2U)
-/*! GF128_SEL - GF128 hash selection.
- */
-#define AES_CFG0_15_GF128_SEL(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_GF128_SEL_SHIFT)) & AES_CFG0_15_GF128_SEL_MASK)
-#define AES_CFG0_15_INTEXT_BSWAP_MASK (0x10U)
-#define AES_CFG0_15_INTEXT_BSWAP_SHIFT (4U)
-/*! INTEXT_BSWAP - Byte swap input text.
- */
-#define AES_CFG0_15_INTEXT_BSWAP(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_INTEXT_BSWAP_SHIFT)) & AES_CFG0_15_INTEXT_BSWAP_MASK)
-#define AES_CFG0_15_INTEXT_WSWAP_MASK (0x20U)
-#define AES_CFG0_15_INTEXT_WSWAP_SHIFT (5U)
-/*! INTEXT_WSWAP - Word swap input text.
- */
-#define AES_CFG0_15_INTEXT_WSWAP(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_INTEXT_WSWAP_SHIFT)) & AES_CFG0_15_INTEXT_WSWAP_MASK)
-#define AES_CFG0_15_OUTTEXT_BSWAP_MASK (0x40U)
-#define AES_CFG0_15_OUTTEXT_BSWAP_SHIFT (6U)
-/*! OUTTEXT_BSWAP - Byte swap output text.
- */
-#define AES_CFG0_15_OUTTEXT_BSWAP(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_OUTTEXT_BSWAP_SHIFT)) & AES_CFG0_15_OUTTEXT_BSWAP_MASK)
-#define AES_CFG0_15_OUTTEXT_WSWAP_MASK (0x80U)
-#define AES_CFG0_15_OUTTEXT_WSWAP_SHIFT (7U)
-/*! OUTTEXT_WSWAP - Word swap output text.
- */
-#define AES_CFG0_15_OUTTEXT_WSWAP(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_OUTTEXT_WSWAP_SHIFT)) & AES_CFG0_15_OUTTEXT_WSWAP_MASK)
-#define AES_CFG0_15_KEY_CFG_MASK (0x300U)
-#define AES_CFG0_15_KEY_CFG_SHIFT (8U)
-/*! KEY_CFG - Key Configuration.
- */
-#define AES_CFG0_15_KEY_CFG(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_KEY_CFG_SHIFT)) & AES_CFG0_15_KEY_CFG_MASK)
-/*! @} */
-
-/*! @name CFG0_7 - AES Configuration register 0:7 */
-/*! @{ */
-#define AES_CFG0_7_PROC_EN_MASK (0x3U)
-#define AES_CFG0_7_PROC_EN_SHIFT (0U)
-/*! PROC_EN - Process type enable.
- */
-#define AES_CFG0_7_PROC_EN(x) (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_PROC_EN_SHIFT)) & AES_CFG0_7_PROC_EN_MASK)
-#define AES_CFG0_7_GF128_SEL_MASK (0x4U)
-#define AES_CFG0_7_GF128_SEL_SHIFT (2U)
-/*! GF128_SEL - GF128 hash selection.
- */
-#define AES_CFG0_7_GF128_SEL(x) (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_GF128_SEL_SHIFT)) & AES_CFG0_7_GF128_SEL_MASK)
-#define AES_CFG0_7_INTEXT_BSWAP_MASK (0x10U)
-#define AES_CFG0_7_INTEXT_BSWAP_SHIFT (4U)
-/*! INTEXT_BSWAP - Byte swap input text.
- */
-#define AES_CFG0_7_INTEXT_BSWAP(x) (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_INTEXT_BSWAP_SHIFT)) & AES_CFG0_7_INTEXT_BSWAP_MASK)
-#define AES_CFG0_7_INTEXT_WSWAP_MASK (0x20U)
-#define AES_CFG0_7_INTEXT_WSWAP_SHIFT (5U)
-/*! INTEXT_WSWAP - Word swap input text.
- */
-#define AES_CFG0_7_INTEXT_WSWAP(x) (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_INTEXT_WSWAP_SHIFT)) & AES_CFG0_7_INTEXT_WSWAP_MASK)
-#define AES_CFG0_7_OUTTEXT_BSWAP_MASK (0x40U)
-#define AES_CFG0_7_OUTTEXT_BSWAP_SHIFT (6U)
-/*! OUTTEXT_BSWAP - Byte swap output text.
- */
-#define AES_CFG0_7_OUTTEXT_BSWAP(x) (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_OUTTEXT_BSWAP_SHIFT)) & AES_CFG0_7_OUTTEXT_BSWAP_MASK)
-#define AES_CFG0_7_OUTTEXT_WSWAP_MASK (0x80U)
-#define AES_CFG0_7_OUTTEXT_WSWAP_SHIFT (7U)
-/*! OUTTEXT_WSWAP - Word swap output text.
- */
-#define AES_CFG0_7_OUTTEXT_WSWAP(x) (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_OUTTEXT_WSWAP_SHIFT)) & AES_CFG0_7_OUTTEXT_WSWAP_MASK)
-/*! @} */
-
-/*! @name CFG8_15 - AES Configuration register 8:15 */
-/*! @{ */
-#define AES_CFG8_15_KEY_CFG_MASK (0x3U)
-#define AES_CFG8_15_KEY_CFG_SHIFT (0U)
-/*! KEY_CFG - Key Configuration.
- */
-#define AES_CFG8_15_KEY_CFG(x) (((uint8_t)(((uint8_t)(x)) << AES_CFG8_15_KEY_CFG_SHIFT)) & AES_CFG8_15_KEY_CFG_MASK)
-/*! @} */
-
-/*! @name CFG16_31 - AES Configuration register 16:31 */
-/*! @{ */
-#define AES_CFG16_31_INBLK_SEL_MASK (0x3U)
-#define AES_CFG16_31_INBLK_SEL_SHIFT (0U)
-/*! INBLK_SEL - Input block select.
- */
-#define AES_CFG16_31_INBLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG16_31_INBLK_SEL_SHIFT)) & AES_CFG16_31_INBLK_SEL_MASK)
-#define AES_CFG16_31_HOLD_SEL_MASK (0x30U)
-#define AES_CFG16_31_HOLD_SEL_SHIFT (4U)
-/*! HOLD_SEL - Holding register source select.
- */
-#define AES_CFG16_31_HOLD_SEL(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG16_31_HOLD_SEL_SHIFT)) & AES_CFG16_31_HOLD_SEL_MASK)
-#define AES_CFG16_31_OUTTEXT_SEL_MASK (0x300U)
-#define AES_CFG16_31_OUTTEXT_SEL_SHIFT (8U)
-/*! OUTTEXT_SEL - Output text source select.
- */
-#define AES_CFG16_31_OUTTEXT_SEL(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG16_31_OUTTEXT_SEL_SHIFT)) & AES_CFG16_31_OUTTEXT_SEL_MASK)
-/*! @} */
-
-/*! @name CMD - AES Command register */
-/*! @{ */
+#define AES_CMD_COPY_SKEY(x) (((uint32_t)(((uint32_t)(x)) << AES_CMD_COPY_SKEY_SHIFT)) & AES_CMD_COPY_SKEY_MASK)
#define AES_CMD_COPY_TO_Y_MASK (0x2U)
#define AES_CMD_COPY_TO_Y_SHIFT (1U)
-/*! COPY_TO_Y - Copy output text to GF128Y.
+/*! COPY_TO_Y - Copies Output Text to GF128 Y. Typically used for GCM where the Hash requires a Y
+ * input which is the result of an ECB encryption of 0s. Should be performed after encryption of 0s.
*/
#define AES_CMD_COPY_TO_Y(x) (((uint32_t)(((uint32_t)(x)) << AES_CMD_COPY_TO_Y_SHIFT)) & AES_CMD_COPY_TO_Y_MASK)
#define AES_CMD_SWITCH_MODE_MASK (0x10U)
#define AES_CMD_SWITCH_MODE_SHIFT (4U)
-/*! SWITCH_MODE - When this bit is set the mode switches from forward mode (encryption) to reverse
- * mode (decryption) or reverse mode to forward mode.
+/*! SWITCH_MODE - Switches mode from Forward to Reverse or from Reverse to Forward. Must wait for
+ * Idle after command. Typically used for non-counter modes (ECB, CBC, CFB, OFB) to switch from
+ * forward to reverse mode for decryption.
*/
#define AES_CMD_SWITCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << AES_CMD_SWITCH_MODE_SHIFT)) & AES_CMD_SWITCH_MODE_MASK)
#define AES_CMD_ABORT_MASK (0x100U)
#define AES_CMD_ABORT_SHIFT (8U)
-/*! ABORT - Aborts Encrypt/Decrypt and GF128 Hash operation.
+/*! ABORT - Aborts Encrypt/Decrypt and GF128 Hash, clears INTEXT, clears OUTTEXT, and clears HOLDING
*/
#define AES_CMD_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AES_CMD_ABORT_SHIFT)) & AES_CMD_ABORT_MASK)
#define AES_CMD_WIPE_MASK (0x200U)
#define AES_CMD_WIPE_SHIFT (9U)
-/*! WIPE - When set this bit performs abort, clears KEY and GF128_Y registers and disables cipher.
+/*! WIPE - Performs Abort, clears KEY, disables cipher, and clears GF128_Y
*/
#define AES_CMD_WIPE(x) (((uint32_t)(((uint32_t)(x)) << AES_CMD_WIPE_SHIFT)) & AES_CMD_WIPE_MASK)
/*! @} */
-/*! @name STAT - AES Status register */
+/*! @name STAT - Status */
/*! @{ */
#define AES_STAT_IDLE_MASK (0x1U)
#define AES_STAT_IDLE_SHIFT (0U)
-/*! IDLE - AES engine Idle.
+/*! IDLE - When set, all state machines are idle
*/
#define AES_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << AES_STAT_IDLE_SHIFT)) & AES_STAT_IDLE_MASK)
#define AES_STAT_IN_READY_MASK (0x2U)
#define AES_STAT_IN_READY_SHIFT (1U)
-/*! IN_READY - Input text ready.
+/*! IN_READY - When set, input Text can be written
*/
#define AES_STAT_IN_READY(x) (((uint32_t)(((uint32_t)(x)) << AES_STAT_IN_READY_SHIFT)) & AES_STAT_IN_READY_MASK)
#define AES_STAT_OUT_READY_MASK (0x4U)
#define AES_STAT_OUT_READY_SHIFT (2U)
-/*! OUT_READY - Output text ready.
+/*! OUT_READY - When set, output Text can be read
*/
#define AES_STAT_OUT_READY(x) (((uint32_t)(((uint32_t)(x)) << AES_STAT_OUT_READY_SHIFT)) & AES_STAT_OUT_READY_MASK)
#define AES_STAT_REVERSE_MASK (0x10U)
#define AES_STAT_REVERSE_SHIFT (4U)
-/*! REVERSE - Reverse mode.
+/*! REVERSE - When set, Cipher in reverse mode
*/
#define AES_STAT_REVERSE(x) (((uint32_t)(((uint32_t)(x)) << AES_STAT_REVERSE_SHIFT)) & AES_STAT_REVERSE_MASK)
#define AES_STAT_KEY_VALID_MASK (0x20U)
#define AES_STAT_KEY_VALID_SHIFT (5U)
-/*! KEY_VALID - Key valid.
+/*! KEY_VALID - When set, Key is valid
*/
#define AES_STAT_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << AES_STAT_KEY_VALID_SHIFT)) & AES_STAT_KEY_VALID_MASK)
/*! @} */
-/*! @name CTR_INCR - Counter Increment */
+/*! @name CTR_INCR - Counter Increment. Increment value for HOLDING when in Counter modes */
/*! @{ */
#define AES_CTR_INCR_CTR_INCR_MASK (0xFFFFFFFFU)
#define AES_CTR_INCR_CTR_INCR_SHIFT (0U)
-/*! CTR_INCR - Increment value for HOLDING register when in counter modes.
+/*! CTR_INCR - Counter Increment. Increment value for HOLDING when in Counter modes
*/
#define AES_CTR_INCR_CTR_INCR(x) (((uint32_t)(((uint32_t)(x)) << AES_CTR_INCR_CTR_INCR_SHIFT)) & AES_CTR_INCR_CTR_INCR_MASK)
/*! @} */
@@ -1436,11 +1383,6 @@
/*! ENABLE - Temperature sensor enable
*/
#define ASYNC_SYSCON_TEMPSENSORCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_TEMPSENSORCTRL_ENABLE_SHIFT)) & ASYNC_SYSCON_TEMPSENSORCTRL_ENABLE_MASK)
-#define ASYNC_SYSCON_TEMPSENSORCTRL_SLOPE_MASK (0x2U)
-#define ASYNC_SYSCON_TEMPSENSORCTRL_SLOPE_SHIFT (1U)
-/*! SLOPE - Temperature sensor sloe selection. 0x0: Unity gain slope; 0x1: Double gain slope; Only setting 0 should be used.
- */
-#define ASYNC_SYSCON_TEMPSENSORCTRL_SLOPE(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_TEMPSENSORCTRL_SLOPE_SHIFT)) & ASYNC_SYSCON_TEMPSENSORCTRL_SLOPE_MASK)
#define ASYNC_SYSCON_TEMPSENSORCTRL_CM_MASK (0xCU)
#define ASYNC_SYSCON_TEMPSENSORCTRL_CM_SHIFT (2U)
/*! CM - Temerature sensor common mode output voltage selection: 0x0: high negative offset added;
@@ -1509,11 +1451,6 @@
/*! I2C_SCL_EHS0 - I2C_SCL IO Driver slew rate LSB. (I2C_SCL_EHS1, I2C_SCL_EHS0). RESERVED: use default value (0)
*/
#define ASYNC_SYSCON_NFCTAGPADSCTRL_I2C_SCL_EHS0(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_NFCTAGPADSCTRL_I2C_SCL_EHS0_SHIFT)) & ASYNC_SYSCON_NFCTAGPADSCTRL_I2C_SCL_EHS0_MASK)
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_I2C_SCL_INVERT_MASK (0x800U)
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_I2C_SCL_INVERT_SHIFT (11U)
-/*! I2C_SCL_INVERT - I2C_SCL, Input polarity: 0: Input function is not inverted; 1: Input function is inverted.
- */
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_I2C_SCL_INVERT(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_NFCTAGPADSCTRL_I2C_SCL_INVERT_SHIFT)) & ASYNC_SYSCON_NFCTAGPADSCTRL_I2C_SCL_INVERT_MASK)
#define ASYNC_SYSCON_NFCTAGPADSCTRL_I2C_SCL_ENZI_MASK (0x1000U)
#define ASYNC_SYSCON_NFCTAGPADSCTRL_I2C_SCL_ENZI_SHIFT (12U)
/*! I2C_SCL_ENZI - I2C_SCL Receiver enable, active high
@@ -1536,16 +1473,6 @@
* Simulated open-drain output (high drive disabled).
*/
#define ASYNC_SYSCON_NFCTAGPADSCTRL_I2C_SCL_OD(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_NFCTAGPADSCTRL_I2C_SCL_OD_SHIFT)) & ASYNC_SYSCON_NFCTAGPADSCTRL_I2C_SCL_OD_MASK)
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_INT_EPD_MASK (0x10000U)
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_INT_EPD_SHIFT (16U)
-/*! INT_EPD - Reserved. NTAG INT/FD IO cell no longer supports pull-down
- */
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_INT_EPD(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_NFCTAGPADSCTRL_INT_EPD_SHIFT)) & ASYNC_SYSCON_NFCTAGPADSCTRL_INT_EPD_MASK)
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_INT_EPUN_MASK (0x20000U)
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_INT_EPUN_SHIFT (17U)
-/*! INT_EPUN - Reserved. NTAG INT/FD IO cell pull-up always on, not configurable
- */
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_INT_EPUN(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_NFCTAGPADSCTRL_INT_EPUN_SHIFT)) & ASYNC_SYSCON_NFCTAGPADSCTRL_INT_EPUN_MASK)
#define ASYNC_SYSCON_NFCTAGPADSCTRL_INT_INVERT_MASK (0x40000U)
#define ASYNC_SYSCON_NFCTAGPADSCTRL_INT_INVERT_SHIFT (18U)
/*! INT_INVERT - NTAG INT/FD Input polarity: 0: Input function is not inverted; 1: Input function is inverted.
@@ -1578,22 +1505,6 @@
* is to use default value (0)
*/
#define ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_EHS0(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_EHS0_SHIFT)) & ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_EHS0_MASK)
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_INVERT_MASK (0x1000000U)
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_INVERT_SHIFT (24U)
-/*! VDD_INVERT - NTAG VDD Input polarity: 0: Input function is not inverted; 1: Input function is inverted.
- */
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_INVERT(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_INVERT_SHIFT)) & ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_INVERT_MASK)
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_ENZI_MASK (0x2000000U)
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_ENZI_SHIFT (25U)
-/*! VDD_ENZI - NTAG VDD Receiver enable, active high
- */
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_ENZI(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_ENZI_SHIFT)) & ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_ENZI_MASK)
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_FILTEROFF_MASK (0x4000000U)
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_FILTEROFF_SHIFT (26U)
-/*! VDD_FILTEROFF - NTAG VDD input glitch filter control: 0: Filter enabled. Noise pulses below
- * approximately 10 ns are filtered out; 1: Filter disabled. No input filtering is done.
- */
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_FILTEROFF_SHIFT)) & ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_FILTEROFF_MASK)
#define ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_EHS1_MASK (0x8000000U)
#define ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_EHS1_SHIFT (27U)
/*! VDD_EHS1 - NTAG VDD IO Driver slew rate MSB. (VDD_EHS1, VDD_EHS0) sets IO cell speed when
@@ -1611,21 +1522,11 @@
/*! @name XTAL32MLDOCTRL - XTAL 32 MHz LDO control register. If XTAL has been auto started due to EFUSE XTAL32MSTART_ENA or BLE low power timers then the effect of these need disabling via SYSCON.XTAL32MCTRL before the full control by this register is possible. */
/*! @{ */
-#define ASYNC_SYSCON_XTAL32MLDOCTRL_BYPASS_MASK (0x1U)
-#define ASYNC_SYSCON_XTAL32MLDOCTRL_BYPASS_SHIFT (0U)
-/*! BYPASS - Activate LDO bypass, only required for test purposes.
- */
-#define ASYNC_SYSCON_XTAL32MLDOCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_XTAL32MLDOCTRL_BYPASS_SHIFT)) & ASYNC_SYSCON_XTAL32MLDOCTRL_BYPASS_MASK)
#define ASYNC_SYSCON_XTAL32MLDOCTRL_ENABLE_MASK (0x2U)
#define ASYNC_SYSCON_XTAL32MLDOCTRL_ENABLE_SHIFT (1U)
/*! ENABLE - Enable the LDO when set. Setting managed by software API.
*/
#define ASYNC_SYSCON_XTAL32MLDOCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_XTAL32MLDOCTRL_ENABLE_SHIFT)) & ASYNC_SYSCON_XTAL32MLDOCTRL_ENABLE_MASK)
-#define ASYNC_SYSCON_XTAL32MLDOCTRL_HIGHZ_MASK (0x4U)
-#define ASYNC_SYSCON_XTAL32MLDOCTRL_HIGHZ_SHIFT (2U)
-/*! HIGHZ - Put the output in high impedance state, only required for test purposes.
- */
-#define ASYNC_SYSCON_XTAL32MLDOCTRL_HIGHZ(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_XTAL32MLDOCTRL_HIGHZ_SHIFT)) & ASYNC_SYSCON_XTAL32MLDOCTRL_HIGHZ_MASK)
#define ASYNC_SYSCON_XTAL32MLDOCTRL_VOUT_MASK (0x38U)
#define ASYNC_SYSCON_XTAL32MLDOCTRL_VOUT_SHIFT (3U)
/*! VOUT - Adjust the output voltage level, setting managed by software API.
@@ -1734,16 +1635,6 @@
* amount of leakage current during power down.
*/
#define ASYNC_SYSCON_DCBUSCTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_DCBUSCTRL_ADDR_SHIFT)) & ASYNC_SYSCON_DCBUSCTRL_ADDR_MASK)
-#define ASYNC_SYSCON_DCBUSCTRL_MUX1_MASK (0x1E00U)
-#define ASYNC_SYSCON_DCBUSCTRL_MUX1_SHIFT (9U)
-/*! MUX1 - MUX1
- */
-#define ASYNC_SYSCON_DCBUSCTRL_MUX1(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_DCBUSCTRL_MUX1_SHIFT)) & ASYNC_SYSCON_DCBUSCTRL_MUX1_MASK)
-#define ASYNC_SYSCON_DCBUSCTRL_MUX2_MASK (0x1E000U)
-#define ASYNC_SYSCON_DCBUSCTRL_MUX2_SHIFT (13U)
-/*! MUX2 - MUX2
- */
-#define ASYNC_SYSCON_DCBUSCTRL_MUX2(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_DCBUSCTRL_MUX2_SHIFT)) & ASYNC_SYSCON_DCBUSCTRL_MUX2_MASK)
/*! @} */
/*! @name FREQMECTRL - Frequency measure register */
@@ -2180,9 +2071,10 @@
__IO uint32_t MCR; /**< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs., offset: 0x14 */
__IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
__IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */
- __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn.0 input., array offset: 0x2C, array step: 0x4 */
+ __I uint32_t CR[2]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn.0 input., array offset: 0x2C, array step: 0x4 */
+ uint8_t RESERVED_0[8];
__IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */
- uint8_t RESERVED_0[48];
+ uint8_t RESERVED_1[48];
__IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */
__IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */
} CTIMER_Type;
@@ -2407,7 +2299,7 @@
/*! @} */
/* The count of CTIMER_CR */
-#define CTIMER_CR_COUNT (4U)
+#define CTIMER_CR_COUNT (2U)
/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
/*! @{ */
@@ -3481,12 +3373,9 @@
__IO uint32_t AUTOPROG; /**< specifies what commands are performed on AHB write, offset: 0xC */
__IO uint32_t STARTA; /**< start address for next flash command, offset: 0x10 */
__IO uint32_t STOPA; /**< end address for next flash command, if command operates on address ranges, offset: 0x14 */
- __IO uint32_t TEST; /**< test configuration register, offset: 0x18 */
- __IO uint32_t PARW; /**< parity register; Memory parity data., offset: 0x1C */
- __IO uint32_t FSQ[4]; /**< Flexible SeQuence register 0-3, array offset: 0x20, array step: 0x4 */
- uint8_t RESERVED_1[80];
- __IO uint32_t DATAW[8]; /**< data register, word 0-7; Memory data, or command parameter, or command result., array offset: 0x80, array step: 0x4 */
- uint8_t RESERVED_2[3896];
+ uint8_t RESERVED_1[104];
+ __IO uint32_t DATAW[4]; /**< data register, word 0-3; Memory data, or command parameter, or command result., array offset: 0x80, array step: 0x4 */
+ uint8_t RESERVED_2[3912];
__O uint32_t INT_CLR_ENABLE; /**< Clear interrupt enable bits, offset: 0xFD8 */
__O uint32_t INT_SET_ENABLE; /**< Set interrupt enable bits, offset: 0xFDC */
__I uint32_t INT_STATUS; /**< Interrupt status bits, offset: 0xFE0 */
@@ -3566,72 +3455,17 @@
#define FLASH_STOPA_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STOPA_STOPA_SHIFT)) & FLASH_STOPA_STOPA_MASK)
/*! @} */
-/*! @name TEST - test configuration register */
-/*! @{ */
-#define FLASH_TEST_DCM1_MASK (0xFFU)
-#define FLASH_TEST_DCM1_SHIFT (0U)
-/*! DCM1 - These bit fields select which internal signal is brought onto the DCM1/2 pads
- */
-#define FLASH_TEST_DCM1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_TEST_DCM1_SHIFT)) & FLASH_TEST_DCM1_MASK)
-#define FLASH_TEST_DCM2_MASK (0xFF00U)
-#define FLASH_TEST_DCM2_SHIFT (8U)
-/*! DCM2 - These bit fields select which internal signal is brought onto the DCM1/2 pads
- */
-#define FLASH_TEST_DCM2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_TEST_DCM2_SHIFT)) & FLASH_TEST_DCM2_MASK)
-#define FLASH_TEST_EXT48_MASK (0x10000U)
-#define FLASH_TEST_EXT48_SHIFT (16U)
-/*! EXT48 - This bit controls the extclk48mhz controller output
- */
-#define FLASH_TEST_EXT48(x) (((uint32_t)(((uint32_t)(x)) << FLASH_TEST_EXT48_SHIFT)) & FLASH_TEST_EXT48_MASK)
-/*! @} */
-
-/*! @name PARW - parity register; Memory parity data. */
-/*! @{ */
-#define FLASH_PARW_PARW_MASK (0xFFFFFFFFU)
-#define FLASH_PARW_PARW_SHIFT (0U)
-/*! PARW - parity register; Memory parity data.
- */
-#define FLASH_PARW_PARW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_PARW_PARW_SHIFT)) & FLASH_PARW_PARW_MASK)
-/*! @} */
-
-/*! @name FSQ - Flexible SeQuence register 0-3 */
-/*! @{ */
-#define FLASH_FSQ_ST1_MASK (0xFFU)
-#define FLASH_FSQ_ST1_SHIFT (0U)
-/*! ST1 - Start state of sub-sequence 1
- */
-#define FLASH_FSQ_ST1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_FSQ_ST1_SHIFT)) & FLASH_FSQ_ST1_MASK)
-#define FLASH_FSQ_EN1_MASK (0xFF00U)
-#define FLASH_FSQ_EN1_SHIFT (8U)
-/*! EN1 - End state of sub-sequence 1
- */
-#define FLASH_FSQ_EN1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_FSQ_EN1_SHIFT)) & FLASH_FSQ_EN1_MASK)
-#define FLASH_FSQ_ST2_MASK (0xFF0000U)
-#define FLASH_FSQ_ST2_SHIFT (16U)
-/*! ST2 - Start state of sub-sequence 2
- */
-#define FLASH_FSQ_ST2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_FSQ_ST2_SHIFT)) & FLASH_FSQ_ST2_MASK)
-#define FLASH_FSQ_EN2_MASK (0xFF000000U)
-#define FLASH_FSQ_EN2_SHIFT (24U)
-/*! EN2 - End state of sub-sequence 2
- */
-#define FLASH_FSQ_EN2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_FSQ_EN2_SHIFT)) & FLASH_FSQ_EN2_MASK)
-/*! @} */
-
-/* The count of FLASH_FSQ */
-#define FLASH_FSQ_COUNT (4U)
-
-/*! @name DATAW - data register, word 0-7; Memory data, or command parameter, or command result. */
+/*! @name DATAW - data register, word 0-3; Memory data, or command parameter, or command result. */
/*! @{ */
#define FLASH_DATAW_DATAW_MASK (0xFFFFFFFFU)
#define FLASH_DATAW_DATAW_SHIFT (0U)
-/*! DATAW - data register, word 0-7; Memory data, or command parameter, or command result.
+/*! DATAW - data register, word 0-3; Memory data, or command parameter, or command result.
*/
#define FLASH_DATAW_DATAW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_DATAW_DATAW_SHIFT)) & FLASH_DATAW_DATAW_MASK)
/*! @} */
/* The count of FLASH_DATAW */
-#define FLASH_DATAW_COUNT (8U)
+#define FLASH_DATAW_COUNT (4U)
/*! @name INT_CLR_ENABLE - Clear interrupt enable bits */
/*! @{ */
@@ -6313,7 +6147,7 @@
/*! @{ */
#define IOCON_PIO_FUNC_MASK (0x7U)
#define IOCON_PIO_FUNC_SHIFT (0U)
-/*! FUNC - Selects digital function assigned to this pin. 0 is for GPIO mode. For other values, see IO mux
+/*! FUNC - Select digital function assigned to this pin.
* 0b000..Alternative connection 0.
* 0b001..Alternative connection 1.
* 0b010..Alternative connection 2.
@@ -6326,22 +6160,22 @@
#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK)
#define IOCON_PIO_EGP_MASK (0x8U)
#define IOCON_PIO_EGP_SHIFT (3U)
-/*! EGP - Enable GPIO mode of the IO cell. 0=IIC mode 1=GPIO mode.
+/*! EGP - GPIO Mode of IO Cell.
* 0b0..IIC mode.
* 0b1..GPIO mode.
*/
#define IOCON_PIO_EGP(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_EGP_SHIFT)) & IOCON_PIO_EGP_MASK)
#define IOCON_PIO_MODE_MASK (0x18U)
#define IOCON_PIO_MODE_SHIFT (3U)
-/*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control). For MFIO type ONLY
+/*! MODE - Select function mode (on-chip pull-up/pull-down resistor control). For MFIO type ONLY
* (all PIOs except PIO10 & 11): 0x0 : Pull-up. Pull-up resistor enabled. 0x1 : Repeater mode (bus
* keeper) 0x2 : Plain Input 0x3 : Pull-down. Pull-down resistor enabled. Note: When the register
* is related to a general purpose MFIO type pad (that is all PIOs except PIO10 & 11) - Bit [3]
* (of the register) is connected to EPD (enable pull-down) input of the MFIO pad. - Bit [4] (of
* the register) is connected to EPUN (enable pull-up NOT) input of MFIO pad.
* 0b00..Pull-up. Pull-up resistor enabled.
- * 0b01..Repeater. Repeater mode.
- * 0b10..Inactive. Inactive (no pull-down/pull-up resistor enabled).
+ * 0b01..Repeater. Repeater mode (bus keeper).
+ * 0b10..Inactive. Plain Input.
* 0b11..Pull-down. Pull-down resistor enabled.
*/
#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK)
@@ -6363,9 +6197,7 @@
#define IOCON_PIO_EHS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_EHS_SHIFT)) & IOCON_PIO_EHS_MASK)
#define IOCON_PIO_SLEW0_MASK (0x20U)
#define IOCON_PIO_SLEW0_SHIFT (5U)
-/*! SLEW0 - Driver slew rate. Note: -When the register is related to a general purpose MFIO type pad
- * (that is all PIOs except PIO10 & 11), this bit field (Bit [5]) is connected to EHS0 input of
- * the MFIO pad. To be used in combination with SLEW1 'EHS1'. The higher [EHS1,EHS0] the quicker.
+/*! SLEW0 - This bit field is used in combination with SLEW1. The higher [SLEW1,SLEW0] the quicker the IO cell slew rate.
* 0b0..Driver slew0 rate is disabled.
* 0b1..Driver slew0 rate is enabled.
*/
@@ -6391,53 +6223,44 @@
#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK)
#define IOCON_PIO_FILTEROFF_MASK (0x100U)
#define IOCON_PIO_FILTEROFF_SHIFT (8U)
-/*! FILTEROFF - Controls input glitch filter. 0 Filter enabled. Noise pulses below approximately 1ns
- * are filtered out. 1 Filter disabled. No input filtering is done.
+/*! FILTEROFF - Controls input glitch filter.
* 0b0..Filter enabled. Noise pulses below approximately 10 ns are filtered out.
* 0b1..Filter disabled. No input filtering is done.
*/
#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK)
#define IOCON_PIO_FSEL_MASK (0x200U)
#define IOCON_PIO_FSEL_SHIFT (9U)
-/*! FSEL - Controls input glitch filter when IO is in IIC mode.0 Noise pulses below approximately
- * 50ns are filtered out. 1 Noise pulses below approximately 10ns are filtered out. If IO is in
- * GPIO mode this control bit is irrelevant, a 3ns filter is used.
+/*! FSEL - Control Input Glitch Filter.
* 0b0..In IIC mode: Noise pulses below approximately 50ns are filtered out. In GPIO mode: A 3ns filter is used.
* 0b1..In IIC mode: Noise pulses below approximately 10ns are filtered out. In GPIO mode: A 3ns filter is used.
*/
#define IOCON_PIO_FSEL(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FSEL_SHIFT)) & IOCON_PIO_FSEL_MASK)
#define IOCON_PIO_SLEW1_MASK (0x200U)
#define IOCON_PIO_SLEW1_SHIFT (9U)
-/*! SLEW1 - Driver slew rate. Note, this bit field (Bit [9]) is connected to EHS1 input of the MFIO
- * pad. To be used in combination with SLEW0 'EHS0'. The higher [EHS1,EHS0] the quicker
+/*! SLEW1 - Driver Slew Rate. This bit is used in combination with SLEW0. The higher [SLEW1,SLEW0], the quicker the slew rate.
* 0b0..Driver slew1 rate is disabled.
* 0b1..Driver slew1 rate is enabled.
*/
#define IOCON_PIO_SLEW1(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW1_SHIFT)) & IOCON_PIO_SLEW1_MASK)
#define IOCON_PIO_OD_MASK (0x400U)
#define IOCON_PIO_OD_SHIFT (10U)
-/*! OD - Controls open-drain mode. 0 : Normal. Normal push-pull output 1 : Open-drain. Simulated
- * open-drain output (high drive disabled).
+/*! OD - Controls open-drain mode.
* 0b0..Normal. Normal push-pull output
* 0b1..Open-drain. Simulated open-drain output (high drive disabled).
*/
#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK)
#define IOCON_PIO_SSEL_MASK (0x800U)
#define IOCON_PIO_SSEL_SHIFT (11U)
-/*! SSEL - This bit controls the IO clamping function. - IO_CLAMP . Assert to freeze the IO. Also
- * needs SYSCON:RETENTIONCTRL set as well. Useful in power down mode. This mode is held through
- * power down cycle. Before releasing this mode on a wake-up, ensure the IO is set to the required
- * direction and value using GPIO DIR and PIN registers.
+/*! SSEL - This bit controls the IO clamping function.
* 0b0..This bit controls the IO clamping function is disabled.
* 0b1..This bit controls the IO clamping function is enabled.
*/
#define IOCON_PIO_SSEL(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SSEL_SHIFT)) & IOCON_PIO_SSEL_MASK)
#define IOCON_PIO_IO_CLAMP_MASK (0x1000U)
#define IOCON_PIO_IO_CLAMP_SHIFT (12U)
-/*! IO_CLAMP - IO_CLAMP = bit [12], assert to freeze the IO. Also needs SYSCON:RETENTIONCTRL set as
- * well. Useful in power down mode. This mode is held through power down cycle. Before releasing
- * this mode on a wake-up, ensure the IO is set to the required direction and value using GPIO
- * DIR and PIN registers.
+/*! IO_CLAMP - Assert to freeze the IO. Also needs SYSCON:RETENTIONCTRL set as well. Useful in power
+ * down mode. This mode is held through power down cycle. Before releasing this mode on a
+ * wake-up, ensure the IO is set to the required direction and value using GPIO DIR and PIN registers.
* 0b0..IO_CLAMP is disabled.
* 0b1..IO_CLAMP is enabled.
*/
@@ -6496,9 +6319,9 @@
__IO uint32_t MCRL_MSB; /**< Mute card Counter RST Low register (MSB), offset: 0x2C */
__IO uint32_t MCRH_LSB; /**< Mute card Counter RST High register (LSB), offset: 0x30 */
__IO uint32_t MCRH_MSB; /**< Mute card Counter RST High register (MSB), offset: 0x34 */
- __IO uint32_t SRR; /**< Slew Rate configuration Register, offset: 0x38 */
+ uint8_t RESERVED_0[4];
__IO uint32_t URR_UTR; /**< UART Receive Register / UART Transmit Register, offset: 0x3C */
- uint8_t RESERVED_0[12];
+ uint8_t RESERVED_1[12];
__O uint32_t TOR1; /**< Time-Out Register 1, offset: 0x4C */
__O uint32_t TOR2; /**< Time-Out Register 2, offset: 0x50 */
__O uint32_t TOR3; /**< Time-Out Register 3, offset: 0x54 */
@@ -6528,6 +6351,11 @@
* soft reset is finished by reading SSR register before any further action.
*/
#define ISO7816_SSR_SOFTRESETN(x) (((uint32_t)(((uint32_t)(x)) << ISO7816_SSR_SOFTRESETN_SHIFT)) & ISO7816_SSR_SOFTRESETN_MASK)
+#define ISO7816_SSR_SEQ_EN_MASK (0x2U)
+#define ISO7816_SSR_SEQ_EN_SHIFT (1U)
+/*! SEQ_EN - Set this bit to enable the sequencer. If this field is 0b, the sequencer will not respond to the Start control bit.
+ */
+#define ISO7816_SSR_SEQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ISO7816_SSR_SEQ_EN_SHIFT)) & ISO7816_SSR_SEQ_EN_MASK)
/*! @} */
/*! @name PDR1_LSB - Programmable Divider Register (LSB) slot 1. Least significant byte of a 16-bit counter defining the ETU. The ETU counter counts a number of cycles of the Contact Interface clock, this defines the ETU. The minimum acceptable value is 0001 0000b. */
@@ -6805,15 +6633,6 @@
#define ISO7816_MCRH_MSB_MCRH_MSB(x) (((uint32_t)(((uint32_t)(x)) << ISO7816_MCRH_MSB_MCRH_MSB_SHIFT)) & ISO7816_MCRH_MSB_MCRH_MSB_MASK)
/*! @} */
-/*! @name SRR - Slew Rate configuration Register */
-/*! @{ */
-#define ISO7816_SRR_SRR_MASK (0xFFFFFFFFU)
-#define ISO7816_SRR_SRR_SHIFT (0U)
-/*! SRR - Slew Rate configuration Register
- */
-#define ISO7816_SRR_SRR(x) (((uint32_t)(((uint32_t)(x)) << ISO7816_SRR_SRR_SHIFT)) & ISO7816_SRR_SRR_MASK)
-/*! @} */
-
/*! @name URR_UTR - UART Receive Register / UART Transmit Register */
/*! @{ */
#define ISO7816_URR_UTR_URR_UTR_MASK (0xFFFFFFFFU)
@@ -7761,29 +7580,28 @@
uint8_t RESERVED_1[12];
__IO uint32_t FRO192M; /**< High Speed FRO control register This reigster is controlled by the boot code and the Low power API software. [Reset by POR, RSTN, WDT ], offset: 0x40 */
__IO uint32_t FRO1M; /**< 1 MHz Free Running Oscillator control register. [Reset by all reset sources, except ARM SystemReset], offset: 0x44 */
- __IO uint32_t FRO32K; /**< 32 KHz Free Running Oscillator (FRO) control register. [Reset by POR, RSTN, WDT ], offset: 0x48 */
- __IO uint32_t XTAL32K; /**< 32 KHz Chrystal oscillator (XTAL) control register. [Reset by all reset sources, except ARM SystemReset], offset: 0x4C */
+ uint8_t RESERVED_2[8];
__IO uint32_t ANAMUXCOMP; /**< Analog Comparator and Analog Mux control register. [Reset by all reset sources, except ARM SystemReset], offset: 0x50 */
- uint8_t RESERVED_2[12];
+ uint8_t RESERVED_3[12];
__I uint32_t PWRSWACK; /**< Power Switch acknowledge. [Reset by all reset sources, except ARM SystemReset], offset: 0x60 */
__IO uint32_t DPDWKSRC; /**< Power Down and Deep Power Down wake-up source. [Reset by POR, RSTN, WDT ], offset: 0x64 */
__I uint32_t STATUSPWR; /**< Power OK and Ready signals from various analog modules (DCDC, LDO, ). [Reset by all reset sources, except ARM SystemReset], offset: 0x68 */
__I uint32_t STATUSCLK; /**< FRO and XTAL status register. [Reset by all reset sources, except ARM SystemReset], offset: 0x6C */
__IO uint32_t RESETCAUSE; /**< Reset Cause register. [Reset by POR], offset: 0x70 */
- uint8_t RESERVED_3[12];
+ uint8_t RESERVED_4[12];
__IO uint32_t AOREG0; /**< General purpose always on domain data storage. [Reset by all reset sources, except ARM SystemReset], offset: 0x80 */
__IO uint32_t AOREG1; /**< General purpose always on domain data storage. [Reset by POR, RSTN], offset: 0x84 */
__IO uint32_t AOREG2; /**< General purpose always on domain data storage. [Reset by POR, RSTN], offset: 0x88 */
- uint8_t RESERVED_4[12];
+ uint8_t RESERVED_5[12];
__IO uint32_t DPDCTRL; /**< Configuration parameters for Power Down and Deep Power Down mode. [Reset by POR, RSTN, WDT ], offset: 0x98 */
__I uint32_t PIOPORCAP; /**< The PIOPORCAP register captures the state of GPIO at power-on-reset or pin reset. Each bit represents the power-on reset state of one GPIO pin. [Reset by POR, RSTN], offset: 0x9C */
__I uint32_t PIORESCAP; /**< The PIORESCAP0 register captures the state of GPIO port 0 when a reset other than a power-on reset or pin reset occurs. Each bit represents the reset state of one GPIO pin. [Reset by WDT, BOD, WAKEUP IO, ARM System reset ], offset: 0xA0 */
- uint8_t RESERVED_5[12];
+ uint8_t RESERVED_6[12];
__IO uint32_t PDSLEEPCFG; /**< Controls the power to various modules in Low Power modes. [Reset by all reset sources, except ARM SystemReset], offset: 0xB0 */
- uint8_t RESERVED_6[4];
+ uint8_t RESERVED_7[4];
__IO uint32_t PDRUNCFG; /**< Controls the power to various analog blocks. [Reset by all reset sources, except ARM SystemReset], offset: 0xB8 */
__I uint32_t WAKEIOCAUSE; /**< Wake-up source from Power Down and Deep Power Down modes. Allow to identify the Wake-up source from Power-Down mode or Deep Power Down mode.[Reset by POR, RSTN, WDT ], offset: 0xBC */
- uint8_t RESERVED_7[12];
+ uint8_t RESERVED_8[12];
__IO uint32_t CTRLNORST; /**< Extension of CTRL register, but never reset except by POR, offset: 0xCC */
} PMC_Type;
@@ -7826,11 +7644,6 @@
* bit does not care. Do not set unless entering Deep Power Down.
*/
#define PMC_CTRL_NTAGWAKUPRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_NTAGWAKUPRESETENABLE_SHIFT)) & PMC_CTRL_NTAGWAKUPRESETENABLE_MASK)
-#define PMC_CTRL_SELCLOCK_MASK (0x80U)
-#define PMC_CTRL_SELCLOCK_SHIFT (7U)
-/*! SELCLOCK - Select PMC functional clock : 0: 1 MHz FRO; 1: 12 MHz FRO.
- */
-#define PMC_CTRL_SELCLOCK(x) (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_SELCLOCK_SHIFT)) & PMC_CTRL_SELCLOCK_MASK)
#define PMC_CTRL_SELLDOVOLTAGE_MASK (0x100U)
#define PMC_CTRL_SELLDOVOLTAGE_SHIFT (8U)
/*! SELLDOVOLTAGE - 0 = all LDOs current output levels are determined by their associated VADJ
@@ -7950,27 +7763,6 @@
/*! @name FRO192M - High Speed FRO control register This reigster is controlled by the boot code and the Low power API software. [Reset by POR, RSTN, WDT ] */
/*! @{ */
-#define PMC_FRO192M_TEMPTRIM_MASK (0x3FU)
-#define PMC_FRO192M_TEMPTRIM_SHIFT (0U)
-/*! TEMPTRIM - Temperature coefficient trimming bits. This field is used to give accurate frequency
- * for each device. The required setting is based upon calibration data sotred in OTP during
- * device test. This setting is applied by the clock driver function.
- */
-#define PMC_FRO192M_TEMPTRIM(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO192M_TEMPTRIM_SHIFT)) & PMC_FRO192M_TEMPTRIM_MASK)
-#define PMC_FRO192M_BIASTRIM_MASK (0xFC0U)
-#define PMC_FRO192M_BIASTRIM_SHIFT (6U)
-/*! BIASTRIM - Bias trimming bits (course frequency trimming). This field is used to give accurate
- * frequency for each device. The required setting is based upon calibration data sotred in OTP
- * during device test. This setting is applied by the clock driver function.
- */
-#define PMC_FRO192M_BIASTRIM(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO192M_BIASTRIM_SHIFT)) & PMC_FRO192M_BIASTRIM_MASK)
-#define PMC_FRO192M_DACTRIM_MASK (0xFF000U)
-#define PMC_FRO192M_DACTRIM_SHIFT (12U)
-/*! DACTRIM - Curdac trimming bits (fine frequency trimming). This field is used to give accurate
- * frequency for each device. The required setting is based upon calibration data sotred in OTP
- * during device test. This setting is applied by the clock driver function.
- */
-#define PMC_FRO192M_DACTRIM(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO192M_DACTRIM_SHIFT)) & PMC_FRO192M_DACTRIM_MASK)
#define PMC_FRO192M_DIVSEL_MASK (0x1F00000U)
#define PMC_FRO192M_DIVSEL_SHIFT (20U)
/*! DIVSEL - Mode of operation (which clock to output). Each bit enables a clocks as shown. Enables
@@ -7978,11 +7770,6 @@
* xxx1x: 32MHz enabled; xx1xx: 48MHz enabled; x1xxx: 64MHz enabled; 1xxxx: Not applicable.
*/
#define PMC_FRO192M_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO192M_DIVSEL_SHIFT)) & PMC_FRO192M_DIVSEL_MASK)
-#define PMC_FRO192M_ATBCTRL_MASK (0x6000000U)
-#define PMC_FRO192M_ATBCTRL_SHIFT (25U)
-/*! ATBCTRL - Debug control bits to set the analog/digital test modes; only required for test purposes.
- */
-#define PMC_FRO192M_ATBCTRL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO192M_ATBCTRL_SHIFT)) & PMC_FRO192M_ATBCTRL_MASK)
/*! @} */
/*! @name FRO1M - 1 MHz Free Running Oscillator control register. [Reset by all reset sources, except ARM SystemReset] */
@@ -8006,57 +7793,6 @@
#define PMC_FRO1M_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO1M_DIVSEL_SHIFT)) & PMC_FRO1M_DIVSEL_MASK)
/*! @} */
-/*! @name FRO32K - 32 KHz Free Running Oscillator (FRO) control register. [Reset by POR, RSTN, WDT ] */
-/*! @{ */
-#define PMC_FRO32K_NTAT_MASK (0xEU)
-#define PMC_FRO32K_NTAT_SHIFT (1U)
-/*! NTAT - Temperature coefficient trimming bits. After flash initialisation this field is
- * automatically updated by HW using a value from flash.
- */
-#define PMC_FRO32K_NTAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_NTAT_SHIFT)) & PMC_FRO32K_NTAT_MASK)
-#define PMC_FRO32K_PTAT_MASK (0x70U)
-#define PMC_FRO32K_PTAT_SHIFT (4U)
-/*! PTAT - Bias trimming bits (course frequency trimming). After flash initialisation this field is
- * automatically updated by HW using a value from flash.
- */
-#define PMC_FRO32K_PTAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_PTAT_SHIFT)) & PMC_FRO32K_PTAT_MASK)
-#define PMC_FRO32K_CAPCAL_MASK (0xFF80U)
-#define PMC_FRO32K_CAPCAL_SHIFT (7U)
-/*! CAPCAL - Capacitive dac calibration bits (fine frequency trimming). After flash initialisation
- * this field is automatically updated by HW using a value from flash.
- */
-#define PMC_FRO32K_CAPCAL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_CAPCAL_SHIFT)) & PMC_FRO32K_CAPCAL_MASK)
-#define PMC_FRO32K_ATBCTRL_MASK (0x30000U)
-#define PMC_FRO32K_ATBCTRL_SHIFT (16U)
-/*! ATBCTRL - Debug control bits to set the analog/digital test modes, only required for test purposes.
- */
-#define PMC_FRO32K_ATBCTRL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_ATBCTRL_SHIFT)) & PMC_FRO32K_ATBCTRL_MASK)
-/*! @} */
-
-/*! @name XTAL32K - 32 KHz Chrystal oscillator (XTAL) control register. [Reset by all reset sources, except ARM SystemReset] */
-/*! @{ */
-#define PMC_XTAL32K_IREF_MASK (0x6U)
-#define PMC_XTAL32K_IREF_SHIFT (1U)
-/*! IREF - Reference output current selection inputs; setting managed by clock driver function.
- */
-#define PMC_XTAL32K_IREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IREF_SHIFT)) & PMC_XTAL32K_IREF_MASK)
-#define PMC_XTAL32K_TEST_MASK (0x8U)
-#define PMC_XTAL32K_TEST_SHIFT (3U)
-/*! TEST - Oscillator Test Mode, only required for test purposes.
- */
-#define PMC_XTAL32K_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_TEST_SHIFT)) & PMC_XTAL32K_TEST_MASK)
-#define PMC_XTAL32K_IBIAS_MASK (0x30U)
-#define PMC_XTAL32K_IBIAS_SHIFT (4U)
-/*! IBIAS - Control of bias current in XTAL; setting managed by clock driver function.
- */
-#define PMC_XTAL32K_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IBIAS_SHIFT)) & PMC_XTAL32K_IBIAS_MASK)
-#define PMC_XTAL32K_AMPL_MASK (0xC0U)
-#define PMC_XTAL32K_AMPL_SHIFT (6U)
-/*! AMPL - Control of Amplitude of oscillation. 00 gives lowest amplitude; setting managed by clock driver function.
- */
-#define PMC_XTAL32K_AMPL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_AMPL_SHIFT)) & PMC_XTAL32K_AMPL_MASK)
-/*! @} */
-
/*! @name ANAMUXCOMP - Analog Comparator and Analog Mux control register. [Reset by all reset sources, except ARM SystemReset] */
/*! @{ */
#define PMC_ANAMUXCOMP_COMP_HYST_MASK (0x2U)
@@ -9689,20 +9425,18 @@
/** SHA - Register Layout Typedef */
typedef struct {
__IO uint32_t CTRL; /**< Control register, offset: 0x0 */
- __I uint32_t STATUS; /**< Status register, offset: 0x4 */
+ __I uint32_t STATUS; /**< Status Regsiter, offset: 0x4 */
__IO uint32_t INTENSET; /**< Interrupt Enable and Interrupt enable set function, offset: 0x8 */
- __O uint32_t INTENCLR; /**< Interrupt Clear register, offset: 0xC */
+ __O uint32_t INTENCLR; /**< Interrupt Clear Register, offset: 0xC */
__IO uint32_t MEMCTRL; /**< Setup Master to access memory, offset: 0x10 */
__IO uint32_t MEMADDR; /**< Address to start memory access from, offset: 0x14 */
uint8_t RESERVED_0[8];
__IO uint32_t INDATA[8]; /**< Input Data register, array offset: 0x20, array step: 0x4 */
__I uint32_t DIGEST[8]; /**< DIGEST or OUTD0, 5 or 8 bytes of output data, depending upon mode, array offset: 0x40, array step: 0x4 */
- uint8_t RESERVED_1[36];
- __I uint32_t CONFIG; /**< Indicates configuration status of block, showing features supported, offset: 0x84 */
- uint8_t RESERVED_2[8];
+ uint8_t RESERVED_1[48];
__IO uint32_t MASK; /**< Mask register, offset: 0x90 */
- uint8_t RESERVED_3[44];
- __I uint32_t OUTD[8]; /**< Remaining output data for 512bit mode, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_2[3944];
+ __I uint32_t ID; /**< IP identifier, offset: 0xFFC */
} SHA_Type;
/* ----------------------------------------------------------------------------
@@ -9718,7 +9452,7 @@
/*! @{ */
#define SHA_CTRL_MODE_MASK (0x7U)
#define SHA_CTRL_MODE_SHIFT (0U)
-/*! MODE - Operational mode: 0= Disabled; 1=SHA1; 2=SHA2-256; 3=SHA2-512; 4-7= Not valid
+/*! MODE - Operational mode: 0: Disabled; 1: SHA1; 2: SHA2-256; 3: SHA2-512; 4-7: Not valid
*/
#define SHA_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << SHA_CTRL_MODE_SHIFT)) & SHA_CTRL_MODE_MASK)
#define SHA_CTRL_NEW_MASK (0x10U)
@@ -9750,13 +9484,13 @@
#define SHA_CTRL_HASHSWPB(x) (((uint32_t)(((uint32_t)(x)) << SHA_CTRL_HASHSWPB_SHIFT)) & SHA_CTRL_HASHSWPB_MASK)
/*! @} */
-/*! @name STATUS - Status register */
+/*! @name STATUS - Status Regsiter */
/*! @{ */
#define SHA_STATUS_WAITING_MASK (0x1U)
#define SHA_STATUS_WAITING_SHIFT (0U)
-/*! WAITING - 0: Not waiting for data may be disabled or may be busy. Note that for cryptographic
- * uses, this is not set if IsLast is set nor will it set until at least 1 word is read of the
- * output. 1: Waiting for data to be written in (16 words)
+/*! WAITING - Waiting Status 0: Not waiting for data may be disabled or may be busy. Note that for
+ * cryptographic uses, this is not set if IsLast is set nor will it set until at least 1 word is
+ * read of the output. 1: Waiting for data to be written in (16 words)
*/
#define SHA_STATUS_WAITING(x) (((uint32_t)(((uint32_t)(x)) << SHA_STATUS_WAITING_SHIFT)) & SHA_STATUS_WAITING_MASK)
#define SHA_STATUS_DIGEST_MASK (0x2U)
@@ -9807,7 +9541,7 @@
#define SHA_INTENSET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENSET_ERROR_SHIFT)) & SHA_INTENSET_ERROR_MASK)
/*! @} */
-/*! @name INTENCLR - Interrupt Clear register */
+/*! @name INTENCLR - Interrupt Clear Register */
/*! @{ */
#define SHA_INTENCLR_WAITING_MASK (0x1U)
#define SHA_INTENCLR_WAITING_SHIFT (0U)
@@ -9831,7 +9565,7 @@
#define SHA_MEMCTRL_MASTER_MASK (0x1U)
#define SHA_MEMCTRL_MASTER_SHIFT (0U)
/*! MASTER - Enables Mastering. 0: Mastering is not used and the normal DMA or Interrupt based model
- * is used with INDATA 1: Mastering is enabled and DMA and INDATA should not be used
+ * is used with INDATA. 1: Mastering is enabled and DMA and INDATA should not be used.
*/
#define SHA_MEMCTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SHA_MEMCTRL_MASTER_SHIFT)) & SHA_MEMCTRL_MASTER_MASK)
#define SHA_MEMCTRL_COUNT_MASK (0x7FF0000U)
@@ -9876,30 +9610,6 @@
/* The count of SHA_DIGEST */
#define SHA_DIGEST_COUNT (8U)
-/*! @name CONFIG - Indicates configuration status of block, showing features supported */
-/*! @{ */
-#define SHA_CONFIG_DUAL_MASK (0x1U)
-#define SHA_CONFIG_DUAL_SHIFT (0U)
-/*! DUAL - 1 if 2 x 512 bit buffers, 0 if only 1 x 512 bit
- */
-#define SHA_CONFIG_DUAL(x) (((uint32_t)(((uint32_t)(x)) << SHA_CONFIG_DUAL_SHIFT)) & SHA_CONFIG_DUAL_MASK)
-#define SHA_CONFIG_DMA_MASK (0x2U)
-#define SHA_CONFIG_DMA_SHIFT (1U)
-/*! DMA - 1 if DMA is connected
- */
-#define SHA_CONFIG_DMA(x) (((uint32_t)(((uint32_t)(x)) << SHA_CONFIG_DMA_SHIFT)) & SHA_CONFIG_DMA_MASK)
-#define SHA_CONFIG_AHB_MASK (0x8U)
-#define SHA_CONFIG_AHB_SHIFT (3U)
-/*! AHB - 1 if AHB master is connected
- */
-#define SHA_CONFIG_AHB(x) (((uint32_t)(((uint32_t)(x)) << SHA_CONFIG_AHB_SHIFT)) & SHA_CONFIG_AHB_MASK)
-#define SHA_CONFIG_SHA512_MASK (0x20U)
-#define SHA_CONFIG_SHA512_SHIFT (5U)
-/*! SHA512 - 1 if SHA2-512 supported
- */
-#define SHA_CONFIG_SHA512(x) (((uint32_t)(((uint32_t)(x)) << SHA_CONFIG_SHA512_SHIFT)) & SHA_CONFIG_SHA512_MASK)
-/*! @} */
-
/*! @name MASK - Mask register */
/*! @{ */
#define SHA_MASK_MASK_MASK (0xFFFFFFFFU)
@@ -9909,18 +9619,30 @@
#define SHA_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << SHA_MASK_MASK_SHIFT)) & SHA_MASK_MASK_MASK)
/*! @} */
-/*! @name OUTD - Remaining output data for 512bit mode */
+/*! @name ID - IP identifier */
/*! @{ */
-#define SHA_OUTD_OUTPUT_MASK (0xFFFFFFFFU)
-#define SHA_OUTD_OUTPUT_SHIFT (0U)
-/*! OUTPUT - For SHA512 holds the remaining 8 output values.
+#define SHA_ID_APERTURE_MASK (0xFFU)
+#define SHA_ID_APERTURE_SHIFT (0U)
+/*! APERTURE - Aperture i.e. number minus 1 of consecutive packets 4 Kbytes reserved for this IP
*/
-#define SHA_OUTD_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << SHA_OUTD_OUTPUT_SHIFT)) & SHA_OUTD_OUTPUT_MASK)
+#define SHA_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SHA_ID_APERTURE_SHIFT)) & SHA_ID_APERTURE_MASK)
+#define SHA_ID_MIN_REV_MASK (0xF00U)
+#define SHA_ID_MIN_REV_SHIFT (8U)
+/*! MIN_REV - Minor revision i.e. with no software consequences
+ */
+#define SHA_ID_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << SHA_ID_MIN_REV_SHIFT)) & SHA_ID_MIN_REV_MASK)
+#define SHA_ID_MAJ_REV_MASK (0xF000U)
+#define SHA_ID_MAJ_REV_SHIFT (12U)
+/*! MAJ_REV - Major revision i.e. implies software modifications
+ */
+#define SHA_ID_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << SHA_ID_MAJ_REV_SHIFT)) & SHA_ID_MAJ_REV_MASK)
+#define SHA_ID_ID_MASK (0xFFFF0000U)
+#define SHA_ID_ID_SHIFT (16U)
+/*! ID - Identifier. This is the unique identifier of the module
+ */
+#define SHA_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SHA_ID_ID_SHIFT)) & SHA_ID_ID_MASK)
/*! @} */
-/* The count of SHA_OUTD */
-#define SHA_OUTD_COUNT (8U)
-
/*!
* @}
@@ -10317,22 +10039,6 @@
/*! DMARX - DMA configuration for receive.
*/
#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK)
-#define SPI_FIFOCFG_WAKETX_MASK (0x4000U)
-#define SPI_FIFOCFG_WAKETX_SHIFT (14U)
-/*! WAKETX - Wakeup for transmit FIFO level. This allows the device to be woken from reduced power
- * modes (up to power-down, as long as the peripheral function works in that power mode) without
- * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
- * CPU will remain stopped until woken by another cause, such as DMA completion.
- */
-#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK)
-#define SPI_FIFOCFG_WAKERX_MASK (0x8000U)
-#define SPI_FIFOCFG_WAKERX_SHIFT (15U)
-/*! WAKERX - Wakeup for receive FIFO level. This allows the device to be woken from reduced power
- * modes (up to power-down, as long as the peripheral function works in that power mode) without
- * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU
- * will remain stopped until woken by another cause, such as DMA completion.
- */
-#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK)
#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U)
#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U)
/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
@@ -10549,13 +10255,6 @@
* the CFG register.
*/
#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
-#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U)
-#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U)
-/*! TXSSEL3_N - Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the
- * pin is active LOW by default. Remark: The active state of the SSEL3 pin is configured by bits in
- * the CFG register.
- */
-#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK)
#define SPI_FIFOWR_EOT_MASK (0x100000U)
#define SPI_FIFOWR_EOT_SHIFT (20U)
/*! EOT - End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain
@@ -10619,14 +10318,6 @@
* pin is configured by the related SPOL bit in CFG.
*/
#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK)
-#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U)
-#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U)
-/*! RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved
- * along with received data. The value will reflect the SSEL3 pin for both master and slave
- * operation. A zero indicates that a slave select is active. The actual polarity of each slave select
- * pin is configured by the related SPOL bit in CFG.
- */
-#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK)
#define SPI_FIFORD_SOT_MASK (0x100000U)
#define SPI_FIFORD_SOT_SHIFT (20U)
/*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went
@@ -10668,14 +10359,6 @@
* pin is configured by the related SPOL bit in CFG.
*/
#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK)
-#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U)
-#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U)
-/*! RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved
- * along with received data. The value will reflect the SSEL3 pin for both master and slave
- * operation. A zero indicates that a slave select is active. The actual polarity of each slave select
- * pin is configured by the related SPOL bit in CFG.
- */
-#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK)
#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U)
#define SPI_FIFORDNOPOP_SOT_SHIFT (20U)
/*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went
@@ -11178,17 +10861,15 @@
__IO uint32_t RTC1HZCLKDIV; /**< Real Time Clock divider (1 Hz clock generation. The divider is fixed to 32768), offset: 0x3AC */
uint8_t RESERVED_21[76];
__IO uint32_t CLOCKGENUPDATELOCKOUT; /**< Control clock configuration registers access (like xxxDIV, xxxSEL), offset: 0x3FC */
- uint8_t RESERVED_22[404];
- __IO uint32_t EFUSECLKCTRL; /**< eFUSE/ OPT controller clock control, offset: 0x594 */
- uint8_t RESERVED_23[4];
+ uint8_t RESERVED_22[412];
__IO uint32_t RNGCLKCTRL; /**< Random Number Generator Clocks control, offset: 0x59C */
__IO uint32_t SRAMCTRL; /**< All SRAMs common control signals, offset: 0x5A0 */
- uint8_t RESERVED_24[40];
+ uint8_t RESERVED_23[40];
__IO uint32_t MODEMCTRL; /**< 32K clock enable, offset: 0x5CC */
- uint8_t RESERVED_25[4];
+ uint8_t RESERVED_24[4];
__IO uint32_t XTAL32KCAP; /**< XTAL 32 KHz oscillator Capacitor control, offset: 0x5D4 */
__IO uint32_t XTAL32MCTRL; /**< XTAL 32 MHz oscillator control register, offset: 0x5D8 */
- uint8_t RESERVED_26[164];
+ uint8_t RESERVED_25[164];
union { /* offset: 0x680 */
struct { /* offset: 0x680 */
__IO uint32_t STARTER0; /**< Start logic 0 wake-up enable register. Enable an interrupt for wake-up from deep-sleep mode. Some bits can also control wake-up from powerdown mode, offset: 0x680 */
@@ -11196,7 +10877,7 @@
} STARTER;
__IO uint32_t STARTERS[2]; /**< Pin assign register, array offset: 0x680, array step: 0x4 */
};
- uint8_t RESERVED_27[24];
+ uint8_t RESERVED_26[24];
union { /* offset: 0x6A0 */
struct { /* offset: 0x6A0 */
__O uint32_t STARTERSET0; /**< Set bits in STARTER0, offset: 0x6A0 */
@@ -11204,7 +10885,7 @@
} STARTERSET;
__IO uint32_t STARTERSETS[2]; /**< Pin assign register, array offset: 0x6A0, array step: 0x4 */
};
- uint8_t RESERVED_28[24];
+ uint8_t RESERVED_27[24];
union { /* offset: 0x6C0 */
struct { /* offset: 0x6C0 */
__O uint32_t STARTERCLR0; /**< Clear bits in STARTER0, offset: 0x6C0 */
@@ -11212,11 +10893,11 @@
} STARTERCLR;
__IO uint32_t STARTERCLRS[2]; /**< Pin assign register, array offset: 0x6C0, array step: 0x4 */
};
- uint8_t RESERVED_29[64];
+ uint8_t RESERVED_28[64];
__IO uint32_t RETENTIONCTRL; /**< I/O retention control register, offset: 0x708 */
- uint8_t RESERVED_30[252];
+ uint8_t RESERVED_29[252];
__IO uint32_t CPSTACK; /**< CPSTACK, offset: 0x808 */
- uint8_t RESERVED_31[500];
+ uint8_t RESERVED_30[500];
__IO uint32_t ANACTRL_CTRL; /**< Analog Interrupt control register. Requires AHBCLKCTRL0.ANA_INT_CTRL to be set., offset: 0xA00 */
__I uint32_t ANACTRL_VAL; /**< Analog modules (BOD and Analog Comparator) outputs current values (BOD 'Power OK' and Analog comparator out). Requires AHBCLKCTRL0.ANA_INT_CTRL to be set., offset: 0xA04 */
__IO uint32_t ANACTRL_STAT; /**< Analog modules (BOD and Analog Comparator) interrupt status. Requires AHBCLKCTRL0.ANA_INT_CTRL to be set., offset: 0xA08 */
@@ -11224,7 +10905,7 @@
__O uint32_t ANACTRL_INTENCLR; /**< Analog modules (BOD and Analog Comparator) Interrupt Enable Clear register. Writing ones clears the corresponding interrupt enable bits. Note, interrupt enable bits are set in ANACTRL_INTENSET. Requires AHBCLKCTRL0.ANA_INT_CTRL to be set to use this register., offset: 0xA10 */
__I uint32_t ANACTRL_INTSTAT; /**< Analog modules (BOD and Analog Comparator) Interrupt Status register (masked with interrupt enable). Requires AHBCLKCTRL0.ANA_INT_CTRL to be set to use this register. Interrupt status bit are cleared using ANACTRL_STAT., offset: 0xA14 */
__IO uint32_t CLOCK_CTRL; /**< Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measure function, offset: 0xA18 */
- uint8_t RESERVED_32[4];
+ uint8_t RESERVED_31[4];
__IO uint32_t WKT_CTRL; /**< Wake-up timers control, offset: 0xA20 */
__IO uint32_t WKT_LOAD_WKT0_LSB; /**< Wake-up timer 0 reload value least significant bits ([31:0])., offset: 0xA24 */
__IO uint32_t WKT_LOAD_WKT0_MSB; /**< Wake-up timer 0 reload value most significant bits ([8:0])., offset: 0xA28 */
@@ -11236,11 +10917,11 @@
__IO uint32_t WKT_INTENSET; /**< Interrupt Enable Read and Set register, offset: 0xA40 */
__O uint32_t WKT_INTENCLR; /**< Interrupt Enable Clear register, offset: 0xA44 */
__I uint32_t WKT_INTSTAT; /**< Interrupt Status register, offset: 0xA48 */
- uint8_t RESERVED_33[956];
+ uint8_t RESERVED_32[956];
__IO uint32_t GPIOPSYNC; /**< Enable bypass of the first stage of synchonization inside GPIO_INT module., offset: 0xE08 */
- uint8_t RESERVED_34[420];
+ uint8_t RESERVED_33[420];
__I uint32_t DIEID; /**< Chip revision ID & Number, offset: 0xFB0 */
- uint8_t RESERVED_35[60];
+ uint8_t RESERVED_34[60];
__O uint32_t CODESECURITYPROT; /**< Security code to allow test access via SWD/JTAG. Reset with POR, SW reset or BOD, offset: 0xFF0 */
} SYSCON_Type;
@@ -11261,28 +10942,6 @@
* 2: Vector Table in Flash. 3: Vector Table in Flash.
*/
#define SYSCON_MEMORYREMAP_MAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_MAP_SHIFT)) & SYSCON_MEMORYREMAP_MAP_MASK)
-#define SYSCON_MEMORYREMAP_FLASH_REMAP_APP_0_MASK (0x4U)
-#define SYSCON_MEMORYREMAP_FLASH_REMAP_APP_0_SHIFT (2U)
-/*! FLASH_REMAP_APP_0 - Controls remapping of Application 0 flash space. 0: No remapping of
- * Application 0 Flash space. 1: Remapping of Application 0 Flash space.
- */
-#define SYSCON_MEMORYREMAP_FLASH_REMAP_APP_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_FLASH_REMAP_APP_0_SHIFT)) & SYSCON_MEMORYREMAP_FLASH_REMAP_APP_0_MASK)
-#define SYSCON_MEMORYREMAP_FLASH_REMAP_APP_1_MASK (0x8U)
-#define SYSCON_MEMORYREMAP_FLASH_REMAP_APP_1_SHIFT (3U)
-/*! FLASH_REMAP_APP_1 - Controls remapping of Application 1 flash space. 0: No remapping of
- * Application 0 Flash space. 1: Remapping of Application 0 Flash space.
- */
-#define SYSCON_MEMORYREMAP_FLASH_REMAP_APP_1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_FLASH_REMAP_APP_1_SHIFT)) & SYSCON_MEMORYREMAP_FLASH_REMAP_APP_1_MASK)
-#define SYSCON_MEMORYREMAP_FLASH_APP_0_SIZE_MASK (0x7F0U)
-#define SYSCON_MEMORYREMAP_FLASH_APP_0_SIZE_SHIFT (4U)
-/*! FLASH_APP_0_SIZE - Application 0 flash size, in number of 8-KB units. Max allowed value is 80 (640 KB of Flash).
- */
-#define SYSCON_MEMORYREMAP_FLASH_APP_0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_FLASH_APP_0_SIZE_SHIFT)) & SYSCON_MEMORYREMAP_FLASH_APP_0_SIZE_MASK)
-#define SYSCON_MEMORYREMAP_FLASH_APP_1_SIZE_MASK (0x7F000U)
-#define SYSCON_MEMORYREMAP_FLASH_APP_1_SIZE_SHIFT (12U)
-/*! FLASH_APP_1_SIZE - Application 1 flash size, in number of 8-KB units. Max allowed value is 80 (640 KB of Flash).
- */
-#define SYSCON_MEMORYREMAP_FLASH_APP_1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_FLASH_APP_1_SIZE_SHIFT)) & SYSCON_MEMORYREMAP_FLASH_APP_1_SIZE_MASK)
#define SYSCON_MEMORYREMAP_QSPI_REMAP_APP_0_MASK (0x300000U)
#define SYSCON_MEMORYREMAP_QSPI_REMAP_APP_0_SHIFT (20U)
/*! QSPI_REMAP_APP_0 - Address bits to use when QSPI Flash address [19:18] = 0 (256-KB unit page). Setting 00 gives no remapping.
@@ -11366,11 +11025,6 @@
/*! @name PRESETCTRL0 - Peripheral reset control 0 */
/*! @{ */
-#define SYSCON_PRESETCTRL0_FLASH_RST_MASK (0x100U)
-#define SYSCON_PRESETCTRL0_FLASH_RST_SHIFT (8U)
-/*! FLASH_RST - Flash controller reset control. 0: Clear reset to this function. 1: Assert reset to this function.
- */
-#define SYSCON_PRESETCTRL0_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLASH_RST_MASK)
#define SYSCON_PRESETCTRL0_SPIFI_RST_MASK (0x400U)
#define SYSCON_PRESETCTRL0_SPIFI_RST_SHIFT (10U)
/*! SPIFI_RST - Quad SPI Flash controller reset control. 0: Clear reset to this function. 1: Assert reset to this function.
@@ -11439,11 +11093,6 @@
/*! ADC_RST - ADC reset control. 0: Clear reset to this function. 1: Assert reset to this function.
*/
#define SYSCON_PRESETCTRL0_ADC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC_RST_SHIFT)) & SYSCON_PRESETCTRL0_ADC_RST_MASK)
-#define SYSCON_PRESETCTRL0_EFUSE_RST_MASK (0x10000000U)
-#define SYSCON_PRESETCTRL0_EFUSE_RST_SHIFT (28U)
-/*! EFUSE_RST - eFUSE / OTP Controller APB bus interface reset. 0: Clear reset to this function. 1: Assert reset to this function.
- */
-#define SYSCON_PRESETCTRL0_EFUSE_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_EFUSE_RST_SHIFT)) & SYSCON_PRESETCTRL0_EFUSE_RST_MASK)
/*! @} */
/*! @name PRESETCTRL1 - Peripheral reset control 1 */
@@ -11542,11 +11191,6 @@
/*! @name PRESETCTRLSET0 - Set bits in PRESETCTRL0. It is recommended that changes to PRESETCTRL registers be accomplished by using the related PRESETCTRLSET and PRESETCTRLCLR registers. */
/*! @{ */
-#define SYSCON_PRESETCTRLSET0_FLASH_RST_SET_MASK (0x100U)
-#define SYSCON_PRESETCTRLSET0_FLASH_RST_SET_SHIFT (8U)
-/*! FLASH_RST_SET - Writing one to this register sets the FLASH_RST bit in the PRESETCTRL0 register
- */
-#define SYSCON_PRESETCTRLSET0_FLASH_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET0_FLASH_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET0_FLASH_RST_SET_MASK)
#define SYSCON_PRESETCTRLSET0_SPIFI_RST_SET_MASK (0x400U)
#define SYSCON_PRESETCTRLSET0_SPIFI_RST_SET_SHIFT (10U)
/*! SPIFI_RST_SET - Writing one to this register sets the SPIFI_RST bit in the PRESETCTRL0 register
@@ -11612,11 +11256,6 @@
/*! ADC_RST_SET - Writing one to this register sets the ADC_RST bit in the PRESETCTRL0 register
*/
#define SYSCON_PRESETCTRLSET0_ADC_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET0_ADC_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET0_ADC_RST_SET_MASK)
-#define SYSCON_PRESETCTRLSET0_EFUSE_RST_SET_MASK (0x10000000U)
-#define SYSCON_PRESETCTRLSET0_EFUSE_RST_SET_SHIFT (28U)
-/*! EFUSE_RST_SET - Writing one to this register sets the EFUSE_RST bit in the PRESETCTRL0 register
- */
-#define SYSCON_PRESETCTRLSET0_EFUSE_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET0_EFUSE_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET0_EFUSE_RST_SET_MASK)
/*! @} */
/*! @name PRESETCTRLSET1 - Set bits in PRESETCTRL1. It is recommended that changes to PRESETCTRL registers be accomplished by using the related PRESETCTRLSET and PRESETCTRLCLR registers. */
@@ -11715,11 +11354,6 @@
/*! @name PRESETCTRLCLR0 - Clear bits in PRESETCTRL0. It is recommended that changes to PRESETCTRL registers be accomplished by using the related PRESETCTRLSET and PRESETCTRLCLR registers. */
/*! @{ */
-#define SYSCON_PRESETCTRLCLR0_FLASH_RST_CLR_MASK (0x100U)
-#define SYSCON_PRESETCTRLCLR0_FLASH_RST_CLR_SHIFT (8U)
-/*! FLASH_RST_CLR - Writing one to this register clears the FLASH_RST bit in the PRESETCTRL0 register
- */
-#define SYSCON_PRESETCTRLCLR0_FLASH_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR0_FLASH_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR0_FLASH_RST_CLR_MASK)
#define SYSCON_PRESETCTRLCLR0_SPIFI_RST_CLR_MASK (0x400U)
#define SYSCON_PRESETCTRLCLR0_SPIFI_RST_CLR_SHIFT (10U)
/*! SPIFI_RST_CLR - Writing one to this register clears the SPIFI_RST bit in the PRESETCTRL0 register
@@ -11785,11 +11419,6 @@
/*! ADC_RST_CLR - Writing one to this register clears the ADC_RST bit in the PRESETCTRL0 register
*/
#define SYSCON_PRESETCTRLCLR0_ADC_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR0_ADC_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR0_ADC_RST_CLR_MASK)
-#define SYSCON_PRESETCTRLCLR0_EFUSE_RST_CLR_MASK (0x10000000U)
-#define SYSCON_PRESETCTRLCLR0_EFUSE_RST_CLR_SHIFT (28U)
-/*! EFUSE_RST_CLR - Writing one to this register clears the EFUSE_RST bit in the PRESETCTRL0 register
- */
-#define SYSCON_PRESETCTRLCLR0_EFUSE_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR0_EFUSE_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR0_EFUSE_RST_CLR_MASK)
/*! @} */
/*! @name PRESETCTRLCLR1 - Clear bits in PRESETCTRL1. It is recommended that changes to PRESETCTRL registers be accomplished by using the related PRESETCTRLSET and PRESETCTRLCLR registers. */
@@ -11888,11 +11517,6 @@
/*! @name AHBCLKCTRL0 - AHB Clock control 0 */
/*! @{ */
-#define SYSCON_AHBCLKCTRL0_ROM_MASK (0x2U)
-#define SYSCON_AHBCLKCTRL0_ROM_SHIFT (1U)
-/*! ROM - Enables the clock for the ROM. 0: Disable. 1: Enable.
- */
-#define SYSCON_AHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK)
#define SYSCON_AHBCLKCTRL0_SRAM_CTRL0_MASK (0x8U)
#define SYSCON_AHBCLKCTRL0_SRAM_CTRL0_SHIFT (3U)
/*! SRAM_CTRL0 - Enables the clock for the SRAM Controller 0 (SRAM 0 to SRAM 7). 0: Disable. 1: Enable.
@@ -11903,11 +11527,6 @@
/*! SRAM_CTRL1 - Enables the clock for the SRAM Controller 1 (SRAM 8 to SRAM 11). 0: Disable. 1: Enable.
*/
#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK)
-#define SYSCON_AHBCLKCTRL0_FLASH_MASK (0x100U)
-#define SYSCON_AHBCLKCTRL0_FLASH_SHIFT (8U)
-/*! FLASH - Enables the clock for the Flash controller. 0: Disable. 1: Enable.
- */
-#define SYSCON_AHBCLKCTRL0_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL0_FLASH_MASK)
#define SYSCON_AHBCLKCTRL0_SPIFI_MASK (0x400U)
#define SYSCON_AHBCLKCTRL0_SPIFI_SHIFT (10U)
/*! SPIFI - Enables the clock for the Quad SPI Flash controller [Note: SPIFI IOs need configuring
@@ -11975,11 +11594,6 @@
/*! ADC - Enables the clock for the ADC Controller. 0: Disable. 1: Enable.
*/
#define SYSCON_AHBCLKCTRL0_ADC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ADC_SHIFT)) & SYSCON_AHBCLKCTRL0_ADC_MASK)
-#define SYSCON_AHBCLKCTRL0_EFUSE_MASK (0x10000000U)
-#define SYSCON_AHBCLKCTRL0_EFUSE_SHIFT (28U)
-/*! EFUSE - Enables the (APB interface) clock for the EFUSE/ OTP Controller. 0: Disable. 1: Enable.
- */
-#define SYSCON_AHBCLKCTRL0_EFUSE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_EFUSE_SHIFT)) & SYSCON_AHBCLKCTRL0_EFUSE_MASK)
/*! @} */
/*! @name AHBCLKCTRL1 - AHB Clock control 1 */
@@ -12078,11 +11692,6 @@
/*! @name AHBCLKCTRLSET0 - Set bits in AHBCLKCTRL0 */
/*! @{ */
-#define SYSCON_AHBCLKCTRLSET0_ROM_CLK_SET_MASK (0x2U)
-#define SYSCON_AHBCLKCTRLSET0_ROM_CLK_SET_SHIFT (1U)
-/*! ROM_CLK_SET - Writing one to this register sets the ROM bit in the AHBCLKCTRL0 register.
- */
-#define SYSCON_AHBCLKCTRLSET0_ROM_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET0_ROM_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET0_ROM_CLK_SET_MASK)
#define SYSCON_AHBCLKCTRLSET0_SRAM_CTRL0_CLK_SET_MASK (0x8U)
#define SYSCON_AHBCLKCTRLSET0_SRAM_CTRL0_CLK_SET_SHIFT (3U)
/*! SRAM_CTRL0_CLK_SET - Writing one to this register sets the SRAM_CTRL0 bit in the AHBCLKCTRL0 register.
@@ -12093,11 +11702,6 @@
/*! SRAM_CTRL1_CLK_SET - Writing one to this register sets the SRAM_CTRL1 bit in the AHBCLKCTRL0 register.
*/
#define SYSCON_AHBCLKCTRLSET0_SRAM_CTRL1_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET0_SRAM_CTRL1_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET0_SRAM_CTRL1_CLK_SET_MASK)
-#define SYSCON_AHBCLKCTRLSET0_FLASH_CLK_SET_MASK (0x100U)
-#define SYSCON_AHBCLKCTRLSET0_FLASH_CLK_SET_SHIFT (8U)
-/*! FLASH_CLK_SET - Writing one to this register sets the FLASH bit in the AHBCLKCTRL0 register.
- */
-#define SYSCON_AHBCLKCTRLSET0_FLASH_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET0_FLASH_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET0_FLASH_CLK_SET_MASK)
#define SYSCON_AHBCLKCTRLSET0_SPIFI_CLK_SET_MASK (0x400U)
#define SYSCON_AHBCLKCTRLSET0_SPIFI_CLK_SET_SHIFT (10U)
/*! SPIFI_CLK_SET - Writing one to this register sets the SPIFI bit in the AHBCLKCTRL0 register.
@@ -12163,11 +11767,6 @@
/*! ADC_CLK_SET - Writing one to this register sets the ADC bit in the AHBCLKCTRL0 register.
*/
#define SYSCON_AHBCLKCTRLSET0_ADC_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET0_ADC_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET0_ADC_CLK_SET_MASK)
-#define SYSCON_AHBCLKCTRLSET0_EFUSE_CLK_SET_MASK (0x10000000U)
-#define SYSCON_AHBCLKCTRLSET0_EFUSE_CLK_SET_SHIFT (28U)
-/*! EFUSE_CLK_SET - Writing one to this register sets the EFUSE bit in the AHBCLKCTRL0 register.
- */
-#define SYSCON_AHBCLKCTRLSET0_EFUSE_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET0_EFUSE_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET0_EFUSE_CLK_SET_MASK)
/*! @} */
/*! @name AHBCLKCTRLSET1 - Set bits in AHBCLKCTRL1 */
@@ -12494,6 +12093,7 @@
* 0b011..32 MHz crystal oscillator (XTAL)
* 0b101..48 MHz free running oscillator (FRO)
* 0b110..1 MHz free running oscillator (FRO)
+ * 0b111..No clock
*/
#define SYSCON_CLKOUTSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK)
/*! @} */
@@ -12505,8 +12105,8 @@
/*! SEL - SPIFICLK clock source selection
* 0b000..CPU & System Bus clock
* 0b001..32 MHz crystal oscillator (XTAL)
- * 0b010..64 MHz free running oscillator (FRO)
- * 0b011..48 MHz free running oscillator (FRO)
+ * 0b010..No clock
+ * 0b011..No clock
* 0b100..No clock
* 0b101..No clock
* 0b110..No clock
@@ -12946,15 +12546,6 @@
#define SYSCON_CLOCKGENUPDATELOCKOUT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCKGENUPDATELOCKOUT_LOCK_SHIFT)) & SYSCON_CLOCKGENUPDATELOCKOUT_LOCK_MASK)
/*! @} */
-/*! @name EFUSECLKCTRL - eFUSE/ OPT controller clock control */
-/*! @{ */
-#define SYSCON_EFUSECLKCTRL_ENABLE_MASK (0x1U)
-#define SYSCON_EFUSECLKCTRL_ENABLE_SHIFT (0U)
-/*! ENABLE - Enable the eFUSE OTP controller IP clock (FRO 12 MHz)
- */
-#define SYSCON_EFUSECLKCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EFUSECLKCTRL_ENABLE_SHIFT)) & SYSCON_EFUSECLKCTRL_ENABLE_MASK)
-/*! @} */
-
/*! @name RNGCLKCTRL - Random Number Generator Clocks control */
/*! @{ */
#define SYSCON_RNGCLKCTRL_ENABLE_MASK (0x1U)
@@ -12971,51 +12562,6 @@
/*! SMB - SMB
*/
#define SYSCON_SRAMCTRL_SMB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAMCTRL_SMB_SHIFT)) & SYSCON_SRAMCTRL_SMB_MASK)
-#define SYSCON_SRAMCTRL_RM_MASK (0x1CU)
-#define SYSCON_SRAMCTRL_RM_SHIFT (2U)
-/*! RM - RM
- */
-#define SYSCON_SRAMCTRL_RM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAMCTRL_RM_SHIFT)) & SYSCON_SRAMCTRL_RM_MASK)
-#define SYSCON_SRAMCTRL_WM_MASK (0xE0U)
-#define SYSCON_SRAMCTRL_WM_SHIFT (5U)
-/*! WM - WM
- */
-#define SYSCON_SRAMCTRL_WM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAMCTRL_WM_SHIFT)) & SYSCON_SRAMCTRL_WM_MASK)
-#define SYSCON_SRAMCTRL_WRME_MASK (0x100U)
-#define SYSCON_SRAMCTRL_WRME_SHIFT (8U)
-/*! WRME - WRME
- */
-#define SYSCON_SRAMCTRL_WRME(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAMCTRL_WRME_SHIFT)) & SYSCON_SRAMCTRL_WRME_MASK)
-#define SYSCON_SRAMCTRL_RAM_MASK (0x1E00U)
-#define SYSCON_SRAMCTRL_RAM_SHIFT (9U)
-/*! RAM - RAM
- */
-#define SYSCON_SRAMCTRL_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAMCTRL_RAM_SHIFT)) & SYSCON_SRAMCTRL_RAM_MASK)
-#define SYSCON_SRAMCTRL_WAM_MASK (0x6000U)
-#define SYSCON_SRAMCTRL_WAM_SHIFT (13U)
-/*! WAM - WAM
- */
-#define SYSCON_SRAMCTRL_WAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAMCTRL_WAM_SHIFT)) & SYSCON_SRAMCTRL_WAM_MASK)
-#define SYSCON_SRAMCTRL_RAEN_MASK (0x8000U)
-#define SYSCON_SRAMCTRL_RAEN_SHIFT (15U)
-/*! RAEN - RAEN
- */
-#define SYSCON_SRAMCTRL_RAEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAMCTRL_RAEN_SHIFT)) & SYSCON_SRAMCTRL_RAEN_MASK)
-#define SYSCON_SRAMCTRL_WAEN_MASK (0x10000U)
-#define SYSCON_SRAMCTRL_WAEN_SHIFT (16U)
-/*! WAEN - WAEN
- */
-#define SYSCON_SRAMCTRL_WAEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAMCTRL_WAEN_SHIFT)) & SYSCON_SRAMCTRL_WAEN_MASK)
-#define SYSCON_SRAMCTRL_STBP_MASK (0x20000U)
-#define SYSCON_SRAMCTRL_STBP_SHIFT (17U)
-/*! STBP - STBP
- */
-#define SYSCON_SRAMCTRL_STBP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAMCTRL_STBP_SHIFT)) & SYSCON_SRAMCTRL_STBP_MASK)
-#define SYSCON_SRAMCTRL_VSBTEST_MASK (0x40000U)
-#define SYSCON_SRAMCTRL_VSBTEST_SHIFT (18U)
-/*! VSBTEST - VSBTEST
- */
-#define SYSCON_SRAMCTRL_VSBTEST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAMCTRL_VSBTEST_SHIFT)) & SYSCON_SRAMCTRL_VSBTEST_MASK)
/*! @} */
/*! @name MODEMCTRL - 32K clock enable */
@@ -15155,13 +14701,6 @@
* of WDWARNINT and WDWINDOW, otherwise a 'feed error' is created.
*/
#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK)
-#define WWDT_MOD_LOCK_MASK (0x20U)
-#define WWDT_MOD_LOCK_SHIFT (5U)
-/*! LOCK - Once this bit is set to one and a watchdog feed is performed, disabling or powering down
- * the watchdog oscillator is prevented by hardware. This bit can be set once by software and is
- * only cleared by any reset.
- */
-#define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK)
/*! @} */
/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */
@@ -15332,6 +14871,7 @@
#define DMIC_IRQn DMIC0_IRQn
#define HWVAD_IRQn HWVAD0_IRQn
#define AES256_Type AES_Type
+#define NTAG_IRQ NFCTag_IRQn
#define PRESETCTRL PRESETCTRLS
#define PRESETCTRLSET PRESETCTRLSETS
#define PRESETCTRLCLR PRESETCTRLCLRS
diff --git a/third_party/nxp/JN5189/JN5189_features.h b/third_party/nxp/JN5189DK6/devices/JN5189/JN5189_features.h
similarity index 63%
rename from third_party/nxp/JN5189/JN5189_features.h
rename to third_party/nxp/JN5189DK6/devices/JN5189/JN5189_features.h
index 1335bbe..219c60d 100755
--- a/third_party/nxp/JN5189/JN5189_features.h
+++ b/third_party/nxp/JN5189DK6/devices/JN5189/JN5189_features.h
@@ -1,13 +1,14 @@
/*
** ###################################################################
-** Version: rev. 1.0, 2016-05-09
-** Build: b160714
+** Version: rev. 1.0, 2018-07-31
+** Build: b191225
**
** Abstract:
** Chip specific module features.
**
** Copyright 2016 Freescale Semiconductor, Inc.
-** Copyright 2016-2018 NXP
+** Copyright 2016-2019 NXP
+** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
@@ -15,206 +16,227 @@
** mail: support@nxp.com
**
** Revisions:
-** - rev. 1.0 (2016-05-09)
+** - rev. 1.0 (2018-07-31)
** Initial version.
**
** ###################################################################
*/
-#ifndef _JN518X_FEATURES_H_
-#define _JN518X_FEATURES_H_
+#ifndef _JN5189_FEATURES_H_
+#define _JN5189_FEATURES_H_
/* SOC module features */
/* @brief ADC availability on the SoC. */
#define FSL_FEATURE_SOC_ADC_COUNT (1)
+/* @brief AES availability on the SoC. */
+#define FSL_FEATURE_SOC_AES_COUNT (1)
/* @brief ASYNC_SYSCON availability on the SoC. */
#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1)
-/* @brief CRC availability on the SoC. */
-#define FSL_FEATURE_SOC_CRC_COUNT (1)
+/* @brief CIC_IRB availability on the SoC. */
+#define FSL_FEATURE_SOC_CIC_IRB_COUNT (1)
+/* @brief CTIMER availability on the SoC. */
+#define FSL_FEATURE_SOC_CTIMER_COUNT (2)
/* @brief DMA availability on the SoC. */
#define FSL_FEATURE_SOC_DMA_COUNT (1)
-/* @brief Number of DMA channels on the SOC. */
+/* @brief DMIC availability on the SoC. */
+#define FSL_FEATURE_SOC_DMIC_COUNT (1)
+/* @brief FLASH availability on the SoC. */
+#define FSL_FEATURE_SOC_FLASH_COUNT (1)
+/* @brief FLEXCOMM availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (7)
+/* @brief GINT availability on the SoC. */
+#define FSL_FEATURE_SOC_GINT_COUNT (1)
+/* @brief I2C availability on the SoC. */
+#define FSL_FEATURE_SOC_I2C_COUNT (3)
+/* @brief INPUTMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
+/* @brief IOCON availability on the SoC. */
+#define FSL_FEATURE_SOC_IOCON_COUNT (1)
+/* @brief LPC_GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_LPC_GPIO_COUNT (1)
+/* @brief LPC_RTC availability on the SoC. */
+#define FSL_FEATURE_SOC_LPC_RTC_COUNT (1)
+/* @brief PINT availability on the SoC. */
+#define FSL_FEATURE_SOC_PINT_COUNT (1)
+/* @brief PMC availability on the SoC. */
+#define FSL_FEATURE_SOC_PMC_COUNT (1)
+/* @brief PWM availability on the SoC. */
+#define FSL_FEATURE_SOC_PWM_COUNT (1)
+/* @brief SHA availability on the SoC. */
+#define FSL_FEATURE_SOC_SHA_COUNT (1)
+/* @brief SPI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPI_COUNT (2)
+/* @brief SPIFI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPIFI_COUNT (1)
+/* @brief SYSCON availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
+/* @brief TRNG availability on the SoC. */
+#define FSL_FEATURE_SOC_TRNG_COUNT (1)
+/* @brief USART availability on the SoC. */
+#define FSL_FEATURE_SOC_USART_COUNT (2)
+/* @brief WWDT availability on the SoC. */
+#define FSL_FEATURE_SOC_WWDT_COUNT (1)
+
+/* ADC module features */
+
+/* @brief ADC data alignment mode. */
+#define FSL_FEATURE_ADC_DAT_OF_HIGH_ALIGNMENT (1)
+/* @brief ADC data alignment mode. */
+#define FSL_FEATURE_ADC_SYNCHRONOUS_USE_GPADC_CTRL (1)
+/* @brief Has no Calibration function. */
+#define FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC (1)
+/* @brief ADC has single SEQ. */
+#define FSL_FEATURE_ADC_HAS_SINGLE_SEQ (1)
+/* @brief Has ADC_INIT bitfile in STARTUP register. */
+#define FSL_FEATURE_ADC_HAS_STARTUP_ADC_INIT (0)
+/* @brief Has OFFSET_CAL bitfile in GPADC_CTRL1 reigster. */
+#define FSL_FEATURE_ADC_HAS_GPADC_CTRL1_OFFSET_CAL (1)
+/* @brief Has LDO_POWER_EN bitfile in GPADC_CTRL0 reigster. */
+#define FSL_FEATURE_ADC_HAS_GPADC_CTRL0_LDO_POWER_EN (1)
+/* @brief ADC require a delay. */
+#define FSL_FEATURE_ADC_REQUIRE_DELAY (1)
+/* @brief ADC TEMPSENSORCTRL in ASYNC_SYSCON. */
+#define FSL_FEATURE_ADC_ASYNC_SYSCON_TEMP (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (0)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (0)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (0)
+/* @brief Has ADTrim register */
+#define FSL_FEATURE_ADC_HAS_TRIM_REG (0)
+/* @brief Has Calibration register. */
+#define FSL_FEATURE_ADC_HAS_CALIB_REG (0)
+
+/* ASYNC_SYSCON module features */
+
+/* @brief FMEAS FMEAS_INDEX is 20. */
+#define FSL_FEATURE_FMEAS_INDEX_20 (1)
+/* @brief FMEAS FREQMECTRL in ASYNC_SYSCON. */
+#define FSL_FEATURE_FMEAS_ASYNC_SYSCON_FREQMECTRL (1)
+/* @brief FMEAS SYSCON use ASYNC_SYSCON. */
+#define FSL_FEATURE_FMEAS_USE_ASYNC_SYSCON (1)
+/* @brief FMEAS start frequency with ASYNC_SYSCON. */
+#define FSL_FEATURE_FMEAS_START_FRG_ASYNC_SYSCON (1)
+/* @brief FMEAS get frequency with ASYNC_SYSCON. */
+#define FSL_FEATURE_FMEAS_GET_FRG_ASYNC_SYSCON (1)
+/* @brief FMEAS get clock count with scale. */
+#define FSL_FEATURE_FMEAS_GET_COUNT_SCALE (1)
+/* @brief FMEAS start measure with scale. */
+#define FSL_FEATURE_FMEAS_STARTMEAS_SCALE (1)
+
+/* CTIMER module features */
+
+/* @brief CTIMER capture 3 interrupt. */
+#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1)
+/* @brief CTIMER has no capture channel. */
+#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (1)
+
+/* DMA module features */
+
+/* @brief Number of channels */
#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (19)
/* @brief Align size of DMA descriptor */
#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512)
/* @brief DMA head link descriptor table align size */
#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)
-/* @brief DMIC availability on the SoC. */
-#define FSL_FEATURE_SOC_DMIC_COUNT (1)
-/* @brief FLEXCOMM availability on the SoC. */
-#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (7)
-/* @brief GINT availability on the SoC. */
-#define FSL_FEATURE_SOC_GINT_COUNT (1)
-/* @brief GPIO availability on the SoC. */
-#define FSL_FEATURE_SOC_LPC_GPIO_COUNT (1)
-#define FSL_FEATURE_SOC_GPIO_COUNT FSL_FEATURE_SOC_LPC_GPIO_COUNT
-/* @brief I2C availability on the SoC. */
-#define FSL_FEATURE_SOC_I2C_COUNT (3)
-/* @brief I2C are FLEXCOMM on the SoC. */
-#define FSL_FEATURE_SOC_FLEXCOMM_I2C_COUNT FSL_FEATURE_SOC_I2C_COUNT
-/* @brief INPUTMUX availability on the SoC. */
-#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
-/* @brief IOCON availability on the SoC. */
-#define FSL_FEATURE_SOC_IOCON_COUNT (1)
-/* @brief MAILBOX availability on the SoC. */
-#define FSL_FEATURE_SOC_MAILBOX_COUNT (1)
-/* @brief MRT availability on the SoC. */
-#define FSL_FEATURE_SOC_MRT_COUNT (1)
-/* @brief PINT availability on the SoC. */
-#define FSL_FEATURE_SOC_PINT_COUNT (1)
-/* @brief RTC availability on the SoC. */
-#define FSL_FEATURE_SOC_LPC_RTC_COUNT (1)
-/* @brief SCT availability on the SoC. */
-#define FSL_FEATURE_SOC_SCT_COUNT (1)
-/* @brief SPI availability on the SoC. */
-#define FSL_FEATURE_SOC_SPI_COUNT (2)
-/* @brief SPI are FLEXCOMM on the SoC. */
-#define FSL_FEATURE_SOC_FLEXCOMM_SPI_COUNT FSL_FEATURE_SOC_SPI_COUNT
-/* @brief SPIFI availability on the SoC. */
-#define FSL_FEATURE_SOC_SPIFI_COUNT (1)
-/* @brief SYSCON availability on the SoC. */
-#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
-/* @brief CTIMER availability on the SoC. */
-#define FSL_FEATURE_SOC_CTIMER_COUNT (2)
-/* @brief USART availability on the SoC. */
-#define FSL_FEATURE_SOC_USART_COUNT (2)
-/* @brief USART availability on the SoC. */
-#define FSL_FEATURE_SOC_FLEXCOMM_USART_COUNT FSL_FEATURE_SOC_USART_COUNT
-/* @brief USB availability on the SoC. */
-#define FSL_FEATURE_SOC_UTICK_COUNT (1)
-/* @brief WWDT availability on the SoC. */
-#define FSL_FEATURE_SOC_WWDT_COUNT (1)
-/* @brief IRB availability on the SoC. */
-#define FSL_FEATURE_SOC_CIC_IRB_COUNT (1)
-/* @brief reduced functionality FLEXCOMM for low power JN518x family */
-#define FSL_REDUCED_FUNCTION_FLEXCOMM
-/* @brief PWM availability on the Soc */
-#define FSL_FEATURE_SOC_PWM_COUNT (10)
-
-/* @brief HASH/SHA availability on the SoC. */
-#define FSL_FEATURE_SOC_SHA_COUNT (1)
-/* @brief AES availability on the SoC. */
-#define FSL_FEATURE_SOC_AES_COUNT (1)
-
-/* @brief RNG availability on the SoC. */
-#define FSL_FEATURE_SOC_TRNG_COUNT (1)
-
-/* SPIFI module features */
-/* @brief SPIFI start address */
-#define FSL_FEATURE_SPIFI_START_ADDR (0x10000000)
-/* @brief SPIFI end address */
-#define FSL_FEATURE_SPIFI_END_ADDR (0x17FFFFFF)
-/* @brief SPIFI DATALEN bitfile in CMD register*/
-#define FSL_FEATURE_SPIFI_DATALEN_CTRL (1)
-
-/* @brief Pointer to ROM IAP entry functions */
-#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
-
-/* PINT module features */
-/* @brief Number of connected outputs */
-#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (4)
-/* @brief Number of PIOs */
-#define FSL_FEATURE_GPIO_PIO_COUNT (22)
-
-/* PMC module features */
-/* @brief FRO1M trim address */
-#define FSL_FEATURE_PMC_FRO1M_ADDRESS (0x9FCD0U)
-/* @brief FRO1M trim valid mask */
-#define FSL_FEATURE_PMC_FRO1M_VALID_MASK (0x1U)
-
-/* SPI module features */
-/* @brief SPI SIZE bitfile in FIFOCFG register */
-#define FSL_FEATURE_SPI_FIFOSIZE_CFG (1)
-/* @brief SPI has only three SSEL pins */
-#define FSL_FEATURE_IS_SPI_SSEL_PIN_COUNT_EQUAL_TO_THREE (1)
-
-/* ADC module features */
-/* @brief ADC data alignment mode */
-#define FSL_FEATURE_ADC_DAT_OF_HIGH_ALIGNMENT (1)
-/* @brief ADC synchronous mode do not modify CTRL.TSAMP [14:12] */
-#define FSL_FEATURE_ADC_SYNCHRONOUS_USE_GPADC_CTRL (1)
-/* @brief ADC temp cal flash addr */
-#define FSL_FEATURE_FLASH_ADDR_OF_TEMP_CAL (0x9FC80)
-/* @brief ADC temp cal flash data vaild mask*/
-#define FSL_FEATURE_FLASH_ADDR_OF_TEMP_CAL_VALID (0x1)
-/* @brief Has ASYNMODE bitfile in CTRL reigster. */
-#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1)
-/* @brief Has RESOL bitfile in CTRL reigster. */
-#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1)
-/* @brief Has BYPASSCAL bitfile in CTRL reigster. */
-#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (0)
-/* @brief Has TSAMP bitfile in CTRL reigster. */
-#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1)
-/* @brief ADC NO calibration*/
-#define FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC (1)
-/* @brief ADC TEMPSENSORCTRL in ASYNC_SYSCON*/
-#define FSL_FEATURE_ADC_ASYNC_SYSCON_TEMP (1)
-/* @brief ADC require a delay*/
-#define FSL_FEATURE_ADC_REQUIRE_DELAY (1)
-/* @brief Has LDO_POWER_EN bitfile in GPADC_CTRL0 register. */
-#define FSL_FEATURE_ADC_HAS_GPADC_CTRL0_LDO_POWER_EN (1)
-/* @brief Has OFFSET_CAL bitfile in GPADC_CTRL1 register. */
-#define FSL_FEATURE_ADC_HAS_GPADC_CTRL1_OFFSET_CAL (1)
-/* @brief Has ADC_INIT bitfile in STARTUP register. */
-#define FSL_FEATURE_ADC_HAS_STARTUP_ADC_INIT (0)
-/* @brief ADC has single SEQ */
-#define FSL_FEATURE_ADC_HAS_SINGLE_SEQ (1)
-/* SYSCON module features */
/* FLASH module features */
+
/* @brief P-Flash write unit size. */
#define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (512U)
/* @brief P-Flash sector size. */
#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (512U)
-/* @brief P-Flash block count */
+/* @brief P-Flash block count. */
#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
/* @brief P-Flash block size. */
#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0xA0000U)
+/* @brief ADC temp cal flash addr. */
+#define FSL_FEATURE_FLASH_ADDR_OF_TEMP_CAL (0x9FC80)
+/* @brief ADC temp cal flash data vaild mask. */
+#define FSL_FEATURE_FLASH_ADDR_OF_TEMP_CAL_VALID (0x1)
-/* CTIMER module features */
-/* @brief CTIMER capture channel 3. */
-#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1)
-/* @brief CTIMER capture 3 interrupt. */
-#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1)
+/* FLEXCOMM module features */
-/* WWDT module features */
-/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */
-#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (1)
-/* @brief WWDT NO PDCFG*/
-#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
+/* @brief Has no reset in FLEXCOMM register. */
+#define FSL_FEATURE_FLEXCOMM_HAS_NO_RESET (1)
+/* @brief USART availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCOMM_USART_COUNT (FSL_FEATURE_SOC_USART_COUNT)
+/* @brief SPI are FLEXCOMM on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCOMM_SPI_COUNT (FSL_FEATURE_SOC_SPI_COUNT)
+/* @brief I2C are FLEXCOMM on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCOMM_I2C_COUNT (FSL_FEATURE_SOC_I2C_COUNT)
+
+/* GPIO module features */
+
+/* @brief GPIO DIRSET and DIRCLR register. */
+#define FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR (1)
+/* @brief Number of PIOs. */
+#define FSL_FEATURE_GPIO_PIO_COUNT (22)
+/* @brief GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_GPIO_COUNT (FSL_FEATURE_SOC_LPC_GPIO_COUNT)
/* I2C module features */
-/* @brief I2C peripheral clock frequency 8MHz */
+
+/* @brief I2C peripheral clock frequency 8MHz. */
#define FSL_FEATURE_I2C_PREPCLKFRG_8MHZ (1)
-/* GPIO module feature */
-/* @brief GPIO DIRSET and DIRCLR register */
-#define FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR (1)
+/* IOCON module features */
-/* FMEAS module feature */
-/* @brief FMEAS FMEAS_INDEX is 20 */
-#define FSL_FEATURE_FMEAS_INDEX_20 (1)
-/* @brief FMEAS FREQMECTRL in ASYNC_SYSCON */
-#define FSL_FEATURE_FMEAS_ASYNC_SYSCON_FREQMECTRL (1)
-/* @brief FMEAS SYSCON use ASYNC_SYSCON */
-#define FSL_FEATURE_FMEAS_USE_ASYNC_SYSCON (1)
-/* @brief FMEAS start frequency with ASYNC_SYSCON */
-#define FSL_FEATURE_FMEAS_START_FRG_ASYNC_SYSCON (1)
-/* @brief FMEAS get frequency with ASYNC_SYSCON */
-#define FSL_FEATURE_FMEAS_GET_FRG_ASYNC_SYSCON (1)
-/* @brief FMEAS get clock count with scale */
-#define FSL_FEATURE_FMEAS_GET_COUNT_SCALE (1)
-/* @brief FMEAS start measure with scale */
-#define FSL_FEATURE_FMEAS_STARTMEAS_SCALE (1)
+/* @brief Func bit field width */
+#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (3)
+
+/* PINT module features */
+
+/* @brief Number of connected outputs */
+#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (4)
+
+/* PMC module features */
+
+/* @brief FRO1M trim address. */
+#define FSL_FEATURE_PMC_FRO1M_ADDRESS (0x9FCD0U)
+/* @brief FRO1M trim valid mask. */
+#define FSL_FEATURE_PMC_FRO1M_VALID_MASK (0x1U)
/* RTC module features */
+
/* @brief Has no separate RTC OSC PD in CTRL register. */
#define FSL_FEATURE_RTC_HAS_NO_OSC_PD (1)
-/* FLEXCOMM module features */
-/* @brief Has no reset in FLEXCOMM register. */
-#define FSL_FEATURE_FLEXCOMM_HAS_NO_RESET (1)
+/* SPI module features */
-#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (1)
-#endif /* _JN518X_FEATURES_H_ */
+/* @brief SPI SIZE bitfile in FIFOCFG register */
+#define FSL_FEATURE_SPI_FIFOSIZE_CFG (1)
+/* @brief SPI has only three SSEL pins */
+#define FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE (1)
+
+/* SPIFI module features */
+
+/* @brief SPIFI start address */
+#define FSL_FEATURE_SPIFI_START_ADDR (0x10000000)
+/* @brief SPIFI end address */
+#define FSL_FEATURE_SPIFI_END_ADDR (0x103FFFFF)
+/* @brief SPIFI DATALEN bitfile in CMD register */
+#define FSL_FEATURE_SPIFI_DATALEN_CTRL (1)
+
+/* SYSCON module features */
+
+/* No feature definitions */
+
+/* WWDT module features */
+
+/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */
+#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (1)
+/* @brief WWDT NO PDCFG. */
+#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
+/* @brief WWDT LOCK bitfile in MOD register */
+#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1)
+
+#endif /* _JN5189_FEATURES_H_ */
diff --git a/third_party/nxp/JN5189/rom_apis/flash_header.h b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/flash_header.h
similarity index 100%
rename from third_party/nxp/JN5189/rom_apis/flash_header.h
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/flash_header.h
diff --git a/third_party/nxp/JN5189/drivers/aes/fsl_aes.c b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_aes.c
similarity index 100%
rename from third_party/nxp/JN5189/drivers/aes/fsl_aes.c
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_aes.c
diff --git a/third_party/nxp/JN5189/drivers/aes/fsl_aes.h b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_aes.h
similarity index 100%
rename from third_party/nxp/JN5189/drivers/aes/fsl_aes.h
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_aes.h
diff --git a/third_party/nxp/JN5189/drivers/fsl_clock.c b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_clock.c
similarity index 91%
rename from third_party/nxp/JN5189/drivers/fsl_clock.c
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_clock.c
index 003794c..4081940 100755
--- a/third_party/nxp/JN5189/drivers/fsl_clock.c
+++ b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_clock.c
@@ -10,6 +10,10 @@
/*******************************************************************************
* Definitions
******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.clock"
+#endif
#define OSC32K_FREQ 32768UL
#define FRO32K_FREQ 32768UL
#define OSC32M_FREQ 32000000UL
@@ -70,7 +74,7 @@
uint32_t CLOCK_GetWdtOscFreq(void);
uint32_t CLOCK_GetPWMClockFreq(void);
-static uint8_t CLOCK_u8OscCapConvert(uint8_t u8OscCap, uint8_t u8CapBankDiscontinuity);
+static uint8_t CLOCK_u8OscCapConvert(uint32_t OscCap, uint8_t u8CapBankDiscontinuity);
/*******************************************************************************
* types
@@ -157,6 +161,11 @@
pClkSel[mux] |= ((pos - 2) << SYSCON_OSC32CLKSEL_SEL32KHZ_SHIFT);
}
}
+ else if (mux == CM_MODEMCLKSEL)
+ {
+ pClkSel[mux] |= SYSCON_MODEMCLKSEL_SEL_ZIGBEE_MASK;
+ pClkSel[mux] &= ((uint32_t)pos | 0xfffeU);
+ }
else
{
pClkSel[mux] = pos;
@@ -726,6 +735,9 @@
case kCLOCK_ApbFro48M: /* FRO48M */
freq = CLOCK_GetFro48MFreq();
break;
+ default:
+ freq = 0;
+ break;
}
return freq;
@@ -755,7 +767,6 @@
switch (clk)
{
case kCLOCK_Xtal32k:
- PMC->PDRUNCFG &= ~PMC_PDRUNCFG_ENA_FRO32K_MASK;
PMC->PDRUNCFG |= PMC_PDRUNCFG_ENA_XTAL32K_MASK;
SYSCON->OSC32CLKSEL |= SYSCON_OSC32CLKSEL_SEL32KHZ_MASK;
break;
@@ -775,7 +786,6 @@
break;
case kCLOCK_Fro32k:
- PMC->PDRUNCFG &= ~PMC_PDRUNCFG_ENA_XTAL32K_MASK;
PMC->PDRUNCFG |= PMC_PDRUNCFG_ENA_FRO32K_MASK;
SYSCON->OSC32CLKSEL &= ~SYSCON_OSC32CLKSEL_SEL32KHZ_MASK;
break;
@@ -977,7 +987,7 @@
uint8_t u8IECXinCapCal6pF, u8IECXinCapCal8pF, u8IECXoutCapCal6pF, u8IECXoutCapCal8pF, u8XOSlave;
int32_t iaXin_x4, ibXin, iaXout_x4, ibXout;
int32_t iXOCapInpF_x100, iXOCapOutpF_x100;
- uint8_t u8XOCapInCtrl, u8XOCapOutCtrl;
+ uint32_t u32XOCapInCtrl, u32XOCapOutCtrl;
uint32_t u32RegVal;
/* Enable and set LDO, if not already done */
@@ -987,7 +997,7 @@
u32XOTrimValue = GET_32MXO_TRIM();
/* Check validity and apply */
- if ((u32XOTrimValue & 1) && ((u32XOTrimValue >> 15) & 1) && (GET_CAL_DATE() >= 20180301))
+ if ((u32XOTrimValue & 1) && ((u32XOTrimValue >> 15) & 1) && (GET_CAL_DATE() >= 20181203))
{
/* These fields are 7 bits, unsigned */
u8IECXinCapCal6pF = (u32XOTrimValue >> 1) & 0x7f;
@@ -1022,11 +1032,11 @@
iXOCapOutpF_x100 = iXOCapOutpF_x100 + XO_32M_OSC_CAP_Delta_x1000 / 5;
/* In & out XO_OSC_CAP_Code_CTRL calculation, with rounding */
- u8XOCapInCtrl = (uint8_t)(((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400);
- u8XOCapOutCtrl = (uint8_t)(((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400);
+ u32XOCapInCtrl = (uint32_t)(((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400);
+ u32XOCapOutCtrl = (uint32_t)(((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400);
- u8XOCapInCtrl = CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13);
- u8XOCapOutCtrl = CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13);
+ uint8_t u8XOCapInCtrl = CLOCK_u8OscCapConvert(u32XOCapInCtrl, 13);
+ uint8_t u8XOCapOutCtrl = CLOCK_u8OscCapConvert(u32XOCapOutCtrl, 13);
/* Read register and clear fields to be written */
u32RegVal = ASYNC_SYSCON->XTAL32MCTRL;
@@ -1055,7 +1065,7 @@
uint8_t u8IECXinCapCal6pF, u8IECXinCapCal8pF, u8IECXoutCapCal6pF, u8IECXoutCapCal8pF;
int32_t iaXin_x4, ibXin, iaXout_x4, ibXout;
int32_t iXOCapInpF_x100, iXOCapOutpF_x100;
- uint8_t u8XOCapInCtrl, u8XOCapOutCtrl;
+ uint32_t u32XOCapInCtrl, u32XOCapOutCtrl;
uint32_t u32RegVal;
/* Get Cal values from Flash */
@@ -1092,11 +1102,11 @@
iXOCapOutpF_x100 = iXOCapOutpF_x100 + XO_32k_OSC_CAP_Delta_x1000 / 5;
/* In & out XO_OSC_CAP_Code_CTRL calculation, with rounding */
- u8XOCapInCtrl = (uint8_t)(((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400);
- u8XOCapOutCtrl = (uint8_t)(((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400);
+ u32XOCapInCtrl = (uint32_t)(((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400);
+ u32XOCapOutCtrl = (uint32_t)(((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400);
- u8XOCapInCtrl = CLOCK_u8OscCapConvert(u8XOCapInCtrl, 23);
- u8XOCapOutCtrl = CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 23);
+ uint8_t u8XOCapInCtrl = CLOCK_u8OscCapConvert(u32XOCapInCtrl, 23);
+ uint8_t u8XOCapOutCtrl = CLOCK_u8OscCapConvert(u32XOCapOutCtrl, 23);
/* Read register and clear fields to be written */
u32RegVal = SYSCON->XTAL32KCAP;
@@ -1151,79 +1161,31 @@
CLOCK_uDelay(u32AdditionalWait_us);
}
-static uint8_t CLOCK_u8OscCapConvert(uint8_t u8OscCap, uint8_t u8CapBankDiscontinuity)
+static uint8_t CLOCK_u8OscCapConvert(uint32_t OscCap_val, uint8_t u8CapBankDiscontinuity)
{
/* Compensate for discontinuity in the capacitor banks */
- if (u8OscCap < 64)
+ if (OscCap_val < 64)
{
- if (u8OscCap >= u8CapBankDiscontinuity)
+ if (OscCap_val >= u8CapBankDiscontinuity)
{
- u8OscCap -= u8CapBankDiscontinuity;
+ OscCap_val -= u8CapBankDiscontinuity;
}
else
{
- u8OscCap = 0;
+ OscCap_val = 0;
}
}
else
{
- if (u8OscCap <= (127 - u8CapBankDiscontinuity))
+ if (OscCap_val <= (127 - u8CapBankDiscontinuity))
{
- u8OscCap += u8CapBankDiscontinuity;
+ OscCap_val += u8CapBankDiscontinuity;
}
else
{
- u8OscCap = 127;
+ OscCap_val = 127;
}
}
- return u8OscCap;
-}
-
-/*!
- * brief Use DWT to delay at least for some time.
- * Please note that, this API will calculate the microsecond period with the maximum devices
- * supported CPU frequency, so this API will only delay for at least the given microseconds, if precise
- * delay count was needed, please implement a new timer count to achieve this function.
- *
- * param delay_us Delay time in unit of microsecond.
- */
-__attribute__((weak)) void SDK_DelayAtLeastUs(uint32_t delay_us)
-{
- assert(0U != delay_us);
- uint64_t count = 0U;
- uint32_t period = SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY / 1000000;
-
- /* Make sure the DWT trace fucntion is enabled. */
- if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR))
- {
- CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
- }
-
- /* CYCCNT not supported on this device. */
- assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk));
-
- /* If CYCCENT has already been enabled, read directly, otherwise, need enable it. */
- if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL))
- {
- DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
- }
-
- /* Calculate the count ticks. */
- count = DWT->CYCCNT;
- count += (uint64_t)period * delay_us;
-
- if (count > 0xFFFFFFFFUL)
- {
- count -= 0xFFFFFFFFUL;
- /* wait for cyccnt overflow. */
- while (count < DWT->CYCCNT)
- {
- }
- }
-
- /* Wait for cyccnt reach count value. */
- while (count > DWT->CYCCNT)
- {
- }
+ return (uint8_t)OscCap_val;
}
diff --git a/third_party/nxp/JN5189/drivers/fsl_clock.h b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_clock.h
similarity index 95%
rename from third_party/nxp/JN5189/drivers/fsl_clock.h
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_clock.h
index d1746af..caec656 100755
--- a/third_party/nxp/JN5189/drivers/fsl_clock.h
+++ b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_clock.h
@@ -20,6 +20,12 @@
/*! @file */
+/*! @name Driver version */
+/*@{*/
+/*! @brief CLOCK driver version 2.1.0. */
+#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*@}*/
+
#ifdef FPGA_50MHZ
#define SYSCON_BASE_CLOCK_DIV (6)
#define SYSCON_BASE_CLOCK_MUL (5)
@@ -134,10 +140,8 @@
*/
typedef enum _clock_name
{
- kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_ROM_SHIFT), /*!< ROM clock */
kCLOCK_Sram0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_SRAM_CTRL0_SHIFT), /*!< SRAM0 clock */
kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT), /*!< SRAM1 clock */
- kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_FLASH_SHIFT), /*!< Flash clock */
kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_SPIFI_SHIFT), /*!< SPIFI clock */
kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_MUX_SHIFT), /*!< InputMux clock */
kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_IOCON_SHIFT), /*!< IOCON clock */
@@ -154,7 +158,6 @@
kCLOCK_WakeTmr =
CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_WAKE_UP_TIMERS_SHIFT), /*!< Wake up Timers clock */
kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_ADC_SHIFT), /*!< ADC0 clock */
- kCLOCK_Efuse = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_EFUSE_SHIFT), /*!< EFuse clock */
kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_USART0_SHIFT), /*!< FlexComm0 clock */
kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_USART1_SHIFT), /*!< FlexComm1 clock */
kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_I2C0_SHIFT), /*!< FlexComm2 clock */
@@ -246,7 +249,7 @@
kFRO32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), /*!< Select FRO 32K for CLKOUT */
kXTAL32M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), /*!< Select XTAL 32M for CLKOUT */
kDCDC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), /*!< Select DCDC for CLKOUT */
- kFROM48M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), /*!< Select FRO 48M for CLKOUT */
+ kFRO48M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), /*!< Select FRO 48M for CLKOUT */
kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), /*!< Select FRO 1M for CLKOUT */
kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), /*!< No clock for CLKOUT */
@@ -297,10 +300,11 @@
kFRO12M_to_DMI_CLK = MUX_A(CM_DMICLKSEL, 5), /*!< Select FRO 12M for DMIC */
kNONE_to_DMI_CLK = MUX_A(CM_DMICLKSEL, 6), /*!< No clock for DMIC */
- kOSC32K_to_WKT_CLK = MUX_A(CM_WKTCLKSEL, 0),
- kFRO1M_to_WKT_CLK = MUX_A(CM_WKTCLKSEL, 1),
- kNONE_to_WKT_CLK = MUX_A(CM_WKTCLKSEL, 2),
- kTESTCLK_to_WKT_CLK = MUX_A(CM_WKTCLKSEL, 3),
+ kOSC32K_to_WKT_CLK = MUX_A(CM_WKTCLKSEL, 0), /*!< Select OSC 32K for WKT */
+ kNONE_to_WKT_CLK = MUX_A(CM_WKTCLKSEL, 3), /*!< No clock for WKT */
+
+ kXTAL32M_DIV2_to_ZIGBEE_CLK = MUX_A(CM_MODEMCLKSEL, 0), /*!< Select XTAL 32M for ZIGBEE */
+ kNONE_to_ZIGBEE_CLK = MUX_A(CM_MODEMCLKSEL, 1), /*!< No clock for ZIGBEE */
kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0), /*!< Select main clock for Asynchronous APB */
kXTAL32M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1), /*!< Select XTAL 32M for Asynchronous APB */
@@ -447,9 +451,13 @@
uint32_t clk_XtalNPcbParCappF_x100; /*< XTAL PCB -ve parasitic capacitance */
} ClockCapacitanceCompensation_t;
-#ifdef __cplusplus
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
extern "C" {
-#endif
+#endif /* __cplusplus */
/**
* @brief Obtains frequency of specified clock
@@ -572,16 +580,6 @@
*/
void CLOCK_Xtal32M_WaitUntilStable(uint32_t u32AdditionalWait_us);
-/*!
- * @brief Use DWT to delay at least for some time.
- * Please note that, this API will calculate the microsecond period with the maximum devices
- * supported CPU frequency, so this API will only delay for at least the given microseconds, if precise
- * delay count was needed, please implement a new timer count to achieve this function.
- *
- * @param delay_us Delay time in unit of microsecond.
- */
-void SDK_DelayAtLeastUs(uint32_t delay_us);
-
#if defined(__cplusplus)
}
#endif /* __cplusplus */
diff --git a/third_party/nxp/JN5189/drivers/fsl_common.h b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_common.h
similarity index 97%
rename from third_party/nxp/JN5189/drivers/fsl_common.h
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_common.h
index 4e79ae6..c5e1c2f 100755
--- a/third_party/nxp/JN5189/drivers/fsl_common.h
+++ b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_common.h
@@ -38,8 +38,8 @@
/*! @name Driver version */
/*@{*/
-/*! @brief common driver version 2.1.3. */
-#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
+/*! @brief common driver version 2.2.0. */
+#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
/*@}*/
/* Debug console type definition. */
@@ -611,6 +611,16 @@
*/
void SDK_Free(void *ptr);
+ /*!
+ * @brief Delay at least for some time.
+ * Please note that, this API uses while loop for delay, different run-time environments make the time not precise,
+ * if precise delay count was needed, please implement a new delay function with hardware timer.
+ *
+ * @param delay_us Delay time in unit of microsecond.
+ * @param coreClock_Hz Core clock frequency with Hz.
+ */
+ void SDK_DelayAtLeastUs(uint32_t delay_us, uint32_t coreClock_Hz);
+
#if defined(__cplusplus)
}
#endif
diff --git a/third_party/nxp/JN5189/drivers/fsl_ctimer.c b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_ctimer.c
similarity index 100%
rename from third_party/nxp/JN5189/drivers/fsl_ctimer.c
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_ctimer.c
diff --git a/third_party/nxp/JN5189/drivers/fsl_ctimer.h b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_ctimer.h
similarity index 100%
rename from third_party/nxp/JN5189/drivers/fsl_ctimer.h
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_ctimer.h
diff --git a/third_party/nxp/JN5189/drivers/fsl_flash.c b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_flash.c
similarity index 100%
rename from third_party/nxp/JN5189/drivers/fsl_flash.c
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_flash.c
diff --git a/third_party/nxp/JN5189/drivers/fsl_flash.h b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_flash.h
similarity index 100%
rename from third_party/nxp/JN5189/drivers/fsl_flash.h
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_flash.h
diff --git a/third_party/nxp/JN5189/drivers/fsl_flexcomm.c b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_flexcomm.c
similarity index 100%
rename from third_party/nxp/JN5189/drivers/fsl_flexcomm.c
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_flexcomm.c
diff --git a/third_party/nxp/JN5189/drivers/fsl_flexcomm.h b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_flexcomm.h
similarity index 100%
rename from third_party/nxp/JN5189/drivers/fsl_flexcomm.h
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_flexcomm.h
diff --git a/third_party/nxp/JN5189/drivers/fsl_gpio.c b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_gpio.c
similarity index 100%
rename from third_party/nxp/JN5189/drivers/fsl_gpio.c
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_gpio.c
diff --git a/third_party/nxp/JN5189/drivers/fsl_gpio.h b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_gpio.h
similarity index 100%
rename from third_party/nxp/JN5189/drivers/fsl_gpio.h
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_gpio.h
diff --git a/third_party/nxp/JN5189/drivers/fsl_iocon.h b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_iocon.h
similarity index 93%
rename from third_party/nxp/JN5189/drivers/fsl_iocon.h
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_iocon.h
index 78e765a..1b0c3da 100755
--- a/third_party/nxp/JN5189/drivers/fsl_iocon.h
+++ b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_iocon.h
@@ -60,7 +60,7 @@
#define IOCON_MODE_PULLDOWN IOCON_PIO_MODE(3) /*!< Selects pull-down function */
#define IOCON_HYS_EN (0x1 << 5) /*!< Enables hysteresis ??*/
-#define IOCON_GPIO_MODE IOCON_PIO_SLEW0(1) /*!< GPIO Mode */
+#define IOCON_GPIO_MODE IOCON_PIO_EGP(1) /*!< GPIO Mode */
#define IOCON_I2C_SLEW IOCON_PIO_SLEW0(1) /*!< I2C Slew Rate Control */
#define IOCON_INV_EN IOCON_PIO_INVERT(1) /*!< Enables invert function on input */
@@ -90,6 +90,14 @@
#define IOCON_IO_CLAMPING_NORMAL_MFIO (1 << 11)
#define IOCON_IO_CLAMPING_COMBO_MFIO_I2C (1 << 12) /* Use this flag for PIO11 and PIO12 only */
+#define IOCON_PIO_DBG_FUNC_MASK (0xF000U)
+#define IOCON_PIO_DBG_FUNC_SHIFT (12U)
+#define IOCON_PIO_DBG_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DBG_FUNC_SHIFT)) & IOCON_PIO_DBG_FUNC_MASK)
+#define IOCON_PIO_DBG_MODE_MASK (0x10000U)
+#define IOCON_PIO_DBG_MODE_SHIFT (16U)
+#define IOCON_PIO_DBG_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DBG_MODE_SHIFT)) & IOCON_PIO_DBG_MODE_MASK)
+
+
#define IOCON_CFG(dbg_func) (IOCON_PIO_FUNC(0) | IOCON_MODE_PULLDOWN |\
IOCON_DIGITAL_EN | IOCON_INPFILT_OFF | \
IOCON_PIO_DBG_FUNC(dbg_func) | IOCON_PIO_DBG_MODE(1))
diff --git a/third_party/nxp/JN5189/drivers/fsl_power.c b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_power.c
similarity index 100%
rename from third_party/nxp/JN5189/drivers/fsl_power.c
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_power.c
diff --git a/third_party/nxp/JN5189/drivers/fsl_power.h b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_power.h
similarity index 100%
rename from third_party/nxp/JN5189/drivers/fsl_power.h
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_power.h
diff --git a/third_party/nxp/JN5189/drivers/fsl_reset.c b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_reset.c
similarity index 91%
rename from third_party/nxp/JN5189/drivers/fsl_reset.c
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_reset.c
index a0ba825..c4a584d 100755
--- a/third_party/nxp/JN5189/drivers/fsl_reset.c
+++ b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_reset.c
@@ -14,8 +14,12 @@
/*******************************************************************************
* Definitions
******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.reset"
+#endif
/* RG TODO This should be defined in jn518x.h */
-#define SYSCON_PRESETCTRL_COUNT 2
+#define SYSCON_PRESETCTRL_COUNT 2
/*******************************************************************************
* Variables
@@ -43,8 +47,8 @@
void RESET_SetPeripheralReset(reset_ip_name_t peripheral)
{
const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
- const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
- const uint32_t bitMask = 1u << bitPos;
+ const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
+ const uint32_t bitMask = 1u << bitPos;
assert(bitPos < 32u);
@@ -84,8 +88,8 @@
void RESET_ClearPeripheralReset(reset_ip_name_t peripheral)
{
const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
- const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
- const uint32_t bitMask = 1u << bitPos;
+ const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
+ const uint32_t bitMask = 1u << bitPos;
assert(bitPos < 32u);
@@ -130,7 +134,6 @@
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */
-
/*!
* brief Reset the chip.
*
diff --git a/third_party/nxp/JN5189/drivers/fsl_reset.h b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_reset.h
similarity index 97%
rename from third_party/nxp/JN5189/drivers/fsl_reset.h
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_reset.h
index 731a52e..5d88ab7 100755
--- a/third_party/nxp/JN5189/drivers/fsl_reset.h
+++ b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_reset.h
@@ -24,6 +24,12 @@
* Definitions
******************************************************************************/
+/*! @name Driver version */
+/*@{*/
+/*! @brief RESET driver version 2.0.1. */
+#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
/*!
* @brief Enumeration for peripheral reset control bits
*
@@ -31,7 +37,6 @@
*/
typedef enum _SYSCON_RSTn
{
- kFLASH_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_FLASH_RST_SHIFT), /**< Flash controller reset control */
kSPIFI_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_SPIFI_RST_SHIFT), /**< SpiFi reset control */
kMUX_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_MUX_RST_SHIFT), /**< Input mux reset control */
kIOCON_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_IOCON_RST_SHIFT), /**< IOCON reset control */
@@ -44,7 +49,6 @@
kANA_INT_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_ANA_INT_CTRL_RST_SHIFT), /**< Analog interrupt controller reset */
kWKT_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_WAKE_UP_TIMERS_RST_SHIFT), /**< Wakeup timer reset */
kADC0_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_ADC_RST_SHIFT), /**< ADC0 reset control */
- kEFUSE_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_EFUSE_RST_SHIFT), /**< EFUSE reset control */
kFC0_RST_SHIFT_RSTn =
((1UL << 16) | SYSCON_PRESETCTRL1_USART0_RST_SHIFT), /**< Flexcomm Interface 0 reset control */
kFC1_RST_SHIFT_RSTn =
diff --git a/third_party/nxp/JN5189/drivers/fsl_rng.c b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_rng.c
similarity index 100%
rename from third_party/nxp/JN5189/drivers/fsl_rng.c
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_rng.c
diff --git a/third_party/nxp/JN5189/drivers/fsl_rng.h b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_rng.h
similarity index 100%
rename from third_party/nxp/JN5189/drivers/fsl_rng.h
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_rng.h
diff --git a/third_party/nxp/JN5189/drivers/sha/fsl_sha.c b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_sha.c
similarity index 100%
rename from third_party/nxp/JN5189/drivers/sha/fsl_sha.c
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_sha.c
diff --git a/third_party/nxp/JN5189/drivers/sha/fsl_sha.h b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_sha.h
similarity index 100%
rename from third_party/nxp/JN5189/drivers/sha/fsl_sha.h
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_sha.h
diff --git a/third_party/nxp/JN5189/drivers/fsl_usart.c b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_usart.c
similarity index 100%
rename from third_party/nxp/JN5189/drivers/fsl_usart.c
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_usart.c
diff --git a/third_party/nxp/JN5189/drivers/fsl_usart.h b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_usart.h
similarity index 100%
rename from third_party/nxp/JN5189/drivers/fsl_usart.h
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_usart.h
diff --git a/third_party/nxp/JN5189/drivers/fsl_wtimer.c b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_wtimer.c
similarity index 100%
rename from third_party/nxp/JN5189/drivers/fsl_wtimer.c
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_wtimer.c
diff --git a/third_party/nxp/JN5189/drivers/fsl_wtimer.h b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_wtimer.h
similarity index 100%
rename from third_party/nxp/JN5189/drivers/fsl_wtimer.h
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_wtimer.h
diff --git a/third_party/nxp/JN5189/rom_apis/rom_aes.h b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/rom_aes.h
similarity index 100%
rename from third_party/nxp/JN5189/rom_apis/rom_aes.h
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/rom_aes.h
diff --git a/third_party/nxp/JN5189/rom_apis/rom_api.h b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/rom_api.h
similarity index 96%
rename from third_party/nxp/JN5189/rom_apis/rom_api.h
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/rom_api.h
index fcf35b5..569bb7e 100755
--- a/third_party/nxp/JN5189/rom_apis/rom_api.h
+++ b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/rom_api.h
@@ -28,11 +28,20 @@
#include "rom_psector.h"
#include "flash_header.h"
#include "rom_aes.h"
+#include "rom_efuse.h"
/****************************************************************************/
/*** Macro Definitions ***/
/****************************************************************************/
-
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.jn_romapi"
+#endif
+/*! @name Driver version */
+/*@{*/
+/*! @brief JN_ROMAPI driver version 2.0.0. */
+#define FSL_JN_ROMAPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
/****************************************************************************/
/*** Type Definitions ***/
/****************************************************************************/
diff --git a/third_party/nxp/JN5189/rom_apis/rom_common.h b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/rom_common.h
similarity index 100%
rename from third_party/nxp/JN5189/rom_apis/rom_common.h
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/rom_common.h
diff --git a/third_party/nxp/JN5189DK6/devices/JN5189/drivers/rom_efuse.h b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/rom_efuse.h
new file mode 100755
index 0000000..1f1badb
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/rom_efuse.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ROM_EFUSE_H_
+#define ROM_EFUSE_H_
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+/****************************************************************************/
+/*** Include Files ***/
+/****************************************************************************/
+
+#include <rom_common.h>
+
+/****************************************************************************/
+/*** Macro Definitions ***/
+/****************************************************************************/
+
+/****************************************************************************/
+/*** Type Definitions ***/
+/****************************************************************************/
+
+/****************************************************************************/
+/*** Exported Functions ***/
+/****************************************************************************/
+static inline bool efuse_ReadBit(uint8_t efuse_bitpos)
+{
+ bool (*p_efuse_ReadBit)(uint8_t bitpos);
+ p_efuse_ReadBit = (bool (*)(uint8_t bitpos))0x03001671U;
+
+ return p_efuse_ReadBit(efuse_bitpos);
+}
+/****************************************************************************/
+/*** Exported Variables
+ ***/
+/****************************************************************************/
+
+#if defined __cplusplus
+}
+#endif
+
+#endif /* ROM_EFUSE_H_ */
+
+/****************************************************************************/
+/*** END OF FILE ***/
+/****************************************************************************/
diff --git a/third_party/nxp/JN5189/rom_apis/rom_lowpower.h b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/rom_lowpower.h
similarity index 98%
rename from third_party/nxp/JN5189/rom_apis/rom_lowpower.h
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/rom_lowpower.h
index 49a7a4f..9651e35 100755
--- a/third_party/nxp/JN5189/rom_apis/rom_lowpower.h
+++ b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/rom_lowpower.h
@@ -15,11 +15,13 @@
#include <rom_common.h>
#include <rom_pmc.h>
-/** @defgroup LOWPOWER_JN518X CHIP: JN518X LOWPOWER Driver
- * @ingroup CHIP_JN518X_DRIVERS
+/*!
+ * @addtogroup ROM_API
* @{
*/
+/*! @file */
+
/*******************
* EXPORTED MACROS *
********************/
@@ -389,8 +391,8 @@
*/
static inline void Chip_LOWPOWER_SetUpLowPowerModeWakeUpTimer(LPC_LOWPOWER_T *p_lowpower_cfg)
{
- void (*p_Chip_LOWPOWER_SetUpLowPowerModeWakeUpTimer)(LPC_LOWPOWER_T *p_lowpower_cfg);
- p_Chip_LOWPOWER_SetUpLowPowerModeWakeUpTimer = (void (*)(LPC_LOWPOWER_T *p_lowpower_cfg))0x030038d1U;
+ void (*p_Chip_LOWPOWER_SetUpLowPowerModeWakeUpTimer)(LPC_LOWPOWER_T * p_lowpower_cfg);
+ p_Chip_LOWPOWER_SetUpLowPowerModeWakeUpTimer = (void (*)(LPC_LOWPOWER_T * p_lowpower_cfg))0x030038d1U;
p_Chip_LOWPOWER_SetUpLowPowerModeWakeUpTimer(p_lowpower_cfg);
}
@@ -429,8 +431,8 @@
*/
static inline void Chip_LOWPOWER_GetSystemVoltages(LPC_LOWPOWER_LDOVOLTAGE_T *p_ldo_voltage)
{
- void (*p_Chip_LOWPOWER_GetSystemVoltages)(LPC_LOWPOWER_LDOVOLTAGE_T *p_ldo_voltage);
- p_Chip_LOWPOWER_GetSystemVoltages = (void (*)(LPC_LOWPOWER_LDOVOLTAGE_T *p_ldo_voltage))0x03003de1U;
+ void (*p_Chip_LOWPOWER_GetSystemVoltages)(LPC_LOWPOWER_LDOVOLTAGE_T * p_ldo_voltage);
+ p_Chip_LOWPOWER_GetSystemVoltages = (void (*)(LPC_LOWPOWER_LDOVOLTAGE_T * p_ldo_voltage))0x03003de1U;
p_Chip_LOWPOWER_GetSystemVoltages(p_ldo_voltage);
}
@@ -442,8 +444,8 @@
*/
static inline void Chip_LOWPOWER_SetSystemVoltages(LPC_LOWPOWER_LDOVOLTAGE_T *p_ldo_voltage)
{
- void (*p_Chip_LOWPOWER_SetSystemVoltages)(LPC_LOWPOWER_LDOVOLTAGE_T *p_ldo_voltage);
- p_Chip_LOWPOWER_SetSystemVoltages = (void (*)(LPC_LOWPOWER_LDOVOLTAGE_T *p_ldo_voltage))0x03003e99U;
+ void (*p_Chip_LOWPOWER_SetSystemVoltages)(LPC_LOWPOWER_LDOVOLTAGE_T * p_ldo_voltage);
+ p_Chip_LOWPOWER_SetSystemVoltages = (void (*)(LPC_LOWPOWER_LDOVOLTAGE_T * p_ldo_voltage))0x03003e99U;
p_Chip_LOWPOWER_SetSystemVoltages(p_ldo_voltage);
}
@@ -455,8 +457,8 @@
*/
static inline void Chip_LOWPOWER_SetLowPowerMode(LPC_LOWPOWER_T *p_lowpower_cfg)
{
- void (*p_Chip_LOWPOWER_SetLowPowerMode)(LPC_LOWPOWER_T *p_lowpower_cfg);
- p_Chip_LOWPOWER_SetLowPowerMode = (void (*)(LPC_LOWPOWER_T *p_lowpower_cfg))0x0300404dU;
+ void (*p_Chip_LOWPOWER_SetLowPowerMode)(LPC_LOWPOWER_T * p_lowpower_cfg);
+ p_Chip_LOWPOWER_SetLowPowerMode = (void (*)(LPC_LOWPOWER_T * p_lowpower_cfg))0x0300404dU;
p_Chip_LOWPOWER_SetLowPowerMode(p_lowpower_cfg);
}
diff --git a/third_party/nxp/JN5189/rom_apis/rom_mpu.h b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/rom_mpu.h
similarity index 100%
rename from third_party/nxp/JN5189/rom_apis/rom_mpu.h
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/rom_mpu.h
diff --git a/third_party/nxp/JN5189/rom_apis/rom_pmc.h b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/rom_pmc.h
similarity index 100%
rename from third_party/nxp/JN5189/rom_apis/rom_pmc.h
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/rom_pmc.h
diff --git a/third_party/nxp/JN5189/rom_apis/rom_psector.h b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/rom_psector.h
similarity index 99%
rename from third_party/nxp/JN5189/rom_apis/rom_psector.h
rename to third_party/nxp/JN5189DK6/devices/JN5189/drivers/rom_psector.h
index e5474f1..e27d231 100755
--- a/third_party/nxp/JN5189/rom_apis/rom_psector.h
+++ b/third_party/nxp/JN5189DK6/devices/JN5189/drivers/rom_psector.h
@@ -213,7 +213,7 @@
* 0 means invalid
* Any other value means valid
*/
- uint32_t backdoor_disable; /*!< Back door control:
+ uint32_t hwtestmode_disable; /*< HW test mode control:
* 0 means enabled
* Any other value means disabled
*/
diff --git a/third_party/nxp/JN5189/fsl_device_registers.h b/third_party/nxp/JN5189DK6/devices/JN5189/fsl_device_registers.h
similarity index 100%
rename from third_party/nxp/JN5189/fsl_device_registers.h
rename to third_party/nxp/JN5189DK6/devices/JN5189/fsl_device_registers.h
diff --git a/third_party/nxp/JN5189/startup_JN5189.c b/third_party/nxp/JN5189DK6/devices/JN5189/mcuxpresso/startup_JN5189.c
similarity index 98%
rename from third_party/nxp/JN5189/startup_JN5189.c
rename to third_party/nxp/JN5189DK6/devices/JN5189/mcuxpresso/startup_JN5189.c
index a6290b2..f537bfb 100755
--- a/third_party/nxp/JN5189/startup_JN5189.c
+++ b/third_party/nxp/JN5189DK6/devices/JN5189/mcuxpresso/startup_JN5189.c
@@ -39,6 +39,16 @@
extern "C" {
#endif
+//*****************************************************************************
+// Variable to store CRP value in. Will be placed automatically
+// by the linker when "Enable Code Read Protect" selected.
+// See crp.h header for more information
+//*****************************************************************************
+#if (defined(__MCUXPRESSO))
+#include <NXP/crp.h>
+__CRP const unsigned int CRP_WORD = CRP_NO_CRP ;
+#endif
+
#include "fsl_device_registers.h"
#include "rom_api.h"
@@ -133,9 +143,7 @@
WEAK void BLE_DP2_IRQHandler(void);
WEAK void BLE_LL_ALL_IRQHandler(void);
WEAK void ZIGBEE_MAC_IRQHandler(void);
-WEAK void vMMAC_IntHandlerBbc(void);
WEAK void ZIGBEE_MODEM_IRQHandler(void);
-WEAK void vMMAC_IntHandlerPhy(void);
WEAK void RFP_TMU_IRQHandler(void);
WEAK void RFP_AGC_IRQHandler(void);
WEAK void ISO7816_IRQHandler(void);
@@ -148,6 +156,8 @@
WEAK void PVTVF1_RED_IRQHandler(void);
WEAK void BLE_WAKE_UP_TIMER_IRQHandler(void);
WEAK void SHA_IRQHandler(void);
+WEAK void vMMAC_IntHandlerBbc(void);
+WEAK void vMMAC_IntHandlerPhy(void);
//*****************************************************************************
// Forward declaration of the driver IRQ handlers. These are aliased
@@ -391,7 +401,7 @@
"BX R0\t\n");
}
-__attribute__ ((section(".after_vectors"))) void ResetISR2(void)
+__attribute__ ((used, section(".after_vectors"))) void ResetISR2(void)
{
if ( WarmMain )
{
diff --git a/third_party/nxp/JN5189DK6/devices/JN5189/system_JN5189.c b/third_party/nxp/JN5189DK6/devices/JN5189/system_JN5189.c
new file mode 100755
index 0000000..28c225e
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/devices/JN5189/system_JN5189.c
@@ -0,0 +1,383 @@
+/*
+** ###################################################################
+** Processors: JN5189HN
+** JN5189THN
+**
+** Compilers: Keil ARM C/C++ Compiler
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+** MCUXpresso Compiler
+**
+** Reference manual: JN5189 User manual Rev0.1 27 July 2018
+** Version: rev. 1.0, 2018-07-31
+** Build: b180731
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2018 NXP
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** Revisions:
+** - rev. 1.0 (2018-07-31)
+** Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file JN5189
+ * @version 1.0
+ * @date 2018-07-31
+ * @brief Device specific configuration file for JN5189 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+#include "rom_api.h"
+
+/**
+ * Clock source selections for the Main Clock
+ */
+typedef enum _main_clock_src
+{
+ kCLOCK_MainFro12M = 0,
+ kCLOCK_MainOsc32k = 1,
+ kCLOCK_MainXtal32M = 2,
+ kCLOCK_MainFro32M = 3,
+ kCLOCK_MainFro48M = 4,
+ kCLOCK_MainExtClk = 5,
+ kCLOCK_MainFro1M = 6,
+} main_clock_src_t;
+
+
+/**
+ * Clock source selections for CLKOUT
+ */
+typedef enum _clkout_clock_src
+{
+ kCLOCK_ClkoutMainClk = 0,
+ kCLOCK_ClkoutXtal32k = 1,
+ kCLOCK_ClkoutFro32k = 2,
+ kCLOCK_ClkoutXtal32M = 3,
+ kCLOCK_ClkoutDcDcTest= 4,
+ kCLOCK_ClkoutFro48M = 5,
+ kCLOCK_ClkoutFro1M = 6,
+ kCLOCK_ClkoutNoClock = 7
+} clkout_clock_src_t;
+
+typedef enum
+{
+ FRO12M_ENA = (1 << 0),
+ FRO32M_ENA = (1 << 1),
+ FRO48M_ENA = (1 << 2),
+ FRO64M_ENA = (1 << 3),
+ FRO96M_ENA = (1 << 4)
+} Fro_ClkSel_t;
+
+#define OSC32K_FREQ 32768UL
+#define FRO32K_FREQ 32768UL
+#define OSC32M_FREQ 32000000UL
+#define XTAL32M_FREQ 32000000UL
+#define FRO64M_FREQ 64000000UL
+#define FRO1M_FREQ 1000000UL
+#define FRO12M_FREQ 12000000UL
+#define FRO32M_FREQ 32000000UL
+#define FRO48M_FREQ 48000000UL
+
+static const uint32_t g_Ext_Clk_Freq = 0U;
+
+extern unsigned int __Vectors;
+extern WEAK void SystemInit(void);
+extern WEAK void WarmMain(void);
+
+static uint32_t CLOCK_GetXtal32kFreq(void)
+{
+ uint32_t freq = 0;
+
+ if (((PMC->PDRUNCFG & PMC_PDRUNCFG_ENA_XTAL32K_MASK)
+ >> PMC_PDRUNCFG_ENA_XTAL32K_SHIFT) != 0)
+ {
+ freq = OSC32K_FREQ;
+ }
+
+ return freq;
+}
+
+static uint32_t CLOCK_GetXtal32MFreq(void)
+{
+ return XTAL32M_FREQ;
+}
+
+static uint32_t CLOCK_GetFro32kFreq(void)
+{
+ uint32_t freq = 0;
+
+ if (((PMC->PDRUNCFG & PMC_PDRUNCFG_ENA_FRO32K_MASK)
+ >> PMC_PDRUNCFG_ENA_FRO32K_SHIFT) != 0)
+ {
+ freq = FRO32K_FREQ;
+ }
+
+ return freq;
+}
+
+static uint32_t CLOCK_GetFro1MFreq(void)
+{
+ return FRO1M_FREQ;
+}
+
+static uint32_t CLOCK_GetFro12MFreq(void)
+{
+ uint32_t freq = 0;
+
+ if (((PMC->FRO192M & PMC_FRO192M_DIVSEL_MASK) >>
+ PMC_FRO192M_DIVSEL_SHIFT) & FRO12M_ENA)
+ {
+ freq = FRO12M_FREQ;
+ }
+
+ return freq;
+}
+
+static uint32_t CLOCK_GetFro32MFreq(void)
+{
+ uint32_t freq = 0;
+
+ if (((PMC->FRO192M & PMC_FRO192M_DIVSEL_MASK) >>
+ PMC_FRO192M_DIVSEL_SHIFT) & FRO32M_ENA)
+ {
+ freq = FRO32M_FREQ;
+ }
+
+ return freq;
+}
+
+static uint32_t CLOCK_GetFro48MFreq(void)
+{
+ uint32_t freq = 0;
+
+ if (((PMC->FRO192M & PMC_FRO192M_DIVSEL_MASK) >>
+ PMC_FRO192M_DIVSEL_SHIFT) & FRO48M_ENA)
+ {
+ freq = FRO48M_FREQ;
+ }
+
+ return freq;
+}
+
+static uint32_t CLOCK_GetOsc32kFreq(void)
+{
+ uint32_t freq = 0;
+ if ((SYSCON->OSC32CLKSEL & SYSCON_OSC32CLKSEL_SEL32KHZ_MASK) != 0)
+ {
+ freq = CLOCK_GetXtal32kFreq();
+ }
+ else
+ {
+ freq = CLOCK_GetFro32kFreq();
+ }
+ return freq;
+}
+
+/* Return main clock rate */
+static uint32_t CLOCK_GetMainClockRate(void)
+{
+ uint32_t freq = 0;
+
+ switch ((main_clock_src_t)((SYSCON->MAINCLKSEL & SYSCON_MAINCLKSEL_SEL_MASK)
+ >> SYSCON_MAINCLKSEL_SEL_SHIFT))
+ {
+ case kCLOCK_MainFro12M:
+ freq = CLOCK_GetFro12MFreq();
+ break;
+
+ case kCLOCK_MainOsc32k:
+ freq = CLOCK_GetOsc32kFreq();
+ break;
+
+ case kCLOCK_MainXtal32M:
+ freq = CLOCK_GetXtal32MFreq();
+ break;
+
+ case kCLOCK_MainFro32M:
+ freq = CLOCK_GetFro32MFreq();
+ break;
+
+ case kCLOCK_MainFro48M:
+ freq = CLOCK_GetFro48MFreq();
+ break;
+
+ case kCLOCK_MainExtClk:
+ freq = g_Ext_Clk_Freq;
+ break;
+
+ case kCLOCK_MainFro1M:
+ freq = CLOCK_GetFro1MFreq();
+ break;
+ }
+
+ return freq;
+}
+
+
+
+/* ----------------------------------------------------------------------------
+ -- Core clock
+ ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+#if defined(__ICCARM__)
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//*****************************************************************************
+void ResetISR(void)
+{
+ __asm volatile(
+ "LDR R0,=0x40000804\t\n" // load co-processor boot address (from CPBOOT)
+ "LDR R0,[R0]\t\n" // get address to branch to
+ "MOVS R0,R0\t\n" // Check if 0
+ "BEQ.N masterboot\t\n" // if zero in boot reg, we just branch to real reset
+ "LDR R1,=0x40000808\t\n" // load co-processor stack pointer (from CPSTACK)
+ "LDR R1,[R1]\t\n"
+ "MOV SP,R1\t\n"
+ "BX R0\t\n" // branch to boot address
+ "masterboot:\t\n"
+ "LDR R0, =ResetISR2\t\n" // jump to 'real' reset handler
+ "BX R0\t\n");
+}
+
+void ResetISR2(void)
+{
+ if ((void (*)(void))WarmMain != NULL)
+ {
+ unsigned int warm_start;
+ uint32_t pmc_lpmode;
+ uint32_t pmc_resetcause;
+ uint32_t pwr_pdsleepcfg;
+
+ pmc_resetcause = PMC->RESETCAUSE;
+ pwr_pdsleepcfg = PMC->PDSLEEPCFG;
+
+ pmc_lpmode = BOOT_GetStartPowerMode();
+
+ warm_start = (pmc_lpmode == 0x02); /* coming from power down mode*/
+
+ // check if the reset cause is only a timer wakeup or io wakeup with all memory banks held
+ warm_start &= ( !(pmc_resetcause & (PMC_RESETCAUSE_POR_MASK
+ | PMC_RESETCAUSE_PADRESET_MASK
+ | PMC_RESETCAUSE_BODRESET_MASK
+ | PMC_RESETCAUSE_SYSTEMRESET_MASK
+ | PMC_RESETCAUSE_WDTRESET_MASK
+ | PMC_RESETCAUSE_WAKEUPIORESET_MASK ))
+ && ( pmc_resetcause & PMC_RESETCAUSE_WAKEUPPWDNRESET_MASK )
+ && ((pwr_pdsleepcfg & PMC_PDSLEEPCFG_PDEN_PD_MEM7_MASK) == 0x0 ) /* BANK7 memory bank held */
+ && ( pwr_pdsleepcfg & PMC_PDSLEEPCFG_PDEN_LDO_MEM_MASK ) /* LDO MEM enabled */
+ );
+
+ if (warm_start)
+ {
+
+ if (SYSCON->CPSTACK)
+ {
+ /* if CPSTACK is not NULL, switch to CPSTACK value so we avoid to corrupt the stack used before power down
+ * Note: it looks like enough to switch to new SP now and not earlier */
+ __asm volatile(
+ "LDR R1,=0x40000808\t\n" // load co-processor stack pointer (from CPSTACK)
+ "LDR R1,[R1]\t\n"
+ "MOV SP,R1\t\n"
+ );
+ }
+ // Check to see if we are running the code from a non-zero
+ // address (eg RAM, external flash), in which case we need
+ // to modify the VTOR register to tell the CPU that the
+ // vector table is located at a non-0x0 address.
+ unsigned int *pSCB_VTOR = (unsigned int *)0xE000ED08;
+ if (((unsigned int)(&__Vectors) != 0))
+ {
+ // CMSIS : SCB->VTOR = <address of vector table>
+ *pSCB_VTOR = (unsigned int)(&__Vectors);
+ }
+
+ if ((void (*)(void))SystemInit != NULL)
+ {
+ SystemInit();
+ }
+
+ WarmMain();
+
+ //
+ // WarmMain() shouldn't return, but if it does, we'll just enter an infinite loop
+ //
+ while (1)
+ {
+ ;
+ }
+ }
+ }
+
+ // Check to see if we are running the code from a non-zero
+ // address (eg RAM, external flash), in which case we need
+ // to modify the VTOR register to tell the CPU that the
+ // vector table is located at a non-0x0 address.
+ unsigned int *pSCB_VTOR = (unsigned int *)0xE000ED08;
+ if ((unsigned int)(&__Vectors) != 0)
+ {
+ // CMSIS : SCB->VTOR = <address of vector table>
+ *pSCB_VTOR = (unsigned int)(&__Vectors);
+ }
+
+ SystemInit();
+
+#if defined(__cplusplus)
+ //
+ // Call C++ library initialisation
+ //
+ __libc_init_array();
+#endif
+}
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- SystemInit()
+ ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+ uint32_t trim;
+ /* Initialise SystemCoreClock value */
+ SystemCoreClockUpdate();
+
+ /* Initialise NVIC priority grouping value */
+ NVIC_SetPriorityGrouping(4);
+
+ /* Apply FRO1M trim value */
+ trim = *(uint32_t*)(0x9FCD0U);
+
+ if(trim & 0x1U)
+ {
+ PMC->FRO1M = (PMC->FRO1M & ~PMC_FRO1M_FREQSEL_MASK) | ((trim>>1) & PMC_FRO1M_FREQSEL_MASK);
+ }
+}
+
+/* ----------------------------------------------------------------------------
+ -- SystemCoreClockUpdate()
+ ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+ SystemCoreClock = (CLOCK_GetMainClockRate() / ((SYSCON->AHBCLKDIV & SYSCON_AHBCLKDIV_DIV_MASK) + 1U));
+}
+
diff --git a/third_party/nxp/JN5189/system_JN5189.h b/third_party/nxp/JN5189DK6/devices/JN5189/system_JN5189.h
similarity index 100%
rename from third_party/nxp/JN5189/system_JN5189.h
rename to third_party/nxp/JN5189DK6/devices/JN5189/system_JN5189.h
diff --git a/third_party/nxp/JN5189DK6/devices/JN5189/utilities/debug_console/fsl_debug_console.c b/third_party/nxp/JN5189DK6/devices/JN5189/utilities/debug_console/fsl_debug_console.c
new file mode 100755
index 0000000..9f4b4ff
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/devices/JN5189/utilities/debug_console/fsl_debug_console.c
@@ -0,0 +1,1131 @@
+/*
+ * This is a modified version of the file printf.c, which was distributed
+ * by Motorola as part of the M5407C3BOOT.zip package used to initialize
+ * the M5407C3 evaluation board.
+ *
+ * Copyright:
+ * 1999-2000 MOTOROLA, INC. All Rights Reserved.
+ * You are hereby granted a copyright license to use, modify, and
+ * distribute the SOFTWARE so long as this entire notice is
+ * retained without alteration in any modified and/or redistributed
+ * versions, and that such modified versions are clearly identified
+ * as such. No licenses are granted by implication, estoppel or
+ * otherwise under any patents or trademarks of Motorola, Inc. This
+ * software is provided on an "AS IS" basis and without warranty.
+ *
+ * To the maximum extent permitted by applicable law, MOTOROLA
+ * DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING
+ * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
+ * PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE
+ * SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY
+ * ACCOMPANYING WRITTEN MATERIALS.
+ *
+ * To the maximum extent permitted by applicable law, IN NO EVENT
+ * SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING
+ * WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS
+ * INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
+ * LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
+ *
+ * Motorola assumes no responsibility for the maintenance and support
+ * of this software
+
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdarg.h>
+#include <stdlib.h>
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+#include <stdio.h>
+#endif
+
+#ifdef FSL_RTOS_FREE_RTOS
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "task.h"
+#endif
+
+#include "fsl_debug_console_conf.h"
+#include "fsl_str.h"
+
+#include "fsl_common.h"
+#include "serial_manager.h"
+
+#include "fsl_debug_console.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#ifndef NDEBUG
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
+#undef assert
+#define assert(n)
+#endif
+#endif
+
+#if SDK_DEBUGCONSOLE
+#define DEBUG_CONSOLE_FUNCTION_PREFIX
+#else
+#define DEBUG_CONSOLE_FUNCTION_PREFIX static
+#endif
+
+/*! @brief character backspace ASCII value */
+#define DEBUG_CONSOLE_BACKSPACE 127U
+
+/* lock definition */
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+
+static SemaphoreHandle_t s_debugConsoleReadSemaphore;
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+static SemaphoreHandle_t s_debugConsoleReadWaitSemaphore;
+#endif
+
+#elif (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM)
+
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+static volatile uint8_t s_debugConsoleReadWaitSemaphore;
+#endif
+
+#else
+
+#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */
+
+/*! @brief get current runing environment is ISR or not */
+#ifdef __CA7_REV
+#define IS_RUNNING_IN_ISR() SystemGetIRQNestingLevel()
+#else
+#define IS_RUNNING_IN_ISR() __get_IPSR()
+#endif /* __CA7_REV */
+
+/* semaphore definition */
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+
+/* mutex semaphore */
+#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex) ((mutex) = xSemaphoreCreateMutex())
+
+/* clang-format off */
+#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex) \
+{ \
+ if (IS_RUNNING_IN_ISR() == 0U) \
+ { \
+ (void)xSemaphoreGive(mutex); \
+ } \
+}
+
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) \
+{ \
+ if (IS_RUNNING_IN_ISR() == 0U) \
+ { \
+ (void)xSemaphoreTake(mutex, portMAX_DELAY); \
+ } \
+}
+
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) \
+{ \
+ if (IS_RUNNING_IN_ISR() == 0U) \
+ { \
+ result = xSemaphoreTake(mutex, 0U); \
+ } \
+ else \
+ { \
+ result = 1U; \
+ } \
+}
+/* clang-format on */
+
+/* Binary semaphore */
+#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary) ((binary) = xSemaphoreCreateBinary())
+#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) ((void)xSemaphoreTake(binary, portMAX_DELAY))
+#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) ((void)xSemaphoreGiveFromISR(binary, NULL))
+
+#elif (DEBUG_CONSOLE_SYNCHRONIZATION_BM == DEBUG_CONSOLE_SYNCHRONIZATION_MODE)
+
+#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex)
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex)
+#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex)
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) (result = 1U)
+
+#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary)
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) \
+ { \
+ while (!binary) \
+ { \
+ } \
+ binary = false; \
+ }
+#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) (binary = true)
+#else
+#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary)
+#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary)
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+/* add other implementation here
+ *such as :
+ * #elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DDEBUG_CONSOLE_SYNCHRONIZATION_xxx)
+ */
+
+#else
+
+#error RTOS type is not defined by DEBUG_CONSOLE_SYNCHRONIZATION_MODE.
+
+#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/* receive state structure */
+typedef struct _debug_console_write_ring_buffer
+{
+ uint32_t ringBufferSize;
+ volatile uint32_t ringHead;
+ volatile uint32_t ringTail;
+ uint8_t ringBuffer[DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN];
+} debug_console_write_ring_buffer_t;
+#endif
+
+typedef struct _debug_console_state_struct
+{
+ uint8_t serialHandleBuffer[SERIAL_MANAGER_HANDLE_SIZE];
+ serial_handle_t serialHandle; /*!< serial manager handle */
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+ debug_console_write_ring_buffer_t writeRingBuffer;
+ uint8_t readRingBuffer[DEBUG_CONSOLE_RECEIVE_BUFFER_LEN];
+#endif
+ uint8_t serialWriteHandleBuffer[SERIAL_MANAGER_WRITE_HANDLE_SIZE];
+ uint8_t serialReadHandleBuffer[SERIAL_MANAGER_READ_HANDLE_SIZE];
+} debug_console_state_struct_t;
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Debug console state information. */
+static debug_console_state_struct_t s_debugConsoleState;
+serial_handle_t g_serialHandle; /*!< serial manager handle */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief This is a printf call back function which is used to relocate the log to buffer
+ * or print the log immediately when the local buffer is full.
+ *
+ * @param[in] buf Buffer to store log.
+ * @param[in] indicator Buffer index.
+ * @param[in] val Target character to store.
+ * @param[in] len length of the character
+ *
+ */
+#if SDK_DEBUGCONSOLE
+static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, int len);
+#endif
+
+status_t DbgConsole_ReadOneCharacter(uint8_t *ch);
+int DbgConsole_SendData(uint8_t *ch, size_t size);
+int DbgConsole_SendDataReliable(uint8_t *ch, size_t size);
+int DbgConsole_ReadLine(uint8_t *buf, size_t size);
+int DbgConsole_ReadCharacter(uint8_t *ch);
+
+#if ((SDK_DEBUGCONSOLE > 0U) || \
+ ((SDK_DEBUGCONSOLE == 0U) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \
+ (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))))
+DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void);
+#endif
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+
+static void DbgConsole_SerialManagerTxCallback(void *callbackParam,
+ serial_manager_callback_message_t *message,
+ serial_manager_status_t status)
+{
+ debug_console_state_struct_t *ioState;
+ uint32_t sendDataLength;
+
+ if ((NULL == callbackParam) || (NULL == message))
+ {
+ return;
+ }
+
+ ioState = (debug_console_state_struct_t *)callbackParam;
+
+ ioState->writeRingBuffer.ringTail += message->length;
+ if (ioState->writeRingBuffer.ringTail >= ioState->writeRingBuffer.ringBufferSize)
+ {
+ ioState->writeRingBuffer.ringTail = 0U;
+ }
+
+ if (kStatus_SerialManager_Success == status)
+ {
+ if (ioState->writeRingBuffer.ringTail != ioState->writeRingBuffer.ringHead)
+ {
+ if (ioState->writeRingBuffer.ringHead > ioState->writeRingBuffer.ringTail)
+ {
+ sendDataLength = ioState->writeRingBuffer.ringHead - ioState->writeRingBuffer.ringTail;
+ }
+ else
+ {
+ sendDataLength = ioState->writeRingBuffer.ringBufferSize - ioState->writeRingBuffer.ringTail;
+ }
+
+ (void)SerialManager_WriteNonBlocking(
+ ((serial_write_handle_t)&ioState->serialWriteHandleBuffer[0]),
+ &ioState->writeRingBuffer.ringBuffer[ioState->writeRingBuffer.ringTail], sendDataLength);
+ }
+ }
+ else if (kStatus_SerialManager_Canceled == status)
+ {
+ ioState->writeRingBuffer.ringTail = 0U;
+ ioState->writeRingBuffer.ringHead = 0U;
+ }
+ else
+ {
+ /*MISRA rule 16.4*/
+ }
+}
+
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+
+static void DbgConsole_SerialManagerRxCallback(void *callbackParam,
+ serial_manager_callback_message_t *message,
+ serial_manager_status_t status)
+{
+ if ((NULL == callbackParam) || (NULL == message))
+ {
+ return;
+ }
+
+ if (kStatus_SerialManager_Notify == status)
+ {
+ }
+ else if (kStatus_SerialManager_Success == status)
+ {
+ /* release s_debugConsoleReadWaitSemaphore from RX callback */
+ DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(s_debugConsoleReadWaitSemaphore);
+ }
+ else
+ {
+ /*MISRA rule 16.4*/
+ }
+}
+#endif
+
+#endif
+
+status_t DbgConsole_ReadOneCharacter(uint8_t *ch)
+{
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \
+ (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)
+ return kStatus_Fail;
+#else
+ status_t status = (status_t)kStatus_SerialManager_Error;
+
+/* recieve one char every time */
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+ status = (status_t)SerialManager_ReadNonBlocking(
+ ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1);
+#else
+ status = (status_t)SerialManager_ReadBlocking(
+ ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1);
+#endif
+ if ((status_t)kStatus_SerialManager_Success != status)
+ {
+ return (status_t)kStatus_Fail;
+ }
+ /* wait s_debugConsoleReadWaitSemaphore from RX callback */
+ DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(s_debugConsoleReadWaitSemaphore);
+
+ return (status_t)kStatus_Success;
+#endif
+
+#else
+
+ return (status_t)kStatus_Fail;
+
+#endif
+}
+
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
+static status_t DbgConsole_EchoCharacter(uint8_t *ch, bool isGetChar, int *index)
+{
+ /* Due to scanf take \n and \r as end of string,should not echo */
+ if (((*ch != (uint8_t)'\r') && (*ch != (uint8_t)'\n')) || (isGetChar))
+ {
+ /* recieve one char every time */
+ if (1 != DbgConsole_SendDataReliable(ch, 1U))
+ {
+ return (status_t)kStatus_Fail;
+ }
+ }
+
+ if ((!isGetChar) && (index != NULL))
+ {
+ if (DEBUG_CONSOLE_BACKSPACE == *ch)
+ {
+ if ((*index >= 2))
+ {
+ *index -= 2;
+ }
+ else
+ {
+ *index = 0;
+ }
+ }
+ }
+
+ return (status_t)kStatus_Success;
+}
+#endif
+
+int DbgConsole_SendData(uint8_t *ch, size_t size)
+{
+ status_t status = (status_t)kStatus_SerialManager_Error;
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+ uint32_t sendDataLength;
+ int txBusy = 0;
+#endif
+ assert(NULL != ch);
+ assert(0 != size);
+
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+ uint32_t regPrimask = DisableGlobalIRQ();
+ if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)
+ {
+ txBusy = 1;
+ sendDataLength =
+ (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize -
+ s_debugConsoleState.writeRingBuffer.ringTail) %
+ s_debugConsoleState.writeRingBuffer.ringBufferSize;
+ }
+ else
+ {
+ sendDataLength = 0U;
+ }
+ sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength - 1;
+ if (sendDataLength <= size)
+ {
+ EnableGlobalIRQ(regPrimask);
+ return -1;
+ }
+ for (int i = 0; i < (int)size; i++)
+ {
+ s_debugConsoleState.writeRingBuffer.ringBuffer[s_debugConsoleState.writeRingBuffer.ringHead++] = ch[i];
+ if (s_debugConsoleState.writeRingBuffer.ringHead >= s_debugConsoleState.writeRingBuffer.ringBufferSize)
+ {
+ s_debugConsoleState.writeRingBuffer.ringHead = 0U;
+ }
+ }
+
+ status = (status_t)kStatus_SerialManager_Success;
+
+ if (txBusy == 0)
+ {
+ if (s_debugConsoleState.writeRingBuffer.ringHead > s_debugConsoleState.writeRingBuffer.ringTail)
+ {
+ sendDataLength =
+ s_debugConsoleState.writeRingBuffer.ringHead - s_debugConsoleState.writeRingBuffer.ringTail;
+ }
+ else
+ {
+ sendDataLength =
+ s_debugConsoleState.writeRingBuffer.ringBufferSize - s_debugConsoleState.writeRingBuffer.ringTail;
+ }
+
+ status = (status_t)SerialManager_WriteNonBlocking(
+ ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]),
+ &s_debugConsoleState.writeRingBuffer.ringBuffer[s_debugConsoleState.writeRingBuffer.ringTail],
+ sendDataLength);
+ }
+ EnableGlobalIRQ(regPrimask);
+#else
+ status = (status_t)SerialManager_WriteBlocking(
+ ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size);
+#endif
+ return (((status_t)kStatus_Success == status) ? (int)size : -1);
+}
+
+int DbgConsole_SendDataReliable(uint8_t *ch, size_t size)
+{
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+#if (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))
+ status_t status = kStatus_SerialManager_Error;
+ uint32_t sendDataLength;
+ uint32_t totalLength = size;
+ int sentLength;
+#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */
+#else
+ status_t status = kStatus_SerialManager_Error;
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+ assert(NULL != ch);
+ assert(0 != size);
+
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+
+#if (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))
+ do
+ {
+ uint32_t regPrimask = DisableGlobalIRQ();
+ if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)
+ {
+ sendDataLength =
+ (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize -
+ s_debugConsoleState.writeRingBuffer.ringTail) %
+ s_debugConsoleState.writeRingBuffer.ringBufferSize;
+ }
+ else
+ {
+ sendDataLength = 0U;
+ }
+ sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength - 1U;
+
+ if (sendDataLength > 0U)
+ {
+ if (sendDataLength > totalLength)
+ {
+ sendDataLength = totalLength;
+ }
+
+ sentLength = DbgConsole_SendData(&ch[size - totalLength], sendDataLength);
+ if (sentLength > 0)
+ {
+ totalLength = totalLength - (uint32_t)sentLength;
+ }
+ }
+ EnableGlobalIRQ(regPrimask);
+
+ if (totalLength != 0U)
+ {
+ status = DbgConsole_Flush();
+ if ((status_t)kStatus_Success != status)
+ {
+ break;
+ }
+ }
+ } while (totalLength != 0U);
+ return (status_t)(uint32_t)((uint32_t)size - totalLength);
+#else
+ return DbgConsole_SendData(ch, size);
+#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */
+
+#else
+ status = (status_t)SerialManager_WriteBlocking(
+ ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size);
+ return (((status_t)kStatus_Success == status) ? (int)size : -1);
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+}
+
+int DbgConsole_ReadLine(uint8_t *buf, size_t size)
+{
+ int i = 0;
+
+ assert(buf != NULL);
+
+ /* take mutex lock function */
+ DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore);
+
+ do
+ {
+ /* recieve one char every time */
+ if ((status_t)kStatus_Success != DbgConsole_ReadOneCharacter(&buf[i]))
+ {
+ /* release mutex lock function */
+ DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
+ i = -1;
+ break;
+ }
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
+ (void)DbgConsole_EchoCharacter(&buf[i], false, &i);
+#endif
+ /* analysis data */
+ if (((uint8_t)'\r' == buf[i]) || ((uint8_t)'\n' == buf[i]))
+ {
+ /* End of Line. */
+ if (0 == i)
+ {
+ buf[i] = (uint8_t)'\0';
+ continue;
+ }
+ else
+ {
+ break;
+ }
+ }
+ i++;
+ } while (i < (int)size);
+
+ /* get char should not add '\0'*/
+ if (i == (int)size)
+ {
+ buf[i] = (uint8_t)'\0';
+ }
+ else
+ {
+ buf[i + 1] = (uint8_t)'\0';
+ }
+
+ /* release mutex lock function */
+ DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
+
+ return i;
+}
+
+int DbgConsole_ReadCharacter(uint8_t *ch)
+{
+ int ret;
+
+ assert(ch);
+
+ /* take mutex lock function */
+ DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore);
+ /* read one character */
+ if ((status_t)kStatus_Success == DbgConsole_ReadOneCharacter(ch))
+ {
+ ret = 1;
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
+ (void)DbgConsole_EchoCharacter(ch, true, NULL);
+#endif
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ /* release mutex lock function */
+ DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
+
+ return ret;
+}
+
+#if SDK_DEBUGCONSOLE
+static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, int len)
+{
+ int i = 0;
+
+ for (i = 0; i < len; i++)
+ {
+ if (((uint32_t)*indicator + 1UL) >= DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN)
+ {
+ (void)DbgConsole_SendDataReliable((uint8_t *)buf, (uint32_t)(*indicator));
+ *indicator = 0;
+ }
+
+ buf[*indicator] = dbgVal;
+ (*indicator)++;
+ }
+}
+#endif
+
+/*************Code for DbgConsole Init, Deinit, Printf, Scanf *******************************/
+
+/* See fsl_debug_console.h for documentation of this function. */
+status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq)
+{
+ serial_manager_config_t serialConfig;
+ status_t status = (status_t)kStatus_SerialManager_Error;
+
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ serial_port_uart_config_t uartConfig = {
+ .instance = instance,
+ .clockRate = clkSrcFreq,
+ .baudRate = baudRate,
+ .parityMode = kSerialManager_UartParityDisabled,
+ .stopBitCount = kSerialManager_UartOneStopBit,
+ .enableRx = 1,
+ .enableTx = 1,
+ };
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ serial_port_usb_cdc_config_t usbCdcConfig = {
+ .controllerIndex = (serial_port_usb_cdc_controller_index_t)instance,
+ };
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ serial_port_swo_config_t swoConfig = {
+ .clockRate = clkSrcFreq,
+ .baudRate = baudRate,
+ .port = instance,
+ .protocol = kSerialManager_SwoProtocolNrz,
+ };
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ serial_port_usb_cdc_virtual_config_t usbCdcVirtualConfig = {
+ .controllerIndex = (serial_port_usb_cdc_virtual_controller_index_t)instance,
+ };
+#endif
+ serialConfig.type = device;
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+ serialConfig.ringBuffer = &s_debugConsoleState.readRingBuffer[0];
+ serialConfig.ringBufferSize = DEBUG_CONSOLE_RECEIVE_BUFFER_LEN;
+#endif
+
+ if (kSerialPort_Uart == device)
+ {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ serialConfig.portConfig = &uartConfig;
+#else
+ return status;
+#endif
+ }
+ else if (kSerialPort_UsbCdc == device)
+ {
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ serialConfig.portConfig = &usbCdcConfig;
+#else
+ return status;
+#endif
+ }
+ else if (kSerialPort_Swo == device)
+ {
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ serialConfig.portConfig = &swoConfig;
+#else
+ return status;
+#endif
+ }
+ else if (kSerialPort_UsbCdcVirtual == device)
+ {
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ serialConfig.portConfig = &usbCdcVirtualConfig;
+#else
+ return status;
+#endif
+ }
+ else
+ {
+ return status;
+ }
+
+ (void)memset(&s_debugConsoleState, 0, sizeof(s_debugConsoleState));
+
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+ s_debugConsoleState.writeRingBuffer.ringBufferSize = DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN;
+#endif
+
+ s_debugConsoleState.serialHandle = (serial_handle_t)&s_debugConsoleState.serialHandleBuffer[0];
+ status = (status_t)SerialManager_Init(s_debugConsoleState.serialHandle, &serialConfig);
+
+ assert(kStatus_SerialManager_Success == status);
+
+ DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+ DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore);
+#endif
+
+ {
+ status = (status_t)SerialManager_OpenWriteHandle(
+ s_debugConsoleState.serialHandle, ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]));
+ assert(kStatus_SerialManager_Success == status);
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+ (void)SerialManager_InstallTxCallback(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]),
+ DbgConsole_SerialManagerTxCallback, &s_debugConsoleState);
+#endif
+ }
+
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+ {
+ status = (status_t)SerialManager_OpenReadHandle(
+ s_debugConsoleState.serialHandle, ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]));
+ assert(kStatus_SerialManager_Success == status);
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+ (void)SerialManager_InstallRxCallback(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]),
+ DbgConsole_SerialManagerRxCallback, &s_debugConsoleState);
+#endif
+ }
+#endif
+
+ g_serialHandle = s_debugConsoleState.serialHandle;
+
+ return kStatus_Success;
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+status_t DbgConsole_Deinit(void)
+{
+ {
+ if (s_debugConsoleState.serialHandle != NULL)
+ {
+ (void)SerialManager_CloseWriteHandle(
+ ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]));
+ }
+ }
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+ {
+ if (s_debugConsoleState.serialHandle != NULL)
+ {
+ (void)SerialManager_CloseReadHandle(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]));
+ }
+ }
+#endif
+ if (s_debugConsoleState.serialHandle)
+ {
+ if (kStatus_SerialManager_Success == SerialManager_Deinit(s_debugConsoleState.serialHandle))
+ {
+ s_debugConsoleState.serialHandle = NULL;
+ g_serialHandle = NULL;
+ }
+ }
+ return (status_t)kStatus_Success;
+}
+
+#if ((SDK_DEBUGCONSOLE > 0U) || \
+ ((SDK_DEBUGCONSOLE == 0U) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \
+ (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))))
+DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void)
+{
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)
+
+ if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)
+ {
+ return (status_t)kStatus_Fail;
+ }
+
+#else
+
+ while (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)
+ {
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+ if (0U == IS_RUNNING_IN_ISR())
+ {
+ if (taskSCHEDULER_RUNNING == xTaskGetSchedulerState())
+ {
+ vTaskDelay(1);
+ }
+ }
+ else
+ {
+ return (status_t)kStatus_Fail;
+ }
+#endif
+ }
+
+#endif
+
+#endif
+ return (status_t)kStatus_Success;
+}
+#endif
+
+#if SDK_DEBUGCONSOLE
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Printf(const char *formatString, ...)
+{
+ va_list ap;
+ int logLength = 0, dbgResult = 0;
+ char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {'\0'};
+
+ if (NULL == g_serialHandle)
+ {
+ return 0;
+ }
+
+ va_start(ap, formatString);
+ /* format print log first */
+ logLength = StrFormatPrintf(formatString, ap, printBuf, DbgConsole_PrintCallback);
+ /* print log */
+ dbgResult = DbgConsole_SendDataReliable((uint8_t *)printBuf, (size_t)logLength);
+
+ va_end(ap);
+
+ return dbgResult;
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Putchar(int ch)
+{
+ /* print char */
+ return DbgConsole_SendDataReliable((uint8_t *)&ch, 1U);
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Scanf(char *formatString, ...)
+{
+ va_list ap;
+ int formatResult;
+ char scanfBuf[DEBUG_CONSOLE_SCANF_MAX_LOG_LEN + 1U] = {'\0'};
+
+ /* scanf log */
+ (void)DbgConsole_ReadLine((uint8_t *)scanfBuf, DEBUG_CONSOLE_SCANF_MAX_LOG_LEN);
+ /* get va_list */
+ va_start(ap, formatString);
+ /* format scanf log */
+ formatResult = StrFormatScanf(scanfBuf, formatString, ap);
+
+ va_end(ap);
+
+ return formatResult;
+}
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+status_t DbgConsole_TryGetchar(char *ch)
+{
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+ uint32_t length = 0;
+ status_t status = (status_t)kStatus_Fail;
+
+ assert(ch);
+
+ /* take mutex lock function */
+ DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore);
+
+ if (kStatus_SerialManager_Success ==
+ SerialManager_TryRead(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), (uint8_t *)ch, 1,
+ &length))
+ {
+ if (length != 0U)
+ {
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
+ (void)DbgConsole_EchoCharacter((uint8_t *)ch, true, NULL);
+#endif
+ status = (status_t)kStatus_Success;
+ }
+ }
+ /* release mutex lock function */
+ DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
+ return status;
+#else
+ return (status_t)kStatus_Fail;
+#endif
+}
+#endif
+
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Getchar(void)
+{
+ uint8_t ch = 0U;
+
+ /* Get char */
+ (void)DbgConsole_ReadCharacter(&ch);
+
+ return (int)ch;
+}
+
+#endif /* SDK_DEBUGCONSOLE */
+
+/*************Code to support toolchain's printf, scanf *******************************/
+/* These function __write and __read is used to support IAR toolchain to printf and scanf*/
+#if (defined(__ICCARM__))
+#if defined(SDK_DEBUGCONSOLE_UART)
+#pragma weak __write
+size_t __write(int handle, const unsigned char *buffer, size_t size)
+{
+ if (buffer == 0)
+ {
+ /*
+ * This means that we should flush internal buffers. Since we don't we just return.
+ * (Remember, "handle" == -1 means that all handles should be flushed.)
+ */
+ return 0;
+ }
+
+ /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
+ if ((handle != 1) && (handle != 2))
+ {
+ return ((size_t)-1);
+ }
+
+ /* Send data. */
+ DbgConsole_SendDataReliable((uint8_t *)buffer, size);
+
+ return size;
+}
+
+#pragma weak __read
+size_t __read(int handle, unsigned char *buffer, size_t size)
+{
+ uint8_t ch = 0U;
+ int actualSize = 0U;
+
+ /* This function only reads from "standard in", for all other file handles it returns failure. */
+ if (handle != 0)
+ {
+ return ((size_t)-1);
+ }
+
+ /* Receive data.*/
+ for (; size > 0; size--)
+ {
+ DbgConsole_ReadCharacter(&ch);
+ if (ch == 0)
+ {
+ break;
+ }
+
+ *buffer++ = ch;
+ actualSize++;
+ }
+
+ return actualSize;
+}
+#endif /* SDK_DEBUGCONSOLE_UART */
+
+/* support LPC Xpresso with RedLib */
+#elif (defined(__REDLIB__))
+
+#if (defined(SDK_DEBUGCONSOLE_UART))
+int __attribute__((weak)) __sys_write(int handle, char *buffer, int size)
+{
+ if (buffer == 0)
+ {
+ /* return -1 if error. */
+ return -1;
+ }
+
+ /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
+ if ((handle != 1) && (handle != 2))
+ {
+ return -1;
+ }
+
+ /* Send data. */
+ DbgConsole_SendDataReliable((uint8_t *)buffer, size);
+
+ return 0;
+}
+
+int __attribute__((weak)) __sys_readc(void)
+{
+ char tmp;
+
+ /* Receive data. */
+ DbgConsole_ReadCharacter((uint8_t *)&tmp);
+
+ return tmp;
+}
+#endif
+
+/* These function fputc and fgetc is used to support KEIL toolchain to printf and scanf*/
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+#if defined(SDK_DEBUGCONSOLE_UART)
+#if defined(__CC_ARM)
+struct __FILE
+{
+ int handle;
+ /*
+ * Whatever you require here. If the only file you are using is standard output using printf() for debugging,
+ * no file handling is required.
+ */
+};
+#endif
+
+/* FILE is typedef in stdio.h. */
+#pragma weak __stdout
+#pragma weak __stdin
+FILE __stdout;
+FILE __stdin;
+
+#pragma weak fputc
+int fputc(int ch, FILE *f)
+{
+ /* Send data. */
+ return DbgConsole_SendDataReliable((uint8_t *)(&ch), 1);
+}
+
+#pragma weak fgetc
+int fgetc(FILE *f)
+{
+ char ch;
+
+ /* Receive data. */
+ DbgConsole_ReadCharacter((uint8_t *)&ch);
+
+ return ch;
+}
+
+/*
+ * Terminate the program, passing a return code back to the user.
+ * This function may not return.
+ */
+void _sys_exit(int returncode)
+{
+ while (1)
+ {
+ }
+}
+
+/*
+ * Writes a character to the output channel. This function is used
+ * for last-resort error message output.
+ */
+void _ttywrch(int ch)
+{
+ char ench = ch;
+ DbgConsole_SendDataReliable((uint8_t *)(&ench), 1);
+}
+
+char *_sys_command_string(char *cmd, int len)
+{
+ return (cmd);
+}
+#endif /* SDK_DEBUGCONSOLE_UART */
+
+/* These function __write and __read is used to support ARM_GCC, KDS, Atollic toolchains to printf and scanf*/
+#elif (defined(__GNUC__))
+
+#if ((defined(__GNUC__) && (!defined(__MCUXPRESSO)) && (defined(SDK_DEBUGCONSOLE_UART))) || \
+ (defined(__MCUXPRESSO) && (defined(SDK_DEBUGCONSOLE_UART))))
+int __attribute__((weak)) _write(int handle, char *buffer, int size);
+int __attribute__((weak)) _write(int handle, char *buffer, int size)
+{
+ if (buffer == NULL)
+ {
+ /* return -1 if error. */
+ return -1;
+ }
+
+ /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
+ if ((handle != 1) && (handle != 2))
+ {
+ return -1;
+ }
+
+ /* Send data. */
+ (void)DbgConsole_SendDataReliable((uint8_t *)buffer, (size_t)size);
+
+ return size;
+}
+
+int __attribute__((weak)) _read(int handle, char *buffer, int size);
+int __attribute__((weak)) _read(int handle, char *buffer, int size)
+{
+ uint8_t ch = 0U;
+ int actualSize = 0;
+
+ /* This function only reads from "standard in", for all other file handles it returns failure. */
+ if (handle != 0)
+ {
+ return -1;
+ }
+
+ /* Receive data. */
+ for (; size > 0; size--)
+ {
+ if (DbgConsole_ReadCharacter(&ch) < 0)
+ {
+ break;
+ }
+
+ *buffer++ = (char)ch;
+ actualSize++;
+
+ if ((ch == 0U) || (ch == (uint8_t)'\n') || (ch == (uint8_t)'\r'))
+ {
+ break;
+ }
+ }
+
+ return (actualSize > 0) ? actualSize : -1;
+}
+#endif
+
+#endif /* __ICCARM__ */
diff --git a/third_party/nxp/JN5189DK6/devices/JN5189/utilities/debug_console/fsl_debug_console.h b/third_party/nxp/JN5189DK6/devices/JN5189/utilities/debug_console/fsl_debug_console.h
new file mode 100755
index 0000000..9adf809
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/devices/JN5189/utilities/debug_console/fsl_debug_console.h
@@ -0,0 +1,227 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Debug console shall provide input and output functions to scan and print formatted data.
+ * o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier"
+ * - [flags] :'-', '+', '#', ' ', '0'
+ * - [width]: number (0,1...)
+ * - [.precision]: number (0,1...)
+ * - [length]: do not support
+ * - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n'
+ * o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier"
+ * - [*]: is supported.
+ * - [width]: number (0,1...)
+ * - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t')
+ * - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's'
+ */
+
+#ifndef _FSL_DEBUGCONSOLE_H_
+#define _FSL_DEBUGCONSOLE_H_
+
+#include "fsl_common.h"
+#include "serial_manager.h"
+
+/*!
+ * @addtogroup debugconsole
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+extern serial_handle_t g_serialHandle; /*!< serial manager handle */
+
+/*! @brief Definition select redirect toolchain printf, scanf to uart or not. */
+#define DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN 0U /*!< Select toolchain printf and scanf. */
+#define DEBUGCONSOLE_REDIRECT_TO_SDK 1U /*!< Select SDK version printf, scanf. */
+#define DEBUGCONSOLE_DISABLE 2U /*!< Disable debugconsole function. */
+
+/*! @brief Definition to select sdk or toolchain printf, scanf. The macro only support
+ * to be redefined in project setting.
+ */
+#ifndef SDK_DEBUGCONSOLE
+#define SDK_DEBUGCONSOLE 1U
+#endif
+
+/*! @brief whether provide low level IO implementation to toolchain printf and scanf.
+ * For example, within MCUXpresso, if the macro SDK_DEBUGCONSOLE_UART is defined,
+ * __sys_write and __sys_readc will be used when __REDLIB__ is defined;
+ * _write and _read will be used in other cases.
+ * If the macro SDK_DEBUGCONSOLE_UART is not defined, the semihost will be used.
+ */
+#ifndef SDK_DEBUGCONSOLE_UART
+/* mcux will handle this macro, not define it here */
+#if (!defined(__MCUXPRESSO))
+#define SDK_DEBUGCONSOLE_UART
+#endif
+#endif
+
+#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE)
+#include <stdio.h>
+#endif
+
+/*! @brief Definition to select redirect toolchain printf, scanf to uart or not.
+ *
+ * if SDK_DEBUGCONSOLE defined to 0,it represents select toolchain printf, scanf.
+ * if SDK_DEBUGCONSOLE defined to 1,it represents select SDK version printf, scanf.
+ * if SDK_DEBUGCONSOLE defined to 2,it represents disable debugconsole function.
+ */
+#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE /* Disable debug console */
+#define PRINTF(...) \
+ do \
+ { \
+ } while (0)
+#define SCANF(...) \
+ do \
+ { \
+ } while (0)
+#define PUTCHAR(...) \
+ do \
+ { \
+ } while (0)
+#define GETCHAR() -1
+#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK /* Select printf, scanf, putchar, getchar of SDK version. */
+#define PRINTF DbgConsole_Printf
+#define SCANF DbgConsole_Scanf
+#define PUTCHAR DbgConsole_Putchar
+#define GETCHAR DbgConsole_Getchar
+#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN /* Select printf, scanf, putchar, getchar of toolchain. \ \
+ */
+#define PRINTF printf
+#define SCANF scanf
+#define PUTCHAR putchar
+#define GETCHAR getchar
+#endif /* SDK_DEBUGCONSOLE */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*! @name Initialization*/
+/* @{ */
+
+/*!
+ * @brief Initializes the peripheral used for debug messages.
+ *
+ * Call this function to enable debug log messages to be output via the specified peripheral
+ * initialized by the serial manager module.
+ * After this function has returned, stdout and stdin are connected to the selected peripheral.
+ *
+ * @param instance The instance of the module.
+ * @param baudRate The desired baud rate in bits per second.
+ * @param device Low level device type for the debug console, can be one of the following.
+ * @arg kSerialPort_Uart,
+ * @arg kSerialPort_UsbCdc
+ * @arg kSerialPort_UsbCdcVirtual.
+ * @param clkSrcFreq Frequency of peripheral source clock.
+ *
+ * @return Indicates whether initialization was successful or not.
+ * @retval kStatus_Success Execution successfully
+ */
+status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq);
+
+/*!
+ * @brief De-initializes the peripheral used for debug messages.
+ *
+ * Call this function to disable debug log messages to be output via the specified peripheral
+ * initialized by the serial manager module.
+ *
+ * @return Indicates whether de-initialization was successful or not.
+ */
+status_t DbgConsole_Deinit(void);
+
+#if SDK_DEBUGCONSOLE
+/*!
+ * @brief Writes formatted output to the standard output stream.
+ *
+ * Call this function to write a formatted output to the standard output stream.
+ *
+ * @param formatString Format control string.
+ * @return Returns the number of characters printed or a negative value if an error occurs.
+ */
+int DbgConsole_Printf(const char *formatString, ...);
+
+/*!
+ * @brief Writes a character to stdout.
+ *
+ * Call this function to write a character to stdout.
+ *
+ * @param ch Character to be written.
+ * @return Returns the character written.
+ */
+int DbgConsole_Putchar(int ch);
+
+/*!
+ * @brief Reads formatted data from the standard input stream.
+ *
+ * Call this function to read formatted data from the standard input stream.
+ *
+ * @note Due the limitation in the BM OSA environment (CPU is blocked in the function,
+ * other tasks will not be scheduled), the function cannot be used when the
+ * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment.
+ * And an error is returned when the function called in this case. The suggestion
+ * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char.
+ *
+ * @param formatString Format control string.
+ * @return Returns the number of fields successfully converted and assigned.
+ */
+int DbgConsole_Scanf(char *formatString, ...);
+
+/*!
+ * @brief Reads a character from standard input.
+ *
+ * Call this function to read a character from standard input.
+ *
+ * @note Due the limitation in the BM OSA environment (CPU is blocked in the function,
+ * other tasks will not be scheduled), the function cannot be used when the
+ * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment.
+ * And an error is returned when the function called in this case. The suggestion
+ * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char.
+ *
+ * @return Returns the character read.
+ */
+int DbgConsole_Getchar(void);
+
+/*!
+ * @brief Debug console flush.
+ *
+ * Call this function to wait the tx buffer empty.
+ * If interrupt transfer is using, make sure the global IRQ is enable before call this function
+ * This function should be called when
+ * 1, before enter power down mode
+ * 2, log is required to print to terminal immediately
+ * @return Indicates whether wait idle was successful or not.
+ */
+status_t DbgConsole_Flush(void);
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/*!
+ * @brief Debug console try to get char
+ * This function provides a API which will not block current task, if character is
+ * available return it, otherwise return fail.
+ * @param ch the address of char to receive
+ * @return Indicates get char was successful or not.
+ */
+status_t DbgConsole_TryGetchar(char *ch);
+#endif
+
+#endif /* SDK_DEBUGCONSOLE */
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_DEBUGCONSOLE_H_ */
diff --git a/third_party/nxp/JN5189DK6/devices/JN5189/utilities/debug_console/fsl_debug_console_conf.h b/third_party/nxp/JN5189DK6/devices/JN5189/utilities/debug_console/fsl_debug_console_conf.h
new file mode 100755
index 0000000..366c6cd
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/devices/JN5189/utilities/debug_console/fsl_debug_console_conf.h
@@ -0,0 +1,158 @@
+/*
+ * Copyright 2017 - 2019 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_DEBUG_CONSOLE_CONF_H_
+#define _FSL_DEBUG_CONSOLE_CONF_H_
+
+/****************Debug console configuration********************/
+
+/*! @brief If Non-blocking mode is needed, please define it at project setting,
+ * otherwise blocking mode is the default transfer mode.
+ * Warning: If you want to use non-blocking transfer,please make sure the corresponding
+ * IO interrupt is enable, otherwise there is no output.
+ * And non-blocking is combine with buffer, no matter bare-metal or rtos.
+ * Below shows how to configure in your project if you want to use non-blocking mode.
+ * For IAR, right click project and select "Options", define it in "C/C++ Compiler->Preprocessor->Defined symbols".
+ * For KEIL, click "Options for Target…", define it in "C/C++->Preprocessor Symbols->Define".
+ * For ARMGCC, open CmakeLists.txt and add the following lines,
+ * "SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for debug target.
+ * "SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for release target.
+ * For MCUxpresso, right click project and select "Properties", define it in "C/C++ Build->Settings->MCU C
+ * Complier->Preprocessor".
+ *
+ */
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/*! @brief define the transmit buffer length which is used to store the multi task log, buffer is enabled automatically
+ * when
+ * non-blocking transfer is using,
+ * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.
+ * If it is configured too small, log maybe missed , because the log will not be
+ * buffered if the buffer is full, and the print will return immediately with -1.
+ * And this value should be multiple of 4 to meet memory alignment.
+ *
+ */
+#ifndef DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN
+#define DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN (512U)
+#endif /* DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN */
+
+/*! @brief define the receive buffer length which is used to store the user input, buffer is enabled automatically when
+ * non-blocking transfer is using,
+ * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.
+ * If it is configured too small, log maybe missed, because buffer will be overwrited if buffer is too small.
+ * And this value should be multiple of 4 to meet memory alignment.
+ *
+ */
+#ifndef DEBUG_CONSOLE_RECEIVE_BUFFER_LEN
+#define DEBUG_CONSOLE_RECEIVE_BUFFER_LEN (1024U)
+#endif /* DEBUG_CONSOLE_RECEIVE_BUFFER_LEN */
+
+/*!@ brief Whether enable the reliable TX function
+ * If the macro is zero, the reliable TX function of the debug console is disabled.
+ * When the macro is zero, the string of PRINTF will be thrown away after the transmit buffer is full.
+ */
+#ifndef DEBUG_CONSOLE_TX_RELIABLE_ENABLE
+#define DEBUG_CONSOLE_TX_RELIABLE_ENABLE (1U)
+#endif /* DEBUG_CONSOLE_RX_ENABLE */
+
+#else
+#define DEBUG_CONSOLE_TRANSFER_BLOCKING
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+/*!@ brief Whether enable the RX function
+ * If the macro is zero, the receive function of the debug console is disabled.
+ */
+#ifndef DEBUG_CONSOLE_RX_ENABLE
+#define DEBUG_CONSOLE_RX_ENABLE (1U)
+#endif /* DEBUG_CONSOLE_RX_ENABLE */
+
+/*!@ brief define the MAX log length debug console support , that is when you call printf("log", x);, the log
+ * length can not bigger than this value.
+ * This macro decide the local log buffer length, the buffer locate at stack, the stack maybe overflow if
+ * the buffer is too big and current task stack size not big enough.
+ */
+#ifndef DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN
+#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN (128U)
+#endif /* DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN */
+
+/*!@ brief define the buffer support buffer scanf log length, that is when you call scanf("log", &x);, the log
+ * length can not bigger than this value.
+ * As same as the DEBUG_CONSOLE_BUFFER_PRINTF_MAX_LOG_LEN.
+ */
+#ifndef DEBUG_CONSOLE_SCANF_MAX_LOG_LEN
+#define DEBUG_CONSOLE_SCANF_MAX_LOG_LEN (20U)
+#endif /* DEBUG_CONSOLE_SCANF_MAX_LOG_LEN */
+
+/*! @brief Debug console synchronization
+ * User should not change these macro for synchronization mode, but add the
+ * corresponding synchronization mechanism per different software environment.
+ * Such as, if another RTOS is used,
+ * add:
+ * #define DEBUG_CONSOLE_SYNCHRONIZATION_XXXX 3
+ * in this configuration file and implement the synchronization in fsl.log.c.
+ */
+/*! @brief synchronization for baremetal software */
+#define DEBUG_CONSOLE_SYNCHRONIZATION_BM 0
+/*! @brief synchronization for freertos software */
+#define DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS 1
+
+/*! @brief RTOS synchronization mechanism disable
+ * If not defined, default is enable, to avoid multitask log print mess.
+ * If other RTOS is used, you can implement the RTOS's specific synchronization mechanism in fsl.log.c
+ * If synchronization is disabled, log maybe messed on terminal.
+ */
+#ifndef DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+#ifdef FSL_RTOS_FREE_RTOS
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS
+#else
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM
+#endif /* FSL_RTOS_FREE_RTOS */
+#else
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+#endif /* DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION */
+
+/*! @brief echo function support
+ * If you want to use the echo function,please define DEBUG_CONSOLE_ENABLE_ECHO
+ * at your project setting.
+ */
+#ifndef DEBUG_CONSOLE_ENABLE_ECHO
+#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 0
+#else
+#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 1
+#endif /* DEBUG_CONSOLE_ENABLE_ECHO */
+
+/*********************************************************************/
+
+/***************Debug console other configuration*********************/
+/*! @brief Definition to printf the float number. */
+#ifndef PRINTF_FLOAT_ENABLE
+#define PRINTF_FLOAT_ENABLE 0U
+#endif /* PRINTF_FLOAT_ENABLE */
+
+/*! @brief Definition to scanf the float number. */
+#ifndef SCANF_FLOAT_ENABLE
+#define SCANF_FLOAT_ENABLE 0U
+#endif /* SCANF_FLOAT_ENABLE */
+
+/*! @brief Definition to support advanced format specifier for printf. */
+#ifndef PRINTF_ADVANCED_ENABLE
+#define PRINTF_ADVANCED_ENABLE 0U
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+/*! @brief Definition to support advanced format specifier for scanf. */
+#ifndef SCANF_ADVANCED_ENABLE
+#define SCANF_ADVANCED_ENABLE 0U
+#endif /* SCANF_ADVANCED_ENABLE */
+
+/*! @brief Definition to select virtual com(USB CDC) as the debug console. */
+#ifndef BOARD_USE_VIRTUALCOM
+#define BOARD_USE_VIRTUALCOM 0U
+#endif
+/*******************************************************************/
+
+#endif /* _FSL_DEBUG_CONSOLE_CONF_H_ */
diff --git a/third_party/nxp/JN5189/drivers/fsl_assert.c b/third_party/nxp/JN5189DK6/devices/JN5189/utilities/fsl_assert.c
similarity index 99%
rename from third_party/nxp/JN5189/drivers/fsl_assert.c
rename to third_party/nxp/JN5189DK6/devices/JN5189/utilities/fsl_assert.c
index b33ad7a..9052faf 100755
--- a/third_party/nxp/JN5189/drivers/fsl_assert.c
+++ b/third_party/nxp/JN5189DK6/devices/JN5189/utilities/fsl_assert.c
@@ -6,6 +6,7 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+
#include "fsl_common.h"
#include "fsl_debug_console.h"
diff --git a/third_party/nxp/JN5189DK6/devices/JN5189/utilities/str/fsl_str.c b/third_party/nxp/JN5189DK6/devices/JN5189/utilities/str/fsl_str.c
new file mode 100755
index 0000000..c4d1a0c
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/devices/JN5189/utilities/str/fsl_str.c
@@ -0,0 +1,1324 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include <math.h>
+#include <stdarg.h>
+#include <stdlib.h>
+#include "fsl_str.h"
+#include "fsl_debug_console_conf.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief The overflow value.*/
+#ifndef HUGE_VAL
+#define HUGE_VAL (99.e99)
+#endif /* HUGE_VAL */
+
+#if PRINTF_ADVANCED_ENABLE
+/*! @brief Specification modifier flags for printf. */
+enum _debugconsole_printf_flag
+{
+ kPRINTF_Minus = 0x01U, /*!< Minus FLag. */
+ kPRINTF_Plus = 0x02U, /*!< Plus Flag. */
+ kPRINTF_Space = 0x04U, /*!< Space Flag. */
+ kPRINTF_Zero = 0x08U, /*!< Zero Flag. */
+ kPRINTF_Pound = 0x10U, /*!< Pound Flag. */
+ kPRINTF_LengthChar = 0x20U, /*!< Length: Char Flag. */
+ kPRINTF_LengthShortInt = 0x40U, /*!< Length: Short Int Flag. */
+ kPRINTF_LengthLongInt = 0x80U, /*!< Length: Long Int Flag. */
+ kPRINTF_LengthLongLongInt = 0x100U, /*!< Length: Long Long Int Flag. */
+};
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+/*! @brief Specification modifier flags for scanf. */
+enum _debugconsole_scanf_flag
+{
+ kSCANF_Suppress = 0x2U, /*!< Suppress Flag. */
+ kSCANF_DestMask = 0x7cU, /*!< Destination Mask. */
+ kSCANF_DestChar = 0x4U, /*!< Destination Char Flag. */
+ kSCANF_DestString = 0x8U, /*!< Destination String FLag. */
+ kSCANF_DestSet = 0x10U, /*!< Destination Set Flag. */
+ kSCANF_DestInt = 0x20U, /*!< Destination Int Flag. */
+ kSCANF_DestFloat = 0x30U, /*!< Destination Float Flag. */
+ kSCANF_LengthMask = 0x1f00U, /*!< Length Mask Flag. */
+#if SCANF_ADVANCED_ENABLE
+ kSCANF_LengthChar = 0x100U, /*!< Length Char Flag. */
+ kSCANF_LengthShortInt = 0x200U, /*!< Length ShortInt Flag. */
+ kSCANF_LengthLongInt = 0x400U, /*!< Length LongInt Flag. */
+ kSCANF_LengthLongLongInt = 0x800U, /*!< Length LongLongInt Flag. */
+#endif /* SCANF_ADVANCED_ENABLE */
+#if SCANF_FLOAT_ENABLE
+ kSCANF_LengthLongLongDouble = 0x1000U, /*!< Length LongLongDuoble Flag. */
+#endif /*PRINTF_FLOAT_ENABLE */
+ kSCANF_TypeSinged = 0x2000U, /*!< TypeSinged Flag. */
+};
+
+/*! @brief Keil: suppress ellipsis warning in va_arg usage below. */
+#if defined(__CC_ARM)
+#pragma diag_suppress 1256
+#endif /* __CC_ARM */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Scanline function which ignores white spaces.
+ *
+ * @param[in] s The address of the string pointer to update.
+ * @return String without white spaces.
+ */
+static uint32_t ScanIgnoreWhiteSpace(const char **s);
+
+/*!
+ * @brief Converts a radix number to a string and return its length.
+ *
+ * @param[in] numstr Converted string of the number.
+ * @param[in] nump Pointer to the number.
+ * @param[in] neg Polarity of the number.
+ * @param[in] radix The radix to be converted to.
+ * @param[in] use_caps Used to identify %x/X output format.
+
+ * @return Length of the converted string.
+ */
+static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps);
+
+#if PRINTF_FLOAT_ENABLE
+/*!
+ * @brief Converts a floating radix number to a string and return its length.
+ *
+ * @param[in] numstr Converted string of the number.
+ * @param[in] nump Pointer to the number.
+ * @param[in] radix The radix to be converted to.
+ * @param[in] precision_width Specify the precision width.
+
+ * @return Length of the converted string.
+ */
+static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width);
+#endif /* PRINTF_FLOAT_ENABLE */
+
+/*!
+ *
+ */
+double modf(double input_dbl, double *intpart_ptr);
+
+/*************Code for process formatted data*******************************/
+
+static uint32_t ScanIgnoreWhiteSpace(const char **s)
+{
+ uint8_t count = 0;
+ uint8_t c;
+
+ c = **s;
+ while ((c == ' ') || (c == '\t') || (c == '\n') || (c == '\r') || (c == '\v') || (c == '\f'))
+ {
+ count++;
+ (*s)++;
+ c = **s;
+ }
+ return count;
+}
+
+static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps)
+{
+#if PRINTF_ADVANCED_ENABLE
+ int64_t a;
+ int64_t b;
+ int64_t c;
+
+ uint64_t ua;
+ uint64_t ub;
+ uint64_t uc;
+#else
+ int32_t a;
+ int32_t b;
+ int32_t c;
+
+ uint32_t ua;
+ uint32_t ub;
+ uint32_t uc;
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+ int32_t nlen;
+ char *nstrp;
+
+ nlen = 0;
+ nstrp = numstr;
+ *nstrp++ = '\0';
+
+ if (neg)
+ {
+#if PRINTF_ADVANCED_ENABLE
+ a = *(int64_t *)nump;
+#else
+ a = *(int32_t *)nump;
+#endif /* PRINTF_ADVANCED_ENABLE */
+ if (a == 0)
+ {
+ *nstrp = '0';
+ ++nlen;
+ return nlen;
+ }
+ while (a != 0)
+ {
+#if PRINTF_ADVANCED_ENABLE
+ b = (int64_t)a / (int64_t)radix;
+ c = (int64_t)a - ((int64_t)b * (int64_t)radix);
+ if (c < 0)
+ {
+ uc = (uint64_t)c;
+ c = (int64_t)(~uc) + 1 + '0';
+ }
+#else
+ b = a / radix;
+ c = a - (b * radix);
+ if (c < 0)
+ {
+ uc = (uint32_t)c;
+ c = (uint32_t)(~uc) + 1 + '0';
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ else
+ {
+ c = c + '0';
+ }
+ a = b;
+ *nstrp++ = (char)c;
+ ++nlen;
+ }
+ }
+ else
+ {
+#if PRINTF_ADVANCED_ENABLE
+ ua = *(uint64_t *)nump;
+#else
+ ua = *(uint32_t *)nump;
+#endif /* PRINTF_ADVANCED_ENABLE */
+ if (ua == 0)
+ {
+ *nstrp = '0';
+ ++nlen;
+ return nlen;
+ }
+ while (ua != 0)
+ {
+#if PRINTF_ADVANCED_ENABLE
+ ub = (uint64_t)ua / (uint64_t)radix;
+ uc = (uint64_t)ua - ((uint64_t)ub * (uint64_t)radix);
+#else
+ ub = ua / (uint32_t)radix;
+ uc = ua - (ub * (uint32_t)radix);
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+ if (uc < 10)
+ {
+ uc = uc + '0';
+ }
+ else
+ {
+ uc = uc - 10 + (use_caps ? 'A' : 'a');
+ }
+ ua = ub;
+ *nstrp++ = (char)uc;
+ ++nlen;
+ }
+ }
+ return nlen;
+}
+
+#if PRINTF_FLOAT_ENABLE
+static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width)
+{
+ int32_t a;
+ int32_t b;
+ int32_t c;
+ int32_t i;
+ uint32_t uc;
+ double fa;
+ double dc;
+ double fb;
+ double r;
+ double fractpart;
+ double intpart;
+
+ int32_t nlen;
+ char *nstrp;
+ nlen = 0;
+ nstrp = numstr;
+ *nstrp++ = '\0';
+ r = *(double *)nump;
+ if (!r)
+ {
+ *nstrp = '0';
+ ++nlen;
+ return nlen;
+ }
+ fractpart = modf((double)r, (double *)&intpart);
+ /* Process fractional part. */
+ for (i = 0; i < precision_width; i++)
+ {
+ fractpart *= radix;
+ }
+ if (r >= 0)
+ {
+ fa = fractpart + (double)0.5;
+ if (fa >= pow(10, precision_width))
+ {
+ intpart++;
+ }
+ }
+ else
+ {
+ fa = fractpart - (double)0.5;
+ if (fa <= -pow(10, precision_width))
+ {
+ intpart--;
+ }
+ }
+ for (i = 0; i < precision_width; i++)
+ {
+ fb = fa / (int32_t)radix;
+ dc = (fa - (int64_t)fb * (int32_t)radix);
+ c = (int32_t)dc;
+ if (c < 0)
+ {
+ uc = (uint32_t)c;
+ c = (int32_t)(~uc) + 1 + '0';
+ }
+ else
+ {
+ c = c + '0';
+ }
+ fa = fb;
+ *nstrp++ = (char)c;
+ ++nlen;
+ }
+ *nstrp++ = (char)'.';
+ ++nlen;
+ a = (int32_t)intpart;
+ if (a == 0)
+ {
+ *nstrp++ = '0';
+ ++nlen;
+ }
+ else
+ {
+ while (a != 0)
+ {
+ b = (int32_t)a / (int32_t)radix;
+ c = (int32_t)a - ((int32_t)b * (int32_t)radix);
+ if (c < 0)
+ {
+ uc = (uint32_t)c;
+ c = (int32_t)(~uc) + 1 + '0';
+ }
+ else
+ {
+ c = c + '0';
+ }
+ a = b;
+ *nstrp++ = (char)c;
+ ++nlen;
+ }
+ }
+ return nlen;
+}
+#endif /* PRINTF_FLOAT_ENABLE */
+
+/*!
+ * brief This function outputs its parameters according to a formatted string.
+ *
+ * note I/O is performed by calling given function pointer using following
+ * (*func_ptr)(c);
+ *
+ * param[in] fmt_ptr Format string for printf.
+ * param[in] args_ptr Arguments to printf.
+ * param[in] buf pointer to the buffer
+ * param cb print callback function pointer
+ *
+ * return Number of characters to be print
+ */
+int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb)
+{
+ /* va_list ap; */
+ char *p;
+ int32_t c;
+
+ char vstr[33];
+ char *vstrp = NULL;
+ int32_t vlen = 0;
+
+ int32_t done;
+ int32_t count = 0;
+
+ uint32_t field_width;
+ uint32_t precision_width;
+ char *sval;
+ int32_t cval;
+ bool use_caps;
+ uint8_t radix = 0;
+
+#if PRINTF_ADVANCED_ENABLE
+ uint32_t flags_used;
+ int32_t schar, dschar;
+ int64_t ival;
+ uint64_t uval = 0;
+ bool valid_precision_width;
+#else
+ int32_t ival;
+ uint32_t uval = 0;
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+#if PRINTF_FLOAT_ENABLE
+ double fval;
+#endif /* PRINTF_FLOAT_ENABLE */
+
+ /* Start parsing apart the format string and display appropriate formats and data. */
+ for (p = (char *)fmt; (c = *p) != 0; p++)
+ {
+ /*
+ * All formats begin with a '%' marker. Special chars like
+ * '\n' or '\t' are normally converted to the appropriate
+ * character by the __compiler__. Thus, no need for this
+ * routine to account for the '\' character.
+ */
+ if (c != '%')
+ {
+ cb(buf, &count, c, 1);
+ /* By using 'continue', the next iteration of the loop is used, skipping the code that follows. */
+ continue;
+ }
+
+ use_caps = true;
+
+#if PRINTF_ADVANCED_ENABLE
+ /* First check for specification modifier flags. */
+ flags_used = 0;
+ done = false;
+ while (!done)
+ {
+ switch (*++p)
+ {
+ case '-':
+ flags_used |= kPRINTF_Minus;
+ break;
+ case '+':
+ flags_used |= kPRINTF_Plus;
+ break;
+ case ' ':
+ flags_used |= kPRINTF_Space;
+ break;
+ case '0':
+ flags_used |= kPRINTF_Zero;
+ break;
+ case '#':
+ flags_used |= kPRINTF_Pound;
+ break;
+ default:
+ /* We've gone one char too far. */
+ --p;
+ done = true;
+ break;
+ }
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+ /* Next check for minimum field width. */
+ field_width = 0;
+ done = false;
+ while (!done)
+ {
+ c = *++p;
+ if ((c >= '0') && (c <= '9'))
+ {
+ field_width = (field_width * 10) + (c - '0');
+ }
+#if PRINTF_ADVANCED_ENABLE
+ else if (c == '*')
+ {
+ field_width = (uint32_t)va_arg(ap, uint32_t);
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ else
+ {
+ /* We've gone one char too far. */
+ --p;
+ done = true;
+ }
+ }
+ /* Next check for the width and precision field separator. */
+ precision_width = 6;
+#if PRINTF_ADVANCED_ENABLE
+ valid_precision_width = false;
+#endif /* PRINTF_ADVANCED_ENABLE */
+ if (*++p == '.')
+ {
+ /* Must get precision field width, if present. */
+ precision_width = 0;
+ done = false;
+ while (!done)
+ {
+ c = *++p;
+ if ((c >= '0') && (c <= '9'))
+ {
+ precision_width = (precision_width * 10) + (c - '0');
+#if PRINTF_ADVANCED_ENABLE
+ valid_precision_width = true;
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+#if PRINTF_ADVANCED_ENABLE
+ else if (c == '*')
+ {
+ precision_width = (uint32_t)va_arg(ap, uint32_t);
+ valid_precision_width = true;
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ else
+ {
+ /* We've gone one char too far. */
+ --p;
+ done = true;
+ }
+ }
+ }
+ else
+ {
+ /* We've gone one char too far. */
+ --p;
+ }
+#if PRINTF_ADVANCED_ENABLE
+ /*
+ * Check for the length modifier.
+ */
+ switch (/* c = */ *++p)
+ {
+ case 'h':
+ if (*++p != 'h')
+ {
+ flags_used |= kPRINTF_LengthShortInt;
+ --p;
+ }
+ else
+ {
+ flags_used |= kPRINTF_LengthChar;
+ }
+ break;
+ case 'l':
+ if (*++p != 'l')
+ {
+ flags_used |= kPRINTF_LengthLongInt;
+ --p;
+ }
+ else
+ {
+ flags_used |= kPRINTF_LengthLongLongInt;
+ }
+ break;
+ default:
+ /* we've gone one char too far */
+ --p;
+ break;
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ /* Now we're ready to examine the format. */
+ c = *++p;
+ {
+ if ((c == 'd') || (c == 'i') || (c == 'f') || (c == 'F') || (c == 'x') || (c == 'X') || (c == 'o') ||
+ (c == 'b') || (c == 'p') || (c == 'u'))
+ {
+ if ((c == 'd') || (c == 'i'))
+ {
+#if PRINTF_ADVANCED_ENABLE
+ if (flags_used & kPRINTF_LengthLongLongInt)
+ {
+ ival = (int64_t)va_arg(ap, int64_t);
+ }
+ else
+#endif /* PRINTF_ADVANCED_ENABLE */
+ {
+ ival = (int32_t)va_arg(ap, int32_t);
+ }
+ vlen = ConvertRadixNumToString(vstr, &ival, true, 10, use_caps);
+ vstrp = &vstr[vlen];
+#if PRINTF_ADVANCED_ENABLE
+ if (ival < 0)
+ {
+ schar = '-';
+ ++vlen;
+ }
+ else
+ {
+ if (flags_used & kPRINTF_Plus)
+ {
+ schar = '+';
+ ++vlen;
+ }
+ else
+ {
+ if (flags_used & kPRINTF_Space)
+ {
+ schar = ' ';
+ ++vlen;
+ }
+ else
+ {
+ schar = 0;
+ }
+ }
+ }
+ dschar = false;
+ /* Do the ZERO pad. */
+ if (flags_used & kPRINTF_Zero)
+ {
+ if (schar)
+ {
+ cb(buf, &count, schar, 1);
+ }
+ dschar = true;
+
+ cb(buf, &count, '0', field_width - vlen);
+ vlen = field_width;
+ }
+ else
+ {
+ if (!(flags_used & kPRINTF_Minus))
+ {
+ cb(buf, &count, ' ', field_width - vlen);
+ if (schar)
+ {
+ cb(buf, &count, schar, 1);
+ }
+ dschar = true;
+ }
+ }
+ /* The string was built in reverse order, now display in correct order. */
+ if ((!dschar) && schar)
+ {
+ cb(buf, &count, schar, 1);
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+
+#if PRINTF_FLOAT_ENABLE
+ if ((c == 'f') || (c == 'F'))
+ {
+ fval = (double)va_arg(ap, double);
+ vlen = ConvertFloatRadixNumToString(vstr, &fval, 10, precision_width);
+ vstrp = &vstr[vlen];
+
+#if PRINTF_ADVANCED_ENABLE
+ if (fval < 0)
+ {
+ schar = '-';
+ ++vlen;
+ }
+ else
+ {
+ if (flags_used & kPRINTF_Plus)
+ {
+ schar = '+';
+ ++vlen;
+ }
+ else
+ {
+ if (flags_used & kPRINTF_Space)
+ {
+ schar = ' ';
+ ++vlen;
+ }
+ else
+ {
+ schar = 0;
+ }
+ }
+ }
+ dschar = false;
+ if (flags_used & kPRINTF_Zero)
+ {
+ if (schar)
+ {
+ cb(buf, &count, schar, 1);
+ }
+ dschar = true;
+ cb(buf, &count, '0', field_width - vlen);
+ vlen = field_width;
+ }
+ else
+ {
+ if (!(flags_used & kPRINTF_Minus))
+ {
+ cb(buf, &count, ' ', field_width - vlen);
+ if (schar)
+ {
+ cb(buf, &count, schar, 1);
+ }
+ dschar = true;
+ }
+ }
+ if ((!dschar) && schar)
+ {
+ cb(buf, &count, schar, 1);
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+#endif /* PRINTF_FLOAT_ENABLE */
+ if ((c == 'X') || (c == 'x'))
+ {
+ if (c == 'x')
+ {
+ use_caps = false;
+ }
+#if PRINTF_ADVANCED_ENABLE
+ if (flags_used & kPRINTF_LengthLongLongInt)
+ {
+ uval = (uint64_t)va_arg(ap, uint64_t);
+ }
+ else
+#endif /* PRINTF_ADVANCED_ENABLE */
+ {
+ uval = (uint32_t)va_arg(ap, uint32_t);
+ }
+ vlen = ConvertRadixNumToString(vstr, &uval, false, 16, use_caps);
+ vstrp = &vstr[vlen];
+
+#if PRINTF_ADVANCED_ENABLE
+ dschar = false;
+ if (flags_used & kPRINTF_Zero)
+ {
+ if (flags_used & kPRINTF_Pound)
+ {
+ cb(buf, &count, '0', 1);
+ cb(buf, &count, (use_caps ? 'X' : 'x'), 1);
+ dschar = true;
+ }
+ cb(buf, &count, '0', field_width - vlen);
+ vlen = field_width;
+ }
+ else
+ {
+ if (!(flags_used & kPRINTF_Minus))
+ {
+ if (flags_used & kPRINTF_Pound)
+ {
+ vlen += 2;
+ }
+ cb(buf, &count, ' ', field_width - vlen);
+ if (flags_used & kPRINTF_Pound)
+ {
+ cb(buf, &count, '0', 1);
+ cb(buf, &count, (use_caps ? 'X' : 'x'), 1);
+ dschar = true;
+ }
+ }
+ }
+
+ if ((flags_used & kPRINTF_Pound) && (!dschar))
+ {
+ cb(buf, &count, '0', 1);
+ cb(buf, &count, (use_caps ? 'X' : 'x'), 1);
+ vlen += 2;
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+ if ((c == 'o') || (c == 'b') || (c == 'p') || (c == 'u'))
+ {
+#if PRINTF_ADVANCED_ENABLE
+ if (flags_used & kPRINTF_LengthLongLongInt)
+ {
+ uval = (uint64_t)va_arg(ap, uint64_t);
+ }
+ else
+#endif /* PRINTF_ADVANCED_ENABLE */
+ {
+ uval = (uint32_t)va_arg(ap, uint32_t);
+ }
+
+ if (c == 'o')
+ {
+ radix = 8;
+ }
+ else if (c == 'b')
+ {
+ radix = 2;
+ }
+ else if (c == 'p')
+ {
+ radix = 16;
+ }
+ else
+ {
+ radix = 10;
+ }
+
+ vlen = ConvertRadixNumToString(vstr, &uval, false, radix, use_caps);
+ vstrp = &vstr[vlen];
+#if PRINTF_ADVANCED_ENABLE
+ if (flags_used & kPRINTF_Zero)
+ {
+ cb(buf, &count, '0', field_width - vlen);
+ vlen = field_width;
+ }
+ else
+ {
+ if (!(flags_used & kPRINTF_Minus))
+ {
+ cb(buf, &count, ' ', field_width - vlen);
+ }
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+#if !PRINTF_ADVANCED_ENABLE
+ cb(buf, &count, ' ', field_width - vlen);
+#endif /* !PRINTF_ADVANCED_ENABLE */
+ if (vstrp != NULL)
+ {
+ while (*vstrp)
+ {
+ cb(buf, &count, *vstrp--, 1);
+ }
+ }
+#if PRINTF_ADVANCED_ENABLE
+ if (flags_used & kPRINTF_Minus)
+ {
+ cb(buf, &count, ' ', field_width - vlen);
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+ else if (c == 'c')
+ {
+ cval = (char)va_arg(ap, uint32_t);
+ cb(buf, &count, cval, 1);
+ }
+ else if (c == 's')
+ {
+ sval = (char *)va_arg(ap, char *);
+ if (sval)
+ {
+#if PRINTF_ADVANCED_ENABLE
+ if (valid_precision_width)
+ {
+ vlen = precision_width;
+ }
+ else
+ {
+ vlen = strlen(sval);
+ }
+#else
+ vlen = strlen(sval);
+#endif /* PRINTF_ADVANCED_ENABLE */
+#if PRINTF_ADVANCED_ENABLE
+ if (!(flags_used & kPRINTF_Minus))
+#endif /* PRINTF_ADVANCED_ENABLE */
+ {
+ cb(buf, &count, ' ', field_width - vlen);
+ }
+
+#if PRINTF_ADVANCED_ENABLE
+ if (valid_precision_width)
+ {
+ while ((*sval) && (vlen > 0))
+ {
+ cb(buf, &count, *sval++, 1);
+ vlen--;
+ }
+ /* In case that vlen sval is shorter than vlen */
+ vlen = precision_width - vlen;
+ }
+ else
+ {
+#endif /* PRINTF_ADVANCED_ENABLE */
+ while (*sval)
+ {
+ cb(buf, &count, *sval++, 1);
+ }
+#if PRINTF_ADVANCED_ENABLE
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+#if PRINTF_ADVANCED_ENABLE
+ if (flags_used & kPRINTF_Minus)
+ {
+ cb(buf, &count, ' ', field_width - vlen);
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+ }
+ else
+ {
+ cb(buf, &count, c, 1);
+ }
+ }
+ }
+
+ return count;
+}
+
+/*!
+ * brief Converts an input line of ASCII characters based upon a provided
+ * string format.
+ *
+ * param[in] line_ptr The input line of ASCII data.
+ * param[in] format Format first points to the format string.
+ * param[in] args_ptr The list of parameters.
+ *
+ * return Number of input items converted and assigned.
+ * retval IO_EOF When line_ptr is empty string "".
+ */
+int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr)
+{
+ uint8_t base;
+ int8_t neg;
+ /* Identifier for the format string. */
+ char *c = format;
+ char temp;
+ char *buf;
+ /* Flag telling the conversion specification. */
+ uint32_t flag = 0;
+ /* Filed width for the matching input streams. */
+ uint32_t field_width;
+ /* How many arguments are assigned except the suppress. */
+ uint32_t nassigned = 0;
+ /* How many characters are read from the input streams. */
+ uint32_t n_decode = 0;
+
+ int32_t val;
+
+ const char *s;
+ /* Identifier for the input string. */
+ const char *p = line_ptr;
+
+#if SCANF_FLOAT_ENABLE
+ double fnum = 0.0;
+#endif /* SCANF_FLOAT_ENABLE */
+ /* Return EOF error before any conversion. */
+ if (*p == '\0')
+ {
+ return -1;
+ }
+
+ /* Decode directives. */
+ while ((*c) && (*p))
+ {
+ /* Ignore all white-spaces in the format strings. */
+ if (ScanIgnoreWhiteSpace((const char **)&c))
+ {
+ n_decode += ScanIgnoreWhiteSpace(&p);
+ }
+ else if ((*c != '%') || ((*c == '%') && (*(c + 1) == '%')))
+ {
+ /* Ordinary characters. */
+ c++;
+ if (*p == *c)
+ {
+ n_decode++;
+ p++;
+ c++;
+ }
+ else
+ {
+ /* Match failure. Misalignment with C99, the unmatched characters need to be pushed back to stream.
+ * However, it is deserted now. */
+ break;
+ }
+ }
+ else
+ {
+ /* convernsion specification */
+ c++;
+ /* Reset. */
+ flag = 0;
+ field_width = 0;
+ base = 0;
+
+ /* Loop to get full conversion specification. */
+ while ((*c) && (!(flag & kSCANF_DestMask)))
+ {
+ switch (*c)
+ {
+#if SCANF_ADVANCED_ENABLE
+ case '*':
+ if (flag & kSCANF_Suppress)
+ {
+ /* Match failure. */
+ return nassigned;
+ }
+ flag |= kSCANF_Suppress;
+ c++;
+ break;
+ case 'h':
+ if (flag & kSCANF_LengthMask)
+ {
+ /* Match failure. */
+ return nassigned;
+ }
+
+ if (c[1] == 'h')
+ {
+ flag |= kSCANF_LengthChar;
+ c++;
+ }
+ else
+ {
+ flag |= kSCANF_LengthShortInt;
+ }
+ c++;
+ break;
+ case 'l':
+ if (flag & kSCANF_LengthMask)
+ {
+ /* Match failure. */
+ return nassigned;
+ }
+
+ if (c[1] == 'l')
+ {
+ flag |= kSCANF_LengthLongLongInt;
+ c++;
+ }
+ else
+ {
+ flag |= kSCANF_LengthLongInt;
+ }
+ c++;
+ break;
+#endif /* SCANF_ADVANCED_ENABLE */
+#if SCANF_FLOAT_ENABLE
+ case 'L':
+ if (flag & kSCANF_LengthMask)
+ {
+ /* Match failure. */
+ return nassigned;
+ }
+ flag |= kSCANF_LengthLongLongDouble;
+ c++;
+ break;
+#endif /* SCANF_FLOAT_ENABLE */
+ case '0':
+ case '1':
+ case '2':
+ case '3':
+ case '4':
+ case '5':
+ case '6':
+ case '7':
+ case '8':
+ case '9':
+ if (field_width)
+ {
+ /* Match failure. */
+ return nassigned;
+ }
+ do
+ {
+ field_width = field_width * 10 + *c - '0';
+ c++;
+ } while ((*c >= '0') && (*c <= '9'));
+ break;
+ case 'd':
+ base = 10;
+ flag |= kSCANF_TypeSinged;
+ flag |= kSCANF_DestInt;
+ c++;
+ break;
+ case 'u':
+ base = 10;
+ flag |= kSCANF_DestInt;
+ c++;
+ break;
+ case 'o':
+ base = 8;
+ flag |= kSCANF_DestInt;
+ c++;
+ break;
+ case 'x':
+ case 'X':
+ base = 16;
+ flag |= kSCANF_DestInt;
+ c++;
+ break;
+ case 'i':
+ base = 0;
+ flag |= kSCANF_DestInt;
+ c++;
+ break;
+#if SCANF_FLOAT_ENABLE
+ case 'a':
+ case 'A':
+ case 'e':
+ case 'E':
+ case 'f':
+ case 'F':
+ case 'g':
+ case 'G':
+ flag |= kSCANF_DestFloat;
+ c++;
+ break;
+#endif /* SCANF_FLOAT_ENABLE */
+ case 'c':
+ flag |= kSCANF_DestChar;
+ if (!field_width)
+ {
+ field_width = 1;
+ }
+ c++;
+ break;
+ case 's':
+ flag |= kSCANF_DestString;
+ c++;
+ break;
+ default:
+ return nassigned;
+ }
+ }
+
+ if (!(flag & kSCANF_DestMask))
+ {
+ /* Format strings are exhausted. */
+ return nassigned;
+ }
+
+ if (!field_width)
+ {
+ /* Large than length of a line. */
+ field_width = 99;
+ }
+
+ /* Matching strings in input streams and assign to argument. */
+ switch (flag & kSCANF_DestMask)
+ {
+ case kSCANF_DestChar:
+ s = (const char *)p;
+ buf = va_arg(args_ptr, char *);
+ while ((field_width--) && (*p))
+ {
+ if (!(flag & kSCANF_Suppress))
+ {
+ *buf++ = *p++;
+ }
+ else
+ {
+ p++;
+ }
+ n_decode++;
+ }
+
+ if ((!(flag & kSCANF_Suppress)) && (s != p))
+ {
+ nassigned++;
+ }
+ break;
+ case kSCANF_DestString:
+ n_decode += ScanIgnoreWhiteSpace(&p);
+ s = p;
+ buf = va_arg(args_ptr, char *);
+ while ((field_width--) && (*p != '\0') && (*p != ' ') && (*p != '\t') && (*p != '\n') &&
+ (*p != '\r') && (*p != '\v') && (*p != '\f'))
+ {
+ if (flag & kSCANF_Suppress)
+ {
+ p++;
+ }
+ else
+ {
+ *buf++ = *p++;
+ }
+ n_decode++;
+ }
+
+ if ((!(flag & kSCANF_Suppress)) && (s != p))
+ {
+ /* Add NULL to end of string. */
+ *buf = '\0';
+ nassigned++;
+ }
+ break;
+ case kSCANF_DestInt:
+ n_decode += ScanIgnoreWhiteSpace(&p);
+ s = p;
+ val = 0;
+ if ((base == 0) || (base == 16))
+ {
+ if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X')))
+ {
+ base = 16;
+ if (field_width >= 1)
+ {
+ p += 2;
+ n_decode += 2;
+ field_width -= 2;
+ }
+ }
+ }
+
+ if (base == 0)
+ {
+ if (s[0] == '0')
+ {
+ base = 8;
+ }
+ else
+ {
+ base = 10;
+ }
+ }
+
+ neg = 1;
+ switch (*p)
+ {
+ case '-':
+ neg = -1;
+ n_decode++;
+ p++;
+ field_width--;
+ break;
+ case '+':
+ neg = 1;
+ n_decode++;
+ p++;
+ field_width--;
+ break;
+ default:
+ break;
+ }
+
+ while ((*p) && (field_width--))
+ {
+ if ((*p <= '9') && (*p >= '0'))
+ {
+ temp = *p - '0';
+ }
+ else if ((*p <= 'f') && (*p >= 'a'))
+ {
+ temp = *p - 'a' + 10;
+ }
+ else if ((*p <= 'F') && (*p >= 'A'))
+ {
+ temp = *p - 'A' + 10;
+ }
+ else
+ {
+ temp = base;
+ }
+
+ if (temp >= base)
+ {
+ break;
+ }
+ else
+ {
+ val = base * val + temp;
+ }
+ p++;
+ n_decode++;
+ }
+ val *= neg;
+ if (!(flag & kSCANF_Suppress))
+ {
+#if SCANF_ADVANCED_ENABLE
+ switch (flag & kSCANF_LengthMask)
+ {
+ case kSCANF_LengthChar:
+ if (flag & kSCANF_TypeSinged)
+ {
+ *va_arg(args_ptr, signed char *) = (signed char)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned char *) = (unsigned char)val;
+ }
+ break;
+ case kSCANF_LengthShortInt:
+ if (flag & kSCANF_TypeSinged)
+ {
+ *va_arg(args_ptr, signed short *) = (signed short)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned short *) = (unsigned short)val;
+ }
+ break;
+ case kSCANF_LengthLongInt:
+ if (flag & kSCANF_TypeSinged)
+ {
+ *va_arg(args_ptr, signed long int *) = (signed long int)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned long int *) = (unsigned long int)val;
+ }
+ break;
+ case kSCANF_LengthLongLongInt:
+ if (flag & kSCANF_TypeSinged)
+ {
+ *va_arg(args_ptr, signed long long int *) = (signed long long int)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned long long int *) = (unsigned long long int)val;
+ }
+ break;
+ default:
+ /* The default type is the type int. */
+ if (flag & kSCANF_TypeSinged)
+ {
+ *va_arg(args_ptr, signed int *) = (signed int)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned int *) = (unsigned int)val;
+ }
+ break;
+ }
+#else
+ /* The default type is the type int. */
+ if (flag & kSCANF_TypeSinged)
+ {
+ *va_arg(args_ptr, signed int *) = (signed int)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned int *) = (unsigned int)val;
+ }
+#endif /* SCANF_ADVANCED_ENABLE */
+ nassigned++;
+ }
+ break;
+#if SCANF_FLOAT_ENABLE
+ case kSCANF_DestFloat:
+ n_decode += ScanIgnoreWhiteSpace(&p);
+ fnum = strtod(p, (char **)&s);
+
+ if ((fnum >= HUGE_VAL) || (fnum <= -HUGE_VAL))
+ {
+ break;
+ }
+
+ n_decode += (int)(s) - (int)(p);
+ p = s;
+ if (!(flag & kSCANF_Suppress))
+ {
+ if (flag & kSCANF_LengthLongLongDouble)
+ {
+ *va_arg(args_ptr, double *) = fnum;
+ }
+ else
+ {
+ *va_arg(args_ptr, float *) = (float)fnum;
+ }
+ nassigned++;
+ }
+ break;
+#endif /* SCANF_FLOAT_ENABLE */
+ default:
+ return nassigned;
+ }
+ }
+ }
+ return nassigned;
+}
diff --git a/third_party/nxp/JN5189DK6/devices/JN5189/utilities/str/fsl_str.h b/third_party/nxp/JN5189DK6/devices/JN5189/utilities/str/fsl_str.h
new file mode 100755
index 0000000..bf7adcc
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/devices/JN5189/utilities/str/fsl_str.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _FSL_STR_H
+#define _FSL_STR_H
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup debugconsole
+ * @{
+ */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @brief A function pointer which is used when format printf log.
+ */
+typedef void (*printfCb)(char *buf, int32_t *indicator, char val, int len);
+
+/*!
+ * @brief This function outputs its parameters according to a formatted string.
+ *
+ * @note I/O is performed by calling given function pointer using following
+ * (*func_ptr)(c);
+ *
+ * @param[in] fmt Format string for printf.
+ * @param[in] ap Arguments to printf.
+ * @param[in] buf pointer to the buffer
+ * @param cb print callbck function pointer
+ *
+ * @return Number of characters to be print
+ */
+int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb);
+
+/*!
+ * @brief Converts an input line of ASCII characters based upon a provided
+ * string format.
+ *
+ * @param[in] line_ptr The input line of ASCII data.
+ * @param[in] format Format first points to the format string.
+ * @param[in] args_ptr The list of parameters.
+ *
+ * @return Number of input items converted and assigned.
+ * @retval IO_EOF When line_ptr is empty string "".
+ */
+int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_STR_H */
diff --git a/third_party/nxp/JN5189/crypto/aes_alt.c b/third_party/nxp/JN5189DK6/middleware/mbedtls/port/ksdk/aes_alt.c
similarity index 98%
rename from third_party/nxp/JN5189/crypto/aes_alt.c
rename to third_party/nxp/JN5189DK6/middleware/mbedtls/port/ksdk/aes_alt.c
index aa5173b..31acea7 100755
--- a/third_party/nxp/JN5189/crypto/aes_alt.c
+++ b/third_party/nxp/JN5189DK6/middleware/mbedtls/port/ksdk/aes_alt.c
@@ -4,6 +4,7 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+
#if !defined(MBEDTLS_CONFIG_FILE)
#include "mbedtls/config.h"
#else
@@ -24,7 +25,7 @@
#endif
#if defined(MBEDTLS_AES_ALT)
-
+/* clang-format off */
/*
* 32-bit integer manipulation macros (little endian)
*/
@@ -1360,9 +1361,11 @@
}
#endif /* !MBEDTLS_AES_CRYPT_CTR_ALT */
#endif /* MBEDTLS_CIPHER_MODE_CTR */
+/* clang-format on */
/* HASHCRYPT AES */
#if defined(MBEDTLS_FREESCALE_HASHCRYPT_AES)
+
/*
* AES key schedule (encryption)
*/
@@ -1384,7 +1387,7 @@
default:
return (MBEDTLS_ERR_AES_INVALID_KEY_LENGTH);
}
- /* secret bus is marked as key address == hashcrypt base */
+ /* secret bus is marked as key address == HASHCRYPT base */
if ((uint32_t)key == (uint32_t)HASHCRYPT)
{
ctx->keyType = kHASHCRYPT_SecretKey;
@@ -1422,7 +1425,7 @@
default:
return (MBEDTLS_ERR_AES_INVALID_KEY_LENGTH);
}
- /* secret bus is marked as key address == hashcrypt base */
+ /* secret bus is marked as key address == HASHCRYPT base */
if ((uint32_t)key == (uint32_t)HASHCRYPT)
{
ctx->keyType = kHASHCRYPT_SecretKey;
@@ -1507,15 +1510,15 @@
* AES-CTR buffer encryption/decryption
*/
int mbedtls_aes_crypt_ctr(mbedtls_aes_context *ctx,
- size_t length,
- size_t *nc_off,
- unsigned char nonce_counter[16],
- unsigned char stream_block[16],
- const unsigned char *input,
- unsigned char *output)
+ size_t length,
+ size_t *nc_off,
+ unsigned char nonce_counter[16],
+ unsigned char stream_block[16],
+ const unsigned char *input,
+ unsigned char *output)
{
- if (kStatus_Success != HASHCRYPT_AES_CryptCtr(HASHCRYPT, ctx, input, output, length, nonce_counter,
- stream_block, nc_off))
+ if (kStatus_Success !=
+ HASHCRYPT_AES_CryptCtr(HASHCRYPT, ctx, input, output, length, nonce_counter, stream_block, nc_off))
{
return (MBEDTLS_ERR_AES_HW_ACCEL_FAILED);
}
diff --git a/third_party/nxp/JN5189/crypto/aes_alt.h b/third_party/nxp/JN5189DK6/middleware/mbedtls/port/ksdk/aes_alt.h
similarity index 100%
rename from third_party/nxp/JN5189/crypto/aes_alt.h
rename to third_party/nxp/JN5189DK6/middleware/mbedtls/port/ksdk/aes_alt.h
diff --git a/third_party/nxp/JN5189/crypto/ksdk_mbedtls.c b/third_party/nxp/JN5189DK6/middleware/mbedtls/port/ksdk/ksdk_mbedtls.c
similarity index 99%
rename from third_party/nxp/JN5189/crypto/ksdk_mbedtls.c
rename to third_party/nxp/JN5189DK6/middleware/mbedtls/port/ksdk/ksdk_mbedtls.c
index fbeaa31..ad9f0a2 100755
--- a/third_party/nxp/JN5189/crypto/ksdk_mbedtls.c
+++ b/third_party/nxp/JN5189DK6/middleware/mbedtls/port/ksdk/ksdk_mbedtls.c
@@ -31,7 +31,11 @@
#include "fsl_hashcrypt.h"
#endif
#if defined(FSL_FEATURE_SOC_TRNG_COUNT) && (FSL_FEATURE_SOC_TRNG_COUNT > 0)
-#include "fsl_rng.h"
+#if defined CPU_JN518X
+ #include "fsl_rng.h"
+#else
+ #include "fsl_trng.h"
+#endif
#elif defined(FSL_FEATURE_SOC_RNG_COUNT) && (FSL_FEATURE_SOC_RNG_COUNT > 0)
#include "fsl_rnga.h"
#elif defined(FSL_FEATURE_SOC_LPC_RNG1_COUNT) && (FSL_FEATURE_SOC_LPC_RNG1_COUNT > 0)
@@ -159,8 +163,14 @@
#endif
{ /* Init RNG module.*/
#if defined(FSL_FEATURE_SOC_TRNG_COUNT) && (FSL_FEATURE_SOC_TRNG_COUNT > 0)
-#if defined(RNG)
-#define TRNG0 RNG
+#if defined CPU_JN518X
+ #if defined(RNG)
+ #define TRNG0 RNG
+ #endif
+#else
+ #if defined(TRNG)
+ #define TRNG0 TRNG
+ #endif
#endif
trng_config_t trngConfig;
@@ -590,7 +600,7 @@
int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, const unsigned char *key, unsigned int keybits)
{
uint32_t *RK;
-
+
#ifdef MBEDTLS_AES_ALT_NO_192
if (keybits == 192u)
{
@@ -607,7 +617,7 @@
#if defined(MBEDTLS_FREESCALE_LTC_AES) || defined(MBEDTLS_FREESCALE_LPC_AES) || defined(MBEDTLS_FREESCALE_CAU3_AES) || \
defined(MBEDTLS_FREESCALE_CAAM_AES) || defined(MBEDTLS_FREESCALE_DCP_AES)
- const unsigned char *key_tmp = key;
+ const unsigned char *key_tmp = key;
ctx->rk = RK = ctx->buf;
memcpy(RK, key_tmp, keybits / 8);
@@ -659,7 +669,7 @@
int mbedtls_aes_setkey_dec(mbedtls_aes_context *ctx, const unsigned char *key, unsigned int keybits)
{
uint32_t *RK;
-
+
#ifdef MBEDTLS_AES_ALT_NO_192
if (keybits == 192u)
{
@@ -4377,7 +4387,11 @@
#if defined(MBEDTLS_ENTROPY_HARDWARE_ALT)
#if defined(FSL_FEATURE_SOC_TRNG_COUNT) && (FSL_FEATURE_SOC_TRNG_COUNT > 0)
-#include "fsl_rng.h"
+#if defined CPU_JN518X
+ #include "fsl_rng.h"
+#else
+ #include "fsl_trng.h"
+#endif
#elif defined(FSL_FEATURE_SOC_RNG_COUNT) && (FSL_FEATURE_SOC_RNG_COUNT > 0)
#include "fsl_rnga.h"
#elif defined(FSL_FEATURE_SOC_LPC_RNG_COUNT) && (FSL_FEATURE_SOC_LPC_RNG_COUNT > 0)
@@ -4391,8 +4405,14 @@
status_t result = kStatus_Success;
#if defined(FSL_FEATURE_SOC_TRNG_COUNT) && (FSL_FEATURE_SOC_TRNG_COUNT > 0)
-#ifndef RNG
-#define TRNG0 RNG
+#if defined CPU_JN518X
+ #ifndef TRNG0
+ #define TRNG0 RNG
+ #endif
+#else
+ #ifndef TRNG0
+ #define TRNG0 TRNG
+ #endif
#endif
result = TRNG_GetRandomData(TRNG0, output, len);
#elif defined(FSL_FEATURE_SOC_RNG_COUNT) && (FSL_FEATURE_SOC_RNG_COUNT > 0)
diff --git a/third_party/nxp/JN5189/crypto/ksdk_mbedtls.h b/third_party/nxp/JN5189DK6/middleware/mbedtls/port/ksdk/ksdk_mbedtls.h
similarity index 84%
rename from third_party/nxp/JN5189/crypto/ksdk_mbedtls.h
rename to third_party/nxp/JN5189DK6/middleware/mbedtls/port/ksdk/ksdk_mbedtls.h
index 0d9d965..cb545c5 100755
--- a/third_party/nxp/JN5189/crypto/ksdk_mbedtls.h
+++ b/third_party/nxp/JN5189DK6/middleware/mbedtls/port/ksdk/ksdk_mbedtls.h
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2017, NXP Semiconductors, Inc.
+ * Copyright 2017 NXP
* All rights reserved.
*
- *
+ *
* SPDX-License-Identifier: BSD-3-Clause
*/
-
+
#ifndef KSDK_MBEDTLS_H
#define KSDK_MBEDTLS_H
diff --git a/third_party/nxp/JN5189/crypto/sha1_alt.h b/third_party/nxp/JN5189DK6/middleware/mbedtls/port/ksdk/sha1_alt.h
similarity index 100%
rename from third_party/nxp/JN5189/crypto/sha1_alt.h
rename to third_party/nxp/JN5189DK6/middleware/mbedtls/port/ksdk/sha1_alt.h
diff --git a/third_party/nxp/JN5189/crypto/sha256_alt.h b/third_party/nxp/JN5189DK6/middleware/mbedtls/port/ksdk/sha256_alt.h
similarity index 97%
rename from third_party/nxp/JN5189/crypto/sha256_alt.h
rename to third_party/nxp/JN5189DK6/middleware/mbedtls/port/ksdk/sha256_alt.h
index eeb850c..2fe0148 100755
--- a/third_party/nxp/JN5189/crypto/sha256_alt.h
+++ b/third_party/nxp/JN5189DK6/middleware/mbedtls/port/ksdk/sha256_alt.h
@@ -57,7 +57,7 @@
/**
* \brief SHA-256 context structure
*/
-#define mbedtls_sha256_context cau3_hash_ctx_t
+#define mbedtls_sha256_context cau3_hash_ctx_t
#elif defined(MBEDTLS_FREESCALE_DCP_SHA256)
diff --git a/third_party/nxp/JN5189DK6/middleware/wireless/framework/Common/MicroInt_arm_sdk2.c b/third_party/nxp/JN5189DK6/middleware/wireless/framework/Common/MicroInt_arm_sdk2.c
new file mode 100755
index 0000000..c6d0ab5
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/middleware/wireless/framework/Common/MicroInt_arm_sdk2.c
@@ -0,0 +1,233 @@
+/*****************************************************************************
+ *
+ * MODULE: Microspecific
+ *
+ * COMPONENT: Microspecific
+ *
+ * AUTHOR: Wayne Ellis
+ *
+ * DESCRIPTION: JN517x Microspecific Interrupt Controller Code
+ *
+ * $HeadURL: $
+ *
+ * $Revision: $
+ *
+ * $LastChangedBy: we1 $
+ *
+ * $LastChangedDate: $
+ *
+ * $Id: $
+ *
+ *****************************************************************************
+ *
+ * This software is owned by Jennic and/or its supplier and is protected
+ * under applicable copyright laws. All rights are reserved. We grant You,
+ * and any third parties, a license to use this software solely and
+ * exclusively on Jennic products. You, and any third parties must reproduce
+ * the copyright and warranty notice and any other legend of ownership on each
+ * copy or partial copy of the software.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". JENNIC MAKES NO WARRANTIES, WHETHER
+ * EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE,
+ * ACCURACY OR LACK OF NEGLIGENCE. JENNIC SHALL NOT, IN ANY CIRCUMSTANCES,
+ * BE LIABLE FOR ANY DAMAGES, INCLUDING, BUT NOT LIMITED TO, SPECIAL,
+ * INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON WHATSOEVER.
+ *
+ * Copyright Jennic Ltd. 2014 All rights reserved
+ *
+ ****************************************************************************/
+
+/****************************************************************************/
+/*** Include files ***/
+/****************************************************************************/
+#include "jendefs.h"
+
+#include "MicroSpecific.h"
+//#include "jn518x.h"
+//#include "PeripheralRegs.h"
+//#include <ARMcortexM3Registers_JN51xx.h>
+
+/****************************************************************************/
+/*** Macro Definitions ***/
+/****************************************************************************/
+// PreEmpt Priority field is [7:5]
+#define PREEMPT_PRIORITY_FIELD (4)
+
+/****************************************************************************/
+/*** Type Definitions ***/
+/****************************************************************************/
+
+/****************************************************************************/
+/*** Local Function Prototypes ***/
+/****************************************************************************/
+
+/****************************************************************************/
+/*** Exported Variables ***/
+/****************************************************************************/
+
+/****************************************************************************/
+/*** Local Variables ***/
+/****************************************************************************/
+
+/****************************************************************************/
+/*** Exported Functions ***/
+/****************************************************************************/
+#if 0
+/****************************************************************************
+ * NAME: vAHI_InitialiseInterruptController
+ *
+ * DESCRIPTION:
+ * Initialise ARM NVIC.
+ *
+ * RETURNS:
+ * Nothing.
+ *
+ * NOTES:
+ *
+ ****************************************************************************/
+
+PUBLIC void vAHI_InitialiseInterruptController(
+ uint32 *pu32InterruptVectorTable)
+{
+ uint32 u32RegisterValue=0;
+
+ // set application interrupt and reset control register
+
+ // write vector key
+ U32_SET_BITS(&u32RegisterValue, REG_APP_INT_RESET_CTRL_VECTKEY);
+ // set priority group
+ U32_SET_BITS(&u32RegisterValue, PREEMPT_PRIORITY_FIELD << REG_APP_INT_RESET_CTRL_PRIGROUP_BIT);
+
+ vREG_Write(REG_APP_INT_RESET_CTRL, u32RegisterValue);
+
+ // set vector table location
+ u32RegisterValue=0;
+
+ // table in RAM - this bit isn't required in the JN5172 at all
+ // U32_SET_BITS(&u32RegisterValue, 1 << REG_INT_VECTOR_TABLE_OFFSET_TBLBASE_BIT);
+
+ // table address
+ U32_SET_BITS(&u32RegisterValue, (uint32)pu32InterruptVectorTable);
+ vREG_Write(REG_INT_VECTOR_TABLE_OFFSET, u32RegisterValue);
+
+ // enable exception features - DIV0 and align errors
+ u32RegisterValue=0;
+
+ U32_SET_BITS(
+ &u32RegisterValue,
+ /* REG_CONFIGURATION_CONTROL_UNALIGN_TRP_MASK | */REG_CONFIGURATION_CONTROL_DIV_0_TRP_MASK);
+
+ vREG_Write(REG_CONFIGURATION_CONTROL, u32RegisterValue);
+
+ // set the exception priorities here - benign but listed so we know where they are
+ // MemManage
+ vREG_Write8(REG_SYSTEM_HANDLER_PRIORITY_4, 0);
+ // BusFault
+ vREG_Write8(REG_SYSTEM_HANDLER_PRIORITY_5, 0);
+ // UsageFault
+ vREG_Write8(REG_SYSTEM_HANDLER_PRIORITY_6, 0);
+ // SVC
+ vREG_Write8(REG_SYSTEM_HANDLER_PRIORITY_11, 0);
+ // debug monitor
+ vREG_Write8(REG_SYSTEM_HANDLER_PRIORITY_12, 0);
+ // pend SV
+ vREG_Write8(REG_SYSTEM_HANDLER_PRIORITY_14, 0);
+ // SYSTICK
+ vREG_Write8(REG_SYSTEM_HANDLER_PRIORITY_15, MICRO_INTERRUPT_WRITE_PRIORITY_VALUE(MICRO_JENNIC_TO_ARM_PRIORITY_MAP(8)));
+
+ u32RegisterValue=0;
+ U32_SET_BITS(
+ &u32RegisterValue,
+ REG_SYSTEM_HANDLER_CNTRL_STATE_USGFAULTEN_MASK | REG_SYSTEM_HANDLER_CNTRL_STATE_BUSFAULTEN_MASK | REG_SYSTEM_HANDLER_CNTRL_STATE_MEMFAULTEN_MASK);
+ vREG_Write(REG_SYSTEM_HANDLER_CNTRL_STATE, u32RegisterValue);
+
+}
+#endif
+
+#if 0
+/****************************************************************************
+ * NAME: vMicroIntSetGlobalEnable
+ *
+ * DESCRIPTION:
+ * Enable specified interrupts.
+ *
+ * RETURNS:
+ * Nothing.
+ *
+ * NOTES:
+ *
+ ****************************************************************************/
+
+PUBLIC void vMicroIntSetGlobalEnable(
+ uint32 u32EnableMask)
+{
+ // all API's work with the old BA stack numbers, appropriate translations
+ // occur within the call
+ vAHI_InterruptSetPriority(u32EnableMask, 12);
+}
+#endif
+
+/****************************************************************************
+ * NAME: vMicroIntEnableOnly
+ *
+ * DESCRIPTION:
+ * Enable specified interrupt.
+ *
+ * RETURNS:
+ * Nothing.
+ *
+ * NOTES:
+ *
+ ****************************************************************************/
+
+PUBLIC void vMicroIntEnableOnly(
+ tsMicroIntStorage *psIntStorage,
+ uint32 u32EnableMask)
+{
+ uint32 u32Store;
+
+ /* Not used in this implementation */
+ VARIABLE_INTENTIONALLY_NOT_REFERENCED(u32EnableMask)
+
+ /* Disable interrupts for duration of this function */
+#if defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)
+ /* unroll MICRO_DISABLE_AND_SAVE_INTERRUPTS macro content becasue IAR < 8.40 fails to see u32Store is set */
+ u32Store = __get_PRIMASK();
+ __disable_irq();
+#else
+ MICRO_DISABLE_AND_SAVE_INTERRUPTS(u32Store);
+#endif
+ /* Store old priority level */
+ psIntStorage->u8Level = MICRO_GET_ACTIVE_INT_LEVEL();
+
+ /* Update priority level, but only if it is a more restrictive value */
+ MICRO_SET_ACTIVE_INT_LEVEL_MAX(MICRO_INTERRUPT_WRITE_PRIORITY_VALUE(3));
+
+ /* Restore interrupts */
+ MICRO_RESTORE_INTERRUPTS(u32Store);
+}
+
+/****************************************************************************
+ * NAME: vMicroIntRestoreState
+ *
+ * DESCRIPTION:
+ * Restore Previous Interrupt State.
+ *
+ * RETURNS:
+ * Nothing.
+ *
+ * NOTES:
+ *
+ ****************************************************************************/
+
+PUBLIC void vMicroIntRestoreState(
+ tsMicroIntStorage *psIntStorage)
+{
+ // write value direct into register ARM to ARM, no translations required
+ MICRO_SET_ACTIVE_INT_LEVEL(psIntStorage->u8Level);
+}
+
+/****************************************************************************/
+/*** End of file ***/
+/****************************************************************************/
diff --git a/third_party/nxp/JN5189DK6/middleware/wireless/framework/Common/MicroSpecific.h b/third_party/nxp/JN5189DK6/middleware/wireless/framework/Common/MicroSpecific.h
new file mode 100755
index 0000000..ff8a0fb
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/middleware/wireless/framework/Common/MicroSpecific.h
@@ -0,0 +1,52 @@
+/*****************************************************************************
+ *
+ * MODULE: Definitions specific to a particular processor
+ *
+ * DESCRIPTION:
+ * Definitions for a specific processor, i.e. functions that can only be
+ * resolved by op codes
+ *
+ ****************************************************************************
+ *
+ * This software is owned by NXP B.V. and/or its supplier and is protected
+ * under applicable copyright laws. All rights are reserved. We grant You,
+ * and any third parties, a license to use this software solely and
+ * exclusively on NXP products [NXP Microcontrollers such as JN5148, JN5142, JN5139].
+ * You, and any third parties must reproduce the copyright and warranty notice
+ * and any other legend of ownership on each copy or partial copy of the
+ * software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Copyright NXP B.V. 2012. All rights reserved
+ *
+ ***************************************************************************/
+
+/****************************************************************************/
+/*** Include files ***/
+/****************************************************************************/
+
+#define EXPAND1(x) x
+#define EXPAND2(x, y) EXPAND1(x)y
+#define EXPAND3(x, y, z) EXPAND2(x, y)z
+
+/* Convoluted way to #include <MicroSpecific_JN51xx.h> */
+#undef INCLUDE_NAME
+#define INCLUDE_NAME <EXPAND3(MicroSpecific,JENNIC_CHIP_FAMILY_NAME,.h)>
+#include INCLUDE_NAME
+
+/****************************************************************************/
+/*** END OF FILE ***/
+/****************************************************************************/
+
+
diff --git a/third_party/nxp/JN5189DK6/middleware/wireless/framework/Common/MicroSpecific_JN518x.h b/third_party/nxp/JN5189DK6/middleware/wireless/framework/Common/MicroSpecific_JN518x.h
new file mode 100755
index 0000000..596fae7
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/middleware/wireless/framework/Common/MicroSpecific_JN518x.h
@@ -0,0 +1,45 @@
+/*****************************************************************************
+ *
+ * MODULE: Definitions specific to a particular processor
+ *
+ * DESCRIPTION:
+ * Definitions for a specific processor, i.e. functions that can only be
+ * resolved by op codes
+ *
+ ****************************************************************************
+ *
+ * This software is owned by NXP B.V. and/or its supplier and is protected
+ * under applicable copyright laws. All rights are reserved. We grant You,
+ * and any third parties, a license to use this software solely and
+ * exclusively on NXP products [NXP Microcontrollers such as JN5148, JN5142, JN5139].
+ * You, and any third parties must reproduce the copyright and warranty notice
+ * and any other legend of ownership on each copy or partial copy of the
+ * software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Copyright NXP B.V. 2012. All rights reserved
+ *
+ ***************************************************************************/
+
+/****************************************************************************/
+/*** Include files ***/
+/****************************************************************************/
+
+#include "MicroSpecific_arm_sdk2.h"
+
+/****************************************************************************/
+/*** END OF FILE ***/
+/****************************************************************************/
+
+
diff --git a/third_party/nxp/JN5189DK6/middleware/wireless/framework/Common/MicroSpecific_arm_sdk2.h b/third_party/nxp/JN5189DK6/middleware/wireless/framework/Common/MicroSpecific_arm_sdk2.h
new file mode 100755
index 0000000..1639803
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/middleware/wireless/framework/Common/MicroSpecific_arm_sdk2.h
@@ -0,0 +1,389 @@
+/*****************************************************************************
+ *
+ * MODULE: Definitions specific to a particular processor
+ *
+ * DESCRIPTION:
+ * Definitions for a specific processor, i.e. functions that can only be
+ * resolved by op codes
+ *
+ ****************************************************************************
+ *
+ * This software is owned by NXP B.V. and/or its supplier and is protected
+ * under applicable copyright laws. All rights are reserved. We grant You,
+ * and any third parties, a license to use this software solely and
+ * exclusively on NXP products [NXP Microcontrollers such as JN5148, JN5142, JN5139].
+ * You, and any third parties must reproduce the copyright and warranty notice
+ * and any other legend of ownership on each copy or partial copy of the
+ * software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Copyright NXP B.V. 2012, 2019. All rights reserved
+ *
+ ***************************************************************************/
+
+#ifndef MICRO_SPECIFIC_INCLUDED
+#define MICRO_SPECIFIC_INCLUDED
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+/****************************************************************************/
+/*** Include Files ***/
+/****************************************************************************/
+#include <jendefs.h>
+#include "fsl_device_registers.h"
+
+extern void (*isr_handlers[])(void);
+
+/****************************************************************************/
+/*** Macro Definitions ***/
+/****************************************************************************/
+
+/** @{ Defined system call numbers */
+#define SYSCALL_SEMIHOSTING 0xAB
+
+#define SEMIHOSTING_WRITE0 0x04
+#define SEMIHOSTING_READC 0x07
+/** @} */
+
+#define MICRO_INTERRUPT_EXCEPTION_OFFSET 16
+
+// number of bits are defined by the hardware
+#define MICRO_INTERRUPT_NUMBER_OF_PRIORITY_BITS __NVIC_PRIO_BITS
+
+// this macro depends on the setting of the priority group in the NVIC, setting G=3 in this case
+#define MICRO_INTERRUPT_MAX_PRIORITY ((1 << MICRO_INTERRUPT_NUMBER_OF_PRIORITY_BITS) - 1)
+// half way
+#define MICRO_INTERRUPT_MID_PRIORITY (MICRO_INTERRUPT_MAX_PRIORITY/2)
+
+// Priority levels in the arm are higher for lower values - B-Semi chips were the other way around
+#define MICRO_INTERRUPT_ELEVATED_PRIORITY (11)
+#define MICRO_INTERRUPT_MEDIUM_PRIORITY (12)
+
+// priority/sub priority register 8-bits wide
+// read/write priority
+#define MICRO_INTERRUPT_WRITE_PRIORITY_VALUE(W) ((W) << (8 - MICRO_INTERRUPT_NUMBER_OF_PRIORITY_BITS))
+#define MICRO_INTERRUPT_READ_PRIORITY_VALUE(R) ((R) >> (8 - MICRO_INTERRUPT_NUMBER_OF_PRIORITY_BITS))
+// read/write sub-priority
+#define MICRO_INTERRUPT_SUBPRIORITY_MASK ((1 << (8 - MICRO_INTERRUPT_NUMBER_OF_PRIORITY_BITS)) -1)
+#define MICRO_INTERRUPT_SUBPRIORITY_VALUE(S) ((S) & (MICRO_INTERRUPT_SUBPRIORITY_MASK))
+
+
+extern void vAHI_InterruptSetPriority(uint32 u32Mask, uint8 u8Level);
+extern uint8 u8AHI_InterruptGetPriority(uint32 u32InterruptNumber);
+extern void vAHI_InterruptDisable(uint32 u32EnableMask);
+extern void vAHI_TickTimerIntEnable(bool_t bIntEnable);
+extern void vAHI_InterruptSetActivePriorityLevel(uint8 u8Level);
+extern uint8 u8AHI_InterruptReadActivePriorityLevel(void);
+
+#define MICRO_ENABLE_TICK_TIMER_INTERRUPT(); \
+ vAHI_TickTimerIntEnable(TRUE);
+
+// use same value as Jennic/BA devices
+#define MICRO_SET_PIC_ENABLE(A) \
+ vAHI_InterruptSetPriority(A, 8);
+
+#define MICRO_CLEAR_PIC_ENABLE(A) \
+ vAHI_InterruptDisable(A)
+
+#define MICRO_SET_PIC_PRIORITY_LEVEL(A,B) \
+ vAHI_InterruptSetPriority(A, B);
+
+#define MICRO_GET_PIC_PRIORITY_LEVEL(A) \
+ u8AHI_InterruptGetPriority(A);
+
+/* Actual macros are instantiated in the respective CMSIS files */
+#define MICRO_ENABLE_INTERRUPTS() __enable_irq()
+
+#define MICRO_DISABLE_INTERRUPTS() __disable_irq()
+
+#define MICRO_GET_PRIMASK_LEVEL() __get_PRIMASK()
+/* Former implementation : deprecated since CMSIS alternative exists
+ * #define MICRO_GET_PRIMASK_LEVEL() \
+ * ({ \
+ * register uint32 __u32primaskLevelStore; \
+ * asm volatile ("MRS %[primasklevelstore], PRIMASK;" \
+ * :[primasklevelstore] "=r"(__u32primaskLevelStore) \
+ * : \
+ * ); \
+ * __u32primaskLevelStore; \
+ * })
+ */
+#define MICRO_SET_PRIMASK_LEVEL(A) __set_PRIMASK(A)
+/* Former implementation : deprecated since CMSIS alternative exists
+ * #define MICRO_SET_PRIMASK_LEVEL(A) \
+ * ({ \
+ * register uint32 __u32primaskLevelStore = A; \
+ * asm volatile ("MSR PRIMASK, %[primasklevelstore];" \
+ * : \
+ * :[primasklevelstore] "r"(__u32primaskLevelStore) \
+ * ); \
+ * })
+ */
+#define MICRO_GET_ACTIVE_INT_LEVEL() __get_BASEPRI()
+/* Former implementation : deprecated since CMSIS alternative exists
+ * #define MICRO_GET_ACTIVE_INT_LEVEL() \
+ * ({ \
+ * register uint32 __u32interruptActiveLevel; \
+ * asm volatile ("MRS %[activelevelstore], BASEPRI;" \
+ * :[activelevelstore] "=r"(__u32interruptActiveLevel) \
+ * : ); \
+ * __u32interruptActiveLevel; \
+ * })
+ */
+#define MICRO_SET_ACTIVE_INT_LEVEL_MAX(A) __set_BASEPRI_MAX(A)
+/* Former implementation : deprecated since CMSIS alternative exists
+ * #define MICRO_SET_ACTIVE_INT_LEVEL_MAX(A) \
+ * ({ \
+ * register uint32 __u32interruptLevelStore = A; \
+ * asm volatile ("MSR BASEPRI_MAX, %[intlevelstore];" \
+ * : \
+ * :[intlevelstore] "r"(__u32interruptLevelStore) \
+ * ); \
+ * })
+ */
+#define MICRO_SET_ACTIVE_INT_LEVEL(A) __set_BASEPRI(A)
+/* Former implementation : deprecated since CMSIS alternative exists
+ * #define MICRO_SET_ACTIVE_INT_LEVEL(A) \
+ * ({ \
+ * register uint32 __u32interruptLevelStore = A; \
+ * asm volatile ("MSR BASEPRI, %[intlevelstore];" \
+ * : \
+ * :[intlevelstore] "r"(__u32interruptLevelStore) \
+ * ); \
+ * })
+ */
+/* Read back PRIMASK status into u32Store variable then disable
+ * the interrupts */
+#define MICRO_DISABLE_AND_SAVE_INTERRUPTS(u32Store) \
+ ({ \
+ u32Store = __get_PRIMASK(); \
+ __disable_irq(); \
+ })
+/* Former implementation : deprecated since combining CMSIS alternative is
+ * possible.
+ * #define MICRO_DISABLE_AND_SAVE_INTERRUPTS(u32Store) \
+ * ({ \
+ * asm volatile ("MRS %[primasklevelstore], PRIMASK;" \
+ * :[primasklevelstore] "=r"(u32Store) \
+ * : \
+ * ); \
+ * asm volatile ("CPSID I;" : : ); \
+ * })
+ */
+#define MICRO_RESTORE_INTERRUPTS(u32Store) __set_PRIMASK(u32Store)
+/* Former implementation : deprecated since CMSIS equivalent exist.
+ * #define MICRO_RESTORE_INTERRUPTS(u32Store) \
+ * ({ \
+ * asm volatile ("MSR PRIMASK, %[primasklevelstore];" \
+ * : \
+ * :[primasklevelstore] "r"(u32Store) \
+ * ); \
+ * })
+ */
+#define MICRO_GET_EXCEPTION_STACK_FRAME() __get_MSP()
+/* Former implementation : deprecated since CMSIS equivalent exist.
+ * using AAPCS the parameter (the stack frame) wouuld map to r0
+ * #define MICRO_GET_EXCEPTION_STACK_FRAME() \
+ * { \
+ * asm volatile("MRS R0, MSP"); \
+ * }
+ */
+
+#if defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)
+/* Count Trailing Zeroes implementation for IAR :
+ * no builtin implementation for IAR, whereas __CLZ exists */
+static inline uint32_t __ctz(uint32_t x)
+{
+ uint32_t res;
+ x = __RBIT(x);
+ res = __CLZ(x);
+ return res;
+}
+#define _CTZ(x) __ctz(x)
+
+/* Find First Set : returns 0 if no bit set, otherwise returns the order
+ * of LSB bit set + 1
+ * __ffs(0) return 0, __ffs(1) returns 1, __ffs(0x8000000) returns 31
+ */
+static inline uint32_t __ffs(uint32_t x)
+{
+ register uint32 __u32Reg;
+ __u32Reg = _CTZ(x);
+ __u32Reg = __u32Reg == 32 ? 0 : __u32Reg + 1U;
+ return __u32Reg;
+}
+
+#define _FFS(x) __ffs(x)
+#else /* __IAR_SYSTEMS_ICC__ */
+/* GCC builtin */
+#define _CTZ(x) __builtin_ctz(x)
+
+#define _FFS(x) \
+({ register uint32_t __u32Reg, __ret; \
+ __u32Reg = _CTZ(x); \
+ __ret = __u32Reg == 32 ? 0 : __u32Reg + 1U; \
+ __ret; \
+})
+#endif /* __IAR_SYSTEMS_ICC__ */
+
+/* Bit Scan Reverse */
+#define MICRO_BSR(x) (31 - _CLZ(x))
+/* Bit Scan Forward */
+#define MICRO_BSF(x) _CTZ(x)
+
+#define MICRO_FFS(x) _FFS(x)
+
+
+#define FF1(__input) MICRO_FFS(__input)
+
+#define MICRO_GET_LX() __get_LR()
+/* Former implementation : deprecated since CMSIS equivalent exist.
+ * #define MICRO_GET_LX() \
+ * ({ \
+ * register uint32 __u32lxRegister; \
+ * asm volatile ("MOV %[lxRegister], R14;" \
+ * :[lxRegister] "=r"(__u32lxRegister) \
+ * : \
+ * ); \
+ * __u32lxRegister; \
+ * })
+ */
+#define MICRO_GET_STACK_LEVEL() __get_SP()
+/* Former implementation : deprecated since CMSIS equivalent exist.
+ * #define MICRO_GET_STACK_LEVEL() \
+ * ({ \
+ * register uint32 __u32stackRegister; \
+ * asm volatile ("MOV %[stackRegister], SP;" \
+ * :[stackRegister] "=r"(__u32stackRegister) \
+ * : \
+ * ); \
+ * __u32stackRegister; \
+ * })
+ */
+
+#define MICRO_TRAP() __BKPT(0)
+/* Former implementation : deprecated since CMSIS equivalent exist.
+ * #define MICRO_TRAP() asm volatile("BKPT 0;")
+ */
+#define MICRO_NOP() __NOP()
+/* Former implementation : deprecated since CMSIS equivalent exist.
+ * #define MICRO_NOP() asm volatile ("nop;")
+ */
+
+/* macro using privilege/non-privilege model:
+ * u32reg is the register to return the stack pointer that corresponds to
+ * the mode we are in: either MSP or PSP.
+ * Note: this macro has chnaged fir IAR compatibility u32reg is the return
+ * register so that R0 is not implicitly the returned value
+ */
+#define MICRO_GET_EXCEPTION_STACK_FRAME_PNPM(u32reg) \
+ register uint32_t u32reg; \
+ asm volatile("TST LR, #4\n\t" \
+ "ITE EQ\n\t" \
+ "MRSEQ R0, MSP\n\t" \
+ "MRSNE R0, PSP\n\t"); \
+ asm volatile ("MOV %0, R0" : "=r" (u32reg) : /* no input */ );
+
+/* Interrupt Handler registration - only useful if you're putting the handlers
+ * in RAM */
+
+/* Location of isr_handlers is no longer at a known location, but we can link
+ to it directly instead */
+#define MICRO_SET_INT_HANDLER(INT, FUNC); \
+ isr_handlers[(MICRO_INTERRUPT_EXCEPTION_OFFSET + INT)] = (void *)(FUNC);
+
+#define MICRO_GET_INT_HANDLER(INT) \
+ (isr_handlers[(MICRO_INTERRUPT_EXCEPTION_OFFSET + INT)])
+
+/* Nested interrupt control */
+#define MICRO_INT_STORAGE tsMicroIntStorage sIntStorage
+#define MICRO_INT_ENABLE_ONLY(A) vMicroIntEnableOnly(&sIntStorage, A)
+#define MICRO_INT_RESTORE_STATE() vMicroIntRestoreState(&sIntStorage)
+
+/* Exception Handlers */
+#define MICRO_ESR_NUM_RESETISR 1
+#define MICRO_ESR_NUM_NMI 2
+#define MICRO_ESR_NUM_HARDFAULT 3
+#define MICRO_ESR_NUM_MEMMANAGE 4
+#define MICRO_ESR_NUM_BUSFAULT 5
+#define MICRO_ESR_NUM_USGFAULT 6
+// 4 reserved handlers here
+#define MICRO_ESR_NUM_SVCALL 11
+#define MICRO_ESR_NUM_DEBUGMON 12
+// 1 reserved handler here
+#define MICRO_ESR_NUM_PENDSV 14
+#define MICRO_ESR_NUM_SYSTICK 15
+
+/* Location of exception_handlers is no longer at a known location, but we can link
+ to it directly instead - only useful if you're putting the handlers
+ * in RAM */
+#define MICRO_SET_EXCEPTION_HANDLER(EXCEPTION, FUNC) \
+ isr_handlers[EXCEPTION] = (void *)(FUNC);
+
+#define MICRO_GET_EXCEPTION_HANDLER(INT) \
+ (isr_handlers[EXCEPTION])
+
+/* NOP instruction */
+
+
+/* TRAP instruction */
+
+#define MICRO_JUMP_TO_ADDRESS(ADDRESS) \
+ ({ \
+ register uint32 __u32programAddressStore = ADDRESS | 0x1; \
+ asm volatile ("BLX %[programAddressStore];" \
+ : \
+ :[programAddressStore] "r"(__u32programAddressStore)); \
+ })
+
+/****************************************************************************/
+/*** Type Definitions ***/
+/****************************************************************************/
+/* Nested interrupt control */
+typedef struct
+{
+ uint8 u8Level;
+} tsMicroIntStorage;
+
+/****************************************************************************/
+/*** Exported Functions ***/
+/****************************************************************************/
+PUBLIC void vAHI_InitialiseInterruptController(uint32 *pu32InterruptVectorTable);
+
+/* Nested interrupt control */
+PUBLIC void vMicroIntSetGlobalEnable(uint32 u32EnableMask);
+PUBLIC void vMicroIntEnableOnly(tsMicroIntStorage *, uint32 u32EnableMask);
+PUBLIC void vMicroIntRestoreState(tsMicroIntStorage *);
+/* Default Exception Handler */
+PUBLIC void vIntDefaultHandler(void);
+
+PUBLIC void __attribute__((noinline)) vMicroSyscall(volatile uint32 u32SysCallNumber, ...);
+PUBLIC void __attribute__((noinline)) vMicroSemihost(volatile uint32 u32SemihostNumber, ...);
+
+/****************************************************************************/
+/*** Exported Variables ***/
+/****************************************************************************/
+
+#if defined __cplusplus
+}
+#endif
+
+#endif /* MICRO_SPECIFIC_INCLUDED */
+
+/****************************************************************************/
+/*** END OF FILE ***/
+/****************************************************************************/
+
diff --git a/third_party/nxp/JN5189/JennicCommon/Include/jendefs.h b/third_party/nxp/JN5189DK6/middleware/wireless/framework/Common/jendefs.h
similarity index 86%
rename from third_party/nxp/JN5189/JennicCommon/Include/jendefs.h
rename to third_party/nxp/JN5189DK6/middleware/wireless/framework/Common/jendefs.h
index 8b65463..a54189f 100755
--- a/third_party/nxp/JN5189/JennicCommon/Include/jendefs.h
+++ b/third_party/nxp/JN5189DK6/middleware/wireless/framework/Common/jendefs.h
@@ -1,10 +1,35 @@
-/*
-* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
-* Copyright 2016-2019 NXP
-* All rights reserved.
-*
-* SPDX-License-Identifier: BSD-3-Clause
-*/
+/*****************************************************************************
+ *
+ * MODULE: ALL MODULES
+ *
+ * DESCRIPTION: The JENNIC standard header file defining extensions to
+ * ANSI C standard required by the Jennic C coding standard.
+ *
+ ****************************************************************************
+ *
+ * This software is owned by NXP B.V. and/or its supplier and is protected
+ * under applicable copyright laws. All rights are reserved. We grant You,
+ * and any third parties, a license to use this software solely and
+ * exclusively on NXP products [NXP Microcontrollers such as JN5148, JN5142, JN5139].
+ * You, and any third parties must reproduce the copyright and warranty notice
+ * and any other legend of ownership on each copy or partial copy of the
+ * software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Copyright NXP B.V. 2012. All rights reserved
+ *
+ ***************************************************************************/
#ifndef JENDEFS_INCLUDED
#define JENDEFS_INCLUDED
@@ -73,6 +98,9 @@
#define ALWAYS_INLINE
#define INLINE __inline
+
+#elif defined(__IAR_SYSTEMS_ICC__)
+// if compiled for IAR, none of the above defines are required
#else
#error "Unsupported compiler"
#endif
@@ -312,3 +340,5 @@
/****************************************************************************/
/*** END OF FILE ***/
/****************************************************************************/
+
+
diff --git a/third_party/nxp/JN5189/Radio_JN5189/Include/radio.h b/third_party/nxp/JN5189DK6/middleware/wireless/framework/XCVR/DK6/radio.h
similarity index 98%
rename from third_party/nxp/JN5189/Radio_JN5189/Include/radio.h
rename to third_party/nxp/JN5189DK6/middleware/wireless/framework/XCVR/DK6/radio.h
index 71f0638..a081ddb 100755
--- a/third_party/nxp/JN5189/Radio_JN5189/Include/radio.h
+++ b/third_party/nxp/JN5189DK6/middleware/wireless/framework/XCVR/DK6/radio.h
@@ -2,8 +2,7 @@
* @brief Radio driver
*
* @note
- * Copyright(C) NXP Semiconductors, 2014
- * All rights reserved.
+ * Copyright 2019 NXP
*
* @par
* Software that is described herein is for illustrative purposes only
@@ -47,7 +46,7 @@
/****************************************************************************/
/*** Radio driver version (XYYY): X major version, YYY minor version ***/
/****************************************************************************/
-#define RADIO_VERSION (2085)
+#define RADIO_VERSION (2088)
/****************************************************************************/
/*** Radio calibration data record version ***/
@@ -785,6 +784,22 @@
uint8_t u8Radio_AntennaDiversityStatus(void);
+/****************************************************************************
+ *
+ * NAME: vRadio_SetBLEdpTopEmAddr
+ *
+ * DESCRIPTION:
+ * Configure LL_EM_BASE_ADDRESS of BLEMODEM parameter.
+ *
+ * PARAMETERS:
+ * uint32_t em_addr: EM address.
+ *
+ * RETURNS:
+ * None.
+ *
+ ****************************************************************************/
+void vRadio_SetBLEdpTopEmAddr(uint32_t em_addr);
+
#ifdef __cplusplus
}
diff --git a/third_party/nxp/JN5189DK6/middleware/wireless/framework/XCVR/lib/libRadio.a b/third_party/nxp/JN5189DK6/middleware/wireless/framework/XCVR/lib/libRadio.a
new file mode 100755
index 0000000..b4e3ae9
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/middleware/wireless/framework/XCVR/lib/libRadio.a
Binary files differ
diff --git a/third_party/nxp/JN5189DK6/middleware/wireless/ieee-802.15.4/lib/libMiniMac.a b/third_party/nxp/JN5189DK6/middleware/wireless/ieee-802.15.4/lib/libMiniMac.a
new file mode 100755
index 0000000..4c5bd12
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/middleware/wireless/ieee-802.15.4/lib/libMiniMac.a
Binary files differ
diff --git a/third_party/nxp/JN5189/uMac/Include/MMAC.h b/third_party/nxp/JN5189DK6/middleware/wireless/ieee-802.15.4/uMac/Include/MMAC.h
similarity index 92%
rename from third_party/nxp/JN5189/uMac/Include/MMAC.h
rename to third_party/nxp/JN5189DK6/middleware/wireless/ieee-802.15.4/uMac/Include/MMAC.h
index 21b325e..dba5a96 100755
--- a/third_party/nxp/JN5189/uMac/Include/MMAC.h
+++ b/third_party/nxp/JN5189DK6/middleware/wireless/ieee-802.15.4/uMac/Include/MMAC.h
@@ -22,6 +22,7 @@
/****************************************************************************/
/*** Macro/Type Definitions ***/
/****************************************************************************/
+
typedef struct
{
uint32 u32L; /**< Low word */
@@ -147,9 +148,11 @@
/* Flags for transmit status, as returned by u32MMAC_GetTxErrors */
typedef enum
{
- E_MMAC_TXSTAT_CCA_BUSY = 0x01, /* Channel wasn't free */
- E_MMAC_TXSTAT_NO_ACK = 0x02, /* Ack requested but not seen */
- E_MMAC_TXSTAT_ABORTED = 0x04 /* Transmission aborted by user */
+ E_MMAC_TXSTAT_CCA_BUSY = 0x01, /* Channel wasn't free */
+ E_MMAC_TXSTAT_NO_ACK = 0x02, /* Ack requested but not seen */
+ E_MMAC_TXSTAT_ABORTED = 0x04, /* Transmission aborted by user */
+ E_MMAC_TXSTAT_TXTO = 0x20, /* Radio transmission timeout */
+ E_MMAC_TXSTAT_TXPCTO = 0x40 /* Modem transmission timeout */
} teTxStatus;
/* Flags for interrupt status, as returned to handler registered with
@@ -202,6 +205,9 @@
PUBLIC void vMMAC_RxCtlUpdate(uint32 u32NewValue);
PUBLIC void vMMAC_AbortRadio(void);
PUBLIC void vMMAC_SetHighPowerOptions(void);
+PUBLIC void vMMAC_PromiscuousMode(bool_t bPromiscuous);
+PUBLIC void vMMAC_WriteCcaThreshold(uint8 u8CcaThreshold);
+PUBLIC uint8 u8MMAC_ReadCcaThreshold(void);
/* Receive */
PUBLIC void vMMAC_SetRxAddress(uint32 u32PanId, uint16 u16Short,
@@ -212,6 +218,8 @@
PUBLIC void vMMAC_SetRxStartTime(uint32 u32Time);
PUBLIC void vMMAC_StartMacReceive(tsMacFrame *psFrame, teRxOption eOptions);
PUBLIC void vMMAC_StartPhyReceive(tsPhyFrame *psFrame, teRxOption eOptions);
+PUBLIC void vMMAC_SetRxFrame(tsRxFrameFormat *pRxFrame);
+PUBLIC void vMMAC_SetRxProm(uint32_t u32Prom);
PUBLIC bool_t bMMAC_RxDetected(void);
PUBLIC uint32 u32MMAC_GetRxErrors(void);
PUBLIC uint32 u32MMAC_GetRxTime(void);
@@ -224,6 +232,7 @@
PUBLIC void vMMAC_SetCcaMode(teCcaMode eCcaMode);
PUBLIC void vMMAC_StartMacTransmit(tsMacFrame *psFrame, teTxOption eOptions);
PUBLIC void vMMAC_StartPhyTransmit(tsPhyFrame *psFrame, teTxOption eOptions);
+PUBLIC void vMMAC_SetTxPend(bool_t bTxPend);
PUBLIC uint32 u32MMAC_GetTxErrors(void);
PUBLIC bool_t bMMAC_PowerStatus(void);
diff --git a/third_party/nxp/JN5189/app/app_ota.h b/third_party/nxp/JN5189DK6/middleware/wireless/openthread/examples/posix_ota_server/app_ota.h
similarity index 92%
rename from third_party/nxp/JN5189/app/app_ota.h
rename to third_party/nxp/JN5189DK6/middleware/wireless/openthread/examples/posix_ota_server/app_ota.h
index 26e6309..df7d876 100755
--- a/third_party/nxp/JN5189/app/app_ota.h
+++ b/third_party/nxp/JN5189DK6/middleware/wireless/openthread/examples/posix_ota_server/app_ota.h
@@ -1,6 +1,5 @@
/*
-* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
-* Copyright 2016-2017 NXP
+* Copyright 2019-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -71,20 +70,22 @@
/*! Ota status */
typedef enum otaStatus_tag
{
- gOtaStatus_Success_c = 0x00,
- gOtaStatus_Failed_c = 0x01,
- gOtaStatus_InvalidInstance_c = 0x02,
- gOtaStatus_InvalidParam_c = 0x03,
- gOtaStatus_NotPermitted_c = 0x04,
- gOtaStatus_NotStarted_c = 0x05,
- gOtaStatus_NoMem_c = 0x06,
- gOtaStatus_UnsupportedAttr_c = 0x07,
- gOtaStatus_EmptyEntry_c = 0x08,
- gOtaStatus_InvalidValue_c = 0x09,
- gOtaStatus_AlreadyStarted_c = 0x0A,
- gOtaStatus_NoTimers_c = 0x0B,
- gOtaStatus_NoUdpSocket_c = 0x0C,
- gOtaStatus_EntryNotFound_c = 0xFF
+ gOtaStatus_Success_c = 0x00,
+ gOtaStatus_Failed_c = 0x01,
+ gOtaStatus_InvalidInstance_c = 0x02,
+ gOtaStatus_InvalidParam_c = 0x03,
+ gOtaStatus_NotPermitted_c = 0x04,
+ gOtaStatus_NotStarted_c = 0x05,
+ gOtaStatus_NoMem_c = 0x06,
+ gOtaStatus_UnsupportedAttr_c = 0x07,
+ gOtaStatus_EmptyEntry_c = 0x08,
+ gOtaStatus_InvalidValue_c = 0x09,
+ gOtaStatus_AlreadyStarted_c = 0x0A,
+ gOtaStatus_NoTimers_c = 0x0B,
+ gOtaStatus_NoUdpSocket_c = 0x0C,
+ gOtaStatus_FlashError_c = 0x0D,
+ gOtaStatus_TransferTypeNotSupported_c = 0x0E,
+ gOtaStatus_EntryNotFound_c = 0xFF
} otaStatus_t;
/* OTA File Status */
diff --git a/third_party/nxp/JN5189/app/app_ota_server.c b/third_party/nxp/JN5189DK6/middleware/wireless/openthread/examples/posix_ota_server/app_ota_server.c
similarity index 98%
rename from third_party/nxp/JN5189/app/app_ota_server.c
rename to third_party/nxp/JN5189DK6/middleware/wireless/openthread/examples/posix_ota_server/app_ota_server.c
index d9a4475..8c7792a 100755
--- a/third_party/nxp/JN5189/app/app_ota_server.c
+++ b/third_party/nxp/JN5189DK6/middleware/wireless/openthread/examples/posix_ota_server/app_ota_server.c
@@ -1,13 +1,12 @@
/*
-* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
-* Copyright 2016-2017 NXP
+* Copyright 2019-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*!=================================================================================================
-\file app_ota_server.c
+\file app_ota_server.c
\brief This is a public source file for the OTA server module
==================================================================================================*/
@@ -87,6 +86,14 @@
gOtaServerMulticastState_ResetMulticast_c
} otaServerMulticastState_t;
+/* ota server multicast state: */
+typedef enum
+{
+ otaServerClientImageTypeREED = 0x0000,
+ otaServerClientImageTypeED = 0x0001,
+ otaServerClientImageTypeLPED = 0x0002
+} otaServerClientImageType;
+
typedef struct otaServerSetup_tag
{
otInstance *pOtInstance;
@@ -298,22 +305,26 @@
otaStatus_t OtaServer_StartOta(uint8_t otaType, const char *pFilePath)
{
otaServer_ImageNotify_t *pImageNotify = NULL;
+ otaStatus_t status = gOtaStatus_Success_c;
if ((otaType != gOtaUnicast_c) && (otaType != gOtaMulticast_c))
{
- return gOtaStatus_Failed_c;
+ status = gOtaStatus_Failed_c;
+ goto exit;
}
// Check if device is connected before starting OTA
if (otThreadGetDeviceRole(mOtaServerSetup.pOtInstance) < OT_DEVICE_ROLE_CHILD)
{
- return gOtaStatus_NotPermitted_c;
+ status = gOtaStatus_NotPermitted_c;
+ goto exit;
}
// Check if OTA process is already active
if (mOtaServerSetup.isActive == true)
{
- return gOtaStatus_AlreadyStarted_c;
+ status = gOtaStatus_AlreadyStarted_c;
+ goto exit;
}
if (pFilePath != NULL)
@@ -322,12 +333,14 @@
if (!(access(binary_file_path, F_OK) != -1))
{
- return gOtaStatus_InvalidValue_c;
+ status = gOtaStatus_InvalidValue_c;
+ goto exit;
}
}
else
{
- return gOtaStatus_EmptyEntry_c;
+ status = gOtaStatus_EmptyEntry_c;
+ goto exit;
}
// Set multicast addresses used in OTA process
@@ -347,6 +360,16 @@
OtaServer_InitStandaloneOpMode();
+ if (mOtaServerImageList[mOtaServerTempImageIdx].imageType == otaServerClientImageTypeLPED)
+ {
+ if (otaType == gOtaMulticast_c)
+ {
+ mOtaServerSetup.transferType = gOtaUnicast_c;
+ mOtaServerPercentageInformation.otaType = gOtaUnicast_c;
+ status = gOtaStatus_TransferTypeNotSupported_c;
+ }
+ }
+
// OTA Multicast parameters. Not used for OTA unicast.
if (mOtaServerSetup.transferType == gOtaMulticast_c)
{
@@ -361,7 +384,8 @@
OtaServer_SetTimeCallback(OtaServer_MulticastTimeoutCb, (void *)pImageNotify, 100);
}
- return gOtaStatus_Success_c;
+exit:
+ return status;
}
/*!*************************************************************************************************
diff --git a/third_party/nxp/JN5189DK6/middleware/wireless/openthread/examples/posix_ota_server/example_vendor_hook.cpp b/third_party/nxp/JN5189DK6/middleware/wireless/openthread/examples/posix_ota_server/example_vendor_hook.cpp
new file mode 100755
index 0000000..0c47ca4
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/middleware/wireless/openthread/examples/posix_ota_server/example_vendor_hook.cpp
@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2019-2020, The OpenThread Authors.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ * This file shows how to implement the NCP vendor hook.
+ */
+
+#if OPENTHREAD_ENABLE_NCP_VENDOR_HOOK
+
+#include "ncp_base.hpp"
+
+#include "../../third_party/nxp/JN5189DK6/middleware/wireless/openthread/examples/posix_ota_server/app_ota.h"
+namespace ot {
+namespace Ncp {
+
+otError NcpBase::VendorCommandHandler(uint8_t aHeader, unsigned int aCommand)
+{
+ otError error = OT_ERROR_NONE;
+
+ switch (aCommand)
+ {
+
+ // TODO: Implement your command handlers here.
+ case SPINEL_CMD_VENDOR_NXP_OTA_START:
+ uint8_t otaType, start_result;
+ const char * file_path;
+
+ SuccessOrExit(error = mDecoder.ReadUint8(otaType));
+ SuccessOrExit(error = mDecoder.ReadUtf8(file_path));
+
+ //Start OTA process
+ start_result = OtaServer_StartOta(otaType, file_path);
+
+ SuccessOrExit(error = mEncoder.BeginFrame(aHeader, SPINEL_CMD_PROP_VALUE_IS, SPINEL_PROP_NXP_OTA_START_RET));
+ SuccessOrExit(error = mEncoder.WriteUint8(start_result));
+ SuccessOrExit(error = mEncoder.EndFrame());
+
+ break;
+
+ case SPINEL_CMD_VENDOR_NXP_OTA_STOP:
+ //Stop OTA process
+ SuccessOrExit(error = mEncoder.BeginFrame(aHeader, SPINEL_CMD_PROP_VALUE_IS, SPINEL_PROP_NXP_OTA_STOP_RET));
+ SuccessOrExit(error = mEncoder.WriteUint8(OtaServer_StopOta()));
+ SuccessOrExit(error = mEncoder.EndFrame());
+
+ break;
+
+ case SPINEL_CMD_VENDOR_NXP_OTA_STATUS:
+ //Get OTA process status
+ otaServerPercentageInfo_t otaInfo;
+ OtaServer_GetOtaStatus(&otaInfo);
+
+ SuccessOrExit(error = mEncoder.BeginFrame(aHeader, SPINEL_CMD_PROP_VALUE_IS, SPINEL_PROP_NXP_OTA_STATUS_RET));
+ SuccessOrExit(error = mEncoder.WriteData((uint8_t *)&otaInfo, sizeof(otaInfo)));
+ SuccessOrExit(error = mEncoder.EndFrame());
+
+ break;
+
+ default:
+ error = PrepareLastStatusResponse(aHeader, SPINEL_STATUS_INVALID_COMMAND);
+ }
+
+exit:
+
+ return error;
+}
+
+void NcpBase::VendorHandleFrameRemovedFromNcpBuffer(NcpFrameBuffer::FrameTag aFrameTag)
+{
+ // This method is a callback which mirrors `NcpBase::HandleFrameRemovedFromNcpBuffer()`.
+ // It is called when a spinel frame is sent and removed from NCP buffer.
+ //
+ // (a) This can be used to track and verify that a vendor spinel frame response is
+ // delivered to the host (tracking the frame using its tag).
+ //
+ // (b) It indicates that NCP buffer space is now available (since a spinel frame is
+ // removed). This can be used to implement reliability mechanisms to re-send
+ // a failed spinel command response (or an async spinel frame) transmission
+ // (failed earlier due to NCP buffer being full).
+
+ OT_UNUSED_VARIABLE(aFrameTag);
+}
+
+otError NcpBase::VendorGetPropertyHandler(spinel_prop_key_t aPropKey)
+{
+ otError error = OT_ERROR_NONE;
+
+ switch (aPropKey)
+ {
+
+ // TODO: Implement your property get handlers here.
+ //
+ // Get handler should retrieve the property value and then encode and write the
+ // value into the NCP buffer. If the "get" operation itself fails, handler should
+ // write a `LAST_STATUS` with the error status into the NCP buffer. `OT_ERROR_NO_BUFS`
+ // should be returned if NCP buffer is full and response cannot be written.
+
+ default:
+ error = OT_ERROR_NOT_FOUND;
+ break;
+ }
+
+ return error;
+}
+
+otError NcpBase::VendorSetPropertyHandler(spinel_prop_key_t aPropKey)
+{
+ otError error = OT_ERROR_NONE;
+
+ switch (aPropKey)
+ {
+
+ // TODO: Implement your property set handlers here.
+ //
+ // Set handler should first decode the value from the input Spinel frame and then
+ // perform the corresponding set operation. The handler should not prepare the
+ // spinel response and therefore should not write anything to the NCP buffer.
+ // The error returned from handler (other than `OT_ERROR_NOT_FOUND`) indicates the
+ // error in either parsing of the input or the error of the set operation. In case
+ // of a successful "set", `NcpBase` set command handler will invoke the
+ // `VendorGetPropertyHandler()` for the same property key to prepare the response.
+
+ default:
+ error = OT_ERROR_NOT_FOUND;
+ break;
+ }
+
+ return error;
+}
+
+} // namespace Ncp
+} // namespace ot
+
+//-------------------------------------------------------------------------------------------------------------------
+// When OPENTHREAD_ENABLE_NCP_VENDOR_HOOK is enabled, vendor code is
+// expected to provide the `otNcpInit()` function. The reason behind
+// this is to enable vendor code to define its own sub-class of
+// `NcpBase` or `NcpUart`/`NcpSpi`.
+//
+// Example below show how to add a vendor sub-class over `NcpUart`.
+
+#include "ncp_uart.hpp"
+#include "common/new.hpp"
+
+class NcpVendorUart : public ot::Ncp::NcpUart
+{
+public:
+ NcpVendorUart(ot::Instance *aInstance)
+ : ot::Ncp::NcpUart(aInstance)
+ {}
+
+ // Add public/private methods or member variables
+};
+
+static otDEFINE_ALIGNED_VAR(sNcpVendorRaw, sizeof(NcpVendorUart), uint64_t);
+
+extern "C" void otNcpInit(otInstance *aInstance)
+{
+ NcpVendorUart *ncpVendor = NULL;
+ ot::Instance * instance = static_cast<ot::Instance *>(aInstance);
+
+ ncpVendor = new (&sNcpVendorRaw) NcpVendorUart(instance);
+
+ if (ncpVendor == NULL || ncpVendor != ot::Ncp::NcpBase::GetNcpInstance())
+ {
+ assert(false);
+ }
+}
+
+#endif // #if OPENTHREAD_ENABLE_NCP_VENDOR_HOOK
diff --git a/third_party/nxp/JN5189/app/network_utils.c b/third_party/nxp/JN5189DK6/middleware/wireless/openthread/examples/posix_ota_server/network_utils.c
similarity index 98%
rename from third_party/nxp/JN5189/app/network_utils.c
rename to third_party/nxp/JN5189DK6/middleware/wireless/openthread/examples/posix_ota_server/network_utils.c
index 626d2b1..6cd1baf 100755
--- a/third_party/nxp/JN5189/app/network_utils.c
+++ b/third_party/nxp/JN5189DK6/middleware/wireless/openthread/examples/posix_ota_server/network_utils.c
@@ -1,6 +1,5 @@
/*
-* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
-* Copyright 2016-2017 NXP
+* Copyright 2019-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/third_party/nxp/JN5189/app/network_utils.h b/third_party/nxp/JN5189DK6/middleware/wireless/openthread/examples/posix_ota_server/network_utils.h
similarity index 94%
rename from third_party/nxp/JN5189/app/network_utils.h
rename to third_party/nxp/JN5189DK6/middleware/wireless/openthread/examples/posix_ota_server/network_utils.h
index 17c142e..2145c94 100755
--- a/third_party/nxp/JN5189/app/network_utils.h
+++ b/third_party/nxp/JN5189DK6/middleware/wireless/openthread/examples/posix_ota_server/network_utils.h
@@ -1,10 +1,5 @@
-/*! *********************************************************************************
- * \defgroup NUT Thread Network Utilities Interface
- * @{
- ***********************************************************************************/
/*
-* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
-* Copyright 2016-2017 NXP
+* Copyright 2019-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/third_party/nxp/JN5189DK6/middleware/wireless/openthread/examples/posix_ota_server/posix_ota_server_readme.txt b/third_party/nxp/JN5189DK6/middleware/wireless/openthread/examples/posix_ota_server/posix_ota_server_readme.txt
new file mode 100755
index 0000000..8a11ceb
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/middleware/wireless/openthread/examples/posix_ota_server/posix_ota_server_readme.txt
@@ -0,0 +1,64 @@
+This readme is intended to be used as a guideline for building the OpenThread POSIX Border Router application with NXP OTA server support,
+available for JN5189/K32W061(041) OpenThread SDK.
+
+The following steps must be followed:
+1. Clone the OpenThread repository available here: https://github.com/openthread
+
+2. Search for the spinel.h header file and open it. In older releases, the file was located in <ot_root>\src\ncp\, while in newer releases, the file resides in <ot_root>\src\lib\spinel\.
+
+ a. Beneath the line containing "SPINEL_CMD_VENDOR__BEGIN = 15360,", add the following lines:
+"
+ // NXP OTA START COMMAND
+ SPINEL_CMD_VENDOR_NXP_OTA_START = SPINEL_CMD_VENDOR__BEGIN + 1,
+ SPINEL_CMD_VENDOR_NXP_OTA_START_RET = SPINEL_CMD_VENDOR__BEGIN + 2,
+ SPINEL_CMD_VENDOR_NXP_OTA_STOP = SPINEL_CMD_VENDOR__BEGIN + 3,
+ SPINEL_CMD_VENDOR_NXP_OTA_STOP_RET = SPINEL_CMD_VENDOR__BEGIN + 4,
+ SPINEL_CMD_VENDOR_NXP_OTA_STATUS = SPINEL_CMD_VENDOR__BEGIN + 5,
+ SPINEL_CMD_VENDOR_NXP_OTA_STATUS_RET = SPINEL_CMD_VENDOR__BEGIN + 6,
+"
+
+ b. Beneath the line containing "SPINEL_PROP_VENDOR__BEGIN = 0x3C00,", add the following lines:
+"
+ SPINEL_PROP_NXP_OTA_START_RET = SPINEL_PROP_VENDOR__BEGIN + 0,
+ SPINEL_PROP_NXP_OTA_STOP_RET = SPINEL_PROP_VENDOR__BEGIN + 1,
+ SPINEL_PROP_NXP_OTA_STATUS_RET = SPINEL_PROP_VENDOR__BEGIN + 2,
+"
+
+ c. Save and close the file.
+
+3. Open main.c source file from <ot_root>\src\posix\.
+ a. Add the following include at the beginning of the file: #include "app_ota.h"
+ b. Before the "while (true)" loop, add a function call to OtaServerInit, for example "OtaServerInit(instance);".
+ c. At the end of the loop, before the closing brackets, add a function call to OtaServer_CheckTime, for example "OtaServer_CheckTime();".
+ d. Save and close the file.
+
+4. In Makefile.am from <ot_root>\src\posix\, do the following changes:
+ a. Add the following entry to CPPFLAGS_COMMON before $(NULL):
+"-I$(top_srcdir)/third_party/nxp/<sdk_root>/middleware/wireless/openthread/examples/posix_ota_server \"
+
+ b. Add the following entry to ot_ncp_SOURCES before $(NULL):
+"
+@top_builddir@/third_party/nxp/<sdk_root>/middleware/wireless/openthread/examples/posix_ota_server/app_ota_server.c \
+@top_builddir@/third_party/nxp/<sdk_root>/middleware/wireless/openthread/examples/posix_ota_server/network_utils.c \
+"
+
+ c. Add the following entry to ot_cli_SOURCES before $(NULL):
+"
+@top_builddir@/third_party/nxp/<sdk_root>/middleware/wireless/openthread/examples/posix_ota_server/app_ota_server.c \
+@top_builddir@/third_party/nxp/<sdk_root>/middleware/wireless/openthread/examples/posix_ota_server/network_utils.c \
+"
+
+ d. Save and close the file.
+
+5. In Makefile-posix from <ot_root>\src\posix\, do the following changes:
+ a. Add the following entry to configure_OPTIONS before $(NULL):
+"--with-ncp-vendor-hook-source="$(AbsTopSourceDir)/third_party/nxp/<sdk_root>/middleware/wireless/openthread/examples/posix_ota_server/example_vendor_hook.cpp"\"
+
+ b. Add the following line under "# Platform specific switches":
+"COMMONCFLAGS += -DOPENTHREAD_ENABLE_NCP_VENDOR_HOOK=1"
+
+ c. Save and close the file.
+
+6. Run the bootstrap script and follow the rest of the steps to build and run the POSIX application described in <ot_root>\src\posix\README.md.
+
+Note: <sdk_root> needs to be replaced with JN5189DK6 or K32W061DK6.
\ No newline at end of file
diff --git a/third_party/nxp/JN5189DK6/tools/imagetool/dk6_image_tool.py b/third_party/nxp/JN5189DK6/tools/imagetool/dk6_image_tool.py
new file mode 100755
index 0000000..48ea6a2
--- /dev/null
+++ b/third_party/nxp/JN5189DK6/tools/imagetool/dk6_image_tool.py
@@ -0,0 +1,503 @@
+#!python
+
+from collections import namedtuple
+import re
+import argparse
+import subprocess
+import struct
+from Crypto.Signature import pkcs1_15
+from Crypto.PublicKey import RSA
+from Crypto.Hash import SHA256
+from Crypto.Util import number
+import binascii
+import os
+import StringIO
+
+def auto_int(x):
+ return int(x, 0)
+
+parser = argparse.ArgumentParser(description='DK6 Image Header Generator')
+parser.add_argument('in_file', help="Binary to be post-processed: generating header and optionally appending certificate and/or signature.")
+parser.add_argument('out_file', nargs='?')
+parser.add_argument('-g', '--signature_path', help="Sets directory from which certificate and private key are to be retrieved")
+parser.add_argument('-k', '--key', action='store_true', help="2048 bits RSA private key in PEM format used to sign the full image. If -c option is used the full image includes the certificate + the signature of the certificate. The key shall be located in the same directory as the image_tool script. See priv_key.pem example.")
+parser.add_argument('-p', '--password',help="This is the pass phrase from which the encryption key is derived. This parameter is only required if key provided through the -k option is a PEM encrypted key.")
+parser.add_argument('-c', '--certificate', action='store_true', help="When option is selected, the certificate cert.bin is appended to the image.")
+parser.add_argument('-i', '--image_identifier', type=int, help="This parameter is to set the archive identifier. 0: SSBL or legacy JN518x/QN9090 applications, loaded at 0x00000000. 1: application (ZB) loaded at address 0x00004000 by default. 2: application (BLE) image loaded at address 0x00053000 by default")
+parser.add_argument('-a', '--appcore_image', action='store_true',help="This parameter is only relevant if dual application (app1 image) shall reside in flash. Do not use in conjunction with -i option.")
+parser.add_argument('-t', '--target_addr', type=int, help="Target address of image. Used in conjunction with -i option to override the default set by image identifier, or with -a option to specify address of the appcore image (app1 image).")
+parser.add_argument('-s', '--stated_size', type=int, help="This is the stated size of the image in bytes. Default is 0x48000.")
+parser.add_argument('-v', '--version', type=auto_int, default=0, help="Image version. Default is 0.")
+parser.add_argument('-b', '--verbose', type=int, default=0, help="verbosity level. Default is 0.")
+parser.add_argument('-cl', '--compatibility_list', help="Compatibility list")
+parser.add_argument('-sota', '--sota_number_of_blob', type=int, help="This parameter is used to generate the image directory command to be provisioned")
+parser.add_argument('-bid', '--blob_id', type=auto_int, help="This parameter is to add a blob id. Can be used only if the sota arg is given")
+
+
+JN518x_ES1 = 0
+args = parser.parse_args()
+
+elf_file_name = args.in_file
+bin_file_name = elf_file_name.split(".")[0]+'_temp.bin'
+
+if args.out_file is None:
+ args.out_file = elf_file_name
+
+verbose = args.verbose != 0
+
+
+def get_symbol_value(file, symb_name):
+ val = 0
+
+ objdump = subprocess.check_output(['arm-none-eabi-objdump', '--syms', file])
+
+ symb_re = re.compile(r'^([0-9a-f]{8})[\s\S]+[\s]+([0-9a-f]{8})\s([\w\.]+)')
+
+ for ln in StringIO.StringIO(objdump):
+ m = symb_re.match(ln)
+ if m:
+ if m.group(3) == symb_name:
+ val = int(m.group(1), 16)
+ break
+
+ return val
+
+def parse_sections(file):
+ sections = {}
+
+ Section = namedtuple('Section', ['idx', 'name', 'size', 'vma', 'lma', 'offset', 'align', 'flags'])
+
+ objdump = subprocess.check_output(['arm-none-eabi-objdump', '-h', file])
+
+ section_re = re.compile(r'(?P<idx>[0-9]+)\s'
+ r'(?P<name>.{13,})s*'
+ r'(?P<size>[0-9a-f]{8})\s*'
+ r'(?P<vma>[0-9a-f]{8})\s*'
+ r'(?P<lma>[0-9a-f]{8})\s*'
+ r'(?P<offset>[0-9a-f]{8})\s*'
+ r'(?P<align>[0-9*]*)\s*'
+ r'(?P<flags>[[[\w]*[, [\w]*]*)')
+
+ for match in re.finditer(section_re, objdump):
+ sec_dict = match.groupdict()
+
+ sec_dict['idx'] = int(sec_dict['idx'])
+
+ for attr in ['vma', 'lma', 'size', 'offset']:
+ sec_dict[attr] = int(sec_dict[attr], 16)
+
+ sec_dict['align'] = eval(sec_dict['align'])
+
+ sections[sec_dict['name']] = Section(**sec_dict)
+
+ return sections
+
+def reverseString2by2(string, stringLength):
+ result = ""
+ i = stringLength-1
+ while i >=0:
+ result = result + string[i-1]
+ result = result + string[i]
+ i = i-2
+ return result
+
+def print_sota_img_directory_cmd(blobNumber):
+ nbBlobFound = 0
+ sota_final_print = ""
+ sota_final_print += "=================> SOTA information\n"
+ # Generate the image directory command that will be used to provison the device
+ valueToPrint = ".\\DK6Programmer.exe -V5 -s <COM_PORT> -P 1000000 -w PSECT:64@0x160="
+ for i in range(1,9):
+ bootable = "00"
+ if i==1:
+ bootable = "01"
+ position_in_flash = get_symbol_value(elf_file_name, "m_blob_position"+str(i))
+ position_in_flash = '%0*X' % (2,position_in_flash)
+ blobTargetAddr = get_symbol_value(elf_file_name, "m_blob"+str(i)+"_start")
+ blobTargetAddr = '%0*X' % (8,blobTargetAddr)
+ blobStatedSize = get_symbol_value(elf_file_name, "m_blob"+str(i)+"_size")
+ if position_in_flash != "00" and blobStatedSize != 0:
+ nbBlobFound=nbBlobFound+1
+ sota_final_print += "Position in flash = "+ position_in_flash+" - targetAddr = 0x" +blobTargetAddr+ "\n"
+ blobTargetAddr = reverseString2by2(blobTargetAddr, len(blobTargetAddr))
+ blobNbPage = blobStatedSize/512
+ blobNbPage = '%0*X' % (4,blobNbPage)
+ blobNbPage = reverseString2by2(blobNbPage, len(blobNbPage))
+ if blobStatedSize != 0:
+ valueToPrint = valueToPrint + blobTargetAddr + blobNbPage + bootable + position_in_flash
+ else:
+ valueToPrint = valueToPrint + "0000000000000000"
+ sota_final_print += "=====> Image directory command"
+ sota_final_print += valueToPrint
+ sota_final_print += "=================> (end) SOTA information"
+ if nbBlobFound == blobNumber:
+ print sota_final_print
+
+#
+# JN518x ES1 version
+######################
+if JN518x_ES1 == 1: # deprecated
+
+ BOOT_BLOCK_MARKER = 0xBB0110BB
+
+ header_struct = struct.Struct('<7LLLLL')
+ boot_block_struct = struct.Struct('<6LQ')
+
+ sections = parse_sections(args.in_file)
+
+ last_section = None
+
+ for name, section in sections.iteritems():
+ if 'LOAD' in section.flags:
+ if last_section is None or section.lma > last_section.lma:
+ if section.size > 0:
+ last_section = section
+
+ if args.appcore_image is True:
+ image_size = last_section.lma + last_section.size - args.target_appcore_addr
+ else:
+ image_size = last_section.lma + last_section.size
+
+ dump_section = subprocess.check_output(['arm-none-eabi-objcopy', '--dump-section', '%s=data.bin' % last_section.name, args.in_file])
+
+ if args.appcore_image is True:
+ boot_block = boot_block_struct.pack(BOOT_BLOCK_MARKER, 1, args.target_appcore_addr, image_size + boot_block_struct.size, 0, 0, 0)
+ else:
+ boot_block = boot_block_struct.pack(BOOT_BLOCK_MARKER, 0, 0, image_size + boot_block_struct.size, 0, 0, 0)
+
+ with open('data.bin', 'ab') as out_file:
+ out_file.write(boot_block)
+
+ update_section = subprocess.check_output(['arm-none-eabi-objcopy', '--update-section', '%s=data.bin' % last_section.name, args.in_file, args.out_file])
+
+ first_section = None
+
+ for name, section in sections.iteritems():
+ if 'LOAD' in section.flags:
+ if first_section is None or section.lma < first_section.lma:
+ first_section = section
+
+ with open(args.out_file, 'r+b') as elf_file:
+ elf_file.seek(first_section.offset)
+ vectors = elf_file.read(header_struct.size)
+
+ fields = list(header_struct.unpack(vectors))
+
+ vectsum = 0
+
+ for x in range(7):
+ vectsum += fields[x]
+
+ fields[7] = (~vectsum & 0xFFFFFFFF) + 1
+ if args.appcore_image is True:
+ fields[9] = 0x02794498
+ else:
+ fields[9] = 0x98447902
+ #fields[9] = 0x98447902
+ fields[10] = image_size
+
+ print "Writing checksum {:08x} to file {:s}".format(vectsum, args.out_file)
+
+ elf_file.seek(first_section.offset)
+ elf_file.write(header_struct.pack(*fields))
+
+#
+# JN518x ES2 version
+######################
+else:
+ is_signature = False
+ error = 0
+ if args.signature_path is not None:
+ sign_dir_path = os.path.join(os.path.dirname(__file__), args.signature_path)
+ priv_key_file_path = os.path.join(sign_dir_path, 'priv_key.pem')
+ cert_file_path = os.path.join(sign_dir_path, 'cert.bin')
+ else:
+ sign_dir_path = os.path.join(os.path.dirname(__file__), '')
+ priv_key_file_path = os.path.join(sign_dir_path, 'testkey_es2.pem')
+ cert_file_path = os.path.join(sign_dir_path, 'certif_es2')
+
+ if args.key is True:
+ key_file_path = priv_key_file_path
+ if verbose:
+ print "key path is " + key_file_path
+ if (os.path.isfile(key_file_path)):
+ key_file=open(key_file_path, 'r')
+ key = RSA.importKey(key_file.read(), args.password)
+ print "Private RSA key processing..."
+ is_signature = True
+
+ compatibility_struct = struct.Struct('<2L')
+ compatibility_len_struct = struct.Struct('<L')
+ if args.compatibility_list is not None:
+ print "Compatibility list:"
+ if verbose:
+ print " {}".format(args.compatibility_list)
+ compatibility_list = [map(auto_int, compatibility_item.split(",")) for compatibility_item in args.compatibility_list.split(";")]
+ print " Length: {}".format(len(compatibility_list))
+ for i in range(len(compatibility_list)):
+ item = compatibility_list[i]
+ for j in range(len(item)):
+ if j ==1:
+ blobIdCompatibilityList = " Blob ID 0x=" + '%0*X' % (8,item[j-1])
+ print "Blob ID =0x"+'%0*X' % (4,item[j-1]) +" - version =0x"+'%0*X' % (8,item[j])
+ compatibility_len = len(compatibility_list) * compatibility_struct.size + compatibility_len_struct.size
+ if verbose:
+ print " {}".format(compatibility_len)
+ else:
+ compatibility_list = []
+ compatibility_len = 0
+ print "No compatibility list"
+
+ # make sure that the compatibility list is added and equals to nb_blob - 1
+ if args.sota_number_of_blob is not None and (compatibility_len/compatibility_struct.size) != args.sota_number_of_blob-1:
+ print "!!! Error the compatibility list length must be = to the number of blobs -1 : "+str(compatibility_len/compatibility_struct.size)+"(len) != "+ str(args.sota_number_of_blob-1)
+ error = 1
+ #make sure that the blob ID is given
+ if args.sota_number_of_blob is not None and args.blob_id is None:
+ print "!!! Error the blob ID is missing"
+ error = 1
+
+ bin_output = subprocess.check_output(['arm-none-eabi-objcopy', '-O', 'binary', elf_file_name, bin_file_name])
+
+ with open(bin_file_name, 'rb') as in_file:
+ input_file = in_file.read()
+
+ BOOT_BLOCK_MARKER = 0xBB0110BB
+ IMAGE_HEADER_MARKER = 0x98447902
+ IMAGE_HEADER_APP_CORE = 0x02794498
+ IMAGE_HEADER_ESCORE = IMAGE_HEADER_MARKER
+ SSBL_OR_LEGACY_ADDRESS = 0x00000000
+ SSBL_STATED_SIZE = 0x2000
+ ZB_TARGET_ADDRESS = SSBL_STATED_SIZE * 2
+ ZB_STATED_SIZE = 0x4f000
+ BLE_TARGET_ADDRESS = ZB_TARGET_ADDRESS + ZB_STATED_SIZE
+ BLE_STATED_SIZE = 0x40000
+
+ header_struct = struct.Struct('<7LLLLL')
+ boot_block_struct = struct.Struct('<8L')
+
+ boot_block_marker = BOOT_BLOCK_MARKER
+ if args.image_identifier is not None:
+ image_iden = args.image_identifier
+ else:
+ image_iden = 0
+
+ if verbose:
+ print "Image Identifier is {:d}".format(image_iden)
+
+ #Default value initialization
+ image_addr = 0
+ stated_size = 0
+
+ #Default value for SSBL, ZigbeeFull and BleFull image id
+ if image_iden == 0:
+ image_addr = SSBL_OR_LEGACY_ADDRESS
+ stated_size = SSBL_STATED_SIZE
+ elif image_iden == 1:
+ image_addr = ZB_TARGET_ADDRESS
+ elif image_iden == 2:
+ image_addr = BLE_TARGET_ADDRESS
+
+ image_addr = get_symbol_value(elf_file_name, 'm_app_start')
+
+ stated_size = get_symbol_value(elf_file_name, 'm_app_size')
+
+ # In case of SOTA get the position in flash from the linker it should be the app_id
+ if args.sota_number_of_blob is not None:
+ if args.image_identifier is None:
+ image_iden = get_symbol_value(elf_file_name, '__blob_position__')
+ print "Blob position in flash = #"+str(image_iden)
+
+ img_header_marker = IMAGE_HEADER_MARKER + image_iden
+
+ # Overwrite defaults for image address, stated size and header marker (-t, -s, -a options)
+ if args.target_addr is not None:
+ image_addr = args.target_addr
+ if args.stated_size is not None:
+ stated_size = args.stated_size
+ if args.appcore_image is True:
+ img_header_marker = IMAGE_HEADER_APP_CORE
+
+ if verbose:
+ print "image_iden=%d image_addr=%x" % (image_iden, image_addr)
+ print "stated_size=%d" % (stated_size)
+ print "version=0x%0*X" % (8,args.version)
+ print "boot_block_marker=%x" % (boot_block_marker)
+
+ sections = parse_sections(elf_file_name)
+
+ last_section = None
+ for name, section in sections.iteritems():
+ if 'LOAD' in section.flags:
+ if last_section is None or section.lma > last_section.lma:
+ if section.size > 0:
+ last_section = section
+
+ # IAR toolchain uses odd section names that contain spaces
+ # the regexp now may now return trailing spaces too, need to strip them
+ last_section_name = last_section.name.rstrip()
+ # and add quotes around the section name
+ last_section_name = r"%s" % (last_section_name)
+
+ boot_block_offset = last_section.lma + last_section.size + compatibility_len - image_addr
+
+ # Correction for image size not being multiple of 4 (IAR)
+ padding_len = ((4 - (boot_block_offset%4)) & 3)
+ padding_bytes = bytearray(padding_len)
+ boot_block_offset = boot_block_offset + padding_len
+
+ print "boot block offset =%x" % (boot_block_offset)
+ if verbose:
+ print "Last Section LMA={:08x} Size={:08x}".format(last_section.lma, last_section.size)
+ print "ImageAddress={:08x}".format(image_addr)
+
+ first_section = None
+
+ for name, section in sections.iteritems():
+ # print "Section: {:s} {:s} {:x} {:x}".format(name, section.flags, section.lma, section.size)
+ if 'LOAD' in section.flags:
+ if first_section is None or section.lma < first_section.lma:
+ first_section = section
+
+ header=""
+ with open(args.out_file, 'r+b') as elf_file:
+ elf_file.seek(first_section.offset)
+ vectors = elf_file.read(header_struct.size)
+
+ fields = list(header_struct.unpack(vectors))
+
+ vectsum = 0
+ for x in range(7):
+ vectsum += fields[x]
+
+ fields[7] = (~vectsum & 0xFFFFFFFF) + 1
+ fields[8] = img_header_marker
+ fields[9] = boot_block_offset
+
+ #Compute crc
+ head_struct = struct.Struct('<10L')
+ try:
+ if verbose:
+ for i in range(10):
+ print "Header[{:d}]= {:08x}".format(i, fields[i])
+ values = head_struct.pack(fields[0],
+ fields[1],
+ fields[2],
+ fields[3],
+ fields[4],
+ fields[5],
+ fields[6],
+ fields[7],
+ fields[8],
+ fields[9])
+ fields[10] = binascii.crc32(values) & 0xFFFFFFFF
+ except:
+ error = 1
+
+ print "Writing checksum {:08x} to file {:s}".format(vectsum, args.out_file)
+ print "Writing CRC32 of header {:08x} to file {:s}".format(fields[10], args.out_file)
+
+
+ elf_file.seek(first_section.offset)
+ header = header_struct.pack(*fields);
+ elf_file.write(header)
+
+ dump_section = subprocess.check_output(['arm-none-eabi-objcopy',
+ '--dump-section',
+ '%s=data.bin' % last_section_name,
+ args.out_file])
+
+ certificate = ""
+ certificate_offset = 0
+ signature = ""
+ compatibility = ""
+ compatibility_offset = 0
+
+ if args.compatibility_list is not None:
+ compatibility_offset = last_section.lma + last_section.size - image_addr
+ compatibility = compatibility_len_struct.pack(len(compatibility_list)) + ''.join([compatibility_struct.pack(*compatibility_item) for compatibility_item in compatibility_list])
+ print "Compatibility processing..."
+
+ if (args.certificate is True):
+ certificate_offset = boot_block_offset + boot_block_struct.size
+ certif_file_path = cert_file_path
+ if verbose:
+ print "Cert key path is " + cert_file_path
+ if (os.path.isfile(certif_file_path)):
+ certif_file=open(certif_file_path, 'rb')
+ certificate = certif_file.read()
+
+ print "Certificate processing..."
+ if len(certificate) != (40+256+256):
+ print "Certificate error"
+ error = 1
+
+ if verbose:
+ print "stated size is {:08x} ({})".format(stated_size,stated_size)
+
+ if args.appcore_image is True:
+ boot_block_id = 1
+ else:
+ boot_block_id = 0
+
+ if args.blob_id is not None:
+ boot_block_id = args.blob_id
+
+ boot_block = boot_block_struct.pack(boot_block_marker,
+ boot_block_id,
+ image_addr,
+ boot_block_offset + boot_block_struct.size + len(certificate), # padding already included in the boot_block_offset
+ stated_size,
+ certificate_offset,
+ compatibility_offset,
+ args.version)
+
+ if (is_signature == True):
+ # Sign the complete image
+ message = header + input_file[header_struct.size:] + boot_block + certificate
+ hash = SHA256.new(message)
+
+ out_file_path = os.path.join(os.path.dirname(__file__), 'dump_python.bin')
+ file_out=open(out_file_path, 'wb')
+ file_out.write(message)
+
+ signer = pkcs1_15.new(key)
+ signature = signer.sign(hash)
+
+ print "Signature processing..."
+
+ with open('data.bin', 'ab') as out_file:
+ out_file.write(compatibility+padding_bytes+boot_block+certificate+signature)
+ if verbose:
+ print "Updating last section " + last_section.name
+
+ update_section = subprocess.check_output(['arm-none-eabi-objcopy',
+ '--update-section',
+ '%s=data.bin' % last_section_name,
+ elf_file_name,
+ args.out_file])
+
+
+ if (is_signature == True):
+ file_out.close()
+
+ bin_output = subprocess.check_output(['arm-none-eabi-objcopy',
+ '-O',
+ 'binary',
+ elf_file_name,
+ bin_file_name])
+
+ print "Binary size is {:08x} ({})".format(os.stat(bin_file_name).st_size,os.stat(bin_file_name).st_size)
+
+ if args.sota_number_of_blob is not None:
+ print_sota_img_directory_cmd(args.sota_number_of_blob)
+
+ if os.stat(bin_file_name).st_size > stated_size:
+ print "Error: Binary file size ({:08x}) must be less or equal to stated size {:08x}".format(os.stat(bin_file_name).st_size, stated_size)
+ error = 1
+
+ if error != 0:
+ os.remove(elf_file_name)
+ os.remove(out_file_path)
+
+ os.remove(bin_file_name)
diff --git a/third_party/nxp/JN5189/ImageSigning/sign_images.sh b/third_party/nxp/JN5189DK6/tools/imagetool/sign_images.sh
similarity index 96%
rename from third_party/nxp/JN5189/ImageSigning/sign_images.sh
rename to third_party/nxp/JN5189DK6/tools/imagetool/sign_images.sh
index 065e19e..5e0105a 100755
--- a/third_party/nxp/JN5189/ImageSigning/sign_images.sh
+++ b/third_party/nxp/JN5189DK6/tools/imagetool/sign_images.sh
@@ -40,7 +40,7 @@
is_python_package_installed "pycryptodome"
CURR_DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )"
-SIGNING_TOOL=$CURR_DIR/jn518x_image_tool.py
+SIGNING_TOOL=$CURR_DIR/dk6_image_tool.py
MIME_PATTERN="application/x-executable"
if [ "$#" -eq 1 ]; then
diff --git a/third_party/nxp/K32W061DK6/CMSIS/Include/arm_common_tables.h b/third_party/nxp/K32W061DK6/CMSIS/Include/arm_common_tables.h
new file mode 100755
index 0000000..8742a56
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/CMSIS/Include/arm_common_tables.h
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. October 2015
+* $Revision: V.1.4.5 a
+*
+* Project: CMSIS DSP Library
+* Title: arm_common_tables.h
+*
+* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+/* extern const q31_t realCoefAQ31[1024]; */
+/* extern const q31_t realCoefBQ31[1024]; */
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /* ARM_COMMON_TABLES_H */
diff --git a/third_party/nxp/K32W061DK6/CMSIS/Include/arm_const_structs.h b/third_party/nxp/K32W061DK6/CMSIS/Include/arm_const_structs.h
new file mode 100755
index 0000000..726d06e
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/CMSIS/Include/arm_const_structs.h
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_const_structs.h
+*
+* Description: This file has constant structs that are initialized for
+* user convenience. For example, some can be given as
+* arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/third_party/nxp/K32W061DK6/CMSIS/Include/arm_math.h b/third_party/nxp/K32W061DK6/CMSIS/Include/arm_math.h
new file mode 100755
index 0000000..d33f8a9
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/CMSIS/Include/arm_math.h
@@ -0,0 +1,7154 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+*
+* $Date: 20. October 2015
+* $Revision: V1.4.5 b
+*
+* Project: CMSIS DSP Library
+* Title: arm_math.h
+*
+* Description: Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+ \mainpage CMSIS DSP Software Library
+ *
+ * Introduction
+ * ------------
+ *
+ * This user manual describes the CMSIS DSP software library,
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.
+ *
+ * The library is divided into a number of functions each covering a specific category:
+ * - Basic math functions
+ * - Fast math functions
+ * - Complex math functions
+ * - Filters
+ * - Matrix functions
+ * - Transforms
+ * - Motor control functions
+ * - Statistical functions
+ * - Support functions
+ * - Interpolation functions
+ *
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+ * 32-bit integer and 32-bit floating-point values.
+ *
+ * Using the Library
+ * ------------
+ *
+ * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+ * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)
+ * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)
+ * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+ * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+ * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+ * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+ * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)
+ * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)
+ *
+ * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+ * public header file <code> arm_math.h</code> for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+ * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
+ * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+ *
+ * Examples
+ * --------
+ *
+ * The library ships with a number of examples which demonstrate how to use the library functions.
+ *
+ * Toolchain Support
+ * ------------
+ *
+ * The library has been developed and tested with MDK-ARM version 5.14.0.0
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+ *
+ * Building the Library
+ * ------------
+ *
+ * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+ * - arm_cortexM_math.uvprojx
+ *
+ *
+ * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+ *
+ * Pre-processor Macros
+ * ------------
+ *
+ * Each library project have differant pre-processor macros.
+ *
+ * - UNALIGNED_SUPPORT_DISABLE:
+ *
+ * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+ *
+ * - ARM_MATH_BIG_ENDIAN:
+ *
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+ *
+ * - ARM_MATH_MATRIX_CHECK:
+ *
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+ *
+ * - ARM_MATH_ROUNDING:
+ *
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions
+ *
+ * - ARM_MATH_CMx:
+ *
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+ * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+ * ARM_MATH_CM7 for building the library on cortex-M7.
+ *
+ * - __FPU_PRESENT:
+ *
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+ *
+ * <hr>
+ * CMSIS-DSP in ARM::CMSIS Pack
+ * -----------------------------
+ *
+ * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+ * |File/Folder |Content |
+ * |------------------------------|------------------------------------------------------------------------|
+ * |\b CMSIS\\Documentation\\DSP | This documentation |
+ * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |
+ * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |
+ * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |
+ *
+ * <hr>
+ * Revision History of CMSIS-DSP
+ * ------------
+ * Please refer to \ref ChangeLog_pg.
+ *
+ * Copyright Notice
+ * ------------
+ *
+ * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+ */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures. For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ * typedef struct
+ * {
+ * uint16_t numRows; // number of rows of the matrix.
+ * uint16_t numCols; // number of columns of the matrix.
+ * float32_t *pData; // points to the data of the matrix.
+ * } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data. The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order. That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ * pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure. For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ * <pre>
+ * ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ * ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ * ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings. By default this macro is defined
+ * and size checking is enabled. By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster. With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+/* ignore some GCC warnings */
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+ #include "core_cm7.h"
+#elif defined (ARM_MATH_CM4)
+ #include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+ #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+ #include "core_cm0.h"
+ #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+ #include "core_cm0plus.h"
+ #define ARM_MATH_CM0_FAMILY
+#else
+ #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"
+#endif
+
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+ /**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31 (0x100)
+#define DELTA_Q15 0x5
+#define INDEX_MASK 0x0000003F
+#ifndef PI
+#define PI 3.14159265358979f
+#endif
+
+ /**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define FAST_MATH_TABLE_SIZE 512
+#define FAST_MATH_Q31_SHIFT (32 - 10)
+#define FAST_MATH_Q15_SHIFT (16 - 10)
+#define CONTROLLER_Q31_SHIFT (32 - 9)
+#define TABLE_SIZE 256
+#define TABLE_SPACING_Q31 0x400000
+#define TABLE_SPACING_Q15 0x80
+
+ /**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+ /* 1.31(q31) Fixed value of 2/360 */
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+ /**
+ * @brief Macro for Unaligned Support
+ */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+ #define ALIGN4
+#else
+ #if defined (__GNUC__)
+ #define ALIGN4 __attribute__((aligned(4)))
+ #else
+ #define ALIGN4 __align(4)
+ #endif
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /**
+ * @brief Error status returned by some functions in the library.
+ */
+
+ typedef enum
+ {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+ } arm_status;
+
+ /**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+ typedef int8_t q7_t;
+
+ /**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+ typedef int16_t q15_t;
+
+ /**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+ typedef int32_t q31_t;
+
+ /**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+ typedef int64_t q63_t;
+
+ /**
+ * @brief 32-bit floating-point type definition.
+ */
+ typedef float float32_t;
+
+ /**
+ * @brief 64-bit floating-point type definition.
+ */
+ typedef double float64_t;
+
+ /**
+ * @brief definition to read/write two 16 bit values.
+ */
+#if defined __CC_ARM
+ #define __SIMD32_TYPE int32_t __packed
+ #define CMSIS_UNUSED __attribute__((unused))
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+
+#elif defined __GNUC__
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+
+#elif defined __ICCARM__
+ #define __SIMD32_TYPE int32_t __packed
+ #define CMSIS_UNUSED
+
+#elif defined __CSMC__
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED
+
+#elif defined __TASKING__
+ #define __SIMD32_TYPE __unaligned int32_t
+ #define CMSIS_UNUSED
+
+#else
+ #error Unknown compiler
+#endif
+
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))
+#define __SIMD64(addr) (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+ /**
+ * @brief definition to pack two 16 bit values.
+ */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
+
+#endif
+
+
+ /**
+ * @brief definition to pack four 8 bit values.
+ */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+
+#endif
+
+
+ /**
+ * @brief Clips Q63 to Q31 values.
+ */
+ static __INLINE q31_t clip_q63_to_q31(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+ }
+
+ /**
+ * @brief Clips Q63 to Q15 values.
+ */
+ static __INLINE q15_t clip_q63_to_q15(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+ }
+
+ /**
+ * @brief Clips Q31 to Q7 values.
+ */
+ static __INLINE q7_t clip_q31_to_q7(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+ }
+
+ /**
+ * @brief Clips Q31 to Q15 values.
+ */
+ static __INLINE q15_t clip_q31_to_q15(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+ }
+
+ /**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+
+ static __INLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+ {
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y)));
+ }
+
+/*
+ #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM )
+ #define __CLZ __clz
+ #endif
+ */
+/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) )
+ static __INLINE uint32_t __CLZ(
+ q31_t data);
+
+ static __INLINE uint32_t __CLZ(
+ q31_t data)
+ {
+ uint32_t count = 0;
+ uint32_t mask = 0x80000000;
+
+ while((data & mask) == 0)
+ {
+ count += 1u;
+ mask = mask >> 1u;
+ }
+
+ return (count);
+ }
+#endif
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+
+ static __INLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t * dst,
+ q31_t * pRecipTable)
+ {
+ q31_t out;
+ uint32_t tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if(in > 0)
+ {
+ signBits = ((uint32_t) (__CLZ( in) - 1));
+ }
+ else
+ {
+ signBits = ((uint32_t) (__CLZ(-in) - 1));
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 24);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0u; i < 2u; i++)
+ {
+ tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+ tempVal = 0x7FFFFFFFu - tempVal;
+ /* 1.31 with exp 1 */
+ /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+ out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1u);
+ }
+
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+ static __INLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t * dst,
+ q15_t * pRecipTable)
+ {
+ q15_t out = 0;
+ uint32_t tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if(in > 0)
+ {
+ signBits = ((uint32_t)(__CLZ( in) - 17));
+ }
+ else
+ {
+ signBits = ((uint32_t)(__CLZ(-in) - 17));
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 8);
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0u; i < 2u; i++)
+ {
+ tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFFu - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+ }
+
+
+ /*
+ * @brief C custom defined intrinisic function for only M0 processors
+ */
+#if defined(ARM_MATH_CM0_FAMILY)
+ static __INLINE q31_t __SSAT(
+ q31_t x,
+ uint32_t y)
+ {
+ int32_t posMax, negMin;
+ uint32_t i;
+
+ posMax = 1;
+ for (i = 0; i < (y - 1); i++)
+ {
+ posMax = posMax * 2;
+ }
+
+ if(x > 0)
+ {
+ posMax = (posMax - 1);
+
+ if(x > posMax)
+ {
+ x = posMax;
+ }
+ }
+ else
+ {
+ negMin = -posMax;
+
+ if(x < negMin)
+ {
+ x = negMin;
+ }
+ }
+ return (x);
+ }
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+ /*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+ /*
+ * @brief C custom defined QADD8 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QADD8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB8 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QSUB8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */
+ q31_t r = 0, s = 0;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHADD16 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SHADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB16 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSUB16 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SHSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QASX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHASX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SHASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSAX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSAX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SHSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSDX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMUSDX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+ /*
+ * @brief C custom defined SMUADX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMUADX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined QADD for M3 and M0 processors
+ */
+ static __INLINE int32_t __QADD(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB for M3 and M0 processors
+ */
+ static __INLINE int32_t __QSUB(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined SMLAD for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMLAD(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLADX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMLADX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLSDX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMLSDX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALD for M3 and M0 processors
+ */
+ static __INLINE uint64_t __SMLALD(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALDX for M3 and M0 processors
+ */
+ static __INLINE uint64_t __SMLALDX(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUAD for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMUAD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSD for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMUSD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SXTB16 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SXTB16(
+ uint32_t x)
+ {
+ return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+ ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));
+ }
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+ /**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q7;
+
+ /**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] S points to an instance of the Q7 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ */
+ void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] S points to an instance of the Q15 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+ * <code>numTaps</code> is not a supported value.
+ */
+ arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] S points to an instance of the Q31 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] S points to an instance of the floating-point FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_f32(
+ const arm_fir_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q15;
+
+ /**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q31;
+
+ /**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_casd_df1_inst_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f32;
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float64_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f64;
+
+ /**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q31;
+
+
+ /**
+ * @brief Floating-point matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Q31, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+
+ /**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+
+ /**
+ * @brief Q31 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix scaling.
+ * @param[in] pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData);
+
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData);
+
+
+ /**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+ typedef struct
+ {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+ q15_t A1;
+ q15_t A2;
+#else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+ typedef struct
+ {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+ typedef struct
+ {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_f32;
+
+
+
+ /**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ */
+ void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S);
+
+
+ /**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ */
+
+ void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S);
+
+
+ /**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the q15 PID Control structure
+ */
+ void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S);
+
+
+ /**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+ typedef struct
+ {
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
+ float32_t *pYData; /**< pointer to the table of Y values */
+ } arm_linear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q7;
+
+
+ /**
+ * @brief Q7 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+ void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q15_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+ const arm_cfft_instance_q15 * S,
+ q15_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+ const arm_cfft_instance_q31 * S,
+ q31_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_f32;
+
+ void arm_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q15;
+
+ arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+ /**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q31;
+
+ arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_f32;
+
+ arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+typedef struct
+ {
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
+ } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+ arm_rfft_fast_instance_f32 * S,
+ uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+ arm_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut,
+ uint8_t ifftFlag);
+
+ /**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ float32_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+ */
+ arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+
+ /**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ q31_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q31;
+
+
+ /**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q31 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ q15_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q15 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+
+ /**
+ * @brief Floating-point vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_f32(
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q7(
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q15(
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q31(
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+
+ /**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+
+ /**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q7(
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q15(
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q31(
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_f32(
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q7(
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q15(
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q31(
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR decimator.
+ * @param[in,out] S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+ arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+ arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q31(
+ arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+ arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+ } arm_fir_interpolate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+ arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+ arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+ arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+ } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+ /**
+ * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f64;
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_stereo_df2T_f32(
+ const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f64(
+ const arm_biquad_cascade_df2T_instance_f64 * S,
+ float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_stereo_df2T_init_f32(
+ arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f64(
+ arm_biquad_cascade_df2T_instance_f64 * S,
+ uint8_t numStages,
+ float64_t * pCoeffs,
+ float64_t * pState);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ */
+ void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+ } arm_lms_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q15;
+
+
+ /**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+ void arm_correlate_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+ void arm_correlate_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+ void arm_correlate_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+ void arm_correlate_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_correlate_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q7;
+
+
+ /**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cos output.
+ */
+ void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCosVal);
+
+
+ /**
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cosine output.
+ */
+ void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal);
+
+
+ /**
+ * @brief Floating-point complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the PID control data structure. <code>in</code>
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ * <pre>
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ * A0 = Kp + Ki + Kd
+ * A1 = (-Kp ) - (2 * Kd )
+ * A2 = Kd </pre>
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ */
+ static __INLINE float32_t arm_pid_f32(
+ arm_pid_instance_f32 * S,
+ float32_t in)
+ {
+ float32_t out;
+
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = (S->A0 * in) +
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @brief Process function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+ static __INLINE q31_t arm_pid_q31(
+ arm_pid_instance_q31 * S,
+ q31_t in)
+ {
+ q63_t acc;
+ q31_t out;
+
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31u);
+
+ /* out += y[n-1] */
+ out += S->state[2];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+
+ /**
+ * @brief Process function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+ static __INLINE q15_t arm_pid_q15(
+ arm_pid_instance_q15 * S,
+ q15_t in)
+ {
+ q63_t acc;
+ q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+ __SIMD32_TYPE *vstate;
+
+ /* Implementation of PID controller */
+
+ /* acc = A0 * x[n] */
+ acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ vstate = __SIMD32_CONST(S->state);
+ acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);
+#else
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0) * in;
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0];
+ acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+
+ /* saturate the output */
+ out = (q15_t) (__SSAT((acc >> 15), 16));
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+ /**
+ * @} end of PID group
+ */
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32 * src,
+ arm_matrix_instance_f32 * dst);
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f64(
+ const arm_matrix_instance_f64 * src,
+ arm_matrix_instance_f64 * dst);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+ * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+ * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+ * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+ * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup clarke
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate <code>a</code>
+ * @param[in] Ib input three-phase coordinate <code>b</code>
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ */
+ static __INLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+ }
+
+
+ /**
+ * @brief Clarke transform for Q31 version
+ * @param[in] Ia input three-phase coordinate <code>a</code>
+ * @param[in] Ib input three-phase coordinate <code>b</code>
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+ static __INLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+ }
+
+ /**
+ * @} end of clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q31(
+ q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+ * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Clarke transform
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate <code>a</code>
+ * @param[out] pIb points to output three-phase coordinate <code>b</code>
+ */
+ static __INLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
+ {
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+ }
+
+
+ /**
+ * @brief Inverse Clarke transform for Q31 version
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate <code>a</code>
+ * @param[out] pIb points to output three-phase coordinate <code>b</code>
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+ static __INLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+ }
+
+ /**
+ * @} end of inv_clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q15(
+ q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+ * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+ static __INLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+ }
+
+
+ /**
+ * @brief Park transform for Q31 version
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+ static __INLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+ }
+
+ /**
+ * @} end of park group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q7_to_float(
+ q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+ * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Park transform
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ */
+ static __INLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+ }
+
+
+ /**
+ * @brief Inverse Park transform for Q31 version
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+ static __INLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+ }
+
+ /**
+ * @} end of Inverse park group
+ */
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_float(
+ q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ * <pre>
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ * where x0, x1 are nearest values of input x
+ * y0, y1 are nearest values to output y
+ * </pre>
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+ * <code>x</code> is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+ /**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+ static __INLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32 * S,
+ float32_t x)
+ {
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t *pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (int32_t) ((x - S->x1) / xSpacing);
+
+ if(i < 0)
+ {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ }
+ else if((uint32_t)i >= S->nValues)
+ {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues - 1];
+ }
+ else
+ {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i + 1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+ }
+
+ /* returns output value */
+ return (y);
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q31 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q31 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ static __INLINE q31_t arm_linear_interp_q31(
+ q31_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (q31_t)0xFFF00000) >> 20);
+
+ if(index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1u);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ static __INLINE q15_t arm_linear_interp_q15(
+ q15_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (int32_t)0xFFF00000) >> 20);
+
+ if(index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (q15_t) (y >> 20);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+ static __INLINE q7_t arm_linear_interp_q7(
+ q7_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ uint32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ if (x < 0)
+ {
+ return (pYData[0]);
+ }
+ index = (x >> 20) & 0xfff;
+
+ if(index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (q7_t) (y >> 20);
+ }
+ }
+
+ /**
+ * @} end of LinearInterpolate group
+ */
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+ float32_t arm_sin_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q31_t arm_sin_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q15_t arm_sin_q15(
+ q15_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+ float32_t arm_cos_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q31_t arm_cos_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q15_t arm_cos_q15(
+ q15_t x);
+
+
+ /**
+ * @ingroup groupFastMath
+ */
+
+
+ /**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ * <pre>
+ * x1 = x0 - f(x0)/f'(x0)
+ * </pre>
+ * where <code>x1</code> is the current estimate,
+ * <code>x0</code> is the previous estimate, and
+ * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+ * For the square root function, the algorithm reduces to:
+ * <pre>
+ * x0 = in/2 [initial guess]
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]
+ * </pre>
+ */
+
+
+ /**
+ * @addtogroup SQRT
+ * @{
+ */
+
+ /**
+ * @brief Floating-point square root function.
+ * @param[in] in input value.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+ static __INLINE arm_status arm_sqrt_f32(
+ float32_t in,
+ float32_t * pOut)
+ {
+ if(in >= 0.0f)
+ {
+
+#if (__FPU_USED == 1) && defined ( __CC_ARM )
+ *pOut = __sqrtf(in);
+#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+ *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined(__GNUC__)
+ *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
+ __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+#else
+ *pOut = sqrtf(in);
+#endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else
+ {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+ }
+
+
+ /**
+ * @brief Q31 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut);
+
+
+ /**
+ * @brief Q15 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut);
+
+ /**
+ * @} end of SQRT group
+ */
+
+
+ /**
+ * @brief floating-point Circular write function.
+ */
+ static __INLINE void arm_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+
+ /**
+ * @brief floating-point Circular Read function.
+ */
+ static __INLINE void arm_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (int32_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular write function.
+ */
+ static __INLINE void arm_circularWrite_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q15_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular Read function.
+ */
+ static __INLINE void arm_circularRead_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q15_t * dst,
+ q15_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q15_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular write function.
+ */
+ static __INLINE void arm_circularWrite_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q7_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular Read function.
+ */
+ static __INLINE void arm_circularRead_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q7_t * dst,
+ q7_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q7_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Floating-point complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+
+ /**
+ * @brief Q31 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+
+ /**
+ * @brief Floating-point complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+
+ /**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q15(
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q31(
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_f32(
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
+
+
+ /**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[in] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q31(
+ float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q15(
+ float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q7(
+ float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q15(
+ q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q7(
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_float(
+ q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q31(
+ q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q7(
+ q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * <b>Algorithm</b>
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ * <pre>
+ * typedef struct
+ * {
+ * uint16_t numRows;
+ * uint16_t numCols;
+ * float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ * </pre>
+ *
+ * \par
+ * where <code>numRows</code> specifies the number of rows in the table;
+ * <code>numCols</code> specifies the number of columns in the table;
+ * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+ * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+ *
+ * \par
+ * Let <code>(x, y)</code> specify the desired interpolation point. Then define:
+ * <pre>
+ * XF = floor(x)
+ * YF = floor(y)
+ * </pre>
+ * \par
+ * The interpolated output point is computed as:
+ * <pre>
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ * </pre>
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+ /**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+
+ /**
+ *
+ * @brief Floating-point bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate.
+ * @param[in] Y interpolation coordinate.
+ * @return out interpolated value.
+ */
+ static __INLINE float32_t arm_bilinear_interp_f32(
+ const arm_bilinear_interp_instance_f32 * S,
+ float32_t X,
+ float32_t Y)
+ {
+ float32_t out;
+ float32_t f00, f01, f10, f11;
+ float32_t *pData = S->pData;
+ int32_t xIndex, yIndex, index;
+ float32_t xdiff, ydiff;
+ float32_t b1, b2, b3, b4;
+
+ xIndex = (int32_t) X;
+ yIndex = (int32_t) Y;
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* Calculation of index for two nearest points in X-direction */
+ index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+ /* Read two nearest points in X-direction */
+ f00 = pData[index];
+ f01 = pData[index + 1];
+
+ /* Calculation of index for two nearest points in Y-direction */
+ index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+ /* Read two nearest points in Y-direction */
+ f10 = pData[index];
+ f11 = pData[index + 1];
+
+ /* Calculation of intermediate values */
+ b1 = f00;
+ b2 = f01 - f00;
+ b3 = f10 - f00;
+ b4 = f00 - f01 - f10 + f11;
+
+ /* Calculation of fractional part in X */
+ xdiff = X - xIndex;
+
+ /* Calculation of fractional part in Y */
+ ydiff = Y - yIndex;
+
+ /* Calculation of bi-linear interpolated output */
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+ /* return to application */
+ return (out);
+ }
+
+
+ /**
+ *
+ * @brief Q31 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ static __INLINE q31_t arm_bilinear_interp_q31(
+ arm_bilinear_interp_instance_q31 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q31_t out; /* Temporary output */
+ q31_t acc = 0; /* output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q31_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q31_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* shift left xfract by 11 to keep 1.31 format */
+ xfract = (X & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + (int32_t)nCols * (cI) ];
+ x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* shift left yfract by 11 to keep 1.31 format */
+ yfract = (Y & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];
+ y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* Convert acc to 1.31(q31) format */
+ return ((q31_t)(acc << 2));
+ }
+
+
+ /**
+ * @brief Q15 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ static __INLINE q15_t arm_bilinear_interp_q15(
+ arm_bilinear_interp_instance_q15 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q15_t x1, x2, y1, y2; /* Nearest output values */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ int32_t rI, cI; /* Row and column indices */
+ q15_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+ acc = ((q63_t) out * (0xFFFFF - yfract));
+
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+ acc += ((q63_t) out * (xfract));
+
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* acc is in 13.51 format and down shift acc by 36 times */
+ /* Convert out to 1.15 format */
+ return ((q15_t)(acc >> 36));
+ }
+
+
+ /**
+ * @brief Q7 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ static __INLINE q7_t arm_bilinear_interp_q7(
+ arm_bilinear_interp_instance_q7 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q7_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q7_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+ out = ((x1 * (0xFFFFF - xfract)));
+ acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
+ out = ((x2 * (0xFFFFF - yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y1 * (0xFFFFF - xfract)));
+ acc += (((q63_t) out * (yfract)));
+
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y2 * (yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+ return ((q7_t)(acc >> 40));
+ }
+
+ /**
+ * @} end of BilinearInterpolate group
+ */
+
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+ a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+ a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+ a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM )
+ /* Enter low optimization region - place directly above function definition */
+ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("push") \
+ _Pragma ("O1")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+ #define LOW_OPTIMIZATION_EXIT \
+ _Pragma ("pop")
+ #else
+ #define LOW_OPTIMIZATION_EXIT
+ #endif
+
+ /* Enter low optimization region - place directly above function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+ #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__)
+ /* Enter low optimization region - place directly above function definition */
+ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define LOW_OPTIMIZATION_EXIT
+
+ /* Enter low optimization region - place directly above function definition */
+ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__CSMC__)
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__TASKING__)
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/third_party/nxp/K32W061DK6/CMSIS/Include/cmsis_armcc.h b/third_party/nxp/K32W061DK6/CMSIS/Include/cmsis_armcc.h
new file mode 100755
index 0000000..74c49c6
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/CMSIS/Include/cmsis_armcc.h
@@ -0,0 +1,734 @@
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+
+#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() do {\
+ __schedule_barrier();\
+ __isb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+ __schedule_barrier();\
+ __dsb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXB(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXH(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXW(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
+
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
+
+#endif /* (__CORTEX_M >= 0x04) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/third_party/nxp/K32W061DK6/CMSIS/Include/cmsis_armcc_V6.h b/third_party/nxp/K32W061DK6/CMSIS/Include/cmsis_armcc_V6.h
new file mode 100755
index 0000000..cd13240
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/CMSIS/Include/cmsis_armcc_V6.h
@@ -0,0 +1,1800 @@
+/**************************************************************************//**
+ * @file cmsis_armcc_V6.h
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_ARMCC_V6_H
+#define __CMSIS_ARMCC_V6_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get IPSR Register (non-secure)
+ \details Returns the content of the non-secure IPSR Register when in secure state.
+ \return IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get APSR Register (non-secure)
+ \details Returns the content of the non-secure APSR Register when in secure state.
+ \return APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get xPSR Register (non-secure)
+ \details Returns the content of the non-secure xPSR Register when in secure state.
+ \return xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp");
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp");
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Base Priority with condition (non_secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value)
+{
+ __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+
+#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */
+
+
+#if (__ARM_ARCH_8M__ == 1U)
+
+/**
+ \brief Get Process Stack Pointer Limit
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* (__ARM_ARCH_8M__ == 1U) */
+
+
+#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */
+
+/**
+ \brief Get FPSCR
+ \details eturns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#define __get_FPSCR __builtin_arm_get_fpscr
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ uint32_t result;
+
+ __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+#endif
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get FPSCR (non-secure)
+ \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state.
+ \return Floating Point Status/Control register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ uint32_t result;
+
+ __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+#endif
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#define __set_FPSCR __builtin_arm_set_fpscr
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+#endif
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set FPSCR (non-secure)
+ \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+#endif
+
+#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF);
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF);
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF);
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __builtin_bswap32
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+ /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+ int32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+ /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return(result);
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __builtin_clz
+
+
+#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+/*#define __SSAT __builtin_arm_ssat*/
+#define __SSAT(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+#if 0
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+#endif
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */
+
+
+#if (__ARM_ARCH_8M__ == 1U)
+
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* (__ARM_ARCH_8M__ == 1U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1U) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_V6_H */
diff --git a/third_party/nxp/K32W061DK6/CMSIS/Include/cmsis_gcc.h b/third_party/nxp/K32W061DK6/CMSIS/Include/cmsis_gcc.h
new file mode 100755
index 0000000..bb89fbb
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/CMSIS/Include/cmsis_gcc.h
@@ -0,0 +1,1373 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (__CORTEX_M >= 0x03U)
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03U) */
+
+
+#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ uint32_t result;
+
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (short)__builtin_bswap16(value);
+#else
+ int32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return(result);
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __builtin_clz
+
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x04) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* __CMSIS_GCC_H */
diff --git a/third_party/nxp/K32W061DK6/CMSIS/Include/core_cm0.h b/third_party/nxp/K32W061DK6/CMSIS/Include/core_cm0.h
new file mode 100755
index 0000000..711dad5
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/CMSIS/Include/core_cm0.h
@@ -0,0 +1,798 @@
+/**************************************************************************//**
+ * @file core_cm0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M0
+ @{
+ */
+
+/* CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0_REV
+ #define __CM0_REV 0x0000U
+ #warning "__CM0_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/third_party/nxp/K32W061DK6/CMSIS/Include/core_cm0plus.h b/third_party/nxp/K32W061DK6/CMSIS/Include/core_cm0plus.h
new file mode 100755
index 0000000..b04aa39
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/CMSIS/Include/core_cm0plus.h
@@ -0,0 +1,914 @@
+/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex-M0+
+ @{
+ */
+
+/* CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+ __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0PLUS_REV
+ #define __CM0PLUS_REV 0x0000U
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0+ header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/third_party/nxp/K32W061DK6/CMSIS/Include/core_cm3.h b/third_party/nxp/K32W061DK6/CMSIS/Include/core_cm3.h
new file mode 100755
index 0000000..b4ac4c7
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/CMSIS/Include/core_cm3.h
@@ -0,0 +1,1763 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M3
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03U) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200U
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201U) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U))
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in NVIC and returns the active bit.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/third_party/nxp/K32W061DK6/CMSIS/Include/core_cm4.h b/third_party/nxp/K32W061DK6/CMSIS/Include/core_cm4.h
new file mode 100755
index 0000000..dc840eb
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/CMSIS/Include/core_cm4.h
@@ -0,0 +1,1937 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M4
+ @{
+ */
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x04U) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000U
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1U)
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in NVIC and returns the active bit.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/third_party/nxp/K32W061DK6/CMSIS/Include/core_cm7.h b/third_party/nxp/K32W061DK6/CMSIS/Include/core_cm7.h
new file mode 100755
index 0000000..3b7530a
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/CMSIS/Include/core_cm7.h
@@ -0,0 +1,2512 @@
+/**************************************************************************//**
+ * @file core_cm7.h
+ * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M7
+ @{
+ */
+
+/* CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+ __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x07U) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM7_REV
+ #define __CM7_REV 0x0000U
+ #warning "__CM7_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ICACHE_PRESENT
+ #define __ICACHE_PRESENT 0U
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DCACHE_PRESENT
+ #define __DCACHE_PRESENT 0U
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DTCM_PRESENT
+ #define __DTCM_PRESENT 0U
+ #warning "__DTCM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[1U];
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED3[93U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED3[981U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1U)
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in NVIC and returns the active bit.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = SCB->MVFR0;
+ if ((mvfr0 & 0x00000FF0UL) == 0x220UL)
+ {
+ return 2UL; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & 0x00000FF0UL) == 0x020UL)
+ {
+ return 1UL; /* Single precision FPU */
+ }
+ else
+ {
+ return 0UL; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## Cache functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions
+ \brief Functions that configure Instruction and Data cache.
+ @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
+
+
+/**
+ \brief Enable I-Cache
+ \details Turns on I-Cache
+ */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+ #if (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable I-Cache
+ \details Turns off I-Cache
+ */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+ #if (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate I-Cache
+ \details Invalidates I-Cache
+ */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+ #if (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL;
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Enable D-Cache
+ \details Turns on D-Cache
+ */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways--);
+ } while(sets--);
+ __DSB();
+
+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable D-Cache
+ \details Turns off D-Cache
+ */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate D-Cache
+ \details Invalidates D-Cache
+ */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean D-Cache
+ \details Cleans D-Cache
+ */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+ ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean & Invalidate D-Cache
+ \details Cleans and Invalidates D-Cache
+ */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Invalidate by address
+ \details Invalidates D-Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t)addr;
+ int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCIMVAC = op_addr;
+ op_addr += linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean by address
+ \details Cleans D-Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if (__DCACHE_PRESENT == 1)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t) addr;
+ int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCCMVAC = op_addr;
+ op_addr += linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean and Invalidate by address
+ \details Cleans and invalidates D_Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t) addr;
+ int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCCIMVAC = op_addr;
+ op_addr += linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/third_party/nxp/K32W061DK6/CMSIS/Include/core_cmFunc.h b/third_party/nxp/K32W061DK6/CMSIS/Include/core_cmFunc.h
new file mode 100755
index 0000000..652a48a
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/CMSIS/Include/core_cmFunc.h
@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+ #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+ #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+ #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/third_party/nxp/K32W061DK6/CMSIS/Include/core_cmInstr.h b/third_party/nxp/K32W061DK6/CMSIS/Include/core_cmInstr.h
new file mode 100755
index 0000000..f474b0e
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/CMSIS/Include/core_cmInstr.h
@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+ #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+ #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+ #include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/third_party/nxp/K32W061DK6/CMSIS/Include/core_cmSimd.h b/third_party/nxp/K32W061DK6/CMSIS/Include/core_cmSimd.h
new file mode 100755
index 0000000..66bf5c2
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/CMSIS/Include/core_cmSimd.h
@@ -0,0 +1,96 @@
+/**************************************************************************//**
+ * @file core_cmSimd.h
+ * @brief CMSIS Cortex-M SIMD Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+ #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+ #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+ #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */
diff --git a/third_party/nxp/K32W061DK6/CMSIS/Include/core_sc000.h b/third_party/nxp/K32W061DK6/CMSIS/Include/core_sc000.h
new file mode 100755
index 0000000..514dbd8
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/CMSIS/Include/core_sc000.h
@@ -0,0 +1,926 @@
+/**************************************************************************//**
+ * @file core_sc000.h
+ * @brief CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup SC000
+ @{
+ */
+
+/* CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+ __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC (000U) /*!< Cortex secure core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __SC000_REV
+ #define __SC000_REV 0x0000U
+ #warning "__SC000_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ uint32_t RESERVED1[154U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the SC000 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of SC000 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/third_party/nxp/K32W061DK6/CMSIS/Include/core_sc300.h b/third_party/nxp/K32W061DK6/CMSIS/Include/core_sc300.h
new file mode 100755
index 0000000..8bd18aa
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/CMSIS/Include/core_sc300.h
@@ -0,0 +1,1745 @@
+/**************************************************************************//**
+ * @file core_sc300.h
+ * @brief CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup SC3000
+ @{
+ */
+
+/* CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+ __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC (300U) /*!< Cortex secure core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __SC300_REV
+ #define __SC300_REV 0x0000U
+ #warning "__SC300_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED1[129U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ uint32_t RESERVED1[1U];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in NVIC and returns the active bit.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/third_party/nxp/JN5189/dk6_jn5180/board.c b/third_party/nxp/K32W061DK6/boards/k32w061dk6/wireless_examples/openthread/enablement/board.c
similarity index 100%
copy from third_party/nxp/JN5189/dk6_jn5180/board.c
copy to third_party/nxp/K32W061DK6/boards/k32w061dk6/wireless_examples/openthread/enablement/board.c
diff --git a/third_party/nxp/JN5189/dk6_jn5180/board.h b/third_party/nxp/K32W061DK6/boards/k32w061dk6/wireless_examples/openthread/enablement/board.h
similarity index 100%
copy from third_party/nxp/JN5189/dk6_jn5180/board.h
copy to third_party/nxp/K32W061DK6/boards/k32w061dk6/wireless_examples/openthread/enablement/board.h
diff --git a/third_party/nxp/JN5189/dk6_jn5180/clock_config.c b/third_party/nxp/K32W061DK6/boards/k32w061dk6/wireless_examples/openthread/enablement/clock_config.c
similarity index 98%
copy from third_party/nxp/JN5189/dk6_jn5180/clock_config.c
copy to third_party/nxp/K32W061DK6/boards/k32w061dk6/wireless_examples/openthread/enablement/clock_config.c
index b9dca12..1a4ca32 100755
--- a/third_party/nxp/JN5189/dk6_jn5180/clock_config.c
+++ b/third_party/nxp/K32W061DK6/boards/k32w061dk6/wireless_examples/openthread/enablement/clock_config.c
@@ -8,8 +8,6 @@
#include "fsl_common.h"
#include "clock_config.h"
-#include "system_JN5189.h"
-
/*******************************************************************************
* Definitions
******************************************************************************/
diff --git a/third_party/nxp/JN5189/dk6_jn5180/clock_config.h b/third_party/nxp/K32W061DK6/boards/k32w061dk6/wireless_examples/openthread/enablement/clock_config.h
similarity index 100%
copy from third_party/nxp/JN5189/dk6_jn5180/clock_config.h
copy to third_party/nxp/K32W061DK6/boards/k32w061dk6/wireless_examples/openthread/enablement/clock_config.h
diff --git a/third_party/nxp/JN5189/dk6_jn5180/pin_mux.c b/third_party/nxp/K32W061DK6/boards/k32w061dk6/wireless_examples/openthread/enablement/pin_mux.c
similarity index 100%
copy from third_party/nxp/JN5189/dk6_jn5180/pin_mux.c
copy to third_party/nxp/K32W061DK6/boards/k32w061dk6/wireless_examples/openthread/enablement/pin_mux.c
diff --git a/third_party/nxp/JN5189/dk6_jn5180/pin_mux.h b/third_party/nxp/K32W061DK6/boards/k32w061dk6/wireless_examples/openthread/enablement/pin_mux.h
similarity index 100%
copy from third_party/nxp/JN5189/dk6_jn5180/pin_mux.h
copy to third_party/nxp/K32W061DK6/boards/k32w061dk6/wireless_examples/openthread/enablement/pin_mux.h
diff --git a/third_party/nxp/K32W061DK6/components/serial_manager/serial_manager.c b/third_party/nxp/K32W061DK6/components/serial_manager/serial_manager.c
new file mode 100755
index 0000000..42dc0a4
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/components/serial_manager/serial_manager.c
@@ -0,0 +1,1326 @@
+/*
+ * Copyright 2018-2019 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include <string.h>
+
+#include "serial_manager.h"
+#include "serial_port_internal.h"
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+#include "generic_list.h"
+
+/*
+ * The OSA_USED macro can only be defined when the OSA component is used.
+ * If the source code of the OSA component does not exist, the OSA_USED cannot be defined.
+ * OR, If OSA component is not added into project event the OSA source code exists, the OSA_USED
+ * also cannot be defined.
+ * The source code path of the OSA component is <MCUXpresso_SDK>/components/osa.
+ *
+ */
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+#include "common_task.h"
+#else
+#include "fsl_os_abstraction.h"
+#endif
+
+#endif
+
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#ifndef NDEBUG
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
+#undef assert
+#define assert(n)
+#endif
+#endif
+
+#define SERIAL_EVENT_DATA_RECEIVED (1U << 0)
+#define SERIAL_EVENT_DATA_SENT (1U << 1)
+
+#define SERIAL_MANAGER_WRITE_TAG 0xAABB5754U
+#define SERIAL_MANAGER_READ_TAG 0xBBAA5244U
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+typedef enum _serial_manager_transmission_mode
+{
+ kSerialManager_TransmissionBlocking = 0x0U, /*!< Blocking transmission*/
+ kSerialManager_TransmissionNonBlocking = 0x1U, /*!< None blocking transmission*/
+} serial_manager_transmission_mode_t;
+
+/* TX transfer structure */
+typedef struct _serial_manager_transfer
+{
+ uint8_t *buffer;
+ volatile uint32_t length;
+ volatile uint32_t soFar;
+ serial_manager_transmission_mode_t mode;
+ serial_manager_status_t status;
+} serial_manager_transfer_t;
+#endif
+
+/* write handle structure */
+typedef struct _serial_manager_send_handle
+{
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ list_element_t link; /*!< list element of the link */
+ serial_manager_transfer_t transfer;
+#endif
+ struct _serial_manager_handle *serialManagerHandle;
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ serial_manager_callback_t callback;
+ void *callbackParam;
+ uint32_t tag;
+#endif
+} serial_manager_write_handle_t;
+
+typedef serial_manager_write_handle_t serial_manager_read_handle_t;
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+/* receive state structure */
+typedef struct _serial_manager_read_ring_buffer
+{
+ uint8_t *ringBuffer;
+ uint32_t ringBufferSize;
+ volatile uint32_t ringHead;
+ volatile uint32_t ringTail;
+} serial_manager_read_ring_buffer_t;
+#endif
+
+#if defined(__CC_ARM)
+#pragma anon_unions
+#endif
+/* The serial manager handle structure */
+typedef struct _serial_manager_handle
+{
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ list_label_t runningWriteHandleHead; /*!< The queue of running write handle */
+ list_label_t completedWriteHandleHead; /*!< The queue of completed write handle */
+#endif
+ serial_manager_read_handle_t *volatile openedReadHandleHead;
+ volatile uint32_t openedWriteHandleCount;
+ union
+ {
+ uint8_t lowLevelhandleBuffer[1];
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ uint8_t uartHandleBuffer[SERIAL_PORT_UART_HANDLE_SIZE];
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ uint8_t usbcdcHandleBuffer[SERIAL_PORT_USB_CDC_HANDLE_SIZE];
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ uint8_t swoHandleBuffer[SERIAL_PORT_SWO_HANDLE_SIZE];
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ uint8_t usbcdcVirtualHandleBuffer[SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE];
+#endif
+ };
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ serial_manager_read_ring_buffer_t ringBuffer;
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+ common_task_message_t commontaskMsg;
+#else
+ uint8_t event[OSA_EVENT_HANDLE_SIZE]; /*!< Event instance */
+ uint8_t taskId[OSA_TASK_HANDLE_SIZE]; /*!< Task handle */
+#endif
+
+#endif
+
+#endif
+
+ serial_port_type_t type;
+} serial_manager_handle_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+static void SerialManager_Task(void *param);
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+
+#else
+ /*
+ * \brief Defines the serial manager task's stack
+ */
+OSA_TASK_DEFINE(SerialManager_Task, SERIAL_MANAGER_TASK_PRIORITY, 1, SERIAL_MANAGER_TASK_STACK_SIZE, false);
+#endif
+
+#endif
+
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+static void SerialManager_AddTail(list_label_t *queue, serial_manager_write_handle_t *node)
+{
+ (void)LIST_AddTail(queue, &node->link);
+}
+
+static void SerialManager_RemoveHead(list_label_t *queue)
+{
+ (void)LIST_RemoveHead(queue);
+}
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_t *handle)
+{
+ serial_manager_status_t status = kStatus_SerialManager_Error;
+ serial_manager_write_handle_t *writeHandle =
+ (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->runningWriteHandleHead);
+
+ if (writeHandle != NULL)
+ {
+ switch (handle->type)
+ {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ case kSerialPort_Uart:
+ status = Serial_UartWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ writeHandle->transfer.buffer, writeHandle->transfer.length);
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ case kSerialPort_UsbCdc:
+ status = Serial_UsbCdcWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ writeHandle->transfer.buffer, writeHandle->transfer.length);
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ case kSerialPort_Swo:
+ status = Serial_SwoWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ writeHandle->transfer.buffer, writeHandle->transfer.length);
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ case kSerialPort_UsbCdcVirtual:
+ status = Serial_UsbCdcVirtualWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ writeHandle->transfer.buffer, writeHandle->transfer.length);
+ break;
+#endif
+ default:
+ status = kStatus_SerialManager_Error;
+ break;
+ }
+ }
+ return status;
+}
+
+static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_t *handle,
+ serial_manager_read_handle_t *readHandle,
+ uint8_t *buffer,
+ uint32_t length)
+{
+ serial_manager_status_t status = kStatus_SerialManager_Error;
+
+ if (readHandle != NULL)
+ {
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ if (handle->type == kSerialPort_UsbCdc)
+ {
+ status = Serial_UsbCdcRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ }
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ if (handle->type == kSerialPort_UsbCdcVirtual)
+ {
+ status = Serial_UsbCdcVirtualRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ }
+#endif
+ }
+ return status;
+}
+
+#else
+
+static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_t *handle,
+ serial_manager_write_handle_t *writeHandle,
+ uint8_t *buffer,
+ uint32_t length)
+{
+ serial_manager_status_t status = kStatus_SerialManager_Error;
+
+ if (writeHandle != NULL)
+ {
+ switch (handle->type)
+ {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ case kSerialPort_Uart:
+ status = Serial_UartWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ case kSerialPort_UsbCdc:
+ status = Serial_UsbCdcWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ case kSerialPort_Swo:
+ status = Serial_SwoWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ case kSerialPort_UsbCdcVirtual:
+ status = Serial_UsbCdcVirtualWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ break;
+#endif
+ default:
+ status = kStatus_SerialManager_Error;
+ break;
+ }
+ }
+ return status;
+}
+
+static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_t *handle,
+ serial_manager_read_handle_t *readHandle,
+ uint8_t *buffer,
+ uint32_t length)
+{
+ serial_manager_status_t status = kStatus_SerialManager_Error;
+
+ if (readHandle != NULL)
+ {
+ switch (handle->type)
+ {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ case kSerialPort_Uart:
+ status = Serial_UartRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ case kSerialPort_UsbCdc:
+ status = Serial_UsbCdcRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ case kSerialPort_Swo:
+ status = Serial_SwoRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ case kSerialPort_UsbCdcVirtual:
+ status = Serial_UsbCdcVirtualRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
+ break;
+#endif
+ default:
+ status = kStatus_SerialManager_Error;
+ break;
+ }
+ }
+ return status;
+}
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+static void SerialManager_IsrFunction(serial_manager_handle_t *handle)
+{
+ uint32_t regPrimask = DisableGlobalIRQ();
+ switch (handle->type)
+ {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ case kSerialPort_Uart:
+ Serial_UartIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ case kSerialPort_UsbCdc:
+ Serial_UsbCdcIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ case kSerialPort_Swo:
+ Serial_SwoIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ case kSerialPort_UsbCdcVirtual:
+ Serial_UsbCdcVirtualIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+ default:
+ /*MISRA rule 16.4*/
+ break;
+ }
+ EnableGlobalIRQ(regPrimask);
+}
+
+static void SerialManager_Task(void *param)
+{
+ serial_manager_handle_t *handle = (serial_manager_handle_t *)param;
+ serial_manager_write_handle_t *serialWriteHandle;
+ serial_manager_read_handle_t *serialReadHandle;
+ uint32_t primask;
+ serial_manager_callback_message_t msg;
+
+ if (NULL != handle)
+ {
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+#else
+ osa_event_flags_t ev = 0;
+
+ do
+ {
+ if (KOSA_StatusSuccess ==
+ OSA_EventWait((osa_event_handle_t)handle->event, osaEventFlagsAll_c, false, osaWaitForever_c, &ev))
+ {
+ if (ev & SERIAL_EVENT_DATA_SENT)
+#endif
+
+#endif
+ {
+ serialWriteHandle =
+ (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->completedWriteHandleHead);
+ while (NULL != serialWriteHandle)
+ {
+ SerialManager_RemoveHead(&handle->completedWriteHandleHead);
+ msg.buffer = serialWriteHandle->transfer.buffer;
+ msg.length = serialWriteHandle->transfer.soFar;
+ serialWriteHandle->transfer.buffer = NULL;
+ if (serialWriteHandle->callback != NULL)
+ {
+ serialWriteHandle->callback(serialWriteHandle->callbackParam, &msg,
+ serialWriteHandle->transfer.status);
+ }
+ serialWriteHandle =
+ (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->completedWriteHandleHead);
+ }
+ }
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+#else
+ if (ev & SERIAL_EVENT_DATA_RECEIVED)
+#endif
+
+#endif
+ {
+ primask = DisableGlobalIRQ();
+ serialReadHandle = handle->openedReadHandleHead;
+ EnableGlobalIRQ(primask);
+
+ if (serialReadHandle != NULL)
+ {
+ if (serialReadHandle->transfer.buffer != NULL)
+ {
+ if (serialReadHandle->transfer.soFar >= serialReadHandle->transfer.length)
+ {
+ msg.buffer = serialReadHandle->transfer.buffer;
+ msg.length = serialReadHandle->transfer.soFar;
+ serialReadHandle->transfer.buffer = NULL;
+ if (serialReadHandle->callback != NULL)
+ {
+ serialReadHandle->callback(serialReadHandle->callbackParam, &msg,
+ serialReadHandle->transfer.status);
+ }
+ }
+ }
+ }
+ }
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+#else
+ }
+ } while (gUseRtos_c);
+#endif
+
+#endif
+ }
+}
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+static void SerialManager_TxCallback(void *callbackParam,
+ serial_manager_callback_message_t *message,
+ serial_manager_status_t status)
+{
+ serial_manager_handle_t *handle;
+ serial_manager_write_handle_t *writeHandle;
+
+ assert(callbackParam);
+ assert(message);
+
+ handle = (serial_manager_handle_t *)callbackParam;
+
+ writeHandle = (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->runningWriteHandleHead);
+
+ if (NULL != writeHandle)
+ {
+ SerialManager_RemoveHead(&handle->runningWriteHandleHead);
+ (void)SerialManager_StartWriting(handle);
+ writeHandle->transfer.soFar = message->length;
+ writeHandle->transfer.status = status;
+ if (kSerialManager_TransmissionNonBlocking == writeHandle->transfer.mode)
+ {
+ SerialManager_AddTail(&handle->completedWriteHandleHead, writeHandle);
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+ handle->commontaskMsg.callback = SerialManager_Task;
+ handle->commontaskMsg.callbackParam = handle;
+ COMMON_TASK_post_message(&handle->commontaskMsg);
+#else
+ (void)OSA_EventSet((osa_event_handle_t)handle->event, SERIAL_EVENT_DATA_SENT);
+#endif
+
+#else
+ SerialManager_Task(handle);
+#endif
+ }
+ else
+ {
+ writeHandle->transfer.buffer = NULL;
+ }
+ }
+}
+
+static void SerialManager_RxCallback(void *callbackParam,
+ serial_manager_callback_message_t *message,
+ serial_manager_status_t status)
+{
+ serial_manager_handle_t *handle;
+ uint32_t ringBufferLength;
+ uint32_t primask;
+
+ assert(callbackParam);
+ assert(message);
+
+ handle = (serial_manager_handle_t *)callbackParam;
+
+ status = kStatus_SerialManager_Notify;
+
+ for (uint32_t i = 0; i < message->length; i++)
+ {
+ handle->ringBuffer.ringBuffer[handle->ringBuffer.ringHead++] = message->buffer[i];
+ if (handle->ringBuffer.ringHead >= handle->ringBuffer.ringBufferSize)
+ {
+ handle->ringBuffer.ringHead = 0U;
+ }
+ if (handle->ringBuffer.ringHead == handle->ringBuffer.ringTail)
+ {
+ status = kStatus_SerialManager_RingBufferOverflow;
+ handle->ringBuffer.ringTail++;
+ if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize)
+ {
+ handle->ringBuffer.ringTail = 0U;
+ }
+ }
+ }
+
+ ringBufferLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail;
+ ringBufferLength = ringBufferLength % handle->ringBuffer.ringBufferSize;
+
+ primask = DisableGlobalIRQ();
+ if ((handle->openedReadHandleHead != NULL) && (handle->openedReadHandleHead->transfer.buffer != NULL))
+ {
+ if (handle->openedReadHandleHead->transfer.length > handle->openedReadHandleHead->transfer.soFar)
+ {
+ uint32_t remainLength =
+ handle->openedReadHandleHead->transfer.length - handle->openedReadHandleHead->transfer.soFar;
+ for (uint32_t i = 0; i < MIN(ringBufferLength, remainLength); i++)
+ {
+ handle->openedReadHandleHead->transfer.buffer[handle->openedReadHandleHead->transfer.soFar] =
+ handle->ringBuffer.ringBuffer[handle->ringBuffer.ringTail];
+ handle->ringBuffer.ringTail++;
+ handle->openedReadHandleHead->transfer.soFar++;
+ if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize)
+ {
+ handle->ringBuffer.ringTail = 0U;
+ }
+ }
+ ringBufferLength = ringBufferLength - MIN(ringBufferLength, remainLength);
+ }
+
+ if (handle->openedReadHandleHead->transfer.length > handle->openedReadHandleHead->transfer.soFar)
+ {
+ }
+ else
+ {
+ if (kSerialManager_TransmissionBlocking == handle->openedReadHandleHead->transfer.mode)
+ {
+ handle->openedReadHandleHead->transfer.buffer = NULL;
+ }
+ else
+ {
+ handle->openedReadHandleHead->transfer.status = kStatus_SerialManager_Success;
+
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+ handle->commontaskMsg.callback = SerialManager_Task;
+ handle->commontaskMsg.callbackParam = handle;
+ COMMON_TASK_post_message(&handle->commontaskMsg);
+#else
+ (void)OSA_EventSet((osa_event_handle_t)handle->event, SERIAL_EVENT_DATA_RECEIVED);
+#endif
+
+#else
+ SerialManager_Task(handle);
+#endif
+ }
+ }
+ }
+
+ if (ringBufferLength != 0U)
+ {
+ message->buffer = NULL;
+ message->length = ringBufferLength;
+ if ((NULL != handle->openedReadHandleHead) && (NULL != handle->openedReadHandleHead->callback))
+ {
+ handle->openedReadHandleHead->callback(handle->openedReadHandleHead->callbackParam, message, status);
+ }
+ }
+
+ ringBufferLength = handle->ringBuffer.ringBufferSize - 1U - ringBufferLength;
+
+ if (NULL != handle->openedReadHandleHead)
+ {
+ (void)SerialManager_StartReading(handle, handle->openedReadHandleHead, NULL, ringBufferLength);
+ }
+ EnableGlobalIRQ(primask);
+}
+
+static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHandle,
+ uint8_t *buffer,
+ uint32_t length,
+ serial_manager_transmission_mode_t mode)
+{
+ serial_manager_write_handle_t *serialWriteHandle;
+ serial_manager_handle_t *handle;
+ serial_manager_status_t status = kStatus_SerialManager_Success;
+ uint32_t primask;
+ uint8_t isEmpty = 0U;
+
+ assert(writeHandle);
+ assert(buffer);
+ assert(length);
+
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
+ handle = serialWriteHandle->serialManagerHandle;
+
+ assert(handle);
+ assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag);
+ assert(!((kSerialManager_TransmissionNonBlocking == mode) && (NULL == serialWriteHandle->callback)));
+
+ primask = DisableGlobalIRQ();
+ if (serialWriteHandle->transfer.buffer != NULL)
+ {
+ EnableGlobalIRQ(primask);
+ return kStatus_SerialManager_Busy;
+ }
+ serialWriteHandle->transfer.buffer = buffer;
+ serialWriteHandle->transfer.length = length;
+ serialWriteHandle->transfer.soFar = 0U;
+ serialWriteHandle->transfer.mode = mode;
+
+ if (NULL == LIST_GetHead(&handle->runningWriteHandleHead))
+ {
+ isEmpty = 1U;
+ }
+ SerialManager_AddTail(&handle->runningWriteHandleHead, serialWriteHandle);
+ EnableGlobalIRQ(primask);
+
+ if (isEmpty != 0U)
+ {
+ status = SerialManager_StartWriting(handle);
+ if ((serial_manager_status_t)kStatus_SerialManager_Success != status)
+ {
+ return status;
+ }
+ }
+
+ if (kSerialManager_TransmissionBlocking == mode)
+ {
+ while (serialWriteHandle->transfer.length > serialWriteHandle->transfer.soFar)
+ {
+#if defined(__GIC_PRIO_BITS)
+ if ((__get_CPSR() & CPSR_M_Msk) == 0x13)
+#else
+ if (__get_IPSR() != 0U)
+#endif
+ {
+ SerialManager_IsrFunction(handle);
+ }
+ }
+ }
+ return kStatus_SerialManager_Success;
+}
+
+static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandle,
+ uint8_t *buffer,
+ uint32_t length,
+ serial_manager_transmission_mode_t mode,
+ uint32_t *receivedLength)
+{
+ serial_manager_read_handle_t *serialReadHandle;
+ serial_manager_handle_t *handle;
+ uint32_t dataLength;
+ uint32_t primask;
+
+ assert(readHandle);
+ assert(buffer);
+ assert(length);
+
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;
+ handle = serialReadHandle->serialManagerHandle;
+
+ assert(handle);
+ assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag);
+ assert(!((kSerialManager_TransmissionNonBlocking == mode) && (NULL == serialReadHandle->callback)));
+
+ primask = DisableGlobalIRQ();
+ if (serialReadHandle->transfer.buffer != NULL)
+ {
+ EnableGlobalIRQ(primask);
+ return kStatus_SerialManager_Busy;
+ }
+ serialReadHandle->transfer.buffer = buffer;
+ serialReadHandle->transfer.length = length;
+ serialReadHandle->transfer.soFar = 0U;
+ serialReadHandle->transfer.mode = mode;
+
+ dataLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail;
+ dataLength = dataLength % handle->ringBuffer.ringBufferSize;
+
+ for (serialReadHandle->transfer.soFar = 0U; serialReadHandle->transfer.soFar < MIN(dataLength, length);
+ serialReadHandle->transfer.soFar++)
+ {
+ buffer[serialReadHandle->transfer.soFar] = handle->ringBuffer.ringBuffer[handle->ringBuffer.ringTail];
+ handle->ringBuffer.ringTail++;
+ if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize)
+ {
+ handle->ringBuffer.ringTail = 0U;
+ }
+ }
+
+ dataLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail;
+ dataLength = dataLength % handle->ringBuffer.ringBufferSize;
+ dataLength = handle->ringBuffer.ringBufferSize - 1U - dataLength;
+
+ (void)SerialManager_StartReading(handle, readHandle, NULL, dataLength);
+
+ if (receivedLength != NULL)
+ {
+ *receivedLength = serialReadHandle->transfer.soFar;
+ serialReadHandle->transfer.buffer = NULL;
+ EnableGlobalIRQ(primask);
+ }
+ else
+ {
+ if (serialReadHandle->transfer.soFar >= serialReadHandle->transfer.length)
+ {
+ serialReadHandle->transfer.buffer = NULL;
+ EnableGlobalIRQ(primask);
+ if (kSerialManager_TransmissionNonBlocking == mode)
+ {
+ if (serialReadHandle->callback != NULL)
+ {
+ serial_manager_callback_message_t msg;
+ msg.buffer = buffer;
+ msg.length = serialReadHandle->transfer.soFar;
+ serialReadHandle->callback(serialReadHandle->callbackParam, &msg, kStatus_SerialManager_Success);
+ }
+ }
+ }
+ else
+ {
+ EnableGlobalIRQ(primask);
+ }
+
+ if (kSerialManager_TransmissionBlocking == mode)
+ {
+ while (serialReadHandle->transfer.length > serialReadHandle->transfer.soFar)
+ {
+ }
+ }
+ }
+
+ return kStatus_SerialManager_Success;
+}
+
+#else
+
+static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHandle, uint8_t *buffer, uint32_t length)
+{
+ serial_manager_write_handle_t *serialWriteHandle;
+ serial_manager_handle_t *handle;
+
+ assert(writeHandle);
+ assert(buffer);
+ assert(length);
+
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
+ handle = serialWriteHandle->serialManagerHandle;
+
+ assert(handle);
+
+ return SerialManager_StartWriting(handle, serialWriteHandle, buffer, length);
+}
+
+static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length)
+{
+ serial_manager_read_handle_t *serialReadHandle;
+ serial_manager_handle_t *handle;
+
+ assert(readHandle);
+ assert(buffer);
+ assert(length);
+
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;
+ handle = serialReadHandle->serialManagerHandle;
+
+ assert(handle);
+
+ return SerialManager_StartReading(handle, serialReadHandle, buffer, length);
+}
+#endif
+
+serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, serial_manager_config_t *config)
+{
+ serial_manager_handle_t *handle;
+ serial_manager_status_t status = kStatus_SerialManager_Error;
+
+ assert(config);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ assert(config->ringBuffer);
+ assert(config->ringBufferSize);
+#endif
+ assert(serialHandle);
+ assert(SERIAL_MANAGER_HANDLE_SIZE >= sizeof(serial_manager_handle_t));
+
+ handle = (serial_manager_handle_t *)serialHandle;
+
+ (void)memset(handle, 0, SERIAL_MANAGER_HANDLE_SIZE);
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+
+ COMMON_TASK_init();
+
+#else
+ if (KOSA_StatusSuccess != OSA_EventCreate((osa_event_handle_t)handle->event, true))
+ {
+ return kStatus_SerialManager_Error;
+ }
+
+ if (KOSA_StatusSuccess != OSA_TaskCreate((osa_task_handle_t)handle->taskId, OSA_TASK(SerialManager_Task), handle))
+ {
+ return kStatus_SerialManager_Error;
+ }
+#endif
+
+#endif
+
+#endif
+
+ handle->type = config->type;
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ handle->ringBuffer.ringBuffer = config->ringBuffer;
+ handle->ringBuffer.ringBufferSize = config->ringBufferSize;
+#endif
+
+ switch (config->type)
+ {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ case kSerialPort_Uart:
+ status = Serial_UartInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ if ((serial_manager_status_t)kStatus_SerialManager_Success == status)
+ {
+ status = Serial_UartInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ SerialManager_TxCallback, handle);
+ if ((serial_manager_status_t)kStatus_SerialManager_Success == status)
+ {
+ status = Serial_UartInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ SerialManager_RxCallback, handle);
+ }
+ }
+#endif
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ case kSerialPort_UsbCdc:
+ status = Serial_UsbCdcInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ if (kStatus_SerialManager_Success == status)
+ {
+ status = Serial_UsbCdcInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ SerialManager_TxCallback, handle);
+ if (kStatus_SerialManager_Success == status)
+ {
+ status = Serial_UsbCdcInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ SerialManager_RxCallback, handle);
+ }
+ }
+#endif
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ case kSerialPort_Swo:
+ status = Serial_SwoInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ if (kStatus_SerialManager_Success == status)
+ {
+ status = Serial_SwoInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ SerialManager_TxCallback, handle);
+ }
+#endif
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ case kSerialPort_UsbCdcVirtual:
+ status = Serial_UsbCdcVirtualInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ if (kStatus_SerialManager_Success == status)
+ {
+ status = Serial_UsbCdcVirtualInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ SerialManager_TxCallback, handle);
+ if (kStatus_SerialManager_Success == status)
+ {
+ status = Serial_UsbCdcVirtualInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
+ SerialManager_RxCallback, handle);
+ }
+ }
+#endif
+ break;
+#endif
+ default:
+ /*MISRA rule 16.4*/
+ break;
+ }
+
+ return status;
+}
+
+serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle)
+{
+ serial_manager_handle_t *handle;
+ uint32_t primask;
+
+ assert(serialHandle);
+
+ handle = (serial_manager_handle_t *)serialHandle;
+
+ primask = DisableGlobalIRQ();
+ if ((handle->openedReadHandleHead != NULL) || (handle->openedWriteHandleCount != 0U))
+ {
+ EnableGlobalIRQ(primask);
+ return kStatus_SerialManager_Busy;
+ }
+ EnableGlobalIRQ(primask);
+
+ switch (handle->type)
+ {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ case kSerialPort_Uart:
+ (void)Serial_UartDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ case kSerialPort_UsbCdc:
+ (void)Serial_UsbCdcDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ case kSerialPort_Swo:
+ (void)Serial_SwoDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ case kSerialPort_UsbCdcVirtual:
+ (void)Serial_UsbCdcVirtualDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+ default:
+ /*MISRA rule 16.4*/
+ break;
+ }
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+#else
+ OSA_EventDestroy((osa_event_handle_t)handle->event);
+ OSA_TaskDestroy((osa_task_handle_t)handle->taskId);
+#endif
+
+#endif
+
+#endif
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle)
+{
+ serial_manager_handle_t *handle;
+ serial_manager_write_handle_t *serialWriteHandle;
+ uint32_t primask;
+
+ assert(serialHandle);
+ assert(writeHandle);
+ assert(SERIAL_MANAGER_WRITE_HANDLE_SIZE >= sizeof(serial_manager_write_handle_t));
+
+ handle = (serial_manager_handle_t *)serialHandle;
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
+
+ (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_HANDLE_SIZE);
+
+ primask = DisableGlobalIRQ();
+ handle->openedWriteHandleCount++;
+ EnableGlobalIRQ(primask);
+
+ serialWriteHandle->serialManagerHandle = handle;
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ serialWriteHandle->tag = SERIAL_MANAGER_WRITE_TAG;
+#endif
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle)
+{
+ serial_manager_handle_t *handle;
+ serial_manager_write_handle_t *serialWriteHandle;
+ uint32_t primask;
+
+ assert(writeHandle);
+
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
+ handle = (serial_manager_handle_t *)(void *)serialWriteHandle->serialManagerHandle;
+
+ assert(handle);
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag);
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ (void)SerialManager_CancelWriting(writeHandle);
+#endif
+ primask = DisableGlobalIRQ();
+ if (handle->openedWriteHandleCount > 0U)
+ {
+ handle->openedWriteHandleCount--;
+ }
+ EnableGlobalIRQ(primask);
+
+ (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_HANDLE_SIZE);
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle)
+{
+ serial_manager_handle_t *handle;
+ serial_manager_read_handle_t *serialReadHandle;
+ uint32_t primask;
+
+ assert(serialHandle);
+ assert(readHandle);
+ assert(SERIAL_MANAGER_READ_HANDLE_SIZE >= sizeof(serial_manager_read_handle_t));
+
+ handle = (serial_manager_handle_t *)serialHandle;
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;
+
+ primask = DisableGlobalIRQ();
+ if (handle->openedReadHandleHead != NULL)
+ {
+ EnableGlobalIRQ(primask);
+ return kStatus_SerialManager_Busy;
+ }
+ handle->openedReadHandleHead = serialReadHandle;
+ EnableGlobalIRQ(primask);
+
+ (void)memset(readHandle, 0, SERIAL_MANAGER_READ_HANDLE_SIZE);
+
+ serialReadHandle->serialManagerHandle = handle;
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ serialReadHandle->tag = SERIAL_MANAGER_READ_TAG;
+#endif
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle)
+{
+ serial_manager_handle_t *handle;
+ serial_manager_read_handle_t *serialReadHandle;
+ uint32_t primask;
+
+ assert(readHandle);
+
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;
+ handle = (serial_manager_handle_t *)(void *)serialReadHandle->serialManagerHandle;
+
+ assert(handle && (handle->openedReadHandleHead == serialReadHandle));
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag);
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ (void)SerialManager_CancelReading(readHandle);
+#endif
+
+ primask = DisableGlobalIRQ();
+ handle->openedReadHandleHead = NULL;
+ EnableGlobalIRQ(primask);
+
+ (void)memset(readHandle, 0, SERIAL_MANAGER_READ_HANDLE_SIZE);
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle, uint8_t *buffer, uint32_t length)
+{
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ return SerialManager_Write(writeHandle, buffer, length, kSerialManager_TransmissionBlocking);
+#else
+ return SerialManager_Write(writeHandle, buffer, length);
+#endif
+}
+
+serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length)
+{
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionBlocking, NULL);
+#else
+ return SerialManager_Read(readHandle, buffer, length);
+#endif
+}
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle,
+ uint8_t *buffer,
+ uint32_t length)
+{
+ return SerialManager_Write(writeHandle, buffer, length, kSerialManager_TransmissionNonBlocking);
+}
+
+serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length)
+{
+ return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionNonBlocking, NULL);
+}
+
+serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle)
+{
+ serial_manager_write_handle_t *serialWriteHandle;
+ uint32_t primask;
+ uint8_t isNotUsed = 0;
+
+ assert(writeHandle);
+
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
+
+ assert(serialWriteHandle->serialManagerHandle);
+ assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag);
+
+ if ((serialWriteHandle->transfer.buffer != NULL) &&
+ (kSerialManager_TransmissionBlocking == serialWriteHandle->transfer.mode))
+ {
+ return kStatus_SerialManager_Error;
+ }
+
+ primask = DisableGlobalIRQ();
+ if (serialWriteHandle != (serial_manager_write_handle_t *)(void *)LIST_GetHead(
+ &serialWriteHandle->serialManagerHandle->runningWriteHandleHead))
+ {
+ (void)LIST_RemoveElement(&serialWriteHandle->link);
+ isNotUsed = 1;
+ }
+ EnableGlobalIRQ(primask);
+
+ if (isNotUsed != 0U)
+ {
+ serialWriteHandle->transfer.soFar = 0;
+ serialWriteHandle->transfer.status = kStatus_SerialManager_Canceled;
+
+ SerialManager_AddTail(&serialWriteHandle->serialManagerHandle->completedWriteHandleHead, serialWriteHandle);
+#if defined(OSA_USED)
+
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
+ serialWriteHandle->serialManagerHandle->commontaskMsg.callback = SerialManager_Task;
+ serialWriteHandle->serialManagerHandle->commontaskMsg.callbackParam = serialWriteHandle->serialManagerHandle;
+ COMMON_TASK_post_message(&serialWriteHandle->serialManagerHandle->commontaskMsg);
+#else
+ (void)OSA_EventSet((osa_event_handle_t)serialWriteHandle->serialManagerHandle->event, SERIAL_EVENT_DATA_SENT);
+#endif
+
+#else
+ SerialManager_Task(serialWriteHandle->serialManagerHandle);
+#endif
+ }
+ else
+ {
+ switch (serialWriteHandle->serialManagerHandle->type)
+ {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ case kSerialPort_Uart:
+ (void)Serial_UartCancelWrite(
+ ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ case kSerialPort_UsbCdc:
+ (void)Serial_UsbCdcCancelWrite(
+ ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ case kSerialPort_Swo:
+ (void)Serial_SwoCancelWrite(
+ ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ case kSerialPort_UsbCdcVirtual:
+ (void)Serial_UsbCdcVirtualCancelWrite(
+ ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));
+ break;
+#endif
+ default:
+ /*MISRA rule 16.4*/
+ break;
+ }
+ }
+
+ (void)SerialManager_StartWriting(serialWriteHandle->serialManagerHandle);
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle)
+{
+ serial_manager_read_handle_t *serialReadHandle;
+ serial_manager_callback_message_t msg;
+ uint8_t *buffer;
+ uint32_t primask;
+
+ assert(readHandle);
+
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;
+
+ assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag);
+
+ if ((serialReadHandle->transfer.buffer != NULL) &&
+ (kSerialManager_TransmissionBlocking == serialReadHandle->transfer.mode))
+ {
+ return kStatus_SerialManager_Error;
+ }
+
+ primask = DisableGlobalIRQ();
+ buffer = serialReadHandle->transfer.buffer;
+ serialReadHandle->transfer.buffer = NULL;
+ serialReadHandle->transfer.length = 0;
+ msg.buffer = buffer;
+ msg.length = serialReadHandle->transfer.soFar;
+ EnableGlobalIRQ(primask);
+
+ if (buffer != NULL)
+ {
+ if (serialReadHandle->callback != NULL)
+ {
+ serialReadHandle->callback(serialReadHandle->callbackParam, &msg, kStatus_SerialManager_Canceled);
+ }
+ }
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle,
+ uint8_t *buffer,
+ uint32_t length,
+ uint32_t *receivedLength)
+{
+ assert(receivedLength);
+
+ return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionBlocking, receivedLength);
+}
+
+serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam)
+{
+ serial_manager_write_handle_t *serialWriteHandle;
+
+ assert(writeHandle);
+
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
+
+ assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag);
+
+ serialWriteHandle->callbackParam = callbackParam;
+ serialWriteHandle->callback = callback;
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam)
+{
+ serial_manager_read_handle_t *serialReadHandle;
+
+ assert(readHandle);
+
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;
+
+ assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag);
+
+ serialReadHandle->callbackParam = callbackParam;
+ serialReadHandle->callback = callback;
+
+ return kStatus_SerialManager_Success;
+}
+#endif
+
+serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle)
+{
+ assert(serialHandle);
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle)
+{
+ assert(serialHandle);
+
+ return kStatus_SerialManager_Success;
+}
diff --git a/third_party/nxp/K32W061DK6/components/serial_manager/serial_manager.h b/third_party/nxp/K32W061DK6/components/serial_manager/serial_manager.h
new file mode 100755
index 0000000..0b4e334
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/components/serial_manager/serial_manager.h
@@ -0,0 +1,548 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SERIAL_MANAGER_H__
+#define __SERIAL_MANAGER_H__
+
+/*!
+ * @addtogroup serialmanager
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/*! @brief Enable or disable serial manager non-blocking mode (1 - enable, 0 - disable) */
+#define SERIAL_MANAGER_NON_BLOCKING_MODE (1U)
+#else
+#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE
+#define SERIAL_MANAGER_NON_BLOCKING_MODE (0U)
+#endif
+#endif
+
+/*! @brief Enable or disable uart port (1 - enable, 0 - disable) */
+#ifndef SERIAL_PORT_TYPE_UART
+#define SERIAL_PORT_TYPE_UART (1U)
+#endif
+
+/*! @brief Enable or disable USB CDC port (1 - enable, 0 - disable) */
+#ifndef SERIAL_PORT_TYPE_USBCDC
+#define SERIAL_PORT_TYPE_USBCDC (0U)
+#endif
+
+/*! @brief Enable or disable SWO port (1 - enable, 0 - disable) */
+#ifndef SERIAL_PORT_TYPE_SWO
+#define SERIAL_PORT_TYPE_SWO (0U)
+#endif
+
+/*! @brief Enable or disable USB CDC virtual port (1 - enable, 0 - disable) */
+#ifndef SERIAL_PORT_TYPE_USBCDC_VIRTUAL
+#define SERIAL_PORT_TYPE_USBCDC_VIRTUAL (0U)
+#endif
+
+/*! @brief Set serial manager write handle size */
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (44U)
+#define SERIAL_MANAGER_READ_HANDLE_SIZE (44U)
+#else
+#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (4U)
+#define SERIAL_MANAGER_READ_HANDLE_SIZE (4U)
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+#include "serial_port_uart.h"
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#error The serial manager blocking mode cannot be supported for USB CDC.
+#endif
+
+#include "serial_port_usb.h"
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+#include "serial_port_swo.h"
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#error The serial manager blocking mode cannot be supported for USB CDC.
+#endif
+
+#include "serial_port_usb_virtual.h"
+#endif
+
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP 0U
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+
+#if (SERIAL_PORT_UART_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_UART_HANDLE_SIZE
+#endif
+
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+
+#if (SERIAL_PORT_USB_CDC_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_CDC_HANDLE_SIZE
+#endif
+
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+
+#if (SERIAL_PORT_SWO_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_SWO_HANDLE_SIZE
+#endif
+
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+
+#if (SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE
+#endif
+
+#endif
+
+/*! @brief SERIAL_PORT_UART_HANDLE_SIZE/SERIAL_PORT_USB_CDC_HANDLE_SIZE + serial manager dedicated size */
+#if ((defined(SERIAL_MANAGER_HANDLE_SIZE_TEMP) && (SERIAL_MANAGER_HANDLE_SIZE_TEMP > 0U)))
+#else
+#error SERIAL_PORT_TYPE_UART, SERIAL_PORT_TYPE_USBCDC, SERIAL_PORT_TYPE_SWO and SERIAL_PORT_TYPE_USBCDC_VIRTUAL should not be cleared at same time.
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 120U)
+#else
+#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 12U)
+#endif
+
+#define SERIAL_MANAGER_USE_COMMON_TASK (1U)
+#define SERIAL_MANAGER_TASK_PRIORITY (2U)
+#define SERIAL_MANAGER_TASK_STACK_SIZE (1000U)
+
+typedef void *serial_handle_t;
+typedef void *serial_write_handle_t;
+typedef void *serial_read_handle_t;
+
+/*! @brief serial port type*/
+typedef enum _serial_port_type
+{
+ kSerialPort_Uart = 1U, /*!< Serial port UART */
+ kSerialPort_UsbCdc, /*!< Serial port USB CDC */
+ kSerialPort_Swo, /*!< Serial port SWO */
+ kSerialPort_UsbCdcVirtual, /*!< Serial port USB CDC Virtual */
+} serial_port_type_t;
+
+/*! @brief serial manager config structure*/
+typedef struct _serial_manager_config
+{
+ uint8_t *ringBuffer; /*!< Ring buffer address, it is used to buffer data received by the hardware.
+ Besides, the memory space cannot be free during the lifetime of the serial
+ manager module. */
+ uint32_t ringBufferSize; /*!< The size of the ring buffer */
+ serial_port_type_t type; /*!< Serial port type */
+ void *portConfig; /*!< Serial port configuration */
+} serial_manager_config_t;
+
+/*! @brief serial manager error code*/
+typedef enum _serial_manager_status
+{
+ kStatus_SerialManager_Success = kStatus_Success, /*!< Success */
+ kStatus_SerialManager_Error = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 1), /*!< Failed */
+ kStatus_SerialManager_Busy = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 2), /*!< Busy */
+ kStatus_SerialManager_Notify = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 3), /*!< Ring buffer is not empty */
+ kStatus_SerialManager_Canceled =
+ MAKE_STATUS(kStatusGroup_SERIALMANAGER, 4), /*!< the non-blocking request is canceled */
+ kStatus_SerialManager_HandleConflict = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 5), /*!< The handle is opened */
+ kStatus_SerialManager_RingBufferOverflow =
+ MAKE_STATUS(kStatusGroup_SERIALMANAGER, 6), /*!< The ring buffer is overflowed */
+} serial_manager_status_t;
+
+/*! @brief Callback message structure */
+typedef struct _serial_manager_callback_message
+{
+ uint8_t *buffer; /*!< Transferred buffer */
+ uint32_t length; /*!< Transferred data length */
+} serial_manager_callback_message_t;
+
+/*! @brief callback function */
+typedef void (*serial_manager_callback_t)(void *callbackParam,
+ serial_manager_callback_message_t *message,
+ serial_manager_status_t status);
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @brief Initializes a serial manager module with the serial manager handle and the user configuration structure.
+ *
+ * This function configures the Serial Manager module with user-defined settings. The user can configure the
+ * configuration
+ * structure. The parameter serialHandle is a pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE
+ * allocated by the caller.
+ * The Serial Manager module supports two types of serial port, UART (includes UART, USART, LPSCI, LPUART, etc) and USB
+ * CDC.
+ * Please refer to #serial_port_type_t for serial port setting. These two types can be set by using
+ * #serial_manager_config_t.
+ *
+ * Example below shows how to use this API to configure the Serial Manager.
+ * For UART,
+ * @code
+ * #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U)
+ * static uint8_t s_serialHandleBuffer[SERIAL_MANAGER_HANDLE_SIZE];
+ * static serial_handle_t s_serialHandle = &s_serialHandleBuffer[0];
+ * static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];
+ *
+ * serial_manager_config_t config;
+ * serial_port_uart_config_t uartConfig;
+ * config.type = kSerialPort_Uart;
+ * config.ringBuffer = &s_ringBuffer[0];
+ * config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;
+ * uartConfig.instance = 0;
+ * uartConfig.clockRate = 24000000;
+ * uartConfig.baudRate = 115200;
+ * uartConfig.parityMode = kSerialManager_UartParityDisabled;
+ * uartConfig.stopBitCount = kSerialManager_UartOneStopBit;
+ * uartConfig.enableRx = 1;
+ * uartConfig.enableTx = 1;
+ * config.portConfig = &uartConfig;
+ * SerialManager_Init(s_serialHandle, &config);
+ * @endcode
+ * For USB CDC,
+ * @code
+ * #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U)
+ * static uint8_t s_serialHandleBuffer[SERIAL_MANAGER_HANDLE_SIZE];
+ * static serial_handle_t s_serialHandle = &s_serialHandleBuffer[0];
+ * static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];
+ *
+ * serial_manager_config_t config;
+ * serial_port_usb_cdc_config_t usbCdcConfig;
+ * config.type = kSerialPort_UsbCdc;
+ * config.ringBuffer = &s_ringBuffer[0];
+ * config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;
+ * usbCdcConfig.controllerIndex = kSerialManager_UsbControllerKhci0;
+ * config.portConfig = &usbCdcConfig;
+ * SerialManager_Init(s_serialHandle, &config);
+ * @endcode
+ *
+ * @param serialHandle Pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE allocated by the caller.
+ * @param config Pointer to user-defined configuration structure.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ * @retval kStatus_SerialManager_Success The Serial Manager module initialization succeed.
+ */
+serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, serial_manager_config_t *config);
+
+/*!
+ * @brief De-initializes the serial manager module instance.
+ *
+ * This function de-initializes the serial manager module instance. If the opened writing or
+ * reading handle is not closed, the function will return kStatus_SerialManager_Busy.
+ *
+ * @param serialHandle The serial manager module handle pointer.
+ * @retval kStatus_SerialManager_Success The serial manager de-initialization succeed.
+ * @retval kStatus_SerialManager_Busy Opened reading or writing handle is not closed.
+ */
+serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle);
+
+/*!
+ * @brief Opens a writing handle for the serial manager module.
+ *
+ * This function Opens a writing handle for the serial manager module. If the serial manager needs to
+ * be used in different tasks, the task should open a dedicated write handle for itself by calling
+ * #SerialManager_OpenWriteHandle. Since there can only one buffer for transmission for the writing
+ * handle at the same time, multiple writing handles need to be opened when the multiple transmission
+ * is needed for a task.
+ *
+ * @param serialHandle The serial manager module handle pointer.
+ * @param writeHandle The serial manager module writing handle pointer.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ * @retval kStatus_SerialManager_HandleConflict The writing handle was opened.
+ * @retval kStatus_SerialManager_Success The writing handle is opened.
+ *
+ * Example below shows how to use this API to write data.
+ * For task 1,
+ * @code
+ * static uint8_t s_serialWriteHandleBuffer1[SERIAL_MANAGER_WRITE_HANDLE_SIZE];
+ * static serial_write_handle_t s_serialWriteHandle1 = &s_serialWriteHandleBuffer1[0];
+ * static uint8_t s_nonBlockingWelcome1[] = "This is non-blocking writing log for task1!\r\n";
+ * SerialManager_OpenWriteHandle(serialHandle, s_serialWriteHandle1);
+ * SerialManager_InstallTxCallback(s_serialWriteHandle1, Task1_SerialManagerTxCallback, s_serialWriteHandle1);
+ * SerialManager_WriteNonBlocking(s_serialWriteHandle1, s_nonBlockingWelcome1, sizeof(s_nonBlockingWelcome1) - 1);
+ * @endcode
+ * For task 2,
+ * @code
+ * static uint8_t s_serialWriteHandleBuffer2[SERIAL_MANAGER_WRITE_HANDLE_SIZE];
+ * static serial_write_handle_t s_serialWriteHandle2 = &s_serialWriteHandleBuffer2[0];
+ * static uint8_t s_nonBlockingWelcome2[] = "This is non-blocking writing log for task2!\r\n";
+ * SerialManager_OpenWriteHandle(serialHandle, s_serialWriteHandle2);
+ * SerialManager_InstallTxCallback(s_serialWriteHandle2, Task2_SerialManagerTxCallback, s_serialWriteHandle2);
+ * SerialManager_WriteNonBlocking(s_serialWriteHandle2, s_nonBlockingWelcome2, sizeof(s_nonBlockingWelcome2) - 1);
+ * @endcode
+ */
+serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle);
+
+/*!
+ * @brief Closes a writing handle for the serial manager module.
+ *
+ * This function Closes a writing handle for the serial manager module.
+ *
+ * @param writeHandle The serial manager module writing handle pointer.
+ * @retval kStatus_SerialManager_Success The writing handle is closed.
+ */
+serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle);
+
+/*!
+ * @brief Opens a reading handle for the serial manager module.
+ *
+ * This function Opens a reading handle for the serial manager module. The reading handle can not be
+ * opened multiple at the same time. The error code kStatus_SerialManager_Busy would be returned when
+ * the previous reading handle is not closed. And There can only be one buffer for receiving for the
+ * reading handle at the same time.
+ *
+ * @param serialHandle The serial manager module handle pointer.
+ * @param readHandle The serial manager module reading handle pointer.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ * @retval kStatus_SerialManager_Success The reading handle is opened.
+ * @retval kStatus_SerialManager_Busy Previous reading handle is not closed.
+ *
+ * Example below shows how to use this API to read data.
+ * @code
+ * static uint8_t s_serialReadHandleBuffer[SERIAL_MANAGER_READ_HANDLE_SIZE];
+ * static serial_read_handle_t s_serialReadHandle = &s_serialReadHandleBuffer[0];
+ * SerialManager_OpenReadHandle(serialHandle, s_serialReadHandle);
+ * static uint8_t s_nonBlockingBuffer[64];
+ * SerialManager_InstallRxCallback(s_serialReadHandle, APP_SerialManagerRxCallback, s_serialReadHandle);
+ * SerialManager_ReadNonBlocking(s_serialReadHandle, s_nonBlockingBuffer, sizeof(s_nonBlockingBuffer));
+ * @endcode
+ */
+serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle);
+
+/*!
+ * @brief Closes a reading for the serial manager module.
+ *
+ * This function Closes a reading for the serial manager module.
+ *
+ * @param readHandle The serial manager module reading handle pointer.
+ * @retval kStatus_SerialManager_Success The reading handle is closed.
+ */
+serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle);
+
+/*!
+ * @brief Transmits data with the blocking mode.
+ *
+ * This is a blocking function, which polls the sending queue, waits for the sending queue to be empty.
+ * This function sends data using an interrupt method. The interrupt of the hardware could not be disabled.
+ * And There can only one buffer for transmission for the writing handle at the same time.
+ *
+ * @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking
+ * cannot be used at the same time.
+ * And, the function #SerialManager_CancelWriting cannot be used to abort the transmission of this function.
+ *
+ * @param writeHandle The serial manager module handle pointer.
+ * @param buffer Start address of the data to write.
+ * @param length Length of the data to write.
+ * @retval kStatus_SerialManager_Success Successfully sent all data.
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle,
+ uint8_t *buffer,
+ uint32_t length);
+
+/*!
+ * @brief Reads data with the blocking mode.
+ *
+ * This is a blocking function, which polls the receiving buffer, waits for the receiving buffer to be full.
+ * This function receives data using an interrupt method. The interrupt of the hardware could not be disabled.
+ * And There can only one buffer for receiving for the reading handle at the same time.
+ *
+ * @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking
+ * cannot be used at the same time.
+ * And, the function #SerialManager_CancelReading cannot be used to abort the transmission of this function.
+ *
+ * @param readHandle The serial manager module handle pointer.
+ * @param buffer Start address of the data to store the received data.
+ * @param length The length of the data to be received.
+ * @retval kStatus_SerialManager_Success Successfully received all data.
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length);
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+/*!
+ * @brief Transmits data with the non-blocking mode.
+ *
+ * This is a non-blocking function, which returns directly without waiting for all data to be sent.
+ * When all data is sent, the module notifies the upper layer through a TX callback function and passes
+ * the status parameter @ref kStatus_SerialManager_Success.
+ * This function sends data using an interrupt method. The interrupt of the hardware could not be disabled.
+ * And There can only one buffer for transmission for the writing handle at the same time.
+ *
+ * @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking
+ * cannot be used at the same time. And, the TX callback is mandatory before the function could be used.
+ *
+ * @param writeHandle The serial manager module handle pointer.
+ * @param buffer Start address of the data to write.
+ * @param length Length of the data to write.
+ * @retval kStatus_SerialManager_Success Successfully sent all data.
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle,
+ uint8_t *buffer,
+ uint32_t length);
+
+/*!
+ * @brief Reads data with the non-blocking mode.
+ *
+ * This is a non-blocking function, which returns directly without waiting for all data to be received.
+ * When all data is received, the module driver notifies the upper layer
+ * through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Success.
+ * This function receives data using an interrupt method. The interrupt of the hardware could not be disabled.
+ * And There can only one buffer for receiving for the reading handle at the same time.
+ *
+ * @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking
+ * cannot be used at the same time. And, the RX callback is mandatory before the function could be used.
+ *
+ * @param readHandle The serial manager module handle pointer.
+ * @param buffer Start address of the data to store the received data.
+ * @param length The length of the data to be received.
+ * @retval kStatus_SerialManager_Success Successfully received all data.
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle,
+ uint8_t *buffer,
+ uint32_t length);
+
+/*!
+ * @brief Tries to read data.
+ *
+ * The function tries to read data from internal ring buffer. If the ring buffer is not empty, the data will be
+ * copied from ring buffer to up layer buffer. The copied length is the minimum of the ring buffer and up layer length.
+ * After the data is copied, the actual data length is passed by the parameter length.
+ * And There can only one buffer for receiving for the reading handle at the same time.
+ *
+ * @param readHandle The serial manager module handle pointer.
+ * @param buffer Start address of the data to store the received data.
+ * @param length The length of the data to be received.
+ * @param receivedLength Length received from the ring buffer directly.
+ * @retval kStatus_SerialManager_Success Successfully received all data.
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle,
+ uint8_t *buffer,
+ uint32_t length,
+ uint32_t *receivedLength);
+
+/*!
+ * @brief Cancels unfinished send transmission.
+ *
+ * The function cancels unfinished send transmission. When the transfer is canceled, the module notifies the upper layer
+ * through a TX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled.
+ *
+ * @note The function #SerialManager_CancelWriting cannot be used to abort the transmission of
+ * the function #SerialManager_WriteBlocking.
+ *
+ * @param writeHandle The serial manager module handle pointer.
+ * @retval kStatus_SerialManager_Success Get successfully abort the sending.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle);
+
+/*!
+ * @brief Cancels unfinished receive transmission.
+ *
+ * The function cancels unfinished receive transmission. When the transfer is canceled, the module notifies the upper
+ * layer
+ * through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled.
+ *
+ * @note The function #SerialManager_CancelReading cannot be used to abort the transmission of
+ * the function #SerialManager_ReadBlocking.
+ *
+ * @param readHandle The serial manager module handle pointer.
+ * @retval kStatus_SerialManager_Success Get successfully abort the receiving.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle);
+
+/*!
+ * @brief Installs a TX callback and callback parameter.
+ *
+ * This function is used to install the TX callback and callback parameter for the serial manager module.
+ * When any status of TX transmission changed, the driver will notify the upper layer by the installed callback
+ * function. And the status is also passed as status parameter when the callback is called.
+ *
+ * @param writeHandle The serial manager module handle pointer.
+ * @param callback The callback function.
+ * @param callbackParam The parameter of the callback function.
+ * @retval kStatus_SerialManager_Success Successfully install the callback.
+ */
+serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+
+/*!
+ * @brief Installs a RX callback and callback parameter.
+ *
+ * This function is used to install the RX callback and callback parameter for the serial manager module.
+ * When any status of RX transmission changed, the driver will notify the upper layer by the installed callback
+ * function. And the status is also passed as status parameter when the callback is called.
+ *
+ * @param readHandle The serial manager module handle pointer.
+ * @param callback The callback function.
+ * @param callbackParam The parameter of the callback function.
+ * @retval kStatus_SerialManager_Success Successfully install the callback.
+ */
+serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+
+#endif
+
+/*!
+ * @brief Prepares to enter low power consumption.
+ *
+ * This function is used to prepare to enter low power consumption.
+ *
+ * @param serialHandle The serial manager module handle pointer.
+ * @retval kStatus_SerialManager_Success Successful operation.
+ */
+serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle);
+
+/*!
+ * @brief Restores from low power consumption.
+ *
+ * This function is used to restore from low power consumption.
+ *
+ * @param serialHandle The serial manager module handle pointer.
+ * @retval kStatus_SerialManager_Success Successful operation.
+ */
+serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle);
+
+#if defined(__cplusplus)
+}
+#endif
+/*! @} */
+#endif /* __SERIAL_MANAGER_H__ */
diff --git a/third_party/nxp/K32W061DK6/components/serial_manager/serial_port_internal.h b/third_party/nxp/K32W061DK6/components/serial_manager/serial_port_internal.h
new file mode 100755
index 0000000..abccd47
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/components/serial_manager/serial_port_internal.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright 2019 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SERIAL_PORT_INTERNAL_H__
+#define __SERIAL_PORT_INTERNAL_H__
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig);
+serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+void Serial_UartIsrFunction(serial_handle_t serialHandle);
+#endif
+
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+serial_manager_status_t Serial_UsbCdcInit(serial_handle_t serialHandle, void *config);
+serial_manager_status_t Serial_UsbCdcDeinit(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UsbCdcWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_UsbCdcRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_UsbCdcCancelWrite(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UsbCdcInstallTxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+serial_manager_status_t Serial_UsbCdcInstallRxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+void Serial_UsbCdcIsrFunction(serial_handle_t serialHandle);
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+serial_manager_status_t Serial_SwoInit(serial_handle_t serialHandle, void *config);
+serial_manager_status_t Serial_SwoDeinit(serial_handle_t serialHandle);
+serial_manager_status_t Serial_SwoWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_SwoRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#endif
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_SwoCancelWrite(serial_handle_t serialHandle);
+serial_manager_status_t Serial_SwoInstallTxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+serial_manager_status_t Serial_SwoInstallRxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+void Serial_SwoIsrFunction(serial_handle_t serialHandle);
+#endif
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+serial_manager_status_t Serial_UsbCdcVirtualInit(serial_handle_t serialHandle, void *config);
+serial_manager_status_t Serial_UsbCdcVirtualDeinit(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UsbCdcVirtualWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_UsbCdcVirtualRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_UsbCdcVirtualCancelWrite(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UsbCdcVirtualInstallTxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+serial_manager_status_t Serial_UsbCdcVirtualInstallRxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam);
+void Serial_UsbCdcVirtualIsrFunction(serial_handle_t serialHandle);
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __SERIAL_PORT_INTERNAL_H__ */
diff --git a/third_party/nxp/K32W061DK6/components/serial_manager/serial_port_uart.c b/third_party/nxp/K32W061DK6/components/serial_manager/serial_port_uart.c
new file mode 100755
index 0000000..f60320d
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/components/serial_manager/serial_port_uart.c
@@ -0,0 +1,371 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "serial_manager.h"
+#include "serial_port_internal.h"
+
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+#include "uart.h"
+
+#include "serial_port_uart.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#ifndef NDEBUG
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
+#undef assert
+#define assert(n)
+#endif
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#define SERIAL_PORT_UART_RECEIVE_DATA_LENGTH 1U
+
+typedef struct _serial_uart_send_state
+{
+ serial_manager_callback_t callback;
+ void *callbackParam;
+ uint8_t *buffer;
+ uint32_t length;
+ volatile uint8_t busy;
+} serial_uart_send_state_t;
+
+typedef struct _serial_uart_recv_state
+{
+ serial_manager_callback_t callback;
+ void *callbackParam;
+ volatile uint8_t busy;
+ uint8_t readBuffer[SERIAL_PORT_UART_RECEIVE_DATA_LENGTH];
+} serial_uart_recv_state_t;
+#endif
+
+typedef struct _serial_uart_state
+{
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ serial_uart_send_state_t tx;
+ serial_uart_recv_state_t rx;
+#endif
+ uint8_t usartHandleBuffer[HAL_UART_HANDLE_SIZE];
+} serial_uart_state_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+/* UART user callback */
+static void Serial_UartCallback(hal_uart_handle_t handle, hal_uart_status_t status, void *userData)
+{
+ serial_uart_state_t *serialUartHandle;
+ serial_manager_callback_message_t msg;
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ hal_uart_transfer_t transfer;
+#endif
+
+ if (NULL == userData)
+ {
+ return;
+ }
+
+ serialUartHandle = (serial_uart_state_t *)userData;
+
+ if ((hal_uart_status_t)kStatus_HAL_UartRxIdle == status)
+ {
+ if ((NULL != serialUartHandle->rx.callback))
+ {
+ msg.buffer = &serialUartHandle->rx.readBuffer[0];
+ msg.length = sizeof(serialUartHandle->rx.readBuffer);
+ serialUartHandle->rx.callback(serialUartHandle->rx.callbackParam, &msg, kStatus_SerialManager_Success);
+ }
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ transfer.data = &serialUartHandle->rx.readBuffer[0];
+ transfer.dataSize = sizeof(serialUartHandle->rx.readBuffer);
+ if (kStatus_HAL_UartSuccess ==
+ HAL_UartTransferReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer))
+#else
+ if ((hal_uart_status_t)kStatus_HAL_UartSuccess ==
+ HAL_UartReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
+ &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer)))
+#endif
+ {
+ serialUartHandle->rx.busy = 1U;
+ }
+ else
+ {
+ serialUartHandle->rx.busy = 0U;
+ }
+ }
+ else if ((hal_uart_status_t)kStatus_HAL_UartTxIdle == status)
+ {
+ if (serialUartHandle->tx.busy != 0U)
+ {
+ serialUartHandle->tx.busy = 0U;
+ if ((NULL != serialUartHandle->tx.callback))
+ {
+ msg.buffer = serialUartHandle->tx.buffer;
+ msg.length = serialUartHandle->tx.length;
+ serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &msg, kStatus_SerialManager_Success);
+ }
+ }
+ }
+ else
+ {
+ }
+}
+#endif
+
+serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig)
+{
+ serial_uart_state_t *serialUartHandle;
+ serial_port_uart_config_t *uartConfig;
+ hal_uart_config_t config;
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ hal_uart_transfer_t transfer;
+#endif
+#endif
+
+ assert(serialConfig);
+ assert(serialHandle);
+ assert(SERIAL_PORT_UART_HANDLE_SIZE >= sizeof(serial_uart_state_t));
+
+ uartConfig = (serial_port_uart_config_t *)serialConfig;
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+ config.baudRate_Bps = uartConfig->baudRate;
+ config.parityMode = (hal_uart_parity_mode_t)uartConfig->parityMode;
+ config.stopBitCount = (hal_uart_stop_bit_count_t)uartConfig->stopBitCount;
+ config.enableRx = uartConfig->enableRx;
+ config.enableTx = uartConfig->enableTx;
+ config.srcClock_Hz = uartConfig->clockRate;
+ config.instance = uartConfig->instance;
+
+ if (kStatus_HAL_UartSuccess != HAL_UartInit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &config))
+ {
+ return kStatus_SerialManager_Error;
+ }
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ if (kStatus_HAL_UartSuccess !=
+ HAL_UartTransferInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
+ Serial_UartCallback, serialUartHandle))
+#else
+ if (kStatus_HAL_UartSuccess != HAL_UartInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
+ Serial_UartCallback, serialUartHandle))
+#endif
+ {
+ return kStatus_SerialManager_Error;
+ }
+
+ if (uartConfig->enableRx != 0U)
+ {
+ serialUartHandle->rx.busy = 1U;
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ transfer.data = &serialUartHandle->rx.readBuffer[0];
+ transfer.dataSize = sizeof(serialUartHandle->rx.readBuffer);
+ if (kStatus_HAL_UartSuccess !=
+ HAL_UartTransferReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer))
+#else
+ if (kStatus_HAL_UartSuccess !=
+ HAL_UartReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
+ &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer)))
+#endif
+ {
+ serialUartHandle->rx.busy = 0U;
+ return kStatus_SerialManager_Error;
+ }
+ }
+#endif
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle)
+{
+ serial_uart_state_t *serialUartHandle;
+
+ assert(serialHandle);
+
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ (void)HAL_UartTransferAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+#else
+ (void)HAL_UartAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+#endif
+#endif
+ (void)HAL_UartDeinit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+ serialUartHandle->tx.busy = 0U;
+ serialUartHandle->rx.busy = 0U;
+#endif
+
+ return kStatus_SerialManager_Success;
+}
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
+{
+ serial_uart_state_t *serialUartHandle;
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ hal_uart_transfer_t transfer;
+#endif
+
+ assert(serialHandle);
+ assert(buffer);
+ assert(length);
+
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+ if (serialUartHandle->tx.busy != 0U)
+ {
+ return kStatus_SerialManager_Busy;
+ }
+ serialUartHandle->tx.busy = 1U;
+
+ serialUartHandle->tx.buffer = buffer;
+ serialUartHandle->tx.length = length;
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ transfer.data = buffer;
+ transfer.dataSize = length;
+ if (kStatus_HAL_UartSuccess !=
+ HAL_UartTransferSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer))
+#else
+ if (kStatus_HAL_UartSuccess !=
+ HAL_UartSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length))
+#endif
+ {
+ serialUartHandle->tx.busy = 0U;
+ return kStatus_SerialManager_Error;
+ }
+ return kStatus_SerialManager_Success;
+}
+
+#else
+
+serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
+{
+ serial_uart_state_t *serialUartHandle;
+
+ assert(serialHandle);
+ assert(buffer);
+ assert(length);
+
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+ return (serial_manager_status_t)HAL_UartSendBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
+ buffer, length);
+}
+
+serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
+{
+ serial_uart_state_t *serialUartHandle;
+
+ assert(serialHandle);
+ assert(buffer);
+ assert(length);
+
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+ return (serial_manager_status_t)HAL_UartReceiveBlocking(
+ ((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length);
+}
+
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle)
+{
+ serial_uart_state_t *serialUartHandle;
+ serial_manager_callback_message_t msg;
+ uint32_t primask;
+ uint8_t isBusy = 0U;
+
+ assert(serialHandle);
+
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+ primask = DisableGlobalIRQ();
+ isBusy = serialUartHandle->tx.busy;
+ serialUartHandle->tx.busy = 0U;
+ EnableGlobalIRQ(primask);
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ (void)HAL_UartTransferAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+#else
+ (void)HAL_UartAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+#endif
+ if (isBusy != 0U)
+ {
+ if ((NULL != serialUartHandle->tx.callback))
+ {
+ msg.buffer = serialUartHandle->tx.buffer;
+ msg.length = serialUartHandle->tx.length;
+ serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &msg, kStatus_SerialManager_Canceled);
+ }
+ }
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam)
+{
+ serial_uart_state_t *serialUartHandle;
+
+ assert(serialHandle);
+
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+ serialUartHandle->tx.callback = callback;
+ serialUartHandle->tx.callbackParam = callbackParam;
+
+ return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle,
+ serial_manager_callback_t callback,
+ void *callbackParam)
+{
+ serial_uart_state_t *serialUartHandle;
+
+ assert(serialHandle);
+
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+ serialUartHandle->rx.callback = callback;
+ serialUartHandle->rx.callbackParam = callbackParam;
+
+ return kStatus_SerialManager_Success;
+}
+
+void Serial_UartIsrFunction(serial_handle_t serialHandle)
+{
+ serial_uart_state_t *serialUartHandle;
+
+ assert(serialHandle);
+
+ serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+ HAL_UartIsrFunction(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+}
+#endif
+
+#endif
diff --git a/third_party/nxp/K32W061DK6/components/serial_manager/serial_port_uart.h b/third_party/nxp/K32W061DK6/components/serial_manager/serial_port_uart.h
new file mode 100755
index 0000000..2d5d21e
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/components/serial_manager/serial_port_uart.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SERIAL_PORT_UART_H__
+#define __SERIAL_PORT_UART_H__
+
+/*!
+ * @addtogroup serial_port_uart
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief serial port uart handle size*/
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#define SERIAL_PORT_UART_HANDLE_SIZE (166U)
+#else
+#define SERIAL_PORT_UART_HANDLE_SIZE (4U)
+#endif
+
+/*! @brief serial port uart parity mode*/
+typedef enum _serial_port_uart_parity_mode
+{
+ kSerialManager_UartParityDisabled = 0x0U, /*!< Parity disabled */
+ kSerialManager_UartParityEven = 0x1U, /*!< Parity even enabled */
+ kSerialManager_UartParityOdd = 0x2U, /*!< Parity odd enabled */
+} serial_port_uart_parity_mode_t;
+
+/*! @brief serial port uart stop bit count*/
+typedef enum _serial_port_uart_stop_bit_count
+{
+ kSerialManager_UartOneStopBit = 0U, /*!< One stop bit */
+ kSerialManager_UartTwoStopBit = 1U, /*!< Two stop bits */
+} serial_port_uart_stop_bit_count_t;
+
+/*! @brief serial port uart config struct*/
+typedef struct _serial_port_uart_config
+{
+ uint32_t clockRate; /*!< clock rate */
+ uint32_t baudRate; /*!< baud rate */
+ serial_port_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
+ serial_port_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
+ uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information
+ please refer to the SOC corresponding RM. */
+ uint8_t enableRx; /*!< Enable RX */
+ uint8_t enableTx; /*!< Enable TX */
+} serial_port_uart_config_t;
+/*! @} */
+#endif /* __SERIAL_PORT_UART_H__ */
diff --git a/third_party/nxp/K32W061DK6/components/uart/uart.h b/third_party/nxp/K32W061DK6/components/uart/uart.h
new file mode 100755
index 0000000..11db5c4
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/components/uart/uart.h
@@ -0,0 +1,475 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __HAL_UART_ADAPTER_H__
+#define __HAL_UART_ADAPTER_H__
+
+#if defined(FSL_RTOS_FREE_RTOS)
+#include "FreeRTOS.h"
+#endif
+
+/*!
+ * @addtogroup UART_Adapter
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Enable or disable UART adapter non-blocking mode (1 - enable, 0 - disable) */
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+#define UART_ADAPTER_NON_BLOCKING_MODE (1U)
+#else
+#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE
+#define UART_ADAPTER_NON_BLOCKING_MODE (0U)
+#else
+#define UART_ADAPTER_NON_BLOCKING_MODE SERIAL_MANAGER_NON_BLOCKING_MODE
+#endif
+#endif
+
+#if defined(__GIC_PRIO_BITS)
+#define HAL_UART_ISR_PRIORITY (25U)
+#else
+#if defined(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
+#define HAL_UART_ISR_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
+#else
+/* The default value 3 is used to support different ARM Core, such as CM0P, CM4, CM7, and CM33, etc.
+ * The minimum number of priority bits implemented in the NVIC is 2 on these SOCs. The value of mininum
+ * priority is 3 (2^2 - 1). So, the default value is 3.
+ */
+#define HAL_UART_ISR_PRIORITY (3U)
+#endif
+#endif
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+#define HAL_UART_HANDLE_SIZE (90U)
+#else
+#define HAL_UART_HANDLE_SIZE (4U)
+#endif
+
+/*! @brief Whether enable transactional function of the UART. (0 - disable, 1 - enable) */
+#define HAL_UART_TRANSFER_MODE (0U)
+
+typedef void *hal_uart_handle_t;
+
+/*! @brief UART status */
+typedef enum _hal_uart_status
+{
+ kStatus_HAL_UartSuccess = kStatus_Success, /*!< Successfully */
+ kStatus_HAL_UartTxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 1), /*!< TX busy */
+ kStatus_HAL_UartRxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 2), /*!< RX busy */
+ kStatus_HAL_UartTxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 3), /*!< HAL UART transmitter is idle. */
+ kStatus_HAL_UartRxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 4), /*!< HAL UART receiver is idle */
+ kStatus_HAL_UartBaudrateNotSupport =
+ MAKE_STATUS(kStatusGroup_HAL_UART, 5), /*!< Baudrate is not support in current clock source */
+ kStatus_HAL_UartProtocolError = MAKE_STATUS(
+ kStatusGroup_HAL_UART,
+ 6), /*!< Error occurs for Noise, Framing, Parity, etc.
+ For transactional transfer, The up layer needs to abort the transfer and then starts again */
+ kStatus_HAL_UartError = MAKE_STATUS(kStatusGroup_HAL_UART, 7), /*!< Error occurs on HAL UART */
+} hal_uart_status_t;
+
+/*! @brief UART parity mode. */
+typedef enum _hal_uart_parity_mode
+{
+ kHAL_UartParityDisabled = 0x0U, /*!< Parity disabled */
+ kHAL_UartParityEven = 0x1U, /*!< Parity even enabled */
+ kHAL_UartParityOdd = 0x2U, /*!< Parity odd enabled */
+} hal_uart_parity_mode_t;
+
+/*! @brief UART stop bit count. */
+typedef enum _hal_uart_stop_bit_count
+{
+ kHAL_UartOneStopBit = 0U, /*!< One stop bit */
+ kHAL_UartTwoStopBit = 1U, /*!< Two stop bits */
+} hal_uart_stop_bit_count_t;
+
+/*! @brief UART configuration structure. */
+typedef struct _hal_uart_config
+{
+ uint32_t srcClock_Hz; /*!< Source clock */
+ uint32_t baudRate_Bps; /*!< Baud rate */
+ hal_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
+ hal_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
+ uint8_t enableRx; /*!< Enable RX */
+ uint8_t enableTx; /*!< Enable TX */
+ uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information please refer to the
+ SOC corresponding RM.
+ Invalid instance value will cause initialization failure. */
+} hal_uart_config_t;
+
+/*! @brief UART transfer callback function. */
+typedef void (*hal_uart_transfer_callback_t)(hal_uart_handle_t handle, hal_uart_status_t status, void *callbackParam);
+
+/*! @brief UART transfer structure. */
+typedef struct _hal_uart_transfer
+{
+ uint8_t *data; /*!< The buffer of data to be transfer.*/
+ size_t dataSize; /*!< The byte count to be transfer. */
+} hal_uart_transfer_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes a UART instance with the UART handle and the user configuration structure.
+ *
+ * This function configures the UART module with user-defined settings. The user can configure the configuration
+ * structure. The parameter handle is a pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by
+ * the caller. Example below shows how to use this API to configure the UART.
+ * @code
+ * uint8_t g_UartHandleBuffer[HAL_UART_HANDLE_SIZE];
+ * hal_uart_handle_t g_UartHandle = &g_UartHandleBuffer[0];
+ * hal_uart_config_t config;
+ * config.srcClock_Hz = 48000000;
+ * config.baudRate_Bps = 115200U;
+ * config.parityMode = kHAL_UartParityDisabled;
+ * config.stopBitCount = kHAL_UartOneStopBit;
+ * config.enableRx = 1;
+ * config.enableTx = 1;
+ * config.instance = 0;
+ * HAL_UartInit(g_UartHandle, &config);
+ * @endcode
+ *
+ * @param handle Pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by the caller.
+ * @param config Pointer to user-defined configuration structure.
+ * @retval kStatus_HAL_UartBaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_HAL_UartSuccess UART initialization succeed
+ */
+hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, hal_uart_config_t *config);
+
+/*!
+ * @brief Deinitializes a UART instance.
+ *
+ * This function waits for TX complete, disables TX and RX, and disables the UART clock.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_HAL_UartSuccess UART de-initialization succeed
+ */
+hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle);
+
+/*! @}*/
+
+/*!
+ * @name Blocking bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Reads RX data register using a blocking method.
+ *
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
+ * have data, and reads data from the RX register.
+ *
+ * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking
+ * cannot be used at the same time.
+ * And, the function #HAL_UartTransferAbortReceive cannot be used to abort the transmission of this function.
+ *
+ * @param handle UART handle pointer.
+ * @param data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ * @retval kStatus_HAL_UartError An error occurred while receiving data.
+ * @retval kStatus_HAL_UartParityError A parity error occurred while receiving data.
+ * @retval kStatus_HAL_UartSuccess Successfully received all data.
+ */
+hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
+
+/*!
+ * @brief Writes to the TX register using a blocking method.
+ *
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
+ * to have room and writes data to the TX buffer.
+ *
+ * @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking
+ * cannot be used at the same time.
+ * And, the function #HAL_UartTransferAbortSend cannot be used to abort the transmission of this function.
+ *
+ * @param handle UART handle pointer.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_HAL_UartSuccess Successfully sent all data.
+ */
+hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length);
+
+/*! @}*/
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+
+/*!
+ * @name Transactional
+ * @note The transactional API and the functional API cannot be used at the same time. The macro
+ * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the
+ * functional API with non-blocking mode will be used. Otherwise, transactional API will be used.
+ * @{
+ */
+
+/*!
+ * @brief Installs a callback and callback parameter.
+ *
+ * This function is used to install the callback and callback parameter for UART module.
+ * When any status of the UART changed, the driver will notify the upper layer by the installed callback
+ * function. And the status is also passed as status parameter when the callback is called.
+ *
+ * @param handle UART handle pointer.
+ * @param callback The callback function.
+ * @param callbackParam The parameter of the callback function.
+ * @retval kStatus_HAL_UartSuccess Successfully install the callback.
+ */
+hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle,
+ hal_uart_transfer_callback_t callback,
+ void *callbackParam);
+
+/*!
+ * @brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be received.
+ * The receive request is saved by the UART driver.
+ * When the new data arrives, the receive request is serviced first.
+ * When all data is received, the UART driver notifies the upper layer
+ * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle.
+ *
+ * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking
+ * cannot be used at the same time.
+ *
+ * @param handle UART handle pointer.
+ * @param transfer UART transfer structure, see #hal_uart_transfer_t.
+ * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue.
+ * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer);
+
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the ISR, the UART driver calls the callback
+ * function and passes the @ref kStatus_UART_TxIdle as status parameter.
+ *
+ * @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking
+ * cannot be used at the same time.
+ *
+ * @param handle UART handle pointer.
+ * @param transfer UART transfer structure. See #hal_uart_transfer_t.
+ * @retval kStatus_HAL_UartSuccess Successfully start the data transmission.
+ * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer);
+
+/*!
+ * @brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param handle UART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_HAL_UartError An error occurred.
+ * @retval kStatus_Success Get successfully through the parameter \p count.
+ */
+hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count);
+
+/*!
+ * @brief Gets the number of bytes written to the UART TX register.
+ *
+ * This function gets the number of bytes written to the UART TX
+ * register by using the interrupt method.
+ *
+ * @param handle UART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_HAL_UartError An error occurred.
+ * @retval kStatus_Success Get successfully through the parameter \p count.
+ */
+hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
+ * how many bytes are not received yet.
+ *
+ * @note The function #HAL_UartTransferAbortReceive cannot be used to abort the transmission of
+ * the function #HAL_UartReceiveBlocking.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the receiving.
+ */
+hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle);
+
+/*!
+ * @brief Aborts the interrupt-driven data sending.
+ *
+ * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out
+ * how many bytes are not sent out.
+ *
+ * @note The function #HAL_UartTransferAbortSend cannot be used to abort the transmission of
+ * the function #HAL_UartSendBlocking.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the sending.
+ */
+hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle);
+
+/*! @}*/
+
+#else
+
+/*!
+ * @name Functional API with non-blocking mode.
+ * @note The functional API and the transactional API cannot be used at the same time. The macro
+ * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the
+ * functional API with non-blocking mode will be used. Otherwise, transactional API will be used.
+ * @{
+ */
+
+/*!
+ * @brief Installs a callback and callback parameter.
+ *
+ * This function is used to install the callback and callback parameter for UART module.
+ * When non-blocking sending or receiving finished, the adapter will notify the upper layer by the installed callback
+ * function. And the status is also passed as status parameter when the callback is called.
+ *
+ * @param handle UART handle pointer.
+ * @param callback The callback function.
+ * @param callbackParam The parameter of the callback function.
+ * @retval kStatus_HAL_UartSuccess Successfully install the callback.
+ */
+hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle,
+ hal_uart_transfer_callback_t callback,
+ void *callbackParam);
+
+/*!
+ * @brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be received.
+ * The receive request is saved by the UART adapter.
+ * When the new data arrives, the receive request is serviced first.
+ * When all data is received, the UART adapter notifies the upper layer
+ * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle.
+ *
+ * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartReceiveNonBlocking
+ * cannot be used at the same time.
+ *
+ * @param handle UART handle pointer.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue.
+ * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
+
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the ISR, the UART driver calls the callback
+ * function and passes the @ref kStatus_UART_TxIdle as status parameter.
+ *
+ * @note The function #HAL_UartSendBlocking and the function #HAL_UartSendNonBlocking
+ * cannot be used at the same time.
+ *
+ * @param handle UART handle pointer.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_HAL_UartSuccess Successfully start the data transmission.
+ * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
+
+/*!
+ * @brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param handle UART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_HAL_UartError An error occurred.
+ * @retval kStatus_Success Get successfully through the parameter \p count.
+ */
+hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount);
+
+/*!
+ * @brief Gets the number of bytes written to the UART TX register.
+ *
+ * This function gets the number of bytes written to the UART TX
+ * register by using the interrupt method.
+ *
+ * @param handle UART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_HAL_UartError An error occurred.
+ * @retval kStatus_Success Get successfully through the parameter \p count.
+ */
+hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
+ * how many bytes are not received yet.
+ *
+ * @note The function #HAL_UartAbortReceive cannot be used to abort the transmission of
+ * the function #HAL_UartReceiveBlocking.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the receiving.
+ */
+hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle);
+
+/*!
+ * @brief Aborts the interrupt-driven data sending.
+ *
+ * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out
+ * how many bytes are not sent out.
+ *
+ * @note The function #HAL_UartAbortSend cannot be used to abort the transmission of
+ * the function #HAL_UartSendBlocking.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the sending.
+ */
+hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle);
+
+/*! @}*/
+
+#endif
+#endif
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+/*!
+ * @brief UART IRQ handle function.
+ *
+ * This function handles the UART transmit and receive IRQ request.
+ *
+ * @param handle UART handle pointer.
+ */
+void HAL_UartIsrFunction(hal_uart_handle_t handle);
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+/*! @}*/
+#endif /* __HAL_UART_ADAPTER_H__ */
diff --git a/third_party/nxp/K32W061DK6/components/uart/usart_adapter.c b/third_party/nxp/K32W061DK6/components/uart/usart_adapter.c
new file mode 100755
index 0000000..9b04160
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/components/uart/usart_adapter.c
@@ -0,0 +1,629 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_usart.h"
+#include "fsl_flexcomm.h"
+
+#include "uart.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#ifndef NDEBUG
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
+#undef assert
+#define assert(n)
+#endif
+#endif
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+/*! @brief uart RX state structure. */
+typedef struct _hal_uart_receive_state
+{
+ volatile uint8_t *buffer;
+ volatile uint32_t bufferLength;
+ volatile uint32_t bufferSofar;
+} hal_uart_receive_state_t;
+
+/*! @brief uart TX state structure. */
+typedef struct _hal_uart_send_state
+{
+ volatile uint8_t *buffer;
+ volatile uint32_t bufferLength;
+ volatile uint32_t bufferSofar;
+} hal_uart_send_state_t;
+#endif
+/*! @brief uart state structure. */
+typedef struct _hal_uart_state
+{
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+ hal_uart_transfer_callback_t callback;
+ void *callbackParam;
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ usart_handle_t hardwareHandle;
+#endif
+ hal_uart_receive_state_t rx;
+ hal_uart_send_state_t tx;
+#endif
+ uint8_t instance;
+} hal_uart_state_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static USART_Type *const s_UsartAdapterBase[] = USART_BASE_PTRS;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+/* Array of USART IRQ number. */
+static const IRQn_Type s_UsartIRQ[] = USART_IRQS;
+#endif
+
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+static hal_uart_status_t HAL_UartGetStatus(status_t status)
+{
+ hal_uart_status_t uartStatus = kStatus_HAL_UartError;
+ switch (status)
+ {
+ case kStatus_Success:
+ uartStatus = kStatus_HAL_UartSuccess;
+ break;
+ case kStatus_USART_TxBusy:
+ uartStatus = kStatus_HAL_UartTxBusy;
+ break;
+ case kStatus_USART_RxBusy:
+ uartStatus = kStatus_HAL_UartRxBusy;
+ break;
+ case kStatus_USART_TxIdle:
+ uartStatus = kStatus_HAL_UartTxIdle;
+ break;
+ case kStatus_USART_RxIdle:
+ uartStatus = kStatus_HAL_UartRxIdle;
+ break;
+ case kStatus_USART_BaudrateNotSupport:
+ uartStatus = kStatus_HAL_UartBaudrateNotSupport;
+ break;
+ case kStatus_USART_NoiseError:
+ case kStatus_USART_FramingError:
+ case kStatus_USART_ParityError:
+ uartStatus = kStatus_HAL_UartProtocolError;
+ break;
+ default:
+ break;
+ }
+ return uartStatus;
+}
+#else
+static hal_uart_status_t HAL_UartGetStatus(status_t status)
+{
+ if (kStatus_Success == status)
+ {
+ return kStatus_HAL_UartSuccess;
+ }
+ else
+ {
+ return kStatus_HAL_UartError;
+ }
+}
+#endif
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+static void HAL_UartCallback(USART_Type *base, usart_handle_t *handle, status_t status, void *callbackParam)
+{
+ hal_uart_state_t *uartHandle;
+ hal_uart_status_t uartStatus = HAL_UartGetStatus(status);
+ assert(callbackParam);
+
+ uartHandle = (hal_uart_state_t *)callbackParam;
+
+ if (kStatus_HAL_UartProtocolError == uartStatus)
+ {
+ if (uartHandle->hardwareHandle.rxDataSize)
+ {
+ uartStatus = kStatus_HAL_UartError;
+ }
+ }
+
+ if (uartHandle->callback)
+ {
+ uartHandle->callback(uartHandle, uartStatus, uartHandle->callbackParam);
+ }
+}
+
+#else
+
+static void HAL_UartInterruptHandle(USART_Type *base, void *handle)
+{
+ hal_uart_state_t *uartHandle = (hal_uart_state_t *)handle;
+ uint32_t status;
+ uint8_t instance;
+
+ if (NULL == uartHandle)
+ {
+ return;
+ }
+ instance = uartHandle->instance;
+
+ status = USART_GetStatusFlags(s_UsartAdapterBase[instance]);
+
+ /* Receive data register full */
+ if ((USART_FIFOSTAT_RXNOTEMPTY_MASK & status) &&
+ (USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_RXLVL_MASK))
+ {
+ if (uartHandle->rx.buffer)
+ {
+ uartHandle->rx.buffer[uartHandle->rx.bufferSofar++] = USART_ReadByte(s_UsartAdapterBase[instance]);
+ if (uartHandle->rx.bufferSofar >= uartHandle->rx.bufferLength)
+ {
+ USART_DisableInterrupts(s_UsartAdapterBase[instance],
+ USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK);
+ uartHandle->rx.buffer = NULL;
+ if (uartHandle->callback)
+ {
+ uartHandle->callback(uartHandle, kStatus_HAL_UartRxIdle, uartHandle->callbackParam);
+ }
+ }
+ }
+ }
+
+ /* Send data register empty and the interrupt is enabled. */
+ if ((USART_FIFOSTAT_TXNOTFULL_MASK & status) &&
+ (USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_TXLVL_MASK))
+ {
+ if (uartHandle->tx.buffer)
+ {
+ USART_WriteByte(s_UsartAdapterBase[instance], uartHandle->tx.buffer[uartHandle->tx.bufferSofar++]);
+ if (uartHandle->tx.bufferSofar >= uartHandle->tx.bufferLength)
+ {
+ USART_DisableInterrupts(s_UsartAdapterBase[instance], USART_FIFOINTENCLR_TXLVL_MASK);
+ uartHandle->tx.buffer = NULL;
+ if (uartHandle->callback)
+ {
+ uartHandle->callback(uartHandle, kStatus_HAL_UartTxIdle, uartHandle->callbackParam);
+ }
+ }
+ }
+ }
+
+#if 1
+ USART_ClearStatusFlags(s_UsartAdapterBase[instance], status);
+#endif
+}
+#endif
+
+#endif
+
+hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, hal_uart_config_t *config)
+{
+ hal_uart_state_t *uartHandle;
+ usart_config_t usartConfig;
+ status_t status;
+ assert(handle);
+ assert(config);
+ assert(config->instance < (sizeof(s_UsartAdapterBase) / sizeof(USART_Type *)));
+ assert(s_UsartAdapterBase[config->instance]);
+
+ if (HAL_UART_HANDLE_SIZE < sizeof(hal_uart_state_t))
+ {
+ return kStatus_HAL_UartError;
+ }
+
+ USART_GetDefaultConfig(&usartConfig);
+ usartConfig.baudRate_Bps = config->baudRate_Bps;
+
+ if (kHAL_UartParityEven == config->parityMode)
+ {
+ usartConfig.parityMode = kUSART_ParityEven;
+ }
+ else if (kHAL_UartParityOdd == config->parityMode)
+ {
+ usartConfig.parityMode = kUSART_ParityOdd;
+ }
+ else
+ {
+ usartConfig.parityMode = kUSART_ParityDisabled;
+ }
+
+ if (kHAL_UartTwoStopBit == config->stopBitCount)
+ {
+ usartConfig.stopBitCount = kUSART_TwoStopBit;
+ }
+ else
+ {
+ usartConfig.stopBitCount = kUSART_OneStopBit;
+ }
+ usartConfig.enableRx = config->enableRx;
+ usartConfig.enableTx = config->enableTx;
+ usartConfig.txWatermark = kUSART_TxFifo0;
+ usartConfig.rxWatermark = kUSART_RxFifo1;
+
+ status = USART_Init(s_UsartAdapterBase[config->instance], &usartConfig, config->srcClock_Hz);
+
+ if (kStatus_Success != status)
+ {
+ return HAL_UartGetStatus(status);
+ }
+
+ uartHandle = (hal_uart_state_t *)handle;
+ uartHandle->instance = config->instance;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ USART_TransferCreateHandle(s_UsartAdapterBase[config->instance], &uartHandle->hardwareHandle,
+ (usart_transfer_callback_t)HAL_UartCallback, handle);
+#else
+ /* Enable interrupt in NVIC. */
+ FLEXCOMM_SetIRQHandler(s_UsartAdapterBase[config->instance], (flexcomm_irq_handler_t)HAL_UartInterruptHandle,
+ handle);
+ NVIC_SetPriority((IRQn_Type)s_UsartIRQ[config->instance], HAL_UART_ISR_PRIORITY);
+ EnableIRQ(s_UsartIRQ[config->instance]);
+#endif
+
+#endif
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+
+ assert(handle);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ USART_Deinit(s_UsartAdapterBase[uartHandle->instance]);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(data);
+ assert(length);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+ if (uartHandle->rx.buffer)
+ {
+ return kStatus_HAL_UartRxBusy;
+ }
+#endif
+
+ status = USART_ReadBlocking(s_UsartAdapterBase[uartHandle->instance], data, length);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(data);
+ assert(length);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+ if (uartHandle->tx.buffer)
+ {
+ return kStatus_HAL_UartTxBusy;
+ }
+#endif
+
+ USART_WriteBlocking(s_UsartAdapterBase[uartHandle->instance], data, length);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+
+hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle,
+ hal_uart_transfer_callback_t callback,
+ void *callbackParam)
+{
+ hal_uart_state_t *uartHandle;
+
+ assert(handle);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ uartHandle->callbackParam = callbackParam;
+ uartHandle->callback = callback;
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(transfer);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ status = USART_TransferReceiveNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle,
+ (usart_transfer_t *)transfer, NULL);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(transfer);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ status = USART_TransferSendNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle,
+ (usart_transfer_t *)transfer);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(count);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ status =
+ USART_TransferGetReceiveCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(count);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ status = USART_TransferGetSendCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ USART_TransferAbortReceive(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ USART_TransferAbortSend(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+#else
+
+/* None transactional API with non-blocking mode. */
+hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle,
+ hal_uart_transfer_callback_t callback,
+ void *callbackParam)
+{
+ hal_uart_state_t *uartHandle;
+
+ assert(handle);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ uartHandle->callbackParam = callbackParam;
+ uartHandle->callback = callback;
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(data);
+ assert(length);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (uartHandle->rx.buffer)
+ {
+ return kStatus_HAL_UartRxBusy;
+ }
+
+ uartHandle->rx.bufferLength = length;
+ uartHandle->rx.bufferSofar = 0;
+ uartHandle->rx.buffer = data;
+ USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_RXLVL_MASK);
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(data);
+ assert(length);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (uartHandle->tx.buffer)
+ {
+ return kStatus_HAL_UartTxBusy;
+ }
+ uartHandle->tx.bufferLength = length;
+ uartHandle->tx.bufferSofar = 0;
+ uartHandle->tx.buffer = (volatile uint8_t *)data;
+ USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_TXLVL_MASK);
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(reCount);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (uartHandle->rx.buffer)
+ {
+ *reCount = uartHandle->rx.bufferSofar;
+ return kStatus_HAL_UartSuccess;
+ }
+ return kStatus_HAL_UartError;
+}
+
+hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(seCount);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (uartHandle->tx.buffer)
+ {
+ *seCount = uartHandle->tx.bufferSofar;
+ return kStatus_HAL_UartSuccess;
+ }
+ return kStatus_HAL_UartError;
+}
+
+hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (uartHandle->rx.buffer)
+ {
+ USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance],
+ USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK);
+ uartHandle->rx.buffer = NULL;
+ }
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (uartHandle->tx.buffer)
+ {
+ USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENCLR_TXLVL_MASK);
+ uartHandle->tx.buffer = NULL;
+ }
+
+ return kStatus_HAL_UartSuccess;
+}
+
+#endif
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+
+void HAL_UartIsrFunction(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+#if 0
+ DisableIRQ(s_UsartIRQ[uartHandle->instance]);
+#endif
+ USART_TransferHandleIRQ(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
+#if 0
+ NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
+ EnableIRQ(s_UsartIRQ[uartHandle->instance]);
+#endif
+}
+
+#else
+
+void HAL_UartIsrFunction(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+#if 0
+ DisableIRQ(s_UsartIRQ[uartHandle->instance]);
+#endif
+ HAL_UartInterruptHandle(s_UsartAdapterBase[uartHandle->instance], (void *)uartHandle);
+#if 0
+ NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
+ EnableIRQ(s_UsartIRQ[uartHandle->instance]);
+#endif
+}
+
+#endif
+
+#endif
diff --git a/third_party/nxp/JN5189/JN5189.h b/third_party/nxp/K32W061DK6/devices/K32W061/K32W061.h
similarity index 94%
copy from third_party/nxp/JN5189/JN5189.h
copy to third_party/nxp/K32W061DK6/devices/K32W061/K32W061.h
index 8fff510..fa8ccb7 100755
--- a/third_party/nxp/JN5189/JN5189.h
+++ b/third_party/nxp/K32W061DK6/devices/K32W061/K32W061.h
@@ -1,22 +1,22 @@
/*
** ###################################################################
-** Processors: JN5189HN
-** JN5189THN
+** Processors: K32W041HN
+** K32W061HN
**
** Compilers: GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
** Keil ARM C/C++ Compiler
** MCUXpresso Compiler
**
-** Reference manual: QN9090 User manual Rev.0.3 13 September 2018
-** Version: rev. 1.0, 2018-07-31
-** Build: b190827
+** Reference manual: K32W061UM_Rev.0.3 20 December 2019
+** Version: rev. 1.0, 2019-11-05
+** Build: b200228
**
** Abstract:
-** CMSIS Peripheral Access Layer for JN5189
+** CMSIS Peripheral Access Layer for K32W061
**
** Copyright 1997-2016 Freescale Semiconductor, Inc.
-** Copyright 2016-2019 NXP
+** Copyright 2016-2020 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
@@ -25,23 +25,23 @@
** mail: support@nxp.com
**
** Revisions:
-** - rev. 1.0 (2018-07-31)
+** - rev. 1.0 (2019-11-05)
** Initial version.
**
** ###################################################################
*/
/*!
- * @file JN5189.h
+ * @file K32W061.h
* @version 1.0
- * @date 2018-07-31
- * @brief CMSIS Peripheral Access Layer for JN5189
+ * @date 2019-11-05
+ * @brief CMSIS Peripheral Access Layer for K32W061
*
- * CMSIS Peripheral Access Layer for JN5189
+ * CMSIS Peripheral Access Layer for K32W061
*/
-#ifndef _JN5189_H_
-#define _JN5189_H_ /**< Symbol preventing repeated inclusion */
+#ifndef _K32W061_H_
+#define _K32W061_H_ /**< Symbol preventing repeated inclusion */
/** Memory map major version (memory maps with equal major version number are
* compatible) */
@@ -156,7 +156,7 @@
#define __FPU_PRESENT 0 /**< Defines if an FPU is present or not */
#include "core_cm4.h" /* Core Peripheral Access Layer */
-#include "system_JN5189.h" /* Device specific configuration file */
+#include "system_K32W061.h" /* Device specific configuration file */
/*!
* @}
@@ -164,6 +164,63 @@
/* ----------------------------------------------------------------------------
+ -- Mapping Information
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*!
+ * @addtogroup dma_request
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the DMA hardware request
+ *
+ * Defines the structure for the DMA hardware request collections. The user can configure the
+ * hardware request to trigger the DMA transfer accordingly. The index
+ * of the hardware request varies according to the to SoC.
+ */
+typedef enum _dma_request_source
+{
+ kDmaRequestUsart0Rx = 0U, /**< USART 0 RX */
+ kDmaRequestUsart0Tx = 1U, /**< USART 0 TX */
+ kDmaRequestUsart1Rx = 2U, /**< USART 1 RX */
+ kDmaRequestUsart1Tx = 3U, /**< USART 1 TX */
+ kDmaRequestI2c0Slave = 4U, /**< I2C 0 Slave */
+ kDmaRequestI2c0Master = 5U, /**< I2C 0 Master */
+ kDmaRequestI2c1Slave = 6U, /**< I2C 1 Slave */
+ kDmaRequestI2c1Master = 7U, /**< I2C 1 Master */
+ kDmaRequestSpi0Rx = 8U, /**< SPI 0 RX */
+ kDmaRequestSpi0Tx = 9U, /**< SPI 0 TX */
+ kDmaRequestSpi1Rx = 10U, /**< SPI 1 RX */
+ kDmaRequestSpi1Tx = 11U, /**< SPI 1 TX */
+ kDmaRequestSPIFI = 12U, /**< SPIFI */
+ kDmaRequestI2c2Slave = 13U, /**< I2C 2 Slave */
+ kDmaRequestI2c2Master = 14U, /**< I2C 2 Master */
+ kDmaRequestDMIC0 = 15U, /**< DMIC Channel 0 */
+ kDmaRequestDMIC1 = 16U, /**< DMIC Channel 1 */
+ kDmaRequestHashRx = 17U, /**< Hash RX */
+ kDmaRequestHashTx = 18U, /**< Hash TX */
+} dma_request_source_t;
+
+/* @} */
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
+/* ----------------------------------------------------------------------------
-- Device Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -848,13 +905,6 @@
* damage the device. '11': Not used
*/
#define ADC_GPADC_CTRL0_TEST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GPADC_CTRL0_TEST_SHIFT)) & ADC_GPADC_CTRL0_TEST_MASK)
-#define ADC_GPADC_CTRL0_SEL_ATB_MASK (0x30000U)
-#define ADC_GPADC_CTRL0_SEL_ATB_SHIFT (16U)
-/*! SEL_ATB - Select analog test bus '00': normal mode '01': atb_p = out_ana(LDO_output) atb_n =
- * Vssa (LDO analog ground) '10': atb_p = out_ref (LDO output) atb_n = Vrefn (ADC negative
- * reference) '11': atb_p = out_ana (LDO output) atb_n = ADC (ADC analog ground)
- */
-#define ADC_GPADC_CTRL0_SEL_ATB(x) (((uint32_t)(((uint32_t)(x)) << ADC_GPADC_CTRL0_SEL_ATB_SHIFT)) & ADC_GPADC_CTRL0_SEL_ATB_MASK)
/*! @} */
/*! @name GPADC_CTRL1 - Third ADC Control register : ADC internal gain and offset */
@@ -906,22 +956,10 @@
/** AES - Register Layout Typedef */
typedef struct {
- union { /* offset: 0x0 */
- __IO uint32_t CFG; /**< AES Configuration register, offset: 0x0 */
- struct { /* offset: 0x0 */
- union { /* offset: 0x0 */
- __IO uint16_t CFG0_15; /**< AES Configuration register 0:15, offset: 0x0 */
- struct { /* offset: 0x0 */
- __IO uint8_t CFG0_7; /**< AES Configuration register 0:7, offset: 0x0 */
- __IO uint8_t CFG8_15; /**< AES Configuration register 8:15, offset: 0x1 */
- } CFGL;
- };
- __IO uint16_t CFG16_31; /**< AES Configuration register 16:31, offset: 0x2 */
- } CFG0_32;
- };
- __IO uint32_t CMD; /**< AES Command register, offset: 0x4 */
- __IO uint32_t STAT; /**< AES Status register, offset: 0x8 */
- __IO uint32_t CTR_INCR; /**< Counter Increment, offset: 0xC */
+ __IO uint32_t CFG; /**< Configuration, offset: 0x0 */
+ __IO uint32_t CMD; /**< Command, offset: 0x4 */
+ __IO uint32_t STAT; /**< Status, offset: 0x8 */
+ __IO uint32_t CTR_INCR; /**< Counter Increment. Increment value for HOLDING when in Counter modes, offset: 0xC */
uint8_t RESERVED_0[16];
__O uint32_t KEY[8]; /**< Bits of the AES key, array offset: 0x20, array step: 0x4 */
__O uint32_t INTEXT[4]; /**< Input text bits, array offset: 0x40, array step: 0x4 */
@@ -941,220 +979,127 @@
* @{
*/
-/*! @name CFG - AES Configuration register */
+/*! @name CFG - Configuration */
/*! @{ */
#define AES_CFG_PROC_EN_MASK (0x3U)
#define AES_CFG_PROC_EN_SHIFT (0U)
-/*! PROC_EN - Process type enable.
+/*! PROC_EN - Processing Mode Enable. 00: Reserved. 01: Encrypt/Decrypt Only. 10: GF128 Hash Only. 11: Encrypt/Decrypt and Hash.
*/
#define AES_CFG_PROC_EN(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_PROC_EN_SHIFT)) & AES_CFG_PROC_EN_MASK)
#define AES_CFG_GF128_SEL_MASK (0x4U)
#define AES_CFG_GF128_SEL_SHIFT (2U)
-/*! GF128_SEL - GF128 hash selection.
+/*! GF128_SEL - GF128 Select Mode. 0: GF128 Hash Input Text. 1: GF128 Hash Output Text.
*/
#define AES_CFG_GF128_SEL(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_GF128_SEL_SHIFT)) & AES_CFG_GF128_SEL_MASK)
#define AES_CFG_INTEXT_BSWAP_MASK (0x10U)
#define AES_CFG_INTEXT_BSWAP_SHIFT (4U)
-/*! INTEXT_BSWAP - Byte swap input text.
+/*! INTEXT_BSWAP - Input Text Byte Swap
*/
#define AES_CFG_INTEXT_BSWAP(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_INTEXT_BSWAP_SHIFT)) & AES_CFG_INTEXT_BSWAP_MASK)
#define AES_CFG_INTEXT_WSWAP_MASK (0x20U)
#define AES_CFG_INTEXT_WSWAP_SHIFT (5U)
-/*! INTEXT_WSWAP - Word swap input text.
+/*! INTEXT_WSWAP - Input Text Word Swap
*/
#define AES_CFG_INTEXT_WSWAP(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_INTEXT_WSWAP_SHIFT)) & AES_CFG_INTEXT_WSWAP_MASK)
#define AES_CFG_OUTTEXT_BSWAP_MASK (0x40U)
#define AES_CFG_OUTTEXT_BSWAP_SHIFT (6U)
-/*! OUTTEXT_BSWAP - Byte swap output text.
+/*! OUTTEXT_BSWAP - Output Text Byte Swap
*/
#define AES_CFG_OUTTEXT_BSWAP(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_OUTTEXT_BSWAP_SHIFT)) & AES_CFG_OUTTEXT_BSWAP_MASK)
#define AES_CFG_OUTTEXT_WSWAP_MASK (0x80U)
#define AES_CFG_OUTTEXT_WSWAP_SHIFT (7U)
-/*! OUTTEXT_WSWAP - Word swap output text.
+/*! OUTTEXT_WSWAP - Output Text Word Swap
*/
#define AES_CFG_OUTTEXT_WSWAP(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_OUTTEXT_WSWAP_SHIFT)) & AES_CFG_OUTTEXT_WSWAP_MASK)
#define AES_CFG_KEY_CFG_MASK (0x300U)
#define AES_CFG_KEY_CFG_SHIFT (8U)
-/*! KEY_CFG - Key Configuration.
+/*! KEY_CFG - Key Configuration. 00: 128 Bit Key. 01: 192 Bit Key. 10: 256 Bit Key. 11: Reserved.
*/
#define AES_CFG_KEY_CFG(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_KEY_CFG_SHIFT)) & AES_CFG_KEY_CFG_MASK)
#define AES_CFG_INBLK_SEL_MASK (0x30000U)
#define AES_CFG_INBLK_SEL_SHIFT (16U)
-/*! INBLK_SEL - Input block select.
+/*! INBLK_SEL - Input Block Selection From: 00: Reserved. 01: Input Text. 10: Holding. 11: Input Text XOR Holding.
*/
#define AES_CFG_INBLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_INBLK_SEL_SHIFT)) & AES_CFG_INBLK_SEL_MASK)
#define AES_CFG_HOLD_SEL_MASK (0x300000U)
#define AES_CFG_HOLD_SEL_SHIFT (20U)
-/*! HOLD_SEL - Holding register source select.
+/*! HOLD_SEL - Holding Select From: 00: Counter. 01: Input Text. 10: Output Block. 11: Input Text XOR Output Block.
*/
#define AES_CFG_HOLD_SEL(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_HOLD_SEL_SHIFT)) & AES_CFG_HOLD_SEL_MASK)
#define AES_CFG_OUTTEXT_SEL_MASK (0x3000000U)
#define AES_CFG_OUTTEXT_SEL_SHIFT (24U)
-/*! OUTTEXT_SEL - Output text source select.
+/*! OUTTEXT_SEL - Output Text Selection From: 00: Output Block. 01: Output Block XOR Input Text. 10:
+ * Output Block XOR Holding. 11: Reserved.
*/
#define AES_CFG_OUTTEXT_SEL(x) (((uint32_t)(((uint32_t)(x)) << AES_CFG_OUTTEXT_SEL_SHIFT)) & AES_CFG_OUTTEXT_SEL_MASK)
/*! @} */
-/*! @name CFG0_15 - AES Configuration register 0:15 */
+/*! @name CMD - Command */
/*! @{ */
-#define AES_CFG0_15_PROC_EN_MASK (0x3U)
-#define AES_CFG0_15_PROC_EN_SHIFT (0U)
-/*! PROC_EN - Process type enable.
+#define AES_CMD_COPY_SKEY_MASK (0x1U)
+#define AES_CMD_COPY_SKEY_SHIFT (0U)
+/*! COPY_SKEY - Copies Secret Key and enables cipher. Secret key is typically held in OTP or other secure memory.
*/
-#define AES_CFG0_15_PROC_EN(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_PROC_EN_SHIFT)) & AES_CFG0_15_PROC_EN_MASK)
-#define AES_CFG0_15_GF128_SEL_MASK (0x4U)
-#define AES_CFG0_15_GF128_SEL_SHIFT (2U)
-/*! GF128_SEL - GF128 hash selection.
- */
-#define AES_CFG0_15_GF128_SEL(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_GF128_SEL_SHIFT)) & AES_CFG0_15_GF128_SEL_MASK)
-#define AES_CFG0_15_INTEXT_BSWAP_MASK (0x10U)
-#define AES_CFG0_15_INTEXT_BSWAP_SHIFT (4U)
-/*! INTEXT_BSWAP - Byte swap input text.
- */
-#define AES_CFG0_15_INTEXT_BSWAP(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_INTEXT_BSWAP_SHIFT)) & AES_CFG0_15_INTEXT_BSWAP_MASK)
-#define AES_CFG0_15_INTEXT_WSWAP_MASK (0x20U)
-#define AES_CFG0_15_INTEXT_WSWAP_SHIFT (5U)
-/*! INTEXT_WSWAP - Word swap input text.
- */
-#define AES_CFG0_15_INTEXT_WSWAP(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_INTEXT_WSWAP_SHIFT)) & AES_CFG0_15_INTEXT_WSWAP_MASK)
-#define AES_CFG0_15_OUTTEXT_BSWAP_MASK (0x40U)
-#define AES_CFG0_15_OUTTEXT_BSWAP_SHIFT (6U)
-/*! OUTTEXT_BSWAP - Byte swap output text.
- */
-#define AES_CFG0_15_OUTTEXT_BSWAP(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_OUTTEXT_BSWAP_SHIFT)) & AES_CFG0_15_OUTTEXT_BSWAP_MASK)
-#define AES_CFG0_15_OUTTEXT_WSWAP_MASK (0x80U)
-#define AES_CFG0_15_OUTTEXT_WSWAP_SHIFT (7U)
-/*! OUTTEXT_WSWAP - Word swap output text.
- */
-#define AES_CFG0_15_OUTTEXT_WSWAP(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_OUTTEXT_WSWAP_SHIFT)) & AES_CFG0_15_OUTTEXT_WSWAP_MASK)
-#define AES_CFG0_15_KEY_CFG_MASK (0x300U)
-#define AES_CFG0_15_KEY_CFG_SHIFT (8U)
-/*! KEY_CFG - Key Configuration.
- */
-#define AES_CFG0_15_KEY_CFG(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG0_15_KEY_CFG_SHIFT)) & AES_CFG0_15_KEY_CFG_MASK)
-/*! @} */
-
-/*! @name CFG0_7 - AES Configuration register 0:7 */
-/*! @{ */
-#define AES_CFG0_7_PROC_EN_MASK (0x3U)
-#define AES_CFG0_7_PROC_EN_SHIFT (0U)
-/*! PROC_EN - Process type enable.
- */
-#define AES_CFG0_7_PROC_EN(x) (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_PROC_EN_SHIFT)) & AES_CFG0_7_PROC_EN_MASK)
-#define AES_CFG0_7_GF128_SEL_MASK (0x4U)
-#define AES_CFG0_7_GF128_SEL_SHIFT (2U)
-/*! GF128_SEL - GF128 hash selection.
- */
-#define AES_CFG0_7_GF128_SEL(x) (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_GF128_SEL_SHIFT)) & AES_CFG0_7_GF128_SEL_MASK)
-#define AES_CFG0_7_INTEXT_BSWAP_MASK (0x10U)
-#define AES_CFG0_7_INTEXT_BSWAP_SHIFT (4U)
-/*! INTEXT_BSWAP - Byte swap input text.
- */
-#define AES_CFG0_7_INTEXT_BSWAP(x) (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_INTEXT_BSWAP_SHIFT)) & AES_CFG0_7_INTEXT_BSWAP_MASK)
-#define AES_CFG0_7_INTEXT_WSWAP_MASK (0x20U)
-#define AES_CFG0_7_INTEXT_WSWAP_SHIFT (5U)
-/*! INTEXT_WSWAP - Word swap input text.
- */
-#define AES_CFG0_7_INTEXT_WSWAP(x) (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_INTEXT_WSWAP_SHIFT)) & AES_CFG0_7_INTEXT_WSWAP_MASK)
-#define AES_CFG0_7_OUTTEXT_BSWAP_MASK (0x40U)
-#define AES_CFG0_7_OUTTEXT_BSWAP_SHIFT (6U)
-/*! OUTTEXT_BSWAP - Byte swap output text.
- */
-#define AES_CFG0_7_OUTTEXT_BSWAP(x) (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_OUTTEXT_BSWAP_SHIFT)) & AES_CFG0_7_OUTTEXT_BSWAP_MASK)
-#define AES_CFG0_7_OUTTEXT_WSWAP_MASK (0x80U)
-#define AES_CFG0_7_OUTTEXT_WSWAP_SHIFT (7U)
-/*! OUTTEXT_WSWAP - Word swap output text.
- */
-#define AES_CFG0_7_OUTTEXT_WSWAP(x) (((uint8_t)(((uint8_t)(x)) << AES_CFG0_7_OUTTEXT_WSWAP_SHIFT)) & AES_CFG0_7_OUTTEXT_WSWAP_MASK)
-/*! @} */
-
-/*! @name CFG8_15 - AES Configuration register 8:15 */
-/*! @{ */
-#define AES_CFG8_15_KEY_CFG_MASK (0x3U)
-#define AES_CFG8_15_KEY_CFG_SHIFT (0U)
-/*! KEY_CFG - Key Configuration.
- */
-#define AES_CFG8_15_KEY_CFG(x) (((uint8_t)(((uint8_t)(x)) << AES_CFG8_15_KEY_CFG_SHIFT)) & AES_CFG8_15_KEY_CFG_MASK)
-/*! @} */
-
-/*! @name CFG16_31 - AES Configuration register 16:31 */
-/*! @{ */
-#define AES_CFG16_31_INBLK_SEL_MASK (0x3U)
-#define AES_CFG16_31_INBLK_SEL_SHIFT (0U)
-/*! INBLK_SEL - Input block select.
- */
-#define AES_CFG16_31_INBLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG16_31_INBLK_SEL_SHIFT)) & AES_CFG16_31_INBLK_SEL_MASK)
-#define AES_CFG16_31_HOLD_SEL_MASK (0x30U)
-#define AES_CFG16_31_HOLD_SEL_SHIFT (4U)
-/*! HOLD_SEL - Holding register source select.
- */
-#define AES_CFG16_31_HOLD_SEL(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG16_31_HOLD_SEL_SHIFT)) & AES_CFG16_31_HOLD_SEL_MASK)
-#define AES_CFG16_31_OUTTEXT_SEL_MASK (0x300U)
-#define AES_CFG16_31_OUTTEXT_SEL_SHIFT (8U)
-/*! OUTTEXT_SEL - Output text source select.
- */
-#define AES_CFG16_31_OUTTEXT_SEL(x) (((uint16_t)(((uint16_t)(x)) << AES_CFG16_31_OUTTEXT_SEL_SHIFT)) & AES_CFG16_31_OUTTEXT_SEL_MASK)
-/*! @} */
-
-/*! @name CMD - AES Command register */
-/*! @{ */
+#define AES_CMD_COPY_SKEY(x) (((uint32_t)(((uint32_t)(x)) << AES_CMD_COPY_SKEY_SHIFT)) & AES_CMD_COPY_SKEY_MASK)
#define AES_CMD_COPY_TO_Y_MASK (0x2U)
#define AES_CMD_COPY_TO_Y_SHIFT (1U)
-/*! COPY_TO_Y - Copy output text to GF128Y.
+/*! COPY_TO_Y - Copies Output Text to GF128 Y. Typically used for GCM where the Hash requires a Y
+ * input which is the result of an ECB encryption of 0s. Should be performed after encryption of 0s.
*/
#define AES_CMD_COPY_TO_Y(x) (((uint32_t)(((uint32_t)(x)) << AES_CMD_COPY_TO_Y_SHIFT)) & AES_CMD_COPY_TO_Y_MASK)
#define AES_CMD_SWITCH_MODE_MASK (0x10U)
#define AES_CMD_SWITCH_MODE_SHIFT (4U)
-/*! SWITCH_MODE - When this bit is set the mode switches from forward mode (encryption) to reverse
- * mode (decryption) or reverse mode to forward mode.
+/*! SWITCH_MODE - Switches mode from Forward to Reverse or from Reverse to Forward. Must wait for
+ * Idle after command. Typically used for non-counter modes (ECB, CBC, CFB, OFB) to switch from
+ * forward to reverse mode for decryption.
*/
#define AES_CMD_SWITCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << AES_CMD_SWITCH_MODE_SHIFT)) & AES_CMD_SWITCH_MODE_MASK)
#define AES_CMD_ABORT_MASK (0x100U)
#define AES_CMD_ABORT_SHIFT (8U)
-/*! ABORT - Aborts Encrypt/Decrypt and GF128 Hash operation.
+/*! ABORT - Aborts Encrypt/Decrypt and GF128 Hash, clears INTEXT, clears OUTTEXT, and clears HOLDING
*/
#define AES_CMD_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AES_CMD_ABORT_SHIFT)) & AES_CMD_ABORT_MASK)
#define AES_CMD_WIPE_MASK (0x200U)
#define AES_CMD_WIPE_SHIFT (9U)
-/*! WIPE - When set this bit performs abort, clears KEY and GF128_Y registers and disables cipher.
+/*! WIPE - Performs Abort, clears KEY, disables cipher, and clears GF128_Y
*/
#define AES_CMD_WIPE(x) (((uint32_t)(((uint32_t)(x)) << AES_CMD_WIPE_SHIFT)) & AES_CMD_WIPE_MASK)
/*! @} */
-/*! @name STAT - AES Status register */
+/*! @name STAT - Status */
/*! @{ */
#define AES_STAT_IDLE_MASK (0x1U)
#define AES_STAT_IDLE_SHIFT (0U)
-/*! IDLE - AES engine Idle.
+/*! IDLE - When set, all state machines are idle
*/
#define AES_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << AES_STAT_IDLE_SHIFT)) & AES_STAT_IDLE_MASK)
#define AES_STAT_IN_READY_MASK (0x2U)
#define AES_STAT_IN_READY_SHIFT (1U)
-/*! IN_READY - Input text ready.
+/*! IN_READY - When set, input Text can be written
*/
#define AES_STAT_IN_READY(x) (((uint32_t)(((uint32_t)(x)) << AES_STAT_IN_READY_SHIFT)) & AES_STAT_IN_READY_MASK)
#define AES_STAT_OUT_READY_MASK (0x4U)
#define AES_STAT_OUT_READY_SHIFT (2U)
-/*! OUT_READY - Output text ready.
+/*! OUT_READY - When set, output Text can be read
*/
#define AES_STAT_OUT_READY(x) (((uint32_t)(((uint32_t)(x)) << AES_STAT_OUT_READY_SHIFT)) & AES_STAT_OUT_READY_MASK)
#define AES_STAT_REVERSE_MASK (0x10U)
#define AES_STAT_REVERSE_SHIFT (4U)
-/*! REVERSE - Reverse mode.
+/*! REVERSE - When set, Cipher in reverse mode
*/
#define AES_STAT_REVERSE(x) (((uint32_t)(((uint32_t)(x)) << AES_STAT_REVERSE_SHIFT)) & AES_STAT_REVERSE_MASK)
#define AES_STAT_KEY_VALID_MASK (0x20U)
#define AES_STAT_KEY_VALID_SHIFT (5U)
-/*! KEY_VALID - Key valid.
+/*! KEY_VALID - When set, Key is valid
*/
#define AES_STAT_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << AES_STAT_KEY_VALID_SHIFT)) & AES_STAT_KEY_VALID_MASK)
/*! @} */
-/*! @name CTR_INCR - Counter Increment */
+/*! @name CTR_INCR - Counter Increment. Increment value for HOLDING when in Counter modes */
/*! @{ */
#define AES_CTR_INCR_CTR_INCR_MASK (0xFFFFFFFFU)
#define AES_CTR_INCR_CTR_INCR_SHIFT (0U)
-/*! CTR_INCR - Increment value for HOLDING register when in counter modes.
+/*! CTR_INCR - Counter Increment. Increment value for HOLDING when in Counter modes
*/
#define AES_CTR_INCR_CTR_INCR(x) (((uint32_t)(((uint32_t)(x)) << AES_CTR_INCR_CTR_INCR_SHIFT)) & AES_CTR_INCR_CTR_INCR_MASK)
/*! @} */
@@ -1436,11 +1381,6 @@
/*! ENABLE - Temperature sensor enable
*/
#define ASYNC_SYSCON_TEMPSENSORCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_TEMPSENSORCTRL_ENABLE_SHIFT)) & ASYNC_SYSCON_TEMPSENSORCTRL_ENABLE_MASK)
-#define ASYNC_SYSCON_TEMPSENSORCTRL_SLOPE_MASK (0x2U)
-#define ASYNC_SYSCON_TEMPSENSORCTRL_SLOPE_SHIFT (1U)
-/*! SLOPE - Temperature sensor sloe selection. 0x0: Unity gain slope; 0x1: Double gain slope; Only setting 0 should be used.
- */
-#define ASYNC_SYSCON_TEMPSENSORCTRL_SLOPE(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_TEMPSENSORCTRL_SLOPE_SHIFT)) & ASYNC_SYSCON_TEMPSENSORCTRL_SLOPE_MASK)
#define ASYNC_SYSCON_TEMPSENSORCTRL_CM_MASK (0xCU)
#define ASYNC_SYSCON_TEMPSENSORCTRL_CM_SHIFT (2U)
/*! CM - Temerature sensor common mode output voltage selection: 0x0: high negative offset added;
@@ -1509,11 +1449,6 @@
/*! I2C_SCL_EHS0 - I2C_SCL IO Driver slew rate LSB. (I2C_SCL_EHS1, I2C_SCL_EHS0). RESERVED: use default value (0)
*/
#define ASYNC_SYSCON_NFCTAGPADSCTRL_I2C_SCL_EHS0(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_NFCTAGPADSCTRL_I2C_SCL_EHS0_SHIFT)) & ASYNC_SYSCON_NFCTAGPADSCTRL_I2C_SCL_EHS0_MASK)
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_I2C_SCL_INVERT_MASK (0x800U)
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_I2C_SCL_INVERT_SHIFT (11U)
-/*! I2C_SCL_INVERT - I2C_SCL, Input polarity: 0: Input function is not inverted; 1: Input function is inverted.
- */
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_I2C_SCL_INVERT(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_NFCTAGPADSCTRL_I2C_SCL_INVERT_SHIFT)) & ASYNC_SYSCON_NFCTAGPADSCTRL_I2C_SCL_INVERT_MASK)
#define ASYNC_SYSCON_NFCTAGPADSCTRL_I2C_SCL_ENZI_MASK (0x1000U)
#define ASYNC_SYSCON_NFCTAGPADSCTRL_I2C_SCL_ENZI_SHIFT (12U)
/*! I2C_SCL_ENZI - I2C_SCL Receiver enable, active high
@@ -1536,16 +1471,6 @@
* Simulated open-drain output (high drive disabled).
*/
#define ASYNC_SYSCON_NFCTAGPADSCTRL_I2C_SCL_OD(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_NFCTAGPADSCTRL_I2C_SCL_OD_SHIFT)) & ASYNC_SYSCON_NFCTAGPADSCTRL_I2C_SCL_OD_MASK)
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_INT_EPD_MASK (0x10000U)
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_INT_EPD_SHIFT (16U)
-/*! INT_EPD - Reserved. NTAG INT/FD IO cell no longer supports pull-down
- */
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_INT_EPD(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_NFCTAGPADSCTRL_INT_EPD_SHIFT)) & ASYNC_SYSCON_NFCTAGPADSCTRL_INT_EPD_MASK)
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_INT_EPUN_MASK (0x20000U)
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_INT_EPUN_SHIFT (17U)
-/*! INT_EPUN - Reserved. NTAG INT/FD IO cell pull-up always on, not configurable
- */
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_INT_EPUN(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_NFCTAGPADSCTRL_INT_EPUN_SHIFT)) & ASYNC_SYSCON_NFCTAGPADSCTRL_INT_EPUN_MASK)
#define ASYNC_SYSCON_NFCTAGPADSCTRL_INT_INVERT_MASK (0x40000U)
#define ASYNC_SYSCON_NFCTAGPADSCTRL_INT_INVERT_SHIFT (18U)
/*! INT_INVERT - NTAG INT/FD Input polarity: 0: Input function is not inverted; 1: Input function is inverted.
@@ -1578,22 +1503,6 @@
* is to use default value (0)
*/
#define ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_EHS0(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_EHS0_SHIFT)) & ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_EHS0_MASK)
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_INVERT_MASK (0x1000000U)
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_INVERT_SHIFT (24U)
-/*! VDD_INVERT - NTAG VDD Input polarity: 0: Input function is not inverted; 1: Input function is inverted.
- */
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_INVERT(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_INVERT_SHIFT)) & ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_INVERT_MASK)
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_ENZI_MASK (0x2000000U)
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_ENZI_SHIFT (25U)
-/*! VDD_ENZI - NTAG VDD Receiver enable, active high
- */
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_ENZI(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_ENZI_SHIFT)) & ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_ENZI_MASK)
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_FILTEROFF_MASK (0x4000000U)
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_FILTEROFF_SHIFT (26U)
-/*! VDD_FILTEROFF - NTAG VDD input glitch filter control: 0: Filter enabled. Noise pulses below
- * approximately 10 ns are filtered out; 1: Filter disabled. No input filtering is done.
- */
-#define ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_FILTEROFF_SHIFT)) & ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_FILTEROFF_MASK)
#define ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_EHS1_MASK (0x8000000U)
#define ASYNC_SYSCON_NFCTAGPADSCTRL_VDD_EHS1_SHIFT (27U)
/*! VDD_EHS1 - NTAG VDD IO Driver slew rate MSB. (VDD_EHS1, VDD_EHS0) sets IO cell speed when
@@ -1611,21 +1520,11 @@
/*! @name XTAL32MLDOCTRL - XTAL 32 MHz LDO control register. If XTAL has been auto started due to EFUSE XTAL32MSTART_ENA or BLE low power timers then the effect of these need disabling via SYSCON.XTAL32MCTRL before the full control by this register is possible. */
/*! @{ */
-#define ASYNC_SYSCON_XTAL32MLDOCTRL_BYPASS_MASK (0x1U)
-#define ASYNC_SYSCON_XTAL32MLDOCTRL_BYPASS_SHIFT (0U)
-/*! BYPASS - Activate LDO bypass, only required for test purposes.
- */
-#define ASYNC_SYSCON_XTAL32MLDOCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_XTAL32MLDOCTRL_BYPASS_SHIFT)) & ASYNC_SYSCON_XTAL32MLDOCTRL_BYPASS_MASK)
#define ASYNC_SYSCON_XTAL32MLDOCTRL_ENABLE_MASK (0x2U)
#define ASYNC_SYSCON_XTAL32MLDOCTRL_ENABLE_SHIFT (1U)
/*! ENABLE - Enable the LDO when set. Setting managed by software API.
*/
#define ASYNC_SYSCON_XTAL32MLDOCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_XTAL32MLDOCTRL_ENABLE_SHIFT)) & ASYNC_SYSCON_XTAL32MLDOCTRL_ENABLE_MASK)
-#define ASYNC_SYSCON_XTAL32MLDOCTRL_HIGHZ_MASK (0x4U)
-#define ASYNC_SYSCON_XTAL32MLDOCTRL_HIGHZ_SHIFT (2U)
-/*! HIGHZ - Put the output in high impedance state, only required for test purposes.
- */
-#define ASYNC_SYSCON_XTAL32MLDOCTRL_HIGHZ(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_XTAL32MLDOCTRL_HIGHZ_SHIFT)) & ASYNC_SYSCON_XTAL32MLDOCTRL_HIGHZ_MASK)
#define ASYNC_SYSCON_XTAL32MLDOCTRL_VOUT_MASK (0x38U)
#define ASYNC_SYSCON_XTAL32MLDOCTRL_VOUT_SHIFT (3U)
/*! VOUT - Adjust the output voltage level, setting managed by software API.
@@ -1734,16 +1633,6 @@
* amount of leakage current during power down.
*/
#define ASYNC_SYSCON_DCBUSCTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_DCBUSCTRL_ADDR_SHIFT)) & ASYNC_SYSCON_DCBUSCTRL_ADDR_MASK)
-#define ASYNC_SYSCON_DCBUSCTRL_MUX1_MASK (0x1E00U)
-#define ASYNC_SYSCON_DCBUSCTRL_MUX1_SHIFT (9U)
-/*! MUX1 - MUX1
- */
-#define ASYNC_SYSCON_DCBUSCTRL_MUX1(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_DCBUSCTRL_MUX1_SHIFT)) & ASYNC_SYSCON_DCBUSCTRL_MUX1_MASK)
-#define ASYNC_SYSCON_DCBUSCTRL_MUX2_MASK (0x1E000U)
-#define ASYNC_SYSCON_DCBUSCTRL_MUX2_SHIFT (13U)
-/*! MUX2 - MUX2
- */
-#define ASYNC_SYSCON_DCBUSCTRL_MUX2(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_DCBUSCTRL_MUX2_SHIFT)) & ASYNC_SYSCON_DCBUSCTRL_MUX2_MASK)
/*! @} */
/*! @name FREQMECTRL - Frequency measure register */
@@ -1819,6 +1708,62 @@
/* ----------------------------------------------------------------------------
+ -- BLE_DP_TOP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup BLE_DP_TOP_Peripheral_Access_Layer BLE_DP_TOP Peripheral Access Layer
+ * @{
+ */
+
+/** BLE_DP_TOP - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[176];
+ __IO uint32_t ANT_DIVERSITY; /**< Antenna diversity, offset: 0xB0 */
+} BLE_DP_TOP_Type;
+
+/* ----------------------------------------------------------------------------
+ -- BLE_DP_TOP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup BLE_DP_TOP_Register_Masks BLE_DP_TOP Register Masks
+ * @{
+ */
+
+/*! @name ANT_DIVERSITY - Antenna diversity */
+/*! @{ */
+#define BLE_DP_TOP_ANT_DIVERSITY_ble_ant_selected_MASK (0x1U)
+#define BLE_DP_TOP_ANT_DIVERSITY_ble_ant_selected_SHIFT (0U)
+/*! ble_ant_selected - Selection of antenna when selection mode is direct from register, see
+ * ble_ant_mode. 0: ADE is asserted. 1: ADE de-asserted. ADO is always the inverse of ADE and so is also
+ * controlled by this setting as well.
+ */
+#define BLE_DP_TOP_ANT_DIVERSITY_ble_ant_selected(x) (((uint32_t)(((uint32_t)(x)) << BLE_DP_TOP_ANT_DIVERSITY_ble_ant_selected_SHIFT)) & BLE_DP_TOP_ANT_DIVERSITY_ble_ant_selected_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group BLE_DP_TOP_Register_Masks */
+
+
+/* BLE_DP_TOP - Peripheral instance base addresses */
+/** Peripheral BLE_DP_TOP base address */
+#define BLE_DP_TOP_BASE (0x40014000u)
+/** Peripheral BLE_DP_TOP base pointer */
+#define BLE_DP_TOP ((BLE_DP_TOP_Type *)BLE_DP_TOP_BASE)
+/** Array initializer of BLE_DP_TOP peripheral base addresses */
+#define BLE_DP_TOP_BASE_ADDRS { BLE_DP_TOP_BASE }
+/** Array initializer of BLE_DP_TOP peripheral base pointers */
+#define BLE_DP_TOP_BASE_PTRS { BLE_DP_TOP }
+
+/*!
+ * @}
+ */ /* end of group BLE_DP_TOP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
-- CIC_IRB Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -2180,9 +2125,10 @@
__IO uint32_t MCR; /**< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs., offset: 0x14 */
__IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
__IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */
- __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn.0 input., array offset: 0x2C, array step: 0x4 */
+ __I uint32_t CR[2]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn.0 input., array offset: 0x2C, array step: 0x4 */
+ uint8_t RESERVED_0[8];
__IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */
- uint8_t RESERVED_0[48];
+ uint8_t RESERVED_1[48];
__IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */
__IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */
} CTIMER_Type;
@@ -2407,7 +2353,7 @@
/*! @} */
/* The count of CTIMER_CR */
-#define CTIMER_CR_COUNT (4U)
+#define CTIMER_CR_COUNT (2U)
/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
/*! @{ */
@@ -3481,12 +3427,9 @@
__IO uint32_t AUTOPROG; /**< specifies what commands are performed on AHB write, offset: 0xC */
__IO uint32_t STARTA; /**< start address for next flash command, offset: 0x10 */
__IO uint32_t STOPA; /**< end address for next flash command, if command operates on address ranges, offset: 0x14 */
- __IO uint32_t TEST; /**< test configuration register, offset: 0x18 */
- __IO uint32_t PARW; /**< parity register; Memory parity data., offset: 0x1C */
- __IO uint32_t FSQ[4]; /**< Flexible SeQuence register 0-3, array offset: 0x20, array step: 0x4 */
- uint8_t RESERVED_1[80];
- __IO uint32_t DATAW[8]; /**< data register, word 0-7; Memory data, or command parameter, or command result., array offset: 0x80, array step: 0x4 */
- uint8_t RESERVED_2[3896];
+ uint8_t RESERVED_1[104];
+ __IO uint32_t DATAW[4]; /**< data register, word 0-3; Memory data, or command parameter, or command result., array offset: 0x80, array step: 0x4 */
+ uint8_t RESERVED_2[3912];
__O uint32_t INT_CLR_ENABLE; /**< Clear interrupt enable bits, offset: 0xFD8 */
__O uint32_t INT_SET_ENABLE; /**< Set interrupt enable bits, offset: 0xFDC */
__I uint32_t INT_STATUS; /**< Interrupt status bits, offset: 0xFE0 */
@@ -3566,72 +3509,17 @@
#define FLASH_STOPA_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STOPA_STOPA_SHIFT)) & FLASH_STOPA_STOPA_MASK)
/*! @} */
-/*! @name TEST - test configuration register */
-/*! @{ */
-#define FLASH_TEST_DCM1_MASK (0xFFU)
-#define FLASH_TEST_DCM1_SHIFT (0U)
-/*! DCM1 - These bit fields select which internal signal is brought onto the DCM1/2 pads
- */
-#define FLASH_TEST_DCM1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_TEST_DCM1_SHIFT)) & FLASH_TEST_DCM1_MASK)
-#define FLASH_TEST_DCM2_MASK (0xFF00U)
-#define FLASH_TEST_DCM2_SHIFT (8U)
-/*! DCM2 - These bit fields select which internal signal is brought onto the DCM1/2 pads
- */
-#define FLASH_TEST_DCM2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_TEST_DCM2_SHIFT)) & FLASH_TEST_DCM2_MASK)
-#define FLASH_TEST_EXT48_MASK (0x10000U)
-#define FLASH_TEST_EXT48_SHIFT (16U)
-/*! EXT48 - This bit controls the extclk48mhz controller output
- */
-#define FLASH_TEST_EXT48(x) (((uint32_t)(((uint32_t)(x)) << FLASH_TEST_EXT48_SHIFT)) & FLASH_TEST_EXT48_MASK)
-/*! @} */
-
-/*! @name PARW - parity register; Memory parity data. */
-/*! @{ */
-#define FLASH_PARW_PARW_MASK (0xFFFFFFFFU)
-#define FLASH_PARW_PARW_SHIFT (0U)
-/*! PARW - parity register; Memory parity data.
- */
-#define FLASH_PARW_PARW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_PARW_PARW_SHIFT)) & FLASH_PARW_PARW_MASK)
-/*! @} */
-
-/*! @name FSQ - Flexible SeQuence register 0-3 */
-/*! @{ */
-#define FLASH_FSQ_ST1_MASK (0xFFU)
-#define FLASH_FSQ_ST1_SHIFT (0U)
-/*! ST1 - Start state of sub-sequence 1
- */
-#define FLASH_FSQ_ST1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_FSQ_ST1_SHIFT)) & FLASH_FSQ_ST1_MASK)
-#define FLASH_FSQ_EN1_MASK (0xFF00U)
-#define FLASH_FSQ_EN1_SHIFT (8U)
-/*! EN1 - End state of sub-sequence 1
- */
-#define FLASH_FSQ_EN1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_FSQ_EN1_SHIFT)) & FLASH_FSQ_EN1_MASK)
-#define FLASH_FSQ_ST2_MASK (0xFF0000U)
-#define FLASH_FSQ_ST2_SHIFT (16U)
-/*! ST2 - Start state of sub-sequence 2
- */
-#define FLASH_FSQ_ST2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_FSQ_ST2_SHIFT)) & FLASH_FSQ_ST2_MASK)
-#define FLASH_FSQ_EN2_MASK (0xFF000000U)
-#define FLASH_FSQ_EN2_SHIFT (24U)
-/*! EN2 - End state of sub-sequence 2
- */
-#define FLASH_FSQ_EN2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_FSQ_EN2_SHIFT)) & FLASH_FSQ_EN2_MASK)
-/*! @} */
-
-/* The count of FLASH_FSQ */
-#define FLASH_FSQ_COUNT (4U)
-
-/*! @name DATAW - data register, word 0-7; Memory data, or command parameter, or command result. */
+/*! @name DATAW - data register, word 0-3; Memory data, or command parameter, or command result. */
/*! @{ */
#define FLASH_DATAW_DATAW_MASK (0xFFFFFFFFU)
#define FLASH_DATAW_DATAW_SHIFT (0U)
-/*! DATAW - data register, word 0-7; Memory data, or command parameter, or command result.
+/*! DATAW - data register, word 0-3; Memory data, or command parameter, or command result.
*/
#define FLASH_DATAW_DATAW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_DATAW_DATAW_SHIFT)) & FLASH_DATAW_DATAW_MASK)
/*! @} */
/* The count of FLASH_DATAW */
-#define FLASH_DATAW_COUNT (8U)
+#define FLASH_DATAW_COUNT (4U)
/*! @name INT_CLR_ENABLE - Clear interrupt enable bits */
/*! @{ */
@@ -3969,6 +3857,7 @@
#define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6 }
/** Interrupt vectors for the FLEXCOMM peripheral type */
#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn }
+
/*!
* @}
*/ /* end of group FLEXCOMM_Peripheral_Access_Layer */
@@ -6213,11 +6102,11 @@
#define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK (0x1FU)
#define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT (0U)
/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 17). 0: ADC0 Sequence A
- * interrupt; 1: ADC0 Sequence B interrupt; 2: Timer CT32B0 Match 0; 3: Timer CT32B0 Match 1; 4:
- * Timer CT32B1 Match 0; 5: Timer CT32B1 Match 1; 6: Pin interrupt 0; 7: Pin interrupt 1; 8: Pin
- * interrupt 2; 9: Pin interrupt 3; 10: AES RX; 11: AES TX; 12: Hash RX; 13: Hash TX; 14: DMA
- * output trigger mux 0; 15: DMA output trigger mux 1; 16: DMA output trigger mux 2; 17: DMA output
- * trigger mux 3; 18- 31: reserved.
+ * interrupt; 1: Reserved; 2: Timer CT32B0 Match 0; 3: Timer CT32B0 Match 1; 4: Timer CT32B1 Match
+ * 0; 5: Timer CT32B1 Match 1; 6: Pin interrupt 0; 7: Pin interrupt 1; 8: Pin interrupt 2; 9:
+ * Pin interrupt 3; 10: AES RX; 11: AES TX; 12: Hash RX; 13: Hash TX; 14: DMA output trigger mux 0;
+ * 15: DMA output trigger mux 1; 16: DMA output trigger mux 2; 17: DMA output trigger mux 3; 18-
+ * 31: reserved.
*/
#define INPUTMUX_DMA_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK)
/*! @} */
@@ -6313,7 +6202,7 @@
/*! @{ */
#define IOCON_PIO_FUNC_MASK (0x7U)
#define IOCON_PIO_FUNC_SHIFT (0U)
-/*! FUNC - Selects digital function assigned to this pin. 0 is for GPIO mode. For other values, see IO mux
+/*! FUNC - Select digital function assigned to this pin.
* 0b000..Alternative connection 0.
* 0b001..Alternative connection 1.
* 0b010..Alternative connection 2.
@@ -6326,22 +6215,22 @@
#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK)
#define IOCON_PIO_EGP_MASK (0x8U)
#define IOCON_PIO_EGP_SHIFT (3U)
-/*! EGP - Enable GPIO mode of the IO cell. 0=IIC mode 1=GPIO mode.
+/*! EGP - GPIO Mode of IO Cell.
* 0b0..IIC mode.
* 0b1..GPIO mode.
*/
#define IOCON_PIO_EGP(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_EGP_SHIFT)) & IOCON_PIO_EGP_MASK)
#define IOCON_PIO_MODE_MASK (0x18U)
#define IOCON_PIO_MODE_SHIFT (3U)
-/*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control). For MFIO type ONLY
+/*! MODE - Select function mode (on-chip pull-up/pull-down resistor control). For MFIO type ONLY
* (all PIOs except PIO10 & 11): 0x0 : Pull-up. Pull-up resistor enabled. 0x1 : Repeater mode (bus
* keeper) 0x2 : Plain Input 0x3 : Pull-down. Pull-down resistor enabled. Note: When the register
* is related to a general purpose MFIO type pad (that is all PIOs except PIO10 & 11) - Bit [3]
* (of the register) is connected to EPD (enable pull-down) input of the MFIO pad. - Bit [4] (of
* the register) is connected to EPUN (enable pull-up NOT) input of MFIO pad.
* 0b00..Pull-up. Pull-up resistor enabled.
- * 0b01..Repeater. Repeater mode.
- * 0b10..Inactive. Inactive (no pull-down/pull-up resistor enabled).
+ * 0b01..Repeater. Repeater mode (bus keeper).
+ * 0b10..Inactive. Plain Input.
* 0b11..Pull-down. Pull-down resistor enabled.
*/
#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK)
@@ -6355,31 +6244,29 @@
#define IOCON_PIO_ECS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ECS_SHIFT)) & IOCON_PIO_ECS_MASK)
#define IOCON_PIO_EHS_MASK (0x20U)
#define IOCON_PIO_EHS_SHIFT (5U)
-/*! EHS - Speed selection bit. When IO is in GPIO mode set high for high speed GPIO, low for low
- * speed GPIO. For IIC mode this bit has no effect and the IO is always in low speed.
+/*! EHS - Speed selection. When IO is in GPIO mode set 1 for high speed GPIO, 0 for low speed GPIO.
+ * For IIC mode, this bit has no effect and the IO is always in low speed.
* 0b0..low speed for GPIO mode or i2c mode.
* 0b1..High speed for GPIO mode.
*/
#define IOCON_PIO_EHS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_EHS_SHIFT)) & IOCON_PIO_EHS_MASK)
#define IOCON_PIO_SLEW0_MASK (0x20U)
#define IOCON_PIO_SLEW0_SHIFT (5U)
-/*! SLEW0 - Driver slew rate. Note: -When the register is related to a general purpose MFIO type pad
- * (that is all PIOs except PIO10 & 11), this bit field (Bit [5]) is connected to EHS0 input of
- * the MFIO pad. To be used in combination with SLEW1 'EHS1'. The higher [EHS1,EHS0] the quicker.
+/*! SLEW0 - This bit field is used in combination with SLEW1. The higher [SLEW1,SLEW0] the quicker the IO cell slew rate.
* 0b0..Driver slew0 rate is disabled.
* 0b1..Driver slew0 rate is enabled.
*/
#define IOCON_PIO_SLEW0(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW0_SHIFT)) & IOCON_PIO_SLEW0_MASK)
#define IOCON_PIO_INVERT_MASK (0x40U)
#define IOCON_PIO_INVERT_SHIFT (6U)
-/*! INVERT - Input polarity.
+/*! INVERT - Input Polarity.
* 0b0..Disabled. Input function is not inverted.
- * 0b1..Enabled. Input is function inverted.
+ * 0b1..Enabled. Input function is inverted.
*/
#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK)
#define IOCON_PIO_DIGIMODE_MASK (0x80U)
#define IOCON_PIO_DIGIMODE_SHIFT (7U)
-/*! DIGIMODE - Select Analog/Digital mode. 0 Analog mode. 1 Digital mode. When in analog mode, the
+/*! DIGIMODE - Select Analog/Digital Mode. 0 Analog mode. 1 Digital mode. When in analog mode, the
* receiver path in the IO cell is disabled. In this mode, it is essential that the digital
* function (e.g. GPIO) is not configured as an output. Otherwise it may conflict with analog stuff
* (loopback of digital on analog input). In other words, the digital output is not automatically
@@ -6391,53 +6278,44 @@
#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK)
#define IOCON_PIO_FILTEROFF_MASK (0x100U)
#define IOCON_PIO_FILTEROFF_SHIFT (8U)
-/*! FILTEROFF - Controls input glitch filter. 0 Filter enabled. Noise pulses below approximately 1ns
- * are filtered out. 1 Filter disabled. No input filtering is done.
- * 0b0..Filter enabled. Noise pulses below approximately 10 ns are filtered out.
+/*! FILTEROFF - Controls Input Glitch Filter.
+ * 0b0..Filter enabled. Noise pulses below approximately 1 ns are filtered out.
* 0b1..Filter disabled. No input filtering is done.
*/
#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK)
#define IOCON_PIO_FSEL_MASK (0x200U)
#define IOCON_PIO_FSEL_SHIFT (9U)
-/*! FSEL - Controls input glitch filter when IO is in IIC mode.0 Noise pulses below approximately
- * 50ns are filtered out. 1 Noise pulses below approximately 10ns are filtered out. If IO is in
- * GPIO mode this control bit is irrelevant, a 3ns filter is used.
- * 0b0..In IIC mode: Noise pulses below approximately 50ns are filtered out. In GPIO mode: A 3ns filter is used.
- * 0b1..In IIC mode: Noise pulses below approximately 10ns are filtered out. In GPIO mode: A 3ns filter is used.
+/*! FSEL - Control Input Glitch Filter.
+ * 0b0..Noise pulses below approximately 50ns are filtered out.
+ * 0b1..Noise pulses below approximately 10 ns are filtered out. If IO is in GPIO mode this control bit is irrelevant, a 3 ns filter is used.
*/
#define IOCON_PIO_FSEL(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FSEL_SHIFT)) & IOCON_PIO_FSEL_MASK)
#define IOCON_PIO_SLEW1_MASK (0x200U)
#define IOCON_PIO_SLEW1_SHIFT (9U)
-/*! SLEW1 - Driver slew rate. Note, this bit field (Bit [9]) is connected to EHS1 input of the MFIO
- * pad. To be used in combination with SLEW0 'EHS0'. The higher [EHS1,EHS0] the quicker
+/*! SLEW1 - Driver Slew Rate. This bit is used in combination with SLEW0. The higher [SLEW1,SLEW0], the quicker the slew rate.
* 0b0..Driver slew1 rate is disabled.
* 0b1..Driver slew1 rate is enabled.
*/
#define IOCON_PIO_SLEW1(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW1_SHIFT)) & IOCON_PIO_SLEW1_MASK)
#define IOCON_PIO_OD_MASK (0x400U)
#define IOCON_PIO_OD_SHIFT (10U)
-/*! OD - Controls open-drain mode. 0 : Normal. Normal push-pull output 1 : Open-drain. Simulated
- * open-drain output (high drive disabled).
+/*! OD - Controls open-drain mode.
* 0b0..Normal. Normal push-pull output
* 0b1..Open-drain. Simulated open-drain output (high drive disabled).
*/
#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK)
#define IOCON_PIO_SSEL_MASK (0x800U)
#define IOCON_PIO_SSEL_SHIFT (11U)
-/*! SSEL - This bit controls the IO clamping function. - IO_CLAMP . Assert to freeze the IO. Also
- * needs SYSCON:RETENTIONCTRL set as well. Useful in power down mode. This mode is held through
- * power down cycle. Before releasing this mode on a wake-up, ensure the IO is set to the required
- * direction and value using GPIO DIR and PIN registers.
+/*! SSEL - IO Clamping Function
* 0b0..This bit controls the IO clamping function is disabled.
* 0b1..This bit controls the IO clamping function is enabled.
*/
#define IOCON_PIO_SSEL(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SSEL_SHIFT)) & IOCON_PIO_SSEL_MASK)
#define IOCON_PIO_IO_CLAMP_MASK (0x1000U)
#define IOCON_PIO_IO_CLAMP_SHIFT (12U)
-/*! IO_CLAMP - IO_CLAMP = bit [12], assert to freeze the IO. Also needs SYSCON:RETENTIONCTRL set as
- * well. Useful in power down mode. This mode is held through power down cycle. Before releasing
- * this mode on a wake-up, ensure the IO is set to the required direction and value using GPIO
- * DIR and PIN registers.
+/*! IO_CLAMP - Assert to freeze the IO. Also needs SYSCON:RETENTIONCTRL set as well. Useful in power
+ * down mode. This mode is held through power down cycle. Before releasing this mode on a
+ * wake-up, ensure the IO is set to the required direction and value using GPIO DIR and PIN registers.
* 0b0..IO_CLAMP is disabled.
* 0b1..IO_CLAMP is enabled.
*/
@@ -6496,9 +6374,9 @@
__IO uint32_t MCRL_MSB; /**< Mute card Counter RST Low register (MSB), offset: 0x2C */
__IO uint32_t MCRH_LSB; /**< Mute card Counter RST High register (LSB), offset: 0x30 */
__IO uint32_t MCRH_MSB; /**< Mute card Counter RST High register (MSB), offset: 0x34 */
- __IO uint32_t SRR; /**< Slew Rate configuration Register, offset: 0x38 */
+ uint8_t RESERVED_0[4];
__IO uint32_t URR_UTR; /**< UART Receive Register / UART Transmit Register, offset: 0x3C */
- uint8_t RESERVED_0[12];
+ uint8_t RESERVED_1[12];
__O uint32_t TOR1; /**< Time-Out Register 1, offset: 0x4C */
__O uint32_t TOR2; /**< Time-Out Register 2, offset: 0x50 */
__O uint32_t TOR3; /**< Time-Out Register 3, offset: 0x54 */
@@ -6528,6 +6406,11 @@
* soft reset is finished by reading SSR register before any further action.
*/
#define ISO7816_SSR_SOFTRESETN(x) (((uint32_t)(((uint32_t)(x)) << ISO7816_SSR_SOFTRESETN_SHIFT)) & ISO7816_SSR_SOFTRESETN_MASK)
+#define ISO7816_SSR_SEQ_EN_MASK (0x2U)
+#define ISO7816_SSR_SEQ_EN_SHIFT (1U)
+/*! SEQ_EN - Set this bit to enable the sequencer. If this field is 0b, the sequencer will not respond to the Start control bit.
+ */
+#define ISO7816_SSR_SEQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ISO7816_SSR_SEQ_EN_SHIFT)) & ISO7816_SSR_SEQ_EN_MASK)
/*! @} */
/*! @name PDR1_LSB - Programmable Divider Register (LSB) slot 1. Least significant byte of a 16-bit counter defining the ETU. The ETU counter counts a number of cycles of the Contact Interface clock, this defines the ETU. The minimum acceptable value is 0001 0000b. */
@@ -6805,15 +6688,6 @@
#define ISO7816_MCRH_MSB_MCRH_MSB(x) (((uint32_t)(((uint32_t)(x)) << ISO7816_MCRH_MSB_MCRH_MSB_SHIFT)) & ISO7816_MCRH_MSB_MCRH_MSB_MASK)
/*! @} */
-/*! @name SRR - Slew Rate configuration Register */
-/*! @{ */
-#define ISO7816_SRR_SRR_MASK (0xFFFFFFFFU)
-#define ISO7816_SRR_SRR_SHIFT (0U)
-/*! SRR - Slew Rate configuration Register
- */
-#define ISO7816_SRR_SRR(x) (((uint32_t)(((uint32_t)(x)) << ISO7816_SRR_SRR_SHIFT)) & ISO7816_SRR_SRR_MASK)
-/*! @} */
-
/*! @name URR_UTR - UART Receive Register / UART Transmit Register */
/*! @{ */
#define ISO7816_URR_UTR_URR_UTR_MASK (0xFFFFFFFFU)
@@ -7761,29 +7635,28 @@
uint8_t RESERVED_1[12];
__IO uint32_t FRO192M; /**< High Speed FRO control register This reigster is controlled by the boot code and the Low power API software. [Reset by POR, RSTN, WDT ], offset: 0x40 */
__IO uint32_t FRO1M; /**< 1 MHz Free Running Oscillator control register. [Reset by all reset sources, except ARM SystemReset], offset: 0x44 */
- __IO uint32_t FRO32K; /**< 32 KHz Free Running Oscillator (FRO) control register. [Reset by POR, RSTN, WDT ], offset: 0x48 */
- __IO uint32_t XTAL32K; /**< 32 KHz Chrystal oscillator (XTAL) control register. [Reset by all reset sources, except ARM SystemReset], offset: 0x4C */
+ uint8_t RESERVED_2[8];
__IO uint32_t ANAMUXCOMP; /**< Analog Comparator and Analog Mux control register. [Reset by all reset sources, except ARM SystemReset], offset: 0x50 */
- uint8_t RESERVED_2[12];
+ uint8_t RESERVED_3[12];
__I uint32_t PWRSWACK; /**< Power Switch acknowledge. [Reset by all reset sources, except ARM SystemReset], offset: 0x60 */
__IO uint32_t DPDWKSRC; /**< Power Down and Deep Power Down wake-up source. [Reset by POR, RSTN, WDT ], offset: 0x64 */
__I uint32_t STATUSPWR; /**< Power OK and Ready signals from various analog modules (DCDC, LDO, ). [Reset by all reset sources, except ARM SystemReset], offset: 0x68 */
__I uint32_t STATUSCLK; /**< FRO and XTAL status register. [Reset by all reset sources, except ARM SystemReset], offset: 0x6C */
__IO uint32_t RESETCAUSE; /**< Reset Cause register. [Reset by POR], offset: 0x70 */
- uint8_t RESERVED_3[12];
+ uint8_t RESERVED_4[12];
__IO uint32_t AOREG0; /**< General purpose always on domain data storage. [Reset by all reset sources, except ARM SystemReset], offset: 0x80 */
__IO uint32_t AOREG1; /**< General purpose always on domain data storage. [Reset by POR, RSTN], offset: 0x84 */
__IO uint32_t AOREG2; /**< General purpose always on domain data storage. [Reset by POR, RSTN], offset: 0x88 */
- uint8_t RESERVED_4[12];
+ uint8_t RESERVED_5[12];
__IO uint32_t DPDCTRL; /**< Configuration parameters for Power Down and Deep Power Down mode. [Reset by POR, RSTN, WDT ], offset: 0x98 */
__I uint32_t PIOPORCAP; /**< The PIOPORCAP register captures the state of GPIO at power-on-reset or pin reset. Each bit represents the power-on reset state of one GPIO pin. [Reset by POR, RSTN], offset: 0x9C */
__I uint32_t PIORESCAP; /**< The PIORESCAP0 register captures the state of GPIO port 0 when a reset other than a power-on reset or pin reset occurs. Each bit represents the reset state of one GPIO pin. [Reset by WDT, BOD, WAKEUP IO, ARM System reset ], offset: 0xA0 */
- uint8_t RESERVED_5[12];
+ uint8_t RESERVED_6[12];
__IO uint32_t PDSLEEPCFG; /**< Controls the power to various modules in Low Power modes. [Reset by all reset sources, except ARM SystemReset], offset: 0xB0 */
- uint8_t RESERVED_6[4];
+ uint8_t RESERVED_7[4];
__IO uint32_t PDRUNCFG; /**< Controls the power to various analog blocks. [Reset by all reset sources, except ARM SystemReset], offset: 0xB8 */
__I uint32_t WAKEIOCAUSE; /**< Wake-up source from Power Down and Deep Power Down modes. Allow to identify the Wake-up source from Power-Down mode or Deep Power Down mode.[Reset by POR, RSTN, WDT ], offset: 0xBC */
- uint8_t RESERVED_7[12];
+ uint8_t RESERVED_8[12];
__IO uint32_t CTRLNORST; /**< Extension of CTRL register, but never reset except by POR, offset: 0xCC */
} PMC_Type;
@@ -7826,11 +7699,6 @@
* bit does not care. Do not set unless entering Deep Power Down.
*/
#define PMC_CTRL_NTAGWAKUPRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_NTAGWAKUPRESETENABLE_SHIFT)) & PMC_CTRL_NTAGWAKUPRESETENABLE_MASK)
-#define PMC_CTRL_SELCLOCK_MASK (0x80U)
-#define PMC_CTRL_SELCLOCK_SHIFT (7U)
-/*! SELCLOCK - Select PMC functional clock : 0: 1 MHz FRO; 1: 12 MHz FRO.
- */
-#define PMC_CTRL_SELCLOCK(x) (((uint32_t)(((uint32_t)(x)) << PMC_CTRL_SELCLOCK_SHIFT)) & PMC_CTRL_SELCLOCK_MASK)
#define PMC_CTRL_SELLDOVOLTAGE_MASK (0x100U)
#define PMC_CTRL_SELLDOVOLTAGE_SHIFT (8U)
/*! SELLDOVOLTAGE - 0 = all LDOs current output levels are determined by their associated VADJ
@@ -7950,39 +7818,13 @@
/*! @name FRO192M - High Speed FRO control register This reigster is controlled by the boot code and the Low power API software. [Reset by POR, RSTN, WDT ] */
/*! @{ */
-#define PMC_FRO192M_TEMPTRIM_MASK (0x3FU)
-#define PMC_FRO192M_TEMPTRIM_SHIFT (0U)
-/*! TEMPTRIM - Temperature coefficient trimming bits. This field is used to give accurate frequency
- * for each device. The required setting is based upon calibration data sotred in OTP during
- * device test. This setting is applied by the clock driver function.
- */
-#define PMC_FRO192M_TEMPTRIM(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO192M_TEMPTRIM_SHIFT)) & PMC_FRO192M_TEMPTRIM_MASK)
-#define PMC_FRO192M_BIASTRIM_MASK (0xFC0U)
-#define PMC_FRO192M_BIASTRIM_SHIFT (6U)
-/*! BIASTRIM - Bias trimming bits (course frequency trimming). This field is used to give accurate
- * frequency for each device. The required setting is based upon calibration data sotred in OTP
- * during device test. This setting is applied by the clock driver function.
- */
-#define PMC_FRO192M_BIASTRIM(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO192M_BIASTRIM_SHIFT)) & PMC_FRO192M_BIASTRIM_MASK)
-#define PMC_FRO192M_DACTRIM_MASK (0xFF000U)
-#define PMC_FRO192M_DACTRIM_SHIFT (12U)
-/*! DACTRIM - Curdac trimming bits (fine frequency trimming). This field is used to give accurate
- * frequency for each device. The required setting is based upon calibration data sotred in OTP
- * during device test. This setting is applied by the clock driver function.
- */
-#define PMC_FRO192M_DACTRIM(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO192M_DACTRIM_SHIFT)) & PMC_FRO192M_DACTRIM_MASK)
#define PMC_FRO192M_DIVSEL_MASK (0x1F00000U)
#define PMC_FRO192M_DIVSEL_SHIFT (20U)
/*! DIVSEL - Mode of operation (which clock to output). Each bit enables a clocks as shown. Enables
* are additive meaning that two or more clocks can be enabled together. xxxx1: 12MHz enabled;
- * xxx1x: 32MHz enabled; xx1xx: 48MHz enabled; x1xxx: 64MHz enabled; 1xxxx: Not applicable.
+ * xxx1x: 32MHz enabled; xx1xx: 48MHz enabled; x1xxx: Not applicable; 1xxxx: Not applicable.
*/
#define PMC_FRO192M_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO192M_DIVSEL_SHIFT)) & PMC_FRO192M_DIVSEL_MASK)
-#define PMC_FRO192M_ATBCTRL_MASK (0x6000000U)
-#define PMC_FRO192M_ATBCTRL_SHIFT (25U)
-/*! ATBCTRL - Debug control bits to set the analog/digital test modes; only required for test purposes.
- */
-#define PMC_FRO192M_ATBCTRL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO192M_ATBCTRL_SHIFT)) & PMC_FRO192M_ATBCTRL_MASK)
/*! @} */
/*! @name FRO1M - 1 MHz Free Running Oscillator control register. [Reset by all reset sources, except ARM SystemReset] */
@@ -8006,57 +7848,6 @@
#define PMC_FRO1M_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO1M_DIVSEL_SHIFT)) & PMC_FRO1M_DIVSEL_MASK)
/*! @} */
-/*! @name FRO32K - 32 KHz Free Running Oscillator (FRO) control register. [Reset by POR, RSTN, WDT ] */
-/*! @{ */
-#define PMC_FRO32K_NTAT_MASK (0xEU)
-#define PMC_FRO32K_NTAT_SHIFT (1U)
-/*! NTAT - Temperature coefficient trimming bits. After flash initialisation this field is
- * automatically updated by HW using a value from flash.
- */
-#define PMC_FRO32K_NTAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_NTAT_SHIFT)) & PMC_FRO32K_NTAT_MASK)
-#define PMC_FRO32K_PTAT_MASK (0x70U)
-#define PMC_FRO32K_PTAT_SHIFT (4U)
-/*! PTAT - Bias trimming bits (course frequency trimming). After flash initialisation this field is
- * automatically updated by HW using a value from flash.
- */
-#define PMC_FRO32K_PTAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_PTAT_SHIFT)) & PMC_FRO32K_PTAT_MASK)
-#define PMC_FRO32K_CAPCAL_MASK (0xFF80U)
-#define PMC_FRO32K_CAPCAL_SHIFT (7U)
-/*! CAPCAL - Capacitive dac calibration bits (fine frequency trimming). After flash initialisation
- * this field is automatically updated by HW using a value from flash.
- */
-#define PMC_FRO32K_CAPCAL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_CAPCAL_SHIFT)) & PMC_FRO32K_CAPCAL_MASK)
-#define PMC_FRO32K_ATBCTRL_MASK (0x30000U)
-#define PMC_FRO32K_ATBCTRL_SHIFT (16U)
-/*! ATBCTRL - Debug control bits to set the analog/digital test modes, only required for test purposes.
- */
-#define PMC_FRO32K_ATBCTRL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_ATBCTRL_SHIFT)) & PMC_FRO32K_ATBCTRL_MASK)
-/*! @} */
-
-/*! @name XTAL32K - 32 KHz Chrystal oscillator (XTAL) control register. [Reset by all reset sources, except ARM SystemReset] */
-/*! @{ */
-#define PMC_XTAL32K_IREF_MASK (0x6U)
-#define PMC_XTAL32K_IREF_SHIFT (1U)
-/*! IREF - Reference output current selection inputs; setting managed by clock driver function.
- */
-#define PMC_XTAL32K_IREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IREF_SHIFT)) & PMC_XTAL32K_IREF_MASK)
-#define PMC_XTAL32K_TEST_MASK (0x8U)
-#define PMC_XTAL32K_TEST_SHIFT (3U)
-/*! TEST - Oscillator Test Mode, only required for test purposes.
- */
-#define PMC_XTAL32K_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_TEST_SHIFT)) & PMC_XTAL32K_TEST_MASK)
-#define PMC_XTAL32K_IBIAS_MASK (0x30U)
-#define PMC_XTAL32K_IBIAS_SHIFT (4U)
-/*! IBIAS - Control of bias current in XTAL; setting managed by clock driver function.
- */
-#define PMC_XTAL32K_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IBIAS_SHIFT)) & PMC_XTAL32K_IBIAS_MASK)
-#define PMC_XTAL32K_AMPL_MASK (0xC0U)
-#define PMC_XTAL32K_AMPL_SHIFT (6U)
-/*! AMPL - Control of Amplitude of oscillation. 00 gives lowest amplitude; setting managed by clock driver function.
- */
-#define PMC_XTAL32K_AMPL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_AMPL_SHIFT)) & PMC_XTAL32K_AMPL_MASK)
-/*! @} */
-
/*! @name ANAMUXCOMP - Analog Comparator and Analog Mux control register. [Reset by all reset sources, except ARM SystemReset] */
/*! @{ */
#define PMC_ANAMUXCOMP_COMP_HYST_MASK (0x2U)
@@ -9689,20 +9480,18 @@
/** SHA - Register Layout Typedef */
typedef struct {
__IO uint32_t CTRL; /**< Control register, offset: 0x0 */
- __I uint32_t STATUS; /**< Status register, offset: 0x4 */
+ __I uint32_t STATUS; /**< Status Regsiter, offset: 0x4 */
__IO uint32_t INTENSET; /**< Interrupt Enable and Interrupt enable set function, offset: 0x8 */
- __O uint32_t INTENCLR; /**< Interrupt Clear register, offset: 0xC */
+ __O uint32_t INTENCLR; /**< Interrupt Clear Register, offset: 0xC */
__IO uint32_t MEMCTRL; /**< Setup Master to access memory, offset: 0x10 */
__IO uint32_t MEMADDR; /**< Address to start memory access from, offset: 0x14 */
uint8_t RESERVED_0[8];
__IO uint32_t INDATA[8]; /**< Input Data register, array offset: 0x20, array step: 0x4 */
__I uint32_t DIGEST[8]; /**< DIGEST or OUTD0, 5 or 8 bytes of output data, depending upon mode, array offset: 0x40, array step: 0x4 */
- uint8_t RESERVED_1[36];
- __I uint32_t CONFIG; /**< Indicates configuration status of block, showing features supported, offset: 0x84 */
- uint8_t RESERVED_2[8];
+ uint8_t RESERVED_1[48];
__IO uint32_t MASK; /**< Mask register, offset: 0x90 */
- uint8_t RESERVED_3[44];
- __I uint32_t OUTD[8]; /**< Remaining output data for 512bit mode, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_2[3944];
+ __I uint32_t ID; /**< IP identifier, offset: 0xFFC */
} SHA_Type;
/* ----------------------------------------------------------------------------
@@ -9718,7 +9507,7 @@
/*! @{ */
#define SHA_CTRL_MODE_MASK (0x7U)
#define SHA_CTRL_MODE_SHIFT (0U)
-/*! MODE - Operational mode: 0= Disabled; 1=SHA1; 2=SHA2-256; 3=SHA2-512; 4-7= Not valid
+/*! MODE - Operational mode: 0: Disabled; 1: SHA1; 2: SHA2-256; 3: SHA2-512; 4-7: Not valid
*/
#define SHA_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << SHA_CTRL_MODE_SHIFT)) & SHA_CTRL_MODE_MASK)
#define SHA_CTRL_NEW_MASK (0x10U)
@@ -9750,13 +9539,13 @@
#define SHA_CTRL_HASHSWPB(x) (((uint32_t)(((uint32_t)(x)) << SHA_CTRL_HASHSWPB_SHIFT)) & SHA_CTRL_HASHSWPB_MASK)
/*! @} */
-/*! @name STATUS - Status register */
+/*! @name STATUS - Status Regsiter */
/*! @{ */
#define SHA_STATUS_WAITING_MASK (0x1U)
#define SHA_STATUS_WAITING_SHIFT (0U)
-/*! WAITING - 0: Not waiting for data may be disabled or may be busy. Note that for cryptographic
- * uses, this is not set if IsLast is set nor will it set until at least 1 word is read of the
- * output. 1: Waiting for data to be written in (16 words)
+/*! WAITING - Waiting Status 0: Not waiting for data may be disabled or may be busy. Note that for
+ * cryptographic uses, this is not set if IsLast is set nor will it set until at least 1 word is
+ * read of the output. 1: Waiting for data to be written in (16 words)
*/
#define SHA_STATUS_WAITING(x) (((uint32_t)(((uint32_t)(x)) << SHA_STATUS_WAITING_SHIFT)) & SHA_STATUS_WAITING_MASK)
#define SHA_STATUS_DIGEST_MASK (0x2U)
@@ -9807,7 +9596,7 @@
#define SHA_INTENSET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENSET_ERROR_SHIFT)) & SHA_INTENSET_ERROR_MASK)
/*! @} */
-/*! @name INTENCLR - Interrupt Clear register */
+/*! @name INTENCLR - Interrupt Clear Register */
/*! @{ */
#define SHA_INTENCLR_WAITING_MASK (0x1U)
#define SHA_INTENCLR_WAITING_SHIFT (0U)
@@ -9831,7 +9620,7 @@
#define SHA_MEMCTRL_MASTER_MASK (0x1U)
#define SHA_MEMCTRL_MASTER_SHIFT (0U)
/*! MASTER - Enables Mastering. 0: Mastering is not used and the normal DMA or Interrupt based model
- * is used with INDATA 1: Mastering is enabled and DMA and INDATA should not be used
+ * is used with INDATA. 1: Mastering is enabled and DMA and INDATA should not be used.
*/
#define SHA_MEMCTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SHA_MEMCTRL_MASTER_SHIFT)) & SHA_MEMCTRL_MASTER_MASK)
#define SHA_MEMCTRL_COUNT_MASK (0x7FF0000U)
@@ -9876,30 +9665,6 @@
/* The count of SHA_DIGEST */
#define SHA_DIGEST_COUNT (8U)
-/*! @name CONFIG - Indicates configuration status of block, showing features supported */
-/*! @{ */
-#define SHA_CONFIG_DUAL_MASK (0x1U)
-#define SHA_CONFIG_DUAL_SHIFT (0U)
-/*! DUAL - 1 if 2 x 512 bit buffers, 0 if only 1 x 512 bit
- */
-#define SHA_CONFIG_DUAL(x) (((uint32_t)(((uint32_t)(x)) << SHA_CONFIG_DUAL_SHIFT)) & SHA_CONFIG_DUAL_MASK)
-#define SHA_CONFIG_DMA_MASK (0x2U)
-#define SHA_CONFIG_DMA_SHIFT (1U)
-/*! DMA - 1 if DMA is connected
- */
-#define SHA_CONFIG_DMA(x) (((uint32_t)(((uint32_t)(x)) << SHA_CONFIG_DMA_SHIFT)) & SHA_CONFIG_DMA_MASK)
-#define SHA_CONFIG_AHB_MASK (0x8U)
-#define SHA_CONFIG_AHB_SHIFT (3U)
-/*! AHB - 1 if AHB master is connected
- */
-#define SHA_CONFIG_AHB(x) (((uint32_t)(((uint32_t)(x)) << SHA_CONFIG_AHB_SHIFT)) & SHA_CONFIG_AHB_MASK)
-#define SHA_CONFIG_SHA512_MASK (0x20U)
-#define SHA_CONFIG_SHA512_SHIFT (5U)
-/*! SHA512 - 1 if SHA2-512 supported
- */
-#define SHA_CONFIG_SHA512(x) (((uint32_t)(((uint32_t)(x)) << SHA_CONFIG_SHA512_SHIFT)) & SHA_CONFIG_SHA512_MASK)
-/*! @} */
-
/*! @name MASK - Mask register */
/*! @{ */
#define SHA_MASK_MASK_MASK (0xFFFFFFFFU)
@@ -9909,18 +9674,30 @@
#define SHA_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << SHA_MASK_MASK_SHIFT)) & SHA_MASK_MASK_MASK)
/*! @} */
-/*! @name OUTD - Remaining output data for 512bit mode */
+/*! @name ID - IP identifier */
/*! @{ */
-#define SHA_OUTD_OUTPUT_MASK (0xFFFFFFFFU)
-#define SHA_OUTD_OUTPUT_SHIFT (0U)
-/*! OUTPUT - For SHA512 holds the remaining 8 output values.
+#define SHA_ID_APERTURE_MASK (0xFFU)
+#define SHA_ID_APERTURE_SHIFT (0U)
+/*! APERTURE - Aperture i.e. number minus 1 of consecutive packets 4 Kbytes reserved for this IP
*/
-#define SHA_OUTD_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << SHA_OUTD_OUTPUT_SHIFT)) & SHA_OUTD_OUTPUT_MASK)
+#define SHA_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SHA_ID_APERTURE_SHIFT)) & SHA_ID_APERTURE_MASK)
+#define SHA_ID_MIN_REV_MASK (0xF00U)
+#define SHA_ID_MIN_REV_SHIFT (8U)
+/*! MIN_REV - Minor revision i.e. with no software consequences
+ */
+#define SHA_ID_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << SHA_ID_MIN_REV_SHIFT)) & SHA_ID_MIN_REV_MASK)
+#define SHA_ID_MAJ_REV_MASK (0xF000U)
+#define SHA_ID_MAJ_REV_SHIFT (12U)
+/*! MAJ_REV - Major revision i.e. implies software modifications
+ */
+#define SHA_ID_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << SHA_ID_MAJ_REV_SHIFT)) & SHA_ID_MAJ_REV_MASK)
+#define SHA_ID_ID_MASK (0xFFFF0000U)
+#define SHA_ID_ID_SHIFT (16U)
+/*! ID - Identifier. This is the unique identifier of the module
+ */
+#define SHA_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SHA_ID_ID_SHIFT)) & SHA_ID_ID_MASK)
/*! @} */
-/* The count of SHA_OUTD */
-#define SHA_OUTD_COUNT (8U)
-
/*!
* @}
@@ -10317,22 +10094,6 @@
/*! DMARX - DMA configuration for receive.
*/
#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK)
-#define SPI_FIFOCFG_WAKETX_MASK (0x4000U)
-#define SPI_FIFOCFG_WAKETX_SHIFT (14U)
-/*! WAKETX - Wakeup for transmit FIFO level. This allows the device to be woken from reduced power
- * modes (up to power-down, as long as the peripheral function works in that power mode) without
- * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
- * CPU will remain stopped until woken by another cause, such as DMA completion.
- */
-#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK)
-#define SPI_FIFOCFG_WAKERX_MASK (0x8000U)
-#define SPI_FIFOCFG_WAKERX_SHIFT (15U)
-/*! WAKERX - Wakeup for receive FIFO level. This allows the device to be woken from reduced power
- * modes (up to power-down, as long as the peripheral function works in that power mode) without
- * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU
- * will remain stopped until woken by another cause, such as DMA completion.
- */
-#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK)
#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U)
#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U)
/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
@@ -10549,13 +10310,6 @@
* the CFG register.
*/
#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
-#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U)
-#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U)
-/*! TXSSEL3_N - Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the
- * pin is active LOW by default. Remark: The active state of the SSEL3 pin is configured by bits in
- * the CFG register.
- */
-#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK)
#define SPI_FIFOWR_EOT_MASK (0x100000U)
#define SPI_FIFOWR_EOT_SHIFT (20U)
/*! EOT - End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain
@@ -10619,14 +10373,6 @@
* pin is configured by the related SPOL bit in CFG.
*/
#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK)
-#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U)
-#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U)
-/*! RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved
- * along with received data. The value will reflect the SSEL3 pin for both master and slave
- * operation. A zero indicates that a slave select is active. The actual polarity of each slave select
- * pin is configured by the related SPOL bit in CFG.
- */
-#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK)
#define SPI_FIFORD_SOT_MASK (0x100000U)
#define SPI_FIFORD_SOT_SHIFT (20U)
/*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went
@@ -10668,14 +10414,6 @@
* pin is configured by the related SPOL bit in CFG.
*/
#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK)
-#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U)
-#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U)
-/*! RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved
- * along with received data. The value will reflect the SSEL3 pin for both master and slave
- * operation. A zero indicates that a slave select is active. The actual polarity of each slave select
- * pin is configured by the related SPOL bit in CFG.
- */
-#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK)
#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U)
#define SPI_FIFORDNOPOP_SOT_SHIFT (20U)
/*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went
@@ -11178,17 +10916,15 @@
__IO uint32_t RTC1HZCLKDIV; /**< Real Time Clock divider (1 Hz clock generation. The divider is fixed to 32768), offset: 0x3AC */
uint8_t RESERVED_21[76];
__IO uint32_t CLOCKGENUPDATELOCKOUT; /**< Control clock configuration registers access (like xxxDIV, xxxSEL), offset: 0x3FC */
- uint8_t RESERVED_22[404];
- __IO uint32_t EFUSECLKCTRL; /**< eFUSE/ OPT controller clock control, offset: 0x594 */
- uint8_t RESERVED_23[4];
+ uint8_t RESERVED_22[412];
__IO uint32_t RNGCLKCTRL; /**< Random Number Generator Clocks control, offset: 0x59C */
__IO uint32_t SRAMCTRL; /**< All SRAMs common control signals, offset: 0x5A0 */
- uint8_t RESERVED_24[40];
- __IO uint32_t MODEMCTRL; /**< 32K clock enable, offset: 0x5CC */
- uint8_t RESERVED_25[4];
+ uint8_t RESERVED_23[40];
+ __IO uint32_t MODEMCTRL; /**< Modem (Bluetooth) control and 32K clock enable, offset: 0x5CC */
+ __I uint32_t MODEMSTATUS; /**< Modem (Bluetooth) status, offset: 0x5D0 */
__IO uint32_t XTAL32KCAP; /**< XTAL 32 KHz oscillator Capacitor control, offset: 0x5D4 */
__IO uint32_t XTAL32MCTRL; /**< XTAL 32 MHz oscillator control register, offset: 0x5D8 */
- uint8_t RESERVED_26[164];
+ uint8_t RESERVED_24[164];
union { /* offset: 0x680 */
struct { /* offset: 0x680 */
__IO uint32_t STARTER0; /**< Start logic 0 wake-up enable register. Enable an interrupt for wake-up from deep-sleep mode. Some bits can also control wake-up from powerdown mode, offset: 0x680 */
@@ -11196,7 +10932,7 @@
} STARTER;
__IO uint32_t STARTERS[2]; /**< Pin assign register, array offset: 0x680, array step: 0x4 */
};
- uint8_t RESERVED_27[24];
+ uint8_t RESERVED_25[24];
union { /* offset: 0x6A0 */
struct { /* offset: 0x6A0 */
__O uint32_t STARTERSET0; /**< Set bits in STARTER0, offset: 0x6A0 */
@@ -11204,7 +10940,7 @@
} STARTERSET;
__IO uint32_t STARTERSETS[2]; /**< Pin assign register, array offset: 0x6A0, array step: 0x4 */
};
- uint8_t RESERVED_28[24];
+ uint8_t RESERVED_26[24];
union { /* offset: 0x6C0 */
struct { /* offset: 0x6C0 */
__O uint32_t STARTERCLR0; /**< Clear bits in STARTER0, offset: 0x6C0 */
@@ -11212,11 +10948,11 @@
} STARTERCLR;
__IO uint32_t STARTERCLRS[2]; /**< Pin assign register, array offset: 0x6C0, array step: 0x4 */
};
- uint8_t RESERVED_29[64];
+ uint8_t RESERVED_27[64];
__IO uint32_t RETENTIONCTRL; /**< I/O retention control register, offset: 0x708 */
- uint8_t RESERVED_30[252];
+ uint8_t RESERVED_28[252];
__IO uint32_t CPSTACK; /**< CPSTACK, offset: 0x808 */
- uint8_t RESERVED_31[500];
+ uint8_t RESERVED_29[500];
__IO uint32_t ANACTRL_CTRL; /**< Analog Interrupt control register. Requires AHBCLKCTRL0.ANA_INT_CTRL to be set., offset: 0xA00 */
__I uint32_t ANACTRL_VAL; /**< Analog modules (BOD and Analog Comparator) outputs current values (BOD 'Power OK' and Analog comparator out). Requires AHBCLKCTRL0.ANA_INT_CTRL to be set., offset: 0xA04 */
__IO uint32_t ANACTRL_STAT; /**< Analog modules (BOD and Analog Comparator) interrupt status. Requires AHBCLKCTRL0.ANA_INT_CTRL to be set., offset: 0xA08 */
@@ -11224,7 +10960,7 @@
__O uint32_t ANACTRL_INTENCLR; /**< Analog modules (BOD and Analog Comparator) Interrupt Enable Clear register. Writing ones clears the corresponding interrupt enable bits. Note, interrupt enable bits are set in ANACTRL_INTENSET. Requires AHBCLKCTRL0.ANA_INT_CTRL to be set to use this register., offset: 0xA10 */
__I uint32_t ANACTRL_INTSTAT; /**< Analog modules (BOD and Analog Comparator) Interrupt Status register (masked with interrupt enable). Requires AHBCLKCTRL0.ANA_INT_CTRL to be set to use this register. Interrupt status bit are cleared using ANACTRL_STAT., offset: 0xA14 */
__IO uint32_t CLOCK_CTRL; /**< Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measure function, offset: 0xA18 */
- uint8_t RESERVED_32[4];
+ uint8_t RESERVED_30[4];
__IO uint32_t WKT_CTRL; /**< Wake-up timers control, offset: 0xA20 */
__IO uint32_t WKT_LOAD_WKT0_LSB; /**< Wake-up timer 0 reload value least significant bits ([31:0])., offset: 0xA24 */
__IO uint32_t WKT_LOAD_WKT0_MSB; /**< Wake-up timer 0 reload value most significant bits ([8:0])., offset: 0xA28 */
@@ -11236,11 +10972,11 @@
__IO uint32_t WKT_INTENSET; /**< Interrupt Enable Read and Set register, offset: 0xA40 */
__O uint32_t WKT_INTENCLR; /**< Interrupt Enable Clear register, offset: 0xA44 */
__I uint32_t WKT_INTSTAT; /**< Interrupt Status register, offset: 0xA48 */
- uint8_t RESERVED_33[956];
+ uint8_t RESERVED_31[956];
__IO uint32_t GPIOPSYNC; /**< Enable bypass of the first stage of synchonization inside GPIO_INT module., offset: 0xE08 */
- uint8_t RESERVED_34[420];
+ uint8_t RESERVED_32[420];
__I uint32_t DIEID; /**< Chip revision ID & Number, offset: 0xFB0 */
- uint8_t RESERVED_35[60];
+ uint8_t RESERVED_33[60];
__O uint32_t CODESECURITYPROT; /**< Security code to allow test access via SWD/JTAG. Reset with POR, SW reset or BOD, offset: 0xFF0 */
} SYSCON_Type;
@@ -11261,28 +10997,6 @@
* 2: Vector Table in Flash. 3: Vector Table in Flash.
*/
#define SYSCON_MEMORYREMAP_MAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_MAP_SHIFT)) & SYSCON_MEMORYREMAP_MAP_MASK)
-#define SYSCON_MEMORYREMAP_FLASH_REMAP_APP_0_MASK (0x4U)
-#define SYSCON_MEMORYREMAP_FLASH_REMAP_APP_0_SHIFT (2U)
-/*! FLASH_REMAP_APP_0 - Controls remapping of Application 0 flash space. 0: No remapping of
- * Application 0 Flash space. 1: Remapping of Application 0 Flash space.
- */
-#define SYSCON_MEMORYREMAP_FLASH_REMAP_APP_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_FLASH_REMAP_APP_0_SHIFT)) & SYSCON_MEMORYREMAP_FLASH_REMAP_APP_0_MASK)
-#define SYSCON_MEMORYREMAP_FLASH_REMAP_APP_1_MASK (0x8U)
-#define SYSCON_MEMORYREMAP_FLASH_REMAP_APP_1_SHIFT (3U)
-/*! FLASH_REMAP_APP_1 - Controls remapping of Application 1 flash space. 0: No remapping of
- * Application 0 Flash space. 1: Remapping of Application 0 Flash space.
- */
-#define SYSCON_MEMORYREMAP_FLASH_REMAP_APP_1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_FLASH_REMAP_APP_1_SHIFT)) & SYSCON_MEMORYREMAP_FLASH_REMAP_APP_1_MASK)
-#define SYSCON_MEMORYREMAP_FLASH_APP_0_SIZE_MASK (0x7F0U)
-#define SYSCON_MEMORYREMAP_FLASH_APP_0_SIZE_SHIFT (4U)
-/*! FLASH_APP_0_SIZE - Application 0 flash size, in number of 8-KB units. Max allowed value is 80 (640 KB of Flash).
- */
-#define SYSCON_MEMORYREMAP_FLASH_APP_0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_FLASH_APP_0_SIZE_SHIFT)) & SYSCON_MEMORYREMAP_FLASH_APP_0_SIZE_MASK)
-#define SYSCON_MEMORYREMAP_FLASH_APP_1_SIZE_MASK (0x7F000U)
-#define SYSCON_MEMORYREMAP_FLASH_APP_1_SIZE_SHIFT (12U)
-/*! FLASH_APP_1_SIZE - Application 1 flash size, in number of 8-KB units. Max allowed value is 80 (640 KB of Flash).
- */
-#define SYSCON_MEMORYREMAP_FLASH_APP_1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_FLASH_APP_1_SIZE_SHIFT)) & SYSCON_MEMORYREMAP_FLASH_APP_1_SIZE_MASK)
#define SYSCON_MEMORYREMAP_QSPI_REMAP_APP_0_MASK (0x300000U)
#define SYSCON_MEMORYREMAP_QSPI_REMAP_APP_0_SHIFT (20U)
/*! QSPI_REMAP_APP_0 - Address bits to use when QSPI Flash address [19:18] = 0 (256-KB unit page). Setting 00 gives no remapping.
@@ -11366,11 +11080,6 @@
/*! @name PRESETCTRL0 - Peripheral reset control 0 */
/*! @{ */
-#define SYSCON_PRESETCTRL0_FLASH_RST_MASK (0x100U)
-#define SYSCON_PRESETCTRL0_FLASH_RST_SHIFT (8U)
-/*! FLASH_RST - Flash controller reset control. 0: Clear reset to this function. 1: Assert reset to this function.
- */
-#define SYSCON_PRESETCTRL0_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLASH_RST_MASK)
#define SYSCON_PRESETCTRL0_SPIFI_RST_MASK (0x400U)
#define SYSCON_PRESETCTRL0_SPIFI_RST_SHIFT (10U)
/*! SPIFI_RST - Quad SPI Flash controller reset control. 0: Clear reset to this function. 1: Assert reset to this function.
@@ -11381,6 +11090,11 @@
/*! MUX_RST - Input Mux reset control. 0: Clear reset to this function. 1: Assert reset to this function.
*/
#define SYSCON_PRESETCTRL0_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX_RST_MASK)
+#define SYSCON_PRESETCTRL0_BLE_TIMING_GEN_RST_MASK (0x1000U)
+#define SYSCON_PRESETCTRL0_BLE_TIMING_GEN_RST_SHIFT (12U)
+/*! BLE_TIMING_GEN_RST - BLE Low Power Control module reset. 0: Clear reset to this function. 1: Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL0_BLE_TIMING_GEN_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_BLE_TIMING_GEN_RST_SHIFT)) & SYSCON_PRESETCTRL0_BLE_TIMING_GEN_RST_MASK)
#define SYSCON_PRESETCTRL0_IOCON_RST_MASK (0x2000U)
#define SYSCON_PRESETCTRL0_IOCON_RST_SHIFT (13U)
/*! IOCON_RST - I/O controller reset control. 0: Clear reset to this function. 1: Assert reset to this function.
@@ -11439,11 +11153,6 @@
/*! ADC_RST - ADC reset control. 0: Clear reset to this function. 1: Assert reset to this function.
*/
#define SYSCON_PRESETCTRL0_ADC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC_RST_SHIFT)) & SYSCON_PRESETCTRL0_ADC_RST_MASK)
-#define SYSCON_PRESETCTRL0_EFUSE_RST_MASK (0x10000000U)
-#define SYSCON_PRESETCTRL0_EFUSE_RST_SHIFT (28U)
-/*! EFUSE_RST - eFUSE / OTP Controller APB bus interface reset. 0: Clear reset to this function. 1: Assert reset to this function.
- */
-#define SYSCON_PRESETCTRL0_EFUSE_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_EFUSE_RST_SHIFT)) & SYSCON_PRESETCTRL0_EFUSE_RST_MASK)
/*! @} */
/*! @name PRESETCTRL1 - Peripheral reset control 1 */
@@ -11503,6 +11212,11 @@
/*! ZIGBEE_RST - Zigbee reset control. 0: Clear reset to this function. 1: Assert reset to this function.
*/
#define SYSCON_PRESETCTRL1_ZIGBEE_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_ZIGBEE_RST_SHIFT)) & SYSCON_PRESETCTRL1_ZIGBEE_RST_MASK)
+#define SYSCON_PRESETCTRL1_BLE_RST_MASK (0x400000U)
+#define SYSCON_PRESETCTRL1_BLE_RST_SHIFT (22U)
+/*! BLE_RST - BLE reset control. 0: Clear reset to this function. 1: Assert reset to this function.
+ */
+#define SYSCON_PRESETCTRL1_BLE_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_BLE_RST_SHIFT)) & SYSCON_PRESETCTRL1_BLE_RST_MASK)
#define SYSCON_PRESETCTRL1_MODEM_MASTER_RST_MASK (0x800000U)
#define SYSCON_PRESETCTRL1_MODEM_MASTER_RST_SHIFT (23U)
/*! MODEM_MASTER_RST - MODEM AHB Master Interface reset control. 0: Clear reset to this function. 1: Assert reset to this function.
@@ -11542,11 +11256,6 @@
/*! @name PRESETCTRLSET0 - Set bits in PRESETCTRL0. It is recommended that changes to PRESETCTRL registers be accomplished by using the related PRESETCTRLSET and PRESETCTRLCLR registers. */
/*! @{ */
-#define SYSCON_PRESETCTRLSET0_FLASH_RST_SET_MASK (0x100U)
-#define SYSCON_PRESETCTRLSET0_FLASH_RST_SET_SHIFT (8U)
-/*! FLASH_RST_SET - Writing one to this register sets the FLASH_RST bit in the PRESETCTRL0 register
- */
-#define SYSCON_PRESETCTRLSET0_FLASH_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET0_FLASH_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET0_FLASH_RST_SET_MASK)
#define SYSCON_PRESETCTRLSET0_SPIFI_RST_SET_MASK (0x400U)
#define SYSCON_PRESETCTRLSET0_SPIFI_RST_SET_SHIFT (10U)
/*! SPIFI_RST_SET - Writing one to this register sets the SPIFI_RST bit in the PRESETCTRL0 register
@@ -11557,6 +11266,11 @@
/*! MUX_RST_SET - Writing one to this register sets the MUX_RST bit in the PRESETCTRL0 register
*/
#define SYSCON_PRESETCTRLSET0_MUX_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET0_MUX_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET0_MUX_RST_SET_MASK)
+#define SYSCON_PRESETCTRLSET0_BLE_TIMING_GEN_RST_SET_MASK (0x1000U)
+#define SYSCON_PRESETCTRLSET0_BLE_TIMING_GEN_RST_SET_SHIFT (12U)
+/*! BLE_TIMING_GEN_RST_SET - Writing one to this register sets the BLE_TIMING_GEN_RST bit in the PRESETCTRL0 register
+ */
+#define SYSCON_PRESETCTRLSET0_BLE_TIMING_GEN_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET0_BLE_TIMING_GEN_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET0_BLE_TIMING_GEN_RST_SET_MASK)
#define SYSCON_PRESETCTRLSET0_IOCON_RST_SET_MASK (0x2000U)
#define SYSCON_PRESETCTRLSET0_IOCON_RST_SET_SHIFT (13U)
/*! IOCON_RST_SET - Writing one to this register sets the IOCON_RST bit in the PRESETCTRL0 register
@@ -11612,11 +11326,6 @@
/*! ADC_RST_SET - Writing one to this register sets the ADC_RST bit in the PRESETCTRL0 register
*/
#define SYSCON_PRESETCTRLSET0_ADC_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET0_ADC_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET0_ADC_RST_SET_MASK)
-#define SYSCON_PRESETCTRLSET0_EFUSE_RST_SET_MASK (0x10000000U)
-#define SYSCON_PRESETCTRLSET0_EFUSE_RST_SET_SHIFT (28U)
-/*! EFUSE_RST_SET - Writing one to this register sets the EFUSE_RST bit in the PRESETCTRL0 register
- */
-#define SYSCON_PRESETCTRLSET0_EFUSE_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET0_EFUSE_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET0_EFUSE_RST_SET_MASK)
/*! @} */
/*! @name PRESETCTRLSET1 - Set bits in PRESETCTRL1. It is recommended that changes to PRESETCTRL registers be accomplished by using the related PRESETCTRLSET and PRESETCTRLCLR registers. */
@@ -11676,6 +11385,11 @@
/*! ZIGBEE_RST_SET - Writing one to this register sets the ZIGBEE_RST bit in the PRESETCTRL1 register
*/
#define SYSCON_PRESETCTRLSET1_ZIGBEE_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET1_ZIGBEE_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET1_ZIGBEE_RST_SET_MASK)
+#define SYSCON_PRESETCTRLSET1_BLE_RST_SET_MASK (0x400000U)
+#define SYSCON_PRESETCTRLSET1_BLE_RST_SET_SHIFT (22U)
+/*! BLE_RST_SET - Writing one to this register sets the BLE_RST bit in the PRESETCTRL1 register
+ */
+#define SYSCON_PRESETCTRLSET1_BLE_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET1_BLE_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET1_BLE_RST_SET_MASK)
#define SYSCON_PRESETCTRLSET1_MODEM_MASTER_RST_SET_MASK (0x800000U)
#define SYSCON_PRESETCTRLSET1_MODEM_MASTER_RST_SET_SHIFT (23U)
/*! MODEM_MASTER_RST_SET - Writing one to this register sets the MODEM_MASTER_RST bit in the PRESETCTRL1 register
@@ -11715,11 +11429,6 @@
/*! @name PRESETCTRLCLR0 - Clear bits in PRESETCTRL0. It is recommended that changes to PRESETCTRL registers be accomplished by using the related PRESETCTRLSET and PRESETCTRLCLR registers. */
/*! @{ */
-#define SYSCON_PRESETCTRLCLR0_FLASH_RST_CLR_MASK (0x100U)
-#define SYSCON_PRESETCTRLCLR0_FLASH_RST_CLR_SHIFT (8U)
-/*! FLASH_RST_CLR - Writing one to this register clears the FLASH_RST bit in the PRESETCTRL0 register
- */
-#define SYSCON_PRESETCTRLCLR0_FLASH_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR0_FLASH_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR0_FLASH_RST_CLR_MASK)
#define SYSCON_PRESETCTRLCLR0_SPIFI_RST_CLR_MASK (0x400U)
#define SYSCON_PRESETCTRLCLR0_SPIFI_RST_CLR_SHIFT (10U)
/*! SPIFI_RST_CLR - Writing one to this register clears the SPIFI_RST bit in the PRESETCTRL0 register
@@ -11730,6 +11439,11 @@
/*! MUX_RST_CLR - Writing one to this register clears the MUX_RST bit in the PRESETCTRL0 register
*/
#define SYSCON_PRESETCTRLCLR0_MUX_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR0_MUX_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR0_MUX_RST_CLR_MASK)
+#define SYSCON_PRESETCTRLCLR0_BLE_TIMING_GEN_RST_CLR_MASK (0x1000U)
+#define SYSCON_PRESETCTRLCLR0_BLE_TIMING_GEN_RST_CLR_SHIFT (12U)
+/*! BLE_TIMING_GEN_RST_CLR - Writing one to this register clears the BLE_TIMING_GEN_RST bit in the PRESETCTRL0 register
+ */
+#define SYSCON_PRESETCTRLCLR0_BLE_TIMING_GEN_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR0_BLE_TIMING_GEN_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR0_BLE_TIMING_GEN_RST_CLR_MASK)
#define SYSCON_PRESETCTRLCLR0_IOCON_RST_CLR_MASK (0x2000U)
#define SYSCON_PRESETCTRLCLR0_IOCON_RST_CLR_SHIFT (13U)
/*! IOCON_RST_CLR - Writing one to this register clears the IOCON_RST bit in the PRESETCTRL0 register
@@ -11785,11 +11499,6 @@
/*! ADC_RST_CLR - Writing one to this register clears the ADC_RST bit in the PRESETCTRL0 register
*/
#define SYSCON_PRESETCTRLCLR0_ADC_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR0_ADC_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR0_ADC_RST_CLR_MASK)
-#define SYSCON_PRESETCTRLCLR0_EFUSE_RST_CLR_MASK (0x10000000U)
-#define SYSCON_PRESETCTRLCLR0_EFUSE_RST_CLR_SHIFT (28U)
-/*! EFUSE_RST_CLR - Writing one to this register clears the EFUSE_RST bit in the PRESETCTRL0 register
- */
-#define SYSCON_PRESETCTRLCLR0_EFUSE_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR0_EFUSE_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR0_EFUSE_RST_CLR_MASK)
/*! @} */
/*! @name PRESETCTRLCLR1 - Clear bits in PRESETCTRL1. It is recommended that changes to PRESETCTRL registers be accomplished by using the related PRESETCTRLSET and PRESETCTRLCLR registers. */
@@ -11849,6 +11558,11 @@
/*! ZIGBEE_RST_CLR - Writing one to this register clears the ZIGBEE_RST bit in the PRESETCTRL1 register
*/
#define SYSCON_PRESETCTRLCLR1_ZIGBEE_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR1_ZIGBEE_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR1_ZIGBEE_RST_CLR_MASK)
+#define SYSCON_PRESETCTRLCLR1_BLE_RST_CLR_MASK (0x400000U)
+#define SYSCON_PRESETCTRLCLR1_BLE_RST_CLR_SHIFT (22U)
+/*! BLE_RST_CLR - Writing one to this register clears the BLE_RST bit in the PRESETCTRL1 register
+ */
+#define SYSCON_PRESETCTRLCLR1_BLE_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR1_BLE_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR1_BLE_RST_CLR_MASK)
#define SYSCON_PRESETCTRLCLR1_MODEM_MASTER_RST_CLR_MASK (0x800000U)
#define SYSCON_PRESETCTRLCLR1_MODEM_MASTER_RST_CLR_SHIFT (23U)
/*! MODEM_MASTER_RST_CLR - Writing one to this register clears the MODEM_MASTER_RST bit in the PRESETCTRL1 register
@@ -11888,11 +11602,6 @@
/*! @name AHBCLKCTRL0 - AHB Clock control 0 */
/*! @{ */
-#define SYSCON_AHBCLKCTRL0_ROM_MASK (0x2U)
-#define SYSCON_AHBCLKCTRL0_ROM_SHIFT (1U)
-/*! ROM - Enables the clock for the ROM. 0: Disable. 1: Enable.
- */
-#define SYSCON_AHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK)
#define SYSCON_AHBCLKCTRL0_SRAM_CTRL0_MASK (0x8U)
#define SYSCON_AHBCLKCTRL0_SRAM_CTRL0_SHIFT (3U)
/*! SRAM_CTRL0 - Enables the clock for the SRAM Controller 0 (SRAM 0 to SRAM 7). 0: Disable. 1: Enable.
@@ -11903,11 +11612,6 @@
/*! SRAM_CTRL1 - Enables the clock for the SRAM Controller 1 (SRAM 8 to SRAM 11). 0: Disable. 1: Enable.
*/
#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK)
-#define SYSCON_AHBCLKCTRL0_FLASH_MASK (0x100U)
-#define SYSCON_AHBCLKCTRL0_FLASH_SHIFT (8U)
-/*! FLASH - Enables the clock for the Flash controller. 0: Disable. 1: Enable.
- */
-#define SYSCON_AHBCLKCTRL0_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL0_FLASH_MASK)
#define SYSCON_AHBCLKCTRL0_SPIFI_MASK (0x400U)
#define SYSCON_AHBCLKCTRL0_SPIFI_SHIFT (10U)
/*! SPIFI - Enables the clock for the Quad SPI Flash controller [Note: SPIFI IOs need configuring
@@ -11975,11 +11679,6 @@
/*! ADC - Enables the clock for the ADC Controller. 0: Disable. 1: Enable.
*/
#define SYSCON_AHBCLKCTRL0_ADC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ADC_SHIFT)) & SYSCON_AHBCLKCTRL0_ADC_MASK)
-#define SYSCON_AHBCLKCTRL0_EFUSE_MASK (0x10000000U)
-#define SYSCON_AHBCLKCTRL0_EFUSE_SHIFT (28U)
-/*! EFUSE - Enables the (APB interface) clock for the EFUSE/ OTP Controller. 0: Disable. 1: Enable.
- */
-#define SYSCON_AHBCLKCTRL0_EFUSE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_EFUSE_SHIFT)) & SYSCON_AHBCLKCTRL0_EFUSE_MASK)
/*! @} */
/*! @name AHBCLKCTRL1 - AHB Clock control 1 */
@@ -12039,6 +11738,11 @@
/*! ZIGBEE - Enable the clock for the Zigbee Modem . 0: Disable. 1: Enable.
*/
#define SYSCON_AHBCLKCTRL1_ZIGBEE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_ZIGBEE_SHIFT)) & SYSCON_AHBCLKCTRL1_ZIGBEE_MASK)
+#define SYSCON_AHBCLKCTRL1_BLE_MASK (0x400000U)
+#define SYSCON_AHBCLKCTRL1_BLE_SHIFT (22U)
+/*! BLE - Enable the clock for the BLE Modem. 0: Disable. 1: Enable.
+ */
+#define SYSCON_AHBCLKCTRL1_BLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_BLE_SHIFT)) & SYSCON_AHBCLKCTRL1_BLE_MASK)
#define SYSCON_AHBCLKCTRL1_MODEM_MASTER_MASK (0x800000U)
#define SYSCON_AHBCLKCTRL1_MODEM_MASTER_SHIFT (23U)
/*! MODEM_MASTER - Enable the clock for the Modem AHB Master Interface. 0: Disable. 1: Enable.
@@ -12078,11 +11782,6 @@
/*! @name AHBCLKCTRLSET0 - Set bits in AHBCLKCTRL0 */
/*! @{ */
-#define SYSCON_AHBCLKCTRLSET0_ROM_CLK_SET_MASK (0x2U)
-#define SYSCON_AHBCLKCTRLSET0_ROM_CLK_SET_SHIFT (1U)
-/*! ROM_CLK_SET - Writing one to this register sets the ROM bit in the AHBCLKCTRL0 register.
- */
-#define SYSCON_AHBCLKCTRLSET0_ROM_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET0_ROM_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET0_ROM_CLK_SET_MASK)
#define SYSCON_AHBCLKCTRLSET0_SRAM_CTRL0_CLK_SET_MASK (0x8U)
#define SYSCON_AHBCLKCTRLSET0_SRAM_CTRL0_CLK_SET_SHIFT (3U)
/*! SRAM_CTRL0_CLK_SET - Writing one to this register sets the SRAM_CTRL0 bit in the AHBCLKCTRL0 register.
@@ -12093,11 +11792,6 @@
/*! SRAM_CTRL1_CLK_SET - Writing one to this register sets the SRAM_CTRL1 bit in the AHBCLKCTRL0 register.
*/
#define SYSCON_AHBCLKCTRLSET0_SRAM_CTRL1_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET0_SRAM_CTRL1_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET0_SRAM_CTRL1_CLK_SET_MASK)
-#define SYSCON_AHBCLKCTRLSET0_FLASH_CLK_SET_MASK (0x100U)
-#define SYSCON_AHBCLKCTRLSET0_FLASH_CLK_SET_SHIFT (8U)
-/*! FLASH_CLK_SET - Writing one to this register sets the FLASH bit in the AHBCLKCTRL0 register.
- */
-#define SYSCON_AHBCLKCTRLSET0_FLASH_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET0_FLASH_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET0_FLASH_CLK_SET_MASK)
#define SYSCON_AHBCLKCTRLSET0_SPIFI_CLK_SET_MASK (0x400U)
#define SYSCON_AHBCLKCTRLSET0_SPIFI_CLK_SET_SHIFT (10U)
/*! SPIFI_CLK_SET - Writing one to this register sets the SPIFI bit in the AHBCLKCTRL0 register.
@@ -12163,11 +11857,6 @@
/*! ADC_CLK_SET - Writing one to this register sets the ADC bit in the AHBCLKCTRL0 register.
*/
#define SYSCON_AHBCLKCTRLSET0_ADC_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET0_ADC_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET0_ADC_CLK_SET_MASK)
-#define SYSCON_AHBCLKCTRLSET0_EFUSE_CLK_SET_MASK (0x10000000U)
-#define SYSCON_AHBCLKCTRLSET0_EFUSE_CLK_SET_SHIFT (28U)
-/*! EFUSE_CLK_SET - Writing one to this register sets the EFUSE bit in the AHBCLKCTRL0 register.
- */
-#define SYSCON_AHBCLKCTRLSET0_EFUSE_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET0_EFUSE_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET0_EFUSE_CLK_SET_MASK)
/*! @} */
/*! @name AHBCLKCTRLSET1 - Set bits in AHBCLKCTRL1 */
@@ -12227,6 +11916,11 @@
/*! ZIGBEE_CLK_SET - Writing one to this register sets the ZIGBEE bit in the AHBCLKCTRL1 register.
*/
#define SYSCON_AHBCLKCTRLSET1_ZIGBEE_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET1_ZIGBEE_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET1_ZIGBEE_CLK_SET_MASK)
+#define SYSCON_AHBCLKCTRLSET1_BLE_CLK_SET_MASK (0x400000U)
+#define SYSCON_AHBCLKCTRLSET1_BLE_CLK_SET_SHIFT (22U)
+/*! BLE_CLK_SET - Writing one to this register sets the BLE bit in the AHBCLKCTRL1 register.
+ */
+#define SYSCON_AHBCLKCTRLSET1_BLE_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET1_BLE_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET1_BLE_CLK_SET_MASK)
#define SYSCON_AHBCLKCTRLSET1_MODEM_MASTER_CLK_SET_MASK (0x800000U)
#define SYSCON_AHBCLKCTRLSET1_MODEM_MASTER_CLK_SET_SHIFT (23U)
/*! MODEM_MASTER_CLK_SET - Writing one to this register sets the MODEM_MASTER bit in the AHBCLKCTRL1 register.
@@ -12415,6 +12109,11 @@
/*! ZIGBEE_CLK_CLR - Writing one to this register clears the ZIGBEE bit in the AHBCLKCTRL1 register.
*/
#define SYSCON_AHBCLKCTRLCLR1_ZIGBEE_CLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR1_ZIGBEE_CLK_CLR_SHIFT)) & SYSCON_AHBCLKCTRLCLR1_ZIGBEE_CLK_CLR_MASK)
+#define SYSCON_AHBCLKCTRLCLR1_BLE_CLK_CLR_MASK (0x400000U)
+#define SYSCON_AHBCLKCTRLCLR1_BLE_CLK_CLR_SHIFT (22U)
+/*! BLE_CLK_CLR - Writing one to this register clears the BLE bit in the AHBCLKCTRL1 register.
+ */
+#define SYSCON_AHBCLKCTRLCLR1_BLE_CLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR1_BLE_CLK_CLR_SHIFT)) & SYSCON_AHBCLKCTRLCLR1_BLE_CLK_CLR_MASK)
#define SYSCON_AHBCLKCTRLCLR1_MODEM_MASTER_CLK_CLR_MASK (0x800000U)
#define SYSCON_AHBCLKCTRLCLR1_MODEM_MASTER_CLK_CLR_SHIFT (23U)
/*! MODEM_MASTER_CLK_CLR - Writing one to this register clears the MODEM_MASTER bit in the AHBCLKCTRL1 register.
@@ -12494,6 +12193,7 @@
* 0b011..32 MHz crystal oscillator (XTAL)
* 0b101..48 MHz free running oscillator (FRO)
* 0b110..1 MHz free running oscillator (FRO)
+ * 0b111..No clock
*/
#define SYSCON_CLKOUTSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK)
/*! @} */
@@ -12505,8 +12205,8 @@
/*! SEL - SPIFICLK clock source selection
* 0b000..CPU & System Bus clock
* 0b001..32 MHz crystal oscillator (XTAL)
- * 0b010..64 MHz free running oscillator (FRO)
- * 0b011..48 MHz free running oscillator (FRO)
+ * 0b010..No clock
+ * 0b011..No clock
* 0b100..No clock
* 0b101..No clock
* 0b110..No clock
@@ -12610,6 +12310,13 @@
* 0b1..No Clock
*/
#define SYSCON_MODEMCLKSEL_SEL_ZIGBEE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MODEMCLKSEL_SEL_ZIGBEE_SHIFT)) & SYSCON_MODEMCLKSEL_SEL_ZIGBEE_MASK)
+#define SYSCON_MODEMCLKSEL_SEL_BLE_MASK (0x2U)
+#define SYSCON_MODEMCLKSEL_SEL_BLE_SHIFT (1U)
+/*! SEL_BLE - BLE 32 MHz clock source selection
+ * 0b0..32 MHz XTAL
+ * 0b1..No Clock
+ */
+#define SYSCON_MODEMCLKSEL_SEL_BLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MODEMCLKSEL_SEL_BLE_SHIFT)) & SYSCON_MODEMCLKSEL_SEL_BLE_MASK)
/*! @} */
/*! @name FRGCLKSEL - Fractional Rate Generator (FRG) clock source select. The FRG is one of the USART clocking options. */
@@ -12946,15 +12653,6 @@
#define SYSCON_CLOCKGENUPDATELOCKOUT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCKGENUPDATELOCKOUT_LOCK_SHIFT)) & SYSCON_CLOCKGENUPDATELOCKOUT_LOCK_MASK)
/*! @} */
-/*! @name EFUSECLKCTRL - eFUSE/ OPT controller clock control */
-/*! @{ */
-#define SYSCON_EFUSECLKCTRL_ENABLE_MASK (0x1U)
-#define SYSCON_EFUSECLKCTRL_ENABLE_SHIFT (0U)
-/*! ENABLE - Enable the eFUSE OTP controller IP clock (FRO 12 MHz)
- */
-#define SYSCON_EFUSECLKCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EFUSECLKCTRL_ENABLE_SHIFT)) & SYSCON_EFUSECLKCTRL_ENABLE_MASK)
-/*! @} */
-
/*! @name RNGCLKCTRL - Random Number Generator Clocks control */
/*! @{ */
#define SYSCON_RNGCLKCTRL_ENABLE_MASK (0x1U)
@@ -12971,63 +12669,90 @@
/*! SMB - SMB
*/
#define SYSCON_SRAMCTRL_SMB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAMCTRL_SMB_SHIFT)) & SYSCON_SRAMCTRL_SMB_MASK)
-#define SYSCON_SRAMCTRL_RM_MASK (0x1CU)
-#define SYSCON_SRAMCTRL_RM_SHIFT (2U)
-/*! RM - RM
- */
-#define SYSCON_SRAMCTRL_RM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAMCTRL_RM_SHIFT)) & SYSCON_SRAMCTRL_RM_MASK)
-#define SYSCON_SRAMCTRL_WM_MASK (0xE0U)
-#define SYSCON_SRAMCTRL_WM_SHIFT (5U)
-/*! WM - WM
- */
-#define SYSCON_SRAMCTRL_WM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAMCTRL_WM_SHIFT)) & SYSCON_SRAMCTRL_WM_MASK)
-#define SYSCON_SRAMCTRL_WRME_MASK (0x100U)
-#define SYSCON_SRAMCTRL_WRME_SHIFT (8U)
-/*! WRME - WRME
- */
-#define SYSCON_SRAMCTRL_WRME(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAMCTRL_WRME_SHIFT)) & SYSCON_SRAMCTRL_WRME_MASK)
-#define SYSCON_SRAMCTRL_RAM_MASK (0x1E00U)
-#define SYSCON_SRAMCTRL_RAM_SHIFT (9U)
-/*! RAM - RAM
- */
-#define SYSCON_SRAMCTRL_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAMCTRL_RAM_SHIFT)) & SYSCON_SRAMCTRL_RAM_MASK)
-#define SYSCON_SRAMCTRL_WAM_MASK (0x6000U)
-#define SYSCON_SRAMCTRL_WAM_SHIFT (13U)
-/*! WAM - WAM
- */
-#define SYSCON_SRAMCTRL_WAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAMCTRL_WAM_SHIFT)) & SYSCON_SRAMCTRL_WAM_MASK)
-#define SYSCON_SRAMCTRL_RAEN_MASK (0x8000U)
-#define SYSCON_SRAMCTRL_RAEN_SHIFT (15U)
-/*! RAEN - RAEN
- */
-#define SYSCON_SRAMCTRL_RAEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAMCTRL_RAEN_SHIFT)) & SYSCON_SRAMCTRL_RAEN_MASK)
-#define SYSCON_SRAMCTRL_WAEN_MASK (0x10000U)
-#define SYSCON_SRAMCTRL_WAEN_SHIFT (16U)
-/*! WAEN - WAEN
- */
-#define SYSCON_SRAMCTRL_WAEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAMCTRL_WAEN_SHIFT)) & SYSCON_SRAMCTRL_WAEN_MASK)
-#define SYSCON_SRAMCTRL_STBP_MASK (0x20000U)
-#define SYSCON_SRAMCTRL_STBP_SHIFT (17U)
-/*! STBP - STBP
- */
-#define SYSCON_SRAMCTRL_STBP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAMCTRL_STBP_SHIFT)) & SYSCON_SRAMCTRL_STBP_MASK)
-#define SYSCON_SRAMCTRL_VSBTEST_MASK (0x40000U)
-#define SYSCON_SRAMCTRL_VSBTEST_SHIFT (18U)
-/*! VSBTEST - VSBTEST
- */
-#define SYSCON_SRAMCTRL_VSBTEST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAMCTRL_VSBTEST_SHIFT)) & SYSCON_SRAMCTRL_VSBTEST_MASK)
/*! @} */
-/*! @name MODEMCTRL - 32K clock enable */
+/*! @name MODEMCTRL - Modem (Bluetooth) control and 32K clock enable */
/*! @{ */
+#define SYSCON_MODEMCTRL_BLE_LP_SLEEP_TRIG_MASK (0x1U)
+#define SYSCON_MODEMCTRL_BLE_LP_SLEEP_TRIG_SHIFT (0U)
+/*! BLE_LP_SLEEP_TRIG - For normal operation leave at 0. If set to 1 will cause the load of register
+ * in the BLE low power timing block, as if going into deep sleep. This is not needed for the
+ * standard method to enter power down modes.
+ */
+#define SYSCON_MODEMCTRL_BLE_LP_SLEEP_TRIG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MODEMCTRL_BLE_LP_SLEEP_TRIG_SHIFT)) & SYSCON_MODEMCTRL_BLE_LP_SLEEP_TRIG_MASK)
+#define SYSCON_MODEMCTRL_BLE_FREQ_SEL_MASK (0x2U)
+#define SYSCON_MODEMCTRL_BLE_FREQ_SEL_SHIFT (1U)
+/*! BLE_FREQ_SEL - For normal BLE operation set to 1. BLE operation with this bit set to 0 is not supported. 1 = 16 MHz ; 0 = 8 MHz
+ */
+#define SYSCON_MODEMCTRL_BLE_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MODEMCTRL_BLE_FREQ_SEL_SHIFT)) & SYSCON_MODEMCTRL_BLE_FREQ_SEL_MASK)
+#define SYSCON_MODEMCTRL_BLE_DP_DIV_EN_MASK (0x4U)
+#define SYSCON_MODEMCTRL_BLE_DP_DIV_EN_SHIFT (2U)
+/*! BLE_DP_DIV_EN - For normal BLE operation set to 1. BLE operation with this bit set to 0 is not supported.
+ */
+#define SYSCON_MODEMCTRL_BLE_DP_DIV_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MODEMCTRL_BLE_DP_DIV_EN_SHIFT)) & SYSCON_MODEMCTRL_BLE_DP_DIV_EN_MASK)
+#define SYSCON_MODEMCTRL_BLE_CLK32M_SEL_MASK (0x8U)
+#define SYSCON_MODEMCTRL_BLE_CLK32M_SEL_SHIFT (3U)
+/*! BLE_CLK32M_SEL - For normal BLE operation set to 0. BLE operation with this bit set to 1 is not supported.
+ */
+#define SYSCON_MODEMCTRL_BLE_CLK32M_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MODEMCTRL_BLE_CLK32M_SEL_SHIFT)) & SYSCON_MODEMCTRL_BLE_CLK32M_SEL_MASK)
+#define SYSCON_MODEMCTRL_BLE_AHB_DIV0_MASK (0x10U)
+#define SYSCON_MODEMCTRL_BLE_AHB_DIV0_SHIFT (4U)
+/*! BLE_AHB_DIV0 - For normal BLE operation set to 0. BLE operation with this bit set to 1 is not supported.
+ */
+#define SYSCON_MODEMCTRL_BLE_AHB_DIV0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MODEMCTRL_BLE_AHB_DIV0_SHIFT)) & SYSCON_MODEMCTRL_BLE_AHB_DIV0_MASK)
+#define SYSCON_MODEMCTRL_BLE_AHB_DIV1_MASK (0x20U)
+#define SYSCON_MODEMCTRL_BLE_AHB_DIV1_SHIFT (5U)
+/*! BLE_AHB_DIV1 - For normal BLE operation set to 0. BLE operation with this bit set to 1 is not supported.
+ */
+#define SYSCON_MODEMCTRL_BLE_AHB_DIV1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MODEMCTRL_BLE_AHB_DIV1_SHIFT)) & SYSCON_MODEMCTRL_BLE_AHB_DIV1_MASK)
+#define SYSCON_MODEMCTRL_BLE_HCLK_BLE_EN_MASK (0x40U)
+#define SYSCON_MODEMCTRL_BLE_HCLK_BLE_EN_SHIFT (6U)
+/*! BLE_HCLK_BLE_EN - For normal BLE operation set to 1 to enable the register interface clock
+ */
+#define SYSCON_MODEMCTRL_BLE_HCLK_BLE_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MODEMCTRL_BLE_HCLK_BLE_EN_SHIFT)) & SYSCON_MODEMCTRL_BLE_HCLK_BLE_EN_MASK)
+#define SYSCON_MODEMCTRL_BLE_PHASE_MATCH_1_MASK (0x80U)
+#define SYSCON_MODEMCTRL_BLE_PHASE_MATCH_1_SHIFT (7U)
+/*! BLE_PHASE_MATCH_1 - For normal BLE operation set to 0. BLE operation with this bit set to 1 is not supported.
+ */
+#define SYSCON_MODEMCTRL_BLE_PHASE_MATCH_1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MODEMCTRL_BLE_PHASE_MATCH_1_SHIFT)) & SYSCON_MODEMCTRL_BLE_PHASE_MATCH_1_MASK)
+#define SYSCON_MODEMCTRL_BLE_ISO_ENABLE_MASK (0x100U)
+#define SYSCON_MODEMCTRL_BLE_ISO_ENABLE_SHIFT (8U)
+/*! BLE_ISO_ENABLE - Control isolation of BLE Low Power Control module. When the BLE low power
+ * controller/timers is being used then the isolation must be enabled before entering power down
+ * state. Must not be set before MODEMSTATUS.BLE_LL_CLK_STATUS is high ('1'). 0: isolation is
+ * disabled. 1: isolation is enabled.
+ */
+#define SYSCON_MODEMCTRL_BLE_ISO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MODEMCTRL_BLE_ISO_ENABLE_SHIFT)) & SYSCON_MODEMCTRL_BLE_ISO_ENABLE_MASK)
#define SYSCON_MODEMCTRL_BLE_LP_OSC32K_EN_MASK (0x200U)
#define SYSCON_MODEMCTRL_BLE_LP_OSC32K_EN_SHIFT (9U)
-/*! BLE_LP_OSC32K_EN - 1 = enable the 32K clock to the USART 0 & 1, LSPI0 & 1, PMC and the frequency
- * measure block. Note: despite its name, this control bit affects peripheral clocking,
+/*! BLE_LP_OSC32K_EN - 1 = enable the 32K clock to the BLE Low power wake up counter, USART 0 & 1,
+ * LSPI0 & 1, PMC and the frequency measure block
*/
#define SYSCON_MODEMCTRL_BLE_LP_OSC32K_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MODEMCTRL_BLE_LP_OSC32K_EN_SHIFT)) & SYSCON_MODEMCTRL_BLE_LP_OSC32K_EN_MASK)
/*! @} */
+/*! @name MODEMSTATUS - Modem (Bluetooth) status */
+/*! @{ */
+#define SYSCON_MODEMSTATUS_BLE_LL_CLK_STATUS_MASK (0x1U)
+#define SYSCON_MODEMSTATUS_BLE_LL_CLK_STATUS_SHIFT (0U)
+/*! BLE_LL_CLK_STATUS - Status bit to indicate the clocking status from the link layer. 1 = BLE IP
+ * in deep sleep using low power clock; 0 BLE IP active using 32M clocks
+ */
+#define SYSCON_MODEMSTATUS_BLE_LL_CLK_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MODEMSTATUS_BLE_LL_CLK_STATUS_SHIFT)) & SYSCON_MODEMSTATUS_BLE_LL_CLK_STATUS_MASK)
+#define SYSCON_MODEMSTATUS_BLE_LP_OSC_EN_MASK (0x2U)
+#define SYSCON_MODEMSTATUS_BLE_LP_OSC_EN_SHIFT (1U)
+/*! BLE_LP_OSC_EN - BLE low power timing block can be configured to start the wake-up sequence from
+ * power down. This status bit indicates the value of that control bit.
+ */
+#define SYSCON_MODEMSTATUS_BLE_LP_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MODEMSTATUS_BLE_LP_OSC_EN_SHIFT)) & SYSCON_MODEMSTATUS_BLE_LP_OSC_EN_MASK)
+#define SYSCON_MODEMSTATUS_BLE_LP_RADIO_EN_MASK (0x4U)
+#define SYSCON_MODEMSTATUS_BLE_LP_RADIO_EN_SHIFT (2U)
+/*! BLE_LP_RADIO_EN - BLE low power timing block can be configured to start the radio early; this is
+ * not supoorted in this device. However, that control signal can be observed here.
+ */
+#define SYSCON_MODEMSTATUS_BLE_LP_RADIO_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MODEMSTATUS_BLE_LP_RADIO_EN_SHIFT)) & SYSCON_MODEMSTATUS_BLE_LP_RADIO_EN_MASK)
+/*! @} */
+
/*! @name XTAL32KCAP - XTAL 32 KHz oscillator Capacitor control */
/*! @{ */
#define SYSCON_XTAL32KCAP_XO_OSC_CAP_IN_MASK (0x7FU)
@@ -13059,6 +12784,14 @@
* controls coming from PMC. 1: Disable XTAL 32 MHz controls coming from PMC.
*/
#define SYSCON_XTAL32MCTRL_DEACTIVATE_PMC_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_XTAL32MCTRL_DEACTIVATE_PMC_CTRL_SHIFT)) & SYSCON_XTAL32MCTRL_DEACTIVATE_PMC_CTRL_MASK)
+#define SYSCON_XTAL32MCTRL_DEACTIVATE_BLE_CTRL_MASK (0x2U)
+#define SYSCON_XTAL32MCTRL_DEACTIVATE_BLE_CTRL_SHIFT (1U)
+/*! DEACTIVATE_BLE_CTRL - In order to have XTAL ready for BLE after a low power cycle the XTAL must
+ * be started early by the BLE low power module; this can be deactivated. 0: Enable XTAL 32 MHz
+ * controls coming from BLE Low Power Control module. 1: Disable XTAL 32 MHz controls coming from
+ * BLE Low Power Control module.
+ */
+#define SYSCON_XTAL32MCTRL_DEACTIVATE_BLE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_XTAL32MCTRL_DEACTIVATE_BLE_CTRL_SHIFT)) & SYSCON_XTAL32MCTRL_DEACTIVATE_BLE_CTRL_MASK)
/*! @} */
/*! @name STARTER0 - Start logic 0 wake-up enable register. Enable an interrupt for wake-up from deep-sleep mode. Some bits can also control wake-up from powerdown mode */
@@ -13244,6 +12977,31 @@
* Wake-up enabled. Valid from Deep-Sleep.
*/
#define SYSCON_STARTER1_HWVAD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER1_HWVAD_SHIFT)) & SYSCON_STARTER1_HWVAD_MASK)
+#define SYSCON_STARTER1_BLE_DP_MASK (0x20U)
+#define SYSCON_STARTER1_BLE_DP_SHIFT (5U)
+/*! BLE_DP - BLE Datapath interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep.
+ */
+#define SYSCON_STARTER1_BLE_DP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER1_BLE_DP_SHIFT)) & SYSCON_STARTER1_BLE_DP_MASK)
+#define SYSCON_STARTER1_BLE_DP0_MASK (0x40U)
+#define SYSCON_STARTER1_BLE_DP0_SHIFT (6U)
+/*! BLE_DP0 - BLE Datapath 0 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep.
+ */
+#define SYSCON_STARTER1_BLE_DP0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER1_BLE_DP0_SHIFT)) & SYSCON_STARTER1_BLE_DP0_MASK)
+#define SYSCON_STARTER1_BLE_DP1_MASK (0x80U)
+#define SYSCON_STARTER1_BLE_DP1_SHIFT (7U)
+/*! BLE_DP1 - BLE Datapath 1 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep.
+ */
+#define SYSCON_STARTER1_BLE_DP1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER1_BLE_DP1_SHIFT)) & SYSCON_STARTER1_BLE_DP1_MASK)
+#define SYSCON_STARTER1_BLE_DP2_MASK (0x100U)
+#define SYSCON_STARTER1_BLE_DP2_SHIFT (8U)
+/*! BLE_DP2 - BLE Datapath 2 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep.
+ */
+#define SYSCON_STARTER1_BLE_DP2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER1_BLE_DP2_SHIFT)) & SYSCON_STARTER1_BLE_DP2_MASK)
+#define SYSCON_STARTER1_BLE_LL_ALL_MASK (0x200U)
+#define SYSCON_STARTER1_BLE_LL_ALL_SHIFT (9U)
+/*! BLE_LL_ALL - BLE Link Layer interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep.
+ */
+#define SYSCON_STARTER1_BLE_LL_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER1_BLE_LL_ALL_SHIFT)) & SYSCON_STARTER1_BLE_LL_ALL_MASK)
#define SYSCON_STARTER1_ZIGBEE_MAC_MASK (0x400U)
#define SYSCON_STARTER1_ZIGBEE_MAC_SHIFT (10U)
/*! ZIGBEE_MAC - Zigbee MAC interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep.
@@ -13285,6 +13043,18 @@
/*! WAKE_UP_TIMER1 - Wake-up Timer1 interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep and Powerdown.
*/
#define SYSCON_STARTER1_WAKE_UP_TIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER1_WAKE_UP_TIMER1_SHIFT)) & SYSCON_STARTER1_WAKE_UP_TIMER1_MASK)
+#define SYSCON_STARTER1_BLE_WAKE_UP_TIMER_MASK (0x400000U)
+#define SYSCON_STARTER1_BLE_WAKE_UP_TIMER_SHIFT (22U)
+/*! BLE_WAKE_UP_TIMER - BLE Wake-up Timer interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Valid from Deep-Sleep and Powerdown.
+ */
+#define SYSCON_STARTER1_BLE_WAKE_UP_TIMER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER1_BLE_WAKE_UP_TIMER_SHIFT)) & SYSCON_STARTER1_BLE_WAKE_UP_TIMER_MASK)
+#define SYSCON_STARTER1_BLE_OSC_EN_MASK (0x800000U)
+#define SYSCON_STARTER1_BLE_OSC_EN_SHIFT (23U)
+/*! BLE_OSC_EN - BLE Oscillator Enable interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
+ * Valid from Deep-Sleep and Powerdown. Used as early wake-up trigger to allow 32M XTAL to be
+ * started and ready for BLE timeslot
+ */
+#define SYSCON_STARTER1_BLE_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER1_BLE_OSC_EN_SHIFT)) & SYSCON_STARTER1_BLE_OSC_EN_MASK)
#define SYSCON_STARTER1_GPIO_MASK (0x80000000U)
#define SYSCON_STARTER1_GPIO_SHIFT (31U)
/*! GPIO - GPIO interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Set this bit to allow
@@ -13484,6 +13254,31 @@
/*! HWVAD_SET - Writing one to this bit sets the corresponding bit in the STARTER1 register
*/
#define SYSCON_STARTERSET1_HWVAD_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET1_HWVAD_SET_SHIFT)) & SYSCON_STARTERSET1_HWVAD_SET_MASK)
+#define SYSCON_STARTERSET1_BLE_DP_SET_MASK (0x20U)
+#define SYSCON_STARTERSET1_BLE_DP_SET_SHIFT (5U)
+/*! BLE_DP_SET - Writing one to this bit sets the corresponding bit in the STARTER1 register
+ */
+#define SYSCON_STARTERSET1_BLE_DP_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET1_BLE_DP_SET_SHIFT)) & SYSCON_STARTERSET1_BLE_DP_SET_MASK)
+#define SYSCON_STARTERSET1_BLE_DP0_SET_MASK (0x40U)
+#define SYSCON_STARTERSET1_BLE_DP0_SET_SHIFT (6U)
+/*! BLE_DP0_SET - Writing one to this bit sets the corresponding bit in the STARTER1 register
+ */
+#define SYSCON_STARTERSET1_BLE_DP0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET1_BLE_DP0_SET_SHIFT)) & SYSCON_STARTERSET1_BLE_DP0_SET_MASK)
+#define SYSCON_STARTERSET1_BLE_DP1_SET_MASK (0x80U)
+#define SYSCON_STARTERSET1_BLE_DP1_SET_SHIFT (7U)
+/*! BLE_DP1_SET - Writing one to this bit sets the corresponding bit in the STARTER1 register
+ */
+#define SYSCON_STARTERSET1_BLE_DP1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET1_BLE_DP1_SET_SHIFT)) & SYSCON_STARTERSET1_BLE_DP1_SET_MASK)
+#define SYSCON_STARTERSET1_BLE_DP2_SET_MASK (0x100U)
+#define SYSCON_STARTERSET1_BLE_DP2_SET_SHIFT (8U)
+/*! BLE_DP2_SET - Writing one to this bit sets the corresponding bit in the STARTER1 register
+ */
+#define SYSCON_STARTERSET1_BLE_DP2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET1_BLE_DP2_SET_SHIFT)) & SYSCON_STARTERSET1_BLE_DP2_SET_MASK)
+#define SYSCON_STARTERSET1_BLE_LL_ALL_SET_MASK (0x200U)
+#define SYSCON_STARTERSET1_BLE_LL_ALL_SET_SHIFT (9U)
+/*! BLE_LL_ALL_SET - Writing one to this bit sets the corresponding bit in the STARTER1 register
+ */
+#define SYSCON_STARTERSET1_BLE_LL_ALL_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET1_BLE_LL_ALL_SET_SHIFT)) & SYSCON_STARTERSET1_BLE_LL_ALL_SET_MASK)
#define SYSCON_STARTERSET1_ZIGBEE_MAC_SET_MASK (0x400U)
#define SYSCON_STARTERSET1_ZIGBEE_MAC_SET_SHIFT (10U)
/*! ZIGBEE_MAC_SET - Writing one to this bit sets the corresponding bit in the STARTER1 register
@@ -13524,6 +13319,16 @@
/*! WAKE_UP_TIMER1_SET - Writing one to this bit sets the corresponding bit in the STARTER1 register
*/
#define SYSCON_STARTERSET1_WAKE_UP_TIMER1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET1_WAKE_UP_TIMER1_SET_SHIFT)) & SYSCON_STARTERSET1_WAKE_UP_TIMER1_SET_MASK)
+#define SYSCON_STARTERSET1_BLE_WAKE_UP_TIMER_SET_MASK (0x400000U)
+#define SYSCON_STARTERSET1_BLE_WAKE_UP_TIMER_SET_SHIFT (22U)
+/*! BLE_WAKE_UP_TIMER_SET - Writing one to this bit sets the corresponding bit in the STARTER1 register
+ */
+#define SYSCON_STARTERSET1_BLE_WAKE_UP_TIMER_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET1_BLE_WAKE_UP_TIMER_SET_SHIFT)) & SYSCON_STARTERSET1_BLE_WAKE_UP_TIMER_SET_MASK)
+#define SYSCON_STARTERSET1_BLE_OSC_EN_SET_MASK (0x800000U)
+#define SYSCON_STARTERSET1_BLE_OSC_EN_SET_SHIFT (23U)
+/*! BLE_OSC_EN_SET - Writing one to this bit sets the corresponding bit in the STARTER1 register
+ */
+#define SYSCON_STARTERSET1_BLE_OSC_EN_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET1_BLE_OSC_EN_SET_SHIFT)) & SYSCON_STARTERSET1_BLE_OSC_EN_SET_MASK)
#define SYSCON_STARTERSET1_GPIO_SET_MASK (0x80000000U)
#define SYSCON_STARTERSET1_GPIO_SET_SHIFT (31U)
/*! GPIO_SET - Writing one to this bit sets the corresponding bit in the STARTER1 register
@@ -13722,6 +13527,31 @@
/*! HWVAD_CLR - Writing one to this bit clears the corresponding bit in the STARTER1 register
*/
#define SYSCON_STARTERCLR1_HWVAD_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR1_HWVAD_CLR_SHIFT)) & SYSCON_STARTERCLR1_HWVAD_CLR_MASK)
+#define SYSCON_STARTERCLR1_BLE_DP_CLR_MASK (0x20U)
+#define SYSCON_STARTERCLR1_BLE_DP_CLR_SHIFT (5U)
+/*! BLE_DP_CLR - Writing one to this bit clears the corresponding bit in the STARTER1 register
+ */
+#define SYSCON_STARTERCLR1_BLE_DP_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR1_BLE_DP_CLR_SHIFT)) & SYSCON_STARTERCLR1_BLE_DP_CLR_MASK)
+#define SYSCON_STARTERCLR1_BLE_DP0_CLR_MASK (0x40U)
+#define SYSCON_STARTERCLR1_BLE_DP0_CLR_SHIFT (6U)
+/*! BLE_DP0_CLR - Writing one to this bit clears the corresponding bit in the STARTER1 register
+ */
+#define SYSCON_STARTERCLR1_BLE_DP0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR1_BLE_DP0_CLR_SHIFT)) & SYSCON_STARTERCLR1_BLE_DP0_CLR_MASK)
+#define SYSCON_STARTERCLR1_BLE_DP1_CLR_MASK (0x80U)
+#define SYSCON_STARTERCLR1_BLE_DP1_CLR_SHIFT (7U)
+/*! BLE_DP1_CLR - Writing one to this bit clears the corresponding bit in the STARTER1 register
+ */
+#define SYSCON_STARTERCLR1_BLE_DP1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR1_BLE_DP1_CLR_SHIFT)) & SYSCON_STARTERCLR1_BLE_DP1_CLR_MASK)
+#define SYSCON_STARTERCLR1_BLE_DP2_CLR_MASK (0x100U)
+#define SYSCON_STARTERCLR1_BLE_DP2_CLR_SHIFT (8U)
+/*! BLE_DP2_CLR - Writing one to this bit clears the corresponding bit in the STARTER1 register
+ */
+#define SYSCON_STARTERCLR1_BLE_DP2_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR1_BLE_DP2_CLR_SHIFT)) & SYSCON_STARTERCLR1_BLE_DP2_CLR_MASK)
+#define SYSCON_STARTERCLR1_BLE_LL_ALL_CLR_MASK (0x200U)
+#define SYSCON_STARTERCLR1_BLE_LL_ALL_CLR_SHIFT (9U)
+/*! BLE_LL_ALL_CLR - Writing one to this bit clears the corresponding bit in the STARTER1 register
+ */
+#define SYSCON_STARTERCLR1_BLE_LL_ALL_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR1_BLE_LL_ALL_CLR_SHIFT)) & SYSCON_STARTERCLR1_BLE_LL_ALL_CLR_MASK)
#define SYSCON_STARTERCLR1_ZIGBEE_MAC_CLR_MASK (0x400U)
#define SYSCON_STARTERCLR1_ZIGBEE_MAC_CLR_SHIFT (10U)
/*! ZIGBEE_MAC_CLR - Writing one to this bit clears the corresponding bit in the STARTER1 register
@@ -13762,6 +13592,16 @@
/*! WAKE_UP_TIMER1_CLR - Writing one to this bit clears the corresponding bit in the STARTER1 register
*/
#define SYSCON_STARTERCLR1_WAKE_UP_TIMER1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR1_WAKE_UP_TIMER1_CLR_SHIFT)) & SYSCON_STARTERCLR1_WAKE_UP_TIMER1_CLR_MASK)
+#define SYSCON_STARTERCLR1_BLE_WAKE_UP_TIMER_CLR_MASK (0x400000U)
+#define SYSCON_STARTERCLR1_BLE_WAKE_UP_TIMER_CLR_SHIFT (22U)
+/*! BLE_WAKE_UP_TIMER_CLR - Writing one to this bit clears the corresponding bit in the STARTER1 register
+ */
+#define SYSCON_STARTERCLR1_BLE_WAKE_UP_TIMER_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR1_BLE_WAKE_UP_TIMER_CLR_SHIFT)) & SYSCON_STARTERCLR1_BLE_WAKE_UP_TIMER_CLR_MASK)
+#define SYSCON_STARTERCLR1_BLE_OSC_EN_CLR_MASK (0x800000U)
+#define SYSCON_STARTERCLR1_BLE_OSC_EN_CLR_SHIFT (23U)
+/*! BLE_OSC_EN_CLR - Writing one to this bit clears the corresponding bit in the STARTER1 register
+ */
+#define SYSCON_STARTERCLR1_BLE_OSC_EN_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR1_BLE_OSC_EN_CLR_SHIFT)) & SYSCON_STARTERCLR1_BLE_OSC_EN_CLR_MASK)
#define SYSCON_STARTERCLR1_GPIO_CLR_MASK (0x80000000U)
#define SYSCON_STARTERCLR1_GPIO_CLR_SHIFT (31U)
/*! GPIO_CLR - Writing one to this bit clears the corresponding bit in the STARTER1 register
@@ -15155,13 +14995,6 @@
* of WDWARNINT and WDWINDOW, otherwise a 'feed error' is created.
*/
#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK)
-#define WWDT_MOD_LOCK_MASK (0x20U)
-#define WWDT_MOD_LOCK_SHIFT (5U)
-/*! LOCK - Once this bit is set to one and a watchdog feed is performed, disabling or powering down
- * the watchdog oscillator is prevented by hardware. This bit can be set once by software and is
- * only cleared by any reset.
- */
-#define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK)
/*! @} */
/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */
@@ -15332,6 +15165,7 @@
#define DMIC_IRQn DMIC0_IRQn
#define HWVAD_IRQn HWVAD0_IRQn
#define AES256_Type AES_Type
+#define NTAG_IRQ NFCTag_IRQn
#define PRESETCTRL PRESETCTRLS
#define PRESETCTRLSET PRESETCTRLSETS
#define PRESETCTRLCLR PRESETCTRLCLRS
@@ -15347,5 +15181,5 @@
*/ /* end of group SDK_Compatibility_Symbols */
-#endif /* _JN5189_H_ */
+#endif /* _K32W061_H_ */
diff --git a/third_party/nxp/JN5189/JN5189_features.h b/third_party/nxp/K32W061DK6/devices/K32W061/K32W061_features.h
similarity index 63%
copy from third_party/nxp/JN5189/JN5189_features.h
copy to third_party/nxp/K32W061DK6/devices/K32W061/K32W061_features.h
index 1335bbe..2e4881c 100755
--- a/third_party/nxp/JN5189/JN5189_features.h
+++ b/third_party/nxp/K32W061DK6/devices/K32W061/K32W061_features.h
@@ -1,13 +1,14 @@
/*
** ###################################################################
-** Version: rev. 1.0, 2016-05-09
-** Build: b160714
+** Version: rev. 1.0, 2019-11-05
+** Build: b191121
**
** Abstract:
** Chip specific module features.
**
** Copyright 2016 Freescale Semiconductor, Inc.
-** Copyright 2016-2018 NXP
+** Copyright 2016-2019 NXP
+** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
@@ -15,206 +16,225 @@
** mail: support@nxp.com
**
** Revisions:
-** - rev. 1.0 (2016-05-09)
+** - rev. 1.0 (2019-11-05)
** Initial version.
**
** ###################################################################
*/
-#ifndef _JN518X_FEATURES_H_
-#define _JN518X_FEATURES_H_
+#ifndef _K32W061_FEATURES_H_
+#define _K32W061_FEATURES_H_
/* SOC module features */
/* @brief ADC availability on the SoC. */
#define FSL_FEATURE_SOC_ADC_COUNT (1)
+/* @brief AES availability on the SoC. */
+#define FSL_FEATURE_SOC_AES_COUNT (1)
/* @brief ASYNC_SYSCON availability on the SoC. */
#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1)
-/* @brief CRC availability on the SoC. */
-#define FSL_FEATURE_SOC_CRC_COUNT (1)
+/* @brief CIC_IRB availability on the SoC. */
+#define FSL_FEATURE_SOC_CIC_IRB_COUNT (1)
+/* @brief CTIMER availability on the SoC. */
+#define FSL_FEATURE_SOC_CTIMER_COUNT (2)
/* @brief DMA availability on the SoC. */
#define FSL_FEATURE_SOC_DMA_COUNT (1)
-/* @brief Number of DMA channels on the SOC. */
+/* @brief DMIC availability on the SoC. */
+#define FSL_FEATURE_SOC_DMIC_COUNT (1)
+/* @brief FLASH availability on the SoC. */
+#define FSL_FEATURE_SOC_FLASH_COUNT (1)
+/* @brief FLEXCOMM availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (7)
+/* @brief GINT availability on the SoC. */
+#define FSL_FEATURE_SOC_GINT_COUNT (1)
+/* @brief HASH availability on the SoC. */
+#define FSL_FEATURE_SOC_HASH_COUNT (1)
+/* @brief I2C availability on the SoC. */
+#define FSL_FEATURE_SOC_I2C_COUNT (3)
+/* @brief INPUTMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
+/* @brief IOCON availability on the SoC. */
+#define FSL_FEATURE_SOC_IOCON_COUNT (1)
+/* @brief LPC_GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_LPC_GPIO_COUNT (1)
+/* @brief LPC_RTC availability on the SoC. */
+#define FSL_FEATURE_SOC_LPC_RTC_COUNT (1)
+/* @brief PINT availability on the SoC. */
+#define FSL_FEATURE_SOC_PINT_COUNT (1)
+/* @brief PMC availability on the SoC. */
+#define FSL_FEATURE_SOC_PMC_COUNT (1)
+/* @brief PWM availability on the SoC. */
+#define FSL_FEATURE_SOC_PWM_COUNT (1)
+/* @brief SHA availability on the SoC. */
+#define FSL_FEATURE_SOC_SHA_COUNT (1)
+/* @brief SPI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPI_COUNT (2)
+/* @brief SPIFI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPIFI_COUNT (1)
+/* @brief SYSCON availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
+/* @brief TRNG availability on the SoC. */
+#define FSL_FEATURE_SOC_TRNG_COUNT (1)
+/* @brief USART availability on the SoC. */
+#define FSL_FEATURE_SOC_USART_COUNT (2)
+/* @brief WWDT availability on the SoC. */
+#define FSL_FEATURE_SOC_WWDT_COUNT (1)
+
+/* ADC module features */
+
+/* @brief ADC data alignment mode. */
+#define FSL_FEATURE_ADC_DAT_OF_HIGH_ALIGNMENT (1)
+/* @brief ADC data alignment mode. */
+#define FSL_FEATURE_ADC_SYNCHRONOUS_USE_GPADC_CTRL (1)
+/* @brief Has no Calibration function. */
+#define FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC (1)
+/* @brief ADC has single SEQ. */
+#define FSL_FEATURE_ADC_HAS_SINGLE_SEQ (1)
+/* @brief Has ADC_INIT bitfile in STARTUP register. */
+#define FSL_FEATURE_ADC_HAS_STARTUP_ADC_INIT (0)
+/* @brief Has OFFSET_CAL bitfile in GPADC_CTRL1 reigster. */
+#define FSL_FEATURE_ADC_HAS_GPADC_CTRL1_OFFSET_CAL (1)
+/* @brief Has LDO_POWER_EN bitfile in GPADC_CTRL0 reigster. */
+#define FSL_FEATURE_ADC_HAS_GPADC_CTRL0_LDO_POWER_EN (1)
+/* @brief ADC require a delay. */
+#define FSL_FEATURE_ADC_REQUIRE_DELAY (1)
+/* @brief ADC TEMPSENSORCTRL in ASYNC_SYSCON. */
+#define FSL_FEATURE_ADC_ASYNC_SYSCON_TEMP (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (0)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (0)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (0)
+/* @brief Has ADTrim register */
+#define FSL_FEATURE_ADC_HAS_TRIM_REG (0)
+/* @brief Has Calibration register. */
+#define FSL_FEATURE_ADC_HAS_CALIB_REG (0)
+
+/* ASYNC_SYSCON module features */
+
+/* @brief FMEAS FMEAS_INDEX is 20. */
+#define FSL_FEATURE_FMEAS_INDEX_20 (1)
+/* @brief FMEAS FREQMECTRL in ASYNC_SYSCON. */
+#define FSL_FEATURE_FMEAS_ASYNC_SYSCON_FREQMECTRL (1)
+/* @brief FMEAS SYSCON use ASYNC_SYSCON. */
+#define FSL_FEATURE_FMEAS_USE_ASYNC_SYSCON (1)
+/* @brief FMEAS start frequency with ASYNC_SYSCON. */
+#define FSL_FEATURE_FMEAS_START_FRG_ASYNC_SYSCON (1)
+/* @brief FMEAS get frequency with ASYNC_SYSCON. */
+#define FSL_FEATURE_FMEAS_GET_FRG_ASYNC_SYSCON (1)
+/* @brief FMEAS get clock count with scale. */
+#define FSL_FEATURE_FMEAS_GET_COUNT_SCALE (1)
+/* @brief FMEAS start measure with scale. */
+#define FSL_FEATURE_FMEAS_STARTMEAS_SCALE (1)
+
+/* CTIMER module features */
+
+/* @brief CTIMER capture 3 interrupt. */
+#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1)
+/* @brief CTIMER has no capture channel. */
+#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (1)
+
+/* DMA module features */
+
+/* @brief Number of channels */
#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (19)
/* @brief Align size of DMA descriptor */
#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512)
/* @brief DMA head link descriptor table align size */
#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)
-/* @brief DMIC availability on the SoC. */
-#define FSL_FEATURE_SOC_DMIC_COUNT (1)
-/* @brief FLEXCOMM availability on the SoC. */
-#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (7)
-/* @brief GINT availability on the SoC. */
-#define FSL_FEATURE_SOC_GINT_COUNT (1)
-/* @brief GPIO availability on the SoC. */
-#define FSL_FEATURE_SOC_LPC_GPIO_COUNT (1)
-#define FSL_FEATURE_SOC_GPIO_COUNT FSL_FEATURE_SOC_LPC_GPIO_COUNT
-/* @brief I2C availability on the SoC. */
-#define FSL_FEATURE_SOC_I2C_COUNT (3)
-/* @brief I2C are FLEXCOMM on the SoC. */
-#define FSL_FEATURE_SOC_FLEXCOMM_I2C_COUNT FSL_FEATURE_SOC_I2C_COUNT
-/* @brief INPUTMUX availability on the SoC. */
-#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
-/* @brief IOCON availability on the SoC. */
-#define FSL_FEATURE_SOC_IOCON_COUNT (1)
-/* @brief MAILBOX availability on the SoC. */
-#define FSL_FEATURE_SOC_MAILBOX_COUNT (1)
-/* @brief MRT availability on the SoC. */
-#define FSL_FEATURE_SOC_MRT_COUNT (1)
-/* @brief PINT availability on the SoC. */
-#define FSL_FEATURE_SOC_PINT_COUNT (1)
-/* @brief RTC availability on the SoC. */
-#define FSL_FEATURE_SOC_LPC_RTC_COUNT (1)
-/* @brief SCT availability on the SoC. */
-#define FSL_FEATURE_SOC_SCT_COUNT (1)
-/* @brief SPI availability on the SoC. */
-#define FSL_FEATURE_SOC_SPI_COUNT (2)
-/* @brief SPI are FLEXCOMM on the SoC. */
-#define FSL_FEATURE_SOC_FLEXCOMM_SPI_COUNT FSL_FEATURE_SOC_SPI_COUNT
-/* @brief SPIFI availability on the SoC. */
-#define FSL_FEATURE_SOC_SPIFI_COUNT (1)
-/* @brief SYSCON availability on the SoC. */
-#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
-/* @brief CTIMER availability on the SoC. */
-#define FSL_FEATURE_SOC_CTIMER_COUNT (2)
-/* @brief USART availability on the SoC. */
-#define FSL_FEATURE_SOC_USART_COUNT (2)
-/* @brief USART availability on the SoC. */
-#define FSL_FEATURE_SOC_FLEXCOMM_USART_COUNT FSL_FEATURE_SOC_USART_COUNT
-/* @brief USB availability on the SoC. */
-#define FSL_FEATURE_SOC_UTICK_COUNT (1)
-/* @brief WWDT availability on the SoC. */
-#define FSL_FEATURE_SOC_WWDT_COUNT (1)
-/* @brief IRB availability on the SoC. */
-#define FSL_FEATURE_SOC_CIC_IRB_COUNT (1)
-/* @brief reduced functionality FLEXCOMM for low power JN518x family */
-#define FSL_REDUCED_FUNCTION_FLEXCOMM
-/* @brief PWM availability on the Soc */
-#define FSL_FEATURE_SOC_PWM_COUNT (10)
-
-/* @brief HASH/SHA availability on the SoC. */
-#define FSL_FEATURE_SOC_SHA_COUNT (1)
-/* @brief AES availability on the SoC. */
-#define FSL_FEATURE_SOC_AES_COUNT (1)
-
-/* @brief RNG availability on the SoC. */
-#define FSL_FEATURE_SOC_TRNG_COUNT (1)
-
-/* SPIFI module features */
-/* @brief SPIFI start address */
-#define FSL_FEATURE_SPIFI_START_ADDR (0x10000000)
-/* @brief SPIFI end address */
-#define FSL_FEATURE_SPIFI_END_ADDR (0x17FFFFFF)
-/* @brief SPIFI DATALEN bitfile in CMD register*/
-#define FSL_FEATURE_SPIFI_DATALEN_CTRL (1)
-
-/* @brief Pointer to ROM IAP entry functions */
-#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
-
-/* PINT module features */
-/* @brief Number of connected outputs */
-#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (4)
-/* @brief Number of PIOs */
-#define FSL_FEATURE_GPIO_PIO_COUNT (22)
-
-/* PMC module features */
-/* @brief FRO1M trim address */
-#define FSL_FEATURE_PMC_FRO1M_ADDRESS (0x9FCD0U)
-/* @brief FRO1M trim valid mask */
-#define FSL_FEATURE_PMC_FRO1M_VALID_MASK (0x1U)
-
-/* SPI module features */
-/* @brief SPI SIZE bitfile in FIFOCFG register */
-#define FSL_FEATURE_SPI_FIFOSIZE_CFG (1)
-/* @brief SPI has only three SSEL pins */
-#define FSL_FEATURE_IS_SPI_SSEL_PIN_COUNT_EQUAL_TO_THREE (1)
-
-/* ADC module features */
-/* @brief ADC data alignment mode */
-#define FSL_FEATURE_ADC_DAT_OF_HIGH_ALIGNMENT (1)
-/* @brief ADC synchronous mode do not modify CTRL.TSAMP [14:12] */
-#define FSL_FEATURE_ADC_SYNCHRONOUS_USE_GPADC_CTRL (1)
-/* @brief ADC temp cal flash addr */
-#define FSL_FEATURE_FLASH_ADDR_OF_TEMP_CAL (0x9FC80)
-/* @brief ADC temp cal flash data vaild mask*/
-#define FSL_FEATURE_FLASH_ADDR_OF_TEMP_CAL_VALID (0x1)
-/* @brief Has ASYNMODE bitfile in CTRL reigster. */
-#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1)
-/* @brief Has RESOL bitfile in CTRL reigster. */
-#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1)
-/* @brief Has BYPASSCAL bitfile in CTRL reigster. */
-#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (0)
-/* @brief Has TSAMP bitfile in CTRL reigster. */
-#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1)
-/* @brief ADC NO calibration*/
-#define FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC (1)
-/* @brief ADC TEMPSENSORCTRL in ASYNC_SYSCON*/
-#define FSL_FEATURE_ADC_ASYNC_SYSCON_TEMP (1)
-/* @brief ADC require a delay*/
-#define FSL_FEATURE_ADC_REQUIRE_DELAY (1)
-/* @brief Has LDO_POWER_EN bitfile in GPADC_CTRL0 register. */
-#define FSL_FEATURE_ADC_HAS_GPADC_CTRL0_LDO_POWER_EN (1)
-/* @brief Has OFFSET_CAL bitfile in GPADC_CTRL1 register. */
-#define FSL_FEATURE_ADC_HAS_GPADC_CTRL1_OFFSET_CAL (1)
-/* @brief Has ADC_INIT bitfile in STARTUP register. */
-#define FSL_FEATURE_ADC_HAS_STARTUP_ADC_INIT (0)
-/* @brief ADC has single SEQ */
-#define FSL_FEATURE_ADC_HAS_SINGLE_SEQ (1)
-/* SYSCON module features */
/* FLASH module features */
+
/* @brief P-Flash write unit size. */
#define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (512U)
/* @brief P-Flash sector size. */
#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (512U)
-/* @brief P-Flash block count */
+/* @brief P-Flash block count. */
#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
/* @brief P-Flash block size. */
#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0xA0000U)
+/* @brief ADC temp cal flash addr. */
+#define FSL_FEATURE_FLASH_ADDR_OF_TEMP_CAL (0x9FC80)
+/* @brief ADC temp cal flash data vaild mask. */
+#define FSL_FEATURE_FLASH_ADDR_OF_TEMP_CAL_VALID (0x1)
-/* CTIMER module features */
-/* @brief CTIMER capture channel 3. */
-#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1)
-/* @brief CTIMER capture 3 interrupt. */
-#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1)
+/* FLEXCOMM module features */
-/* WWDT module features */
-/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */
-#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (1)
-/* @brief WWDT NO PDCFG*/
-#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
+/* @brief Has no reset in FLEXCOMM register. */
+#define FSL_FEATURE_FLEXCOMM_HAS_NO_RESET (1)
+/* @brief USART availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCOMM_USART_COUNT (FSL_FEATURE_SOC_USART_COUNT)
+/* @brief SPI are FLEXCOMM on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCOMM_SPI_COUNT (FSL_FEATURE_SOC_SPI_COUNT)
+/* @brief I2C are FLEXCOMM on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCOMM_I2C_COUNT (FSL_FEATURE_SOC_I2C_COUNT)
+
+/* GPIO module features */
+
+/* @brief GPIO DIRSET and DIRCLR register. */
+#define FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR (1)
+/* @brief Number of PIOs. */
+#define FSL_FEATURE_GPIO_PIO_COUNT (22)
+/* @brief GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_GPIO_COUNT (FSL_FEATURE_SOC_LPC_GPIO_COUNT)
/* I2C module features */
-/* @brief I2C peripheral clock frequency 8MHz */
+
+/* @brief I2C peripheral clock frequency 8MHz. */
#define FSL_FEATURE_I2C_PREPCLKFRG_8MHZ (1)
-/* GPIO module feature */
-/* @brief GPIO DIRSET and DIRCLR register */
-#define FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR (1)
+/* IOCON module features */
-/* FMEAS module feature */
-/* @brief FMEAS FMEAS_INDEX is 20 */
-#define FSL_FEATURE_FMEAS_INDEX_20 (1)
-/* @brief FMEAS FREQMECTRL in ASYNC_SYSCON */
-#define FSL_FEATURE_FMEAS_ASYNC_SYSCON_FREQMECTRL (1)
-/* @brief FMEAS SYSCON use ASYNC_SYSCON */
-#define FSL_FEATURE_FMEAS_USE_ASYNC_SYSCON (1)
-/* @brief FMEAS start frequency with ASYNC_SYSCON */
-#define FSL_FEATURE_FMEAS_START_FRG_ASYNC_SYSCON (1)
-/* @brief FMEAS get frequency with ASYNC_SYSCON */
-#define FSL_FEATURE_FMEAS_GET_FRG_ASYNC_SYSCON (1)
-/* @brief FMEAS get clock count with scale */
-#define FSL_FEATURE_FMEAS_GET_COUNT_SCALE (1)
-/* @brief FMEAS start measure with scale */
-#define FSL_FEATURE_FMEAS_STARTMEAS_SCALE (1)
+/* @brief Func bit field width */
+#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (3)
+
+/* PINT module features */
+
+/* @brief Number of connected outputs */
+#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (4)
+
+/* PMC module features */
+
+/* @brief FRO1M trim address. */
+#define FSL_FEATURE_PMC_FRO1M_ADDRESS (0x9FCD0U)
+/* @brief FRO1M trim valid mask. */
+#define FSL_FEATURE_PMC_FRO1M_VALID_MASK (0x1U)
/* RTC module features */
+
/* @brief Has no separate RTC OSC PD in CTRL register. */
#define FSL_FEATURE_RTC_HAS_NO_OSC_PD (1)
-/* FLEXCOMM module features */
-/* @brief Has no reset in FLEXCOMM register. */
-#define FSL_FEATURE_FLEXCOMM_HAS_NO_RESET (1)
+/* SPI module features */
-#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (1)
-#endif /* _JN518X_FEATURES_H_ */
+/* @brief SPI SIZE bitfile in FIFOCFG register */
+#define FSL_FEATURE_SPI_FIFOSIZE_CFG (1)
+/* @brief SPI has only three SSEL pins */
+#define FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE (1)
+
+/* SPIFI module features */
+
+/* @brief SPIFI start address */
+#define FSL_FEATURE_SPIFI_START_ADDR (0x10000000)
+/* @brief SPIFI end address */
+#define FSL_FEATURE_SPIFI_END_ADDR (0x103FFFFF)
+/* @brief SPIFI DATALEN bitfile in CMD register */
+#define FSL_FEATURE_SPIFI_DATALEN_CTRL (1)
+
+/* WWDT module features */
+
+/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */
+#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (1)
+/* @brief WWDT NO PDCFG. */
+#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
+/* @brief WWDT LOCK bitfile in MOD register */
+#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1)
+
+#endif /* _K32W061_FEATURES_H_ */
diff --git a/third_party/nxp/JN5189/rom_apis/flash_header.h b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/flash_header.h
similarity index 100%
copy from third_party/nxp/JN5189/rom_apis/flash_header.h
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/flash_header.h
diff --git a/third_party/nxp/JN5189/drivers/aes/fsl_aes.c b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_aes.c
similarity index 100%
copy from third_party/nxp/JN5189/drivers/aes/fsl_aes.c
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_aes.c
diff --git a/third_party/nxp/JN5189/drivers/aes/fsl_aes.h b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_aes.h
similarity index 100%
copy from third_party/nxp/JN5189/drivers/aes/fsl_aes.h
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_aes.h
diff --git a/third_party/nxp/JN5189/drivers/fsl_clock.c b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_clock.c
similarity index 91%
copy from third_party/nxp/JN5189/drivers/fsl_clock.c
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_clock.c
index 003794c..ad8c160 100755
--- a/third_party/nxp/JN5189/drivers/fsl_clock.c
+++ b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_clock.c
@@ -10,6 +10,10 @@
/*******************************************************************************
* Definitions
******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.clock"
+#endif
#define OSC32K_FREQ 32768UL
#define FRO32K_FREQ 32768UL
#define OSC32M_FREQ 32000000UL
@@ -70,7 +74,7 @@
uint32_t CLOCK_GetWdtOscFreq(void);
uint32_t CLOCK_GetPWMClockFreq(void);
-static uint8_t CLOCK_u8OscCapConvert(uint8_t u8OscCap, uint8_t u8CapBankDiscontinuity);
+static uint8_t CLOCK_u8OscCapConvert(uint32_t OscCap, uint8_t u8CapBankDiscontinuity);
/*******************************************************************************
* types
@@ -157,6 +161,19 @@
pClkSel[mux] |= ((pos - 2) << SYSCON_OSC32CLKSEL_SEL32KHZ_SHIFT);
}
}
+ else if (mux == CM_MODEMCLKSEL)
+ {
+ if (pos < 2)
+ {
+ pClkSel[mux] |= SYSCON_MODEMCLKSEL_SEL_ZIGBEE_MASK;
+ pClkSel[mux] &= ((uint32_t)pos | 0x2U);
+ }
+ else
+ {
+ pClkSel[mux] |= SYSCON_MODEMCLKSEL_SEL_BLE_MASK;
+ pClkSel[mux] &= ((uint32_t)((pos - 2) << SYSCON_MODEMCLKSEL_SEL_BLE_SHIFT) | 0x1U);
+ }
+ }
else
{
pClkSel[mux] = pos;
@@ -726,6 +743,9 @@
case kCLOCK_ApbFro48M: /* FRO48M */
freq = CLOCK_GetFro48MFreq();
break;
+ default:
+ freq = 0;
+ break;
}
return freq;
@@ -755,7 +775,6 @@
switch (clk)
{
case kCLOCK_Xtal32k:
- PMC->PDRUNCFG &= ~PMC_PDRUNCFG_ENA_FRO32K_MASK;
PMC->PDRUNCFG |= PMC_PDRUNCFG_ENA_XTAL32K_MASK;
SYSCON->OSC32CLKSEL |= SYSCON_OSC32CLKSEL_SEL32KHZ_MASK;
break;
@@ -775,7 +794,6 @@
break;
case kCLOCK_Fro32k:
- PMC->PDRUNCFG &= ~PMC_PDRUNCFG_ENA_XTAL32K_MASK;
PMC->PDRUNCFG |= PMC_PDRUNCFG_ENA_FRO32K_MASK;
SYSCON->OSC32CLKSEL &= ~SYSCON_OSC32CLKSEL_SEL32KHZ_MASK;
break;
@@ -977,7 +995,7 @@
uint8_t u8IECXinCapCal6pF, u8IECXinCapCal8pF, u8IECXoutCapCal6pF, u8IECXoutCapCal8pF, u8XOSlave;
int32_t iaXin_x4, ibXin, iaXout_x4, ibXout;
int32_t iXOCapInpF_x100, iXOCapOutpF_x100;
- uint8_t u8XOCapInCtrl, u8XOCapOutCtrl;
+ uint32_t u32XOCapInCtrl, u32XOCapOutCtrl;
uint32_t u32RegVal;
/* Enable and set LDO, if not already done */
@@ -987,7 +1005,7 @@
u32XOTrimValue = GET_32MXO_TRIM();
/* Check validity and apply */
- if ((u32XOTrimValue & 1) && ((u32XOTrimValue >> 15) & 1) && (GET_CAL_DATE() >= 20180301))
+ if ((u32XOTrimValue & 1) && ((u32XOTrimValue >> 15) & 1) && (GET_CAL_DATE() >= 20181203))
{
/* These fields are 7 bits, unsigned */
u8IECXinCapCal6pF = (u32XOTrimValue >> 1) & 0x7f;
@@ -1022,11 +1040,11 @@
iXOCapOutpF_x100 = iXOCapOutpF_x100 + XO_32M_OSC_CAP_Delta_x1000 / 5;
/* In & out XO_OSC_CAP_Code_CTRL calculation, with rounding */
- u8XOCapInCtrl = (uint8_t)(((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400);
- u8XOCapOutCtrl = (uint8_t)(((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400);
+ u32XOCapInCtrl = (uint32_t)(((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400);
+ u32XOCapOutCtrl = (uint32_t)(((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400);
- u8XOCapInCtrl = CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13);
- u8XOCapOutCtrl = CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13);
+ uint8_t u8XOCapInCtrl = CLOCK_u8OscCapConvert(u32XOCapInCtrl, 13);
+ uint8_t u8XOCapOutCtrl = CLOCK_u8OscCapConvert(u32XOCapOutCtrl, 13);
/* Read register and clear fields to be written */
u32RegVal = ASYNC_SYSCON->XTAL32MCTRL;
@@ -1055,7 +1073,7 @@
uint8_t u8IECXinCapCal6pF, u8IECXinCapCal8pF, u8IECXoutCapCal6pF, u8IECXoutCapCal8pF;
int32_t iaXin_x4, ibXin, iaXout_x4, ibXout;
int32_t iXOCapInpF_x100, iXOCapOutpF_x100;
- uint8_t u8XOCapInCtrl, u8XOCapOutCtrl;
+ uint32_t u32XOCapInCtrl, u32XOCapOutCtrl;
uint32_t u32RegVal;
/* Get Cal values from Flash */
@@ -1092,11 +1110,11 @@
iXOCapOutpF_x100 = iXOCapOutpF_x100 + XO_32k_OSC_CAP_Delta_x1000 / 5;
/* In & out XO_OSC_CAP_Code_CTRL calculation, with rounding */
- u8XOCapInCtrl = (uint8_t)(((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400);
- u8XOCapOutCtrl = (uint8_t)(((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400);
+ u32XOCapInCtrl = (uint32_t)(((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400);
+ u32XOCapOutCtrl = (uint32_t)(((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400);
- u8XOCapInCtrl = CLOCK_u8OscCapConvert(u8XOCapInCtrl, 23);
- u8XOCapOutCtrl = CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 23);
+ uint8_t u8XOCapInCtrl = CLOCK_u8OscCapConvert(u32XOCapInCtrl, 23);
+ uint8_t u8XOCapOutCtrl = CLOCK_u8OscCapConvert(u32XOCapOutCtrl, 23);
/* Read register and clear fields to be written */
u32RegVal = SYSCON->XTAL32KCAP;
@@ -1151,79 +1169,31 @@
CLOCK_uDelay(u32AdditionalWait_us);
}
-static uint8_t CLOCK_u8OscCapConvert(uint8_t u8OscCap, uint8_t u8CapBankDiscontinuity)
+static uint8_t CLOCK_u8OscCapConvert(uint32_t OscCap_val, uint8_t u8CapBankDiscontinuity)
{
/* Compensate for discontinuity in the capacitor banks */
- if (u8OscCap < 64)
+ if (OscCap_val < 64)
{
- if (u8OscCap >= u8CapBankDiscontinuity)
+ if (OscCap_val >= u8CapBankDiscontinuity)
{
- u8OscCap -= u8CapBankDiscontinuity;
+ OscCap_val -= u8CapBankDiscontinuity;
}
else
{
- u8OscCap = 0;
+ OscCap_val = 0;
}
}
else
{
- if (u8OscCap <= (127 - u8CapBankDiscontinuity))
+ if (OscCap_val <= (127 - u8CapBankDiscontinuity))
{
- u8OscCap += u8CapBankDiscontinuity;
+ OscCap_val += u8CapBankDiscontinuity;
}
else
{
- u8OscCap = 127;
+ OscCap_val = 127;
}
}
- return u8OscCap;
-}
-
-/*!
- * brief Use DWT to delay at least for some time.
- * Please note that, this API will calculate the microsecond period with the maximum devices
- * supported CPU frequency, so this API will only delay for at least the given microseconds, if precise
- * delay count was needed, please implement a new timer count to achieve this function.
- *
- * param delay_us Delay time in unit of microsecond.
- */
-__attribute__((weak)) void SDK_DelayAtLeastUs(uint32_t delay_us)
-{
- assert(0U != delay_us);
- uint64_t count = 0U;
- uint32_t period = SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY / 1000000;
-
- /* Make sure the DWT trace fucntion is enabled. */
- if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR))
- {
- CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
- }
-
- /* CYCCNT not supported on this device. */
- assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk));
-
- /* If CYCCENT has already been enabled, read directly, otherwise, need enable it. */
- if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL))
- {
- DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
- }
-
- /* Calculate the count ticks. */
- count = DWT->CYCCNT;
- count += (uint64_t)period * delay_us;
-
- if (count > 0xFFFFFFFFUL)
- {
- count -= 0xFFFFFFFFUL;
- /* wait for cyccnt overflow. */
- while (count < DWT->CYCCNT)
- {
- }
- }
-
- /* Wait for cyccnt reach count value. */
- while (count > DWT->CYCCNT)
- {
- }
+ return (uint8_t)OscCap_val;
}
diff --git a/third_party/nxp/JN5189/drivers/fsl_clock.h b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_clock.h
similarity index 93%
copy from third_party/nxp/JN5189/drivers/fsl_clock.h
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_clock.h
index d1746af..1e28ade 100755
--- a/third_party/nxp/JN5189/drivers/fsl_clock.h
+++ b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_clock.h
@@ -20,6 +20,12 @@
/*! @file */
+/*! @name Driver version */
+/*@{*/
+/*! @brief CLOCK driver version 2.1.0. */
+#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*@}*/
+
#ifdef FPGA_50MHZ
#define SYSCON_BASE_CLOCK_DIV (6)
#define SYSCON_BASE_CLOCK_MUL (5)
@@ -134,10 +140,8 @@
*/
typedef enum _clock_name
{
- kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_ROM_SHIFT), /*!< ROM clock */
kCLOCK_Sram0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_SRAM_CTRL0_SHIFT), /*!< SRAM0 clock */
kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT), /*!< SRAM1 clock */
- kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_FLASH_SHIFT), /*!< Flash clock */
kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_SPIFI_SHIFT), /*!< SPIFI clock */
kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_MUX_SHIFT), /*!< InputMux clock */
kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_IOCON_SHIFT), /*!< IOCON clock */
@@ -154,7 +158,6 @@
kCLOCK_WakeTmr =
CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_WAKE_UP_TIMERS_SHIFT), /*!< Wake up Timers clock */
kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_ADC_SHIFT), /*!< ADC0 clock */
- kCLOCK_Efuse = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_EFUSE_SHIFT), /*!< EFuse clock */
kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_USART0_SHIFT), /*!< FlexComm0 clock */
kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_USART1_SHIFT), /*!< FlexComm1 clock */
kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_I2C0_SHIFT), /*!< FlexComm2 clock */
@@ -172,6 +175,7 @@
kCLOCK_Spi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_SPI0_SHIFT), /*!< SPI0 clock */
kCLOCK_Spi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_SPI1_SHIFT), /*!< SPI1 clock */
kCLOCK_I2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_I2C2_SHIFT), /*!< I2C2 clock */
+ kCLOCK_BLE = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_BLE_SHIFT), /*!< BLE clock */
kCLOCK_Modem = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_MODEM_MASTER_SHIFT), /*!< MODEM clock */
kCLOCK_Aes = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_AES_SHIFT), /*!< AES clock */
kCLOCK_Rfp = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_RFP_SHIFT), /*!< RFP clock */
@@ -246,7 +250,7 @@
kFRO32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), /*!< Select FRO 32K for CLKOUT */
kXTAL32M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), /*!< Select XTAL 32M for CLKOUT */
kDCDC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), /*!< Select DCDC for CLKOUT */
- kFROM48M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), /*!< Select FRO 48M for CLKOUT */
+ kFRO48M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), /*!< Select FRO 48M for CLKOUT */
kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), /*!< Select FRO 1M for CLKOUT */
kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), /*!< No clock for CLKOUT */
@@ -297,10 +301,13 @@
kFRO12M_to_DMI_CLK = MUX_A(CM_DMICLKSEL, 5), /*!< Select FRO 12M for DMIC */
kNONE_to_DMI_CLK = MUX_A(CM_DMICLKSEL, 6), /*!< No clock for DMIC */
- kOSC32K_to_WKT_CLK = MUX_A(CM_WKTCLKSEL, 0),
- kFRO1M_to_WKT_CLK = MUX_A(CM_WKTCLKSEL, 1),
- kNONE_to_WKT_CLK = MUX_A(CM_WKTCLKSEL, 2),
- kTESTCLK_to_WKT_CLK = MUX_A(CM_WKTCLKSEL, 3),
+ kOSC32K_to_WKT_CLK = MUX_A(CM_WKTCLKSEL, 0), /*!< Select OSC 32K for WKT */
+ kNONE_to_WKT_CLK = MUX_A(CM_WKTCLKSEL, 3), /*!< No clock for WKT */
+
+ kXTAL32M_DIV2_to_ZIGBEE_CLK = MUX_A(CM_MODEMCLKSEL, 0), /*!< Select XTAL 32M for ZIGBEE */
+ kNONE_to_ZIGBEE_CLK = MUX_A(CM_MODEMCLKSEL, 1), /*!< No clock for ZIGBEE */
+ kXTAL32M_to_BLE_CLK = MUX_A(CM_MODEMCLKSEL, 2), /*!< Select XTAL 32M for BLE */
+ kNONE_to_BLE_CLK = MUX_A(CM_MODEMCLKSEL, 3), /*!< No clock for BLE */
kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0), /*!< Select main clock for Asynchronous APB */
kXTAL32M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1), /*!< Select XTAL 32M for Asynchronous APB */
@@ -317,18 +324,18 @@
typedef enum _clock_div_name
{
kCLOCK_DivNone = 0,
- kCLOCK_DivSystickClk = (offsetof(SYSCON_Type, SYSTICKCLKDIV) / sizeof(uint32_t)),
- kCLOCK_DivWdtClk = (offsetof(SYSCON_Type, WDTCLKDIV) / sizeof(uint32_t)),
- kCLOCK_DivIrClk = (offsetof(SYSCON_Type, IRCLKDIV) / sizeof(uint32_t)),
- kCLOCK_DivAhbClk = (offsetof(SYSCON_Type, AHBCLKDIV) / sizeof(uint32_t)),
- kCLOCK_DivClkout = (offsetof(SYSCON_Type, CLKOUTDIV) / sizeof(uint32_t)),
- kCLOCK_DivSpifiClk = (offsetof(SYSCON_Type, SPIFICLKDIV) / sizeof(uint32_t)),
- kCLOCK_DivAdcClk = (offsetof(SYSCON_Type, ADCCLKDIV) / sizeof(uint32_t)),
- kCLOCK_DivRtcClk = (offsetof(SYSCON_Type, RTCCLKDIV) / sizeof(uint32_t)),
- kCLOCK_DivDmicClk = (offsetof(SYSCON_Type, DMICCLKDIV) / sizeof(uint32_t)),
- kCLOCK_DivRtc1HzClk = (offsetof(SYSCON_Type, RTC1HZCLKDIV) / sizeof(uint32_t)),
- kCLOCK_DivTraceClk = (offsetof(SYSCON_Type, TRACECLKDIV) / sizeof(uint32_t)),
- kCLOCK_DivFrg = (offsetof(SYSCON_Type, FRGCTRL) / sizeof(uint32_t))
+ kCLOCK_DivSystickClk = (offsetof(SYSCON_Type, SYSTICKCLKDIV) / sizeof(uint32_t)), /*!< SYSTICK clock divider */
+ kCLOCK_DivTraceClk = (offsetof(SYSCON_Type, TRACECLKDIV) / sizeof(uint32_t)), /*!< TRACE clock divider */
+ kCLOCK_DivWdtClk = (offsetof(SYSCON_Type, WDTCLKDIV) / sizeof(uint32_t)), /*!< Watchdog Timer clock divider */
+ kCLOCK_DivIrClk = (offsetof(SYSCON_Type, IRCLKDIV) / sizeof(uint32_t)), /*!< Infra Red clock divider */
+ kCLOCK_DivAhbClk = (offsetof(SYSCON_Type, AHBCLKDIV) / sizeof(uint32_t)), /*!< System clock divider */
+ kCLOCK_DivClkout = (offsetof(SYSCON_Type, CLKOUTDIV) / sizeof(uint32_t)), /*!< CLKOUT clock divider */
+ kCLOCK_DivSpifiClk = (offsetof(SYSCON_Type, SPIFICLKDIV) / sizeof(uint32_t)), /*!< SPIFI clock divider */
+ kCLOCK_DivAdcClk = (offsetof(SYSCON_Type, ADCCLKDIV) / sizeof(uint32_t)), /*!< ADC clock divider */
+ kCLOCK_DivRtcClk = (offsetof(SYSCON_Type, RTCCLKDIV) / sizeof(uint32_t)), /*!< Real Time Clock divider */
+ kCLOCK_DivDmicClk = (offsetof(SYSCON_Type, DMICCLKDIV) / sizeof(uint32_t)), /*!< DMIC clock divider */
+ kCLOCK_DivRtc1HzClk = (offsetof(SYSCON_Type, RTC1HZCLKDIV) / sizeof(uint32_t)), /*!< Real Time Clock divider */
+ kCLOCK_DivFrg = (offsetof(SYSCON_Type, FRGCTRL) / sizeof(uint32_t)) /*!< FRG Clock divider */
} clock_div_name_t;
/*! @brief Clock source selections for the Main Clock */
@@ -447,9 +454,13 @@
uint32_t clk_XtalNPcbParCappF_x100; /*< XTAL PCB -ve parasitic capacitance */
} ClockCapacitanceCompensation_t;
-#ifdef __cplusplus
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
extern "C" {
-#endif
+#endif /* __cplusplus */
/**
* @brief Obtains frequency of specified clock
@@ -572,16 +583,6 @@
*/
void CLOCK_Xtal32M_WaitUntilStable(uint32_t u32AdditionalWait_us);
-/*!
- * @brief Use DWT to delay at least for some time.
- * Please note that, this API will calculate the microsecond period with the maximum devices
- * supported CPU frequency, so this API will only delay for at least the given microseconds, if precise
- * delay count was needed, please implement a new timer count to achieve this function.
- *
- * @param delay_us Delay time in unit of microsecond.
- */
-void SDK_DelayAtLeastUs(uint32_t delay_us);
-
#if defined(__cplusplus)
}
#endif /* __cplusplus */
diff --git a/third_party/nxp/JN5189/drivers/fsl_common.h b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_common.h
similarity index 97%
copy from third_party/nxp/JN5189/drivers/fsl_common.h
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_common.h
index 4e79ae6..c5e1c2f 100755
--- a/third_party/nxp/JN5189/drivers/fsl_common.h
+++ b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_common.h
@@ -38,8 +38,8 @@
/*! @name Driver version */
/*@{*/
-/*! @brief common driver version 2.1.3. */
-#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
+/*! @brief common driver version 2.2.0. */
+#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
/*@}*/
/* Debug console type definition. */
@@ -611,6 +611,16 @@
*/
void SDK_Free(void *ptr);
+ /*!
+ * @brief Delay at least for some time.
+ * Please note that, this API uses while loop for delay, different run-time environments make the time not precise,
+ * if precise delay count was needed, please implement a new delay function with hardware timer.
+ *
+ * @param delay_us Delay time in unit of microsecond.
+ * @param coreClock_Hz Core clock frequency with Hz.
+ */
+ void SDK_DelayAtLeastUs(uint32_t delay_us, uint32_t coreClock_Hz);
+
#if defined(__cplusplus)
}
#endif
diff --git a/third_party/nxp/JN5189/drivers/fsl_ctimer.c b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_ctimer.c
similarity index 100%
copy from third_party/nxp/JN5189/drivers/fsl_ctimer.c
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_ctimer.c
diff --git a/third_party/nxp/JN5189/drivers/fsl_ctimer.h b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_ctimer.h
similarity index 100%
copy from third_party/nxp/JN5189/drivers/fsl_ctimer.h
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_ctimer.h
diff --git a/third_party/nxp/JN5189/drivers/fsl_flash.c b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_flash.c
similarity index 100%
copy from third_party/nxp/JN5189/drivers/fsl_flash.c
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_flash.c
diff --git a/third_party/nxp/JN5189/drivers/fsl_flash.h b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_flash.h
similarity index 100%
copy from third_party/nxp/JN5189/drivers/fsl_flash.h
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_flash.h
diff --git a/third_party/nxp/JN5189/drivers/fsl_flexcomm.c b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_flexcomm.c
similarity index 100%
copy from third_party/nxp/JN5189/drivers/fsl_flexcomm.c
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_flexcomm.c
diff --git a/third_party/nxp/JN5189/drivers/fsl_flexcomm.h b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_flexcomm.h
similarity index 100%
copy from third_party/nxp/JN5189/drivers/fsl_flexcomm.h
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_flexcomm.h
diff --git a/third_party/nxp/JN5189/drivers/fsl_gpio.c b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_gpio.c
similarity index 100%
copy from third_party/nxp/JN5189/drivers/fsl_gpio.c
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_gpio.c
diff --git a/third_party/nxp/JN5189/drivers/fsl_gpio.h b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_gpio.h
similarity index 100%
copy from third_party/nxp/JN5189/drivers/fsl_gpio.h
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_gpio.h
diff --git a/third_party/nxp/JN5189/drivers/fsl_iocon.h b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_iocon.h
similarity index 93%
copy from third_party/nxp/JN5189/drivers/fsl_iocon.h
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_iocon.h
index 78e765a..1b0c3da 100755
--- a/third_party/nxp/JN5189/drivers/fsl_iocon.h
+++ b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_iocon.h
@@ -60,7 +60,7 @@
#define IOCON_MODE_PULLDOWN IOCON_PIO_MODE(3) /*!< Selects pull-down function */
#define IOCON_HYS_EN (0x1 << 5) /*!< Enables hysteresis ??*/
-#define IOCON_GPIO_MODE IOCON_PIO_SLEW0(1) /*!< GPIO Mode */
+#define IOCON_GPIO_MODE IOCON_PIO_EGP(1) /*!< GPIO Mode */
#define IOCON_I2C_SLEW IOCON_PIO_SLEW0(1) /*!< I2C Slew Rate Control */
#define IOCON_INV_EN IOCON_PIO_INVERT(1) /*!< Enables invert function on input */
@@ -90,6 +90,14 @@
#define IOCON_IO_CLAMPING_NORMAL_MFIO (1 << 11)
#define IOCON_IO_CLAMPING_COMBO_MFIO_I2C (1 << 12) /* Use this flag for PIO11 and PIO12 only */
+#define IOCON_PIO_DBG_FUNC_MASK (0xF000U)
+#define IOCON_PIO_DBG_FUNC_SHIFT (12U)
+#define IOCON_PIO_DBG_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DBG_FUNC_SHIFT)) & IOCON_PIO_DBG_FUNC_MASK)
+#define IOCON_PIO_DBG_MODE_MASK (0x10000U)
+#define IOCON_PIO_DBG_MODE_SHIFT (16U)
+#define IOCON_PIO_DBG_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DBG_MODE_SHIFT)) & IOCON_PIO_DBG_MODE_MASK)
+
+
#define IOCON_CFG(dbg_func) (IOCON_PIO_FUNC(0) | IOCON_MODE_PULLDOWN |\
IOCON_DIGITAL_EN | IOCON_INPFILT_OFF | \
IOCON_PIO_DBG_FUNC(dbg_func) | IOCON_PIO_DBG_MODE(1))
diff --git a/third_party/nxp/JN5189/drivers/fsl_power.c b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_power.c
similarity index 100%
copy from third_party/nxp/JN5189/drivers/fsl_power.c
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_power.c
diff --git a/third_party/nxp/JN5189/drivers/fsl_power.h b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_power.h
similarity index 100%
copy from third_party/nxp/JN5189/drivers/fsl_power.h
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_power.h
diff --git a/third_party/nxp/JN5189/drivers/fsl_reset.c b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_reset.c
similarity index 91%
copy from third_party/nxp/JN5189/drivers/fsl_reset.c
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_reset.c
index a0ba825..c4a584d 100755
--- a/third_party/nxp/JN5189/drivers/fsl_reset.c
+++ b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_reset.c
@@ -14,8 +14,12 @@
/*******************************************************************************
* Definitions
******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.reset"
+#endif
/* RG TODO This should be defined in jn518x.h */
-#define SYSCON_PRESETCTRL_COUNT 2
+#define SYSCON_PRESETCTRL_COUNT 2
/*******************************************************************************
* Variables
@@ -43,8 +47,8 @@
void RESET_SetPeripheralReset(reset_ip_name_t peripheral)
{
const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
- const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
- const uint32_t bitMask = 1u << bitPos;
+ const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
+ const uint32_t bitMask = 1u << bitPos;
assert(bitPos < 32u);
@@ -84,8 +88,8 @@
void RESET_ClearPeripheralReset(reset_ip_name_t peripheral)
{
const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
- const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
- const uint32_t bitMask = 1u << bitPos;
+ const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
+ const uint32_t bitMask = 1u << bitPos;
assert(bitPos < 32u);
@@ -130,7 +134,6 @@
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */
-
/*!
* brief Reset the chip.
*
diff --git a/third_party/nxp/JN5189/drivers/fsl_reset.h b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_reset.h
similarity index 87%
copy from third_party/nxp/JN5189/drivers/fsl_reset.h
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_reset.h
index 731a52e..cd43a11 100755
--- a/third_party/nxp/JN5189/drivers/fsl_reset.h
+++ b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_reset.h
@@ -24,6 +24,12 @@
* Definitions
******************************************************************************/
+/*! @name Driver version */
+/*@{*/
+/*! @brief RESET driver version 2.0.1. */
+#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
/*!
* @brief Enumeration for peripheral reset control bits
*
@@ -31,20 +37,19 @@
*/
typedef enum _SYSCON_RSTn
{
- kFLASH_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_FLASH_RST_SHIFT), /**< Flash controller reset control */
- kSPIFI_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_SPIFI_RST_SHIFT), /**< SpiFi reset control */
- kMUX_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_MUX_RST_SHIFT), /**< Input mux reset control */
- kIOCON_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_IOCON_RST_SHIFT), /**< IOCON reset control */
- kGPIO0_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_GPIO_RST_SHIFT), /**< GPIO0 reset control */
- kPINT_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_PINT_RST_SHIFT), /**< Pin interrupt (PINT) reset control */
- kGINT_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_GINT_RST_SHIFT), /**< Grouped interrupt (PINT) reset control. */
- kDMA_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_DMA_RST_SHIFT), /**< DMA reset control */
- kWWDT_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_WWDT_RST_SHIFT), /**< Watchdog timer reset control */
- kRTC_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_RTC_RST_SHIFT), /**< RTC reset control */
+ kSPIFI_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_SPIFI_RST_SHIFT), /**< SpiFi reset control */
+ kMUX_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_MUX_RST_SHIFT), /**< Input mux reset control */
+ kBLE_TG_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_BLE_TIMING_GEN_RST_SHIFT), /**< BLE power module reset control */
+ kIOCON_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_IOCON_RST_SHIFT), /**< IOCON reset control */
+ kGPIO0_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_GPIO_RST_SHIFT), /**< GPIO0 reset control */
+ kPINT_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_PINT_RST_SHIFT), /**< Pin interrupt (PINT) reset control */
+ kGINT_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_GINT_RST_SHIFT), /**< Grouped interrupt (PINT) reset control. */
+ kDMA_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_DMA_RST_SHIFT), /**< DMA reset control */
+ kWWDT_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_WWDT_RST_SHIFT), /**< Watchdog timer reset control */
+ kRTC_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_RTC_RST_SHIFT), /**< RTC reset control */
kANA_INT_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_ANA_INT_CTRL_RST_SHIFT), /**< Analog interrupt controller reset */
kWKT_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_WAKE_UP_TIMERS_RST_SHIFT), /**< Wakeup timer reset */
kADC0_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_ADC_RST_SHIFT), /**< ADC0 reset control */
- kEFUSE_RST_SHIFT_RSTn = (0 | SYSCON_PRESETCTRL0_EFUSE_RST_SHIFT), /**< EFUSE reset control */
kFC0_RST_SHIFT_RSTn =
((1UL << 16) | SYSCON_PRESETCTRL1_USART0_RST_SHIFT), /**< Flexcomm Interface 0 reset control */
kFC1_RST_SHIFT_RSTn =
@@ -65,6 +70,7 @@
kSPI0_RST_SHIFT_RSTn = kFC4_RST_SHIFT_RSTn, /**< SPI0 reset control == Flexcomm 4 */
kSPI1_RST_SHIFT_RSTn = kFC5_RST_SHIFT_RSTn, /**< SPI1 reset control == Flexcomm 5 */
kI2C2_RST_SHIFT_RSTn = kFC6_RST_SHIFT_RSTn, /**< I2C2 reset control == Flexcomm 6 */
+ kBLE_RST_SHIFT_RSTn = ((1UL << 16) | SYSCON_PRESETCTRL1_BLE_RST_SHIFT), /**< Bluetooth LE modules reset control */
kMODEM_MASTER_SHIFT_RSTn =
((1UL << 16) | SYSCON_PRESETCTRL1_MODEM_MASTER_RST_SHIFT), /**< AHB Modem master interface reset */
kAES_RST_SHIFT_RSTn = ((1UL << 16) | SYSCON_PRESETCTRL1_AES_RST_SHIFT), /**< Encryption module reset control */
diff --git a/third_party/nxp/JN5189/drivers/fsl_rng.c b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_rng.c
similarity index 100%
copy from third_party/nxp/JN5189/drivers/fsl_rng.c
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_rng.c
diff --git a/third_party/nxp/JN5189/drivers/fsl_rng.h b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_rng.h
similarity index 100%
copy from third_party/nxp/JN5189/drivers/fsl_rng.h
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_rng.h
diff --git a/third_party/nxp/JN5189/drivers/sha/fsl_sha.c b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_sha.c
similarity index 100%
copy from third_party/nxp/JN5189/drivers/sha/fsl_sha.c
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_sha.c
diff --git a/third_party/nxp/JN5189/drivers/sha/fsl_sha.h b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_sha.h
similarity index 100%
copy from third_party/nxp/JN5189/drivers/sha/fsl_sha.h
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_sha.h
diff --git a/third_party/nxp/JN5189/drivers/fsl_usart.c b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_usart.c
similarity index 100%
copy from third_party/nxp/JN5189/drivers/fsl_usart.c
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_usart.c
diff --git a/third_party/nxp/JN5189/drivers/fsl_usart.h b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_usart.h
similarity index 100%
copy from third_party/nxp/JN5189/drivers/fsl_usart.h
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_usart.h
diff --git a/third_party/nxp/JN5189/drivers/fsl_wtimer.c b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_wtimer.c
similarity index 100%
copy from third_party/nxp/JN5189/drivers/fsl_wtimer.c
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_wtimer.c
diff --git a/third_party/nxp/JN5189/drivers/fsl_wtimer.h b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_wtimer.h
similarity index 100%
copy from third_party/nxp/JN5189/drivers/fsl_wtimer.h
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_wtimer.h
diff --git a/third_party/nxp/JN5189/rom_apis/rom_aes.h b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/rom_aes.h
similarity index 100%
copy from third_party/nxp/JN5189/rom_apis/rom_aes.h
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/rom_aes.h
diff --git a/third_party/nxp/JN5189/rom_apis/rom_api.h b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/rom_api.h
similarity index 95%
copy from third_party/nxp/JN5189/rom_apis/rom_api.h
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/rom_api.h
index fcf35b5..569bb7e 100755
--- a/third_party/nxp/JN5189/rom_apis/rom_api.h
+++ b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/rom_api.h
@@ -28,11 +28,20 @@
#include "rom_psector.h"
#include "flash_header.h"
#include "rom_aes.h"
+#include "rom_efuse.h"
/****************************************************************************/
/*** Macro Definitions ***/
/****************************************************************************/
-
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.jn_romapi"
+#endif
+/*! @name Driver version */
+/*@{*/
+/*! @brief JN_ROMAPI driver version 2.0.0. */
+#define FSL_JN_ROMAPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
/****************************************************************************/
/*** Type Definitions ***/
/****************************************************************************/
diff --git a/third_party/nxp/K32W061DK6/devices/K32W061/drivers/rom_common.h b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/rom_common.h
new file mode 100755
index 0000000..ae8efd9
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/rom_common.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ROM_COMMON_H_
+#define ROM_COMMON_H_
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+/****************************************************************************/
+/*** Include Files ***/
+/****************************************************************************/
+
+#include <stdbool.h>
+
+/****************************************************************************/
+/*** Macro Definitions ***/
+/****************************************************************************/
+
+/* Define ROM compilation for ES2 - required for lowpower API as it supports ES1/ES2 compilation */
+//#define CPU_JN518X_REV 2
+
+#ifdef ROM_BUILD
+#define ROM_API __attribute__((section(".text.api")))
+#else
+#ifdef __MINGW32__
+#define ROM_API
+#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || (defined(__ICCARM__))
+#define ROM_API
+#else
+#define ROM_API __attribute__((long_call))
+#endif
+#endif
+
+#ifndef WEAK
+#define WEAK __attribute__((weak))
+#endif
+
+#ifdef __CDT_PARSER__
+#define STATIC_ASSERT(value, message)
+#else
+#define STATIC_ASSERT _Static_assert
+#endif
+
+/****************************************************************************/
+/*** Type Definitions ***/
+/****************************************************************************/
+
+/****************************************************************************/
+/*** Exported Functions ***/
+/****************************************************************************/
+
+/****************************************************************************/
+/*** Exported Variables ***/
+/****************************************************************************/
+
+#if defined __cplusplus
+}
+#endif
+
+#endif /* ROM_COMMON_H_ */
+
+/****************************************************************************/
+/*** END OF FILE ***/
+/****************************************************************************/
diff --git a/third_party/nxp/K32W061DK6/devices/K32W061/drivers/rom_efuse.h b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/rom_efuse.h
new file mode 100755
index 0000000..1f1badb
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/rom_efuse.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ROM_EFUSE_H_
+#define ROM_EFUSE_H_
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+/****************************************************************************/
+/*** Include Files ***/
+/****************************************************************************/
+
+#include <rom_common.h>
+
+/****************************************************************************/
+/*** Macro Definitions ***/
+/****************************************************************************/
+
+/****************************************************************************/
+/*** Type Definitions ***/
+/****************************************************************************/
+
+/****************************************************************************/
+/*** Exported Functions ***/
+/****************************************************************************/
+static inline bool efuse_ReadBit(uint8_t efuse_bitpos)
+{
+ bool (*p_efuse_ReadBit)(uint8_t bitpos);
+ p_efuse_ReadBit = (bool (*)(uint8_t bitpos))0x03001671U;
+
+ return p_efuse_ReadBit(efuse_bitpos);
+}
+/****************************************************************************/
+/*** Exported Variables
+ ***/
+/****************************************************************************/
+
+#if defined __cplusplus
+}
+#endif
+
+#endif /* ROM_EFUSE_H_ */
+
+/****************************************************************************/
+/*** END OF FILE ***/
+/****************************************************************************/
diff --git a/third_party/nxp/JN5189/rom_apis/rom_lowpower.h b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/rom_lowpower.h
similarity index 97%
copy from third_party/nxp/JN5189/rom_apis/rom_lowpower.h
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/rom_lowpower.h
index 49a7a4f..33e03d5 100755
--- a/third_party/nxp/JN5189/rom_apis/rom_lowpower.h
+++ b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/rom_lowpower.h
@@ -15,11 +15,13 @@
#include <rom_common.h>
#include <rom_pmc.h>
-/** @defgroup LOWPOWER_JN518X CHIP: JN518X LOWPOWER Driver
- * @ingroup CHIP_JN518X_DRIVERS
+/*!
+ * @addtogroup ROM_API
* @{
*/
+/*! @file */
+
/*******************
* EXPORTED MACROS *
********************/
@@ -389,8 +391,8 @@
*/
static inline void Chip_LOWPOWER_SetUpLowPowerModeWakeUpTimer(LPC_LOWPOWER_T *p_lowpower_cfg)
{
- void (*p_Chip_LOWPOWER_SetUpLowPowerModeWakeUpTimer)(LPC_LOWPOWER_T *p_lowpower_cfg);
- p_Chip_LOWPOWER_SetUpLowPowerModeWakeUpTimer = (void (*)(LPC_LOWPOWER_T *p_lowpower_cfg))0x030038d1U;
+ void (*p_Chip_LOWPOWER_SetUpLowPowerModeWakeUpTimer)(LPC_LOWPOWER_T * p_lowpower_cfg);
+ p_Chip_LOWPOWER_SetUpLowPowerModeWakeUpTimer = (void (*)(LPC_LOWPOWER_T * p_lowpower_cfg))0x030038d1U;
p_Chip_LOWPOWER_SetUpLowPowerModeWakeUpTimer(p_lowpower_cfg);
}
@@ -429,8 +431,8 @@
*/
static inline void Chip_LOWPOWER_GetSystemVoltages(LPC_LOWPOWER_LDOVOLTAGE_T *p_ldo_voltage)
{
- void (*p_Chip_LOWPOWER_GetSystemVoltages)(LPC_LOWPOWER_LDOVOLTAGE_T *p_ldo_voltage);
- p_Chip_LOWPOWER_GetSystemVoltages = (void (*)(LPC_LOWPOWER_LDOVOLTAGE_T *p_ldo_voltage))0x03003de1U;
+ void (*p_Chip_LOWPOWER_GetSystemVoltages)(LPC_LOWPOWER_LDOVOLTAGE_T * p_ldo_voltage);
+ p_Chip_LOWPOWER_GetSystemVoltages = (void (*)(LPC_LOWPOWER_LDOVOLTAGE_T * p_ldo_voltage))0x03003de1U;
p_Chip_LOWPOWER_GetSystemVoltages(p_ldo_voltage);
}
@@ -442,8 +444,8 @@
*/
static inline void Chip_LOWPOWER_SetSystemVoltages(LPC_LOWPOWER_LDOVOLTAGE_T *p_ldo_voltage)
{
- void (*p_Chip_LOWPOWER_SetSystemVoltages)(LPC_LOWPOWER_LDOVOLTAGE_T *p_ldo_voltage);
- p_Chip_LOWPOWER_SetSystemVoltages = (void (*)(LPC_LOWPOWER_LDOVOLTAGE_T *p_ldo_voltage))0x03003e99U;
+ void (*p_Chip_LOWPOWER_SetSystemVoltages)(LPC_LOWPOWER_LDOVOLTAGE_T * p_ldo_voltage);
+ p_Chip_LOWPOWER_SetSystemVoltages = (void (*)(LPC_LOWPOWER_LDOVOLTAGE_T * p_ldo_voltage))0x03003e99U;
p_Chip_LOWPOWER_SetSystemVoltages(p_ldo_voltage);
}
@@ -455,8 +457,8 @@
*/
static inline void Chip_LOWPOWER_SetLowPowerMode(LPC_LOWPOWER_T *p_lowpower_cfg)
{
- void (*p_Chip_LOWPOWER_SetLowPowerMode)(LPC_LOWPOWER_T *p_lowpower_cfg);
- p_Chip_LOWPOWER_SetLowPowerMode = (void (*)(LPC_LOWPOWER_T *p_lowpower_cfg))0x0300404dU;
+ void (*p_Chip_LOWPOWER_SetLowPowerMode)(LPC_LOWPOWER_T * p_lowpower_cfg);
+ p_Chip_LOWPOWER_SetLowPowerMode = (void (*)(LPC_LOWPOWER_T * p_lowpower_cfg))0x0300404dU;
p_Chip_LOWPOWER_SetLowPowerMode(p_lowpower_cfg);
}
@@ -503,4 +505,4 @@
}
#endif
-#endif /* __LOWPOWER_JN518X_H_ */
+#endif /* __ROM_LOWPOWER_H_ */
diff --git a/third_party/nxp/JN5189/rom_apis/rom_mpu.h b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/rom_mpu.h
similarity index 100%
copy from third_party/nxp/JN5189/rom_apis/rom_mpu.h
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/rom_mpu.h
diff --git a/third_party/nxp/JN5189/rom_apis/rom_pmc.h b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/rom_pmc.h
similarity index 100%
copy from third_party/nxp/JN5189/rom_apis/rom_pmc.h
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/rom_pmc.h
diff --git a/third_party/nxp/JN5189/rom_apis/rom_psector.h b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/rom_psector.h
similarity index 99%
copy from third_party/nxp/JN5189/rom_apis/rom_psector.h
copy to third_party/nxp/K32W061DK6/devices/K32W061/drivers/rom_psector.h
index e5474f1..e27d231 100755
--- a/third_party/nxp/JN5189/rom_apis/rom_psector.h
+++ b/third_party/nxp/K32W061DK6/devices/K32W061/drivers/rom_psector.h
@@ -213,7 +213,7 @@
* 0 means invalid
* Any other value means valid
*/
- uint32_t backdoor_disable; /*!< Back door control:
+ uint32_t hwtestmode_disable; /*< HW test mode control:
* 0 means enabled
* Any other value means disabled
*/
diff --git a/third_party/nxp/K32W061DK6/devices/K32W061/fsl_device_registers.h b/third_party/nxp/K32W061DK6/devices/K32W061/fsl_device_registers.h
new file mode 100755
index 0000000..396fb9c
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/devices/K32W061/fsl_device_registers.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if (defined(CPU_K32W061HN) || defined(CPU_K32W041HN) || defined(CPU_JN518X))
+
+#define JN518X_SERIES
+
+#define K32W061_SERIES
+
+/* CMSIS-style register definitions */
+#include "K32W061.h"
+/* CPU specific feature definitions */
+#include "K32W061_features.h"
+
+#else
+#error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/third_party/nxp/K32W061DK6/devices/K32W061/mcuxpresso/startup_k32w061.c b/third_party/nxp/K32W061DK6/devices/K32W061/mcuxpresso/startup_k32w061.c
new file mode 100755
index 0000000..fdf1128
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/devices/K32W061/mcuxpresso/startup_k32w061.c
@@ -0,0 +1,917 @@
+//*****************************************************************************
+// K32W061 startup code for use with MCUXpresso IDE
+//
+// Version : 211119
+//*****************************************************************************
+//
+// Copyright 2016-2019 NXP
+// All rights reserved.
+//
+// SPDX-License-Identifier: BSD-3-Clause
+//*****************************************************************************
+
+#if defined(DEBUG)
+#pragma GCC push_options
+#pragma GCC optimize("Og")
+#endif // (DEBUG)
+
+#if defined(__cplusplus)
+#ifdef __REDLIB__
+#error Redlib does not support C++
+#else
+//*****************************************************************************
+//
+// The entry point for the C++ library startup
+//
+//*****************************************************************************
+extern "C" {
+extern void __libc_init_array(void);
+}
+#endif
+#endif
+
+#define WEAK __attribute__((weak))
+#define WEAK_AV __attribute__((weak, section(".after_vectors")))
+#define ALIAS(f) __attribute__((weak, alias(#f)))
+
+//*****************************************************************************
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+//*****************************************************************************
+// Variable to store CRP value in. Will be placed automatically
+// by the linker when "Enable Code Read Protect" selected.
+// See crp.h header for more information
+//*****************************************************************************
+#if (defined(__MCUXPRESSO))
+#include <NXP/crp.h>
+__CRP const unsigned int CRP_WORD = CRP_NO_CRP;
+#endif
+
+#include "fsl_device_registers.h"
+#include "rom_api.h"
+
+#define PMC_PDSLEEPCFG_PDEN_PD_MEM_ALL_MASK \
+ (PMC_PDSLEEPCFG_PDEN_PD_MEM0_MASK | PMC_PDSLEEPCFG_PDEN_PD_MEM1_MASK | PMC_PDSLEEPCFG_PDEN_PD_MEM2_MASK | \
+ PMC_PDSLEEPCFG_PDEN_PD_MEM3_MASK | PMC_PDSLEEPCFG_PDEN_PD_MEM4_MASK | PMC_PDSLEEPCFG_PDEN_PD_MEM5_MASK | \
+ PMC_PDSLEEPCFG_PDEN_PD_MEM6_MASK | PMC_PDSLEEPCFG_PDEN_PD_MEM7_MASK | PMC_PDSLEEPCFG_PDEN_PD_MEM8_MASK | \
+ PMC_PDSLEEPCFG_PDEN_PD_MEM9_MASK | PMC_PDSLEEPCFG_PDEN_PD_MEM10_MASK | PMC_PDSLEEPCFG_PDEN_PD_MEM11_MASK)
+
+//*****************************************************************************
+// Declaration of external SystemInit function
+//*****************************************************************************
+extern WEAK void SystemInit(void);
+
+//*****************************************************************************
+// Declaration of external WarmMain function
+//*****************************************************************************
+extern WEAK void WarmMain(void);
+
+//*****************************************************************************
+// Forward declaration of the core exception handlers.
+// When the application defines a handler (with the same name), this will
+// automatically take precedence over these weak definitions.
+// If your application is a C++ one, then any interrupt handlers defined
+// in C++ files within in your main application will need to have C linkage
+// rather than C++ linkage. To do this, make sure that you are using extern "C"
+// { .... } around the interrupt handler within your main application code.
+//*****************************************************************************
+void ResetISR(void);
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+WEAK void MemManage_Handler(void);
+WEAK void BusFault_Handler(void);
+WEAK void UsageFault_Handler(void);
+WEAK void SVC_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+WEAK void IntDefaultHandler(void);
+
+//*****************************************************************************
+// Forward declaration of the application IRQ handlers. When the application
+// defines a handler (with the same name), this will automatically take
+// precedence over weak definitions below
+//*****************************************************************************
+WEAK void WDT_BOD_IRQHandler(void);
+WEAK void DMA0_IRQHandler(void);
+WEAK void GINT0_IRQHandler(void);
+WEAK void CIC_IRB_IRQHandler(void);
+WEAK void PIN_INT0_IRQHandler(void);
+WEAK void PIN_INT1_IRQHandler(void);
+WEAK void PIN_INT2_IRQHandler(void);
+WEAK void PIN_INT3_IRQHandler(void);
+WEAK void SPIFI0_IRQHandler(void);
+WEAK void CTIMER0_IRQHandler(void);
+WEAK void CTIMER1_IRQHandler(void);
+WEAK void FLEXCOMM0_IRQHandler(void);
+WEAK void FLEXCOMM1_IRQHandler(void);
+WEAK void FLEXCOMM2_IRQHandler(void);
+WEAK void FLEXCOMM3_IRQHandler(void);
+WEAK void FLEXCOMM4_IRQHandler(void);
+WEAK void FLEXCOMM5_IRQHandler(void);
+WEAK void PWM0_IRQHandler(void);
+WEAK void PWM1_IRQHandler(void);
+WEAK void PWM2_IRQHandler(void);
+WEAK void PWM3_IRQHandler(void);
+WEAK void PWM4_IRQHandler(void);
+WEAK void PWM5_IRQHandler(void);
+WEAK void PWM6_IRQHandler(void);
+WEAK void PWM7_IRQHandler(void);
+WEAK void PWM8_IRQHandler(void);
+WEAK void PWM9_IRQHandler(void);
+WEAK void PWM10_IRQHandler(void);
+WEAK void FLEXCOMM6_IRQHandler(void);
+WEAK void RTC_IRQHandler(void);
+WEAK void NFCTag_IRQHandler(void);
+WEAK void MAILBOX_IRQHandler(void);
+WEAK void ADC0_SEQA_IRQHandler(void);
+WEAK void ADC0_SEQB_IRQHandler(void);
+WEAK void ADC0_THCMP_IRQHandler(void);
+WEAK void DMIC0_IRQHandler(void);
+WEAK void HWVAD0_IRQHandler(void);
+WEAK void BLE_DP_IRQHandler(void);
+WEAK void BLE_DP0_IRQHandler(void);
+WEAK void BLE_DP1_IRQHandler(void);
+WEAK void BLE_DP2_IRQHandler(void);
+WEAK void BLE_LL_ALL_IRQHandler(void);
+WEAK void ZIGBEE_MAC_IRQHandler(void);
+WEAK void ZIGBEE_MODEM_IRQHandler(void);
+WEAK void RFP_TMU_IRQHandler(void);
+WEAK void RFP_AGC_IRQHandler(void);
+WEAK void ISO7816_IRQHandler(void);
+WEAK void ANA_COMP_IRQHandler(void);
+WEAK void WAKE_UP_TIMER0_IRQHandler(void);
+WEAK void WAKE_UP_TIMER1_IRQHandler(void);
+WEAK void PVTVF0_AMBER_IRQHandler(void);
+WEAK void PVTVF0_RED_IRQHandler(void);
+WEAK void PVTVF1_AMBER_IRQHandler(void);
+WEAK void PVTVF1_RED_IRQHandler(void);
+WEAK void BLE_WAKE_UP_TIMER_IRQHandler(void);
+WEAK void SHA_IRQHandler(void);
+
+//*****************************************************************************
+// Forward declaration of the driver IRQ handlers. These are aliased
+// to the IntDefaultHandler, which is a 'forever' loop. When the driver
+// defines a handler (with the same name), this will automatically take
+// precedence over these weak definitions
+//*****************************************************************************
+void WDT_BOD_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void DMA0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GINT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CIC_IRB_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SPIFI0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM5_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PWM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PWM1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PWM2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PWM3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PWM4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PWM5_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PWM6_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PWM7_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PWM8_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PWM9_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PWM10_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM6_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void RTC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void NFCTag_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void MAILBOX_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC0_SEQA_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC0_SEQB_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC0_THCMP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void DMIC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void HWVAD0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void BLE_DP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void BLE_DP0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void BLE_DP1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void BLE_DP2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void BLE_LL_ALL_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ZIGBEE_MAC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ZIGBEE_MODEM_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void RFP_TMU_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void RFP_AGC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ISO7816_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ANA_COMP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void WAKE_UP_TIMER0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void WAKE_UP_TIMER1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PVTVF0_AMBER_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PVTVF0_RED_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PVTVF1_AMBER_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PVTVF1_RED_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void BLE_WAKE_UP_TIMER_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SHA_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+
+//*****************************************************************************
+// The entry point for the application.
+// __main() is the entry point for Redlib based applications
+// main() is the entry point for Newlib based applications
+//*****************************************************************************
+#if defined(__REDLIB__)
+extern void __main(void);
+#endif
+extern int main(void);
+
+//*****************************************************************************
+// External declaration for the pointer to the stack top from the Linker Script
+//*****************************************************************************
+extern void _vStackTop(void);
+//*****************************************************************************
+// External declaration for LPC MCU vector table checksum from Linker Script
+//*****************************************************************************
+WEAK extern void __valid_user_code_checksum();
+
+//*****************************************************************************
+//*****************************************************************************
+#if defined(__cplusplus)
+} // extern "C"
+#endif
+//*****************************************************************************
+// The vector table.
+// This relies on the linker script to place at correct location in memory.
+//*****************************************************************************
+extern void (*const g_pfnVectors[])(void);
+extern void *__Vectors __attribute__((alias("g_pfnVectors")));
+
+__attribute__((used, section(".isr_vector"))) void (*const g_pfnVectors[])(void) = {
+ // Core Level - CM4
+ &_vStackTop, // The initial stack pointer
+ ResetISR, // The reset handler
+ NMI_Handler, // The NMI handler
+ HardFault_Handler, // The hard fault handler
+ MemManage_Handler, // The MPU fault handler
+ BusFault_Handler, // The bus fault handler
+ UsageFault_Handler, // The usage fault handler
+ __valid_user_code_checksum, // LPC MCU checksum
+ 0, // ECRP
+ 0, // Reserved
+ 0, // Reserved
+ SVC_Handler, // SVCall handler
+ 0, // Reserved
+ 0, // Reserved
+ PendSV_Handler, // The PendSV handler
+ SysTick_Handler, // The SysTick handler
+
+ // Chip Level - K32W061
+ WDT_BOD_IRQHandler, // 16: System (BOD, Watchdog Timer, Flash controller) interrupt
+ DMA0_IRQHandler, // 17: DMA interrupt
+ GINT0_IRQHandler, // 18: GPIO global interrupt
+ CIC_IRB_IRQHandler, // 19: Infra Red Blaster interrupt
+ PIN_INT0_IRQHandler, // 20: Pin Interrupt and Pattern matching 0
+ PIN_INT1_IRQHandler, // 21: Pin Interrupt and Pattern matching 1
+ PIN_INT2_IRQHandler, // 22: Pin Interrupt and Pattern matching 2
+ PIN_INT3_IRQHandler, // 23: Pin Interrupt and Pattern matching 3
+ SPIFI0_IRQHandler, // 24: Quad-SPI flash interface interrupt
+ CTIMER0_IRQHandler, // 25: Counter/Timer 0 interrupt
+ CTIMER1_IRQHandler, // 26: Counter/Timer 1 interrupt
+ FLEXCOMM0_IRQHandler, // 27: Flexcomm Interface 0 (USART0, FLEXCOMM0)
+ FLEXCOMM1_IRQHandler, // 28: Flexcomm Interface 1 (USART1, FLEXCOMM1)
+ FLEXCOMM2_IRQHandler, // 29: Flexcomm Interface 2 (I2C0, FLEXCOMM2)
+ FLEXCOMM3_IRQHandler, // 30: Flexcomm Interface 3 (I2C1, FLEXCOMM3)
+ FLEXCOMM4_IRQHandler, // 31: Flexcomm Interface 4 (SPI0, FLEXCOMM4)
+ FLEXCOMM5_IRQHandler, // 32: Flexcomm Interface 5 (SPI5, FLEXCOMM)
+ PWM0_IRQHandler, // 33: PWM channel 0 interrupt
+ PWM1_IRQHandler, // 34: PWM channel 1 interrupt
+ PWM2_IRQHandler, // 35: PWM channel 2 interrupt
+ PWM3_IRQHandler, // 36: PWM channel 3 interrupt
+ PWM4_IRQHandler, // 37: PWM channel 4 interrupt
+ PWM5_IRQHandler, // 38: PWM channel 5 interrupt
+ PWM6_IRQHandler, // 39: PWM channel 6 interrupt
+ PWM7_IRQHandler, // 40: PWM channel 7 interrupt
+ PWM8_IRQHandler, // 41: PWM channel 8 interrupt
+ PWM9_IRQHandler, // 42: PWM channel 9 interrupt
+ PWM10_IRQHandler, // 43: PWM channel 10 interrupt
+ FLEXCOMM6_IRQHandler, // 44: Flexcomm Interface6 (I2C2, FLEXCOMM6)
+ RTC_IRQHandler, // 45: Real Time Clock interrupt
+ NFCTag_IRQHandler, // 46: NFC Tag interrupt
+ MAILBOX_IRQHandler, // 47: Mailbox interrupts, Wake-up from Deep Sleep interrupt
+ ADC0_SEQA_IRQHandler, // 48: ADC Sequence A interrupt
+ ADC0_SEQB_IRQHandler, // 49: ADC Sequence B interrupt
+ ADC0_THCMP_IRQHandler, // 50: ADC Threshold compare and overrun interrupt
+ DMIC0_IRQHandler, // 51: DMIC interrupt
+ HWVAD0_IRQHandler, // 52: Hardware Voice activity detection interrupt
+ BLE_DP_IRQHandler, // 53: BLE Data Path interrupt
+ BLE_DP0_IRQHandler, // 54: BLE Data Path interrupt 0
+ BLE_DP1_IRQHandler, // 55: BLE Data Path interrupt 1
+ BLE_DP2_IRQHandler, // 56: BLE Data Path interrupt 2
+ BLE_LL_ALL_IRQHandler, // 57: All BLE link layer interrupts
+ ZIGBEE_MAC_IRQHandler, // 58: Zigbee MAC interrupt
+ ZIGBEE_MODEM_IRQHandler, // 59: Zigbee MoDem interrupt
+ RFP_TMU_IRQHandler, // 60: RFP Timing Managemnt Unit (TMU) interrupt
+ RFP_AGC_IRQHandler, // 61: RFP AGC interrupt
+ ISO7816_IRQHandler, // 62: ISO7816 controller interrupt
+ ANA_COMP_IRQHandler, // 63: Analog Comparator interrupt
+ WAKE_UP_TIMER0_IRQHandler, // 64: Wake up Timer 0 interrupt
+ WAKE_UP_TIMER1_IRQHandler, // 65: Wake up Timer 1 interrupt
+ PVTVF0_AMBER_IRQHandler, // 66: PVT Monitor interrupt
+ PVTVF0_RED_IRQHandler, // 67: PVT Monitor interrupt
+ PVTVF1_AMBER_IRQHandler, // 68: PVT Monitor interrupt
+ PVTVF1_RED_IRQHandler, // 69: PVT Monitor interrupt
+ BLE_WAKE_UP_TIMER_IRQHandler, // 70: BLE Wake up Timer interrupt
+ SHA_IRQHandler, // 71: SHA interrupt
+
+}; /* End of g_pfnVectors */
+
+//*****************************************************************************
+// Functions to carry out the initialization of RW and BSS data sections. These
+// are written as separate functions rather than being inlined within the
+// ResetISR() function in order to cope with MCUs with multiple banks of
+// memory.
+//*****************************************************************************
+__attribute__((section(".after_vectors.init_data"))) void data_init(unsigned int romstart,
+ unsigned int start,
+ unsigned int len)
+{
+ unsigned int *pulDest = (unsigned int *)start;
+ unsigned int *pulSrc = (unsigned int *)romstart;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4)
+ *pulDest++ = *pulSrc++;
+}
+
+__attribute__((section(".after_vectors.init_bss"))) void bss_init(unsigned int start, unsigned int len)
+{
+ unsigned int *pulDest = (unsigned int *)start;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4)
+ *pulDest++ = 0;
+}
+
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the location of various points in the "Global Section Table". This table is
+// created by the linker via the Code Red managed linker script mechanism. It
+// contains the load address, execution address and length of each RW data
+// section and the execution and length of each BSS (zero initialized) section.
+//*****************************************************************************
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//*****************************************************************************
+__attribute__((section(".after_vectors.reset"))) void ResetISR(void)
+{
+ // Disable interrupts
+ __asm volatile("cpsid i");
+
+ // Enable SRAM clock used by Stack
+ __asm volatile(
+ "LDR R0, =0x40000220\n\t"
+ "MOV R1, #56\n\t"
+ "STR R1, [R0]");
+
+ __asm volatile(
+ ".set cpu_ctrl, 0x40000800\t\n"
+ ".set coproc_boot, 0x40000804\t\n"
+ ".set coproc_stack, 0x40000808\t\n"
+ "LDR R0,=coproc_boot\t\n" // load co-processor boot address (from CPBOOT)
+ "LDR R0,[R0]\t\n" // get address to branch to
+ "MOVS R0,R0\t\n" // Check if 0
+ "BEQ.N masterboot\t\n" // if zero in boot reg, we just branch to real reset
+ "LDR R1,=coproc_stack\t\n" // load co-processor stack pointer (from CPSTACK)
+ "LDR R1,[R1]\t\n"
+ "MOV SP,R1\t\n"
+ "BX R0\t\n" // branch to boot address
+ "masterboot:\t\n"
+ "LDR R0, =ResetISR2\t\n" // jump to 'real' reset handler
+ "BX R0\t\n");
+}
+
+__attribute__((used, section(".after_vectors"))) void ResetISR2(void)
+{
+ if (WarmMain)
+ {
+ unsigned int warm_start;
+ uint32_t pmc_lpmode;
+ uint32_t pmc_resetcause;
+ uint32_t pwr_pdsleepcfg;
+
+ pmc_resetcause = PMC->RESETCAUSE;
+ pwr_pdsleepcfg = PMC->PDSLEEPCFG;
+
+ pmc_lpmode = BOOT_GetStartPowerMode();
+
+ warm_start = (pmc_lpmode == 0x02); /* coming from power down mode*/
+
+ // check if the reset cause is only a timer wakeup or io wakeup with all memory banks held
+ warm_start &= (!(pmc_resetcause & (PMC_RESETCAUSE_POR_MASK | PMC_RESETCAUSE_PADRESET_MASK |
+ PMC_RESETCAUSE_BODRESET_MASK | PMC_RESETCAUSE_SYSTEMRESET_MASK |
+ PMC_RESETCAUSE_WDTRESET_MASK | PMC_RESETCAUSE_WAKEUPIORESET_MASK)) &&
+ (pmc_resetcause & PMC_RESETCAUSE_WAKEUPPWDNRESET_MASK) &&
+ ((pwr_pdsleepcfg & PMC_PDSLEEPCFG_PDEN_PD_MEM7_MASK) == 0x0) /* BANK7 memory bank held */
+ && (pwr_pdsleepcfg & PMC_PDSLEEPCFG_PDEN_LDO_MEM_MASK) /* LDO MEM enabled */
+ );
+
+ if (warm_start)
+ {
+ if (SYSCON->CPSTACK)
+ {
+ /* if CPSTACK is not NULL, switch to CPSTACK value so we avoid to corrupt the stack used before power
+ * down Note: it looks like enough to switch to new SP now and not earlier */
+ __asm volatile(
+ ".set coproc_stack, 0x40000808\t\n"
+ "LDR R1,=coproc_stack\t\n" // load co-processor stack pointer (from CPSTACK)
+ "LDR R1,[R1]\t\n"
+ "MOV SP,R1\t\n");
+ }
+
+ // Check to see if we are running the code from a non-zero
+ // address (eg RAM, external flash), in which case we need
+ // to modify the VTOR register to tell the CPU that the
+ // vector table is located at a non-0x0 address.
+ unsigned int *pSCB_VTOR = (unsigned int *)0xE000ED08;
+ if (((unsigned int)g_pfnVectors != 0))
+ {
+ // CMSIS : SCB->VTOR = <address of vector table>
+ *pSCB_VTOR = (unsigned int)g_pfnVectors;
+ }
+
+ if (SystemInit != 0)
+ {
+ SystemInit();
+ }
+
+ WarmMain();
+
+ //
+ // WarmMain() shouldn't return, but if it does, we'll just enter an infinite loop
+ //
+ while (1)
+ {
+ ;
+ }
+ }
+ }
+
+#if defined(__USE_CMSIS)
+ // If __USE_CMSIS defined, then call CMSIS SystemInit code
+ SystemInit();
+
+#endif // (__USE_CMSIS)
+
+ //
+ // Copy the data sections from flash to SRAM.
+ //
+ unsigned int LoadAddr, ExeAddr, SectionLen;
+ unsigned int *SectionTableAddr;
+
+ // Load base address of Global Section Table
+ SectionTableAddr = &__data_section_table;
+
+ // Copy the data sections from flash to SRAM.
+ while (SectionTableAddr < &__data_section_table_end)
+ {
+ LoadAddr = *SectionTableAddr++;
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ data_init(LoadAddr, ExeAddr, SectionLen);
+ }
+
+ // At this point, SectionTableAddr = &__bss_section_table;
+ // Zero fill the bss segment
+ while (SectionTableAddr < &__bss_section_table_end)
+ {
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ bss_init(ExeAddr, SectionLen);
+ }
+
+#if !defined(__USE_CMSIS)
+// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code
+// will enable the FPU
+#if defined(__VFP_FP__) && !defined(__SOFTFP__)
+ //
+ // Code to enable the Cortex-M4 FPU only included
+ // if appropriate build options have been selected.
+ // Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
+ //
+ // Read CPACR (located at address 0xE000ED88)
+ // Set bits 20-23 to enable CP10 and CP11 coprocessors
+ // Write back the modified value to the CPACR
+ __asm volatile(
+ "LDR.W R0, =0xE000ED88\n\t"
+ "LDR R1, [R0]\n\t"
+ "ORR R1, R1, #(0xF << 20)\n\t"
+ "STR R1, [R0]");
+#endif // (__VFP_FP__) && !(__SOFTFP__)
+#endif // (__USE_CMSIS)
+
+#if !defined(__USE_CMSIS)
+ // Assume that if __USE_CMSIS defined, then CMSIS SystemInit code
+ // will setup the VTOR register
+
+ // Check to see if we are running the code from a non-zero
+ // address (eg RAM, external flash), in which case we need
+ // to modify the VTOR register to tell the CPU that the
+ // vector table is located at a non-0x0 address.
+ unsigned int *pSCB_VTOR = (unsigned int *)0xE000ED08;
+ if ((unsigned int *)g_pfnVectors != (unsigned int *)0x00000000)
+ {
+ *pSCB_VTOR = (unsigned int)g_pfnVectors;
+ }
+#endif // (__USE_CMSIS)
+
+#if defined(__cplusplus)
+ //
+ // Call C++ library initialisation
+ //
+ __libc_init_array();
+#endif
+
+ // Reenable interrupts
+ __asm volatile("cpsie i");
+
+#if defined(__REDLIB__)
+ // Call the Redlib library, which in turn calls main()
+ __main();
+#else
+ main();
+#endif
+
+ //
+ // main() shouldn't return, but if it does, we'll just enter an infinite loop
+ //
+ while (1)
+ {
+ ;
+ }
+}
+
+//*****************************************************************************
+// Default core exception handlers. Override the ones here by defining your own
+// handler routines in your application code.
+//*****************************************************************************
+WEAK_AV void NMI_Handler(void)
+{
+ while (1)
+ {
+ }
+}
+
+WEAK_AV void HardFault_Handler(void)
+{
+ while (1)
+ {
+ }
+}
+
+WEAK_AV void MemManage_Handler(void)
+{
+ while (1)
+ {
+ }
+}
+
+WEAK_AV void BusFault_Handler(void)
+{
+ while (1)
+ {
+ }
+}
+
+WEAK_AV void UsageFault_Handler(void)
+{
+ while (1)
+ {
+ }
+}
+
+WEAK_AV void SVC_Handler(void)
+{
+ while (1)
+ {
+ }
+}
+
+WEAK_AV void PendSV_Handler(void)
+{
+ while (1)
+ {
+ }
+}
+
+WEAK_AV void SysTick_Handler(void)
+{
+ while (1)
+ {
+ }
+}
+
+//*****************************************************************************
+// Processor ends up here if an unexpected interrupt occurs or a specific
+// handler is not present in the application code.
+//*****************************************************************************
+WEAK_AV void IntDefaultHandler(void)
+{
+ while (1)
+ {
+ }
+}
+
+//*****************************************************************************
+// Default application exception handlers. Override the ones here by defining
+// your own handler routines in your application code. These routines call
+// driver exception handlers or IntDefaultHandler() if no driver exception
+// handler is included.
+//*****************************************************************************
+WEAK void WDT_BOD_IRQHandler(void)
+{
+ WDT_BOD_DriverIRQHandler();
+}
+
+WEAK void DMA0_IRQHandler(void)
+{
+ DMA0_DriverIRQHandler();
+}
+
+WEAK void GINT0_IRQHandler(void)
+{
+ GINT0_DriverIRQHandler();
+}
+
+WEAK void CIC_IRB_IRQHandler(void)
+{
+ CIC_IRB_DriverIRQHandler();
+}
+
+WEAK void PIN_INT0_IRQHandler(void)
+{
+ PIN_INT0_DriverIRQHandler();
+}
+
+WEAK void PIN_INT1_IRQHandler(void)
+{
+ PIN_INT1_DriverIRQHandler();
+}
+
+WEAK void PIN_INT2_IRQHandler(void)
+{
+ PIN_INT2_DriverIRQHandler();
+}
+
+WEAK void PIN_INT3_IRQHandler(void)
+{
+ PIN_INT3_DriverIRQHandler();
+}
+
+WEAK void SPIFI0_IRQHandler(void)
+{
+ SPIFI0_DriverIRQHandler();
+}
+
+WEAK void CTIMER0_IRQHandler(void)
+{
+ CTIMER0_DriverIRQHandler();
+}
+
+WEAK void CTIMER1_IRQHandler(void)
+{
+ CTIMER1_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM0_IRQHandler(void)
+{
+ FLEXCOMM0_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM1_IRQHandler(void)
+{
+ FLEXCOMM1_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM2_IRQHandler(void)
+{
+ FLEXCOMM2_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM3_IRQHandler(void)
+{
+ FLEXCOMM3_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM4_IRQHandler(void)
+{
+ FLEXCOMM4_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM5_IRQHandler(void)
+{
+ FLEXCOMM5_DriverIRQHandler();
+}
+
+WEAK void PWM0_IRQHandler(void)
+{
+ PWM0_DriverIRQHandler();
+}
+
+WEAK void PWM1_IRQHandler(void)
+{
+ PWM1_DriverIRQHandler();
+}
+
+WEAK void PWM2_IRQHandler(void)
+{
+ PWM2_DriverIRQHandler();
+}
+
+WEAK void PWM3_IRQHandler(void)
+{
+ PWM3_DriverIRQHandler();
+}
+
+WEAK void PWM4_IRQHandler(void)
+{
+ PWM4_DriverIRQHandler();
+}
+
+WEAK void PWM5_IRQHandler(void)
+{
+ PWM5_DriverIRQHandler();
+}
+
+WEAK void PWM6_IRQHandler(void)
+{
+ PWM6_DriverIRQHandler();
+}
+
+WEAK void PWM7_IRQHandler(void)
+{
+ PWM7_DriverIRQHandler();
+}
+
+WEAK void PWM8_IRQHandler(void)
+{
+ PWM8_DriverIRQHandler();
+}
+
+WEAK void PWM9_IRQHandler(void)
+{
+ PWM9_DriverIRQHandler();
+}
+
+WEAK void PWM10_IRQHandler(void)
+{
+ PWM10_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM6_IRQHandler(void)
+{
+ FLEXCOMM6_DriverIRQHandler();
+}
+
+WEAK void RTC_IRQHandler(void)
+{
+ RTC_DriverIRQHandler();
+}
+
+WEAK void NFCTag_IRQHandler(void)
+{
+ NFCTag_DriverIRQHandler();
+}
+
+WEAK void MAILBOX_IRQHandler(void)
+{
+ MAILBOX_DriverIRQHandler();
+}
+
+WEAK void ADC0_SEQA_IRQHandler(void)
+{
+ ADC0_SEQA_DriverIRQHandler();
+}
+
+WEAK void ADC0_SEQB_IRQHandler(void)
+{
+ ADC0_SEQB_DriverIRQHandler();
+}
+
+WEAK void ADC0_THCMP_IRQHandler(void)
+{
+ ADC0_THCMP_DriverIRQHandler();
+}
+
+WEAK void DMIC0_IRQHandler(void)
+{
+ DMIC0_DriverIRQHandler();
+}
+
+WEAK void HWVAD0_IRQHandler(void)
+{
+ HWVAD0_DriverIRQHandler();
+}
+
+WEAK void BLE_DP_IRQHandler(void)
+{
+ BLE_DP_DriverIRQHandler();
+}
+
+WEAK void BLE_DP0_IRQHandler(void)
+{
+ BLE_DP0_DriverIRQHandler();
+}
+
+WEAK void BLE_DP1_IRQHandler(void)
+{
+ BLE_DP1_DriverIRQHandler();
+}
+
+WEAK void BLE_DP2_IRQHandler(void)
+{
+ BLE_DP2_DriverIRQHandler();
+}
+
+WEAK void BLE_LL_ALL_IRQHandler(void)
+{
+ BLE_LL_ALL_DriverIRQHandler();
+}
+
+WEAK void ZIGBEE_MAC_IRQHandler(void)
+{
+ ZIGBEE_MAC_DriverIRQHandler();
+}
+
+WEAK void ZIGBEE_MODEM_IRQHandler(void)
+{
+ ZIGBEE_MODEM_DriverIRQHandler();
+}
+
+WEAK void RFP_TMU_IRQHandler(void)
+{
+ RFP_TMU_DriverIRQHandler();
+}
+
+WEAK void RFP_AGC_IRQHandler(void)
+{
+ RFP_AGC_DriverIRQHandler();
+}
+
+WEAK void ISO7816_IRQHandler(void)
+{
+ ISO7816_DriverIRQHandler();
+}
+
+WEAK void ANA_COMP_IRQHandler(void)
+{
+ ANA_COMP_DriverIRQHandler();
+}
+
+WEAK void WAKE_UP_TIMER0_IRQHandler(void)
+{
+ WAKE_UP_TIMER0_DriverIRQHandler();
+}
+
+WEAK void WAKE_UP_TIMER1_IRQHandler(void)
+{
+ WAKE_UP_TIMER1_DriverIRQHandler();
+}
+
+WEAK void PVTVF0_AMBER_IRQHandler(void)
+{
+ PVTVF0_AMBER_DriverIRQHandler();
+}
+
+WEAK void PVTVF0_RED_IRQHandler(void)
+{
+ PVTVF0_RED_DriverIRQHandler();
+}
+
+WEAK void PVTVF1_AMBER_IRQHandler(void)
+{
+ PVTVF1_AMBER_DriverIRQHandler();
+}
+
+WEAK void PVTVF1_RED_IRQHandler(void)
+{
+ PVTVF1_RED_DriverIRQHandler();
+}
+
+WEAK void BLE_WAKE_UP_TIMER_IRQHandler(void)
+{
+ BLE_WAKE_UP_TIMER_DriverIRQHandler();
+}
+
+WEAK void SHA_IRQHandler(void)
+{
+ SHA_DriverIRQHandler();
+}
+
+//*****************************************************************************
+
+#if defined(DEBUG)
+#pragma GCC pop_options
+#endif // (DEBUG)
diff --git a/third_party/nxp/K32W061DK6/devices/K32W061/system_K32W061.c b/third_party/nxp/K32W061DK6/devices/K32W061/system_K32W061.c
new file mode 100755
index 0000000..ec550a5
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/devices/K32W061/system_K32W061.c
@@ -0,0 +1,374 @@
+/*
+** ###################################################################
+** Processors: K32W041HN
+** K32W061HN
+**
+** Compilers: IAR ANSI C/C++ Compiler for ARM
+** MCUXpresso Compiler
+**
+** Reference manual: K32W061 User manual Rev.1 11 October 2019
+** Version: rev. 1.0, 2019-11-05
+** Build: b191121
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2019 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** Revisions:
+** - rev. 1.0 (2019-11-05)
+** Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file K32W061
+ * @version 1.0
+ * @date 2019-02-12
+ * @brief Device specific configuration file for K32W061 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+#include "rom_api.h"
+
+/**
+ * Clock source selections for the Main Clock
+ */
+typedef enum _main_clock_src
+{
+ kCLOCK_MainFro12M = 0,
+ kCLOCK_MainOsc32k = 1,
+ kCLOCK_MainXtal32M = 2,
+ kCLOCK_MainFro32M = 3,
+ kCLOCK_MainFro48M = 4,
+ kCLOCK_MainExtClk = 5,
+ kCLOCK_MainFro1M = 6,
+} main_clock_src_t;
+
+/**
+ * Clock source selections for CLKOUT
+ */
+typedef enum _clkout_clock_src
+{
+ kCLOCK_ClkoutMainClk = 0,
+ kCLOCK_ClkoutXtal32k = 1,
+ kCLOCK_ClkoutFro32k = 2,
+ kCLOCK_ClkoutXtal32M = 3,
+ kCLOCK_ClkoutDcDcTest = 4,
+ kCLOCK_ClkoutFro48M = 5,
+ kCLOCK_ClkoutFro1M = 6,
+ kCLOCK_ClkoutNoClock = 7
+} clkout_clock_src_t;
+
+typedef enum
+{
+ FRO12M_ENA = (1 << 0),
+ FRO32M_ENA = (1 << 1),
+ FRO48M_ENA = (1 << 2),
+ FRO64M_ENA = (1 << 3),
+ FRO96M_ENA = (1 << 4)
+} Fro_ClkSel_t;
+
+#define OSC32K_FREQ 32768UL
+#define FRO32K_FREQ 32768UL
+#define OSC32M_FREQ 32000000UL
+#define XTAL32M_FREQ 32000000UL
+#define FRO64M_FREQ 64000000UL
+#define FRO1M_FREQ 1000000UL
+#define FRO12M_FREQ 12000000UL
+#define FRO32M_FREQ 32000000UL
+#define FRO48M_FREQ 48000000UL
+
+static const uint32_t g_Ext_Clk_Freq = 0U;
+
+extern unsigned int __Vectors;
+extern WEAK void SystemInit(void);
+extern WEAK void WarmMain(void);
+
+static uint32_t CLOCK_GetXtal32kFreq(void)
+{
+ uint32_t freq = 0;
+
+ if (((PMC->PDRUNCFG & PMC_PDRUNCFG_ENA_XTAL32K_MASK) >> PMC_PDRUNCFG_ENA_XTAL32K_SHIFT) != 0)
+ {
+ freq = OSC32K_FREQ;
+ }
+
+ return freq;
+}
+
+static uint32_t CLOCK_GetXtal32MFreq(void)
+{
+ return XTAL32M_FREQ;
+}
+
+static uint32_t CLOCK_GetFro32kFreq(void)
+{
+ uint32_t freq = 0;
+
+ if (((PMC->PDRUNCFG & PMC_PDRUNCFG_ENA_FRO32K_MASK) >> PMC_PDRUNCFG_ENA_FRO32K_SHIFT) != 0)
+ {
+ freq = FRO32K_FREQ;
+ }
+
+ return freq;
+}
+
+static uint32_t CLOCK_GetFro1MFreq(void)
+{
+ return FRO1M_FREQ;
+}
+
+static uint32_t CLOCK_GetFro12MFreq(void)
+{
+ uint32_t freq = 0;
+
+ if (((PMC->FRO192M & PMC_FRO192M_DIVSEL_MASK) >> PMC_FRO192M_DIVSEL_SHIFT) & FRO12M_ENA)
+ {
+ freq = FRO12M_FREQ;
+ }
+
+ return freq;
+}
+
+static uint32_t CLOCK_GetFro32MFreq(void)
+{
+ uint32_t freq = 0;
+
+ if (((PMC->FRO192M & PMC_FRO192M_DIVSEL_MASK) >> PMC_FRO192M_DIVSEL_SHIFT) & FRO32M_ENA)
+ {
+ freq = FRO32M_FREQ;
+ }
+
+ return freq;
+}
+
+static uint32_t CLOCK_GetFro48MFreq(void)
+{
+ uint32_t freq = 0;
+
+ if (((PMC->FRO192M & PMC_FRO192M_DIVSEL_MASK) >> PMC_FRO192M_DIVSEL_SHIFT) & FRO48M_ENA)
+ {
+ freq = FRO48M_FREQ;
+ }
+
+ return freq;
+}
+
+static uint32_t CLOCK_GetOsc32kFreq(void)
+{
+ uint32_t freq = 0;
+ if ((SYSCON->OSC32CLKSEL & SYSCON_OSC32CLKSEL_SEL32KHZ_MASK) != 0)
+ {
+ freq = CLOCK_GetXtal32kFreq();
+ }
+ else
+ {
+ freq = CLOCK_GetFro32kFreq();
+ }
+ return freq;
+}
+
+/* Return main clock rate */
+static uint32_t CLOCK_GetMainClockRate(void)
+{
+ uint32_t freq = 0;
+
+ switch ((main_clock_src_t)((SYSCON->MAINCLKSEL & SYSCON_MAINCLKSEL_SEL_MASK) >> SYSCON_MAINCLKSEL_SEL_SHIFT))
+ {
+ case kCLOCK_MainFro12M:
+ freq = CLOCK_GetFro12MFreq();
+ break;
+
+ case kCLOCK_MainOsc32k:
+ freq = CLOCK_GetOsc32kFreq();
+ break;
+
+ case kCLOCK_MainXtal32M:
+ freq = CLOCK_GetXtal32MFreq();
+ break;
+
+ case kCLOCK_MainFro32M:
+ freq = CLOCK_GetFro32MFreq();
+ break;
+
+ case kCLOCK_MainFro48M:
+ freq = CLOCK_GetFro48MFreq();
+ break;
+
+ case kCLOCK_MainExtClk:
+ freq = g_Ext_Clk_Freq;
+ break;
+
+ case kCLOCK_MainFro1M:
+ freq = CLOCK_GetFro1MFreq();
+ break;
+ }
+
+ return freq;
+}
+
+/* ----------------------------------------------------------------------------
+ -- Core clock
+ ---------------------------------------------------------------------------- */
+
+#if !NO_SYSCORECLK_UPD
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+#endif
+
+#if defined(__ICCARM__)
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//*****************************************************************************
+void ResetISR(void)
+{
+ __asm volatile(
+ "LDR R0,=0x40000804\t\n" // load co-processor boot address (from CPBOOT)
+ "LDR R0,[R0]\t\n" // get address to branch to
+ "MOVS R0,R0\t\n" // Check if 0
+ "BEQ.N masterboot\t\n" // if zero in boot reg, we just branch to real reset
+ "LDR R1,=0x40000808\t\n" // load co-processor stack pointer (from CPSTACK)
+ "LDR R1,[R1]\t\n"
+ "MOV SP,R1\t\n"
+ "BX R0\t\n" // branch to boot address
+ "masterboot:\t\n"
+ "LDR R0, =ResetISR2\t\n" // jump to 'real' reset handler
+ "BX R0\t\n");
+}
+
+void ResetISR2(void)
+{
+ if ((void (*)(void))WarmMain != NULL)
+ {
+ unsigned int warm_start;
+ uint32_t pmc_lpmode;
+ uint32_t pmc_resetcause;
+ uint32_t pwr_pdsleepcfg;
+
+ pmc_resetcause = PMC->RESETCAUSE;
+ pwr_pdsleepcfg = PMC->PDSLEEPCFG;
+
+ pmc_lpmode = BOOT_GetStartPowerMode();
+
+ warm_start = (pmc_lpmode == 0x02); /* coming from power down mode*/
+
+ // check if the reset cause is only a timer wakeup or io wakeup with all memory banks held
+ warm_start &= (!(pmc_resetcause & (PMC_RESETCAUSE_POR_MASK | PMC_RESETCAUSE_PADRESET_MASK |
+ PMC_RESETCAUSE_BODRESET_MASK | PMC_RESETCAUSE_SYSTEMRESET_MASK |
+ PMC_RESETCAUSE_WDTRESET_MASK | PMC_RESETCAUSE_WAKEUPIORESET_MASK)) &&
+ (pmc_resetcause & PMC_RESETCAUSE_WAKEUPPWDNRESET_MASK) &&
+ ((pwr_pdsleepcfg & PMC_PDSLEEPCFG_PDEN_PD_MEM7_MASK) == 0x0) /* BANK7 memory bank held */
+ && (pwr_pdsleepcfg & PMC_PDSLEEPCFG_PDEN_LDO_MEM_MASK) /* LDO MEM enabled */
+ );
+
+ if (warm_start)
+ {
+ if (SYSCON->CPSTACK)
+ {
+ /* if CPSTACK is not NULL, switch to CPSTACK value so we avoid to corrupt the stack used before power
+ * down Note: it looks like enough to switch to new SP now and not earlier */
+ __asm volatile(
+ "LDR R1,=0x40000808\t\n" // load co-processor stack pointer (from CPSTACK)
+ "LDR R1,[R1]\t\n"
+ "MOV SP,R1\t\n");
+ }
+ // Check to see if we are running the code from a non-zero
+ // address (eg RAM, external flash), in which case we need
+ // to modify the VTOR register to tell the CPU that the
+ // vector table is located at a non-0x0 address.
+ unsigned int *pSCB_VTOR = (unsigned int *)0xE000ED08;
+ if (((unsigned int)(&__Vectors) != 0))
+ {
+ // CMSIS : SCB->VTOR = <address of vector table>
+ *pSCB_VTOR = (unsigned int)(&__Vectors);
+ }
+
+ if ((void (*)(void))SystemInit != NULL)
+ {
+ SystemInit();
+ }
+
+ WarmMain();
+
+ //
+ // WarmMain() shouldn't return, but if it does, we'll just enter an infinite loop
+ //
+ while (1)
+ {
+ ;
+ }
+ }
+ }
+
+ // Check to see if we are running the code from a non-zero
+ // address (eg RAM, external flash), in which case we need
+ // to modify the VTOR register to tell the CPU that the
+ // vector table is located at a non-0x0 address.
+ unsigned int *pSCB_VTOR = (unsigned int *)0xE000ED08;
+ if ((unsigned int)(&__Vectors) != 0)
+ {
+ // CMSIS : SCB->VTOR = <address of vector table>
+ *pSCB_VTOR = (unsigned int)(&__Vectors);
+ }
+
+ SystemInit();
+
+#if defined(__cplusplus)
+ //
+ // Call C++ library initialisation
+ //
+ __libc_init_array();
+#endif
+}
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- SystemInit()
+ ---------------------------------------------------------------------------- */
+
+void SystemInit(void)
+{
+ uint32_t trim;
+#if !NO_SYSCORECLK_UPD
+ /* Initialise SystemCoreClock value */
+ SystemCoreClockUpdate();
+#endif
+ /* Initialise NVIC priority grouping value */
+ NVIC_SetPriorityGrouping(4);
+
+ /* Apply FRO1M trim value */
+ trim = *(uint32_t *)(0x9FCD0U);
+
+ if (trim & 0x1U)
+ {
+ PMC->FRO1M = (PMC->FRO1M & ~PMC_FRO1M_FREQSEL_MASK) | ((trim >> 1) & PMC_FRO1M_FREQSEL_MASK);
+ }
+}
+
+/* ----------------------------------------------------------------------------
+ -- SystemCoreClockUpdate()
+ ---------------------------------------------------------------------------- */
+
+#if !NO_SYSCORECLK_UPD
+void SystemCoreClockUpdate(void)
+{
+ SystemCoreClock = (CLOCK_GetMainClockRate() / ((SYSCON->AHBCLKDIV & SYSCON_AHBCLKDIV_DIV_MASK) + 1U));
+}
+#endif
diff --git a/third_party/nxp/K32W061DK6/devices/K32W061/system_K32W061.h b/third_party/nxp/K32W061DK6/devices/K32W061/system_K32W061.h
new file mode 100755
index 0000000..6c3db2b
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/devices/K32W061/system_K32W061.h
@@ -0,0 +1,89 @@
+/*
+** ###################################################################
+** Processors: K32W041HN
+** K32W061HN
+**
+** Compilers: IAR ANSI C/C++ Compiler for ARM
+** MCUXpresso Compiler
+**
+** Reference manual: K32W061 User manual Rev.1 11 October 2019
+** Version: rev. 1.0, 2019-11-05
+** Build: b191121
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2019 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** Revisions:
+** - rev. 1.0 (2019-11-05)
+** Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file K32W061
+ * @version 1.0
+ * @date 2019-11-05
+ * @brief Device specific configuration file for K32W061 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef _SYSTEM_K32W061_H_
+#define _SYSTEM_K32W061_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit(void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYSTEM_K32W061_H_ */
diff --git a/third_party/nxp/K32W061DK6/devices/K32W061/utilities/debug_console/fsl_debug_console.c b/third_party/nxp/K32W061DK6/devices/K32W061/utilities/debug_console/fsl_debug_console.c
new file mode 100755
index 0000000..9f4b4ff
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/devices/K32W061/utilities/debug_console/fsl_debug_console.c
@@ -0,0 +1,1131 @@
+/*
+ * This is a modified version of the file printf.c, which was distributed
+ * by Motorola as part of the M5407C3BOOT.zip package used to initialize
+ * the M5407C3 evaluation board.
+ *
+ * Copyright:
+ * 1999-2000 MOTOROLA, INC. All Rights Reserved.
+ * You are hereby granted a copyright license to use, modify, and
+ * distribute the SOFTWARE so long as this entire notice is
+ * retained without alteration in any modified and/or redistributed
+ * versions, and that such modified versions are clearly identified
+ * as such. No licenses are granted by implication, estoppel or
+ * otherwise under any patents or trademarks of Motorola, Inc. This
+ * software is provided on an "AS IS" basis and without warranty.
+ *
+ * To the maximum extent permitted by applicable law, MOTOROLA
+ * DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING
+ * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
+ * PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE
+ * SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY
+ * ACCOMPANYING WRITTEN MATERIALS.
+ *
+ * To the maximum extent permitted by applicable law, IN NO EVENT
+ * SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING
+ * WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS
+ * INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
+ * LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
+ *
+ * Motorola assumes no responsibility for the maintenance and support
+ * of this software
+
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdarg.h>
+#include <stdlib.h>
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+#include <stdio.h>
+#endif
+
+#ifdef FSL_RTOS_FREE_RTOS
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "task.h"
+#endif
+
+#include "fsl_debug_console_conf.h"
+#include "fsl_str.h"
+
+#include "fsl_common.h"
+#include "serial_manager.h"
+
+#include "fsl_debug_console.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#ifndef NDEBUG
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
+#undef assert
+#define assert(n)
+#endif
+#endif
+
+#if SDK_DEBUGCONSOLE
+#define DEBUG_CONSOLE_FUNCTION_PREFIX
+#else
+#define DEBUG_CONSOLE_FUNCTION_PREFIX static
+#endif
+
+/*! @brief character backspace ASCII value */
+#define DEBUG_CONSOLE_BACKSPACE 127U
+
+/* lock definition */
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+
+static SemaphoreHandle_t s_debugConsoleReadSemaphore;
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+static SemaphoreHandle_t s_debugConsoleReadWaitSemaphore;
+#endif
+
+#elif (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM)
+
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+static volatile uint8_t s_debugConsoleReadWaitSemaphore;
+#endif
+
+#else
+
+#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */
+
+/*! @brief get current runing environment is ISR or not */
+#ifdef __CA7_REV
+#define IS_RUNNING_IN_ISR() SystemGetIRQNestingLevel()
+#else
+#define IS_RUNNING_IN_ISR() __get_IPSR()
+#endif /* __CA7_REV */
+
+/* semaphore definition */
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+
+/* mutex semaphore */
+#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex) ((mutex) = xSemaphoreCreateMutex())
+
+/* clang-format off */
+#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex) \
+{ \
+ if (IS_RUNNING_IN_ISR() == 0U) \
+ { \
+ (void)xSemaphoreGive(mutex); \
+ } \
+}
+
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) \
+{ \
+ if (IS_RUNNING_IN_ISR() == 0U) \
+ { \
+ (void)xSemaphoreTake(mutex, portMAX_DELAY); \
+ } \
+}
+
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) \
+{ \
+ if (IS_RUNNING_IN_ISR() == 0U) \
+ { \
+ result = xSemaphoreTake(mutex, 0U); \
+ } \
+ else \
+ { \
+ result = 1U; \
+ } \
+}
+/* clang-format on */
+
+/* Binary semaphore */
+#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary) ((binary) = xSemaphoreCreateBinary())
+#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) ((void)xSemaphoreTake(binary, portMAX_DELAY))
+#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) ((void)xSemaphoreGiveFromISR(binary, NULL))
+
+#elif (DEBUG_CONSOLE_SYNCHRONIZATION_BM == DEBUG_CONSOLE_SYNCHRONIZATION_MODE)
+
+#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex)
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex)
+#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex)
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) (result = 1U)
+
+#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary)
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) \
+ { \
+ while (!binary) \
+ { \
+ } \
+ binary = false; \
+ }
+#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) (binary = true)
+#else
+#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary)
+#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary)
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+/* add other implementation here
+ *such as :
+ * #elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DDEBUG_CONSOLE_SYNCHRONIZATION_xxx)
+ */
+
+#else
+
+#error RTOS type is not defined by DEBUG_CONSOLE_SYNCHRONIZATION_MODE.
+
+#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/* receive state structure */
+typedef struct _debug_console_write_ring_buffer
+{
+ uint32_t ringBufferSize;
+ volatile uint32_t ringHead;
+ volatile uint32_t ringTail;
+ uint8_t ringBuffer[DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN];
+} debug_console_write_ring_buffer_t;
+#endif
+
+typedef struct _debug_console_state_struct
+{
+ uint8_t serialHandleBuffer[SERIAL_MANAGER_HANDLE_SIZE];
+ serial_handle_t serialHandle; /*!< serial manager handle */
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+ debug_console_write_ring_buffer_t writeRingBuffer;
+ uint8_t readRingBuffer[DEBUG_CONSOLE_RECEIVE_BUFFER_LEN];
+#endif
+ uint8_t serialWriteHandleBuffer[SERIAL_MANAGER_WRITE_HANDLE_SIZE];
+ uint8_t serialReadHandleBuffer[SERIAL_MANAGER_READ_HANDLE_SIZE];
+} debug_console_state_struct_t;
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Debug console state information. */
+static debug_console_state_struct_t s_debugConsoleState;
+serial_handle_t g_serialHandle; /*!< serial manager handle */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief This is a printf call back function which is used to relocate the log to buffer
+ * or print the log immediately when the local buffer is full.
+ *
+ * @param[in] buf Buffer to store log.
+ * @param[in] indicator Buffer index.
+ * @param[in] val Target character to store.
+ * @param[in] len length of the character
+ *
+ */
+#if SDK_DEBUGCONSOLE
+static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, int len);
+#endif
+
+status_t DbgConsole_ReadOneCharacter(uint8_t *ch);
+int DbgConsole_SendData(uint8_t *ch, size_t size);
+int DbgConsole_SendDataReliable(uint8_t *ch, size_t size);
+int DbgConsole_ReadLine(uint8_t *buf, size_t size);
+int DbgConsole_ReadCharacter(uint8_t *ch);
+
+#if ((SDK_DEBUGCONSOLE > 0U) || \
+ ((SDK_DEBUGCONSOLE == 0U) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \
+ (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))))
+DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void);
+#endif
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+
+static void DbgConsole_SerialManagerTxCallback(void *callbackParam,
+ serial_manager_callback_message_t *message,
+ serial_manager_status_t status)
+{
+ debug_console_state_struct_t *ioState;
+ uint32_t sendDataLength;
+
+ if ((NULL == callbackParam) || (NULL == message))
+ {
+ return;
+ }
+
+ ioState = (debug_console_state_struct_t *)callbackParam;
+
+ ioState->writeRingBuffer.ringTail += message->length;
+ if (ioState->writeRingBuffer.ringTail >= ioState->writeRingBuffer.ringBufferSize)
+ {
+ ioState->writeRingBuffer.ringTail = 0U;
+ }
+
+ if (kStatus_SerialManager_Success == status)
+ {
+ if (ioState->writeRingBuffer.ringTail != ioState->writeRingBuffer.ringHead)
+ {
+ if (ioState->writeRingBuffer.ringHead > ioState->writeRingBuffer.ringTail)
+ {
+ sendDataLength = ioState->writeRingBuffer.ringHead - ioState->writeRingBuffer.ringTail;
+ }
+ else
+ {
+ sendDataLength = ioState->writeRingBuffer.ringBufferSize - ioState->writeRingBuffer.ringTail;
+ }
+
+ (void)SerialManager_WriteNonBlocking(
+ ((serial_write_handle_t)&ioState->serialWriteHandleBuffer[0]),
+ &ioState->writeRingBuffer.ringBuffer[ioState->writeRingBuffer.ringTail], sendDataLength);
+ }
+ }
+ else if (kStatus_SerialManager_Canceled == status)
+ {
+ ioState->writeRingBuffer.ringTail = 0U;
+ ioState->writeRingBuffer.ringHead = 0U;
+ }
+ else
+ {
+ /*MISRA rule 16.4*/
+ }
+}
+
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+
+static void DbgConsole_SerialManagerRxCallback(void *callbackParam,
+ serial_manager_callback_message_t *message,
+ serial_manager_status_t status)
+{
+ if ((NULL == callbackParam) || (NULL == message))
+ {
+ return;
+ }
+
+ if (kStatus_SerialManager_Notify == status)
+ {
+ }
+ else if (kStatus_SerialManager_Success == status)
+ {
+ /* release s_debugConsoleReadWaitSemaphore from RX callback */
+ DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(s_debugConsoleReadWaitSemaphore);
+ }
+ else
+ {
+ /*MISRA rule 16.4*/
+ }
+}
+#endif
+
+#endif
+
+status_t DbgConsole_ReadOneCharacter(uint8_t *ch)
+{
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \
+ (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)
+ return kStatus_Fail;
+#else
+ status_t status = (status_t)kStatus_SerialManager_Error;
+
+/* recieve one char every time */
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+ status = (status_t)SerialManager_ReadNonBlocking(
+ ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1);
+#else
+ status = (status_t)SerialManager_ReadBlocking(
+ ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1);
+#endif
+ if ((status_t)kStatus_SerialManager_Success != status)
+ {
+ return (status_t)kStatus_Fail;
+ }
+ /* wait s_debugConsoleReadWaitSemaphore from RX callback */
+ DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(s_debugConsoleReadWaitSemaphore);
+
+ return (status_t)kStatus_Success;
+#endif
+
+#else
+
+ return (status_t)kStatus_Fail;
+
+#endif
+}
+
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
+static status_t DbgConsole_EchoCharacter(uint8_t *ch, bool isGetChar, int *index)
+{
+ /* Due to scanf take \n and \r as end of string,should not echo */
+ if (((*ch != (uint8_t)'\r') && (*ch != (uint8_t)'\n')) || (isGetChar))
+ {
+ /* recieve one char every time */
+ if (1 != DbgConsole_SendDataReliable(ch, 1U))
+ {
+ return (status_t)kStatus_Fail;
+ }
+ }
+
+ if ((!isGetChar) && (index != NULL))
+ {
+ if (DEBUG_CONSOLE_BACKSPACE == *ch)
+ {
+ if ((*index >= 2))
+ {
+ *index -= 2;
+ }
+ else
+ {
+ *index = 0;
+ }
+ }
+ }
+
+ return (status_t)kStatus_Success;
+}
+#endif
+
+int DbgConsole_SendData(uint8_t *ch, size_t size)
+{
+ status_t status = (status_t)kStatus_SerialManager_Error;
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+ uint32_t sendDataLength;
+ int txBusy = 0;
+#endif
+ assert(NULL != ch);
+ assert(0 != size);
+
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+ uint32_t regPrimask = DisableGlobalIRQ();
+ if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)
+ {
+ txBusy = 1;
+ sendDataLength =
+ (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize -
+ s_debugConsoleState.writeRingBuffer.ringTail) %
+ s_debugConsoleState.writeRingBuffer.ringBufferSize;
+ }
+ else
+ {
+ sendDataLength = 0U;
+ }
+ sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength - 1;
+ if (sendDataLength <= size)
+ {
+ EnableGlobalIRQ(regPrimask);
+ return -1;
+ }
+ for (int i = 0; i < (int)size; i++)
+ {
+ s_debugConsoleState.writeRingBuffer.ringBuffer[s_debugConsoleState.writeRingBuffer.ringHead++] = ch[i];
+ if (s_debugConsoleState.writeRingBuffer.ringHead >= s_debugConsoleState.writeRingBuffer.ringBufferSize)
+ {
+ s_debugConsoleState.writeRingBuffer.ringHead = 0U;
+ }
+ }
+
+ status = (status_t)kStatus_SerialManager_Success;
+
+ if (txBusy == 0)
+ {
+ if (s_debugConsoleState.writeRingBuffer.ringHead > s_debugConsoleState.writeRingBuffer.ringTail)
+ {
+ sendDataLength =
+ s_debugConsoleState.writeRingBuffer.ringHead - s_debugConsoleState.writeRingBuffer.ringTail;
+ }
+ else
+ {
+ sendDataLength =
+ s_debugConsoleState.writeRingBuffer.ringBufferSize - s_debugConsoleState.writeRingBuffer.ringTail;
+ }
+
+ status = (status_t)SerialManager_WriteNonBlocking(
+ ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]),
+ &s_debugConsoleState.writeRingBuffer.ringBuffer[s_debugConsoleState.writeRingBuffer.ringTail],
+ sendDataLength);
+ }
+ EnableGlobalIRQ(regPrimask);
+#else
+ status = (status_t)SerialManager_WriteBlocking(
+ ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size);
+#endif
+ return (((status_t)kStatus_Success == status) ? (int)size : -1);
+}
+
+int DbgConsole_SendDataReliable(uint8_t *ch, size_t size)
+{
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+#if (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))
+ status_t status = kStatus_SerialManager_Error;
+ uint32_t sendDataLength;
+ uint32_t totalLength = size;
+ int sentLength;
+#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */
+#else
+ status_t status = kStatus_SerialManager_Error;
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+ assert(NULL != ch);
+ assert(0 != size);
+
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+
+#if (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))
+ do
+ {
+ uint32_t regPrimask = DisableGlobalIRQ();
+ if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)
+ {
+ sendDataLength =
+ (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize -
+ s_debugConsoleState.writeRingBuffer.ringTail) %
+ s_debugConsoleState.writeRingBuffer.ringBufferSize;
+ }
+ else
+ {
+ sendDataLength = 0U;
+ }
+ sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength - 1U;
+
+ if (sendDataLength > 0U)
+ {
+ if (sendDataLength > totalLength)
+ {
+ sendDataLength = totalLength;
+ }
+
+ sentLength = DbgConsole_SendData(&ch[size - totalLength], sendDataLength);
+ if (sentLength > 0)
+ {
+ totalLength = totalLength - (uint32_t)sentLength;
+ }
+ }
+ EnableGlobalIRQ(regPrimask);
+
+ if (totalLength != 0U)
+ {
+ status = DbgConsole_Flush();
+ if ((status_t)kStatus_Success != status)
+ {
+ break;
+ }
+ }
+ } while (totalLength != 0U);
+ return (status_t)(uint32_t)((uint32_t)size - totalLength);
+#else
+ return DbgConsole_SendData(ch, size);
+#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */
+
+#else
+ status = (status_t)SerialManager_WriteBlocking(
+ ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size);
+ return (((status_t)kStatus_Success == status) ? (int)size : -1);
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+}
+
+int DbgConsole_ReadLine(uint8_t *buf, size_t size)
+{
+ int i = 0;
+
+ assert(buf != NULL);
+
+ /* take mutex lock function */
+ DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore);
+
+ do
+ {
+ /* recieve one char every time */
+ if ((status_t)kStatus_Success != DbgConsole_ReadOneCharacter(&buf[i]))
+ {
+ /* release mutex lock function */
+ DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
+ i = -1;
+ break;
+ }
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
+ (void)DbgConsole_EchoCharacter(&buf[i], false, &i);
+#endif
+ /* analysis data */
+ if (((uint8_t)'\r' == buf[i]) || ((uint8_t)'\n' == buf[i]))
+ {
+ /* End of Line. */
+ if (0 == i)
+ {
+ buf[i] = (uint8_t)'\0';
+ continue;
+ }
+ else
+ {
+ break;
+ }
+ }
+ i++;
+ } while (i < (int)size);
+
+ /* get char should not add '\0'*/
+ if (i == (int)size)
+ {
+ buf[i] = (uint8_t)'\0';
+ }
+ else
+ {
+ buf[i + 1] = (uint8_t)'\0';
+ }
+
+ /* release mutex lock function */
+ DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
+
+ return i;
+}
+
+int DbgConsole_ReadCharacter(uint8_t *ch)
+{
+ int ret;
+
+ assert(ch);
+
+ /* take mutex lock function */
+ DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore);
+ /* read one character */
+ if ((status_t)kStatus_Success == DbgConsole_ReadOneCharacter(ch))
+ {
+ ret = 1;
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
+ (void)DbgConsole_EchoCharacter(ch, true, NULL);
+#endif
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ /* release mutex lock function */
+ DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
+
+ return ret;
+}
+
+#if SDK_DEBUGCONSOLE
+static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, int len)
+{
+ int i = 0;
+
+ for (i = 0; i < len; i++)
+ {
+ if (((uint32_t)*indicator + 1UL) >= DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN)
+ {
+ (void)DbgConsole_SendDataReliable((uint8_t *)buf, (uint32_t)(*indicator));
+ *indicator = 0;
+ }
+
+ buf[*indicator] = dbgVal;
+ (*indicator)++;
+ }
+}
+#endif
+
+/*************Code for DbgConsole Init, Deinit, Printf, Scanf *******************************/
+
+/* See fsl_debug_console.h for documentation of this function. */
+status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq)
+{
+ serial_manager_config_t serialConfig;
+ status_t status = (status_t)kStatus_SerialManager_Error;
+
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ serial_port_uart_config_t uartConfig = {
+ .instance = instance,
+ .clockRate = clkSrcFreq,
+ .baudRate = baudRate,
+ .parityMode = kSerialManager_UartParityDisabled,
+ .stopBitCount = kSerialManager_UartOneStopBit,
+ .enableRx = 1,
+ .enableTx = 1,
+ };
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ serial_port_usb_cdc_config_t usbCdcConfig = {
+ .controllerIndex = (serial_port_usb_cdc_controller_index_t)instance,
+ };
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ serial_port_swo_config_t swoConfig = {
+ .clockRate = clkSrcFreq,
+ .baudRate = baudRate,
+ .port = instance,
+ .protocol = kSerialManager_SwoProtocolNrz,
+ };
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ serial_port_usb_cdc_virtual_config_t usbCdcVirtualConfig = {
+ .controllerIndex = (serial_port_usb_cdc_virtual_controller_index_t)instance,
+ };
+#endif
+ serialConfig.type = device;
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+ serialConfig.ringBuffer = &s_debugConsoleState.readRingBuffer[0];
+ serialConfig.ringBufferSize = DEBUG_CONSOLE_RECEIVE_BUFFER_LEN;
+#endif
+
+ if (kSerialPort_Uart == device)
+ {
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+ serialConfig.portConfig = &uartConfig;
+#else
+ return status;
+#endif
+ }
+ else if (kSerialPort_UsbCdc == device)
+ {
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+ serialConfig.portConfig = &usbCdcConfig;
+#else
+ return status;
+#endif
+ }
+ else if (kSerialPort_Swo == device)
+ {
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+ serialConfig.portConfig = &swoConfig;
+#else
+ return status;
+#endif
+ }
+ else if (kSerialPort_UsbCdcVirtual == device)
+ {
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+ serialConfig.portConfig = &usbCdcVirtualConfig;
+#else
+ return status;
+#endif
+ }
+ else
+ {
+ return status;
+ }
+
+ (void)memset(&s_debugConsoleState, 0, sizeof(s_debugConsoleState));
+
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+ s_debugConsoleState.writeRingBuffer.ringBufferSize = DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN;
+#endif
+
+ s_debugConsoleState.serialHandle = (serial_handle_t)&s_debugConsoleState.serialHandleBuffer[0];
+ status = (status_t)SerialManager_Init(s_debugConsoleState.serialHandle, &serialConfig);
+
+ assert(kStatus_SerialManager_Success == status);
+
+ DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+ DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore);
+#endif
+
+ {
+ status = (status_t)SerialManager_OpenWriteHandle(
+ s_debugConsoleState.serialHandle, ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]));
+ assert(kStatus_SerialManager_Success == status);
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+ (void)SerialManager_InstallTxCallback(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]),
+ DbgConsole_SerialManagerTxCallback, &s_debugConsoleState);
+#endif
+ }
+
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+ {
+ status = (status_t)SerialManager_OpenReadHandle(
+ s_debugConsoleState.serialHandle, ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]));
+ assert(kStatus_SerialManager_Success == status);
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+ (void)SerialManager_InstallRxCallback(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]),
+ DbgConsole_SerialManagerRxCallback, &s_debugConsoleState);
+#endif
+ }
+#endif
+
+ g_serialHandle = s_debugConsoleState.serialHandle;
+
+ return kStatus_Success;
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+status_t DbgConsole_Deinit(void)
+{
+ {
+ if (s_debugConsoleState.serialHandle != NULL)
+ {
+ (void)SerialManager_CloseWriteHandle(
+ ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]));
+ }
+ }
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+ {
+ if (s_debugConsoleState.serialHandle != NULL)
+ {
+ (void)SerialManager_CloseReadHandle(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]));
+ }
+ }
+#endif
+ if (s_debugConsoleState.serialHandle)
+ {
+ if (kStatus_SerialManager_Success == SerialManager_Deinit(s_debugConsoleState.serialHandle))
+ {
+ s_debugConsoleState.serialHandle = NULL;
+ g_serialHandle = NULL;
+ }
+ }
+ return (status_t)kStatus_Success;
+}
+
+#if ((SDK_DEBUGCONSOLE > 0U) || \
+ ((SDK_DEBUGCONSOLE == 0U) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \
+ (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))))
+DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void)
+{
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
+
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)
+
+ if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)
+ {
+ return (status_t)kStatus_Fail;
+ }
+
+#else
+
+ while (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)
+ {
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+ if (0U == IS_RUNNING_IN_ISR())
+ {
+ if (taskSCHEDULER_RUNNING == xTaskGetSchedulerState())
+ {
+ vTaskDelay(1);
+ }
+ }
+ else
+ {
+ return (status_t)kStatus_Fail;
+ }
+#endif
+ }
+
+#endif
+
+#endif
+ return (status_t)kStatus_Success;
+}
+#endif
+
+#if SDK_DEBUGCONSOLE
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Printf(const char *formatString, ...)
+{
+ va_list ap;
+ int logLength = 0, dbgResult = 0;
+ char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {'\0'};
+
+ if (NULL == g_serialHandle)
+ {
+ return 0;
+ }
+
+ va_start(ap, formatString);
+ /* format print log first */
+ logLength = StrFormatPrintf(formatString, ap, printBuf, DbgConsole_PrintCallback);
+ /* print log */
+ dbgResult = DbgConsole_SendDataReliable((uint8_t *)printBuf, (size_t)logLength);
+
+ va_end(ap);
+
+ return dbgResult;
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Putchar(int ch)
+{
+ /* print char */
+ return DbgConsole_SendDataReliable((uint8_t *)&ch, 1U);
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Scanf(char *formatString, ...)
+{
+ va_list ap;
+ int formatResult;
+ char scanfBuf[DEBUG_CONSOLE_SCANF_MAX_LOG_LEN + 1U] = {'\0'};
+
+ /* scanf log */
+ (void)DbgConsole_ReadLine((uint8_t *)scanfBuf, DEBUG_CONSOLE_SCANF_MAX_LOG_LEN);
+ /* get va_list */
+ va_start(ap, formatString);
+ /* format scanf log */
+ formatResult = StrFormatScanf(scanfBuf, formatString, ap);
+
+ va_end(ap);
+
+ return formatResult;
+}
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+status_t DbgConsole_TryGetchar(char *ch)
+{
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+ uint32_t length = 0;
+ status_t status = (status_t)kStatus_Fail;
+
+ assert(ch);
+
+ /* take mutex lock function */
+ DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore);
+
+ if (kStatus_SerialManager_Success ==
+ SerialManager_TryRead(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), (uint8_t *)ch, 1,
+ &length))
+ {
+ if (length != 0U)
+ {
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
+ (void)DbgConsole_EchoCharacter((uint8_t *)ch, true, NULL);
+#endif
+ status = (status_t)kStatus_Success;
+ }
+ }
+ /* release mutex lock function */
+ DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
+ return status;
+#else
+ return (status_t)kStatus_Fail;
+#endif
+}
+#endif
+
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Getchar(void)
+{
+ uint8_t ch = 0U;
+
+ /* Get char */
+ (void)DbgConsole_ReadCharacter(&ch);
+
+ return (int)ch;
+}
+
+#endif /* SDK_DEBUGCONSOLE */
+
+/*************Code to support toolchain's printf, scanf *******************************/
+/* These function __write and __read is used to support IAR toolchain to printf and scanf*/
+#if (defined(__ICCARM__))
+#if defined(SDK_DEBUGCONSOLE_UART)
+#pragma weak __write
+size_t __write(int handle, const unsigned char *buffer, size_t size)
+{
+ if (buffer == 0)
+ {
+ /*
+ * This means that we should flush internal buffers. Since we don't we just return.
+ * (Remember, "handle" == -1 means that all handles should be flushed.)
+ */
+ return 0;
+ }
+
+ /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
+ if ((handle != 1) && (handle != 2))
+ {
+ return ((size_t)-1);
+ }
+
+ /* Send data. */
+ DbgConsole_SendDataReliable((uint8_t *)buffer, size);
+
+ return size;
+}
+
+#pragma weak __read
+size_t __read(int handle, unsigned char *buffer, size_t size)
+{
+ uint8_t ch = 0U;
+ int actualSize = 0U;
+
+ /* This function only reads from "standard in", for all other file handles it returns failure. */
+ if (handle != 0)
+ {
+ return ((size_t)-1);
+ }
+
+ /* Receive data.*/
+ for (; size > 0; size--)
+ {
+ DbgConsole_ReadCharacter(&ch);
+ if (ch == 0)
+ {
+ break;
+ }
+
+ *buffer++ = ch;
+ actualSize++;
+ }
+
+ return actualSize;
+}
+#endif /* SDK_DEBUGCONSOLE_UART */
+
+/* support LPC Xpresso with RedLib */
+#elif (defined(__REDLIB__))
+
+#if (defined(SDK_DEBUGCONSOLE_UART))
+int __attribute__((weak)) __sys_write(int handle, char *buffer, int size)
+{
+ if (buffer == 0)
+ {
+ /* return -1 if error. */
+ return -1;
+ }
+
+ /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
+ if ((handle != 1) && (handle != 2))
+ {
+ return -1;
+ }
+
+ /* Send data. */
+ DbgConsole_SendDataReliable((uint8_t *)buffer, size);
+
+ return 0;
+}
+
+int __attribute__((weak)) __sys_readc(void)
+{
+ char tmp;
+
+ /* Receive data. */
+ DbgConsole_ReadCharacter((uint8_t *)&tmp);
+
+ return tmp;
+}
+#endif
+
+/* These function fputc and fgetc is used to support KEIL toolchain to printf and scanf*/
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+#if defined(SDK_DEBUGCONSOLE_UART)
+#if defined(__CC_ARM)
+struct __FILE
+{
+ int handle;
+ /*
+ * Whatever you require here. If the only file you are using is standard output using printf() for debugging,
+ * no file handling is required.
+ */
+};
+#endif
+
+/* FILE is typedef in stdio.h. */
+#pragma weak __stdout
+#pragma weak __stdin
+FILE __stdout;
+FILE __stdin;
+
+#pragma weak fputc
+int fputc(int ch, FILE *f)
+{
+ /* Send data. */
+ return DbgConsole_SendDataReliable((uint8_t *)(&ch), 1);
+}
+
+#pragma weak fgetc
+int fgetc(FILE *f)
+{
+ char ch;
+
+ /* Receive data. */
+ DbgConsole_ReadCharacter((uint8_t *)&ch);
+
+ return ch;
+}
+
+/*
+ * Terminate the program, passing a return code back to the user.
+ * This function may not return.
+ */
+void _sys_exit(int returncode)
+{
+ while (1)
+ {
+ }
+}
+
+/*
+ * Writes a character to the output channel. This function is used
+ * for last-resort error message output.
+ */
+void _ttywrch(int ch)
+{
+ char ench = ch;
+ DbgConsole_SendDataReliable((uint8_t *)(&ench), 1);
+}
+
+char *_sys_command_string(char *cmd, int len)
+{
+ return (cmd);
+}
+#endif /* SDK_DEBUGCONSOLE_UART */
+
+/* These function __write and __read is used to support ARM_GCC, KDS, Atollic toolchains to printf and scanf*/
+#elif (defined(__GNUC__))
+
+#if ((defined(__GNUC__) && (!defined(__MCUXPRESSO)) && (defined(SDK_DEBUGCONSOLE_UART))) || \
+ (defined(__MCUXPRESSO) && (defined(SDK_DEBUGCONSOLE_UART))))
+int __attribute__((weak)) _write(int handle, char *buffer, int size);
+int __attribute__((weak)) _write(int handle, char *buffer, int size)
+{
+ if (buffer == NULL)
+ {
+ /* return -1 if error. */
+ return -1;
+ }
+
+ /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
+ if ((handle != 1) && (handle != 2))
+ {
+ return -1;
+ }
+
+ /* Send data. */
+ (void)DbgConsole_SendDataReliable((uint8_t *)buffer, (size_t)size);
+
+ return size;
+}
+
+int __attribute__((weak)) _read(int handle, char *buffer, int size);
+int __attribute__((weak)) _read(int handle, char *buffer, int size)
+{
+ uint8_t ch = 0U;
+ int actualSize = 0;
+
+ /* This function only reads from "standard in", for all other file handles it returns failure. */
+ if (handle != 0)
+ {
+ return -1;
+ }
+
+ /* Receive data. */
+ for (; size > 0; size--)
+ {
+ if (DbgConsole_ReadCharacter(&ch) < 0)
+ {
+ break;
+ }
+
+ *buffer++ = (char)ch;
+ actualSize++;
+
+ if ((ch == 0U) || (ch == (uint8_t)'\n') || (ch == (uint8_t)'\r'))
+ {
+ break;
+ }
+ }
+
+ return (actualSize > 0) ? actualSize : -1;
+}
+#endif
+
+#endif /* __ICCARM__ */
diff --git a/third_party/nxp/K32W061DK6/devices/K32W061/utilities/debug_console/fsl_debug_console.h b/third_party/nxp/K32W061DK6/devices/K32W061/utilities/debug_console/fsl_debug_console.h
new file mode 100755
index 0000000..9adf809
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/devices/K32W061/utilities/debug_console/fsl_debug_console.h
@@ -0,0 +1,227 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Debug console shall provide input and output functions to scan and print formatted data.
+ * o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier"
+ * - [flags] :'-', '+', '#', ' ', '0'
+ * - [width]: number (0,1...)
+ * - [.precision]: number (0,1...)
+ * - [length]: do not support
+ * - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n'
+ * o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier"
+ * - [*]: is supported.
+ * - [width]: number (0,1...)
+ * - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t')
+ * - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's'
+ */
+
+#ifndef _FSL_DEBUGCONSOLE_H_
+#define _FSL_DEBUGCONSOLE_H_
+
+#include "fsl_common.h"
+#include "serial_manager.h"
+
+/*!
+ * @addtogroup debugconsole
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+extern serial_handle_t g_serialHandle; /*!< serial manager handle */
+
+/*! @brief Definition select redirect toolchain printf, scanf to uart or not. */
+#define DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN 0U /*!< Select toolchain printf and scanf. */
+#define DEBUGCONSOLE_REDIRECT_TO_SDK 1U /*!< Select SDK version printf, scanf. */
+#define DEBUGCONSOLE_DISABLE 2U /*!< Disable debugconsole function. */
+
+/*! @brief Definition to select sdk or toolchain printf, scanf. The macro only support
+ * to be redefined in project setting.
+ */
+#ifndef SDK_DEBUGCONSOLE
+#define SDK_DEBUGCONSOLE 1U
+#endif
+
+/*! @brief whether provide low level IO implementation to toolchain printf and scanf.
+ * For example, within MCUXpresso, if the macro SDK_DEBUGCONSOLE_UART is defined,
+ * __sys_write and __sys_readc will be used when __REDLIB__ is defined;
+ * _write and _read will be used in other cases.
+ * If the macro SDK_DEBUGCONSOLE_UART is not defined, the semihost will be used.
+ */
+#ifndef SDK_DEBUGCONSOLE_UART
+/* mcux will handle this macro, not define it here */
+#if (!defined(__MCUXPRESSO))
+#define SDK_DEBUGCONSOLE_UART
+#endif
+#endif
+
+#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE)
+#include <stdio.h>
+#endif
+
+/*! @brief Definition to select redirect toolchain printf, scanf to uart or not.
+ *
+ * if SDK_DEBUGCONSOLE defined to 0,it represents select toolchain printf, scanf.
+ * if SDK_DEBUGCONSOLE defined to 1,it represents select SDK version printf, scanf.
+ * if SDK_DEBUGCONSOLE defined to 2,it represents disable debugconsole function.
+ */
+#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE /* Disable debug console */
+#define PRINTF(...) \
+ do \
+ { \
+ } while (0)
+#define SCANF(...) \
+ do \
+ { \
+ } while (0)
+#define PUTCHAR(...) \
+ do \
+ { \
+ } while (0)
+#define GETCHAR() -1
+#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK /* Select printf, scanf, putchar, getchar of SDK version. */
+#define PRINTF DbgConsole_Printf
+#define SCANF DbgConsole_Scanf
+#define PUTCHAR DbgConsole_Putchar
+#define GETCHAR DbgConsole_Getchar
+#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN /* Select printf, scanf, putchar, getchar of toolchain. \ \
+ */
+#define PRINTF printf
+#define SCANF scanf
+#define PUTCHAR putchar
+#define GETCHAR getchar
+#endif /* SDK_DEBUGCONSOLE */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*! @name Initialization*/
+/* @{ */
+
+/*!
+ * @brief Initializes the peripheral used for debug messages.
+ *
+ * Call this function to enable debug log messages to be output via the specified peripheral
+ * initialized by the serial manager module.
+ * After this function has returned, stdout and stdin are connected to the selected peripheral.
+ *
+ * @param instance The instance of the module.
+ * @param baudRate The desired baud rate in bits per second.
+ * @param device Low level device type for the debug console, can be one of the following.
+ * @arg kSerialPort_Uart,
+ * @arg kSerialPort_UsbCdc
+ * @arg kSerialPort_UsbCdcVirtual.
+ * @param clkSrcFreq Frequency of peripheral source clock.
+ *
+ * @return Indicates whether initialization was successful or not.
+ * @retval kStatus_Success Execution successfully
+ */
+status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq);
+
+/*!
+ * @brief De-initializes the peripheral used for debug messages.
+ *
+ * Call this function to disable debug log messages to be output via the specified peripheral
+ * initialized by the serial manager module.
+ *
+ * @return Indicates whether de-initialization was successful or not.
+ */
+status_t DbgConsole_Deinit(void);
+
+#if SDK_DEBUGCONSOLE
+/*!
+ * @brief Writes formatted output to the standard output stream.
+ *
+ * Call this function to write a formatted output to the standard output stream.
+ *
+ * @param formatString Format control string.
+ * @return Returns the number of characters printed or a negative value if an error occurs.
+ */
+int DbgConsole_Printf(const char *formatString, ...);
+
+/*!
+ * @brief Writes a character to stdout.
+ *
+ * Call this function to write a character to stdout.
+ *
+ * @param ch Character to be written.
+ * @return Returns the character written.
+ */
+int DbgConsole_Putchar(int ch);
+
+/*!
+ * @brief Reads formatted data from the standard input stream.
+ *
+ * Call this function to read formatted data from the standard input stream.
+ *
+ * @note Due the limitation in the BM OSA environment (CPU is blocked in the function,
+ * other tasks will not be scheduled), the function cannot be used when the
+ * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment.
+ * And an error is returned when the function called in this case. The suggestion
+ * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char.
+ *
+ * @param formatString Format control string.
+ * @return Returns the number of fields successfully converted and assigned.
+ */
+int DbgConsole_Scanf(char *formatString, ...);
+
+/*!
+ * @brief Reads a character from standard input.
+ *
+ * Call this function to read a character from standard input.
+ *
+ * @note Due the limitation in the BM OSA environment (CPU is blocked in the function,
+ * other tasks will not be scheduled), the function cannot be used when the
+ * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment.
+ * And an error is returned when the function called in this case. The suggestion
+ * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char.
+ *
+ * @return Returns the character read.
+ */
+int DbgConsole_Getchar(void);
+
+/*!
+ * @brief Debug console flush.
+ *
+ * Call this function to wait the tx buffer empty.
+ * If interrupt transfer is using, make sure the global IRQ is enable before call this function
+ * This function should be called when
+ * 1, before enter power down mode
+ * 2, log is required to print to terminal immediately
+ * @return Indicates whether wait idle was successful or not.
+ */
+status_t DbgConsole_Flush(void);
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/*!
+ * @brief Debug console try to get char
+ * This function provides a API which will not block current task, if character is
+ * available return it, otherwise return fail.
+ * @param ch the address of char to receive
+ * @return Indicates get char was successful or not.
+ */
+status_t DbgConsole_TryGetchar(char *ch);
+#endif
+
+#endif /* SDK_DEBUGCONSOLE */
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_DEBUGCONSOLE_H_ */
diff --git a/third_party/nxp/K32W061DK6/devices/K32W061/utilities/debug_console/fsl_debug_console_conf.h b/third_party/nxp/K32W061DK6/devices/K32W061/utilities/debug_console/fsl_debug_console_conf.h
new file mode 100755
index 0000000..366c6cd
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/devices/K32W061/utilities/debug_console/fsl_debug_console_conf.h
@@ -0,0 +1,158 @@
+/*
+ * Copyright 2017 - 2019 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_DEBUG_CONSOLE_CONF_H_
+#define _FSL_DEBUG_CONSOLE_CONF_H_
+
+/****************Debug console configuration********************/
+
+/*! @brief If Non-blocking mode is needed, please define it at project setting,
+ * otherwise blocking mode is the default transfer mode.
+ * Warning: If you want to use non-blocking transfer,please make sure the corresponding
+ * IO interrupt is enable, otherwise there is no output.
+ * And non-blocking is combine with buffer, no matter bare-metal or rtos.
+ * Below shows how to configure in your project if you want to use non-blocking mode.
+ * For IAR, right click project and select "Options", define it in "C/C++ Compiler->Preprocessor->Defined symbols".
+ * For KEIL, click "Options for Target…", define it in "C/C++->Preprocessor Symbols->Define".
+ * For ARMGCC, open CmakeLists.txt and add the following lines,
+ * "SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for debug target.
+ * "SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for release target.
+ * For MCUxpresso, right click project and select "Properties", define it in "C/C++ Build->Settings->MCU C
+ * Complier->Preprocessor".
+ *
+ */
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/*! @brief define the transmit buffer length which is used to store the multi task log, buffer is enabled automatically
+ * when
+ * non-blocking transfer is using,
+ * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.
+ * If it is configured too small, log maybe missed , because the log will not be
+ * buffered if the buffer is full, and the print will return immediately with -1.
+ * And this value should be multiple of 4 to meet memory alignment.
+ *
+ */
+#ifndef DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN
+#define DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN (512U)
+#endif /* DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN */
+
+/*! @brief define the receive buffer length which is used to store the user input, buffer is enabled automatically when
+ * non-blocking transfer is using,
+ * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.
+ * If it is configured too small, log maybe missed, because buffer will be overwrited if buffer is too small.
+ * And this value should be multiple of 4 to meet memory alignment.
+ *
+ */
+#ifndef DEBUG_CONSOLE_RECEIVE_BUFFER_LEN
+#define DEBUG_CONSOLE_RECEIVE_BUFFER_LEN (1024U)
+#endif /* DEBUG_CONSOLE_RECEIVE_BUFFER_LEN */
+
+/*!@ brief Whether enable the reliable TX function
+ * If the macro is zero, the reliable TX function of the debug console is disabled.
+ * When the macro is zero, the string of PRINTF will be thrown away after the transmit buffer is full.
+ */
+#ifndef DEBUG_CONSOLE_TX_RELIABLE_ENABLE
+#define DEBUG_CONSOLE_TX_RELIABLE_ENABLE (1U)
+#endif /* DEBUG_CONSOLE_RX_ENABLE */
+
+#else
+#define DEBUG_CONSOLE_TRANSFER_BLOCKING
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+/*!@ brief Whether enable the RX function
+ * If the macro is zero, the receive function of the debug console is disabled.
+ */
+#ifndef DEBUG_CONSOLE_RX_ENABLE
+#define DEBUG_CONSOLE_RX_ENABLE (1U)
+#endif /* DEBUG_CONSOLE_RX_ENABLE */
+
+/*!@ brief define the MAX log length debug console support , that is when you call printf("log", x);, the log
+ * length can not bigger than this value.
+ * This macro decide the local log buffer length, the buffer locate at stack, the stack maybe overflow if
+ * the buffer is too big and current task stack size not big enough.
+ */
+#ifndef DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN
+#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN (128U)
+#endif /* DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN */
+
+/*!@ brief define the buffer support buffer scanf log length, that is when you call scanf("log", &x);, the log
+ * length can not bigger than this value.
+ * As same as the DEBUG_CONSOLE_BUFFER_PRINTF_MAX_LOG_LEN.
+ */
+#ifndef DEBUG_CONSOLE_SCANF_MAX_LOG_LEN
+#define DEBUG_CONSOLE_SCANF_MAX_LOG_LEN (20U)
+#endif /* DEBUG_CONSOLE_SCANF_MAX_LOG_LEN */
+
+/*! @brief Debug console synchronization
+ * User should not change these macro for synchronization mode, but add the
+ * corresponding synchronization mechanism per different software environment.
+ * Such as, if another RTOS is used,
+ * add:
+ * #define DEBUG_CONSOLE_SYNCHRONIZATION_XXXX 3
+ * in this configuration file and implement the synchronization in fsl.log.c.
+ */
+/*! @brief synchronization for baremetal software */
+#define DEBUG_CONSOLE_SYNCHRONIZATION_BM 0
+/*! @brief synchronization for freertos software */
+#define DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS 1
+
+/*! @brief RTOS synchronization mechanism disable
+ * If not defined, default is enable, to avoid multitask log print mess.
+ * If other RTOS is used, you can implement the RTOS's specific synchronization mechanism in fsl.log.c
+ * If synchronization is disabled, log maybe messed on terminal.
+ */
+#ifndef DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+#ifdef FSL_RTOS_FREE_RTOS
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS
+#else
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM
+#endif /* FSL_RTOS_FREE_RTOS */
+#else
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+#endif /* DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION */
+
+/*! @brief echo function support
+ * If you want to use the echo function,please define DEBUG_CONSOLE_ENABLE_ECHO
+ * at your project setting.
+ */
+#ifndef DEBUG_CONSOLE_ENABLE_ECHO
+#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 0
+#else
+#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 1
+#endif /* DEBUG_CONSOLE_ENABLE_ECHO */
+
+/*********************************************************************/
+
+/***************Debug console other configuration*********************/
+/*! @brief Definition to printf the float number. */
+#ifndef PRINTF_FLOAT_ENABLE
+#define PRINTF_FLOAT_ENABLE 0U
+#endif /* PRINTF_FLOAT_ENABLE */
+
+/*! @brief Definition to scanf the float number. */
+#ifndef SCANF_FLOAT_ENABLE
+#define SCANF_FLOAT_ENABLE 0U
+#endif /* SCANF_FLOAT_ENABLE */
+
+/*! @brief Definition to support advanced format specifier for printf. */
+#ifndef PRINTF_ADVANCED_ENABLE
+#define PRINTF_ADVANCED_ENABLE 0U
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+/*! @brief Definition to support advanced format specifier for scanf. */
+#ifndef SCANF_ADVANCED_ENABLE
+#define SCANF_ADVANCED_ENABLE 0U
+#endif /* SCANF_ADVANCED_ENABLE */
+
+/*! @brief Definition to select virtual com(USB CDC) as the debug console. */
+#ifndef BOARD_USE_VIRTUALCOM
+#define BOARD_USE_VIRTUALCOM 0U
+#endif
+/*******************************************************************/
+
+#endif /* _FSL_DEBUG_CONSOLE_CONF_H_ */
diff --git a/third_party/nxp/JN5189/drivers/fsl_assert.c b/third_party/nxp/K32W061DK6/devices/K32W061/utilities/fsl_assert.c
similarity index 99%
copy from third_party/nxp/JN5189/drivers/fsl_assert.c
copy to third_party/nxp/K32W061DK6/devices/K32W061/utilities/fsl_assert.c
index b33ad7a..9052faf 100755
--- a/third_party/nxp/JN5189/drivers/fsl_assert.c
+++ b/third_party/nxp/K32W061DK6/devices/K32W061/utilities/fsl_assert.c
@@ -6,6 +6,7 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+
#include "fsl_common.h"
#include "fsl_debug_console.h"
diff --git a/third_party/nxp/K32W061DK6/devices/K32W061/utilities/str/fsl_str.c b/third_party/nxp/K32W061DK6/devices/K32W061/utilities/str/fsl_str.c
new file mode 100755
index 0000000..c4d1a0c
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/devices/K32W061/utilities/str/fsl_str.c
@@ -0,0 +1,1324 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include <math.h>
+#include <stdarg.h>
+#include <stdlib.h>
+#include "fsl_str.h"
+#include "fsl_debug_console_conf.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief The overflow value.*/
+#ifndef HUGE_VAL
+#define HUGE_VAL (99.e99)
+#endif /* HUGE_VAL */
+
+#if PRINTF_ADVANCED_ENABLE
+/*! @brief Specification modifier flags for printf. */
+enum _debugconsole_printf_flag
+{
+ kPRINTF_Minus = 0x01U, /*!< Minus FLag. */
+ kPRINTF_Plus = 0x02U, /*!< Plus Flag. */
+ kPRINTF_Space = 0x04U, /*!< Space Flag. */
+ kPRINTF_Zero = 0x08U, /*!< Zero Flag. */
+ kPRINTF_Pound = 0x10U, /*!< Pound Flag. */
+ kPRINTF_LengthChar = 0x20U, /*!< Length: Char Flag. */
+ kPRINTF_LengthShortInt = 0x40U, /*!< Length: Short Int Flag. */
+ kPRINTF_LengthLongInt = 0x80U, /*!< Length: Long Int Flag. */
+ kPRINTF_LengthLongLongInt = 0x100U, /*!< Length: Long Long Int Flag. */
+};
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+/*! @brief Specification modifier flags for scanf. */
+enum _debugconsole_scanf_flag
+{
+ kSCANF_Suppress = 0x2U, /*!< Suppress Flag. */
+ kSCANF_DestMask = 0x7cU, /*!< Destination Mask. */
+ kSCANF_DestChar = 0x4U, /*!< Destination Char Flag. */
+ kSCANF_DestString = 0x8U, /*!< Destination String FLag. */
+ kSCANF_DestSet = 0x10U, /*!< Destination Set Flag. */
+ kSCANF_DestInt = 0x20U, /*!< Destination Int Flag. */
+ kSCANF_DestFloat = 0x30U, /*!< Destination Float Flag. */
+ kSCANF_LengthMask = 0x1f00U, /*!< Length Mask Flag. */
+#if SCANF_ADVANCED_ENABLE
+ kSCANF_LengthChar = 0x100U, /*!< Length Char Flag. */
+ kSCANF_LengthShortInt = 0x200U, /*!< Length ShortInt Flag. */
+ kSCANF_LengthLongInt = 0x400U, /*!< Length LongInt Flag. */
+ kSCANF_LengthLongLongInt = 0x800U, /*!< Length LongLongInt Flag. */
+#endif /* SCANF_ADVANCED_ENABLE */
+#if SCANF_FLOAT_ENABLE
+ kSCANF_LengthLongLongDouble = 0x1000U, /*!< Length LongLongDuoble Flag. */
+#endif /*PRINTF_FLOAT_ENABLE */
+ kSCANF_TypeSinged = 0x2000U, /*!< TypeSinged Flag. */
+};
+
+/*! @brief Keil: suppress ellipsis warning in va_arg usage below. */
+#if defined(__CC_ARM)
+#pragma diag_suppress 1256
+#endif /* __CC_ARM */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Scanline function which ignores white spaces.
+ *
+ * @param[in] s The address of the string pointer to update.
+ * @return String without white spaces.
+ */
+static uint32_t ScanIgnoreWhiteSpace(const char **s);
+
+/*!
+ * @brief Converts a radix number to a string and return its length.
+ *
+ * @param[in] numstr Converted string of the number.
+ * @param[in] nump Pointer to the number.
+ * @param[in] neg Polarity of the number.
+ * @param[in] radix The radix to be converted to.
+ * @param[in] use_caps Used to identify %x/X output format.
+
+ * @return Length of the converted string.
+ */
+static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps);
+
+#if PRINTF_FLOAT_ENABLE
+/*!
+ * @brief Converts a floating radix number to a string and return its length.
+ *
+ * @param[in] numstr Converted string of the number.
+ * @param[in] nump Pointer to the number.
+ * @param[in] radix The radix to be converted to.
+ * @param[in] precision_width Specify the precision width.
+
+ * @return Length of the converted string.
+ */
+static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width);
+#endif /* PRINTF_FLOAT_ENABLE */
+
+/*!
+ *
+ */
+double modf(double input_dbl, double *intpart_ptr);
+
+/*************Code for process formatted data*******************************/
+
+static uint32_t ScanIgnoreWhiteSpace(const char **s)
+{
+ uint8_t count = 0;
+ uint8_t c;
+
+ c = **s;
+ while ((c == ' ') || (c == '\t') || (c == '\n') || (c == '\r') || (c == '\v') || (c == '\f'))
+ {
+ count++;
+ (*s)++;
+ c = **s;
+ }
+ return count;
+}
+
+static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps)
+{
+#if PRINTF_ADVANCED_ENABLE
+ int64_t a;
+ int64_t b;
+ int64_t c;
+
+ uint64_t ua;
+ uint64_t ub;
+ uint64_t uc;
+#else
+ int32_t a;
+ int32_t b;
+ int32_t c;
+
+ uint32_t ua;
+ uint32_t ub;
+ uint32_t uc;
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+ int32_t nlen;
+ char *nstrp;
+
+ nlen = 0;
+ nstrp = numstr;
+ *nstrp++ = '\0';
+
+ if (neg)
+ {
+#if PRINTF_ADVANCED_ENABLE
+ a = *(int64_t *)nump;
+#else
+ a = *(int32_t *)nump;
+#endif /* PRINTF_ADVANCED_ENABLE */
+ if (a == 0)
+ {
+ *nstrp = '0';
+ ++nlen;
+ return nlen;
+ }
+ while (a != 0)
+ {
+#if PRINTF_ADVANCED_ENABLE
+ b = (int64_t)a / (int64_t)radix;
+ c = (int64_t)a - ((int64_t)b * (int64_t)radix);
+ if (c < 0)
+ {
+ uc = (uint64_t)c;
+ c = (int64_t)(~uc) + 1 + '0';
+ }
+#else
+ b = a / radix;
+ c = a - (b * radix);
+ if (c < 0)
+ {
+ uc = (uint32_t)c;
+ c = (uint32_t)(~uc) + 1 + '0';
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ else
+ {
+ c = c + '0';
+ }
+ a = b;
+ *nstrp++ = (char)c;
+ ++nlen;
+ }
+ }
+ else
+ {
+#if PRINTF_ADVANCED_ENABLE
+ ua = *(uint64_t *)nump;
+#else
+ ua = *(uint32_t *)nump;
+#endif /* PRINTF_ADVANCED_ENABLE */
+ if (ua == 0)
+ {
+ *nstrp = '0';
+ ++nlen;
+ return nlen;
+ }
+ while (ua != 0)
+ {
+#if PRINTF_ADVANCED_ENABLE
+ ub = (uint64_t)ua / (uint64_t)radix;
+ uc = (uint64_t)ua - ((uint64_t)ub * (uint64_t)radix);
+#else
+ ub = ua / (uint32_t)radix;
+ uc = ua - (ub * (uint32_t)radix);
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+ if (uc < 10)
+ {
+ uc = uc + '0';
+ }
+ else
+ {
+ uc = uc - 10 + (use_caps ? 'A' : 'a');
+ }
+ ua = ub;
+ *nstrp++ = (char)uc;
+ ++nlen;
+ }
+ }
+ return nlen;
+}
+
+#if PRINTF_FLOAT_ENABLE
+static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width)
+{
+ int32_t a;
+ int32_t b;
+ int32_t c;
+ int32_t i;
+ uint32_t uc;
+ double fa;
+ double dc;
+ double fb;
+ double r;
+ double fractpart;
+ double intpart;
+
+ int32_t nlen;
+ char *nstrp;
+ nlen = 0;
+ nstrp = numstr;
+ *nstrp++ = '\0';
+ r = *(double *)nump;
+ if (!r)
+ {
+ *nstrp = '0';
+ ++nlen;
+ return nlen;
+ }
+ fractpart = modf((double)r, (double *)&intpart);
+ /* Process fractional part. */
+ for (i = 0; i < precision_width; i++)
+ {
+ fractpart *= radix;
+ }
+ if (r >= 0)
+ {
+ fa = fractpart + (double)0.5;
+ if (fa >= pow(10, precision_width))
+ {
+ intpart++;
+ }
+ }
+ else
+ {
+ fa = fractpart - (double)0.5;
+ if (fa <= -pow(10, precision_width))
+ {
+ intpart--;
+ }
+ }
+ for (i = 0; i < precision_width; i++)
+ {
+ fb = fa / (int32_t)radix;
+ dc = (fa - (int64_t)fb * (int32_t)radix);
+ c = (int32_t)dc;
+ if (c < 0)
+ {
+ uc = (uint32_t)c;
+ c = (int32_t)(~uc) + 1 + '0';
+ }
+ else
+ {
+ c = c + '0';
+ }
+ fa = fb;
+ *nstrp++ = (char)c;
+ ++nlen;
+ }
+ *nstrp++ = (char)'.';
+ ++nlen;
+ a = (int32_t)intpart;
+ if (a == 0)
+ {
+ *nstrp++ = '0';
+ ++nlen;
+ }
+ else
+ {
+ while (a != 0)
+ {
+ b = (int32_t)a / (int32_t)radix;
+ c = (int32_t)a - ((int32_t)b * (int32_t)radix);
+ if (c < 0)
+ {
+ uc = (uint32_t)c;
+ c = (int32_t)(~uc) + 1 + '0';
+ }
+ else
+ {
+ c = c + '0';
+ }
+ a = b;
+ *nstrp++ = (char)c;
+ ++nlen;
+ }
+ }
+ return nlen;
+}
+#endif /* PRINTF_FLOAT_ENABLE */
+
+/*!
+ * brief This function outputs its parameters according to a formatted string.
+ *
+ * note I/O is performed by calling given function pointer using following
+ * (*func_ptr)(c);
+ *
+ * param[in] fmt_ptr Format string for printf.
+ * param[in] args_ptr Arguments to printf.
+ * param[in] buf pointer to the buffer
+ * param cb print callback function pointer
+ *
+ * return Number of characters to be print
+ */
+int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb)
+{
+ /* va_list ap; */
+ char *p;
+ int32_t c;
+
+ char vstr[33];
+ char *vstrp = NULL;
+ int32_t vlen = 0;
+
+ int32_t done;
+ int32_t count = 0;
+
+ uint32_t field_width;
+ uint32_t precision_width;
+ char *sval;
+ int32_t cval;
+ bool use_caps;
+ uint8_t radix = 0;
+
+#if PRINTF_ADVANCED_ENABLE
+ uint32_t flags_used;
+ int32_t schar, dschar;
+ int64_t ival;
+ uint64_t uval = 0;
+ bool valid_precision_width;
+#else
+ int32_t ival;
+ uint32_t uval = 0;
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+#if PRINTF_FLOAT_ENABLE
+ double fval;
+#endif /* PRINTF_FLOAT_ENABLE */
+
+ /* Start parsing apart the format string and display appropriate formats and data. */
+ for (p = (char *)fmt; (c = *p) != 0; p++)
+ {
+ /*
+ * All formats begin with a '%' marker. Special chars like
+ * '\n' or '\t' are normally converted to the appropriate
+ * character by the __compiler__. Thus, no need for this
+ * routine to account for the '\' character.
+ */
+ if (c != '%')
+ {
+ cb(buf, &count, c, 1);
+ /* By using 'continue', the next iteration of the loop is used, skipping the code that follows. */
+ continue;
+ }
+
+ use_caps = true;
+
+#if PRINTF_ADVANCED_ENABLE
+ /* First check for specification modifier flags. */
+ flags_used = 0;
+ done = false;
+ while (!done)
+ {
+ switch (*++p)
+ {
+ case '-':
+ flags_used |= kPRINTF_Minus;
+ break;
+ case '+':
+ flags_used |= kPRINTF_Plus;
+ break;
+ case ' ':
+ flags_used |= kPRINTF_Space;
+ break;
+ case '0':
+ flags_used |= kPRINTF_Zero;
+ break;
+ case '#':
+ flags_used |= kPRINTF_Pound;
+ break;
+ default:
+ /* We've gone one char too far. */
+ --p;
+ done = true;
+ break;
+ }
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+ /* Next check for minimum field width. */
+ field_width = 0;
+ done = false;
+ while (!done)
+ {
+ c = *++p;
+ if ((c >= '0') && (c <= '9'))
+ {
+ field_width = (field_width * 10) + (c - '0');
+ }
+#if PRINTF_ADVANCED_ENABLE
+ else if (c == '*')
+ {
+ field_width = (uint32_t)va_arg(ap, uint32_t);
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ else
+ {
+ /* We've gone one char too far. */
+ --p;
+ done = true;
+ }
+ }
+ /* Next check for the width and precision field separator. */
+ precision_width = 6;
+#if PRINTF_ADVANCED_ENABLE
+ valid_precision_width = false;
+#endif /* PRINTF_ADVANCED_ENABLE */
+ if (*++p == '.')
+ {
+ /* Must get precision field width, if present. */
+ precision_width = 0;
+ done = false;
+ while (!done)
+ {
+ c = *++p;
+ if ((c >= '0') && (c <= '9'))
+ {
+ precision_width = (precision_width * 10) + (c - '0');
+#if PRINTF_ADVANCED_ENABLE
+ valid_precision_width = true;
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+#if PRINTF_ADVANCED_ENABLE
+ else if (c == '*')
+ {
+ precision_width = (uint32_t)va_arg(ap, uint32_t);
+ valid_precision_width = true;
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ else
+ {
+ /* We've gone one char too far. */
+ --p;
+ done = true;
+ }
+ }
+ }
+ else
+ {
+ /* We've gone one char too far. */
+ --p;
+ }
+#if PRINTF_ADVANCED_ENABLE
+ /*
+ * Check for the length modifier.
+ */
+ switch (/* c = */ *++p)
+ {
+ case 'h':
+ if (*++p != 'h')
+ {
+ flags_used |= kPRINTF_LengthShortInt;
+ --p;
+ }
+ else
+ {
+ flags_used |= kPRINTF_LengthChar;
+ }
+ break;
+ case 'l':
+ if (*++p != 'l')
+ {
+ flags_used |= kPRINTF_LengthLongInt;
+ --p;
+ }
+ else
+ {
+ flags_used |= kPRINTF_LengthLongLongInt;
+ }
+ break;
+ default:
+ /* we've gone one char too far */
+ --p;
+ break;
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ /* Now we're ready to examine the format. */
+ c = *++p;
+ {
+ if ((c == 'd') || (c == 'i') || (c == 'f') || (c == 'F') || (c == 'x') || (c == 'X') || (c == 'o') ||
+ (c == 'b') || (c == 'p') || (c == 'u'))
+ {
+ if ((c == 'd') || (c == 'i'))
+ {
+#if PRINTF_ADVANCED_ENABLE
+ if (flags_used & kPRINTF_LengthLongLongInt)
+ {
+ ival = (int64_t)va_arg(ap, int64_t);
+ }
+ else
+#endif /* PRINTF_ADVANCED_ENABLE */
+ {
+ ival = (int32_t)va_arg(ap, int32_t);
+ }
+ vlen = ConvertRadixNumToString(vstr, &ival, true, 10, use_caps);
+ vstrp = &vstr[vlen];
+#if PRINTF_ADVANCED_ENABLE
+ if (ival < 0)
+ {
+ schar = '-';
+ ++vlen;
+ }
+ else
+ {
+ if (flags_used & kPRINTF_Plus)
+ {
+ schar = '+';
+ ++vlen;
+ }
+ else
+ {
+ if (flags_used & kPRINTF_Space)
+ {
+ schar = ' ';
+ ++vlen;
+ }
+ else
+ {
+ schar = 0;
+ }
+ }
+ }
+ dschar = false;
+ /* Do the ZERO pad. */
+ if (flags_used & kPRINTF_Zero)
+ {
+ if (schar)
+ {
+ cb(buf, &count, schar, 1);
+ }
+ dschar = true;
+
+ cb(buf, &count, '0', field_width - vlen);
+ vlen = field_width;
+ }
+ else
+ {
+ if (!(flags_used & kPRINTF_Minus))
+ {
+ cb(buf, &count, ' ', field_width - vlen);
+ if (schar)
+ {
+ cb(buf, &count, schar, 1);
+ }
+ dschar = true;
+ }
+ }
+ /* The string was built in reverse order, now display in correct order. */
+ if ((!dschar) && schar)
+ {
+ cb(buf, &count, schar, 1);
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+
+#if PRINTF_FLOAT_ENABLE
+ if ((c == 'f') || (c == 'F'))
+ {
+ fval = (double)va_arg(ap, double);
+ vlen = ConvertFloatRadixNumToString(vstr, &fval, 10, precision_width);
+ vstrp = &vstr[vlen];
+
+#if PRINTF_ADVANCED_ENABLE
+ if (fval < 0)
+ {
+ schar = '-';
+ ++vlen;
+ }
+ else
+ {
+ if (flags_used & kPRINTF_Plus)
+ {
+ schar = '+';
+ ++vlen;
+ }
+ else
+ {
+ if (flags_used & kPRINTF_Space)
+ {
+ schar = ' ';
+ ++vlen;
+ }
+ else
+ {
+ schar = 0;
+ }
+ }
+ }
+ dschar = false;
+ if (flags_used & kPRINTF_Zero)
+ {
+ if (schar)
+ {
+ cb(buf, &count, schar, 1);
+ }
+ dschar = true;
+ cb(buf, &count, '0', field_width - vlen);
+ vlen = field_width;
+ }
+ else
+ {
+ if (!(flags_used & kPRINTF_Minus))
+ {
+ cb(buf, &count, ' ', field_width - vlen);
+ if (schar)
+ {
+ cb(buf, &count, schar, 1);
+ }
+ dschar = true;
+ }
+ }
+ if ((!dschar) && schar)
+ {
+ cb(buf, &count, schar, 1);
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+#endif /* PRINTF_FLOAT_ENABLE */
+ if ((c == 'X') || (c == 'x'))
+ {
+ if (c == 'x')
+ {
+ use_caps = false;
+ }
+#if PRINTF_ADVANCED_ENABLE
+ if (flags_used & kPRINTF_LengthLongLongInt)
+ {
+ uval = (uint64_t)va_arg(ap, uint64_t);
+ }
+ else
+#endif /* PRINTF_ADVANCED_ENABLE */
+ {
+ uval = (uint32_t)va_arg(ap, uint32_t);
+ }
+ vlen = ConvertRadixNumToString(vstr, &uval, false, 16, use_caps);
+ vstrp = &vstr[vlen];
+
+#if PRINTF_ADVANCED_ENABLE
+ dschar = false;
+ if (flags_used & kPRINTF_Zero)
+ {
+ if (flags_used & kPRINTF_Pound)
+ {
+ cb(buf, &count, '0', 1);
+ cb(buf, &count, (use_caps ? 'X' : 'x'), 1);
+ dschar = true;
+ }
+ cb(buf, &count, '0', field_width - vlen);
+ vlen = field_width;
+ }
+ else
+ {
+ if (!(flags_used & kPRINTF_Minus))
+ {
+ if (flags_used & kPRINTF_Pound)
+ {
+ vlen += 2;
+ }
+ cb(buf, &count, ' ', field_width - vlen);
+ if (flags_used & kPRINTF_Pound)
+ {
+ cb(buf, &count, '0', 1);
+ cb(buf, &count, (use_caps ? 'X' : 'x'), 1);
+ dschar = true;
+ }
+ }
+ }
+
+ if ((flags_used & kPRINTF_Pound) && (!dschar))
+ {
+ cb(buf, &count, '0', 1);
+ cb(buf, &count, (use_caps ? 'X' : 'x'), 1);
+ vlen += 2;
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+ if ((c == 'o') || (c == 'b') || (c == 'p') || (c == 'u'))
+ {
+#if PRINTF_ADVANCED_ENABLE
+ if (flags_used & kPRINTF_LengthLongLongInt)
+ {
+ uval = (uint64_t)va_arg(ap, uint64_t);
+ }
+ else
+#endif /* PRINTF_ADVANCED_ENABLE */
+ {
+ uval = (uint32_t)va_arg(ap, uint32_t);
+ }
+
+ if (c == 'o')
+ {
+ radix = 8;
+ }
+ else if (c == 'b')
+ {
+ radix = 2;
+ }
+ else if (c == 'p')
+ {
+ radix = 16;
+ }
+ else
+ {
+ radix = 10;
+ }
+
+ vlen = ConvertRadixNumToString(vstr, &uval, false, radix, use_caps);
+ vstrp = &vstr[vlen];
+#if PRINTF_ADVANCED_ENABLE
+ if (flags_used & kPRINTF_Zero)
+ {
+ cb(buf, &count, '0', field_width - vlen);
+ vlen = field_width;
+ }
+ else
+ {
+ if (!(flags_used & kPRINTF_Minus))
+ {
+ cb(buf, &count, ' ', field_width - vlen);
+ }
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+#if !PRINTF_ADVANCED_ENABLE
+ cb(buf, &count, ' ', field_width - vlen);
+#endif /* !PRINTF_ADVANCED_ENABLE */
+ if (vstrp != NULL)
+ {
+ while (*vstrp)
+ {
+ cb(buf, &count, *vstrp--, 1);
+ }
+ }
+#if PRINTF_ADVANCED_ENABLE
+ if (flags_used & kPRINTF_Minus)
+ {
+ cb(buf, &count, ' ', field_width - vlen);
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+ else if (c == 'c')
+ {
+ cval = (char)va_arg(ap, uint32_t);
+ cb(buf, &count, cval, 1);
+ }
+ else if (c == 's')
+ {
+ sval = (char *)va_arg(ap, char *);
+ if (sval)
+ {
+#if PRINTF_ADVANCED_ENABLE
+ if (valid_precision_width)
+ {
+ vlen = precision_width;
+ }
+ else
+ {
+ vlen = strlen(sval);
+ }
+#else
+ vlen = strlen(sval);
+#endif /* PRINTF_ADVANCED_ENABLE */
+#if PRINTF_ADVANCED_ENABLE
+ if (!(flags_used & kPRINTF_Minus))
+#endif /* PRINTF_ADVANCED_ENABLE */
+ {
+ cb(buf, &count, ' ', field_width - vlen);
+ }
+
+#if PRINTF_ADVANCED_ENABLE
+ if (valid_precision_width)
+ {
+ while ((*sval) && (vlen > 0))
+ {
+ cb(buf, &count, *sval++, 1);
+ vlen--;
+ }
+ /* In case that vlen sval is shorter than vlen */
+ vlen = precision_width - vlen;
+ }
+ else
+ {
+#endif /* PRINTF_ADVANCED_ENABLE */
+ while (*sval)
+ {
+ cb(buf, &count, *sval++, 1);
+ }
+#if PRINTF_ADVANCED_ENABLE
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+#if PRINTF_ADVANCED_ENABLE
+ if (flags_used & kPRINTF_Minus)
+ {
+ cb(buf, &count, ' ', field_width - vlen);
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+ }
+ else
+ {
+ cb(buf, &count, c, 1);
+ }
+ }
+ }
+
+ return count;
+}
+
+/*!
+ * brief Converts an input line of ASCII characters based upon a provided
+ * string format.
+ *
+ * param[in] line_ptr The input line of ASCII data.
+ * param[in] format Format first points to the format string.
+ * param[in] args_ptr The list of parameters.
+ *
+ * return Number of input items converted and assigned.
+ * retval IO_EOF When line_ptr is empty string "".
+ */
+int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr)
+{
+ uint8_t base;
+ int8_t neg;
+ /* Identifier for the format string. */
+ char *c = format;
+ char temp;
+ char *buf;
+ /* Flag telling the conversion specification. */
+ uint32_t flag = 0;
+ /* Filed width for the matching input streams. */
+ uint32_t field_width;
+ /* How many arguments are assigned except the suppress. */
+ uint32_t nassigned = 0;
+ /* How many characters are read from the input streams. */
+ uint32_t n_decode = 0;
+
+ int32_t val;
+
+ const char *s;
+ /* Identifier for the input string. */
+ const char *p = line_ptr;
+
+#if SCANF_FLOAT_ENABLE
+ double fnum = 0.0;
+#endif /* SCANF_FLOAT_ENABLE */
+ /* Return EOF error before any conversion. */
+ if (*p == '\0')
+ {
+ return -1;
+ }
+
+ /* Decode directives. */
+ while ((*c) && (*p))
+ {
+ /* Ignore all white-spaces in the format strings. */
+ if (ScanIgnoreWhiteSpace((const char **)&c))
+ {
+ n_decode += ScanIgnoreWhiteSpace(&p);
+ }
+ else if ((*c != '%') || ((*c == '%') && (*(c + 1) == '%')))
+ {
+ /* Ordinary characters. */
+ c++;
+ if (*p == *c)
+ {
+ n_decode++;
+ p++;
+ c++;
+ }
+ else
+ {
+ /* Match failure. Misalignment with C99, the unmatched characters need to be pushed back to stream.
+ * However, it is deserted now. */
+ break;
+ }
+ }
+ else
+ {
+ /* convernsion specification */
+ c++;
+ /* Reset. */
+ flag = 0;
+ field_width = 0;
+ base = 0;
+
+ /* Loop to get full conversion specification. */
+ while ((*c) && (!(flag & kSCANF_DestMask)))
+ {
+ switch (*c)
+ {
+#if SCANF_ADVANCED_ENABLE
+ case '*':
+ if (flag & kSCANF_Suppress)
+ {
+ /* Match failure. */
+ return nassigned;
+ }
+ flag |= kSCANF_Suppress;
+ c++;
+ break;
+ case 'h':
+ if (flag & kSCANF_LengthMask)
+ {
+ /* Match failure. */
+ return nassigned;
+ }
+
+ if (c[1] == 'h')
+ {
+ flag |= kSCANF_LengthChar;
+ c++;
+ }
+ else
+ {
+ flag |= kSCANF_LengthShortInt;
+ }
+ c++;
+ break;
+ case 'l':
+ if (flag & kSCANF_LengthMask)
+ {
+ /* Match failure. */
+ return nassigned;
+ }
+
+ if (c[1] == 'l')
+ {
+ flag |= kSCANF_LengthLongLongInt;
+ c++;
+ }
+ else
+ {
+ flag |= kSCANF_LengthLongInt;
+ }
+ c++;
+ break;
+#endif /* SCANF_ADVANCED_ENABLE */
+#if SCANF_FLOAT_ENABLE
+ case 'L':
+ if (flag & kSCANF_LengthMask)
+ {
+ /* Match failure. */
+ return nassigned;
+ }
+ flag |= kSCANF_LengthLongLongDouble;
+ c++;
+ break;
+#endif /* SCANF_FLOAT_ENABLE */
+ case '0':
+ case '1':
+ case '2':
+ case '3':
+ case '4':
+ case '5':
+ case '6':
+ case '7':
+ case '8':
+ case '9':
+ if (field_width)
+ {
+ /* Match failure. */
+ return nassigned;
+ }
+ do
+ {
+ field_width = field_width * 10 + *c - '0';
+ c++;
+ } while ((*c >= '0') && (*c <= '9'));
+ break;
+ case 'd':
+ base = 10;
+ flag |= kSCANF_TypeSinged;
+ flag |= kSCANF_DestInt;
+ c++;
+ break;
+ case 'u':
+ base = 10;
+ flag |= kSCANF_DestInt;
+ c++;
+ break;
+ case 'o':
+ base = 8;
+ flag |= kSCANF_DestInt;
+ c++;
+ break;
+ case 'x':
+ case 'X':
+ base = 16;
+ flag |= kSCANF_DestInt;
+ c++;
+ break;
+ case 'i':
+ base = 0;
+ flag |= kSCANF_DestInt;
+ c++;
+ break;
+#if SCANF_FLOAT_ENABLE
+ case 'a':
+ case 'A':
+ case 'e':
+ case 'E':
+ case 'f':
+ case 'F':
+ case 'g':
+ case 'G':
+ flag |= kSCANF_DestFloat;
+ c++;
+ break;
+#endif /* SCANF_FLOAT_ENABLE */
+ case 'c':
+ flag |= kSCANF_DestChar;
+ if (!field_width)
+ {
+ field_width = 1;
+ }
+ c++;
+ break;
+ case 's':
+ flag |= kSCANF_DestString;
+ c++;
+ break;
+ default:
+ return nassigned;
+ }
+ }
+
+ if (!(flag & kSCANF_DestMask))
+ {
+ /* Format strings are exhausted. */
+ return nassigned;
+ }
+
+ if (!field_width)
+ {
+ /* Large than length of a line. */
+ field_width = 99;
+ }
+
+ /* Matching strings in input streams and assign to argument. */
+ switch (flag & kSCANF_DestMask)
+ {
+ case kSCANF_DestChar:
+ s = (const char *)p;
+ buf = va_arg(args_ptr, char *);
+ while ((field_width--) && (*p))
+ {
+ if (!(flag & kSCANF_Suppress))
+ {
+ *buf++ = *p++;
+ }
+ else
+ {
+ p++;
+ }
+ n_decode++;
+ }
+
+ if ((!(flag & kSCANF_Suppress)) && (s != p))
+ {
+ nassigned++;
+ }
+ break;
+ case kSCANF_DestString:
+ n_decode += ScanIgnoreWhiteSpace(&p);
+ s = p;
+ buf = va_arg(args_ptr, char *);
+ while ((field_width--) && (*p != '\0') && (*p != ' ') && (*p != '\t') && (*p != '\n') &&
+ (*p != '\r') && (*p != '\v') && (*p != '\f'))
+ {
+ if (flag & kSCANF_Suppress)
+ {
+ p++;
+ }
+ else
+ {
+ *buf++ = *p++;
+ }
+ n_decode++;
+ }
+
+ if ((!(flag & kSCANF_Suppress)) && (s != p))
+ {
+ /* Add NULL to end of string. */
+ *buf = '\0';
+ nassigned++;
+ }
+ break;
+ case kSCANF_DestInt:
+ n_decode += ScanIgnoreWhiteSpace(&p);
+ s = p;
+ val = 0;
+ if ((base == 0) || (base == 16))
+ {
+ if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X')))
+ {
+ base = 16;
+ if (field_width >= 1)
+ {
+ p += 2;
+ n_decode += 2;
+ field_width -= 2;
+ }
+ }
+ }
+
+ if (base == 0)
+ {
+ if (s[0] == '0')
+ {
+ base = 8;
+ }
+ else
+ {
+ base = 10;
+ }
+ }
+
+ neg = 1;
+ switch (*p)
+ {
+ case '-':
+ neg = -1;
+ n_decode++;
+ p++;
+ field_width--;
+ break;
+ case '+':
+ neg = 1;
+ n_decode++;
+ p++;
+ field_width--;
+ break;
+ default:
+ break;
+ }
+
+ while ((*p) && (field_width--))
+ {
+ if ((*p <= '9') && (*p >= '0'))
+ {
+ temp = *p - '0';
+ }
+ else if ((*p <= 'f') && (*p >= 'a'))
+ {
+ temp = *p - 'a' + 10;
+ }
+ else if ((*p <= 'F') && (*p >= 'A'))
+ {
+ temp = *p - 'A' + 10;
+ }
+ else
+ {
+ temp = base;
+ }
+
+ if (temp >= base)
+ {
+ break;
+ }
+ else
+ {
+ val = base * val + temp;
+ }
+ p++;
+ n_decode++;
+ }
+ val *= neg;
+ if (!(flag & kSCANF_Suppress))
+ {
+#if SCANF_ADVANCED_ENABLE
+ switch (flag & kSCANF_LengthMask)
+ {
+ case kSCANF_LengthChar:
+ if (flag & kSCANF_TypeSinged)
+ {
+ *va_arg(args_ptr, signed char *) = (signed char)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned char *) = (unsigned char)val;
+ }
+ break;
+ case kSCANF_LengthShortInt:
+ if (flag & kSCANF_TypeSinged)
+ {
+ *va_arg(args_ptr, signed short *) = (signed short)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned short *) = (unsigned short)val;
+ }
+ break;
+ case kSCANF_LengthLongInt:
+ if (flag & kSCANF_TypeSinged)
+ {
+ *va_arg(args_ptr, signed long int *) = (signed long int)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned long int *) = (unsigned long int)val;
+ }
+ break;
+ case kSCANF_LengthLongLongInt:
+ if (flag & kSCANF_TypeSinged)
+ {
+ *va_arg(args_ptr, signed long long int *) = (signed long long int)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned long long int *) = (unsigned long long int)val;
+ }
+ break;
+ default:
+ /* The default type is the type int. */
+ if (flag & kSCANF_TypeSinged)
+ {
+ *va_arg(args_ptr, signed int *) = (signed int)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned int *) = (unsigned int)val;
+ }
+ break;
+ }
+#else
+ /* The default type is the type int. */
+ if (flag & kSCANF_TypeSinged)
+ {
+ *va_arg(args_ptr, signed int *) = (signed int)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned int *) = (unsigned int)val;
+ }
+#endif /* SCANF_ADVANCED_ENABLE */
+ nassigned++;
+ }
+ break;
+#if SCANF_FLOAT_ENABLE
+ case kSCANF_DestFloat:
+ n_decode += ScanIgnoreWhiteSpace(&p);
+ fnum = strtod(p, (char **)&s);
+
+ if ((fnum >= HUGE_VAL) || (fnum <= -HUGE_VAL))
+ {
+ break;
+ }
+
+ n_decode += (int)(s) - (int)(p);
+ p = s;
+ if (!(flag & kSCANF_Suppress))
+ {
+ if (flag & kSCANF_LengthLongLongDouble)
+ {
+ *va_arg(args_ptr, double *) = fnum;
+ }
+ else
+ {
+ *va_arg(args_ptr, float *) = (float)fnum;
+ }
+ nassigned++;
+ }
+ break;
+#endif /* SCANF_FLOAT_ENABLE */
+ default:
+ return nassigned;
+ }
+ }
+ }
+ return nassigned;
+}
diff --git a/third_party/nxp/K32W061DK6/devices/K32W061/utilities/str/fsl_str.h b/third_party/nxp/K32W061DK6/devices/K32W061/utilities/str/fsl_str.h
new file mode 100755
index 0000000..bf7adcc
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/devices/K32W061/utilities/str/fsl_str.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _FSL_STR_H
+#define _FSL_STR_H
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup debugconsole
+ * @{
+ */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @brief A function pointer which is used when format printf log.
+ */
+typedef void (*printfCb)(char *buf, int32_t *indicator, char val, int len);
+
+/*!
+ * @brief This function outputs its parameters according to a formatted string.
+ *
+ * @note I/O is performed by calling given function pointer using following
+ * (*func_ptr)(c);
+ *
+ * @param[in] fmt Format string for printf.
+ * @param[in] ap Arguments to printf.
+ * @param[in] buf pointer to the buffer
+ * @param cb print callbck function pointer
+ *
+ * @return Number of characters to be print
+ */
+int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb);
+
+/*!
+ * @brief Converts an input line of ASCII characters based upon a provided
+ * string format.
+ *
+ * @param[in] line_ptr The input line of ASCII data.
+ * @param[in] format Format first points to the format string.
+ * @param[in] args_ptr The list of parameters.
+ *
+ * @return Number of input items converted and assigned.
+ * @retval IO_EOF When line_ptr is empty string "".
+ */
+int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_STR_H */
diff --git a/third_party/nxp/JN5189/crypto/aes_alt.c b/third_party/nxp/K32W061DK6/middleware/mbedtls/port/ksdk/aes_alt.c
similarity index 98%
copy from third_party/nxp/JN5189/crypto/aes_alt.c
copy to third_party/nxp/K32W061DK6/middleware/mbedtls/port/ksdk/aes_alt.c
index aa5173b..31acea7 100755
--- a/third_party/nxp/JN5189/crypto/aes_alt.c
+++ b/third_party/nxp/K32W061DK6/middleware/mbedtls/port/ksdk/aes_alt.c
@@ -4,6 +4,7 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+
#if !defined(MBEDTLS_CONFIG_FILE)
#include "mbedtls/config.h"
#else
@@ -24,7 +25,7 @@
#endif
#if defined(MBEDTLS_AES_ALT)
-
+/* clang-format off */
/*
* 32-bit integer manipulation macros (little endian)
*/
@@ -1360,9 +1361,11 @@
}
#endif /* !MBEDTLS_AES_CRYPT_CTR_ALT */
#endif /* MBEDTLS_CIPHER_MODE_CTR */
+/* clang-format on */
/* HASHCRYPT AES */
#if defined(MBEDTLS_FREESCALE_HASHCRYPT_AES)
+
/*
* AES key schedule (encryption)
*/
@@ -1384,7 +1387,7 @@
default:
return (MBEDTLS_ERR_AES_INVALID_KEY_LENGTH);
}
- /* secret bus is marked as key address == hashcrypt base */
+ /* secret bus is marked as key address == HASHCRYPT base */
if ((uint32_t)key == (uint32_t)HASHCRYPT)
{
ctx->keyType = kHASHCRYPT_SecretKey;
@@ -1422,7 +1425,7 @@
default:
return (MBEDTLS_ERR_AES_INVALID_KEY_LENGTH);
}
- /* secret bus is marked as key address == hashcrypt base */
+ /* secret bus is marked as key address == HASHCRYPT base */
if ((uint32_t)key == (uint32_t)HASHCRYPT)
{
ctx->keyType = kHASHCRYPT_SecretKey;
@@ -1507,15 +1510,15 @@
* AES-CTR buffer encryption/decryption
*/
int mbedtls_aes_crypt_ctr(mbedtls_aes_context *ctx,
- size_t length,
- size_t *nc_off,
- unsigned char nonce_counter[16],
- unsigned char stream_block[16],
- const unsigned char *input,
- unsigned char *output)
+ size_t length,
+ size_t *nc_off,
+ unsigned char nonce_counter[16],
+ unsigned char stream_block[16],
+ const unsigned char *input,
+ unsigned char *output)
{
- if (kStatus_Success != HASHCRYPT_AES_CryptCtr(HASHCRYPT, ctx, input, output, length, nonce_counter,
- stream_block, nc_off))
+ if (kStatus_Success !=
+ HASHCRYPT_AES_CryptCtr(HASHCRYPT, ctx, input, output, length, nonce_counter, stream_block, nc_off))
{
return (MBEDTLS_ERR_AES_HW_ACCEL_FAILED);
}
diff --git a/third_party/nxp/JN5189/crypto/aes_alt.h b/third_party/nxp/K32W061DK6/middleware/mbedtls/port/ksdk/aes_alt.h
similarity index 100%
copy from third_party/nxp/JN5189/crypto/aes_alt.h
copy to third_party/nxp/K32W061DK6/middleware/mbedtls/port/ksdk/aes_alt.h
diff --git a/third_party/nxp/JN5189/crypto/ksdk_mbedtls.c b/third_party/nxp/K32W061DK6/middleware/mbedtls/port/ksdk/ksdk_mbedtls.c
similarity index 99%
copy from third_party/nxp/JN5189/crypto/ksdk_mbedtls.c
copy to third_party/nxp/K32W061DK6/middleware/mbedtls/port/ksdk/ksdk_mbedtls.c
index fbeaa31..ad9f0a2 100755
--- a/third_party/nxp/JN5189/crypto/ksdk_mbedtls.c
+++ b/third_party/nxp/K32W061DK6/middleware/mbedtls/port/ksdk/ksdk_mbedtls.c
@@ -31,7 +31,11 @@
#include "fsl_hashcrypt.h"
#endif
#if defined(FSL_FEATURE_SOC_TRNG_COUNT) && (FSL_FEATURE_SOC_TRNG_COUNT > 0)
-#include "fsl_rng.h"
+#if defined CPU_JN518X
+ #include "fsl_rng.h"
+#else
+ #include "fsl_trng.h"
+#endif
#elif defined(FSL_FEATURE_SOC_RNG_COUNT) && (FSL_FEATURE_SOC_RNG_COUNT > 0)
#include "fsl_rnga.h"
#elif defined(FSL_FEATURE_SOC_LPC_RNG1_COUNT) && (FSL_FEATURE_SOC_LPC_RNG1_COUNT > 0)
@@ -159,8 +163,14 @@
#endif
{ /* Init RNG module.*/
#if defined(FSL_FEATURE_SOC_TRNG_COUNT) && (FSL_FEATURE_SOC_TRNG_COUNT > 0)
-#if defined(RNG)
-#define TRNG0 RNG
+#if defined CPU_JN518X
+ #if defined(RNG)
+ #define TRNG0 RNG
+ #endif
+#else
+ #if defined(TRNG)
+ #define TRNG0 TRNG
+ #endif
#endif
trng_config_t trngConfig;
@@ -590,7 +600,7 @@
int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, const unsigned char *key, unsigned int keybits)
{
uint32_t *RK;
-
+
#ifdef MBEDTLS_AES_ALT_NO_192
if (keybits == 192u)
{
@@ -607,7 +617,7 @@
#if defined(MBEDTLS_FREESCALE_LTC_AES) || defined(MBEDTLS_FREESCALE_LPC_AES) || defined(MBEDTLS_FREESCALE_CAU3_AES) || \
defined(MBEDTLS_FREESCALE_CAAM_AES) || defined(MBEDTLS_FREESCALE_DCP_AES)
- const unsigned char *key_tmp = key;
+ const unsigned char *key_tmp = key;
ctx->rk = RK = ctx->buf;
memcpy(RK, key_tmp, keybits / 8);
@@ -659,7 +669,7 @@
int mbedtls_aes_setkey_dec(mbedtls_aes_context *ctx, const unsigned char *key, unsigned int keybits)
{
uint32_t *RK;
-
+
#ifdef MBEDTLS_AES_ALT_NO_192
if (keybits == 192u)
{
@@ -4377,7 +4387,11 @@
#if defined(MBEDTLS_ENTROPY_HARDWARE_ALT)
#if defined(FSL_FEATURE_SOC_TRNG_COUNT) && (FSL_FEATURE_SOC_TRNG_COUNT > 0)
-#include "fsl_rng.h"
+#if defined CPU_JN518X
+ #include "fsl_rng.h"
+#else
+ #include "fsl_trng.h"
+#endif
#elif defined(FSL_FEATURE_SOC_RNG_COUNT) && (FSL_FEATURE_SOC_RNG_COUNT > 0)
#include "fsl_rnga.h"
#elif defined(FSL_FEATURE_SOC_LPC_RNG_COUNT) && (FSL_FEATURE_SOC_LPC_RNG_COUNT > 0)
@@ -4391,8 +4405,14 @@
status_t result = kStatus_Success;
#if defined(FSL_FEATURE_SOC_TRNG_COUNT) && (FSL_FEATURE_SOC_TRNG_COUNT > 0)
-#ifndef RNG
-#define TRNG0 RNG
+#if defined CPU_JN518X
+ #ifndef TRNG0
+ #define TRNG0 RNG
+ #endif
+#else
+ #ifndef TRNG0
+ #define TRNG0 TRNG
+ #endif
#endif
result = TRNG_GetRandomData(TRNG0, output, len);
#elif defined(FSL_FEATURE_SOC_RNG_COUNT) && (FSL_FEATURE_SOC_RNG_COUNT > 0)
diff --git a/third_party/nxp/JN5189/crypto/ksdk_mbedtls.h b/third_party/nxp/K32W061DK6/middleware/mbedtls/port/ksdk/ksdk_mbedtls.h
similarity index 84%
copy from third_party/nxp/JN5189/crypto/ksdk_mbedtls.h
copy to third_party/nxp/K32W061DK6/middleware/mbedtls/port/ksdk/ksdk_mbedtls.h
index 0d9d965..cb545c5 100755
--- a/third_party/nxp/JN5189/crypto/ksdk_mbedtls.h
+++ b/third_party/nxp/K32W061DK6/middleware/mbedtls/port/ksdk/ksdk_mbedtls.h
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2017, NXP Semiconductors, Inc.
+ * Copyright 2017 NXP
* All rights reserved.
*
- *
+ *
* SPDX-License-Identifier: BSD-3-Clause
*/
-
+
#ifndef KSDK_MBEDTLS_H
#define KSDK_MBEDTLS_H
diff --git a/third_party/nxp/JN5189/crypto/sha1_alt.h b/third_party/nxp/K32W061DK6/middleware/mbedtls/port/ksdk/sha1_alt.h
similarity index 100%
copy from third_party/nxp/JN5189/crypto/sha1_alt.h
copy to third_party/nxp/K32W061DK6/middleware/mbedtls/port/ksdk/sha1_alt.h
diff --git a/third_party/nxp/JN5189/crypto/sha256_alt.h b/third_party/nxp/K32W061DK6/middleware/mbedtls/port/ksdk/sha256_alt.h
similarity index 97%
copy from third_party/nxp/JN5189/crypto/sha256_alt.h
copy to third_party/nxp/K32W061DK6/middleware/mbedtls/port/ksdk/sha256_alt.h
index eeb850c..2fe0148 100755
--- a/third_party/nxp/JN5189/crypto/sha256_alt.h
+++ b/third_party/nxp/K32W061DK6/middleware/mbedtls/port/ksdk/sha256_alt.h
@@ -57,7 +57,7 @@
/**
* \brief SHA-256 context structure
*/
-#define mbedtls_sha256_context cau3_hash_ctx_t
+#define mbedtls_sha256_context cau3_hash_ctx_t
#elif defined(MBEDTLS_FREESCALE_DCP_SHA256)
diff --git a/third_party/nxp/K32W061DK6/middleware/wireless/framework/Common/MicroInt_arm_sdk2.c b/third_party/nxp/K32W061DK6/middleware/wireless/framework/Common/MicroInt_arm_sdk2.c
new file mode 100755
index 0000000..b1fad83
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/middleware/wireless/framework/Common/MicroInt_arm_sdk2.c
@@ -0,0 +1,233 @@
+/*****************************************************************************
+ *
+ * MODULE: Microspecific
+ *
+ * COMPONENT: Microspecific
+ *
+ * AUTHOR: Wayne Ellis
+ *
+ * DESCRIPTION: JN517x Microspecific Interrupt Controller Code
+ *
+ * $HeadURL: $
+ *
+ * $Revision: $
+ *
+ * $LastChangedBy: we1 $
+ *
+ * $LastChangedDate: $
+ *
+ * $Id: $
+ *
+ *****************************************************************************
+ *
+ * This software is owned by Jennic and/or its supplier and is protected
+ * under applicable copyright laws. All rights are reserved. We grant You,
+ * and any third parties, a license to use this software solely and
+ * exclusively on Jennic products. You, and any third parties must reproduce
+ * the copyright and warranty notice and any other legend of ownership on each
+ * copy or partial copy of the software.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". JENNIC MAKES NO WARRANTIES, WHETHER
+ * EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE,
+ * ACCURACY OR LACK OF NEGLIGENCE. JENNIC SHALL NOT, IN ANY CIRCUMSTANCES,
+ * BE LIABLE FOR ANY DAMAGES, INCLUDING, BUT NOT LIMITED TO, SPECIAL,
+ * INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON WHATSOEVER.
+ *
+ * Copyright Jennic Ltd. 2014 All rights reserved
+ *
+ ****************************************************************************/
+
+/****************************************************************************/
+/*** Include files ***/
+/****************************************************************************/
+#include "jendefs.h"
+
+#include "MicroSpecific.h"
+//#include "jn518x.h"
+//#include "PeripheralRegs.h"
+//#include <ARMcortexM3Registers_JN51xx.h>
+
+/****************************************************************************/
+/*** Macro Definitions ***/
+/****************************************************************************/
+// PreEmpt Priority field is [7:5]
+#define PREEMPT_PRIORITY_FIELD (4)
+
+/****************************************************************************/
+/*** Type Definitions ***/
+/****************************************************************************/
+
+/****************************************************************************/
+/*** Local Function Prototypes ***/
+/****************************************************************************/
+
+/****************************************************************************/
+/*** Exported Variables ***/
+/****************************************************************************/
+
+/****************************************************************************/
+/*** Local Variables ***/
+/****************************************************************************/
+
+/****************************************************************************/
+/*** Exported Functions ***/
+/****************************************************************************/
+#if 0
+/****************************************************************************
+ * NAME: vAHI_InitialiseInterruptController
+ *
+ * DESCRIPTION:
+ * Initialise ARM NVIC.
+ *
+ * RETURNS:
+ * Nothing.
+ *
+ * NOTES:
+ *
+ ****************************************************************************/
+
+PUBLIC void vAHI_InitialiseInterruptController(
+ uint32 *pu32InterruptVectorTable)
+{
+ uint32 u32RegisterValue=0;
+
+ // set application interrupt and reset control register
+
+ // write vector key
+ U32_SET_BITS(&u32RegisterValue, REG_APP_INT_RESET_CTRL_VECTKEY);
+ // set priority group
+ U32_SET_BITS(&u32RegisterValue, PREEMPT_PRIORITY_FIELD << REG_APP_INT_RESET_CTRL_PRIGROUP_BIT);
+
+ vREG_Write(REG_APP_INT_RESET_CTRL, u32RegisterValue);
+
+ // set vector table location
+ u32RegisterValue=0;
+
+ // table in RAM - this bit isn't required in the JN5172 at all
+ // U32_SET_BITS(&u32RegisterValue, 1 << REG_INT_VECTOR_TABLE_OFFSET_TBLBASE_BIT);
+
+ // table address
+ U32_SET_BITS(&u32RegisterValue, (uint32)pu32InterruptVectorTable);
+ vREG_Write(REG_INT_VECTOR_TABLE_OFFSET, u32RegisterValue);
+
+ // enable exception features - DIV0 and align errors
+ u32RegisterValue=0;
+
+ U32_SET_BITS(
+ &u32RegisterValue,
+ /* REG_CONFIGURATION_CONTROL_UNALIGN_TRP_MASK | */REG_CONFIGURATION_CONTROL_DIV_0_TRP_MASK);
+
+ vREG_Write(REG_CONFIGURATION_CONTROL, u32RegisterValue);
+
+ // set the exception priorities here - benign but listed so we know where they are
+ // MemManage
+ vREG_Write8(REG_SYSTEM_HANDLER_PRIORITY_4, 0);
+ // BusFault
+ vREG_Write8(REG_SYSTEM_HANDLER_PRIORITY_5, 0);
+ // UsageFault
+ vREG_Write8(REG_SYSTEM_HANDLER_PRIORITY_6, 0);
+ // SVC
+ vREG_Write8(REG_SYSTEM_HANDLER_PRIORITY_11, 0);
+ // debug monitor
+ vREG_Write8(REG_SYSTEM_HANDLER_PRIORITY_12, 0);
+ // pend SV
+ vREG_Write8(REG_SYSTEM_HANDLER_PRIORITY_14, 0);
+ // SYSTICK
+ vREG_Write8(REG_SYSTEM_HANDLER_PRIORITY_15, MICRO_INTERRUPT_WRITE_PRIORITY_VALUE(MICRO_JENNIC_TO_ARM_PRIORITY_MAP(8)));
+
+ u32RegisterValue=0;
+ U32_SET_BITS(
+ &u32RegisterValue,
+ REG_SYSTEM_HANDLER_CNTRL_STATE_USGFAULTEN_MASK | REG_SYSTEM_HANDLER_CNTRL_STATE_BUSFAULTEN_MASK | REG_SYSTEM_HANDLER_CNTRL_STATE_MEMFAULTEN_MASK);
+ vREG_Write(REG_SYSTEM_HANDLER_CNTRL_STATE, u32RegisterValue);
+
+}
+#endif
+
+#if 0
+/****************************************************************************
+ * NAME: vMicroIntSetGlobalEnable
+ *
+ * DESCRIPTION:
+ * Enable specified interrupts.
+ *
+ * RETURNS:
+ * Nothing.
+ *
+ * NOTES:
+ *
+ ****************************************************************************/
+
+PUBLIC void vMicroIntSetGlobalEnable(
+ uint32 u32EnableMask)
+{
+ // all API's work with the old BA stack numbers, appropriate translations
+ // occur within the call
+ vAHI_InterruptSetPriority(u32EnableMask, 12);
+}
+#endif
+
+/****************************************************************************
+ * NAME: vMicroIntEnableOnly
+ *
+ * DESCRIPTION:
+ * Enable specified interrupt.
+ *
+ * RETURNS:
+ * Nothing.
+ *
+ * NOTES:
+ *
+ ****************************************************************************/
+
+PUBLIC void vMicroIntEnableOnly(
+ tsMicroIntStorage *psIntStorage,
+ uint32 u32EnableMask)
+{
+ uint32 u32Store;
+
+ /* Not used in this implementation */
+ VARIABLE_INTENTIONALLY_NOT_REFERENCED(u32EnableMask)
+
+ /* Disable interrupts for duration of this function */
+#if defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)
+ /* unroll MICRO_DISABLE_AND_SAVE_INTERRUPTS macro content becasue IAR < 8.40 fails to see u32Store is set */
+ u32Store = __get_PRIMASK();
+ __disable_irq();
+#else
+ MICRO_DISABLE_AND_SAVE_INTERRUPTS(u32Store);
+#endif
+ /* Store old priority level */
+ psIntStorage->u8Level = MICRO_GET_ACTIVE_INT_LEVEL();
+
+ /* Update priority level, but only if it is a more restrictive value */
+ MICRO_SET_ACTIVE_INT_LEVEL_MAX(MICRO_INTERRUPT_WRITE_PRIORITY_VALUE(3));
+
+ /* Restore interrupts */
+ MICRO_RESTORE_INTERRUPTS(u32Store);
+}
+
+/****************************************************************************
+ * NAME: vMicroIntRestoreState
+ *
+ * DESCRIPTION:
+ * Restore Previous Interrupt State.
+ *
+ * RETURNS:
+ * Nothing.
+ *
+ * NOTES:
+ *
+ ****************************************************************************/
+
+PUBLIC void vMicroIntRestoreState(
+ tsMicroIntStorage *psIntStorage)
+{
+ // write value direct into register ARM to ARM, no translations required
+ MICRO_SET_ACTIVE_INT_LEVEL(psIntStorage->u8Level);
+}
+
+/****************************************************************************/
+/*** End of file ***/
+/****************************************************************************/
diff --git a/third_party/nxp/K32W061DK6/middleware/wireless/framework/Common/MicroSpecific.h b/third_party/nxp/K32W061DK6/middleware/wireless/framework/Common/MicroSpecific.h
new file mode 100755
index 0000000..ff8a0fb
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/middleware/wireless/framework/Common/MicroSpecific.h
@@ -0,0 +1,52 @@
+/*****************************************************************************
+ *
+ * MODULE: Definitions specific to a particular processor
+ *
+ * DESCRIPTION:
+ * Definitions for a specific processor, i.e. functions that can only be
+ * resolved by op codes
+ *
+ ****************************************************************************
+ *
+ * This software is owned by NXP B.V. and/or its supplier and is protected
+ * under applicable copyright laws. All rights are reserved. We grant You,
+ * and any third parties, a license to use this software solely and
+ * exclusively on NXP products [NXP Microcontrollers such as JN5148, JN5142, JN5139].
+ * You, and any third parties must reproduce the copyright and warranty notice
+ * and any other legend of ownership on each copy or partial copy of the
+ * software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Copyright NXP B.V. 2012. All rights reserved
+ *
+ ***************************************************************************/
+
+/****************************************************************************/
+/*** Include files ***/
+/****************************************************************************/
+
+#define EXPAND1(x) x
+#define EXPAND2(x, y) EXPAND1(x)y
+#define EXPAND3(x, y, z) EXPAND2(x, y)z
+
+/* Convoluted way to #include <MicroSpecific_JN51xx.h> */
+#undef INCLUDE_NAME
+#define INCLUDE_NAME <EXPAND3(MicroSpecific,JENNIC_CHIP_FAMILY_NAME,.h)>
+#include INCLUDE_NAME
+
+/****************************************************************************/
+/*** END OF FILE ***/
+/****************************************************************************/
+
+
diff --git a/third_party/nxp/K32W061DK6/middleware/wireless/framework/Common/MicroSpecific_JN518x.h b/third_party/nxp/K32W061DK6/middleware/wireless/framework/Common/MicroSpecific_JN518x.h
new file mode 100755
index 0000000..596fae7
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/middleware/wireless/framework/Common/MicroSpecific_JN518x.h
@@ -0,0 +1,45 @@
+/*****************************************************************************
+ *
+ * MODULE: Definitions specific to a particular processor
+ *
+ * DESCRIPTION:
+ * Definitions for a specific processor, i.e. functions that can only be
+ * resolved by op codes
+ *
+ ****************************************************************************
+ *
+ * This software is owned by NXP B.V. and/or its supplier and is protected
+ * under applicable copyright laws. All rights are reserved. We grant You,
+ * and any third parties, a license to use this software solely and
+ * exclusively on NXP products [NXP Microcontrollers such as JN5148, JN5142, JN5139].
+ * You, and any third parties must reproduce the copyright and warranty notice
+ * and any other legend of ownership on each copy or partial copy of the
+ * software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Copyright NXP B.V. 2012. All rights reserved
+ *
+ ***************************************************************************/
+
+/****************************************************************************/
+/*** Include files ***/
+/****************************************************************************/
+
+#include "MicroSpecific_arm_sdk2.h"
+
+/****************************************************************************/
+/*** END OF FILE ***/
+/****************************************************************************/
+
+
diff --git a/third_party/nxp/K32W061DK6/middleware/wireless/framework/Common/MicroSpecific_arm_sdk2.h b/third_party/nxp/K32W061DK6/middleware/wireless/framework/Common/MicroSpecific_arm_sdk2.h
new file mode 100755
index 0000000..1639803
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/middleware/wireless/framework/Common/MicroSpecific_arm_sdk2.h
@@ -0,0 +1,389 @@
+/*****************************************************************************
+ *
+ * MODULE: Definitions specific to a particular processor
+ *
+ * DESCRIPTION:
+ * Definitions for a specific processor, i.e. functions that can only be
+ * resolved by op codes
+ *
+ ****************************************************************************
+ *
+ * This software is owned by NXP B.V. and/or its supplier and is protected
+ * under applicable copyright laws. All rights are reserved. We grant You,
+ * and any third parties, a license to use this software solely and
+ * exclusively on NXP products [NXP Microcontrollers such as JN5148, JN5142, JN5139].
+ * You, and any third parties must reproduce the copyright and warranty notice
+ * and any other legend of ownership on each copy or partial copy of the
+ * software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Copyright NXP B.V. 2012, 2019. All rights reserved
+ *
+ ***************************************************************************/
+
+#ifndef MICRO_SPECIFIC_INCLUDED
+#define MICRO_SPECIFIC_INCLUDED
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+/****************************************************************************/
+/*** Include Files ***/
+/****************************************************************************/
+#include <jendefs.h>
+#include "fsl_device_registers.h"
+
+extern void (*isr_handlers[])(void);
+
+/****************************************************************************/
+/*** Macro Definitions ***/
+/****************************************************************************/
+
+/** @{ Defined system call numbers */
+#define SYSCALL_SEMIHOSTING 0xAB
+
+#define SEMIHOSTING_WRITE0 0x04
+#define SEMIHOSTING_READC 0x07
+/** @} */
+
+#define MICRO_INTERRUPT_EXCEPTION_OFFSET 16
+
+// number of bits are defined by the hardware
+#define MICRO_INTERRUPT_NUMBER_OF_PRIORITY_BITS __NVIC_PRIO_BITS
+
+// this macro depends on the setting of the priority group in the NVIC, setting G=3 in this case
+#define MICRO_INTERRUPT_MAX_PRIORITY ((1 << MICRO_INTERRUPT_NUMBER_OF_PRIORITY_BITS) - 1)
+// half way
+#define MICRO_INTERRUPT_MID_PRIORITY (MICRO_INTERRUPT_MAX_PRIORITY/2)
+
+// Priority levels in the arm are higher for lower values - B-Semi chips were the other way around
+#define MICRO_INTERRUPT_ELEVATED_PRIORITY (11)
+#define MICRO_INTERRUPT_MEDIUM_PRIORITY (12)
+
+// priority/sub priority register 8-bits wide
+// read/write priority
+#define MICRO_INTERRUPT_WRITE_PRIORITY_VALUE(W) ((W) << (8 - MICRO_INTERRUPT_NUMBER_OF_PRIORITY_BITS))
+#define MICRO_INTERRUPT_READ_PRIORITY_VALUE(R) ((R) >> (8 - MICRO_INTERRUPT_NUMBER_OF_PRIORITY_BITS))
+// read/write sub-priority
+#define MICRO_INTERRUPT_SUBPRIORITY_MASK ((1 << (8 - MICRO_INTERRUPT_NUMBER_OF_PRIORITY_BITS)) -1)
+#define MICRO_INTERRUPT_SUBPRIORITY_VALUE(S) ((S) & (MICRO_INTERRUPT_SUBPRIORITY_MASK))
+
+
+extern void vAHI_InterruptSetPriority(uint32 u32Mask, uint8 u8Level);
+extern uint8 u8AHI_InterruptGetPriority(uint32 u32InterruptNumber);
+extern void vAHI_InterruptDisable(uint32 u32EnableMask);
+extern void vAHI_TickTimerIntEnable(bool_t bIntEnable);
+extern void vAHI_InterruptSetActivePriorityLevel(uint8 u8Level);
+extern uint8 u8AHI_InterruptReadActivePriorityLevel(void);
+
+#define MICRO_ENABLE_TICK_TIMER_INTERRUPT(); \
+ vAHI_TickTimerIntEnable(TRUE);
+
+// use same value as Jennic/BA devices
+#define MICRO_SET_PIC_ENABLE(A) \
+ vAHI_InterruptSetPriority(A, 8);
+
+#define MICRO_CLEAR_PIC_ENABLE(A) \
+ vAHI_InterruptDisable(A)
+
+#define MICRO_SET_PIC_PRIORITY_LEVEL(A,B) \
+ vAHI_InterruptSetPriority(A, B);
+
+#define MICRO_GET_PIC_PRIORITY_LEVEL(A) \
+ u8AHI_InterruptGetPriority(A);
+
+/* Actual macros are instantiated in the respective CMSIS files */
+#define MICRO_ENABLE_INTERRUPTS() __enable_irq()
+
+#define MICRO_DISABLE_INTERRUPTS() __disable_irq()
+
+#define MICRO_GET_PRIMASK_LEVEL() __get_PRIMASK()
+/* Former implementation : deprecated since CMSIS alternative exists
+ * #define MICRO_GET_PRIMASK_LEVEL() \
+ * ({ \
+ * register uint32 __u32primaskLevelStore; \
+ * asm volatile ("MRS %[primasklevelstore], PRIMASK;" \
+ * :[primasklevelstore] "=r"(__u32primaskLevelStore) \
+ * : \
+ * ); \
+ * __u32primaskLevelStore; \
+ * })
+ */
+#define MICRO_SET_PRIMASK_LEVEL(A) __set_PRIMASK(A)
+/* Former implementation : deprecated since CMSIS alternative exists
+ * #define MICRO_SET_PRIMASK_LEVEL(A) \
+ * ({ \
+ * register uint32 __u32primaskLevelStore = A; \
+ * asm volatile ("MSR PRIMASK, %[primasklevelstore];" \
+ * : \
+ * :[primasklevelstore] "r"(__u32primaskLevelStore) \
+ * ); \
+ * })
+ */
+#define MICRO_GET_ACTIVE_INT_LEVEL() __get_BASEPRI()
+/* Former implementation : deprecated since CMSIS alternative exists
+ * #define MICRO_GET_ACTIVE_INT_LEVEL() \
+ * ({ \
+ * register uint32 __u32interruptActiveLevel; \
+ * asm volatile ("MRS %[activelevelstore], BASEPRI;" \
+ * :[activelevelstore] "=r"(__u32interruptActiveLevel) \
+ * : ); \
+ * __u32interruptActiveLevel; \
+ * })
+ */
+#define MICRO_SET_ACTIVE_INT_LEVEL_MAX(A) __set_BASEPRI_MAX(A)
+/* Former implementation : deprecated since CMSIS alternative exists
+ * #define MICRO_SET_ACTIVE_INT_LEVEL_MAX(A) \
+ * ({ \
+ * register uint32 __u32interruptLevelStore = A; \
+ * asm volatile ("MSR BASEPRI_MAX, %[intlevelstore];" \
+ * : \
+ * :[intlevelstore] "r"(__u32interruptLevelStore) \
+ * ); \
+ * })
+ */
+#define MICRO_SET_ACTIVE_INT_LEVEL(A) __set_BASEPRI(A)
+/* Former implementation : deprecated since CMSIS alternative exists
+ * #define MICRO_SET_ACTIVE_INT_LEVEL(A) \
+ * ({ \
+ * register uint32 __u32interruptLevelStore = A; \
+ * asm volatile ("MSR BASEPRI, %[intlevelstore];" \
+ * : \
+ * :[intlevelstore] "r"(__u32interruptLevelStore) \
+ * ); \
+ * })
+ */
+/* Read back PRIMASK status into u32Store variable then disable
+ * the interrupts */
+#define MICRO_DISABLE_AND_SAVE_INTERRUPTS(u32Store) \
+ ({ \
+ u32Store = __get_PRIMASK(); \
+ __disable_irq(); \
+ })
+/* Former implementation : deprecated since combining CMSIS alternative is
+ * possible.
+ * #define MICRO_DISABLE_AND_SAVE_INTERRUPTS(u32Store) \
+ * ({ \
+ * asm volatile ("MRS %[primasklevelstore], PRIMASK;" \
+ * :[primasklevelstore] "=r"(u32Store) \
+ * : \
+ * ); \
+ * asm volatile ("CPSID I;" : : ); \
+ * })
+ */
+#define MICRO_RESTORE_INTERRUPTS(u32Store) __set_PRIMASK(u32Store)
+/* Former implementation : deprecated since CMSIS equivalent exist.
+ * #define MICRO_RESTORE_INTERRUPTS(u32Store) \
+ * ({ \
+ * asm volatile ("MSR PRIMASK, %[primasklevelstore];" \
+ * : \
+ * :[primasklevelstore] "r"(u32Store) \
+ * ); \
+ * })
+ */
+#define MICRO_GET_EXCEPTION_STACK_FRAME() __get_MSP()
+/* Former implementation : deprecated since CMSIS equivalent exist.
+ * using AAPCS the parameter (the stack frame) wouuld map to r0
+ * #define MICRO_GET_EXCEPTION_STACK_FRAME() \
+ * { \
+ * asm volatile("MRS R0, MSP"); \
+ * }
+ */
+
+#if defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)
+/* Count Trailing Zeroes implementation for IAR :
+ * no builtin implementation for IAR, whereas __CLZ exists */
+static inline uint32_t __ctz(uint32_t x)
+{
+ uint32_t res;
+ x = __RBIT(x);
+ res = __CLZ(x);
+ return res;
+}
+#define _CTZ(x) __ctz(x)
+
+/* Find First Set : returns 0 if no bit set, otherwise returns the order
+ * of LSB bit set + 1
+ * __ffs(0) return 0, __ffs(1) returns 1, __ffs(0x8000000) returns 31
+ */
+static inline uint32_t __ffs(uint32_t x)
+{
+ register uint32 __u32Reg;
+ __u32Reg = _CTZ(x);
+ __u32Reg = __u32Reg == 32 ? 0 : __u32Reg + 1U;
+ return __u32Reg;
+}
+
+#define _FFS(x) __ffs(x)
+#else /* __IAR_SYSTEMS_ICC__ */
+/* GCC builtin */
+#define _CTZ(x) __builtin_ctz(x)
+
+#define _FFS(x) \
+({ register uint32_t __u32Reg, __ret; \
+ __u32Reg = _CTZ(x); \
+ __ret = __u32Reg == 32 ? 0 : __u32Reg + 1U; \
+ __ret; \
+})
+#endif /* __IAR_SYSTEMS_ICC__ */
+
+/* Bit Scan Reverse */
+#define MICRO_BSR(x) (31 - _CLZ(x))
+/* Bit Scan Forward */
+#define MICRO_BSF(x) _CTZ(x)
+
+#define MICRO_FFS(x) _FFS(x)
+
+
+#define FF1(__input) MICRO_FFS(__input)
+
+#define MICRO_GET_LX() __get_LR()
+/* Former implementation : deprecated since CMSIS equivalent exist.
+ * #define MICRO_GET_LX() \
+ * ({ \
+ * register uint32 __u32lxRegister; \
+ * asm volatile ("MOV %[lxRegister], R14;" \
+ * :[lxRegister] "=r"(__u32lxRegister) \
+ * : \
+ * ); \
+ * __u32lxRegister; \
+ * })
+ */
+#define MICRO_GET_STACK_LEVEL() __get_SP()
+/* Former implementation : deprecated since CMSIS equivalent exist.
+ * #define MICRO_GET_STACK_LEVEL() \
+ * ({ \
+ * register uint32 __u32stackRegister; \
+ * asm volatile ("MOV %[stackRegister], SP;" \
+ * :[stackRegister] "=r"(__u32stackRegister) \
+ * : \
+ * ); \
+ * __u32stackRegister; \
+ * })
+ */
+
+#define MICRO_TRAP() __BKPT(0)
+/* Former implementation : deprecated since CMSIS equivalent exist.
+ * #define MICRO_TRAP() asm volatile("BKPT 0;")
+ */
+#define MICRO_NOP() __NOP()
+/* Former implementation : deprecated since CMSIS equivalent exist.
+ * #define MICRO_NOP() asm volatile ("nop;")
+ */
+
+/* macro using privilege/non-privilege model:
+ * u32reg is the register to return the stack pointer that corresponds to
+ * the mode we are in: either MSP or PSP.
+ * Note: this macro has chnaged fir IAR compatibility u32reg is the return
+ * register so that R0 is not implicitly the returned value
+ */
+#define MICRO_GET_EXCEPTION_STACK_FRAME_PNPM(u32reg) \
+ register uint32_t u32reg; \
+ asm volatile("TST LR, #4\n\t" \
+ "ITE EQ\n\t" \
+ "MRSEQ R0, MSP\n\t" \
+ "MRSNE R0, PSP\n\t"); \
+ asm volatile ("MOV %0, R0" : "=r" (u32reg) : /* no input */ );
+
+/* Interrupt Handler registration - only useful if you're putting the handlers
+ * in RAM */
+
+/* Location of isr_handlers is no longer at a known location, but we can link
+ to it directly instead */
+#define MICRO_SET_INT_HANDLER(INT, FUNC); \
+ isr_handlers[(MICRO_INTERRUPT_EXCEPTION_OFFSET + INT)] = (void *)(FUNC);
+
+#define MICRO_GET_INT_HANDLER(INT) \
+ (isr_handlers[(MICRO_INTERRUPT_EXCEPTION_OFFSET + INT)])
+
+/* Nested interrupt control */
+#define MICRO_INT_STORAGE tsMicroIntStorage sIntStorage
+#define MICRO_INT_ENABLE_ONLY(A) vMicroIntEnableOnly(&sIntStorage, A)
+#define MICRO_INT_RESTORE_STATE() vMicroIntRestoreState(&sIntStorage)
+
+/* Exception Handlers */
+#define MICRO_ESR_NUM_RESETISR 1
+#define MICRO_ESR_NUM_NMI 2
+#define MICRO_ESR_NUM_HARDFAULT 3
+#define MICRO_ESR_NUM_MEMMANAGE 4
+#define MICRO_ESR_NUM_BUSFAULT 5
+#define MICRO_ESR_NUM_USGFAULT 6
+// 4 reserved handlers here
+#define MICRO_ESR_NUM_SVCALL 11
+#define MICRO_ESR_NUM_DEBUGMON 12
+// 1 reserved handler here
+#define MICRO_ESR_NUM_PENDSV 14
+#define MICRO_ESR_NUM_SYSTICK 15
+
+/* Location of exception_handlers is no longer at a known location, but we can link
+ to it directly instead - only useful if you're putting the handlers
+ * in RAM */
+#define MICRO_SET_EXCEPTION_HANDLER(EXCEPTION, FUNC) \
+ isr_handlers[EXCEPTION] = (void *)(FUNC);
+
+#define MICRO_GET_EXCEPTION_HANDLER(INT) \
+ (isr_handlers[EXCEPTION])
+
+/* NOP instruction */
+
+
+/* TRAP instruction */
+
+#define MICRO_JUMP_TO_ADDRESS(ADDRESS) \
+ ({ \
+ register uint32 __u32programAddressStore = ADDRESS | 0x1; \
+ asm volatile ("BLX %[programAddressStore];" \
+ : \
+ :[programAddressStore] "r"(__u32programAddressStore)); \
+ })
+
+/****************************************************************************/
+/*** Type Definitions ***/
+/****************************************************************************/
+/* Nested interrupt control */
+typedef struct
+{
+ uint8 u8Level;
+} tsMicroIntStorage;
+
+/****************************************************************************/
+/*** Exported Functions ***/
+/****************************************************************************/
+PUBLIC void vAHI_InitialiseInterruptController(uint32 *pu32InterruptVectorTable);
+
+/* Nested interrupt control */
+PUBLIC void vMicroIntSetGlobalEnable(uint32 u32EnableMask);
+PUBLIC void vMicroIntEnableOnly(tsMicroIntStorage *, uint32 u32EnableMask);
+PUBLIC void vMicroIntRestoreState(tsMicroIntStorage *);
+/* Default Exception Handler */
+PUBLIC void vIntDefaultHandler(void);
+
+PUBLIC void __attribute__((noinline)) vMicroSyscall(volatile uint32 u32SysCallNumber, ...);
+PUBLIC void __attribute__((noinline)) vMicroSemihost(volatile uint32 u32SemihostNumber, ...);
+
+/****************************************************************************/
+/*** Exported Variables ***/
+/****************************************************************************/
+
+#if defined __cplusplus
+}
+#endif
+
+#endif /* MICRO_SPECIFIC_INCLUDED */
+
+/****************************************************************************/
+/*** END OF FILE ***/
+/****************************************************************************/
+
diff --git a/third_party/nxp/JN5189/JennicCommon/Include/jendefs.h b/third_party/nxp/K32W061DK6/middleware/wireless/framework/Common/jendefs.h
similarity index 86%
copy from third_party/nxp/JN5189/JennicCommon/Include/jendefs.h
copy to third_party/nxp/K32W061DK6/middleware/wireless/framework/Common/jendefs.h
index 8b65463..a54189f 100755
--- a/third_party/nxp/JN5189/JennicCommon/Include/jendefs.h
+++ b/third_party/nxp/K32W061DK6/middleware/wireless/framework/Common/jendefs.h
@@ -1,10 +1,35 @@
-/*
-* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
-* Copyright 2016-2019 NXP
-* All rights reserved.
-*
-* SPDX-License-Identifier: BSD-3-Clause
-*/
+/*****************************************************************************
+ *
+ * MODULE: ALL MODULES
+ *
+ * DESCRIPTION: The JENNIC standard header file defining extensions to
+ * ANSI C standard required by the Jennic C coding standard.
+ *
+ ****************************************************************************
+ *
+ * This software is owned by NXP B.V. and/or its supplier and is protected
+ * under applicable copyright laws. All rights are reserved. We grant You,
+ * and any third parties, a license to use this software solely and
+ * exclusively on NXP products [NXP Microcontrollers such as JN5148, JN5142, JN5139].
+ * You, and any third parties must reproduce the copyright and warranty notice
+ * and any other legend of ownership on each copy or partial copy of the
+ * software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Copyright NXP B.V. 2012. All rights reserved
+ *
+ ***************************************************************************/
#ifndef JENDEFS_INCLUDED
#define JENDEFS_INCLUDED
@@ -73,6 +98,9 @@
#define ALWAYS_INLINE
#define INLINE __inline
+
+#elif defined(__IAR_SYSTEMS_ICC__)
+// if compiled for IAR, none of the above defines are required
#else
#error "Unsupported compiler"
#endif
@@ -312,3 +340,5 @@
/****************************************************************************/
/*** END OF FILE ***/
/****************************************************************************/
+
+
diff --git a/third_party/nxp/JN5189/Radio_JN5189/Include/radio.h b/third_party/nxp/K32W061DK6/middleware/wireless/framework/XCVR/DK6/radio.h
similarity index 98%
copy from third_party/nxp/JN5189/Radio_JN5189/Include/radio.h
copy to third_party/nxp/K32W061DK6/middleware/wireless/framework/XCVR/DK6/radio.h
index 71f0638..a081ddb 100755
--- a/third_party/nxp/JN5189/Radio_JN5189/Include/radio.h
+++ b/third_party/nxp/K32W061DK6/middleware/wireless/framework/XCVR/DK6/radio.h
@@ -2,8 +2,7 @@
* @brief Radio driver
*
* @note
- * Copyright(C) NXP Semiconductors, 2014
- * All rights reserved.
+ * Copyright 2019 NXP
*
* @par
* Software that is described herein is for illustrative purposes only
@@ -47,7 +46,7 @@
/****************************************************************************/
/*** Radio driver version (XYYY): X major version, YYY minor version ***/
/****************************************************************************/
-#define RADIO_VERSION (2085)
+#define RADIO_VERSION (2088)
/****************************************************************************/
/*** Radio calibration data record version ***/
@@ -785,6 +784,22 @@
uint8_t u8Radio_AntennaDiversityStatus(void);
+/****************************************************************************
+ *
+ * NAME: vRadio_SetBLEdpTopEmAddr
+ *
+ * DESCRIPTION:
+ * Configure LL_EM_BASE_ADDRESS of BLEMODEM parameter.
+ *
+ * PARAMETERS:
+ * uint32_t em_addr: EM address.
+ *
+ * RETURNS:
+ * None.
+ *
+ ****************************************************************************/
+void vRadio_SetBLEdpTopEmAddr(uint32_t em_addr);
+
#ifdef __cplusplus
}
diff --git a/third_party/nxp/K32W061DK6/middleware/wireless/framework/XCVR/lib/libRadio.a b/third_party/nxp/K32W061DK6/middleware/wireless/framework/XCVR/lib/libRadio.a
new file mode 100755
index 0000000..b4e3ae9
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/middleware/wireless/framework/XCVR/lib/libRadio.a
Binary files differ
diff --git a/third_party/nxp/K32W061DK6/middleware/wireless/ieee-802.15.4/lib/libMiniMac.a b/third_party/nxp/K32W061DK6/middleware/wireless/ieee-802.15.4/lib/libMiniMac.a
new file mode 100755
index 0000000..4c5bd12
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/middleware/wireless/ieee-802.15.4/lib/libMiniMac.a
Binary files differ
diff --git a/third_party/nxp/JN5189/uMac/Include/MMAC.h b/third_party/nxp/K32W061DK6/middleware/wireless/ieee-802.15.4/uMac/Include/MMAC.h
similarity index 92%
copy from third_party/nxp/JN5189/uMac/Include/MMAC.h
copy to third_party/nxp/K32W061DK6/middleware/wireless/ieee-802.15.4/uMac/Include/MMAC.h
index 21b325e..dba5a96 100755
--- a/third_party/nxp/JN5189/uMac/Include/MMAC.h
+++ b/third_party/nxp/K32W061DK6/middleware/wireless/ieee-802.15.4/uMac/Include/MMAC.h
@@ -22,6 +22,7 @@
/****************************************************************************/
/*** Macro/Type Definitions ***/
/****************************************************************************/
+
typedef struct
{
uint32 u32L; /**< Low word */
@@ -147,9 +148,11 @@
/* Flags for transmit status, as returned by u32MMAC_GetTxErrors */
typedef enum
{
- E_MMAC_TXSTAT_CCA_BUSY = 0x01, /* Channel wasn't free */
- E_MMAC_TXSTAT_NO_ACK = 0x02, /* Ack requested but not seen */
- E_MMAC_TXSTAT_ABORTED = 0x04 /* Transmission aborted by user */
+ E_MMAC_TXSTAT_CCA_BUSY = 0x01, /* Channel wasn't free */
+ E_MMAC_TXSTAT_NO_ACK = 0x02, /* Ack requested but not seen */
+ E_MMAC_TXSTAT_ABORTED = 0x04, /* Transmission aborted by user */
+ E_MMAC_TXSTAT_TXTO = 0x20, /* Radio transmission timeout */
+ E_MMAC_TXSTAT_TXPCTO = 0x40 /* Modem transmission timeout */
} teTxStatus;
/* Flags for interrupt status, as returned to handler registered with
@@ -202,6 +205,9 @@
PUBLIC void vMMAC_RxCtlUpdate(uint32 u32NewValue);
PUBLIC void vMMAC_AbortRadio(void);
PUBLIC void vMMAC_SetHighPowerOptions(void);
+PUBLIC void vMMAC_PromiscuousMode(bool_t bPromiscuous);
+PUBLIC void vMMAC_WriteCcaThreshold(uint8 u8CcaThreshold);
+PUBLIC uint8 u8MMAC_ReadCcaThreshold(void);
/* Receive */
PUBLIC void vMMAC_SetRxAddress(uint32 u32PanId, uint16 u16Short,
@@ -212,6 +218,8 @@
PUBLIC void vMMAC_SetRxStartTime(uint32 u32Time);
PUBLIC void vMMAC_StartMacReceive(tsMacFrame *psFrame, teRxOption eOptions);
PUBLIC void vMMAC_StartPhyReceive(tsPhyFrame *psFrame, teRxOption eOptions);
+PUBLIC void vMMAC_SetRxFrame(tsRxFrameFormat *pRxFrame);
+PUBLIC void vMMAC_SetRxProm(uint32_t u32Prom);
PUBLIC bool_t bMMAC_RxDetected(void);
PUBLIC uint32 u32MMAC_GetRxErrors(void);
PUBLIC uint32 u32MMAC_GetRxTime(void);
@@ -224,6 +232,7 @@
PUBLIC void vMMAC_SetCcaMode(teCcaMode eCcaMode);
PUBLIC void vMMAC_StartMacTransmit(tsMacFrame *psFrame, teTxOption eOptions);
PUBLIC void vMMAC_StartPhyTransmit(tsPhyFrame *psFrame, teTxOption eOptions);
+PUBLIC void vMMAC_SetTxPend(bool_t bTxPend);
PUBLIC uint32 u32MMAC_GetTxErrors(void);
PUBLIC bool_t bMMAC_PowerStatus(void);
diff --git a/third_party/nxp/JN5189/app/app_ota.h b/third_party/nxp/K32W061DK6/middleware/wireless/openthread/examples/posix_ota_server/app_ota.h
similarity index 92%
copy from third_party/nxp/JN5189/app/app_ota.h
copy to third_party/nxp/K32W061DK6/middleware/wireless/openthread/examples/posix_ota_server/app_ota.h
index 26e6309..df7d876 100755
--- a/third_party/nxp/JN5189/app/app_ota.h
+++ b/third_party/nxp/K32W061DK6/middleware/wireless/openthread/examples/posix_ota_server/app_ota.h
@@ -1,6 +1,5 @@
/*
-* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
-* Copyright 2016-2017 NXP
+* Copyright 2019-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -71,20 +70,22 @@
/*! Ota status */
typedef enum otaStatus_tag
{
- gOtaStatus_Success_c = 0x00,
- gOtaStatus_Failed_c = 0x01,
- gOtaStatus_InvalidInstance_c = 0x02,
- gOtaStatus_InvalidParam_c = 0x03,
- gOtaStatus_NotPermitted_c = 0x04,
- gOtaStatus_NotStarted_c = 0x05,
- gOtaStatus_NoMem_c = 0x06,
- gOtaStatus_UnsupportedAttr_c = 0x07,
- gOtaStatus_EmptyEntry_c = 0x08,
- gOtaStatus_InvalidValue_c = 0x09,
- gOtaStatus_AlreadyStarted_c = 0x0A,
- gOtaStatus_NoTimers_c = 0x0B,
- gOtaStatus_NoUdpSocket_c = 0x0C,
- gOtaStatus_EntryNotFound_c = 0xFF
+ gOtaStatus_Success_c = 0x00,
+ gOtaStatus_Failed_c = 0x01,
+ gOtaStatus_InvalidInstance_c = 0x02,
+ gOtaStatus_InvalidParam_c = 0x03,
+ gOtaStatus_NotPermitted_c = 0x04,
+ gOtaStatus_NotStarted_c = 0x05,
+ gOtaStatus_NoMem_c = 0x06,
+ gOtaStatus_UnsupportedAttr_c = 0x07,
+ gOtaStatus_EmptyEntry_c = 0x08,
+ gOtaStatus_InvalidValue_c = 0x09,
+ gOtaStatus_AlreadyStarted_c = 0x0A,
+ gOtaStatus_NoTimers_c = 0x0B,
+ gOtaStatus_NoUdpSocket_c = 0x0C,
+ gOtaStatus_FlashError_c = 0x0D,
+ gOtaStatus_TransferTypeNotSupported_c = 0x0E,
+ gOtaStatus_EntryNotFound_c = 0xFF
} otaStatus_t;
/* OTA File Status */
diff --git a/third_party/nxp/JN5189/app/app_ota_server.c b/third_party/nxp/K32W061DK6/middleware/wireless/openthread/examples/posix_ota_server/app_ota_server.c
similarity index 98%
copy from third_party/nxp/JN5189/app/app_ota_server.c
copy to third_party/nxp/K32W061DK6/middleware/wireless/openthread/examples/posix_ota_server/app_ota_server.c
index d9a4475..8c7792a 100755
--- a/third_party/nxp/JN5189/app/app_ota_server.c
+++ b/third_party/nxp/K32W061DK6/middleware/wireless/openthread/examples/posix_ota_server/app_ota_server.c
@@ -1,13 +1,12 @@
/*
-* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
-* Copyright 2016-2017 NXP
+* Copyright 2019-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*!=================================================================================================
-\file app_ota_server.c
+\file app_ota_server.c
\brief This is a public source file for the OTA server module
==================================================================================================*/
@@ -87,6 +86,14 @@
gOtaServerMulticastState_ResetMulticast_c
} otaServerMulticastState_t;
+/* ota server multicast state: */
+typedef enum
+{
+ otaServerClientImageTypeREED = 0x0000,
+ otaServerClientImageTypeED = 0x0001,
+ otaServerClientImageTypeLPED = 0x0002
+} otaServerClientImageType;
+
typedef struct otaServerSetup_tag
{
otInstance *pOtInstance;
@@ -298,22 +305,26 @@
otaStatus_t OtaServer_StartOta(uint8_t otaType, const char *pFilePath)
{
otaServer_ImageNotify_t *pImageNotify = NULL;
+ otaStatus_t status = gOtaStatus_Success_c;
if ((otaType != gOtaUnicast_c) && (otaType != gOtaMulticast_c))
{
- return gOtaStatus_Failed_c;
+ status = gOtaStatus_Failed_c;
+ goto exit;
}
// Check if device is connected before starting OTA
if (otThreadGetDeviceRole(mOtaServerSetup.pOtInstance) < OT_DEVICE_ROLE_CHILD)
{
- return gOtaStatus_NotPermitted_c;
+ status = gOtaStatus_NotPermitted_c;
+ goto exit;
}
// Check if OTA process is already active
if (mOtaServerSetup.isActive == true)
{
- return gOtaStatus_AlreadyStarted_c;
+ status = gOtaStatus_AlreadyStarted_c;
+ goto exit;
}
if (pFilePath != NULL)
@@ -322,12 +333,14 @@
if (!(access(binary_file_path, F_OK) != -1))
{
- return gOtaStatus_InvalidValue_c;
+ status = gOtaStatus_InvalidValue_c;
+ goto exit;
}
}
else
{
- return gOtaStatus_EmptyEntry_c;
+ status = gOtaStatus_EmptyEntry_c;
+ goto exit;
}
// Set multicast addresses used in OTA process
@@ -347,6 +360,16 @@
OtaServer_InitStandaloneOpMode();
+ if (mOtaServerImageList[mOtaServerTempImageIdx].imageType == otaServerClientImageTypeLPED)
+ {
+ if (otaType == gOtaMulticast_c)
+ {
+ mOtaServerSetup.transferType = gOtaUnicast_c;
+ mOtaServerPercentageInformation.otaType = gOtaUnicast_c;
+ status = gOtaStatus_TransferTypeNotSupported_c;
+ }
+ }
+
// OTA Multicast parameters. Not used for OTA unicast.
if (mOtaServerSetup.transferType == gOtaMulticast_c)
{
@@ -361,7 +384,8 @@
OtaServer_SetTimeCallback(OtaServer_MulticastTimeoutCb, (void *)pImageNotify, 100);
}
- return gOtaStatus_Success_c;
+exit:
+ return status;
}
/*!*************************************************************************************************
diff --git a/third_party/nxp/K32W061DK6/middleware/wireless/openthread/examples/posix_ota_server/example_vendor_hook.cpp b/third_party/nxp/K32W061DK6/middleware/wireless/openthread/examples/posix_ota_server/example_vendor_hook.cpp
new file mode 100755
index 0000000..4d62cd0
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/middleware/wireless/openthread/examples/posix_ota_server/example_vendor_hook.cpp
@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2019-2020, The OpenThread Authors.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ * This file shows how to implement the NCP vendor hook.
+ */
+
+#if OPENTHREAD_ENABLE_NCP_VENDOR_HOOK
+
+#include "ncp_base.hpp"
+
+#include "../../third_party/nxp/K32W061DK6/middleware/wireless/openthread/examples/posix_ota_server/app_ota.h"
+namespace ot {
+namespace Ncp {
+
+otError NcpBase::VendorCommandHandler(uint8_t aHeader, unsigned int aCommand)
+{
+ otError error = OT_ERROR_NONE;
+
+ switch (aCommand)
+ {
+
+ // TODO: Implement your command handlers here.
+ case SPINEL_CMD_VENDOR_NXP_OTA_START:
+ uint8_t otaType, start_result;
+ const char * file_path;
+
+ SuccessOrExit(error = mDecoder.ReadUint8(otaType));
+ SuccessOrExit(error = mDecoder.ReadUtf8(file_path));
+
+ //Start OTA process
+ start_result = OtaServer_StartOta(otaType, file_path);
+
+ SuccessOrExit(error = mEncoder.BeginFrame(aHeader, SPINEL_CMD_PROP_VALUE_IS, SPINEL_PROP_NXP_OTA_START_RET));
+ SuccessOrExit(error = mEncoder.WriteUint8(start_result));
+ SuccessOrExit(error = mEncoder.EndFrame());
+
+ break;
+
+ case SPINEL_CMD_VENDOR_NXP_OTA_STOP:
+ //Stop OTA process
+ SuccessOrExit(error = mEncoder.BeginFrame(aHeader, SPINEL_CMD_PROP_VALUE_IS, SPINEL_PROP_NXP_OTA_STOP_RET));
+ SuccessOrExit(error = mEncoder.WriteUint8(OtaServer_StopOta()));
+ SuccessOrExit(error = mEncoder.EndFrame());
+
+ break;
+
+ case SPINEL_CMD_VENDOR_NXP_OTA_STATUS:
+ //Get OTA process status
+ otaServerPercentageInfo_t otaInfo;
+ OtaServer_GetOtaStatus(&otaInfo);
+
+ SuccessOrExit(error = mEncoder.BeginFrame(aHeader, SPINEL_CMD_PROP_VALUE_IS, SPINEL_PROP_NXP_OTA_STATUS_RET));
+ SuccessOrExit(error = mEncoder.WriteData((uint8_t *)&otaInfo, sizeof(otaInfo)));
+ SuccessOrExit(error = mEncoder.EndFrame());
+
+ break;
+
+ default:
+ error = PrepareLastStatusResponse(aHeader, SPINEL_STATUS_INVALID_COMMAND);
+ }
+
+exit:
+
+ return error;
+}
+
+void NcpBase::VendorHandleFrameRemovedFromNcpBuffer(NcpFrameBuffer::FrameTag aFrameTag)
+{
+ // This method is a callback which mirrors `NcpBase::HandleFrameRemovedFromNcpBuffer()`.
+ // It is called when a spinel frame is sent and removed from NCP buffer.
+ //
+ // (a) This can be used to track and verify that a vendor spinel frame response is
+ // delivered to the host (tracking the frame using its tag).
+ //
+ // (b) It indicates that NCP buffer space is now available (since a spinel frame is
+ // removed). This can be used to implement reliability mechanisms to re-send
+ // a failed spinel command response (or an async spinel frame) transmission
+ // (failed earlier due to NCP buffer being full).
+
+ OT_UNUSED_VARIABLE(aFrameTag);
+}
+
+otError NcpBase::VendorGetPropertyHandler(spinel_prop_key_t aPropKey)
+{
+ otError error = OT_ERROR_NONE;
+
+ switch (aPropKey)
+ {
+
+ // TODO: Implement your property get handlers here.
+ //
+ // Get handler should retrieve the property value and then encode and write the
+ // value into the NCP buffer. If the "get" operation itself fails, handler should
+ // write a `LAST_STATUS` with the error status into the NCP buffer. `OT_ERROR_NO_BUFS`
+ // should be returned if NCP buffer is full and response cannot be written.
+
+ default:
+ error = OT_ERROR_NOT_FOUND;
+ break;
+ }
+
+ return error;
+}
+
+otError NcpBase::VendorSetPropertyHandler(spinel_prop_key_t aPropKey)
+{
+ otError error = OT_ERROR_NONE;
+
+ switch (aPropKey)
+ {
+
+ // TODO: Implement your property set handlers here.
+ //
+ // Set handler should first decode the value from the input Spinel frame and then
+ // perform the corresponding set operation. The handler should not prepare the
+ // spinel response and therefore should not write anything to the NCP buffer.
+ // The error returned from handler (other than `OT_ERROR_NOT_FOUND`) indicates the
+ // error in either parsing of the input or the error of the set operation. In case
+ // of a successful "set", `NcpBase` set command handler will invoke the
+ // `VendorGetPropertyHandler()` for the same property key to prepare the response.
+
+ default:
+ error = OT_ERROR_NOT_FOUND;
+ break;
+ }
+
+ return error;
+}
+
+} // namespace Ncp
+} // namespace ot
+
+//-------------------------------------------------------------------------------------------------------------------
+// When OPENTHREAD_ENABLE_NCP_VENDOR_HOOK is enabled, vendor code is
+// expected to provide the `otNcpInit()` function. The reason behind
+// this is to enable vendor code to define its own sub-class of
+// `NcpBase` or `NcpUart`/`NcpSpi`.
+//
+// Example below show how to add a vendor sub-class over `NcpUart`.
+
+#include "ncp_uart.hpp"
+#include "common/new.hpp"
+
+class NcpVendorUart : public ot::Ncp::NcpUart
+{
+public:
+ NcpVendorUart(ot::Instance *aInstance)
+ : ot::Ncp::NcpUart(aInstance)
+ {}
+
+ // Add public/private methods or member variables
+};
+
+static otDEFINE_ALIGNED_VAR(sNcpVendorRaw, sizeof(NcpVendorUart), uint64_t);
+
+extern "C" void otNcpInit(otInstance *aInstance)
+{
+ NcpVendorUart *ncpVendor = NULL;
+ ot::Instance * instance = static_cast<ot::Instance *>(aInstance);
+
+ ncpVendor = new (&sNcpVendorRaw) NcpVendorUart(instance);
+
+ if (ncpVendor == NULL || ncpVendor != ot::Ncp::NcpBase::GetNcpInstance())
+ {
+ assert(false);
+ }
+}
+
+#endif // #if OPENTHREAD_ENABLE_NCP_VENDOR_HOOK
diff --git a/third_party/nxp/JN5189/app/network_utils.c b/third_party/nxp/K32W061DK6/middleware/wireless/openthread/examples/posix_ota_server/network_utils.c
similarity index 98%
copy from third_party/nxp/JN5189/app/network_utils.c
copy to third_party/nxp/K32W061DK6/middleware/wireless/openthread/examples/posix_ota_server/network_utils.c
index 626d2b1..6cd1baf 100755
--- a/third_party/nxp/JN5189/app/network_utils.c
+++ b/third_party/nxp/K32W061DK6/middleware/wireless/openthread/examples/posix_ota_server/network_utils.c
@@ -1,6 +1,5 @@
/*
-* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
-* Copyright 2016-2017 NXP
+* Copyright 2019-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/third_party/nxp/JN5189/app/network_utils.h b/third_party/nxp/K32W061DK6/middleware/wireless/openthread/examples/posix_ota_server/network_utils.h
similarity index 94%
copy from third_party/nxp/JN5189/app/network_utils.h
copy to third_party/nxp/K32W061DK6/middleware/wireless/openthread/examples/posix_ota_server/network_utils.h
index 17c142e..2145c94 100755
--- a/third_party/nxp/JN5189/app/network_utils.h
+++ b/third_party/nxp/K32W061DK6/middleware/wireless/openthread/examples/posix_ota_server/network_utils.h
@@ -1,10 +1,5 @@
-/*! *********************************************************************************
- * \defgroup NUT Thread Network Utilities Interface
- * @{
- ***********************************************************************************/
/*
-* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
-* Copyright 2016-2017 NXP
+* Copyright 2019-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/third_party/nxp/K32W061DK6/middleware/wireless/openthread/examples/posix_ota_server/posix_ota_server_readme.txt b/third_party/nxp/K32W061DK6/middleware/wireless/openthread/examples/posix_ota_server/posix_ota_server_readme.txt
new file mode 100755
index 0000000..8a11ceb
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/middleware/wireless/openthread/examples/posix_ota_server/posix_ota_server_readme.txt
@@ -0,0 +1,64 @@
+This readme is intended to be used as a guideline for building the OpenThread POSIX Border Router application with NXP OTA server support,
+available for JN5189/K32W061(041) OpenThread SDK.
+
+The following steps must be followed:
+1. Clone the OpenThread repository available here: https://github.com/openthread
+
+2. Search for the spinel.h header file and open it. In older releases, the file was located in <ot_root>\src\ncp\, while in newer releases, the file resides in <ot_root>\src\lib\spinel\.
+
+ a. Beneath the line containing "SPINEL_CMD_VENDOR__BEGIN = 15360,", add the following lines:
+"
+ // NXP OTA START COMMAND
+ SPINEL_CMD_VENDOR_NXP_OTA_START = SPINEL_CMD_VENDOR__BEGIN + 1,
+ SPINEL_CMD_VENDOR_NXP_OTA_START_RET = SPINEL_CMD_VENDOR__BEGIN + 2,
+ SPINEL_CMD_VENDOR_NXP_OTA_STOP = SPINEL_CMD_VENDOR__BEGIN + 3,
+ SPINEL_CMD_VENDOR_NXP_OTA_STOP_RET = SPINEL_CMD_VENDOR__BEGIN + 4,
+ SPINEL_CMD_VENDOR_NXP_OTA_STATUS = SPINEL_CMD_VENDOR__BEGIN + 5,
+ SPINEL_CMD_VENDOR_NXP_OTA_STATUS_RET = SPINEL_CMD_VENDOR__BEGIN + 6,
+"
+
+ b. Beneath the line containing "SPINEL_PROP_VENDOR__BEGIN = 0x3C00,", add the following lines:
+"
+ SPINEL_PROP_NXP_OTA_START_RET = SPINEL_PROP_VENDOR__BEGIN + 0,
+ SPINEL_PROP_NXP_OTA_STOP_RET = SPINEL_PROP_VENDOR__BEGIN + 1,
+ SPINEL_PROP_NXP_OTA_STATUS_RET = SPINEL_PROP_VENDOR__BEGIN + 2,
+"
+
+ c. Save and close the file.
+
+3. Open main.c source file from <ot_root>\src\posix\.
+ a. Add the following include at the beginning of the file: #include "app_ota.h"
+ b. Before the "while (true)" loop, add a function call to OtaServerInit, for example "OtaServerInit(instance);".
+ c. At the end of the loop, before the closing brackets, add a function call to OtaServer_CheckTime, for example "OtaServer_CheckTime();".
+ d. Save and close the file.
+
+4. In Makefile.am from <ot_root>\src\posix\, do the following changes:
+ a. Add the following entry to CPPFLAGS_COMMON before $(NULL):
+"-I$(top_srcdir)/third_party/nxp/<sdk_root>/middleware/wireless/openthread/examples/posix_ota_server \"
+
+ b. Add the following entry to ot_ncp_SOURCES before $(NULL):
+"
+@top_builddir@/third_party/nxp/<sdk_root>/middleware/wireless/openthread/examples/posix_ota_server/app_ota_server.c \
+@top_builddir@/third_party/nxp/<sdk_root>/middleware/wireless/openthread/examples/posix_ota_server/network_utils.c \
+"
+
+ c. Add the following entry to ot_cli_SOURCES before $(NULL):
+"
+@top_builddir@/third_party/nxp/<sdk_root>/middleware/wireless/openthread/examples/posix_ota_server/app_ota_server.c \
+@top_builddir@/third_party/nxp/<sdk_root>/middleware/wireless/openthread/examples/posix_ota_server/network_utils.c \
+"
+
+ d. Save and close the file.
+
+5. In Makefile-posix from <ot_root>\src\posix\, do the following changes:
+ a. Add the following entry to configure_OPTIONS before $(NULL):
+"--with-ncp-vendor-hook-source="$(AbsTopSourceDir)/third_party/nxp/<sdk_root>/middleware/wireless/openthread/examples/posix_ota_server/example_vendor_hook.cpp"\"
+
+ b. Add the following line under "# Platform specific switches":
+"COMMONCFLAGS += -DOPENTHREAD_ENABLE_NCP_VENDOR_HOOK=1"
+
+ c. Save and close the file.
+
+6. Run the bootstrap script and follow the rest of the steps to build and run the POSIX application described in <ot_root>\src\posix\README.md.
+
+Note: <sdk_root> needs to be replaced with JN5189DK6 or K32W061DK6.
\ No newline at end of file
diff --git a/third_party/nxp/K32W061DK6/tools/imagetool/dk6_image_tool.py b/third_party/nxp/K32W061DK6/tools/imagetool/dk6_image_tool.py
new file mode 100755
index 0000000..48ea6a2
--- /dev/null
+++ b/third_party/nxp/K32W061DK6/tools/imagetool/dk6_image_tool.py
@@ -0,0 +1,503 @@
+#!python
+
+from collections import namedtuple
+import re
+import argparse
+import subprocess
+import struct
+from Crypto.Signature import pkcs1_15
+from Crypto.PublicKey import RSA
+from Crypto.Hash import SHA256
+from Crypto.Util import number
+import binascii
+import os
+import StringIO
+
+def auto_int(x):
+ return int(x, 0)
+
+parser = argparse.ArgumentParser(description='DK6 Image Header Generator')
+parser.add_argument('in_file', help="Binary to be post-processed: generating header and optionally appending certificate and/or signature.")
+parser.add_argument('out_file', nargs='?')
+parser.add_argument('-g', '--signature_path', help="Sets directory from which certificate and private key are to be retrieved")
+parser.add_argument('-k', '--key', action='store_true', help="2048 bits RSA private key in PEM format used to sign the full image. If -c option is used the full image includes the certificate + the signature of the certificate. The key shall be located in the same directory as the image_tool script. See priv_key.pem example.")
+parser.add_argument('-p', '--password',help="This is the pass phrase from which the encryption key is derived. This parameter is only required if key provided through the -k option is a PEM encrypted key.")
+parser.add_argument('-c', '--certificate', action='store_true', help="When option is selected, the certificate cert.bin is appended to the image.")
+parser.add_argument('-i', '--image_identifier', type=int, help="This parameter is to set the archive identifier. 0: SSBL or legacy JN518x/QN9090 applications, loaded at 0x00000000. 1: application (ZB) loaded at address 0x00004000 by default. 2: application (BLE) image loaded at address 0x00053000 by default")
+parser.add_argument('-a', '--appcore_image', action='store_true',help="This parameter is only relevant if dual application (app1 image) shall reside in flash. Do not use in conjunction with -i option.")
+parser.add_argument('-t', '--target_addr', type=int, help="Target address of image. Used in conjunction with -i option to override the default set by image identifier, or with -a option to specify address of the appcore image (app1 image).")
+parser.add_argument('-s', '--stated_size', type=int, help="This is the stated size of the image in bytes. Default is 0x48000.")
+parser.add_argument('-v', '--version', type=auto_int, default=0, help="Image version. Default is 0.")
+parser.add_argument('-b', '--verbose', type=int, default=0, help="verbosity level. Default is 0.")
+parser.add_argument('-cl', '--compatibility_list', help="Compatibility list")
+parser.add_argument('-sota', '--sota_number_of_blob', type=int, help="This parameter is used to generate the image directory command to be provisioned")
+parser.add_argument('-bid', '--blob_id', type=auto_int, help="This parameter is to add a blob id. Can be used only if the sota arg is given")
+
+
+JN518x_ES1 = 0
+args = parser.parse_args()
+
+elf_file_name = args.in_file
+bin_file_name = elf_file_name.split(".")[0]+'_temp.bin'
+
+if args.out_file is None:
+ args.out_file = elf_file_name
+
+verbose = args.verbose != 0
+
+
+def get_symbol_value(file, symb_name):
+ val = 0
+
+ objdump = subprocess.check_output(['arm-none-eabi-objdump', '--syms', file])
+
+ symb_re = re.compile(r'^([0-9a-f]{8})[\s\S]+[\s]+([0-9a-f]{8})\s([\w\.]+)')
+
+ for ln in StringIO.StringIO(objdump):
+ m = symb_re.match(ln)
+ if m:
+ if m.group(3) == symb_name:
+ val = int(m.group(1), 16)
+ break
+
+ return val
+
+def parse_sections(file):
+ sections = {}
+
+ Section = namedtuple('Section', ['idx', 'name', 'size', 'vma', 'lma', 'offset', 'align', 'flags'])
+
+ objdump = subprocess.check_output(['arm-none-eabi-objdump', '-h', file])
+
+ section_re = re.compile(r'(?P<idx>[0-9]+)\s'
+ r'(?P<name>.{13,})s*'
+ r'(?P<size>[0-9a-f]{8})\s*'
+ r'(?P<vma>[0-9a-f]{8})\s*'
+ r'(?P<lma>[0-9a-f]{8})\s*'
+ r'(?P<offset>[0-9a-f]{8})\s*'
+ r'(?P<align>[0-9*]*)\s*'
+ r'(?P<flags>[[[\w]*[, [\w]*]*)')
+
+ for match in re.finditer(section_re, objdump):
+ sec_dict = match.groupdict()
+
+ sec_dict['idx'] = int(sec_dict['idx'])
+
+ for attr in ['vma', 'lma', 'size', 'offset']:
+ sec_dict[attr] = int(sec_dict[attr], 16)
+
+ sec_dict['align'] = eval(sec_dict['align'])
+
+ sections[sec_dict['name']] = Section(**sec_dict)
+
+ return sections
+
+def reverseString2by2(string, stringLength):
+ result = ""
+ i = stringLength-1
+ while i >=0:
+ result = result + string[i-1]
+ result = result + string[i]
+ i = i-2
+ return result
+
+def print_sota_img_directory_cmd(blobNumber):
+ nbBlobFound = 0
+ sota_final_print = ""
+ sota_final_print += "=================> SOTA information\n"
+ # Generate the image directory command that will be used to provison the device
+ valueToPrint = ".\\DK6Programmer.exe -V5 -s <COM_PORT> -P 1000000 -w PSECT:64@0x160="
+ for i in range(1,9):
+ bootable = "00"
+ if i==1:
+ bootable = "01"
+ position_in_flash = get_symbol_value(elf_file_name, "m_blob_position"+str(i))
+ position_in_flash = '%0*X' % (2,position_in_flash)
+ blobTargetAddr = get_symbol_value(elf_file_name, "m_blob"+str(i)+"_start")
+ blobTargetAddr = '%0*X' % (8,blobTargetAddr)
+ blobStatedSize = get_symbol_value(elf_file_name, "m_blob"+str(i)+"_size")
+ if position_in_flash != "00" and blobStatedSize != 0:
+ nbBlobFound=nbBlobFound+1
+ sota_final_print += "Position in flash = "+ position_in_flash+" - targetAddr = 0x" +blobTargetAddr+ "\n"
+ blobTargetAddr = reverseString2by2(blobTargetAddr, len(blobTargetAddr))
+ blobNbPage = blobStatedSize/512
+ blobNbPage = '%0*X' % (4,blobNbPage)
+ blobNbPage = reverseString2by2(blobNbPage, len(blobNbPage))
+ if blobStatedSize != 0:
+ valueToPrint = valueToPrint + blobTargetAddr + blobNbPage + bootable + position_in_flash
+ else:
+ valueToPrint = valueToPrint + "0000000000000000"
+ sota_final_print += "=====> Image directory command"
+ sota_final_print += valueToPrint
+ sota_final_print += "=================> (end) SOTA information"
+ if nbBlobFound == blobNumber:
+ print sota_final_print
+
+#
+# JN518x ES1 version
+######################
+if JN518x_ES1 == 1: # deprecated
+
+ BOOT_BLOCK_MARKER = 0xBB0110BB
+
+ header_struct = struct.Struct('<7LLLLL')
+ boot_block_struct = struct.Struct('<6LQ')
+
+ sections = parse_sections(args.in_file)
+
+ last_section = None
+
+ for name, section in sections.iteritems():
+ if 'LOAD' in section.flags:
+ if last_section is None or section.lma > last_section.lma:
+ if section.size > 0:
+ last_section = section
+
+ if args.appcore_image is True:
+ image_size = last_section.lma + last_section.size - args.target_appcore_addr
+ else:
+ image_size = last_section.lma + last_section.size
+
+ dump_section = subprocess.check_output(['arm-none-eabi-objcopy', '--dump-section', '%s=data.bin' % last_section.name, args.in_file])
+
+ if args.appcore_image is True:
+ boot_block = boot_block_struct.pack(BOOT_BLOCK_MARKER, 1, args.target_appcore_addr, image_size + boot_block_struct.size, 0, 0, 0)
+ else:
+ boot_block = boot_block_struct.pack(BOOT_BLOCK_MARKER, 0, 0, image_size + boot_block_struct.size, 0, 0, 0)
+
+ with open('data.bin', 'ab') as out_file:
+ out_file.write(boot_block)
+
+ update_section = subprocess.check_output(['arm-none-eabi-objcopy', '--update-section', '%s=data.bin' % last_section.name, args.in_file, args.out_file])
+
+ first_section = None
+
+ for name, section in sections.iteritems():
+ if 'LOAD' in section.flags:
+ if first_section is None or section.lma < first_section.lma:
+ first_section = section
+
+ with open(args.out_file, 'r+b') as elf_file:
+ elf_file.seek(first_section.offset)
+ vectors = elf_file.read(header_struct.size)
+
+ fields = list(header_struct.unpack(vectors))
+
+ vectsum = 0
+
+ for x in range(7):
+ vectsum += fields[x]
+
+ fields[7] = (~vectsum & 0xFFFFFFFF) + 1
+ if args.appcore_image is True:
+ fields[9] = 0x02794498
+ else:
+ fields[9] = 0x98447902
+ #fields[9] = 0x98447902
+ fields[10] = image_size
+
+ print "Writing checksum {:08x} to file {:s}".format(vectsum, args.out_file)
+
+ elf_file.seek(first_section.offset)
+ elf_file.write(header_struct.pack(*fields))
+
+#
+# JN518x ES2 version
+######################
+else:
+ is_signature = False
+ error = 0
+ if args.signature_path is not None:
+ sign_dir_path = os.path.join(os.path.dirname(__file__), args.signature_path)
+ priv_key_file_path = os.path.join(sign_dir_path, 'priv_key.pem')
+ cert_file_path = os.path.join(sign_dir_path, 'cert.bin')
+ else:
+ sign_dir_path = os.path.join(os.path.dirname(__file__), '')
+ priv_key_file_path = os.path.join(sign_dir_path, 'testkey_es2.pem')
+ cert_file_path = os.path.join(sign_dir_path, 'certif_es2')
+
+ if args.key is True:
+ key_file_path = priv_key_file_path
+ if verbose:
+ print "key path is " + key_file_path
+ if (os.path.isfile(key_file_path)):
+ key_file=open(key_file_path, 'r')
+ key = RSA.importKey(key_file.read(), args.password)
+ print "Private RSA key processing..."
+ is_signature = True
+
+ compatibility_struct = struct.Struct('<2L')
+ compatibility_len_struct = struct.Struct('<L')
+ if args.compatibility_list is not None:
+ print "Compatibility list:"
+ if verbose:
+ print " {}".format(args.compatibility_list)
+ compatibility_list = [map(auto_int, compatibility_item.split(",")) for compatibility_item in args.compatibility_list.split(";")]
+ print " Length: {}".format(len(compatibility_list))
+ for i in range(len(compatibility_list)):
+ item = compatibility_list[i]
+ for j in range(len(item)):
+ if j ==1:
+ blobIdCompatibilityList = " Blob ID 0x=" + '%0*X' % (8,item[j-1])
+ print "Blob ID =0x"+'%0*X' % (4,item[j-1]) +" - version =0x"+'%0*X' % (8,item[j])
+ compatibility_len = len(compatibility_list) * compatibility_struct.size + compatibility_len_struct.size
+ if verbose:
+ print " {}".format(compatibility_len)
+ else:
+ compatibility_list = []
+ compatibility_len = 0
+ print "No compatibility list"
+
+ # make sure that the compatibility list is added and equals to nb_blob - 1
+ if args.sota_number_of_blob is not None and (compatibility_len/compatibility_struct.size) != args.sota_number_of_blob-1:
+ print "!!! Error the compatibility list length must be = to the number of blobs -1 : "+str(compatibility_len/compatibility_struct.size)+"(len) != "+ str(args.sota_number_of_blob-1)
+ error = 1
+ #make sure that the blob ID is given
+ if args.sota_number_of_blob is not None and args.blob_id is None:
+ print "!!! Error the blob ID is missing"
+ error = 1
+
+ bin_output = subprocess.check_output(['arm-none-eabi-objcopy', '-O', 'binary', elf_file_name, bin_file_name])
+
+ with open(bin_file_name, 'rb') as in_file:
+ input_file = in_file.read()
+
+ BOOT_BLOCK_MARKER = 0xBB0110BB
+ IMAGE_HEADER_MARKER = 0x98447902
+ IMAGE_HEADER_APP_CORE = 0x02794498
+ IMAGE_HEADER_ESCORE = IMAGE_HEADER_MARKER
+ SSBL_OR_LEGACY_ADDRESS = 0x00000000
+ SSBL_STATED_SIZE = 0x2000
+ ZB_TARGET_ADDRESS = SSBL_STATED_SIZE * 2
+ ZB_STATED_SIZE = 0x4f000
+ BLE_TARGET_ADDRESS = ZB_TARGET_ADDRESS + ZB_STATED_SIZE
+ BLE_STATED_SIZE = 0x40000
+
+ header_struct = struct.Struct('<7LLLLL')
+ boot_block_struct = struct.Struct('<8L')
+
+ boot_block_marker = BOOT_BLOCK_MARKER
+ if args.image_identifier is not None:
+ image_iden = args.image_identifier
+ else:
+ image_iden = 0
+
+ if verbose:
+ print "Image Identifier is {:d}".format(image_iden)
+
+ #Default value initialization
+ image_addr = 0
+ stated_size = 0
+
+ #Default value for SSBL, ZigbeeFull and BleFull image id
+ if image_iden == 0:
+ image_addr = SSBL_OR_LEGACY_ADDRESS
+ stated_size = SSBL_STATED_SIZE
+ elif image_iden == 1:
+ image_addr = ZB_TARGET_ADDRESS
+ elif image_iden == 2:
+ image_addr = BLE_TARGET_ADDRESS
+
+ image_addr = get_symbol_value(elf_file_name, 'm_app_start')
+
+ stated_size = get_symbol_value(elf_file_name, 'm_app_size')
+
+ # In case of SOTA get the position in flash from the linker it should be the app_id
+ if args.sota_number_of_blob is not None:
+ if args.image_identifier is None:
+ image_iden = get_symbol_value(elf_file_name, '__blob_position__')
+ print "Blob position in flash = #"+str(image_iden)
+
+ img_header_marker = IMAGE_HEADER_MARKER + image_iden
+
+ # Overwrite defaults for image address, stated size and header marker (-t, -s, -a options)
+ if args.target_addr is not None:
+ image_addr = args.target_addr
+ if args.stated_size is not None:
+ stated_size = args.stated_size
+ if args.appcore_image is True:
+ img_header_marker = IMAGE_HEADER_APP_CORE
+
+ if verbose:
+ print "image_iden=%d image_addr=%x" % (image_iden, image_addr)
+ print "stated_size=%d" % (stated_size)
+ print "version=0x%0*X" % (8,args.version)
+ print "boot_block_marker=%x" % (boot_block_marker)
+
+ sections = parse_sections(elf_file_name)
+
+ last_section = None
+ for name, section in sections.iteritems():
+ if 'LOAD' in section.flags:
+ if last_section is None or section.lma > last_section.lma:
+ if section.size > 0:
+ last_section = section
+
+ # IAR toolchain uses odd section names that contain spaces
+ # the regexp now may now return trailing spaces too, need to strip them
+ last_section_name = last_section.name.rstrip()
+ # and add quotes around the section name
+ last_section_name = r"%s" % (last_section_name)
+
+ boot_block_offset = last_section.lma + last_section.size + compatibility_len - image_addr
+
+ # Correction for image size not being multiple of 4 (IAR)
+ padding_len = ((4 - (boot_block_offset%4)) & 3)
+ padding_bytes = bytearray(padding_len)
+ boot_block_offset = boot_block_offset + padding_len
+
+ print "boot block offset =%x" % (boot_block_offset)
+ if verbose:
+ print "Last Section LMA={:08x} Size={:08x}".format(last_section.lma, last_section.size)
+ print "ImageAddress={:08x}".format(image_addr)
+
+ first_section = None
+
+ for name, section in sections.iteritems():
+ # print "Section: {:s} {:s} {:x} {:x}".format(name, section.flags, section.lma, section.size)
+ if 'LOAD' in section.flags:
+ if first_section is None or section.lma < first_section.lma:
+ first_section = section
+
+ header=""
+ with open(args.out_file, 'r+b') as elf_file:
+ elf_file.seek(first_section.offset)
+ vectors = elf_file.read(header_struct.size)
+
+ fields = list(header_struct.unpack(vectors))
+
+ vectsum = 0
+ for x in range(7):
+ vectsum += fields[x]
+
+ fields[7] = (~vectsum & 0xFFFFFFFF) + 1
+ fields[8] = img_header_marker
+ fields[9] = boot_block_offset
+
+ #Compute crc
+ head_struct = struct.Struct('<10L')
+ try:
+ if verbose:
+ for i in range(10):
+ print "Header[{:d}]= {:08x}".format(i, fields[i])
+ values = head_struct.pack(fields[0],
+ fields[1],
+ fields[2],
+ fields[3],
+ fields[4],
+ fields[5],
+ fields[6],
+ fields[7],
+ fields[8],
+ fields[9])
+ fields[10] = binascii.crc32(values) & 0xFFFFFFFF
+ except:
+ error = 1
+
+ print "Writing checksum {:08x} to file {:s}".format(vectsum, args.out_file)
+ print "Writing CRC32 of header {:08x} to file {:s}".format(fields[10], args.out_file)
+
+
+ elf_file.seek(first_section.offset)
+ header = header_struct.pack(*fields);
+ elf_file.write(header)
+
+ dump_section = subprocess.check_output(['arm-none-eabi-objcopy',
+ '--dump-section',
+ '%s=data.bin' % last_section_name,
+ args.out_file])
+
+ certificate = ""
+ certificate_offset = 0
+ signature = ""
+ compatibility = ""
+ compatibility_offset = 0
+
+ if args.compatibility_list is not None:
+ compatibility_offset = last_section.lma + last_section.size - image_addr
+ compatibility = compatibility_len_struct.pack(len(compatibility_list)) + ''.join([compatibility_struct.pack(*compatibility_item) for compatibility_item in compatibility_list])
+ print "Compatibility processing..."
+
+ if (args.certificate is True):
+ certificate_offset = boot_block_offset + boot_block_struct.size
+ certif_file_path = cert_file_path
+ if verbose:
+ print "Cert key path is " + cert_file_path
+ if (os.path.isfile(certif_file_path)):
+ certif_file=open(certif_file_path, 'rb')
+ certificate = certif_file.read()
+
+ print "Certificate processing..."
+ if len(certificate) != (40+256+256):
+ print "Certificate error"
+ error = 1
+
+ if verbose:
+ print "stated size is {:08x} ({})".format(stated_size,stated_size)
+
+ if args.appcore_image is True:
+ boot_block_id = 1
+ else:
+ boot_block_id = 0
+
+ if args.blob_id is not None:
+ boot_block_id = args.blob_id
+
+ boot_block = boot_block_struct.pack(boot_block_marker,
+ boot_block_id,
+ image_addr,
+ boot_block_offset + boot_block_struct.size + len(certificate), # padding already included in the boot_block_offset
+ stated_size,
+ certificate_offset,
+ compatibility_offset,
+ args.version)
+
+ if (is_signature == True):
+ # Sign the complete image
+ message = header + input_file[header_struct.size:] + boot_block + certificate
+ hash = SHA256.new(message)
+
+ out_file_path = os.path.join(os.path.dirname(__file__), 'dump_python.bin')
+ file_out=open(out_file_path, 'wb')
+ file_out.write(message)
+
+ signer = pkcs1_15.new(key)
+ signature = signer.sign(hash)
+
+ print "Signature processing..."
+
+ with open('data.bin', 'ab') as out_file:
+ out_file.write(compatibility+padding_bytes+boot_block+certificate+signature)
+ if verbose:
+ print "Updating last section " + last_section.name
+
+ update_section = subprocess.check_output(['arm-none-eabi-objcopy',
+ '--update-section',
+ '%s=data.bin' % last_section_name,
+ elf_file_name,
+ args.out_file])
+
+
+ if (is_signature == True):
+ file_out.close()
+
+ bin_output = subprocess.check_output(['arm-none-eabi-objcopy',
+ '-O',
+ 'binary',
+ elf_file_name,
+ bin_file_name])
+
+ print "Binary size is {:08x} ({})".format(os.stat(bin_file_name).st_size,os.stat(bin_file_name).st_size)
+
+ if args.sota_number_of_blob is not None:
+ print_sota_img_directory_cmd(args.sota_number_of_blob)
+
+ if os.stat(bin_file_name).st_size > stated_size:
+ print "Error: Binary file size ({:08x}) must be less or equal to stated size {:08x}".format(os.stat(bin_file_name).st_size, stated_size)
+ error = 1
+
+ if error != 0:
+ os.remove(elf_file_name)
+ os.remove(out_file_path)
+
+ os.remove(bin_file_name)
diff --git a/third_party/nxp/JN5189/ImageSigning/sign_images.sh b/third_party/nxp/K32W061DK6/tools/imagetool/sign_images.sh
similarity index 96%
copy from third_party/nxp/JN5189/ImageSigning/sign_images.sh
copy to third_party/nxp/K32W061DK6/tools/imagetool/sign_images.sh
index 065e19e..5e0105a 100755
--- a/third_party/nxp/JN5189/ImageSigning/sign_images.sh
+++ b/third_party/nxp/K32W061DK6/tools/imagetool/sign_images.sh
@@ -40,7 +40,7 @@
is_python_package_installed "pycryptodome"
CURR_DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )"
-SIGNING_TOOL=$CURR_DIR/jn518x_image_tool.py
+SIGNING_TOOL=$CURR_DIR/dk6_image_tool.py
MIME_PATTERN="application/x-executable"
if [ "$#" -eq 1 ]; then