commit f46efacd01c8f503b239dd16122ec6de5a684877
author Marek Olšák <marek.olsak@amd.com> Wed Jun 19 22:24:51 2019 -0400
committer Marek Olšák <marek.olsak@amd.com> Mon Jun 24 21:04:10 2019 -0400
tree ff25b6cf0210ece1fb41cc7974ea0bd4340d7043
parent ac4b1e2f0aa987b075be0bac3b4a9e69b5ec4d07

radeonsi: flatten the switch for DPBB tunables

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>

src/gallium/drivers/radeonsi/si_state_binning.c

diff --git a/src/gallium/drivers/radeonsi/si_state_binning.c b/src/gallium/drivers/radeonsi/si_state_binning.c
index 6285ccc..a6b1830 100644
--- a/src/gallium/drivers/radeonsi/si_state_binning.c
+++ b/src/gallium/drivers/radeonsi/si_state_binning.c
@@ -402,20 +402,10 @@
 	unsigned persistent_states_per_bin; /* allowed range: [0, 31] */
 	unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
 
-	switch (sctx->family) {
-	case CHIP_VEGA10:
-	case CHIP_VEGA12:
-	case CHIP_VEGA20:
-	case CHIP_RAVEN:
-	case CHIP_RAVEN2:
-		/* Tuned for Raven. Vega might need different values. */
-		context_states_per_bin = 5;
-		persistent_states_per_bin = 31;
-		fpovs_per_batch = 63;
-		break;
-	default:
-		assert(0);
-	}
+	/* Tuned for Raven. Vega might need different values. */
+	context_states_per_bin = 5;
+	persistent_states_per_bin = 31;
+	fpovs_per_batch = 63;
 
 	/* Emit registers. */
 	struct uvec2 bin_size_extend = {};