anv,radv,tu,val: Call nir_lower_io for push constants
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5275>
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index e2f8d56..88a5041 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -653,6 +653,9 @@
*/
nir_lower_var_copies(nir);
+ NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_push_const,
+ nir_address_format_32bit_offset);
+
NIR_PASS_V(nir, nir_lower_explicit_io,
nir_var_mem_ubo | nir_var_mem_ssbo,
nir_address_format_32bit_index_offset);
diff --git a/src/freedreno/vulkan/tu_shader.c b/src/freedreno/vulkan/tu_shader.c
index 9d4fe21..218a206 100644
--- a/src/freedreno/vulkan/tu_shader.c
+++ b/src/freedreno/vulkan/tu_shader.c
@@ -765,6 +765,9 @@
&shader->multi_pos_output, dev);
}
+ NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_push_const,
+ nir_address_format_32bit_offset);
+
NIR_PASS_V(nir, nir_lower_explicit_io,
nir_var_mem_ubo | nir_var_mem_ssbo,
nir_address_format_vec2_index_32bit_offset);
diff --git a/src/gallium/frontends/vallium/val_pipeline.c b/src/gallium/frontends/vallium/val_pipeline.c
index a1d8390..d884ed5 100644
--- a/src/gallium/frontends/vallium/val_pipeline.c
+++ b/src/gallium/frontends/vallium/val_pipeline.c
@@ -573,6 +573,9 @@
NIR_PASS_V(nir, nir_split_var_copies);
NIR_PASS_V(nir, nir_lower_global_vars_to_local);
+ NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_push_const,
+ nir_address_format_32bit_offset);
+
if (nir->info.stage == MESA_SHADER_COMPUTE) {
NIR_PASS_V(nir, nir_lower_vars_to_explicit_types, nir_var_mem_shared, shared_var_info);
NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_shared, nir_address_format_32bit_offset);
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index a161377..36da2cc 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -765,6 +765,8 @@
NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_global,
nir_address_format_64bit_global);
+ NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_push_const,
+ nir_address_format_32bit_offset);
/* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
anv_nir_apply_pipeline_layout(pdevice,
