| Reading src/freedreno/.gitlab-ci/traces/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.rd.gz... |
| gpu_id: 640 |
| cmd: deqp-vk/74711: fence=247337 |
| ############################################################ |
| cmdstream: 265 dwords |
| t7 opcode: CP_EVENT_WRITE (46) (2 dwords) |
| { EVENT = CACHE_INVALIDATE } |
| event CACHE_INVALIDATE |
| 0000000001058000: 0000: 70460001 00000031 |
| t4 write HLSQ_INVALIDATE_CMD (bb08) |
| HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_SHARED_CONST | GFX_SHARED_CONST | CS_BINDLESS = 0x1f | GFX_BINDLESS = 0x1f } |
| 0000000001058008: 0000: 40bb0801 000fffff |
| t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) |
| 0000000001058010: 0000: 70268000 |
| t4 write RB_CCU_CNTL (8e07) |
| RB_CCU_CNTL: { OFFSET = 0x20000 } |
| 0000000001058014: 0000: 408e0701 10000000 |
| t4 write RB_UNKNOWN_8E04 (8e04) |
| RB_UNKNOWN_8E04: 0x100000 |
| 000000000105801c: 0000: 408e0401 00100000 |
| t4 write SP_UNKNOWN_AE04 (ae04) |
| SP_UNKNOWN_AE04: 0x8 |
| 0000000001058024: 0000: 48ae0401 00000008 |
| t4 write SP_UNKNOWN_AE00 (ae00) |
| SP_UNKNOWN_AE00: 0 |
| 000000000105802c: 0000: 40ae0001 00000000 |
| t4 write SP_UNKNOWN_AE0F (ae0f) |
| SP_UNKNOWN_AE0F: 0x3f |
| 0000000001058034: 0000: 40ae0f01 0000003f |
| t4 write SP_UNKNOWN_B605 (b605) |
| SP_UNKNOWN_B605: 0x44 |
| 000000000105803c: 0000: 40b60501 00000044 |
| t4 write SP_UNKNOWN_B600 (b600) |
| SP_UNKNOWN_B600: 0x100000 |
| 0000000001058044: 0000: 40b60001 00100000 |
| t4 write HLSQ_UNKNOWN_BE00 (be00) |
| HLSQ_UNKNOWN_BE00: 0x80 |
| 000000000105804c: 0000: 48be0001 00000080 |
| t4 write HLSQ_UNKNOWN_BE01 (be01) |
| HLSQ_UNKNOWN_BE01: 0 |
| 0000000001058054: 0000: 40be0101 00000000 |
| t4 write VPC_UNKNOWN_9600 (9600) |
| VPC_UNKNOWN_9600: 0 |
| 000000000105805c: 0000: 48960001 00000000 |
| t4 write GRAS_UNKNOWN_8600 (8600) |
| GRAS_UNKNOWN_8600: 0x880 |
| 0000000001058064: 0000: 40860001 00000880 |
| t4 write HLSQ_UNKNOWN_BE04 (be04) |
| HLSQ_UNKNOWN_BE04: 0 |
| 000000000105806c: 0000: 40be0401 00000000 |
| t4 write SP_UNKNOWN_AE03 (ae03) |
| SP_UNKNOWN_AE03: 0x410 |
| 0000000001058074: 0000: 40ae0301 00000410 |
| t4 write SP_IBO_COUNT (ab20) |
| SP_IBO_COUNT: 0 |
| 000000000105807c: 0000: 48ab2001 00000000 |
| t4 write SP_UNKNOWN_B182 (b182) |
| SP_UNKNOWN_B182: 0 |
| 0000000001058084: 0000: 48b18201 00000000 |
| t4 write HLSQ_SHARED_CONSTS (bb11) |
| HLSQ_SHARED_CONSTS: { 0 } |
| 000000000105808c: 0000: 48bb1101 00000000 |
| t4 write UCHE_UNKNOWN_0E12 (0e12) |
| UCHE_UNKNOWN_0E12: 0x3200000 |
| 0000000001058094: 0000: 400e1201 03200000 |
| t4 write UCHE_CLIENT_PF (0e19) |
| UCHE_CLIENT_PF: { PERFSEL = 0x4 } |
| 000000000105809c: 0000: 480e1901 00000004 |
| t4 write RB_UNKNOWN_8E01 (8e01) |
| RB_UNKNOWN_8E01: 0 |
| 00000000010580a4: 0000: 408e0101 00000000 |
| t4 write SP_UNKNOWN_A982 (a982) |
| SP_UNKNOWN_A982: 0 |
| 00000000010580ac: 0000: 48a98201 00000000 |
| t4 write SP_UNKNOWN_A9A8 (a9a8) |
| SP_UNKNOWN_A9A8: 0 |
| 00000000010580b4: 0000: 40a9a801 00000000 |
| t4 write SP_MODE_CONTROL (ab00) |
| SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | 0x4 } |
| 00000000010580bc: 0000: 40ab0001 00000005 |
| t4 write VFD_ADD_OFFSET (a009) |
| VFD_ADD_OFFSET: { VERTEX } |
| 00000000010580c4: 0000: 48a00901 00000001 |
| t4 write RB_UNKNOWN_8811 (8811) |
| RB_UNKNOWN_8811: 0x1 |
| 00000000010580cc: 0000: 48881101 00000010 |
| t4 write PC_MODE_CNTL (9804) |
| PC_MODE_CNTL: 0x1f |
| 00000000010580d4: 0000: 48980401 0000001f |
| t4 write RB_SRGB_CNTL (880f) |
| RB_SRGB_CNTL: { 0 } |
| 00000000010580dc: 0000: 48880f01 00000000 |
| t4 write GRAS_UNKNOWN_8110 (8110) |
| GRAS_UNKNOWN_8110: 0 |
| 00000000010580e4: 0000: 40811001 00000000 |
| t4 write RB_RENDER_CONTROL0 (8809) |
| RB_RENDER_CONTROL0: { IJ_PERSP_PIXEL | COORD_MASK = 0 | UNK10 } |
| 00000000010580ec: 0000: 48880901 00000401 |
| t4 write RB_RENDER_CONTROL1 (880a) |
| RB_RENDER_CONTROL1: { 0 } |
| 00000000010580f4: 0000: 48880a01 00000000 |
| t4 write RB_FS_OUTPUT_CNTL0 (880b) |
| RB_FS_OUTPUT_CNTL0: { 0 } |
| 00000000010580fc: 0000: 40880b01 00000000 |
| t4 write RB_UNKNOWN_8818 (8818) |
| RB_UNKNOWN_8818: 0 |
| 0000000001058104: 0000: 48881801 00000000 |
| t4 write RB_UNKNOWN_8819 (8819) |
| RB_UNKNOWN_8819: 0 |
| 000000000105810c: 0000: 40881901 00000000 |
| t4 write RB_UNKNOWN_881A (881a) |
| RB_UNKNOWN_881A: 0 |
| 0000000001058114: 0000: 40881a01 00000000 |
| t4 write RB_UNKNOWN_881B (881b) |
| RB_UNKNOWN_881B: 0 |
| 000000000105811c: 0000: 48881b01 00000000 |
| t4 write RB_UNKNOWN_881C (881c) |
| RB_UNKNOWN_881C: 0 |
| 0000000001058124: 0000: 40881c01 00000000 |
| t4 write RB_UNKNOWN_881D (881d) |
| RB_UNKNOWN_881D: 0 |
| 000000000105812c: 0000: 48881d01 00000000 |
| t4 write RB_UNKNOWN_881E (881e) |
| RB_UNKNOWN_881E: 0 |
| 0000000001058134: 0000: 48881e01 00000000 |
| t4 write RB_UNKNOWN_88F0 (88f0) |
| RB_UNKNOWN_88F0: 0 |
| 000000000105813c: 0000: 4888f001 00000000 |
| t4 write VPC_UNKNOWN_9107 (9107) |
| VPC_UNKNOWN_9107: 0 |
| 0000000001058144: 0000: 48910701 00000000 |
| t4 write VPC_POINT_COORD_INVERT (9236) |
| VPC_POINT_COORD_INVERT: { 0 } |
| 000000000105814c: 0000: 40923601 00000000 |
| t4 write VPC_UNKNOWN_9300 (9300) |
| VPC_UNKNOWN_9300: 0 |
| 0000000001058154: 0000: 48930001 00000000 |
| t4 write VPC_SO_DISABLE (9306) |
| VPC_SO_DISABLE: { DISABLE } |
| 000000000105815c: 0000: 48930601 00000001 |
| t4 write PC_UNKNOWN_9980 (9980) |
| PC_UNKNOWN_9980: 0 |
| 0000000001058164: 0000: 40998001 00000000 |
| t4 write PC_PRIMITIVE_CNTL_6 (9b06) |
| PC_PRIMITIVE_CNTL_6: { STRIDE_IN_VPC = 0 } |
| 000000000105816c: 0000: 409b0601 00000000 |
| t4 write PC_UNKNOWN_9B07 (9b07) |
| PC_UNKNOWN_9B07: 0 |
| 0000000001058174: 0000: 489b0701 00000000 |
| t4 write SP_UNKNOWN_A81B (a81b) |
| SP_UNKNOWN_A81B: 0 |
| 000000000105817c: 0000: 40a81b01 00000000 |
| t4 write SP_UNKNOWN_B183 (b183) |
| SP_UNKNOWN_B183: 0 |
| 0000000001058184: 0000: 40b18301 00000000 |
| t4 write GRAS_UNKNOWN_8099 (8099) |
| GRAS_UNKNOWN_8099: 0 |
| 000000000105818c: 0000: 40809901 00000000 |
| t4 write GRAS_UNKNOWN_80A0 (80a0) |
| GRAS_UNKNOWN_80A0: 0x2 |
| 0000000001058194: 0000: 4080a001 00000002 |
| t4 write GRAS_UNKNOWN_80AF (80af) |
| GRAS_UNKNOWN_80AF: FALSE |
| 000000000105819c: 0000: 4080af01 00000000 |
| t4 write VPC_UNKNOWN_9210 (9210) |
| VPC_UNKNOWN_9210: 0 |
| 00000000010581a4: 0000: 48921001 00000000 |
| t4 write VPC_UNKNOWN_9211 (9211) |
| VPC_UNKNOWN_9211: 0 |
| 00000000010581ac: 0000: 40921101 00000000 |
| t4 write VPC_UNKNOWN_9602 (9602) |
| VPC_UNKNOWN_9602: FALSE |
| 00000000010581b4: 0000: 40960201 00000000 |
| t4 write PC_UNKNOWN_9E72 (9e72) |
| PC_UNKNOWN_9E72: 0 |
| 00000000010581bc: 0000: 409e7201 00000000 |
| t4 write SP_TP_UNKNOWN_B309 (b309) |
| SP_TP_UNKNOWN_B309: 0xa2 |
| 00000000010581c4: 0000: 40b30901 000000a2 |
| t4 write HLSQ_CONTROL_5_REG (b986) |
| HLSQ_CONTROL_5_REG: 0xfc |
| 00000000010581cc: 0000: 48b98601 000000fc |
| t4 write VFD_MODE_CNTL (a007) |
| VFD_MODE_CNTL: { 0 } |
| 00000000010581d4: 0000: 40a00701 00000000 |
| t4 write VFD_UNKNOWN_A008 (a008) |
| VFD_UNKNOWN_A008: 0 |
| 00000000010581dc: 0000: 40a00801 00000000 |
| t4 write PC_MODE_CNTL (9804) |
| PC_MODE_CNTL: 0x1f |
| 00000000010581e4: 0000: 48980401 0000001f |
| t7 opcode: CP_SET_DRAW_STATE (43) (4 dwords) |
| { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } |
| { ADDR_LO = 0 } |
| { ADDR_HI = 0 } |
| 00000000010581ec: 0000: 70438003 00040000 00000000 00000000 |
| t4 write SP_HS_CTRL_REG0 (a830) |
| SP_HS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = TWO_QUADS } |
| 00000000010581fc: 0000: 40a83001 00000000 |
| t4 write SP_GS_CTRL_REG0 (a870) |
| SP_GS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = TWO_QUADS } |
| 0000000001058204: 0000: 48a87001 00000000 |
| t4 write GRAS_LRZ_CNTL (8100) |
| GRAS_LRZ_CNTL: { 0 } |
| 000000000105820c: 0000: 48810001 00000000 |
| t4 write RB_LRZ_CNTL (8898) |
| RB_LRZ_CNTL: { 0 } |
| 0000000001058214: 0000: 40889801 00000000 |
| t4 write SP_TP_BORDER_COLOR_BASE_ADDR (b302) |
| SP_TP_BORDER_COLOR_BASE_ADDR: 0x1011000 |
| SP_TP_BORDER_COLOR_BASE_ADDR+0x1: 0 |
| 000000000105821c: 0000: 48b30202 01011000 00000000 |
| t4 write SP_PS_TP_BORDER_COLOR_BASE_ADDR (b180) |
| SP_PS_TP_BORDER_COLOR_BASE_ADDR: 0x1011000 |
| SP_PS_TP_BORDER_COLOR_BASE_ADDR+0x1: 0 |
| 0000000001058228: 0000: 40b18002 01011000 00000000 |
| t4 write VSC_DRAW_STRM_SIZE_ADDRESS_LO (0c03) |
| VSC_DRAW_STRM_SIZE_ADDRESS_LO: 0x10fd000 |
| VSC_DRAW_STRM_SIZE_ADDRESS_HI: 0 |
| 0000000001058234: 0000: 480c0302 010fd000 00000000 |
| t4 write VSC_PRIM_STRM_ADDRESS_LO (0c30) |
| VSC_PRIM_STRM_ADDRESS_LO: 0x105c000 |
| VSC_PRIM_STRM_ADDRESS_HI: 0 |
| 0000000001058240: 0000: 480c3002 0105c000 00000000 |
| t4 write VSC_DRAW_STRM_ADDRESS_LO (0c34) |
| VSC_DRAW_STRM_ADDRESS_LO: 0x10dc800 |
| VSC_DRAW_STRM_ADDRESS_HI: 0 |
| 000000000105824c: 0000: 400c3402 010dc800 00000000 |
| t7 opcode: CP_EVENT_WRITE (46) (5 dwords) |
| { EVENT = PC_CCU_FLUSH_COLOR_TS } |
| { ADDR_0_LO = 0x1011880 } |
| { ADDR_0_HI = 0 } |
| { 3 = 0 } |
| event PC_CCU_FLUSH_COLOR_TS |
| 0000000001058258: 0000: 70460004 0000001d 01011880 00000000 00000000 |
| t7 opcode: CP_EVENT_WRITE (46) (2 dwords) |
| { EVENT = PC_CCU_INVALIDATE_COLOR } |
| event PC_CCU_INVALIDATE_COLOR |
| 000000000105826c: 0000: 70460001 00000019 |
| t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) |
| 0000000001058274: 0000: 70268000 |
| t4 write RB_2D_UNKNOWN_8C01 (8c01) |
| RB_2D_UNKNOWN_8C01: 0 |
| 0000000001058278: 0000: 488c0101 00000000 |
| t4 write RB_2D_BLIT_CNTL (8c00) |
| RB_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 } |
| 0000000001058280: 0000: 408c0001 10f03080 |
| t4 write GRAS_2D_BLIT_CNTL (8400) |
| GRAS_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 } |
| 0000000001058288: 0000: 48840001 10f03080 |
| t4 write SP_2D_DST_FORMAT (acc0) |
| SP_2D_DST_FORMAT: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf } |
| 0000000001058290: 0000: 48acc001 0000f180 |
| t4 write RB_2D_SRC_SOLID_C0 (8c2c) |
| RB_2D_SRC_SOLID_C0: 0 |
| RB_2D_SRC_SOLID_C1: 0 |
| RB_2D_SRC_SOLID_C2: 0 |
| RB_2D_SRC_SOLID_C3: 0xff |
| 0000000001058298: 0000: 488c2c04 00000000 00000000 00000000 000000ff |
| t4 write GRAS_2D_DST_TL (8405) |
| GRAS_2D_DST_TL: { X = 0 | Y = 0 } |
| GRAS_2D_DST_BR: { X = 255 | Y = 255 } |
| 00000000010582ac: 0000: 48840502 00000000 00ff00ff |
| t4 write RB_2D_DST_INFO (8c17) |
| RB_2D_DST_INFO: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | TILE_MODE = TILE6_3 | COLOR_SWAP = WZYX | FLAGS | SAMPLES = MSAA_ONE } |
| RB_2D_DST_LO: 0x1013000 |
| RB_2D_DST_HI: 0 |
| RB_2D_DST_PITCH: 1024 |
| 00000000010582b8: 0000: 408c1704 00001330 01013000 00000000 00000010 |
| t4 write RB_2D_DST_FLAGS_LO (8c20) |
| RB_2D_DST_FLAGS_LO: 0x1012000 |
| RB_2D_DST_FLAGS_HI: 0 |
| RB_2D_DST_FLAGS_PITCH: 64 | 0x4000 |
| 00000000010582cc: 0000: 488c2083 01012000 00000000 00004001 |
| t7 opcode: CP_BLIT (2c) (2 dwords) |
| { OP = BLIT_OP_SCALE } |
| mode: (null) |
| skip_ib2: g=0, l=0 |
| draw[0] register values |
| !+ 010fd000 VSC_DRAW_STRM_SIZE_ADDRESS_LO: 0x10fd000 |
| + 00000000 VSC_DRAW_STRM_SIZE_ADDRESS_HI: 0 |
| !+ 0105c000 VSC_PRIM_STRM_ADDRESS_LO: 0x105c000 |
| + 00000000 VSC_PRIM_STRM_ADDRESS_HI: 0 |
| !+ 010dc800 VSC_DRAW_STRM_ADDRESS_LO: 0x10dc800 |
| + 00000000 VSC_DRAW_STRM_ADDRESS_HI: 0 |
| !+ 03200000 UCHE_UNKNOWN_0E12: 0x3200000 |
| !+ 00000004 UCHE_CLIENT_PF: { PERFSEL = 0x4 } |
| + 00000000 GRAS_UNKNOWN_8099: 0 |
| !+ 00000002 GRAS_UNKNOWN_80A0: 0x2 |
| + 00000000 GRAS_UNKNOWN_80AF: FALSE |
| + 00000000 GRAS_LRZ_CNTL: { 0 } |
| + 00000000 GRAS_UNKNOWN_8110: 0 |
| !+ 10f03080 GRAS_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 } |
| + 00000000 GRAS_2D_DST_TL: { X = 0 | Y = 0 } |
| !+ 00ff00ff GRAS_2D_DST_BR: { X = 255 | Y = 255 } |
| !+ 00000880 GRAS_UNKNOWN_8600: 0x880 |
| !+ 00000401 RB_RENDER_CONTROL0: { IJ_PERSP_PIXEL | COORD_MASK = 0 | UNK10 } |
| + 00000000 RB_RENDER_CONTROL1: { 0 } |
| + 00000000 RB_FS_OUTPUT_CNTL0: { 0 } |
| + 00000000 RB_SRGB_CNTL: { 0 } |
| !+ 00000010 RB_UNKNOWN_8811: 0x1 |
| + 00000000 RB_UNKNOWN_8818: 0 |
| + 00000000 RB_UNKNOWN_8819: 0 |
| + 00000000 RB_UNKNOWN_881A: 0 |
| + 00000000 RB_UNKNOWN_881B: 0 |
| + 00000000 RB_UNKNOWN_881C: 0 |
| + 00000000 RB_UNKNOWN_881D: 0 |
| + 00000000 RB_UNKNOWN_881E: 0 |
| + 00000000 RB_LRZ_CNTL: { 0 } |
| + 00000000 RB_UNKNOWN_88F0: 0 |
| !+ 10f03080 RB_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 } |
| + 00000000 RB_2D_UNKNOWN_8C01: 0 |
| !+ 00001330 RB_2D_DST_INFO: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | TILE_MODE = TILE6_3 | COLOR_SWAP = WZYX | FLAGS | SAMPLES = MSAA_ONE } |
| !+ 01013000 RB_2D_DST_LO: 0x1013000 |
| + 00000000 RB_2D_DST_HI: 0 |
| !+ 00000010 RB_2D_DST_PITCH: 1024 |
| !+ 01012000 RB_2D_DST_FLAGS_LO: 0x1012000 |
| + 00000000 RB_2D_DST_FLAGS_HI: 0 |
| !+ 00004001 RB_2D_DST_FLAGS_PITCH: 64 | 0x4000 |
| + 00000000 RB_2D_SRC_SOLID_C0: 0 |
| + 00000000 RB_2D_SRC_SOLID_C1: 0 |
| + 00000000 RB_2D_SRC_SOLID_C2: 0 |
| !+ 000000ff RB_2D_SRC_SOLID_C3: 0xff |
| + 00000000 RB_UNKNOWN_8E01: 0 |
| !+ 00100000 RB_UNKNOWN_8E04: 0x100000 |
| !+ 10000000 RB_CCU_CNTL: { OFFSET = 0x20000 } |
| + 00000000 VPC_UNKNOWN_9107: 0 |
| + 00000000 VPC_UNKNOWN_9210: 0 |
| + 00000000 VPC_UNKNOWN_9211: 0 |
| + 00000000 VPC_POINT_COORD_INVERT: { 0 } |
| + 00000000 VPC_UNKNOWN_9300: 0 |
| !+ 00000001 VPC_SO_DISABLE: { DISABLE } |
| + 00000000 VPC_UNKNOWN_9600: 0 |
| + 00000000 VPC_UNKNOWN_9602: FALSE |
| !+ 0000001f PC_MODE_CNTL: 0x1f |
| + 00000000 PC_UNKNOWN_9980: 0 |
| + 00000000 PC_PRIMITIVE_CNTL_6: { STRIDE_IN_VPC = 0 } |
| + 00000000 PC_UNKNOWN_9B07: 0 |
| + 00000000 PC_UNKNOWN_9E72: 0 |
| + 00000000 VFD_MODE_CNTL: { 0 } |
| + 00000000 VFD_UNKNOWN_A008: 0 |
| !+ 00000001 VFD_ADD_OFFSET: { VERTEX } |
| + 00000000 SP_UNKNOWN_A81B: 0 |
| + 00000000 SP_HS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = TWO_QUADS } |
| + 00000000 SP_GS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = TWO_QUADS } |
| + 00000000 SP_UNKNOWN_A982: 0 |
| + 00000000 SP_UNKNOWN_A9A8: 0 |
| !+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | 0x4 } |
| + 00000000 SP_IBO_COUNT: 0 |
| !+ 0000f180 SP_2D_DST_FORMAT: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf } |
| + 00000000 SP_UNKNOWN_AE00: 0 |
| !+ 00000410 SP_UNKNOWN_AE03: 0x410 |
| !+ 00000008 SP_UNKNOWN_AE04: 0x8 |
| !+ 0000003f SP_UNKNOWN_AE0F: 0x3f |
| !+ 01011000 SP_PS_TP_BORDER_COLOR_BASE_ADDR: 0x1011000 |
| + 00000000 SP_PS_TP_BORDER_COLOR_BASE_ADDR+0x1: 0 |
| + 00000000 SP_UNKNOWN_B182: 0 |
| + 00000000 SP_UNKNOWN_B183: 0 |
| !+ 01011000 SP_TP_BORDER_COLOR_BASE_ADDR: 0x1011000 |
| + 00000000 SP_TP_BORDER_COLOR_BASE_ADDR+0x1: 0 |
| !+ 000000a2 SP_TP_UNKNOWN_B309: 0xa2 |
| !+ 00100000 SP_UNKNOWN_B600: 0x100000 |
| !+ 00000044 SP_UNKNOWN_B605: 0x44 |
| !+ 000000fc HLSQ_CONTROL_5_REG: 0xfc |
| !+ 000fffff HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_SHARED_CONST | GFX_SHARED_CONST | CS_BINDLESS = 0x1f | GFX_BINDLESS = 0x1f } |
| + 00000000 HLSQ_SHARED_CONSTS: { 0 } |
| !+ 00000080 HLSQ_UNKNOWN_BE00: 0x80 |
| + 00000000 HLSQ_UNKNOWN_BE01: 0 |
| + 00000000 HLSQ_UNKNOWN_BE04: 0 |
| 00000000010582dc: 0000: 702c0001 00000003 |
| t7 opcode: CP_EVENT_WRITE (46) (2 dwords) |
| { EVENT = LRZ_FLUSH } |
| event LRZ_FLUSH |
| 00000000010582e4: 0000: 70460001 00000026 |
| t7 opcode: CP_SKIP_IB2_ENABLE_GLOBAL (1d) (2 dwords) |
| 00000000010582ec: 0000: 709d0001 00000000 |
| t7 opcode: CP_EVENT_WRITE (46) (5 dwords) |
| { EVENT = PC_CCU_FLUSH_COLOR_TS } |
| { ADDR_0_LO = 0x1011880 } |
| { ADDR_0_HI = 0 } |
| { 3 = 0 } |
| event PC_CCU_FLUSH_COLOR_TS |
| 00000000010582f4: 0000: 70460004 0000001d 01011880 00000000 00000000 |
| t7 opcode: CP_EVENT_WRITE (46) (5 dwords) |
| { EVENT = PC_CCU_FLUSH_DEPTH_TS } |
| { ADDR_0_LO = 0x1011880 } |
| { ADDR_0_HI = 0 } |
| { 3 = 0 } |
| event PC_CCU_FLUSH_DEPTH_TS |
| 0000000001058308: 0000: 70460004 0000001c 01011880 00000000 00000000 |
| t7 opcode: CP_EVENT_WRITE (46) (2 dwords) |
| { EVENT = PC_CCU_INVALIDATE_COLOR } |
| event PC_CCU_INVALIDATE_COLOR |
| 000000000105831c: 0000: 70460001 00000019 |
| t7 opcode: CP_EVENT_WRITE (46) (2 dwords) |
| { EVENT = PC_CCU_INVALIDATE_DEPTH } |
| event PC_CCU_INVALIDATE_DEPTH |
| 0000000001058324: 0000: 70460001 00000018 |
| t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) |
| 000000000105832c: 0000: 70268000 |
| t4 write RB_CCU_CNTL (8e07) |
| RB_CCU_CNTL: { OFFSET = 0xf8000 | GMEM } |
| 0000000001058330: 0000: 408e0701 7c400000 |
| t4 write VPC_SO_DISABLE (9306) |
| VPC_SO_DISABLE: { 0 } |
| 0000000001058338: 0000: 48930601 00000000 |
| t4 write GRAS_BIN_CONTROL (80a1) |
| GRAS_BIN_CONTROL: { BINW = 256 | BINH = 256 | UNK22 = 0x18 } |
| 0000000001058340: 0000: 4880a101 06001008 |
| t4 write RB_BIN_CONTROL (8800) |
| RB_BIN_CONTROL: { BINW = 256 | BINH = 256 | UNK22 = 0x18 } |
| 0000000001058348: 0000: 48880001 06001008 |
| t4 write RB_BIN_CONTROL2 (88d3) |
| RB_BIN_CONTROL2: { BINW = 256 | BINH = 256 } |
| 0000000001058350: 0000: 4088d301 00001008 |
| t7 opcode: CP_SET_MARKER (65) (2 dwords) |
| { MODE = RM6_YIELD | MARKER = RM6_YIELD } |
| 0000000001058358: 0000: 70e50001 00000007 |
| t7 opcode: CP_SET_MARKER (65) (2 dwords) |
| { MODE = RM6_GMEM | MARKER = RM6_GMEM } |
| 0000000001058360: 0000: 70e50001 00000004 |
| t4 write GRAS_SC_WINDOW_SCISSOR_TL (80f0) |
| GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } |
| GRAS_SC_WINDOW_SCISSOR_BR: { X = 255 | Y = 255 } |
| 0000000001058368: 0000: 4080f002 00000000 00ff00ff |
| t4 write GRAS_2D_RESOLVE_CNTL_1 (840a) |
| GRAS_2D_RESOLVE_CNTL_1: { X = 0 | Y = 0 } |
| GRAS_2D_RESOLVE_CNTL_2: { X = 255 | Y = 255 } |
| 0000000001058374: 0000: 48840a02 00000000 00ff00ff |
| t4 write RB_WINDOW_OFFSET (8890) |
| RB_WINDOW_OFFSET: { X = 0 | Y = 0 } |
| 0000000001058380: 0000: 48889001 00000000 |
| t4 write RB_WINDOW_OFFSET2 (88d4) |
| RB_WINDOW_OFFSET2: { X = 0 | Y = 0 } |
| 0000000001058388: 0000: 4888d401 00000000 |
| t4 write SP_WINDOW_OFFSET (b4d1) |
| SP_WINDOW_OFFSET: { X = 0 | Y = 0 } |
| 0000000001058390: 0000: 48b4d101 00000000 |
| t4 write SP_TP_WINDOW_OFFSET (b307) |
| SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 } |
| 0000000001058398: 0000: 48b30701 00000000 |
| t4 write VPC_SO_DISABLE (9306) |
| VPC_SO_DISABLE: { 0 } |
| 00000000010583a0: 0000: 48930601 00000000 |
| t7 opcode: CP_SET_VISIBILITY_OVERRIDE (64) (2 dwords) |
| 00000000010583a8: 0000: 70640001 00000001 |
| t7 opcode: CP_SET_MODE (63) (2 dwords) |
| 00000000010583b0: 0000: 70e30001 00000000 |
| t7 opcode: CP_INDIRECT_BUFFER (3f) (4 dwords) |
| ibaddr:000000000115e000 |
| ibsize:000000f1 |
| t7 opcode: CP_COND_REG_EXEC (47) (3 dwords) |
| { REG0 = 0 | GMEM | MODE = RENDER_MODE } |
| { DWORDS = 23 } |
| 000000000115e000: 0000: 70c70002 34000000 00000017 |
| t4 write RB_BLIT_SCISSOR_TL (88d1) |
| RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 } |
| RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 } |
| 000000000115e00c: 0000: 4888d102 00000000 00ff00ff |
| t4 write RB_MSAA_CNTL (88d5) |
| RB_MSAA_CNTL: { SAMPLES = MSAA_ONE } |
| 000000000115e018: 0000: 4088d501 00000000 |
| t4 write RB_BLIT_INFO (88e3) |
| RB_BLIT_INFO: { UNK0 | GMEM | CLEAR_MASK = 0 } |
| 000000000115e020: 0000: 4088e301 00000003 |
| t4 write RB_BLIT_DST_INFO (88d7) |
| RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM } |
| RB_BLIT_DST: 0x1013000 |
| RB_BLIT_DST+0x1: 0 |
| RB_BLIT_DST_PITCH: 1024 |
| 000000000115e028: 0000: 4888d704 00001807 01013000 00000000 00000010 |
| t4 write RB_BLIT_FLAG_DST (88dc) |
| RB_BLIT_FLAG_DST: 0x1012000 |
| RB_BLIT_FLAG_DST+0x1: 0 |
| RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 } |
| 000000000115e03c: 0000: 4088dc83 01012000 00000000 00004001 |
| t4 write RB_BLIT_BASE_GMEM (88d6) |
| RB_BLIT_BASE_GMEM: 0 |
| 000000000115e04c: 0000: 4088d601 00000000 |
| t7 opcode: CP_EVENT_WRITE (46) (2 dwords) |
| { EVENT = BLIT } |
| event BLIT |
| mode: RM6_GMEM |
| skip_ib2: g=0, l=0 |
| draw[1] register values |
| !+ 06001008 GRAS_BIN_CONTROL: { BINW = 256 | BINH = 256 | UNK22 = 0x18 } |
| + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } |
| !+ 00ff00ff GRAS_SC_WINDOW_SCISSOR_BR: { X = 255 | Y = 255 } |
| + 00000000 GRAS_2D_RESOLVE_CNTL_1: { X = 0 | Y = 0 } |
| !+ 00ff00ff GRAS_2D_RESOLVE_CNTL_2: { X = 255 | Y = 255 } |
| !+ 06001008 RB_BIN_CONTROL: { BINW = 256 | BINH = 256 | UNK22 = 0x18 } |
| + 00000000 RB_WINDOW_OFFSET: { X = 0 | Y = 0 } |
| + 00000000 RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 } |
| !+ 00ff00ff RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 } |
| !+ 00001008 RB_BIN_CONTROL2: { BINW = 256 | BINH = 256 } |
| + 00000000 RB_WINDOW_OFFSET2: { X = 0 | Y = 0 } |
| + 00000000 RB_MSAA_CNTL: { SAMPLES = MSAA_ONE } |
| + 00000000 RB_BLIT_BASE_GMEM: 0 |
| !+ 00001807 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM } |
| !+ 01013000 RB_BLIT_DST: 0x1013000 |
| + 00000000 RB_BLIT_DST+0x1: 0 |
| !+ 00000010 RB_BLIT_DST_PITCH: 1024 |
| !+ 01012000 RB_BLIT_FLAG_DST: 0x1012000 |
| + 00000000 RB_BLIT_FLAG_DST+0x1: 0 |
| !+ 00004001 RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 } |
| !+ 00000003 RB_BLIT_INFO: { UNK0 | GMEM | CLEAR_MASK = 0 } |
| !+ 7c400000 RB_CCU_CNTL: { OFFSET = 0xf8000 | GMEM } |
| !+ 00000000 VPC_SO_DISABLE: { 0 } |
| + 00000000 SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 } |
| + 00000000 SP_WINDOW_OFFSET: { X = 0 | Y = 0 } |
| 000000000115e054: 0000: 70460001 0000001e |
| t4 write RB_BLIT_SCISSOR_TL (88d1) |
| RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 } |
| RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 } |
| 000000000115e05c: 0000: 4888d102 00000000 00ff00ff |
| t7 opcode: CP_COND_REG_EXEC (47) (3 dwords) |
| { REG0 = 0 | SYSMEM | MODE = RENDER_MODE } |
| { DWORDS = 0 } |
| 000000000115e068: 0000: 70c70002 38000000 00000000 |
| t4 write RB_DEPTH_BUFFER_INFO (8872) |
| RB_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE } |
| RB_DEPTH_BUFFER_PITCH: 0 |
| RB_DEPTH_BUFFER_ARRAY_PITCH: 0 |
| RB_DEPTH_BUFFER_BASE_LO: 0 |
| RB_DEPTH_BUFFER_BASE_HI: 0 |
| RB_DEPTH_BUFFER_BASE_GMEM: 0 |
| 000000000115e074: 0000: 48887286 00000000 00000000 00000000 00000000 00000000 00000000 |
| t4 write GRAS_SU_DEPTH_BUFFER_INFO (8098) |
| GRAS_SU_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE } |
| 000000000115e090: 0000: 48809801 00000000 |
| t4 write GRAS_LRZ_BUFFER_BASE_LO (8103) |
| GRAS_LRZ_BUFFER_BASE_LO: 0 |
| GRAS_LRZ_BUFFER_BASE_HI: 0 |
| GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } |
| GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO: 0 |
| GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0 |
| 000000000115e098: 0000: 48810385 00000000 00000000 00000000 00000000 00000000 |
| t4 write RB_STENCIL_INFO (8881) |
| RB_STENCIL_INFO: { 0 } |
| 000000000115e0b0: 0000: 48888101 00000000 |
| t4 write RB_MRT[0].BUF_INFO (8822) |
| RB_MRT[0].BUF_INFO: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | COLOR_TILE_MODE = TILE6_3 | COLOR_SWAP = WZYX } |
| RB_MRT[0].PITCH: 1024 |
| RB_MRT[0].ARRAY_PITCH: 262144 |
| RB_MRT[0].BASE_LO: 0x1013000 |
| RB_MRT[0].BASE_HI: 0 |
| RB_MRT[0].BASE_GMEM: 0 |
| 000000000115e0b8: 0000: 48882286 00000330 00000010 00001000 01013000 00000000 00000000 |
| t4 write SP_FS_MRT[0].REG (a996) |
| SP_FS_MRT[0].REG: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM } |
| 000000000115e0d4: 0000: 48a99601 00000030 |
| t4 write RB_MRT_FLAG_BUFFER[0].ADDR_LO (8903) |
| RB_MRT_FLAG_BUFFER[0].ADDR_LO: 0x1012000 |
| RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0 |
| RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 } |
| 000000000115e0dc: 0000: 40890383 01012000 00000000 00004001 |
| t4 write RB_SRGB_CNTL (880f) |
| RB_SRGB_CNTL: { 0 } |
| 000000000115e0ec: 0000: 48880f01 00000000 |
| t4 write SP_SRGB_CNTL (a98a) |
| SP_SRGB_CNTL: { 0 } |
| 000000000115e0f4: 0000: 40a98a01 00000000 |
| t4 write GRAS_MAX_LAYER_INDEX (8004) |
| GRAS_MAX_LAYER_INDEX: 0 |
| 000000000115e0fc: 0000: 48800401 00000000 |
| t4 write SP_TP_RAS_MSAA_CNTL (b300) |
| SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } |
| SP_TP_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE } |
| 000000000115e104: 0000: 40b30002 00000000 00000004 |
| t4 write GRAS_RAS_MSAA_CNTL (80a2) |
| GRAS_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } |
| GRAS_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE } |
| 000000000115e110: 0000: 4880a202 00000000 00000004 |
| t4 write RB_RAS_MSAA_CNTL (8802) |
| RB_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } |
| RB_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE } |
| 000000000115e11c: 0000: 40880202 00000000 00000004 |
| t4 write RB_MSAA_CNTL (88d5) |
| RB_MSAA_CNTL: { SAMPLES = MSAA_ONE } |
| 000000000115e128: 0000: 4088d501 00000000 |
| t7 opcode: CP_COND_REG_EXEC (47) (3 dwords) |
| { REG0 = 0 | GMEM | SYSMEM | MODE = RENDER_MODE } |
| { DWORDS = 4 } |
| 000000000115e130: 0000: 70c70002 3c000000 00000004 |
| t7 opcode: CP_REG_WRITE (6d) (4 dwords) |
| { TRACKER = TRACK_RENDER_CNTL } |
| RB_RENDER_CNTL: { UNK4 | FLAG_MRTS = 0x1 } |
| 000000000115e13c: 0000: 706d8003 00000002 00008801 00010010 |
| t7 opcode: CP_SET_DRAW_STATE (43) (7 dwords) |
| { COUNT = 0 | DISABLE | GMEM | GROUP_ID = 17 } |
| { ADDR_LO = 0 } |
| { ADDR_HI = 0 } |
| { COUNT = 0 | DISABLE | SYSMEM | GROUP_ID = 18 } |
| { ADDR_LO = 0 } |
| { ADDR_HI = 0 } |
| 000000000115e14c: 0000: 70438006 11220000 00000000 00000000 12420000 00000000 00000000 |
| t7 opcode: CP_SET_DRAW_STATE (43) (52 dwords) |
| { COUNT = 157 | GMEM | SYSMEM | GROUP_ID = 0 } |
| { ADDR_LO = 0x1054180 } |
| { ADDR_HI = 0 } |
| { COUNT = 139 | BINNING | GROUP_ID = 1 } |
| { ADDR_LO = 0x10543f4 } |
| { ADDR_HI = 0 } |
| { COUNT = 19 | GMEM | SYSMEM | GROUP_ID = 4 } |
| { ADDR_LO = 0x1054620 } |
| { ADDR_HI = 0 } |
| { COUNT = 19 | BINNING | GROUP_ID = 5 } |
| { ADDR_LO = 0x105466c } |
| { ADDR_HI = 0 } |
| { COUNT = 9 | BINNING | GMEM | SYSMEM | GROUP_ID = 6 } |
| { ADDR_LO = 0x105470c } |
| { ADDR_HI = 0 } |
| { COUNT = 6 | BINNING | GMEM | SYSMEM | GROUP_ID = 7 } |
| { ADDR_LO = 0x1054748 } |
| { ADDR_HI = 0 } |
| { COUNT = 7 | BINNING | GMEM | SYSMEM | GROUP_ID = 8 } |
| { ADDR_LO = 0x1054784 } |
| { ADDR_HI = 0 } |
| { COUNT = 18 | BINNING | GMEM | SYSMEM | GROUP_ID = 19 } |
| { ADDR_LO = 0x10546b8 } |
| { ADDR_HI = 0 } |
| { COUNT = 3 | BINNING | GMEM | SYSMEM | GROUP_ID = 20 } |
| { ADDR_LO = 0x1054700 } |
| { ADDR_HI = 0 } |
| { COUNT = 2 | BINNING | GMEM | SYSMEM | GROUP_ID = 21 } |
| { ADDR_LO = 0x1054730 } |
| { ADDR_HI = 0 } |
| { COUNT = 4 | BINNING | GMEM | SYSMEM | GROUP_ID = 22 } |
| { ADDR_LO = 0x1054738 } |
| { ADDR_HI = 0 } |
| { COUNT = 5 | BINNING | GMEM | SYSMEM | GROUP_ID = 23 } |
| { ADDR_LO = 0x10547a0 } |
| { ADDR_HI = 0 } |
| { COUNT = 3 | BINNING | GMEM | SYSMEM | GROUP_ID = 24 } |
| { ADDR_LO = 0x1054760 } |
| { ADDR_HI = 0 } |
| { COUNT = 2 | BINNING | GMEM | SYSMEM | GROUP_ID = 25 } |
| { ADDR_LO = 0x105476c } |
| { ADDR_HI = 0 } |
| { COUNT = 2 | BINNING | GMEM | SYSMEM | GROUP_ID = 26 } |
| { ADDR_LO = 0x1054774 } |
| { ADDR_HI = 0 } |
| { COUNT = 2 | BINNING | GMEM | SYSMEM | GROUP_ID = 27 } |
| { ADDR_LO = 0x105477c } |
| { ADDR_HI = 0 } |
| { COUNT = 6 | BINNING | GMEM | SYSMEM | GROUP_ID = 28 } |
| { ADDR_LO = 0x10547b4 } |
| { ADDR_HI = 0 } |
| 000000000115e168: 0000: 70438033 0060009d 01054180 00000000 0110008b 010543f4 00000000 04600013 |
| 000000000115e188: 0020: 01054620 00000000 05100013 0105466c 00000000 06700009 0105470c 00000000 |
| 000000000115e1a8: 0040: 07700006 01054748 00000000 08700007 01054784 00000000 13700012 010546b8 |
| 000000000115e1c8: 0060: 00000000 14700003 01054700 00000000 15700002 01054730 00000000 16700004 |
| 000000000115e1e8: 0080: 01054738 00000000 17700005 010547a0 00000000 18700003 01054760 00000000 |
| 000000000115e208: 00a0: 19700002 0105476c 00000000 1a700002 01054774 00000000 1b700002 0105477c |
| 000000000115e228: 00c0: 00000000 1c700006 010547b4 00000000 |
| t4 write PC_RESTART_INDEX (9803) |
| PC_RESTART_INDEX: 4294967295 |
| 000000000115e238: 0000: 40980301 ffffffff |
| t7 opcode: CP_WAIT_FOR_ME (13) (1 dwords) |
| 000000000115e240: 0000: 70138000 |
| t4 write PC_PRIMITIVE_CNTL_0 (9b00) |
| PC_PRIMITIVE_CNTL_0: { 0 } |
| 000000000115e244: 0000: 409b0001 00000000 |
| t7 opcode: CP_SET_DRAW_STATE (43) (82 dwords) |
| { COUNT = 157 | GMEM | SYSMEM | GROUP_ID = 0 } |
| { ADDR_LO = 0x1054180 } |
| { ADDR_HI = 0 } |
| { COUNT = 139 | BINNING | GROUP_ID = 1 } |
| { ADDR_LO = 0x10543f4 } |
| { ADDR_HI = 0 } |
| { COUNT = 0 | DISABLE | BINNING | GMEM | SYSMEM | GROUP_ID = 2 } |
| { ADDR_LO = 0 } |
| { ADDR_HI = 0 } |
| { COUNT = 19 | GMEM | SYSMEM | GROUP_ID = 4 } |
| { ADDR_LO = 0x1054620 } |
| { ADDR_HI = 0 } |
| { COUNT = 19 | BINNING | GROUP_ID = 5 } |
| { ADDR_LO = 0x105466c } |
| { ADDR_HI = 0 } |
| { COUNT = 9 | BINNING | GMEM | SYSMEM | GROUP_ID = 6 } |
| { ADDR_LO = 0x105470c } |
| { ADDR_HI = 0 } |
| { COUNT = 6 | BINNING | GMEM | SYSMEM | GROUP_ID = 7 } |
| { ADDR_LO = 0x1054748 } |
| { ADDR_HI = 0 } |
| { COUNT = 7 | BINNING | GMEM | SYSMEM | GROUP_ID = 8 } |
| { ADDR_LO = 0x1054784 } |
| { ADDR_HI = 0 } |
| { COUNT = 0 | DISABLE | BINNING | GMEM | SYSMEM | GROUP_ID = 9 } |
| { ADDR_LO = 0x115c070 } |
| { ADDR_HI = 0 } |
| { COUNT = 0 | DISABLE | BINNING | GMEM | SYSMEM | GROUP_ID = 10 } |
| { ADDR_LO = 0x115c070 } |
| { ADDR_HI = 0 } |
| { COUNT = 0 | DISABLE | BINNING | GMEM | SYSMEM | GROUP_ID = 11 } |
| { ADDR_LO = 0x115c070 } |
| { ADDR_HI = 0 } |
| { COUNT = 0 | DISABLE | BINNING | GMEM | SYSMEM | GROUP_ID = 12 } |
| { ADDR_LO = 0x115c070 } |
| { ADDR_HI = 0 } |
| { COUNT = 0 | DISABLE | GMEM | SYSMEM | GROUP_ID = 13 } |
| { ADDR_LO = 0x115c070 } |
| { ADDR_HI = 0 } |
| { COUNT = 0 | DISABLE | BINNING | GMEM | SYSMEM | GROUP_ID = 14 } |
| { ADDR_LO = 0 } |
| { ADDR_HI = 0 } |
| { COUNT = 0 | DIRTY | DISABLE | GMEM | SYSMEM | GROUP_ID = 15 } |
| { ADDR_LO = 0 } |
| { ADDR_HI = 0 } |
| { COUNT = 4 | BINNING | GMEM | SYSMEM | GROUP_ID = 3 } |
| { ADDR_LO = 0x115c070 } |
| { ADDR_HI = 0 } |
| { COUNT = 0 | DISABLE | BINNING | GMEM | SYSMEM | GROUP_ID = 16 } |
| { ADDR_LO = 0 } |
| { ADDR_HI = 0 } |
| { COUNT = 18 | BINNING | GMEM | SYSMEM | GROUP_ID = 19 } |
| { ADDR_LO = 0x10546b8 } |
| { ADDR_HI = 0 } |
| { COUNT = 3 | BINNING | GMEM | SYSMEM | GROUP_ID = 20 } |
| { ADDR_LO = 0x1054700 } |
| { ADDR_HI = 0 } |
| { COUNT = 2 | BINNING | GMEM | SYSMEM | GROUP_ID = 21 } |
| { ADDR_LO = 0x1054730 } |
| { ADDR_HI = 0 } |
| { COUNT = 4 | BINNING | GMEM | SYSMEM | GROUP_ID = 22 } |
| { ADDR_LO = 0x1054738 } |
| { ADDR_HI = 0 } |
| { COUNT = 5 | BINNING | GMEM | SYSMEM | GROUP_ID = 23 } |
| { ADDR_LO = 0x10547a0 } |
| { ADDR_HI = 0 } |
| { COUNT = 3 | BINNING | GMEM | SYSMEM | GROUP_ID = 24 } |
| { ADDR_LO = 0x1054760 } |
| { ADDR_HI = 0 } |
| { COUNT = 2 | BINNING | GMEM | SYSMEM | GROUP_ID = 25 } |
| { ADDR_LO = 0x105476c } |
| { ADDR_HI = 0 } |
| { COUNT = 2 | BINNING | GMEM | SYSMEM | GROUP_ID = 26 } |
| { ADDR_LO = 0x1054774 } |
| { ADDR_HI = 0 } |
| { COUNT = 2 | BINNING | GMEM | SYSMEM | GROUP_ID = 27 } |
| { ADDR_LO = 0x105477c } |
| { ADDR_HI = 0 } |
| { COUNT = 6 | BINNING | GMEM | SYSMEM | GROUP_ID = 28 } |
| { ADDR_LO = 0x10547b4 } |
| { ADDR_HI = 0 } |
| 000000000115e24c: 0000: 70430051 0060009d 01054180 00000000 0110008b 010543f4 00000000 02720000 |
| 000000000115e26c: 0020: 00000000 00000000 04600013 01054620 00000000 05100013 0105466c 00000000 |
| 000000000115e28c: 0040: 06700009 0105470c 00000000 07700006 01054748 00000000 08700007 01054784 |
| 000000000115e2ac: 0060: 00000000 09720000 0115c070 00000000 0a720000 0115c070 00000000 0b720000 |
| 000000000115e2cc: 0080: 0115c070 00000000 0c720000 0115c070 00000000 0d620000 0115c070 00000000 |
| 000000000115e2ec: 00a0: 0e720000 00000000 00000000 0f630000 00000000 00000000 03700004 0115c070 |
| 000000000115e30c: 00c0: 00000000 10720000 00000000 00000000 13700012 010546b8 00000000 14700003 |
| 000000000115e32c: 00e0: 01054700 00000000 15700002 01054730 00000000 16700004 01054738 00000000 |
| 000000000115e34c: 0100: 17700005 010547a0 00000000 18700003 01054760 00000000 19700002 0105476c |
| 000000000115e36c: 0120: 00000000 1a700002 01054774 00000000 1b700002 0105477c 00000000 1c700006 |
| 000000000115e38c: 0140: 010547b4 00000000 |
| group_id: 0 |
| count: 157 |
| addr: 0000000001054180 |
| flags: 0 |
| enable_mask: 0x6 |
| 0000000001054180: 0000: 40bb0801 0000009f 40a80001 80100180 48a82302 00000100 00000001 48b80001 |
| 00000000010541a0: 0020: 00000101 48a81c02 01054000 00000000 70328003 00620000 01054000 00000000 |
| 00000000010541c0: 0040: 70320007 00604001 00000000 00000000 3f800000 00000000 d0d0d0d0 d0d0d0d0 |
| 00000000010541e0: 0060: 48a83b01 00000000 40b80101 00000000 40a86301 00000000 40b80201 00000000 |
| 0000000001054200: 0080: 48a89401 00000000 48b80301 00000000 40a98001 81500100 48ab0402 00000100 |
| 0000000001054220: 00a0: 00000001 40bb1001 00000100 40a98302 01054080 00000000 70348003 00720000 |
| 0000000001054240: 00c0: 01054080 00000000 48a9bb01 00000000 40b98701 00000000 48a83101 00000000 |
| 0000000001054260: 00e0: 40a00186 fcfcfc09 0000fcfc fcfcfcfc 000000fc 0000fcfc 00000000 40921204 |
| 0000000001054280: 0100: fffffff0 ffffffff ffffffff ffffffff 70dc0004 00009216 00000000 00009305 |
| 00000000010542a0: 0120: 00000000 40a80301 0f000f08 48a81301 00000400 40930101 00ff0408 48910101 |
| 00000000010542c0: 0140: 00ffff00 48800101 00000000 489b0101 00000008 48a80201 00000002 48910401 |
| 00000000010542e0: 0160: 0000ffff 48809b01 00000000 40980601 00000000 40930401 ff01ff04 40920008 |
| * |
| 0000000001054320: 01a0: 48920808 00000000 00000000 00000000 00000000 00000000 00000000 00000000 |
| 0000000001054340: 01c0: 00000000 40a99e01 00007fc0 40b98285 00000007 fcfcfcfc fcfcfc00 fcfcfcfc |
| 0000000001054360: 01e0: 000000fc 48b98001 00000003 40800501 00000001 48880902 00000401 00000000 |
| 0000000001054380: 0200: 40881001 00000000 40810101 00000000 48810901 00000000 40a98c02 fcfcfc00 |
| 00000000010543a0: 0220: 00000001 48a98e08 00000002 000000fc 000000fc 000000fc 000000fc 000000fc |
| 00000000010543c0: 0240: 000000fc 000000fc 48a98b01 0000000f 40880b02 00000000 00000001 40880d01 |
| 00000000010543e0: 0260: 0000000f 48809401 00000000 40887001 00000000 |
| t4 write HLSQ_INVALIDATE_CMD (bb08) |
| HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 } |
| 0000000001054180: 0000: 40bb0801 0000009f |
| t4 write SP_VS_CTRL_REG0 (a800) |
| SP_VS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 3 | BRANCHSTACK = 0 | THREADSIZE = FOUR_QUADS | MERGEDREGS } |
| 0000000001054188: 0000: 40a80001 80100180 |
| t4 write SP_VS_CONFIG (a823) |
| SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } |
| SP_VS_INSTRLEN: 1 |
| 0000000001054190: 0000: 48a82302 00000100 00000001 |
| t4 write HLSQ_VS_CNTL (b800) |
| HLSQ_VS_CNTL: { CONSTLEN = 4 | ENABLED } |
| 000000000105419c: 0000: 48b80001 00000101 |
| t4 write SP_VS_OBJ_START_LO (a81c) |
| SP_VS_OBJ_START_LO: 0x1054000 base=1054000, offset=0, size=12288 |
| SP_VS_OBJ_START_HI: 0 base=1054000, offset=0, size=12288 |
| 0000000001054000: 0000: 00080009 42bc080b 10040004 64858008 10050005 64858009 10050006 6485800a |
| 0000000001054020: 0020: 10040007 6485800b 00000000 03000000 00000000 00000000 00000000 00000000 |
| * |
| 0000000001054080: 0080: 00002000 47300002 00002001 47300003 00002002 47300004 00002003 47308005 |
| 00000000010540a0: 00a0: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000 |
| * |
| :2:0000:0000[42bc080bx_00080009x] (nop3) cmps.s.eq r2.w, r2.y, r2.x |
| :3:0001:0004[64858008x_10040004x] sel.b32 r2.x, r1.x, r2.w, c1.x |
| :3:0002:0005[64858009x_10050005x] sel.b32 r2.y, r1.y, r2.w, c1.y |
| :3:0003:0006[6485800ax_10050006x] sel.b32 r2.z, r1.z, r2.w, c1.y |
| :3:0004:0007[6485800bx_10040007x] sel.b32 r2.w, r1.w, r2.w, c1.x |
| :0:0005:0008[03000000x_00000000x] end |
| :0:0006:0009[00000000x_00000000x] nop |
| :0:0007:0010[00000000x_00000000x] nop |
| :0:0008:0011[00000000x_00000000x] nop |
| :0:0009:0012[00000000x_00000000x] nop |
| Register Stats: |
| - used (half): (cnt=0, max=0) |
| - used (full): 4-11 (cnt=8, max=11) |
| - used (merged): 8-23 (cnt=16, max=23) |
| - input (half): (cnt=0, max=0) |
| - input (full): 4-9 (cnt=6, max=9) |
| - max const: 5 |
| |
| - output (half): (cnt=0, max=0) (estimated) |
| - output (full): 8-11 (cnt=4, max=11) (estimated) |
| - shaderdb: 13 instructions, 7 nops, 6 non-nops, (10 instlen), 0 last-baryf, 0 half, 3 full |
| - shaderdb: 8 cat0, 0 cat1, 1 cat2, 4 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 |
| - shaderdb: 0 (ss), 0 (sy) |
| 00000000010541a4: 0000: 48a81c02 01054000 00000000 |
| t7 opcode: CP_LOAD_STATE6_GEOM (32) (4 dwords) |
| { DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_VS_SHADER | NUM_UNIT = 1 } |
| { EXT_SRC_ADDR = 0x1054000 } |
| { EXT_SRC_ADDR_HI = 0 } |
| :2:0000:0000[42bc080bx_00080009x] (nop3) cmps.s.eq r2.w, r2.y, r2.x |
| :3:0001:0004[64858008x_10040004x] sel.b32 r2.x, r1.x, r2.w, c1.x |
| :3:0002:0005[64858009x_10050005x] sel.b32 r2.y, r1.y, r2.w, c1.y |
| :3:0003:0006[6485800ax_10050006x] sel.b32 r2.z, r1.z, r2.w, c1.y |
| :3:0004:0007[6485800bx_10040007x] sel.b32 r2.w, r1.w, r2.w, c1.x |
| :0:0005:0008[03000000x_00000000x] end |
| :0:0006:0009[00000000x_00000000x] nop |
| :0:0007:0010[00000000x_00000000x] nop |
| :0:0008:0011[00000000x_00000000x] nop |
| :0:0009:0012[00000000x_00000000x] nop |
| Register Stats: |
| - used (half): (cnt=0, max=0) |
| - used (full): 4-11 (cnt=8, max=11) |
| - used (merged): 8-23 (cnt=16, max=23) |
| - input (half): (cnt=0, max=0) |
| - input (full): 4-9 (cnt=6, max=9) |
| - max const: 5 |
| |
| - output (half): (cnt=0, max=0) (estimated) |
| - output (full): 8-11 (cnt=4, max=11) (estimated) |
| - shaderdb: 13 instructions, 7 nops, 6 non-nops, (10 instlen), 0 last-baryf, 0 half, 3 full |
| - shaderdb: 8 cat0, 0 cat1, 1 cat2, 4 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 |
| - shaderdb: 0 (ss), 0 (sy) |
| 00000000010541b0: 0000: 70328003 00620000 01054000 00000000 |
| t7 opcode: CP_LOAD_STATE6_GEOM (32) (8 dwords) |
| { DST_OFF = 1 | STATE_TYPE = ST6_CONSTANTS | STATE_SRC = SS6_DIRECT | STATE_BLOCK = SB6_VS_SHADER | NUM_UNIT = 1 } |
| { EXT_SRC_ADDR = 0 } |
| { EXT_SRC_ADDR_HI = 0 } |
| 00000000010541d0: 1.000000 0.000000 -28026765312.000000 -28026765312.000000 |
| 00000000010541d0: 0000: 3f800000 00000000 d0d0d0d0 d0d0d0d0 |
| 00000000010541c0: 0000: 70320007 00604001 00000000 00000000 3f800000 00000000 d0d0d0d0 d0d0d0d0 |
| t4 write SP_HS_CONFIG (a83b) |
| SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } |
| 00000000010541e0: 0000: 48a83b01 00000000 |
| t4 write HLSQ_HS_CNTL (b801) |
| HLSQ_HS_CNTL: { CONSTLEN = 0 } |
| 00000000010541e8: 0000: 40b80101 00000000 |
| t4 write SP_DS_CONFIG (a863) |
| SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } |
| 00000000010541f0: 0000: 40a86301 00000000 |
| t4 write HLSQ_DS_CNTL (b802) |
| HLSQ_DS_CNTL: { CONSTLEN = 0 } |
| 00000000010541f8: 0000: 40b80201 00000000 |
| t4 write SP_GS_CONFIG (a894) |
| SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } |
| 0000000001054200: 0000: 48a89401 00000000 |
| t4 write HLSQ_GS_CNTL (b803) |
| HLSQ_GS_CNTL: { CONSTLEN = 0 } |
| 0000000001054208: 0000: 48b80301 00000000 |
| t4 write SP_FS_CTRL_REG0 (a980) |
| SP_FS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | BRANCHSTACK = 0 | THREADSIZE = FOUR_QUADS | VARYING | MERGEDREGS | 0x1000000 } |
| 0000000001054210: 0000: 40a98001 81500100 |
| t4 write SP_FS_CONFIG (ab04) |
| SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } |
| SP_FS_INSTRLEN: 1 |
| 0000000001054218: 0000: 48ab0402 00000100 00000001 |
| t4 write HLSQ_FS_CNTL (bb10) |
| HLSQ_FS_CNTL: { CONSTLEN = 0 | ENABLED } |
| 0000000001054224: 0000: 40bb1001 00000100 |
| t4 write SP_FS_OBJ_START_LO (a983) |
| SP_FS_OBJ_START_LO: 0x1054080 base=1054000, offset=128, size=12288 |
| SP_FS_OBJ_START_HI: 0 base=1054000, offset=128, size=12288 |
| 0000000001054080: 0000: 00002000 47300002 00002001 47300003 00002002 47300004 00002003 47308005 |
| 00000000010540a0: 0020: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000 |
| * |
| 0000000001054100: 0080: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000 |
| * |
| :2:0000:0000[47300002x_00002000x] bary.f r0.z, 0, r0.x |
| :2:0001:0001[47300003x_00002001x] bary.f r0.w, 1, r0.x |
| :2:0002:0002[47300004x_00002002x] bary.f r1.x, 2, r0.x |
| :2:0003:0003[47308005x_00002003x] bary.f (ei)r1.y, 3, r0.x |
| :0:0004:0004[03000000x_00000000x] end |
| :0:0005:0005[00000000x_00000000x] nop |
| :0:0006:0006[00000000x_00000000x] nop |
| :0:0007:0007[00000000x_00000000x] nop |
| :0:0008:0008[00000000x_00000000x] nop |
| Register Stats: |
| - used (half): (cnt=0, max=0) |
| - used (full): 0 2-5 (cnt=5, max=5) |
| - used (merged): 0-1 4-11 (cnt=10, max=11) |
| - input (half): (cnt=0, max=0) |
| - input (full): 0 (cnt=1, max=0) |
| - max const: 0 |
| |
| - output (half): (cnt=0, max=0) (estimated) |
| - output (full): 2-5 (cnt=4, max=5) (estimated) |
| - shaderdb: 9 instructions, 4 nops, 5 non-nops, (9 instlen), 3 last-baryf, 0 half, 2 full |
| - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 |
| - shaderdb: 0 (ss), 0 (sy) |
| 000000000105422c: 0000: 40a98302 01054080 00000000 |
| t7 opcode: CP_LOAD_STATE6_FRAG (34) (4 dwords) |
| { DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_FS_SHADER | NUM_UNIT = 1 } |
| { EXT_SRC_ADDR = 0x1054080 } |
| { EXT_SRC_ADDR_HI = 0 } |
| :2:0000:0000[47300002x_00002000x] bary.f r0.z, 0, r0.x |
| :2:0001:0001[47300003x_00002001x] bary.f r0.w, 1, r0.x |
| :2:0002:0002[47300004x_00002002x] bary.f r1.x, 2, r0.x |
| :2:0003:0003[47308005x_00002003x] bary.f (ei)r1.y, 3, r0.x |
| :0:0004:0004[03000000x_00000000x] end |
| :0:0005:0005[00000000x_00000000x] nop |
| :0:0006:0006[00000000x_00000000x] nop |
| :0:0007:0007[00000000x_00000000x] nop |
| :0:0008:0008[00000000x_00000000x] nop |
| Register Stats: |
| - used (half): (cnt=0, max=0) |
| - used (full): 0 2-5 (cnt=5, max=5) |
| - used (merged): 0-1 4-11 (cnt=10, max=11) |
| - input (half): (cnt=0, max=0) |
| - input (full): 0 (cnt=1, max=0) |
| - max const: 0 |
| |
| - output (half): (cnt=0, max=0) (estimated) |
| - output (full): 2-5 (cnt=4, max=5) (estimated) |
| - shaderdb: 9 instructions, 4 nops, 5 non-nops, (9 instlen), 3 last-baryf, 0 half, 2 full |
| - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 |
| - shaderdb: 0 (ss), 0 (sy) |
| 0000000001054238: 0000: 70348003 00720000 01054080 00000000 |
| t4 write SP_CS_CONFIG (a9bb) |
| SP_CS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } |
| 0000000001054248: 0000: 48a9bb01 00000000 |
| t4 write HLSQ_CS_CNTL (b987) |
| HLSQ_CS_CNTL: { CONSTLEN = 0 } |
| 0000000001054250: 0000: 40b98701 00000000 |
| t4 write SP_HS_UNKNOWN_A831 (a831) |
| SP_HS_UNKNOWN_A831: 0 |
| 0000000001054258: 0000: 48a83101 00000000 |
| t4 write VFD_CONTROL_1 (a001) |
| VFD_CONTROL_1: { REGID4VTX = r2.y | REGID4INST = r63.x | REGID4PRIMID = r63.x | 0xfc000000 } |
| VFD_CONTROL_2: { REGID_HSPATCHID = r63.x | REGID_INVOCATIONID = r63.x } |
| VFD_CONTROL_3: { REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x | 0xfc } |
| VFD_CONTROL_4: 0xfc |
| VFD_CONTROL_5: { REGID_GSHEADER = r63.x | 0xfc00 } |
| VFD_CONTROL_6: { 0 } |
| 0000000001054260: 0000: 40a00186 fcfcfc09 0000fcfc fcfcfcfc 000000fc 0000fcfc 00000000 |
| t4 write VPC_VAR[0].DISABLE (9212) |
| VPC_VAR[0].DISABLE: 0xfffffff0 |
| VPC_VAR[0x1].DISABLE: 0xffffffff |
| VPC_VAR[0x2].DISABLE: 0xffffffff |
| VPC_VAR[0x3].DISABLE: 0xffffffff |
| 000000000105427c: 0000: 40921204 fffffff0 ffffffff ffffffff ffffffff |
| t7 opcode: CP_CONTEXT_REG_BUNCH (5c) (5 dwords) |
| VPC_SO_CNTL: { 0 } |
| VPC_SO_BUF_CNTL: { 0 } |
| 0000000001054290: 0000: 70dc0004 00009216 00000000 00009305 00000000 |
| t4 write SP_VS_OUT[0].REG (a803) |
| SP_VS_OUT[0].REG: { A_REGID = r2.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0xf } |
| 00000000010542a4: 0000: 40a80301 0f000f08 |
| t4 write SP_VS_VPC_DST[0].REG (a813) |
| SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 4 | OUTLOC2 = 0 | OUTLOC3 = 0 } |
| 00000000010542ac: 0000: 48a81301 00000400 |
| t4 write VPC_VS_PACK (9301) |
| VPC_VS_PACK: { STRIDE_IN_VPC = 8 | POSITIONLOC = 4 | PSIZELOC = 255 } |
| 00000000010542b4: 0000: 40930101 00ff0408 |
| t4 write VPC_VS_CLIP_CNTL (9101) |
| VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 } |
| 00000000010542bc: 0000: 48910101 00ffff00 |
| t4 write GRAS_VS_CL_CNTL (8001) |
| GRAS_VS_CL_CNTL: { CLIP_MASK = 0 | CULL_MASK = 0 } |
| 00000000010542c4: 0000: 48800101 00000000 |
| t4 write PC_VS_OUT_CNTL (9b01) |
| PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 8 | CLIP_MASK = 0 } |
| 00000000010542cc: 0000: 489b0101 00000008 |
| t4 write SP_VS_PRIMITIVE_CNTL (a802) |
| SP_VS_PRIMITIVE_CNTL: { OUT = 2 } |
| 00000000010542d4: 0000: 48a80201 00000002 |
| t4 write VPC_VS_LAYER_CNTL (9104) |
| VPC_VS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 } |
| 00000000010542dc: 0000: 48910401 0000ffff |
| t4 write GRAS_VS_LAYER_CNTL (809b) |
| GRAS_VS_LAYER_CNTL: { 0 } |
| 00000000010542e4: 0000: 48809b01 00000000 |
| t4 write PC_PRIMID_PASSTHRU (9806) |
| PC_PRIMID_PASSTHRU: FALSE |
| 00000000010542ec: 0000: 40980601 00000000 |
| t4 write VPC_CNTL_0 (9304) |
| VPC_CNTL_0: { NUMNONPOSVAR = 4 | PRIMIDLOC = 255 | VARYING | UNKLOC = 255 } |
| 00000000010542f4: 0000: 40930401 ff01ff04 |
| t4 write VPC_VARYING_INTERP[0].MODE (9200) |
| VPC_VARYING_INTERP[0].MODE: 0 |
| VPC_VARYING_INTERP[0x1].MODE: 0 |
| VPC_VARYING_INTERP[0x2].MODE: 0 |
| VPC_VARYING_INTERP[0x3].MODE: 0 |
| VPC_VARYING_INTERP[0x4].MODE: 0 |
| VPC_VARYING_INTERP[0x5].MODE: 0 |
| VPC_VARYING_INTERP[0x6].MODE: 0 |
| VPC_VARYING_INTERP[0x7].MODE: 0 |
| 00000000010542fc: 0000: 40920008 00000000 00000000 00000000 00000000 00000000 00000000 00000000 |
| * |
| t4 write VPC_VARYING_PS_REPL[0].MODE (9208) |
| VPC_VARYING_PS_REPL[0].MODE: 0 |
| VPC_VARYING_PS_REPL[0x1].MODE: 0 |
| VPC_VARYING_PS_REPL[0x2].MODE: 0 |
| VPC_VARYING_PS_REPL[0x3].MODE: 0 |
| VPC_VARYING_PS_REPL[0x4].MODE: 0 |
| VPC_VARYING_PS_REPL[0x5].MODE: 0 |
| VPC_VARYING_PS_REPL[0x6].MODE: 0 |
| VPC_VARYING_PS_REPL[0x7].MODE: 0 |
| 0000000001054320: 0000: 48920808 00000000 00000000 00000000 00000000 00000000 00000000 00000000 |
| * |
| t4 write SP_FS_PREFETCH_CNTL (a99e) |
| SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK4 = r63.x | 0x7000 } |
| 0000000001054344: 0000: 40a99e01 00007fc0 |
| t4 write HLSQ_CONTROL_1_REG (b982) |
| HLSQ_CONTROL_1_REG: 0x7 |
| HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | SIZE = r63.x } |
| HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } |
| HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r63.x | ZWCOORDREGID = r63.x } |
| HLSQ_CONTROL_5_REG: 0xfc |
| 000000000105434c: 0000: 40b98285 00000007 fcfcfcfc fcfcfc00 fcfcfcfc 000000fc |
| t4 write HLSQ_UNKNOWN_B980 (b980) |
| HLSQ_UNKNOWN_B980: 0x3 |
| 0000000001054364: 0000: 48b98001 00000003 |
| t4 write GRAS_CNTL (8005) |
| GRAS_CNTL: { IJ_PERSP_PIXEL | COORD_MASK = 0 } |
| 000000000105436c: 0000: 40800501 00000001 |
| t4 write RB_RENDER_CONTROL0 (8809) |
| RB_RENDER_CONTROL0: { IJ_PERSP_PIXEL | COORD_MASK = 0 | UNK10 } |
| RB_RENDER_CONTROL1: { 0 } |
| 0000000001054374: 0000: 48880902 00000401 00000000 |
| t4 write RB_SAMPLE_CNTL (8810) |
| RB_SAMPLE_CNTL: { 0 } |
| 0000000001054380: 0000: 40881001 00000000 |
| t4 write GRAS_UNKNOWN_8101 (8101) |
| GRAS_UNKNOWN_8101: 0 |
| 0000000001054388: 0000: 40810101 00000000 |
| t4 write GRAS_SAMPLE_CNTL (8109) |
| GRAS_SAMPLE_CNTL: { 0 } |
| 0000000001054390: 0000: 48810901 00000000 |
| t4 write SP_FS_OUTPUT_CNTL0 (a98c) |
| SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x } |
| SP_FS_OUTPUT_CNTL1: { MRT = 1 } |
| 0000000001054398: 0000: 40a98c02 fcfcfc00 00000001 |
| t4 write SP_FS_OUTPUT[0].REG (a98e) |
| SP_FS_OUTPUT[0].REG: { REGID = r0.z } |
| SP_FS_OUTPUT[0x1].REG: { REGID = r63.x } |
| SP_FS_OUTPUT[0x2].REG: { REGID = r63.x } |
| SP_FS_OUTPUT[0x3].REG: { REGID = r63.x } |
| SP_FS_OUTPUT[0x4].REG: { REGID = r63.x } |
| SP_FS_OUTPUT[0x5].REG: { REGID = r63.x } |
| SP_FS_OUTPUT[0x6].REG: { REGID = r63.x } |
| SP_FS_OUTPUT[0x7].REG: { REGID = r63.x } |
| 00000000010543a4: 0000: 48a98e08 00000002 000000fc 000000fc 000000fc 000000fc 000000fc 000000fc |
| 00000000010543c4: 0020: 000000fc |
| t4 write SP_FS_RENDER_COMPONENTS (a98b) |
| SP_FS_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } |
| 00000000010543c8: 0000: 48a98b01 0000000f |
| t4 write RB_FS_OUTPUT_CNTL0 (880b) |
| RB_FS_OUTPUT_CNTL0: { 0 } |
| RB_FS_OUTPUT_CNTL1: { MRT = 1 } |
| 00000000010543d0: 0000: 40880b02 00000000 00000001 |
| t4 write RB_RENDER_COMPONENTS (880d) |
| RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } |
| 00000000010543dc: 0000: 40880d01 0000000f |
| t4 write GRAS_SU_DEPTH_PLANE_CNTL (8094) |
| GRAS_SU_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z } |
| 00000000010543e4: 0000: 48809401 00000000 |
| t4 write RB_DEPTH_PLANE_CNTL (8870) |
| RB_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z } |
| 00000000010543ec: 0000: 40887001 00000000 |
| group_id: 1 |
| count: 139 |
| addr: 00000000010543f4 |
| flags: 0 |
| enable_mask: 0x1 |
| skipped! |
| |
| group_id: 3 |
| count: 4 |
| addr: 000000000115c070 |
| flags: 0 |
| enable_mask: 0x7 |
| 000000000115c070: 0000: 40a01083 01053000 00000000 00000318 |
| t4 write VFD_FETCH[0].BASE (a010) |
| VFD_FETCH[0].BASE: 0x1053000 |
| VFD_FETCH[0].BASE+0x1: 0 |
| VFD_FETCH[0].SIZE: 792 |
| 000000000115c070: 0000: 40a01083 01053000 00000000 00000318 |
| group_id: 4 |
| count: 19 |
| addr: 0000000001054620 |
| flags: 0 |
| enable_mask: 0x6 |
| 0000000001054620: 0000: 40a01301 00000024 48a09002 c8200000 00000001 40a0d001 0000000f 40a09202 |
| 0000000001054640: 0020: c8200200 00000001 48a0d101 0000004f 40a09402 44c00400 00000001 48a0d201 |
| 0000000001054660: 0040: 00000081 48a00001 00000303 |
| t4 write VFD_FETCH[0].STRIDE (a013) |
| VFD_FETCH[0].STRIDE: 36 |
| 0000000001054620: 0000: 40a01301 00000024 |
| t4 write VFD_DECODE[0].INSTR (a090) |
| VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT } |
| VFD_DECODE[0].STEP_RATE: 0x1 |
| 0000000001054628: 0000: 48a09002 c8200000 00000001 |
| t4 write VFD_DEST_CNTL[0].INSTR (a0d0) |
| VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0xf | REGID = r0.x } |
| 0000000001054634: 0000: 40a0d001 0000000f |
| t4 write VFD_DECODE[0x1].INSTR (a092) |
| VFD_DECODE[0x1].INSTR: { IDX = 0 | OFFSET = 0x10 | FORMAT = FMT6_32_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT } |
| VFD_DECODE[0x1].STEP_RATE: 0x1 |
| 000000000105463c: 0000: 40a09202 c8200200 00000001 |
| t4 write VFD_DEST_CNTL[0x1].INSTR (a0d1) |
| VFD_DEST_CNTL[0x1].INSTR: { WRITEMASK = 0xf | REGID = r1.x } |
| 0000000001054648: 0000: 48a0d101 0000004f |
| t4 write VFD_DECODE[0x2].INSTR (a094) |
| VFD_DECODE[0x2].INSTR: { IDX = 0 | OFFSET = 0x20 | FORMAT = FMT6_32_SINT | SWAP = WZYX | UNK30 } |
| VFD_DECODE[0x2].STEP_RATE: 0x1 |
| 0000000001054650: 0000: 40a09402 44c00400 00000001 |
| t4 write VFD_DEST_CNTL[0x2].INSTR (a0d2) |
| VFD_DEST_CNTL[0x2].INSTR: { WRITEMASK = 0x1 | REGID = r2.x } |
| 000000000105465c: 0000: 48a0d201 00000081 |
| t4 write VFD_CONTROL_0 (a000) |
| VFD_CONTROL_0: { FETCH_CNT = 3 | DECODE_CNT = 3 } |
| 0000000001054664: 0000: 48a00001 00000303 |
| group_id: 5 |
| count: 19 |
| addr: 000000000105466c |
| flags: 0 |
| enable_mask: 0x1 |
| skipped! |
| |
| group_id: 6 |
| count: 9 |
| addr: 000000000105470c |
| flags: 0 |
| enable_mask: 0x7 |
| 000000000105470c: 0000: 40800001 000000c0 48910801 00000003 48998101 00000003 48809102 ffc00001 |
| 000000000105472c: 0020: 00000010 |
| t4 write GRAS_CL_CNTL (8000) |
| GRAS_CL_CNTL: { ZERO_GB_SCALE_Z | VP_CLIP_CODE_IGNORE } |
| 000000000105470c: 0000: 40800001 000000c0 |
| t4 write VPC_POLYGON_MODE (9108) |
| VPC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES } |
| 0000000001054714: 0000: 48910801 00000003 |
| t4 write PC_POLYGON_MODE (9981) |
| PC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES } |
| 000000000105471c: 0000: 48998101 00000003 |
| t4 write GRAS_SU_POINT_MINMAX (8091) |
| GRAS_SU_POINT_MINMAX: { MIN = 0.062500 | MAX = 4092.000000 } |
| GRAS_SU_POINT_SIZE: 1.000000 |
| 0000000001054724: 0000: 48809102 ffc00001 00000010 |
| group_id: 7 |
| count: 6 |
| addr: 0000000001054748 |
| flags: 0 |
| enable_mask: 0x7 |
| 0000000001054748: 0000: 40886401 00000000 48887101 00000000 40888001 00000000 |
| t4 write RB_ALPHA_CONTROL (8864) |
| RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_NEVER } |
| 0000000001054748: 0000: 40886401 00000000 |
| t4 write RB_DEPTH_CNTL (8871) |
| RB_DEPTH_CNTL: { ZFUNC = FUNC_NEVER } |
| 0000000001054750: 0000: 48887101 00000000 |
| t4 write RB_STENCIL_CONTROL (8880) |
| RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } |
| 0000000001054758: 0000: 40888001 00000000 |
| group_id: 8 |
| count: 7 |
| addr: 0000000001054784 |
| flags: 0 |
| enable_mask: 0x7 |
| 0000000001054784: 0000: 40882002 00000780 08040804 40a98901 00000100 48886501 ffff0100 |
| t4 write RB_MRT[0].CONTROL (8820) |
| RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } |
| RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_SRC_COLOR | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_DST_COLOR | ALPHA_SRC_FACTOR = FACTOR_SRC_COLOR | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_DST_COLOR } |
| 0000000001054784: 0000: 40882002 00000780 08040804 |
| t4 write SP_BLEND_CNTL (a989) |
| SP_BLEND_CNTL: { UNK8 } |
| 0000000001054790: 0000: 40a98901 00000100 |
| t4 write RB_BLEND_CNTL (8865) |
| RB_BLEND_CNTL: { ENABLE_BLEND = 0 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff } |
| 0000000001054798: 0000: 48886501 ffff0100 |
| group_id: 19 |
| count: 18 |
| addr: 00000000010546b8 |
| flags: 0 |
| enable_mask: 0x7 |
| 00000000010546b8: 0000: 48801086 43000000 43000000 43000000 43000000 00000000 3f800000 4880d002 |
| 00000000010546d8: 0020: 00000000 00ff00ff 40800601 0007fdff 48807002 00000000 3f800000 4888c002 |
| 00000000010546f8: 0040: 00000000 3f800000 |
| t4 write GRAS_CL_VPORT[0].XOFFSET (8010) |
| GRAS_CL_VPORT[0].XOFFSET: 128.000000 |
| GRAS_CL_VPORT[0].XSCALE: 128.000000 |
| GRAS_CL_VPORT[0].YOFFSET: 128.000000 |
| GRAS_CL_VPORT[0].YSCALE: 128.000000 |
| GRAS_CL_VPORT[0].ZOFFSET: 0.000000 |
| GRAS_CL_VPORT[0].ZSCALE: 1.000000 |
| 00000000010546b8: 0000: 48801086 43000000 43000000 43000000 43000000 00000000 3f800000 |
| t4 write GRAS_SC_VIEWPORT_SCISSOR[0].TL (80d0) |
| GRAS_SC_VIEWPORT_SCISSOR[0].TL: { X = 0 | Y = 0 } |
| GRAS_SC_VIEWPORT_SCISSOR[0].BR: { X = 255 | Y = 255 } |
| 00000000010546d4: 0000: 4880d002 00000000 00ff00ff |
| t4 write GRAS_CL_GUARDBAND_CLIP_ADJ (8006) |
| GRAS_CL_GUARDBAND_CLIP_ADJ: { HORZ = 511 | VERT = 511 } |
| 00000000010546e0: 0000: 40800601 0007fdff |
| t4 write GRAS_CL_Z_CLAMP[0].MIN (8070) |
| GRAS_CL_Z_CLAMP[0].MIN: 0.000000 |
| GRAS_CL_Z_CLAMP[0].MAX: 1.000000 |
| 00000000010546e8: 0000: 48807002 00000000 3f800000 |
| t4 write RB_Z_CLAMP_MIN (88c0) |
| RB_Z_CLAMP_MIN: 0.000000 |
| RB_Z_CLAMP_MAX: 1.000000 |
| 00000000010546f4: 0000: 4888c002 00000000 3f800000 |
| group_id: 20 |
| count: 3 |
| addr: 0000000001054700 |
| flags: 0 |
| enable_mask: 0x7 |
| 0000000001054700: 0000: 4880b002 00000000 00ff00ff |
| t4 write GRAS_SC_SCREEN_SCISSOR[0].TL (80b0) |
| GRAS_SC_SCREEN_SCISSOR[0].TL: { X = 0 | Y = 0 } |
| GRAS_SC_SCREEN_SCISSOR[0].BR: { X = 255 | Y = 255 } |
| 0000000001054700: 0000: 4880b002 00000000 00ff00ff |
| group_id: 21 |
| count: 2 |
| addr: 0000000001054730 |
| flags: 0 |
| enable_mask: 0x7 |
| 0000000001054730: 0000: 40809001 00000814 |
| t4 write GRAS_SU_CNTL (8090) |
| GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | POLY_OFFSET } |
| 0000000001054730: 0000: 40809001 00000814 |
| group_id: 22 |
| count: 4 |
| addr: 0000000001054738 |
| flags: 0 |
| enable_mask: 0x7 |
| 0000000001054738: 0000: 40809583 00000000 00000000 00000000 |
| t4 write GRAS_SU_POLY_OFFSET_SCALE (8095) |
| GRAS_SU_POLY_OFFSET_SCALE: 0.000000 |
| GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 |
| GRAS_SU_POLY_OFFSET_OFFSET_CLAMP: 0.000000 |
| 0000000001054738: 0000: 40809583 00000000 00000000 00000000 |
| group_id: 23 |
| count: 5 |
| addr: 00000000010547a0 |
| flags: 0 |
| enable_mask: 0x7 |
| 00000000010547a0: 0000: 48886004 dffe8440 0000ffff dffe8678 0000ffff |
| t4 write RB_BLEND_RED_F32 (8860) |
| RB_BLEND_RED_F32: -36679707902607360000.000000 |
| RB_BLEND_GREEN_F32: 0.000000 |
| RB_BLEND_BLUE_F32: -36680956947816513536.000000 |
| RB_BLEND_ALPHA_F32: 0.000000 |
| 00000000010547a0: 0000: 48886004 dffe8440 0000ffff dffe8678 0000ffff |
| group_id: 24 |
| count: 3 |
| addr: 0000000001054760 |
| flags: 0 |
| enable_mask: 0x7 |
| 0000000001054760: 0000: 48887802 00000000 00000000 |
| t4 write RB_Z_BOUNDS_MIN (8878) |
| RB_Z_BOUNDS_MIN: 0.000000 |
| RB_Z_BOUNDS_MAX: 0.000000 |
| 0000000001054760: 0000: 48887802 00000000 00000000 |
| group_id: 25 |
| count: 2 |
| addr: 000000000105476c |
| flags: 0 |
| enable_mask: 0x7 |
| 000000000105476c: 0000: 48888801 00000000 |
| t4 write RB_STENCILMASK (8888) |
| RB_STENCILMASK: { MASK = 0 | BFMASK = 0 } |
| 000000000105476c: 0000: 48888801 00000000 |
| group_id: 26 |
| count: 2 |
| addr: 0000000001054774 |
| flags: 0 |
| enable_mask: 0x7 |
| 0000000001054774: 0000: 40888901 00000000 |
| t4 write RB_STENCILWRMASK (8889) |
| RB_STENCILWRMASK: { WRMASK = 0 | BFWRMASK = 0 } |
| 0000000001054774: 0000: 40888901 00000000 |
| group_id: 27 |
| count: 2 |
| addr: 000000000105477c |
| flags: 0 |
| enable_mask: 0x7 |
| 000000000105477c: 0000: 48888701 00000000 |
| t4 write RB_STENCILREF (8887) |
| RB_STENCILREF: { REF = 0 | BFREF = 0 } |
| 000000000105477c: 0000: 48888701 00000000 |
| group_id: 28 |
| count: 6 |
| addr: 00000000010547b4 |
| flags: 0 |
| enable_mask: 0x7 |
| 00000000010547b4: 0000: 4880a401 00000000 40880401 00000000 48b30401 00000000 |
| t4 write GRAS_SAMPLE_CONFIG (80a4) |
| GRAS_SAMPLE_CONFIG: { 0 } |
| 00000000010547b4: 0000: 4880a401 00000000 |
| t4 write RB_SAMPLE_CONFIG (8804) |
| RB_SAMPLE_CONFIG: { 0 } |
| 00000000010547bc: 0000: 40880401 00000000 |
| t4 write SP_TP_SAMPLE_CONFIG (b304) |
| SP_TP_SAMPLE_CONFIG: { 0 } |
| 00000000010547c4: 0000: 48b30401 00000000 |
| t7 opcode: CP_DRAW_INDIRECT_MULTI (2a) (12 dwords) |
| { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS } |
| { OPCODE = INDIRECT_OP_INDIRECT_COUNT_INDEXED | DST_OFF = 0 } |
| { DRAW_COUNT = 3 } |
| { INDEX = 0x1057000 } |
| { MAX_INDICES = 9 } |
| { INDIRECT = 0x1162008 } |
| { INDIRECT_COUNT = 0x116300c } |
| { STRIDE = 40 } |
| mode: RM6_GMEM |
| skip_ib2: g=0, l=0 |
| indirect count: 2 |
| draw 0: |
| 0000000001162008: 0000: 00000003 00000001 00000002 0000000d 00000000 fffffffc fffffffe fffffff5 |
| 0000000001162028: 0020: 00000009 fffffff9 00000003 00000001 00000005 0000000d 00000000 fffffffc |
| draw 1: |
| 0000000001162030: 0000: 00000003 00000001 00000005 0000000d 00000000 fffffffc fffffffe fffffff5 |
| 0000000001162050: 0020: 00000009 fffffff9 fffffffc fffffffe fffffff5 00000009 fffffff9 fffffffc |
| draw[2] register values |
| !+ 000000c0 GRAS_CL_CNTL: { ZERO_GB_SCALE_Z | VP_CLIP_CODE_IGNORE } |
| + 00000000 GRAS_VS_CL_CNTL: { CLIP_MASK = 0 | CULL_MASK = 0 } |
| + 00000000 GRAS_MAX_LAYER_INDEX: 0 |
| !+ 00000001 GRAS_CNTL: { IJ_PERSP_PIXEL | COORD_MASK = 0 } |
| !+ 0007fdff GRAS_CL_GUARDBAND_CLIP_ADJ: { HORZ = 511 | VERT = 511 } |
| !+ 43000000 GRAS_CL_VPORT[0].XOFFSET: 128.000000 |
| !+ 43000000 GRAS_CL_VPORT[0].XSCALE: 128.000000 |
| !+ 43000000 GRAS_CL_VPORT[0].YOFFSET: 128.000000 |
| !+ 43000000 GRAS_CL_VPORT[0].YSCALE: 128.000000 |
| + 00000000 GRAS_CL_VPORT[0].ZOFFSET: 0.000000 |
| !+ 3f800000 GRAS_CL_VPORT[0].ZSCALE: 1.000000 |
| + 00000000 GRAS_CL_Z_CLAMP[0].MIN: 0.000000 |
| !+ 3f800000 GRAS_CL_Z_CLAMP[0].MAX: 1.000000 |
| !+ 00000814 GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | POLY_OFFSET } |
| !+ ffc00001 GRAS_SU_POINT_MINMAX: { MIN = 0.062500 | MAX = 4092.000000 } |
| !+ 00000010 GRAS_SU_POINT_SIZE: 1.000000 |
| + 00000000 GRAS_SU_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z } |
| + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000 |
| + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000 |
| + 00000000 GRAS_SU_POLY_OFFSET_OFFSET_CLAMP: 0.000000 |
| + 00000000 GRAS_SU_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE } |
| + 00000000 GRAS_VS_LAYER_CNTL: { 0 } |
| + 00000000 GRAS_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } |
| !+ 00000004 GRAS_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE } |
| + 00000000 GRAS_SAMPLE_CONFIG: { 0 } |
| + 00000000 GRAS_SC_SCREEN_SCISSOR[0].TL: { X = 0 | Y = 0 } |
| !+ 00ff00ff GRAS_SC_SCREEN_SCISSOR[0].BR: { X = 255 | Y = 255 } |
| + 00000000 GRAS_SC_VIEWPORT_SCISSOR[0].TL: { X = 0 | Y = 0 } |
| !+ 00ff00ff GRAS_SC_VIEWPORT_SCISSOR[0].BR: { X = 255 | Y = 255 } |
| + 00000000 GRAS_UNKNOWN_8101: 0 |
| + 00000000 GRAS_LRZ_BUFFER_BASE_LO: 0 |
| + 00000000 GRAS_LRZ_BUFFER_BASE_HI: 0 |
| + 00000000 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } |
| + 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO: 0 |
| + 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0 |
| + 00000000 GRAS_SAMPLE_CNTL: { 0 } |
| !+ 00010010 RB_RENDER_CNTL: { UNK4 | FLAG_MRTS = 0x1 } |
| + 00000000 RB_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } |
| !+ 00000004 RB_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE } |
| + 00000000 RB_SAMPLE_CONFIG: { 0 } |
| + 00000401 RB_RENDER_CONTROL0: { IJ_PERSP_PIXEL | COORD_MASK = 0 | UNK10 } |
| + 00000000 RB_RENDER_CONTROL1: { 0 } |
| + 00000000 RB_FS_OUTPUT_CNTL0: { 0 } |
| !+ 00000001 RB_FS_OUTPUT_CNTL1: { MRT = 1 } |
| !+ 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } |
| + 00000000 RB_SRGB_CNTL: { 0 } |
| + 00000000 RB_SAMPLE_CNTL: { 0 } |
| !+ 00000780 RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf } |
| !+ 08040804 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_SRC_COLOR | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_DST_COLOR | ALPHA_SRC_FACTOR = FACTOR_SRC_COLOR | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_DST_COLOR } |
| !+ 00000330 RB_MRT[0].BUF_INFO: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | COLOR_TILE_MODE = TILE6_3 | COLOR_SWAP = WZYX } |
| !+ 00000010 RB_MRT[0].PITCH: 1024 |
| !+ 00001000 RB_MRT[0].ARRAY_PITCH: 262144 |
| !+ 01013000 RB_MRT[0].BASE_LO: 0x1013000 |
| + 00000000 RB_MRT[0].BASE_HI: 0 |
| + 00000000 RB_MRT[0].BASE_GMEM: 0 |
| !+ dffe8440 RB_BLEND_RED_F32: -36679707902607360000.000000 |
| !+ 0000ffff RB_BLEND_GREEN_F32: 0.000000 |
| !+ dffe8678 RB_BLEND_BLUE_F32: -36680956947816513536.000000 |
| !+ 0000ffff RB_BLEND_ALPHA_F32: 0.000000 |
| + 00000000 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_NEVER } |
| !+ ffff0100 RB_BLEND_CNTL: { ENABLE_BLEND = 0 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff } |
| + 00000000 RB_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z } |
| + 00000000 RB_DEPTH_CNTL: { ZFUNC = FUNC_NEVER } |
| + 00000000 RB_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE } |
| + 00000000 RB_DEPTH_BUFFER_PITCH: 0 |
| + 00000000 RB_DEPTH_BUFFER_ARRAY_PITCH: 0 |
| + 00000000 RB_DEPTH_BUFFER_BASE_LO: 0 |
| + 00000000 RB_DEPTH_BUFFER_BASE_HI: 0 |
| + 00000000 RB_DEPTH_BUFFER_BASE_GMEM: 0 |
| + 00000000 RB_Z_BOUNDS_MIN: 0.000000 |
| + 00000000 RB_Z_BOUNDS_MAX: 0.000000 |
| + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP } |
| + 00000000 RB_STENCIL_INFO: { 0 } |
| + 00000000 RB_STENCILREF: { REF = 0 | BFREF = 0 } |
| + 00000000 RB_STENCILMASK: { MASK = 0 | BFMASK = 0 } |
| + 00000000 RB_STENCILWRMASK: { WRMASK = 0 | BFWRMASK = 0 } |
| + 00000000 RB_Z_CLAMP_MIN: 0.000000 |
| !+ 3f800000 RB_Z_CLAMP_MAX: 1.000000 |
| + 00000000 RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 } |
| + 00ff00ff RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 } |
| + 00000000 RB_MSAA_CNTL: { SAMPLES = MSAA_ONE } |
| !+ 01012000 RB_MRT_FLAG_BUFFER[0].ADDR_LO: 0x1012000 |
| + 00000000 RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0 |
| !+ 00004001 RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 } |
| !+ 00ffff00 VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 } |
| !+ 0000ffff VPC_VS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 } |
| !+ 00000003 VPC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES } |
| + 00000000 VPC_VARYING_INTERP[0].MODE: 0 |
| + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0 |
| + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0 |
| + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0 |
| + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0 |
| + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0 |
| + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0 |
| + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0 |
| + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0 |
| + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0 |
| + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0 |
| + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0 |
| + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0 |
| + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0 |
| + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0 |
| + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0 |
| !+ fffffff0 VPC_VAR[0].DISABLE: 0xfffffff0 |
| !+ ffffffff VPC_VAR[0x1].DISABLE: 0xffffffff |
| !+ ffffffff VPC_VAR[0x2].DISABLE: 0xffffffff |
| !+ ffffffff VPC_VAR[0x3].DISABLE: 0xffffffff |
| + 00000000 VPC_SO_CNTL: { 0 } |
| !+ 00ff0408 VPC_VS_PACK: { STRIDE_IN_VPC = 8 | POSITIONLOC = 4 | PSIZELOC = 255 } |
| !+ ff01ff04 VPC_CNTL_0: { NUMNONPOSVAR = 4 | PRIMIDLOC = 255 | VARYING | UNKLOC = 255 } |
| + 00000000 VPC_SO_BUF_CNTL: { 0 } |
| !+ ffffffff PC_RESTART_INDEX: 4294967295 |
| + 00000000 PC_PRIMID_PASSTHRU: FALSE |
| !+ 00000003 PC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES } |
| + 00000000 PC_PRIMITIVE_CNTL_0: { 0 } |
| !+ 00000008 PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 8 | CLIP_MASK = 0 } |
| !+ 00000303 VFD_CONTROL_0: { FETCH_CNT = 3 | DECODE_CNT = 3 } |
| !+ fcfcfc09 VFD_CONTROL_1: { REGID4VTX = r2.y | REGID4INST = r63.x | REGID4PRIMID = r63.x | 0xfc000000 } |
| !+ 0000fcfc VFD_CONTROL_2: { REGID_HSPATCHID = r63.x | REGID_INVOCATIONID = r63.x } |
| !+ fcfcfcfc VFD_CONTROL_3: { REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x | 0xfc } |
| !+ 000000fc VFD_CONTROL_4: 0xfc |
| !+ 0000fcfc VFD_CONTROL_5: { REGID_GSHEADER = r63.x | 0xfc00 } |
| + 00000000 VFD_CONTROL_6: { 0 } |
| !+ 01053000 VFD_FETCH[0].BASE: 0x1053000 |
| + 00000000 VFD_FETCH[0].BASE+0x1: 0 |
| !+ 00000318 VFD_FETCH[0].SIZE: 792 |
| !+ 00000024 VFD_FETCH[0].STRIDE: 36 |
| !+ c8200000 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT } |
| !+ 00000001 VFD_DECODE[0].STEP_RATE: 0x1 |
| !+ c8200200 VFD_DECODE[0x1].INSTR: { IDX = 0 | OFFSET = 0x10 | FORMAT = FMT6_32_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT } |
| !+ 00000001 VFD_DECODE[0x1].STEP_RATE: 0x1 |
| !+ 44c00400 VFD_DECODE[0x2].INSTR: { IDX = 0 | OFFSET = 0x20 | FORMAT = FMT6_32_SINT | SWAP = WZYX | UNK30 } |
| !+ 00000001 VFD_DECODE[0x2].STEP_RATE: 0x1 |
| !+ 0000000f VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0xf | REGID = r0.x } |
| !+ 0000004f VFD_DEST_CNTL[0x1].INSTR: { WRITEMASK = 0xf | REGID = r1.x } |
| !+ 00000081 VFD_DEST_CNTL[0x2].INSTR: { WRITEMASK = 0x1 | REGID = r2.x } |
| !+ 80100180 SP_VS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 3 | BRANCHSTACK = 0 | THREADSIZE = FOUR_QUADS | MERGEDREGS } |
| !+ 00000002 SP_VS_PRIMITIVE_CNTL: { OUT = 2 } |
| !+ 0f000f08 SP_VS_OUT[0].REG: { A_REGID = r2.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0xf } |
| !+ 00000400 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 4 | OUTLOC2 = 0 | OUTLOC3 = 0 } |
| !+ 01054000 SP_VS_OBJ_START_LO: 0x1054000 base=1054000, offset=0, size=12288 |
| + 00000000 SP_VS_OBJ_START_HI: 0 base=1054000, offset=0, size=12288 |
| 0000000001054000: 0000: 00080009 42bc080b 10040004 64858008 10050005 64858009 10050006 6485800a |
| 0000000001054020: 0020: 10040007 6485800b 00000000 03000000 00000000 00000000 00000000 00000000 |
| * |
| 0000000001054080: 0080: 00002000 47300002 00002001 47300003 00002002 47300004 00002003 47308005 |
| 00000000010540a0: 00a0: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000 |
| * |
| :2:0000:0000[42bc080bx_00080009x] (nop3) cmps.s.eq r2.w, r2.y, r2.x |
| :3:0001:0004[64858008x_10040004x] sel.b32 r2.x, r1.x, r2.w, c1.x |
| :3:0002:0005[64858009x_10050005x] sel.b32 r2.y, r1.y, r2.w, c1.y |
| :3:0003:0006[6485800ax_10050006x] sel.b32 r2.z, r1.z, r2.w, c1.y |
| :3:0004:0007[6485800bx_10040007x] sel.b32 r2.w, r1.w, r2.w, c1.x |
| :0:0005:0008[03000000x_00000000x] end |
| :0:0006:0009[00000000x_00000000x] nop |
| :0:0007:0010[00000000x_00000000x] nop |
| :0:0008:0011[00000000x_00000000x] nop |
| :0:0009:0012[00000000x_00000000x] nop |
| Register Stats: |
| - used (half): (cnt=0, max=0) |
| - used (full): 4-11 (cnt=8, max=11) |
| - used (merged): 8-23 (cnt=16, max=23) |
| - input (half): (cnt=0, max=0) |
| - input (full): 4-9 (cnt=6, max=9) |
| - max const: 5 |
| |
| - output (half): (cnt=0, max=0) (estimated) |
| - output (full): 8-11 (cnt=4, max=11) (estimated) |
| - shaderdb: 13 instructions, 7 nops, 6 non-nops, (10 instlen), 0 last-baryf, 0 half, 3 full |
| - shaderdb: 8 cat0, 0 cat1, 1 cat2, 4 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 |
| - shaderdb: 0 (ss), 0 (sy) |
| !+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } |
| !+ 00000001 SP_VS_INSTRLEN: 1 |
| + 00000000 SP_HS_UNKNOWN_A831: 0 |
| + 00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } |
| + 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } |
| + 00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } |
| !+ 81500100 SP_FS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | BRANCHSTACK = 0 | THREADSIZE = FOUR_QUADS | VARYING | MERGEDREGS | 0x1000000 } |
| !+ 01054080 SP_FS_OBJ_START_LO: 0x1054080 base=1054000, offset=128, size=12288 |
| + 00000000 SP_FS_OBJ_START_HI: 0 base=1054000, offset=128, size=12288 |
| 0000000001054080: 0000: 00002000 47300002 00002001 47300003 00002002 47300004 00002003 47308005 |
| 00000000010540a0: 0020: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000 |
| * |
| 0000000001054100: 0080: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000 |
| * |
| :2:0000:0000[47300002x_00002000x] bary.f r0.z, 0, r0.x |
| :2:0001:0001[47300003x_00002001x] bary.f r0.w, 1, r0.x |
| :2:0002:0002[47300004x_00002002x] bary.f r1.x, 2, r0.x |
| :2:0003:0003[47308005x_00002003x] bary.f (ei)r1.y, 3, r0.x |
| :0:0004:0004[03000000x_00000000x] end |
| :0:0005:0005[00000000x_00000000x] nop |
| :0:0006:0006[00000000x_00000000x] nop |
| :0:0007:0007[00000000x_00000000x] nop |
| :0:0008:0008[00000000x_00000000x] nop |
| Register Stats: |
| - used (half): (cnt=0, max=0) |
| - used (full): 0 2-5 (cnt=5, max=5) |
| - used (merged): 0-1 4-11 (cnt=10, max=11) |
| - input (half): (cnt=0, max=0) |
| - input (full): 0 (cnt=1, max=0) |
| - max const: 0 |
| |
| - output (half): (cnt=0, max=0) (estimated) |
| - output (full): 2-5 (cnt=4, max=5) (estimated) |
| - shaderdb: 9 instructions, 4 nops, 5 non-nops, (9 instlen), 3 last-baryf, 0 half, 2 full |
| - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 |
| - shaderdb: 0 (ss), 0 (sy) |
| !+ 00000100 SP_BLEND_CNTL: { UNK8 } |
| + 00000000 SP_SRGB_CNTL: { 0 } |
| !+ 0000000f SP_FS_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } |
| !+ fcfcfc00 SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x } |
| !+ 00000001 SP_FS_OUTPUT_CNTL1: { MRT = 1 } |
| !+ 00000002 SP_FS_OUTPUT[0].REG: { REGID = r0.z } |
| !+ 000000fc SP_FS_OUTPUT[0x1].REG: { REGID = r63.x } |
| !+ 000000fc SP_FS_OUTPUT[0x2].REG: { REGID = r63.x } |
| !+ 000000fc SP_FS_OUTPUT[0x3].REG: { REGID = r63.x } |
| !+ 000000fc SP_FS_OUTPUT[0x4].REG: { REGID = r63.x } |
| !+ 000000fc SP_FS_OUTPUT[0x5].REG: { REGID = r63.x } |
| !+ 000000fc SP_FS_OUTPUT[0x6].REG: { REGID = r63.x } |
| !+ 000000fc SP_FS_OUTPUT[0x7].REG: { REGID = r63.x } |
| !+ 00000030 SP_FS_MRT[0].REG: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM } |
| !+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK4 = r63.x | 0x7000 } |
| + 00000000 SP_CS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } |
| !+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } |
| !+ 00000001 SP_FS_INSTRLEN: 1 |
| + 00000000 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } |
| !+ 00000004 SP_TP_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE } |
| + 00000000 SP_TP_SAMPLE_CONFIG: { 0 } |
| !+ 00000101 HLSQ_VS_CNTL: { CONSTLEN = 4 | ENABLED } |
| + 00000000 HLSQ_HS_CNTL: { CONSTLEN = 0 } |
| + 00000000 HLSQ_DS_CNTL: { CONSTLEN = 0 } |
| + 00000000 HLSQ_GS_CNTL: { CONSTLEN = 0 } |
| !+ 00000003 HLSQ_UNKNOWN_B980: 0x3 |
| !+ 00000007 HLSQ_CONTROL_1_REG: 0x7 |
| !+ fcfcfcfc HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | SIZE = r63.x } |
| !+ fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x } |
| !+ fcfcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r63.x | ZWCOORDREGID = r63.x } |
| + 000000fc HLSQ_CONTROL_5_REG: 0xfc |
| + 00000000 HLSQ_CS_CNTL: { CONSTLEN = 0 } |
| !+ 0000009f HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 } |
| !+ 00000100 HLSQ_FS_CNTL: { CONSTLEN = 0 | ENABLED } |
| 000000000115e394: 0000: 702a000b 00000904 00000007 00000003 01057000 00000000 00000009 01162008 |
| 000000000115e3b4: 0020: 00000000 0116300c 00000000 00000028 |
| 00000000010583b8: 0000: 70bf8003 0115e000 00000000 000000f1 |
| t7 opcode: CP_INDIRECT_BUFFER (3f) (4 dwords) |
| ibaddr:000000000115c000 |
| ibsize:0000001c |
| t7 opcode: CP_SET_DRAW_STATE (43) (4 dwords) |
| { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 } |
| { ADDR_LO = 0 } |
| { ADDR_HI = 0 } |
| 000000000115c000: 0000: 70438003 00040000 00000000 00000000 |
| t7 opcode: CP_SKIP_IB2_ENABLE_GLOBAL (1d) (2 dwords) |
| 000000000115c010: 0000: 709d0001 00000000 |
| t7 opcode: CP_SET_MARKER (65) (2 dwords) |
| { MODE = RM6_RESOLVE | MARKER = RM6_RESOLVE } |
| 000000000115c018: 0000: 70e50001 00000006 |
| t4 write RB_BLIT_SCISSOR_TL (88d1) |
| RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 } |
| RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 } |
| 000000000115c020: 0000: 4888d102 00000000 00ff00ff |
| t4 write RB_MSAA_CNTL (88d5) |
| RB_MSAA_CNTL: { SAMPLES = MSAA_ONE } |
| 000000000115c02c: 0000: 4088d501 00000000 |
| t4 write RB_BLIT_INFO (88e3) |
| RB_BLIT_INFO: { CLEAR_MASK = 0 } |
| 000000000115c034: 0000: 4088e301 00000000 |
| t4 write RB_BLIT_DST_INFO (88d7) |
| RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM } |
| RB_BLIT_DST: 0x1013000 |
| RB_BLIT_DST+0x1: 0 |
| RB_BLIT_DST_PITCH: 1024 |
| 000000000115c03c: 0000: 4888d704 00001807 01013000 00000000 00000010 |
| t4 write RB_BLIT_FLAG_DST (88dc) |
| RB_BLIT_FLAG_DST: 0x1012000 |
| RB_BLIT_FLAG_DST+0x1: 0 |
| RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 } |
| 000000000115c050: 0000: 4088dc83 01012000 00000000 00004001 |
| t4 write RB_BLIT_BASE_GMEM (88d6) |
| RB_BLIT_BASE_GMEM: 0 |
| 000000000115c060: 0000: 4088d601 00000000 |
| t7 opcode: CP_EVENT_WRITE (46) (2 dwords) |
| { EVENT = BLIT } |
| event BLIT |
| mode: RM6_RESOLVE |
| skip_ib2: g=0, l=0 |
| draw[3] register values |
| + 00000000 RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 } |
| + 00ff00ff RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 } |
| + 00000000 RB_MSAA_CNTL: { SAMPLES = MSAA_ONE } |
| + 00000000 RB_BLIT_BASE_GMEM: 0 |
| + 00001807 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM } |
| + 01013000 RB_BLIT_DST: 0x1013000 |
| + 00000000 RB_BLIT_DST+0x1: 0 |
| + 00000010 RB_BLIT_DST_PITCH: 1024 |
| + 01012000 RB_BLIT_FLAG_DST: 0x1012000 |
| + 00000000 RB_BLIT_FLAG_DST+0x1: 0 |
| + 00004001 RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 } |
| !+ 00000000 RB_BLIT_INFO: { CLEAR_MASK = 0 } |
| 000000000115c068: 0000: 70460001 0000001e |
| 00000000010583c8: 0000: 70bf8003 0115c000 00000000 0000001c |
| t4 write GRAS_LRZ_CNTL (8100) |
| GRAS_LRZ_CNTL: { 0 } |
| 00000000010583d8: 0000: 48810001 00000000 |
| t7 opcode: CP_EVENT_WRITE (46) (2 dwords) |
| { EVENT = LRZ_FLUSH } |
| event LRZ_FLUSH |
| 00000000010583e0: 0000: 70460001 00000026 |
| t7 opcode: CP_EVENT_WRITE (46) (5 dwords) |
| { EVENT = PC_CCU_RESOLVE_TS } |
| { ADDR_0_LO = 0x1011880 } |
| { ADDR_0_HI = 0 } |
| { 3 = 0 } |
| event PC_CCU_RESOLVE_TS |
| 00000000010583e8: 0000: 70460004 0000001a 01011880 00000000 00000000 |
| t7 opcode: CP_EVENT_WRITE (46) (5 dwords) |
| { EVENT = PC_CCU_FLUSH_COLOR_TS } |
| { ADDR_0_LO = 0x1011880 } |
| { ADDR_0_HI = 0 } |
| { 3 = 0 } |
| event PC_CCU_FLUSH_COLOR_TS |
| 00000000010583fc: 0000: 70460004 0000001d 01011880 00000000 00000000 |
| t7 opcode: CP_EVENT_WRITE (46) (5 dwords) |
| { EVENT = PC_CCU_FLUSH_DEPTH_TS } |
| { ADDR_0_LO = 0x1011880 } |
| { ADDR_0_HI = 0 } |
| { 3 = 0 } |
| event PC_CCU_FLUSH_DEPTH_TS |
| 0000000001058410: 0000: 70460004 0000001c 01011880 00000000 00000000 |
| ############################################################ |
| vertices: 0 |
| cmd: deqp-vk/74711: fence=247338 |
