commit ad513fd386bf14b66a5b775e84a8ca32e8f8e3e8
author Rafael Antognolli <rafael.antognolli@intel.com> Mon Jul 01 13:34:08 2019 -0700
committer Rafael Antognolli <rafael.antognolli@intel.com> Mon Aug 12 16:19:08 2019 -0700
tree 72c544b62b68393924e86c171a86b2ea998a8579
parent 32344dc5811021409f04db50f461582c05aa6a80

intel: Get information about pixel pipes subslices.

v2: Use 1 instead of 1UL (Ken).

src/intel/dev/gen_device_info.c

diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c
index cbe5500..3953a1f 100644
--- a/src/intel/dev/gen_device_info.c
+++ b/src/intel/dev/gen_device_info.c
@@ -1073,6 +1073,7 @@
    memset(&devinfo->slice_masks, 0, sizeof(devinfo->slice_masks));
    memset(devinfo->subslice_masks, 0, sizeof(devinfo->subslice_masks));
    memset(devinfo->eu_masks, 0, sizeof(devinfo->eu_masks));
+   memset(devinfo->ppipe_subslices, 0, sizeof(devinfo->ppipe_subslices));
 }
 
 static void
@@ -1098,7 +1099,7 @@
 
    uint32_t n_subslices = 0;
    for (int s = 0; s < topology->max_slices; s++) {
-      if ((devinfo->slice_masks & (1UL << s)) == 0)
+      if ((devinfo->slice_masks & (1 << s)) == 0)
          continue;
 
       for (int b = 0; b < devinfo->subslice_slice_stride; b++) {
@@ -1109,6 +1110,23 @@
    }
    assert(n_subslices > 0);
 
+   if (devinfo->gen == 11) {
+      /* On ICL we only have one slice */
+      assert(devinfo->slice_masks == 1);
+
+      /* Count the number of subslices on each pixel pipe. Assume that
+       * subslices 0-3 are on pixel pipe 0, and 4-7 are on pixel pipe 1.
+       */
+      unsigned subslices = devinfo->subslice_masks[0];
+      unsigned ss = 0;
+      while (subslices > 0) {
+         if (subslices & 1)
+            devinfo->ppipe_subslices[ss >= 4 ? 1 : 0] += 1;
+         subslices >>= 1;
+         ss++;
+      }
+   }
+
    uint32_t eu_mask_len =
       topology->eu_stride * topology->max_subslices * topology->max_slices;
    assert(sizeof(devinfo->eu_masks) >= eu_mask_len);

src/intel/dev/gen_device_info.h

diff --git a/src/intel/dev/gen_device_info.h b/src/intel/dev/gen_device_info.h
index 57f1495..ea34468 100644
--- a/src/intel/dev/gen_device_info.h
+++ b/src/intel/dev/gen_device_info.h
@@ -39,6 +39,7 @@
 #define GEN_DEVICE_MAX_SLICES           (6)  /* Maximum on gen10 */
 #define GEN_DEVICE_MAX_SUBSLICES        (8)  /* Maximum on gen11 */
 #define GEN_DEVICE_MAX_EUS_PER_SUBSLICE (10) /* Maximum on Haswell */
+#define GEN_DEVICE_MAX_PIXEL_PIPES      (2)  /* Maximum on gen11 */
 
 /**
  * Intel hardware information and quirks
@@ -125,6 +126,11 @@
    unsigned num_subslices[GEN_DEVICE_MAX_SUBSLICES];
 
    /**
+    * Number of subslices on each pixel pipe (ICL).
+    */
+   unsigned ppipe_subslices[GEN_DEVICE_MAX_PIXEL_PIPES];
+
+   /**
     * Upper bound of number of EU per subslice (some SKUs might have just 1 EU
     * fused across all subslices, like 47 EUs, in which case this number won't
     * be acurate for one subslice).