commit a1b237b9ef684ef1684508921c70259c35ff8463
author Samuel Pitoiset <samuel.pitoiset@gmail.com> Thu Jul 09 10:33:16 2020 +0200
committer Marge Bot <eric+marge@anholt.net> Fri Jul 24 12:30:03 2020 +0000
tree cf10eeb2fa915e40797410afc28065c3a5d3f32d
parent cf89bdb9ba9c7a7ba39d142ee3c83e0379c2092a

radv: set LDS TCS size at shaders creation for GFX9+

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5837>

src/amd/vulkan/radv_pipeline.c

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index e598ddb..bc1b1c1 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -4054,20 +4054,11 @@
 static void
 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
 			     struct radv_pipeline *pipeline,
-			     struct radv_shader_variant *shader,
-			     const struct radv_tessellation_state *tess)
+			     struct radv_shader_variant *shader)
 {
 	uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
 
 	if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
-		unsigned hs_rsrc2 = shader->config.rsrc2;
-
-		if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
-			hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->num_lds_blocks);
-		} else {
-			hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->num_lds_blocks);
-		}
-
 		if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
 			radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
 			radeon_emit(cs, va >> 8);
@@ -4080,7 +4071,7 @@
 
 		radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
 		radeon_emit(cs, shader->config.rsrc1);
-		radeon_emit(cs, hs_rsrc2);
+		radeon_emit(cs, shader->config.rsrc2);
 	} else {
 		radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
 		radeon_emit(cs, va >> 8);
@@ -4136,7 +4127,7 @@
 			radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
 	}
 
-	radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
+	radv_pipeline_generate_hw_hs(cs, pipeline, tcs);
 
 	radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
 			       tess->tf_param);

src/amd/vulkan/radv_shader.c

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 11f8fbe..a055d86 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -813,8 +813,10 @@
 			 */
 			if (pdevice->rad_info.chip_class >= GFX10) {
 				vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1;
+				config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX10(info->tcs.num_lds_blocks);
 			} else {
 				vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
+				config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX9(info->tcs.num_lds_blocks);
 			}
 		} else {
 			config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);