i965: move exec_size from fs_instruction to backend_instruction
We are going to need this in the vec4 backend too.
Reviewed-by: Matt Turner <mattst88@gmail.com>
diff --git a/src/mesa/drivers/dri/i965/brw_ir_fs.h b/src/mesa/drivers/dri/i965/brw_ir_fs.h
index 16ee3d2..c569bd4 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_fs.h
@@ -368,13 +368,6 @@
uint8_t sources; /**< Number of fs_reg sources. */
/**
- * Execution size of the instruction. This is used by the generator to
- * generate the correct binary for the given fs_inst. Current valid
- * values are 1, 8, 16.
- */
- uint8_t exec_size;
-
- /**
* Channel group from the hardware execution and predication mask that
* should be applied to the instruction. The subset of channel enable
* signals (calculated from the EU control flow and predication state)
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
index e8b34d5..b5af6ab 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -133,6 +133,13 @@
const char *annotation;
/** @} */
+ /**
+ * Execution size of the instruction. This is used by the generator to
+ * generate the correct binary for the given instruction. Current valid
+ * values are 1, 4, 8, 16, 32.
+ */
+ uint8_t exec_size;
+
uint32_t offset; /**< spill/unspill offset or texture offset bitfield */
uint8_t mlen; /**< SEND message length */
int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index c615ac0..e88bb7c 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -55,6 +55,7 @@
this->mlen = 0;
this->base_mrf = 0;
this->offset = 0;
+ this->exec_size = 8;
this->annotation = NULL;
}
