commit 713c123bfa90fa845cf603a2d82a338b363cb4ee
author Matt Turner <mattst88@gmail.com> Tue Jan 21 10:44:59 2020 -0800
committer Marge Bot <eric+marge@anholt.net> Wed Jan 22 00:19:20 2020 +0000
tree 7cb849098205a48bb50680180e17923f8e2edd61
parent 49c21802cbca8240b272318759b1e472142929e6

intel/compiler: Don't disassemble align1 3-src operands on Gen < 10

Since the platforms don't support align1 3-src instructions, the
contents of these operands are not going to be meaningful. Just don't
print them to avoid hitting some assertions in brw_inst functions.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>

src/intel/compiler/brw_disasm.c

diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index 31d932b..e3e9b50 100644
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel/compiler/brw_disasm.c
@@ -829,6 +829,9 @@
    unsigned subreg_nr;
    enum brw_reg_type type;
 
+   if (devinfo->gen < 10 && is_align1)
+      return 0;
+
    if (devinfo->gen == 6 && brw_inst_3src_a16_dst_reg_file(devinfo, inst))
       reg_file = BRW_MESSAGE_REGISTER_FILE;
    else if (devinfo->gen >= 12)
@@ -1101,6 +1104,9 @@
    bool is_scalar_region;
    bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
 
+   if (devinfo->gen < 10 && is_align1)
+      return 0;
+
    if (is_align1) {
       if (devinfo->gen >= 12 && !brw_inst_3src_a1_src0_is_imm(devinfo, inst)) {
          _file = brw_inst_3src_a1_src0_reg_file(devinfo, inst);
@@ -1184,6 +1190,9 @@
    bool is_scalar_region;
    bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
 
+   if (devinfo->gen < 10 && is_align1)
+      return 0;
+
    if (is_align1) {
       if (devinfo->gen >= 12) {
          _file = brw_inst_3src_a1_src1_reg_file(devinfo, inst);
@@ -1254,6 +1263,9 @@
    bool is_scalar_region;
    bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
 
+   if (devinfo->gen < 10 && is_align1)
+      return 0;
+
    if (is_align1) {
       if (devinfo->gen >= 12 && !brw_inst_3src_a1_src2_is_imm(devinfo, inst)) {
          _file = brw_inst_3src_a1_src2_reg_file(devinfo, inst);