commit 545d852a7a7bc8a509d22096bdb7fb578d4bab65
author Anuj Phogat <anuj.phogat@gmail.com> Wed Sep 09 11:05:18 2020 -0700
committer Anuj Phogat <anuj.phogat@gmail.com> Thu Oct 01 16:57:50 2020 +0000
tree 05f3f47654ef82e465144df141c11656b879be9d
parent 237f4d9d187ec21d880c7fb4441456d22b4269b6

intel/gen9: Enable MSC RAW Hazard Avoidance

Workaround # 22011374674
Applied to i965, iris and anv drivers
No performance impact is observed with WA.

Cc: mesa-stable
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

src/gallium/drivers/iris/iris_state.c

diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index 29c0bf9..e1717dc 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -972,6 +972,8 @@
    iris_pack_state(GENX(CACHE_MODE_1), &reg_val, reg) {
       reg.FloatBlendOptimizationEnable = true;
       reg.FloatBlendOptimizationEnableMask = true;
+      reg.MSCRAWHazardAvoidanceBit = true;
+      reg.MSCRAWHazardAvoidanceBitMask = true;
       reg.PartialResolveDisableInVC = true;
       reg.PartialResolveDisableInVCMask = true;
    }

src/intel/vulkan/genX_state.c

diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index a29938e..e490c40 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -131,6 +131,8 @@
    anv_pack_struct(&cache_mode_1, GENX(CACHE_MODE_1),
                    .FloatBlendOptimizationEnable = true,
                    .FloatBlendOptimizationEnableMask = true,
+                   .MSCRAWHazardAvoidanceBit = true,
+                   .MSCRAWHazardAvoidanceBitMask = true,
                    .PartialResolveDisableInVC = true,
                    .PartialResolveDisableInVCMask = true);
 

src/mesa/drivers/dri/i965/brw_defines.h

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 76ec9a2..e52e75f 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1561,6 +1561,7 @@
 #define GEN7_CACHE_MODE_0               0x7000
 #define GEN7_CACHE_MODE_1               0x7004
 # define GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
+# define GEN9_MSC_RAW_HAZARD_AVOIDANCE_BIT    (1 << 9)
 # define GEN8_HIZ_NP_PMA_FIX_ENABLE        (1 << 11)
 # define GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE (1 << 13)
 # define GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC (1 << 1)

src/mesa/drivers/dri/i965/brw_state_upload.c

diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 564ac0e..7d0cf96 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -206,8 +206,10 @@
        */
       brw_load_register_imm32(brw, GEN7_CACHE_MODE_1,
                               REG_MASK(GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE) |
+                              REG_MASK(GEN9_MSC_RAW_HAZARD_AVOIDANCE_BIT) |
                               REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC) |
                               GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE |
+                              GEN9_MSC_RAW_HAZARD_AVOIDANCE_BIT |
                               GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC);
    }