commit 3c5eb1f7615c44d0ba4d95b45d1fd71c54be8344
author Samuel Pitoiset <samuel.pitoiset@gmail.com> Mon Oct 05 11:30:39 2020 +0200
committer Samuel Pitoiset <samuel.pitoiset@gmail.com> Wed Oct 07 13:31:36 2020 +0200
tree 3401f63eb1dfe652786d7568ca95d60d8f7a8fe9
parent 1211d05befaf82e56c8f30d1b5ab02cd3fed6a00

aco: more uses of nir_get_io_offset_src()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7003>

src/amd/compiler/aco_instruction_selection.cpp

diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index f72dda5..cdb2bc4 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -4123,8 +4123,9 @@
    unsigned write_mask = nir_intrinsic_write_mask(instr);
    unsigned component = nir_intrinsic_component(instr);
    unsigned idx = nir_intrinsic_base(instr) * 4u + component;
+   nir_src offset = *nir_get_io_offset_src(instr);
 
-   if (!nir_src_is_const(instr->src[1]) || nir_src_as_uint(instr->src[1]))
+   if (!nir_src_is_const(offset) || nir_src_as_uint(offset))
       return false;
 
    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
@@ -4507,10 +4508,12 @@
 {
    Builder bld(ctx->program, ctx->block);
    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
+   nir_src offset = *nir_get_io_offset_src(instr);
+
    if (ctx->shader->info.stage == MESA_SHADER_VERTEX) {
 
-      if (!nir_src_is_const(instr->src[0]) || nir_src_as_uint(instr->src[0]))
-         isel_err(instr->src[0].ssa->parent_instr, "Unimplemented non-zero nir_intrinsic_load_input offset");
+      if (!nir_src_is_const(offset) || nir_src_as_uint(offset))
+         isel_err(offset.ssa->parent_instr, "Unimplemented non-zero nir_intrinsic_load_input offset");
 
       Temp vertex_buffers = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->vertex_buffers));
 
@@ -4716,9 +4719,8 @@
             ctx->allocated_vec.emplace(dst.id(), elems);
       }
    } else if (ctx->shader->info.stage == MESA_SHADER_FRAGMENT) {
-      nir_src *off_src = nir_get_io_offset_src(instr);
-      if (!nir_src_is_const(*off_src) || nir_src_as_uint(*off_src))
-         isel_err(off_src->ssa->parent_instr, "Unimplemented non-zero nir_intrinsic_load_input offset");
+      if (!nir_src_is_const(offset) || nir_src_as_uint(offset))
+         isel_err(offset.ssa->parent_instr, "Unimplemented non-zero nir_intrinsic_load_input offset");
 
       Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask);