src/gallium/drivers/swr/rasterizer/archrast/events_private.proto

# Copyright (C) 2018 Intel Corporation.   All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
# to deal in the Software without restriction, including without limitation
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
# and/or sell copies of the Software, and to permit persons to whom the
# Software is furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice (including the next
# paragraph) shall be included in all copies or substantial portions of the
# Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
# IN THE SOFTWARE.
#
# Provides definitions for private internal events that are only used internally
# to rasty for communicating information between Rasty and Archrast. One goal for
# ArchRast is to not pollute the Rasty code with lots of calculations, etc. that
# are needed to compute per draw statistics, etc.

event PipelineStats::EarlyDepthStencilInfoSingleSample
{
    uint64_t depthPassMask;
    uint64_t stencilPassMask;
    uint64_t coverageMask;
};

event PipelineStats::EarlyDepthStencilInfoSampleRate
{
    uint64_t depthPassMask;
    uint64_t stencilPassMask;
    uint64_t coverageMask;
};

event PipelineStats::EarlyDepthStencilInfoNullPS
{
    uint64_t depthPassMask;
    uint64_t stencilPassMask;
    uint64_t coverageMask;
};

event PipelineStats::LateDepthStencilInfoSingleSample
{
    uint64_t depthPassMask;
    uint64_t stencilPassMask;
    uint64_t coverageMask;
};

event PipelineStats::LateDepthStencilInfoSampleRate
{
    uint64_t depthPassMask;
    uint64_t stencilPassMask;
    uint64_t coverageMask;
};

event PipelineStats::LateDepthStencilInfoNullPS
{
    uint64_t depthPassMask;
    uint64_t stencilPassMask;
    uint64_t coverageMask;
};

event PipelineStats::EarlyDepthInfoPixelRate
{
    uint64_t depthPassCount;
    uint64_t activeLanes;
};


event PipelineStats::LateDepthInfoPixelRate
{
    uint64_t depthPassCount;
    uint64_t activeLanes;
};


event PipelineStats::BackendDrawEndEvent
{
    uint32_t drawId;
};

event PipelineStats::FrontendDrawEndEvent
{
    uint32_t drawId;
};

event Memory::MemoryAccessEvent
{
    uint32_t drawId;
    uint64_t tsc;
    uint64_t ptr;
    uint32_t size;
    uint8_t isRead;
    uint8_t client;
};

event Memory::MemoryStatsEndEvent
{
    uint32_t drawId;
};

event PipelineStats::TessPrimCount
{
    uint64_t primCount;
};

event PipelineStats::RasterTileCount
{
    uint32_t drawId;
    uint64_t rasterTiles;
};

event PipelineStats::GSPrimInfo
{
    uint64_t inputPrimCount;
    uint64_t primGeneratedCount;
    uint64_t vertsInput;
};

// validMask is primitives that still need to be clipped. They weren't rejected due to trivial reject or nan.
// clipMask is primitives that need to be clipped. So trivial accepts will be 0 while validMask for that is 1.
// Trivial reject is numInvocations - pop_cnt32(validMask)
// Trivial accept is validMask & ~clipMask
// Must clip count is pop_cnt32(clipMask)
event PipelineStats::ClipInfoEvent
{
    uint32_t numInvocations;
    uint32_t validMask;
    uint32_t clipMask;
};

event PipelineStats::CullInfoEvent
{
    uint32_t drawId;
    uint64_t degeneratePrimMask;
    uint64_t backfacePrimMask;
    uint32_t validMask;
};

event PipelineStats::AlphaInfoEvent
{
    uint32_t drawId;
    uint32_t alphaTestEnable;
    uint32_t alphaBlendEnable;
};

event PipelineStats::DrawInstancedEvent
{
    uint32_t drawId;
    uint32_t topology;
    uint32_t numVertices;
    int32_t  startVertex;
    uint32_t numInstances;
    uint32_t startInstance;
    uint32_t tsEnable;
    uint32_t gsEnable;
    uint32_t soEnable;
    uint32_t soTopology;
    uint32_t splitId; // Split draw count or id.
};

event PipelineStats::DrawIndexedInstancedEvent
{
    uint32_t drawId;
    uint32_t topology;
    uint32_t numIndices;
    int32_t  indexOffset;
    int32_t  baseVertex;
    uint32_t numInstances;
    uint32_t startInstance;
    uint32_t tsEnable;
    uint32_t gsEnable;
    uint32_t soEnable;
    uint32_t soTopology;
    uint32_t splitId; // Split draw count or id.
};

event ShaderStats::VSStats
{
    HANDLE hStats;      // SWR_SHADER_STATS
};

event ShaderStats::HSStats
{
    HANDLE hStats;      // SWR_SHADER_STATS
};

event ShaderStats::DSStats
{
    HANDLE hStats;      // SWR_SHADER_STATS
};

event ShaderStats::GSStats
{
    HANDLE hStats;      // SWR_SHADER_STATS
};

event ShaderStats::PSStats
{
    HANDLE hStats;      // SWR_SHADER_STATS
};

event ShaderStats::CSStats
{
    HANDLE hStats;      // SWR_SHADER_STATS
};