commit 3457252b74f5490cff8915cac1e5fe0bf1031f5b
author Connor Abbott <connor.w.abbott@intel.com> Thu Aug 13 14:35:46 2015 -0700
committer Samuel Iglesias Gonsálvez <siglesias@igalia.com> Tue Jan 03 11:26:50 2017 +0100
tree 13be7ef0650d384de92ec8463cb6336da0598328
parent fef06f635610ddc730a213576e59afb638c6051d

i965/vec4/nir: set the right type for 64-bit registers

Reviewed-by: Matt Turner <mattst88@gmail.com>

src/mesa/drivers/dri/i965/brw_vec4_nir.cpp

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 062215d..bdee84b 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -142,6 +142,9 @@
          reg->num_array_elems == 0 ? 1 : reg->num_array_elems;
       const unsigned num_regs = array_elems * DIV_ROUND_UP(reg->bit_size, 32);
       nir_locals[reg->index] = dst_reg(VGRF, alloc.allocate(num_regs));
+
+      if (reg->bit_size == 64)
+         nir_locals[reg->index].type = BRW_REGISTER_TYPE_DF;
    }
 
    nir_ssa_values = ralloc_array(mem_ctx, dst_reg, impl->ssa_alloc);