commit 2715bd02ee7e67a28ccf96ed24aeb8182bbef747
author Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Sat Sep 28 09:48:53 2019 -0400
committer Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Mon Sep 30 08:40:13 2019 -0400
tree ffba87a41cd2480ff8ded09078feb56b2876138b
parent 57bac68fffe4d7dcb5cf573ca9ad4cd262d3a5e1

pan/midgard: Schedule to smul/sadd

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

src/panfrost/midgard/midgard_schedule.c

diff --git a/src/panfrost/midgard/midgard_schedule.c b/src/panfrost/midgard/midgard_schedule.c
index dfc02f1..ddd5edd 100644
--- a/src/panfrost/midgard/midgard_schedule.c
+++ b/src/panfrost/midgard/midgard_schedule.c
@@ -753,6 +753,8 @@
                         unreachable("Bad condition");
         }
 
+        mir_choose_alu(&smul, instructions, worklist, len, &predicate, UNIT_SMUL);
+
         if (!writeout)
                 mir_choose_alu(&vlut, instructions, worklist, len, &predicate, UNIT_VLUT);
 
@@ -777,6 +779,9 @@
                         unreachable("Bad condition");
         }
 
+        /* Stage 2, let's schedule sadd before vmul for writeout */
+        mir_choose_alu(&sadd, instructions, worklist, len, &predicate, UNIT_SADD);
+
         /* Check if writeout reads its own register */
         bool bad_writeout = false;