commit 200a2f245518bef173c642fa1fd2e4fbf1cc52c7
author Daniel Schürmann <daniel@schuermann.dev> Fri Dec 11 09:23:04 2020 +0100
committer Dylan Baker <dylan.c.baker@intel.com> Fri Dec 11 09:41:41 2020 -0800
tree 4d680cb0d9c31150a3b3558de816107f39b8fe6c
parent 5e65a36a7f80b98eb9958e93aad393008527cad9

aco/ra: use get_reg_specified() for p_extract_vector

On GFX6/7, it might violate validation rules, otherwise.

Fixes: 51f4b22feec3720c89458094a3245efc984115ee ('aco: don't allow unaligned subdword accesses on GFX6/7')
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8047>
(cherry picked from commit fd49ba59a3888795ad0788259e3472e08c42bc24)

.pick_status.json

diff --git a/.pick_status.json b/.pick_status.json
index 01a4c43..f7707c7 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -40,7 +40,7 @@
         "description": "aco/ra: use get_reg_specified() for p_extract_vector",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "master_sha": null,
         "because_sha": "51f4b22feec3720c89458094a3245efc984115ee"
     },

src/amd/compiler/aco_register_allocation.cpp

diff --git a/src/amd/compiler/aco_register_allocation.cpp b/src/amd/compiler/aco_register_allocation.cpp
index 39c7842..3cf0153 100644
--- a/src/amd/compiler/aco_register_allocation.cpp
+++ b/src/amd/compiler/aco_register_allocation.cpp
@@ -2202,14 +2202,10 @@
                    !register_file.test(reg, definition->bytes()))
                   definition->setFixed(reg);
             } else if (instr->opcode == aco_opcode::p_extract_vector) {
-               PhysReg reg;
-               if (instr->operands[0].isKillBeforeDef() &&
-                   instr->operands[0].getTemp().type() == definition->getTemp().type()) {
-                  reg = instr->operands[0].physReg();
-                  reg.reg_b += definition->bytes() * instr->operands[1].constantValue();
-                  assert(!register_file.test(reg, definition->bytes()));
+               PhysReg reg = instr->operands[0].physReg();
+               reg.reg_b += definition->bytes() * instr->operands[1].constantValue();
+               if (get_reg_specified(ctx, register_file, definition->regClass(), parallelcopy, instr, reg))
                   definition->setFixed(reg);
-               }
             } else if (instr->opcode == aco_opcode::p_create_vector) {
                PhysReg reg = get_reg_create_vector(ctx, register_file, definition->getTemp(),
                                                    parallelcopy, instr);