commit 17af07024dfc8302b37a270cea4ef3eae06fe5e2
author Marek Olšák <marek.olsak@amd.com> Fri Aug 14 19:31:46 2020 -0400
committer Marge Bot <eric+marge@anholt.net> Mon Aug 24 19:07:18 2020 +0000
tree 5f9600b31a19d47bd2a5bb34a8ee6ef842007195
parent 502abfce7f5df1811b619657e2e973916699dbc0

nir: gather all IO info from IO intrinsics

nir_io_add_const_offset_to_base will shrink num_slots, so it's better to
call it before nir_shader_gather_info.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6442>

src/compiler/nir/nir_gather_info.c

diff --git a/src/compiler/nir/nir_gather_info.c b/src/compiler/nir/nir_gather_info.c
index 5f59dd2..03f0d15 100644
--- a/src/compiler/nir/nir_gather_info.c
+++ b/src/compiler/nir/nir_gather_info.c
@@ -297,6 +297,14 @@
 gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
                       void *dead_ctx)
 {
+   unsigned slot_mask = 0;
+
+   if (nir_intrinsic_infos[instr->intrinsic].index_map[NIR_INTRINSIC_IO_SEMANTICS] > 0) {
+      nir_io_semantics semantics = nir_intrinsic_io_semantics(instr);
+
+      slot_mask = BITFIELD64_RANGE(semantics.location, semantics.num_slots);
+   }
+
    switch (instr->intrinsic) {
    case nir_intrinsic_demote:
    case nir_intrinsic_demote_if:
@@ -345,6 +353,41 @@
       break;
    }
 
+   case nir_intrinsic_load_input:
+      if (shader->info.stage == MESA_SHADER_TESS_EVAL)
+         shader->info.patch_inputs_read |= slot_mask;
+      else
+         shader->info.inputs_read |= slot_mask;
+      break;
+
+   case nir_intrinsic_load_per_vertex_input:
+   case nir_intrinsic_load_input_vertex:
+   case nir_intrinsic_load_interpolated_input:
+      shader->info.inputs_read |= slot_mask;
+      break;
+
+   case nir_intrinsic_load_output:
+      if (shader->info.stage == MESA_SHADER_TESS_CTRL)
+         shader->info.patch_outputs_read |= slot_mask;
+      else
+         shader->info.outputs_read |= slot_mask;
+      break;
+
+   case nir_intrinsic_load_per_vertex_output:
+      shader->info.outputs_read |= slot_mask;
+      break;
+
+   case nir_intrinsic_store_output:
+      if (shader->info.stage == MESA_SHADER_TESS_CTRL)
+         shader->info.patch_outputs_written |= slot_mask;
+      else
+         shader->info.outputs_written |= slot_mask;
+      break;
+
+   case nir_intrinsic_store_per_vertex_output:
+      shader->info.outputs_written |= slot_mask;
+      break;
+
    case nir_intrinsic_load_draw_id:
    case nir_intrinsic_load_frag_coord:
    case nir_intrinsic_load_point_coord: