commit 0f096b1e5a5e31a5efba7279326ec8bc8478bb56
author Iago Toral Quiroga <itoral@igalia.com> Mon Nov 02 00:07:27 2015 -0500
committer Samuel Iglesias Gonsálvez <siglesias@igalia.com> Tue Jan 03 11:26:50 2017 +0100
tree 8e8dda147ac455fd0f29854326500da3c94a8a85
parent 2d81a292036445c440e56d07ce3d5294e0411d71

i965/vec4/nir: Add bit-size information to types

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

src/mesa/drivers/dri/i965/brw_vec4_nir.cpp

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 37c9926..5c56e08 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -325,7 +325,7 @@
 vec4_visitor::get_nir_src(const nir_src &src, unsigned num_components)
 {
    /* if type is not specified, default to signed int */
-   return get_nir_src(src, nir_type_int, num_components);
+   return get_nir_src(src, nir_type_int32, num_components);
 }
 
 src_reg
@@ -742,7 +742,7 @@
       const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
 
       /* Get the arguments of the atomic intrinsic. */
-      src_reg offset = get_nir_src(instr->src[0], nir_type_int,
+      src_reg offset = get_nir_src(instr->src[0], nir_type_int32,
                                    instr->num_components);
       const src_reg surface = brw_imm_ud(surf_index);
       const src_reg src0 = (info->num_srcs >= 2
@@ -788,7 +788,7 @@
           * from any live channel.
           */
          surf_index = src_reg(this, glsl_type::uint_type);
-         emit(ADD(dst_reg(surf_index), get_nir_src(instr->src[0], nir_type_int,
+         emit(ADD(dst_reg(surf_index), get_nir_src(instr->src[0], nir_type_int32,
                                                    instr->num_components),
                   brw_imm_ud(prog_data->base.binding_table.ubo_start)));
          surf_index = emit_uniformize(surf_index);
@@ -806,7 +806,7 @@
       if (const_offset) {
          offset = brw_imm_ud(const_offset->u32[0] & ~15);
       } else {
-         offset = get_nir_src(instr->src[1], nir_type_int, 1);
+         offset = get_nir_src(instr->src[1], nir_type_uint32, 1);
       }
 
       src_reg packed_consts = src_reg(this, glsl_type::vec4_type);