intel/assembler: Add labels support
Use labels instead of numeric JIP/UIP offsets.
Works for gen6+.
v2:
- Change asm tests to use labels on gen6+
- Remove usage of relative offsets on gen6+
- Consider brw_jump_scale when setting relative offset
- Return error if there is a JIP/UIP label without matching target
- Fix matching of label tokens
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4245>
diff --git a/src/intel/tools/i965_asm.c b/src/intel/tools/i965_asm.c
index 1e6e090..2be74e3 100644
--- a/src/intel/tools/i965_asm.c
+++ b/src/intel/tools/i965_asm.c
@@ -38,6 +38,9 @@
char *input_filename = NULL;
int errors;
+struct list_head instr_labels;
+struct list_head target_labels;
+
static void
print_help(const char *progname, FILE *file)
{
@@ -119,6 +122,90 @@
return devinfo;
}
+static bool
+i965_postprocess_labels()
+{
+ if (p->devinfo->gen < 6) {
+ return true;
+ }
+
+ void *store = p->store;
+
+ struct target_label *tlabel;
+ struct instr_label *ilabel, *s;
+
+ const unsigned to_bytes_scale = brw_jump_scale(p->devinfo);
+
+ LIST_FOR_EACH_ENTRY(tlabel, &target_labels, link) {
+ LIST_FOR_EACH_ENTRY_SAFE(ilabel, s, &instr_labels, link) {
+ if (!strcmp(tlabel->name, ilabel->name)) {
+ brw_inst *inst = store + ilabel->offset;
+
+ int relative_offset = (tlabel->offset - ilabel->offset) / sizeof(brw_inst);
+ relative_offset *= to_bytes_scale;
+
+ unsigned opcode = brw_inst_opcode(p->devinfo, inst);
+
+ if (ilabel->type == INSTR_LABEL_JIP) {
+ switch (opcode) {
+ case BRW_OPCODE_IF:
+ case BRW_OPCODE_ELSE:
+ case BRW_OPCODE_ENDIF:
+ case BRW_OPCODE_WHILE:
+ if (p->devinfo->gen >= 7) {
+ brw_inst_set_jip(p->devinfo, inst, relative_offset);
+ } else if (p->devinfo->gen == 6) {
+ brw_inst_set_gen6_jump_count(p->devinfo, inst, relative_offset);
+ }
+ break;
+ case BRW_OPCODE_BREAK:
+ case BRW_OPCODE_HALT:
+ case BRW_OPCODE_CONTINUE:
+ brw_inst_set_jip(p->devinfo, inst, relative_offset);
+ break;
+ default:
+ fprintf(stderr, "Unknown opcode %d with JIP label\n", opcode);
+ return false;
+ }
+ } else {
+ switch (opcode) {
+ case BRW_OPCODE_IF:
+ case BRW_OPCODE_ELSE:
+ if (p->devinfo->gen > 7) {
+ brw_inst_set_uip(p->devinfo, inst, relative_offset);
+ } else if (p->devinfo->gen == 7) {
+ brw_inst_set_uip(p->devinfo, inst, relative_offset);
+ } else if (p->devinfo->gen == 6) {
+ // Nothing
+ }
+ break;
+ case BRW_OPCODE_WHILE:
+ case BRW_OPCODE_ENDIF:
+ fprintf(stderr, "WHILE/ENDIF cannot have UIP offset\n");
+ return false;
+ case BRW_OPCODE_BREAK:
+ case BRW_OPCODE_CONTINUE:
+ case BRW_OPCODE_HALT:
+ brw_inst_set_uip(p->devinfo, inst, relative_offset);
+ break;
+ default:
+ fprintf(stderr, "Unknown opcode %d with UIP label\n", opcode);
+ return false;
+ }
+ }
+
+ list_del(&ilabel->link);
+ }
+ }
+ }
+
+ LIST_FOR_EACH_ENTRY(ilabel, &instr_labels, link) {
+ fprintf(stderr, "Unknown label '%s'\n", ilabel->name);
+ }
+
+ return list_is_empty(&instr_labels);
+}
+
int main(int argc, char **argv)
{
char *output_file = NULL;
@@ -132,6 +219,8 @@
struct disasm_info *disasm_info;
struct gen_device_info *devinfo = NULL;
int result = EXIT_FAILURE;
+ list_inithead(&instr_labels);
+ list_inithead(&target_labels);
const struct option i965_asm_opts[] = {
{ "help", no_argument, (int *) &help, true },
@@ -230,6 +319,9 @@
if (err || errors)
goto end;
+ if (!i965_postprocess_labels())
+ goto end;
+
store = p->store;
disasm_info = disasm_initialize(p->devinfo, NULL);
diff --git a/src/intel/tools/i965_asm.h b/src/intel/tools/i965_asm.h
index dd29208..a7e4e86 100644
--- a/src/intel/tools/i965_asm.h
+++ b/src/intel/tools/i965_asm.h
@@ -35,6 +35,7 @@
#include "compiler/brw_inst.h"
#include "compiler/brw_eu.h"
#include "dev/gen_device_info.h"
+#include "util/list.h"
/* glibc < 2.27 defines OVERFLOW in /usr/include/math.h. */
#undef OVERFLOW
@@ -48,6 +49,9 @@
extern int errors;
extern char *input_filename;
+extern struct list_head instr_labels;
+extern struct list_head target_labels;
+
struct condition {
unsigned cond_modifier:4;
unsigned flag_reg_nr:1;
@@ -77,4 +81,24 @@
unsigned is_compr:1;
};
+enum instr_label_type {
+ INSTR_LABEL_JIP,
+ INSTR_LABEL_UIP,
+};
+
+struct instr_label {
+ struct list_head link;
+
+ char *name;
+ int offset;
+ enum instr_label_type type;
+};
+
+struct target_label {
+ struct list_head link;
+
+ char *name;
+ int offset;
+};
+
#endif /* __I965_ASM_H__ */
diff --git a/src/intel/tools/i965_gram.y b/src/intel/tools/i965_gram.y
index 2b65768..e5fb228 100644
--- a/src/intel/tools/i965_gram.y
+++ b/src/intel/tools/i965_gram.y
@@ -310,6 +310,22 @@
}
}
+static void
+add_label(struct brw_codegen *p, const char* label_name, enum instr_label_type type)
+{
+ if (!label_name) {
+ return;
+ }
+
+ struct instr_label *label = rzalloc(p->mem_ctx, struct instr_label);
+
+ label->name = ralloc_strdup(p->mem_ctx, label_name);
+ label->offset = p->next_insn_offset;
+ label->type = type;
+
+ list_addtail(&label->link, &instr_labels);
+}
+
%}
%locations
@@ -317,6 +333,7 @@
%start ROOT
%union {
+ char *string;
double number;
int integer;
unsigned long long int llint;
@@ -350,6 +367,10 @@
%token <integer> TYPE_DF TYPE_NF
%token <integer> TYPE_VF
+/* label */
+%token <string> JUMP_LABEL
+%token <string> JUMP_LABEL_TARGET
+
/* opcodes */
%token <integer> ADD ADD3 ADDC AND ASR AVG
%token <integer> BFE BFI1 BFI2 BFB BFREV BRC BRD BREAK
@@ -502,6 +523,9 @@
%type <integer> negate abs chansel math_function sharedfunction
+%type <string> jumplabeltarget
+%type <string> jumplabel
+
%code {
static void
@@ -608,6 +632,8 @@
| instrseq relocatableinstruction SEMICOLON
| instruction SEMICOLON
| relocatableinstruction SEMICOLON
+ | instrseq jumplabeltarget
+ | jumplabeltarget
;
/* Instruction Group */
@@ -1072,24 +1098,16 @@
/* branch instruction */
branchinstruction:
- predicate ENDIF execsize relativelocation instoptions
+ predicate ENDIF execsize JUMP_LABEL instoptions
{
+ add_label(p, $4, INSTR_LABEL_JIP);
+
brw_next_insn(p, $2);
i965_asm_set_instruction_options(p, $5);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
- if (p->devinfo->gen < 6) {
- brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
- BRW_REGISTER_TYPE_D));
- brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
- BRW_REGISTER_TYPE_D));
- brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
- brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
- $4);
- } else if (p->devinfo->gen == 6) {
+ if (p->devinfo->gen == 6) {
brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
- brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
- $4);
brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
@@ -1100,34 +1118,41 @@
brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
- brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
} else {
- brw_set_src0(p, brw_last_inst, brw_imm_d($4));
+ brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
}
- if (p->devinfo->gen < 6)
- brw_inst_set_thread_control(p->devinfo, brw_last_inst,
- BRW_THREAD_SWITCH);
brw_pop_insn_state(p);
}
- | ELSE execsize relativelocation rellocation instoptions
+ | predicate ENDIF execsize relativelocation instoptions
{
+ brw_next_insn(p, $2);
+ i965_asm_set_instruction_options(p, $5);
+ brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
+
+ brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
+ BRW_REGISTER_TYPE_D));
+ brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
+ BRW_REGISTER_TYPE_D));
+ brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
+ brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $4);
+
+ brw_inst_set_thread_control(p->devinfo, brw_last_inst,
+ BRW_THREAD_SWITCH);
+
+ brw_pop_insn_state(p);
+ }
+ | ELSE execsize JUMP_LABEL jumplabel instoptions
+ {
+ add_label(p, $3, INSTR_LABEL_JIP);
+ add_label(p, $4, INSTR_LABEL_UIP);
+
brw_next_insn(p, $1);
i965_asm_set_instruction_options(p, $5);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
- if (p->devinfo->gen < 6) {
- brw_set_dest(p, brw_last_inst, brw_ip_reg());
- brw_set_src0(p, brw_last_inst, brw_ip_reg());
- brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
- brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
- $3);
- brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
- $4);
- } else if (p->devinfo->gen == 6) {
+ if (p->devinfo->gen == 6) {
brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
- brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
- $3);
brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
@@ -1137,39 +1162,41 @@
BRW_REGISTER_TYPE_D));
brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
- brw_set_src1(p, brw_last_inst, brw_imm_w($3));
- brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
- brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
+ brw_set_src1(p, brw_last_inst, brw_imm_w(0));
} else {
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
- brw_set_src0(p, brw_last_inst, brw_imm_d($3));
- brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
- brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
+ if (p->devinfo->gen < 12)
+ brw_set_src0(p, brw_last_inst, brw_imm_d(0));
}
+ }
+ | ELSE execsize relativelocation rellocation instoptions
+ {
+ brw_next_insn(p, $1);
+ i965_asm_set_instruction_options(p, $5);
+ brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
- if (!p->single_program_flow && p->devinfo->gen < 6)
+ brw_set_dest(p, brw_last_inst, brw_ip_reg());
+ brw_set_src0(p, brw_last_inst, brw_ip_reg());
+ brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
+ brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $3);
+ brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $4);
+
+ if (!p->single_program_flow)
brw_inst_set_thread_control(p->devinfo, brw_last_inst,
BRW_THREAD_SWITCH);
}
- | predicate IF execsize relativelocation rellocation instoptions
+ | predicate IF execsize JUMP_LABEL jumplabel instoptions
{
+ add_label(p, $4, INSTR_LABEL_JIP);
+ add_label(p, $5, INSTR_LABEL_UIP);
+
brw_next_insn(p, $2);
i965_asm_set_instruction_options(p, $6);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
- if (p->devinfo->gen < 6) {
- brw_set_dest(p, brw_last_inst, brw_ip_reg());
- brw_set_src0(p, brw_last_inst, brw_ip_reg());
- brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
- brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
- $4);
- brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
- $5);
- } else if (p->devinfo->gen == 6) {
+ if (p->devinfo->gen == 6) {
brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
- brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
- $4);
brw_set_src0(p, brw_last_inst,
vec1(retype(brw_null_reg(),
BRW_REGISTER_TYPE_D)));
@@ -1183,64 +1210,80 @@
brw_set_src0(p, brw_last_inst,
vec1(retype(brw_null_reg(),
BRW_REGISTER_TYPE_D)));
- brw_set_src1(p, brw_last_inst, brw_imm_w($4));
- brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
- brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
+ brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
} else {
brw_set_dest(p, brw_last_inst,
vec1(retype(brw_null_reg(),
BRW_REGISTER_TYPE_D)));
- brw_set_src0(p, brw_last_inst, brw_imm_d($4));
- brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
- brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
+ if (p->devinfo->gen < 12)
+ brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
}
- if (!p->single_program_flow && p->devinfo->gen < 6)
+ brw_pop_insn_state(p);
+ }
+ | predicate IF execsize relativelocation rellocation instoptions
+ {
+ brw_next_insn(p, $2);
+ i965_asm_set_instruction_options(p, $6);
+ brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
+
+ brw_set_dest(p, brw_last_inst, brw_ip_reg());
+ brw_set_src0(p, brw_last_inst, brw_ip_reg());
+ brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
+ brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4);
+ brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $5);
+
+ if (!p->single_program_flow)
brw_inst_set_thread_control(p->devinfo, brw_last_inst,
BRW_THREAD_SWITCH);
brw_pop_insn_state(p);
}
+ | predicate IFF execsize JUMP_LABEL instoptions
+ {
+ add_label(p, $4, INSTR_LABEL_JIP);
+
+ brw_next_insn(p, $2);
+ i965_asm_set_instruction_options(p, $5);
+ brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
+
+ if (p->devinfo->gen == 6) {
+ brw_set_src0(p, brw_last_inst,
+ vec1(retype(brw_null_reg(),
+ BRW_REGISTER_TYPE_D)));
+ brw_set_src1(p, brw_last_inst,
+ vec1(retype(brw_null_reg(),
+ BRW_REGISTER_TYPE_D)));
+ } else if (p->devinfo->gen == 7) {
+ brw_set_dest(p, brw_last_inst,
+ vec1(retype(brw_null_reg(),
+ BRW_REGISTER_TYPE_D)));
+ brw_set_src0(p, brw_last_inst,
+ vec1(retype(brw_null_reg(),
+ BRW_REGISTER_TYPE_D)));
+ brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
+ } else {
+ brw_set_dest(p, brw_last_inst,
+ vec1(retype(brw_null_reg(),
+ BRW_REGISTER_TYPE_D)));
+ if (p->devinfo->gen < 12)
+ brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
+ }
+
+ brw_pop_insn_state(p);
+ }
| predicate IFF execsize relativelocation instoptions
{
brw_next_insn(p, $2);
i965_asm_set_instruction_options(p, $5);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
- if (p->devinfo->gen < 6) {
- brw_set_dest(p, brw_last_inst, brw_ip_reg());
- brw_set_src0(p, brw_last_inst, brw_ip_reg());
- brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
- $4);
- brw_set_src1(p, brw_last_inst, brw_imm_d($4));
- } else if (p->devinfo->gen == 6) {
- brw_set_dest(p, brw_last_inst, brw_imm_w($4));
- brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
- $4);
- brw_set_src0(p, brw_last_inst,
- vec1(retype(brw_null_reg(),
- BRW_REGISTER_TYPE_D)));
- brw_set_src1(p, brw_last_inst,
- vec1(retype(brw_null_reg(),
- BRW_REGISTER_TYPE_D)));
- } else if (p->devinfo->gen == 7) {
- brw_set_dest(p, brw_last_inst,
- vec1(retype(brw_null_reg(),
- BRW_REGISTER_TYPE_D)));
- brw_set_src0(p, brw_last_inst,
- vec1(retype(brw_null_reg(),
- BRW_REGISTER_TYPE_D)));
- brw_set_src1(p, brw_last_inst, brw_imm_w($4));
- brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
- } else {
- brw_set_dest(p, brw_last_inst,
- vec1(retype(brw_null_reg(),
- BRW_REGISTER_TYPE_D)));
- brw_set_src0(p, brw_last_inst, brw_imm_d($4));
- brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
- }
+ brw_set_dest(p, brw_last_inst, brw_ip_reg());
+ brw_set_src0(p, brw_last_inst, brw_ip_reg());
+ brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4);
+ brw_set_src1(p, brw_last_inst, brw_imm_d($4));
- if (!p->single_program_flow && p->devinfo->gen < 6)
+ if (!p->single_program_flow)
brw_inst_set_thread_control(p->devinfo, brw_last_inst,
BRW_THREAD_SWITCH);
@@ -1250,8 +1293,11 @@
/* break instruction */
breakinstruction:
- predicate BREAK execsize relativelocation relativelocation instoptions
+ predicate BREAK execsize JUMP_LABEL JUMP_LABEL instoptions
{
+ add_label(p, $4, INSTR_LABEL_JIP);
+ add_label(p, $5, INSTR_LABEL_UIP);
+
brw_next_insn(p, $2);
i965_asm_set_instruction_options(p, $6);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
@@ -1259,47 +1305,70 @@
if (p->devinfo->gen >= 8) {
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
- brw_set_src0(p, brw_last_inst, brw_imm_d($4));
- brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
- } else if (p->devinfo->gen >= 6) {
+ brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
+ } else {
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
- brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
- brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
- } else {
- brw_set_dest(p, brw_last_inst, brw_ip_reg());
- brw_set_src0(p, brw_last_inst, brw_ip_reg());
- brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
- brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
- $4);
- brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
- $5);
}
brw_pop_insn_state(p);
}
- | predicate HALT execsize relativelocation relativelocation instoptions
+ | predicate BREAK execsize relativelocation relativelocation instoptions
{
brw_next_insn(p, $2);
i965_asm_set_instruction_options(p, $6);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
+
+ brw_set_dest(p, brw_last_inst, brw_ip_reg());
+ brw_set_src0(p, brw_last_inst, brw_ip_reg());
+ brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
+ brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4);
+ brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $5);
+
+ brw_pop_insn_state(p);
+ }
+ | predicate HALT execsize JUMP_LABEL JUMP_LABEL instoptions
+ {
+ add_label(p, $4, INSTR_LABEL_JIP);
+ add_label(p, $5, INSTR_LABEL_UIP);
+
+ brw_next_insn(p, $2);
+ i965_asm_set_instruction_options(p, $6);
+ brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
+
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
if (p->devinfo->gen >= 8) {
- brw_set_src0(p, brw_last_inst, brw_imm_d($4));
- brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
+ brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
} else {
brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
BRW_REGISTER_TYPE_D));
- brw_set_src1(p, brw_last_inst, brw_imm_d($5));
+ brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
}
- brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
- brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
+ brw_pop_insn_state(p);
+ }
+ | predicate CONT execsize JUMP_LABEL JUMP_LABEL instoptions
+ {
+ add_label(p, $4, INSTR_LABEL_JIP);
+ add_label(p, $5, INSTR_LABEL_UIP);
+
+ brw_next_insn(p, $2);
+ i965_asm_set_instruction_options(p, $6);
+ brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
+ brw_set_dest(p, brw_last_inst, brw_ip_reg());
+
+ if (p->devinfo->gen >= 8) {
+ brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
+ } else {
+ brw_set_src0(p, brw_last_inst, brw_ip_reg());
+ brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
+ }
+
brw_pop_insn_state(p);
}
| predicate CONT execsize relativelocation relativelocation instoptions
@@ -1309,23 +1378,11 @@
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_set_dest(p, brw_last_inst, brw_ip_reg());
- if (p->devinfo->gen >= 8) {
- brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
- brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
- brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
- } else {
- brw_set_src0(p, brw_last_inst, brw_ip_reg());
- brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
- if (p->devinfo->gen >= 6) {
- brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
- brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
- } else {
- brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
- $4);
- brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
- $5);
- }
- }
+ brw_set_src0(p, brw_last_inst, brw_ip_reg());
+ brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
+
+ brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4);
+ brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $5);
brw_pop_insn_state(p);
}
@@ -1333,50 +1390,52 @@
/* loop instruction */
loopinstruction:
- predicate WHILE execsize relativelocation instoptions
+ predicate WHILE execsize JUMP_LABEL instoptions
+ {
+ add_label(p, $4, INSTR_LABEL_JIP);
+
+ brw_next_insn(p, $2);
+ i965_asm_set_instruction_options(p, $5);
+ brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
+
+ if (p->devinfo->gen >= 8) {
+ brw_set_dest(p, brw_last_inst,
+ retype(brw_null_reg(),
+ BRW_REGISTER_TYPE_D));
+ brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
+ } else if (p->devinfo->gen == 7) {
+ brw_set_dest(p, brw_last_inst,
+ retype(brw_null_reg(),
+ BRW_REGISTER_TYPE_D));
+ brw_set_src0(p, brw_last_inst,
+ retype(brw_null_reg(),
+ BRW_REGISTER_TYPE_D));
+ brw_set_src1(p, brw_last_inst,
+ brw_imm_w(0x0));
+ } else {
+ brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
+ brw_set_src0(p, brw_last_inst,
+ retype(brw_null_reg(),
+ BRW_REGISTER_TYPE_D));
+ brw_set_src1(p, brw_last_inst,
+ retype(brw_null_reg(),
+ BRW_REGISTER_TYPE_D));
+ }
+
+ brw_pop_insn_state(p);
+ }
+ | predicate WHILE execsize relativelocation instoptions
{
brw_next_insn(p, $2);
i965_asm_set_instruction_options(p, $5);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
- if (p->devinfo->gen >= 6) {
- if (p->devinfo->gen >= 8) {
- brw_set_dest(p, brw_last_inst,
- retype(brw_null_reg(),
- BRW_REGISTER_TYPE_D));
- brw_set_src0(p, brw_last_inst, brw_imm_d($4));
- } else if (p->devinfo->gen == 7) {
- brw_set_dest(p, brw_last_inst,
- retype(brw_null_reg(),
- BRW_REGISTER_TYPE_D));
- brw_set_src0(p, brw_last_inst,
- retype(brw_null_reg(),
- BRW_REGISTER_TYPE_D));
- brw_set_src1(p, brw_last_inst,
- brw_imm_w(0x0));
- brw_inst_set_jip(p->devinfo, brw_last_inst,
- $4);
- } else {
- brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
- brw_inst_set_gen6_jump_count(p->devinfo,
- brw_last_inst,
- $4);
- brw_set_src0(p, brw_last_inst,
- retype(brw_null_reg(),
- BRW_REGISTER_TYPE_D));
- brw_set_src1(p, brw_last_inst,
- retype(brw_null_reg(),
- BRW_REGISTER_TYPE_D));
- }
- } else {
- brw_set_dest(p, brw_last_inst, brw_ip_reg());
- brw_set_src0(p, brw_last_inst, brw_ip_reg());
- brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
- brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
- $4);
- brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
- 0);
- }
+ brw_set_dest(p, brw_last_inst, brw_ip_reg());
+ brw_set_src0(p, brw_last_inst, brw_ip_reg());
+ brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
+ brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4);
+ brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, 0);
+
brw_pop_insn_state(p);
}
| DO execsize instoptions
@@ -1419,6 +1478,23 @@
}
;
+jumplabel:
+ JUMP_LABEL { $$ = $1; }
+ | %empty { $$ = NULL; }
+ ;
+
+jumplabeltarget:
+ JUMP_LABEL_TARGET
+ {
+ struct target_label *label = rzalloc(p->mem_ctx, struct target_label);
+
+ label->name = ralloc_strdup(p->mem_ctx, $1);
+ label->offset = p->next_insn_offset;
+
+ list_addtail(&label->link, &target_labels);
+ }
+ ;
+
/* Destination register */
dst:
dstoperand
diff --git a/src/intel/tools/i965_lex.l b/src/intel/tools/i965_lex.l
index 4e575a3..7798636 100644
--- a/src/intel/tools/i965_lex.l
+++ b/src/intel/tools/i965_lex.l
@@ -24,6 +24,7 @@
%x CHANNEL
%x REG
%x DOTSEL
+%x LABEL
%%
/* eat up single line comment */
@@ -367,8 +368,8 @@
/* Eat up JIP and UIP token, their values will be parsed
* in numeric section
*/
-"JIP: " { }
-"UIP: " { }
+"JIP: " { BEGIN(LABEL); }
+"UIP: " { BEGIN(LABEL); }
"Jump: " { }
"Pop: " { }
[ \t]+ { }
@@ -383,6 +384,21 @@
return LONG;
}
+ /* jump label target */
+[a-zA-Z_][0-9a-zA-Z_]*":" {
+ yylval.string = ralloc_strdup(p->mem_ctx, yytext);
+ /* Stomp the trailing ':' */
+ yylval.string[yyleng - 1] = '\0';
+ return JUMP_LABEL_TARGET;
+}
+
+ /* jump label */
+<LABEL>[a-zA-Z_][0-9a-zA-Z_]* {
+ yylval.string = ralloc_strdup(p->mem_ctx, yytext);
+ BEGIN(INITIAL);
+ return JUMP_LABEL;
+}
+
\n { yycolumn = 1; }
. {
diff --git a/src/intel/tools/tests/gen6/break.asm b/src/intel/tools/tests/gen6/break.asm
index 4b8afa9..afb8586 100644
--- a/src/intel/tools/tests/gen6/break.asm
+++ b/src/intel/tools/tests/gen6/break.asm
@@ -1,6 +1,9 @@
-break(8) JIP: 2 UIP: 12 { align16 1Q };
-break(8) JIP: 2 UIP: 104 { align1 1Q };
-break(16) JIP: 2 UIP: 104 { align1 1H };
-(+f0.0) break(8) JIP: 4 UIP: 12 { align1 1Q };
-(+f0.0) break(16) JIP: 4 UIP: 12 { align1 1H };
-(+f0.0.x) break(8) JIP: 122 UIP: 124 { align16 1Q };
+break(8) JIP: LABEL1 UIP: LABEL2 { align16 1Q };
+LABEL1:
+break(8) JIP: LABEL2 UIP: LABEL2 { align1 1Q };
+break(16) JIP: LABEL2 UIP: LABEL2 { align1 1H };
+LABEL2:
+(+f0.0) break(8) JIP: LABEL3 UIP: LABEL3 { align1 1Q };
+(+f0.0) break(16) JIP: LABEL3 UIP: LABEL3 { align1 1H };
+(+f0.0.x) break(8) JIP: LABEL3 UIP: LABEL3 { align16 1Q };
+LABEL3:
diff --git a/src/intel/tools/tests/gen6/break.expected b/src/intel/tools/tests/gen6/break.expected
index 9ab35ec..dcf4d4f 100644
--- a/src/intel/tools/tests/gen6/break.expected
+++ b/src/intel/tools/tests/gen6/break.expected
@@ -1,6 +1,6 @@
-28 01 60 00 84 1c 0f 20 04 00 6e 00 02 00 0c 00
-28 00 60 00 84 1c 00 20 00 00 8d 00 02 00 68 00
-28 00 80 00 84 1c 00 20 00 00 8d 00 02 00 68 00
-28 00 61 00 84 1c 00 20 00 00 8d 00 04 00 0c 00
-28 00 81 00 84 1c 00 20 00 00 8d 00 04 00 0c 00
-28 01 62 00 84 1c 0f 20 04 00 6e 00 7a 00 7c 00
+28 01 60 00 84 1c 0f 20 04 00 6e 00 02 00 06 00
+28 00 60 00 84 1c 00 20 00 00 8d 00 04 00 04 00
+28 00 80 00 84 1c 00 20 00 00 8d 00 02 00 02 00
+28 00 61 00 84 1c 00 20 00 00 8d 00 06 00 06 00
+28 00 81 00 84 1c 00 20 00 00 8d 00 04 00 04 00
+28 01 62 00 84 1c 0f 20 04 00 6e 00 02 00 02 00
diff --git a/src/intel/tools/tests/gen6/cont.asm b/src/intel/tools/tests/gen6/cont.asm
index 7f7a9c4..497a115 100644
--- a/src/intel/tools/tests/gen6/cont.asm
+++ b/src/intel/tools/tests/gen6/cont.asm
@@ -1,3 +1,6 @@
-cont(8) JIP: 2 UIP: 8 { align1 1Q };
-cont(16) JIP: 2 UIP: 8 { align1 1H };
-cont(8) JIP: 2 UIP: 8 { align16 1Q };
+cont(8) JIP: LABEL0 UIP: LABEL2 { align1 1Q };
+LABEL0:
+cont(16) JIP: LABEL1 UIP: LABEL2 { align1 1H };
+LABEL1:
+cont(8) JIP: LABEL2 UIP: LABEL2 { align16 1Q };
+LABEL2:
diff --git a/src/intel/tools/tests/gen6/cont.expected b/src/intel/tools/tests/gen6/cont.expected
index a8376c2..704ea3a 100644
--- a/src/intel/tools/tests/gen6/cont.expected
+++ b/src/intel/tools/tests/gen6/cont.expected
@@ -1,3 +1,3 @@
-29 00 60 00 00 1c 00 34 00 14 60 00 02 00 08 00
-29 00 80 00 00 1c 00 34 00 14 60 00 02 00 08 00
-29 01 60 00 00 1c 0f 34 04 14 6e 00 02 00 08 00
+29 00 60 00 00 1c 00 34 00 14 60 00 02 00 06 00
+29 00 80 00 00 1c 00 34 00 14 60 00 02 00 04 00
+29 01 60 00 00 1c 0f 34 04 14 6e 00 02 00 02 00
diff --git a/src/intel/tools/tests/gen6/else.asm b/src/intel/tools/tests/gen6/else.asm
index 71a09a3..b3f4044 100644
--- a/src/intel/tools/tests/gen6/else.asm
+++ b/src/intel/tools/tests/gen6/else.asm
@@ -1,3 +1,4 @@
-else(8) JIP: 12 { align1 1Q };
-else(16) JIP: 12 { align1 1H };
-else(8) JIP: 18 { align16 1Q };
+else(8) JIP: LABEL0 { align1 1Q };
+else(16) JIP: LABEL0 { align1 1H };
+else(8) JIP: LABEL0 { align16 1Q };
+LABEL0:
diff --git a/src/intel/tools/tests/gen6/else.expected b/src/intel/tools/tests/gen6/else.expected
index 9e1b70e..05f52d5 100644
--- a/src/intel/tools/tests/gen6/else.expected
+++ b/src/intel/tools/tests/gen6/else.expected
@@ -1,3 +1,3 @@
-24 00 60 00 8f 10 0c 00 00 00 8d 00 00 00 8d 00
-24 00 80 00 8f 10 0c 00 00 00 8d 00 00 00 8d 00
-24 01 60 00 8f 10 12 00 04 00 6e 00 04 00 6e 00
+24 00 60 00 8f 10 06 00 00 00 8d 00 00 00 8d 00
+24 00 80 00 8f 10 04 00 00 00 8d 00 00 00 8d 00
+24 01 60 00 8f 10 02 00 04 00 6e 00 04 00 6e 00
diff --git a/src/intel/tools/tests/gen6/endif.asm b/src/intel/tools/tests/gen6/endif.asm
index b3a5066..c601516 100644
--- a/src/intel/tools/tests/gen6/endif.asm
+++ b/src/intel/tools/tests/gen6/endif.asm
@@ -1,3 +1,6 @@
-endif(8) JIP: 2 { align16 1Q };
-endif(8) JIP: 2 { align1 1Q };
-endif(16) JIP: 2 { align1 1H };
+endif(8) JIP: LABEL1 { align16 1Q };
+LABEL1:
+endif(8) JIP: LABEL2 { align1 1Q };
+LABEL2:
+endif(16) JIP: LABEL3 { align1 1H };
+LABEL3:
diff --git a/src/intel/tools/tests/gen6/halt.asm b/src/intel/tools/tests/gen6/halt.asm
index 3674b30..5f29e88 100644
--- a/src/intel/tools/tests/gen6/halt.asm
+++ b/src/intel/tools/tests/gen6/halt.asm
@@ -1,4 +1,6 @@
-(-f0.1.any4h) halt(8) JIP: 96 UIP: 98 { align1 1Q };
-halt(8) JIP: 2 UIP: 2 { align1 1Q };
-(-f0.1.any4h) halt(16) JIP: 100 UIP: 102 { align1 1H };
-halt(16) JIP: 2 UIP: 2 { align1 1H };
+(-f0.1.any4h) halt(8) JIP: LABEL0 UIP: LABEL0 { align1 1Q };
+halt(8) JIP: LABEL1 UIP: LABEL1 { align1 1Q };
+LABEL1:
+(-f0.1.any4h) halt(16) JIP: LABEL0 UIP: LABEL0 { align1 1H };
+halt(16) JIP: LABEL0 UIP: LABEL0 { align1 1H };
+LABEL0:
diff --git a/src/intel/tools/tests/gen6/halt.expected b/src/intel/tools/tests/gen6/halt.expected
index b5b612a..f76a4b1 100644
--- a/src/intel/tools/tests/gen6/halt.expected
+++ b/src/intel/tools/tests/gen6/halt.expected
@@ -1,4 +1,4 @@
-2a 00 76 00 84 1c 00 20 00 00 8d 02 60 00 62 00
+2a 00 76 00 84 1c 00 20 00 00 8d 02 08 00 08 00
2a 00 60 00 84 1c 00 20 00 00 8d 00 02 00 02 00
-2a 00 96 00 84 1c 00 20 00 00 8d 02 64 00 66 00
+2a 00 96 00 84 1c 00 20 00 00 8d 02 04 00 04 00
2a 00 80 00 84 1c 00 20 00 00 8d 00 02 00 02 00
diff --git a/src/intel/tools/tests/gen6/if.asm b/src/intel/tools/tests/gen6/if.asm
index 532dbda..958a2d6 100644
--- a/src/intel/tools/tests/gen6/if.asm
+++ b/src/intel/tools/tests/gen6/if.asm
@@ -1,6 +1,8 @@
-(+f0.0) if(8) JIP: 84 { align16 1Q };
-(+f0.0) if(8) JIP: 32 { align1 1Q };
-(+f0.0) if(16) JIP: 32 { align1 1H };
-(+f0.0.x) if(8) JIP: 18 { align16 1Q };
-(-f0.0) if(8) JIP: 12 { align1 1Q };
-(-f0.0) if(16) JIP: 12 { align1 1H };
+(+f0.0) if(8) JIP: LABEL0 { align16 1Q };
+LABEL0:
+(+f0.0) if(8) JIP: LABEL1 { align1 1Q };
+(+f0.0) if(16) JIP: LABEL1 { align1 1H };
+(+f0.0.x) if(8) JIP: LABEL1 { align16 1Q };
+(-f0.0) if(8) JIP: LABEL1 { align1 1Q };
+(-f0.0) if(16) JIP: LABEL1 { align1 1H };
+LABEL1:
diff --git a/src/intel/tools/tests/gen6/if.expected b/src/intel/tools/tests/gen6/if.expected
index e5a2666..65c43f9 100644
--- a/src/intel/tools/tests/gen6/if.expected
+++ b/src/intel/tools/tests/gen6/if.expected
@@ -1,6 +1,6 @@
-22 01 61 00 8f 10 54 00 04 00 0e 00 04 00 0e 00
-22 00 61 00 8f 10 20 00 00 00 00 00 00 00 00 00
-22 00 81 00 8f 10 20 00 00 00 00 00 00 00 00 00
-22 01 62 00 8f 10 12 00 04 00 0e 00 04 00 0e 00
-22 00 71 00 8f 10 0c 00 00 00 00 00 00 00 00 00
-22 00 91 00 8f 10 0c 00 00 00 00 00 00 00 00 00
+22 01 61 00 8f 10 02 00 04 00 0e 00 04 00 0e 00
+22 00 61 00 8f 10 0a 00 00 00 00 00 00 00 00 00
+22 00 81 00 8f 10 08 00 00 00 00 00 00 00 00 00
+22 01 62 00 8f 10 06 00 04 00 0e 00 04 00 0e 00
+22 00 71 00 8f 10 04 00 00 00 00 00 00 00 00 00
+22 00 91 00 8f 10 02 00 00 00 00 00 00 00 00 00
diff --git a/src/intel/tools/tests/gen6/while.asm b/src/intel/tools/tests/gen6/while.asm
index 0df3ed7..df99348 100644
--- a/src/intel/tools/tests/gen6/while.asm
+++ b/src/intel/tools/tests/gen6/while.asm
@@ -1,6 +1,7 @@
-while(8) JIP: -76 { align16 1Q };
-while(8) JIP: -108 { align1 1Q };
-while(16) JIP: -108 { align1 1H };
-(-f0.0) while(8) JIP: -48 { align1 1Q };
-(-f0.0) while(16) JIP: -48 { align1 1H };
-(-f0.0.x) while(8) JIP: -48 { align16 1Q };
+LABEL0:
+while(8) JIP: LABEL0 { align16 1Q };
+while(8) JIP: LABEL0 { align1 1Q };
+while(16) JIP: LABEL0 { align1 1H };
+(-f0.0) while(8) JIP: LABEL0 { align1 1Q };
+(-f0.0) while(16) JIP: LABEL0 { align1 1H };
+(-f0.0.x) while(8) JIP: LABEL0 { align16 1Q };
diff --git a/src/intel/tools/tests/gen6/while.expected b/src/intel/tools/tests/gen6/while.expected
index 4ea711e..35f4eb4 100644
--- a/src/intel/tools/tests/gen6/while.expected
+++ b/src/intel/tools/tests/gen6/while.expected
@@ -1,6 +1,6 @@
-27 01 60 00 8f 10 b4 ff 04 00 6e 00 04 00 6e 00
-27 00 60 00 8f 10 94 ff 00 00 8d 00 00 00 8d 00
-27 00 80 00 8f 10 94 ff 00 00 8d 00 00 00 8d 00
-27 00 71 00 8f 10 d0 ff 00 00 8d 00 00 00 8d 00
-27 00 91 00 8f 10 d0 ff 00 00 8d 00 00 00 8d 00
-27 01 72 00 8f 10 d0 ff 04 00 6e 00 04 00 6e 00
+27 01 60 00 8f 10 00 00 04 00 6e 00 04 00 6e 00
+27 00 60 00 8f 10 fe ff 00 00 8d 00 00 00 8d 00
+27 00 80 00 8f 10 fc ff 00 00 8d 00 00 00 8d 00
+27 00 71 00 8f 10 fa ff 00 00 8d 00 00 00 8d 00
+27 00 91 00 8f 10 f8 ff 00 00 8d 00 00 00 8d 00
+27 01 72 00 8f 10 f6 ff 04 00 6e 00 04 00 6e 00
diff --git a/src/intel/tools/tests/gen7.5/break.asm b/src/intel/tools/tests/gen7.5/break.asm
index fb3fb5c..d4c7619 100644
--- a/src/intel/tools/tests/gen7.5/break.asm
+++ b/src/intel/tools/tests/gen7.5/break.asm
@@ -1,6 +1,8 @@
-break(8) JIP: 2 UIP: 8 { align1 1Q };
-break(16) JIP: 2 UIP: 8 { align1 1H };
-break(8) JIP: 2 UIP: 10 { align16 1Q };
-(+f0.0) break(8) JIP: 4 UIP: 10 { align1 1Q };
-(+f0.0) break(16) JIP: 4 UIP: 10 { align1 1H };
-(+f0.0.x) break(8) JIP: 110 UIP: 110 { align16 1Q };
+break(8) JIP: LABEL0 UIP: LABEL1 { align1 1Q };
+break(16) JIP: LABEL0 UIP: LABEL1 { align1 1H };
+break(8) JIP: LABEL0 UIP: LABEL1 { align16 1Q };
+LABEL0:
+(+f0.0) break(8) JIP: LABEL1 UIP: LABEL1 { align1 1Q };
+(+f0.0) break(16) JIP: LABEL1 UIP: LABEL1 { align1 1H };
+(+f0.0.x) break(8) JIP: LABEL1 UIP: LABEL1 { align16 1Q };
+LABEL1:
diff --git a/src/intel/tools/tests/gen7.5/break.expected b/src/intel/tools/tests/gen7.5/break.expected
index 8f8ccc8..309b551 100644
--- a/src/intel/tools/tests/gen7.5/break.expected
+++ b/src/intel/tools/tests/gen7.5/break.expected
@@ -1,6 +1,6 @@
-28 00 60 00 84 1c 00 20 00 00 8d 00 02 00 08 00
-28 00 80 00 84 1c 00 20 00 00 8d 00 02 00 08 00
-28 01 60 00 84 1c 0f 20 04 00 6e 00 02 00 0a 00
-28 00 61 00 84 1c 00 20 00 00 8d 00 04 00 0a 00
-28 00 81 00 84 1c 00 20 00 00 8d 00 04 00 0a 00
-28 01 62 00 84 1c 0f 20 04 00 6e 00 6e 00 6e 00
+28 00 60 00 84 1c 00 20 00 00 8d 00 06 00 0c 00
+28 00 80 00 84 1c 00 20 00 00 8d 00 04 00 0a 00
+28 01 60 00 84 1c 0f 20 04 00 6e 00 02 00 08 00
+28 00 61 00 84 1c 00 20 00 00 8d 00 06 00 06 00
+28 00 81 00 84 1c 00 20 00 00 8d 00 04 00 04 00
+28 01 62 00 84 1c 0f 20 04 00 6e 00 02 00 02 00
diff --git a/src/intel/tools/tests/gen7.5/cont.asm b/src/intel/tools/tests/gen7.5/cont.asm
index 7f7a9c4..497a115 100644
--- a/src/intel/tools/tests/gen7.5/cont.asm
+++ b/src/intel/tools/tests/gen7.5/cont.asm
@@ -1,3 +1,6 @@
-cont(8) JIP: 2 UIP: 8 { align1 1Q };
-cont(16) JIP: 2 UIP: 8 { align1 1H };
-cont(8) JIP: 2 UIP: 8 { align16 1Q };
+cont(8) JIP: LABEL0 UIP: LABEL2 { align1 1Q };
+LABEL0:
+cont(16) JIP: LABEL1 UIP: LABEL2 { align1 1H };
+LABEL1:
+cont(8) JIP: LABEL2 UIP: LABEL2 { align16 1Q };
+LABEL2:
diff --git a/src/intel/tools/tests/gen7.5/cont.expected b/src/intel/tools/tests/gen7.5/cont.expected
index a8376c2..704ea3a 100644
--- a/src/intel/tools/tests/gen7.5/cont.expected
+++ b/src/intel/tools/tests/gen7.5/cont.expected
@@ -1,3 +1,3 @@
-29 00 60 00 00 1c 00 34 00 14 60 00 02 00 08 00
-29 00 80 00 00 1c 00 34 00 14 60 00 02 00 08 00
-29 01 60 00 00 1c 0f 34 04 14 6e 00 02 00 08 00
+29 00 60 00 00 1c 00 34 00 14 60 00 02 00 06 00
+29 00 80 00 00 1c 00 34 00 14 60 00 02 00 04 00
+29 01 60 00 00 1c 0f 34 04 14 6e 00 02 00 02 00
diff --git a/src/intel/tools/tests/gen7.5/else.asm b/src/intel/tools/tests/gen7.5/else.asm
index 080628a..794e4af 100644
--- a/src/intel/tools/tests/gen7.5/else.asm
+++ b/src/intel/tools/tests/gen7.5/else.asm
@@ -1,3 +1,4 @@
-else(8) JIP: 4 { align16 1Q };
-else(8) JIP: 72 { align1 1Q };
-else(16) JIP: 72 { align1 1H };
+else(8) JIP: LABEL0 { align16 1Q };
+else(8) JIP: LABEL0 { align1 1Q };
+else(16) JIP: LABEL0 { align1 1H };
+LABEL0:
\ No newline at end of file
diff --git a/src/intel/tools/tests/gen7.5/else.expected b/src/intel/tools/tests/gen7.5/else.expected
index f780798..4e694cc 100644
--- a/src/intel/tools/tests/gen7.5/else.expected
+++ b/src/intel/tools/tests/gen7.5/else.expected
@@ -1,3 +1,3 @@
-24 01 60 00 84 3c 0f 20 04 00 6e 00 04 00 00 00
-24 00 60 00 84 3c 00 20 00 00 8d 00 48 00 00 00
-24 00 80 00 84 3c 00 20 00 00 8d 00 48 00 00 00
+24 01 60 00 84 3c 0f 20 04 00 6e 00 06 00 00 00
+24 00 60 00 84 3c 00 20 00 00 8d 00 04 00 00 00
+24 00 80 00 84 3c 00 20 00 00 8d 00 02 00 00 00
diff --git a/src/intel/tools/tests/gen7.5/endif.asm b/src/intel/tools/tests/gen7.5/endif.asm
index 4595507..e1dc0eb 100644
--- a/src/intel/tools/tests/gen7.5/endif.asm
+++ b/src/intel/tools/tests/gen7.5/endif.asm
@@ -1,3 +1,5 @@
-endif(8) JIP: 6 { align1 1Q };
-endif(16) JIP: 6 { align1 1H };
-endif(8) JIP: 2 { align16 1Q };
+endif(8) JIP: LABEL0 { align1 1Q };
+LABEL0:
+endif(16) JIP: LABEL1 { align1 1H };
+endif(8) JIP: LABEL1 { align16 1Q };
+LABEL1:
\ No newline at end of file
diff --git a/src/intel/tools/tests/gen7.5/endif.expected b/src/intel/tools/tests/gen7.5/endif.expected
index 73a60a3..5d3b34d 100644
--- a/src/intel/tools/tests/gen7.5/endif.expected
+++ b/src/intel/tools/tests/gen7.5/endif.expected
@@ -1,3 +1,3 @@
-25 00 60 00 84 3c 00 20 00 00 8d 00 06 00 00 00
-25 00 80 00 84 3c 00 20 00 00 8d 00 06 00 00 00
+25 00 60 00 84 3c 00 20 00 00 8d 00 02 00 00 00
+25 00 80 00 84 3c 00 20 00 00 8d 00 04 00 00 00
25 01 60 00 84 3c 0f 20 04 00 6e 00 02 00 00 00
diff --git a/src/intel/tools/tests/gen7.5/halt.asm b/src/intel/tools/tests/gen7.5/halt.asm
index 71ad27b..5f29e88 100644
--- a/src/intel/tools/tests/gen7.5/halt.asm
+++ b/src/intel/tools/tests/gen7.5/halt.asm
@@ -1,4 +1,6 @@
-(-f0.1.any4h) halt(8) JIP: 72 UIP: 74 { align1 1Q };
-halt(8) JIP: 2 UIP: 2 { align1 1Q };
-(-f0.1.any4h) halt(16) JIP: 72 UIP: 74 { align1 1H };
-halt(16) JIP: 2 UIP: 2 { align1 1H };
+(-f0.1.any4h) halt(8) JIP: LABEL0 UIP: LABEL0 { align1 1Q };
+halt(8) JIP: LABEL1 UIP: LABEL1 { align1 1Q };
+LABEL1:
+(-f0.1.any4h) halt(16) JIP: LABEL0 UIP: LABEL0 { align1 1H };
+halt(16) JIP: LABEL0 UIP: LABEL0 { align1 1H };
+LABEL0:
diff --git a/src/intel/tools/tests/gen7.5/halt.expected b/src/intel/tools/tests/gen7.5/halt.expected
index 84b32b1..f76a4b1 100644
--- a/src/intel/tools/tests/gen7.5/halt.expected
+++ b/src/intel/tools/tests/gen7.5/halt.expected
@@ -1,4 +1,4 @@
-2a 00 76 00 84 1c 00 20 00 00 8d 02 48 00 4a 00
+2a 00 76 00 84 1c 00 20 00 00 8d 02 08 00 08 00
2a 00 60 00 84 1c 00 20 00 00 8d 00 02 00 02 00
-2a 00 96 00 84 1c 00 20 00 00 8d 02 48 00 4a 00
+2a 00 96 00 84 1c 00 20 00 00 8d 02 04 00 04 00
2a 00 80 00 84 1c 00 20 00 00 8d 00 02 00 02 00
diff --git a/src/intel/tools/tests/gen7.5/if.asm b/src/intel/tools/tests/gen7.5/if.asm
index 0ebd44d..596e8ed 100644
--- a/src/intel/tools/tests/gen7.5/if.asm
+++ b/src/intel/tools/tests/gen7.5/if.asm
@@ -1,6 +1,9 @@
-(-f0.0) if(8) JIP: 8 UIP: 8 { align1 1Q };
-(-f0.0) if(16) JIP: 8 UIP: 8 { align1 1H };
-(+f0.0.x) if(8) JIP: 18 UIP: 18 { align16 1Q };
-(+f0.0) if(8) JIP: 14 UIP: 14 { align16 1Q };
-(+f0.0) if(8) JIP: 12 UIP: 82 { align1 1Q };
-(+f0.0) if(16) JIP: 12 UIP: 82 { align1 1H };
+(-f0.0) if(8) JIP: LABEL0 UIP: LABEL2 { align1 1Q };
+LABEL0:
+(-f0.0) if(16) JIP: LABEL2 UIP: LABEL1 { align1 1H };
+(+f0.0.x) if(8) JIP: LABEL2 UIP: LABEL1 { align16 1Q };
+LABEL1:
+(+f0.0) if(8) JIP: LABEL2 UIP: LABEL2 { align16 1Q };
+(+f0.0) if(8) JIP: LABEL2 UIP: LABEL2 { align1 1Q };
+(+f0.0) if(16) JIP: LABEL2 UIP: LABEL2 { align1 1H };
+LABEL2:
diff --git a/src/intel/tools/tests/gen7.5/if.expected b/src/intel/tools/tests/gen7.5/if.expected
index d2bccde..2cb44c1 100644
--- a/src/intel/tools/tests/gen7.5/if.expected
+++ b/src/intel/tools/tests/gen7.5/if.expected
@@ -1,6 +1,6 @@
-22 00 71 00 84 3c 00 20 00 00 00 00 08 00 08 00
-22 00 91 00 84 3c 00 20 00 00 00 00 08 00 08 00
-22 01 62 00 84 3c 0f 20 04 00 0e 00 12 00 12 00
-22 01 61 00 84 3c 0f 20 04 00 0e 00 0e 00 0e 00
-22 00 61 00 84 3c 00 20 00 00 00 00 0c 00 52 00
-22 00 81 00 84 3c 00 20 00 00 00 00 0c 00 52 00
+22 00 71 00 84 3c 00 20 00 00 00 00 02 00 0c 00
+22 00 91 00 84 3c 00 20 00 00 00 00 0a 00 04 00
+22 01 62 00 84 3c 0f 20 04 00 0e 00 08 00 02 00
+22 01 61 00 84 3c 0f 20 04 00 0e 00 06 00 06 00
+22 00 61 00 84 3c 00 20 00 00 00 00 04 00 04 00
+22 00 81 00 84 3c 00 20 00 00 00 00 02 00 02 00
diff --git a/src/intel/tools/tests/gen7.5/while.asm b/src/intel/tools/tests/gen7.5/while.asm
index a6d5abc..035f965 100644
--- a/src/intel/tools/tests/gen7.5/while.asm
+++ b/src/intel/tools/tests/gen7.5/while.asm
@@ -1,6 +1,7 @@
-while(8) JIP: -20 { align1 1Q };
-while(16) JIP: -20 { align1 1H };
-while(8) JIP: -30 { align16 1Q };
-(-f0.0) while(8) JIP: -48 { align1 1Q };
-(-f0.0) while(16) JIP: -48 { align1 1H };
-(-f0.0.x) while(8) JIP: -48 { align16 1Q };
+LABEL0:
+while(8) JIP: LABEL0 { align1 1Q };
+while(16) JIP: LABEL0 { align1 1H };
+while(8) JIP: LABEL0 { align16 1Q };
+(-f0.0) while(8) JIP: LABEL0 { align1 1Q };
+(-f0.0) while(16) JIP: LABEL0 { align1 1H };
+(-f0.0.x) while(8) JIP: LABEL0 { align16 1Q };
diff --git a/src/intel/tools/tests/gen7.5/while.expected b/src/intel/tools/tests/gen7.5/while.expected
index 769cbaf..2ea22612 100644
--- a/src/intel/tools/tests/gen7.5/while.expected
+++ b/src/intel/tools/tests/gen7.5/while.expected
@@ -1,6 +1,6 @@
-27 00 60 00 84 3c 00 20 00 00 8d 00 ec ff 00 00
-27 00 80 00 84 3c 00 20 00 00 8d 00 ec ff 00 00
-27 01 60 00 84 3c 0f 20 04 00 6e 00 e2 ff 00 00
-27 00 71 00 84 3c 00 20 00 00 8d 00 d0 ff 00 00
-27 00 91 00 84 3c 00 20 00 00 8d 00 d0 ff 00 00
-27 01 72 00 84 3c 0f 20 04 00 6e 00 d0 ff 00 00
+27 00 60 00 84 3c 00 20 00 00 8d 00 00 00 00 00
+27 00 80 00 84 3c 00 20 00 00 8d 00 fe ff 00 00
+27 01 60 00 84 3c 0f 20 04 00 6e 00 fc ff 00 00
+27 00 71 00 84 3c 00 20 00 00 8d 00 fa ff 00 00
+27 00 91 00 84 3c 00 20 00 00 8d 00 f8 ff 00 00
+27 01 72 00 84 3c 0f 20 04 00 6e 00 f6 ff 00 00
diff --git a/src/intel/tools/tests/gen7/break.asm b/src/intel/tools/tests/gen7/break.asm
index 5a51f7a..ae39f9a 100644
--- a/src/intel/tools/tests/gen7/break.asm
+++ b/src/intel/tools/tests/gen7/break.asm
@@ -1,6 +1,9 @@
-break(8) JIP: 2 UIP: 40 { align1 1Q };
-break(16) JIP: 2 UIP: 48 { align1 1H };
-(+f0.0.x) break(8) JIP: 110 UIP: 110 { align16 1Q };
-(+f0.0) break(8) JIP: 2 UIP: 12 { align1 1Q };
-(+f0.0) break(16) JIP: 2 UIP: 12 { align1 1H };
-break(8) JIP: 2 UIP: 38 { align16 1Q };
+break(8) JIP: LABEL0 UIP: LABEL0 { align1 1Q };
+LABEL0:
+break(16) JIP: LABEL1 UIP: LABEL2 { align1 1H };
+(+f0.0.x) break(8) JIP: LABEL1 UIP: LABEL2 { align16 1Q };
+LABEL1:
+(+f0.0) break(8) JIP: LABEL2 UIP: LABEL2 { align1 1Q };
+(+f0.0) break(16) JIP: LABEL2 UIP: LABEL2 { align1 1H };
+break(8) JIP: LABEL2 UIP: LABEL2 { align16 1Q };
+LABEL2:
\ No newline at end of file
diff --git a/src/intel/tools/tests/gen7/break.expected b/src/intel/tools/tests/gen7/break.expected
index 9cc7f8a..7ded8f0 100644
--- a/src/intel/tools/tests/gen7/break.expected
+++ b/src/intel/tools/tests/gen7/break.expected
@@ -1,6 +1,6 @@
-28 00 60 00 84 1c 00 20 00 00 8d 00 02 00 28 00
-28 00 80 00 84 1c 00 20 00 00 8d 00 02 00 30 00
-28 01 62 00 84 1c 0f 20 04 00 6e 00 6e 00 6e 00
-28 00 61 00 84 1c 00 20 00 00 8d 00 02 00 0c 00
-28 00 81 00 84 1c 00 20 00 00 8d 00 02 00 0c 00
-28 01 60 00 84 1c 0f 20 04 00 6e 00 02 00 26 00
+28 00 60 00 84 1c 00 20 00 00 8d 00 02 00 02 00
+28 00 80 00 84 1c 00 20 00 00 8d 00 04 00 0a 00
+28 01 62 00 84 1c 0f 20 04 00 6e 00 02 00 08 00
+28 00 61 00 84 1c 00 20 00 00 8d 00 06 00 06 00
+28 00 81 00 84 1c 00 20 00 00 8d 00 04 00 04 00
+28 01 60 00 84 1c 0f 20 04 00 6e 00 02 00 02 00
diff --git a/src/intel/tools/tests/gen7/else.asm b/src/intel/tools/tests/gen7/else.asm
index 71a09a3..5450c0f 100644
--- a/src/intel/tools/tests/gen7/else.asm
+++ b/src/intel/tools/tests/gen7/else.asm
@@ -1,3 +1,4 @@
-else(8) JIP: 12 { align1 1Q };
-else(16) JIP: 12 { align1 1H };
-else(8) JIP: 18 { align16 1Q };
+else(8) JIP: LABEL0 { align1 1Q };
+else(16) JIP: LABEL0 { align1 1H };
+else(8) JIP: LABEL0 { align16 1Q };
+LABEL0:
diff --git a/src/intel/tools/tests/gen7/else.expected b/src/intel/tools/tests/gen7/else.expected
index 86cf63f..1c4b351 100644
--- a/src/intel/tools/tests/gen7/else.expected
+++ b/src/intel/tools/tests/gen7/else.expected
@@ -1,3 +1,3 @@
-24 00 60 00 84 3c 00 20 00 00 8d 00 0c 00 00 00
-24 00 80 00 84 3c 00 20 00 00 8d 00 0c 00 00 00
-24 01 60 00 84 3c 0f 20 04 00 6e 00 12 00 00 00
+24 00 60 00 84 3c 00 20 00 00 8d 00 06 00 00 00
+24 00 80 00 84 3c 00 20 00 00 8d 00 04 00 00 00
+24 01 60 00 84 3c 0f 20 04 00 6e 00 02 00 00 00
diff --git a/src/intel/tools/tests/gen7/endif.asm b/src/intel/tools/tests/gen7/endif.asm
index b3a5066..fc00e24 100644
--- a/src/intel/tools/tests/gen7/endif.asm
+++ b/src/intel/tools/tests/gen7/endif.asm
@@ -1,3 +1,6 @@
-endif(8) JIP: 2 { align16 1Q };
-endif(8) JIP: 2 { align1 1Q };
-endif(16) JIP: 2 { align1 1H };
+endif(8) JIP: LABEL1 { align16 1Q };
+LABEL1:
+endif(8) JIP: LABEL2 { align1 1Q };
+LABEL2:
+endif(16) JIP: LABEL3 { align1 1H };
+LABEL3:
diff --git a/src/intel/tools/tests/gen7/halt.asm b/src/intel/tools/tests/gen7/halt.asm
index 0a06cc5..5f29e88 100644
--- a/src/intel/tools/tests/gen7/halt.asm
+++ b/src/intel/tools/tests/gen7/halt.asm
@@ -1,4 +1,6 @@
-(-f0.1.any4h) halt(8) JIP: 72 UIP: 74 { align1 1Q };
-halt(8) JIP: 2 UIP: 2 { align1 1Q };
-(-f0.1.any4h) halt(16) JIP: 76 UIP: 78 { align1 1H };
-halt(16) JIP: 2 UIP: 2 { align1 1H };
+(-f0.1.any4h) halt(8) JIP: LABEL0 UIP: LABEL0 { align1 1Q };
+halt(8) JIP: LABEL1 UIP: LABEL1 { align1 1Q };
+LABEL1:
+(-f0.1.any4h) halt(16) JIP: LABEL0 UIP: LABEL0 { align1 1H };
+halt(16) JIP: LABEL0 UIP: LABEL0 { align1 1H };
+LABEL0:
diff --git a/src/intel/tools/tests/gen7/halt.expected b/src/intel/tools/tests/gen7/halt.expected
index edc7d9e..f76a4b1 100644
--- a/src/intel/tools/tests/gen7/halt.expected
+++ b/src/intel/tools/tests/gen7/halt.expected
@@ -1,4 +1,4 @@
-2a 00 76 00 84 1c 00 20 00 00 8d 02 48 00 4a 00
+2a 00 76 00 84 1c 00 20 00 00 8d 02 08 00 08 00
2a 00 60 00 84 1c 00 20 00 00 8d 00 02 00 02 00
-2a 00 96 00 84 1c 00 20 00 00 8d 02 4c 00 4e 00
+2a 00 96 00 84 1c 00 20 00 00 8d 02 04 00 04 00
2a 00 80 00 84 1c 00 20 00 00 8d 00 02 00 02 00
diff --git a/src/intel/tools/tests/gen7/if.asm b/src/intel/tools/tests/gen7/if.asm
index e6d096d..5e6bb07 100644
--- a/src/intel/tools/tests/gen7/if.asm
+++ b/src/intel/tools/tests/gen7/if.asm
@@ -1,6 +1,9 @@
-(+f0.0.x) if(8) JIP: 18 UIP: 18 { align16 1Q };
-(+f0.0) if(8) JIP: 14 UIP: 14 { align16 1Q };
-(+f0.0) if(8) JIP: 32 UIP: 96 { align1 1Q };
-(+f0.0) if(16) JIP: 32 UIP: 96 { align1 1H };
-(-f0.0) if(8) JIP: 10 UIP: 10 { align1 1Q };
-(-f0.0) if(16) JIP: 10 UIP: 10 { align1 1H };
+(+f0.0.x) if(8) JIP: LABEL0 UIP: LABEL2 { align16 1Q };
+LABEL0:
+(+f0.0) if(8) JIP: LABEL2 UIP: LABEL1 { align16 1Q };
+(+f0.0) if(8) JIP: LABEL2 UIP: LABEL1 { align1 1Q };
+LABEL1:
+(+f0.0) if(16) JIP: LABEL2 UIP: LABEL2 { align1 1H };
+(-f0.0) if(8) JIP: LABEL2 UIP: LABEL2 { align1 1Q };
+(-f0.0) if(16) JIP: LABEL2 UIP: LABEL2 { align1 1H };
+LABEL2:
diff --git a/src/intel/tools/tests/gen7/if.expected b/src/intel/tools/tests/gen7/if.expected
index c08f2ff..e5e6c19 100644
--- a/src/intel/tools/tests/gen7/if.expected
+++ b/src/intel/tools/tests/gen7/if.expected
@@ -1,6 +1,6 @@
-22 01 62 00 84 3c 0f 20 04 00 0e 00 12 00 12 00
-22 01 61 00 84 3c 0f 20 04 00 0e 00 0e 00 0e 00
-22 00 61 00 84 3c 00 20 00 00 00 00 20 00 60 00
-22 00 81 00 84 3c 00 20 00 00 00 00 20 00 60 00
-22 00 71 00 84 3c 00 20 00 00 00 00 0a 00 0a 00
-22 00 91 00 84 3c 00 20 00 00 00 00 0a 00 0a 00
+22 01 62 00 84 3c 0f 20 04 00 0e 00 02 00 0c 00
+22 01 61 00 84 3c 0f 20 04 00 0e 00 0a 00 04 00
+22 00 61 00 84 3c 00 20 00 00 00 00 08 00 02 00
+22 00 81 00 84 3c 00 20 00 00 00 00 06 00 06 00
+22 00 71 00 84 3c 00 20 00 00 00 00 04 00 04 00
+22 00 91 00 84 3c 00 20 00 00 00 00 02 00 02 00
diff --git a/src/intel/tools/tests/gen7/while.asm b/src/intel/tools/tests/gen7/while.asm
index be4e182..8465a91 100644
--- a/src/intel/tools/tests/gen7/while.asm
+++ b/src/intel/tools/tests/gen7/while.asm
@@ -1,5 +1,6 @@
-while(8) JIP: -50 { align1 1Q };
-while(16) JIP: -58 { align1 1H };
-while(8) JIP: -8 { align16 1Q };
-(-f0.0) while(8) JIP: -10 { align1 1Q };
-(-f0.0) while(16) JIP: -10 { align1 1H };
+LABEL0:
+while(8) JIP: LABEL0 { align1 1Q };
+while(16) JIP: LABEL0 { align1 1H };
+while(8) JIP: LABEL0 { align16 1Q };
+(-f0.0) while(8) JIP: LABEL0 { align1 1Q };
+(-f0.0) while(16) JIP: LABEL0 { align1 1H };
diff --git a/src/intel/tools/tests/gen7/while.expected b/src/intel/tools/tests/gen7/while.expected
index 70dd598..379819a 100644
--- a/src/intel/tools/tests/gen7/while.expected
+++ b/src/intel/tools/tests/gen7/while.expected
@@ -1,5 +1,5 @@
-27 00 60 00 84 3c 00 20 00 00 8d 00 ce ff 00 00
-27 00 80 00 84 3c 00 20 00 00 8d 00 c6 ff 00 00
-27 01 60 00 84 3c 0f 20 04 00 6e 00 f8 ff 00 00
-27 00 71 00 84 3c 00 20 00 00 8d 00 f6 ff 00 00
-27 00 91 00 84 3c 00 20 00 00 8d 00 f6 ff 00 00
+27 00 60 00 84 3c 00 20 00 00 8d 00 00 00 00 00
+27 00 80 00 84 3c 00 20 00 00 8d 00 fe ff 00 00
+27 01 60 00 84 3c 0f 20 04 00 6e 00 fc ff 00 00
+27 00 71 00 84 3c 00 20 00 00 8d 00 fa ff 00 00
+27 00 91 00 84 3c 00 20 00 00 8d 00 f8 ff 00 00
diff --git a/src/intel/tools/tests/gen8/break.asm b/src/intel/tools/tests/gen8/break.asm
index 093ae61..681b3d2 100644
--- a/src/intel/tools/tests/gen8/break.asm
+++ b/src/intel/tools/tests/gen8/break.asm
@@ -1,4 +1,6 @@
-break(8) JIP: 16 UIP: 64 { align1 1Q };
-break(16) JIP: 16 UIP: 64 { align1 1H };
-(+f0.0) break(8) JIP: 32 UIP: 80 { align1 1Q };
-(+f0.0) break(16) JIP: 32 UIP: 80 { align1 1H };
+break(8) JIP: LABEL0 UIP: LABEL1 { align1 1Q };
+break(16) JIP: LABEL0 UIP: LABEL1 { align1 1H };
+LABEL0:
+(+f0.0) break(8) JIP: LABEL1 UIP: LABEL1 { align1 1Q };
+(+f0.0) break(16) JIP: LABEL1 UIP: LABEL1 { align1 1H };
+LABEL1:
diff --git a/src/intel/tools/tests/gen8/break.expected b/src/intel/tools/tests/gen8/break.expected
index 305af58..f5448cd 100644
--- a/src/intel/tools/tests/gen8/break.expected
+++ b/src/intel/tools/tests/gen8/break.expected
@@ -1,4 +1,4 @@
-28 00 60 00 20 0e 00 20 40 00 00 00 10 00 00 00
-28 00 80 00 20 0e 00 20 40 00 00 00 10 00 00 00
-28 00 61 00 20 0e 00 20 50 00 00 00 20 00 00 00
-28 00 81 00 20 0e 00 20 50 00 00 00 20 00 00 00
+28 00 60 00 20 0e 00 20 40 00 00 00 20 00 00 00
+28 00 80 00 20 0e 00 20 30 00 00 00 10 00 00 00
+28 00 61 00 20 0e 00 20 20 00 00 00 20 00 00 00
+28 00 81 00 20 0e 00 20 10 00 00 00 10 00 00 00
diff --git a/src/intel/tools/tests/gen8/cont.asm b/src/intel/tools/tests/gen8/cont.asm
index c5a194b..ca97a55 100644
--- a/src/intel/tools/tests/gen8/cont.asm
+++ b/src/intel/tools/tests/gen8/cont.asm
@@ -1,2 +1,4 @@
-cont(8) JIP: 16 UIP: 64 { align1 1Q };
-cont(16) JIP: 16 UIP: 64 { align1 1H };
+cont(8) JIP: LABEL0 UIP: LABEL1 { align1 1Q };
+LABEL0:
+cont(16) JIP: LABEL1 UIP: LABEL1 { align1 1H };
+LABEL1:
diff --git a/src/intel/tools/tests/gen8/cont.expected b/src/intel/tools/tests/gen8/cont.expected
index 83aa4f5..d8036df 100644
--- a/src/intel/tools/tests/gen8/cont.expected
+++ b/src/intel/tools/tests/gen8/cont.expected
@@ -1,2 +1,2 @@
-29 00 60 00 00 0e 00 34 40 00 00 00 10 00 00 00
-29 00 80 00 00 0e 00 34 40 00 00 00 10 00 00 00
+29 00 60 00 00 0e 00 34 20 00 00 00 10 00 00 00
+29 00 80 00 00 0e 00 34 10 00 00 00 10 00 00 00
diff --git a/src/intel/tools/tests/gen8/else.asm b/src/intel/tools/tests/gen8/else.asm
index 837df09..ce868a2 100644
--- a/src/intel/tools/tests/gen8/else.asm
+++ b/src/intel/tools/tests/gen8/else.asm
@@ -1,3 +1,4 @@
-else(8) JIP: 288 UIP: 288 { align1 1Q };
-else(16) JIP: 240 UIP: 240 { align1 1H };
-else(32) JIP: 144 UIP: 144 { align1 };
+else(8) JIP: LABEL0 UIP: LABEL0 { align1 1Q };
+else(16) JIP: LABEL0 UIP: LABEL0 { align1 1H };
+else(32) JIP: LABEL0 UIP: LABEL0 { align1 };
+LABEL0:
\ No newline at end of file
diff --git a/src/intel/tools/tests/gen8/else.expected b/src/intel/tools/tests/gen8/else.expected
index 1394b46..c7834d7 100644
--- a/src/intel/tools/tests/gen8/else.expected
+++ b/src/intel/tools/tests/gen8/else.expected
@@ -1,3 +1,3 @@
-24 00 60 00 20 0e 00 20 20 01 00 00 20 01 00 00
-24 00 80 00 20 0e 00 20 f0 00 00 00 f0 00 00 00
-24 00 a0 00 20 0e 00 20 90 00 00 00 90 00 00 00
+24 00 60 00 20 0e 00 20 30 00 00 00 30 00 00 00
+24 00 80 00 20 0e 00 20 20 00 00 00 20 00 00 00
+24 00 a0 00 20 0e 00 20 10 00 00 00 10 00 00 00
diff --git a/src/intel/tools/tests/gen8/endif.asm b/src/intel/tools/tests/gen8/endif.asm
index bfd04ea..206798e 100644
--- a/src/intel/tools/tests/gen8/endif.asm
+++ b/src/intel/tools/tests/gen8/endif.asm
@@ -1,3 +1,4 @@
-endif(8) JIP: 80 { align1 1Q };
-endif(16) JIP: 48 { align1 1H };
-endif(32) JIP: 16 { align1 };
+endif(8) JIP: LABEL0 { align1 1Q };
+endif(16) JIP: LABEL0 { align1 1H };
+endif(32) JIP: LABEL0 { align1 };
+LABEL0:
diff --git a/src/intel/tools/tests/gen8/endif.expected b/src/intel/tools/tests/gen8/endif.expected
index 898a148..5f6a9fe 100644
--- a/src/intel/tools/tests/gen8/endif.expected
+++ b/src/intel/tools/tests/gen8/endif.expected
@@ -1,3 +1,3 @@
-25 00 60 00 00 0e 00 00 00 00 00 08 50 00 00 00
-25 00 80 00 00 0e 00 00 00 00 00 08 30 00 00 00
+25 00 60 00 00 0e 00 00 00 00 00 08 30 00 00 00
+25 00 80 00 00 0e 00 00 00 00 00 08 20 00 00 00
25 00 a0 00 00 0e 00 00 00 00 00 08 10 00 00 00
diff --git a/src/intel/tools/tests/gen8/halt.asm b/src/intel/tools/tests/gen8/halt.asm
index d844326..726d191 100644
--- a/src/intel/tools/tests/gen8/halt.asm
+++ b/src/intel/tools/tests/gen8/halt.asm
@@ -1,4 +1,6 @@
-(-f0.1.any4h) halt(8) JIP: 176 UIP: 192 { align1 1Q };
-halt(8) JIP: 16 UIP: 16 { align1 1Q };
-(-f0.1.any4h) halt(16) JIP: 176 UIP: 192 { align1 1H };
-halt(16) JIP: 16 UIP: 16 { align1 1H };
+(-f0.1.any4h) halt(8) JIP: LABEL0 UIP: LABEL0 { align1 1Q };
+halt(8) JIP: LABEL1 UIP: LABEL1 { align1 1Q };
+LABEL1:
+(-f0.1.any4h) halt(16) JIP: LABEL0 UIP: LABEL0 { align1 1H };
+halt(16) JIP: LABEL0 UIP: LABEL0 { align1 1H };
+LABEL0:
\ No newline at end of file
diff --git a/src/intel/tools/tests/gen8/halt.expected b/src/intel/tools/tests/gen8/halt.expected
index 4e4573d..b0867fe 100644
--- a/src/intel/tools/tests/gen8/halt.expected
+++ b/src/intel/tools/tests/gen8/halt.expected
@@ -1,4 +1,4 @@
-2a 00 76 00 21 0e 00 20 c0 00 00 00 b0 00 00 00
+2a 00 76 00 21 0e 00 20 40 00 00 00 40 00 00 00
2a 00 60 00 20 0e 00 20 10 00 00 00 10 00 00 00
-2a 00 96 00 21 0e 00 20 c0 00 00 00 b0 00 00 00
+2a 00 96 00 21 0e 00 20 20 00 00 00 20 00 00 00
2a 00 80 00 20 0e 00 20 10 00 00 00 10 00 00 00
diff --git a/src/intel/tools/tests/gen8/if.asm b/src/intel/tools/tests/gen8/if.asm
index 5eb7b53..d6f8b84 100644
--- a/src/intel/tools/tests/gen8/if.asm
+++ b/src/intel/tools/tests/gen8/if.asm
@@ -1,5 +1,7 @@
-(+f0.0) if(8) JIP: 1376 UIP: 1392 { align1 1Q };
-(-f0.0) if(8) JIP: 4704 UIP: 4704 { align1 1Q };
-(-f0.0) if(16) JIP: 64 UIP: 64 { align1 1H };
-(+f0.0) if(16) JIP: 96 UIP: 320 { align1 1H };
-(+f0.0) if(32) JIP: 80 UIP: 80 { align1 };
+(+f0.0) if(8) JIP: LABEL0 UIP: LABEL1 { align1 1Q };
+(-f0.0) if(8) JIP: LABEL0 UIP: LABEL1 { align1 1Q };
+LABEL0:
+(-f0.0) if(16) JIP: LABEL1 UIP: LABEL1 { align1 1H };
+(+f0.0) if(16) JIP: LABEL1 UIP: LABEL1 { align1 1H };
+(+f0.0) if(32) JIP: LABEL1 UIP: LABEL1 { align1 };
+LABEL1:
diff --git a/src/intel/tools/tests/gen8/if.expected b/src/intel/tools/tests/gen8/if.expected
index b2fc285..d11bebc 100644
--- a/src/intel/tools/tests/gen8/if.expected
+++ b/src/intel/tools/tests/gen8/if.expected
@@ -1,5 +1,5 @@
-22 00 61 00 20 0e 00 20 70 05 00 00 60 05 00 00
-22 00 71 00 20 0e 00 20 60 12 00 00 60 12 00 00
-22 00 91 00 20 0e 00 20 40 00 00 00 40 00 00 00
-22 00 81 00 20 0e 00 20 40 01 00 00 60 00 00 00
-22 00 a1 00 20 0e 00 20 50 00 00 00 50 00 00 00
+22 00 61 00 20 0e 00 20 50 00 00 00 20 00 00 00
+22 00 71 00 20 0e 00 20 40 00 00 00 10 00 00 00
+22 00 91 00 20 0e 00 20 30 00 00 00 30 00 00 00
+22 00 81 00 20 0e 00 20 20 00 00 00 20 00 00 00
+22 00 a1 00 20 0e 00 20 10 00 00 00 10 00 00 00
diff --git a/src/intel/tools/tests/gen8/while.asm b/src/intel/tools/tests/gen8/while.asm
index 00bd8e1..7aaae75 100644
--- a/src/intel/tools/tests/gen8/while.asm
+++ b/src/intel/tools/tests/gen8/while.asm
@@ -1,4 +1,5 @@
-while(8) JIP: -160 { align1 1Q };
-while(16) JIP: -160 { align1 1H };
-(-f0.0) while(8) JIP: -384 { align1 1Q };
-(-f0.0) while(16) JIP: -384 { align1 1H };
+LABEL0:
+while(8) JIP: LABEL0 { align1 1Q };
+while(16) JIP: LABEL0 { align1 1H };
+(-f0.0) while(8) JIP: LABEL0 { align1 1Q };
+(-f0.0) while(16) JIP: LABEL0 { align1 1H };
diff --git a/src/intel/tools/tests/gen8/while.expected b/src/intel/tools/tests/gen8/while.expected
index 5b0fd85..8b6c4da 100644
--- a/src/intel/tools/tests/gen8/while.expected
+++ b/src/intel/tools/tests/gen8/while.expected
@@ -1,4 +1,4 @@
-27 00 60 00 20 0e 00 20 00 00 00 08 60 ff ff ff
-27 00 80 00 20 0e 00 20 00 00 00 08 60 ff ff ff
-27 00 71 00 20 0e 00 20 00 00 00 08 80 fe ff ff
-27 00 91 00 20 0e 00 20 00 00 00 08 80 fe ff ff
+27 00 60 00 20 0e 00 20 00 00 00 08 00 00 00 00
+27 00 80 00 20 0e 00 20 00 00 00 08 f0 ff ff ff
+27 00 71 00 20 0e 00 20 00 00 00 08 e0 ff ff ff
+27 00 91 00 20 0e 00 20 00 00 00 08 d0 ff ff ff
diff --git a/src/intel/tools/tests/gen9/break.asm b/src/intel/tools/tests/gen9/break.asm
index 093ae61..681b3d2 100644
--- a/src/intel/tools/tests/gen9/break.asm
+++ b/src/intel/tools/tests/gen9/break.asm
@@ -1,4 +1,6 @@
-break(8) JIP: 16 UIP: 64 { align1 1Q };
-break(16) JIP: 16 UIP: 64 { align1 1H };
-(+f0.0) break(8) JIP: 32 UIP: 80 { align1 1Q };
-(+f0.0) break(16) JIP: 32 UIP: 80 { align1 1H };
+break(8) JIP: LABEL0 UIP: LABEL1 { align1 1Q };
+break(16) JIP: LABEL0 UIP: LABEL1 { align1 1H };
+LABEL0:
+(+f0.0) break(8) JIP: LABEL1 UIP: LABEL1 { align1 1Q };
+(+f0.0) break(16) JIP: LABEL1 UIP: LABEL1 { align1 1H };
+LABEL1:
diff --git a/src/intel/tools/tests/gen9/break.expected b/src/intel/tools/tests/gen9/break.expected
index 305af58..f5448cd 100644
--- a/src/intel/tools/tests/gen9/break.expected
+++ b/src/intel/tools/tests/gen9/break.expected
@@ -1,4 +1,4 @@
-28 00 60 00 20 0e 00 20 40 00 00 00 10 00 00 00
-28 00 80 00 20 0e 00 20 40 00 00 00 10 00 00 00
-28 00 61 00 20 0e 00 20 50 00 00 00 20 00 00 00
-28 00 81 00 20 0e 00 20 50 00 00 00 20 00 00 00
+28 00 60 00 20 0e 00 20 40 00 00 00 20 00 00 00
+28 00 80 00 20 0e 00 20 30 00 00 00 10 00 00 00
+28 00 61 00 20 0e 00 20 20 00 00 00 20 00 00 00
+28 00 81 00 20 0e 00 20 10 00 00 00 10 00 00 00
diff --git a/src/intel/tools/tests/gen9/cont.asm b/src/intel/tools/tests/gen9/cont.asm
index c5a194b..ca97a55 100644
--- a/src/intel/tools/tests/gen9/cont.asm
+++ b/src/intel/tools/tests/gen9/cont.asm
@@ -1,2 +1,4 @@
-cont(8) JIP: 16 UIP: 64 { align1 1Q };
-cont(16) JIP: 16 UIP: 64 { align1 1H };
+cont(8) JIP: LABEL0 UIP: LABEL1 { align1 1Q };
+LABEL0:
+cont(16) JIP: LABEL1 UIP: LABEL1 { align1 1H };
+LABEL1:
diff --git a/src/intel/tools/tests/gen9/cont.expected b/src/intel/tools/tests/gen9/cont.expected
index 83aa4f5..d8036df 100644
--- a/src/intel/tools/tests/gen9/cont.expected
+++ b/src/intel/tools/tests/gen9/cont.expected
@@ -1,2 +1,2 @@
-29 00 60 00 00 0e 00 34 40 00 00 00 10 00 00 00
-29 00 80 00 00 0e 00 34 40 00 00 00 10 00 00 00
+29 00 60 00 00 0e 00 34 20 00 00 00 10 00 00 00
+29 00 80 00 00 0e 00 34 10 00 00 00 10 00 00 00
diff --git a/src/intel/tools/tests/gen9/else.asm b/src/intel/tools/tests/gen9/else.asm
index 8324624..ce868a2 100644
--- a/src/intel/tools/tests/gen9/else.asm
+++ b/src/intel/tools/tests/gen9/else.asm
@@ -1,3 +1,4 @@
-else(8) JIP: 288 UIP: 288 { align1 1Q };
-else(16) JIP: 240 UIP: 240 { align1 1H };
-else(32) JIP: 272 UIP: 272 { align1 };
+else(8) JIP: LABEL0 UIP: LABEL0 { align1 1Q };
+else(16) JIP: LABEL0 UIP: LABEL0 { align1 1H };
+else(32) JIP: LABEL0 UIP: LABEL0 { align1 };
+LABEL0:
\ No newline at end of file
diff --git a/src/intel/tools/tests/gen9/else.expected b/src/intel/tools/tests/gen9/else.expected
index 44503c7f..c7834d7 100644
--- a/src/intel/tools/tests/gen9/else.expected
+++ b/src/intel/tools/tests/gen9/else.expected
@@ -1,3 +1,3 @@
-24 00 60 00 20 0e 00 20 20 01 00 00 20 01 00 00
-24 00 80 00 20 0e 00 20 f0 00 00 00 f0 00 00 00
-24 00 a0 00 20 0e 00 20 10 01 00 00 10 01 00 00
+24 00 60 00 20 0e 00 20 30 00 00 00 30 00 00 00
+24 00 80 00 20 0e 00 20 20 00 00 00 20 00 00 00
+24 00 a0 00 20 0e 00 20 10 00 00 00 10 00 00 00
diff --git a/src/intel/tools/tests/gen9/endif.asm b/src/intel/tools/tests/gen9/endif.asm
index bfd04ea..206798e 100644
--- a/src/intel/tools/tests/gen9/endif.asm
+++ b/src/intel/tools/tests/gen9/endif.asm
@@ -1,3 +1,4 @@
-endif(8) JIP: 80 { align1 1Q };
-endif(16) JIP: 48 { align1 1H };
-endif(32) JIP: 16 { align1 };
+endif(8) JIP: LABEL0 { align1 1Q };
+endif(16) JIP: LABEL0 { align1 1H };
+endif(32) JIP: LABEL0 { align1 };
+LABEL0:
diff --git a/src/intel/tools/tests/gen9/endif.expected b/src/intel/tools/tests/gen9/endif.expected
index 898a148..5f6a9fe 100644
--- a/src/intel/tools/tests/gen9/endif.expected
+++ b/src/intel/tools/tests/gen9/endif.expected
@@ -1,3 +1,3 @@
-25 00 60 00 00 0e 00 00 00 00 00 08 50 00 00 00
-25 00 80 00 00 0e 00 00 00 00 00 08 30 00 00 00
+25 00 60 00 00 0e 00 00 00 00 00 08 30 00 00 00
+25 00 80 00 00 0e 00 00 00 00 00 08 20 00 00 00
25 00 a0 00 00 0e 00 00 00 00 00 08 10 00 00 00
diff --git a/src/intel/tools/tests/gen9/halt.asm b/src/intel/tools/tests/gen9/halt.asm
index d844326..726d191 100644
--- a/src/intel/tools/tests/gen9/halt.asm
+++ b/src/intel/tools/tests/gen9/halt.asm
@@ -1,4 +1,6 @@
-(-f0.1.any4h) halt(8) JIP: 176 UIP: 192 { align1 1Q };
-halt(8) JIP: 16 UIP: 16 { align1 1Q };
-(-f0.1.any4h) halt(16) JIP: 176 UIP: 192 { align1 1H };
-halt(16) JIP: 16 UIP: 16 { align1 1H };
+(-f0.1.any4h) halt(8) JIP: LABEL0 UIP: LABEL0 { align1 1Q };
+halt(8) JIP: LABEL1 UIP: LABEL1 { align1 1Q };
+LABEL1:
+(-f0.1.any4h) halt(16) JIP: LABEL0 UIP: LABEL0 { align1 1H };
+halt(16) JIP: LABEL0 UIP: LABEL0 { align1 1H };
+LABEL0:
\ No newline at end of file
diff --git a/src/intel/tools/tests/gen9/halt.expected b/src/intel/tools/tests/gen9/halt.expected
index 4e4573d..b0867fe 100644
--- a/src/intel/tools/tests/gen9/halt.expected
+++ b/src/intel/tools/tests/gen9/halt.expected
@@ -1,4 +1,4 @@
-2a 00 76 00 21 0e 00 20 c0 00 00 00 b0 00 00 00
+2a 00 76 00 21 0e 00 20 40 00 00 00 40 00 00 00
2a 00 60 00 20 0e 00 20 10 00 00 00 10 00 00 00
-2a 00 96 00 21 0e 00 20 c0 00 00 00 b0 00 00 00
+2a 00 96 00 21 0e 00 20 20 00 00 00 20 00 00 00
2a 00 80 00 20 0e 00 20 10 00 00 00 10 00 00 00
diff --git a/src/intel/tools/tests/gen9/if.asm b/src/intel/tools/tests/gen9/if.asm
index 5eb7b53..e5192c4 100644
--- a/src/intel/tools/tests/gen9/if.asm
+++ b/src/intel/tools/tests/gen9/if.asm
@@ -1,5 +1,7 @@
-(+f0.0) if(8) JIP: 1376 UIP: 1392 { align1 1Q };
-(-f0.0) if(8) JIP: 4704 UIP: 4704 { align1 1Q };
-(-f0.0) if(16) JIP: 64 UIP: 64 { align1 1H };
-(+f0.0) if(16) JIP: 96 UIP: 320 { align1 1H };
-(+f0.0) if(32) JIP: 80 UIP: 80 { align1 };
+(+f0.0) if(8) JIP: LABEL0 UIP: LABEL1 { align1 1Q };
+(-f0.0) if(8) JIP: LABEL0 UIP: LABEL1 { align1 1Q };
+LABEL0:
+(-f0.0) if(16) JIP: LABEL1 UIP: LABEL1 { align1 1H };
+(+f0.0) if(16) JIP: LABEL1 UIP: LABEL1 { align1 1H };
+(+f0.0) if(32) JIP: LABEL1 UIP: LABEL1 { align1 };
+LABEL1:
diff --git a/src/intel/tools/tests/gen9/if.expected b/src/intel/tools/tests/gen9/if.expected
index b2fc285..d11bebc 100644
--- a/src/intel/tools/tests/gen9/if.expected
+++ b/src/intel/tools/tests/gen9/if.expected
@@ -1,5 +1,5 @@
-22 00 61 00 20 0e 00 20 70 05 00 00 60 05 00 00
-22 00 71 00 20 0e 00 20 60 12 00 00 60 12 00 00
-22 00 91 00 20 0e 00 20 40 00 00 00 40 00 00 00
-22 00 81 00 20 0e 00 20 40 01 00 00 60 00 00 00
-22 00 a1 00 20 0e 00 20 50 00 00 00 50 00 00 00
+22 00 61 00 20 0e 00 20 50 00 00 00 20 00 00 00
+22 00 71 00 20 0e 00 20 40 00 00 00 10 00 00 00
+22 00 91 00 20 0e 00 20 30 00 00 00 30 00 00 00
+22 00 81 00 20 0e 00 20 20 00 00 00 20 00 00 00
+22 00 a1 00 20 0e 00 20 10 00 00 00 10 00 00 00
diff --git a/src/intel/tools/tests/gen9/while.asm b/src/intel/tools/tests/gen9/while.asm
index 00bd8e1..7aaae75 100644
--- a/src/intel/tools/tests/gen9/while.asm
+++ b/src/intel/tools/tests/gen9/while.asm
@@ -1,4 +1,5 @@
-while(8) JIP: -160 { align1 1Q };
-while(16) JIP: -160 { align1 1H };
-(-f0.0) while(8) JIP: -384 { align1 1Q };
-(-f0.0) while(16) JIP: -384 { align1 1H };
+LABEL0:
+while(8) JIP: LABEL0 { align1 1Q };
+while(16) JIP: LABEL0 { align1 1H };
+(-f0.0) while(8) JIP: LABEL0 { align1 1Q };
+(-f0.0) while(16) JIP: LABEL0 { align1 1H };
diff --git a/src/intel/tools/tests/gen9/while.expected b/src/intel/tools/tests/gen9/while.expected
index 5b0fd85..8b6c4da 100644
--- a/src/intel/tools/tests/gen9/while.expected
+++ b/src/intel/tools/tests/gen9/while.expected
@@ -1,4 +1,4 @@
-27 00 60 00 20 0e 00 20 00 00 00 08 60 ff ff ff
-27 00 80 00 20 0e 00 20 00 00 00 08 60 ff ff ff
-27 00 71 00 20 0e 00 20 00 00 00 08 80 fe ff ff
-27 00 91 00 20 0e 00 20 00 00 00 08 80 fe ff ff
+27 00 60 00 20 0e 00 20 00 00 00 08 00 00 00 00
+27 00 80 00 20 0e 00 20 00 00 00 08 f0 ff ff ff
+27 00 71 00 20 0e 00 20 00 00 00 08 e0 ff ff ff
+27 00 91 00 20 0e 00 20 00 00 00 08 d0 ff ff ff
