white space cleanups
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139994 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index 7c59c7e..80b4c60 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -61,8 +61,8 @@
// Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
// SINT_TO_FLOAT and SHR on vectors isn't legal.
SDValue ExpandUINT_TO_FLOAT(SDValue Op);
- // Implement vselect in terms of XOR, AND,OR when blend is not supported
- // by the target.
+ // Implement vselect in terms of XOR, AND, OR when blend is not supported
+ // by the target.
SDValue ExpandVSELECT(SDValue Op);
SDValue ExpandFNEG(SDValue Op);
// Implements vector promotion; this is essentially just bitcasting the
@@ -277,9 +277,8 @@
// AND,OR,XOR, we will have to scalarize the op.
if (!TLI.isOperationLegalOrCustom(ISD::AND, VT) ||
!TLI.isOperationLegalOrCustom(ISD::XOR, VT) ||
- !TLI.isOperationLegalOrCustom(ISD::OR, VT)) {
- return DAG.UnrollVectorOp(Op.getNode());
- }
+ !TLI.isOperationLegalOrCustom(ISD::OR, VT))
+ return DAG.UnrollVectorOp(Op.getNode());
assert(VT.getSizeInBits() == OVT.getSizeInBits() && "Invalid mask size");
// Bitcast the operands to be the same type as the mask.
