commit b5b7c96ce4e120297304e5cef5b4b0af8e9e8691
author Andrew Trick <atrick@apple.com> Fri Sep 23 23:05:19 2011 +0000
committer Andrew Trick <atrick@apple.com> Fri Sep 23 23:05:19 2011 +0000
tree ea811f2451a06295f6010881b376e7000795f66a
parent b0387f9e06aca7f891e2aad22bc0b859d6dfd2f1

LSR minor bug fix in RateRegister.

No test case. Noticed by inspection and I doubt it ever affects the
outcome of the overall heuristic, let alone final codegen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140431 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Transforms/Scalar/LoopStrengthReduce.cpp

diff --git a/lib/Transforms/Scalar/LoopStrengthReduce.cpp b/lib/Transforms/Scalar/LoopStrengthReduce.cpp
index 3938ab6..33858ad 100644
--- a/lib/Transforms/Scalar/LoopStrengthReduce.cpp
+++ b/lib/Transforms/Scalar/LoopStrengthReduce.cpp
@@ -728,7 +728,7 @@
     // Add the step value register, if it needs one.
     // TODO: The non-affine case isn't precisely modeled here.
     if (!AR->isAffine() || !isa<SCEVConstant>(AR->getOperand(1)))
-      if (!Regs.count(AR->getStart()))
+      if (!Regs.count(AR->getOperand(1)))
         RateRegister(AR->getOperand(1), Regs, L, SE, DT);
   }
   ++NumRegs;