commit b07a3d68972039426a87f1cac82e348e3bb1877b
author Akira Hatanaka <ahatanaka@mips.com> Tue Oct 11 20:44:43 2011 +0000
committer Akira Hatanaka <ahatanaka@mips.com> Tue Oct 11 20:44:43 2011 +0000
tree f9613e44f2d95e2824ed76810f4c31d42b3d0749
parent fbab2206cfe5573bdc215fb40dc9df0d562cb02f

Use sltiu instead of sltu when a register operand and immediate are compared.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141708 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Mips/Mips64InstrInfo.td

diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td
index 8c8bc76..495b969 100644
--- a/lib/Target/Mips/Mips64InstrInfo.td
+++ b/lib/Target/Mips/Mips64InstrInfo.td
@@ -242,7 +242,7 @@
 
 // setcc patterns
 def : Pat<(seteq CPU64Regs:$lhs, CPU64Regs:$rhs),
-          (SLTu64 (DXOR CPU64Regs:$lhs, CPU64Regs:$rhs), 1)>;
+          (SLTiu64 (DXOR CPU64Regs:$lhs, CPU64Regs:$rhs), 1)>;
 def : Pat<(setne CPU64Regs:$lhs, CPU64Regs:$rhs),
           (SLTu64 ZERO_64, (DXOR CPU64Regs:$lhs, CPU64Regs:$rhs))>;
 

lib/Target/Mips/MipsInstrInfo.td

diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index 9b07082..2c18930 100644
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -954,7 +954,7 @@
 
 // setcc patterns
 def : Pat<(seteq CPURegs:$lhs, CPURegs:$rhs),
-          (SLTu (XOR CPURegs:$lhs, CPURegs:$rhs), 1)>;
+          (SLTiu (XOR CPURegs:$lhs, CPURegs:$rhs), 1)>;
 def : Pat<(setne CPURegs:$lhs, CPURegs:$rhs),
           (SLTu ZERO, (XOR CPURegs:$lhs, CPURegs:$rhs))>;