commit b0786b33fa9090adee9a30796ead7969f948f4cd
author Jim Grosbach <grosbach@apple.com> Wed Oct 12 18:11:24 2011 +0000
committer Jim Grosbach <grosbach@apple.com> Wed Oct 12 18:11:24 2011 +0000
tree 5ec7120d6b1e3103b04eedfc2e3dd2b868617d1e
parent 9f45754750b03516db23b21021db72b20336ea85

addrmode2 is gone from these, so no need for the reg0 operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141794 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/Disassembler/ARMDisassembler.cpp

diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 5f6fc29b..7576801 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -1232,30 +1232,6 @@
   Inst.addOperand(MCOperand::CreateImm(CRd));
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
-  switch (Inst.getOpcode()) {
-    case ARM::LDC_OPTION:
-    case ARM::LDCL_OPTION:
-    case ARM::LDC2_OPTION:
-    case ARM::LDC2L_OPTION:
-    case ARM::STC_OPTION:
-    case ARM::STCL_OPTION:
-    case ARM::STC2_OPTION:
-    case ARM::STC2L_OPTION:
-    case ARM::LDCL_POST:
-    case ARM::STCL_POST:
-    case ARM::LDC2L_POST:
-    case ARM::STC2L_POST:
-    case ARM::t2LDC_OPTION:
-    case ARM::t2LDCL_OPTION:
-    case ARM::t2STC_OPTION:
-    case ARM::t2STCL_OPTION:
-    case ARM::t2LDCL_POST:
-    case ARM::t2STCL_POST:
-      break;
-    default:
-      Inst.addOperand(MCOperand::CreateReg(0));
-      break;
-  }
 
   unsigned P = fieldFromInstruction32(Insn, 24, 1);
   unsigned W = fieldFromInstruction32(Insn, 21, 1);