commit 9a439affd74e7d4ad77dc7a28a16319d6e08db19
author Akira Hatanaka <ahatanak@gmail.com> Fri Sep 09 21:31:46 2011 +0000
committer Akira Hatanaka <ahatanak@gmail.com> Fri Sep 09 21:31:46 2011 +0000
tree a69b48d2651e6d037fc0dc89d58ca6ae964c7af7
parent 9db817fd0ce0949d0358f5cedfd9ca5a9f1726dd

Mips32 does not reserve even-numbered floating point registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139412 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Mips/MipsRegisterInfo.cpp

diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp
index 94e84d7..c12b356 100644
--- a/lib/Target/Mips/MipsRegisterInfo.cpp
+++ b/lib/Target/Mips/MipsRegisterInfo.cpp
@@ -132,11 +132,6 @@
   Reserved.set(Mips::F31);
   Reserved.set(Mips::D15);
 
-  // SRV4 requires that odd register can't be used.
-  if (!Subtarget.isSingleFloat() && !Subtarget.isMips32())
-    for (unsigned FReg=(Mips::F0)+1; FReg < Mips::F30; FReg+=2)
-      Reserved.set(FReg);
-
   return Reserved;
 }