commit 80eb99492902884651ccc064188074af250ec433
author Akira Hatanaka <ahatanaka@mips.com> Tue Oct 11 23:43:48 2011 +0000
committer Akira Hatanaka <ahatanaka@mips.com> Tue Oct 11 23:43:48 2011 +0000
tree 06c34b251e39c159d4dc5f91fe0a2547b15abae3
parent 2dfd3a978936c39194246676af5c4791e65e5001

Change name of class to ArithOverflowR.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141743 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Mips/MipsInstrInfo.td

diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index 4938cf8..2ee32fa 100644
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -260,7 +260,7 @@
   let isCommutable = isComm;
 }
 
-class ArithLogicOfR<bits<6> op, bits<6> func, string instr_asm,
+class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm,
                     InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
   FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
      !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], itin> {
@@ -616,8 +616,8 @@
 /// Arithmetic Instructions (3-Operand, R-Type)
 def ADDu    : ArithLogicR<0x00, 0x21, "addu", add, IIAlu, CPURegs, 1>;
 def SUBu    : ArithLogicR<0x00, 0x23, "subu", sub, IIAlu, CPURegs>;
-def ADD     : ArithLogicOfR<0x00, 0x20, "add", IIAlu, CPURegs, 1>;
-def SUB     : ArithLogicOfR<0x00, 0x22, "sub", IIAlu, CPURegs>;
+def ADD     : ArithOverflowR<0x00, 0x20, "add", IIAlu, CPURegs, 1>;
+def SUB     : ArithOverflowR<0x00, 0x22, "sub", IIAlu, CPURegs>;
 def SLT     : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>;
 def SLTu    : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>;
 def AND     : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPURegs, 1>;