Thumb2 assembly parsing and encoding for SUB(register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140024 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s
index 7f08d48..da14338 100644
--- a/test/MC/ARM/basic-thumb2-instructions.s
+++ b/test/MC/ARM/basic-thumb2-instructions.s
@@ -2421,7 +2421,19 @@
@------------------------------------------------------------------------------
@ SUB (register)
@------------------------------------------------------------------------------
+ sub r4, r5, r6
+ sub r4, r5, r6, lsl #5
+ sub r4, r5, r6, lsr #5
+ sub.w r4, r5, r6, lsr #5
+ sub r4, r5, r6, asr #5
+ sub r4, r5, r6, ror #5
sub.w r5, r2, r12, rrx
-@ CHECK: sub.w r5, r2, r12, rrx @ encoding: [0xa2,0xeb,0x3c,0x05]
+@ CHECK: sub.w r4, r5, r6 @ encoding: [0xa5,0xeb,0x06,0x04]
+@ CHECK: sub.w r4, r5, r6, lsl #5 @ encoding: [0xa5,0xeb,0x46,0x14]
+@ CHECK: sub.w r4, r5, r6, lsr #5 @ encoding: [0xa5,0xeb,0x56,0x14]
+@ CHECK: sub.w r4, r5, r6, lsr #5 @ encoding: [0xa5,0xeb,0x56,0x14]
+@ CHECK: sub.w r4, r5, r6, asr #5 @ encoding: [0xa5,0xeb,0x66,0x14]
+@ CHECK: sub.w r4, r5, r6, ror #5 @ encoding: [0xa5,0xeb,0x76,0x14]
+@ CHECK: sub.w r5, r2, r12, rrx @ encoding: [0xa2,0xeb,0x3c,0x05]
