| # RUN: llvm-mc -triple armv8 -mattr=+v8.1a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V81a |
| # RUN: not llvm-mc -triple armv8 -mattr=+v8 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V8 |
| |
| [0x54,0x0b,0x12,0xf3] |
| [0x12,0x0b,0x21,0xf3] |
| [0x54,0x0c,0x12,0xf3] |
| [0x12,0x0c,0x21,0xf3] |
| # CHECK-V81a: vqrdmlah.s16 q0, q1, q2 |
| # CHECK-V81a: vqrdmlah.s32 d0, d1, d2 |
| # CHECK-V81a: vqrdmlsh.s16 q0, q1, q2 |
| # CHECK-V81a: vqrdmlsh.s32 d0, d1, d2 |
| # CHECK-V8: warning: invalid instruction encoding |
| # CHECK-V8: [0x54,0x0b,0x12,0xf3] |
| # CHECK-V8: warning: invalid instruction encoding |
| # CHECK-V8: [0x12,0x0b,0x21,0xf3] |
| # CHECK-V8: warning: invalid instruction encoding |
| # CHECK-V8: [0x54,0x0c,0x12,0xf3] |
| # CHECK-V8: warning: invalid instruction encoding |
| # CHECK-V8: [0x12,0x0c,0x21,0xf3] |
| |
| [0x42,0x0e,0x92,0xf3] |
| [0x42,0x0e,0xa1,0xf2] |
| [0x42,0x0f,0x92,0xf3] |
| [0x42,0x0f,0xa1,0xf2] |
| # CHECK-V81a: vqrdmlah.s16 q0, q1, d2[0] |
| # CHECK-V81a: vqrdmlah.s32 d0, d1, d2[0] |
| # CHECK-V81a: vqrdmlsh.s16 q0, q1, d2[0] |
| # CHECK-V81a: vqrdmlsh.s32 d0, d1, d2[0] |
| # CHECK-V8: warning: invalid instruction encoding |
| # CHECK-V8: [0x42,0x0e,0x92,0xf3] |
| # CHECK-V8: warning: invalid instruction encoding |
| # CHECK-V8: [0x42,0x0e,0xa1,0xf2] |
| # CHECK-V8: warning: invalid instruction encoding |
| # CHECK-V8: [0x42,0x0f,0x92,0xf3] |
| # CHECK-V8: warning: invalid instruction encoding |
| # CHECK-V8: [0x42,0x0f,0xa1,0xf2] |
| |
| # The SETPAN(v8.1a) and TST(v8) instructions occupy the same space, but SETPAN |
| # uses the encoding for the invalid NV predicate operand. This test checks that |
| # the disassembler is correctly disambiguating and decoding these instructions. |
| |
| [0x00 0x00 0x10 0xf1] |
| # CHECK: setpan #0 |
| |
| [0x00 0x02 0x10 0xf1] |
| # CHECK: setpan #1 |
| |
| [0x00 0x00 0x10 0xe1] |
| # CHECK: tst r0, r0 |
| |
| [0x00 0x02 0x10 0xe1] |
| # CHECK: tst r0, r0, lsl #4 |
