Merge "[AArch64] Add fallback in FastISel fp16 conversions"
am: e412d8b5df
Change-Id: Ife5ad96b2e94d683dae4e22c9bbf3ee88be46834
diff --git a/lib/Target/AArch64/AArch64FastISel.cpp b/lib/Target/AArch64/AArch64FastISel.cpp
index ce8eb0a..3a09c4b 100644
--- a/lib/Target/AArch64/AArch64FastISel.cpp
+++ b/lib/Target/AArch64/AArch64FastISel.cpp
@@ -2748,7 +2748,7 @@
return false;
EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true);
- if (SrcVT == MVT::f128)
+ if (SrcVT == MVT::f128 || SrcVT == MVT::f16)
return false;
unsigned Opc;
@@ -2775,8 +2775,12 @@
MVT DestVT;
if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
return false;
- assert ((DestVT == MVT::f32 || DestVT == MVT::f64) &&
- "Unexpected value type.");
+ // Let regular ISEL handle FP16
+ if (DestVT == MVT::f16)
+ return false;
+
+ assert((DestVT == MVT::f32 || DestVT == MVT::f64) &&
+ "Unexpected value type.");
unsigned SrcReg = getRegForValue(I->getOperand(0));
if (!SrcReg)
diff --git a/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll b/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll
new file mode 100644
index 0000000..16a02de
--- /dev/null
+++ b/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll
@@ -0,0 +1,131 @@
+; RUN: llc -O0 -verify-machineinstrs -mtriple=arm64-eabi < %s | FileCheck --enable-var-scope %s
+
+; Test fptosi
+define i32 @fptosi_wh(half %a) nounwind ssp {
+entry:
+; CHECK-LABEL: fptosi_wh
+; CHECK: fcvt s1, h0
+; CHECK: fcvtzs [[REG:w[0-9]+]], s1
+; CHECK: mov w0, [[REG]]
+ %conv = fptosi half %a to i32
+ ret i32 %conv
+}
+
+; Test fptoui
+define i32 @fptoui_swh(half %a) nounwind ssp {
+entry:
+; CHECK-LABEL: fptoui_swh
+; CHECK: fcvt s1, h0
+; CHECK: fcvtzu [[REG:w[0-9]+]], s1
+; CHECK: mov w0, [[REG]]
+ %conv = fptoui half %a to i32
+ ret i32 %conv
+}
+
+; Test sitofp
+define half @sitofp_hw_i1(i1 %a) nounwind ssp {
+entry:
+; CHECK-LABEL: sitofp_hw_i1
+; CHECK: sbfx w0, w0, #0, #1
+; CHECK: scvtf s0, w0
+; CHECK: fcvt h0, s0
+ %conv = sitofp i1 %a to half
+ ret half %conv
+}
+
+; Test sitofp
+define half @sitofp_hw_i8(i8 %a) nounwind ssp {
+entry:
+; CHECK-LABEL: sitofp_hw_i8
+; CHECK: sxtb w0, w0
+; CHECK: scvtf s0, w0
+; CHECK: fcvt h0, s0
+ %conv = sitofp i8 %a to half
+ ret half %conv
+}
+
+; Test sitofp
+define half @sitofp_hw_i16(i16 %a) nounwind ssp {
+entry:
+; CHECK-LABEL: sitofp_hw_i16
+; CHECK: sxth w0, w0
+; CHECK: scvtf s0, w0
+; CHECK: fcvt h0, s0
+ %conv = sitofp i16 %a to half
+ ret half %conv
+}
+
+; Test sitofp
+define half @sitofp_hw_i32(i32 %a) nounwind ssp {
+entry:
+; CHECK-LABEL: sitofp_hw_i32
+; CHECK: scvtf s0, w0
+; CHECK: fcvt h0, s0
+ %conv = sitofp i32 %a to half
+ ret half %conv
+}
+
+; Test sitofp
+define half @sitofp_hx(i64 %a) nounwind ssp {
+entry:
+; CHECK-LABEL: sitofp_hx
+; CHECK: scvtf s0, x0
+; CHECK: fcvt h0, s0
+ %conv = sitofp i64 %a to half
+ ret half %conv
+}
+
+; Test uitofp
+define half @uitofp_hw_i1(i1 %a) nounwind ssp {
+entry:
+; CHECK-LABEL: uitofp_hw_i1
+; CHECK: and w0, w0, #0x1
+; CHECK: ucvtf s0, w0
+; CHECK: fcvt h0, s0
+ %conv = uitofp i1 %a to half
+ ret half %conv
+}
+
+; Test uitofp
+define half @uitofp_hw_i8(i8 %a) nounwind ssp {
+entry:
+; CHECK-LABEL: uitofp_hw_i8
+; CHECK: and w0, w0, #0xff
+; CHECK: ucvtf s0, w0
+; CHECK: fcvt h0, s0
+ %conv = uitofp i8 %a to half
+ ret half %conv
+}
+
+; Test uitofp
+define half @uitofp_hw_i16(i16 %a) nounwind ssp {
+entry:
+; CHECK-LABEL: uitofp_hw_i16
+; CHECK: and w0, w0, #0xffff
+; CHECK: ucvtf s0, w0
+; CHECK: fcvt h0, s0
+ %conv = uitofp i16 %a to half
+ ret half %conv
+}
+
+; Test uitofp
+define half @uitofp_hw_i32(i32 %a) nounwind ssp {
+entry:
+; CHECK-LABEL: uitofp_hw_i32
+; CHECK: ucvtf s0, w0
+; CHECK: fcvt h0, s0
+ %conv = uitofp i32 %a to half
+ ret half %conv
+}
+
+; Test uitofp
+define half @uitofp_hx(i64 %a) nounwind ssp {
+entry:
+; CHECK-LABEL: uitofp_hx
+; CHECK: ucvtf s0, x0
+; CHECK: fcvt h0, s0
+ %conv = uitofp i64 %a to half
+ ret half %conv
+}
+
+
