PTX: Add support for sitofp in backend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140593 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PTX/PTXInstrInfo.td b/lib/Target/PTX/PTXInstrInfo.td
index a33bd23..56f7144 100644
--- a/lib/Target/PTX/PTXInstrInfo.td
+++ b/lib/Target/PTX/PTXInstrInfo.td
@@ -826,6 +826,19 @@
: InstPTX<(outs RegF32:$d), (ins RegF64:$a), "cvt.rn.f32.f64\t$d, $a",
[(set RegF32:$d, (fround RegF64:$a))]>;
+def CVT_f32_s16
+ : InstPTX<(outs RegF32:$d), (ins RegI16:$a), "cvt.rn.f32.s16\t$d, $a",
+ [(set RegF32:$d, (sint_to_fp RegI16:$a))]>;
+
+def CVT_f32_s32
+ : InstPTX<(outs RegF32:$d), (ins RegI32:$a), "cvt.rn.f32.s32\t$d, $a",
+ [(set RegF32:$d, (sint_to_fp RegI32:$a))]>;
+
+def CVT_f32_s64
+ : InstPTX<(outs RegF32:$d), (ins RegI64:$a), "cvt.rn.f32.s64\t$d, $a",
+ [(set RegF32:$d, (sint_to_fp RegI64:$a))]>;
+
+
// Conversion to f64
def CVT_f64_pred
@@ -849,6 +862,18 @@
: InstPTX<(outs RegF64:$d), (ins RegF32:$a), "cvt.f64.f32\t$d, $a",
[(set RegF64:$d, (fextend RegF32:$a))]>;
+def CVT_f64_s16
+ : InstPTX<(outs RegF64:$d), (ins RegI16:$a), "cvt.rn.f64.s16\t$d, $a",
+ [(set RegF64:$d, (sint_to_fp RegI16:$a))]>;
+
+def CVT_f64_s32
+ : InstPTX<(outs RegF64:$d), (ins RegI32:$a), "cvt.rn.f64.s32\t$d, $a",
+ [(set RegF64:$d, (sint_to_fp RegI32:$a))]>;
+
+def CVT_f64_s64
+ : InstPTX<(outs RegF64:$d), (ins RegI64:$a), "cvt.rn.f64.s64\t$d, $a",
+ [(set RegF64:$d, (sint_to_fp RegI64:$a))]>;
+
// NOTE: These are temporarily here to help test some Clang-generated code.
// We really need to properly introduce anyext and bitconvert into the back-end.
// ANY_EXTEND
diff --git a/test/CodeGen/PTX/20110926-sitofp.ll b/test/CodeGen/PTX/20110926-sitofp.ll
new file mode 100644
index 0000000..38d35c5
--- /dev/null
+++ b/test/CodeGen/PTX/20110926-sitofp.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=ptx32 | FileCheck %s
+
+@A = common global [1536 x [1536 x float]] zeroinitializer, align 4
+@B = common global [1536 x [1536 x float]] zeroinitializer, align 4
+
+define internal ptx_device void @init_array(i32 %x, i32 %y) {
+ %arrayidx103 = getelementptr [1536 x [1536 x float]]* @A, i32 0, i32 %x, i32 %y
+ %arrayidx224 = getelementptr [1536 x [1536 x float]]* @B, i32 0, i32 %x, i32 %y
+ %mul5 = mul i32 %x, %y
+ %rem = srem i32 %mul5, 1024
+ %add = add nsw i32 %rem, 1
+; CHECK: cvt.rn.f64.s32 %fd{{[0-9]+}}, %r{{[0-9]+}}
+ %conv = sitofp i32 %add to double
+ %div = fmul double %conv, 5.000000e-01
+ %conv7 = fptrunc double %div to float
+ store float %conv7, float* %arrayidx103, align 4
+ %rem14 = srem i32 %mul5, 1024
+ %add15 = add nsw i32 %rem14, 1
+ %conv16 = sitofp i32 %add15 to double
+ %div17 = fmul double %conv16, 5.000000e-01
+ %conv18 = fptrunc double %div17 to float
+ store float %conv18, float* %arrayidx224, align 4
+ ret void
+}
diff --git a/test/CodeGen/PTX/cvt.ll b/test/CodeGen/PTX/cvt.ll
index 943712f..abab40e 100644
--- a/test/CodeGen/PTX/cvt.ll
+++ b/test/CodeGen/PTX/cvt.ll
@@ -206,6 +206,27 @@
ret float %a
}
+define ptx_device float @cvt_f32_s16(i16 %x) {
+; CHECK: cvt.rn.f32.s16 %ret{{[0-9]+}}, %rh{{[0-9]+}}
+; CHECK: ret
+ %a = sitofp i16 %x to float
+ ret float %a
+}
+
+define ptx_device float @cvt_f32_s32(i32 %x) {
+; CHECK: cvt.rn.f32.s32 %ret{{[0-9]+}}, %r{{[0-9]+}}
+; CHECK: ret
+ %a = sitofp i32 %x to float
+ ret float %a
+}
+
+define ptx_device float @cvt_f32_s64(i64 %x) {
+; CHECK: cvt.rn.f32.s64 %ret{{[0-9]+}}, %rd{{[0-9]+}}
+; CHECK: ret
+ %a = sitofp i64 %x to float
+ ret float %a
+}
+
; f64
define ptx_device double @cvt_f64_preds(i1 %x) {
@@ -242,3 +263,24 @@
%a = fpext float %x to double
ret double %a
}
+
+define ptx_device double @cvt_f64_s16(i16 %x) {
+; CHECK: cvt.rn.f64.s16 %ret{{[0-9]+}}, %rh{{[0-9]+}}
+; CHECK: ret
+ %a = sitofp i16 %x to double
+ ret double %a
+}
+
+define ptx_device double @cvt_f64_s32(i32 %x) {
+; CHECK: cvt.rn.f64.s32 %ret{{[0-9]+}}, %r{{[0-9]+}}
+; CHECK: ret
+ %a = sitofp i32 %x to double
+ ret double %a
+}
+
+define ptx_device double @cvt_f64_s64(i64 %x) {
+; CHECK: cvt.rn.f64.s64 %ret{{[0-9]+}}, %rd{{[0-9]+}}
+; CHECK: ret
+ %a = sitofp i64 %x to double
+ ret double %a
+}
