| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright (c) 2018 Amlogic, Inc. All rights reserved. |
| */ |
| |
| #include <dt-bindings/phy/phy.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/clock/g12a-clkc.h> |
| #include <dt-bindings/clock/g12a-aoclkc.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/reset/amlogic,meson-g12a-reset.h> |
| |
| / { |
| compatible = "amlogic,g12a"; |
| |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| cpus { |
| #address-cells = <0x2>; |
| #size-cells = <0x0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x0 0x0>; |
| enable-method = "psci"; |
| next-level-cache = <&l2>; |
| }; |
| |
| cpu1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x0 0x1>; |
| enable-method = "psci"; |
| next-level-cache = <&l2>; |
| }; |
| |
| cpu2: cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x0 0x2>; |
| enable-method = "psci"; |
| next-level-cache = <&l2>; |
| }; |
| |
| cpu3: cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x0 0x3>; |
| enable-method = "psci"; |
| next-level-cache = <&l2>; |
| }; |
| |
| l2: l2-cache0 { |
| compatible = "cache"; |
| }; |
| }; |
| |
| efuse: efuse { |
| compatible = "amlogic,meson-gxbb-efuse"; |
| clocks = <&clkc CLKID_EFUSE>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| read-only; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ |
| secmon_reserved: secmon@5000000 { |
| reg = <0x0 0x05000000 0x0 0x300000>; |
| no-map; |
| }; |
| |
| linux,cma { |
| compatible = "shared-dma-pool"; |
| reusable; |
| size = <0x0 0x10000000>; |
| alignment = <0x0 0x400000>; |
| linux,cma-default; |
| }; |
| }; |
| |
| sm: secure-monitor { |
| compatible = "amlogic,meson-gxbb-sm"; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| apb: bus@ff600000 { |
| compatible = "simple-bus"; |
| reg = <0x0 0xff600000 0x0 0x200000>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; |
| |
| hdmi_tx: hdmi-tx@0 { |
| compatible = "amlogic,meson-g12a-dw-hdmi"; |
| reg = <0x0 0x0 0x0 0x10000>; |
| interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; |
| resets = <&reset RESET_HDMITX_CAPB3>, |
| <&reset RESET_HDMITX_PHY>, |
| <&reset RESET_HDMITX>; |
| reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; |
| clocks = <&clkc CLKID_HDMI>, |
| <&clkc CLKID_HTX_PCLK>, |
| <&clkc CLKID_VPU_INTR>; |
| clock-names = "isfr", "iahb", "venci"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| |
| /* VPU VENC Input */ |
| hdmi_tx_venc_port: port@0 { |
| reg = <0>; |
| |
| hdmi_tx_in: endpoint { |
| remote-endpoint = <&hdmi_tx_out>; |
| }; |
| }; |
| |
| /* TMDS Output */ |
| hdmi_tx_tmds_port: port@1 { |
| reg = <1>; |
| }; |
| }; |
| |
| periphs: bus@34400 { |
| compatible = "simple-bus"; |
| reg = <0x0 0x34400 0x0 0x400>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; |
| |
| periphs_pinctrl: pinctrl@40 { |
| compatible = "amlogic,meson-g12a-periphs-pinctrl"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| gpio: bank@40 { |
| reg = <0x0 0x40 0x0 0x4c>, |
| <0x0 0xe8 0x0 0x18>, |
| <0x0 0x120 0x0 0x18>, |
| <0x0 0x2c0 0x0 0x40>, |
| <0x0 0x340 0x0 0x1c>; |
| reg-names = "gpio", |
| "pull", |
| "pull-enable", |
| "mux", |
| "ds"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&periphs_pinctrl 0 0 86>; |
| }; |
| |
| cec_ao_a_h_pins: cec_ao_a_h { |
| mux { |
| groups = "cec_ao_a_h"; |
| function = "cec_ao_a_h"; |
| bias-disable; |
| }; |
| }; |
| |
| cec_ao_b_h_pins: cec_ao_b_h { |
| mux { |
| groups = "cec_ao_b_h"; |
| function = "cec_ao_b_h"; |
| bias-disable; |
| }; |
| }; |
| |
| emmc_pins: emmc { |
| mux-0 { |
| groups = "emmc_nand_d0", |
| "emmc_nand_d1", |
| "emmc_nand_d2", |
| "emmc_nand_d3", |
| "emmc_nand_d4", |
| "emmc_nand_d5", |
| "emmc_nand_d6", |
| "emmc_nand_d7", |
| "emmc_cmd"; |
| function = "emmc"; |
| bias-pull-up; |
| drive-strength-microamp = <4000>; |
| }; |
| |
| mux-1 { |
| groups = "emmc_clk"; |
| function = "emmc"; |
| bias-disable; |
| drive-strength-microamp = <4000>; |
| }; |
| }; |
| |
| emmc_ds_pins: emmc-ds { |
| mux { |
| groups = "emmc_nand_ds"; |
| function = "emmc"; |
| bias-pull-down; |
| drive-strength-microamp = <4000>; |
| }; |
| }; |
| |
| emmc_clk_gate_pins: emmc_clk_gate { |
| mux { |
| groups = "BOOT_8"; |
| function = "gpio_periphs"; |
| bias-pull-down; |
| drive-strength-microamp = <4000>; |
| }; |
| }; |
| |
| hdmitx_ddc_pins: hdmitx_ddc { |
| mux { |
| groups = "hdmitx_sda", |
| "hdmitx_sck"; |
| function = "hdmitx"; |
| bias-disable; |
| }; |
| }; |
| |
| hdmitx_hpd_pins: hdmitx_hpd { |
| mux { |
| groups = "hdmitx_hpd_in"; |
| function = "hdmitx"; |
| bias-disable; |
| }; |
| }; |
| |
| |
| i2c0_sda_c_pins: i2c0-sda-c { |
| mux { |
| groups = "i2c0_sda_c"; |
| function = "i2c0"; |
| bias-disable; |
| drive-strength-microamp = <3000>; |
| |
| }; |
| }; |
| |
| i2c0_sck_c_pins: i2c0-sck-c { |
| mux { |
| groups = "i2c0_sck_c"; |
| function = "i2c0"; |
| bias-disable; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| i2c0_sda_z0_pins: i2c0-sda-z0 { |
| mux { |
| groups = "i2c0_sda_z0"; |
| function = "i2c0"; |
| bias-disable; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| i2c0_sck_z1_pins: i2c0-sck-z1 { |
| mux { |
| groups = "i2c0_sck_z1"; |
| function = "i2c0"; |
| bias-disable; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| i2c0_sda_z7_pins: i2c0-sda-z7 { |
| mux { |
| groups = "i2c0_sda_z7"; |
| function = "i2c0"; |
| bias-disable; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| i2c0_sda_z8_pins: i2c0-sda-z8 { |
| mux { |
| groups = "i2c0_sda_z8"; |
| function = "i2c0"; |
| bias-disable; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| i2c1_sda_x_pins: i2c1-sda-x { |
| mux { |
| groups = "i2c1_sda_x"; |
| function = "i2c1"; |
| bias-disable; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| i2c1_sck_x_pins: i2c1-sck-x { |
| mux { |
| groups = "i2c1_sck_x"; |
| function = "i2c1"; |
| bias-disable; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| i2c1_sda_h2_pins: i2c1-sda-h2 { |
| mux { |
| groups = "i2c1_sda_h2"; |
| function = "i2c1"; |
| bias-disable; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| i2c1_sck_h3_pins: i2c1-sck-h3 { |
| mux { |
| groups = "i2c1_sck_h3"; |
| function = "i2c1"; |
| bias-disable; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| i2c1_sda_h6_pins: i2c1-sda-h6 { |
| mux { |
| groups = "i2c1_sda_h6"; |
| function = "i2c1"; |
| bias-disable; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| i2c1_sck_h7_pins: i2c1-sck-h7 { |
| mux { |
| groups = "i2c1_sck_h7"; |
| function = "i2c1"; |
| bias-disable; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| i2c2_sda_x_pins: i2c2-sda-x { |
| mux { |
| groups = "i2c2_sda_x"; |
| function = "i2c2"; |
| bias-disable; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| i2c2_sck_x_pins: i2c2-sck-x { |
| mux { |
| groups = "i2c2_sck_x"; |
| function = "i2c2"; |
| bias-disable; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| i2c2_sda_z_pins: i2c2-sda-z { |
| mux { |
| groups = "i2c2_sda_z"; |
| function = "i2c2"; |
| bias-disable; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| i2c2_sck_z_pins: i2c2-sck-z { |
| mux { |
| groups = "i2c2_sck_z"; |
| function = "i2c2"; |
| bias-disable; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| i2c3_sda_h_pins: i2c3-sda-h { |
| mux { |
| groups = "i2c3_sda_h"; |
| function = "i2c3"; |
| bias-disable; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| i2c3_sck_h_pins: i2c3-sck-h { |
| mux { |
| groups = "i2c3_sck_h"; |
| function = "i2c3"; |
| bias-disable; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| i2c3_sda_a_pins: i2c3-sda-a { |
| mux { |
| groups = "i2c3_sda_a"; |
| function = "i2c3"; |
| bias-disable; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| i2c3_sck_a_pins: i2c3-sck-a { |
| mux { |
| groups = "i2c3_sck_a"; |
| function = "i2c3"; |
| bias-disable; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| pwm_a_pins: pwm-a { |
| mux { |
| groups = "pwm_a"; |
| function = "pwm_a"; |
| bias-disable; |
| }; |
| }; |
| |
| pwm_b_x7_pins: pwm-b-x7 { |
| mux { |
| groups = "pwm_b_x7"; |
| function = "pwm_b"; |
| bias-disable; |
| }; |
| }; |
| |
| pwm_b_x19_pins: pwm-b-x19 { |
| mux { |
| groups = "pwm_b_x19"; |
| function = "pwm_b"; |
| bias-disable; |
| }; |
| }; |
| |
| pwm_c_c_pins: pwm-c-c { |
| mux { |
| groups = "pwm_c_c"; |
| function = "pwm_c"; |
| bias-disable; |
| }; |
| }; |
| |
| pwm_c_x5_pins: pwm-c-x5 { |
| mux { |
| groups = "pwm_c_x5"; |
| function = "pwm_c"; |
| bias-disable; |
| }; |
| }; |
| |
| pwm_c_x8_pins: pwm-c-x8 { |
| mux { |
| groups = "pwm_c_x8"; |
| function = "pwm_c"; |
| bias-disable; |
| }; |
| }; |
| |
| pwm_d_x3_pins: pwm-d-x3 { |
| mux { |
| groups = "pwm_d_x3"; |
| function = "pwm_d"; |
| bias-disable; |
| }; |
| }; |
| |
| pwm_d_x6_pins: pwm-d-x6 { |
| mux { |
| groups = "pwm_d_x6"; |
| function = "pwm_d"; |
| bias-disable; |
| }; |
| }; |
| |
| pwm_e_pins: pwm-e { |
| mux { |
| groups = "pwm_e"; |
| function = "pwm_e"; |
| bias-disable; |
| }; |
| }; |
| |
| pwm_f_x_pins: pwm-f-x { |
| mux { |
| groups = "pwm_f_x"; |
| function = "pwm_f"; |
| bias-disable; |
| }; |
| }; |
| |
| pwm_f_h_pins: pwm-f-h { |
| mux { |
| groups = "pwm_f_h"; |
| function = "pwm_f"; |
| bias-disable; |
| }; |
| }; |
| |
| sdcard_c_pins: sdcard_c { |
| mux-0 { |
| groups = "sdcard_d0_c", |
| "sdcard_d1_c", |
| "sdcard_d2_c", |
| "sdcard_d3_c", |
| "sdcard_cmd_c"; |
| function = "sdcard"; |
| bias-pull-up; |
| drive-strength-microamp = <4000>; |
| }; |
| |
| mux-1 { |
| groups = "sdcard_clk_c"; |
| function = "sdcard"; |
| bias-disable; |
| drive-strength-microamp = <4000>; |
| }; |
| }; |
| |
| sdcard_clk_gate_c_pins: sdcard_clk_gate_c { |
| mux { |
| groups = "GPIOC_4"; |
| function = "gpio_periphs"; |
| bias-pull-down; |
| drive-strength-microamp = <4000>; |
| }; |
| }; |
| |
| sdcard_z_pins: sdcard_z { |
| mux-0 { |
| groups = "sdcard_d0_z", |
| "sdcard_d1_z", |
| "sdcard_d2_z", |
| "sdcard_d3_z", |
| "sdcard_cmd_z"; |
| function = "sdcard"; |
| bias-pull-up; |
| drive-strength-microamp = <4000>; |
| }; |
| |
| mux-1 { |
| groups = "sdcard_clk_z"; |
| function = "sdcard"; |
| bias-disable; |
| drive-strength-microamp = <4000>; |
| }; |
| }; |
| |
| sdcard_clk_gate_z_pins: sdcard_clk_gate_z { |
| mux { |
| groups = "GPIOZ_6"; |
| function = "gpio_periphs"; |
| bias-pull-down; |
| drive-strength-microamp = <4000>; |
| }; |
| }; |
| |
| uart_a_pins: uart-a { |
| mux { |
| groups = "uart_a_tx", |
| "uart_a_rx"; |
| function = "uart_a"; |
| bias-disable; |
| }; |
| }; |
| |
| uart_a_cts_rts_pins: uart-a-cts-rts { |
| mux { |
| groups = "uart_a_cts", |
| "uart_a_rts"; |
| function = "uart_a"; |
| bias-disable; |
| }; |
| }; |
| |
| uart_b_pins: uart-b { |
| mux { |
| groups = "uart_b_tx", |
| "uart_b_rx"; |
| function = "uart_b"; |
| bias-disable; |
| }; |
| }; |
| |
| uart_c_pins: uart-c { |
| mux { |
| groups = "uart_c_tx", |
| "uart_c_rx"; |
| function = "uart_c"; |
| bias-disable; |
| }; |
| }; |
| |
| uart_c_cts_rts_pins: uart-c-cts-rts { |
| mux { |
| groups = "uart_c_cts", |
| "uart_c_rts"; |
| function = "uart_c"; |
| bias-disable; |
| }; |
| }; |
| }; |
| }; |
| |
| usb2_phy0: phy@36000 { |
| compatible = "amlogic,g12a-usb2-phy"; |
| reg = <0x0 0x36000 0x0 0x2000>; |
| clocks = <&xtal>; |
| clock-names = "xtal"; |
| resets = <&reset RESET_USB_PHY20>; |
| reset-names = "phy"; |
| #phy-cells = <0>; |
| }; |
| |
| dmc: bus@38000 { |
| compatible = "simple-bus"; |
| reg = <0x0 0x38000 0x0 0x400>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; |
| |
| canvas: video-lut@48 { |
| compatible = "amlogic,canvas"; |
| reg = <0x0 0x48 0x0 0x14>; |
| }; |
| }; |
| |
| usb2_phy1: phy@3a000 { |
| compatible = "amlogic,g12a-usb2-phy"; |
| reg = <0x0 0x3a000 0x0 0x2000>; |
| clocks = <&xtal>; |
| clock-names = "xtal"; |
| resets = <&reset RESET_USB_PHY21>; |
| reset-names = "phy"; |
| #phy-cells = <0>; |
| }; |
| |
| hiu: bus@3c000 { |
| compatible = "simple-bus"; |
| reg = <0x0 0x3c000 0x0 0x1400>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; |
| |
| hhi: system-controller@0 { |
| compatible = "amlogic,meson-gx-hhi-sysctrl", |
| "simple-mfd", "syscon"; |
| reg = <0 0 0 0x400>; |
| |
| clkc: clock-controller { |
| compatible = "amlogic,g12a-clkc"; |
| #clock-cells = <1>; |
| clocks = <&xtal>; |
| clock-names = "xtal"; |
| }; |
| }; |
| }; |
| |
| usb3_pcie_phy: phy@46000 { |
| compatible = "amlogic,g12a-usb3-pcie-phy"; |
| reg = <0x0 0x46000 0x0 0x2000>; |
| clocks = <&clkc CLKID_PCIE_PLL>; |
| clock-names = "ref_clk"; |
| resets = <&reset RESET_PCIE_PHY>; |
| reset-names = "phy"; |
| assigned-clocks = <&clkc CLKID_PCIE_PLL>; |
| assigned-clock-rates = <100000000>; |
| #phy-cells = <1>; |
| }; |
| }; |
| |
| aobus: bus@ff800000 { |
| compatible = "simple-bus"; |
| reg = <0x0 0xff800000 0x0 0x100000>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; |
| |
| rti: sys-ctrl@0 { |
| compatible = "amlogic,meson-gx-ao-sysctrl", |
| "simple-mfd", "syscon"; |
| reg = <0x0 0x0 0x0 0x100>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; |
| |
| clkc_AO: clock-controller { |
| compatible = "amlogic,meson-g12a-aoclkc"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| clocks = <&xtal>, <&clkc CLKID_CLK81>; |
| clock-names = "xtal", "mpeg-clk"; |
| }; |
| |
| pwrc_vpu: power-controller-vpu { |
| compatible = "amlogic,meson-g12a-pwrc-vpu"; |
| #power-domain-cells = <0>; |
| amlogic,hhi-sysctrl = <&hhi>; |
| resets = <&reset RESET_VIU>, |
| <&reset RESET_VENC>, |
| <&reset RESET_VCBUS>, |
| <&reset RESET_BT656>, |
| <&reset RESET_RDMA>, |
| <&reset RESET_VENCI>, |
| <&reset RESET_VENCP>, |
| <&reset RESET_VDAC>, |
| <&reset RESET_VDI6>, |
| <&reset RESET_VENCL>, |
| <&reset RESET_VID_LOCK>; |
| clocks = <&clkc CLKID_VPU>, |
| <&clkc CLKID_VAPB>; |
| clock-names = "vpu", "vapb"; |
| /* |
| * VPU clocking is provided by two identical clock paths |
| * VPU_0 and VPU_1 muxed to a single clock by a glitch |
| * free mux to safely change frequency while running. |
| * Same for VAPB but with a final gate after the glitch free mux. |
| */ |
| assigned-clocks = <&clkc CLKID_VPU_0_SEL>, |
| <&clkc CLKID_VPU_0>, |
| <&clkc CLKID_VPU>, /* Glitch free mux */ |
| <&clkc CLKID_VAPB_0_SEL>, |
| <&clkc CLKID_VAPB_0>, |
| <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ |
| assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, |
| <0>, /* Do Nothing */ |
| <&clkc CLKID_VPU_0>, |
| <&clkc CLKID_FCLK_DIV4>, |
| <0>, /* Do Nothing */ |
| <&clkc CLKID_VAPB_0>; |
| assigned-clock-rates = <0>, /* Do Nothing */ |
| <666666666>, |
| <0>, /* Do Nothing */ |
| <0>, /* Do Nothing */ |
| <250000000>, |
| <0>; /* Do Nothing */ |
| }; |
| |
| ao_pinctrl: pinctrl@14 { |
| compatible = "amlogic,meson-g12a-aobus-pinctrl"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| gpio_ao: bank@14 { |
| reg = <0x0 0x14 0x0 0x8>, |
| <0x0 0x1c 0x0 0x8>, |
| <0x0 0x24 0x0 0x14>; |
| reg-names = "mux", |
| "ds", |
| "gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&ao_pinctrl 0 0 15>; |
| }; |
| |
| i2c_ao_sck_pins: i2c_ao_sck_pins { |
| mux { |
| groups = "i2c_ao_sck"; |
| function = "i2c_ao"; |
| bias-disable; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| i2c_ao_sda_pins: i2c_ao_sda { |
| mux { |
| groups = "i2c_ao_sda"; |
| function = "i2c_ao"; |
| bias-disable; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| i2c_ao_sck_e_pins: i2c_ao_sck_e { |
| mux { |
| groups = "i2c_ao_sck_e"; |
| function = "i2c_ao"; |
| bias-disable; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| i2c_ao_sda_e_pins: i2c_ao_sda_e { |
| mux { |
| groups = "i2c_ao_sda_e"; |
| function = "i2c_ao"; |
| bias-disable; |
| drive-strength-microamp = <3000>; |
| }; |
| }; |
| |
| uart_ao_a_pins: uart-a-ao { |
| mux { |
| groups = "uart_ao_a_tx", |
| "uart_ao_a_rx"; |
| function = "uart_ao_a"; |
| bias-disable; |
| }; |
| }; |
| |
| uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { |
| mux { |
| groups = "uart_ao_a_cts", |
| "uart_ao_a_rts"; |
| function = "uart_ao_a"; |
| bias-disable; |
| }; |
| }; |
| |
| pwm_ao_a_pins: pwm-ao-a { |
| mux { |
| groups = "pwm_ao_a"; |
| function = "pwm_ao_a"; |
| bias-disable; |
| }; |
| }; |
| |
| pwm_ao_b_pins: pwm-ao-b { |
| mux { |
| groups = "pwm_ao_b"; |
| function = "pwm_ao_b"; |
| bias-disable; |
| }; |
| }; |
| |
| pwm_ao_c_4_pins: pwm-ao-c-4 { |
| mux { |
| groups = "pwm_ao_c_4"; |
| function = "pwm_ao_c"; |
| bias-disable; |
| }; |
| }; |
| |
| pwm_ao_c_6_pins: pwm-ao-c-6 { |
| mux { |
| groups = "pwm_ao_c_6"; |
| function = "pwm_ao_c"; |
| bias-disable; |
| }; |
| }; |
| |
| pwm_ao_d_5_pins: pwm-ao-d-5 { |
| mux { |
| groups = "pwm_ao_d_5"; |
| function = "pwm_ao_d"; |
| bias-disable; |
| }; |
| }; |
| |
| pwm_ao_d_10_pins: pwm-ao-d-10 { |
| mux { |
| groups = "pwm_ao_d_10"; |
| function = "pwm_ao_d"; |
| bias-disable; |
| }; |
| }; |
| |
| pwm_ao_d_e_pins: pwm-ao-d-e { |
| mux { |
| groups = "pwm_ao_d_e"; |
| function = "pwm_ao_d"; |
| }; |
| }; |
| |
| remote_input_ao_pins: remote-input-ao { |
| mux { |
| groups = "remote_ao_input"; |
| function = "remote_ao_input"; |
| bias-disable; |
| }; |
| }; |
| }; |
| }; |
| |
| cec_AO: cec@100 { |
| compatible = "amlogic,meson-gx-ao-cec"; |
| reg = <0x0 0x00100 0x0 0x14>; |
| interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; |
| clocks = <&clkc_AO CLKID_AO_CEC>; |
| clock-names = "core"; |
| status = "disabled"; |
| }; |
| |
| sec_AO: ao-secure@140 { |
| compatible = "amlogic,meson-gx-ao-secure", "syscon"; |
| reg = <0x0 0x140 0x0 0x140>; |
| amlogic,has-chip-id; |
| }; |
| |
| cecb_AO: cec@280 { |
| compatible = "amlogic,meson-g12a-ao-cec"; |
| reg = <0x0 0x00280 0x0 0x1c>; |
| interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; |
| clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; |
| clock-names = "oscin"; |
| status = "disabled"; |
| }; |
| |
| pwm_AO_cd: pwm@2000 { |
| compatible = "amlogic,meson-g12a-ao-pwm-cd"; |
| reg = <0x0 0x2000 0x0 0x20>; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| uart_AO: serial@3000 { |
| compatible = "amlogic,meson-gx-uart", |
| "amlogic,meson-ao-uart"; |
| reg = <0x0 0x3000 0x0 0x18>; |
| interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; |
| clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; |
| clock-names = "xtal", "pclk", "baud"; |
| status = "disabled"; |
| }; |
| |
| uart_AO_B: serial@4000 { |
| compatible = "amlogic,meson-gx-uart", |
| "amlogic,meson-ao-uart"; |
| reg = <0x0 0x4000 0x0 0x18>; |
| interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; |
| clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; |
| clock-names = "xtal", "pclk", "baud"; |
| status = "disabled"; |
| }; |
| |
| i2c_AO: i2c@5000 { |
| compatible = "amlogic,meson-axg-i2c"; |
| status = "disabled"; |
| reg = <0x0 0x05000 0x0 0x20>; |
| interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&clkc CLKID_I2C>; |
| }; |
| |
| pwm_AO_ab: pwm@7000 { |
| compatible = "amlogic,meson-g12a-ao-pwm-ab"; |
| reg = <0x0 0x7000 0x0 0x20>; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| ir: ir@8000 { |
| compatible = "amlogic,meson-gxbb-ir"; |
| reg = <0x0 0x8000 0x0 0x20>; |
| interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; |
| status = "disabled"; |
| }; |
| |
| saradc: adc@9000 { |
| compatible = "amlogic,meson-g12a-saradc", |
| "amlogic,meson-saradc"; |
| reg = <0x0 0x9000 0x0 0x48>; |
| #io-channel-cells = <1>; |
| interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; |
| clocks = <&xtal>, |
| <&clkc_AO CLKID_AO_SAR_ADC>, |
| <&clkc_AO CLKID_AO_SAR_ADC_CLK>, |
| <&clkc_AO CLKID_AO_SAR_ADC_SEL>; |
| clock-names = "clkin", "core", "adc_clk", "adc_sel"; |
| status = "disabled"; |
| }; |
| }; |
| |
| vpu: vpu@ff900000 { |
| compatible = "amlogic,meson-g12a-vpu"; |
| reg = <0x0 0xff900000 0x0 0x100000>, |
| <0x0 0xff63c000 0x0 0x1000>; |
| reg-names = "vpu", "hhi"; |
| interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| amlogic,canvas = <&canvas>; |
| power-domains = <&pwrc_vpu>; |
| |
| /* CVBS VDAC output port */ |
| cvbs_vdac_port: port@0 { |
| reg = <0>; |
| }; |
| |
| /* HDMI-TX output port */ |
| hdmi_tx_port: port@1 { |
| reg = <1>; |
| |
| hdmi_tx_out: endpoint { |
| remote-endpoint = <&hdmi_tx_in>; |
| }; |
| }; |
| }; |
| |
| gic: interrupt-controller@ffc01000 { |
| compatible = "arm,gic-400"; |
| reg = <0x0 0xffc01000 0 0x1000>, |
| <0x0 0xffc02000 0 0x2000>, |
| <0x0 0xffc04000 0 0x2000>, |
| <0x0 0xffc06000 0 0x2000>; |
| interrupt-controller; |
| interrupts = <GIC_PPI 9 |
| (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; |
| #interrupt-cells = <3>; |
| #address-cells = <0>; |
| }; |
| |
| cbus: bus@ffd00000 { |
| compatible = "simple-bus"; |
| reg = <0x0 0xffd00000 0x0 0x100000>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; |
| |
| reset: reset-controller@1004 { |
| compatible = "amlogic,meson-g12a-reset", |
| "amlogic,meson-axg-reset"; |
| reg = <0x0 0x1004 0x0 0x9c>; |
| #reset-cells = <1>; |
| }; |
| |
| pwm_ef: pwm@19000 { |
| compatible = "amlogic,meson-g12a-ee-pwm"; |
| reg = <0x0 0x19000 0x0 0x20>; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| pwm_cd: pwm@1a000 { |
| compatible = "amlogic,meson-g12a-ee-pwm"; |
| reg = <0x0 0x1a000 0x0 0x20>; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| pwm_ab: pwm@1b000 { |
| compatible = "amlogic,meson-g12a-ee-pwm"; |
| reg = <0x0 0x1b000 0x0 0x20>; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@1c000 { |
| compatible = "amlogic,meson-axg-i2c"; |
| status = "disabled"; |
| reg = <0x0 0x1c000 0x0 0x20>; |
| interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&clkc CLKID_I2C>; |
| }; |
| |
| i2c2: i2c@1d000 { |
| compatible = "amlogic,meson-axg-i2c"; |
| status = "disabled"; |
| reg = <0x0 0x1d000 0x0 0x20>; |
| interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&clkc CLKID_I2C>; |
| }; |
| |
| i2c1: i2c@1e000 { |
| compatible = "amlogic,meson-axg-i2c"; |
| status = "disabled"; |
| reg = <0x0 0x1e000 0x0 0x20>; |
| interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&clkc CLKID_I2C>; |
| }; |
| |
| i2c0: i2c@1f000 { |
| compatible = "amlogic,meson-axg-i2c"; |
| status = "disabled"; |
| reg = <0x0 0x1f000 0x0 0x20>; |
| interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&clkc CLKID_I2C>; |
| }; |
| |
| clk_msr: clock-measure@18000 { |
| compatible = "amlogic,meson-g12a-clk-measure"; |
| reg = <0x0 0x18000 0x0 0x10>; |
| }; |
| |
| uart_C: serial@22000 { |
| compatible = "amlogic,meson-gx-uart"; |
| reg = <0x0 0x22000 0x0 0x18>; |
| interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; |
| clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; |
| clock-names = "xtal", "pclk", "baud"; |
| status = "disabled"; |
| }; |
| |
| uart_B: serial@23000 { |
| compatible = "amlogic,meson-gx-uart"; |
| reg = <0x0 0x23000 0x0 0x18>; |
| interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; |
| clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; |
| clock-names = "xtal", "pclk", "baud"; |
| status = "disabled"; |
| }; |
| |
| uart_A: serial@24000 { |
| compatible = "amlogic,meson-gx-uart"; |
| reg = <0x0 0x24000 0x0 0x18>; |
| interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; |
| clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; |
| clock-names = "xtal", "pclk", "baud"; |
| status = "disabled"; |
| }; |
| }; |
| |
| sd_emmc_b: sd@ffe05000 { |
| compatible = "amlogic,meson-axg-mmc"; |
| reg = <0x0 0xffe05000 0x0 0x800>; |
| interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; |
| status = "disabled"; |
| clocks = <&clkc CLKID_SD_EMMC_B>, |
| <&clkc CLKID_SD_EMMC_B_CLK0>, |
| <&clkc CLKID_FCLK_DIV2>; |
| clock-names = "core", "clkin0", "clkin1"; |
| resets = <&reset RESET_SD_EMMC_B>; |
| }; |
| |
| sd_emmc_c: mmc@ffe07000 { |
| compatible = "amlogic,meson-axg-mmc"; |
| reg = <0x0 0xffe07000 0x0 0x800>; |
| interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; |
| status = "disabled"; |
| clocks = <&clkc CLKID_SD_EMMC_C>, |
| <&clkc CLKID_SD_EMMC_C_CLK0>, |
| <&clkc CLKID_FCLK_DIV2>; |
| clock-names = "core", "clkin0", "clkin1"; |
| resets = <&reset RESET_SD_EMMC_C>; |
| }; |
| |
| usb: usb@ffe09000 { |
| status = "disabled"; |
| compatible = "amlogic,meson-g12a-usb-ctrl"; |
| reg = <0x0 0xffe09000 0x0 0xa0>; |
| interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| clocks = <&clkc CLKID_USB>; |
| resets = <&reset RESET_USB>; |
| |
| dr_mode = "otg"; |
| |
| phys = <&usb2_phy0>, <&usb2_phy1>, |
| <&usb3_pcie_phy PHY_TYPE_USB3>; |
| phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; |
| |
| dwc2: usb@ff400000 { |
| compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; |
| reg = <0x0 0xff400000 0x0 0x40000>; |
| interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; |
| clock-names = "ddr"; |
| phys = <&usb2_phy1>; |
| dr_mode = "peripheral"; |
| g-rx-fifo-size = <192>; |
| g-np-tx-fifo-size = <128>; |
| g-tx-fifo-size = <128 128 16 16 16>; |
| }; |
| |
| dwc3: usb@ff500000 { |
| compatible = "snps,dwc3"; |
| reg = <0x0 0xff500000 0x0 0x100000>; |
| interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
| dr_mode = "host"; |
| snps,dis_u2_susphy_quirk; |
| snps,quirk-frame-length-adjustment; |
| }; |
| }; |
| |
| mali: gpu@ffe40000 { |
| compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; |
| reg = <0x0 0xffe40000 0x0 0x40000>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "gpu", "mmu", "job"; |
| clocks = <&clkc CLKID_MALI>; |
| resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; |
| |
| /* |
| * Mali clocking is provided by two identical clock paths |
| * MALI_0 and MALI_1 muxed to a single clock by a glitch |
| * free mux to safely change frequency while running. |
| */ |
| assigned-clocks = <&clkc CLKID_MALI_0_SEL>, |
| <&clkc CLKID_MALI_0>, |
| <&clkc CLKID_MALI>; /* Glitch free mux */ |
| assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>, |
| <0>, /* Do Nothing */ |
| <&clkc CLKID_MALI_0>; |
| assigned-clock-rates = <0>, /* Do Nothing */ |
| <800000000>, |
| <0>; /* Do Nothing */ |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 |
| (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 |
| (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 |
| (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 |
| (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| |
| xtal: xtal-clk { |
| compatible = "fixed-clock"; |
| clock-frequency = <24000000>; |
| clock-output-names = "xtal"; |
| #clock-cells = <0>; |
| }; |
| |
| }; |
