| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Device Tree Source for the r8a774b1 SoC |
| * |
| * Copyright (C) 2019 Renesas Electronics Corp. |
| */ |
| |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/clock/r8a774b1-cpg-mssr.h> |
| #include <dt-bindings/power/r8a774b1-sysc.h> |
| |
| / { |
| compatible = "renesas,r8a774b1"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| /* |
| * The external audio clocks are configured as 0 Hz fixed frequency |
| * clocks by default. |
| * Boards that provide audio clocks should override them. |
| */ |
| audio_clk_a: audio_clk_a { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| audio_clk_b: audio_clk_b { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| audio_clk_c: audio_clk_c { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| /* External CAN clock - to be overridden by boards that provide it */ |
| can_clk: can { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| cluster0_opp: opp_table0 { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| opp-500000000 { |
| opp-hz = /bits/ 64 <500000000>; |
| opp-microvolt = <830000>; |
| clock-latency-ns = <300000>; |
| }; |
| opp-1000000000 { |
| opp-hz = /bits/ 64 <1000000000>; |
| opp-microvolt = <830000>; |
| clock-latency-ns = <300000>; |
| }; |
| opp-1500000000 { |
| opp-hz = /bits/ 64 <1500000000>; |
| opp-microvolt = <830000>; |
| clock-latency-ns = <300000>; |
| opp-suspend; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| a57_0: cpu@0 { |
| compatible = "arm,cortex-a57"; |
| reg = <0x0>; |
| device_type = "cpu"; |
| power-domains = <&sysc R8A774B1_PD_CA57_CPU0>; |
| next-level-cache = <&L2_CA57>; |
| enable-method = "psci"; |
| #cooling-cells = <2>; |
| dynamic-power-coefficient = <854>; |
| clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; |
| operating-points-v2 = <&cluster0_opp>; |
| }; |
| |
| a57_1: cpu@1 { |
| compatible = "arm,cortex-a57"; |
| reg = <0x1>; |
| device_type = "cpu"; |
| power-domains = <&sysc R8A774B1_PD_CA57_CPU1>; |
| next-level-cache = <&L2_CA57>; |
| enable-method = "psci"; |
| clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; |
| operating-points-v2 = <&cluster0_opp>; |
| }; |
| |
| L2_CA57: cache-controller-0 { |
| compatible = "cache"; |
| power-domains = <&sysc R8A774B1_PD_CA57_SCU>; |
| cache-unified; |
| cache-level = <2>; |
| }; |
| }; |
| |
| extal_clk: extal { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| /* This value must be overridden by the board */ |
| clock-frequency = <0>; |
| }; |
| |
| extalr_clk: extalr { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| /* This value must be overridden by the board */ |
| clock-frequency = <0>; |
| }; |
| |
| /* External PCIe clock - can be overridden by the board */ |
| pcie_bus_clk: pcie_bus { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| pmu_a57 { |
| compatible = "arm,cortex-a57-pmu"; |
| interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, |
| <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-affinity = <&a57_0>, <&a57_1>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0", "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| /* External SCIF clock - to be overridden by boards that provide it */ |
| scif_clk: scif { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| rwdt: watchdog@e6020000 { |
| reg = <0 0xe6020000 0 0x0c>; |
| /* placeholder */ |
| }; |
| |
| gpio0: gpio@e6050000 { |
| compatible = "renesas,gpio-r8a774b1", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6050000 0 0x50>; |
| interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 0 16>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 912>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 912>; |
| }; |
| |
| gpio1: gpio@e6051000 { |
| compatible = "renesas,gpio-r8a774b1", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6051000 0 0x50>; |
| interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 32 29>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 911>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 911>; |
| }; |
| |
| gpio2: gpio@e6052000 { |
| compatible = "renesas,gpio-r8a774b1", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6052000 0 0x50>; |
| interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 64 15>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 910>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 910>; |
| }; |
| |
| gpio3: gpio@e6053000 { |
| compatible = "renesas,gpio-r8a774b1", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6053000 0 0x50>; |
| interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 96 16>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 909>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 909>; |
| }; |
| |
| gpio4: gpio@e6054000 { |
| compatible = "renesas,gpio-r8a774b1", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6054000 0 0x50>; |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 128 18>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 908>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 908>; |
| }; |
| |
| gpio5: gpio@e6055000 { |
| compatible = "renesas,gpio-r8a774b1", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6055000 0 0x50>; |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 160 26>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 907>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 907>; |
| }; |
| |
| gpio6: gpio@e6055400 { |
| compatible = "renesas,gpio-r8a774b1", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6055400 0 0x50>; |
| interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 192 32>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 906>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 906>; |
| }; |
| |
| gpio7: gpio@e6055800 { |
| compatible = "renesas,gpio-r8a774b1", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6055800 0 0x50>; |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 224 4>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 905>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 905>; |
| }; |
| |
| pfc: pin-controller@e6060000 { |
| compatible = "renesas,pfc-r8a774b1"; |
| reg = <0 0xe6060000 0 0x50c>; |
| }; |
| |
| cmt0: timer@e60f0000 { |
| compatible = "renesas,r8a774b1-cmt0", |
| "renesas,rcar-gen3-cmt0"; |
| reg = <0 0xe60f0000 0 0x1004>; |
| interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 303>; |
| clock-names = "fck"; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 303>; |
| status = "disabled"; |
| }; |
| |
| cmt1: timer@e6130000 { |
| compatible = "renesas,r8a774b1-cmt1", |
| "renesas,rcar-gen3-cmt1"; |
| reg = <0 0xe6130000 0 0x1004>; |
| interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 302>; |
| clock-names = "fck"; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 302>; |
| status = "disabled"; |
| }; |
| |
| cmt2: timer@e6140000 { |
| compatible = "renesas,r8a774b1-cmt1", |
| "renesas,rcar-gen3-cmt1"; |
| reg = <0 0xe6140000 0 0x1004>; |
| interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 301>; |
| clock-names = "fck"; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 301>; |
| status = "disabled"; |
| }; |
| |
| cmt3: timer@e6148000 { |
| compatible = "renesas,r8a774b1-cmt1", |
| "renesas,rcar-gen3-cmt1"; |
| reg = <0 0xe6148000 0 0x1004>; |
| interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 300>; |
| clock-names = "fck"; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 300>; |
| status = "disabled"; |
| }; |
| |
| cpg: clock-controller@e6150000 { |
| compatible = "renesas,r8a774b1-cpg-mssr"; |
| reg = <0 0xe6150000 0 0x1000>; |
| clocks = <&extal_clk>, <&extalr_clk>; |
| clock-names = "extal", "extalr"; |
| #clock-cells = <2>; |
| #power-domain-cells = <0>; |
| #reset-cells = <1>; |
| }; |
| |
| rst: reset-controller@e6160000 { |
| compatible = "renesas,r8a774b1-rst"; |
| reg = <0 0xe6160000 0 0x0200>; |
| }; |
| |
| sysc: system-controller@e6180000 { |
| compatible = "renesas,r8a774b1-sysc"; |
| reg = <0 0xe6180000 0 0x0400>; |
| #power-domain-cells = <1>; |
| }; |
| |
| tsc: thermal@e6198000 { |
| compatible = "renesas,r8a774b1-thermal"; |
| reg = <0 0xe6198000 0 0x100>, |
| <0 0xe61a0000 0 0x100>, |
| <0 0xe61a8000 0 0x100>; |
| interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 522>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 522>; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| tmu0: timer@e61e0000 { |
| compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; |
| reg = <0 0xe61e0000 0 0x30>; |
| interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 125>; |
| clock-names = "fck"; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 125>; |
| status = "disabled"; |
| }; |
| |
| tmu1: timer@e6fc0000 { |
| compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; |
| reg = <0 0xe6fc0000 0 0x30>; |
| interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 124>; |
| clock-names = "fck"; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 124>; |
| status = "disabled"; |
| }; |
| |
| tmu2: timer@e6fd0000 { |
| compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; |
| reg = <0 0xe6fd0000 0 0x30>; |
| interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 123>; |
| clock-names = "fck"; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 123>; |
| status = "disabled"; |
| }; |
| |
| tmu3: timer@e6fe0000 { |
| compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; |
| reg = <0 0xe6fe0000 0 0x30>; |
| interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 122>; |
| clock-names = "fck"; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 122>; |
| status = "disabled"; |
| }; |
| |
| tmu4: timer@ffc00000 { |
| compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; |
| reg = <0 0xffc00000 0 0x30>; |
| interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 121>; |
| clock-names = "fck"; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 121>; |
| status = "disabled"; |
| }; |
| |
| i2c0: i2c@e6500000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "renesas,i2c-r8a774b1", |
| "renesas,rcar-gen3-i2c"; |
| reg = <0 0xe6500000 0 0x40>; |
| interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 931>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 931>; |
| dmas = <&dmac1 0x91>, <&dmac1 0x90>, |
| <&dmac2 0x91>, <&dmac2 0x90>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| i2c-scl-internal-delay-ns = <110>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@e6508000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "renesas,i2c-r8a774b1", |
| "renesas,rcar-gen3-i2c"; |
| reg = <0 0xe6508000 0 0x40>; |
| interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 930>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 930>; |
| dmas = <&dmac1 0x93>, <&dmac1 0x92>, |
| <&dmac2 0x93>, <&dmac2 0x92>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| i2c-scl-internal-delay-ns = <6>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@e6510000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "renesas,i2c-r8a774b1", |
| "renesas,rcar-gen3-i2c"; |
| reg = <0 0xe6510000 0 0x40>; |
| interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 929>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 929>; |
| dmas = <&dmac1 0x95>, <&dmac1 0x94>, |
| <&dmac2 0x95>, <&dmac2 0x94>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| i2c-scl-internal-delay-ns = <6>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@e66d0000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "renesas,i2c-r8a774b1", |
| "renesas,rcar-gen3-i2c"; |
| reg = <0 0xe66d0000 0 0x40>; |
| interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 928>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 928>; |
| dmas = <&dmac0 0x97>, <&dmac0 0x96>; |
| dma-names = "tx", "rx"; |
| i2c-scl-internal-delay-ns = <110>; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@e66d8000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "renesas,i2c-r8a774b1", |
| "renesas,rcar-gen3-i2c"; |
| reg = <0 0xe66d8000 0 0x40>; |
| interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 927>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 927>; |
| dmas = <&dmac0 0x99>, <&dmac0 0x98>; |
| dma-names = "tx", "rx"; |
| i2c-scl-internal-delay-ns = <110>; |
| status = "disabled"; |
| }; |
| |
| i2c5: i2c@e66e0000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "renesas,i2c-r8a774b1", |
| "renesas,rcar-gen3-i2c"; |
| reg = <0 0xe66e0000 0 0x40>; |
| interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 919>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 919>; |
| dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; |
| dma-names = "tx", "rx"; |
| i2c-scl-internal-delay-ns = <110>; |
| status = "disabled"; |
| }; |
| |
| i2c6: i2c@e66e8000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "renesas,i2c-r8a774b1", |
| "renesas,rcar-gen3-i2c"; |
| reg = <0 0xe66e8000 0 0x40>; |
| interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 918>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 918>; |
| dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; |
| dma-names = "tx", "rx"; |
| i2c-scl-internal-delay-ns = <6>; |
| status = "disabled"; |
| }; |
| |
| i2c_dvfs: i2c@e60b0000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "renesas,iic-r8a774b1", |
| "renesas,rcar-gen3-iic", |
| "renesas,rmobile-iic"; |
| reg = <0 0xe60b0000 0 0x425>; |
| interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 926>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 926>; |
| dmas = <&dmac0 0x11>, <&dmac0 0x10>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| hscif0: serial@e6540000 { |
| compatible = "renesas,hscif-r8a774b1", |
| "renesas,rcar-gen3-hscif", |
| "renesas,hscif"; |
| reg = <0 0xe6540000 0 0x60>; |
| interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 520>, |
| <&cpg CPG_CORE R8A774B1_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac1 0x31>, <&dmac1 0x30>, |
| <&dmac2 0x31>, <&dmac2 0x30>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 520>; |
| status = "disabled"; |
| }; |
| |
| hscif1: serial@e6550000 { |
| compatible = "renesas,hscif-r8a774b1", |
| "renesas,rcar-gen3-hscif", |
| "renesas,hscif"; |
| reg = <0 0xe6550000 0 0x60>; |
| interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 519>, |
| <&cpg CPG_CORE R8A774B1_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac1 0x33>, <&dmac1 0x32>, |
| <&dmac2 0x33>, <&dmac2 0x32>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 519>; |
| status = "disabled"; |
| }; |
| |
| hscif2: serial@e6560000 { |
| compatible = "renesas,hscif-r8a774b1", |
| "renesas,rcar-gen3-hscif", |
| "renesas,hscif"; |
| reg = <0 0xe6560000 0 0x60>; |
| interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 518>, |
| <&cpg CPG_CORE R8A774B1_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac1 0x35>, <&dmac1 0x34>, |
| <&dmac2 0x35>, <&dmac2 0x34>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 518>; |
| status = "disabled"; |
| }; |
| |
| hscif3: serial@e66a0000 { |
| compatible = "renesas,hscif-r8a774b1", |
| "renesas,rcar-gen3-hscif", |
| "renesas,hscif"; |
| reg = <0 0xe66a0000 0 0x60>; |
| interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 517>, |
| <&cpg CPG_CORE R8A774B1_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac0 0x37>, <&dmac0 0x36>; |
| dma-names = "tx", "rx"; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 517>; |
| status = "disabled"; |
| }; |
| |
| hscif4: serial@e66b0000 { |
| compatible = "renesas,hscif-r8a774b1", |
| "renesas,rcar-gen3-hscif", |
| "renesas,hscif"; |
| reg = <0 0xe66b0000 0 0x60>; |
| interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 516>, |
| <&cpg CPG_CORE R8A774B1_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac0 0x39>, <&dmac0 0x38>; |
| dma-names = "tx", "rx"; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 516>; |
| status = "disabled"; |
| }; |
| |
| hsusb: usb@e6590000 { |
| reg = <0 0xe6590000 0 0x200>; |
| /* placeholder */ |
| }; |
| |
| usb3_phy0: usb-phy@e65ee000 { |
| reg = <0 0xe65ee000 0 0x90>; |
| #phy-cells = <0>; |
| /* placeholder */ |
| }; |
| |
| dmac0: dma-controller@e6700000 { |
| compatible = "renesas,dmac-r8a774b1", |
| "renesas,rcar-dmac"; |
| reg = <0 0xe6700000 0 0x10000>; |
| interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "error", |
| "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15"; |
| clocks = <&cpg CPG_MOD 219>; |
| clock-names = "fck"; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 219>; |
| #dma-cells = <1>; |
| dma-channels = <16>; |
| iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, |
| <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, |
| <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, |
| <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, |
| <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, |
| <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, |
| <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, |
| <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; |
| }; |
| |
| dmac1: dma-controller@e7300000 { |
| compatible = "renesas,dmac-r8a774b1", |
| "renesas,rcar-dmac"; |
| reg = <0 0xe7300000 0 0x10000>; |
| interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "error", |
| "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15"; |
| clocks = <&cpg CPG_MOD 218>; |
| clock-names = "fck"; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 218>; |
| #dma-cells = <1>; |
| dma-channels = <16>; |
| iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, |
| <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, |
| <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, |
| <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, |
| <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, |
| <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, |
| <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, |
| <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; |
| }; |
| |
| dmac2: dma-controller@e7310000 { |
| compatible = "renesas,dmac-r8a774b1", |
| "renesas,rcar-dmac"; |
| reg = <0 0xe7310000 0 0x10000>; |
| interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "error", |
| "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15"; |
| clocks = <&cpg CPG_MOD 217>; |
| clock-names = "fck"; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 217>; |
| #dma-cells = <1>; |
| dma-channels = <16>; |
| iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, |
| <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, |
| <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, |
| <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, |
| <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, |
| <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, |
| <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, |
| <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; |
| }; |
| |
| ipmmu_ds0: mmu@e6740000 { |
| compatible = "renesas,ipmmu-r8a774b1"; |
| reg = <0 0xe6740000 0 0x1000>; |
| renesas,ipmmu-main = <&ipmmu_mm 0>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| #iommu-cells = <1>; |
| }; |
| |
| ipmmu_ds1: mmu@e7740000 { |
| compatible = "renesas,ipmmu-r8a774b1"; |
| reg = <0 0xe7740000 0 0x1000>; |
| renesas,ipmmu-main = <&ipmmu_mm 1>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| #iommu-cells = <1>; |
| }; |
| |
| ipmmu_hc: mmu@e6570000 { |
| compatible = "renesas,ipmmu-r8a774b1"; |
| reg = <0 0xe6570000 0 0x1000>; |
| renesas,ipmmu-main = <&ipmmu_mm 2>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| #iommu-cells = <1>; |
| }; |
| |
| ipmmu_mm: mmu@e67b0000 { |
| compatible = "renesas,ipmmu-r8a774b1"; |
| reg = <0 0xe67b0000 0 0x1000>; |
| interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| #iommu-cells = <1>; |
| }; |
| |
| ipmmu_mp: mmu@ec670000 { |
| compatible = "renesas,ipmmu-r8a774b1"; |
| reg = <0 0xec670000 0 0x1000>; |
| renesas,ipmmu-main = <&ipmmu_mm 4>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| #iommu-cells = <1>; |
| }; |
| |
| ipmmu_pv0: mmu@fd800000 { |
| compatible = "renesas,ipmmu-r8a774b1"; |
| reg = <0 0xfd800000 0 0x1000>; |
| renesas,ipmmu-main = <&ipmmu_mm 6>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| #iommu-cells = <1>; |
| }; |
| |
| ipmmu_vc0: mmu@fe6b0000 { |
| compatible = "renesas,ipmmu-r8a774b1"; |
| reg = <0 0xfe6b0000 0 0x1000>; |
| renesas,ipmmu-main = <&ipmmu_mm 12>; |
| power-domains = <&sysc R8A774B1_PD_A3VC>; |
| #iommu-cells = <1>; |
| }; |
| |
| ipmmu_vi0: mmu@febd0000 { |
| compatible = "renesas,ipmmu-r8a774b1"; |
| reg = <0 0xfebd0000 0 0x1000>; |
| renesas,ipmmu-main = <&ipmmu_mm 14>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| #iommu-cells = <1>; |
| }; |
| |
| ipmmu_vp0: mmu@fe990000 { |
| compatible = "renesas,ipmmu-r8a774b1"; |
| reg = <0 0xfe990000 0 0x1000>; |
| renesas,ipmmu-main = <&ipmmu_mm 16>; |
| power-domains = <&sysc R8A774B1_PD_A3VP>; |
| #iommu-cells = <1>; |
| }; |
| |
| avb: ethernet@e6800000 { |
| compatible = "renesas,etheravb-r8a774b1", |
| "renesas,etheravb-rcar-gen3"; |
| reg = <0 0xe6800000 0 0x800>; |
| interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15", |
| "ch16", "ch17", "ch18", "ch19", |
| "ch20", "ch21", "ch22", "ch23", |
| "ch24"; |
| clocks = <&cpg CPG_MOD 812>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 812>; |
| phy-mode = "rgmii"; |
| iommus = <&ipmmu_ds0 16>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| can0: can@e6c30000 { |
| reg = <0 0xe6c30000 0 0x1000>; |
| /* placeholder */ |
| }; |
| |
| can1: can@e6c38000 { |
| reg = <0 0xe6c38000 0 0x1000>; |
| /* placeholder */ |
| }; |
| |
| canfd: can@e66c0000 { |
| reg = <0 0xe66c0000 0 0x8000>; |
| /* placeholder */ |
| }; |
| |
| scif0: serial@e6e60000 { |
| compatible = "renesas,scif-r8a774b1", |
| "renesas,rcar-gen3-scif", "renesas,scif"; |
| reg = <0 0xe6e60000 0 0x40>; |
| interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 207>, |
| <&cpg CPG_CORE R8A774B1_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac1 0x51>, <&dmac1 0x50>, |
| <&dmac2 0x51>, <&dmac2 0x50>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 207>; |
| status = "disabled"; |
| }; |
| |
| scif1: serial@e6e68000 { |
| compatible = "renesas,scif-r8a774b1", |
| "renesas,rcar-gen3-scif", "renesas,scif"; |
| reg = <0 0xe6e68000 0 0x40>; |
| interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 206>, |
| <&cpg CPG_CORE R8A774B1_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac1 0x53>, <&dmac1 0x52>, |
| <&dmac2 0x53>, <&dmac2 0x52>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 206>; |
| status = "disabled"; |
| }; |
| |
| scif2: serial@e6e88000 { |
| compatible = "renesas,scif-r8a774b1", |
| "renesas,rcar-gen3-scif", "renesas,scif"; |
| reg = <0 0xe6e88000 0 0x40>; |
| interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 310>, |
| <&cpg CPG_CORE R8A774B1_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac1 0x13>, <&dmac1 0x12>, |
| <&dmac2 0x13>, <&dmac2 0x12>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 310>; |
| status = "disabled"; |
| }; |
| |
| scif3: serial@e6c50000 { |
| compatible = "renesas,scif-r8a774b1", |
| "renesas,rcar-gen3-scif", "renesas,scif"; |
| reg = <0 0xe6c50000 0 0x40>; |
| interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 204>, |
| <&cpg CPG_CORE R8A774B1_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac0 0x57>, <&dmac0 0x56>; |
| dma-names = "tx", "rx"; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 204>; |
| status = "disabled"; |
| }; |
| |
| scif4: serial@e6c40000 { |
| compatible = "renesas,scif-r8a774b1", |
| "renesas,rcar-gen3-scif", "renesas,scif"; |
| reg = <0 0xe6c40000 0 0x40>; |
| interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 203>, |
| <&cpg CPG_CORE R8A774B1_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac0 0x59>, <&dmac0 0x58>; |
| dma-names = "tx", "rx"; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 203>; |
| status = "disabled"; |
| }; |
| |
| scif5: serial@e6f30000 { |
| compatible = "renesas,scif-r8a774b1", |
| "renesas,rcar-gen3-scif", "renesas,scif"; |
| reg = <0 0xe6f30000 0 0x40>; |
| interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 202>, |
| <&cpg CPG_CORE R8A774B1_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, |
| <&dmac2 0x5b>, <&dmac2 0x5a>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 202>; |
| status = "disabled"; |
| }; |
| |
| rcar_sound: sound@ec500000 { |
| reg = <0 0xec500000 0 0x1000>, /* SCU */ |
| <0 0xec5a0000 0 0x100>, /* ADG */ |
| <0 0xec540000 0 0x1000>, /* SSIU */ |
| <0 0xec541000 0 0x280>, /* SSI */ |
| <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ |
| |
| rcar_sound,ssi { |
| ssi0: ssi-0 { }; |
| ssi1: ssi-1 { }; |
| ssi2: ssi-2 { }; |
| ssi3: ssi-3 { }; |
| ssi4: ssi-4 { }; |
| ssi5: ssi-5 { }; |
| ssi6: ssi-6 { }; |
| ssi7: ssi-7 { }; |
| ssi8: ssi-8 { }; |
| ssi9: ssi-9 { }; |
| }; |
| }; |
| |
| xhci0: usb@ee000000 { |
| reg = <0 0xee000000 0 0xc00>; |
| /* placeholder */ |
| }; |
| |
| usb3_peri0: usb@ee020000 { |
| reg = <0 0xee020000 0 0x400>; |
| /* placeholder */ |
| }; |
| |
| ohci0: usb@ee080000 { |
| reg = <0 0xee080000 0 0x100>; |
| /* placeholder */ |
| }; |
| |
| ohci1: usb@ee0a0000 { |
| reg = <0 0xee0a0000 0 0x100>; |
| /* placeholder */ |
| }; |
| |
| ehci0: usb@ee080100 { |
| reg = <0 0xee080100 0 0x100>; |
| /* placeholder */ |
| }; |
| |
| ehci1: usb@ee0a0100 { |
| reg = <0 0xee0a0100 0 0x100>; |
| /* placeholder */ |
| }; |
| |
| usb2_phy0: usb-phy@ee080200 { |
| reg = <0 0xee080200 0 0x700>; |
| /* placeholder */ |
| }; |
| |
| usb2_phy1: usb-phy@ee0a0200 { |
| reg = <0 0xee0a0200 0 0x700>; |
| /* placeholder */ |
| }; |
| |
| sdhi0: sd@ee100000 { |
| compatible = "renesas,sdhi-r8a774b1", |
| "renesas,rcar-gen3-sdhi"; |
| reg = <0 0xee100000 0 0x2000>; |
| interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 314>; |
| max-frequency = <200000000>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 314>; |
| status = "disabled"; |
| }; |
| |
| sdhi1: sd@ee120000 { |
| compatible = "renesas,sdhi-r8a774b1", |
| "renesas,rcar-gen3-sdhi"; |
| reg = <0 0xee120000 0 0x2000>; |
| interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 313>; |
| max-frequency = <200000000>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 313>; |
| status = "disabled"; |
| }; |
| |
| sdhi2: sd@ee140000 { |
| compatible = "renesas,sdhi-r8a774b1", |
| "renesas,rcar-gen3-sdhi"; |
| reg = <0 0xee140000 0 0x2000>; |
| interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 312>; |
| max-frequency = <200000000>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 312>; |
| status = "disabled"; |
| }; |
| |
| sdhi3: sd@ee160000 { |
| compatible = "renesas,sdhi-r8a774b1", |
| "renesas,rcar-gen3-sdhi"; |
| reg = <0 0xee160000 0 0x2000>; |
| interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 311>; |
| max-frequency = <200000000>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 311>; |
| status = "disabled"; |
| }; |
| |
| gic: interrupt-controller@f1010000 { |
| compatible = "arm,gic-400"; |
| #interrupt-cells = <3>; |
| #address-cells = <0>; |
| interrupt-controller; |
| reg = <0x0 0xf1010000 0 0x1000>, |
| <0x0 0xf1020000 0 0x20000>, |
| <0x0 0xf1040000 0 0x20000>, |
| <0x0 0xf1060000 0 0x20000>; |
| interrupts = <GIC_PPI 9 |
| (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
| clocks = <&cpg CPG_MOD 408>; |
| clock-names = "clk"; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 408>; |
| }; |
| |
| pciec0: pcie@fe000000 { |
| reg = <0 0xfe000000 0 0x80000>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| bus-range = <0x00 0xff>; |
| /* placeholder */ |
| }; |
| |
| pciec1: pcie@ee800000 { |
| reg = <0 0xee800000 0 0x80000>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| bus-range = <0x00 0xff>; |
| /* placeholder */ |
| }; |
| |
| fcpf0: fcp@fe950000 { |
| compatible = "renesas,fcpf"; |
| reg = <0 0xfe950000 0 0x200>; |
| clocks = <&cpg CPG_MOD 615>; |
| power-domains = <&sysc R8A774B1_PD_A3VP>; |
| resets = <&cpg 615>; |
| }; |
| |
| vspb: vsp@fe960000 { |
| compatible = "renesas,vsp2"; |
| reg = <0 0xfe960000 0 0x8000>; |
| interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 626>; |
| power-domains = <&sysc R8A774B1_PD_A3VP>; |
| resets = <&cpg 626>; |
| |
| renesas,fcp = <&fcpvb0>; |
| }; |
| |
| vspi0: vsp@fe9a0000 { |
| compatible = "renesas,vsp2"; |
| reg = <0 0xfe9a0000 0 0x8000>; |
| interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 631>; |
| power-domains = <&sysc R8A774B1_PD_A3VP>; |
| resets = <&cpg 631>; |
| |
| renesas,fcp = <&fcpvi0>; |
| }; |
| |
| vspd0: vsp@fea20000 { |
| compatible = "renesas,vsp2"; |
| reg = <0 0xfea20000 0 0x5000>; |
| interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 623>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 623>; |
| |
| renesas,fcp = <&fcpvd0>; |
| }; |
| |
| vspd1: vsp@fea28000 { |
| compatible = "renesas,vsp2"; |
| reg = <0 0xfea28000 0 0x5000>; |
| interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 622>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 622>; |
| |
| renesas,fcp = <&fcpvd1>; |
| }; |
| |
| fcpvb0: fcp@fe96f000 { |
| compatible = "renesas,fcpv"; |
| reg = <0 0xfe96f000 0 0x200>; |
| clocks = <&cpg CPG_MOD 607>; |
| power-domains = <&sysc R8A774B1_PD_A3VP>; |
| resets = <&cpg 607>; |
| }; |
| |
| fcpvd0: fcp@fea27000 { |
| compatible = "renesas,fcpv"; |
| reg = <0 0xfea27000 0 0x200>; |
| clocks = <&cpg CPG_MOD 603>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 603>; |
| }; |
| |
| fcpvd1: fcp@fea2f000 { |
| compatible = "renesas,fcpv"; |
| reg = <0 0xfea2f000 0 0x200>; |
| clocks = <&cpg CPG_MOD 602>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 602>; |
| }; |
| |
| fcpvi0: fcp@fe9af000 { |
| compatible = "renesas,fcpv"; |
| reg = <0 0xfe9af000 0 0x200>; |
| clocks = <&cpg CPG_MOD 611>; |
| power-domains = <&sysc R8A774B1_PD_A3VP>; |
| resets = <&cpg 611>; |
| }; |
| |
| hdmi0: hdmi@fead0000 { |
| compatible = "renesas,r8a774b1-hdmi", |
| "renesas,rcar-gen3-hdmi"; |
| reg = <0 0xfead0000 0 0x10000>; |
| interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 729>, |
| <&cpg CPG_CORE R8A774B1_CLK_HDMI>; |
| clock-names = "iahb", "isfr"; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 729>; |
| status = "disabled"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| dw_hdmi0_in: endpoint { |
| remote-endpoint = <&du_out_hdmi0>; |
| }; |
| }; |
| port@1 { |
| reg = <1>; |
| }; |
| port@2 { |
| /* HDMI sound */ |
| reg = <2>; |
| }; |
| }; |
| }; |
| |
| du: display@feb00000 { |
| compatible = "renesas,du-r8a774b1"; |
| reg = <0 0xfeb00000 0 0x80000>; |
| interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 724>, |
| <&cpg CPG_MOD 723>, |
| <&cpg CPG_MOD 721>; |
| clock-names = "du.0", "du.1", "du.3"; |
| status = "disabled"; |
| |
| vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| du_out_rgb: endpoint { |
| }; |
| }; |
| port@1 { |
| reg = <1>; |
| du_out_hdmi0: endpoint { |
| remote-endpoint = <&dw_hdmi0_in>; |
| }; |
| }; |
| port@2 { |
| reg = <2>; |
| du_out_lvds0: endpoint { |
| remote-endpoint = <&lvds0_in>; |
| }; |
| }; |
| }; |
| }; |
| |
| lvds0: lvds@feb90000 { |
| compatible = "renesas,r8a774b1-lvds"; |
| reg = <0 0xfeb90000 0 0x14>; |
| clocks = <&cpg CPG_MOD 727>; |
| power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
| resets = <&cpg 727>; |
| status = "disabled"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| lvds0_in: endpoint { |
| remote-endpoint = <&du_out_lvds0>; |
| }; |
| }; |
| port@1 { |
| reg = <1>; |
| lvds0_out: endpoint { |
| }; |
| }; |
| }; |
| }; |
| |
| prr: chipid@fff00044 { |
| compatible = "renesas,prr"; |
| reg = <0 0xfff00044 0 4>; |
| }; |
| }; |
| |
| thermal-zones { |
| sensor_thermal1: sensor-thermal1 { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| thermal-sensors = <&tsc 0>; |
| sustainable-power = <2439>; |
| |
| trips { |
| sensor1_crit: sensor1-crit { |
| temperature = <120000>; |
| hysteresis = <1000>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| |
| sensor_thermal2: sensor-thermal2 { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| thermal-sensors = <&tsc 1>; |
| sustainable-power = <2439>; |
| |
| trips { |
| sensor2_crit: sensor2-crit { |
| temperature = <120000>; |
| hysteresis = <1000>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| |
| sensor_thermal3: sensor-thermal3 { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| thermal-sensors = <&tsc 2>; |
| sustainable-power = <2439>; |
| |
| cooling-maps { |
| map0 { |
| trip = <&target>; |
| cooling-device = <&a57_0 0 2>; |
| contribution = <1024>; |
| }; |
| }; |
| trips { |
| target: trip-point1 { |
| temperature = <100000>; |
| hysteresis = <1000>; |
| type = "passive"; |
| }; |
| |
| sensor3_crit: sensor3-crit { |
| temperature = <120000>; |
| hysteresis = <1000>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| |
| /* External USB clocks - can be overridden by the board */ |
| usb3s0_clk: usb3s0 { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| usb_extal_clk: usb_extal { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| }; |
