commit 12bdb4a06d4e0c96cccd8c7d1bd60c2ffc36defa
author Harish Mahendrakar <harish.mahendrakar@ittiam.com> Wed Jan 20 13:24:52 2016 +0530
committer gitbuildkicker <android-build@google.com> Thu Aug 25 16:19:05 2016 -0700
tree 8a98d9fac5a29bc39ea9d6bd0feea5845a622f2d
parent c07d2b24adc12b6f424397a4dc06f939ed196c83

Added memory barrier calls

On some A72 based devices, data shared between cores was found to be
inconsistent which was resulting in an infinite loop.

Adding memory barriers before marking a CTB as parsed/processed,
all the pending memory operations are guaranteed to be completed.

Change-Id: I6e3bb11123a3c12ba7e69c4bfcd38960616f9fb5
(cherry picked from commit 031b91dde5dd07c15d6401601e47e7c937e79051)
(cherry picked from commit 27405a217f75f663a814454068bd81fcf30e9cf6)

common/arm/ihevc_platform_macros.h

diff --git a/common/arm/ihevc_platform_macros.h b/common/arm/ihevc_platform_macros.h
index 6d48cd9..3d79d07 100644
--- a/common/arm/ihevc_platform_macros.h
+++ b/common/arm/ihevc_platform_macros.h
@@ -143,6 +143,7 @@
     }
 }
 
+#define DATA_SYNC()  __sync_synchronize()
 
 /**
 ******************************************************************************

common/mips/ihevc_platform_macros.h

diff --git a/common/mips/ihevc_platform_macros.h b/common/mips/ihevc_platform_macros.h
index b028624..f820cf2 100644
--- a/common/mips/ihevc_platform_macros.h
+++ b/common/mips/ihevc_platform_macros.h
@@ -93,4 +93,6 @@
 #define MEM_ALIGN16 __attribute__ ((aligned (16)))
 #define MEM_ALIGN32 __attribute__ ((aligned (32)))
 
+#define DATA_SYNC()  __sync_synchronize()
+
 #endif /* _IHEVC_PLATFORM_MACROS_H_ */

common/x86/ihevc_platform_macros.h

diff --git a/common/x86/ihevc_platform_macros.h b/common/x86/ihevc_platform_macros.h
index 1d5dc74..66ef542 100644
--- a/common/x86/ihevc_platform_macros.h
+++ b/common/x86/ihevc_platform_macros.h
@@ -96,6 +96,8 @@
     }
 }
 
+#define DATA_SYNC()  __sync_synchronize()
+
 /**
 ******************************************************************************
  *  @brief  returns postion of msb bit for 32bit input

decoder/ihevcd_parse_slice.c

diff --git a/decoder/ihevcd_parse_slice.c b/decoder/ihevcd_parse_slice.c
index 3bb658e..853afee 100644
--- a/decoder/ihevcd_parse_slice.c
+++ b/decoder/ihevcd_parse_slice.c
@@ -3115,6 +3115,7 @@
 
         }
 
+        DATA_SYNC();
 
         /* Update the parse status map */
         {

decoder/ihevcd_process_slice.c

diff --git a/decoder/ihevcd_process_slice.c b/decoder/ihevcd_process_slice.c
index 09b596a..f57cc31 100644
--- a/decoder/ihevcd_process_slice.c
+++ b/decoder/ihevcd_process_slice.c
@@ -189,6 +189,7 @@
                 //NOP(128 * 16);
             }
         }
+        DATA_SYNC();
     }
 }
 
@@ -202,6 +203,7 @@
     /* Update the current CTBs processing status */
     if(ps_proc->i4_check_proc_status)
     {
+        DATA_SYNC();
         for(i = 0; i < nctb; i++)
         {
             sps_t *ps_sps = ps_proc->ps_sps;