ARM Unwind syntax
This patch fixes the bad argument that GAS accepted but the IAS didn't,
ie. {#0x20}, moving it to {0x20} which both accept. It also makes the
ARMv7+ save/restore correct by using VFP instructions rather than old
co-processor ones.
Fixes PR20529.
git-svn-id: https://llvm.org/svn/llvm-project/libcxxabi/trunk@217585 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/src/Unwind/UnwindRegistersRestore.S b/src/Unwind/UnwindRegistersRestore.S
index 5fdb789..8744535 100644
--- a/src/Unwind/UnwindRegistersRestore.S
+++ b/src/Unwind/UnwindRegistersRestore.S
@@ -347,7 +347,11 @@
@ these registers implies they are, actually, available on the target, so
@ it's ok to execute.
@ So, generate the instruction using the corresponding coprocessor mnemonic.
- ldc p11, cr0, [r0], {#0x20} @ fldmiad r0, {d0-d15}
+#if __ARM_ARCH < 7
+ ldc p11, cr0, [r0], {0x20} @ fldmiad r0, {d0-d15}
+#else
+ vldmia r0, {d0-d15}
+#endif
mov pc, lr
@
@@ -358,7 +362,11 @@
@
.p2align 2
DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm19restoreVFPWithFLDMXEPy)
- ldc p11, cr0, [r0], {#0x21} @ fldmiax r0, {d0-d15}
+#if __ARM_ARCH < 7
+ ldc p11, cr0, [r0], {0x21} @ fldmiax r0, {d0-d15}
+#else
+ vldmia r0, {d0-d15} @ fldmiax is deprecated in ARMv7+ and now behaves like vldmia
+#endif
mov pc, lr
@
@@ -369,7 +377,11 @@
@
.p2align 2
DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm12restoreVFPv3EPy)
- ldcl p11, cr0, [r0], {#0x20} @ vldm r0, {d16-d31}
+#if __ARM_ARCH < 7
+ ldcl p11, cr0, [r0], {0x20} @ vldm r0, {d16-d31}
+#else
+ vldmia r0, {d16-d31}
+#endif
mov pc, lr
@
diff --git a/src/Unwind/UnwindRegistersSave.S b/src/Unwind/UnwindRegistersSave.S
index 1e988e2..8f8c359 100644
--- a/src/Unwind/UnwindRegistersSave.S
+++ b/src/Unwind/UnwindRegistersSave.S
@@ -318,7 +318,11 @@
@
.p2align 2
DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm16saveVFPWithFSTMDEPy)
- stc p11, cr0, [r0], {#0x20} @ fstmiad r0, {d0-d15}
+#if __ARM_ARCH < 7
+ stc p11, cr0, [r0], {0x20} @ fstmiad r0, {d0-d15}
+#else
+ vstmia r0, {d0-d15}
+#endif
mov pc, lr
@
@@ -329,7 +333,11 @@
@
.p2align 2
DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm16saveVFPWithFSTMXEPy)
- stc p11, cr0, [r0], {#0x21} @ fstmiax r0, {d0-d15}
+#if __ARM_ARCH < 7
+ stc p11, cr0, [r0], {0x21} @ fstmiax r0, {d0-d15}
+#else
+ vstmia r0, {d0-d15} @ fstmiax is deprecated in ARMv7+ and now behaves like vstmia
+#endif
mov pc, lr
@
@@ -347,7 +355,11 @@
@ these registers implies they are, actually, available on the target, so
@ it's ok to execute.
@ So, generate the instructions using the corresponding coprocessor mnemonic.
- stcl p11, cr0, [r0], {#0x20} @ vldm r0, {d16-d31}
+#if __ARM_ARCH < 7
+ stcl p11, cr0, [r0], {0x20} @ vstm r0, {d16-d31}
+#else
+ vstmia r0, {d16-d31}
+#endif
mov pc, lr
@
