commit 9535009c98f9cab028bc95dbccd8d26737cd65af
author Miao Wang <miaowang@google.com> Tue Jul 12 16:29:52 2016 -0700
committer Miao Wang <miaowang@google.com> Tue Jul 12 16:31:24 2016 -0700
tree a245dae5386d77c83c2d0b5e65a5eff2f759f49e
parent d2f96f0c9363004d5bd8d042dbc70c1519875d33

Add MemoryBarrier for MIPS target

  - Fix the build breakage introduced by upstream change.

Change-Id: Iaa408e3319ab9661feb82373b5f7fb13b09cc96f

internal/multi_thread_gemm.h

diff --git a/internal/multi_thread_gemm.h b/internal/multi_thread_gemm.h
index 9223a42..0aacddb 100644
--- a/internal/multi_thread_gemm.h
+++ b/internal/multi_thread_gemm.h
@@ -73,6 +73,8 @@
   asm volatile("dmb ishst" ::: "memory");
 #elif defined(GEMMLOWP_X86)
   asm volatile("sfence" ::: "memory");
+#elif defined(__mips__)
+  MemoryBarrier();
 #else
 #error "Unsupported architecture for WriteBarrier."
 #endif
@@ -85,6 +87,8 @@
   asm volatile("dmb ishld" ::: "memory");
 #elif defined(GEMMLOWP_X86)
   asm volatile("lfence" ::: "memory");
+#elif defined(__mips__)
+  MemoryBarrier();
 #else
 #error "Unsupported architecture for ReadBarrier."
 #endif