Patch cpuinfo based on XNNPACK cpuinfo.patch
Test: mm
Change-Id: Iaa41be1a7d0245766876aa4751786650c092acea
diff --git a/include/cpuinfo.h b/include/cpuinfo.h
index 903d1cf..2a154c6 100644
--- a/include/cpuinfo.h
+++ b/include/cpuinfo.h
@@ -415,10 +415,10 @@
cpuinfo_uarch_cortex_a75 = 0x00300375,
/** ARM Cortex-A76. */
cpuinfo_uarch_cortex_a76 = 0x00300376,
- /** ARM Cortex-A76AE. */
- cpuinfo_uarch_cortex_a76ae = 0x00300378,
/** ARM Cortex-A77. */
cpuinfo_uarch_cortex_a77 = 0x00300377,
+ /** ARM Cortex-A78. */
+ cpuinfo_uarch_cortex_a78 = 0x00300378,
/** ARM Neoverse N1. */
cpuinfo_uarch_neoverse_n1 = 0x00300400,
@@ -454,6 +454,8 @@
/** Samsung Exynos M5 (Exynos 9830 big cores). */
cpuinfo_uarch_exynos_m5 = 0x00600104,
+ /** Deprecated synonym for Cortex-A76AE. */
+ cpuinfo_uarch_cortex_a76ae = 0x00300376,
/* Old names for Exynos. */
cpuinfo_uarch_mongoose_m1 = 0x00600100,
cpuinfo_uarch_mongoose_m2 = 0x00600101,
@@ -1434,6 +1436,7 @@
bool armv6k;
bool armv7;
bool armv7mp;
+ bool armv8;
bool idiv;
bool vfpv2;
@@ -1521,6 +1524,16 @@
#endif
}
+static inline bool cpuinfo_has_arm_v8(void) {
+ #if CPUINFO_ARCH_ARM64
+ return true;
+ #elif CPUINFO_ARCH_ARM
+ return cpuinfo_isa.armv8;
+ #else
+ return false;
+ #endif
+}
+
static inline bool cpuinfo_has_arm_idiv(void) {
#if CPUINFO_ARCH_ARM64
return true;
@@ -1645,6 +1658,16 @@
#endif
}
+static inline bool cpuinfo_has_arm_neon_v8(void) {
+ #if CPUINFO_ARCH_ARM64
+ return true;
+ #elif CPUINFO_ARCH_ARM
+ return cpuinfo_isa.neon && cpuinfo_isa.armv8;
+ #else
+ return false;
+ #endif
+}
+
static inline bool cpuinfo_has_arm_atomics(void) {
#if CPUINFO_ARCH_ARM64
return cpuinfo_isa.atomics;
diff --git a/src/arm/cache.c b/src/arm/cache.c
index 70f11fd..e9102ed 100644
--- a/src/arm/cache.c
+++ b/src/arm/cache.c
@@ -1106,7 +1106,6 @@
break;
}
case cpuinfo_uarch_cortex_a76:
- case cpuinfo_uarch_cortex_a76ae:
{
/*
* ARM Cortex-A76 Core Technical Reference Manual
diff --git a/src/arm/linux/aarch32-isa.c b/src/arm/linux/aarch32-isa.c
index 92095e1..6e659f5 100644
--- a/src/arm/linux/aarch32-isa.c
+++ b/src/arm/linux/aarch32-isa.c
@@ -43,6 +43,7 @@
isa->armv6k = true;
isa->armv7 = true;
isa->armv7mp = true;
+ isa->armv8 = true;
isa->thumb = true;
isa->thumb2 = true;
isa->idiv = true;
diff --git a/src/arm/mach/init.c b/src/arm/mach/init.c
index bd27259..b6c4a7b 100644
--- a/src/arm/mach/init.c
+++ b/src/arm/mach/init.c
@@ -307,6 +307,7 @@
case CPU_TYPE_ARM:
switch (cpu_subtype) {
case CPU_SUBTYPE_ARM_V8:
+ cpuinfo_isa.armv8 = true;
cpuinfo_isa.aes = true;
cpuinfo_isa.sha1 = true;
cpuinfo_isa.sha2 = true;
diff --git a/src/arm/midr.h b/src/arm/midr.h
index d5a28e3..3d3aaa9 100644
--- a/src/arm/midr.h
+++ b/src/arm/midr.h
@@ -183,6 +183,7 @@
case UINT32_C(0x51008000): /* Kryo 260 / 280 Gold */
case UINT32_C(0x51002050): /* Kryo Gold */
case UINT32_C(0x4800D400): /* Cortex-A76 (HiSilicon) */
+ case UINT32_C(0x4100D410): /* Cortex-A78 */
case UINT32_C(0x4100D0D0): /* Cortex-A77 */
case UINT32_C(0x4100D0E0): /* Cortex-A76AE */
case UINT32_C(0x4100D0B0): /* Cortex-A76 */
diff --git a/src/arm/uarch.c b/src/arm/uarch.c
index e5e3cbc..e8b4c5e 100644
--- a/src/arm/uarch.c
+++ b/src/arm/uarch.c
@@ -91,6 +91,9 @@
case 0xD0E:
*uarch = cpuinfo_uarch_cortex_a76ae;
break;
+ case 0xD41: /* Cortex-A78 */
+ *uarch = cpuinfo_uarch_cortex_a78;
+ break;
#if CPUINFO_ARCH_ARM64 && !defined(__ANDROID__)
case 0xD4A:
*uarch = cpuinfo_uarch_neoverse_e1;
diff --git a/tools/cpu-info.c b/tools/cpu-info.c
index 7963c00..d8f11dd 100644
--- a/tools/cpu-info.c
+++ b/tools/cpu-info.c
@@ -179,10 +179,10 @@
return "Cortex-A75";
case cpuinfo_uarch_cortex_a76:
return "Cortex-A76";
- case cpuinfo_uarch_cortex_a76ae:
- return "Cortex-A76AE";
case cpuinfo_uarch_cortex_a77:
return "Cortex-A77";
+ case cpuinfo_uarch_cortex_a78:
+ return "Cortex-A78";
case cpuinfo_uarch_scorpion:
return "Scorpion";
case cpuinfo_uarch_krait:
diff --git a/tools/isa-info.c b/tools/isa-info.c
index 98ef919..8365846 100644
--- a/tools/isa-info.c
+++ b/tools/isa-info.c
@@ -121,6 +121,7 @@
printf("\tARMv6-K: %s\n", cpuinfo_has_arm_v6k() ? "yes" : "no");
printf("\tARMv7: %s\n", cpuinfo_has_arm_v7() ? "yes" : "no");
printf("\tARMv7 MP: %s\n", cpuinfo_has_arm_v7mp() ? "yes" : "no");
+ printf("\tARMv8: %s\n", cpuinfo_has_arm_v8() ? "yes" : "no");
printf("\tIDIV: %s\n", cpuinfo_has_arm_idiv() ? "yes" : "no");
printf("Floating-Point support:\n");
