Upgrade cpuinfo to 2b14e445016dd46f7de821cdf3093e2823b9ab21 am: f248cf624a
Change-Id: I321488912f94d5de77db7e5402e8fb4cef6ceb26
diff --git a/METADATA b/METADATA
index e85d587..5577a5b 100644
--- a/METADATA
+++ b/METADATA
@@ -1,8 +1,5 @@
name: "cpuinfo"
-description:
- "cpuinfo is a library to detect essential for performance optimization "
- "information about host CPU."
-
+description: "cpuinfo is a library to detect essential for performance optimization information about host CPU."
third_party {
url {
type: HOMEPAGE
@@ -12,7 +9,11 @@
type: GIT
value: "https://github.com/pytorch/cpuinfo"
}
- version: "e39a5790059b6b8274ed91f7b5b5b13641dff267"
- last_upgrade_date { year: 2020 month: 2 day: 3 }
+ version: "2b14e445016dd46f7de821cdf3093e2823b9ab21"
license_type: NOTICE
+ last_upgrade_date {
+ year: 2020
+ month: 4
+ day: 29
+ }
}
diff --git a/include/cpuinfo.h b/include/cpuinfo.h
index e4d2d0c..903d1cf 100644
--- a/include/cpuinfo.h
+++ b/include/cpuinfo.h
@@ -499,6 +499,9 @@
/** Applied Micro X-Gene. */
cpuinfo_uarch_xgene = 0x00B00100,
+ /** Huawei hisilicon Kunpeng Series CPU. */
+ cpuinfo_uarch_taishanv110 = 0x00C00100,
+
/* Hygon Dhyana (a modification of AMD Zen for Chinese market). */
cpuinfo_uarch_dhyana = 0x01000100,
};
diff --git a/src/api.c b/src/api.c
index 0cc5d4e..38cea86 100644
--- a/src/api.c
+++ b/src/api.c
@@ -10,6 +10,9 @@
#include <unistd.h>
#include <sys/syscall.h>
+ #if !defined(__NR_getcpu)
+ #include <asm-generic/unistd.h>
+ #endif
#endif
bool cpuinfo_is_initialized = false;
diff --git a/src/arm/cache.c b/src/arm/cache.c
index c2bc7d2..70f11fd 100644
--- a/src/arm/cache.c
+++ b/src/arm/cache.c
@@ -1448,6 +1448,46 @@
.line_size = 64 /* assumption */
};
break;
+ case cpuinfo_uarch_taishanv110:
+ /*
+ * Kunpeng920 series CPU designed by Huawei hisilicon for server,
+ * L1 and L2 cache is private to each core, L3 is shared with all cores.
+ * +--------------------+-------+-----------+-----------+-----------+----------+------------+
+ * | Processor model | Cores | L1D cache | L1I cache | L2 cache | L3 cache | Reference |
+ * +--------------------+-------+-----------+-----------+-----------+----------+------------+
+ * | Kunpeng920-3226 | 32 | 64K | 64K | 512K | 32M | [1] |
+ * +--------------------+-------+-----------+-----------+-----------+----------+------------+
+ * | Kunpeng920-4826 | 48 | 64K | 64K | 512K | 48M | [2] |
+ * +--------------------+-------+-----------+-----------+-----------+----------+------------+
+ * | Kunpeng920-6426 | 64 | 64K | 64K | 512K | 64M | [3] |
+ * +--------------------+-------+-----------+-----------+-----------+----------+------------+
+ *
+ * [1] https://en.wikichip.org/wiki/hisilicon/kunpeng/920-3226
+ * [2] https://en.wikichip.org/wiki/hisilicon/kunpeng/920-4826
+ * [3] https://en.wikichip.org/wiki/hisilicon/kunpeng/920-6426
+ */
+ *l1i = (struct cpuinfo_cache) {
+ .size = 64 * 1024,
+ .associativity = 4 /* assumption */,
+ .line_size = 128 /* assumption */,
+ };
+ *l1d = (struct cpuinfo_cache) {
+ .size = 64 * 1024,
+ .associativity = 4 /* assumption */,
+ .line_size = 128 /* assumption */,
+ };
+ *l2 = (struct cpuinfo_cache) {
+ .size = 512 * 1024,
+ .associativity = 8 /* assumption */,
+ .line_size = 128 /* assumption */,
+ .flags = CPUINFO_CACHE_INCLUSIVE /* assumption */,
+ };
+ *l3 = (struct cpuinfo_cache) {
+ .size = cluster_cores * 1024 * 1024,
+ .associativity = 16 /* assumption */,
+ .line_size = 128 /* assumption */,
+ };
+ break;
#endif
case cpuinfo_uarch_cortex_a12:
case cpuinfo_uarch_cortex_a32:
diff --git a/src/arm/uarch.c b/src/arm/uarch.c
index 2aef9e7..e5e3cbc 100644
--- a/src/arm/uarch.c
+++ b/src/arm/uarch.c
@@ -155,6 +155,9 @@
case 'H':
*vendor = cpuinfo_vendor_huawei;
switch (midr_get_part(midr)) {
+ case 0xD01: /* Kunpeng920 ARM-base CPU*/
+ *uarch = cpuinfo_uarch_taishanv110;
+ break;
case 0xD40: /* Kirin 980 Big/Medium cores -> Cortex-A76 */
*vendor = cpuinfo_vendor_arm;
*uarch = cpuinfo_uarch_cortex_a76;
