Merge Android Pie into master

Bug: 112104996
Change-Id: Ia7b223444dd16077e99243c71b3772ae48d3e9b4
diff --git a/.appveyor.yml b/.appveyor.yml
new file mode 100644
index 0000000..7626808e
--- /dev/null
+++ b/.appveyor.yml
@@ -0,0 +1,14 @@
+version: 3.0.4-{build}
+
+os:
+  - Visual Studio 2015
+
+before_build:
+  - call "C:\Program Files (x86)\Microsoft Visual Studio 14.0\VC\vcvarsall.bat" amd64
+
+build_script:
+  - mkdir build
+  - cd build
+  - cmake -DCMAKE_BUILD_TYPE=RELEASE -G "NMake Makefiles" ..
+  - nmake
+
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..c0a4926
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,112 @@
+# Object files
+*.o
+*.ko
+
+# Gcc dependency-tracking files
+*.d
+
+# Libraries
+*.lib
+*.a
+
+# Shared objects (inc. Windows DLLs)
+*.dll
+*.so
+*.so.*
+*.dylib
+
+# Executables
+*.exe
+*.out
+*.app
+
+# python
+bindings/python/build/
+bindings/python/capstone.egg-info/
+*.pyc
+
+# java
+bindings/java/capstone.jar
+
+# ocaml
+bindings/ocaml/*.cmi
+bindings/ocaml/*.cmx
+bindings/ocaml/*.cmxa
+bindings/ocaml/*.mli
+bindings/ocaml/test
+bindings/ocaml/test_arm
+bindings/ocaml/test_arm64
+bindings/ocaml/test_mips
+bindings/ocaml/test_x86
+bindings/ocaml/test_detail
+bindings/ocaml/test_ppc
+bindings/ocaml/test_sparc
+bindings/ocaml/test_systemz
+bindings/ocaml/test_xcore
+
+
+# test binaries
+tests/test
+tests/test_detail
+tests/test_iter
+tests/test_arm
+tests/test_arm64
+tests/test_mips
+tests/test_x86
+tests/test_ppc
+tests/test_skipdata
+tests/test_sparc
+tests/test_systemz
+tests/test_xcore
+tests/*.static
+tests/test_basic
+tests/test_customized_mnem
+
+
+# regress binaries
+suite/regress/invalid_read_in_print_operand
+
+
+# vim tmp file
+*.swp
+*~
+
+capstone.pc
+
+# local files
+_*
+
+# freebsd ports: generated file with "make makesum" command
+packages/freebsd/ports/devel/capstone/distinfo
+
+# VisualStudio
+ProjectUpgradeLog.log
+Debug/
+Release/
+ipch/
+*.sdf
+*.opensdf
+*.suo
+*.user
+*.backup
+*.VC.db
+*.VC.opendb
+
+# CMake build directories
+build*/
+
+# Xcode
+xcode/Capstone.xcodeproj/xcuserdata
+xcode/Capstone.xcodeproj/project.xcworkspace/xcuserdata
+
+# suite/
+test_arm_regression
+test_arm_regression.o
+fuzz_harness
+test_iter_benchmark
+
+
+*.s
+.DS_Store
+
+cstool/cstool
diff --git a/.travis.yml b/.travis.yml
new file mode 100644
index 0000000..bd7085a
--- /dev/null
+++ b/.travis.yml
@@ -0,0 +1,16 @@
+language: cpp
+sudo: false
+before_install:
+        - export LD_LIBRARY_PATH=`pwd`/tests/:$LD_LIBRARY_PATH
+script:
+        - ./make.sh
+        - make check
+        - if [[ "$TRAVIS_OS_NAME" == "linux" ]]; then cp libcapstone.so bindings/python/; fi
+        - if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then cp libcapstone.dylib bindings/python/; fi
+        - cd bindings/python && make check
+compiler:
+        - clang
+        - gcc
+os:
+        - linux
+        - osx
diff --git a/Android.bp b/Android.bp
new file mode 100644
index 0000000..f580d14
--- /dev/null
+++ b/Android.bp
@@ -0,0 +1,70 @@
+
+arm_flags = ["-DCAPSTONE_HAS_ARM"]
+arm_srcs = [
+    "arch/ARM/ARMDisassembler.c",
+    "arch/ARM/ARMInstPrinter.c",
+    "arch/ARM/ARMMapping.c",
+    "arch/ARM/ARMModule.c",
+]
+
+arm64_flags = ["-DCAPSTONE_HAS_ARM64"]
+arm64_srcs = [
+    "arch/AArch64/AArch64BaseInfo.c",
+    "arch/AArch64/AArch64Disassembler.c",
+    "arch/AArch64/AArch64InstPrinter.c",
+    "arch/AArch64/AArch64Mapping.c",
+    "arch/AArch64/AArch64Module.c",
+]
+
+x86_flags = ["-DCAPSTONE_HAS_X86"]
+x86_srcs = [
+    "arch/X86/X86DisassemblerDecoder.c",
+    "arch/X86/X86Disassembler.c",
+    "arch/X86/X86IntelInstPrinter.c",
+    "arch/X86/X86ATTInstPrinter.c",
+    "arch/X86/X86Mapping.c",
+    "arch/X86/X86Module.c",
+]
+
+cc_defaults {
+    name: "capstone-defaults",
+    srcs: [
+        "cs.c",
+        "utils.c",
+        "SStream.c",
+        "MCInstrDesc.c",
+        "MCRegisterInfo.c",
+        "MCInst.c",
+    ],
+    cflags: [
+        "-Wall",
+        "-Werror",
+        "-Wno-error=unused-parameter",
+        "-DCAPSTONE_USE_SYS_DYN_MEM",
+    ],
+    export_include_dirs: [".", "include"],
+    clang: true,
+    arch: {
+        arm: {
+            cflags: arm_flags,
+            srcs: arm_srcs,
+        },
+        x86: {
+            cflags: arm_flags + arm64_flags + x86_flags,
+            srcs: arm_srcs + arm64_srcs + x86_srcs,
+        },
+        arm64: {
+            cflags: arm_flags + arm64_flags,
+            srcs: arm_srcs + arm64_srcs
+        }
+    }
+}
+
+// For the host and device platform
+// =====================================================
+
+cc_library {
+    name: "libcapstone",
+    host_supported: true,
+    defaults: ["capstone-defaults"],
+}
diff --git a/CMakeLists.txt b/CMakeLists.txt
new file mode 100644
index 0000000..66127c4
--- /dev/null
+++ b/CMakeLists.txt
@@ -0,0 +1,417 @@
+cmake_minimum_required(VERSION 2.6)
+project(capstone)
+
+set(VERSION_MAJOR 3)
+set(VERSION_MINOR 0)
+set(VERSION_PATCH 5)
+
+# to configure the options specify them in in the command line or change them in the cmake UI.
+# Don't edit the makefile!
+option(CAPSTONE_BUILD_STATIC_RUNTIME "Embed static runtime" OFF)
+option(CAPSTONE_BUILD_STATIC "Build static library" ON)
+option(CAPSTONE_BUILD_SHARED "Build shared library" ON)
+option(CAPSTONE_BUILD_DIET "Build diet library" OFF)
+option(CAPSTONE_BUILD_TESTS "Build tests" ON)
+option(CAPSTONE_USE_DEFAULT_ALLOC "Use default memory allocation functions" ON)
+
+option(CAPSTONE_ARM_SUPPORT "ARM support" ON)
+option(CAPSTONE_ARM64_SUPPORT "ARM64 support" ON)
+option(CAPSTONE_MIPS_SUPPORT "MIPS support" ON)
+option(CAPSTONE_PPC_SUPPORT "PowerPC support" ON)
+option(CAPSTONE_SPARC_SUPPORT "Sparc support" ON)
+option(CAPSTONE_SYSZ_SUPPORT "SystemZ support" ON)
+option(CAPSTONE_XCORE_SUPPORT "XCore support" ON)
+option(CAPSTONE_X86_SUPPORT "x86 support" ON)
+option(CAPSTONE_X86_REDUCE "x86 with reduce instruction sets to minimize library" OFF)
+option(CAPSTONE_X86_ATT_DISABLE "Disable x86 AT&T syntax" OFF)
+option(CAPSTONE_OSXKERNEL_SUPPORT "Support to embed Capstone into OS X Kernel extensions" OFF)
+
+if (CAPSTONE_BUILD_DIET)
+    add_definitions(-DCAPSTONE_DIET)
+endif ()
+
+if (CAPSTONE_USE_DEFAULT_ALLOC)
+    add_definitions(-DCAPSTONE_USE_SYS_DYN_MEM)
+endif ()
+
+if (CAPSTONE_X86_REDUCE)
+    add_definitions(-DCAPSTONE_X86_REDUCE)
+endif ()
+
+if (CAPSTONE_X86_ATT_DISABLE)
+    add_definitions(-DCAPSTONE_X86_ATT_DISABLE)
+endif ()
+
+## sources
+set(SOURCES_ENGINE
+    cs.c
+    MCInst.c
+    MCInstrDesc.c
+    MCRegisterInfo.c
+    SStream.c
+    utils.c
+    )
+
+set(HEADERS_ENGINE
+    include/capstone.h
+    utils.h
+    MCRegisterInfo.h
+    MCInst.h
+    MCInstrDesc.h
+    SStream.h
+    cs_priv.h
+    include/platform.h
+    )
+
+set(HEADERS_COMMON
+    include/arm64.h
+    include/arm.h
+    include/capstone.h
+    include/mips.h
+    include/ppc.h
+    include/x86.h
+    include/sparc.h
+    include/systemz.h
+    include/xcore.h
+    include/platform.h
+    )
+
+
+set(TEST_SOURCES test_basic.c test_detail.c test_skipdata.c test_iter.c)
+
+## architecture support
+if (CAPSTONE_ARM_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_ARM)
+    set(SOURCES_ARM
+        arch/ARM/ARMDisassembler.c
+        arch/ARM/ARMInstPrinter.c
+        arch/ARM/ARMMapping.c
+        arch/ARM/ARMModule.c
+        )
+    set(HEADERS_ARM
+        arch/ARM/ARMAddressingModes.h
+        arch/ARM/ARMBaseInfo.h
+        arch/ARM/ARMDisassembler.h
+        arch/ARM/ARMGenAsmWriter.inc
+        arch/ARM/ARMGenDisassemblerTables.inc
+        arch/ARM/ARMGenInstrInfo.inc
+        arch/ARM/ARMGenRegisterInfo.inc
+        arch/ARM/ARMGenSubtargetInfo.inc
+        arch/ARM/ARMInstPrinter.h
+        arch/ARM/ARMMapping.h
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_arm.c)
+endif ()
+
+if (CAPSTONE_ARM64_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_ARM64)
+    set(SOURCES_ARM64
+        arch/AArch64/AArch64BaseInfo.c
+        arch/AArch64/AArch64Disassembler.c
+        arch/AArch64/AArch64InstPrinter.c
+        arch/AArch64/AArch64Mapping.c
+        arch/AArch64/AArch64Module.c
+        )
+    set(HEADERS_ARM64
+        arch/AArch64/AArch64AddressingModes.h
+        arch/AArch64/AArch64BaseInfo.h
+        arch/AArch64/AArch64Disassembler.h
+        arch/AArch64/AArch64GenAsmWriter.inc
+        arch/AArch64/AArch64GenDisassemblerTables.inc
+        arch/AArch64/AArch64GenInstrInfo.inc
+        arch/AArch64/AArch64GenRegisterInfo.inc
+        arch/AArch64/AArch64GenSubtargetInfo.inc
+        arch/AArch64/AArch64InstPrinter.h
+        arch/AArch64/AArch64Mapping.h
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_arm64.c)
+endif ()
+
+if (CAPSTONE_MIPS_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_MIPS)
+    set(SOURCES_MIPS
+        arch/Mips/MipsDisassembler.c
+        arch/Mips/MipsInstPrinter.c
+        arch/Mips/MipsMapping.c
+        arch/Mips/MipsModule.c
+        )
+    set(HEADERS_MIPS
+        arch/Mips/MipsDisassembler.h
+        arch/Mips/MipsGenAsmWriter.inc
+        arch/Mips/MipsGenDisassemblerTables.inc
+        arch/Mips/MipsGenInstrInfo.inc
+        arch/Mips/MipsGenRegisterInfo.inc
+        arch/Mips/MipsGenSubtargetInfo.inc
+        arch/Mips/MipsInstPrinter.h
+        arch/Mips/MipsMapping.h
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_mips.c)
+endif ()
+
+if (CAPSTONE_PPC_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_POWERPC)
+    set(SOURCES_PPC
+        arch/PowerPC/PPCDisassembler.c
+        arch/PowerPC/PPCInstPrinter.c
+        arch/PowerPC/PPCMapping.c
+        arch/PowerPC/PPCModule.c
+        )
+    set(HEADERS_PPC
+        arch/PowerPC/PPCDisassembler.h
+        arch/PowerPC/PPCGenAsmWriter.inc
+        arch/PowerPC/PPCGenDisassemblerTables.inc
+        arch/PowerPC/PPCGenInstrInfo.inc
+        arch/PowerPC/PPCGenRegisterInfo.inc
+        arch/PowerPC/PPCGenSubtargetInfo.inc
+        arch/PowerPC/PPCInstPrinter.h
+        arch/PowerPC/PPCMapping.h
+        arch/PowerPC/PPCPredicates.h
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_ppc.c)
+endif ()
+
+if (CAPSTONE_X86_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_X86)
+    set(SOURCES_X86
+        arch/X86/X86Disassembler.c
+        arch/X86/X86DisassemblerDecoder.c
+        arch/X86/X86IntelInstPrinter.c
+        arch/X86/X86Mapping.c
+        arch/X86/X86Module.c
+        )
+    set(HEADERS_X86
+        arch/X86/X86BaseInfo.h
+        arch/X86/X86Disassembler.h
+        arch/X86/X86DisassemblerDecoder.h
+        arch/X86/X86DisassemblerDecoderCommon.h
+        arch/X86/X86GenAsmWriter.inc
+        arch/X86/X86GenAsmWriter1.inc
+        arch/X86/X86GenAsmWriter1_reduce.inc
+        arch/X86/X86GenAsmWriter_reduce.inc
+        arch/X86/X86GenDisassemblerTables.inc
+        arch/X86/X86GenDisassemblerTables_reduce.inc
+        arch/X86/X86GenInstrInfo.inc
+        arch/X86/X86GenInstrInfo_reduce.inc
+        arch/X86/X86GenRegisterInfo.inc
+        arch/X86/X86InstPrinter.h
+        arch/X86/X86Mapping.h
+        )
+    if (NOT CAPSTONE_BUILD_DIET)
+        set(SOURCES_X86 ${SOURCES_X86} arch/X86/X86ATTInstPrinter.c)
+    endif ()
+    set(TEST_SOURCES ${TEST_SOURCES} test_x86.c)
+endif ()
+
+if (CAPSTONE_SPARC_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_SPARC)
+    set(SOURCES_SPARC
+        arch/Sparc/SparcDisassembler.c
+        arch/Sparc/SparcInstPrinter.c
+        arch/Sparc/SparcMapping.c
+        arch/Sparc/SparcModule.c
+        )
+    set(HEADERS_SPARC
+        arch/Sparc/Sparc.h
+        arch/Sparc/SparcDisassembler.h
+        arch/Sparc/SparcGenAsmWriter.inc
+        arch/Sparc/SparcGenDisassemblerTables.inc
+        arch/Sparc/SparcGenInstrInfo.inc
+        arch/Sparc/SparcGenRegisterInfo.inc
+        arch/Sparc/SparcGenSubtargetInfo.inc
+        arch/Sparc/SparcInstPrinter.h
+        arch/Sparc/SparcMapping.h
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_sparc.c)
+endif ()
+
+if (CAPSTONE_SYSZ_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_SYSZ)
+    set(SOURCES_SYSZ
+        arch/SystemZ/SystemZDisassembler.c
+        arch/SystemZ/SystemZInstPrinter.c
+        arch/SystemZ/SystemZMapping.c
+        arch/SystemZ/SystemZModule.c
+        arch/SystemZ/SystemZMCTargetDesc.c
+        )
+    set(HEADERS_SYSZ
+        arch/SystemZ/SystemZDisassembler.h
+        arch/SystemZ/SystemZGenAsmWriter.inc
+        arch/SystemZ/SystemZGenDisassemblerTables.inc
+        arch/SystemZ/SystemZGenInstrInfo.inc
+        arch/SystemZ/SystemZGenRegisterInfo.inc
+        arch/SystemZ/SystemZGenSubtargetInfo.inc
+        arch/SystemZ/SystemZInstPrinter.h
+        arch/SystemZ/SystemZMCTargetDesc.h
+        arch/SystemZ/SystemZMapping.h
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_systemz.c)
+endif ()
+
+if (CAPSTONE_XCORE_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_XCORE)
+    set(SOURCES_XCORE
+        arch/XCore/XCoreDisassembler.c
+        arch/XCore/XCoreInstPrinter.c
+        arch/XCore/XCoreMapping.c
+        arch/XCore/XCoreModule.c
+        )
+    set(HEADERS_XCORE
+        arch/XCore/XCoreDisassembler.h
+        arch/XCore/XCoreGenAsmWriter.inc
+        arch/XCore/XCoreGenDisassemblerTables.inc
+        arch/XCore/XCoreGenInstrInfo.inc
+        arch/XCore/XCoreGenRegisterInfo.inc
+        arch/XCore/XCoreInstPrinter.h
+        arch/XCore/XCoreMapping.h
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_xcore.c)
+endif ()
+
+if (CAPSTONE_OSXKERNEL_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_OSXKERNEL)
+endif ()
+
+set(ALL_SOURCES
+    ${SOURCES_ENGINE}
+    ${SOURCES_ARM}
+    ${SOURCES_ARM64}
+    ${SOURCES_MIPS}
+    ${SOURCES_PPC}
+    ${SOURCES_X86}
+    ${SOURCES_SPARC}
+    ${SOURCES_SYSZ}
+    ${SOURCES_XCORE}
+    )
+
+set(ALL_HEADERS
+    ${HEADERS_COMMON}
+    ${HEADERS_ENGINE}
+    ${HEADERS_ARM}
+    ${HEADERS_ARM64}
+    ${HEADERS_MIPS}
+    ${HEADERS_PPC}
+    ${HEADERS_X86}
+    ${HEADERS_SPARC}
+    ${HEADERS_SYSZ}
+    ${HEADERS_XCORE}
+    )
+
+include_directories("${PROJECT_SOURCE_DIR}/include")
+
+## properties
+# version info
+set_property(GLOBAL PROPERTY VERSION ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH})
+
+## targets
+if (CAPSTONE_BUILD_STATIC)
+    add_library(capstone-static STATIC ${ALL_SOURCES} ${ALL_HEADERS})
+    set_property(TARGET capstone-static PROPERTY OUTPUT_NAME capstone)
+    set(default-target capstone-static)
+endif ()
+
+# Force static runtime libraries
+if (CAPSTONE_BUILD_STATIC_RUNTIME)
+    FOREACH(flag
+        CMAKE_C_FLAGS_RELEASE CMAKE_C_FLAGS_RELWITHDEBINFO
+        CMAKE_C_FLAGS_DEBUG CMAKE_C_FLAGS_DEBUG_INIT
+        CMAKE_CXX_FLAGS_RELEASE  CMAKE_CXX_FLAGS_RELWITHDEBINFO
+        CMAKE_CXX_FLAGS_DEBUG  CMAKE_CXX_FLAGS_DEBUG_INIT)
+        if (MSVC)
+            STRING(REPLACE "/MD"  "/MT" "${flag}" "${${flag}}")
+            SET("${flag}" "${${flag}} /EHsc")
+        endif (MSVC)
+    ENDFOREACH()
+endif ()
+
+if (CAPSTONE_BUILD_SHARED)
+    add_library(capstone-shared SHARED ${ALL_SOURCES} ${ALL_HEADERS})
+    set_property(TARGET capstone-shared PROPERTY OUTPUT_NAME capstone)
+    set_property(TARGET capstone-shared PROPERTY COMPILE_FLAGS -DCAPSTONE_SHARED)
+
+    if (MSVC)
+        set_target_properties(capstone-shared PROPERTIES IMPORT_SUFFIX _dll.lib)
+    else()
+        set_target_properties(capstone-shared PROPERTIES
+	    VERSION ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH}
+	    SOVERSION ${VERSION_MAJOR})
+    endif ()
+
+    if(NOT DEFINED default-target)      # honor `capstone-static` for tests first.
+        set(default-target capstone-shared)
+        add_definitions(-DCAPSTONE_SHARED)
+    endif ()
+endif ()
+
+if (CAPSTONE_BUILD_TESTS)
+    foreach (TSRC ${TEST_SOURCES})
+        STRING(REGEX REPLACE ".c$" "" TBIN ${TSRC})
+        add_executable(${TBIN} "tests/${TSRC}")
+        target_link_libraries(${TBIN} ${default-target})
+    endforeach ()
+    if (CAPSTONE_ARM_SUPPORT)
+        set(ARM_REGRESS_TEST test_arm_regression.c)
+        STRING(REGEX REPLACE ".c$" "" ARM_REGRESS_BIN ${ARM_REGRESS_TEST})
+        add_executable(${ARM_REGRESS_BIN} "suite/arm/${ARM_REGRESS_TEST}")
+        target_link_libraries(${ARM_REGRESS_BIN} ${default-target})
+    endif()
+endif ()
+
+source_group("Source\\Engine" FILES ${SOURCES_ENGINE})
+source_group("Source\\ARM" FILES ${SOURCES_ARM})
+source_group("Source\\ARM64" FILES ${SOURCES_ARM64})
+source_group("Source\\Mips" FILES ${SOURCES_MIPS})
+source_group("Source\\PowerPC" FILES ${SOURCES_PPC})
+source_group("Source\\Sparc" FILES ${SOURCES_SPARC})
+source_group("Source\\SystemZ" FILES ${SOURCES_SYSZ})
+source_group("Source\\X86" FILES ${SOURCES_X86})
+source_group("Source\\XCore" FILES ${SOURCES_XCORE})
+
+source_group("Include\\Common" FILES ${HEADERS_COMMON})
+source_group("Include\\Engine" FILES ${HEADERS_ENGINE})
+source_group("Include\\ARM" FILES ${HEADERS_ARM})
+source_group("Include\\ARM64" FILES ${HEADERS_ARM64})
+source_group("Include\\Mips" FILES ${HEADERS_MIPS})
+source_group("Include\\PowerPC" FILES ${HEADERS_PPC})
+source_group("Include\\Sparc" FILES ${HEADERS_SPARC})
+source_group("Include\\SystemZ" FILES ${HEADERS_SYSZ})
+source_group("Include\\X86" FILES ${HEADERS_X86})
+source_group("Include\\XCore" FILES ${HEADERS_XCORE})
+
+### test library 64bit routine:
+get_property(LIB64 GLOBAL PROPERTY FIND_LIBRARY_USE_LIB64_PATHS)
+
+if (NOT APPLE AND "${LIB64}" STREQUAL "TRUE")
+    set(LIBSUFFIX 64)
+else()
+    set(LIBSUFFIX "")
+endif()
+
+set(INSTALL_LIB_DIR     lib${LIBSUFFIX} CACHE PATH "Installation directory for libraries")
+mark_as_advanced(INSTALL_LIB_DIR)
+
+## installation
+install(FILES ${HEADERS_COMMON} DESTINATION include/capstone)
+configure_file(capstone.pc.in capstone.pc)
+
+if (CAPSTONE_BUILD_STATIC)
+    install(TARGETS capstone-static
+            RUNTIME DESTINATION bin
+            LIBRARY DESTINATION ${INSTALL_LIB_DIR}
+            ARCHIVE DESTINATION ${INSTALL_LIB_DIR})
+endif ()
+
+if (CAPSTONE_BUILD_SHARED)
+    install(TARGETS capstone-shared
+            RUNTIME DESTINATION bin
+            LIBRARY DESTINATION ${INSTALL_LIB_DIR}
+            ARCHIVE DESTINATION ${INSTALL_LIB_DIR})
+endif ()
+
+if (CAPSTONE_BUILD_SHARED)
+FILE(GLOB CSTOOL_SRC cstool/*.c)
+add_executable(cstool ${CSTOOL_SRC})
+target_link_libraries(cstool ${default-target})
+
+install(TARGETS cstool DESTINATION bin)
+install(FILES ${CMAKE_BINARY_DIR}/capstone.pc DESTINATION lib/pkgconfig)
+endif ()
diff --git a/COMPILE.TXT b/COMPILE.TXT
new file mode 100644
index 0000000..6c7f948
--- /dev/null
+++ b/COMPILE.TXT
@@ -0,0 +1,193 @@
+This documentation explains how to compile, install & run Capstone on MacOSX,
+Linux, *BSD & Solaris. We also show steps to cross-compile for Microsoft Windows.
+
+To natively compile for Windows using Microsoft Visual Studio, see COMPILE_MSVC.TXT.
+
+To compile using CMake, see COMPILE_CMAKE.TXT.
+
+To compile using XCode on MacOSX, see xcode/README.md.
+
+                        *-*-*-*-*-*
+
+Capstone requires no prerequisite packages, so it is easy to compile & install.
+
+
+
+(0) Tailor Capstone to your need.
+
+  Out of 8 archtitectures supported by Capstone (Arm, Arm64, Mips, PPC, Sparc,
+  SystemZ, XCore & X86), if you just need several selected archs, choose which
+  ones you want to compile in by editing "config.mk" before going to next steps.
+
+  By default, all 8 architectures are compiled.
+
+  The other way of customize Capstone without having to edit config.mk is to
+  pass the desired options on the commandline to ./make.sh. Currently,
+  Capstone supports 5 options, as followings.
+
+  - CAPSTONE_ARCHS: specify list of architectures to compiled in.
+  - CAPSTONE_USE_SYS_DYN_MEM: change this if you have your own dynamic memory management.
+  - CAPSTONE_DIET: use this to make the output binaries more compact.
+  - CAPSTONE_X86_REDUCE: another option to make X86 binary smaller.
+  - CAPSTONE_X86_ATT_DISABLE: disables AT&T syntax on x86.
+  - CAPSTONE_STATIC: build static library.
+  - CAPSTONE_SHARED: build dynamic (shared) library.
+
+  By default, Capstone uses system dynamic memory management, both DIET and X86_REDUCE
+  modes are disable, and builds all the static & shared libraries.
+
+  To avoid editing config.mk for these customization, we can pass their values to
+  make.sh, as followings.
+
+  $ CAPSTONE_ARCHS="arm aarch64 x86" CAPSTONE_USE_SYS_DYN_MEM=no CAPSTONE_DIET=yes CAPSTONE_X86_REDUCE=yes ./make.sh
+
+  NOTE: on commandline, put these values in front of ./make.sh, not after it.
+
+  For each option, refer to docs/README for more details.
+
+
+
+(1) Compile from source
+
+  On *nix (such as MacOSX, Linux, *BSD, Solaris):
+
+  - To compile for current platform, run:
+
+		$ ./make.sh
+
+  - On 64-bit OS, run the command below to cross-compile Capstone for 32-bit binary:
+
+		$ ./make.sh nix32
+
+
+
+(2) Install Capstone on *nix
+
+  To install Capstone, run:
+
+	$ sudo ./make.sh install
+
+	For FreeBSD/OpenBSD, where sudo is unavailable, run:
+
+		$ su; ./make.sh install
+
+  Users are then required to enter root password to copy Capstone into machine
+  system directories.
+
+  Afterwards, run ./tests/test* to see the tests disassembling sample code.
+
+
+  NOTE: The core framework installed by "./make.sh install" consist of
+  following files:
+
+	/usr/include/capstone/capstone.h
+	/usr/include/capstone/x86.h
+	/usr/include/capstone/arm.h
+	/usr/include/capstone/arm64.h
+	/usr/include/capstone/mips.h
+	/usr/include/capstone/ppc.h
+	/usr/include/capstone/sparc.h
+	/usr/include/capstone/systemz.h
+	/usr/include/capstone/xcore.h
+	/usr/include/capstone/platform.h
+	/usr/lib/libcapstone.so (for Linux/*nix), or /usr/lib/libcapstone.dylib (OSX)
+	/usr/lib/libcapstone.a
+
+
+
+(3) Cross-compile for Windows from *nix
+
+  To cross-compile for Windows, Linux & gcc-mingw-w64-i686 (and also gcc-mingw-w64-x86-64
+  for 64-bit binaries) are required.
+
+	- To cross-compile Windows 32-bit binary, simply run:
+
+		$ ./make.sh cross-win32
+
+	- To cross-compile Windows 64-bit binary, run:
+
+		$ ./make.sh cross-win64
+
+  Resulted files libcapstone.dll, libcapstone.dll.a & tests/test*.exe can then
+  be used on Windows machine.
+
+
+
+(4) Cross-compile for iOS from Mac OSX.
+
+  To cross-compile for iOS (iPhone/iPad/iPod), Mac OSX with XCode installed is required. 
+
+	- To cross-compile for ArmV7 (iPod 4, iPad 1/2/3, iPhone4, iPhone4S), run:
+		$ ./make.sh ios_armv7
+
+	- To cross-compile for ArmV7s (iPad 4, iPhone 5C, iPad mini), run:
+		$ ./make.sh ios_armv7s
+
+	- To cross-compile for Arm64 (iPhone 5S, iPad mini Retina, iPad Air), run:
+		$ ./make.sh ios_arm64
+
+	- To cross-compile for all iDevices (armv7 + armv7s + arm64), run:
+		$ ./make.sh ios
+
+  Resulted files libcapstone.dylib, libcapstone.a & tests/test* can then
+  be used on iOS devices.
+
+
+
+(5) Cross-compile for Android
+
+  To cross-compile for Android (smartphone/tablet), Android NDK is required.
+  NOTE: Only ARM and ARM64 are currently supported.
+
+       $ NDK=/android/android-ndk-r10e ./make.sh cross-android arm
+       or
+       $ NDK=/android/android-ndk-r10e ./make.sh cross-android arm64
+
+  Resulted files libcapstone.so, libcapstone.a & tests/test* can then
+  be used on Android devices.
+
+
+
+(6) Compile on Windows with Cygwin
+
+  To compile under Cygwin gcc-mingw-w64-i686 or x86_64-w64-mingw32 run:
+
+        - To compile Windows 32-bit binary under Cygwin, run:
+
+                $ ./make.sh cygwin-mingw32
+
+        - To compile Windows 64-bit binary under Cygwin, run:
+
+                $ ./make.sh cygwin-mingw64
+
+  Resulted files libcapstone.dll, libcapstone.dll.a & tests/test*.exe can then
+  be used on Windows machine.
+
+
+
+(7) By default, "cc" (default C compiler on the system) is used as compiler.
+
+	- To use "clang" compiler instead, run the command below:
+
+		$ ./make.sh clang
+
+	- To use "gcc" compiler instead, run:
+
+		$ ./make.sh gcc
+
+
+
+(8) To uninstall Capstone, run the command below:
+
+		$ sudo ./make.sh uninstall
+
+
+
+(9) Language bindings
+
+  So far, Python, Ocaml & Java are supported by bindings in the main code.
+  Look for the bindings under directory bindings/, and refer to README file
+  of corresponding languages.
+
+  Community also provide bindings for C#, Go, Ruby, NodeJS, C++ & Vala. Links to
+  these can be found at address http://capstone-engine.org/download.html
diff --git a/COMPILE_CMAKE.TXT b/COMPILE_CMAKE.TXT
new file mode 100644
index 0000000..57d5f5e
--- /dev/null
+++ b/COMPILE_CMAKE.TXT
@@ -0,0 +1,80 @@
+This documentation explains how to compile Capstone with CMake, focus on
+using Microsoft Visual C as the compiler.
+
+To compile Capstone on *nix, see COMPILE.TXT.
+
+To compile Capstone on Windows using Visual Studio, see COMPILE_MSVC.TXT.
+
+                        *-*-*-*-*-*
+
+This documentation requires CMake & Windows SDK or MS Visual Studio installed on
+your machine.
+
+Get CMake for free from http://www.cmake.org.
+
+
+
+(0) Tailor Capstone to your need.
+
+  Out of 8 archtitectures supported by Capstone (Arm, Arm64, Mips, PPC, Sparc,
+  SystemZ, X86 & XCore), if you just need several selected archs, run "cmake"
+  with the unwanted archs disabled (set to 0) as followings.
+
+  - CAPSTONE_ARM_SUPPORT: support ARM. Run cmake with -DCAPSTONE_ARM_SUPPORT=0 to remove ARM.
+  - CAPSTONE_ARM64_SUPPORT: support ARM64. Run cmake with -DCAPSTONE_ARM64_SUPPORT=0 to remove ARM64.
+  - CAPSTONE_MIPS_SUPPORT: support Mips. Run cmake with -DCAPSTONE_MIPS_SUPPORT=0 to remove Mips.
+  - CAPSTONE_PPC_SUPPORT: support PPC. Run cmake with -DCAPSTONE_PPC_SUPPORT=0 to remove PPC.
+  - CAPSTONE_SPARC_SUPPORT: support Sparc. Run cmake with -DCAPSTONE_SPARC_SUPPORT=0 to remove Sparc.
+  - CAPSTONE_SYSZ_SUPPORT: support SystemZ. Run cmake with -DCAPSTONE_SYSZ_SUPPORT=0 to remove SystemZ.
+  - CAPSTONE_XCORE_SUPPORT: support XCore. Run cmake with -DCAPSTONE_XCORE_SUPPORT=0 to remove XCore.
+  - CAPSTONE_X86_SUPPORT: support X86. Run cmake with -DCAPSTONE_X86_SUPPORT=0 to remove X86.
+
+  By default, all 8 architectures are compiled in.
+
+
+  Besides, Capstone also allows some more customization via following macros.
+
+  - CAPSTONE_USE_SYS_DYN_MEM: change this to OFF to use your own dynamic memory management.
+  - CAPSTONE_BUILD_DIET: change this to ON to make the binaries more compact.
+  - CAPSTONE_X86_REDUCE: change this to ON to make X86 binary smaller.
+  - CAPSTONE_X86_ATT_DISABLE: change this to ON to disable AT&T syntax on x86.
+
+  By default, Capstone use system dynamic memory management, and both DIET and X86_REDUCE
+  modes are disabled. To use your own memory allocations, turn ON both DIET &
+  X86_REDUCE, run "cmake" with: -DCAPSTONE_USE_SYS_DYN_MEM=0 -DCAPSTONE_BUILD_DIET=1 -DCAPSTONE_X86_REDUCE=1
+
+
+  For each option, refer to docs/README for more details.
+
+
+
+(1) CMake allows you to generate different generators to build Capstone. Below is
+    some examples on how to build Capstone on Windows with CMake.
+
+
+  (*) To build Capstone using Nmake of Windows SDK, do:
+
+      mkdir build
+      cd build
+      ..\nmake.bat
+
+  After this, find the samples test*.exe, capstone.lib & capstone.dll
+  in the same directory.
+
+
+
+  (*) To build Capstone using Visual Studio, choose the generator accordingly to the
+  version of Visual Studio on your machine. For example, with Visual Studio 2013, do:
+
+      mkdir build
+      cd build
+      cmake -G "Visual Studio 12" ..
+
+  After this, find capstone.sln in the same directory. Open it with Visual Studio
+  and build the solution including libraries & all test as usual.
+
+
+
+(2) You can make sure the prior steps successfully worked by launching one of the
+  testing binary (test*.exe).
+
diff --git a/COMPILE_MSVC.TXT b/COMPILE_MSVC.TXT
new file mode 100644
index 0000000..f54b95b
--- /dev/null
+++ b/COMPILE_MSVC.TXT
@@ -0,0 +1,107 @@
+This documentation explains how to compile Capstone on Windows using
+Microsoft Visual Studio version 2010 or newer.
+
+To compile Capstone on *nix, see COMPILE.TXT
+
+To compile Capstone with CMake, see COMPILE_CMAKE.TXT
+
+                        *-*-*-*-*-*
+
+Capstone requires no prerequisite packages with default configurations, so it is
+easy to compile & install. Open the Visual Studio solution "msvc/capstone.sln"
+and follow the instructions below.
+
+NOTE: This requires Visual Studio 2010 or newer versions.
+
+If you wish to embed Capstone in a kernel driver, Visual Studio 2013 or newer
+versions, and Windows Driver Kit 8.1 Update 1 or newer versions are required.
+
+
+(0) Tailor Capstone to your need.
+
+  Out of 8 archtitectures supported by Capstone (Arm, Arm64, Mips, PPC, Sparc,
+  SystemZ, X86 & XCore), if you just need several selected archs, choose the ones
+  you want to compile in by opening Visual Studio solution "msvc\capstone.sln",
+  then directly editing the projects "capstone_static" & "capstone_dll" for static
+  and dynamic libraries, respectively. This must be done before going to the next
+  steps.
+
+  In VisualStudio interface, modify the preprocessor definitions via
+  "Project Properties" -> "Configuration Properties" -> "C/C++" -> "Preprocessor"
+  to customize Capstone library, as followings.
+
+  - CAPSTONE_HAS_ARM: support ARM. Delete this to remove ARM support.
+  - CAPSTONE_HAS_ARM64: support ARM64. Delete this to remove ARM64 support.
+  - CAPSTONE_HAS_MIPS: support Mips. Delete this to remove Mips support.
+  - CAPSTONE_HAS_PPC: support PPC. Delete this to remove PPC support.
+  - CAPSTONE_HAS_SPARC: support Sparc. Delete this to remove Sparc support.
+  - CAPSTONE_HAS_SYSZ: support SystemZ. Delete this to remove SystemZ support.
+  - CAPSTONE_HAS_X86: support X86. Delete this to remove X86 support.
+  - CAPSTONE_HAS_XCORE: support XCore. Delete this to remove XCore support.
+
+  By default, all 8 architectures are compiled in.
+
+
+  Besides, Capstone also allows some more customization via following macros.
+
+  - CAPSTONE_USE_SYS_DYN_MEM: delete this to use your own dynamic memory management.
+  - CAPSTONE_DIET_NO: rename this to "CAPSTONE_DIET" to make the binaries more compact.
+  - CAPSTONE_X86_REDUCE_NO: rename this to "CAPSTONE_X86_REDUCE" to make X86 binary smaller.
+  - CAPSTONE_X86_ATT_DISABLE_NO: rename this to "CAPSTONE_X86_ATT_DISABLE" to disable
+    AT&T syntax on x86.
+
+  By default, Capstone use system dynamic memory management, and both DIET and X86_REDUCE
+  modes are disable.
+
+
+  For each option, refer to docs/README for more details.
+
+
+
+(1) Compile from source on Windows with Visual Studio
+
+  - Choose the configuration and the platform you want: Release/Debug & Win32/Win64.
+  - Build only the libraries, or the libraries along with all the tests.
+  - "capstone_static_winkernel" is for compiling Capstone for a driver and
+    "test_winkernel" is a test for a driver, and those are excluded from build by
+    default. To compile them, open the Configuration Manager through the [Build]
+    menu and check "Build" check boxes for those project.
+
+
+
+(2) You can make sure the prior steps successfully worked by launching one of the
+  testing binary (test*.exe).
+
+  The testing binary for a driver "test_winkernel.sys" is made up of all tests for
+  supported architectures configured with the step (0) along side its own tests.
+  Below explains a procedure to run the test driver and check test results.
+
+  On the x64 platform, the test signing mode has to be enabled to install the test
+  driver. To do it, open the command prompt with the administrator privileges and
+  type the following command, and then restart the system to activate the change:
+
+      >bcdedit /set testsigning on
+
+  Test results from the test driver is sent to kernel debug buffer. In order to
+  see those results, download DebugView and run it with the administrator
+  privileges, then check [Capture Kernel] through the [Capture] menu.
+
+  DebugView: https://technet.microsoft.com/en-us/sysinternals/debugview.aspx
+
+  To install and uninstall the driver, use the 'sc' command. For installing and
+  executing test_winkernel.sys, execute the following commands with the
+  administrator privileges:
+
+      >sc create test_winkernel type= kernel binPath= <full path to test_winkernel.sys>
+      [SC] CreateService SUCCESS
+
+      >sc start test_winkernel
+      [SC] StartService FAILED 995:
+
+      The I/O operation has been aborted because of either a thread exit or an application request.
+
+  To uninstall the driver, execute the following commands with the administrator
+  privileges:
+
+      >sc delete test_winkernel
+      >bcdedit /deletevalue testsigning
diff --git a/CREDITS.TXT b/CREDITS.TXT
new file mode 100644
index 0000000..2038ef6
--- /dev/null
+++ b/CREDITS.TXT
@@ -0,0 +1,65 @@
+This file credits all the contributors of the Capstone engine project.
+
+Key developers
+==============
+1. Nguyen Anh Quynh <aquynh -at- gmail.com>
+	- Core engine
+	- Bindings: Python, Ruby, OCaml, Java, C#
+
+2. Tan Sheng Di <shengdi -at- coseinc.com>
+	- Bindings: Ruby
+
+3. Ben Nagy <ben -at- coseinc.com>
+	- Bindings: Ruby, Go
+
+4. Dang Hoang Vu <dang.hvu -at- gmail.com>
+	- Bindings: Java
+
+
+Beta testers (in random order)
+==============================
+Pancake
+Van Hauser
+FX of Phenoelit
+The Grugq, The Grugq   <-- our hero for submitting the first ever patch!
+Isaac Dawson, Veracode Inc
+Patroklos Argyroudis, Census Inc. (http://census-labs.com)
+Attila Suszter
+Le Dinh Long
+Nicolas Ruff
+Gunther
+Alex Ionescu, Winsider Seminars & Solutions Inc.
+Snare
+Daniel Godas-Lopez
+Joshua J. Drake
+Edgar Barbosa
+Ralf-Philipp Weinmann
+Hugo Fortier
+Joxean Koret
+Bruce Dang
+Andrew Dunham
+
+
+Contributors (in no particular order)
+=====================================
+(Please let us know if you want to have your name here)
+
+Ole André Vadla Ravnås (author of the 100th Pull-Request in our Github repo, thanks!)
+Axel "0vercl0k" Souchet (@0vercl0k) & Alex Ionescu: port to MSVC.
+Daniel Pistelli: Cmake support.
+Peter Hlavaty: integrate Capstone for Windows kernel drivers.
+Guillaume Jeanne: Ocaml binding.
+Martin Tofall, Obsidium Software: Optimize X86 performance & size.
+David Martínez Moreno & Hilko Bengen: Debian package.
+Félix Cloutier: Xcode project.
+Benoit Lecocq: OpenBSD package.
+Christophe Avoinne (Hlide): Improve memory management for better performance.
+Michael Cohen & Nguyen Tan Cong: Python module installer.
+Adel Gadllah, Francisco Alonso & Stefan Cornelius: RPM package.
+Felix Gröbert (Google): fuzz testing harness.
+Xipiter LLC: Capstone logo redesigned.
+Satoshi Tanda: Support Windows kernel driver.
+Tang Yuhang: cstool.
+Andrew Dutcher: better Python setup.
+Ruben Boonen: PowerShell binding.
+David Zimmer: VB6 binding.
diff --git a/ChangeLog b/ChangeLog
new file mode 100644
index 0000000..8bd7086
--- /dev/null
+++ b/ChangeLog
@@ -0,0 +1,554 @@
+This file details the changelog of Capstone.
+
+---------------------------------
+Version 3.0.5-rc3: July 31st, 2017
+
+
+[ Core ]
+
+- Fix compilation for MacOS kernel extension
+- cstool to support armbe and arm64be modes
+- Add nmake.bat for Windows build
+- Fix an integer overflow for Windows kernel driver
+- Support to embedded Capstone into MacOS kernel
+- cstool: fix mips64 mode
+- Fix a compiling error in MS Visual Studio 2015
+- Install pkgconfig file with CMake build
+- Fix SOVERSION property of CMake build
+- Properly handle switching to Endian mode at run-time for Arm, Arm64, Mips & Sparc
+- Fix MingW build
+- Better handle CMake installation for Linux 64bit
+
+
+[ X86 ]
+
+- Support BND prefix of Intel MPX extension
+- Correct operand size for CALL/JMP in 64bit mode with prefix 0x66
+- LOCK NOP is a valid instruction
+- Fix ATT syntax for instruction with zero offset segment register
+- LES/LDS are invalid in 64bit mode
+- Fix number of operands for some MOV instructions
+
+
+[ ARM ]
+
+- Fix POP reg to update SP register
+- Update flags for UADD8 instruction
+
+
+[ ARM64 ]
+
+- Better performance with new lookup table
+- Handle system registers added in ARMv8.1/2
+
+
+[ Java binding ]
+
+- Better handle input with invalid code
+
+
+[ Visual Basic binding ]
+
+- New binding
+
+---------------------------------
+Version 3.0.5-rc2: March 2nd, 2017
+
+
+[ Core ]
+
+- Fix build for Visual Studio 2012
+- Fix X86_REL_ADDR macro
+- Add CS_VERSION_MAJOR, CS_VERSION_MINOR, CS_VERSION_EXTRA
+- Better support for embedding Capstone into Windows kernel drivers
+- Support to embedded Capstone into MacOS kernel
+- Support MacOS 10.11 and up
+- Better support for Cygwin
+- Support build packages for FreeBSD & DragonflyBSD
+- Add a command-line tool "cstool"
+- Properly handle switching to Endian mode at run-time for Arm, Arm64, Mips & Sparc
+
+
+[ X86 ]
+
+- Some random 16-bit code can be handled wrongly.
+- Remove abundant operand type X86_OP_FP
+- Fix instructions MOVQ, LOOP, LOOPE, LOOPNE, CALL/JMP rel16, REPNE LODSD, MOV *AX, MOFFS, FAR JMP/CALL
+- Add X86_REG_EFLAGS for STC and STD
+- Fix instruction attributes for SYSEXIT, MOVW, ROL, LGS, SLDT
+- Rename registers ST0-ST7 to be consistent with asm output
+
+
+[ ARM ]
+
+- Properly handle IT instruction
+- Fix LDRSB
+- Fix writeback for LDR
+- Fix Thumb BigEndian setup
+
+
+[ ARM64 ]
+
+- Fix arith extender
+- Fix writeback for LDR
+- Rename enum arm64_mrs_reg to arm64_sysreg
+
+
+[ PowerPC ]
+
+- Print 0 offset for memory operand
+
+
+[ Sparc ]
+
+- Fix POPC instruction
+
+
+[ Python binding ]
+
+- Better PyPy support
+- Add __version__
+- Better support for Python 3
+- Fix CS_SKIPDATA_CALLBACK prototype
+- Cast skipdata function inside binding to simplify the API
+
+
+[ Java binding ]
+
+- Better handle input with invalid code
+
+
+[ PowerShell ]
+
+- New binding
+
+---------------------------------
+Version 3.0.4: July 15th, 2015
+
+
+[ Library ]
+
+- Improve cross-compile for Android using Android NDK.
+- Support cross-compile for AArch64 Android (with Linux GCC).
+- Removed osxkernel_inttypes.h that is incompatible with BSD license.
+- Make it possible to compile with CC having a space inside (like "ccache gcc").
+
+
+[ X86 ]
+
+- Fix a null pointer dereference bug on handling code with special prefixes.
+- Properly handle AL/AX/EAX operand for OUT instruction in AT&T syntax.
+- Print immediate operand in positive form in some algorithm instructions.
+- Properly decode some SSE instructions.
+
+
+[ PowerPC ]
+
+- Fixed a memory corruption bug.
+- Fixed a memory corruption bug for the engine built in DIET mode.
+
+
+[ Mips ]
+
+- Fixed instruction ID of SUBU instruction.
+- Fixed a memory corruption bug.
+
+
+[ Arm ]
+
+- Fixed a memory corruption bug on IT instruction.
+
+
+[ XCore ]
+
+- Fixed a memory corruption bug when instruction has a memory operand.
+
+
+[ Python ]
+
+- Support Virtualenv.
+- setup.py supports option --user if not in a virtualenv to allow for local usage.
+- Properly handle the destruction of Cs object in the case the shared library
+  was already unloaded.
+
+---------------------------------
+Version 3.0.3: May 08th, 2015
+
+
+[ Library ]
+
+- Support to embed into Mac OS X kernel extensions.
+- Now it is possible to compile Capstone with older C compilers, such as
+  GCC 4.8 on Ubuntu 12.04.
+- Add "test_iter" to MSVC project.
+
+
+[ X86 ]
+
+- All shifted instructions SHL, SHR, SAL, SAR, RCL, RCR, ROL & ROR now support
+  $1 as first operand in *AT&T* syntax (so we have "rcll $1, %edx" instead of
+  "rcll %edx").
+- CMPXCHG16B is a valid instruction with LOCK prefix.
+- Fixed a segfault on the input of 0xF3.
+
+
+[ Arm ]
+
+- BLX instruction modifies PC & LR registers.
+
+
+[ Sparc ]
+
+- Improved displacement decoding for sparc banching instructions.
+
+
+[ Python binding ]
+
+- Fix for Cython so it can properly initialize.
+- X86Op.avx_zero_mask now has c_bool type, but not c_uint8 type.
+- Properly support compile with Cygwin & install binding (setup.py).
+
+---------------------------------
+Version 3.0.2: March 11th, 2015
+
+
+[ Library ]
+
+- On *nix, only export symbols that are part of the API (instead of all
+  the internal symbols).
+
+
+[ X86 ]
+
+- Do not consider 0xF2 as REPNE prefix if it is a part of instruction encoding.
+- Fix implicit registers read/written & instruction groups of some instructions.
+- More flexible on the order of prefixes, so better handle some tricky
+  instructions.
+- REPNE prefix can go with STOS & MOVS instructions.
+- Fix a compilation bug for X86_REDUCE mode.
+- Fix operand size of instructions with operand PTR []
+
+
+[ Arm ]
+
+- Fix a bug where arm_op_mem.disp is wrongly calculated (in DETAIL mode).
+- Fix a bug on handling the If-Then block.
+
+
+[ Mips ]
+
+- Sanity check for the input size for MIPS64 mode.
+
+
+[ MSVC ]
+
+- Compile capstone.dll with static runtime MSVCR built in.
+
+
+[ Python binding ]
+
+- Fix a compiling issue of Cython binding with gcc 4.9.
+
+---------------------------------
+Version 3.0.1: February 03rd, 2015
+
+[ X86 ]
+
+- Properly handle LOCK, REP, REPE & REPNE prefixes.
+- Handle undocumented immediates for SSE's (V)CMPPS/PD/SS/SD instructions.
+- Print LJUMP/LCALL without * as prefix for Intel syntax.
+- Handle REX prefix properly for segment/MMX related instructions (x86_64).
+- Instruction with length > 15 is consider invalid.
+- Handle some tricky encodings for instructions MOVSXD, FXCH, FCOM, FCOMP,
+  FSTP, FSTPNCE, NOP.
+- Handle some tricky code for some X86_64 instructions with REX prefix.
+- Add missing operands in detail mode for PUSH , POP , IN/OUT reg, reg
+- MOV32ms & MOV32sm should reference word rather than dword.
+
+
+[ Arm64 ]
+
+- BL & BLR instructions do not read SP register.
+- Print absolute (rather than relative) address for instructions B, BL,
+  CBNZ, ADR.
+
+
+[ Arm ]
+
+- Instructions ADC & SBC do not update flags.
+- BL & BLX do not read SP, but PC register.
+- Alias LDR instruction with operands [sp], 4 to POP.
+- Print immediate operand of MVN instruction in positive hexadecimal form.
+
+
+[ PowerPC ]
+
+- Fix some compilation bugs when DIET mode is enable.
+- Populate SLWI/SRWI instruction details with SH operand.
+
+
+[ Python binding ]
+
+- Fix a Cython bug when CsInsn.bytes returns a shorten array of bytes.
+- Fixed a memory leak for Cython disasm functions when we immaturely quit
+  the enumeration of disassembled instructions.
+- Fix a NULL memory access issue when SKIPDATA & Detail modes are enable
+  at the same time.
+- Fix a memory leaking bug when when we stop enumeration over the disassembled
+  instructions prematurely.
+- Export generic operand types & groups (CS_OP_xxx & CS_GRP_xxx).
+
+---------------------------------
+Version 3.0: November 19th, 2014
+
+[ API ]
+
+- New API: cs_disasm_iter & cs_malloc. See docs/README for tutorials.
+- Renamed cs_disasm_ex to cs_disasm (cs_disasm_ex is still supported, but
+  marked obsolete to be removed in future)
+- Support SKIPDATA mode, so Capstone can jump over unknown data and keep going
+  from the next legitimate instruction. See docs/README for tutorials.
+- More details provided in cs_detail struct for all architectures.
+- API version was bumped to 3.0.
+
+
+[ Bindings ]
+
+- Python binding supports Python3 (besides Python2).
+- Support Ocaml binding.
+- Java: add close() method to be used to deinitialize a Capstone object when
+  no longer use it.
+
+
+[ Architectures ]
+
+- New architectures: Sparc, SystemZ & XCore.
+- Important bugfixes for Arm, Arm64, Mips, PowerPC & X86.
+- Support more instructions for Arm, Arm64, Mips, PowerPC & X86.
+- Always expose absolute addresses rather than relative addresses (Arm, Arm64,
+  Mips, PPC, Sparc, X86).
+- Use common instruction operand types REG, IMM, MEM & FP across all
+  architectures (to enable cross-architecture analysis).
+- Use common instruction group types across all architectures (to enable
+  cross-architecture analysis).
+
+
+[ X86 ]
+
+- X86 engine is mature & handles all the malware tricks (that we are aware of).
+- Added a lot of new instructions (such as AVX512, 3DNow, etc).
+- Add prefix symbols X86_PREFIX_REP/REPNE/LOCK/CS/DS/SS/FS/GS/ES/OPSIZE/ADDRSIZE.
+- Print immediate in positive form & hexadecimal for AND/OR/XOR instructions.
+- More friendly disassembly for JMP16i (in the form segment:offset)
+
+
+[ Mips ]
+
+- Engine added supports for new hardware modes: Mips32R6 (CS_MODE_MIPS32R6) &
+  MipsGP64 (CS_MODE_MIPSGP64).
+- Removed the ABI-only mode CS_MODE_N64.
+- New modes CS_MODE_MIPS32 & CS_MODE_MIPS64 (to use instead of CS_MODE_32 &
+  CS_MODE_64).
+
+
+[ ARM ]
+
+- Support new mode CS_MODE_V8 for Armv8 A32 encodings.
+- Print immediate in positive form & hexadecimal for AND/ORR/EOR/BIC instructions
+
+
+[ ARM64 ]
+
+- Print immediate in hexadecimal for AND/ORR/EOR/TST instructions.
+
+
+[ PowerPC ]
+
+- Do not print a dot in front of absolute address.
+
+
+[ Other features ]
+
+- Support for Microsoft Visual Studio (so enable Windows native compilation).
+- Support CMake compilation.
+- Cross-compile for Android.
+- Build libraries/tests using XCode project
+- Much faster, while consuming less memory for all architectures.
+
+---------------------------------
+Version 2.1.2: April 3rd, 2014
+
+This is a stable release to fix some bugs deep in the core. There is no update
+to any architectures or bindings, so bindings version 2.1 can be used with this
+version 2.1.2 just fine.
+
+[ Core changes]
+
+- Support cross-compilation for all iDevices (iPhone/iPad/iPod).
+- X86: do not print memory offset in negative form.
+- Fix a bug in X86 when Capstone cannot handle short instruction.
+- Print negative number above -9 without prefix 0x (arm64, mips, arm).
+- Correct the SONAME setup for library versioning (Linux, *BSD, Solaris).
+- Set library versioning for dylib of OSX.
+
+---------------------------------
+Version 2.1.1: March 13th, 2014
+
+This is a stable release to fix some bugs deep in the core. There is no update
+to any architectures or bindings, so bindings version 2.1 can be used with this
+version 2.1.1 just fine.
+
+[ Core changes]
+
+- Fix a buffer overflow bug in Thumb mode (ARM). Some special input can
+  trigger this flaw.
+- Fix a crash issue when embedding Capstone into OSX kernel. This should
+  also enable Capstone to be embedded into other systems with limited stack
+  memory size such as Linux kernel or some firmwares.
+- Use a proper SONAME for library versioning (Linux).
+
+---------------------------------
+Version 2.1: March 5th, 2014
+
+[ API changes ]
+
+- API version has been bumped to 2.1.
+- Change prototype of cs_close() to be able to invalidate closed handle.
+  See http://capstone-engine.org/version_2.1_API.html for more information.
+- Extend cs_support() to handle more query types, not only about supported
+  architectures. This change is backward compatible, however, so existent code
+  do not need to be modified to support this.
+- New query type CS_SUPPORT_DIET for cs_support() to ask about diet status of
+  the engine.
+- New error code CS_ERR_DIET to report errors about newly added diet mode.
+- New error code CS_ERR_VERSION to report issue of incompatible versions between
+  bindings & core engine.
+
+
+[ Core changes ]
+
+- On memory usage, Capstone uses about 40% less memory, while still faster
+  than version 2.0.
+- All architectures are much smaller: binaries size reduce at least 30%.
+  Especially, X86-only binary reduces from 1.9MB to just 720KB.
+- Support "diet" mode, in which engine size is further reduced (by around 40%)
+  for embedding purpose. The price to pay is that we have to sacrifice some
+  non-critical data fields. See http://capstone-engine.org/diet.html for more
+  details.
+
+
+[ Architectures ]
+
+- Update all 5 architectures to fix bugs.
+- PowerPC:
+	- New instructions: FMR & MSYNC.
+- Mips:
+	- New instruction: DLSA
+- X86:
+	- Properly handle AVX-512 instructions.
+	- New instructions: PSETPM, SALC, INT1, GETSEC.
+	- Fix some memory leaking issues in case of prefixed instructions such
+	  as LOCK, REP, REPNE.
+
+
+[ Python binding ]
+
+- Verify the core version at initialization time. Refuse to run if its version
+  is different from the core's version.
+- New API disasm_lite() added to Cs class. This light API only returns tuples of
+  (address, size, mnemonic, op_str), rather than list of CsInsn objects. This
+  improves performance by around 30% in some benchmarks.
+- New API version_bind() returns binding's version, which might differ from
+  the core's API version if the binding is out-of-date.
+- New API debug() returns information on Cython support, diet status & archs
+  compiled in.
+- Fixed some memory leaking bugs for Cython binding.
+- Fix a bug crashing Cython code when accessing @regs_read/regs_write/groups.
+- Support diet mode.
+
+
+[ Java binding ]
+
+- Fix some memory leaking bugs.
+- New API version() returns combined version.
+- Support diet mode.
+- Better support for detail option.
+
+
+[ Miscellaneous ]
+
+- make.sh now can uninstall the core engine. This is done with:
+
+	$ sudo ./make.sh uninstall
+
+----------------------------------
+Version 2.0: January 22nd, 2014
+
+Release 2.0 deprecates verison 1.0 and brings a lot of crucial changes.
+
+[ API changes ]
+
+- API version has been bumped to 2.0 (see cs_version() API)
+- New API cs_strerror(errno) returns a string describing error code given
+  in its only argument.
+- cs_version() now returns combined version encoding both major & minor versions.
+- New option CS_OPT_MODE allows to change engine’s mode at run-time with
+  cs_option().
+- New option CS_OPT_MEM allows to specify user-defined functions for dynamically
+  memory management used internally by Capstone. This is useful to embed Capstone
+  into special environments such as kernel or firware.
+- New API cs_support() can be used to check if this lib supports a particular
+  architecture (this is necessary since we now allow to choose which architectures
+  to compile in).
+- The detail option is OFF by default now. To get detail information, it should be
+  explicitly turned ON. The details then can be accessed using cs_insn.detail
+  pointer (to newly added structure cs_detail)
+
+
+[ Core changes ]
+
+- On memory usage, Capstone uses much less memory, but a lot faster now.
+- User now can choose which architectures to be supported by modifying config.mk
+  before compiling/installing.
+
+
+[ Architectures ]
+
+- Arm
+     - Support Big-Endian mode (besides Little-Endian mode).
+     - Support friendly register, so instead of output sub "r12,r11,0x14",
+	 we have "sub ip,fp,0x14".
+- Arm64: support Big-Endian mode (besides Little-Endian mode).
+- PowerPC: newly added.
+- Mips: support friendly register, so instead of output "srl $2,$1,0x1f",
+     we have "srl $v0,$at,0x1f".
+- X86: bug fixes.
+
+
+[ Python binding ]
+
+- Python binding is vastly improved in performance: around 3 ~ 4 times faster
+  than in 1.0.
+- Cython support has been added, which can further speed up over the default
+  pure Python binding (up to 30% in some cases)
+- Function cs_disasm_quick() & Cs.disasm() now use generator (rather than a list)
+  to return succesfully disassembled instructions. This improves the performance
+  and reduces memory usage.
+
+
+[ Java binding ]
+
+- Better performance & bug fixes.
+
+
+[ Miscellaneous ]
+
+- Fixed some installation issues with Gentoo Linux.
+- Capstone now can easily compile/install on all *nix, including Linux, OSX,
+  {Net, Free, Open}BSD & Solaris.
+
+----------------------------------
+[Version 1.0]: December 18th, 2013
+
+- Initial public release.
+
diff --git a/HACK.TXT b/HACK.TXT
new file mode 100644
index 0000000..5864bff
--- /dev/null
+++ b/HACK.TXT
@@ -0,0 +1,46 @@
+Capstone source is organized as followings.
+
+
+.                   <- core engine + README + COMPILE.TXT etc
+├── arch            <- code handling disasm engine for each arch
+│   ├── AArch64     <- ARM64 (aka ARMv8) engine
+│   ├── ARM         <- ARM engine
+│   ├── Mips        <- Mips engine
+│   ├── PowerPC     <- PowerPC engine
+│   ├── Sparc       <- Sparc engine
+│   ├── SystemZ     <- SystemZ engine
+│   ├── X86         <- X86 engine
+│   └── XCore       <- XCore engine
+├── bindings        <- all bindings are under this dir
+│   ├── java        <- Java bindings + test code
+│   ├── ocaml       <- Ocaml bindings + test code
+│   └── python      <- Python bindings + test code
+├── contrib         <- Code contributed by community to help Capstone integration
+├── cstool          <- Cstool
+├── docs            <- Documentation
+├── include         <- API headers in C language (*.h)
+├── msvc            <- Microsoft Visual Studio support (for Windows compile)
+├── packages        <- Packages for Linux/OSX/BSD.
+├── windows         <- Windows support (for Windows kernel driver compile)
+├── suite           <- Development test tools - for Capstone developers only
+├── tests           <- Test code (in C language)
+└── xcode           <- Xcode support (for MacOSX compile)
+
+
+Follow instructions in COMPILE.TXT for how to compile and run test code.
+
+Note: if you find some strange bugs, it is recommended to firstly clean
+the code and try to recompile/reinstall again. This can be done with:
+
+	$ ./make.sh
+	$ sudo ./make.sh install
+
+Then test Capstone with cstool, for example:
+
+	$ cstool x32 "90 91"
+
+At the same time, for Java/Ocaml/Python bindings, be sure to always use
+the bindings coming with the core to avoid potential incompatibility issue
+with older versions.
+See bindings/<language>/README for detail instructions on how to compile &
+install the bindings.
diff --git a/LEB128.h b/LEB128.h
new file mode 100644
index 0000000..6a45274
--- /dev/null
+++ b/LEB128.h
@@ -0,0 +1,40 @@
+//===- llvm/Support/LEB128.h - [SU]LEB128 utility functions -----*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares some utility functions for encoding SLEB128 and
+// ULEB128 values.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_LLVM_SUPPORT_LEB128_H
+#define CS_LLVM_SUPPORT_LEB128_H
+
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
+#include <stdint.h>
+#endif
+
+/// Utility function to decode a ULEB128 value.
+static inline uint64_t decodeULEB128(const uint8_t *p, unsigned *n)
+{
+	const uint8_t *orig_p = p;
+	uint64_t Value = 0;
+	unsigned Shift = 0;
+	do {
+		Value += (*p & 0x7f) << Shift;
+		Shift += 7;
+	} while (*p++ >= 128);
+	if (n)
+		*n = (unsigned)(p - orig_p);
+	return Value;
+}
+
+#endif  // LLVM_SYSTEM_LEB128_H
diff --git a/LICENSE b/LICENSE
new file mode 100644
index 0000000..0dabdc7
--- /dev/null
+++ b/LICENSE
@@ -0,0 +1,31 @@
+This is the software license for Capstone disassembly framework.
+Capstone has been designed & implemented by Nguyen Anh Quynh <aquynh@gmail.com>
+
+See http://www.capstone-engine.org for further information.
+
+Copyright (c) 2013, COSEINC.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice,
+  this list of conditions and the following disclaimer in the documentation
+  and/or other materials provided with the distribution.
+* Neither the name of the developer(s) nor the names of its
+  contributors may be used to endorse or promote products derived from this
+  software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
diff --git a/LICENSE.TXT b/LICENSE.TXT
new file mode 100644
index 0000000..0dabdc7
--- /dev/null
+++ b/LICENSE.TXT
@@ -0,0 +1,31 @@
+This is the software license for Capstone disassembly framework.
+Capstone has been designed & implemented by Nguyen Anh Quynh <aquynh@gmail.com>
+
+See http://www.capstone-engine.org for further information.
+
+Copyright (c) 2013, COSEINC.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice,
+  this list of conditions and the following disclaimer in the documentation
+  and/or other materials provided with the distribution.
+* Neither the name of the developer(s) nor the names of its
+  contributors may be used to endorse or promote products derived from this
+  software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
diff --git a/LICENSE_LLVM.TXT b/LICENSE_LLVM.TXT
new file mode 100644
index 0000000..66d6647
--- /dev/null
+++ b/LICENSE_LLVM.TXT
@@ -0,0 +1,71 @@
+==============================================================================
+LLVM Release License
+==============================================================================
+University of Illinois/NCSA
+Open Source License
+
+Copyright (c) 2003-2013 University of Illinois at Urbana-Champaign.
+All rights reserved.
+
+Developed by:
+
+    LLVM Team
+
+    University of Illinois at Urbana-Champaign
+
+    http://llvm.org
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal with
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+    * Redistributions of source code must retain the above copyright notice,
+      this list of conditions and the following disclaimers.
+
+    * Redistributions in binary form must reproduce the above copyright notice,
+      this list of conditions and the following disclaimers in the
+      documentation and/or other materials provided with the distribution.
+
+    * Neither the names of the LLVM Team, University of Illinois at
+      Urbana-Champaign, nor the names of its contributors may be used to
+      endorse or promote products derived from this Software without specific
+      prior written permission.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+SOFTWARE.
+
+==============================================================================
+Copyrights and Licenses for Third Party Software Distributed with LLVM:
+==============================================================================
+The LLVM software contains code written by third parties.  Such software will
+have its own individual LICENSE.TXT file in the directory in which it appears.
+This file will describe the copyrights, license, and restrictions which apply
+to that code.
+
+The disclaimer of warranty in the University of Illinois Open Source License
+applies to all code in the LLVM Distribution, and nothing in any of the
+other licenses gives permission to use the names of the LLVM Team or the
+University of Illinois to endorse or promote products derived from this
+Software.
+
+The following pieces of software have additional or alternate copyrights,
+licenses, and/or restrictions:
+
+Program             Directory
+-------             ---------
+Autoconf            llvm/autoconf
+                    llvm/projects/ModuleMaker/autoconf
+                    llvm/projects/sample/autoconf
+Google Test         llvm/utils/unittest/googletest
+OpenBSD regex       llvm/lib/Support/{reg*, COPYRIGHT.regex}
+pyyaml tests        llvm/test/YAMLParser/{*.data, LICENSE.TXT}
+ARM contributions   llvm/lib/Target/ARM/LICENSE.TXT
+md5 contributions   llvm/lib/Support/MD5.cpp llvm/include/llvm/Support/MD5.h
diff --git a/MCDisassembler.h b/MCDisassembler.h
new file mode 100644
index 0000000..bbbd38a
--- /dev/null
+++ b/MCDisassembler.h
@@ -0,0 +1,14 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_MCDISASSEMBLER_H
+#define CS_MCDISASSEMBLER_H
+
+typedef enum DecodeStatus {
+	MCDisassembler_Fail = 0,
+	MCDisassembler_SoftFail = 1,
+	MCDisassembler_Success = 3,
+} DecodeStatus;
+
+#endif
+
diff --git a/MCFixedLenDisassembler.h b/MCFixedLenDisassembler.h
new file mode 100644
index 0000000..ab8b968
--- /dev/null
+++ b/MCFixedLenDisassembler.h
@@ -0,0 +1,30 @@
+//===-- llvm/MC/MCFixedLenDisassembler.h - Decoder driver -------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+// Fixed length disassembler decoder state machine driver.
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_LLVM_MC_MCFIXEDLENDISASSEMBLER_H
+#define CS_LLVM_MC_MCFIXEDLENDISASSEMBLER_H
+
+// Disassembler state machine opcodes.
+enum DecoderOps {
+	MCD_OPC_ExtractField = 1, // OPC_ExtractField(uint8_t Start, uint8_t Len)
+	MCD_OPC_FilterValue,      // OPC_FilterValue(uleb128 Val, uint16_t NumToSkip)
+	MCD_OPC_CheckField,       // OPC_CheckField(uint8_t Start, uint8_t Len,
+							  //                uleb128 Val, uint16_t NumToSkip)
+	MCD_OPC_CheckPredicate,   // OPC_CheckPredicate(uleb128 PIdx, uint16_t NumToSkip)
+	MCD_OPC_Decode,           // OPC_Decode(uleb128 Opcode, uleb128 DIdx)
+	MCD_OPC_SoftFail,         // OPC_SoftFail(uleb128 PMask, uleb128 NMask)
+	MCD_OPC_Fail              // OPC_Fail()
+};
+
+#endif
diff --git a/MCInst.c b/MCInst.c
new file mode 100644
index 0000000..bdbb82d
--- /dev/null
+++ b/MCInst.c
@@ -0,0 +1,176 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#if defined(CAPSTONE_HAS_OSXKERNEL)
+#include <libkern/libkern.h>
+#else
+#include <stdio.h>
+#include <stdlib.h>
+#endif
+#include <string.h>
+
+#include "MCInst.h"
+#include "utils.h"
+
+#define MCINST_CACHE (ARR_SIZE(mcInst->Operands) - 1)
+
+void MCInst_Init(MCInst *inst)
+{
+	inst->OpcodePub = 0;
+	inst->size = 0;
+	inst->has_imm = false;
+	inst->op1_size = 0;
+	inst->writeback = false;
+}
+
+void MCInst_clear(MCInst *inst)
+{
+	inst->size = 0;
+}
+
+// do not free @Op
+void MCInst_insert0(MCInst *inst, int index, MCOperand *Op)
+{
+	int i;
+
+	for(i = inst->size; i > index; i--)
+		//memcpy(&(inst->Operands[i]), &(inst->Operands[i-1]), sizeof(MCOperand));
+		inst->Operands[i] = inst->Operands[i-1];
+
+	inst->Operands[index] = *Op;
+	inst->size++;
+}
+
+void MCInst_setOpcode(MCInst *inst, unsigned Op)
+{
+	inst->Opcode = Op;
+}
+
+void MCInst_setOpcodePub(MCInst *inst, unsigned Op)
+{
+	inst->OpcodePub = Op;
+}
+
+unsigned MCInst_getOpcode(const MCInst *inst)
+{
+	return inst->Opcode;
+}
+
+unsigned MCInst_getOpcodePub(const MCInst *inst)
+{
+	return inst->OpcodePub;
+}
+
+MCOperand *MCInst_getOperand(MCInst *inst, unsigned i)
+{
+	return &inst->Operands[i];
+}
+
+unsigned MCInst_getNumOperands(const MCInst *inst)
+{
+	return inst->size;
+}
+
+// This addOperand2 function doesnt free Op
+void MCInst_addOperand2(MCInst *inst, MCOperand *Op)
+{
+	inst->Operands[inst->size] = *Op;
+
+	inst->size++;
+}
+
+void MCOperand_Init(MCOperand *op)
+{
+	op->Kind = kInvalid;
+	op->FPImmVal = 0.0;
+}
+
+bool MCOperand_isValid(const MCOperand *op)
+{
+	return op->Kind != kInvalid;
+}
+
+bool MCOperand_isReg(const MCOperand *op)
+{
+	return op->Kind == kRegister;
+}
+
+bool MCOperand_isImm(const MCOperand *op)
+{
+	return op->Kind == kImmediate;
+}
+
+bool MCOperand_isFPImm(const MCOperand *op)
+{
+	return op->Kind == kFPImmediate;
+}
+
+/// getReg - Returns the register number.
+unsigned MCOperand_getReg(const MCOperand *op)
+{
+	return op->RegVal;
+}
+
+/// setReg - Set the register number.
+void MCOperand_setReg(MCOperand *op, unsigned Reg)
+{
+	op->RegVal = Reg;
+}
+
+int64_t MCOperand_getImm(MCOperand *op)
+{
+	return op->ImmVal;
+}
+
+void MCOperand_setImm(MCOperand *op, int64_t Val)
+{
+	op->ImmVal = Val;
+}
+
+double MCOperand_getFPImm(const MCOperand *op)
+{
+	return op->FPImmVal;
+}
+
+void MCOperand_setFPImm(MCOperand *op, double Val)
+{
+	op->FPImmVal = Val;
+}
+
+MCOperand *MCOperand_CreateReg1(MCInst *mcInst, unsigned Reg)
+{
+	MCOperand *op = &(mcInst->Operands[MCINST_CACHE]);
+
+	op->Kind = kRegister;
+	op->RegVal = Reg;
+
+	return op;
+}
+
+void MCOperand_CreateReg0(MCInst *mcInst, unsigned Reg)
+{
+	MCOperand *op = &(mcInst->Operands[mcInst->size]);
+	mcInst->size++;
+
+	op->Kind = kRegister;
+	op->RegVal = Reg;
+}
+
+MCOperand *MCOperand_CreateImm1(MCInst *mcInst, int64_t Val)
+{
+	MCOperand *op = &(mcInst->Operands[MCINST_CACHE]);
+
+	op->Kind = kImmediate;
+	op->ImmVal = Val;
+
+	return op;
+}
+
+void MCOperand_CreateImm0(MCInst *mcInst, int64_t Val)
+{
+	MCOperand *op = &(mcInst->Operands[mcInst->size]);
+	mcInst->size++;
+
+	op->Kind = kImmediate;
+	op->ImmVal = Val;
+}
diff --git a/MCInst.h b/MCInst.h
new file mode 100644
index 0000000..b98f37f
--- /dev/null
+++ b/MCInst.h
@@ -0,0 +1,133 @@
+//===-- llvm/MC/MCInst.h - MCInst class -------------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the declaration of the MCInst and MCOperand classes, which
+// is the basic representation used to represent low-level machine code
+// instructions.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_MCINST_H
+#define CS_MCINST_H
+
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
+#include <stdint.h>
+#endif
+#include "include/capstone.h"
+
+typedef struct MCInst MCInst;
+typedef struct cs_struct cs_struct;
+typedef struct MCOperand MCOperand;
+
+/// MCOperand - Instances of this class represent operands of the MCInst class.
+/// This is a simple discriminated union.
+struct MCOperand {
+	enum {
+		kInvalid = 0,                 ///< Uninitialized.
+		kRegister,                ///< Register operand.
+		kImmediate,               ///< Immediate operand.
+		kFPImmediate,             ///< Floating-point immediate operand.
+	} MachineOperandType;
+	unsigned char Kind;
+
+	union {
+		unsigned RegVal;
+		int64_t ImmVal;
+		double FPImmVal;
+	};
+};
+
+bool MCOperand_isValid(const MCOperand *op);
+
+bool MCOperand_isReg(const MCOperand *op);
+
+bool MCOperand_isImm(const MCOperand *op);
+
+bool MCOperand_isFPImm(const MCOperand *op);
+
+bool MCOperand_isInst(const MCOperand *op);
+
+/// getReg - Returns the register number.
+unsigned MCOperand_getReg(const MCOperand *op);
+
+/// setReg - Set the register number.
+void MCOperand_setReg(MCOperand *op, unsigned Reg);
+
+int64_t MCOperand_getImm(MCOperand *op);
+
+void MCOperand_setImm(MCOperand *op, int64_t Val);
+
+double MCOperand_getFPImm(const MCOperand *op);
+
+void MCOperand_setFPImm(MCOperand *op, double Val);
+
+const MCInst *MCOperand_getInst(const MCOperand *op);
+
+void MCOperand_setInst(MCOperand *op, const MCInst *Val);
+
+// create Reg operand in the next slot
+void MCOperand_CreateReg0(MCInst *inst, unsigned Reg);
+
+// create Reg operand use the last-unused slot
+MCOperand *MCOperand_CreateReg1(MCInst *inst, unsigned Reg);
+
+// create Imm operand in the next slot
+void MCOperand_CreateImm0(MCInst *inst, int64_t Val);
+
+// create Imm operand in the last-unused slot
+MCOperand *MCOperand_CreateImm1(MCInst *inst, int64_t Val);
+
+/// MCInst - Instances of this class represent a single low-level machine
+/// instruction.
+struct MCInst {
+	unsigned OpcodePub;
+	uint8_t size;	// number of operands
+	bool has_imm;	// indicate this instruction has an X86_OP_IMM operand - used for ATT syntax
+	uint8_t op1_size; // size of 1st operand - for X86 Intel syntax
+	unsigned Opcode;
+	MCOperand Operands[48];
+	cs_insn *flat_insn;	// insn to be exposed to public
+	uint64_t address;	// address of this insn
+	cs_struct *csh;	// save the main csh
+	uint8_t x86opsize;	// opsize for [mem] operand
+
+	// (Optional) instruction prefix, which can be up to 4 bytes.
+	// A prefix byte gets value 0 when irrelevant.
+	// This is copied from cs_x86 struct
+	uint8_t x86_prefix[4];
+	uint8_t imm_size;	// immediate size for X86_OP_IMM operand
+	bool writeback;	// writeback for ARM
+};
+
+void MCInst_Init(MCInst *inst);
+
+void MCInst_clear(MCInst *inst);
+
+// do not free operand after inserting
+void MCInst_insert0(MCInst *inst, int index, MCOperand *Op);
+
+void MCInst_setOpcode(MCInst *inst, unsigned Op);
+
+unsigned MCInst_getOpcode(const MCInst*);
+
+void MCInst_setOpcodePub(MCInst *inst, unsigned Op);
+
+unsigned MCInst_getOpcodePub(const MCInst*);
+
+MCOperand *MCInst_getOperand(MCInst *inst, unsigned i);
+
+unsigned MCInst_getNumOperands(const MCInst *inst);
+
+// This addOperand2 function doesnt free Op
+void MCInst_addOperand2(MCInst *inst, MCOperand *Op);
+
+#endif
diff --git a/MCInstrDesc.c b/MCInstrDesc.c
new file mode 100644
index 0000000..7b834d3
--- /dev/null
+++ b/MCInstrDesc.c
@@ -0,0 +1,18 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#include "MCInstrDesc.h"
+
+/// isPredicate - Set if this is one of the operands that made up of
+/// the predicate operand that controls an isPredicable() instruction.
+bool MCOperandInfo_isPredicate(MCOperandInfo *m)
+{
+	return m->Flags & (1 << MCOI_Predicate);
+}
+
+/// isOptionalDef - Set if this operand is a optional def.
+///
+bool MCOperandInfo_isOptionalDef(MCOperandInfo *m)
+{
+	return m->Flags & (1 << MCOI_OptionalDef);
+}
diff --git a/MCInstrDesc.h b/MCInstrDesc.h
new file mode 100644
index 0000000..d2c3c51
--- /dev/null
+++ b/MCInstrDesc.h
@@ -0,0 +1,145 @@
+//===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the MCOperandInfo and MCInstrDesc classes, which
+// are used to describe target instructions and their operands.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_LLVM_MC_MCINSTRDESC_H
+#define CS_LLVM_MC_MCINSTRDESC_H
+
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
+#include <stdint.h>
+#endif
+#include "include/platform.h"
+
+//===----------------------------------------------------------------------===//
+// Machine Operand Flags and Description
+//===----------------------------------------------------------------------===//
+
+// Operand constraints
+enum MCOI_OperandConstraint {
+	MCOI_TIED_TO = 0,    // Must be allocated the same register as.
+	MCOI_EARLY_CLOBBER   // Operand is an early clobber register operand
+};
+
+/// OperandFlags - These are flags set on operands, but should be considered
+/// private, all access should go through the MCOperandInfo accessors.
+/// See the accessors for a description of what these are.
+enum MCOI_OperandFlags {
+	MCOI_LookupPtrRegClass = 0,
+	MCOI_Predicate,
+	MCOI_OptionalDef
+};
+
+/// Operand Type - Operands are tagged with one of the values of this enum.
+enum MCOI_OperandType {
+	MCOI_OPERAND_UNKNOWN,
+	MCOI_OPERAND_IMMEDIATE,
+	MCOI_OPERAND_REGISTER,
+	MCOI_OPERAND_MEMORY,
+	MCOI_OPERAND_PCREL
+};
+
+
+/// MCOperandInfo - This holds information about one operand of a machine
+/// instruction, indicating the register class for register operands, etc.
+///
+typedef struct MCOperandInfo {
+	/// RegClass - This specifies the register class enumeration of the operand
+	/// if the operand is a register.  If isLookupPtrRegClass is set, then this is
+	/// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
+	/// get a dynamic register class.
+	int16_t RegClass;
+
+	/// Flags - These are flags from the MCOI::OperandFlags enum.
+	uint8_t Flags;
+
+	/// OperandType - Information about the type of the operand.
+	uint8_t OperandType;
+
+	/// Lower 16 bits are used to specify which constraints are set. The higher 16
+	/// bits are used to specify the value of constraints (4 bits each).
+	uint32_t Constraints;
+	/// Currently no other information.
+} MCOperandInfo;
+
+
+//===----------------------------------------------------------------------===//
+// Machine Instruction Flags and Description
+//===----------------------------------------------------------------------===//
+
+/// MCInstrDesc flags - These should be considered private to the
+/// implementation of the MCInstrDesc class.  Clients should use the predicate
+/// methods on MCInstrDesc, not use these directly.  These all correspond to
+/// bitfields in the MCInstrDesc::Flags field.
+enum {
+	MCID_Variadic = 0,
+	MCID_HasOptionalDef,
+	MCID_Pseudo,
+	MCID_Return,
+	MCID_Call,
+	MCID_Barrier,
+	MCID_Terminator,
+	MCID_Branch,
+	MCID_IndirectBranch,
+	MCID_Compare,
+	MCID_MoveImm,
+	MCID_Bitcast,
+	MCID_Select,
+	MCID_DelaySlot,
+	MCID_FoldableAsLoad,
+	MCID_MayLoad,
+	MCID_MayStore,
+	MCID_Predicable,
+	MCID_NotDuplicable,
+	MCID_UnmodeledSideEffects,
+	MCID_Commutable,
+	MCID_ConvertibleTo3Addr,
+	MCID_UsesCustomInserter,
+	MCID_HasPostISelHook,
+	MCID_Rematerializable,
+	MCID_CheapAsAMove,
+	MCID_ExtraSrcRegAllocReq,
+	MCID_ExtraDefRegAllocReq,
+	MCID_RegSequence,
+};
+
+/// MCInstrDesc - Describe properties that are true of each instruction in the
+/// target description file.  This captures information about side effects,
+/// register use and many other things.  There is one instance of this struct
+/// for each target instruction class, and the MachineInstr class points to
+/// this struct directly to describe itself.
+typedef struct MCInstrDesc {
+	unsigned short  Opcode;        // The opcode number
+	unsigned char  NumOperands;   // Num of args (may be more if variable_ops)
+	unsigned char  NumDefs;       // Num of args that are definitions
+	unsigned short  SchedClass;    // enum identifying instr sched class
+	unsigned char  Size;          // Number of bytes in encoding.
+	unsigned        Flags;         // Flags identifying machine instr class
+	uint64_t        TSFlags;       // Target Specific Flag values
+	char ImplicitUses;  // Registers implicitly read by this instr
+	char ImplicitDefs;  // Registers implicitly defined by this instr
+	MCOperandInfo *OpInfo;   // 'NumOperands' entries about operands
+	uint64_t DeprecatedFeatureMask;// Feature bits that this is deprecated on, if any     
+	// A complex method to determine is a certain is deprecated or not, and return        
+	// the reason for deprecation.
+	//bool (*ComplexDeprecationInfo)(MCInst &, MCSubtargetInfo &, std::string &);           
+	unsigned char ComplexDeprecationInfo;	// dummy field, just to satisfy initializer
+} MCInstrDesc;
+
+bool MCOperandInfo_isPredicate(MCOperandInfo *m);
+
+bool MCOperandInfo_isOptionalDef(MCOperandInfo *m);
+
+#endif
diff --git a/MCRegisterInfo.c b/MCRegisterInfo.c
new file mode 100644
index 0000000..df1e836
--- /dev/null
+++ b/MCRegisterInfo.c
@@ -0,0 +1,143 @@
+//=== MC/MCRegisterInfo.cpp - Target Register Description -------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements MCRegisterInfo functions.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#include "MCRegisterInfo.h"
+
+/// DiffListIterator - Base iterator class that can traverse the
+/// differentially encoded register and regunit lists in DiffLists.
+/// Don't use this class directly, use one of the specialized sub-classes
+/// defined below.
+typedef struct DiffListIterator {
+	uint16_t Val;
+	MCPhysReg *List;
+} DiffListIterator;
+
+void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI,
+		MCRegisterDesc *D, unsigned NR,
+		unsigned RA, unsigned PC,
+		MCRegisterClass *C, unsigned NC,
+		uint16_t (*RURoots)[2], unsigned NRU,
+		MCPhysReg *DL,
+		char *Strings,
+		uint16_t *SubIndices, unsigned NumIndices,
+		uint16_t *RET)
+{
+	RI->Desc = D;
+	RI->NumRegs = NR;
+	RI->RAReg = RA;
+	RI->PCReg = PC;
+	RI->Classes = C;
+	RI->DiffLists = DL;
+	RI->RegStrings = Strings;
+	RI->NumClasses = NC;
+	RI->RegUnitRoots = RURoots;
+	RI->NumRegUnits = NRU;
+	RI->SubRegIndices = SubIndices;
+	RI->NumSubRegIndices = NumIndices;
+	RI->RegEncodingTable = RET;
+}
+
+static void DiffListIterator_init(DiffListIterator *d, MCPhysReg InitVal, MCPhysReg *DiffList)
+{
+	d->Val = InitVal;
+	d->List = DiffList;
+}
+
+static uint16_t DiffListIterator_getVal(DiffListIterator *d)
+{
+	return d->Val;
+}
+
+static bool DiffListIterator_next(DiffListIterator *d)
+{
+	MCPhysReg D;
+
+	if (d->List == 0)
+		return false;
+
+	D = *d->List;
+	d->List++;
+	d->Val += D;
+
+	if (!D)
+		d->List = 0;
+
+	return (D != 0);
+}
+
+static bool DiffListIterator_isValid(DiffListIterator *d)
+{
+	return (d->List != 0);
+}
+
+unsigned MCRegisterInfo_getMatchingSuperReg(MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, MCRegisterClass *RC)
+{
+	DiffListIterator iter;
+
+	if (Reg >= RI->NumRegs) {
+		return 0;
+	}
+
+	DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SuperRegs);
+	DiffListIterator_next(&iter);
+
+	while(DiffListIterator_isValid(&iter)) {
+		uint16_t val = DiffListIterator_getVal(&iter);
+		if (MCRegisterClass_contains(RC, val) && Reg ==  MCRegisterInfo_getSubReg(RI, val, SubIdx))
+			return val;
+
+		DiffListIterator_next(&iter);
+	}
+
+	return 0;
+}
+
+unsigned MCRegisterInfo_getSubReg(MCRegisterInfo *RI, unsigned Reg, unsigned Idx)
+{
+	DiffListIterator iter;
+	uint16_t *SRI = RI->SubRegIndices + RI->Desc[Reg].SubRegIndices;
+
+	DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SubRegs);
+	DiffListIterator_next(&iter);
+
+	while(DiffListIterator_isValid(&iter)) {
+		if (*SRI == Idx)
+			return DiffListIterator_getVal(&iter);
+		DiffListIterator_next(&iter);
+		++SRI;
+	}
+
+	return 0;
+}
+
+MCRegisterClass* MCRegisterInfo_getRegClass(MCRegisterInfo *RI, unsigned i)
+{
+	//assert(i < getNumRegClasses() && "Register Class ID out of range");
+	if (i >= RI->NumClasses)
+		return 0;
+	return &(RI->Classes[i]);
+}
+
+bool MCRegisterClass_contains(MCRegisterClass *c, unsigned Reg)
+{
+	unsigned InByte = Reg % 8;
+	unsigned Byte = Reg / 8;
+
+	if (Byte >= c->RegSetSize)
+		return false;
+
+	return (c->RegSet[Byte] & (1 << InByte)) != 0;
+}
diff --git a/MCRegisterInfo.h b/MCRegisterInfo.h
new file mode 100644
index 0000000..528f164
--- /dev/null
+++ b/MCRegisterInfo.h
@@ -0,0 +1,116 @@
+//=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes an abstract interface used to get information about a
+// target machines register file.  This information is used for a variety of
+// purposed, especially register allocation.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_LLVM_MC_MCREGISTERINFO_H
+#define CS_LLVM_MC_MCREGISTERINFO_H
+
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
+#include <stdint.h>
+#endif
+#include "include/platform.h"
+
+/// An unsigned integer type large enough to represent all physical registers,
+/// but not necessarily virtual registers.
+typedef uint16_t MCPhysReg;
+typedef MCPhysReg* iterator;
+
+typedef struct MCRegisterClass {
+	char *Name;
+	iterator RegsBegin;
+	uint8_t *RegSet;
+	uint16_t RegsSize;
+	uint16_t RegSetSize;
+	uint16_t ID;
+	uint16_t RegSize, Alignment; // Size & Alignment of register in bytes
+	int8_t CopyCost;
+	bool Allocatable;
+} MCRegisterClass;
+
+/// MCRegisterDesc - This record contains information about a particular
+/// register.  The SubRegs field is a zero terminated array of registers that
+/// are sub-registers of the specific register, e.g. AL, AH are sub-registers
+/// of AX. The SuperRegs field is a zero terminated array of registers that are
+/// super-registers of the specific register, e.g. RAX, EAX, are
+/// super-registers of AX.
+///
+typedef struct MCRegisterDesc {
+	uint32_t Name;      // Printable name for the reg (for debugging)
+	uint32_t SubRegs;   // Sub-register set, described above
+	uint32_t SuperRegs; // Super-register set, described above
+
+	// Offset into MCRI::SubRegIndices of a list of sub-register indices for each
+	// sub-register in SubRegs.
+	uint32_t SubRegIndices;
+
+	// RegUnits - Points to the list of register units. The low 4 bits holds the
+	// Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
+	uint32_t RegUnits;
+} MCRegisterDesc;
+
+/// MCRegisterInfo base class - We assume that the target defines a static
+/// array of MCRegisterDesc objects that represent all of the machine
+/// registers that the target has.  As such, we simply have to track a pointer
+/// to this array so that we can turn register number into a register
+/// descriptor.
+///
+/// Note this class is designed to be a base class of TargetRegisterInfo, which
+/// is the interface used by codegen. However, specific targets *should never*
+/// specialize this class. MCRegisterInfo should only contain getters to access
+/// TableGen generated physical register data. It must not be extended with
+/// virtual methods.
+///
+typedef struct MCRegisterInfo {
+	MCRegisterDesc *Desc;                 // Pointer to the descriptor array
+	unsigned NumRegs;                           // Number of entries in the array
+	unsigned RAReg;                             // Return address register
+	unsigned PCReg;                             // Program counter register
+	MCRegisterClass *Classes;             // Pointer to the regclass array
+	unsigned NumClasses;                        // Number of entries in the array
+	unsigned NumRegUnits;                       // Number of regunits.
+	uint16_t (*RegUnitRoots)[2];          // Pointer to regunit root table.
+	MCPhysReg *DiffLists;                 // Pointer to the difflists array
+	char *RegStrings;                     // Pointer to the string table.
+	uint16_t *SubRegIndices;              // Pointer to the subreg lookup
+	// array.
+	unsigned NumSubRegIndices;                  // Number of subreg indices.
+	uint16_t *RegEncodingTable;           // Pointer to array of register
+	// encodings.
+} MCRegisterInfo;
+
+void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI,
+		MCRegisterDesc *D, unsigned NR, unsigned RA,
+		unsigned PC,
+		MCRegisterClass *C, unsigned NC,
+		uint16_t (*RURoots)[2],
+		unsigned NRU,
+		MCPhysReg *DL,
+		char *Strings,
+		uint16_t *SubIndices,
+		unsigned NumIndices,
+		uint16_t *RET);
+
+
+unsigned MCRegisterInfo_getMatchingSuperReg(MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, MCRegisterClass *RC);
+
+unsigned MCRegisterInfo_getSubReg(MCRegisterInfo *RI, unsigned Reg, unsigned Idx);
+
+MCRegisterClass* MCRegisterInfo_getRegClass(MCRegisterInfo *RI, unsigned i);
+
+bool MCRegisterClass_contains(MCRegisterClass *c, unsigned Reg);
+
+#endif
diff --git a/METADATA b/METADATA
new file mode 100644
index 0000000..da76ca9
--- /dev/null
+++ b/METADATA
@@ -0,0 +1,20 @@
+name: "capstone"
+description:
+    "Capstone is a disassembly framework with the target of becoming the "
+    "ultimate disasm engine for binary analysis and reversing in the security "
+    "community. "
+    ""
+
+third_party {
+  url {
+    type: HOMEPAGE
+    value: "https://github.com/aquynh/capstone"
+  }
+  url {
+    type: GIT
+    value: "https://github.com/aquynh/capstone"
+  }
+  version: "3.0.5-rc3"
+  last_upgrade_date { year: 2017 month: 8 day: 25 }
+  license_type: NOTICE
+}
diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..f7167d9
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,488 @@
+# Capstone Disassembly Engine
+# By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014
+
+include config.mk
+include pkgconfig.mk	# package version
+include functions.mk
+
+# Verbose output?
+V ?= 0
+
+ifeq ($(PKG_EXTRA),)
+PKG_VERSION = $(PKG_MAJOR).$(PKG_MINOR)
+else
+PKG_VERSION = $(PKG_MAJOR).$(PKG_MINOR).$(PKG_EXTRA)
+endif
+
+ifeq ($(CROSS),)
+CC ?= cc
+AR ?= ar
+RANLIB ?= ranlib
+STRIP ?= strip
+else
+CC = $(CROSS)gcc
+AR = $(CROSS)ar
+RANLIB = $(CROSS)ranlib
+STRIP = $(CROSS)strip
+endif
+
+ifneq (,$(findstring yes,$(CAPSTONE_DIET)))
+CFLAGS ?= -Os
+CFLAGS += -DCAPSTONE_DIET
+else
+CFLAGS ?= -O3
+endif
+
+ifneq (,$(findstring yes,$(CAPSTONE_X86_ATT_DISABLE)))
+CFLAGS += -DCAPSTONE_X86_ATT_DISABLE
+endif
+
+CFLAGS += -fPIC -Wall -Iinclude
+
+ifeq ($(CAPSTONE_USE_SYS_DYN_MEM),yes)
+CFLAGS += -DCAPSTONE_USE_SYS_DYN_MEM
+endif
+
+ifeq ($(CAPSTONE_HAS_OSXKERNEL), yes)
+CFLAGS += -DCAPSTONE_HAS_OSXKERNEL
+SDKROOT ?= $(shell xcodebuild -version -sdk macosx Path)
+CFLAGS += -mmacosx-version-min=10.5 \
+		  -isysroot$(SDKROOT) \
+		  -I$(SDKROOT)/System/Library/Frameworks/Kernel.framework/Headers \
+		  -mkernel \
+		  -fno-builtin
+endif
+
+CFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch))
+LDFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch))
+
+PREFIX ?= /usr
+DESTDIR ?=
+ifndef BUILDDIR
+BLDIR = .
+OBJDIR = .
+else
+BLDIR = $(abspath $(BUILDDIR))
+OBJDIR = $(BLDIR)/obj
+endif
+INCDIR = $(DESTDIR)$(PREFIX)/include
+
+UNAME_S := $(shell uname -s)
+
+LIBDIRARCH ?= lib
+# Uncomment the below line to installs x86_64 libs to lib64/ directory.
+# Or better, pass 'LIBDIRARCH=lib64' to 'make install/uninstall' via 'make.sh'.
+#LIBDIRARCH ?= lib64
+LIBDIR = $(DESTDIR)$(PREFIX)/$(LIBDIRARCH)
+BINDIR = $(DESTDIR)$(PREFIX)/bin
+
+LIBDATADIR = $(LIBDIR)
+
+# Don't redefine $LIBDATADIR when global environment variable
+# USE_GENERIC_LIBDATADIR is set. This is used by the pkgsrc framework.
+
+ifndef USE_GENERIC_LIBDATADIR
+ifeq ($(UNAME_S), FreeBSD)
+LIBDATADIR = $(DESTDIR)$(PREFIX)/libdata
+endif
+ifeq ($(UNAME_S), DragonFly)
+LIBDATADIR = $(DESTDIR)$(PREFIX)/libdata
+endif
+endif
+
+INSTALL_BIN ?= install
+INSTALL_DATA ?= $(INSTALL_BIN) -m0644
+INSTALL_LIB ?= $(INSTALL_BIN) -m0755
+
+LIBNAME = capstone
+
+
+DEP_ARM =
+DEP_ARM += arch/ARM/ARMGenAsmWriter.inc
+DEP_ARM += arch/ARM/ARMGenDisassemblerTables.inc
+DEP_ARM += arch/ARM/ARMGenInstrInfo.inc
+DEP_ARM += arch/ARM/ARMGenRegisterInfo.inc
+DEP_ARM += arch/ARM/ARMGenSubtargetInfo.inc
+
+LIBOBJ_ARM =
+ifneq (,$(findstring arm,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_ARM
+	LIBOBJ_ARM += $(OBJDIR)/arch/ARM/ARMDisassembler.o
+	LIBOBJ_ARM += $(OBJDIR)/arch/ARM/ARMInstPrinter.o
+	LIBOBJ_ARM += $(OBJDIR)/arch/ARM/ARMMapping.o
+	LIBOBJ_ARM += $(OBJDIR)/arch/ARM/ARMModule.o
+endif
+
+DEP_ARM64 =
+DEP_ARM64 += arch/AArch64/AArch64GenAsmWriter.inc
+DEP_ARM64 += arch/AArch64/AArch64GenInstrInfo.inc
+DEP_ARM64 += arch/AArch64/AArch64GenSubtargetInfo.inc
+DEP_ARM64 += arch/AArch64/AArch64GenDisassemblerTables.inc
+DEP_ARM64 += arch/AArch64/AArch64GenRegisterInfo.inc
+
+LIBOBJ_ARM64 =
+ifneq (,$(findstring aarch64,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_ARM64
+	LIBOBJ_ARM64 += $(OBJDIR)/arch/AArch64/AArch64BaseInfo.o
+	LIBOBJ_ARM64 += $(OBJDIR)/arch/AArch64/AArch64Disassembler.o
+	LIBOBJ_ARM64 += $(OBJDIR)/arch/AArch64/AArch64InstPrinter.o
+	LIBOBJ_ARM64 += $(OBJDIR)/arch/AArch64/AArch64Mapping.o
+	LIBOBJ_ARM64 += $(OBJDIR)/arch/AArch64/AArch64Module.o
+endif
+
+
+DEP_MIPS =
+DEP_MIPS += arch/Mips/MipsGenAsmWriter.inc
+DEP_MIPS += arch/Mips/MipsGenDisassemblerTables.inc
+DEP_MIPS += arch/Mips/MipsGenInstrInfo.inc
+DEP_MIPS += arch/Mips/MipsGenRegisterInfo.inc
+DEP_MIPS += arch/Mips/MipsGenSubtargetInfo.inc
+
+LIBOBJ_MIPS =
+ifneq (,$(findstring mips,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_MIPS
+	LIBOBJ_MIPS += $(OBJDIR)/arch/Mips/MipsDisassembler.o
+	LIBOBJ_MIPS += $(OBJDIR)/arch/Mips/MipsInstPrinter.o
+	LIBOBJ_MIPS += $(OBJDIR)/arch/Mips/MipsMapping.o
+	LIBOBJ_MIPS += $(OBJDIR)/arch/Mips/MipsModule.o
+endif
+
+
+DEP_PPC =
+DEP_PPC += arch/PowerPC/PPCGenAsmWriter.inc
+DEP_PPC += arch/PowerPC/PPCGenInstrInfo.inc
+DEP_PPC += arch/PowerPC/PPCGenSubtargetInfo.inc
+DEP_PPC += arch/PowerPC/PPCGenDisassemblerTables.inc
+DEP_PPC += arch/PowerPC/PPCGenRegisterInfo.inc
+
+LIBOBJ_PPC =
+ifneq (,$(findstring powerpc,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_POWERPC
+	LIBOBJ_PPC += $(OBJDIR)/arch/PowerPC/PPCDisassembler.o
+	LIBOBJ_PPC += $(OBJDIR)/arch/PowerPC/PPCInstPrinter.o
+	LIBOBJ_PPC += $(OBJDIR)/arch/PowerPC/PPCMapping.o
+	LIBOBJ_PPC += $(OBJDIR)/arch/PowerPC/PPCModule.o
+endif
+
+
+DEP_SPARC =
+DEP_SPARC += arch/Sparc/SparcGenAsmWriter.inc
+DEP_SPARC += arch/Sparc/SparcGenInstrInfo.inc
+DEP_SPARC += arch/Sparc/SparcGenSubtargetInfo.inc
+DEP_SPARC += arch/Sparc/SparcGenDisassemblerTables.inc
+DEP_SPARC += arch/Sparc/SparcGenRegisterInfo.inc
+
+LIBOBJ_SPARC =
+ifneq (,$(findstring sparc,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_SPARC
+	LIBOBJ_SPARC += $(OBJDIR)/arch/Sparc/SparcDisassembler.o
+	LIBOBJ_SPARC += $(OBJDIR)/arch/Sparc/SparcInstPrinter.o
+	LIBOBJ_SPARC += $(OBJDIR)/arch/Sparc/SparcMapping.o
+	LIBOBJ_SPARC += $(OBJDIR)/arch/Sparc/SparcModule.o
+endif
+
+
+DEP_SYSZ =
+DEP_SYSZ += arch/SystemZ/SystemZGenAsmWriter.inc
+DEP_SYSZ += arch/SystemZ/SystemZGenInstrInfo.inc
+DEP_SYSZ += arch/SystemZ/SystemZGenSubtargetInfo.inc
+DEP_SYSZ += arch/SystemZ/SystemZGenDisassemblerTables.inc
+DEP_SYSZ += arch/SystemZ/SystemZGenRegisterInfo.inc
+
+LIBOBJ_SYSZ =
+ifneq (,$(findstring systemz,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_SYSZ
+	LIBOBJ_SYSZ += $(OBJDIR)/arch/SystemZ/SystemZDisassembler.o
+	LIBOBJ_SYSZ += $(OBJDIR)/arch/SystemZ/SystemZInstPrinter.o
+	LIBOBJ_SYSZ += $(OBJDIR)/arch/SystemZ/SystemZMapping.o
+	LIBOBJ_SYSZ += $(OBJDIR)/arch/SystemZ/SystemZModule.o
+	LIBOBJ_SYSZ += $(OBJDIR)/arch/SystemZ/SystemZMCTargetDesc.o
+endif
+
+
+# by default, we compile full X86 instruction sets
+X86_REDUCE =
+ifneq (,$(findstring yes,$(CAPSTONE_X86_REDUCE)))
+X86_REDUCE = _reduce
+CFLAGS += -DCAPSTONE_X86_REDUCE -Os
+endif
+
+DEP_X86 =
+DEP_X86 += arch/X86/X86GenAsmWriter$(X86_REDUCE).inc
+DEP_X86 += arch/X86/X86GenAsmWriter1$(X86_REDUCE).inc
+DEP_X86 += arch/X86/X86GenDisassemblerTables$(X86_REDUCE).inc
+DEP_X86 += arch/X86/X86GenInstrInfo$(X86_REDUCE).inc
+DEP_X86 += arch/X86/X86GenRegisterInfo.inc
+
+LIBOBJ_X86 =
+ifneq (,$(findstring x86,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_X86
+	LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86DisassemblerDecoder.o
+	LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Disassembler.o
+	LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86IntelInstPrinter.o
+# assembly syntax is irrelevant in Diet mode, when this info is suppressed
+ifeq (,$(findstring yes,$(CAPSTONE_DIET)))
+ifeq (,$(findstring yes,$(CAPSTONE_X86_ATT_DISABLE)))
+	LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86ATTInstPrinter.o
+endif
+endif
+	LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Mapping.o
+	LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Module.o
+endif
+
+
+DEP_XCORE =
+DEP_XCORE += arch/XCore/XCoreGenAsmWriter.inc
+DEP_XCORE += arch/XCore/XCoreGenInstrInfo.inc
+DEP_XCORE += arch/XCore/XCoreGenDisassemblerTables.inc
+DEP_XCORE += arch/XCore/XCoreGenRegisterInfo.inc
+
+LIBOBJ_XCORE =
+ifneq (,$(findstring xcore,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_XCORE
+	LIBOBJ_XCORE += $(OBJDIR)/arch/XCore/XCoreDisassembler.o
+	LIBOBJ_XCORE += $(OBJDIR)/arch/XCore/XCoreInstPrinter.o
+	LIBOBJ_XCORE += $(OBJDIR)/arch/XCore/XCoreMapping.o
+	LIBOBJ_XCORE += $(OBJDIR)/arch/XCore/XCoreModule.o
+endif
+
+
+LIBOBJ =
+LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o
+LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_ARM64) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) $(LIBOBJ_X86) $(LIBOBJ_XCORE)
+LIBOBJ += $(OBJDIR)/MCInst.o
+
+
+PKGCFGDIR ?= $(LIBDATADIR)/pkgconfig
+API_MAJOR=$(shell echo `grep -e CS_API_MAJOR include/capstone.h | grep -v = | awk '{print $$3}'` | awk '{print $$1}')
+VERSION_EXT =
+
+IS_APPLE := $(shell $(CC) -dM -E - < /dev/null | grep -cm 1 -e __apple_build_version__ -e __APPLE_CC__)
+ifeq ($(IS_APPLE),1)
+EXT = dylib
+VERSION_EXT = $(API_MAJOR).$(EXT)
+$(LIBNAME)_LDFLAGS += -dynamiclib -install_name lib$(LIBNAME).$(VERSION_EXT) -current_version $(PKG_MAJOR).$(PKG_MINOR).$(PKG_EXTRA) -compatibility_version $(PKG_MAJOR).$(PKG_MINOR)
+AR_EXT = a
+# Homebrew wants to make sure its formula does not disable FORTIFY_SOURCE
+# However, this is not really necessary because 'CAPSTONE_USE_SYS_DYN_MEM=yes' by default
+ifneq ($(HOMEBREW_CAPSTONE),1)
+ifneq ($(CAPSTONE_USE_SYS_DYN_MEM),yes)
+# remove string check because OSX kernel complains about missing symbols
+CFLAGS += -D_FORTIFY_SOURCE=0
+endif
+endif
+else
+$(LIBNAME)_LDFLAGS += -shared
+# Cygwin?
+IS_CYGWIN := $(shell $(CC) -dumpmachine | grep -i cygwin | wc -l)
+ifeq ($(IS_CYGWIN),1)
+EXT = dll
+AR_EXT = lib
+# Cygwin doesn't like -fPIC
+CFLAGS := $(CFLAGS:-fPIC=)
+# On Windows we need the shared library to be executable
+else
+# mingw?
+IS_MINGW := $(shell $(CC) --version | grep -i mingw | wc -l)
+ifeq ($(IS_MINGW),1)
+EXT = dll
+AR_EXT = lib
+# mingw doesn't like -fPIC either
+CFLAGS := $(CFLAGS:-fPIC=)
+# On Windows we need the shared library to be executable
+else
+# Linux, *BSD
+EXT = so
+VERSION_EXT = $(EXT).$(API_MAJOR)
+AR_EXT = a
+$(LIBNAME)_LDFLAGS += -Wl,-soname,lib$(LIBNAME).$(VERSION_EXT)
+endif
+endif
+endif
+
+ifeq ($(CAPSTONE_SHARED),yes)
+ifeq ($(IS_MINGW),1)
+LIBRARY = $(BLDIR)/$(LIBNAME).$(EXT)
+else ifeq ($(IS_CYGWIN),1)
+LIBRARY = $(BLDIR)/$(LIBNAME).$(EXT)
+else	# *nix
+LIBRARY = $(BLDIR)/lib$(LIBNAME).$(EXT)
+CFLAGS += -fvisibility=hidden
+endif
+endif
+
+ifeq ($(CAPSTONE_STATIC),yes)
+ifeq ($(IS_MINGW),1)
+ARCHIVE = $(BLDIR)/$(LIBNAME).$(AR_EXT)
+else ifeq ($(IS_CYGWIN),1)
+ARCHIVE = $(BLDIR)/$(LIBNAME).$(AR_EXT)
+else
+ARCHIVE = $(BLDIR)/lib$(LIBNAME).$(AR_EXT)
+endif
+endif
+
+PKGCFGF = $(BLDIR)/$(LIBNAME).pc
+
+.PHONY: all clean install uninstall dist
+
+all: $(LIBRARY) $(ARCHIVE) $(PKGCFGF)
+ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
+	@V=$(V) CC=$(CC) $(MAKE) -C cstool
+ifndef BUILDDIR
+	cd tests && $(MAKE)
+else
+	cd tests && $(MAKE) BUILDDIR=$(BLDIR)
+endif
+	$(call install-library,$(BLDIR)/tests/)
+endif
+
+ifeq ($(CAPSTONE_SHARED),yes)
+$(LIBRARY): $(LIBOBJ)
+ifeq ($(V),0)
+	$(call log,LINK,$(@:$(BLDIR)/%=%))
+	@$(create-library)
+else
+	$(create-library)
+endif
+endif
+
+$(LIBOBJ): *.h include/*.h config.mk
+
+$(LIBOBJ_ARM): $(DEP_ARM)
+$(LIBOBJ_ARM64): $(DEP_ARM64)
+$(LIBOBJ_MIPS): $(DEP_MIPS)
+$(LIBOBJ_PPC): $(DEP_PPC)
+$(LIBOBJ_SPARC): $(DEP_SPARC)
+$(LIBOBJ_SYSZ): $(DEP_SYSZ)
+$(LIBOBJ_X86): $(DEP_X86)
+$(LIBOBJ_XCORE): $(DEP_XCORE)
+
+ifeq ($(CAPSTONE_STATIC),yes)
+$(ARCHIVE): $(LIBOBJ)
+	@rm -f $(ARCHIVE)
+ifeq ($(V),0)
+	$(call log,AR,$(@:$(BLDIR)/%=%))
+	@$(create-archive)
+else
+	$(create-archive)
+endif
+endif
+
+$(PKGCFGF):
+ifeq ($(V),0)
+	$(call log,GEN,$(@:$(BLDIR)/%=%))
+	@$(generate-pkgcfg)
+else
+	$(generate-pkgcfg)
+endif
+
+install: $(PKGCFGF) $(ARCHIVE) $(LIBRARY)
+	mkdir -p $(LIBDIR)
+	$(call install-library,$(LIBDIR))
+ifeq ($(CAPSTONE_STATIC),yes)
+	$(INSTALL_DATA) $(ARCHIVE) $(LIBDIR)
+endif
+	mkdir -p $(INCDIR)/$(LIBNAME)
+	$(INSTALL_DATA) include/*.h $(INCDIR)/$(LIBNAME)
+	mkdir -p $(PKGCFGDIR)
+	$(INSTALL_DATA) $(PKGCFGF) $(PKGCFGDIR)/
+	mkdir -p $(BINDIR)
+	$(INSTALL_LIB) cstool/cstool $(BINDIR)
+
+uninstall:
+	rm -rf $(INCDIR)/$(LIBNAME)
+	rm -f $(LIBDIR)/lib$(LIBNAME).*
+	rm -f $(PKGCFGDIR)/$(LIBNAME).pc
+	rm -f $(BINDIR)/cstool
+
+clean:
+	rm -f $(LIBOBJ)
+	rm -f $(BLDIR)/lib$(LIBNAME).* $(BLDIR)/$(LIBNAME).pc
+	rm -f $(PKGCFGF)
+	$(MAKE) -C cstool clean
+
+ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
+	cd tests && $(MAKE) clean
+	rm -f $(BLDIR)/tests/lib$(LIBNAME).$(EXT)
+endif
+
+ifdef BUILDDIR
+	rm -rf $(BUILDDIR)
+endif
+
+ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
+	cd bindings/python && $(MAKE) clean
+	cd bindings/java && $(MAKE) clean
+	cd bindings/ocaml && $(MAKE) clean
+endif
+
+
+TAG ?= HEAD
+ifeq ($(TAG), HEAD)
+DIST_VERSION = latest
+else
+DIST_VERSION = $(TAG)
+endif
+
+dist:
+	git archive --format=tar.gz --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).tgz
+	git archive --format=zip --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).zip
+
+
+TESTS = test_basic test_detail test_arm test_arm64 test_mips test_ppc test_sparc
+TESTS += test_systemz test_x86 test_xcore test_iter
+TESTS += test_basic.static test_detail.static test_arm.static test_arm64.static
+TESTS += test_mips.static test_ppc.static test_sparc.static
+TESTS += test_systemz.static test_x86.static test_xcore.static
+TESTS += test_skipdata test_skipdata.static test_iter.static
+check:
+	@for t in $(TESTS); do \
+		echo Check $$t ... ; \
+		LD_LIBRARY_PATH=./tests ./tests/$$t > /dev/null && echo OK || echo FAILED; \
+	done
+
+$(OBJDIR)/%.o: %.c
+	@mkdir -p $(@D)
+ifeq ($(V),0)
+	$(call log,CC,$(@:$(OBJDIR)/%=%))
+	@$(compile)
+else
+	$(compile)
+endif
+
+
+ifeq ($(CAPSTONE_SHARED),yes)
+define install-library
+	$(INSTALL_LIB) $(LIBRARY) $1
+	$(if $(VERSION_EXT),
+		cd $1 && \
+		mv lib$(LIBNAME).$(EXT) lib$(LIBNAME).$(VERSION_EXT) && \
+		ln -s lib$(LIBNAME).$(VERSION_EXT) lib$(LIBNAME).$(EXT))
+endef
+else
+define install-library
+endef
+endif
+
+
+define create-archive
+	$(AR) q $(ARCHIVE) $(LIBOBJ)
+	$(RANLIB) $(ARCHIVE)
+endef
+
+
+define create-library
+	$(CC) $(LDFLAGS) $($(LIBNAME)_LDFLAGS) $(LIBOBJ) -o $(LIBRARY)
+endef
+
+
+define generate-pkgcfg
+	echo 'Name: capstone' > $(PKGCFGF)
+	echo 'Description: Capstone disassembly engine' >> $(PKGCFGF)
+	echo 'Version: $(PKG_VERSION)' >> $(PKGCFGF)
+	echo 'libdir=$(LIBDIR)' >> $(PKGCFGF)
+	echo 'includedir=$(INCDIR)/capstone' >> $(PKGCFGF)
+	echo 'archive=$${libdir}/libcapstone.a' >> $(PKGCFGF)
+	echo 'Libs: -L$${libdir} -lcapstone' >> $(PKGCFGF)
+	echo 'Cflags: -I$${includedir}' >> $(PKGCFGF)
+endef
diff --git a/MathExtras.h b/MathExtras.h
new file mode 100644
index 0000000..db98a2f
--- /dev/null
+++ b/MathExtras.h
@@ -0,0 +1,441 @@
+//===-- llvm/Support/MathExtras.h - Useful math functions -------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains some functions that are useful for math stuff.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_LLVM_SUPPORT_MATHEXTRAS_H
+#define CS_LLVM_SUPPORT_MATHEXTRAS_H
+
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
+#include <stdint.h>
+#endif
+
+#ifdef _MSC_VER
+# include <intrin.h>
+#endif
+
+#ifndef __cplusplus
+#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)
+#define inline /* inline */
+#endif
+#endif
+
+// NOTE: The following support functions use the _32/_64 extensions instead of
+// type overloading so that signed and unsigned integers can be used without
+// ambiguity.
+
+/// Hi_32 - This function returns the high 32 bits of a 64 bit value.
+static inline uint32_t Hi_32(uint64_t Value) {
+	return (uint32_t)(Value >> 32);
+}
+
+/// Lo_32 - This function returns the low 32 bits of a 64 bit value.
+static inline uint32_t Lo_32(uint64_t Value) {
+	return (uint32_t)(Value);
+}
+
+/// isUIntN - Checks if an unsigned integer fits into the given (dynamic)
+/// bit width.
+static inline bool isUIntN(unsigned N, uint64_t x) {
+	return x == (x & (~0ULL >> (64 - N)));
+}
+
+/// isIntN - Checks if an signed integer fits into the given (dynamic)
+/// bit width.
+//static inline bool isIntN(unsigned N, int64_t x) {
+//  return N >= 64 || (-(INT64_C(1)<<(N-1)) <= x && x < (INT64_C(1)<<(N-1)));
+//}
+
+/// isMask_32 - This function returns true if the argument is a sequence of ones
+/// starting at the least significant bit with the remainder zero (32 bit
+/// version).   Ex. isMask_32(0x0000FFFFU) == true.
+static inline bool isMask_32(uint32_t Value) {
+	return Value && ((Value + 1) & Value) == 0;
+}
+
+/// isMask_64 - This function returns true if the argument is a sequence of ones
+/// starting at the least significant bit with the remainder zero (64 bit
+/// version).
+static inline bool isMask_64(uint64_t Value) {
+	return Value && ((Value + 1) & Value) == 0;
+}
+
+/// isShiftedMask_32 - This function returns true if the argument contains a
+/// sequence of ones with the remainder zero (32 bit version.)
+/// Ex. isShiftedMask_32(0x0000FF00U) == true.
+static inline bool isShiftedMask_32(uint32_t Value) {
+	return isMask_32((Value - 1) | Value);
+}
+
+/// isShiftedMask_64 - This function returns true if the argument contains a
+/// sequence of ones with the remainder zero (64 bit version.)
+static inline bool isShiftedMask_64(uint64_t Value) {
+	return isMask_64((Value - 1) | Value);
+}
+
+/// isPowerOf2_32 - This function returns true if the argument is a power of
+/// two > 0. Ex. isPowerOf2_32(0x00100000U) == true (32 bit edition.)
+static inline bool isPowerOf2_32(uint32_t Value) {
+	return Value && !(Value & (Value - 1));
+}
+
+/// CountLeadingZeros_32 - this function performs the platform optimal form of
+/// counting the number of zeros from the most significant bit to the first one
+/// bit.  Ex. CountLeadingZeros_32(0x00F000FF) == 8.
+/// Returns 32 if the word is zero.
+static inline unsigned CountLeadingZeros_32(uint32_t Value) {
+	unsigned Count; // result
+#if __GNUC__ >= 4
+	// PowerPC is defined for __builtin_clz(0)
+#if !defined(__ppc__) && !defined(__ppc64__)
+	if (!Value) return 32;
+#endif
+	Count = __builtin_clz(Value);
+#else
+	unsigned Shift;
+	if (!Value) return 32;
+	Count = 0;
+	// bisection method for count leading zeros
+	for (Shift = 32 >> 1; Shift; Shift >>= 1) {
+		uint32_t Tmp = Value >> Shift;
+		if (Tmp) {
+			Value = Tmp;
+		} else {
+			Count |= Shift;
+		}
+	}
+#endif
+	return Count;
+}
+
+/// CountLeadingOnes_32 - this function performs the operation of
+/// counting the number of ones from the most significant bit to the first zero
+/// bit.  Ex. CountLeadingOnes_32(0xFF0FFF00) == 8.
+/// Returns 32 if the word is all ones.
+static inline unsigned CountLeadingOnes_32(uint32_t Value) {
+	return CountLeadingZeros_32(~Value);
+}
+
+/// CountLeadingZeros_64 - This function performs the platform optimal form
+/// of counting the number of zeros from the most significant bit to the first
+/// one bit (64 bit edition.)
+/// Returns 64 if the word is zero.
+static inline unsigned CountLeadingZeros_64(uint64_t Value) {
+	unsigned Count; // result
+#if __GNUC__ >= 4
+	// PowerPC is defined for __builtin_clzll(0)
+#if !defined(__ppc__) && !defined(__ppc64__)
+	if (!Value) return 64;
+#endif
+	Count = __builtin_clzll(Value);
+#else
+#ifndef _MSC_VER
+	unsigned Shift;
+	if (sizeof(long) == sizeof(int64_t))
+	{
+		if (!Value) return 64;
+		Count = 0;
+		// bisection method for count leading zeros
+		for (Shift = 64 >> 1; Shift; Shift >>= 1) {
+			uint64_t Tmp = Value >> Shift;
+			if (Tmp) {
+				Value = Tmp;
+			} else {
+				Count |= Shift;
+			}
+		}
+	}
+	else
+#endif
+	{
+		// get hi portion
+		uint32_t Hi = Hi_32(Value);
+
+		// if some bits in hi portion
+		if (Hi) {
+			// leading zeros in hi portion plus all bits in lo portion
+			Count = CountLeadingZeros_32(Hi);
+		} else {
+			// get lo portion
+			uint32_t Lo = Lo_32(Value);
+			// same as 32 bit value
+			Count = CountLeadingZeros_32(Lo)+32;
+		}
+	}
+#endif
+	return Count;
+}
+
+/// CountLeadingOnes_64 - This function performs the operation
+/// of counting the number of ones from the most significant bit to the first
+/// zero bit (64 bit edition.)
+/// Returns 64 if the word is all ones.
+static inline unsigned CountLeadingOnes_64(uint64_t Value) {
+	return CountLeadingZeros_64(~Value);
+}
+
+/// CountTrailingZeros_32 - this function performs the platform optimal form of
+/// counting the number of zeros from the least significant bit to the first one
+/// bit.  Ex. CountTrailingZeros_32(0xFF00FF00) == 8.
+/// Returns 32 if the word is zero.
+static inline unsigned CountTrailingZeros_32(uint32_t Value) {
+#if __GNUC__ >= 4
+	return Value ? __builtin_ctz(Value) : 32;
+#else
+	static const unsigned Mod37BitPosition[] = {
+		32, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13,
+		4, 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9,
+		5, 20, 8, 19, 18
+	};
+	// Replace "-Value" by "1+~Value" in the following commented code to avoid 
+	// MSVC warning C4146
+	//    return Mod37BitPosition[(-Value & Value) % 37];
+	return Mod37BitPosition[((1 + ~Value) & Value) % 37];
+#endif
+}
+
+/// CountTrailingOnes_32 - this function performs the operation of
+/// counting the number of ones from the least significant bit to the first zero
+/// bit.  Ex. CountTrailingOnes_32(0x00FF00FF) == 8.
+/// Returns 32 if the word is all ones.
+static inline unsigned CountTrailingOnes_32(uint32_t Value) {
+	return CountTrailingZeros_32(~Value);
+}
+
+/// CountTrailingZeros_64 - This function performs the platform optimal form
+/// of counting the number of zeros from the least significant bit to the first
+/// one bit (64 bit edition.)
+/// Returns 64 if the word is zero.
+static inline unsigned CountTrailingZeros_64(uint64_t Value) {
+#if __GNUC__ >= 4
+	return Value ? __builtin_ctzll(Value) : 64;
+#else
+	static const unsigned Mod67Position[] = {
+		64, 0, 1, 39, 2, 15, 40, 23, 3, 12, 16, 59, 41, 19, 24, 54,
+		4, 64, 13, 10, 17, 62, 60, 28, 42, 30, 20, 51, 25, 44, 55,
+		47, 5, 32, 65, 38, 14, 22, 11, 58, 18, 53, 63, 9, 61, 27,
+		29, 50, 43, 46, 31, 37, 21, 57, 52, 8, 26, 49, 45, 36, 56,
+		7, 48, 35, 6, 34, 33, 0
+	};
+	// Replace "-Value" by "1+~Value" in the following commented code to avoid 
+	// MSVC warning C4146
+	//    return Mod67Position[(-Value & Value) % 67];
+	return Mod67Position[((1 + ~Value) & Value) % 67];
+#endif
+}
+
+/// CountTrailingOnes_64 - This function performs the operation
+/// of counting the number of ones from the least significant bit to the first
+/// zero bit (64 bit edition.)
+/// Returns 64 if the word is all ones.
+static inline unsigned CountTrailingOnes_64(uint64_t Value) {
+	return CountTrailingZeros_64(~Value);
+}
+
+/// CountPopulation_32 - this function counts the number of set bits in a value.
+/// Ex. CountPopulation(0xF000F000) = 8
+/// Returns 0 if the word is zero.
+static inline unsigned CountPopulation_32(uint32_t Value) {
+#if __GNUC__ >= 4
+	return __builtin_popcount(Value);
+#else
+	uint32_t v = Value - ((Value >> 1) & 0x55555555);
+	v = (v & 0x33333333) + ((v >> 2) & 0x33333333);
+	return (((v + (v >> 4)) & 0xF0F0F0F) * 0x1010101) >> 24;
+#endif
+}
+
+/// CountPopulation_64 - this function counts the number of set bits in a value,
+/// (64 bit edition.)
+static inline unsigned CountPopulation_64(uint64_t Value) {
+#if __GNUC__ >= 4
+	return __builtin_popcountll(Value);
+#else
+	uint64_t v = Value - ((Value >> 1) & 0x5555555555555555ULL);
+	v = (v & 0x3333333333333333ULL) + ((v >> 2) & 0x3333333333333333ULL);
+	v = (v + (v >> 4)) & 0x0F0F0F0F0F0F0F0FULL;
+	return (uint64_t)((v * 0x0101010101010101ULL) >> 56);
+#endif
+}
+
+/// Log2_32 - This function returns the floor log base 2 of the specified value,
+/// -1 if the value is zero. (32 bit edition.)
+/// Ex. Log2_32(32) == 5, Log2_32(1) == 0, Log2_32(0) == -1, Log2_32(6) == 2
+static inline unsigned Log2_32(uint32_t Value) {
+	return 31 - CountLeadingZeros_32(Value);
+}
+
+/// Log2_64 - This function returns the floor log base 2 of the specified value,
+/// -1 if the value is zero. (64 bit edition.)
+static inline unsigned Log2_64(uint64_t Value) {
+	return 63 - CountLeadingZeros_64(Value);
+}
+
+/// Log2_32_Ceil - This function returns the ceil log base 2 of the specified
+/// value, 32 if the value is zero. (32 bit edition).
+/// Ex. Log2_32_Ceil(32) == 5, Log2_32_Ceil(1) == 0, Log2_32_Ceil(6) == 3
+static inline unsigned Log2_32_Ceil(uint32_t Value) {
+	return 32-CountLeadingZeros_32(Value-1);
+}
+
+/// Log2_64_Ceil - This function returns the ceil log base 2 of the specified
+/// value, 64 if the value is zero. (64 bit edition.)
+static inline unsigned Log2_64_Ceil(uint64_t Value) {
+	return 64-CountLeadingZeros_64(Value-1);
+}
+
+/// GreatestCommonDivisor64 - Return the greatest common divisor of the two
+/// values using Euclid's algorithm.
+static inline uint64_t GreatestCommonDivisor64(uint64_t A, uint64_t B) {
+	while (B) {
+		uint64_t T = B;
+		B = A % B;
+		A = T;
+	}
+	return A;
+}
+
+/// BitsToDouble - This function takes a 64-bit integer and returns the bit
+/// equivalent double.
+static inline double BitsToDouble(uint64_t Bits) {
+	union {
+		uint64_t L;
+		double D;
+	} T;
+	T.L = Bits;
+	return T.D;
+}
+
+/// BitsToFloat - This function takes a 32-bit integer and returns the bit
+/// equivalent float.
+static inline float BitsToFloat(uint32_t Bits) {
+	union {
+		uint32_t I;
+		float F;
+	} T;
+	T.I = Bits;
+	return T.F;
+}
+
+/// DoubleToBits - This function takes a double and returns the bit
+/// equivalent 64-bit integer.  Note that copying doubles around
+/// changes the bits of NaNs on some hosts, notably x86, so this
+/// routine cannot be used if these bits are needed.
+static inline uint64_t DoubleToBits(double Double) {
+	union {
+		uint64_t L;
+		double D;
+	} T;
+	T.D = Double;
+	return T.L;
+}
+
+/// FloatToBits - This function takes a float and returns the bit
+/// equivalent 32-bit integer.  Note that copying floats around
+/// changes the bits of NaNs on some hosts, notably x86, so this
+/// routine cannot be used if these bits are needed.
+static inline uint32_t FloatToBits(float Float) {
+	union {
+		uint32_t I;
+		float F;
+	} T;
+	T.F = Float;
+	return T.I;
+}
+
+/// MinAlign - A and B are either alignments or offsets.  Return the minimum
+/// alignment that may be assumed after adding the two together.
+static inline uint64_t MinAlign(uint64_t A, uint64_t B) {
+	// The largest power of 2 that divides both A and B.
+	//
+	// Replace "-Value" by "1+~Value" in the following commented code to avoid 
+	// MSVC warning C4146
+	//    return (A | B) & -(A | B);
+	return (A | B) & (1 + ~(A | B));
+}
+
+/// NextPowerOf2 - Returns the next power of two (in 64-bits)
+/// that is strictly greater than A.  Returns zero on overflow.
+static inline uint64_t NextPowerOf2(uint64_t A) {
+	A |= (A >> 1);
+	A |= (A >> 2);
+	A |= (A >> 4);
+	A |= (A >> 8);
+	A |= (A >> 16);
+	A |= (A >> 32);
+	return A + 1;
+}
+
+/// Returns the next integer (mod 2**64) that is greater than or equal to
+/// \p Value and is a multiple of \p Align. \p Align must be non-zero.
+///
+/// Examples:
+/// \code
+///   RoundUpToAlignment(5, 8) = 8
+///   RoundUpToAlignment(17, 8) = 24
+///   RoundUpToAlignment(~0LL, 8) = 0
+/// \endcode
+static inline uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align) {
+	return ((Value + Align - 1) / Align) * Align;
+}
+
+/// Returns the offset to the next integer (mod 2**64) that is greater than
+/// or equal to \p Value and is a multiple of \p Align. \p Align must be
+/// non-zero.
+static inline uint64_t OffsetToAlignment(uint64_t Value, uint64_t Align) {
+	return RoundUpToAlignment(Value, Align) - Value;
+}
+
+/// abs64 - absolute value of a 64-bit int.  Not all environments support
+/// "abs" on whatever their name for the 64-bit int type is.  The absolute
+/// value of the largest negative number is undefined, as with "abs".
+static inline int64_t abs64(int64_t x) {
+	return (x < 0) ? -x : x;
+}
+
+/// \brief Sign extend number in the bottom B bits of X to a 32-bit int.
+/// Requires 0 < B <= 32.
+static inline int32_t SignExtend32(uint32_t X, unsigned B) {
+	return (int32_t)(X << (32 - B)) >> (32 - B);
+}
+
+/// \brief Sign extend number in the bottom B bits of X to a 64-bit int.
+/// Requires 0 < B <= 64.
+static inline int64_t SignExtend64(uint64_t X, unsigned B) {
+	return (int64_t)(X << (64 - B)) >> (64 - B);
+}
+
+/// \brief Count number of 0's from the most significant bit to the least
+///   stopping at the first 1.
+///
+/// Only unsigned integral types are allowed.
+///
+/// \param ZB the behavior on an input of 0. Only ZB_Width and ZB_Undefined are
+///   valid arguments.
+static inline unsigned int countLeadingZeros(int x)
+{
+	unsigned count = 0;
+	int i;
+	const unsigned bits = sizeof(x) * 8;
+
+	for (i = bits; --i; ) {
+		if (x < 0) break;
+		count++;
+		x <<= 1;
+	}
+
+	return count;
+}
+
+#endif
diff --git a/README b/README
new file mode 100644
index 0000000..d968236
--- /dev/null
+++ b/README
@@ -0,0 +1,55 @@
+Capstone is a disassembly framework with the target of becoming the ultimate
+disasm engine for binary analysis and reversing in the security community.
+
+Created by Nguyen Anh Quynh, then developed and maintained by a small community,
+Capstone offers some unparalleled features:
+
+- Support multiple hardware architectures: ARM, ARM64 (ARMv8), Mips, PPC, Sparc,
+  SystemZ, XCore and X86 (including X86_64).
+
+- Having clean/simple/lightweight/intuitive architecture-neutral API.
+
+- Provide details on disassembled instruction (called “decomposer” by others).
+
+- Provide semantics of the disassembled instruction, such as list of implicit
+  registers read & written.
+
+- Implemented in pure C language, with lightweight bindings for Visual Basic, PHP,
+  PowerShell, Emacs, Haskell, Perl, Python, Ruby, C#, NodeJS, Java, GO, C++, OCaml,
+  Lua, Rust, Delphi, Free Pascal & Vala ready either in main code, or provided
+  externally by the community).
+
+- Native support for all popular platforms: Windows, Mac OSX, iOS, Android,
+  Linux, *BSD, Solaris, etc.
+
+- Thread-safe by design.
+
+- Special support for embedding into firmware or OS kernel.
+
+- High performance & suitable for malware analysis (capable of handling various
+  X86 malware tricks).
+
+- Distributed under the open source BSD license.
+
+Further information is available at http://www.capstone-engine.org
+
+
+[Compile]
+
+See COMPILE.TXT file for how to compile and install Capstone.
+
+
+[Documentation]
+
+See docs/README for how to customize & program your own tools with Capstone.
+
+
+[Hack]
+
+See HACK.TXT file for the structure of the source code.
+
+
+[License]
+
+This project is released under the BSD license. If you redistribute the binary
+or source code of Capstone, please attach file LICENSE.TXT with your products.
diff --git a/RELEASE_NOTES b/RELEASE_NOTES
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/RELEASE_NOTES
diff --git a/SStream.c b/SStream.c
new file mode 100644
index 0000000..2228e99
--- /dev/null
+++ b/SStream.c
@@ -0,0 +1,169 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
+#include <stdint.h>
+#endif
+#include <stdarg.h>
+#if defined(CAPSTONE_HAS_OSXKERNEL)
+#include <libkern/libkern.h>
+#else
+#include <stdio.h>
+#endif
+#include <string.h>
+
+#include <platform.h>
+
+#include "SStream.h"
+#include "cs_priv.h"
+#include "utils.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable: 4996) // disable MSVC's warning on strcpy()
+#endif
+
+void SStream_Init(SStream *ss)
+{
+	ss->index = 0;
+	ss->buffer[0] = '\0';
+}
+
+void SStream_concat0(SStream *ss, char *s)
+{
+#ifndef CAPSTONE_DIET
+	unsigned int len = (unsigned int) strlen(s);
+
+	memcpy(ss->buffer + ss->index, s, len);
+	ss->index += len;
+	ss->buffer[ss->index] = '\0';
+#endif
+}
+
+void SStream_concat(SStream *ss, const char *fmt, ...)
+{
+#ifndef CAPSTONE_DIET
+	va_list ap;
+	int ret;
+
+	va_start(ap, fmt);
+	ret = cs_vsnprintf(ss->buffer + ss->index, sizeof(ss->buffer) - (ss->index + 1), fmt, ap);
+	va_end(ap);
+	ss->index += ret;
+#endif
+}
+
+// print number with prefix #
+void printInt64Bang(SStream *O, int64_t val)
+{
+	if (val >= 0) {
+		if (val > HEX_THRESHOLD)
+			SStream_concat(O, "#0x%"PRIx64, val);
+		else
+			SStream_concat(O, "#%"PRIu64, val);
+	} else {
+		if (val <- HEX_THRESHOLD)
+			SStream_concat(O, "#-0x%"PRIx64, -val);
+		else
+			SStream_concat(O, "#-%"PRIu64, -val);
+	}
+}
+
+void printUInt64Bang(SStream *O, uint64_t val)
+{
+	if (val > HEX_THRESHOLD)
+		SStream_concat(O, "#0x%"PRIx64, val);
+	else
+		SStream_concat(O, "#%"PRIu64, val);
+}
+
+// print number
+void printInt64(SStream *O, int64_t val)
+{
+	if (val >= 0) {
+		if (val > HEX_THRESHOLD)
+			SStream_concat(O, "0x%"PRIx64, val);
+		else
+			SStream_concat(O, "%"PRIu64, val);
+	} else {
+		if (val <- HEX_THRESHOLD)
+			SStream_concat(O, "-0x%"PRIx64, -val);
+		else
+			SStream_concat(O, "-%"PRIu64, -val);
+	}
+}
+
+// print number in decimal mode
+void printInt32BangDec(SStream *O, int32_t val)
+{
+	if (val >= 0)
+		SStream_concat(O, "#%u", val);
+	else
+		SStream_concat(O, "#-%u", -val);
+}
+
+void printInt32Bang(SStream *O, int32_t val)
+{
+	if (val >= 0) {
+		if (val > HEX_THRESHOLD)
+			SStream_concat(O, "#0x%x", val);
+		else
+			SStream_concat(O, "#%u", val);
+	} else {
+		if (val <- HEX_THRESHOLD)
+			SStream_concat(O, "#-0x%x", -val);
+		else
+			SStream_concat(O, "#-%u", -val);
+	}
+}
+
+void printInt32(SStream *O, int32_t val)
+{
+	if (val >= 0) {
+		if (val > HEX_THRESHOLD)
+			SStream_concat(O, "0x%x", val);
+		else
+			SStream_concat(O, "%u", val);
+	} else {
+		if (val <- HEX_THRESHOLD)
+			SStream_concat(O, "-0x%x", -val);
+		else
+			SStream_concat(O, "-%u", -val);
+	}
+}
+
+void printUInt32Bang(SStream *O, uint32_t val)
+{
+	if (val > HEX_THRESHOLD)
+		SStream_concat(O, "#0x%x", val);
+	else
+		SStream_concat(O, "#%u", val);
+}
+
+void printUInt32(SStream *O, uint32_t val)
+{
+	if (val > HEX_THRESHOLD)
+		SStream_concat(O, "0x%x", val);
+	else
+		SStream_concat(O, "%u", val);
+}
+
+/*
+   int main()
+   {
+   SStream ss;
+   int64_t i;
+
+   SStream_Init(&ss);
+
+   SStream_concat(&ss, "hello ");
+   SStream_concat(&ss, "%d - 0x%x", 200, 16);
+
+   i = 123;
+   SStream_concat(&ss, " + %ld", i);
+   SStream_concat(&ss, "%s", "haaaaa");
+
+   printf("%s\n", ss.buffer);
+
+   return 0;
+   }
+ */
diff --git a/SStream.h b/SStream.h
new file mode 100644
index 0000000..dad0e7f
--- /dev/null
+++ b/SStream.h
@@ -0,0 +1,35 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_SSTREAM_H_
+#define CS_SSTREAM_H_
+
+typedef struct SStream {
+	char buffer[512];
+	int index;
+} SStream;
+
+void SStream_Init(SStream *ss);
+
+void SStream_concat(SStream *ss, const char *fmt, ...);
+
+void SStream_concat0(SStream *ss, char *s);
+
+void printInt64Bang(SStream *O, int64_t val);
+
+void printUInt64Bang(SStream *O, uint64_t val);
+
+void printInt64(SStream *O, int64_t val);
+
+void printInt32Bang(SStream *O, int32_t val);
+
+void printInt32(SStream *O, int32_t val);
+
+void printUInt32Bang(SStream *O, uint32_t val);
+
+void printUInt32(SStream *O, uint32_t val);
+
+// print number in decimal mode
+void printInt32BangDec(SStream *O, int32_t val);
+
+#endif
diff --git a/TODO b/TODO
new file mode 100644
index 0000000..e7117ee
--- /dev/null
+++ b/TODO
@@ -0,0 +1,16 @@
+Issues to be solved in next versions
+
+
+[Core]
+
+- X86 can already handle all the malware tricks we are aware of. If you find
+  any such instruction sequence that Capstone disassembles wrongly or fails
+  completely, please report. Fixing this issue is always the top priority of
+  our project.
+
+- More optimization for better performance.
+
+
+[Bindings]
+
+- OCaml binding is working, but still needs to support the core API better.
diff --git a/arch/AArch64/AArch64AddressingModes.h b/arch/AArch64/AArch64AddressingModes.h
new file mode 100644
index 0000000..e162fda
--- /dev/null
+++ b/arch/AArch64/AArch64AddressingModes.h
@@ -0,0 +1,225 @@
+//===- AArch64AddressingModes.h - AArch64 Addressing Modes ------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the AArch64 addressing mode implementation stuff.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef CS_AARCH64_ADDRESSINGMODES_H
+#define CS_AARCH64_ADDRESSINGMODES_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014 */
+
+#include "../../MathExtras.h"
+
+/// AArch64_AM - AArch64 Addressing Mode Stuff
+
+//===----------------------------------------------------------------------===//
+// Shifts
+//
+
+typedef enum AArch64_AM_ShiftExtendType {
+	AArch64_AM_InvalidShiftExtend = -1,
+	AArch64_AM_LSL = 0,
+	AArch64_AM_LSR,
+	AArch64_AM_ASR,
+	AArch64_AM_ROR,
+	AArch64_AM_MSL,
+
+	AArch64_AM_UXTB,
+	AArch64_AM_UXTH,
+	AArch64_AM_UXTW,
+	AArch64_AM_UXTX,
+
+	AArch64_AM_SXTB,
+	AArch64_AM_SXTH,
+	AArch64_AM_SXTW,
+	AArch64_AM_SXTX,
+} AArch64_AM_ShiftExtendType;
+
+/// getShiftName - Get the string encoding for the shift type.
+static inline const char *AArch64_AM_getShiftExtendName(AArch64_AM_ShiftExtendType ST)
+{
+	switch (ST) {
+		default: return NULL; // never reach
+		case AArch64_AM_LSL: return "lsl";
+		case AArch64_AM_LSR: return "lsr";
+		case AArch64_AM_ASR: return "asr";
+		case AArch64_AM_ROR: return "ror";
+		case AArch64_AM_MSL: return "msl";
+		case AArch64_AM_UXTB: return "uxtb";
+		case AArch64_AM_UXTH: return "uxth";
+		case AArch64_AM_UXTW: return "uxtw";
+		case AArch64_AM_UXTX: return "uxtx";
+		case AArch64_AM_SXTB: return "sxtb";
+		case AArch64_AM_SXTH: return "sxth";
+		case AArch64_AM_SXTW: return "sxtw";
+		case AArch64_AM_SXTX: return "sxtx";
+	}
+}
+
+/// getShiftType - Extract the shift type.
+static inline AArch64_AM_ShiftExtendType AArch64_AM_getShiftType(unsigned Imm)
+{
+	switch ((Imm >> 6) & 0x7) {
+		default: return AArch64_AM_InvalidShiftExtend;
+		case 0: return AArch64_AM_LSL;
+		case 1: return AArch64_AM_LSR;
+		case 2: return AArch64_AM_ASR;
+		case 3: return AArch64_AM_ROR;
+		case 4: return AArch64_AM_MSL;
+	}
+}
+
+/// getShiftValue - Extract the shift value.
+static inline unsigned AArch64_AM_getShiftValue(unsigned Imm)
+{
+	return Imm & 0x3f;
+}
+
+//===----------------------------------------------------------------------===//
+// Extends
+//
+
+/// getArithShiftValue - get the arithmetic shift value.
+static inline unsigned AArch64_AM_getArithShiftValue(unsigned Imm)
+{
+	return Imm & 0x7;
+}
+
+/// getExtendType - Extract the extend type for operands of arithmetic ops.
+static inline AArch64_AM_ShiftExtendType AArch64_AM_getExtendType(unsigned Imm)
+{
+	// assert((Imm & 0x7) == Imm && "invalid immediate!");
+	switch (Imm) {
+		default: // llvm_unreachable("Compiler bug!");
+		case 0: return AArch64_AM_UXTB;
+		case 1: return AArch64_AM_UXTH;
+		case 2: return AArch64_AM_UXTW;
+		case 3: return AArch64_AM_UXTX;
+		case 4: return AArch64_AM_SXTB;
+		case 5: return AArch64_AM_SXTH;
+		case 6: return AArch64_AM_SXTW;
+		case 7: return AArch64_AM_SXTX;
+	}
+}
+
+static inline AArch64_AM_ShiftExtendType AArch64_AM_getArithExtendType(unsigned Imm)
+{
+	return AArch64_AM_getExtendType((Imm >> 3) & 0x7);
+}
+
+static inline uint64_t ror(uint64_t elt, unsigned size)
+{
+	return ((elt & 1) << (size-1)) | (elt >> 1);
+}
+
+/// decodeLogicalImmediate - Decode a logical immediate value in the form
+/// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the
+/// integer value it represents with regSize bits.
+static inline uint64_t AArch64_AM_decodeLogicalImmediate(uint64_t val, unsigned regSize)
+{
+	// Extract the N, imms, and immr fields.
+	unsigned N = (val >> 12) & 1;
+	unsigned immr = (val >> 6) & 0x3f;
+	unsigned imms = val & 0x3f;
+	unsigned i;
+
+	// assert((regSize == 64 || N == 0) && "undefined logical immediate encoding");
+	int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
+	// assert(len >= 0 && "undefined logical immediate encoding");
+	unsigned size = (1 << len);
+	unsigned R = immr & (size - 1);
+	unsigned S = imms & (size - 1);
+	// assert(S != size - 1 && "undefined logical immediate encoding");
+	uint64_t pattern = (1ULL << (S + 1)) - 1;
+	for (i = 0; i < R; ++i)
+		pattern = ror(pattern, size);
+
+	// Replicate the pattern to fill the regSize.
+	while (size != regSize) {
+		pattern |= (pattern << size);
+		size *= 2;
+	}
+
+	return pattern;
+}
+
+/// isValidDecodeLogicalImmediate - Check to see if the logical immediate value
+/// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits)
+/// is a valid encoding for an integer value with regSize bits.
+static inline bool AArch64_AM_isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)
+{
+	unsigned size;
+	unsigned S;
+	int len;
+	// Extract the N and imms fields needed for checking.
+	unsigned N = (val >> 12) & 1;
+	unsigned imms = val & 0x3f;
+
+	if (regSize == 32 && N != 0) // undefined logical immediate encoding
+		return false;
+	len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
+	if (len < 0) // undefined logical immediate encoding
+		return false;
+	size = (1 << len);
+	S = imms & (size - 1);
+	if (S == size - 1) // undefined logical immediate encoding
+		return false;
+
+	return true;
+}
+
+//===----------------------------------------------------------------------===//
+// Floating-point Immediates
+//
+static inline float AArch64_AM_getFPImmFloat(unsigned Imm)
+{
+	// We expect an 8-bit binary encoding of a floating-point number here.
+	union {
+		uint32_t I;
+		float F;
+	} FPUnion;
+
+	uint8_t Sign = (Imm >> 7) & 0x1;
+	uint8_t Exp = (Imm >> 4) & 0x7;
+	uint8_t Mantissa = Imm & 0xf;
+
+	//   8-bit FP    iEEEE Float Encoding
+	//   abcd efgh   aBbbbbbc defgh000 00000000 00000000
+	//
+	// where B = NOT(b);
+
+	FPUnion.I = 0;
+	FPUnion.I |= Sign << 31;
+	FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
+	FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
+	FPUnion.I |= (Exp & 0x3) << 23;
+	FPUnion.I |= Mantissa << 19;
+
+	return FPUnion.F;
+}
+
+//===--------------------------------------------------------------------===//
+// AdvSIMD Modified Immediates
+//===--------------------------------------------------------------------===//
+
+static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType10(uint8_t Imm)
+{
+	static const uint32_t lookup[16] = {
+		0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff, 
+		0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff, 
+		0xff000000, 0xff0000ff, 0xff00ff00, 0xff00ffff, 
+		0xffff0000, 0xffff00ff, 0xffffff00, 0xffffffff
+        };
+	return lookup[Imm & 0x0f] | ((uint64_t)lookup[Imm >> 4] << 32);
+}
+
+#endif
diff --git a/arch/AArch64/AArch64BaseInfo.c b/arch/AArch64/AArch64BaseInfo.c
new file mode 100644
index 0000000..468d0ff
--- /dev/null
+++ b/arch/AArch64/AArch64BaseInfo.c
@@ -0,0 +1,999 @@
+//===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides basic encoding and assembly information for AArch64.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifdef CAPSTONE_HAS_ARM64
+
+#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)
+#pragma warning(disable:4996)			// disable MSVC's warning on strcpy()
+#pragma warning(disable:28719)		// disable MSVC's warning on strcpy()
+#endif
+
+#include "../../utils.h"
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "AArch64BaseInfo.h"
+
+char *A64NamedImmMapper_toString(A64NamedImmMapper *N, uint32_t Value, bool *Valid)
+{
+	unsigned i;
+	for (i = 0; i < N->NumPairs; ++i) {
+		if (N->Pairs[i].Value == Value) {
+			*Valid = true;
+			return N->Pairs[i].Name;
+		}
+	}
+
+	*Valid = false;
+	return 0;
+}
+
+// compare s1 with lower(s2)
+// return true if s1 == lower(f2), and false otherwise
+static bool compare_lower_str(char *s1, char *s2)
+{
+	bool res;
+	char *lower = cs_strdup(s2), *c;
+	for (c = lower; *c; c++)
+		*c = (char)tolower((int) *c);
+
+	res = (strcmp(s1, lower) == 0);
+	cs_mem_free(lower);
+
+	return res;
+}
+
+uint32_t A64NamedImmMapper_fromString(A64NamedImmMapper *N, char *Name, bool *Valid)
+{
+	unsigned i;
+	for (i = 0; i < N->NumPairs; ++i) {
+		if (compare_lower_str(N->Pairs[i].Name, Name)) {
+			*Valid = true;
+			return N->Pairs[i].Value;
+		}
+	}
+
+	*Valid = false;
+	return (uint32_t)-1;
+}
+
+bool A64NamedImmMapper_validImm(A64NamedImmMapper *N, uint32_t Value)
+{
+	return Value < N->TooBigImm;
+}
+
+// return a string representing the number X
+// NOTE: caller must free() the result itself to avoid memory leak
+static char *utostr(uint64_t X, bool isNeg)
+{
+	char Buffer[22];
+	char *BufPtr = Buffer+21;
+	char *result;
+
+	Buffer[21] = '\0';
+	if (X == 0) *--BufPtr = '0';  // Handle special case...
+
+	while (X) {
+		*--BufPtr = X % 10 + '0';
+		X /= 10;
+	}
+
+	if (isNeg) *--BufPtr = '-';   // Add negative sign...
+
+	result = cs_strdup(BufPtr);
+	return result;
+}
+
+static A64NamedImmMapper_Mapping SysRegPairs[] = {
+	{"pan", A64SysReg_PAN},
+	{"uao", A64SysReg_UAO},
+	{"osdtrrx_el1", A64SysReg_OSDTRRX_EL1},
+	{"osdtrtx_el1",  A64SysReg_OSDTRTX_EL1},
+	{"teecr32_el1", A64SysReg_TEECR32_EL1},
+	{"mdccint_el1", A64SysReg_MDCCINT_EL1},
+	{"mdscr_el1", A64SysReg_MDSCR_EL1},
+	{"dbgdtr_el0", A64SysReg_DBGDTR_EL0},
+	{"oseccr_el1", A64SysReg_OSECCR_EL1},
+	{"dbgvcr32_el2", A64SysReg_DBGVCR32_EL2},
+	{"dbgbvr0_el1", A64SysReg_DBGBVR0_EL1},
+	{"dbgbvr1_el1", A64SysReg_DBGBVR1_EL1},
+	{"dbgbvr2_el1", A64SysReg_DBGBVR2_EL1},
+	{"dbgbvr3_el1", A64SysReg_DBGBVR3_EL1},
+	{"dbgbvr4_el1", A64SysReg_DBGBVR4_EL1},
+	{"dbgbvr5_el1", A64SysReg_DBGBVR5_EL1},
+	{"dbgbvr6_el1", A64SysReg_DBGBVR6_EL1},
+	{"dbgbvr7_el1", A64SysReg_DBGBVR7_EL1},
+	{"dbgbvr8_el1", A64SysReg_DBGBVR8_EL1},
+	{"dbgbvr9_el1", A64SysReg_DBGBVR9_EL1},
+	{"dbgbvr10_el1", A64SysReg_DBGBVR10_EL1},
+	{"dbgbvr11_el1", A64SysReg_DBGBVR11_EL1},
+	{"dbgbvr12_el1", A64SysReg_DBGBVR12_EL1},
+	{"dbgbvr13_el1", A64SysReg_DBGBVR13_EL1},
+	{"dbgbvr14_el1", A64SysReg_DBGBVR14_EL1},
+	{"dbgbvr15_el1", A64SysReg_DBGBVR15_EL1},
+	{"dbgbcr0_el1", A64SysReg_DBGBCR0_EL1},
+	{"dbgbcr1_el1", A64SysReg_DBGBCR1_EL1},
+	{"dbgbcr2_el1", A64SysReg_DBGBCR2_EL1},
+	{"dbgbcr3_el1", A64SysReg_DBGBCR3_EL1},
+	{"dbgbcr4_el1", A64SysReg_DBGBCR4_EL1},
+	{"dbgbcr5_el1", A64SysReg_DBGBCR5_EL1},
+	{"dbgbcr6_el1", A64SysReg_DBGBCR6_EL1},
+	{"dbgbcr7_el1", A64SysReg_DBGBCR7_EL1},
+	{"dbgbcr8_el1", A64SysReg_DBGBCR8_EL1},
+	{"dbgbcr9_el1", A64SysReg_DBGBCR9_EL1},
+	{"dbgbcr10_el1", A64SysReg_DBGBCR10_EL1},
+	{"dbgbcr11_el1", A64SysReg_DBGBCR11_EL1},
+	{"dbgbcr12_el1", A64SysReg_DBGBCR12_EL1},
+	{"dbgbcr13_el1", A64SysReg_DBGBCR13_EL1},
+	{"dbgbcr14_el1", A64SysReg_DBGBCR14_EL1},
+	{"dbgbcr15_el1", A64SysReg_DBGBCR15_EL1},
+	{"dbgwvr0_el1", A64SysReg_DBGWVR0_EL1},
+	{"dbgwvr1_el1", A64SysReg_DBGWVR1_EL1},
+	{"dbgwvr2_el1", A64SysReg_DBGWVR2_EL1},
+	{"dbgwvr3_el1", A64SysReg_DBGWVR3_EL1},
+	{"dbgwvr4_el1", A64SysReg_DBGWVR4_EL1},
+	{"dbgwvr5_el1", A64SysReg_DBGWVR5_EL1},
+	{"dbgwvr6_el1", A64SysReg_DBGWVR6_EL1},
+	{"dbgwvr7_el1", A64SysReg_DBGWVR7_EL1},
+	{"dbgwvr8_el1", A64SysReg_DBGWVR8_EL1},
+	{"dbgwvr9_el1", A64SysReg_DBGWVR9_EL1},
+	{"dbgwvr10_el1", A64SysReg_DBGWVR10_EL1},
+	{"dbgwvr11_el1", A64SysReg_DBGWVR11_EL1},
+	{"dbgwvr12_el1", A64SysReg_DBGWVR12_EL1},
+	{"dbgwvr13_el1", A64SysReg_DBGWVR13_EL1},
+	{"dbgwvr14_el1", A64SysReg_DBGWVR14_EL1},
+	{"dbgwvr15_el1", A64SysReg_DBGWVR15_EL1},
+	{"dbgwcr0_el1", A64SysReg_DBGWCR0_EL1},
+	{"dbgwcr1_el1", A64SysReg_DBGWCR1_EL1},
+	{"dbgwcr2_el1", A64SysReg_DBGWCR2_EL1},
+	{"dbgwcr3_el1", A64SysReg_DBGWCR3_EL1},
+	{"dbgwcr4_el1", A64SysReg_DBGWCR4_EL1},
+	{"dbgwcr5_el1", A64SysReg_DBGWCR5_EL1},
+	{"dbgwcr6_el1", A64SysReg_DBGWCR6_EL1},
+	{"dbgwcr7_el1", A64SysReg_DBGWCR7_EL1},
+	{"dbgwcr8_el1", A64SysReg_DBGWCR8_EL1},
+	{"dbgwcr9_el1", A64SysReg_DBGWCR9_EL1},
+	{"dbgwcr10_el1", A64SysReg_DBGWCR10_EL1},
+	{"dbgwcr11_el1", A64SysReg_DBGWCR11_EL1},
+	{"dbgwcr12_el1", A64SysReg_DBGWCR12_EL1},
+	{"dbgwcr13_el1", A64SysReg_DBGWCR13_EL1},
+	{"dbgwcr14_el1", A64SysReg_DBGWCR14_EL1},
+	{"dbgwcr15_el1", A64SysReg_DBGWCR15_EL1},
+	{"teehbr32_el1", A64SysReg_TEEHBR32_EL1},
+	{"osdlr_el1", A64SysReg_OSDLR_EL1},
+	{"dbgprcr_el1", A64SysReg_DBGPRCR_EL1},
+	{"dbgclaimset_el1", A64SysReg_DBGCLAIMSET_EL1},
+	{"dbgclaimclr_el1", A64SysReg_DBGCLAIMCLR_EL1},
+	{"csselr_el1", A64SysReg_CSSELR_EL1},
+	{"vpidr_el2", A64SysReg_VPIDR_EL2},
+	{"vmpidr_el2", A64SysReg_VMPIDR_EL2},
+	{"sctlr_el1", A64SysReg_SCTLR_EL1},
+	{"sctlr_el12", A64SysReg_SCTLR_EL12},
+	{"sctlr_el2", A64SysReg_SCTLR_EL2},
+	{"sctlr_el3", A64SysReg_SCTLR_EL3},
+	{"actlr_el1", A64SysReg_ACTLR_EL1},
+	{"actlr_el2", A64SysReg_ACTLR_EL2},
+	{"actlr_el3", A64SysReg_ACTLR_EL3},
+	{"cpacr_el1", A64SysReg_CPACR_EL1},
+	{"cpacr_el12", A64SysReg_CPACR_EL12},
+	{"hcr_el2", A64SysReg_HCR_EL2},
+	{"scr_el3", A64SysReg_SCR_EL3},
+	{"mdcr_el2", A64SysReg_MDCR_EL2},
+	{"sder32_el3", A64SysReg_SDER32_EL3},
+	{"cptr_el2", A64SysReg_CPTR_EL2},
+	{"cptr_el3", A64SysReg_CPTR_EL3},
+	{"hstr_el2", A64SysReg_HSTR_EL2},
+	{"hacr_el2", A64SysReg_HACR_EL2},
+	{"mdcr_el3", A64SysReg_MDCR_EL3},
+	{"ttbr0_el1", A64SysReg_TTBR0_EL1},
+	{"ttbr0_el12", A64SysReg_TTBR0_EL12},
+	{"ttbr0_el2", A64SysReg_TTBR0_EL2},
+	{"ttbr0_el3", A64SysReg_TTBR0_EL3},
+	{"ttbr1_el1", A64SysReg_TTBR1_EL1},
+	{"ttbr1_el12", A64SysReg_TTBR1_EL12},
+	{"ttbr1_el2", A64SysReg_TTBR1_EL2},
+	{"tcr_el1", A64SysReg_TCR_EL1},
+	{"tcr_el12", A64SysReg_TCR_EL12},
+	{"tcr_el2", A64SysReg_TCR_EL2},
+	{"tcr_el3", A64SysReg_TCR_EL3},
+	{"vttbr_el2", A64SysReg_VTTBR_EL2},
+	{"vtcr_el2", A64SysReg_VTCR_EL2},
+	{"dacr32_el2", A64SysReg_DACR32_EL2},
+	{"spsr_el1", A64SysReg_SPSR_EL1},
+	{"spsr_el12", A64SysReg_SPSR_EL12},
+	{"spsr_el2", A64SysReg_SPSR_EL2},
+	{"spsr_el3", A64SysReg_SPSR_EL3},
+	{"elr_el1", A64SysReg_ELR_EL1},
+	{"elr_el12", A64SysReg_ELR_EL12},
+	{"elr_el2", A64SysReg_ELR_EL2},
+	{"elr_el3", A64SysReg_ELR_EL3},
+	{"sp_el0", A64SysReg_SP_EL0},
+	{"sp_el1", A64SysReg_SP_EL1},
+	{"sp_el2", A64SysReg_SP_EL2},
+	{"spsel", A64SysReg_SPSel},
+	{"nzcv", A64SysReg_NZCV},
+	{"daif", A64SysReg_DAIF},
+	{"currentel", A64SysReg_CurrentEL},
+	{"spsr_irq", A64SysReg_SPSR_irq},
+	{"spsr_abt", A64SysReg_SPSR_abt},
+	{"spsr_und", A64SysReg_SPSR_und},
+	{"spsr_fiq", A64SysReg_SPSR_fiq},
+	{"fpcr", A64SysReg_FPCR},
+	{"fpsr", A64SysReg_FPSR},
+	{"dspsr_el0", A64SysReg_DSPSR_EL0},
+	{"dlr_el0", A64SysReg_DLR_EL0},
+	{"ifsr32_el2", A64SysReg_IFSR32_EL2},
+	{"afsr0_el1", A64SysReg_AFSR0_EL1},
+	{"afsr0_el12", A64SysReg_AFSR0_EL12},
+	{"afsr0_el2", A64SysReg_AFSR0_EL2},
+	{"afsr0_el3", A64SysReg_AFSR0_EL3},
+	{"afsr1_el1", A64SysReg_AFSR1_EL1},
+	{"afsr1_el12", A64SysReg_AFSR1_EL12},
+	{"afsr1_el2", A64SysReg_AFSR1_EL2},
+	{"afsr1_el3", A64SysReg_AFSR1_EL3},
+	{"esr_el1", A64SysReg_ESR_EL1},
+	{"esr_el12", A64SysReg_ESR_EL12},
+	{"esr_el2", A64SysReg_ESR_EL2},
+	{"esr_el3", A64SysReg_ESR_EL3},
+	{"fpexc32_el2", A64SysReg_FPEXC32_EL2},
+	{"far_el1", A64SysReg_FAR_EL1},
+	{"far_el12", A64SysReg_FAR_EL12},
+	{"far_el2", A64SysReg_FAR_EL2},
+	{"far_el3", A64SysReg_FAR_EL3},
+	{"hpfar_el2", A64SysReg_HPFAR_EL2},
+	{"par_el1", A64SysReg_PAR_EL1},
+	{"pmcr_el0", A64SysReg_PMCR_EL0},
+	{"pmcntenset_el0", A64SysReg_PMCNTENSET_EL0},
+	{"pmcntenclr_el0", A64SysReg_PMCNTENCLR_EL0},
+	{"pmovsclr_el0", A64SysReg_PMOVSCLR_EL0},
+	{"pmselr_el0", A64SysReg_PMSELR_EL0},
+	{"pmccntr_el0", A64SysReg_PMCCNTR_EL0},
+	{"pmxevtyper_el0", A64SysReg_PMXEVTYPER_EL0},
+	{"pmxevcntr_el0", A64SysReg_PMXEVCNTR_EL0},
+	{"pmuserenr_el0", A64SysReg_PMUSERENR_EL0},
+	{"pmintenset_el1", A64SysReg_PMINTENSET_EL1},
+	{"pmintenclr_el1", A64SysReg_PMINTENCLR_EL1},
+	{"pmovsset_el0", A64SysReg_PMOVSSET_EL0},
+	{"mair_el1", A64SysReg_MAIR_EL1},
+	{"mair_el12", A64SysReg_MAIR_EL12},
+	{"mair_el2", A64SysReg_MAIR_EL2},
+	{"mair_el3", A64SysReg_MAIR_EL3},
+	{"amair_el1", A64SysReg_AMAIR_EL1},
+	{"amair_el12", A64SysReg_AMAIR_EL12},
+	{"amair_el2", A64SysReg_AMAIR_EL2},
+	{"amair_el3", A64SysReg_AMAIR_EL3},
+	{"vbar_el1", A64SysReg_VBAR_EL1},
+	{"vbar_el12", A64SysReg_VBAR_EL12},
+	{"vbar_el2", A64SysReg_VBAR_EL2},
+	{"vbar_el3", A64SysReg_VBAR_EL3},
+	{"rmr_el1", A64SysReg_RMR_EL1},
+	{"rmr_el2", A64SysReg_RMR_EL2},
+	{"rmr_el3", A64SysReg_RMR_EL3},
+	{"contextidr_el1", A64SysReg_CONTEXTIDR_EL1},
+	{"contextidr_el12", A64SysReg_CONTEXTIDR_EL12},
+	{"contextidr_el2", A64SysReg_CONTEXTIDR_EL2},
+	{"tpidr_el0", A64SysReg_TPIDR_EL0},
+	{"tpidr_el2", A64SysReg_TPIDR_EL2},
+	{"tpidr_el3", A64SysReg_TPIDR_EL3},
+	{"tpidrro_el0", A64SysReg_TPIDRRO_EL0},
+	{"tpidr_el1", A64SysReg_TPIDR_EL1},
+	{"cntfrq_el0", A64SysReg_CNTFRQ_EL0},
+	{"cntvoff_el2", A64SysReg_CNTVOFF_EL2},
+	{"cntkctl_el1", A64SysReg_CNTKCTL_EL1},
+	{"cntkctl_el12", A64SysReg_CNTKCTL_EL12},
+	{"cnthctl_el2", A64SysReg_CNTHCTL_EL2},
+	{"cntp_tval_el0", A64SysReg_CNTP_TVAL_EL0},
+	{"cntp_tval_el02", A64SysReg_CNTP_TVAL_EL02},
+	{"cnthp_tval_el2", A64SysReg_CNTHP_TVAL_EL2},
+	{"cntps_tval_el1", A64SysReg_CNTPS_TVAL_EL1},
+	{"cntp_ctl_el0", A64SysReg_CNTP_CTL_EL0},
+	{"cnthp_ctl_el2", A64SysReg_CNTHP_CTL_EL2},
+	{"cnthv_ctl_el2", A64SysReg_CNTHVCTL_EL2},
+	{"cnthv_cval_el2", A64SysReg_CNTHV_CVAL_EL2},
+	{"cnthv_tval_el2", A64SysReg_CNTHV_TVAL_EL2},
+	{"cntps_ctl_el1", A64SysReg_CNTPS_CTL_EL1},
+	{"cntp_cval_el0", A64SysReg_CNTP_CVAL_EL0},
+	{"cntp_cval_el02", A64SysReg_CNTP_CVAL_EL02},
+	{"cnthp_cval_el2", A64SysReg_CNTHP_CVAL_EL2},
+	{"cntps_cval_el1", A64SysReg_CNTPS_CVAL_EL1},
+	{"cntv_tval_el0", A64SysReg_CNTV_TVAL_EL0},
+	{"cntv_tval_el02", A64SysReg_CNTV_TVAL_EL02},
+	{"cntv_ctl_el0", A64SysReg_CNTV_CTL_EL0},
+	{"cntv_ctl_el02", A64SysReg_CNTV_CTL_EL02},
+	{"cntv_cval_el0", A64SysReg_CNTV_CVAL_EL0},
+	{"cntv_cval_el02", A64SysReg_CNTV_CVAL_EL02},
+	{"pmevcntr0_el0", A64SysReg_PMEVCNTR0_EL0},
+	{"pmevcntr1_el0", A64SysReg_PMEVCNTR1_EL0},
+	{"pmevcntr2_el0", A64SysReg_PMEVCNTR2_EL0},
+	{"pmevcntr3_el0", A64SysReg_PMEVCNTR3_EL0},
+	{"pmevcntr4_el0", A64SysReg_PMEVCNTR4_EL0},
+	{"pmevcntr5_el0", A64SysReg_PMEVCNTR5_EL0},
+	{"pmevcntr6_el0", A64SysReg_PMEVCNTR6_EL0},
+	{"pmevcntr7_el0", A64SysReg_PMEVCNTR7_EL0},
+	{"pmevcntr8_el0", A64SysReg_PMEVCNTR8_EL0},
+	{"pmevcntr9_el0", A64SysReg_PMEVCNTR9_EL0},
+	{"pmevcntr10_el0", A64SysReg_PMEVCNTR10_EL0},
+	{"pmevcntr11_el0", A64SysReg_PMEVCNTR11_EL0},
+	{"pmevcntr12_el0", A64SysReg_PMEVCNTR12_EL0},
+	{"pmevcntr13_el0", A64SysReg_PMEVCNTR13_EL0},
+	{"pmevcntr14_el0", A64SysReg_PMEVCNTR14_EL0},
+	{"pmevcntr15_el0", A64SysReg_PMEVCNTR15_EL0},
+	{"pmevcntr16_el0", A64SysReg_PMEVCNTR16_EL0},
+	{"pmevcntr17_el0", A64SysReg_PMEVCNTR17_EL0},
+	{"pmevcntr18_el0", A64SysReg_PMEVCNTR18_EL0},
+	{"pmevcntr19_el0", A64SysReg_PMEVCNTR19_EL0},
+	{"pmevcntr20_el0", A64SysReg_PMEVCNTR20_EL0},
+	{"pmevcntr21_el0", A64SysReg_PMEVCNTR21_EL0},
+	{"pmevcntr22_el0", A64SysReg_PMEVCNTR22_EL0},
+	{"pmevcntr23_el0", A64SysReg_PMEVCNTR23_EL0},
+	{"pmevcntr24_el0", A64SysReg_PMEVCNTR24_EL0},
+	{"pmevcntr25_el0", A64SysReg_PMEVCNTR25_EL0},
+	{"pmevcntr26_el0", A64SysReg_PMEVCNTR26_EL0},
+	{"pmevcntr27_el0", A64SysReg_PMEVCNTR27_EL0},
+	{"pmevcntr28_el0", A64SysReg_PMEVCNTR28_EL0},
+	{"pmevcntr29_el0", A64SysReg_PMEVCNTR29_EL0},
+	{"pmevcntr30_el0", A64SysReg_PMEVCNTR30_EL0},
+	{"pmccfiltr_el0", A64SysReg_PMCCFILTR_EL0},
+	{"pmevtyper0_el0", A64SysReg_PMEVTYPER0_EL0},
+	{"pmevtyper1_el0", A64SysReg_PMEVTYPER1_EL0},
+	{"pmevtyper2_el0", A64SysReg_PMEVTYPER2_EL0},
+	{"pmevtyper3_el0", A64SysReg_PMEVTYPER3_EL0},
+	{"pmevtyper4_el0", A64SysReg_PMEVTYPER4_EL0},
+	{"pmevtyper5_el0", A64SysReg_PMEVTYPER5_EL0},
+	{"pmevtyper6_el0", A64SysReg_PMEVTYPER6_EL0},
+	{"pmevtyper7_el0", A64SysReg_PMEVTYPER7_EL0},
+	{"pmevtyper8_el0", A64SysReg_PMEVTYPER8_EL0},
+	{"pmevtyper9_el0", A64SysReg_PMEVTYPER9_EL0},
+	{"pmevtyper10_el0", A64SysReg_PMEVTYPER10_EL0},
+	{"pmevtyper11_el0", A64SysReg_PMEVTYPER11_EL0},
+	{"pmevtyper12_el0", A64SysReg_PMEVTYPER12_EL0},
+	{"pmevtyper13_el0", A64SysReg_PMEVTYPER13_EL0},
+	{"pmevtyper14_el0", A64SysReg_PMEVTYPER14_EL0},
+	{"pmevtyper15_el0", A64SysReg_PMEVTYPER15_EL0},
+	{"pmevtyper16_el0", A64SysReg_PMEVTYPER16_EL0},
+	{"pmevtyper17_el0", A64SysReg_PMEVTYPER17_EL0},
+	{"pmevtyper18_el0", A64SysReg_PMEVTYPER18_EL0},
+	{"pmevtyper19_el0", A64SysReg_PMEVTYPER19_EL0},
+	{"pmevtyper20_el0", A64SysReg_PMEVTYPER20_EL0},
+	{"pmevtyper21_el0", A64SysReg_PMEVTYPER21_EL0},
+	{"pmevtyper22_el0", A64SysReg_PMEVTYPER22_EL0},
+	{"pmevtyper23_el0", A64SysReg_PMEVTYPER23_EL0},
+	{"pmevtyper24_el0", A64SysReg_PMEVTYPER24_EL0},
+	{"pmevtyper25_el0", A64SysReg_PMEVTYPER25_EL0},
+	{"pmevtyper26_el0", A64SysReg_PMEVTYPER26_EL0},
+	{"pmevtyper27_el0", A64SysReg_PMEVTYPER27_EL0},
+	{"pmevtyper28_el0", A64SysReg_PMEVTYPER28_EL0},
+	{"pmevtyper29_el0", A64SysReg_PMEVTYPER29_EL0},
+	{"pmevtyper30_el0", A64SysReg_PMEVTYPER30_EL0},
+	{"lorc_el1", A64SysReg_LORC_EL1},
+	{"lorea_el1", A64SysReg_LOREA_EL1},
+	{"lorn_el1", A64SysReg_LORN_EL1},
+	{"lorsa_el1", A64SysReg_LORSA_EL1},
+
+	// Trace registers
+	{"trcprgctlr", A64SysReg_TRCPRGCTLR},
+	{"trcprocselr", A64SysReg_TRCPROCSELR},
+	{"trcconfigr", A64SysReg_TRCCONFIGR},
+	{"trcauxctlr", A64SysReg_TRCAUXCTLR},
+	{"trceventctl0r", A64SysReg_TRCEVENTCTL0R},
+	{"trceventctl1r", A64SysReg_TRCEVENTCTL1R},
+	{"trcstallctlr", A64SysReg_TRCSTALLCTLR},
+	{"trctsctlr", A64SysReg_TRCTSCTLR},
+	{"trcsyncpr", A64SysReg_TRCSYNCPR},
+	{"trcccctlr", A64SysReg_TRCCCCTLR},
+	{"trcbbctlr", A64SysReg_TRCBBCTLR},
+	{"trctraceidr", A64SysReg_TRCTRACEIDR},
+	{"trcqctlr", A64SysReg_TRCQCTLR},
+	{"trcvictlr", A64SysReg_TRCVICTLR},
+	{"trcviiectlr", A64SysReg_TRCVIIECTLR},
+	{"trcvissctlr", A64SysReg_TRCVISSCTLR},
+	{"trcvipcssctlr", A64SysReg_TRCVIPCSSCTLR},
+	{"trcvdctlr", A64SysReg_TRCVDCTLR},
+	{"trcvdsacctlr", A64SysReg_TRCVDSACCTLR},
+	{"trcvdarcctlr", A64SysReg_TRCVDARCCTLR},
+	{"trcseqevr0", A64SysReg_TRCSEQEVR0},
+	{"trcseqevr1", A64SysReg_TRCSEQEVR1},
+	{"trcseqevr2", A64SysReg_TRCSEQEVR2},
+	{"trcseqrstevr", A64SysReg_TRCSEQRSTEVR},
+	{"trcseqstr", A64SysReg_TRCSEQSTR},
+	{"trcextinselr", A64SysReg_TRCEXTINSELR},
+	{"trccntrldvr0", A64SysReg_TRCCNTRLDVR0},
+	{"trccntrldvr1", A64SysReg_TRCCNTRLDVR1},
+	{"trccntrldvr2", A64SysReg_TRCCNTRLDVR2},
+	{"trccntrldvr3", A64SysReg_TRCCNTRLDVR3},
+	{"trccntctlr0", A64SysReg_TRCCNTCTLR0},
+	{"trccntctlr1", A64SysReg_TRCCNTCTLR1},
+	{"trccntctlr2", A64SysReg_TRCCNTCTLR2},
+	{"trccntctlr3", A64SysReg_TRCCNTCTLR3},
+	{"trccntvr0", A64SysReg_TRCCNTVR0},
+	{"trccntvr1", A64SysReg_TRCCNTVR1},
+	{"trccntvr2", A64SysReg_TRCCNTVR2},
+	{"trccntvr3", A64SysReg_TRCCNTVR3},
+	{"trcimspec0", A64SysReg_TRCIMSPEC0},
+	{"trcimspec1", A64SysReg_TRCIMSPEC1},
+	{"trcimspec2", A64SysReg_TRCIMSPEC2},
+	{"trcimspec3", A64SysReg_TRCIMSPEC3},
+	{"trcimspec4", A64SysReg_TRCIMSPEC4},
+	{"trcimspec5", A64SysReg_TRCIMSPEC5},
+	{"trcimspec6", A64SysReg_TRCIMSPEC6},
+	{"trcimspec7", A64SysReg_TRCIMSPEC7},
+	{"trcrsctlr2", A64SysReg_TRCRSCTLR2},
+	{"trcrsctlr3", A64SysReg_TRCRSCTLR3},
+	{"trcrsctlr4", A64SysReg_TRCRSCTLR4},
+	{"trcrsctlr5", A64SysReg_TRCRSCTLR5},
+	{"trcrsctlr6", A64SysReg_TRCRSCTLR6},
+	{"trcrsctlr7", A64SysReg_TRCRSCTLR7},
+	{"trcrsctlr8", A64SysReg_TRCRSCTLR8},
+	{"trcrsctlr9", A64SysReg_TRCRSCTLR9},
+	{"trcrsctlr10", A64SysReg_TRCRSCTLR10},
+	{"trcrsctlr11", A64SysReg_TRCRSCTLR11},
+	{"trcrsctlr12", A64SysReg_TRCRSCTLR12},
+	{"trcrsctlr13", A64SysReg_TRCRSCTLR13},
+	{"trcrsctlr14", A64SysReg_TRCRSCTLR14},
+	{"trcrsctlr15", A64SysReg_TRCRSCTLR15},
+	{"trcrsctlr16", A64SysReg_TRCRSCTLR16},
+	{"trcrsctlr17", A64SysReg_TRCRSCTLR17},
+	{"trcrsctlr18", A64SysReg_TRCRSCTLR18},
+	{"trcrsctlr19", A64SysReg_TRCRSCTLR19},
+	{"trcrsctlr20", A64SysReg_TRCRSCTLR20},
+	{"trcrsctlr21", A64SysReg_TRCRSCTLR21},
+	{"trcrsctlr22", A64SysReg_TRCRSCTLR22},
+	{"trcrsctlr23", A64SysReg_TRCRSCTLR23},
+	{"trcrsctlr24", A64SysReg_TRCRSCTLR24},
+	{"trcrsctlr25", A64SysReg_TRCRSCTLR25},
+	{"trcrsctlr26", A64SysReg_TRCRSCTLR26},
+	{"trcrsctlr27", A64SysReg_TRCRSCTLR27},
+	{"trcrsctlr28", A64SysReg_TRCRSCTLR28},
+	{"trcrsctlr29", A64SysReg_TRCRSCTLR29},
+	{"trcrsctlr30", A64SysReg_TRCRSCTLR30},
+	{"trcrsctlr31", A64SysReg_TRCRSCTLR31},
+	{"trcssccr0", A64SysReg_TRCSSCCR0},
+	{"trcssccr1", A64SysReg_TRCSSCCR1},
+	{"trcssccr2", A64SysReg_TRCSSCCR2},
+	{"trcssccr3", A64SysReg_TRCSSCCR3},
+	{"trcssccr4", A64SysReg_TRCSSCCR4},
+	{"trcssccr5", A64SysReg_TRCSSCCR5},
+	{"trcssccr6", A64SysReg_TRCSSCCR6},
+	{"trcssccr7", A64SysReg_TRCSSCCR7},
+	{"trcsscsr0", A64SysReg_TRCSSCSR0},
+	{"trcsscsr1", A64SysReg_TRCSSCSR1},
+	{"trcsscsr2", A64SysReg_TRCSSCSR2},
+	{"trcsscsr3", A64SysReg_TRCSSCSR3},
+	{"trcsscsr4", A64SysReg_TRCSSCSR4},
+	{"trcsscsr5", A64SysReg_TRCSSCSR5},
+	{"trcsscsr6", A64SysReg_TRCSSCSR6},
+	{"trcsscsr7", A64SysReg_TRCSSCSR7},
+	{"trcsspcicr0", A64SysReg_TRCSSPCICR0},
+	{"trcsspcicr1", A64SysReg_TRCSSPCICR1},
+	{"trcsspcicr2", A64SysReg_TRCSSPCICR2},
+	{"trcsspcicr3", A64SysReg_TRCSSPCICR3},
+	{"trcsspcicr4", A64SysReg_TRCSSPCICR4},
+	{"trcsspcicr5", A64SysReg_TRCSSPCICR5},
+	{"trcsspcicr6", A64SysReg_TRCSSPCICR6},
+	{"trcsspcicr7", A64SysReg_TRCSSPCICR7},
+	{"trcpdcr", A64SysReg_TRCPDCR},
+	{"trcacvr0", A64SysReg_TRCACVR0},
+	{"trcacvr1", A64SysReg_TRCACVR1},
+	{"trcacvr2", A64SysReg_TRCACVR2},
+	{"trcacvr3", A64SysReg_TRCACVR3},
+	{"trcacvr4", A64SysReg_TRCACVR4},
+	{"trcacvr5", A64SysReg_TRCACVR5},
+	{"trcacvr6", A64SysReg_TRCACVR6},
+	{"trcacvr7", A64SysReg_TRCACVR7},
+	{"trcacvr8", A64SysReg_TRCACVR8},
+	{"trcacvr9", A64SysReg_TRCACVR9},
+	{"trcacvr10", A64SysReg_TRCACVR10},
+	{"trcacvr11", A64SysReg_TRCACVR11},
+	{"trcacvr12", A64SysReg_TRCACVR12},
+	{"trcacvr13", A64SysReg_TRCACVR13},
+	{"trcacvr14", A64SysReg_TRCACVR14},
+	{"trcacvr15", A64SysReg_TRCACVR15},
+	{"trcacatr0", A64SysReg_TRCACATR0},
+	{"trcacatr1", A64SysReg_TRCACATR1},
+	{"trcacatr2", A64SysReg_TRCACATR2},
+	{"trcacatr3", A64SysReg_TRCACATR3},
+	{"trcacatr4", A64SysReg_TRCACATR4},
+	{"trcacatr5", A64SysReg_TRCACATR5},
+	{"trcacatr6", A64SysReg_TRCACATR6},
+	{"trcacatr7", A64SysReg_TRCACATR7},
+	{"trcacatr8", A64SysReg_TRCACATR8},
+	{"trcacatr9", A64SysReg_TRCACATR9},
+	{"trcacatr10", A64SysReg_TRCACATR10},
+	{"trcacatr11", A64SysReg_TRCACATR11},
+	{"trcacatr12", A64SysReg_TRCACATR12},
+	{"trcacatr13", A64SysReg_TRCACATR13},
+	{"trcacatr14", A64SysReg_TRCACATR14},
+	{"trcacatr15", A64SysReg_TRCACATR15},
+	{"trcdvcvr0", A64SysReg_TRCDVCVR0},
+	{"trcdvcvr1", A64SysReg_TRCDVCVR1},
+	{"trcdvcvr2", A64SysReg_TRCDVCVR2},
+	{"trcdvcvr3", A64SysReg_TRCDVCVR3},
+	{"trcdvcvr4", A64SysReg_TRCDVCVR4},
+	{"trcdvcvr5", A64SysReg_TRCDVCVR5},
+	{"trcdvcvr6", A64SysReg_TRCDVCVR6},
+	{"trcdvcvr7", A64SysReg_TRCDVCVR7},
+	{"trcdvcmr0", A64SysReg_TRCDVCMR0},
+	{"trcdvcmr1", A64SysReg_TRCDVCMR1},
+	{"trcdvcmr2", A64SysReg_TRCDVCMR2},
+	{"trcdvcmr3", A64SysReg_TRCDVCMR3},
+	{"trcdvcmr4", A64SysReg_TRCDVCMR4},
+	{"trcdvcmr5", A64SysReg_TRCDVCMR5},
+	{"trcdvcmr6", A64SysReg_TRCDVCMR6},
+	{"trcdvcmr7", A64SysReg_TRCDVCMR7},
+	{"trccidcvr0", A64SysReg_TRCCIDCVR0},
+	{"trccidcvr1", A64SysReg_TRCCIDCVR1},
+	{"trccidcvr2", A64SysReg_TRCCIDCVR2},
+	{"trccidcvr3", A64SysReg_TRCCIDCVR3},
+	{"trccidcvr4", A64SysReg_TRCCIDCVR4},
+	{"trccidcvr5", A64SysReg_TRCCIDCVR5},
+	{"trccidcvr6", A64SysReg_TRCCIDCVR6},
+	{"trccidcvr7", A64SysReg_TRCCIDCVR7},
+	{"trcvmidcvr0", A64SysReg_TRCVMIDCVR0},
+	{"trcvmidcvr1", A64SysReg_TRCVMIDCVR1},
+	{"trcvmidcvr2", A64SysReg_TRCVMIDCVR2},
+	{"trcvmidcvr3", A64SysReg_TRCVMIDCVR3},
+	{"trcvmidcvr4", A64SysReg_TRCVMIDCVR4},
+	{"trcvmidcvr5", A64SysReg_TRCVMIDCVR5},
+	{"trcvmidcvr6", A64SysReg_TRCVMIDCVR6},
+	{"trcvmidcvr7", A64SysReg_TRCVMIDCVR7},
+	{"trccidcctlr0", A64SysReg_TRCCIDCCTLR0},
+	{"trccidcctlr1", A64SysReg_TRCCIDCCTLR1},
+	{"trcvmidcctlr0", A64SysReg_TRCVMIDCCTLR0},
+	{"trcvmidcctlr1", A64SysReg_TRCVMIDCCTLR1},
+	{"trcitctrl", A64SysReg_TRCITCTRL},
+	{"trcclaimset", A64SysReg_TRCCLAIMSET},
+	{"trcclaimclr", A64SysReg_TRCCLAIMCLR},
+
+	// GICv3 registers
+	{"icc_bpr1_el1", A64SysReg_ICC_BPR1_EL1},
+	{"icc_bpr0_el1", A64SysReg_ICC_BPR0_EL1},
+	{"icc_pmr_el1", A64SysReg_ICC_PMR_EL1},
+	{"icc_ctlr_el1", A64SysReg_ICC_CTLR_EL1},
+	{"icc_ctlr_el3", A64SysReg_ICC_CTLR_EL3},
+	{"icc_sre_el1", A64SysReg_ICC_SRE_EL1},
+	{"icc_sre_el2", A64SysReg_ICC_SRE_EL2},
+	{"icc_sre_el3", A64SysReg_ICC_SRE_EL3},
+	{"icc_igrpen0_el1", A64SysReg_ICC_IGRPEN0_EL1},
+	{"icc_igrpen1_el1", A64SysReg_ICC_IGRPEN1_EL1},
+	{"icc_igrpen1_el3", A64SysReg_ICC_IGRPEN1_EL3},
+	{"icc_seien_el1", A64SysReg_ICC_SEIEN_EL1},
+	{"icc_ap0r0_el1", A64SysReg_ICC_AP0R0_EL1},
+	{"icc_ap0r1_el1", A64SysReg_ICC_AP0R1_EL1},
+	{"icc_ap0r2_el1", A64SysReg_ICC_AP0R2_EL1},
+	{"icc_ap0r3_el1", A64SysReg_ICC_AP0R3_EL1},
+	{"icc_ap1r0_el1", A64SysReg_ICC_AP1R0_EL1},
+	{"icc_ap1r1_el1", A64SysReg_ICC_AP1R1_EL1},
+	{"icc_ap1r2_el1", A64SysReg_ICC_AP1R2_EL1},
+	{"icc_ap1r3_el1", A64SysReg_ICC_AP1R3_EL1},
+	{"ich_ap0r0_el2", A64SysReg_ICH_AP0R0_EL2},
+	{"ich_ap0r1_el2", A64SysReg_ICH_AP0R1_EL2},
+	{"ich_ap0r2_el2", A64SysReg_ICH_AP0R2_EL2},
+	{"ich_ap0r3_el2", A64SysReg_ICH_AP0R3_EL2},
+	{"ich_ap1r0_el2", A64SysReg_ICH_AP1R0_EL2},
+	{"ich_ap1r1_el2", A64SysReg_ICH_AP1R1_EL2},
+	{"ich_ap1r2_el2", A64SysReg_ICH_AP1R2_EL2},
+	{"ich_ap1r3_el2", A64SysReg_ICH_AP1R3_EL2},
+	{"ich_hcr_el2", A64SysReg_ICH_HCR_EL2},
+	{"ich_misr_el2", A64SysReg_ICH_MISR_EL2},
+	{"ich_vmcr_el2", A64SysReg_ICH_VMCR_EL2},
+	{"ich_vseir_el2", A64SysReg_ICH_VSEIR_EL2},
+	{"ich_lr0_el2", A64SysReg_ICH_LR0_EL2},
+	{"ich_lr1_el2", A64SysReg_ICH_LR1_EL2},
+	{"ich_lr2_el2", A64SysReg_ICH_LR2_EL2},
+	{"ich_lr3_el2", A64SysReg_ICH_LR3_EL2},
+	{"ich_lr4_el2", A64SysReg_ICH_LR4_EL2},
+	{"ich_lr5_el2", A64SysReg_ICH_LR5_EL2},
+	{"ich_lr6_el2", A64SysReg_ICH_LR6_EL2},
+	{"ich_lr7_el2", A64SysReg_ICH_LR7_EL2},
+	{"ich_lr8_el2", A64SysReg_ICH_LR8_EL2},
+	{"ich_lr9_el2", A64SysReg_ICH_LR9_EL2},
+	{"ich_lr10_el2", A64SysReg_ICH_LR10_EL2},
+	{"ich_lr11_el2", A64SysReg_ICH_LR11_EL2},
+	{"ich_lr12_el2", A64SysReg_ICH_LR12_EL2},
+	{"ich_lr13_el2", A64SysReg_ICH_LR13_EL2},
+	{"ich_lr14_el2", A64SysReg_ICH_LR14_EL2},
+	{"ich_lr15_el2", A64SysReg_ICH_LR15_EL2},
+
+	// Statistical profiling registers
+	{"pmblimitr_el1", A64SysReg_PMBLIMITR_EL1},
+	{"pmbptr_el1", A64SysReg_PMBPTR_EL1},
+	{"pmbsr_el1", A64SysReg_PMBSR_EL1},
+	{"pmscr_el1", A64SysReg_PMSCR_EL1},
+	{"pmscr_el12", A64SysReg_PMSCR_EL12},
+	{"pmscr_el2", A64SysReg_PMSCR_EL2},
+	{"pmsicr_el1", A64SysReg_PMSICR_EL1},
+	{"pmsirr_el1", A64SysReg_PMSIRR_EL1},
+	{"pmsfcr_el1", A64SysReg_PMSFCR_EL1},
+	{"pmsevfr_el1", A64SysReg_PMSEVFR_EL1},
+	{"pmslatfr_el1", A64SysReg_PMSLATFR_EL1}
+};
+
+static A64NamedImmMapper_Mapping CycloneSysRegPairs[] = {
+	{"cpm_ioacc_ctl_el3", A64SysReg_CPM_IOACC_CTL_EL3}
+};
+
+// result must be a big enough buffer: 128 bytes is more than enough
+void A64SysRegMapper_toString(A64SysRegMapper *S, uint32_t Bits, bool *Valid, char *result)
+{
+	int dummy;
+	uint32_t Op0, Op1, CRn, CRm, Op2;
+	char *Op1S, *CRnS, *CRmS, *Op2S;
+	unsigned i;
+
+	// First search the registers shared by all
+	for (i = 0; i < ARR_SIZE(SysRegPairs); ++i) {
+		if (SysRegPairs[i].Value == Bits) {
+			*Valid = true;
+			strcpy(result, SysRegPairs[i].Name);
+			return;
+		}
+	}
+
+	// Next search for target specific registers
+	// if (FeatureBits & AArch64_ProcCyclone) {
+	if (true) {
+		for (i = 0; i < ARR_SIZE(CycloneSysRegPairs); ++i) {
+			if (CycloneSysRegPairs[i].Value == Bits) {
+				*Valid = true;
+				strcpy(result, CycloneSysRegPairs[i].Name);
+				return;
+			}
+		}
+	}
+
+	// Now try the instruction-specific registers (either read-only or
+	// write-only).
+	for (i = 0; i < S->NumInstPairs; ++i) {
+		if (S->InstPairs[i].Value == Bits) {
+			*Valid = true;
+			strcpy(result, S->InstPairs[i].Name);
+			return;
+		}
+	}
+
+	Op0 = (Bits >> 14) & 0x3;
+	Op1 = (Bits >> 11) & 0x7;
+	CRn = (Bits >> 7) & 0xf;
+	CRm = (Bits >> 3) & 0xf;
+	Op2 = Bits & 0x7;
+
+	// Only combinations matching: 11 xxx 1x11 xxxx xxx are valid for a generic
+	// name.
+	if (Op0 != 3 || (CRn != 11 && CRn != 15)) {
+		*Valid = false;
+		return;
+	}
+
+	//assert(Op0 == 3 && (CRn == 11 || CRn == 15) && "Invalid generic sysreg");
+
+	*Valid = true;
+
+	Op1S = utostr(Op1, false);
+	CRnS = utostr(CRn, false);
+	CRmS = utostr(CRm, false);
+	Op2S = utostr(Op2, false);
+
+	//printf("Op1S: %s, CRnS: %s, CRmS: %s, Op2S: %s\n", Op1S, CRnS, CRmS, Op2S);
+	dummy = cs_snprintf(result, 128, "s3_%s_c%s_c%s_%s", Op1S, CRnS, CRmS, Op2S);
+	(void)dummy;
+
+	cs_mem_free(Op1S);
+	cs_mem_free(CRnS);
+	cs_mem_free(CRmS);
+	cs_mem_free(Op2S);
+}
+
+static A64NamedImmMapper_Mapping TLBIPairs[] = {
+	{"ipas2e1is", A64TLBI_IPAS2E1IS},
+	{"ipas2le1is", A64TLBI_IPAS2LE1IS},
+	{"vmalle1is", A64TLBI_VMALLE1IS},
+	{"alle2is", A64TLBI_ALLE2IS},
+	{"alle3is", A64TLBI_ALLE3IS},
+	{"vae1is", A64TLBI_VAE1IS},
+	{"vae2is", A64TLBI_VAE2IS},
+	{"vae3is", A64TLBI_VAE3IS},
+	{"aside1is", A64TLBI_ASIDE1IS},
+	{"vaae1is", A64TLBI_VAAE1IS},
+	{"alle1is", A64TLBI_ALLE1IS},
+	{"vale1is", A64TLBI_VALE1IS},
+	{"vale2is", A64TLBI_VALE2IS},
+	{"vale3is", A64TLBI_VALE3IS},
+	{"vmalls12e1is", A64TLBI_VMALLS12E1IS},
+	{"vaale1is", A64TLBI_VAALE1IS},
+	{"ipas2e1", A64TLBI_IPAS2E1},
+	{"ipas2le1", A64TLBI_IPAS2LE1},
+	{"vmalle1", A64TLBI_VMALLE1},
+	{"alle2", A64TLBI_ALLE2},
+	{"alle3", A64TLBI_ALLE3},
+	{"vae1", A64TLBI_VAE1},
+	{"vae2", A64TLBI_VAE2},
+	{"vae3", A64TLBI_VAE3},
+	{"aside1", A64TLBI_ASIDE1},
+	{"vaae1", A64TLBI_VAAE1},
+	{"alle1", A64TLBI_ALLE1},
+	{"vale1", A64TLBI_VALE1},
+	{"vale2", A64TLBI_VALE2},
+	{"vale3", A64TLBI_VALE3},
+	{"vmalls12e1", A64TLBI_VMALLS12E1},
+	{"vaale1", A64TLBI_VAALE1}
+};
+
+A64NamedImmMapper A64TLBI_TLBIMapper = {
+	TLBIPairs,
+	ARR_SIZE(TLBIPairs),
+	0,
+};
+
+static A64NamedImmMapper_Mapping ATPairs[] = {
+	{"s1e1r", A64AT_S1E1R},
+	{"s1e2r", A64AT_S1E2R},
+	{"s1e3r", A64AT_S1E3R},
+	{"s1e1w", A64AT_S1E1W},
+	{"s1e2w", A64AT_S1E2W},
+	{"s1e3w", A64AT_S1E3W},
+	{"s1e0r", A64AT_S1E0R},
+	{"s1e0w", A64AT_S1E0W},
+	{"s12e1r", A64AT_S12E1R},
+	{"s12e1w", A64AT_S12E1W},
+	{"s12e0r", A64AT_S12E0R},
+	{"s12e0w", A64AT_S12E0W}
+};
+
+A64NamedImmMapper A64AT_ATMapper = {
+	ATPairs,
+	ARR_SIZE(ATPairs),
+	0,
+};
+
+static A64NamedImmMapper_Mapping DBarrierPairs[] = {
+	{"oshld", A64DB_OSHLD},
+	{"oshst", A64DB_OSHST},
+	{"osh", A64DB_OSH},
+	{"nshld", A64DB_NSHLD},
+	{"nshst", A64DB_NSHST},
+	{"nsh", A64DB_NSH},
+	{"ishld", A64DB_ISHLD},
+	{"ishst", A64DB_ISHST},
+	{"ish", A64DB_ISH},
+	{"ld", A64DB_LD},
+	{"st", A64DB_ST},
+	{"sy", A64DB_SY}
+};
+
+A64NamedImmMapper A64DB_DBarrierMapper = {
+	DBarrierPairs,
+	ARR_SIZE(DBarrierPairs),
+	16,
+};
+
+static A64NamedImmMapper_Mapping DCPairs[] = {
+	{"zva", A64DC_ZVA},
+	{"ivac", A64DC_IVAC},
+	{"isw", A64DC_ISW},
+	{"cvac", A64DC_CVAC},
+	{"csw", A64DC_CSW},
+	{"cvau", A64DC_CVAU},
+	{"civac", A64DC_CIVAC},
+	{"cisw", A64DC_CISW}
+};
+
+A64NamedImmMapper A64DC_DCMapper = {
+	DCPairs,
+	ARR_SIZE(DCPairs),
+	0,
+};
+
+static A64NamedImmMapper_Mapping ICPairs[] = {
+	{"ialluis",  A64IC_IALLUIS},
+	{"iallu", A64IC_IALLU},
+	{"ivau", A64IC_IVAU}
+};
+
+A64NamedImmMapper A64IC_ICMapper = {
+	ICPairs,
+	ARR_SIZE(ICPairs),
+	0,
+};
+
+static A64NamedImmMapper_Mapping ISBPairs[] = {
+	{"sy",  A64DB_SY},
+};
+
+A64NamedImmMapper A64ISB_ISBMapper = {
+	ISBPairs,
+	ARR_SIZE(ISBPairs),
+	16,
+};
+
+static A64NamedImmMapper_Mapping PRFMPairs[] = {
+	{"pldl1keep", A64PRFM_PLDL1KEEP},
+	{"pldl1strm", A64PRFM_PLDL1STRM},
+	{"pldl2keep", A64PRFM_PLDL2KEEP},
+	{"pldl2strm", A64PRFM_PLDL2STRM},
+	{"pldl3keep", A64PRFM_PLDL3KEEP},
+	{"pldl3strm", A64PRFM_PLDL3STRM},
+	{"plil1keep", A64PRFM_PLIL1KEEP},
+	{"plil1strm", A64PRFM_PLIL1STRM},
+	{"plil2keep", A64PRFM_PLIL2KEEP},
+	{"plil2strm", A64PRFM_PLIL2STRM},
+	{"plil3keep", A64PRFM_PLIL3KEEP},
+	{"plil3strm", A64PRFM_PLIL3STRM},
+	{"pstl1keep", A64PRFM_PSTL1KEEP},
+	{"pstl1strm", A64PRFM_PSTL1STRM},
+	{"pstl2keep", A64PRFM_PSTL2KEEP},
+	{"pstl2strm", A64PRFM_PSTL2STRM},
+	{"pstl3keep", A64PRFM_PSTL3KEEP},
+	{"pstl3strm", A64PRFM_PSTL3STRM}
+};
+
+A64NamedImmMapper A64PRFM_PRFMMapper = {
+	PRFMPairs,
+	ARR_SIZE(PRFMPairs),
+	32,
+};
+
+static A64NamedImmMapper_Mapping PStatePairs[] = {
+	{"spsel", A64PState_SPSel},
+	{"daifset", A64PState_DAIFSet},
+	{"daifclr", A64PState_DAIFClr},
+	{"pan", A64PState_PAN},
+	{"uao", A64PState_UAO}
+};
+
+A64NamedImmMapper A64PState_PStateMapper = {
+	PStatePairs,
+	ARR_SIZE(PStatePairs),
+	0,
+};
+
+static A64NamedImmMapper_Mapping MRSPairs[] = {
+	{"mdccsr_el0", A64SysReg_MDCCSR_EL0},
+	{"dbgdtrrx_el0", A64SysReg_DBGDTRRX_EL0},
+	{"mdrar_el1", A64SysReg_MDRAR_EL1},
+	{"oslsr_el1", A64SysReg_OSLSR_EL1},
+	{"dbgauthstatus_el1", A64SysReg_DBGAUTHSTATUS_EL1},
+	{"pmceid0_el0", A64SysReg_PMCEID0_EL0},
+	{"pmceid1_el0", A64SysReg_PMCEID1_EL0},
+	{"midr_el1", A64SysReg_MIDR_EL1},
+	{"ccsidr_el1", A64SysReg_CCSIDR_EL1},
+	{"clidr_el1", A64SysReg_CLIDR_EL1},
+	{"ctr_el0", A64SysReg_CTR_EL0},
+	{"mpidr_el1", A64SysReg_MPIDR_EL1},
+	{"revidr_el1", A64SysReg_REVIDR_EL1},
+	{"aidr_el1", A64SysReg_AIDR_EL1},
+	{"dczid_el0", A64SysReg_DCZID_EL0},
+	{"id_pfr0_el1", A64SysReg_ID_PFR0_EL1},
+	{"id_pfr1_el1", A64SysReg_ID_PFR1_EL1},
+	{"id_dfr0_el1", A64SysReg_ID_DFR0_EL1},
+	{"id_afr0_el1", A64SysReg_ID_AFR0_EL1},
+	{"id_mmfr0_el1", A64SysReg_ID_MMFR0_EL1},
+	{"id_mmfr1_el1", A64SysReg_ID_MMFR1_EL1},
+	{"id_mmfr2_el1", A64SysReg_ID_MMFR2_EL1},
+	{"id_mmfr3_el1", A64SysReg_ID_MMFR3_EL1},
+	{"id_mmfr4_el1", A64SysReg_ID_MMFR4_EL1},
+	{"id_isar0_el1", A64SysReg_ID_ISAR0_EL1},
+	{"id_isar1_el1", A64SysReg_ID_ISAR1_EL1},
+	{"id_isar2_el1", A64SysReg_ID_ISAR2_EL1},
+	{"id_isar3_el1", A64SysReg_ID_ISAR3_EL1},
+	{"id_isar4_el1", A64SysReg_ID_ISAR4_EL1},
+	{"id_isar5_el1", A64SysReg_ID_ISAR5_EL1},
+	{"id_aa64pfr0_el1", A64SysReg_ID_A64PFR0_EL1},
+	{"id_aa64pfr1_el1", A64SysReg_ID_A64PFR1_EL1},
+	{"id_aa64dfr0_el1", A64SysReg_ID_A64DFR0_EL1},
+	{"id_aa64dfr1_el1", A64SysReg_ID_A64DFR1_EL1},
+	{"id_aa64afr0_el1", A64SysReg_ID_A64AFR0_EL1},
+	{"id_aa64afr1_el1", A64SysReg_ID_A64AFR1_EL1},
+	{"id_aa64isar0_el1", A64SysReg_ID_A64ISAR0_EL1},
+	{"id_aa64isar1_el1", A64SysReg_ID_A64ISAR1_EL1},
+	{"id_aa64mmfr0_el1", A64SysReg_ID_A64MMFR0_EL1},
+	{"id_aa64mmfr1_el1", A64SysReg_ID_A64MMFR1_EL1},
+	{"id_aa64mmfr2_el1", A64SysReg_ID_A64MMFR2_EL1},
+	{"lorid_el1", A64SysReg_LORID_EL1},
+	{"mvfr0_el1", A64SysReg_MVFR0_EL1},
+	{"mvfr1_el1", A64SysReg_MVFR1_EL1},
+	{"mvfr2_el1", A64SysReg_MVFR2_EL1},
+	{"rvbar_el1", A64SysReg_RVBAR_EL1},
+	{"rvbar_el2", A64SysReg_RVBAR_EL2},
+	{"rvbar_el3", A64SysReg_RVBAR_EL3},
+	{"isr_el1", A64SysReg_ISR_EL1},
+	{"cntpct_el0", A64SysReg_CNTPCT_EL0},
+	{"cntvct_el0", A64SysReg_CNTVCT_EL0},
+
+	// Trace registers
+	{"trcstatr", A64SysReg_TRCSTATR},
+	{"trcidr8", A64SysReg_TRCIDR8},
+	{"trcidr9", A64SysReg_TRCIDR9},
+	{"trcidr10", A64SysReg_TRCIDR10},
+	{"trcidr11", A64SysReg_TRCIDR11},
+	{"trcidr12", A64SysReg_TRCIDR12},
+	{"trcidr13", A64SysReg_TRCIDR13},
+	{"trcidr0", A64SysReg_TRCIDR0},
+	{"trcidr1", A64SysReg_TRCIDR1},
+	{"trcidr2", A64SysReg_TRCIDR2},
+	{"trcidr3", A64SysReg_TRCIDR3},
+	{"trcidr4", A64SysReg_TRCIDR4},
+	{"trcidr5", A64SysReg_TRCIDR5},
+	{"trcidr6", A64SysReg_TRCIDR6},
+	{"trcidr7", A64SysReg_TRCIDR7},
+	{"trcoslsr", A64SysReg_TRCOSLSR},
+	{"trcpdsr", A64SysReg_TRCPDSR},
+	{"trcdevaff0", A64SysReg_TRCDEVAFF0},
+	{"trcdevaff1", A64SysReg_TRCDEVAFF1},
+	{"trclsr", A64SysReg_TRCLSR},
+	{"trcauthstatus", A64SysReg_TRCAUTHSTATUS},
+	{"trcdevarch", A64SysReg_TRCDEVARCH},
+	{"trcdevid", A64SysReg_TRCDEVID},
+	{"trcdevtype", A64SysReg_TRCDEVTYPE},
+	{"trcpidr4", A64SysReg_TRCPIDR4},
+	{"trcpidr5", A64SysReg_TRCPIDR5},
+	{"trcpidr6", A64SysReg_TRCPIDR6},
+	{"trcpidr7", A64SysReg_TRCPIDR7},
+	{"trcpidr0", A64SysReg_TRCPIDR0},
+	{"trcpidr1", A64SysReg_TRCPIDR1},
+	{"trcpidr2", A64SysReg_TRCPIDR2},
+	{"trcpidr3", A64SysReg_TRCPIDR3},
+	{"trccidr0", A64SysReg_TRCCIDR0},
+	{"trccidr1", A64SysReg_TRCCIDR1},
+	{"trccidr2", A64SysReg_TRCCIDR2},
+	{"trccidr3", A64SysReg_TRCCIDR3},
+
+	// GICv3 registers
+	{"icc_iar1_el1", A64SysReg_ICC_IAR1_EL1},
+	{"icc_iar0_el1", A64SysReg_ICC_IAR0_EL1},
+	{"icc_hppir1_el1", A64SysReg_ICC_HPPIR1_EL1},
+	{"icc_hppir0_el1", A64SysReg_ICC_HPPIR0_EL1},
+	{"icc_rpr_el1", A64SysReg_ICC_RPR_EL1},
+	{"ich_vtr_el2", A64SysReg_ICH_VTR_EL2},
+	{"ich_eisr_el2", A64SysReg_ICH_EISR_EL2},
+	{"ich_elsr_el2", A64SysReg_ICH_ELSR_EL2},
+
+	// Statistical profiling registers
+	{"pmsidr_el1", A64SysReg_PMSIDR_EL1},
+	{"pmbidr_el1", A64SysReg_PMBIDR_EL1}
+};
+
+A64SysRegMapper AArch64_MRSMapper = {
+	NULL,
+	MRSPairs,
+	ARR_SIZE(MRSPairs),
+};
+
+static A64NamedImmMapper_Mapping MSRPairs[] = {
+	{"dbgdtrtx_el0", A64SysReg_DBGDTRTX_EL0},
+	{"oslar_el1", A64SysReg_OSLAR_EL1},
+	{"pmswinc_el0", A64SysReg_PMSWINC_EL0},
+
+	// Trace registers
+	{"trcoslar", A64SysReg_TRCOSLAR},
+	{"trclar", A64SysReg_TRCLAR},
+
+	// GICv3 registers
+	{"icc_eoir1_el1", A64SysReg_ICC_EOIR1_EL1},
+	{"icc_eoir0_el1", A64SysReg_ICC_EOIR0_EL1},
+	{"icc_dir_el1", A64SysReg_ICC_DIR_EL1},
+	{"icc_sgi1r_el1", A64SysReg_ICC_SGI1R_EL1},
+	{"icc_asgi1r_el1", A64SysReg_ICC_ASGI1R_EL1},
+	{"icc_sgi0r_el1", A64SysReg_ICC_SGI0R_EL1}
+};
+
+A64SysRegMapper AArch64_MSRMapper = {
+	NULL,
+	MSRPairs,
+	ARR_SIZE(MSRPairs),
+};
+
+#endif
diff --git a/arch/AArch64/AArch64BaseInfo.h b/arch/AArch64/AArch64BaseInfo.h
new file mode 100644
index 0000000..f988e87
--- /dev/null
+++ b/arch/AArch64/AArch64BaseInfo.h
@@ -0,0 +1,1013 @@
+//===-- AArch64BaseInfo.h - Top level definitions for AArch64- --*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains small standalone helper functions and enum definitions for
+// the AArch64 target useful for the compiler back-end and the MC libraries.
+// As such, it deliberately does not include references to LLVM core
+// code gen types, passes, etc..
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_LLVM_AARCH64_BASEINFO_H
+#define CS_LLVM_AARCH64_BASEINFO_H
+
+#include <ctype.h>
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
+#include <stdint.h>
+#endif
+#include <string.h>
+
+#ifndef __cplusplus
+#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)
+#define inline /* inline */
+#endif
+#endif
+
+inline static unsigned getWRegFromXReg(unsigned Reg)
+{
+	switch (Reg) {
+		case ARM64_REG_X0: return ARM64_REG_W0;
+		case ARM64_REG_X1: return ARM64_REG_W1;
+		case ARM64_REG_X2: return ARM64_REG_W2;
+		case ARM64_REG_X3: return ARM64_REG_W3;
+		case ARM64_REG_X4: return ARM64_REG_W4;
+		case ARM64_REG_X5: return ARM64_REG_W5;
+		case ARM64_REG_X6: return ARM64_REG_W6;
+		case ARM64_REG_X7: return ARM64_REG_W7;
+		case ARM64_REG_X8: return ARM64_REG_W8;
+		case ARM64_REG_X9: return ARM64_REG_W9;
+		case ARM64_REG_X10: return ARM64_REG_W10;
+		case ARM64_REG_X11: return ARM64_REG_W11;
+		case ARM64_REG_X12: return ARM64_REG_W12;
+		case ARM64_REG_X13: return ARM64_REG_W13;
+		case ARM64_REG_X14: return ARM64_REG_W14;
+		case ARM64_REG_X15: return ARM64_REG_W15;
+		case ARM64_REG_X16: return ARM64_REG_W16;
+		case ARM64_REG_X17: return ARM64_REG_W17;
+		case ARM64_REG_X18: return ARM64_REG_W18;
+		case ARM64_REG_X19: return ARM64_REG_W19;
+		case ARM64_REG_X20: return ARM64_REG_W20;
+		case ARM64_REG_X21: return ARM64_REG_W21;
+		case ARM64_REG_X22: return ARM64_REG_W22;
+		case ARM64_REG_X23: return ARM64_REG_W23;
+		case ARM64_REG_X24: return ARM64_REG_W24;
+		case ARM64_REG_X25: return ARM64_REG_W25;
+		case ARM64_REG_X26: return ARM64_REG_W26;
+		case ARM64_REG_X27: return ARM64_REG_W27;
+		case ARM64_REG_X28: return ARM64_REG_W28;
+		case ARM64_REG_FP: return ARM64_REG_W29;
+		case ARM64_REG_LR: return ARM64_REG_W30;
+		case ARM64_REG_SP: return ARM64_REG_WSP;
+		case ARM64_REG_XZR: return ARM64_REG_WZR;
+	}
+
+	// For anything else, return it unchanged.
+	return Reg;
+}
+
+// // Enums corresponding to AArch64 condition codes
+// The CondCodes constants map directly to the 4-bit encoding of the
+// condition field for predicated instructions.
+typedef enum A64CC_CondCode { // Meaning (integer)     Meaning (floating-point)
+	A64CC_EQ = 0,        // Equal                      Equal
+	A64CC_NE,            // Not equal                  Not equal, or unordered
+	A64CC_HS,            // Unsigned higher or same    >, ==, or unordered
+	A64CC_LO,            // Unsigned lower or same     Less than
+	A64CC_MI,            // Minus, negative            Less than
+	A64CC_PL,            // Plus, positive or zero     >, ==, or unordered
+	A64CC_VS,            // Overflow                   Unordered
+	A64CC_VC,            // No overflow                Ordered
+	A64CC_HI,            // Unsigned higher            Greater than, or unordered
+	A64CC_LS,            // Unsigned lower or same     Less than or equal
+	A64CC_GE,            // Greater than or equal      Greater than or equal
+	A64CC_LT,            // Less than                  Less than, or unordered
+	A64CC_GT,            // Signed greater than        Greater than
+	A64CC_LE,            // Signed less than or equal  <, ==, or unordered
+	A64CC_AL,            // Always (unconditional)     Always (unconditional)
+	A64CC_NV,             // Always (unconditional)     Always (unconditional)
+	// Note the NV exists purely to disassemble 0b1111. Execution is "always".
+	A64CC_Invalid
+} A64CC_CondCode;
+
+inline static char *getCondCodeName(A64CC_CondCode CC)
+{
+	switch (CC) {
+		default: return NULL;	// never reach
+		case A64CC_EQ:  return "eq";
+		case A64CC_NE:  return "ne";
+		case A64CC_HS:  return "hs";
+		case A64CC_LO:  return "lo";
+		case A64CC_MI:  return "mi";
+		case A64CC_PL:  return "pl";
+		case A64CC_VS:  return "vs";
+		case A64CC_VC:  return "vc";
+		case A64CC_HI:  return "hi";
+		case A64CC_LS:  return "ls";
+		case A64CC_GE:  return "ge";
+		case A64CC_LT:  return "lt";
+		case A64CC_GT:  return "gt";
+		case A64CC_LE:  return "le";
+		case A64CC_AL:  return "al";
+		case A64CC_NV:  return "nv";
+	}
+}
+
+inline static A64CC_CondCode getInvertedCondCode(A64CC_CondCode Code)
+{
+	// To reverse a condition it's necessary to only invert the low bit:
+	return (A64CC_CondCode)((unsigned)Code ^ 0x1);
+}
+
+/// Instances of this class can perform bidirectional mapping from random
+/// identifier strings to operand encodings. For example "MSR" takes a named
+/// system-register which must be encoded somehow and decoded for printing. This
+/// central location means that the information for those transformations is not
+/// duplicated and remains in sync.
+///
+/// FIXME: currently the algorithm is a completely unoptimised linear
+/// search. Obviously this could be improved, but we would probably want to work
+/// out just how often these instructions are emitted before working on it. It
+/// might even be optimal to just reorder the tables for the common instructions
+/// rather than changing the algorithm.
+typedef struct A64NamedImmMapper_Mapping {
+	char *Name;
+	uint32_t Value;
+} A64NamedImmMapper_Mapping;
+
+typedef struct A64NamedImmMapper {
+	A64NamedImmMapper_Mapping *Pairs;
+	size_t NumPairs;
+	uint32_t TooBigImm;
+} A64NamedImmMapper;
+
+typedef struct A64SysRegMapper {
+	A64NamedImmMapper_Mapping *SysRegPairs;
+	A64NamedImmMapper_Mapping *InstPairs;
+	size_t NumInstPairs;
+} A64SysRegMapper;
+
+extern A64SysRegMapper AArch64_MSRMapper;
+extern A64SysRegMapper AArch64_MRSMapper;
+
+extern A64NamedImmMapper A64DB_DBarrierMapper;
+extern A64NamedImmMapper A64AT_ATMapper;
+extern A64NamedImmMapper A64DC_DCMapper;
+extern A64NamedImmMapper A64IC_ICMapper;
+extern A64NamedImmMapper A64ISB_ISBMapper;
+extern A64NamedImmMapper A64PRFM_PRFMMapper;
+extern A64NamedImmMapper A64PState_PStateMapper;
+extern A64NamedImmMapper A64TLBI_TLBIMapper;
+
+enum {
+	A64AT_Invalid = -1,    // Op0 Op1  CRn   CRm   Op2
+	A64AT_S1E1R = 0x43c0,  // 01  000  0111  1000  000
+	A64AT_S1E2R = 0x63c0,  // 01  100  0111  1000  000
+	A64AT_S1E3R = 0x73c0,  // 01  110  0111  1000  000
+	A64AT_S1E1W = 0x43c1,  // 01  000  0111  1000  001
+	A64AT_S1E2W = 0x63c1,  // 01  100  0111  1000  001
+	A64AT_S1E3W = 0x73c1,  // 01  110  0111  1000  001
+	A64AT_S1E0R = 0x43c2,  // 01  000  0111  1000  010
+	A64AT_S1E0W = 0x43c3,  // 01  000  0111  1000  011
+	A64AT_S12E1R = 0x63c4, // 01  100  0111  1000  100
+	A64AT_S12E1W = 0x63c5, // 01  100  0111  1000  101
+	A64AT_S12E0R = 0x63c6, // 01  100  0111  1000  110
+	A64AT_S12E0W = 0x63c7  // 01  100  0111  1000  111
+};
+
+enum A64DBValues {
+	A64DB_Invalid = -1,
+	A64DB_OSHLD = 0x1,
+	A64DB_OSHST = 0x2,
+	A64DB_OSH =   0x3,
+	A64DB_NSHLD = 0x5,
+	A64DB_NSHST = 0x6,
+	A64DB_NSH =   0x7,
+	A64DB_ISHLD = 0x9,
+	A64DB_ISHST = 0xa,
+	A64DB_ISH =   0xb,
+	A64DB_LD =    0xd,
+	A64DB_ST =    0xe,
+	A64DB_SY =    0xf
+};
+
+enum A64DCValues {
+	A64DC_Invalid = -1,   // Op1  CRn   CRm   Op2
+	A64DC_ZVA   = 0x5ba1, // 01  011  0111  0100  001
+	A64DC_IVAC  = 0x43b1, // 01  000  0111  0110  001
+	A64DC_ISW   = 0x43b2, // 01  000  0111  0110  010
+	A64DC_CVAC  = 0x5bd1, // 01  011  0111  1010  001
+	A64DC_CSW   = 0x43d2, // 01  000  0111  1010  010
+	A64DC_CVAU  = 0x5bd9, // 01  011  0111  1011  001
+	A64DC_CIVAC = 0x5bf1, // 01  011  0111  1110  001
+	A64DC_CISW  = 0x43f2  // 01  000  0111  1110  010
+};
+
+enum A64ICValues {
+	A64IC_Invalid = -1,     // Op1  CRn   CRm   Op2
+	A64IC_IALLUIS = 0x0388, // 000  0111  0001  000
+	A64IC_IALLU = 0x03a8,   // 000  0111  0101  000
+	A64IC_IVAU = 0x1ba9     // 011  0111  0101  001
+};
+
+enum A64ISBValues {
+	A64ISB_Invalid = -1,
+	A64ISB_SY = 0xf
+};
+
+enum A64PRFMValues {
+	A64PRFM_Invalid = -1,
+	A64PRFM_PLDL1KEEP = 0x00,
+	A64PRFM_PLDL1STRM = 0x01,
+	A64PRFM_PLDL2KEEP = 0x02,
+	A64PRFM_PLDL2STRM = 0x03,
+	A64PRFM_PLDL3KEEP = 0x04,
+	A64PRFM_PLDL3STRM = 0x05,
+	A64PRFM_PLIL1KEEP = 0x08,
+	A64PRFM_PLIL1STRM = 0x09,
+	A64PRFM_PLIL2KEEP = 0x0a,
+	A64PRFM_PLIL2STRM = 0x0b,
+	A64PRFM_PLIL3KEEP = 0x0c,
+	A64PRFM_PLIL3STRM = 0x0d,
+	A64PRFM_PSTL1KEEP = 0x10,
+	A64PRFM_PSTL1STRM = 0x11,
+	A64PRFM_PSTL2KEEP = 0x12,
+	A64PRFM_PSTL2STRM = 0x13,
+	A64PRFM_PSTL3KEEP = 0x14,
+	A64PRFM_PSTL3STRM = 0x15
+};
+
+enum A64PStateValues {
+	A64PState_Invalid = -1,
+	A64PState_SPSel = 0x05,
+	A64PState_DAIFSet = 0x1e,
+	A64PState_DAIFClr = 0x1f,
+	A64PState_PAN	= 0x4,
+	A64PState_UAO	= 0x3
+};
+
+typedef enum A64SE_ShiftExtSpecifiers {
+	A64SE_Invalid = -1,
+	A64SE_LSL,
+	A64SE_MSL,
+	A64SE_LSR,
+	A64SE_ASR,
+	A64SE_ROR,
+
+	A64SE_UXTB,
+	A64SE_UXTH,
+	A64SE_UXTW,
+	A64SE_UXTX,
+
+	A64SE_SXTB,
+	A64SE_SXTH,
+	A64SE_SXTW,
+	A64SE_SXTX
+} A64SE_ShiftExtSpecifiers;
+
+typedef enum A64Layout_VectorLayout {
+	A64Layout_Invalid = -1,
+	A64Layout_VL_8B,
+	A64Layout_VL_4H,
+	A64Layout_VL_2S,
+	A64Layout_VL_1D,
+
+	A64Layout_VL_16B,
+	A64Layout_VL_8H,
+	A64Layout_VL_4S,
+	A64Layout_VL_2D,
+
+	// Bare layout for the 128-bit vector
+	// (only show ".b", ".h", ".s", ".d" without vector number)
+	A64Layout_VL_B,
+	A64Layout_VL_H,
+	A64Layout_VL_S,
+	A64Layout_VL_D
+} A64Layout_VectorLayout;
+
+inline static char *A64VectorLayoutToString(A64Layout_VectorLayout Layout)
+{
+	switch (Layout) {
+		case A64Layout_VL_8B:  return ".8b";
+		case A64Layout_VL_4H:  return ".4h";
+		case A64Layout_VL_2S:  return ".2s";
+		case A64Layout_VL_1D:  return ".1d";
+		case A64Layout_VL_16B:  return ".16b";
+		case A64Layout_VL_8H:  return ".8h";
+		case A64Layout_VL_4S:  return ".4s";
+		case A64Layout_VL_2D:  return ".2d";
+		case A64Layout_VL_B:  return ".b";
+		case A64Layout_VL_H:  return ".h";
+		case A64Layout_VL_S:  return ".s";
+		case A64Layout_VL_D:  return ".d";
+		default: return NULL;	// never reach
+	}
+}
+
+enum A64SysRegROValues {
+	A64SysReg_MDCCSR_EL0        = 0x9808, // 10  011  0000  0001  000
+	A64SysReg_DBGDTRRX_EL0      = 0x9828, // 10  011  0000  0101  000
+	A64SysReg_MDRAR_EL1         = 0x8080, // 10  000  0001  0000  000
+	A64SysReg_OSLSR_EL1         = 0x808c, // 10  000  0001  0001  100
+	A64SysReg_DBGAUTHSTATUS_EL1 = 0x83f6, // 10  000  0111  1110  110
+	A64SysReg_PMCEID0_EL0       = 0xdce6, // 11  011  1001  1100  110
+	A64SysReg_PMCEID1_EL0       = 0xdce7, // 11  011  1001  1100  111
+	A64SysReg_MIDR_EL1          = 0xc000, // 11  000  0000  0000  000
+	A64SysReg_CCSIDR_EL1        = 0xc800, // 11  001  0000  0000  000
+	A64SysReg_CLIDR_EL1         = 0xc801, // 11  001  0000  0000  001
+	A64SysReg_CTR_EL0           = 0xd801, // 11  011  0000  0000  001
+	A64SysReg_MPIDR_EL1         = 0xc005, // 11  000  0000  0000  101
+	A64SysReg_REVIDR_EL1        = 0xc006, // 11  000  0000  0000  110
+	A64SysReg_AIDR_EL1          = 0xc807, // 11  001  0000  0000  111
+	A64SysReg_DCZID_EL0         = 0xd807, // 11  011  0000  0000  111
+	A64SysReg_ID_PFR0_EL1       = 0xc008, // 11  000  0000  0001  000
+	A64SysReg_ID_PFR1_EL1       = 0xc009, // 11  000  0000  0001  001
+	A64SysReg_ID_DFR0_EL1       = 0xc00a, // 11  000  0000  0001  010
+	A64SysReg_ID_AFR0_EL1       = 0xc00b, // 11  000  0000  0001  011
+	A64SysReg_ID_MMFR0_EL1      = 0xc00c, // 11  000  0000  0001  100
+	A64SysReg_ID_MMFR1_EL1      = 0xc00d, // 11  000  0000  0001  101
+	A64SysReg_ID_MMFR2_EL1      = 0xc00e, // 11  000  0000  0001  110
+	A64SysReg_ID_MMFR3_EL1      = 0xc00f, // 11  000  0000  0001  111
+	A64SysReg_ID_MMFR4_EL1      = 0xc016, // 11  000  0000  0010  110
+	A64SysReg_ID_ISAR0_EL1      = 0xc010, // 11  000  0000  0010  000
+	A64SysReg_ID_ISAR1_EL1      = 0xc011, // 11  000  0000  0010  001
+	A64SysReg_ID_ISAR2_EL1      = 0xc012, // 11  000  0000  0010  010
+	A64SysReg_ID_ISAR3_EL1      = 0xc013, // 11  000  0000  0010  011
+	A64SysReg_ID_ISAR4_EL1      = 0xc014, // 11  000  0000  0010  100
+	A64SysReg_ID_ISAR5_EL1      = 0xc015, // 11  000  0000  0010  101
+	A64SysReg_ID_A64PFR0_EL1   = 0xc020, // 11  000  0000  0100  000
+	A64SysReg_ID_A64PFR1_EL1   = 0xc021, // 11  000  0000  0100  001
+	A64SysReg_ID_A64DFR0_EL1   = 0xc028, // 11  000  0000  0101  000
+	A64SysReg_ID_A64DFR1_EL1   = 0xc029, // 11  000  0000  0101  001
+	A64SysReg_ID_A64AFR0_EL1   = 0xc02c, // 11  000  0000  0101  100
+	A64SysReg_ID_A64AFR1_EL1   = 0xc02d, // 11  000  0000  0101  101
+	A64SysReg_ID_A64ISAR0_EL1  = 0xc030, // 11  000  0000  0110  000
+	A64SysReg_ID_A64ISAR1_EL1  = 0xc031, // 11  000  0000  0110  001
+	A64SysReg_ID_A64MMFR0_EL1  = 0xc038, // 11  000  0000  0111  000
+	A64SysReg_ID_A64MMFR1_EL1  = 0xc039, // 11  000  0000  0111  001
+	A64SysReg_ID_A64MMFR2_EL1  = 0xC03A, // 11  000  0000  0111  010
+  	A64SysReg_LORC_EL1         = 0xc523, // 11  000  1010  0100  011
+  	A64SysReg_LOREA_EL1        = 0xc521, // 11  000  1010  0100  001
+  	A64SysReg_LORID_EL1        = 0xc527, // 11  000  1010  0100  111
+  	A64SysReg_LORN_EL1         = 0xc522, // 11  000  1010  0100  010
+  	A64SysReg_LORSA_EL1        = 0xc520, // 11  000  1010  0100  000
+	A64SysReg_MVFR0_EL1         = 0xc018, // 11  000  0000  0011  000
+	A64SysReg_MVFR1_EL1         = 0xc019, // 11  000  0000  0011  001
+	A64SysReg_MVFR2_EL1         = 0xc01a, // 11  000  0000  0011  010
+	A64SysReg_RVBAR_EL1         = 0xc601, // 11  000  1100  0000  001
+	A64SysReg_RVBAR_EL2         = 0xe601, // 11  100  1100  0000  001
+	A64SysReg_RVBAR_EL3         = 0xf601, // 11  110  1100  0000  001
+	A64SysReg_ISR_EL1           = 0xc608, // 11  000  1100  0001  000
+	A64SysReg_CNTPCT_EL0        = 0xdf01, // 11  011  1110  0000  001
+	A64SysReg_CNTVCT_EL0        = 0xdf02,  // 11  011  1110  0000  010
+
+	// Trace registers
+	A64SysReg_TRCSTATR          = 0x8818, // 10  001  0000  0011  000
+	A64SysReg_TRCIDR8           = 0x8806, // 10  001  0000  0000  110
+	A64SysReg_TRCIDR9           = 0x880e, // 10  001  0000  0001  110
+	A64SysReg_TRCIDR10          = 0x8816, // 10  001  0000  0010  110
+	A64SysReg_TRCIDR11          = 0x881e, // 10  001  0000  0011  110
+	A64SysReg_TRCIDR12          = 0x8826, // 10  001  0000  0100  110
+	A64SysReg_TRCIDR13          = 0x882e, // 10  001  0000  0101  110
+	A64SysReg_TRCIDR0           = 0x8847, // 10  001  0000  1000  111
+	A64SysReg_TRCIDR1           = 0x884f, // 10  001  0000  1001  111
+	A64SysReg_TRCIDR2           = 0x8857, // 10  001  0000  1010  111
+	A64SysReg_TRCIDR3           = 0x885f, // 10  001  0000  1011  111
+	A64SysReg_TRCIDR4           = 0x8867, // 10  001  0000  1100  111
+	A64SysReg_TRCIDR5           = 0x886f, // 10  001  0000  1101  111
+	A64SysReg_TRCIDR6           = 0x8877, // 10  001  0000  1110  111
+	A64SysReg_TRCIDR7           = 0x887f, // 10  001  0000  1111  111
+	A64SysReg_TRCOSLSR          = 0x888c, // 10  001  0001  0001  100
+	A64SysReg_TRCPDSR           = 0x88ac, // 10  001  0001  0101  100
+	A64SysReg_TRCDEVAFF0        = 0x8bd6, // 10  001  0111  1010  110
+	A64SysReg_TRCDEVAFF1        = 0x8bde, // 10  001  0111  1011  110
+	A64SysReg_TRCLSR            = 0x8bee, // 10  001  0111  1101  110
+	A64SysReg_TRCAUTHSTATUS     = 0x8bf6, // 10  001  0111  1110  110
+	A64SysReg_TRCDEVARCH        = 0x8bfe, // 10  001  0111  1111  110
+	A64SysReg_TRCDEVID          = 0x8b97, // 10  001  0111  0010  111
+	A64SysReg_TRCDEVTYPE        = 0x8b9f, // 10  001  0111  0011  111
+	A64SysReg_TRCPIDR4          = 0x8ba7, // 10  001  0111  0100  111
+	A64SysReg_TRCPIDR5          = 0x8baf, // 10  001  0111  0101  111
+	A64SysReg_TRCPIDR6          = 0x8bb7, // 10  001  0111  0110  111
+	A64SysReg_TRCPIDR7          = 0x8bbf, // 10  001  0111  0111  111
+	A64SysReg_TRCPIDR0          = 0x8bc7, // 10  001  0111  1000  111
+	A64SysReg_TRCPIDR1          = 0x8bcf, // 10  001  0111  1001  111
+	A64SysReg_TRCPIDR2          = 0x8bd7, // 10  001  0111  1010  111
+	A64SysReg_TRCPIDR3          = 0x8bdf, // 10  001  0111  1011  111
+	A64SysReg_TRCCIDR0          = 0x8be7, // 10  001  0111  1100  111
+	A64SysReg_TRCCIDR1          = 0x8bef, // 10  001  0111  1101  111
+	A64SysReg_TRCCIDR2          = 0x8bf7, // 10  001  0111  1110  111
+	A64SysReg_TRCCIDR3          = 0x8bff, // 10  001  0111  1111  111
+
+	// GICv3 registers
+	A64SysReg_ICC_IAR1_EL1      = 0xc660, // 11  000  1100  1100  000
+	A64SysReg_ICC_IAR0_EL1      = 0xc640, // 11  000  1100  1000  000
+	A64SysReg_ICC_HPPIR1_EL1    = 0xc662, // 11  000  1100  1100  010
+	A64SysReg_ICC_HPPIR0_EL1    = 0xc642, // 11  000  1100  1000  010
+	A64SysReg_ICC_RPR_EL1       = 0xc65b, // 11  000  1100  1011  011
+	A64SysReg_ICH_VTR_EL2       = 0xe659, // 11  100  1100  1011  001
+	A64SysReg_ICH_EISR_EL2      = 0xe65b, // 11  100  1100  1011  011
+	A64SysReg_ICH_ELSR_EL2      = 0xe65d  // 11  100  1100  1011  101
+};
+
+enum A64SysRegWOValues {
+	A64SysReg_DBGDTRTX_EL0      = 0x9828, // 10  011  0000  0101  000
+	A64SysReg_OSLAR_EL1         = 0x8084, // 10  000  0001  0000  100
+	A64SysReg_PMSWINC_EL0       = 0xdce4,  // 11  011  1001  1100  100
+
+	// Trace Registers
+	A64SysReg_TRCOSLAR          = 0x8884, // 10  001  0001  0000  100
+	A64SysReg_TRCLAR            = 0x8be6, // 10  001  0111  1100  110
+
+	// GICv3 registers
+	A64SysReg_ICC_EOIR1_EL1     = 0xc661, // 11  000  1100  1100  001
+	A64SysReg_ICC_EOIR0_EL1     = 0xc641, // 11  000  1100  1000  001
+	A64SysReg_ICC_DIR_EL1       = 0xc659, // 11  000  1100  1011  001
+	A64SysReg_ICC_SGI1R_EL1     = 0xc65d, // 11  000  1100  1011  101
+	A64SysReg_ICC_ASGI1R_EL1    = 0xc65e, // 11  000  1100  1011  110
+	A64SysReg_ICC_SGI0R_EL1     = 0xc65f  // 11  000  1100  1011  111
+};
+
+enum A64SysRegValues {
+	A64SysReg_Invalid = -1,               // Op0 Op1  CRn   CRm   Op2
+	A64SysReg_PAN               = 0xc213, // 11  000  0100  0010  011
+	A64SysReg_UAO               = 0xc214, // 11  000  0100  0010  100
+	A64SysReg_OSDTRRX_EL1       = 0x8002, // 10  000  0000  0000  010
+	A64SysReg_OSDTRTX_EL1       = 0x801a, // 10  000  0000  0011  010
+	A64SysReg_TEECR32_EL1       = 0x9000, // 10  010  0000  0000  000
+	A64SysReg_MDCCINT_EL1       = 0x8010, // 10  000  0000  0010  000
+	A64SysReg_MDSCR_EL1         = 0x8012, // 10  000  0000  0010  010
+	A64SysReg_DBGDTR_EL0        = 0x9820, // 10  011  0000  0100  000
+	A64SysReg_OSECCR_EL1        = 0x8032, // 10  000  0000  0110  010
+	A64SysReg_DBGVCR32_EL2      = 0xa038, // 10  100  0000  0111  000
+	A64SysReg_DBGBVR0_EL1       = 0x8004, // 10  000  0000  0000  100
+	A64SysReg_DBGBVR1_EL1       = 0x800c, // 10  000  0000  0001  100
+	A64SysReg_DBGBVR2_EL1       = 0x8014, // 10  000  0000  0010  100
+	A64SysReg_DBGBVR3_EL1       = 0x801c, // 10  000  0000  0011  100
+	A64SysReg_DBGBVR4_EL1       = 0x8024, // 10  000  0000  0100  100
+	A64SysReg_DBGBVR5_EL1       = 0x802c, // 10  000  0000  0101  100
+	A64SysReg_DBGBVR6_EL1       = 0x8034, // 10  000  0000  0110  100
+	A64SysReg_DBGBVR7_EL1       = 0x803c, // 10  000  0000  0111  100
+	A64SysReg_DBGBVR8_EL1       = 0x8044, // 10  000  0000  1000  100
+	A64SysReg_DBGBVR9_EL1       = 0x804c, // 10  000  0000  1001  100
+	A64SysReg_DBGBVR10_EL1      = 0x8054, // 10  000  0000  1010  100
+	A64SysReg_DBGBVR11_EL1      = 0x805c, // 10  000  0000  1011  100
+	A64SysReg_DBGBVR12_EL1      = 0x8064, // 10  000  0000  1100  100
+	A64SysReg_DBGBVR13_EL1      = 0x806c, // 10  000  0000  1101  100
+	A64SysReg_DBGBVR14_EL1      = 0x8074, // 10  000  0000  1110  100
+	A64SysReg_DBGBVR15_EL1      = 0x807c, // 10  000  0000  1111  100
+	A64SysReg_DBGBCR0_EL1       = 0x8005, // 10  000  0000  0000  101
+	A64SysReg_DBGBCR1_EL1       = 0x800d, // 10  000  0000  0001  101
+	A64SysReg_DBGBCR2_EL1       = 0x8015, // 10  000  0000  0010  101
+	A64SysReg_DBGBCR3_EL1       = 0x801d, // 10  000  0000  0011  101
+	A64SysReg_DBGBCR4_EL1       = 0x8025, // 10  000  0000  0100  101
+	A64SysReg_DBGBCR5_EL1       = 0x802d, // 10  000  0000  0101  101
+	A64SysReg_DBGBCR6_EL1       = 0x8035, // 10  000  0000  0110  101
+	A64SysReg_DBGBCR7_EL1       = 0x803d, // 10  000  0000  0111  101
+	A64SysReg_DBGBCR8_EL1       = 0x8045, // 10  000  0000  1000  101
+	A64SysReg_DBGBCR9_EL1       = 0x804d, // 10  000  0000  1001  101
+	A64SysReg_DBGBCR10_EL1      = 0x8055, // 10  000  0000  1010  101
+	A64SysReg_DBGBCR11_EL1      = 0x805d, // 10  000  0000  1011  101
+	A64SysReg_DBGBCR12_EL1      = 0x8065, // 10  000  0000  1100  101
+	A64SysReg_DBGBCR13_EL1      = 0x806d, // 10  000  0000  1101  101
+	A64SysReg_DBGBCR14_EL1      = 0x8075, // 10  000  0000  1110  101
+	A64SysReg_DBGBCR15_EL1      = 0x807d, // 10  000  0000  1111  101
+	A64SysReg_DBGWVR0_EL1       = 0x8006, // 10  000  0000  0000  110
+	A64SysReg_DBGWVR1_EL1       = 0x800e, // 10  000  0000  0001  110
+	A64SysReg_DBGWVR2_EL1       = 0x8016, // 10  000  0000  0010  110
+	A64SysReg_DBGWVR3_EL1       = 0x801e, // 10  000  0000  0011  110
+	A64SysReg_DBGWVR4_EL1       = 0x8026, // 10  000  0000  0100  110
+	A64SysReg_DBGWVR5_EL1       = 0x802e, // 10  000  0000  0101  110
+	A64SysReg_DBGWVR6_EL1       = 0x8036, // 10  000  0000  0110  110
+	A64SysReg_DBGWVR7_EL1       = 0x803e, // 10  000  0000  0111  110
+	A64SysReg_DBGWVR8_EL1       = 0x8046, // 10  000  0000  1000  110
+	A64SysReg_DBGWVR9_EL1       = 0x804e, // 10  000  0000  1001  110
+	A64SysReg_DBGWVR10_EL1      = 0x8056, // 10  000  0000  1010  110
+	A64SysReg_DBGWVR11_EL1      = 0x805e, // 10  000  0000  1011  110
+	A64SysReg_DBGWVR12_EL1      = 0x8066, // 10  000  0000  1100  110
+	A64SysReg_DBGWVR13_EL1      = 0x806e, // 10  000  0000  1101  110
+	A64SysReg_DBGWVR14_EL1      = 0x8076, // 10  000  0000  1110  110
+	A64SysReg_DBGWVR15_EL1      = 0x807e, // 10  000  0000  1111  110
+	A64SysReg_DBGWCR0_EL1       = 0x8007, // 10  000  0000  0000  111
+	A64SysReg_DBGWCR1_EL1       = 0x800f, // 10  000  0000  0001  111
+	A64SysReg_DBGWCR2_EL1       = 0x8017, // 10  000  0000  0010  111
+	A64SysReg_DBGWCR3_EL1       = 0x801f, // 10  000  0000  0011  111
+	A64SysReg_DBGWCR4_EL1       = 0x8027, // 10  000  0000  0100  111
+	A64SysReg_DBGWCR5_EL1       = 0x802f, // 10  000  0000  0101  111
+	A64SysReg_DBGWCR6_EL1       = 0x8037, // 10  000  0000  0110  111
+	A64SysReg_DBGWCR7_EL1       = 0x803f, // 10  000  0000  0111  111
+	A64SysReg_DBGWCR8_EL1       = 0x8047, // 10  000  0000  1000  111
+	A64SysReg_DBGWCR9_EL1       = 0x804f, // 10  000  0000  1001  111
+	A64SysReg_DBGWCR10_EL1      = 0x8057, // 10  000  0000  1010  111
+	A64SysReg_DBGWCR11_EL1      = 0x805f, // 10  000  0000  1011  111
+	A64SysReg_DBGWCR12_EL1      = 0x8067, // 10  000  0000  1100  111
+	A64SysReg_DBGWCR13_EL1      = 0x806f, // 10  000  0000  1101  111
+	A64SysReg_DBGWCR14_EL1      = 0x8077, // 10  000  0000  1110  111
+	A64SysReg_DBGWCR15_EL1      = 0x807f, // 10  000  0000  1111  111
+	A64SysReg_TEEHBR32_EL1      = 0x9080, // 10  010  0001  0000  000
+	A64SysReg_OSDLR_EL1         = 0x809c, // 10  000  0001  0011  100
+	A64SysReg_DBGPRCR_EL1       = 0x80a4, // 10  000  0001  0100  100
+	A64SysReg_DBGCLAIMSET_EL1   = 0x83c6, // 10  000  0111  1000  110
+	A64SysReg_DBGCLAIMCLR_EL1   = 0x83ce, // 10  000  0111  1001  110
+	A64SysReg_CSSELR_EL1        = 0xd000, // 11  010  0000  0000  000
+	A64SysReg_VPIDR_EL2         = 0xe000, // 11  100  0000  0000  000
+	A64SysReg_VMPIDR_EL2        = 0xe005, // 11  100  0000  0000  101
+	A64SysReg_CPACR_EL1         = 0xc082, // 11  000  0001  0000  010
+  	A64SysReg_CPACR_EL12        = 0xe882, // 11  101  0001  0000  010
+	A64SysReg_SCTLR_EL1         = 0xc080, // 11  000  0001  0000  000
+  	A64SysReg_SCTLR_EL12        = 0xe880, // 11  101  0001  0000  000
+	A64SysReg_SCTLR_EL2         = 0xe080, // 11  100  0001  0000  000
+	A64SysReg_SCTLR_EL3         = 0xf080, // 11  110  0001  0000  000
+	A64SysReg_ACTLR_EL1         = 0xc081, // 11  000  0001  0000  001
+	A64SysReg_ACTLR_EL2         = 0xe081, // 11  100  0001  0000  001
+	A64SysReg_ACTLR_EL3         = 0xf081, // 11  110  0001  0000  001
+	A64SysReg_HCR_EL2           = 0xe088, // 11  100  0001  0001  000
+	A64SysReg_SCR_EL3           = 0xf088, // 11  110  0001  0001  000
+	A64SysReg_MDCR_EL2          = 0xe089, // 11  100  0001  0001  001
+	A64SysReg_SDER32_EL3        = 0xf089, // 11  110  0001  0001  001
+	A64SysReg_CPTR_EL2          = 0xe08a, // 11  100  0001  0001  010
+	A64SysReg_CPTR_EL3          = 0xf08a, // 11  110  0001  0001  010
+	A64SysReg_HSTR_EL2          = 0xe08b, // 11  100  0001  0001  011
+	A64SysReg_HACR_EL2          = 0xe08f, // 11  100  0001  0001  111
+	A64SysReg_MDCR_EL3          = 0xf099, // 11  110  0001  0011  001
+	A64SysReg_TTBR0_EL1         = 0xc100, // 11  000  0010  0000  000
+  	A64SysReg_TTBR0_EL12        = 0xe900, // 11  101  0010  0000  000
+	A64SysReg_TTBR0_EL2         = 0xe100, // 11  100  0010  0000  000
+	A64SysReg_TTBR0_EL3         = 0xf100, // 11  110  0010  0000  000
+	A64SysReg_TTBR1_EL1         = 0xc101, // 11  000  0010  0000  001
+  	A64SysReg_TTBR1_EL12        = 0xe901, // 11  101  0010  0000  001
+  	A64SysReg_TTBR1_EL2         = 0xe101, // 11  100  0010  0000  001
+	A64SysReg_TCR_EL1           = 0xc102, // 11  000  0010  0000  010
+  	A64SysReg_TCR_EL12          = 0xe902, // 11  101  0010  0000  010
+	A64SysReg_TCR_EL2           = 0xe102, // 11  100  0010  0000  010
+	A64SysReg_TCR_EL3           = 0xf102, // 11  110  0010  0000  010
+	A64SysReg_VTTBR_EL2         = 0xe108, // 11  100  0010  0001  000
+	A64SysReg_VTCR_EL2          = 0xe10a, // 11  100  0010  0001  010
+	A64SysReg_DACR32_EL2        = 0xe180, // 11  100  0011  0000  000
+	A64SysReg_SPSR_EL1          = 0xc200, // 11  000  0100  0000  000
+  	A64SysReg_SPSR_EL12         = 0xea00, // 11  101  0100  0000  000
+	A64SysReg_SPSR_EL2          = 0xe200, // 11  100  0100  0000  000
+	A64SysReg_SPSR_EL3          = 0xf200, // 11  110  0100  0000  000
+	A64SysReg_ELR_EL1           = 0xc201, // 11  000  0100  0000  001
+  	A64SysReg_ELR_EL12          = 0xea01, // 11  101  0100  0000  001
+	A64SysReg_ELR_EL2           = 0xe201, // 11  100  0100  0000  001
+	A64SysReg_ELR_EL3           = 0xf201, // 11  110  0100  0000  001
+	A64SysReg_SP_EL0            = 0xc208, // 11  000  0100  0001  000
+	A64SysReg_SP_EL1            = 0xe208, // 11  100  0100  0001  000
+	A64SysReg_SP_EL2            = 0xf208, // 11  110  0100  0001  000
+	A64SysReg_SPSel             = 0xc210, // 11  000  0100  0010  000
+	A64SysReg_NZCV              = 0xda10, // 11  011  0100  0010  000
+	A64SysReg_DAIF              = 0xda11, // 11  011  0100  0010  001
+	A64SysReg_CurrentEL         = 0xc212, // 11  000  0100  0010  010
+	A64SysReg_SPSR_irq          = 0xe218, // 11  100  0100  0011  000
+	A64SysReg_SPSR_abt          = 0xe219, // 11  100  0100  0011  001
+	A64SysReg_SPSR_und          = 0xe21a, // 11  100  0100  0011  010
+	A64SysReg_SPSR_fiq          = 0xe21b, // 11  100  0100  0011  011
+	A64SysReg_FPCR              = 0xda20, // 11  011  0100  0100  000
+	A64SysReg_FPSR              = 0xda21, // 11  011  0100  0100  001
+	A64SysReg_DSPSR_EL0         = 0xda28, // 11  011  0100  0101  000
+	A64SysReg_DLR_EL0           = 0xda29, // 11  011  0100  0101  001
+	A64SysReg_IFSR32_EL2        = 0xe281, // 11  100  0101  0000  001
+	A64SysReg_AFSR0_EL1         = 0xc288, // 11  000  0101  0001  000
+  	A64SysReg_AFSR0_EL12        = 0xea88, // 11  101  0101  0001  000
+	A64SysReg_AFSR0_EL2         = 0xe288, // 11  100  0101  0001  000
+	A64SysReg_AFSR0_EL3         = 0xf288, // 11  110  0101  0001  000
+	A64SysReg_AFSR1_EL1         = 0xc289, // 11  000  0101  0001  001
+ 	A64SysReg_AFSR1_EL12        = 0xea89, // 11  101  0101  0001  001
+	A64SysReg_AFSR1_EL2         = 0xe289, // 11  100  0101  0001  001
+	A64SysReg_AFSR1_EL3         = 0xf289, // 11  110  0101  0001  001
+	A64SysReg_ESR_EL1           = 0xc290, // 11  000  0101  0010  000
+	A64SysReg_ESR_EL12          = 0xea90, // 11  101  0101  0010  000
+	A64SysReg_ESR_EL2           = 0xe290, // 11  100  0101  0010  000
+	A64SysReg_ESR_EL3           = 0xf290, // 11  110  0101  0010  000
+	A64SysReg_FPEXC32_EL2       = 0xe298, // 11  100  0101  0011  000
+	A64SysReg_FAR_EL1           = 0xc300, // 11  000  0110  0000  000
+	A64SysReg_FAR_EL12          = 0xeb00, // 11  101  0110  0000  000
+	A64SysReg_FAR_EL2           = 0xe300, // 11  100  0110  0000  000
+	A64SysReg_FAR_EL3           = 0xf300, // 11  110  0110  0000  000
+	A64SysReg_HPFAR_EL2         = 0xe304, // 11  100  0110  0000  100
+	A64SysReg_PAR_EL1           = 0xc3a0, // 11  000  0111  0100  000
+	A64SysReg_PMCR_EL0          = 0xdce0, // 11  011  1001  1100  000
+	A64SysReg_PMCNTENSET_EL0    = 0xdce1, // 11  011  1001  1100  001
+	A64SysReg_PMCNTENCLR_EL0    = 0xdce2, // 11  011  1001  1100  010
+	A64SysReg_PMOVSCLR_EL0      = 0xdce3, // 11  011  1001  1100  011
+	A64SysReg_PMSELR_EL0        = 0xdce5, // 11  011  1001  1100  101
+	A64SysReg_PMCCNTR_EL0       = 0xdce8, // 11  011  1001  1101  000
+	A64SysReg_PMXEVTYPER_EL0    = 0xdce9, // 11  011  1001  1101  001
+	A64SysReg_PMXEVCNTR_EL0     = 0xdcea, // 11  011  1001  1101  010
+	A64SysReg_PMUSERENR_EL0     = 0xdcf0, // 11  011  1001  1110  000
+	A64SysReg_PMINTENSET_EL1    = 0xc4f1, // 11  000  1001  1110  001
+	A64SysReg_PMINTENCLR_EL1    = 0xc4f2, // 11  000  1001  1110  010
+	A64SysReg_PMOVSSET_EL0      = 0xdcf3, // 11  011  1001  1110  011
+	A64SysReg_MAIR_EL1          = 0xc510, // 11  000  1010  0010  000
+	A64SysReg_MAIR_EL12         = 0xed10, // 11  101  1010  0010  000
+	A64SysReg_MAIR_EL2          = 0xe510, // 11  100  1010  0010  000
+	A64SysReg_MAIR_EL3          = 0xf510, // 11  110  1010  0010  000
+	A64SysReg_AMAIR_EL1         = 0xc518, // 11  000  1010  0011  000
+	A64SysReg_AMAIR_EL12        = 0xed18, // 11  101  1010  0011  000
+	A64SysReg_AMAIR_EL2         = 0xe518, // 11  100  1010  0011  000
+	A64SysReg_AMAIR_EL3         = 0xf518, // 11  110  1010  0011  000
+	A64SysReg_VBAR_EL1          = 0xc600, // 11  000  1100  0000  000
+	A64SysReg_VBAR_EL12         = 0xee00, // 11  101  1100  0000  000
+	A64SysReg_VBAR_EL2          = 0xe600, // 11  100  1100  0000  000
+	A64SysReg_VBAR_EL3          = 0xf600, // 11  110  1100  0000  000
+	A64SysReg_RMR_EL1           = 0xc602, // 11  000  1100  0000  010
+	A64SysReg_RMR_EL2           = 0xe602, // 11  100  1100  0000  010
+	A64SysReg_RMR_EL3           = 0xf602, // 11  110  1100  0000  010
+	A64SysReg_CONTEXTIDR_EL1    = 0xc681, // 11  000  1101  0000  001
+	A64SysReg_CONTEXTIDR_EL12   = 0xee81, // 11  101  1101  0000  001
+	A64SysReg_CONTEXTIDR_EL2    = 0xe681, // 11  100  1101  0000  001
+	A64SysReg_TPIDR_EL0         = 0xde82, // 11  011  1101  0000  010
+	A64SysReg_TPIDR_EL2         = 0xe682, // 11  100  1101  0000  010
+	A64SysReg_TPIDR_EL3         = 0xf682, // 11  110  1101  0000  010
+	A64SysReg_TPIDRRO_EL0       = 0xde83, // 11  011  1101  0000  011
+	A64SysReg_TPIDR_EL1         = 0xc684, // 11  000  1101  0000  100
+	A64SysReg_CNTFRQ_EL0        = 0xdf00, // 11  011  1110  0000  000
+	A64SysReg_CNTVOFF_EL2       = 0xe703, // 11  100  1110  0000  011
+	A64SysReg_CNTKCTL_EL1       = 0xc708, // 11  000  1110  0001  000
+	A64SysReg_CNTKCTL_EL12      = 0xef08, // 11  101  1110  0001  000
+	A64SysReg_CNTHCTL_EL2       = 0xe708, // 11  100  1110  0001  000
+	A64SysReg_CNTHVCTL_EL2      = 0xe719, // 11  100  1110  0011  001
+	A64SysReg_CNTHV_CVAL_EL2    = 0xe71a, // 11  100  1110  0011  010
+	A64SysReg_CNTHV_TVAL_EL2    = 0xe718, // 11  100  1110  0011  000
+	A64SysReg_CNTP_TVAL_EL0     = 0xdf10, // 11  011  1110  0010  000
+	A64SysReg_CNTP_TVAL_EL02    = 0xef10, // 11  101  1110  0010  000
+	A64SysReg_CNTHP_TVAL_EL2    = 0xe710, // 11  100  1110  0010  000
+	A64SysReg_CNTPS_TVAL_EL1    = 0xff10, // 11  111  1110  0010  000
+	A64SysReg_CNTP_CTL_EL0      = 0xdf11, // 11  011  1110  0010  001
+	A64SysReg_CNTHP_CTL_EL2     = 0xe711, // 11  100  1110  0010  001
+	A64SysReg_CNTPS_CTL_EL1     = 0xff11, // 11  111  1110  0010  001
+	A64SysReg_CNTP_CVAL_EL0     = 0xdf12, // 11  011  1110  0010  010
+	A64SysReg_CNTP_CVAL_EL02    = 0xef12, // 11  101  1110  0010  010
+	A64SysReg_CNTHP_CVAL_EL2    = 0xe712, // 11  100  1110  0010  010
+	A64SysReg_CNTPS_CVAL_EL1    = 0xff12, // 11  111  1110  0010  010
+	A64SysReg_CNTV_TVAL_EL0     = 0xdf18, // 11  011  1110  0011  000
+	A64SysReg_CNTV_TVAL_EL02    = 0xef18, // 11  101  1110  0011  000
+	A64SysReg_CNTV_CTL_EL0      = 0xdf19, // 11  011  1110  0011  001
+	A64SysReg_CNTV_CTL_EL02	    = 0xef19, // 11  101  1110  0011  001
+	A64SysReg_CNTV_CVAL_EL0     = 0xdf1a, // 11  011  1110  0011  010
+	A64SysReg_CNTV_CVAL_EL02    = 0xef1a, // 11  101  1110  0011  010
+	A64SysReg_PMEVCNTR0_EL0     = 0xdf40, // 11  011  1110  1000  000
+	A64SysReg_PMEVCNTR1_EL0     = 0xdf41, // 11  011  1110  1000  001
+	A64SysReg_PMEVCNTR2_EL0     = 0xdf42, // 11  011  1110  1000  010
+	A64SysReg_PMEVCNTR3_EL0     = 0xdf43, // 11  011  1110  1000  011
+	A64SysReg_PMEVCNTR4_EL0     = 0xdf44, // 11  011  1110  1000  100
+	A64SysReg_PMEVCNTR5_EL0     = 0xdf45, // 11  011  1110  1000  101
+	A64SysReg_PMEVCNTR6_EL0     = 0xdf46, // 11  011  1110  1000  110
+	A64SysReg_PMEVCNTR7_EL0     = 0xdf47, // 11  011  1110  1000  111
+	A64SysReg_PMEVCNTR8_EL0     = 0xdf48, // 11  011  1110  1001  000
+	A64SysReg_PMEVCNTR9_EL0     = 0xdf49, // 11  011  1110  1001  001
+	A64SysReg_PMEVCNTR10_EL0    = 0xdf4a, // 11  011  1110  1001  010
+	A64SysReg_PMEVCNTR11_EL0    = 0xdf4b, // 11  011  1110  1001  011
+	A64SysReg_PMEVCNTR12_EL0    = 0xdf4c, // 11  011  1110  1001  100
+	A64SysReg_PMEVCNTR13_EL0    = 0xdf4d, // 11  011  1110  1001  101
+	A64SysReg_PMEVCNTR14_EL0    = 0xdf4e, // 11  011  1110  1001  110
+	A64SysReg_PMEVCNTR15_EL0    = 0xdf4f, // 11  011  1110  1001  111
+	A64SysReg_PMEVCNTR16_EL0    = 0xdf50, // 11  011  1110  1010  000
+	A64SysReg_PMEVCNTR17_EL0    = 0xdf51, // 11  011  1110  1010  001
+	A64SysReg_PMEVCNTR18_EL0    = 0xdf52, // 11  011  1110  1010  010
+	A64SysReg_PMEVCNTR19_EL0    = 0xdf53, // 11  011  1110  1010  011
+	A64SysReg_PMEVCNTR20_EL0    = 0xdf54, // 11  011  1110  1010  100
+	A64SysReg_PMEVCNTR21_EL0    = 0xdf55, // 11  011  1110  1010  101
+	A64SysReg_PMEVCNTR22_EL0    = 0xdf56, // 11  011  1110  1010  110
+	A64SysReg_PMEVCNTR23_EL0    = 0xdf57, // 11  011  1110  1010  111
+	A64SysReg_PMEVCNTR24_EL0    = 0xdf58, // 11  011  1110  1011  000
+	A64SysReg_PMEVCNTR25_EL0    = 0xdf59, // 11  011  1110  1011  001
+	A64SysReg_PMEVCNTR26_EL0    = 0xdf5a, // 11  011  1110  1011  010
+	A64SysReg_PMEVCNTR27_EL0    = 0xdf5b, // 11  011  1110  1011  011
+	A64SysReg_PMEVCNTR28_EL0    = 0xdf5c, // 11  011  1110  1011  100
+	A64SysReg_PMEVCNTR29_EL0    = 0xdf5d, // 11  011  1110  1011  101
+	A64SysReg_PMEVCNTR30_EL0    = 0xdf5e, // 11  011  1110  1011  110
+	A64SysReg_PMCCFILTR_EL0     = 0xdf7f, // 11  011  1110  1111  111
+	A64SysReg_PMEVTYPER0_EL0    = 0xdf60, // 11  011  1110  1100  000
+	A64SysReg_PMEVTYPER1_EL0    = 0xdf61, // 11  011  1110  1100  001
+	A64SysReg_PMEVTYPER2_EL0    = 0xdf62, // 11  011  1110  1100  010
+	A64SysReg_PMEVTYPER3_EL0    = 0xdf63, // 11  011  1110  1100  011
+	A64SysReg_PMEVTYPER4_EL0    = 0xdf64, // 11  011  1110  1100  100
+	A64SysReg_PMEVTYPER5_EL0    = 0xdf65, // 11  011  1110  1100  101
+	A64SysReg_PMEVTYPER6_EL0    = 0xdf66, // 11  011  1110  1100  110
+	A64SysReg_PMEVTYPER7_EL0    = 0xdf67, // 11  011  1110  1100  111
+	A64SysReg_PMEVTYPER8_EL0    = 0xdf68, // 11  011  1110  1101  000
+	A64SysReg_PMEVTYPER9_EL0    = 0xdf69, // 11  011  1110  1101  001
+	A64SysReg_PMEVTYPER10_EL0   = 0xdf6a, // 11  011  1110  1101  010
+	A64SysReg_PMEVTYPER11_EL0   = 0xdf6b, // 11  011  1110  1101  011
+	A64SysReg_PMEVTYPER12_EL0   = 0xdf6c, // 11  011  1110  1101  100
+	A64SysReg_PMEVTYPER13_EL0   = 0xdf6d, // 11  011  1110  1101  101
+	A64SysReg_PMEVTYPER14_EL0   = 0xdf6e, // 11  011  1110  1101  110
+	A64SysReg_PMEVTYPER15_EL0   = 0xdf6f, // 11  011  1110  1101  111
+	A64SysReg_PMEVTYPER16_EL0   = 0xdf70, // 11  011  1110  1110  000
+	A64SysReg_PMEVTYPER17_EL0   = 0xdf71, // 11  011  1110  1110  001
+	A64SysReg_PMEVTYPER18_EL0   = 0xdf72, // 11  011  1110  1110  010
+	A64SysReg_PMEVTYPER19_EL0   = 0xdf73, // 11  011  1110  1110  011
+	A64SysReg_PMEVTYPER20_EL0   = 0xdf74, // 11  011  1110  1110  100
+	A64SysReg_PMEVTYPER21_EL0   = 0xdf75, // 11  011  1110  1110  101
+	A64SysReg_PMEVTYPER22_EL0   = 0xdf76, // 11  011  1110  1110  110
+	A64SysReg_PMEVTYPER23_EL0   = 0xdf77, // 11  011  1110  1110  111
+	A64SysReg_PMEVTYPER24_EL0   = 0xdf78, // 11  011  1110  1111  000
+	A64SysReg_PMEVTYPER25_EL0   = 0xdf79, // 11  011  1110  1111  001
+	A64SysReg_PMEVTYPER26_EL0   = 0xdf7a, // 11  011  1110  1111  010
+	A64SysReg_PMEVTYPER27_EL0   = 0xdf7b, // 11  011  1110  1111  011
+	A64SysReg_PMEVTYPER28_EL0   = 0xdf7c, // 11  011  1110  1111  100
+	A64SysReg_PMEVTYPER29_EL0   = 0xdf7d, // 11  011  1110  1111  101
+	A64SysReg_PMEVTYPER30_EL0   = 0xdf7e, // 11  011  1110  1111  110
+
+	// Trace registers
+	A64SysReg_TRCPRGCTLR        = 0x8808, // 10  001  0000  0001  000
+	A64SysReg_TRCPROCSELR       = 0x8810, // 10  001  0000  0010  000
+	A64SysReg_TRCCONFIGR        = 0x8820, // 10  001  0000  0100  000
+	A64SysReg_TRCAUXCTLR        = 0x8830, // 10  001  0000  0110  000
+	A64SysReg_TRCEVENTCTL0R     = 0x8840, // 10  001  0000  1000  000
+	A64SysReg_TRCEVENTCTL1R     = 0x8848, // 10  001  0000  1001  000
+	A64SysReg_TRCSTALLCTLR      = 0x8858, // 10  001  0000  1011  000
+	A64SysReg_TRCTSCTLR         = 0x8860, // 10  001  0000  1100  000
+	A64SysReg_TRCSYNCPR         = 0x8868, // 10  001  0000  1101  000
+	A64SysReg_TRCCCCTLR         = 0x8870, // 10  001  0000  1110  000
+	A64SysReg_TRCBBCTLR         = 0x8878, // 10  001  0000  1111  000
+	A64SysReg_TRCTRACEIDR       = 0x8801, // 10  001  0000  0000  001
+	A64SysReg_TRCQCTLR          = 0x8809, // 10  001  0000  0001  001
+	A64SysReg_TRCVICTLR         = 0x8802, // 10  001  0000  0000  010
+	A64SysReg_TRCVIIECTLR       = 0x880a, // 10  001  0000  0001  010
+	A64SysReg_TRCVISSCTLR       = 0x8812, // 10  001  0000  0010  010
+	A64SysReg_TRCVIPCSSCTLR     = 0x881a, // 10  001  0000  0011  010
+	A64SysReg_TRCVDCTLR         = 0x8842, // 10  001  0000  1000  010
+	A64SysReg_TRCVDSACCTLR      = 0x884a, // 10  001  0000  1001  010
+	A64SysReg_TRCVDARCCTLR      = 0x8852, // 10  001  0000  1010  010
+	A64SysReg_TRCSEQEVR0        = 0x8804, // 10  001  0000  0000  100
+	A64SysReg_TRCSEQEVR1        = 0x880c, // 10  001  0000  0001  100
+	A64SysReg_TRCSEQEVR2        = 0x8814, // 10  001  0000  0010  100
+	A64SysReg_TRCSEQRSTEVR      = 0x8834, // 10  001  0000  0110  100
+	A64SysReg_TRCSEQSTR         = 0x883c, // 10  001  0000  0111  100
+	A64SysReg_TRCEXTINSELR      = 0x8844, // 10  001  0000  1000  100
+	A64SysReg_TRCCNTRLDVR0      = 0x8805, // 10  001  0000  0000  101
+	A64SysReg_TRCCNTRLDVR1      = 0x880d, // 10  001  0000  0001  101
+	A64SysReg_TRCCNTRLDVR2      = 0x8815, // 10  001  0000  0010  101
+	A64SysReg_TRCCNTRLDVR3      = 0x881d, // 10  001  0000  0011  101
+	A64SysReg_TRCCNTCTLR0       = 0x8825, // 10  001  0000  0100  101
+	A64SysReg_TRCCNTCTLR1       = 0x882d, // 10  001  0000  0101  101
+	A64SysReg_TRCCNTCTLR2       = 0x8835, // 10  001  0000  0110  101
+	A64SysReg_TRCCNTCTLR3       = 0x883d, // 10  001  0000  0111  101
+	A64SysReg_TRCCNTVR0         = 0x8845, // 10  001  0000  1000  101
+	A64SysReg_TRCCNTVR1         = 0x884d, // 10  001  0000  1001  101
+	A64SysReg_TRCCNTVR2         = 0x8855, // 10  001  0000  1010  101
+	A64SysReg_TRCCNTVR3         = 0x885d, // 10  001  0000  1011  101
+	A64SysReg_TRCIMSPEC0        = 0x8807, // 10  001  0000  0000  111
+	A64SysReg_TRCIMSPEC1        = 0x880f, // 10  001  0000  0001  111
+	A64SysReg_TRCIMSPEC2        = 0x8817, // 10  001  0000  0010  111
+	A64SysReg_TRCIMSPEC3        = 0x881f, // 10  001  0000  0011  111
+	A64SysReg_TRCIMSPEC4        = 0x8827, // 10  001  0000  0100  111
+	A64SysReg_TRCIMSPEC5        = 0x882f, // 10  001  0000  0101  111
+	A64SysReg_TRCIMSPEC6        = 0x8837, // 10  001  0000  0110  111
+	A64SysReg_TRCIMSPEC7        = 0x883f, // 10  001  0000  0111  111
+	A64SysReg_TRCRSCTLR2        = 0x8890, // 10  001  0001  0010  000
+	A64SysReg_TRCRSCTLR3        = 0x8898, // 10  001  0001  0011  000
+	A64SysReg_TRCRSCTLR4        = 0x88a0, // 10  001  0001  0100  000
+	A64SysReg_TRCRSCTLR5        = 0x88a8, // 10  001  0001  0101  000
+	A64SysReg_TRCRSCTLR6        = 0x88b0, // 10  001  0001  0110  000
+	A64SysReg_TRCRSCTLR7        = 0x88b8, // 10  001  0001  0111  000
+	A64SysReg_TRCRSCTLR8        = 0x88c0, // 10  001  0001  1000  000
+	A64SysReg_TRCRSCTLR9        = 0x88c8, // 10  001  0001  1001  000
+	A64SysReg_TRCRSCTLR10       = 0x88d0, // 10  001  0001  1010  000
+	A64SysReg_TRCRSCTLR11       = 0x88d8, // 10  001  0001  1011  000
+	A64SysReg_TRCRSCTLR12       = 0x88e0, // 10  001  0001  1100  000
+	A64SysReg_TRCRSCTLR13       = 0x88e8, // 10  001  0001  1101  000
+	A64SysReg_TRCRSCTLR14       = 0x88f0, // 10  001  0001  1110  000
+	A64SysReg_TRCRSCTLR15       = 0x88f8, // 10  001  0001  1111  000
+	A64SysReg_TRCRSCTLR16       = 0x8881, // 10  001  0001  0000  001
+	A64SysReg_TRCRSCTLR17       = 0x8889, // 10  001  0001  0001  001
+	A64SysReg_TRCRSCTLR18       = 0x8891, // 10  001  0001  0010  001
+	A64SysReg_TRCRSCTLR19       = 0x8899, // 10  001  0001  0011  001
+	A64SysReg_TRCRSCTLR20       = 0x88a1, // 10  001  0001  0100  001
+	A64SysReg_TRCRSCTLR21       = 0x88a9, // 10  001  0001  0101  001
+	A64SysReg_TRCRSCTLR22       = 0x88b1, // 10  001  0001  0110  001
+	A64SysReg_TRCRSCTLR23       = 0x88b9, // 10  001  0001  0111  001
+	A64SysReg_TRCRSCTLR24       = 0x88c1, // 10  001  0001  1000  001
+	A64SysReg_TRCRSCTLR25       = 0x88c9, // 10  001  0001  1001  001
+	A64SysReg_TRCRSCTLR26       = 0x88d1, // 10  001  0001  1010  001
+	A64SysReg_TRCRSCTLR27       = 0x88d9, // 10  001  0001  1011  001
+	A64SysReg_TRCRSCTLR28       = 0x88e1, // 10  001  0001  1100  001
+	A64SysReg_TRCRSCTLR29       = 0x88e9, // 10  001  0001  1101  001
+	A64SysReg_TRCRSCTLR30       = 0x88f1, // 10  001  0001  1110  001
+	A64SysReg_TRCRSCTLR31       = 0x88f9, // 10  001  0001  1111  001
+	A64SysReg_TRCSSCCR0         = 0x8882, // 10  001  0001  0000  010
+	A64SysReg_TRCSSCCR1         = 0x888a, // 10  001  0001  0001  010
+	A64SysReg_TRCSSCCR2         = 0x8892, // 10  001  0001  0010  010
+	A64SysReg_TRCSSCCR3         = 0x889a, // 10  001  0001  0011  010
+	A64SysReg_TRCSSCCR4         = 0x88a2, // 10  001  0001  0100  010
+	A64SysReg_TRCSSCCR5         = 0x88aa, // 10  001  0001  0101  010
+	A64SysReg_TRCSSCCR6         = 0x88b2, // 10  001  0001  0110  010
+	A64SysReg_TRCSSCCR7         = 0x88ba, // 10  001  0001  0111  010
+	A64SysReg_TRCSSCSR0         = 0x88c2, // 10  001  0001  1000  010
+	A64SysReg_TRCSSCSR1         = 0x88ca, // 10  001  0001  1001  010
+	A64SysReg_TRCSSCSR2         = 0x88d2, // 10  001  0001  1010  010
+	A64SysReg_TRCSSCSR3         = 0x88da, // 10  001  0001  1011  010
+	A64SysReg_TRCSSCSR4         = 0x88e2, // 10  001  0001  1100  010
+	A64SysReg_TRCSSCSR5         = 0x88ea, // 10  001  0001  1101  010
+	A64SysReg_TRCSSCSR6         = 0x88f2, // 10  001  0001  1110  010
+	A64SysReg_TRCSSCSR7         = 0x88fa, // 10  001  0001  1111  010
+	A64SysReg_TRCSSPCICR0       = 0x8883, // 10  001  0001  0000  011
+	A64SysReg_TRCSSPCICR1       = 0x888b, // 10  001  0001  0001  011
+	A64SysReg_TRCSSPCICR2       = 0x8893, // 10  001  0001  0010  011
+	A64SysReg_TRCSSPCICR3       = 0x889b, // 10  001  0001  0011  011
+	A64SysReg_TRCSSPCICR4       = 0x88a3, // 10  001  0001  0100  011
+	A64SysReg_TRCSSPCICR5       = 0x88ab, // 10  001  0001  0101  011
+	A64SysReg_TRCSSPCICR6       = 0x88b3, // 10  001  0001  0110  011
+	A64SysReg_TRCSSPCICR7       = 0x88bb, // 10  001  0001  0111  011
+	A64SysReg_TRCPDCR           = 0x88a4, // 10  001  0001  0100  100
+	A64SysReg_TRCACVR0          = 0x8900, // 10  001  0010  0000  000
+	A64SysReg_TRCACVR1          = 0x8910, // 10  001  0010  0010  000
+	A64SysReg_TRCACVR2          = 0x8920, // 10  001  0010  0100  000
+	A64SysReg_TRCACVR3          = 0x8930, // 10  001  0010  0110  000
+	A64SysReg_TRCACVR4          = 0x8940, // 10  001  0010  1000  000
+	A64SysReg_TRCACVR5          = 0x8950, // 10  001  0010  1010  000
+	A64SysReg_TRCACVR6          = 0x8960, // 10  001  0010  1100  000
+	A64SysReg_TRCACVR7          = 0x8970, // 10  001  0010  1110  000
+	A64SysReg_TRCACVR8          = 0x8901, // 10  001  0010  0000  001
+	A64SysReg_TRCACVR9          = 0x8911, // 10  001  0010  0010  001
+	A64SysReg_TRCACVR10         = 0x8921, // 10  001  0010  0100  001
+	A64SysReg_TRCACVR11         = 0x8931, // 10  001  0010  0110  001
+	A64SysReg_TRCACVR12         = 0x8941, // 10  001  0010  1000  001
+	A64SysReg_TRCACVR13         = 0x8951, // 10  001  0010  1010  001
+	A64SysReg_TRCACVR14         = 0x8961, // 10  001  0010  1100  001
+	A64SysReg_TRCACVR15         = 0x8971, // 10  001  0010  1110  001
+	A64SysReg_TRCACATR0         = 0x8902, // 10  001  0010  0000  010
+	A64SysReg_TRCACATR1         = 0x8912, // 10  001  0010  0010  010
+	A64SysReg_TRCACATR2         = 0x8922, // 10  001  0010  0100  010
+	A64SysReg_TRCACATR3         = 0x8932, // 10  001  0010  0110  010
+	A64SysReg_TRCACATR4         = 0x8942, // 10  001  0010  1000  010
+	A64SysReg_TRCACATR5         = 0x8952, // 10  001  0010  1010  010
+	A64SysReg_TRCACATR6         = 0x8962, // 10  001  0010  1100  010
+	A64SysReg_TRCACATR7         = 0x8972, // 10  001  0010  1110  010
+	A64SysReg_TRCACATR8         = 0x8903, // 10  001  0010  0000  011
+	A64SysReg_TRCACATR9         = 0x8913, // 10  001  0010  0010  011
+	A64SysReg_TRCACATR10        = 0x8923, // 10  001  0010  0100  011
+	A64SysReg_TRCACATR11        = 0x8933, // 10  001  0010  0110  011
+	A64SysReg_TRCACATR12        = 0x8943, // 10  001  0010  1000  011
+	A64SysReg_TRCACATR13        = 0x8953, // 10  001  0010  1010  011
+	A64SysReg_TRCACATR14        = 0x8963, // 10  001  0010  1100  011
+	A64SysReg_TRCACATR15        = 0x8973, // 10  001  0010  1110  011
+	A64SysReg_TRCDVCVR0         = 0x8904, // 10  001  0010  0000  100
+	A64SysReg_TRCDVCVR1         = 0x8924, // 10  001  0010  0100  100
+	A64SysReg_TRCDVCVR2         = 0x8944, // 10  001  0010  1000  100
+	A64SysReg_TRCDVCVR3         = 0x8964, // 10  001  0010  1100  100
+	A64SysReg_TRCDVCVR4         = 0x8905, // 10  001  0010  0000  101
+	A64SysReg_TRCDVCVR5         = 0x8925, // 10  001  0010  0100  101
+	A64SysReg_TRCDVCVR6         = 0x8945, // 10  001  0010  1000  101
+	A64SysReg_TRCDVCVR7         = 0x8965, // 10  001  0010  1100  101
+	A64SysReg_TRCDVCMR0         = 0x8906, // 10  001  0010  0000  110
+	A64SysReg_TRCDVCMR1         = 0x8926, // 10  001  0010  0100  110
+	A64SysReg_TRCDVCMR2         = 0x8946, // 10  001  0010  1000  110
+	A64SysReg_TRCDVCMR3         = 0x8966, // 10  001  0010  1100  110
+	A64SysReg_TRCDVCMR4         = 0x8907, // 10  001  0010  0000  111
+	A64SysReg_TRCDVCMR5         = 0x8927, // 10  001  0010  0100  111
+	A64SysReg_TRCDVCMR6         = 0x8947, // 10  001  0010  1000  111
+	A64SysReg_TRCDVCMR7         = 0x8967, // 10  001  0010  1100  111
+	A64SysReg_TRCCIDCVR0        = 0x8980, // 10  001  0011  0000  000
+	A64SysReg_TRCCIDCVR1        = 0x8990, // 10  001  0011  0010  000
+	A64SysReg_TRCCIDCVR2        = 0x89a0, // 10  001  0011  0100  000
+	A64SysReg_TRCCIDCVR3        = 0x89b0, // 10  001  0011  0110  000
+	A64SysReg_TRCCIDCVR4        = 0x89c0, // 10  001  0011  1000  000
+	A64SysReg_TRCCIDCVR5        = 0x89d0, // 10  001  0011  1010  000
+	A64SysReg_TRCCIDCVR6        = 0x89e0, // 10  001  0011  1100  000
+	A64SysReg_TRCCIDCVR7        = 0x89f0, // 10  001  0011  1110  000
+	A64SysReg_TRCVMIDCVR0       = 0x8981, // 10  001  0011  0000  001
+	A64SysReg_TRCVMIDCVR1       = 0x8991, // 10  001  0011  0010  001
+	A64SysReg_TRCVMIDCVR2       = 0x89a1, // 10  001  0011  0100  001
+	A64SysReg_TRCVMIDCVR3       = 0x89b1, // 10  001  0011  0110  001
+	A64SysReg_TRCVMIDCVR4       = 0x89c1, // 10  001  0011  1000  001
+	A64SysReg_TRCVMIDCVR5       = 0x89d1, // 10  001  0011  1010  001
+	A64SysReg_TRCVMIDCVR6       = 0x89e1, // 10  001  0011  1100  001
+	A64SysReg_TRCVMIDCVR7       = 0x89f1, // 10  001  0011  1110  001
+	A64SysReg_TRCCIDCCTLR0      = 0x8982, // 10  001  0011  0000  010
+	A64SysReg_TRCCIDCCTLR1      = 0x898a, // 10  001  0011  0001  010
+	A64SysReg_TRCVMIDCCTLR0     = 0x8992, // 10  001  0011  0010  010
+	A64SysReg_TRCVMIDCCTLR1     = 0x899a, // 10  001  0011  0011  010
+	A64SysReg_TRCITCTRL         = 0x8b84, // 10  001  0111  0000  100
+	A64SysReg_TRCCLAIMSET       = 0x8bc6, // 10  001  0111  1000  110
+	A64SysReg_TRCCLAIMCLR       = 0x8bce, // 10  001  0111  1001  110
+
+	// GICv3 registers
+	A64SysReg_ICC_BPR1_EL1      = 0xc663, // 11  000  1100  1100  011
+	A64SysReg_ICC_BPR0_EL1      = 0xc643, // 11  000  1100  1000  011
+	A64SysReg_ICC_PMR_EL1       = 0xc230, // 11  000  0100  0110  000
+	A64SysReg_ICC_CTLR_EL1      = 0xc664, // 11  000  1100  1100  100
+	A64SysReg_ICC_CTLR_EL3      = 0xf664, // 11  110  1100  1100  100
+	A64SysReg_ICC_SRE_EL1       = 0xc665, // 11  000  1100  1100  101
+	A64SysReg_ICC_SRE_EL2       = 0xe64d, // 11  100  1100  1001  101
+	A64SysReg_ICC_SRE_EL3       = 0xf665, // 11  110  1100  1100  101
+	A64SysReg_ICC_IGRPEN0_EL1   = 0xc666, // 11  000  1100  1100  110
+	A64SysReg_ICC_IGRPEN1_EL1   = 0xc667, // 11  000  1100  1100  111
+	A64SysReg_ICC_IGRPEN1_EL3   = 0xf667, // 11  110  1100  1100  111
+	A64SysReg_ICC_SEIEN_EL1     = 0xc668, // 11  000  1100  1101  000
+	A64SysReg_ICC_AP0R0_EL1     = 0xc644, // 11  000  1100  1000  100
+	A64SysReg_ICC_AP0R1_EL1     = 0xc645, // 11  000  1100  1000  101
+	A64SysReg_ICC_AP0R2_EL1     = 0xc646, // 11  000  1100  1000  110
+	A64SysReg_ICC_AP0R3_EL1     = 0xc647, // 11  000  1100  1000  111
+	A64SysReg_ICC_AP1R0_EL1     = 0xc648, // 11  000  1100  1001  000
+	A64SysReg_ICC_AP1R1_EL1     = 0xc649, // 11  000  1100  1001  001
+	A64SysReg_ICC_AP1R2_EL1     = 0xc64a, // 11  000  1100  1001  010
+	A64SysReg_ICC_AP1R3_EL1     = 0xc64b, // 11  000  1100  1001  011
+	A64SysReg_ICH_AP0R0_EL2     = 0xe640, // 11  100  1100  1000  000
+	A64SysReg_ICH_AP0R1_EL2     = 0xe641, // 11  100  1100  1000  001
+	A64SysReg_ICH_AP0R2_EL2     = 0xe642, // 11  100  1100  1000  010
+	A64SysReg_ICH_AP0R3_EL2     = 0xe643, // 11  100  1100  1000  011
+	A64SysReg_ICH_AP1R0_EL2     = 0xe648, // 11  100  1100  1001  000
+	A64SysReg_ICH_AP1R1_EL2     = 0xe649, // 11  100  1100  1001  001
+	A64SysReg_ICH_AP1R2_EL2     = 0xe64a, // 11  100  1100  1001  010
+	A64SysReg_ICH_AP1R3_EL2     = 0xe64b, // 11  100  1100  1001  011
+	A64SysReg_ICH_HCR_EL2       = 0xe658, // 11  100  1100  1011  000
+	A64SysReg_ICH_MISR_EL2      = 0xe65a, // 11  100  1100  1011  010
+	A64SysReg_ICH_VMCR_EL2      = 0xe65f, // 11  100  1100  1011  111
+	A64SysReg_ICH_VSEIR_EL2     = 0xe64c, // 11  100  1100  1001  100
+	A64SysReg_ICH_LR0_EL2       = 0xe660, // 11  100  1100  1100  000
+	A64SysReg_ICH_LR1_EL2       = 0xe661, // 11  100  1100  1100  001
+	A64SysReg_ICH_LR2_EL2       = 0xe662, // 11  100  1100  1100  010
+	A64SysReg_ICH_LR3_EL2       = 0xe663, // 11  100  1100  1100  011
+	A64SysReg_ICH_LR4_EL2       = 0xe664, // 11  100  1100  1100  100
+	A64SysReg_ICH_LR5_EL2       = 0xe665, // 11  100  1100  1100  101
+	A64SysReg_ICH_LR6_EL2       = 0xe666, // 11  100  1100  1100  110
+	A64SysReg_ICH_LR7_EL2       = 0xe667, // 11  100  1100  1100  111
+	A64SysReg_ICH_LR8_EL2       = 0xe668, // 11  100  1100  1101  000
+	A64SysReg_ICH_LR9_EL2       = 0xe669, // 11  100  1100  1101  001
+	A64SysReg_ICH_LR10_EL2      = 0xe66a, // 11  100  1100  1101  010
+	A64SysReg_ICH_LR11_EL2      = 0xe66b, // 11  100  1100  1101  011
+	A64SysReg_ICH_LR12_EL2      = 0xe66c, // 11  100  1100  1101  100
+	A64SysReg_ICH_LR13_EL2      = 0xe66d, // 11  100  1100  1101  101
+	A64SysReg_ICH_LR14_EL2      = 0xe66e, // 11  100  1100  1101  110
+	A64SysReg_ICH_LR15_EL2      = 0xe66f, // 11  100  1100  1101  111
+
+	// Statistical profiling registers
+	A64SysReg_PMSIDR_EL1        = 0xc4cf, // 11  000  1001  1001  111
+	A64SysReg_PMBIDR_EL1        = 0xc4d7, // 11  000  1001  1010  111
+	A64SysReg_PMBLIMITR_EL1     = 0xc4d0, // 11  000  1001  1010  000
+	A64SysReg_PMBPTR_EL1        = 0xc4d1, // 11  000  1001  1010  001
+	A64SysReg_PMBSR_EL1         = 0xc4d3, // 11  000  1001  1010  011
+	A64SysReg_PMSCR_EL1         = 0xc4c8, // 11  000  1001  1001  000
+	A64SysReg_PMSCR_EL12        = 0xecc8, // 11  101  1001  1001  000
+	A64SysReg_PMSCR_EL2         = 0xe4c8, // 11  100  1001  1001  000
+	A64SysReg_PMSICR_EL1        = 0xc4ca, // 11  000  1001  1001  010
+	A64SysReg_PMSIRR_EL1        = 0xc4cb, // 11  000  1001  1001  011
+	A64SysReg_PMSFCR_EL1        = 0xc4cc, // 11  000  1001  1001  100
+	A64SysReg_PMSEVFR_EL1       = 0xc4cd, // 11  000  1001  1001  101
+	A64SysReg_PMSLATFR_EL1      = 0xc4ce  // 11  000  1001  1001  110
+};
+
+// Cyclone specific system registers
+enum A64CycloneSysRegValues {
+	A64SysReg_CPM_IOACC_CTL_EL3 = 0xff90
+};
+
+enum A64TLBIValues {
+	A64TLBI_Invalid = -1,          // Op0 Op1  CRn   CRm   Op2
+	A64TLBI_IPAS2E1IS    = 0x6401, // 01  100  1000  0000  001
+	A64TLBI_IPAS2LE1IS   = 0x6405, // 01  100  1000  0000  101
+	A64TLBI_VMALLE1IS    = 0x4418, // 01  000  1000  0011  000
+	A64TLBI_ALLE2IS      = 0x6418, // 01  100  1000  0011  000
+	A64TLBI_ALLE3IS      = 0x7418, // 01  110  1000  0011  000
+	A64TLBI_VAE1IS       = 0x4419, // 01  000  1000  0011  001
+	A64TLBI_VAE2IS       = 0x6419, // 01  100  1000  0011  001
+	A64TLBI_VAE3IS       = 0x7419, // 01  110  1000  0011  001
+	A64TLBI_ASIDE1IS     = 0x441a, // 01  000  1000  0011  010
+	A64TLBI_VAAE1IS      = 0x441b, // 01  000  1000  0011  011
+	A64TLBI_ALLE1IS      = 0x641c, // 01  100  1000  0011  100
+	A64TLBI_VALE1IS      = 0x441d, // 01  000  1000  0011  101
+	A64TLBI_VALE2IS      = 0x641d, // 01  100  1000  0011  101
+	A64TLBI_VALE3IS      = 0x741d, // 01  110  1000  0011  101
+	A64TLBI_VMALLS12E1IS = 0x641e, // 01  100  1000  0011  110
+	A64TLBI_VAALE1IS     = 0x441f, // 01  000  1000  0011  111
+	A64TLBI_IPAS2E1      = 0x6421, // 01  100  1000  0100  001
+	A64TLBI_IPAS2LE1     = 0x6425, // 01  100  1000  0100  101
+	A64TLBI_VMALLE1      = 0x4438, // 01  000  1000  0111  000
+	A64TLBI_ALLE2        = 0x6438, // 01  100  1000  0111  000
+	A64TLBI_ALLE3        = 0x7438, // 01  110  1000  0111  000
+	A64TLBI_VAE1         = 0x4439, // 01  000  1000  0111  001
+	A64TLBI_VAE2         = 0x6439, // 01  100  1000  0111  001
+	A64TLBI_VAE3         = 0x7439, // 01  110  1000  0111  001
+	A64TLBI_ASIDE1       = 0x443a, // 01  000  1000  0111  010
+	A64TLBI_VAAE1        = 0x443b, // 01  000  1000  0111  011
+	A64TLBI_ALLE1        = 0x643c, // 01  100  1000  0111  100
+	A64TLBI_VALE1        = 0x443d, // 01  000  1000  0111  101
+	A64TLBI_VALE2        = 0x643d, // 01  100  1000  0111  101
+	A64TLBI_VALE3        = 0x743d, // 01  110  1000  0111  101
+	A64TLBI_VMALLS12E1   = 0x643e, // 01  100  1000  0111  110
+	A64TLBI_VAALE1       = 0x443f  // 01  000  1000  0111  111
+};
+
+bool A64Imms_isLogicalImmBits(unsigned RegWidth, uint32_t Bits, uint64_t *Imm);
+
+char *A64NamedImmMapper_toString(A64NamedImmMapper *N, uint32_t Value, bool *Valid);
+
+uint32_t A64NamedImmMapper_fromString(A64NamedImmMapper *N, char *Name, bool *Valid);
+
+bool A64NamedImmMapper_validImm(A64NamedImmMapper *N, uint32_t Value);
+
+void A64SysRegMapper_toString(A64SysRegMapper *S, uint32_t Bits, bool *Valid, char *result);
+
+#endif
diff --git a/arch/AArch64/AArch64Disassembler.c b/arch/AArch64/AArch64Disassembler.c
new file mode 100644
index 0000000..56a14a8
--- /dev/null
+++ b/arch/AArch64/AArch64Disassembler.c
@@ -0,0 +1,1680 @@
+//===- AArch64Disassembler.cpp - Disassembler for AArch64 ISA -------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the functions necessary to decode AArch64 instruction
+// bitpatterns into MCInsts (with the help of TableGenerated information from
+// the instruction definitions).
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifdef CAPSTONE_HAS_ARM64
+
+#include <stdio.h>	// DEBUG
+#include <stdlib.h>
+
+#include "../../cs_priv.h"
+#include "../../utils.h"
+
+#include "../../MCInst.h"
+#include "../../MCInstrDesc.h"
+#include "../../MCFixedLenDisassembler.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCDisassembler.h"
+
+#include "AArch64BaseInfo.h"
+#include "AArch64AddressingModes.h"
+
+
+// Forward declare these because the autogenerated code will reference them.
+// Definitions are further down.
+static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst,
+		unsigned RegNo, uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodeFPR128_loRegisterClass(MCInst *Inst,
+		unsigned RegNo,
+		uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodeGPR64spRegisterClass(MCInst *Inst,
+		unsigned RegNo, uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodeGPR32spRegisterClass(MCInst *Inst,
+		unsigned RegNo, uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodeQQRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodeQQQRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodeQQQQRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodeDDRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodeDDDRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodeDDDDRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address,
+		void *Decoder);
+
+static DecodeStatus DecodeFixedPointScaleImm32(MCInst *Inst, unsigned Imm,
+		uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodeFixedPointScaleImm64(MCInst *Inst, unsigned Imm,
+		uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodePCRelLabel19(MCInst *Inst, unsigned Imm,
+		uint64_t Address, void *Decoder);
+static DecodeStatus DecodeMemExtend(MCInst *Inst, unsigned Imm,
+		uint64_t Address, void *Decoder);
+static DecodeStatus DecodeMRSSystemRegister(MCInst *Inst, unsigned Imm,
+		uint64_t Address, void *Decoder);
+static DecodeStatus DecodeMSRSystemRegister(MCInst *Inst, unsigned Imm,
+		uint64_t Address, void *Decoder);
+static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst,
+		uint32_t insn,
+		uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodeMoveImmInstruction(MCInst *Inst, uint32_t insn,
+		uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst,
+		uint32_t insn,
+		uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst,
+		uint32_t insn, uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst,
+		uint32_t insn,
+		uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn,
+		uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodeAddSubERegInstruction(MCInst *Inst,
+		uint32_t insn, uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodeLogicalImmInstruction(MCInst *Inst,
+		uint32_t insn, uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodeModImmInstruction(MCInst *Inst, uint32_t insn,
+		uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodeModImmTiedInstruction(MCInst *Inst,
+		uint32_t insn, uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodeAdrInstruction(MCInst *Inst, uint32_t insn,
+		uint64_t Address, void *Decoder);
+static DecodeStatus DecodeBaseAddSubImm(MCInst *Inst, uint32_t insn,
+		uint64_t Address, void *Decoder);
+static DecodeStatus DecodeUnconditionalBranch(MCInst *Inst, uint32_t insn,
+		uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodeSystemPStateInstruction(MCInst *Inst,
+		uint32_t insn,
+		uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodeTestAndBranch(MCInst *Inst, uint32_t insn,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn,
+		uint64_t Address,
+		void *Decoder);
+static DecodeStatus DecodeVecShiftR64Imm(MCInst *Inst, unsigned Imm,
+		uint64_t Addr, void *Decoder);
+static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst *Inst, unsigned Imm,
+		uint64_t Addr,
+		void *Decoder);
+static DecodeStatus DecodeVecShiftR32Imm(MCInst *Inst, unsigned Imm,
+		uint64_t Addr, void *Decoder);
+static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst *Inst, unsigned Imm,
+		uint64_t Addr,
+		void *Decoder);
+static DecodeStatus DecodeVecShiftR16Imm(MCInst *Inst, unsigned Imm,
+		uint64_t Addr, void *Decoder);
+static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst *Inst, unsigned Imm,
+		uint64_t Addr,
+		void *Decoder);
+static DecodeStatus DecodeVecShiftR8Imm(MCInst *Inst, unsigned Imm,
+		uint64_t Addr, void *Decoder);
+static DecodeStatus DecodeVecShiftL64Imm(MCInst *Inst, unsigned Imm,
+		uint64_t Addr, void *Decoder);
+static DecodeStatus DecodeVecShiftL32Imm(MCInst *Inst, unsigned Imm,
+		uint64_t Addr, void *Decoder);
+static DecodeStatus DecodeVecShiftL16Imm(MCInst *Inst, unsigned Imm,
+		uint64_t Addr, void *Decoder);
+static DecodeStatus DecodeVecShiftL8Imm(MCInst *Inst, unsigned Imm,
+		uint64_t Addr, void *Decoder);
+
+static bool Check(DecodeStatus *Out, DecodeStatus In)
+{
+	switch (In) {
+		default:	// never reach
+			return true;
+		case MCDisassembler_Success:
+			// Out stays the same.
+			return true;
+		case MCDisassembler_SoftFail:
+			*Out = In;
+			return true;
+		case MCDisassembler_Fail:
+			*Out = In;
+			return false;
+	}
+	// llvm_unreachable("Invalid DecodeStatus!");
+}
+
+// Hacky: enable all features for disassembler
+static uint64_t getFeatureBits(int feature)
+{
+	// enable all features
+	return (uint64_t)-1;
+}
+
+#define GET_SUBTARGETINFO_ENUM
+#include "AArch64GenSubtargetInfo.inc"
+
+#include "AArch64GenDisassemblerTables.inc"
+
+#define GET_INSTRINFO_ENUM
+#include "AArch64GenInstrInfo.inc"
+
+#define GET_REGINFO_ENUM
+#define GET_REGINFO_MC_DESC
+#include "AArch64GenRegisterInfo.inc"
+
+#define Success MCDisassembler_Success
+#define Fail MCDisassembler_Fail
+#define SoftFail MCDisassembler_SoftFail
+
+static DecodeStatus _getInstruction(cs_struct *ud, MCInst *MI,
+		const uint8_t *code, size_t code_len,
+		uint16_t *Size,
+		uint64_t Address, MCRegisterInfo *MRI)
+{
+	uint32_t insn;
+	DecodeStatus result;
+	size_t i;
+
+	if (code_len < 4) {
+		// not enough data
+		*Size = 0;
+		return MCDisassembler_Fail;
+	}
+
+	if (MI->flat_insn->detail) {
+		memset(MI->flat_insn->detail, 0, sizeof(cs_detail));
+		for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm64.operands); i++)
+			MI->flat_insn->detail->arm64.operands[i].vector_index = -1;
+	}
+
+	if (ud->big_endian)
+		insn = (code[3] << 0) | (code[2] << 8) |
+			(code[1] <<  16) | (code[0] <<  24);
+	else
+		insn = (code[3] << 24) | (code[2] << 16) |
+			(code[1] <<  8) | (code[0] <<  0);
+
+	// Calling the auto-generated decoder function.
+	result = decodeInstruction(DecoderTable32, MI, insn, Address, MRI, 0);
+	if (result != MCDisassembler_Fail) {
+		*Size = 4;
+		return result;
+	}
+
+	MCInst_clear(MI);
+	*Size = 0;
+	return MCDisassembler_Fail;
+}
+
+bool AArch64_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+		MCInst *instr, uint16_t *size, uint64_t address, void *info)
+{
+	DecodeStatus status = _getInstruction((cs_struct *)ud, instr,
+			code, code_len,
+			size,
+			address, (MCRegisterInfo *)info);
+
+	return status == MCDisassembler_Success;
+}
+
+static const unsigned FPR128DecoderTable[] = {
+	AArch64_Q0,  AArch64_Q1,  AArch64_Q2,  AArch64_Q3,  AArch64_Q4,
+	AArch64_Q5,  AArch64_Q6,  AArch64_Q7,  AArch64_Q8,  AArch64_Q9,
+	AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14,
+	AArch64_Q15, AArch64_Q16, AArch64_Q17, AArch64_Q18, AArch64_Q19,
+	AArch64_Q20, AArch64_Q21, AArch64_Q22, AArch64_Q23, AArch64_Q24,
+	AArch64_Q25, AArch64_Q26, AArch64_Q27, AArch64_Q28, AArch64_Q29,
+	AArch64_Q30, AArch64_Q31
+};
+
+static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Addr,
+		void *Decoder)
+{
+	unsigned Register;
+	if (RegNo > 31)
+		return Fail;
+
+	Register = FPR128DecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, Register);
+	return Success;
+}
+
+static DecodeStatus DecodeFPR128_loRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Addr,
+		void *Decoder)
+{
+	if (RegNo > 15)
+		return Fail;
+
+	return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
+}
+
+static const unsigned FPR64DecoderTable[] = {
+	AArch64_D0,  AArch64_D1,  AArch64_D2,  AArch64_D3,  AArch64_D4,
+	AArch64_D5,  AArch64_D6,  AArch64_D7,  AArch64_D8,  AArch64_D9,
+	AArch64_D10, AArch64_D11, AArch64_D12, AArch64_D13, AArch64_D14,
+	AArch64_D15, AArch64_D16, AArch64_D17, AArch64_D18, AArch64_D19,
+	AArch64_D20, AArch64_D21, AArch64_D22, AArch64_D23, AArch64_D24,
+	AArch64_D25, AArch64_D26, AArch64_D27, AArch64_D28, AArch64_D29,
+	AArch64_D30, AArch64_D31
+};
+
+static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Addr,
+		void *Decoder)
+{
+	unsigned Register;
+
+	if (RegNo > 31)
+		return Fail;
+
+	Register = FPR64DecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, Register);
+	return Success;
+}
+
+static const unsigned FPR32DecoderTable[] = {
+	AArch64_S0,  AArch64_S1,  AArch64_S2,  AArch64_S3,  AArch64_S4,
+	AArch64_S5,  AArch64_S6,  AArch64_S7,  AArch64_S8,  AArch64_S9,
+	AArch64_S10, AArch64_S11, AArch64_S12, AArch64_S13, AArch64_S14,
+	AArch64_S15, AArch64_S16, AArch64_S17, AArch64_S18, AArch64_S19,
+	AArch64_S20, AArch64_S21, AArch64_S22, AArch64_S23, AArch64_S24,
+	AArch64_S25, AArch64_S26, AArch64_S27, AArch64_S28, AArch64_S29,
+	AArch64_S30, AArch64_S31
+};
+
+static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Addr,
+		void *Decoder)
+{
+	unsigned Register;
+
+	if (RegNo > 31)
+		return Fail;
+
+	Register = FPR32DecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, Register);
+	return Success;
+}
+
+static const unsigned FPR16DecoderTable[] = {
+	AArch64_H0,  AArch64_H1,  AArch64_H2,  AArch64_H3,  AArch64_H4,
+	AArch64_H5,  AArch64_H6,  AArch64_H7,  AArch64_H8,  AArch64_H9,
+	AArch64_H10, AArch64_H11, AArch64_H12, AArch64_H13, AArch64_H14,
+	AArch64_H15, AArch64_H16, AArch64_H17, AArch64_H18, AArch64_H19,
+	AArch64_H20, AArch64_H21, AArch64_H22, AArch64_H23, AArch64_H24,
+	AArch64_H25, AArch64_H26, AArch64_H27, AArch64_H28, AArch64_H29,
+	AArch64_H30, AArch64_H31
+};
+
+static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Addr,
+		void *Decoder)
+{
+	unsigned Register;
+
+	if (RegNo > 31)
+		return Fail;
+
+	Register = FPR16DecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, Register);
+	return Success;
+}
+
+static const unsigned FPR8DecoderTable[] = {
+	AArch64_B0,  AArch64_B1,  AArch64_B2,  AArch64_B3,  AArch64_B4,
+	AArch64_B5,  AArch64_B6,  AArch64_B7,  AArch64_B8,  AArch64_B9,
+	AArch64_B10, AArch64_B11, AArch64_B12, AArch64_B13, AArch64_B14,
+	AArch64_B15, AArch64_B16, AArch64_B17, AArch64_B18, AArch64_B19,
+	AArch64_B20, AArch64_B21, AArch64_B22, AArch64_B23, AArch64_B24,
+	AArch64_B25, AArch64_B26, AArch64_B27, AArch64_B28, AArch64_B29,
+	AArch64_B30, AArch64_B31
+};
+
+static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Addr,
+		void *Decoder)
+{
+	unsigned Register;
+
+	if (RegNo > 31)
+		return Fail;
+
+	Register = FPR8DecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, Register);
+	return Success;
+}
+
+static const unsigned GPR64DecoderTable[] = {
+	AArch64_X0,  AArch64_X1,  AArch64_X2,  AArch64_X3,  AArch64_X4,
+	AArch64_X5,  AArch64_X6,  AArch64_X7,  AArch64_X8,  AArch64_X9,
+	AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14,
+	AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19,
+	AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24,
+	AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP,
+	AArch64_LR,  AArch64_XZR
+};
+
+static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Addr,
+		void *Decoder)
+{
+	unsigned Register;
+
+	if (RegNo > 31)
+		return Fail;
+
+	Register = GPR64DecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, Register);
+	return Success;
+}
+
+static DecodeStatus DecodeGPR64spRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Addr,
+		void *Decoder)
+{
+	unsigned Register;
+
+	if (RegNo > 31)
+		return Fail;
+
+	Register = GPR64DecoderTable[RegNo];
+	if (Register == AArch64_XZR)
+		Register = AArch64_SP;
+
+	MCOperand_CreateReg0(Inst, Register);
+
+	return Success;
+}
+
+static const unsigned GPR32DecoderTable[] = {
+	AArch64_W0,  AArch64_W1,  AArch64_W2,  AArch64_W3,  AArch64_W4,
+	AArch64_W5,  AArch64_W6,  AArch64_W7,  AArch64_W8,  AArch64_W9,
+	AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14,
+	AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19,
+	AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24,
+	AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29,
+	AArch64_W30, AArch64_WZR
+};
+
+static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Addr,
+		void *Decoder)
+{
+	unsigned Register;
+
+	if (RegNo > 31)
+		return Fail;
+
+	Register = GPR32DecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, Register);
+	return Success;
+}
+
+static DecodeStatus DecodeGPR32spRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Addr,
+		void *Decoder)
+{
+	unsigned Register;
+
+	if (RegNo > 31)
+		return Fail;
+
+	Register = GPR32DecoderTable[RegNo];
+	if (Register == AArch64_WZR)
+		Register = AArch64_WSP;
+
+	MCOperand_CreateReg0(Inst, Register);
+	return Success;
+}
+
+static const unsigned VectorDecoderTable[] = {
+	AArch64_Q0,  AArch64_Q1,  AArch64_Q2,  AArch64_Q3,  AArch64_Q4,
+	AArch64_Q5,  AArch64_Q6,  AArch64_Q7,  AArch64_Q8,  AArch64_Q9,
+	AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14,
+	AArch64_Q15, AArch64_Q16, AArch64_Q17, AArch64_Q18, AArch64_Q19,
+	AArch64_Q20, AArch64_Q21, AArch64_Q22, AArch64_Q23, AArch64_Q24,
+	AArch64_Q25, AArch64_Q26, AArch64_Q27, AArch64_Q28, AArch64_Q29,
+	AArch64_Q30, AArch64_Q31
+};
+
+static DecodeStatus DecodeVectorRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Addr,
+		void *Decoder)
+{
+	unsigned Register;
+
+	if (RegNo > 31)
+		return Fail;
+
+	Register = VectorDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, Register);
+	return Success;
+}
+
+static const unsigned QQDecoderTable[] = {
+	AArch64_Q0_Q1,   AArch64_Q1_Q2,   AArch64_Q2_Q3,   AArch64_Q3_Q4,
+	AArch64_Q4_Q5,   AArch64_Q5_Q6,   AArch64_Q6_Q7,   AArch64_Q7_Q8,
+	AArch64_Q8_Q9,   AArch64_Q9_Q10,  AArch64_Q10_Q11, AArch64_Q11_Q12,
+	AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q15_Q16,
+	AArch64_Q16_Q17, AArch64_Q17_Q18, AArch64_Q18_Q19, AArch64_Q19_Q20,
+	AArch64_Q20_Q21, AArch64_Q21_Q22, AArch64_Q22_Q23, AArch64_Q23_Q24,
+	AArch64_Q24_Q25, AArch64_Q25_Q26, AArch64_Q26_Q27, AArch64_Q27_Q28,
+	AArch64_Q28_Q29, AArch64_Q29_Q30, AArch64_Q30_Q31, AArch64_Q31_Q0
+};
+
+static DecodeStatus DecodeQQRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Addr, void *Decoder)
+{
+	unsigned Register;
+
+	if (RegNo > 31)
+		return Fail;
+
+	Register = QQDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, Register);
+	return Success;
+}
+
+static const unsigned QQQDecoderTable[] = {
+	AArch64_Q0_Q1_Q2,    AArch64_Q1_Q2_Q3,    AArch64_Q2_Q3_Q4,
+	AArch64_Q3_Q4_Q5,    AArch64_Q4_Q5_Q6,    AArch64_Q5_Q6_Q7,
+	AArch64_Q6_Q7_Q8,    AArch64_Q7_Q8_Q9,    AArch64_Q8_Q9_Q10,
+	AArch64_Q9_Q10_Q11,  AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13,
+	AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16,
+	AArch64_Q15_Q16_Q17, AArch64_Q16_Q17_Q18, AArch64_Q17_Q18_Q19,
+	AArch64_Q18_Q19_Q20, AArch64_Q19_Q20_Q21, AArch64_Q20_Q21_Q22,
+	AArch64_Q21_Q22_Q23, AArch64_Q22_Q23_Q24, AArch64_Q23_Q24_Q25,
+	AArch64_Q24_Q25_Q26, AArch64_Q25_Q26_Q27, AArch64_Q26_Q27_Q28,
+	AArch64_Q27_Q28_Q29, AArch64_Q28_Q29_Q30, AArch64_Q29_Q30_Q31,
+	AArch64_Q30_Q31_Q0,  AArch64_Q31_Q0_Q1
+};
+
+static DecodeStatus DecodeQQQRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Addr, void *Decoder)
+{
+	unsigned Register;
+
+	if (RegNo > 31)
+		return Fail;
+
+	Register = QQQDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, Register);
+	return Success;
+}
+
+static const unsigned QQQQDecoderTable[] = {
+	AArch64_Q0_Q1_Q2_Q3,     AArch64_Q1_Q2_Q3_Q4,     AArch64_Q2_Q3_Q4_Q5,
+	AArch64_Q3_Q4_Q5_Q6,     AArch64_Q4_Q5_Q6_Q7,     AArch64_Q5_Q6_Q7_Q8,
+	AArch64_Q6_Q7_Q8_Q9,     AArch64_Q7_Q8_Q9_Q10,    AArch64_Q8_Q9_Q10_Q11,
+	AArch64_Q9_Q10_Q11_Q12,  AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14,
+	AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17,
+	AArch64_Q15_Q16_Q17_Q18, AArch64_Q16_Q17_Q18_Q19, AArch64_Q17_Q18_Q19_Q20,
+	AArch64_Q18_Q19_Q20_Q21, AArch64_Q19_Q20_Q21_Q22, AArch64_Q20_Q21_Q22_Q23,
+	AArch64_Q21_Q22_Q23_Q24, AArch64_Q22_Q23_Q24_Q25, AArch64_Q23_Q24_Q25_Q26,
+	AArch64_Q24_Q25_Q26_Q27, AArch64_Q25_Q26_Q27_Q28, AArch64_Q26_Q27_Q28_Q29,
+	AArch64_Q27_Q28_Q29_Q30, AArch64_Q28_Q29_Q30_Q31, AArch64_Q29_Q30_Q31_Q0,
+	AArch64_Q30_Q31_Q0_Q1,   AArch64_Q31_Q0_Q1_Q2
+};
+
+static DecodeStatus DecodeQQQQRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Addr,
+		void *Decoder)
+{
+	unsigned Register;
+	if (RegNo > 31)
+		return Fail;
+
+	Register = QQQQDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, Register);
+	return Success;
+}
+
+static const unsigned DDDecoderTable[] = {
+	AArch64_D0_D1,   AArch64_D1_D2,   AArch64_D2_D3,   AArch64_D3_D4,
+	AArch64_D4_D5,   AArch64_D5_D6,   AArch64_D6_D7,   AArch64_D7_D8,
+	AArch64_D8_D9,   AArch64_D9_D10,  AArch64_D10_D11, AArch64_D11_D12,
+	AArch64_D12_D13, AArch64_D13_D14, AArch64_D14_D15, AArch64_D15_D16,
+	AArch64_D16_D17, AArch64_D17_D18, AArch64_D18_D19, AArch64_D19_D20,
+	AArch64_D20_D21, AArch64_D21_D22, AArch64_D22_D23, AArch64_D23_D24,
+	AArch64_D24_D25, AArch64_D25_D26, AArch64_D26_D27, AArch64_D27_D28,
+	AArch64_D28_D29, AArch64_D29_D30, AArch64_D30_D31, AArch64_D31_D0
+};
+
+static DecodeStatus DecodeDDRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Addr, void *Decoder)
+{
+	unsigned Register;
+
+	if (RegNo > 31)
+		return Fail;
+
+	Register = DDDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, Register);
+	return Success;
+}
+
+static const unsigned DDDDecoderTable[] = {
+	AArch64_D0_D1_D2,    AArch64_D1_D2_D3,    AArch64_D2_D3_D4,
+	AArch64_D3_D4_D5,    AArch64_D4_D5_D6,    AArch64_D5_D6_D7,
+	AArch64_D6_D7_D8,    AArch64_D7_D8_D9,    AArch64_D8_D9_D10,
+	AArch64_D9_D10_D11,  AArch64_D10_D11_D12, AArch64_D11_D12_D13,
+	AArch64_D12_D13_D14, AArch64_D13_D14_D15, AArch64_D14_D15_D16,
+	AArch64_D15_D16_D17, AArch64_D16_D17_D18, AArch64_D17_D18_D19,
+	AArch64_D18_D19_D20, AArch64_D19_D20_D21, AArch64_D20_D21_D22,
+	AArch64_D21_D22_D23, AArch64_D22_D23_D24, AArch64_D23_D24_D25,
+	AArch64_D24_D25_D26, AArch64_D25_D26_D27, AArch64_D26_D27_D28,
+	AArch64_D27_D28_D29, AArch64_D28_D29_D30, AArch64_D29_D30_D31,
+	AArch64_D30_D31_D0,  AArch64_D31_D0_D1
+};
+
+static DecodeStatus DecodeDDDRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Addr, void *Decoder)
+{
+	unsigned Register;
+
+	if (RegNo > 31)
+		return Fail;
+
+	Register = DDDDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, Register);
+	return Success;
+}
+
+static const unsigned DDDDDecoderTable[] = {
+	AArch64_D0_D1_D2_D3,     AArch64_D1_D2_D3_D4,     AArch64_D2_D3_D4_D5,
+	AArch64_D3_D4_D5_D6,     AArch64_D4_D5_D6_D7,     AArch64_D5_D6_D7_D8,
+	AArch64_D6_D7_D8_D9,     AArch64_D7_D8_D9_D10,    AArch64_D8_D9_D10_D11,
+	AArch64_D9_D10_D11_D12,  AArch64_D10_D11_D12_D13, AArch64_D11_D12_D13_D14,
+	AArch64_D12_D13_D14_D15, AArch64_D13_D14_D15_D16, AArch64_D14_D15_D16_D17,
+	AArch64_D15_D16_D17_D18, AArch64_D16_D17_D18_D19, AArch64_D17_D18_D19_D20,
+	AArch64_D18_D19_D20_D21, AArch64_D19_D20_D21_D22, AArch64_D20_D21_D22_D23,
+	AArch64_D21_D22_D23_D24, AArch64_D22_D23_D24_D25, AArch64_D23_D24_D25_D26,
+	AArch64_D24_D25_D26_D27, AArch64_D25_D26_D27_D28, AArch64_D26_D27_D28_D29,
+	AArch64_D27_D28_D29_D30, AArch64_D28_D29_D30_D31, AArch64_D29_D30_D31_D0,
+	AArch64_D30_D31_D0_D1,   AArch64_D31_D0_D1_D2
+};
+
+static DecodeStatus DecodeDDDDRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Addr,
+		void *Decoder)
+{
+	unsigned Register;
+
+	if (RegNo > 31)
+		return Fail;
+
+	Register = DDDDDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, Register);
+	return Success;
+}
+
+static DecodeStatus DecodeFixedPointScaleImm32(MCInst *Inst, unsigned Imm,
+		uint64_t Addr,
+		void *Decoder)
+{
+	// scale{5} is asserted as 1 in tblgen.
+	Imm |= 0x20;  
+	MCOperand_CreateImm0(Inst, 64 - Imm);
+	return Success;
+}
+
+static DecodeStatus DecodeFixedPointScaleImm64(MCInst *Inst, unsigned Imm,
+		uint64_t Addr,
+		void *Decoder)
+{
+	MCOperand_CreateImm0(Inst, 64 - Imm);
+	return Success;
+}
+
+static DecodeStatus DecodePCRelLabel19(MCInst *Inst, unsigned Imm,
+		uint64_t Addr, void *Decoder)
+{
+	int64_t ImmVal = Imm;
+
+	// Sign-extend 19-bit immediate.
+	if (ImmVal & (1 << (19 - 1)))
+		ImmVal |= ~((1LL << 19) - 1);
+
+	MCOperand_CreateImm0(Inst, ImmVal);
+	return Success;
+}
+
+static DecodeStatus DecodeMemExtend(MCInst *Inst, unsigned Imm,
+		uint64_t Address, void *Decoder)
+{
+	MCOperand_CreateImm0(Inst, (Imm  >> 1) & 1);
+	MCOperand_CreateImm0(Inst, Imm & 1);
+	return Success;
+}
+
+static DecodeStatus DecodeMRSSystemRegister(MCInst *Inst, unsigned Imm,
+		uint64_t Address, void *Decoder)
+{
+	bool ValidNamed;
+	char result[128];
+
+	Imm |= 0x8000;
+	MCOperand_CreateImm0(Inst, Imm);
+
+	A64SysRegMapper_toString(&AArch64_MRSMapper, Imm, &ValidNamed, result);
+
+	return ValidNamed ? Success : Fail;
+}
+
+static DecodeStatus DecodeMSRSystemRegister(MCInst *Inst, unsigned Imm,
+		uint64_t Address,
+		void *Decoder)
+{
+	bool ValidNamed;
+	char result[128];
+
+	Imm |= 0x8000;
+	MCOperand_CreateImm0(Inst, Imm);
+
+	A64SysRegMapper_toString(&AArch64_MSRMapper, Imm, &ValidNamed, result);
+
+	return ValidNamed ? Success : Fail;
+}
+
+static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn,
+		uint64_t Address,
+		void *Decoder)
+{
+	// This decoder exists to add the dummy Lane operand to the MCInst, which must
+	// be 1 in assembly but has no other real manifestation.
+	unsigned Rd = fieldFromInstruction(Insn, 0, 5);
+	unsigned Rn = fieldFromInstruction(Insn, 5, 5);
+	unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
+
+	if (IsToVec) {
+		DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
+		DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
+	} else {
+		DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
+		DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
+	}
+
+	// Add the lane
+	MCOperand_CreateImm0(Inst, 1);
+
+	return Success;
+}
+
+static DecodeStatus DecodeVecShiftRImm(MCInst *Inst, unsigned Imm,
+		unsigned Add)
+{
+	MCOperand_CreateImm0(Inst, Add - Imm);
+	return Success;
+}
+
+static DecodeStatus DecodeVecShiftLImm(MCInst *Inst, unsigned Imm,
+		unsigned Add)
+{
+	MCOperand_CreateImm0(Inst, (Imm + Add) & (Add - 1));
+	return Success;
+}
+
+static DecodeStatus DecodeVecShiftR64Imm(MCInst *Inst, unsigned Imm,
+		uint64_t Addr, void *Decoder)
+{
+	return DecodeVecShiftRImm(Inst, Imm, 64);
+}
+
+static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst *Inst, unsigned Imm,
+		uint64_t Addr,
+		void *Decoder)
+{
+	return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
+}
+
+static DecodeStatus DecodeVecShiftR32Imm(MCInst *Inst, unsigned Imm,
+		uint64_t Addr, void *Decoder)
+{
+	return DecodeVecShiftRImm(Inst, Imm, 32);
+}
+
+static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst *Inst, unsigned Imm,
+		uint64_t Addr,
+		void *Decoder)
+{
+	return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
+}
+
+static DecodeStatus DecodeVecShiftR16Imm(MCInst *Inst, unsigned Imm,
+		uint64_t Addr, void *Decoder)
+{
+	return DecodeVecShiftRImm(Inst, Imm, 16);
+}
+
+static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst *Inst, unsigned Imm,
+		uint64_t Addr,
+		void *Decoder)
+{
+	return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
+}
+
+static DecodeStatus DecodeVecShiftR8Imm(MCInst *Inst, unsigned Imm,
+		uint64_t Addr, void *Decoder)
+{
+	return DecodeVecShiftRImm(Inst, Imm, 8);
+}
+
+static DecodeStatus DecodeVecShiftL64Imm(MCInst *Inst, unsigned Imm,
+		uint64_t Addr, void *Decoder)
+{
+	return DecodeVecShiftLImm(Inst, Imm, 64);
+}
+
+static DecodeStatus DecodeVecShiftL32Imm(MCInst *Inst, unsigned Imm,
+		uint64_t Addr, void *Decoder)
+{
+	return DecodeVecShiftLImm(Inst, Imm, 32);
+}
+
+static DecodeStatus DecodeVecShiftL16Imm(MCInst *Inst, unsigned Imm,
+		uint64_t Addr, void *Decoder)
+{
+	return DecodeVecShiftLImm(Inst, Imm, 16);
+}
+
+static DecodeStatus DecodeVecShiftL8Imm(MCInst *Inst, unsigned Imm,
+		uint64_t Addr, void *Decoder)
+{
+	return DecodeVecShiftLImm(Inst, Imm, 8);
+}
+
+static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst,
+		uint32_t insn, uint64_t Addr,
+		void *Decoder)
+{
+	unsigned Rd = fieldFromInstruction(insn, 0, 5);
+	unsigned Rn = fieldFromInstruction(insn, 5, 5);
+	unsigned Rm = fieldFromInstruction(insn, 16, 5);
+	unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
+	unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
+	unsigned shift = (shiftHi << 6) | shiftLo;
+
+	switch (MCInst_getOpcode(Inst)) {
+		default:
+			return Fail;
+		case AArch64_ADDWrs:
+		case AArch64_ADDSWrs:
+		case AArch64_SUBWrs:
+		case AArch64_SUBSWrs:
+			// if shift == '11' then ReservedValue()
+			if (shiftHi == 0x3)
+				return Fail;
+			// Deliberate fallthrough
+		case AArch64_ANDWrs:
+		case AArch64_ANDSWrs:
+		case AArch64_BICWrs:
+		case AArch64_BICSWrs:
+		case AArch64_ORRWrs:
+		case AArch64_ORNWrs:
+		case AArch64_EORWrs:
+		case AArch64_EONWrs: {
+				// if sf == '0' and imm6<5> == '1' then ReservedValue()
+				if (shiftLo >> 5 == 1)
+					return Fail;
+				DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
+				DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
+				DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
+				break;
+			}
+		case AArch64_ADDXrs:
+		case AArch64_ADDSXrs:
+		case AArch64_SUBXrs:
+		case AArch64_SUBSXrs:
+				 // if shift == '11' then ReservedValue()
+				 if (shiftHi == 0x3)
+					 return Fail;
+				 // Deliberate fallthrough
+		case AArch64_ANDXrs:
+		case AArch64_ANDSXrs:
+		case AArch64_BICXrs:
+		case AArch64_BICSXrs:
+		case AArch64_ORRXrs:
+		case AArch64_ORNXrs:
+		case AArch64_EORXrs:
+		case AArch64_EONXrs:
+				 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
+				 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
+				 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
+				 break;
+	}
+
+	MCOperand_CreateImm0(Inst, shift);
+	return Success;
+}
+
+static DecodeStatus DecodeMoveImmInstruction(MCInst *Inst, uint32_t insn,
+		uint64_t Addr,
+		void *Decoder)
+{
+	unsigned Rd = fieldFromInstruction(insn, 0, 5);
+	unsigned imm = fieldFromInstruction(insn, 5, 16);
+	unsigned shift = fieldFromInstruction(insn, 21, 2);
+
+	shift <<= 4;
+
+	switch (MCInst_getOpcode(Inst)) {
+		default:
+			return Fail;
+		case AArch64_MOVZWi:
+		case AArch64_MOVNWi:
+		case AArch64_MOVKWi:
+			if (shift & (1U << 5))
+				return Fail;
+			DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
+			break;
+		case AArch64_MOVZXi:
+		case AArch64_MOVNXi:
+		case AArch64_MOVKXi:
+			DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
+			break;
+	}
+
+	if (MCInst_getOpcode(Inst) == AArch64_MOVKWi ||
+			MCInst_getOpcode(Inst) == AArch64_MOVKXi)
+		MCInst_addOperand2(Inst, MCInst_getOperand(Inst, 0));
+
+	MCOperand_CreateImm0(Inst, imm);
+	MCOperand_CreateImm0(Inst, shift);
+	return Success;
+}
+
+static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst,
+		uint32_t insn, uint64_t Addr,
+		void *Decoder)
+{
+	unsigned Rt = fieldFromInstruction(insn, 0, 5);
+	unsigned Rn = fieldFromInstruction(insn, 5, 5);
+	unsigned offset = fieldFromInstruction(insn, 10, 12);
+
+	switch (MCInst_getOpcode(Inst)) {
+		default:
+			return Fail;
+		case AArch64_PRFMui:
+			// Rt is an immediate in prefetch.
+			MCOperand_CreateImm0(Inst, Rt);
+			break;
+		case AArch64_STRBBui:
+		case AArch64_LDRBBui:
+		case AArch64_LDRSBWui:
+		case AArch64_STRHHui:
+		case AArch64_LDRHHui:
+		case AArch64_LDRSHWui:
+		case AArch64_STRWui:
+		case AArch64_LDRWui:
+			DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
+			break;
+		case AArch64_LDRSBXui:
+		case AArch64_LDRSHXui:
+		case AArch64_LDRSWui:
+		case AArch64_STRXui:
+		case AArch64_LDRXui:
+			DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
+			break;
+		case AArch64_LDRQui:
+		case AArch64_STRQui:
+			DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
+			break;
+		case AArch64_LDRDui:
+		case AArch64_STRDui:
+			DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
+			break;
+		case AArch64_LDRSui:
+		case AArch64_STRSui:
+			DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
+			break;
+		case AArch64_LDRHui:
+		case AArch64_STRHui:
+			DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
+			break;
+		case AArch64_LDRBui:
+		case AArch64_STRBui:
+			DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
+			break;
+	}
+
+	DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
+	//if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
+	MCOperand_CreateImm0(Inst, offset);
+
+	return Success;
+}
+
+static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst,
+		uint32_t insn, uint64_t Addr,
+		void *Decoder)
+{
+	bool IsLoad;
+	bool IsIndexed;
+	bool IsFP;
+	unsigned Rt = fieldFromInstruction(insn, 0, 5);
+	unsigned Rn = fieldFromInstruction(insn, 5, 5);
+	int64_t offset = fieldFromInstruction(insn, 12, 9);
+
+	// offset is a 9-bit signed immediate, so sign extend it to
+	// fill the unsigned.
+	if (offset & (1 << (9 - 1)))
+		offset |= ~((1LL << 9) - 1);
+
+	// First operand is always the writeback to the address register, if needed.
+	switch (MCInst_getOpcode(Inst)) {
+		default:
+			break;
+		case AArch64_LDRSBWpre:
+		case AArch64_LDRSHWpre:
+		case AArch64_STRBBpre:
+		case AArch64_LDRBBpre:
+		case AArch64_STRHHpre:
+		case AArch64_LDRHHpre:
+		case AArch64_STRWpre:
+		case AArch64_LDRWpre:
+		case AArch64_LDRSBWpost:
+		case AArch64_LDRSHWpost:
+		case AArch64_STRBBpost:
+		case AArch64_LDRBBpost:
+		case AArch64_STRHHpost:
+		case AArch64_LDRHHpost:
+		case AArch64_STRWpost:
+		case AArch64_LDRWpost:
+		case AArch64_LDRSBXpre:
+		case AArch64_LDRSHXpre:
+		case AArch64_STRXpre:
+		case AArch64_LDRSWpre:
+		case AArch64_LDRXpre:
+		case AArch64_LDRSBXpost:
+		case AArch64_LDRSHXpost:
+		case AArch64_STRXpost:
+		case AArch64_LDRSWpost:
+		case AArch64_LDRXpost:
+		case AArch64_LDRQpre:
+		case AArch64_STRQpre:
+		case AArch64_LDRQpost:
+		case AArch64_STRQpost:
+		case AArch64_LDRDpre:
+		case AArch64_STRDpre:
+		case AArch64_LDRDpost:
+		case AArch64_STRDpost:
+		case AArch64_LDRSpre:
+		case AArch64_STRSpre:
+		case AArch64_LDRSpost:
+		case AArch64_STRSpost:
+		case AArch64_LDRHpre:
+		case AArch64_STRHpre:
+		case AArch64_LDRHpost:
+		case AArch64_STRHpost:
+		case AArch64_LDRBpre:
+		case AArch64_STRBpre:
+		case AArch64_LDRBpost:
+		case AArch64_STRBpost:
+			DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
+			break;
+	}
+
+	switch (MCInst_getOpcode(Inst)) {
+		default:
+			return Fail;
+		case AArch64_PRFUMi:
+			// Rt is an immediate in prefetch.
+			MCOperand_CreateImm0(Inst, Rt);
+			break;
+		case AArch64_STURBBi:
+		case AArch64_LDURBBi:
+		case AArch64_LDURSBWi:
+		case AArch64_STURHHi:
+		case AArch64_LDURHHi:
+		case AArch64_LDURSHWi:
+		case AArch64_STURWi:
+		case AArch64_LDURWi:
+		case AArch64_LDTRSBWi:
+		case AArch64_LDTRSHWi:
+		case AArch64_STTRWi:
+		case AArch64_LDTRWi:
+		case AArch64_STTRHi:
+		case AArch64_LDTRHi:
+		case AArch64_LDTRBi:
+		case AArch64_STTRBi:
+		case AArch64_LDRSBWpre:
+		case AArch64_LDRSHWpre:
+		case AArch64_STRBBpre:
+		case AArch64_LDRBBpre:
+		case AArch64_STRHHpre:
+		case AArch64_LDRHHpre:
+		case AArch64_STRWpre:
+		case AArch64_LDRWpre:
+		case AArch64_LDRSBWpost:
+		case AArch64_LDRSHWpost:
+		case AArch64_STRBBpost:
+		case AArch64_LDRBBpost:
+		case AArch64_STRHHpost:
+		case AArch64_LDRHHpost:
+		case AArch64_STRWpost:
+		case AArch64_LDRWpost:
+			DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
+			break;
+		case AArch64_LDURSBXi:
+		case AArch64_LDURSHXi:
+		case AArch64_LDURSWi:
+		case AArch64_STURXi:
+		case AArch64_LDURXi:
+		case AArch64_LDTRSBXi:
+		case AArch64_LDTRSHXi:
+		case AArch64_LDTRSWi:
+		case AArch64_STTRXi:
+		case AArch64_LDTRXi:
+		case AArch64_LDRSBXpre:
+		case AArch64_LDRSHXpre:
+		case AArch64_STRXpre:
+		case AArch64_LDRSWpre:
+		case AArch64_LDRXpre:
+		case AArch64_LDRSBXpost:
+		case AArch64_LDRSHXpost:
+		case AArch64_STRXpost:
+		case AArch64_LDRSWpost:
+		case AArch64_LDRXpost:
+			DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
+			break;
+		case AArch64_LDURQi:
+		case AArch64_STURQi:
+		case AArch64_LDRQpre:
+		case AArch64_STRQpre:
+		case AArch64_LDRQpost:
+		case AArch64_STRQpost:
+			DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
+			break;
+		case AArch64_LDURDi:
+		case AArch64_STURDi:
+		case AArch64_LDRDpre:
+		case AArch64_STRDpre:
+		case AArch64_LDRDpost:
+		case AArch64_STRDpost:
+			DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
+			break;
+		case AArch64_LDURSi:
+		case AArch64_STURSi:
+		case AArch64_LDRSpre:
+		case AArch64_STRSpre:
+		case AArch64_LDRSpost:
+		case AArch64_STRSpost:
+			DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
+			break;
+		case AArch64_LDURHi:
+		case AArch64_STURHi:
+		case AArch64_LDRHpre:
+		case AArch64_STRHpre:
+		case AArch64_LDRHpost:
+		case AArch64_STRHpost:
+			DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
+			break;
+		case AArch64_LDURBi:
+		case AArch64_STURBi:
+		case AArch64_LDRBpre:
+		case AArch64_STRBpre:
+		case AArch64_LDRBpost:
+		case AArch64_STRBpost:
+			DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
+			break;
+	}
+
+	DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
+	MCOperand_CreateImm0(Inst, offset);
+
+	IsLoad = fieldFromInstruction(insn, 22, 1) != 0;
+	IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
+	IsFP = fieldFromInstruction(insn, 26, 1) != 0;
+
+	// Cannot write back to a transfer register (but xzr != sp).
+	if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
+		return SoftFail;
+
+	return Success;
+}
+
+static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst,
+		uint32_t insn, uint64_t Addr,
+		void *Decoder)
+{
+	unsigned Rt = fieldFromInstruction(insn, 0, 5);
+	unsigned Rn = fieldFromInstruction(insn, 5, 5);
+	unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
+	unsigned Rs = fieldFromInstruction(insn, 16, 5);
+	unsigned Opcode = MCInst_getOpcode(Inst);
+
+	switch (Opcode) {
+		default:
+			return Fail;
+		case AArch64_STLXRW:
+		case AArch64_STLXRB:
+		case AArch64_STLXRH:
+		case AArch64_STXRW:
+		case AArch64_STXRB:
+		case AArch64_STXRH:
+			DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
+			// FALLTHROUGH
+		case AArch64_LDARW:
+		case AArch64_LDARB:
+		case AArch64_LDARH:
+		case AArch64_LDAXRW:
+		case AArch64_LDAXRB:
+		case AArch64_LDAXRH:
+		case AArch64_LDXRW:
+		case AArch64_LDXRB:
+		case AArch64_LDXRH:
+		case AArch64_STLRW:
+		case AArch64_STLRB:
+		case AArch64_STLRH:
+			DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
+			break;
+		case AArch64_STLXRX:
+		case AArch64_STXRX:
+			DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
+			// FALLTHROUGH
+		case AArch64_LDARX:
+		case AArch64_LDAXRX:
+		case AArch64_LDXRX:
+		case AArch64_STLRX:
+			DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
+			break;
+		case AArch64_STLXPW:
+		case AArch64_STXPW:
+			DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
+			// FALLTHROUGH
+		case AArch64_LDAXPW:
+		case AArch64_LDXPW:
+			DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
+			DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
+			break;
+		case AArch64_STLXPX:
+		case AArch64_STXPX:
+			DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
+			// FALLTHROUGH
+		case AArch64_LDAXPX:
+		case AArch64_LDXPX:
+			DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
+			DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
+			break;
+	}
+
+	DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
+
+	// You shouldn't load to the same register twice in an instruction...
+	if ((Opcode == AArch64_LDAXPW || Opcode == AArch64_LDXPW ||
+				Opcode == AArch64_LDAXPX || Opcode == AArch64_LDXPX) &&
+			Rt == Rt2)
+		return SoftFail;
+
+	return Success;
+}
+
+static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn,
+		uint64_t Addr,
+		void *Decoder)
+{
+	unsigned Rt = fieldFromInstruction(insn, 0, 5);
+	unsigned Rn = fieldFromInstruction(insn, 5, 5);
+	unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
+	int64_t offset = fieldFromInstruction(insn, 15, 7);
+	bool IsLoad = fieldFromInstruction(insn, 22, 1) != 0;
+	unsigned Opcode = MCInst_getOpcode(Inst);
+	bool NeedsDisjointWritebackTransfer = false;
+
+	// offset is a 7-bit signed immediate, so sign extend it to
+	// fill the unsigned.
+	if (offset & (1 << (7 - 1)))
+		offset |= ~((1LL << 7) - 1);
+
+	// First operand is always writeback of base register.
+	switch (Opcode) {
+		default:
+			break;
+		case AArch64_LDPXpost:
+		case AArch64_STPXpost:
+		case AArch64_LDPSWpost:
+		case AArch64_LDPXpre:
+		case AArch64_STPXpre:
+		case AArch64_LDPSWpre:
+		case AArch64_LDPWpost:
+		case AArch64_STPWpost:
+		case AArch64_LDPWpre:
+		case AArch64_STPWpre:
+		case AArch64_LDPQpost:
+		case AArch64_STPQpost:
+		case AArch64_LDPQpre:
+		case AArch64_STPQpre:
+		case AArch64_LDPDpost:
+		case AArch64_STPDpost:
+		case AArch64_LDPDpre:
+		case AArch64_STPDpre:
+		case AArch64_LDPSpost:
+		case AArch64_STPSpost:
+		case AArch64_LDPSpre:
+		case AArch64_STPSpre:
+			DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
+			break;
+	}
+
+	switch (Opcode) {
+		default:
+			return Fail;
+		case AArch64_LDPXpost:
+		case AArch64_STPXpost:
+		case AArch64_LDPSWpost:
+		case AArch64_LDPXpre:
+		case AArch64_STPXpre:
+		case AArch64_LDPSWpre:
+			NeedsDisjointWritebackTransfer = true;
+			// Fallthrough
+		case AArch64_LDNPXi:
+		case AArch64_STNPXi:
+		case AArch64_LDPXi:
+		case AArch64_STPXi:
+		case AArch64_LDPSWi:
+			DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
+			DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
+			break;
+		case AArch64_LDPWpost:
+		case AArch64_STPWpost:
+		case AArch64_LDPWpre:
+		case AArch64_STPWpre:
+			NeedsDisjointWritebackTransfer = true;
+			// Fallthrough
+		case AArch64_LDNPWi:
+		case AArch64_STNPWi:
+		case AArch64_LDPWi:
+		case AArch64_STPWi:
+			DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
+			DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
+			break;
+		case AArch64_LDNPQi:
+		case AArch64_STNPQi:
+		case AArch64_LDPQpost:
+		case AArch64_STPQpost:
+		case AArch64_LDPQi:
+		case AArch64_STPQi:
+		case AArch64_LDPQpre:
+		case AArch64_STPQpre:
+			DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
+			DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
+			break;
+		case AArch64_LDNPDi:
+		case AArch64_STNPDi:
+		case AArch64_LDPDpost:
+		case AArch64_STPDpost:
+		case AArch64_LDPDi:
+		case AArch64_STPDi:
+		case AArch64_LDPDpre:
+		case AArch64_STPDpre:
+			DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
+			DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
+			break;
+		case AArch64_LDNPSi:
+		case AArch64_STNPSi:
+		case AArch64_LDPSpost:
+		case AArch64_STPSpost:
+		case AArch64_LDPSi:
+		case AArch64_STPSi:
+		case AArch64_LDPSpre:
+		case AArch64_STPSpre:
+			DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
+			DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
+			break;
+	}
+
+	DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
+	MCOperand_CreateImm0(Inst, offset);
+
+	// You shouldn't load to the same register twice in an instruction...
+	if (IsLoad && Rt == Rt2)
+		return SoftFail;
+
+	// ... or do any operation that writes-back to a transfer register. But note
+	// that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
+	if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
+		return SoftFail;
+
+	return Success;
+}
+
+static DecodeStatus DecodeAddSubERegInstruction(MCInst *Inst,
+		uint32_t insn, uint64_t Addr,
+		void *Decoder)
+{
+  unsigned Rd, Rn, Rm;
+  unsigned extend = fieldFromInstruction(insn, 10, 6);
+  unsigned shift = extend & 0x7;
+
+  if (shift > 4)
+    return Fail;
+
+  Rd = fieldFromInstruction(insn, 0, 5);
+  Rn = fieldFromInstruction(insn, 5, 5);
+  Rm = fieldFromInstruction(insn, 16, 5);
+
+  switch (MCInst_getOpcode(Inst)) {
+  default:
+    return Fail;
+  case AArch64_ADDWrx:
+  case AArch64_SUBWrx:
+    DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
+    DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
+    DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
+    break;
+  case AArch64_ADDSWrx:
+  case AArch64_SUBSWrx:
+    DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
+    DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
+    DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
+    break;
+  case AArch64_ADDXrx:
+  case AArch64_SUBXrx:
+    DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
+    DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
+    DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
+    break;
+  case AArch64_ADDSXrx:
+  case AArch64_SUBSXrx:
+    DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
+    DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
+    DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
+    break;
+  case AArch64_ADDXrx64:
+  case AArch64_SUBXrx64:
+    DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
+    DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
+    DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
+    break;
+  case AArch64_SUBSXrx64:
+  case AArch64_ADDSXrx64:
+    DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
+    DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
+    DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
+    break;
+  }
+
+  MCOperand_CreateImm0(Inst, extend);
+  return Success;
+}
+
+static DecodeStatus DecodeLogicalImmInstruction(MCInst *Inst,
+		uint32_t insn, uint64_t Addr,
+		void *Decoder)
+{
+	unsigned Rd = fieldFromInstruction(insn, 0, 5);
+	unsigned Rn = fieldFromInstruction(insn, 5, 5);
+	unsigned Datasize = fieldFromInstruction(insn, 31, 1);
+	unsigned imm;
+
+	if (Datasize) {
+		if (MCInst_getOpcode(Inst) == AArch64_ANDSXri)
+			DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
+		else
+			DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
+		DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
+		imm = fieldFromInstruction(insn, 10, 13);
+		if (!AArch64_AM_isValidDecodeLogicalImmediate(imm, 64))
+			return Fail;
+	} else {
+		if (MCInst_getOpcode(Inst) == AArch64_ANDSWri)
+			DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
+		else
+			DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
+		DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
+		imm = fieldFromInstruction(insn, 10, 12);
+		if (!AArch64_AM_isValidDecodeLogicalImmediate(imm, 32))
+			return Fail;
+	}
+
+	MCOperand_CreateImm0(Inst, imm);
+	return Success;
+}
+
+static DecodeStatus DecodeModImmInstruction(MCInst *Inst, uint32_t insn,
+		uint64_t Addr,
+		void *Decoder)
+{
+	unsigned Rd = fieldFromInstruction(insn, 0, 5);
+	unsigned cmode = fieldFromInstruction(insn, 12, 4);
+	unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
+	imm |= fieldFromInstruction(insn, 5, 5);
+
+	if (MCInst_getOpcode(Inst) == AArch64_MOVID)
+		DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
+	else
+		DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
+
+	MCOperand_CreateImm0(Inst, imm);
+
+	switch (MCInst_getOpcode(Inst)) {
+		default:
+			break;
+		case AArch64_MOVIv4i16:
+		case AArch64_MOVIv8i16:
+		case AArch64_MVNIv4i16:
+		case AArch64_MVNIv8i16:
+		case AArch64_MOVIv2i32:
+		case AArch64_MOVIv4i32:
+		case AArch64_MVNIv2i32:
+		case AArch64_MVNIv4i32:
+			MCOperand_CreateImm0(Inst, (cmode & 6) << 2);
+			break;
+		case AArch64_MOVIv2s_msl:
+		case AArch64_MOVIv4s_msl:
+		case AArch64_MVNIv2s_msl:
+		case AArch64_MVNIv4s_msl:
+			MCOperand_CreateImm0(Inst, cmode & 1 ? 0x110 : 0x108);
+			break;
+	}
+
+	return Success;
+}
+
+static DecodeStatus DecodeModImmTiedInstruction(MCInst *Inst,
+		uint32_t insn, uint64_t Addr,
+		void *Decoder)
+{
+	unsigned Rd = fieldFromInstruction(insn, 0, 5);
+	unsigned cmode = fieldFromInstruction(insn, 12, 4);
+	unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
+	imm |= fieldFromInstruction(insn, 5, 5);
+
+	// Tied operands added twice.
+	DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
+	DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
+
+	MCOperand_CreateImm0(Inst, imm);
+	MCOperand_CreateImm0(Inst, (cmode & 6) << 2);
+
+	return Success;
+}
+
+static DecodeStatus DecodeAdrInstruction(MCInst *Inst, uint32_t insn,
+		uint64_t Addr, void *Decoder)
+{
+	unsigned Rd = fieldFromInstruction(insn, 0, 5);
+	int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
+	imm |= fieldFromInstruction(insn, 29, 2);
+
+	// Sign-extend the 21-bit immediate.
+	if (imm & (1 << (21 - 1)))
+		imm |= ~((1LL << 21) - 1);
+
+	DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
+	//if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
+	MCOperand_CreateImm0(Inst, imm);
+
+	return Success;
+}
+
+static DecodeStatus DecodeBaseAddSubImm(MCInst *Inst, uint32_t insn,
+		uint64_t Addr, void *Decoder)
+{
+	unsigned Rd = fieldFromInstruction(insn, 0, 5);
+	unsigned Rn = fieldFromInstruction(insn, 5, 5);
+	unsigned Imm = fieldFromInstruction(insn, 10, 14);
+	unsigned S = fieldFromInstruction(insn, 29, 1);
+	unsigned Datasize = fieldFromInstruction(insn, 31, 1);
+
+	unsigned ShifterVal = (Imm >> 12) & 3;
+	unsigned ImmVal = Imm & 0xFFF;
+
+	if (ShifterVal != 0 && ShifterVal != 1)
+		return Fail;
+
+	if (Datasize) {
+		if (Rd == 31 && !S)
+			DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
+		else
+			DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
+		DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
+	} else {
+		if (Rd == 31 && !S)
+			DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
+		else
+			DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
+		DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
+	}
+
+	//if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
+	MCOperand_CreateImm0(Inst, ImmVal);
+	MCOperand_CreateImm0(Inst, 12 * ShifterVal);
+	return Success;
+}
+
+static DecodeStatus DecodeUnconditionalBranch(MCInst *Inst, uint32_t insn,
+		uint64_t Addr,
+		void *Decoder)
+{
+	int64_t imm = fieldFromInstruction(insn, 0, 26);
+
+	// Sign-extend the 26-bit immediate.
+	if (imm & (1 << (26 - 1)))
+		imm |= ~((1LL << 26) - 1);
+
+	// if (!Dis->tryAddingSymbolicOperand(Inst, imm << 2, Addr, true, 0, 4))
+	MCOperand_CreateImm0(Inst, imm);
+
+	return Success;
+}
+
+static DecodeStatus DecodeSystemPStateInstruction(MCInst *Inst,
+		uint32_t insn, uint64_t Addr,
+		void *Decoder)
+{
+	uint64_t op1 = fieldFromInstruction(insn, 16, 3);
+	uint64_t op2 = fieldFromInstruction(insn, 5, 3);
+	uint64_t crm = fieldFromInstruction(insn, 8, 4);
+	bool ValidNamed;
+	uint64_t pstate_field = (op1 << 3) | op2;
+
+	MCOperand_CreateImm0(Inst, pstate_field);
+	MCOperand_CreateImm0(Inst, crm);
+
+	A64NamedImmMapper_toString(&A64PState_PStateMapper, pstate_field, &ValidNamed);
+
+	return ValidNamed ? Success : Fail;
+}
+
+static DecodeStatus DecodeTestAndBranch(MCInst *Inst, uint32_t insn,
+		uint64_t Addr, void *Decoder)
+{
+	uint64_t Rt = fieldFromInstruction(insn, 0, 5);
+	uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
+	int64_t dst = fieldFromInstruction(insn, 5, 14);
+
+	bit |= fieldFromInstruction(insn, 19, 5);
+
+	// Sign-extend 14-bit immediate.
+	if (dst & (1 << (14 - 1)))
+		dst |= ~((1LL << 14) - 1);
+
+	if (fieldFromInstruction(insn, 31, 1) == 0)
+		DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
+	else
+		DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
+
+	MCOperand_CreateImm0(Inst, bit);
+	//if (!Dis->tryAddingSymbolicOperand(Inst, dst << 2, Addr, true, 0, 4))
+	MCOperand_CreateImm0(Inst, dst);
+
+	return Success;
+}
+
+void AArch64_init(MCRegisterInfo *MRI)
+{
+	/*
+		InitMCRegisterInfo(AArch64RegDesc, 420,
+			RA, PC,
+			AArch64MCRegisterClasses, 43,
+			AArch64RegUnitRoots, 66, AArch64RegDiffLists,
+			AArch64RegStrings,
+			AArch64SubRegIdxLists, 53,
+			AArch64SubRegIdxRanges,
+			AArch64RegEncodingTable);
+	*/
+
+	MCRegisterInfo_InitMCRegisterInfo(MRI, AArch64RegDesc, 420,
+			0, 0, 
+			AArch64MCRegisterClasses, 43,
+			0, 0, AArch64RegDiffLists,
+			0, 
+			AArch64SubRegIdxLists, 53,
+			0);
+}
+
+#endif
diff --git a/arch/AArch64/AArch64Disassembler.h b/arch/AArch64/AArch64Disassembler.h
new file mode 100644
index 0000000..9879d7c
--- /dev/null
+++ b/arch/AArch64/AArch64Disassembler.h
@@ -0,0 +1,20 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_AARCH64_DISASSEMBLER_H
+#define CS_AARCH64_DISASSEMBLER_H
+
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
+#include <stdint.h>
+#endif
+
+#include "../../include/capstone.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCInst.h"
+
+void AArch64_init(MCRegisterInfo *MRI);
+
+bool AArch64_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+		MCInst *instr, uint16_t *size, uint64_t address, void *info);
+
+#endif
diff --git a/arch/AArch64/AArch64GenAsmWriter.inc b/arch/AArch64/AArch64GenAsmWriter.inc
new file mode 100644
index 0000000..008d285
--- /dev/null
+++ b/arch/AArch64/AArch64GenAsmWriter.inc
@@ -0,0 +1,12607 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|*Assembly Writer Source Fragment                                             *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+/// printInstruction - This method is automatically generated by tablegen
+/// from the instruction set description.
+static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
+{
+  static const uint32_t OpInfo[] = {
+    0U,	// PHI
+    0U,	// INLINEASM
+    0U,	// CFI_INSTRUCTION
+    0U,	// EH_LABEL
+    0U,	// GC_LABEL
+    0U,	// KILL
+    0U,	// EXTRACT_SUBREG
+    0U,	// INSERT_SUBREG
+    0U,	// IMPLICIT_DEF
+    0U,	// SUBREG_TO_REG
+    0U,	// COPY_TO_REGCLASS
+    2694U,	// DBG_VALUE
+    0U,	// REG_SEQUENCE
+    0U,	// COPY
+    2687U,	// BUNDLE
+    2704U,	// LIFETIME_START
+    2674U,	// LIFETIME_END
+    0U,	// STACKMAP
+    0U,	// PATCHPOINT
+    0U,	// LOAD_STACK_GUARD
+    6182U,	// ABSv16i8
+    553920550U,	// ABSv1i64
+    1074272294U,	// ABSv2i32
+    1611405350U,	// ABSv2i64
+    2148538406U,	// ABSv4i16
+    2685671462U,	// ABSv4i32
+    3222804518U,	// ABSv8i16
+    3759937574U,	// ABSv8i8
+    17049662U,	// ADCSWr
+    17049662U,	// ADCSXr
+    17048298U,	// ADCWr
+    17048298U,	// ADCXr
+    537400863U,	// ADDHNv2i64_v2i32
+    571748634U,	// ADDHNv2i64_v4i32
+    1074796063U,	// ADDHNv4i32_v4i16
+    1108881690U,	// ADDHNv4i32_v8i16
+    1644179738U,	// ADDHNv8i16_v16i8
+    1612453407U,	// ADDHNv8i16_v8i8
+    2147489464U,	// ADDPv16i8
+    2684884664U,	// ADDPv2i32
+    537663160U,	// ADDPv2i64
+    1610884792U,	// ADDPv2i64p
+    3222279864U,	// ADDPv4i16
+    1075058360U,	// ADDPv4i32
+    1612191416U,	// ADDPv8i16
+    3759937208U,	// ADDPv8i8
+    17049674U,	// ADDSWri
+    0U,	// ADDSWrr
+    17049674U,	// ADDSWrs
+    17049674U,	// ADDSWrx
+    17049674U,	// ADDSXri
+    0U,	// ADDSXrr
+    17049674U,	// ADDSXrs
+    17049674U,	// ADDSXrx
+    17049674U,	// ADDSXrx64
+    272671U,	// ADDVv16i8v
+    2147756319U,	// ADDVv4i16v
+    2684627231U,	// ADDVv4i32v
+    3221498143U,	// ADDVv8i16v
+    3758369055U,	// ADDVv8i8v
+    17048359U,	// ADDWri
+    0U,	// ADDWrr
+    17048359U,	// ADDWrs
+    17048359U,	// ADDWrx
+    17048359U,	// ADDXri
+    0U,	// ADDXrr
+    17048359U,	// ADDXrs
+    17048359U,	// ADDXrx
+    17048359U,	// ADDXrx64
+    2147488551U,	// ADDv16i8
+    17048359U,	// ADDv1i64
+    2684883751U,	// ADDv2i32
+    537662247U,	// ADDv2i64
+    3222278951U,	// ADDv4i16
+    1075057447U,	// ADDv4i32
+    1612190503U,	// ADDv8i16
+    3759936295U,	// ADDv8i8
+    0U,	// ADJCALLSTACKDOWN
+    0U,	// ADJCALLSTACKUP
+    553920403U,	// ADR
+    50603811U,	// ADRP
+    33567598U,	// AESDrr
+    33567656U,	// AESErr
+    4852U,	// AESIMCrr
+    4860U,	// AESMCrr
+    17049680U,	// ANDSWri
+    0U,	// ANDSWrr
+    17049680U,	// ANDSWrs
+    17049680U,	// ANDSXri
+    0U,	// ANDSXrr
+    17049680U,	// ANDSXrs
+    17048425U,	// ANDWri
+    0U,	// ANDWrr
+    17048425U,	// ANDWrs
+    17048425U,	// ANDXri
+    0U,	// ANDXrr
+    17048425U,	// ANDXrs
+    2147488617U,	// ANDv16i8
+    3759936361U,	// ANDv8i8
+    17049553U,	// ASRVWr
+    17049553U,	// ASRVXr
+    16935U,	// B
+    67380710U,	// BFMWri
+    67380710U,	// BFMXri
+    0U,	// BICSWrr
+    17049668U,	// BICSWrs
+    0U,	// BICSXrr
+    17049668U,	// BICSXrs
+    0U,	// BICWrr
+    17048303U,	// BICWrs
+    0U,	// BICXrr
+    17048303U,	// BICXrs
+    2147488495U,	// BICv16i8
+    84423407U,	// BICv2i32
+    84947695U,	// BICv4i16
+    85209839U,	// BICv4i32
+    85471983U,	// BICv8i16
+    3759936239U,	// BICv8i8
+    2147488704U,	// BIFv16i8
+    3759936448U,	// BIFv8i8
+    2181052603U,	// BITv16i8
+    3793500347U,	// BITv8i8
+    17641U,	// BL
+    2107319U,	// BLR
+    2107279U,	// BR
+    21688U,	// BRK
+    2181051810U,	// BSLv16i8
+    3793499554U,	// BSLv8i8
+    27247U,	// Bcc
+    100936257U,	// CBNZW
+    100936257U,	// CBNZX
+    100936242U,	// CBZW
+    100936242U,	// CBZX
+    17049144U,	// CCMNWi
+    17049144U,	// CCMNWr
+    17049144U,	// CCMNXi
+    17049144U,	// CCMNXr
+    17049316U,	// CCMPWi
+    17049316U,	// CCMPWr
+    17049316U,	// CCMPXi
+    17049316U,	// CCMPXr
+    2107924U,	// CLREX
+    553920604U,	// CLSWr
+    553920604U,	// CLSXr
+    6236U,	// CLSv16i8
+    1074272348U,	// CLSv2i32
+    2148538460U,	// CLSv4i16
+    2685671516U,	// CLSv4i32
+    3222804572U,	// CLSv8i16
+    3759937628U,	// CLSv8i8
+    553921084U,	// CLZWr
+    553921084U,	// CLZXr
+    6716U,	// CLZv16i8
+    1074272828U,	// CLZv2i32
+    2148538940U,	// CLZv4i16
+    2685671996U,	// CLZv4i32
+    3222805052U,	// CLZv8i16
+    3759938108U,	// CLZv8i8
+    2147489643U,	// CMEQv16i8
+    5995U,	// CMEQv16i8rz
+    17049451U,	// CMEQv1i64
+    553920363U,	// CMEQv1i64rz
+    2684884843U,	// CMEQv2i32
+    1074272107U,	// CMEQv2i32rz
+    537663339U,	// CMEQv2i64
+    1611405163U,	// CMEQv2i64rz
+    3222280043U,	// CMEQv4i16
+    2148538219U,	// CMEQv4i16rz
+    1075058539U,	// CMEQv4i32
+    2685671275U,	// CMEQv4i32rz
+    1612191595U,	// CMEQv8i16
+    3222804331U,	// CMEQv8i16rz
+    3759937387U,	// CMEQv8i8
+    3759937387U,	// CMEQv8i8rz
+    2147488636U,	// CMGEv16i8
+    4988U,	// CMGEv16i8rz
+    17048444U,	// CMGEv1i64
+    553919356U,	// CMGEv1i64rz
+    2684883836U,	// CMGEv2i32
+    1074271100U,	// CMGEv2i32rz
+    537662332U,	// CMGEv2i64
+    1611404156U,	// CMGEv2i64rz
+    3222279036U,	// CMGEv4i16
+    2148537212U,	// CMGEv4i16rz
+    1075057532U,	// CMGEv4i32
+    2685670268U,	// CMGEv4i32rz
+    1612190588U,	// CMGEv8i16
+    3222803324U,	// CMGEv8i16rz
+    3759936380U,	// CMGEv8i8
+    3759936380U,	// CMGEv8i8rz
+    2147489972U,	// CMGTv16i8
+    6324U,	// CMGTv16i8rz
+    17049780U,	// CMGTv1i64
+    553920692U,	// CMGTv1i64rz
+    2684885172U,	// CMGTv2i32
+    1074272436U,	// CMGTv2i32rz
+    537663668U,	// CMGTv2i64
+    1611405492U,	// CMGTv2i64rz
+    3222280372U,	// CMGTv4i16
+    2148538548U,	// CMGTv4i16rz
+    1075058868U,	// CMGTv4i32
+    2685671604U,	// CMGTv4i32rz
+    1612191924U,	// CMGTv8i16
+    3222804660U,	// CMGTv8i16rz
+    3759937716U,	// CMGTv8i8
+    3759937716U,	// CMGTv8i8rz
+    2147488916U,	// CMHIv16i8
+    17048724U,	// CMHIv1i64
+    2684884116U,	// CMHIv2i32
+    537662612U,	// CMHIv2i64
+    3222279316U,	// CMHIv4i16
+    1075057812U,	// CMHIv4i32
+    1612190868U,	// CMHIv8i16
+    3759936660U,	// CMHIv8i8
+    2147489878U,	// CMHSv16i8
+    17049686U,	// CMHSv1i64
+    2684885078U,	// CMHSv2i32
+    537663574U,	// CMHSv2i64
+    3222280278U,	// CMHSv4i16
+    1075058774U,	// CMHSv4i32
+    1612191830U,	// CMHSv8i16
+    3759937622U,	// CMHSv8i8
+    4995U,	// CMLEv16i8rz
+    553919363U,	// CMLEv1i64rz
+    1074271107U,	// CMLEv2i32rz
+    1611404163U,	// CMLEv2i64rz
+    2148537219U,	// CMLEv4i16rz
+    2685670275U,	// CMLEv4i32rz
+    3222803331U,	// CMLEv8i16rz
+    3759936387U,	// CMLEv8i8rz
+    6342U,	// CMLTv16i8rz
+    553920710U,	// CMLTv1i64rz
+    1074272454U,	// CMLTv2i32rz
+    1611405510U,	// CMLTv2i64rz
+    2148538566U,	// CMLTv4i16rz
+    2685671622U,	// CMLTv4i32rz
+    3222804678U,	// CMLTv8i16rz
+    3759937734U,	// CMLTv8i8rz
+    2147490013U,	// CMTSTv16i8
+    17049821U,	// CMTSTv1i64
+    2684885213U,	// CMTSTv2i32
+    537663709U,	// CMTSTv2i64
+    3222280413U,	// CMTSTv4i16
+    1075058909U,	// CMTSTv4i32
+    1612191965U,	// CMTSTv8i16
+    3759937757U,	// CMTSTv8i8
+    6348U,	// CNTv16i8
+    3759937740U,	// CNTv8i8
+    272763U,	// CPYi16
+    537143675U,	// CPYi32
+    1074014587U,	// CPYi64
+    1610885499U,	// CPYi8
+    17048098U,	// CRC32Brr
+    17048106U,	// CRC32CBrr
+    17048575U,	// CRC32CHrr
+    17050039U,	// CRC32CWrr
+    17050123U,	// CRC32CXrr
+    17048558U,	// CRC32Hrr
+    17050017U,	// CRC32Wrr
+    17050092U,	// CRC32Xrr
+    17048888U,	// CSELWr
+    17048888U,	// CSELXr
+    17048323U,	// CSINCWr
+    17048323U,	// CSINCXr
+    17049971U,	// CSINVWr
+    17049971U,	// CSINVXr
+    17048544U,	// CSNEGWr
+    17048544U,	// CSNEGXr
+    20524U,	// DCPS1
+    20889U,	// DCPS2
+    20938U,	// DCPS3
+    29235U,	// DMB
+    2719U,	// DRPS
+    29324U,	// DSB
+    553654070U,	// DUPv16i8gpr
+    1610618678U,	// DUPv16i8lane
+    554178358U,	// DUPv2i32gpr
+    537401142U,	// DUPv2i32lane
+    554440502U,	// DUPv2i64gpr
+    1074534198U,	// DUPv2i64lane
+    554702646U,	// DUPv4i16gpr
+    1054518U,	// DUPv4i16lane
+    554964790U,	// DUPv4i32gpr
+    538187574U,	// DUPv4i32lane
+    555226934U,	// DUPv8i16gpr
+    1578806U,	// DUPv8i16lane
+    555489078U,	// DUPv8i8gpr
+    1612453686U,	// DUPv8i8lane
+    0U,	// EONWrr
+    17049150U,	// EONWrs
+    0U,	// EONXrr
+    17049150U,	// EONXrs
+    17049538U,	// EORWri
+    0U,	// EORWrr
+    17049538U,	// EORWrs
+    17049538U,	// EORXri
+    0U,	// EORXrr
+    17049538U,	// EORXrs
+    2147489730U,	// EORv16i8
+    3759937474U,	// EORv8i8
+    2724U,	// ERET
+    17049585U,	// EXTRWrri
+    17049585U,	// EXTRXrri
+    2147490026U,	// EXTv16i8
+    3759937770U,	// EXTv8i8
+    0U,	// F128CSEL
+    17048340U,	// FABD32
+    17048340U,	// FABD64
+    2684883732U,	// FABDv2f32
+    537662228U,	// FABDv2f64
+    1075057428U,	// FABDv4f32
+    553920549U,	// FABSDr
+    553920549U,	// FABSSr
+    1074272293U,	// FABSv2f32
+    1611405349U,	// FABSv2f64
+    2685671461U,	// FABSv4f32
+    17048436U,	// FACGE32
+    17048436U,	// FACGE64
+    2684883828U,	// FACGEv2f32
+    537662324U,	// FACGEv2f64
+    1075057524U,	// FACGEv4f32
+    17049772U,	// FACGT32
+    17049772U,	// FACGT64
+    2684885164U,	// FACGTv2f32
+    537663660U,	// FACGTv2f64
+    1075058860U,	// FACGTv4f32
+    17048358U,	// FADDDrr
+    2684884663U,	// FADDPv2f32
+    537663159U,	// FADDPv2f64
+    1074013879U,	// FADDPv2i32p
+    1610884791U,	// FADDPv2i64p
+    1075058359U,	// FADDPv4f32
+    17048358U,	// FADDSrr
+    2684883750U,	// FADDv2f32
+    537662246U,	// FADDv2f64
+    1075057446U,	// FADDv4f32
+    17049315U,	// FCCMPDrr
+    17048473U,	// FCCMPEDrr
+    17048473U,	// FCCMPESrr
+    17049315U,	// FCCMPSrr
+    17049450U,	// FCMEQ32
+    17049450U,	// FCMEQ64
+    2164533098U,	// FCMEQv1i32rz
+    2164533098U,	// FCMEQv1i64rz
+    2684884842U,	// FCMEQv2f32
+    537663338U,	// FCMEQv2f64
+    2684884842U,	// FCMEQv2i32rz
+    3222017898U,	// FCMEQv2i64rz
+    1075058538U,	// FCMEQv4f32
+    3759413098U,	// FCMEQv4i32rz
+    17048443U,	// FCMGE32
+    17048443U,	// FCMGE64
+    2164532091U,	// FCMGEv1i32rz
+    2164532091U,	// FCMGEv1i64rz
+    2684883835U,	// FCMGEv2f32
+    537662331U,	// FCMGEv2f64
+    2684883835U,	// FCMGEv2i32rz
+    3222016891U,	// FCMGEv2i64rz
+    1075057531U,	// FCMGEv4f32
+    3759412091U,	// FCMGEv4i32rz
+    17049779U,	// FCMGT32
+    17049779U,	// FCMGT64
+    2164533427U,	// FCMGTv1i32rz
+    2164533427U,	// FCMGTv1i64rz
+    2684885171U,	// FCMGTv2f32
+    537663667U,	// FCMGTv2f64
+    2684885171U,	// FCMGTv2i32rz
+    3222018227U,	// FCMGTv2i64rz
+    1075058867U,	// FCMGTv4f32
+    3759413427U,	// FCMGTv4i32rz
+    2164532098U,	// FCMLEv1i32rz
+    2164532098U,	// FCMLEv1i64rz
+    2684883842U,	// FCMLEv2i32rz
+    3222016898U,	// FCMLEv2i64rz
+    3759412098U,	// FCMLEv4i32rz
+    2164533445U,	// FCMLTv1i32rz
+    2164533445U,	// FCMLTv1i64rz
+    2684885189U,	// FCMLTv2i32rz
+    3222018245U,	// FCMLTv2i64rz
+    3759413445U,	// FCMLTv4i32rz
+    2369258U,	// FCMPDri
+    553920234U,	// FCMPDrr
+    2368417U,	// FCMPEDri
+    553919393U,	// FCMPEDrr
+    2368417U,	// FCMPESri
+    553919393U,	// FCMPESrr
+    2369258U,	// FCMPSri
+    553920234U,	// FCMPSrr
+    17048887U,	// FCSELDrrr
+    17048887U,	// FCSELSrrr
+    553920541U,	// FCVTASUWDr
+    553920541U,	// FCVTASUWSr
+    553920541U,	// FCVTASUXDr
+    553920541U,	// FCVTASUXSr
+    553920541U,	// FCVTASv1i32
+    553920541U,	// FCVTASv1i64
+    1074272285U,	// FCVTASv2f32
+    1611405341U,	// FCVTASv2f64
+    2685671453U,	// FCVTASv4f32
+    553920751U,	// FCVTAUUWDr
+    553920751U,	// FCVTAUUWSr
+    553920751U,	// FCVTAUUXDr
+    553920751U,	// FCVTAUUXSr
+    553920751U,	// FCVTAUv1i32
+    553920751U,	// FCVTAUv1i64
+    1074272495U,	// FCVTAUv2f32
+    1611405551U,	// FCVTAUv2f64
+    2685671663U,	// FCVTAUv4f32
+    553920740U,	// FCVTDHr
+    553920740U,	// FCVTDSr
+    553920740U,	// FCVTHDr
+    553920740U,	// FCVTHSr
+    1074533828U,	// FCVTLv2i32
+    2148799940U,	// FCVTLv4i16
+    2685145352U,	// FCVTLv4i32
+    3222540552U,	// FCVTLv8i16
+    553920615U,	// FCVTMSUWDr
+    553920615U,	// FCVTMSUWSr
+    553920615U,	// FCVTMSUXDr
+    553920615U,	// FCVTMSUXSr
+    553920615U,	// FCVTMSv1i32
+    553920615U,	// FCVTMSv1i64
+    1074272359U,	// FCVTMSv2f32
+    1611405415U,	// FCVTMSv2f64
+    2685671527U,	// FCVTMSv4f32
+    553920767U,	// FCVTMUUWDr
+    553920767U,	// FCVTMUUWSr
+    553920767U,	// FCVTMUUXDr
+    553920767U,	// FCVTMUUXSr
+    553920767U,	// FCVTMUv1i32
+    553920767U,	// FCVTMUv1i64
+    1074272511U,	// FCVTMUv2f32
+    1611405567U,	// FCVTMUv2f64
+    2685671679U,	// FCVTMUv4f32
+    553920628U,	// FCVTNSUWDr
+    553920628U,	// FCVTNSUWSr
+    553920628U,	// FCVTNSUXDr
+    553920628U,	// FCVTNSUXSr
+    553920628U,	// FCVTNSv1i32
+    553920628U,	// FCVTNSv1i64
+    1074272372U,	// FCVTNSv2f32
+    1611405428U,	// FCVTNSv2f64
+    2685671540U,	// FCVTNSv4f32
+    553920775U,	// FCVTNUUWDr
+    553920775U,	// FCVTNUUWSr
+    553920775U,	// FCVTNUUXDr
+    553920775U,	// FCVTNUUXSr
+    553920775U,	// FCVTNUv1i32
+    553920775U,	// FCVTNUv1i64
+    1074272519U,	// FCVTNUv2f32
+    1611405575U,	// FCVTNUv2f64
+    2685671687U,	// FCVTNUv4f32
+    1611142770U,	// FCVTNv2i32
+    2685408882U,	// FCVTNv4i16
+    1645490510U,	// FCVTNv4i32
+    2719494478U,	// FCVTNv8i16
+    553920644U,	// FCVTPSUWDr
+    553920644U,	// FCVTPSUWSr
+    553920644U,	// FCVTPSUXDr
+    553920644U,	// FCVTPSUXSr
+    553920644U,	// FCVTPSv1i32
+    553920644U,	// FCVTPSv1i64
+    1074272388U,	// FCVTPSv2f32
+    1611405444U,	// FCVTPSv2f64
+    2685671556U,	// FCVTPSv4f32
+    553920783U,	// FCVTPUUWDr
+    553920783U,	// FCVTPUUWSr
+    553920783U,	// FCVTPUUXDr
+    553920783U,	// FCVTPUUXSr
+    553920783U,	// FCVTPUv1i32
+    553920783U,	// FCVTPUv1i64
+    1074272527U,	// FCVTPUv2f32
+    1611405583U,	// FCVTPUv2f64
+    2685671695U,	// FCVTPUv4f32
+    553920740U,	// FCVTSDr
+    553920740U,	// FCVTSHr
+    553920168U,	// FCVTXNv1i64
+    1611142824U,	// FCVTXNv2f32
+    1645490564U,	// FCVTXNv4f32
+    17049759U,	// FCVTZSSWDri
+    17049759U,	// FCVTZSSWSri
+    17049759U,	// FCVTZSSXDri
+    17049759U,	// FCVTZSSXSri
+    553920671U,	// FCVTZSUWDr
+    553920671U,	// FCVTZSUWSr
+    553920671U,	// FCVTZSUXDr
+    553920671U,	// FCVTZSUXSr
+    17049759U,	// FCVTZS_IntSWDri
+    17049759U,	// FCVTZS_IntSWSri
+    17049759U,	// FCVTZS_IntSXDri
+    17049759U,	// FCVTZS_IntSXSri
+    553920671U,	// FCVTZS_IntUWDr
+    553920671U,	// FCVTZS_IntUWSr
+    553920671U,	// FCVTZS_IntUXDr
+    553920671U,	// FCVTZS_IntUXSr
+    1074272415U,	// FCVTZS_Intv2f32
+    1611405471U,	// FCVTZS_Intv2f64
+    2685671583U,	// FCVTZS_Intv4f32
+    17049759U,	// FCVTZSd
+    17049759U,	// FCVTZSs
+    553920671U,	// FCVTZSv1i32
+    553920671U,	// FCVTZSv1i64
+    1074272415U,	// FCVTZSv2f32
+    1611405471U,	// FCVTZSv2f64
+    2684885151U,	// FCVTZSv2i32_shift
+    537663647U,	// FCVTZSv2i64_shift
+    2685671583U,	// FCVTZSv4f32
+    1075058847U,	// FCVTZSv4i32_shift
+    17049879U,	// FCVTZUSWDri
+    17049879U,	// FCVTZUSWSri
+    17049879U,	// FCVTZUSXDri
+    17049879U,	// FCVTZUSXSri
+    553920791U,	// FCVTZUUWDr
+    553920791U,	// FCVTZUUWSr
+    553920791U,	// FCVTZUUXDr
+    553920791U,	// FCVTZUUXSr
+    17049879U,	// FCVTZU_IntSWDri
+    17049879U,	// FCVTZU_IntSWSri
+    17049879U,	// FCVTZU_IntSXDri
+    17049879U,	// FCVTZU_IntSXSri
+    553920791U,	// FCVTZU_IntUWDr
+    553920791U,	// FCVTZU_IntUWSr
+    553920791U,	// FCVTZU_IntUXDr
+    553920791U,	// FCVTZU_IntUXSr
+    1074272535U,	// FCVTZU_Intv2f32
+    1611405591U,	// FCVTZU_Intv2f64
+    2685671703U,	// FCVTZU_Intv4f32
+    17049879U,	// FCVTZUd
+    17049879U,	// FCVTZUs
+    553920791U,	// FCVTZUv1i32
+    553920791U,	// FCVTZUv1i64
+    1074272535U,	// FCVTZUv2f32
+    1611405591U,	// FCVTZUv2f64
+    2684885271U,	// FCVTZUv2i32_shift
+    537663767U,	// FCVTZUv2i64_shift
+    2685671703U,	// FCVTZUv4f32
+    1075058967U,	// FCVTZUv4i32_shift
+    17049898U,	// FDIVDrr
+    17049898U,	// FDIVSrr
+    2684885290U,	// FDIVv2f32
+    537663786U,	// FDIVv2f64
+    1075058986U,	// FDIVv4f32
+    17048394U,	// FMADDDrrr
+    17048394U,	// FMADDSrrr
+    17050100U,	// FMAXDrr
+    17049087U,	// FMAXNMDrr
+    2684884729U,	// FMAXNMPv2f32
+    537663225U,	// FMAXNMPv2f64
+    1074013945U,	// FMAXNMPv2i32p
+    1610884857U,	// FMAXNMPv2i64p
+    1075058425U,	// FMAXNMPv4f32
+    17049087U,	// FMAXNMSrr
+    2684627285U,	// FMAXNMVv4i32v
+    2684884479U,	// FMAXNMv2f32
+    537662975U,	// FMAXNMv2f64
+    1075058175U,	// FMAXNMv4f32
+    2684884802U,	// FMAXPv2f32
+    537663298U,	// FMAXPv2f64
+    1074014018U,	// FMAXPv2i32p
+    1610884930U,	// FMAXPv2i64p
+    1075058498U,	// FMAXPv4f32
+    17050100U,	// FMAXSrr
+    2684627340U,	// FMAXVv4i32v
+    2684885492U,	// FMAXv2f32
+    537663988U,	// FMAXv2f64
+    1075059188U,	// FMAXv4f32
+    17049126U,	// FMINDrr
+    17049079U,	// FMINNMDrr
+    2684884720U,	// FMINNMPv2f32
+    537663216U,	// FMINNMPv2f64
+    1074013936U,	// FMINNMPv2i32p
+    1610884848U,	// FMINNMPv2i64p
+    1075058416U,	// FMINNMPv4f32
+    17049079U,	// FMINNMSrr
+    2684627276U,	// FMINNMVv4i32v
+    2684884471U,	// FMINNMv2f32
+    537662967U,	// FMINNMv2f64
+    1075058167U,	// FMINNMv4f32
+    2684884744U,	// FMINPv2f32
+    537663240U,	// FMINPv2f64
+    1074013960U,	// FMINPv2i32p
+    1610884872U,	// FMINPv2i64p
+    1075058440U,	// FMINPv4f32
+    17049126U,	// FMINSrr
+    2684627294U,	// FMINVv4i32v
+    2684884518U,	// FMINv2f32
+    537663014U,	// FMINv2f64
+    1075058214U,	// FMINv4f32
+    67404282U,	// FMLAv1i32_indexed
+    67404282U,	// FMLAv1i64_indexed
+    2718446074U,	// FMLAv2f32
+    571224570U,	// FMLAv2f64
+    2718446074U,	// FMLAv2i32_indexed
+    571224570U,	// FMLAv2i64_indexed
+    1108619770U,	// FMLAv4f32
+    1108619770U,	// FMLAv4i32_indexed
+    67405921U,	// FMLSv1i32_indexed
+    67405921U,	// FMLSv1i64_indexed
+    2718447713U,	// FMLSv2f32
+    571226209U,	// FMLSv2f64
+    2718447713U,	// FMLSv2i32_indexed
+    571226209U,	// FMLSv2i64_indexed
+    1108621409U,	// FMLSv4f32
+    1108621409U,	// FMLSv4i32_indexed
+    1074014586U,	// FMOVDXHighr
+    553920890U,	// FMOVDXr
+    117713274U,	// FMOVDi
+    553920890U,	// FMOVDr
+    553920890U,	// FMOVSWr
+    117713274U,	// FMOVSi
+    553920890U,	// FMOVSr
+    553920890U,	// FMOVWSr
+    556276090U,	// FMOVXDHighr
+    553920890U,	// FMOVXDr
+    117971322U,	// FMOVv2f32_ns
+    118233466U,	// FMOVv2f64_ns
+    118757754U,	// FMOVv4f32_ns
+    17048257U,	// FMSUBDrrr
+    17048257U,	// FMSUBSrrr
+    17049035U,	// FMULDrr
+    17049035U,	// FMULSrr
+    17050139U,	// FMULX32
+    17050139U,	// FMULX64
+    17050139U,	// FMULXv1i32_indexed
+    17050139U,	// FMULXv1i64_indexed
+    2684885531U,	// FMULXv2f32
+    537664027U,	// FMULXv2f64
+    2684885531U,	// FMULXv2i32_indexed
+    537664027U,	// FMULXv2i64_indexed
+    1075059227U,	// FMULXv4f32
+    1075059227U,	// FMULXv4i32_indexed
+    17049035U,	// FMULv1i32_indexed
+    17049035U,	// FMULv1i64_indexed
+    2684884427U,	// FMULv2f32
+    537662923U,	// FMULv2f64
+    2684884427U,	// FMULv2i32_indexed
+    537662923U,	// FMULv2i64_indexed
+    1075058123U,	// FMULv4f32
+    1075058123U,	// FMULv4i32_indexed
+    553919443U,	// FNEGDr
+    553919443U,	// FNEGSr
+    1074271187U,	// FNEGv2f32
+    1611404243U,	// FNEGv2f64
+    2685670355U,	// FNEGv4f32
+    17048401U,	// FNMADDDrrr
+    17048401U,	// FNMADDSrrr
+    17048264U,	// FNMSUBDrrr
+    17048264U,	// FNMSUBSrrr
+    17049041U,	// FNMULDrr
+    17049041U,	// FNMULSrr
+    553919369U,	// FRECPEv1i32
+    553919369U,	// FRECPEv1i64
+    1074271113U,	// FRECPEv2f32
+    1611404169U,	// FRECPEv2f64
+    2685670281U,	// FRECPEv4f32
+    17049724U,	// FRECPS32
+    17049724U,	// FRECPS64
+    2684885116U,	// FRECPSv2f32
+    537663612U,	// FRECPSv2f64
+    1075058812U,	// FRECPSv4f32
+    553921058U,	// FRECPXv1i32
+    553921058U,	// FRECPXv1i64
+    553919002U,	// FRINTADr
+    553919002U,	// FRINTASr
+    1074270746U,	// FRINTAv2f32
+    1611403802U,	// FRINTAv2f64
+    2685669914U,	// FRINTAv4f32
+    553919658U,	// FRINTIDr
+    553919658U,	// FRINTISr
+    1074271402U,	// FRINTIv2f32
+    1611404458U,	// FRINTIv2f64
+    2685670570U,	// FRINTIv4f32
+    553920007U,	// FRINTMDr
+    553920007U,	// FRINTMSr
+    1074271751U,	// FRINTMv2f32
+    1611404807U,	// FRINTMv2f64
+    2685670919U,	// FRINTMv4f32
+    553920106U,	// FRINTNDr
+    553920106U,	// FRINTNSr
+    1074271850U,	// FRINTNv2f32
+    1611404906U,	// FRINTNv2f64
+    2685671018U,	// FRINTNv4f32
+    553920297U,	// FRINTPDr
+    553920297U,	// FRINTPSr
+    1074272041U,	// FRINTPv2f32
+    1611405097U,	// FRINTPv2f64
+    2685671209U,	// FRINTPv4f32
+    553921066U,	// FRINTXDr
+    553921066U,	// FRINTXSr
+    1074272810U,	// FRINTXv2f32
+    1611405866U,	// FRINTXv2f64
+    2685671978U,	// FRINTXv4f32
+    553921101U,	// FRINTZDr
+    553921101U,	// FRINTZSr
+    1074272845U,	// FRINTZv2f32
+    1611405901U,	// FRINTZv2f64
+    2685672013U,	// FRINTZv4f32
+    553919406U,	// FRSQRTEv1i32
+    553919406U,	// FRSQRTEv1i64
+    1074271150U,	// FRSQRTEv2f32
+    1611404206U,	// FRSQRTEv2f64
+    2685670318U,	// FRSQRTEv4f32
+    17049745U,	// FRSQRTS32
+    17049745U,	// FRSQRTS64
+    2684885137U,	// FRSQRTSv2f32
+    537663633U,	// FRSQRTSv2f64
+    1075058833U,	// FRSQRTSv4f32
+    553920726U,	// FSQRTDr
+    553920726U,	// FSQRTSr
+    1074272470U,	// FSQRTv2f32
+    1611405526U,	// FSQRTv2f64
+    2685671638U,	// FSQRTv4f32
+    17048237U,	// FSUBDrr
+    17048237U,	// FSUBSrr
+    2684883629U,	// FSUBv2f32
+    537662125U,	// FSUBv2f64
+    1075057325U,	// FSUBv4f32
+    23145U,	// HINT
+    22720U,	// HLT
+    21258U,	// HVC
+    137115759U,	// INSvi16gpr
+    153892975U,	// INSvi16lane
+    137377903U,	// INSvi32gpr
+    691026031U,	// INSvi32lane
+    136853615U,	// INSvi64gpr
+    1227372655U,	// INSvi64lane
+    137640047U,	// INSvi8gpr
+    1765029999U,	// INSvi8lane
+    29329U,	// ISB
+    36885U,	// LD1Fourv16b
+    3710997U,	// LD1Fourv16b_POST
+    45077U,	// LD1Fourv1d
+    3981333U,	// LD1Fourv1d_POST
+    53269U,	// LD1Fourv2d
+    3727381U,	// LD1Fourv2d_POST
+    61461U,	// LD1Fourv2s
+    3997717U,	// LD1Fourv2s_POST
+    69653U,	// LD1Fourv4h
+    4005909U,	// LD1Fourv4h_POST
+    77845U,	// LD1Fourv4s
+    3751957U,	// LD1Fourv4s_POST
+    86037U,	// LD1Fourv8b
+    4022293U,	// LD1Fourv8b_POST
+    94229U,	// LD1Fourv8h
+    3768341U,	// LD1Fourv8h_POST
+    36885U,	// LD1Onev16b
+    4235285U,	// LD1Onev16b_POST
+    45077U,	// LD1Onev1d
+    4505621U,	// LD1Onev1d_POST
+    53269U,	// LD1Onev2d
+    4251669U,	// LD1Onev2d_POST
+    61461U,	// LD1Onev2s
+    4522005U,	// LD1Onev2s_POST
+    69653U,	// LD1Onev4h
+    4530197U,	// LD1Onev4h_POST
+    77845U,	// LD1Onev4s
+    4276245U,	// LD1Onev4s_POST
+    86037U,	// LD1Onev8b
+    4546581U,	// LD1Onev8b_POST
+    94229U,	// LD1Onev8h
+    4292629U,	// LD1Onev8h_POST
+    38769U,	// LD1Rv16b
+    4761457U,	// LD1Rv16b_POST
+    46961U,	// LD1Rv1d
+    4507505U,	// LD1Rv1d_POST
+    55153U,	// LD1Rv2d
+    4515697U,	// LD1Rv2d_POST
+    63345U,	// LD1Rv2s
+    5048177U,	// LD1Rv2s_POST
+    71537U,	// LD1Rv4h
+    5318513U,	// LD1Rv4h_POST
+    79729U,	// LD1Rv4s
+    5064561U,	// LD1Rv4s_POST
+    87921U,	// LD1Rv8b
+    4810609U,	// LD1Rv8b_POST
+    96113U,	// LD1Rv8h
+    5343089U,	// LD1Rv8h_POST
+    36885U,	// LD1Threev16b
+    5546005U,	// LD1Threev16b_POST
+    45077U,	// LD1Threev1d
+    5816341U,	// LD1Threev1d_POST
+    53269U,	// LD1Threev2d
+    5562389U,	// LD1Threev2d_POST
+    61461U,	// LD1Threev2s
+    5832725U,	// LD1Threev2s_POST
+    69653U,	// LD1Threev4h
+    5840917U,	// LD1Threev4h_POST
+    77845U,	// LD1Threev4s
+    5586965U,	// LD1Threev4s_POST
+    86037U,	// LD1Threev8b
+    5857301U,	// LD1Threev8b_POST
+    94229U,	// LD1Threev8h
+    5603349U,	// LD1Threev8h_POST
+    36885U,	// LD1Twov16b
+    3973141U,	// LD1Twov16b_POST
+    45077U,	// LD1Twov1d
+    4243477U,	// LD1Twov1d_POST
+    53269U,	// LD1Twov2d
+    3989525U,	// LD1Twov2d_POST
+    61461U,	// LD1Twov2s
+    4259861U,	// LD1Twov2s_POST
+    69653U,	// LD1Twov4h
+    4268053U,	// LD1Twov4h_POST
+    77845U,	// LD1Twov4s
+    4014101U,	// LD1Twov4s_POST
+    86037U,	// LD1Twov8b
+    4284437U,	// LD1Twov8b_POST
+    94229U,	// LD1Twov8h
+    4030485U,	// LD1Twov8h_POST
+    6131733U,	// LD1i16
+    6397973U,	// LD1i16_POST
+    6139925U,	// LD1i32
+    6668309U,	// LD1i32_POST
+    6148117U,	// LD1i64
+    6938645U,	// LD1i64_POST
+    6156309U,	// LD1i8
+    7208981U,	// LD1i8_POST
+    38775U,	// LD2Rv16b
+    5285751U,	// LD2Rv16b_POST
+    46967U,	// LD2Rv1d
+    4245367U,	// LD2Rv1d_POST
+    55159U,	// LD2Rv2d
+    4253559U,	// LD2Rv2d_POST
+    63351U,	// LD2Rv2s
+    4523895U,	// LD2Rv2s_POST
+    71543U,	// LD2Rv4h
+    5056375U,	// LD2Rv4h_POST
+    79735U,	// LD2Rv4s
+    4540279U,	// LD2Rv4s_POST
+    87927U,	// LD2Rv8b
+    5334903U,	// LD2Rv8b_POST
+    96119U,	// LD2Rv8h
+    5080951U,	// LD2Rv8h_POST
+    36947U,	// LD2Twov16b
+    3973203U,	// LD2Twov16b_POST
+    53331U,	// LD2Twov2d
+    3989587U,	// LD2Twov2d_POST
+    61523U,	// LD2Twov2s
+    4259923U,	// LD2Twov2s_POST
+    69715U,	// LD2Twov4h
+    4268115U,	// LD2Twov4h_POST
+    77907U,	// LD2Twov4s
+    4014163U,	// LD2Twov4s_POST
+    86099U,	// LD2Twov8b
+    4284499U,	// LD2Twov8b_POST
+    94291U,	// LD2Twov8h
+    4030547U,	// LD2Twov8h_POST
+    6131795U,	// LD2i16
+    6660179U,	// LD2i16_POST
+    6139987U,	// LD2i32
+    6930515U,	// LD2i32_POST
+    6148179U,	// LD2i64
+    7462995U,	// LD2i64_POST
+    6156371U,	// LD2i8
+    6422611U,	// LD2i8_POST
+    38781U,	// LD3Rv16b
+    7645053U,	// LD3Rv16b_POST
+    46973U,	// LD3Rv1d
+    5818237U,	// LD3Rv1d_POST
+    55165U,	// LD3Rv2d
+    5826429U,	// LD3Rv2d_POST
+    63357U,	// LD3Rv2s
+    7931773U,	// LD3Rv2s_POST
+    71549U,	// LD3Rv4h
+    8202109U,	// LD3Rv4h_POST
+    79741U,	// LD3Rv4s
+    7948157U,	// LD3Rv4s_POST
+    87933U,	// LD3Rv8b
+    7694205U,	// LD3Rv8b_POST
+    96125U,	// LD3Rv8h
+    8226685U,	// LD3Rv8h_POST
+    37317U,	// LD3Threev16b
+    5546437U,	// LD3Threev16b_POST
+    53701U,	// LD3Threev2d
+    5562821U,	// LD3Threev2d_POST
+    61893U,	// LD3Threev2s
+    5833157U,	// LD3Threev2s_POST
+    70085U,	// LD3Threev4h
+    5841349U,	// LD3Threev4h_POST
+    78277U,	// LD3Threev4s
+    5587397U,	// LD3Threev4s_POST
+    86469U,	// LD3Threev8b
+    5857733U,	// LD3Threev8b_POST
+    94661U,	// LD3Threev8h
+    5603781U,	// LD3Threev8h_POST
+    6132165U,	// LD3i16
+    8495557U,	// LD3i16_POST
+    6140357U,	// LD3i32
+    8765893U,	// LD3i32_POST
+    6148549U,	// LD3i64
+    9036229U,	// LD3i64_POST
+    6156741U,	// LD3i8
+    9306565U,	// LD3i8_POST
+    37341U,	// LD4Fourv16b
+    3711453U,	// LD4Fourv16b_POST
+    53725U,	// LD4Fourv2d
+    3727837U,	// LD4Fourv2d_POST
+    61917U,	// LD4Fourv2s
+    3998173U,	// LD4Fourv2s_POST
+    70109U,	// LD4Fourv4h
+    4006365U,	// LD4Fourv4h_POST
+    78301U,	// LD4Fourv4s
+    3752413U,	// LD4Fourv4s_POST
+    86493U,	// LD4Fourv8b
+    4022749U,	// LD4Fourv8b_POST
+    94685U,	// LD4Fourv8h
+    3768797U,	// LD4Fourv8h_POST
+    38787U,	// LD4Rv16b
+    5023619U,	// LD4Rv16b_POST
+    46979U,	// LD4Rv1d
+    3983235U,	// LD4Rv1d_POST
+    55171U,	// LD4Rv2d
+    3991427U,	// LD4Rv2d_POST
+    63363U,	// LD4Rv2s
+    4261763U,	// LD4Rv2s_POST
+    71555U,	// LD4Rv4h
+    4532099U,	// LD4Rv4h_POST
+    79747U,	// LD4Rv4s
+    4278147U,	// LD4Rv4s_POST
+    87939U,	// LD4Rv8b
+    5072771U,	// LD4Rv8b_POST
+    96131U,	// LD4Rv8h
+    4556675U,	// LD4Rv8h_POST
+    6132189U,	// LD4i16
+    6922717U,	// LD4i16_POST
+    6140381U,	// LD4i32
+    7455197U,	// LD4i32_POST
+    6148573U,	// LD4i64
+    9560541U,	// LD4i64_POST
+    6156765U,	// LD4i8
+    6685149U,	// LD4i8_POST
+    26485304U,	// LDARB
+    26485801U,	// LDARH
+    26486665U,	// LDARW
+    26486665U,	// LDARX
+    553920315U,	// LDAXPW
+    553920315U,	// LDAXPX
+    26485358U,	// LDAXRB
+    26485855U,	// LDAXRH
+    26486787U,	// LDAXRW
+    26486787U,	// LDAXRX
+    553920258U,	// LDNPDi
+    553920258U,	// LDNPQi
+    553920258U,	// LDNPSi
+    553920258U,	// LDNPWi
+    553920258U,	// LDNPXi
+    553920190U,	// LDPDi
+    604276414U,	// LDPDpost
+    604276414U,	// LDPDpre
+    553920190U,	// LDPQi
+    604276414U,	// LDPQpost
+    604276414U,	// LDPQpre
+    553920974U,	// LDPSWi
+    604277198U,	// LDPSWpost
+    604277198U,	// LDPSWpre
+    553920190U,	// LDPSi
+    604276414U,	// LDPSpost
+    604276414U,	// LDPSpre
+    553920190U,	// LDPWi
+    604276414U,	// LDPWpost
+    604276414U,	// LDPWpre
+    553920190U,	// LDPXi
+    604276414U,	// LDPXpost
+    604276414U,	// LDPXpre
+    1150583359U,	// LDRBBpost
+    76841535U,	// LDRBBpre
+    26485311U,	// LDRBBroW
+    26485311U,	// LDRBBroX
+    26485311U,	// LDRBBui
+    1150584728U,	// LDRBpost
+    76842904U,	// LDRBpre
+    26486680U,	// LDRBroW
+    26486680U,	// LDRBroX
+    26486680U,	// LDRBui
+    100935576U,	// LDRDl
+    1150584728U,	// LDRDpost
+    76842904U,	// LDRDpre
+    26486680U,	// LDRDroW
+    26486680U,	// LDRDroX
+    26486680U,	// LDRDui
+    1150583856U,	// LDRHHpost
+    76842032U,	// LDRHHpre
+    26485808U,	// LDRHHroW
+    26485808U,	// LDRHHroX
+    26485808U,	// LDRHHui
+    1150584728U,	// LDRHpost
+    76842904U,	// LDRHpre
+    26486680U,	// LDRHroW
+    26486680U,	// LDRHroX
+    26486680U,	// LDRHui
+    100935576U,	// LDRQl
+    1150584728U,	// LDRQpost
+    76842904U,	// LDRQpre
+    26486680U,	// LDRQroW
+    26486680U,	// LDRQroX
+    26486680U,	// LDRQui
+    1150583446U,	// LDRSBWpost
+    76841622U,	// LDRSBWpre
+    26485398U,	// LDRSBWroW
+    26485398U,	// LDRSBWroX
+    26485398U,	// LDRSBWui
+    1150583446U,	// LDRSBXpost
+    76841622U,	// LDRSBXpre
+    26485398U,	// LDRSBXroW
+    26485398U,	// LDRSBXroX
+    26485398U,	// LDRSBXui
+    1150583933U,	// LDRSHWpost
+    76842109U,	// LDRSHWpre
+    26485885U,	// LDRSHWroW
+    26485885U,	// LDRSHWroX
+    26485885U,	// LDRSHWui
+    1150583933U,	// LDRSHXpost
+    76842109U,	// LDRSHXpre
+    26485885U,	// LDRSHXroW
+    26485885U,	// LDRSHXroX
+    26485885U,	// LDRSHXui
+    100936149U,	// LDRSWl
+    1150585301U,	// LDRSWpost
+    76843477U,	// LDRSWpre
+    26487253U,	// LDRSWroW
+    26487253U,	// LDRSWroX
+    26487253U,	// LDRSWui
+    100935576U,	// LDRSl
+    1150584728U,	// LDRSpost
+    76842904U,	// LDRSpre
+    26486680U,	// LDRSroW
+    26486680U,	// LDRSroX
+    26486680U,	// LDRSui
+    100935576U,	// LDRWl
+    1150584728U,	// LDRWpost
+    76842904U,	// LDRWpre
+    26486680U,	// LDRWroW
+    26486680U,	// LDRWroX
+    26486680U,	// LDRWui
+    100935576U,	// LDRXl
+    1150584728U,	// LDRXpost
+    76842904U,	// LDRXpre
+    26486680U,	// LDRXroW
+    26486680U,	// LDRXroX
+    26486680U,	// LDRXui
+    26485324U,	// LDTRBi
+    26485821U,	// LDTRHi
+    26485405U,	// LDTRSBWi
+    26485405U,	// LDTRSBXi
+    26485892U,	// LDTRSHWi
+    26485892U,	// LDTRSHXi
+    26487260U,	// LDTRSWi
+    26486752U,	// LDTRWi
+    26486752U,	// LDTRXi
+    26485344U,	// LDURBBi
+    26486775U,	// LDURBi
+    26486775U,	// LDURDi
+    26485841U,	// LDURHHi
+    26486775U,	// LDURHi
+    26486775U,	// LDURQi
+    26485413U,	// LDURSBWi
+    26485413U,	// LDURSBXi
+    26485900U,	// LDURSHWi
+    26485900U,	// LDURSHXi
+    26487268U,	// LDURSWi
+    26486775U,	// LDURSi
+    26486775U,	// LDURWi
+    26486775U,	// LDURXi
+    553920343U,	// LDXPW
+    553920343U,	// LDXPX
+    26485366U,	// LDXRB
+    26485863U,	// LDXRH
+    26486794U,	// LDXRW
+    26486794U,	// LDXRX
+    0U,	// LOADgot
+    17049003U,	// LSLVWr
+    17049003U,	// LSLVXr
+    17049558U,	// LSRVWr
+    17049558U,	// LSRVXr
+    17048395U,	// MADDWrrr
+    17048395U,	// MADDXrrr
+    2181050875U,	// MLAv16i8
+    2718446075U,	// MLAv2i32
+    2718446075U,	// MLAv2i32_indexed
+    3255841275U,	// MLAv4i16
+    3255841275U,	// MLAv4i16_indexed
+    1108619771U,	// MLAv4i32
+    1108619771U,	// MLAv4i32_indexed
+    1645752827U,	// MLAv8i16
+    1645752827U,	// MLAv8i16_indexed
+    3793498619U,	// MLAv8i8
+    2181052514U,	// MLSv16i8
+    2718447714U,	// MLSv2i32
+    2718447714U,	// MLSv2i32_indexed
+    3255842914U,	// MLSv4i16
+    3255842914U,	// MLSv4i16_indexed
+    1108621410U,	// MLSv4i32
+    1108621410U,	// MLSv4i32_indexed
+    1645754466U,	// MLSv8i16
+    1645754466U,	// MLSv8i16_indexed
+    3793500258U,	// MLSv8i8
+    168043698U,	// MOVID
+    721425586U,	// MOVIv16b_ns
+    168563890U,	// MOVIv2d_ns
+    1795691698U,	// MOVIv2i32
+    1795691698U,	// MOVIv2s_msl
+    1796215986U,	// MOVIv4i16
+    1796478130U,	// MOVIv4i32
+    1796478130U,	// MOVIv4s_msl
+    723260594U,	// MOVIv8b_ns
+    1796740274U,	// MOVIv8i16
+    84157629U,	// MOVKWi
+    84157629U,	// MOVKXi
+    1795434146U,	// MOVNWi
+    1795434146U,	// MOVNXi
+    1795435093U,	// MOVZWi
+    1795435093U,	// MOVZXi
+    0U,	// MOVaddr
+    0U,	// MOVaddrBA
+    0U,	// MOVaddrCP
+    0U,	// MOVaddrEXT
+    0U,	// MOVaddrJT
+    0U,	// MOVaddrTLS
+    0U,	// MOVi32imm
+    0U,	// MOVi64imm
+    201599116U,	// MRS
+    137179U,	// MSR
+    141275U,	// MSRpstate
+    17048258U,	// MSUBWrrr
+    17048258U,	// MSUBXrrr
+    2147489228U,	// MULv16i8
+    2684884428U,	// MULv2i32
+    2684884428U,	// MULv2i32_indexed
+    3222279628U,	// MULv4i16
+    3222279628U,	// MULv4i16_indexed
+    1075058124U,	// MULv4i32
+    1075058124U,	// MULv4i32_indexed
+    1612191180U,	// MULv8i16
+    1612191180U,	// MULv8i16_indexed
+    3759936972U,	// MULv8i8
+    1795691679U,	// MVNIv2i32
+    1795691679U,	// MVNIv2s_msl
+    1796215967U,	// MVNIv4i16
+    1796478111U,	// MVNIv4i32
+    1796478111U,	// MVNIv4s_msl
+    1796740255U,	// MVNIv8i16
+    5076U,	// NEGv16i8
+    553919444U,	// NEGv1i64
+    1074271188U,	// NEGv2i32
+    1611404244U,	// NEGv2i64
+    2148537300U,	// NEGv4i16
+    2685670356U,	// NEGv4i32
+    3222803412U,	// NEGv8i16
+    3759936468U,	// NEGv8i8
+    6353U,	// NOTv16i8
+    3759937745U,	// NOTv8i8
+    0U,	// ORNWrr
+    17049189U,	// ORNWrs
+    0U,	// ORNXrr
+    17049189U,	// ORNXrs
+    2147489381U,	// ORNv16i8
+    3759937125U,	// ORNv8i8
+    17049548U,	// ORRWri
+    0U,	// ORRWrr
+    17049548U,	// ORRWrs
+    17049548U,	// ORRXri
+    0U,	// ORRXrr
+    17049548U,	// ORRXrs
+    2147489740U,	// ORRv16i8
+    84424652U,	// ORRv2i32
+    84948940U,	// ORRv4i16
+    85211084U,	// ORRv4i32
+    85473228U,	// ORRv8i16
+    3759937484U,	// ORRv8i8
+    2149060822U,	// PMULLv16i8
+    228070797U,	// PMULLv1i64
+    244846806U,	// PMULLv2i64
+    3759674765U,	// PMULLv8i8
+    2147489240U,	// PMULv16i8
+    3759936984U,	// PMULv8i8
+    101070321U,	// PRFMl
+    26621425U,	// PRFMroW
+    26621425U,	// PRFMroX
+    26621425U,	// PRFMui
+    26621455U,	// PRFUMi
+    537400862U,	// RADDHNv2i64_v2i32
+    571748633U,	// RADDHNv2i64_v4i32
+    1074796062U,	// RADDHNv4i32_v4i16
+    1108881689U,	// RADDHNv4i32_v8i16
+    1644179737U,	// RADDHNv8i16_v16i8
+    1612453406U,	// RADDHNv8i16_v8i8
+    553920698U,	// RBITWr
+    553920698U,	// RBITXr
+    6330U,	// RBITv16i8
+    3759937722U,	// RBITv8i8
+    2107559U,	// RET
+    0U,	// RET_ReallyLR
+    553918951U,	// REV16Wr
+    553918951U,	// REV16Xr
+    4583U,	// REV16v16i8
+    3759935975U,	// REV16v8i8
+    553918540U,	// REV32Xr
+    4172U,	// REV32v16i8
+    2148536396U,	// REV32v4i16
+    3222802508U,	// REV32v8i16
+    3759935564U,	// REV32v8i8
+    4566U,	// REV64v16i8
+    1074270678U,	// REV64v2i32
+    2148536790U,	// REV64v4i16
+    2685669846U,	// REV64v4i32
+    3222802902U,	// REV64v8i16
+    3759935958U,	// REV64v8i8
+    553920805U,	// REVWr
+    553920805U,	// REVXr
+    17049543U,	// RORVWr
+    17049543U,	// RORVXr
+    1644179766U,	// RSHRNv16i8_shift
+    537400917U,	// RSHRNv2i32_shift
+    1074796117U,	// RSHRNv4i16_shift
+    571748662U,	// RSHRNv4i32_shift
+    1108881718U,	// RSHRNv8i16_shift
+    1612453461U,	// RSHRNv8i8_shift
+    537400854U,	// RSUBHNv2i64_v2i32
+    571748624U,	// RSUBHNv2i64_v4i32
+    1074796054U,	// RSUBHNv4i32_v4i16
+    1108881680U,	// RSUBHNv4i32_v8i16
+    1644179728U,	// RSUBHNv8i16_v16i8
+    1612453398U,	// RSUBHNv8i16_v8i8
+    2182623330U,	// SABALv16i8_v8i16
+    2718708931U,	// SABALv2i32_v2i64
+    3256104131U,	// SABALv4i16_v4i32
+    1108095074U,	// SABALv4i32_v2i64
+    1645490274U,	// SABALv8i16_v4i32
+    3793237187U,	// SABALv8i8_v8i16
+    2181050862U,	// SABAv16i8
+    2718446062U,	// SABAv2i32
+    3255841262U,	// SABAv4i16
+    1108619758U,	// SABAv4i32
+    1645752814U,	// SABAv8i16
+    3793498606U,	// SABAv8i8
+    2149060764U,	// SABDLv16i8_v8i16
+    2685146379U,	// SABDLv2i32_v2i64
+    3222541579U,	// SABDLv4i16_v4i32
+    1074532508U,	// SABDLv4i32_v2i64
+    1611927708U,	// SABDLv8i16_v4i32
+    3759674635U,	// SABDLv8i8_v8i16
+    2147488538U,	// SABDv16i8
+    2684883738U,	// SABDv2i32
+    3222278938U,	// SABDv4i16
+    1075057434U,	// SABDv4i32
+    1612190490U,	// SABDv8i16
+    3759936282U,	// SABDv8i8
+    35141315U,	// SADALPv16i8_v8i16
+    1117533891U,	// SADALPv2i32_v1i64
+    2181576387U,	// SADALPv4i16_v2i32
+    2718709443U,	// SADALPv4i32_v2i64
+    3256104643U,	// SADALPv8i16_v4i32
+    3792713411U,	// SADALPv8i8_v4i16
+    1578707U,	// SADDLPv16i8_v8i16
+    1083971283U,	// SADDLPv2i32_v1i64
+    2148013779U,	// SADDLPv4i16_v2i32
+    2685146835U,	// SADDLPv4i32_v2i64
+    3222542035U,	// SADDLPv8i16_v4i32
+    3759150803U,	// SADDLPv8i8_v4i16
+    272700U,	// SADDLVv16i8v
+    2147756348U,	// SADDLVv4i16v
+    2684627260U,	// SADDLVv4i32v
+    3221498172U,	// SADDLVv8i16v
+    3758369084U,	// SADDLVv8i8v
+    2149060780U,	// SADDLv16i8_v8i16
+    2685146409U,	// SADDLv2i32_v2i64
+    3222541609U,	// SADDLv4i16_v4i32
+    1074532524U,	// SADDLv4i32_v2i64
+    1611927724U,	// SADDLv8i16_v4i32
+    3759674665U,	// SADDLv8i8_v8i16
+    1612190133U,	// SADDWv16i8_v8i16
+    537663936U,	// SADDWv2i32_v2i64
+    1075059136U,	// SADDWv4i16_v4i32
+    537661877U,	// SADDWv4i32_v2i64
+    1075057077U,	// SADDWv8i16_v4i32
+    1612192192U,	// SADDWv8i8_v8i16
+    17049656U,	// SBCSWr
+    17049656U,	// SBCSXr
+    17048293U,	// SBCWr
+    17048293U,	// SBCXr
+    17049061U,	// SBFMWri
+    17049061U,	// SBFMXri
+    17048517U,	// SCVTFSWDri
+    17048517U,	// SCVTFSWSri
+    17048517U,	// SCVTFSXDri
+    17048517U,	// SCVTFSXSri
+    553919429U,	// SCVTFUWDri
+    553919429U,	// SCVTFUWSri
+    553919429U,	// SCVTFUXDri
+    553919429U,	// SCVTFUXSri
+    17048517U,	// SCVTFd
+    17048517U,	// SCVTFs
+    553919429U,	// SCVTFv1i32
+    553919429U,	// SCVTFv1i64
+    1074271173U,	// SCVTFv2f32
+    1611404229U,	// SCVTFv2f64
+    2684883909U,	// SCVTFv2i32_shift
+    537662405U,	// SCVTFv2i64_shift
+    2685670341U,	// SCVTFv4f32
+    1075057605U,	// SCVTFv4i32_shift
+    17049904U,	// SDIVWr
+    17049904U,	// SDIVXr
+    17049904U,	// SDIV_IntWr
+    17049904U,	// SDIV_IntXr
+    67404510U,	// SHA1Crrr
+    553919463U,	// SHA1Hrr
+    67405278U,	// SHA1Mrrr
+    67405488U,	// SHA1Prrr
+    1108619265U,	// SHA1SU0rrr
+    2719232056U,	// SHA1SU1rr
+    67403864U,	// SHA256H2rrr
+    67404790U,	// SHA256Hrrr
+    2719232010U,	// SHA256SU0rr
+    1108619329U,	// SHA256SU1rrr
+    2147488572U,	// SHADDv16i8
+    2684883772U,	// SHADDv2i32
+    3222278972U,	// SHADDv4i16
+    1075057468U,	// SHADDv4i32
+    1612190524U,	// SHADDv8i16
+    3759936316U,	// SHADDv8i8
+    2149060797U,	// SHLLv16i8
+    2685146487U,	// SHLLv2i32
+    3222541687U,	// SHLLv4i16
+    3758887101U,	// SHLLv4i32
+    1315005U,	// SHLLv8i16
+    538449271U,	// SHLLv8i8
+    17048896U,	// SHLd
+    2147489088U,	// SHLv16i8_shift
+    2684884288U,	// SHLv2i32_shift
+    537662784U,	// SHLv2i64_shift
+    3222279488U,	// SHLv4i16_shift
+    1075057984U,	// SHLv4i32_shift
+    1612191040U,	// SHLv8i16_shift
+    3759936832U,	// SHLv8i8_shift
+    1644179748U,	// SHRNv16i8_shift
+    537400901U,	// SHRNv2i32_shift
+    1074796101U,	// SHRNv4i16_shift
+    571748644U,	// SHRNv4i32_shift
+    1108881700U,	// SHRNv8i16_shift
+    1612453445U,	// SHRNv8i8_shift
+    2147488435U,	// SHSUBv16i8
+    2684883635U,	// SHSUBv2i32
+    3222278835U,	// SHSUBv4i16
+    1075057331U,	// SHSUBv4i32
+    1612190387U,	// SHSUBv8i16
+    3759936179U,	// SHSUBv8i8
+    67404954U,	// SLId
+    2181051546U,	// SLIv16i8_shift
+    2718446746U,	// SLIv2i32_shift
+    571225242U,	// SLIv2i64_shift
+    3255841946U,	// SLIv4i16_shift
+    1108620442U,	// SLIv4i32_shift
+    1645753498U,	// SLIv8i16_shift
+    3793499290U,	// SLIv8i8_shift
+    17048857U,	// SMADDLrrr
+    2147489609U,	// SMAXPv16i8
+    2684884809U,	// SMAXPv2i32
+    3222280009U,	// SMAXPv4i16
+    1075058505U,	// SMAXPv4i32
+    1612191561U,	// SMAXPv8i16
+    3759937353U,	// SMAXPv8i8
+    272787U,	// SMAXVv16i8v
+    2147756435U,	// SMAXVv4i16v
+    2684627347U,	// SMAXVv4i32v
+    3221498259U,	// SMAXVv8i16v
+    3758369171U,	// SMAXVv8i8v
+    2147490298U,	// SMAXv16i8
+    2684885498U,	// SMAXv2i32
+    3222280698U,	// SMAXv4i16
+    1075059194U,	// SMAXv4i32
+    1612192250U,	// SMAXv8i16
+    3759938042U,	// SMAXv8i8
+    21246U,	// SMC
+    2147489551U,	// SMINPv16i8
+    2684884751U,	// SMINPv2i32
+    3222279951U,	// SMINPv4i16
+    1075058447U,	// SMINPv4i32
+    1612191503U,	// SMINPv8i16
+    3759937295U,	// SMINPv8i8
+    272741U,	// SMINVv16i8v
+    2147756389U,	// SMINVv4i16v
+    2684627301U,	// SMINVv4i32v
+    3221498213U,	// SMINVv8i16v
+    3758369125U,	// SMINVv8i8v
+    2147489324U,	// SMINv16i8
+    2684884524U,	// SMINv2i32
+    3222279724U,	// SMINv4i16
+    1075058220U,	// SMINv4i32
+    1612191276U,	// SMINv8i16
+    3759937068U,	// SMINv8i8
+    2182623356U,	// SMLALv16i8_v8i16
+    2718708954U,	// SMLALv2i32_indexed
+    2718708954U,	// SMLALv2i32_v2i64
+    3256104154U,	// SMLALv4i16_indexed
+    3256104154U,	// SMLALv4i16_v4i32
+    1108095100U,	// SMLALv4i32_indexed
+    1108095100U,	// SMLALv4i32_v2i64
+    1645490300U,	// SMLALv8i16_indexed
+    1645490300U,	// SMLALv8i16_v4i32
+    3793237210U,	// SMLALv8i8_v8i16
+    2182623480U,	// SMLSLv16i8_v8i16
+    2718709168U,	// SMLSLv2i32_indexed
+    2718709168U,	// SMLSLv2i32_v2i64
+    3256104368U,	// SMLSLv4i16_indexed
+    3256104368U,	// SMLSLv4i16_v4i32
+    1108095224U,	// SMLSLv4i32_indexed
+    1108095224U,	// SMLSLv4i32_v2i64
+    1645490424U,	// SMLSLv8i16_indexed
+    1645490424U,	// SMLSLv8i16_v4i32
+    3793237424U,	// SMLSLv8i8_v8i16
+    272768U,	// SMOVvi16to32
+    272768U,	// SMOVvi16to64
+    537143680U,	// SMOVvi32to64
+    1610885504U,	// SMOVvi8to32
+    1610885504U,	// SMOVvi8to64
+    17048813U,	// SMSUBLrrr
+    17048603U,	// SMULHrr
+    2149060830U,	// SMULLv16i8_v8i16
+    2685146516U,	// SMULLv2i32_indexed
+    2685146516U,	// SMULLv2i32_v2i64
+    3222541716U,	// SMULLv4i16_indexed
+    3222541716U,	// SMULLv4i16_v4i32
+    1074532574U,	// SMULLv4i32_indexed
+    1074532574U,	// SMULLv4i32_v2i64
+    1611927774U,	// SMULLv8i16_indexed
+    1611927774U,	// SMULLv8i16_v4i32
+    3759674772U,	// SMULLv8i8_v8i16
+    6187U,	// SQABSv16i8
+    553920555U,	// SQABSv1i16
+    553920555U,	// SQABSv1i32
+    553920555U,	// SQABSv1i64
+    553920555U,	// SQABSv1i8
+    1074272299U,	// SQABSv2i32
+    1611405355U,	// SQABSv2i64
+    2148538411U,	// SQABSv4i16
+    2685671467U,	// SQABSv4i32
+    3222804523U,	// SQABSv8i16
+    3759937579U,	// SQABSv8i8
+    2147488602U,	// SQADDv16i8
+    17048410U,	// SQADDv1i16
+    17048410U,	// SQADDv1i32
+    17048410U,	// SQADDv1i64
+    17048410U,	// SQADDv1i8
+    2684883802U,	// SQADDv2i32
+    537662298U,	// SQADDv2i64
+    3222279002U,	// SQADDv4i16
+    1075057498U,	// SQADDv4i32
+    1612190554U,	// SQADDv8i16
+    3759936346U,	// SQADDv8i8
+    67405009U,	// SQDMLALi16
+    67405009U,	// SQDMLALi32
+    67405009U,	// SQDMLALv1i32_indexed
+    67405009U,	// SQDMLALv1i64_indexed
+    2718708945U,	// SQDMLALv2i32_indexed
+    2718708945U,	// SQDMLALv2i32_v2i64
+    3256104145U,	// SQDMLALv4i16_indexed
+    3256104145U,	// SQDMLALv4i16_v4i32
+    1108095090U,	// SQDMLALv4i32_indexed
+    1108095090U,	// SQDMLALv4i32_v2i64
+    1645490290U,	// SQDMLALv8i16_indexed
+    1645490290U,	// SQDMLALv8i16_v4i32
+    67405223U,	// SQDMLSLi16
+    67405223U,	// SQDMLSLi32
+    67405223U,	// SQDMLSLv1i32_indexed
+    67405223U,	// SQDMLSLv1i64_indexed
+    2718709159U,	// SQDMLSLv2i32_indexed
+    2718709159U,	// SQDMLSLv2i32_v2i64
+    3256104359U,	// SQDMLSLv4i16_indexed
+    3256104359U,	// SQDMLSLv4i16_v4i32
+    1108095214U,	// SQDMLSLv4i32_indexed
+    1108095214U,	// SQDMLSLv4i32_v2i64
+    1645490414U,	// SQDMLSLv8i16_indexed
+    1645490414U,	// SQDMLSLv8i16_v4i32
+    17048584U,	// SQDMULHv1i16
+    17048584U,	// SQDMULHv1i16_indexed
+    17048584U,	// SQDMULHv1i32
+    17048584U,	// SQDMULHv1i32_indexed
+    2684883976U,	// SQDMULHv2i32
+    2684883976U,	// SQDMULHv2i32_indexed
+    3222279176U,	// SQDMULHv4i16
+    3222279176U,	// SQDMULHv4i16_indexed
+    1075057672U,	// SQDMULHv4i32
+    1075057672U,	// SQDMULHv4i32_indexed
+    1612190728U,	// SQDMULHv8i16
+    1612190728U,	// SQDMULHv8i16_indexed
+    17048964U,	// SQDMULLi16
+    17048964U,	// SQDMULLi32
+    17048964U,	// SQDMULLv1i32_indexed
+    17048964U,	// SQDMULLv1i64_indexed
+    2685146500U,	// SQDMULLv2i32_indexed
+    2685146500U,	// SQDMULLv2i32_v2i64
+    3222541700U,	// SQDMULLv4i16_indexed
+    3222541700U,	// SQDMULLv4i16_v4i32
+    1074532556U,	// SQDMULLv4i32_indexed
+    1074532556U,	// SQDMULLv4i32_v2i64
+    1611927756U,	// SQDMULLv8i16_indexed
+    1611927756U,	// SQDMULLv8i16_v4i32
+    5081U,	// SQNEGv16i8
+    553919449U,	// SQNEGv1i16
+    553919449U,	// SQNEGv1i32
+    553919449U,	// SQNEGv1i64
+    553919449U,	// SQNEGv1i8
+    1074271193U,	// SQNEGv2i32
+    1611404249U,	// SQNEGv2i64
+    2148537305U,	// SQNEGv4i16
+    2685670361U,	// SQNEGv4i32
+    3222803417U,	// SQNEGv8i16
+    3759936473U,	// SQNEGv8i8
+    17048593U,	// SQRDMULHv1i16
+    17048593U,	// SQRDMULHv1i16_indexed
+    17048593U,	// SQRDMULHv1i32
+    17048593U,	// SQRDMULHv1i32_indexed
+    2684883985U,	// SQRDMULHv2i32
+    2684883985U,	// SQRDMULHv2i32_indexed
+    3222279185U,	// SQRDMULHv4i16
+    3222279185U,	// SQRDMULHv4i16_indexed
+    1075057681U,	// SQRDMULHv4i32
+    1075057681U,	// SQRDMULHv4i32_indexed
+    1612190737U,	// SQRDMULHv8i16
+    1612190737U,	// SQRDMULHv8i16_indexed
+    2147489100U,	// SQRSHLv16i8
+    17048908U,	// SQRSHLv1i16
+    17048908U,	// SQRSHLv1i32
+    17048908U,	// SQRSHLv1i64
+    17048908U,	// SQRSHLv1i8
+    2684884300U,	// SQRSHLv2i32
+    537662796U,	// SQRSHLv2i64
+    3222279500U,	// SQRSHLv4i16
+    1075057996U,	// SQRSHLv4i32
+    1612191052U,	// SQRSHLv8i16
+    3759936844U,	// SQRSHLv8i8
+    17049171U,	// SQRSHRNb
+    17049171U,	// SQRSHRNh
+    17049171U,	// SQRSHRNs
+    1644179764U,	// SQRSHRNv16i8_shift
+    537400915U,	// SQRSHRNv2i32_shift
+    1074796115U,	// SQRSHRNv4i16_shift
+    571748660U,	// SQRSHRNv4i32_shift
+    1108881716U,	// SQRSHRNv8i16_shift
+    1612453459U,	// SQRSHRNv8i8_shift
+    17049232U,	// SQRSHRUNb
+    17049232U,	// SQRSHRUNh
+    17049232U,	// SQRSHRUNs
+    1644179824U,	// SQRSHRUNv16i8_shift
+    537400976U,	// SQRSHRUNv2i32_shift
+    1074796176U,	// SQRSHRUNv4i16_shift
+    571748720U,	// SQRSHRUNv4i32_shift
+    1108881776U,	// SQRSHRUNv8i16_shift
+    1612453520U,	// SQRSHRUNv8i8_shift
+    17049847U,	// SQSHLUb
+    17049847U,	// SQSHLUd
+    17049847U,	// SQSHLUh
+    17049847U,	// SQSHLUs
+    2147490039U,	// SQSHLUv16i8_shift
+    2684885239U,	// SQSHLUv2i32_shift
+    537663735U,	// SQSHLUv2i64_shift
+    3222280439U,	// SQSHLUv4i16_shift
+    1075058935U,	// SQSHLUv4i32_shift
+    1612191991U,	// SQSHLUv8i16_shift
+    3759937783U,	// SQSHLUv8i8_shift
+    17048894U,	// SQSHLb
+    17048894U,	// SQSHLd
+    17048894U,	// SQSHLh
+    17048894U,	// SQSHLs
+    2147489086U,	// SQSHLv16i8
+    2147489086U,	// SQSHLv16i8_shift
+    17048894U,	// SQSHLv1i16
+    17048894U,	// SQSHLv1i32
+    17048894U,	// SQSHLv1i64
+    17048894U,	// SQSHLv1i8
+    2684884286U,	// SQSHLv2i32
+    2684884286U,	// SQSHLv2i32_shift
+    537662782U,	// SQSHLv2i64
+    537662782U,	// SQSHLv2i64_shift
+    3222279486U,	// SQSHLv4i16
+    3222279486U,	// SQSHLv4i16_shift
+    1075057982U,	// SQSHLv4i32
+    1075057982U,	// SQSHLv4i32_shift
+    1612191038U,	// SQSHLv8i16
+    1612191038U,	// SQSHLv8i16_shift
+    3759936830U,	// SQSHLv8i8
+    3759936830U,	// SQSHLv8i8_shift
+    17049155U,	// SQSHRNb
+    17049155U,	// SQSHRNh
+    17049155U,	// SQSHRNs
+    1644179746U,	// SQSHRNv16i8_shift
+    537400899U,	// SQSHRNv2i32_shift
+    1074796099U,	// SQSHRNv4i16_shift
+    571748642U,	// SQSHRNv4i32_shift
+    1108881698U,	// SQSHRNv8i16_shift
+    1612453443U,	// SQSHRNv8i8_shift
+    17049223U,	// SQSHRUNb
+    17049223U,	// SQSHRUNh
+    17049223U,	// SQSHRUNs
+    1644179814U,	// SQSHRUNv16i8_shift
+    537400967U,	// SQSHRUNv2i32_shift
+    1074796167U,	// SQSHRUNv4i16_shift
+    571748710U,	// SQSHRUNv4i32_shift
+    1108881766U,	// SQSHRUNv8i16_shift
+    1612453511U,	// SQSHRUNv8i8_shift
+    2147488464U,	// SQSUBv16i8
+    17048272U,	// SQSUBv1i16
+    17048272U,	// SQSUBv1i32
+    17048272U,	// SQSUBv1i64
+    17048272U,	// SQSUBv1i8
+    2684883664U,	// SQSUBv2i32
+    537662160U,	// SQSUBv2i64
+    3222278864U,	// SQSUBv4i16
+    1075057360U,	// SQSUBv4i32
+    1612190416U,	// SQSUBv8i16
+    3759936208U,	// SQSUBv8i8
+    3254792534U,	// SQXTNv16i8
+    553920121U,	// SQXTNv1i16
+    553920121U,	// SQXTNv1i32
+    553920121U,	// SQXTNv1i8
+    1611142777U,	// SQXTNv2i32
+    2685408889U,	// SQXTNv4i16
+    1645490518U,	// SQXTNv4i32
+    2719494486U,	// SQXTNv8i16
+    3223066233U,	// SQXTNv8i8
+    3254792571U,	// SQXTUNv16i8
+    553920154U,	// SQXTUNv1i16
+    553920154U,	// SQXTUNv1i32
+    553920154U,	// SQXTUNv1i8
+    1611142810U,	// SQXTUNv2i32
+    2685408922U,	// SQXTUNv4i16
+    1645490555U,	// SQXTUNv4i32
+    2719494523U,	// SQXTUNv8i16
+    3223066266U,	// SQXTUNv8i8
+    2147488556U,	// SRHADDv16i8
+    2684883756U,	// SRHADDv2i32
+    3222278956U,	// SRHADDv4i16
+    1075057452U,	// SRHADDv4i32
+    1612190508U,	// SRHADDv8i16
+    3759936300U,	// SRHADDv8i8
+    67404965U,	// SRId
+    2181051557U,	// SRIv16i8_shift
+    2718446757U,	// SRIv2i32_shift
+    571225253U,	// SRIv2i64_shift
+    3255841957U,	// SRIv4i16_shift
+    1108620453U,	// SRIv4i32_shift
+    1645753509U,	// SRIv8i16_shift
+    3793499301U,	// SRIv8i8_shift
+    2147489116U,	// SRSHLv16i8
+    17048924U,	// SRSHLv1i64
+    2684884316U,	// SRSHLv2i32
+    537662812U,	// SRSHLv2i64
+    3222279516U,	// SRSHLv4i16
+    1075058012U,	// SRSHLv4i32
+    1612191068U,	// SRSHLv8i16
+    3759936860U,	// SRSHLv8i8
+    17049501U,	// SRSHRd
+    2147489693U,	// SRSHRv16i8_shift
+    2684884893U,	// SRSHRv2i32_shift
+    537663389U,	// SRSHRv2i64_shift
+    3222280093U,	// SRSHRv4i16_shift
+    1075058589U,	// SRSHRv4i32_shift
+    1612191645U,	// SRSHRv8i16_shift
+    3759937437U,	// SRSHRv8i8_shift
+    67404288U,	// SRSRAd
+    2181050880U,	// SRSRAv16i8_shift
+    2718446080U,	// SRSRAv2i32_shift
+    571224576U,	// SRSRAv2i64_shift
+    3255841280U,	// SRSRAv4i16_shift
+    1108619776U,	// SRSRAv4i32_shift
+    1645752832U,	// SRSRAv8i16_shift
+    3793498624U,	// SRSRAv8i8_shift
+    2149060796U,	// SSHLLv16i8_shift
+    2685146486U,	// SSHLLv2i32_shift
+    3222541686U,	// SSHLLv4i16_shift
+    1074532540U,	// SSHLLv4i32_shift
+    1611927740U,	// SSHLLv8i16_shift
+    3759674742U,	// SSHLLv8i8_shift
+    2147489130U,	// SSHLv16i8
+    17048938U,	// SSHLv1i64
+    2684884330U,	// SSHLv2i32
+    537662826U,	// SSHLv2i64
+    3222279530U,	// SSHLv4i16
+    1075058026U,	// SSHLv4i32
+    1612191082U,	// SSHLv8i16
+    3759936874U,	// SSHLv8i8
+    17049515U,	// SSHRd
+    2147489707U,	// SSHRv16i8_shift
+    2684884907U,	// SSHRv2i32_shift
+    537663403U,	// SSHRv2i64_shift
+    3222280107U,	// SSHRv4i16_shift
+    1075058603U,	// SSHRv4i32_shift
+    1612191659U,	// SSHRv8i16_shift
+    3759937451U,	// SSHRv8i8_shift
+    67404302U,	// SSRAd
+    2181050894U,	// SSRAv16i8_shift
+    2718446094U,	// SSRAv2i32_shift
+    571224590U,	// SSRAv2i64_shift
+    3255841294U,	// SSRAv4i16_shift
+    1108619790U,	// SSRAv4i32_shift
+    1645752846U,	// SSRAv8i16_shift
+    3793498638U,	// SSRAv8i8_shift
+    2149060748U,	// SSUBLv16i8_v8i16
+    2685146365U,	// SSUBLv2i32_v2i64
+    3222541565U,	// SSUBLv4i16_v4i32
+    1074532492U,	// SSUBLv4i32_v2i64
+    1611927692U,	// SSUBLv8i16_v4i32
+    3759674621U,	// SSUBLv8i8_v8i16
+    1612190117U,	// SSUBWv16i8_v8i16
+    537663913U,	// SSUBWv2i32_v2i64
+    1075059113U,	// SSUBWv4i16_v4i32
+    537661861U,	// SSUBWv4i32_v2i64
+    1075057061U,	// SSUBWv8i16_v4i32
+    1612192169U,	// SSUBWv8i8_v8i16
+    36915U,	// ST1Fourv16b
+    3711027U,	// ST1Fourv16b_POST
+    45107U,	// ST1Fourv1d
+    3981363U,	// ST1Fourv1d_POST
+    53299U,	// ST1Fourv2d
+    3727411U,	// ST1Fourv2d_POST
+    61491U,	// ST1Fourv2s
+    3997747U,	// ST1Fourv2s_POST
+    69683U,	// ST1Fourv4h
+    4005939U,	// ST1Fourv4h_POST
+    77875U,	// ST1Fourv4s
+    3751987U,	// ST1Fourv4s_POST
+    86067U,	// ST1Fourv8b
+    4022323U,	// ST1Fourv8b_POST
+    94259U,	// ST1Fourv8h
+    3768371U,	// ST1Fourv8h_POST
+    36915U,	// ST1Onev16b
+    4235315U,	// ST1Onev16b_POST
+    45107U,	// ST1Onev1d
+    4505651U,	// ST1Onev1d_POST
+    53299U,	// ST1Onev2d
+    4251699U,	// ST1Onev2d_POST
+    61491U,	// ST1Onev2s
+    4522035U,	// ST1Onev2s_POST
+    69683U,	// ST1Onev4h
+    4530227U,	// ST1Onev4h_POST
+    77875U,	// ST1Onev4s
+    4276275U,	// ST1Onev4s_POST
+    86067U,	// ST1Onev8b
+    4546611U,	// ST1Onev8b_POST
+    94259U,	// ST1Onev8h
+    4292659U,	// ST1Onev8h_POST
+    36915U,	// ST1Threev16b
+    5546035U,	// ST1Threev16b_POST
+    45107U,	// ST1Threev1d
+    5816371U,	// ST1Threev1d_POST
+    53299U,	// ST1Threev2d
+    5562419U,	// ST1Threev2d_POST
+    61491U,	// ST1Threev2s
+    5832755U,	// ST1Threev2s_POST
+    69683U,	// ST1Threev4h
+    5840947U,	// ST1Threev4h_POST
+    77875U,	// ST1Threev4s
+    5586995U,	// ST1Threev4s_POST
+    86067U,	// ST1Threev8b
+    5857331U,	// ST1Threev8b_POST
+    94259U,	// ST1Threev8h
+    5603379U,	// ST1Threev8h_POST
+    36915U,	// ST1Twov16b
+    3973171U,	// ST1Twov16b_POST
+    45107U,	// ST1Twov1d
+    4243507U,	// ST1Twov1d_POST
+    53299U,	// ST1Twov2d
+    3989555U,	// ST1Twov2d_POST
+    61491U,	// ST1Twov2s
+    4259891U,	// ST1Twov2s_POST
+    69683U,	// ST1Twov4h
+    4268083U,	// ST1Twov4h_POST
+    77875U,	// ST1Twov4s
+    4014131U,	// ST1Twov4s_POST
+    86067U,	// ST1Twov8b
+    4284467U,	// ST1Twov8b_POST
+    94259U,	// ST1Twov8h
+    4030515U,	// ST1Twov8h_POST
+    147507U,	// ST1i16
+    262246451U,	// ST1i16_POST
+    151603U,	// ST1i32
+    279031859U,	// ST1i32_POST
+    155699U,	// ST1i64
+    295817267U,	// ST1i64_POST
+    159795U,	// ST1i8
+    312602675U,	// ST1i8_POST
+    37280U,	// ST2Twov16b
+    3973536U,	// ST2Twov16b_POST
+    53664U,	// ST2Twov2d
+    3989920U,	// ST2Twov2d_POST
+    61856U,	// ST2Twov2s
+    4260256U,	// ST2Twov2s_POST
+    70048U,	// ST2Twov4h
+    4268448U,	// ST2Twov4h_POST
+    78240U,	// ST2Twov4s
+    4014496U,	// ST2Twov4s_POST
+    86432U,	// ST2Twov8b
+    4284832U,	// ST2Twov8b_POST
+    94624U,	// ST2Twov8h
+    4030880U,	// ST2Twov8h_POST
+    147872U,	// ST2i16
+    279024032U,	// ST2i16_POST
+    151968U,	// ST2i32
+    295809440U,	// ST2i32_POST
+    156064U,	// ST2i64
+    329372064U,	// ST2i64_POST
+    160160U,	// ST2i8
+    262271392U,	// ST2i8_POST
+    37329U,	// ST3Threev16b
+    5546449U,	// ST3Threev16b_POST
+    53713U,	// ST3Threev2d
+    5562833U,	// ST3Threev2d_POST
+    61905U,	// ST3Threev2s
+    5833169U,	// ST3Threev2s_POST
+    70097U,	// ST3Threev4h
+    5841361U,	// ST3Threev4h_POST
+    78289U,	// ST3Threev4s
+    5587409U,	// ST3Threev4s_POST
+    86481U,	// ST3Threev8b
+    5857745U,	// ST3Threev8b_POST
+    94673U,	// ST3Threev8h
+    5603793U,	// ST3Threev8h_POST
+    147921U,	// ST3i16
+    346132945U,	// ST3i16_POST
+    152017U,	// ST3i32
+    362918353U,	// ST3i32_POST
+    156113U,	// ST3i64
+    379703761U,	// ST3i64_POST
+    160209U,	// ST3i8
+    396489169U,	// ST3i8_POST
+    37346U,	// ST4Fourv16b
+    3711458U,	// ST4Fourv16b_POST
+    53730U,	// ST4Fourv2d
+    3727842U,	// ST4Fourv2d_POST
+    61922U,	// ST4Fourv2s
+    3998178U,	// ST4Fourv2s_POST
+    70114U,	// ST4Fourv4h
+    4006370U,	// ST4Fourv4h_POST
+    78306U,	// ST4Fourv4s
+    3752418U,	// ST4Fourv4s_POST
+    86498U,	// ST4Fourv8b
+    4022754U,	// ST4Fourv8b_POST
+    94690U,	// ST4Fourv8h
+    3768802U,	// ST4Fourv8h_POST
+    147938U,	// ST4i16
+    295801314U,	// ST4i16_POST
+    152034U,	// ST4i32
+    329363938U,	// ST4i32_POST
+    156130U,	// ST4i64
+    413258210U,	// ST4i64_POST
+    160226U,	// ST4i8
+    279048674U,	// ST4i8_POST
+    26485317U,	// STLRB
+    26485814U,	// STLRH
+    26486716U,	// STLRW
+    26486716U,	// STLRX
+    17049437U,	// STLXPW
+    17049437U,	// STLXPX
+    553919101U,	// STLXRB
+    553919598U,	// STLXRH
+    553920528U,	// STLXRW
+    553920528U,	// STLXRX
+    553920285U,	// STNPDi
+    553920285U,	// STNPQi
+    553920285U,	// STNPSi
+    553920285U,	// STNPWi
+    553920285U,	// STNPXi
+    553920305U,	// STPDi
+    604276529U,	// STPDpost
+    604276529U,	// STPDpre
+    553920305U,	// STPQi
+    604276529U,	// STPQpost
+    604276529U,	// STPQpre
+    553920305U,	// STPSi
+    604276529U,	// STPSpost
+    604276529U,	// STPSpre
+    553920305U,	// STPWi
+    604276529U,	// STPWpost
+    604276529U,	// STPWpre
+    553920305U,	// STPXi
+    604276529U,	// STPXpost
+    604276529U,	// STPXpre
+    1150583379U,	// STRBBpost
+    76841555U,	// STRBBpre
+    26485331U,	// STRBBroW
+    26485331U,	// STRBBroX
+    26485331U,	// STRBBui
+    1150584806U,	// STRBpost
+    76842982U,	// STRBpre
+    26486758U,	// STRBroW
+    26486758U,	// STRBroX
+    26486758U,	// STRBui
+    1150584806U,	// STRDpost
+    76842982U,	// STRDpre
+    26486758U,	// STRDroW
+    26486758U,	// STRDroX
+    26486758U,	// STRDui
+    1150583876U,	// STRHHpost
+    76842052U,	// STRHHpre
+    26485828U,	// STRHHroW
+    26485828U,	// STRHHroX
+    26485828U,	// STRHHui
+    1150584806U,	// STRHpost
+    76842982U,	// STRHpre
+    26486758U,	// STRHroW
+    26486758U,	// STRHroX
+    26486758U,	// STRHui
+    1150584806U,	// STRQpost
+    76842982U,	// STRQpre
+    26486758U,	// STRQroW
+    26486758U,	// STRQroX
+    26486758U,	// STRQui
+    1150584806U,	// STRSpost
+    76842982U,	// STRSpre
+    26486758U,	// STRSroW
+    26486758U,	// STRSroX
+    26486758U,	// STRSui
+    1150584806U,	// STRWpost
+    76842982U,	// STRWpre
+    26486758U,	// STRWroW
+    26486758U,	// STRWroX
+    26486758U,	// STRWui
+    1150584806U,	// STRXpost
+    76842982U,	// STRXpre
+    26486758U,	// STRXroW
+    26486758U,	// STRXroX
+    26486758U,	// STRXui
+    26485337U,	// STTRBi
+    26485834U,	// STTRHi
+    26486763U,	// STTRWi
+    26486763U,	// STTRXi
+    26485351U,	// STURBBi
+    26486781U,	// STURBi
+    26486781U,	// STURDi
+    26485848U,	// STURHHi
+    26486781U,	// STURHi
+    26486781U,	// STURQi
+    26486781U,	// STURSi
+    26486781U,	// STURWi
+    26486781U,	// STURXi
+    17049444U,	// STXPW
+    17049444U,	// STXPX
+    553919109U,	// STXRB
+    553919606U,	// STXRH
+    553920535U,	// STXRW
+    553920535U,	// STXRX
+    537400855U,	// SUBHNv2i64_v2i32
+    571748625U,	// SUBHNv2i64_v4i32
+    1074796055U,	// SUBHNv4i32_v4i16
+    1108881681U,	// SUBHNv4i32_v8i16
+    1644179729U,	// SUBHNv8i16_v16i8
+    1612453399U,	// SUBHNv8i16_v8i8
+    17049650U,	// SUBSWri
+    0U,	// SUBSWrr
+    17049650U,	// SUBSWrs
+    17049650U,	// SUBSWrx
+    17049650U,	// SUBSXri
+    0U,	// SUBSXrr
+    17049650U,	// SUBSXrs
+    17049650U,	// SUBSXrx
+    17049650U,	// SUBSXrx64
+    17048238U,	// SUBWri
+    0U,	// SUBWrr
+    17048238U,	// SUBWrs
+    17048238U,	// SUBWrx
+    17048238U,	// SUBXri
+    0U,	// SUBXrr
+    17048238U,	// SUBXrs
+    17048238U,	// SUBXrx
+    17048238U,	// SUBXrx64
+    2147488430U,	// SUBv16i8
+    17048238U,	// SUBv1i64
+    2684883630U,	// SUBv2i32
+    537662126U,	// SUBv2i64
+    3222278830U,	// SUBv4i16
+    1075057326U,	// SUBv4i32
+    1612190382U,	// SUBv8i16
+    3759936174U,	// SUBv8i8
+    33567585U,	// SUQADDv16i8
+    604275553U,	// SUQADDv1i16
+    604275553U,	// SUQADDv1i32
+    604275553U,	// SUQADDv1i64
+    604275553U,	// SUQADDv1i8
+    1107833697U,	// SUQADDv2i32
+    1644966753U,	// SUQADDv2i64
+    2182099809U,	// SUQADDv4i16
+    2719232865U,	// SUQADDv4i32
+    3256365921U,	// SUQADDv8i16
+    3793498977U,	// SUQADDv8i8
+    21263U,	// SVC
+    17049022U,	// SYSLxt
+    419702938U,	// SYSxt
+    436212968U,	// TBLv16i8Four
+    436212968U,	// TBLv16i8One
+    436212968U,	// TBLv16i8Three
+    436212968U,	// TBLv16i8Two
+    4196144360U,	// TBLv8i8Four
+    4196144360U,	// TBLv8i8One
+    4196144360U,	// TBLv8i8Three
+    4196144360U,	// TBLv8i8Two
+    17050183U,	// TBNZW
+    17050183U,	// TBNZX
+    452999686U,	// TBXv16i8Four
+    452999686U,	// TBXv16i8One
+    452999686U,	// TBXv16i8Three
+    452999686U,	// TBXv16i8Two
+    4212931078U,	// TBXv8i8Four
+    4212931078U,	// TBXv8i8One
+    4212931078U,	// TBXv8i8Three
+    4212931078U,	// TBXv8i8Two
+    17050167U,	// TBZW
+    17050167U,	// TBZX
+    0U,	// TCRETURNdi
+    0U,	// TCRETURNri
+    2107995U,	// TLSDESCCALL
+    0U,	// TLSDESC_BLR
+    2147487770U,	// TRN1v16i8
+    2684882970U,	// TRN1v2i32
+    537661466U,	// TRN1v2i64
+    3222278170U,	// TRN1v4i16
+    1075056666U,	// TRN1v4i32
+    1612189722U,	// TRN1v8i16
+    3759935514U,	// TRN1v8i8
+    2147488072U,	// TRN2v16i8
+    2684883272U,	// TRN2v2i32
+    537661768U,	// TRN2v2i64
+    3222278472U,	// TRN2v4i16
+    1075056968U,	// TRN2v4i32
+    1612190024U,	// TRN2v8i16
+    3759935816U,	// TRN2v8i8
+    2182623338U,	// UABALv16i8_v8i16
+    2718708938U,	// UABALv2i32_v2i64
+    3256104138U,	// UABALv4i16_v4i32
+    1108095082U,	// UABALv4i32_v2i64
+    1645490282U,	// UABALv8i16_v4i32
+    3793237194U,	// UABALv8i8_v8i16
+    2181050868U,	// UABAv16i8
+    2718446068U,	// UABAv2i32
+    3255841268U,	// UABAv4i16
+    1108619764U,	// UABAv4i32
+    1645752820U,	// UABAv8i16
+    3793498612U,	// UABAv8i8
+    2149060772U,	// UABDLv16i8_v8i16
+    2685146386U,	// UABDLv2i32_v2i64
+    3222541586U,	// UABDLv4i16_v4i32
+    1074532516U,	// UABDLv4i32_v2i64
+    1611927716U,	// UABDLv8i16_v4i32
+    3759674642U,	// UABDLv8i8_v8i16
+    2147488544U,	// UABDv16i8
+    2684883744U,	// UABDv2i32
+    3222278944U,	// UABDv4i16
+    1075057440U,	// UABDv4i32
+    1612190496U,	// UABDv8i16
+    3759936288U,	// UABDv8i8
+    35141323U,	// UADALPv16i8_v8i16
+    1117533899U,	// UADALPv2i32_v1i64
+    2181576395U,	// UADALPv4i16_v2i32
+    2718709451U,	// UADALPv4i32_v2i64
+    3256104651U,	// UADALPv8i16_v4i32
+    3792713419U,	// UADALPv8i8_v4i16
+    1578715U,	// UADDLPv16i8_v8i16
+    1083971291U,	// UADDLPv2i32_v1i64
+    2148013787U,	// UADDLPv4i16_v2i32
+    2685146843U,	// UADDLPv4i32_v2i64
+    3222542043U,	// UADDLPv8i16_v4i32
+    3759150811U,	// UADDLPv8i8_v4i16
+    272708U,	// UADDLVv16i8v
+    2147756356U,	// UADDLVv4i16v
+    2684627268U,	// UADDLVv4i32v
+    3221498180U,	// UADDLVv8i16v
+    3758369092U,	// UADDLVv8i8v
+    2149060788U,	// UADDLv16i8_v8i16
+    2685146416U,	// UADDLv2i32_v2i64
+    3222541616U,	// UADDLv4i16_v4i32
+    1074532532U,	// UADDLv4i32_v2i64
+    1611927732U,	// UADDLv8i16_v4i32
+    3759674672U,	// UADDLv8i8_v8i16
+    1612190141U,	// UADDWv16i8_v8i16
+    537663943U,	// UADDWv2i32_v2i64
+    1075059143U,	// UADDWv4i16_v4i32
+    537661885U,	// UADDWv4i32_v2i64
+    1075057085U,	// UADDWv8i16_v4i32
+    1612192199U,	// UADDWv8i8_v8i16
+    17049067U,	// UBFMWri
+    17049067U,	// UBFMXri
+    17048524U,	// UCVTFSWDri
+    17048524U,	// UCVTFSWSri
+    17048524U,	// UCVTFSXDri
+    17048524U,	// UCVTFSXSri
+    553919436U,	// UCVTFUWDri
+    553919436U,	// UCVTFUWSri
+    553919436U,	// UCVTFUXDri
+    553919436U,	// UCVTFUXSri
+    17048524U,	// UCVTFd
+    17048524U,	// UCVTFs
+    553919436U,	// UCVTFv1i32
+    553919436U,	// UCVTFv1i64
+    1074271180U,	// UCVTFv2f32
+    1611404236U,	// UCVTFv2f64
+    2684883916U,	// UCVTFv2i32_shift
+    537662412U,	// UCVTFv2i64_shift
+    2685670348U,	// UCVTFv4f32
+    1075057612U,	// UCVTFv4i32_shift
+    17049910U,	// UDIVWr
+    17049910U,	// UDIVXr
+    17049910U,	// UDIV_IntWr
+    17049910U,	// UDIV_IntXr
+    2147488579U,	// UHADDv16i8
+    2684883779U,	// UHADDv2i32
+    3222278979U,	// UHADDv4i16
+    1075057475U,	// UHADDv4i32
+    1612190531U,	// UHADDv8i16
+    3759936323U,	// UHADDv8i8
+    2147488442U,	// UHSUBv16i8
+    2684883642U,	// UHSUBv2i32
+    3222278842U,	// UHSUBv4i16
+    1075057338U,	// UHSUBv4i32
+    1612190394U,	// UHSUBv8i16
+    3759936186U,	// UHSUBv8i8
+    17048865U,	// UMADDLrrr
+    2147489616U,	// UMAXPv16i8
+    2684884816U,	// UMAXPv2i32
+    3222280016U,	// UMAXPv4i16
+    1075058512U,	// UMAXPv4i32
+    1612191568U,	// UMAXPv8i16
+    3759937360U,	// UMAXPv8i8
+    272794U,	// UMAXVv16i8v
+    2147756442U,	// UMAXVv4i16v
+    2684627354U,	// UMAXVv4i32v
+    3221498266U,	// UMAXVv8i16v
+    3758369178U,	// UMAXVv8i8v
+    2147490304U,	// UMAXv16i8
+    2684885504U,	// UMAXv2i32
+    3222280704U,	// UMAXv4i16
+    1075059200U,	// UMAXv4i32
+    1612192256U,	// UMAXv8i16
+    3759938048U,	// UMAXv8i8
+    2147489558U,	// UMINPv16i8
+    2684884758U,	// UMINPv2i32
+    3222279958U,	// UMINPv4i16
+    1075058454U,	// UMINPv4i32
+    1612191510U,	// UMINPv8i16
+    3759937302U,	// UMINPv8i8
+    272748U,	// UMINVv16i8v
+    2147756396U,	// UMINVv4i16v
+    2684627308U,	// UMINVv4i32v
+    3221498220U,	// UMINVv8i16v
+    3758369132U,	// UMINVv8i8v
+    2147489330U,	// UMINv16i8
+    2684884530U,	// UMINv2i32
+    3222279730U,	// UMINv4i16
+    1075058226U,	// UMINv4i32
+    1612191282U,	// UMINv8i16
+    3759937074U,	// UMINv8i8
+    2182623364U,	// UMLALv16i8_v8i16
+    2718708961U,	// UMLALv2i32_indexed
+    2718708961U,	// UMLALv2i32_v2i64
+    3256104161U,	// UMLALv4i16_indexed
+    3256104161U,	// UMLALv4i16_v4i32
+    1108095108U,	// UMLALv4i32_indexed
+    1108095108U,	// UMLALv4i32_v2i64
+    1645490308U,	// UMLALv8i16_indexed
+    1645490308U,	// UMLALv8i16_v4i32
+    3793237217U,	// UMLALv8i8_v8i16
+    2182623488U,	// UMLSLv16i8_v8i16
+    2718709175U,	// UMLSLv2i32_indexed
+    2718709175U,	// UMLSLv2i32_v2i64
+    3256104375U,	// UMLSLv4i16_indexed
+    3256104375U,	// UMLSLv4i16_v4i32
+    1108095232U,	// UMLSLv4i32_indexed
+    1108095232U,	// UMLSLv4i32_v2i64
+    1645490432U,	// UMLSLv8i16_indexed
+    1645490432U,	// UMLSLv8i16_v4i32
+    3793237431U,	// UMLSLv8i8_v8i16
+    272774U,	// UMOVvi16
+    537143686U,	// UMOVvi32
+    1074014598U,	// UMOVvi64
+    1610885510U,	// UMOVvi8
+    17048821U,	// UMSUBLrrr
+    17048610U,	// UMULHrr
+    2149060838U,	// UMULLv16i8_v8i16
+    2685146523U,	// UMULLv2i32_indexed
+    2685146523U,	// UMULLv2i32_v2i64
+    3222541723U,	// UMULLv4i16_indexed
+    3222541723U,	// UMULLv4i16_v4i32
+    1074532582U,	// UMULLv4i32_indexed
+    1074532582U,	// UMULLv4i32_v2i64
+    1611927782U,	// UMULLv8i16_indexed
+    1611927782U,	// UMULLv8i16_v4i32
+    3759674779U,	// UMULLv8i8_v8i16
+    2147488610U,	// UQADDv16i8
+    17048418U,	// UQADDv1i16
+    17048418U,	// UQADDv1i32
+    17048418U,	// UQADDv1i64
+    17048418U,	// UQADDv1i8
+    2684883810U,	// UQADDv2i32
+    537662306U,	// UQADDv2i64
+    3222279010U,	// UQADDv4i16
+    1075057506U,	// UQADDv4i32
+    1612190562U,	// UQADDv8i16
+    3759936354U,	// UQADDv8i8
+    2147489108U,	// UQRSHLv16i8
+    17048916U,	// UQRSHLv1i16
+    17048916U,	// UQRSHLv1i32
+    17048916U,	// UQRSHLv1i64
+    17048916U,	// UQRSHLv1i8
+    2684884308U,	// UQRSHLv2i32
+    537662804U,	// UQRSHLv2i64
+    3222279508U,	// UQRSHLv4i16
+    1075058004U,	// UQRSHLv4i32
+    1612191060U,	// UQRSHLv8i16
+    3759936852U,	// UQRSHLv8i8
+    17049180U,	// UQRSHRNb
+    17049180U,	// UQRSHRNh
+    17049180U,	// UQRSHRNs
+    1644179774U,	// UQRSHRNv16i8_shift
+    537400924U,	// UQRSHRNv2i32_shift
+    1074796124U,	// UQRSHRNv4i16_shift
+    571748670U,	// UQRSHRNv4i32_shift
+    1108881726U,	// UQRSHRNv8i16_shift
+    1612453468U,	// UQRSHRNv8i8_shift
+    17048901U,	// UQSHLb
+    17048901U,	// UQSHLd
+    17048901U,	// UQSHLh
+    17048901U,	// UQSHLs
+    2147489093U,	// UQSHLv16i8
+    2147489093U,	// UQSHLv16i8_shift
+    17048901U,	// UQSHLv1i16
+    17048901U,	// UQSHLv1i32
+    17048901U,	// UQSHLv1i64
+    17048901U,	// UQSHLv1i8
+    2684884293U,	// UQSHLv2i32
+    2684884293U,	// UQSHLv2i32_shift
+    537662789U,	// UQSHLv2i64
+    537662789U,	// UQSHLv2i64_shift
+    3222279493U,	// UQSHLv4i16
+    3222279493U,	// UQSHLv4i16_shift
+    1075057989U,	// UQSHLv4i32
+    1075057989U,	// UQSHLv4i32_shift
+    1612191045U,	// UQSHLv8i16
+    1612191045U,	// UQSHLv8i16_shift
+    3759936837U,	// UQSHLv8i8
+    3759936837U,	// UQSHLv8i8_shift
+    17049163U,	// UQSHRNb
+    17049163U,	// UQSHRNh
+    17049163U,	// UQSHRNs
+    1644179755U,	// UQSHRNv16i8_shift
+    537400907U,	// UQSHRNv2i32_shift
+    1074796107U,	// UQSHRNv4i16_shift
+    571748651U,	// UQSHRNv4i32_shift
+    1108881707U,	// UQSHRNv8i16_shift
+    1612453451U,	// UQSHRNv8i8_shift
+    2147488471U,	// UQSUBv16i8
+    17048279U,	// UQSUBv1i16
+    17048279U,	// UQSUBv1i32
+    17048279U,	// UQSUBv1i64
+    17048279U,	// UQSUBv1i8
+    2684883671U,	// UQSUBv2i32
+    537662167U,	// UQSUBv2i64
+    3222278871U,	// UQSUBv4i16
+    1075057367U,	// UQSUBv4i32
+    1612190423U,	// UQSUBv8i16
+    3759936215U,	// UQSUBv8i8
+    3254792542U,	// UQXTNv16i8
+    553920128U,	// UQXTNv1i16
+    553920128U,	// UQXTNv1i32
+    553920128U,	// UQXTNv1i8
+    1611142784U,	// UQXTNv2i32
+    2685408896U,	// UQXTNv4i16
+    1645490526U,	// UQXTNv4i32
+    2719494494U,	// UQXTNv8i16
+    3223066240U,	// UQXTNv8i8
+    1074271121U,	// URECPEv2i32
+    2685670289U,	// URECPEv4i32
+    2147488564U,	// URHADDv16i8
+    2684883764U,	// URHADDv2i32
+    3222278964U,	// URHADDv4i16
+    1075057460U,	// URHADDv4i32
+    1612190516U,	// URHADDv8i16
+    3759936308U,	// URHADDv8i8
+    2147489123U,	// URSHLv16i8
+    17048931U,	// URSHLv1i64
+    2684884323U,	// URSHLv2i32
+    537662819U,	// URSHLv2i64
+    3222279523U,	// URSHLv4i16
+    1075058019U,	// URSHLv4i32
+    1612191075U,	// URSHLv8i16
+    3759936867U,	// URSHLv8i8
+    17049508U,	// URSHRd
+    2147489700U,	// URSHRv16i8_shift
+    2684884900U,	// URSHRv2i32_shift
+    537663396U,	// URSHRv2i64_shift
+    3222280100U,	// URSHRv4i16_shift
+    1075058596U,	// URSHRv4i32_shift
+    1612191652U,	// URSHRv8i16_shift
+    3759937444U,	// URSHRv8i8_shift
+    1074271159U,	// URSQRTEv2i32
+    2685670327U,	// URSQRTEv4i32
+    67404295U,	// URSRAd
+    2181050887U,	// URSRAv16i8_shift
+    2718446087U,	// URSRAv2i32_shift
+    571224583U,	// URSRAv2i64_shift
+    3255841287U,	// URSRAv4i16_shift
+    1108619783U,	// URSRAv4i32_shift
+    1645752839U,	// URSRAv8i16_shift
+    3793498631U,	// URSRAv8i8_shift
+    2149060804U,	// USHLLv16i8_shift
+    2685146493U,	// USHLLv2i32_shift
+    3222541693U,	// USHLLv4i16_shift
+    1074532548U,	// USHLLv4i32_shift
+    1611927748U,	// USHLLv8i16_shift
+    3759674749U,	// USHLLv8i8_shift
+    2147489136U,	// USHLv16i8
+    17048944U,	// USHLv1i64
+    2684884336U,	// USHLv2i32
+    537662832U,	// USHLv2i64
+    3222279536U,	// USHLv4i16
+    1075058032U,	// USHLv4i32
+    1612191088U,	// USHLv8i16
+    3759936880U,	// USHLv8i8
+    17049521U,	// USHRd
+    2147489713U,	// USHRv16i8_shift
+    2684884913U,	// USHRv2i32_shift
+    537663409U,	// USHRv2i64_shift
+    3222280113U,	// USHRv4i16_shift
+    1075058609U,	// USHRv4i32_shift
+    1612191665U,	// USHRv8i16_shift
+    3759937457U,	// USHRv8i8_shift
+    33567577U,	// USQADDv16i8
+    604275545U,	// USQADDv1i16
+    604275545U,	// USQADDv1i32
+    604275545U,	// USQADDv1i64
+    604275545U,	// USQADDv1i8
+    1107833689U,	// USQADDv2i32
+    1644966745U,	// USQADDv2i64
+    2182099801U,	// USQADDv4i16
+    2719232857U,	// USQADDv4i32
+    3256365913U,	// USQADDv8i16
+    3793498969U,	// USQADDv8i8
+    67404308U,	// USRAd
+    2181050900U,	// USRAv16i8_shift
+    2718446100U,	// USRAv2i32_shift
+    571224596U,	// USRAv2i64_shift
+    3255841300U,	// USRAv4i16_shift
+    1108619796U,	// USRAv4i32_shift
+    1645752852U,	// USRAv8i16_shift
+    3793498644U,	// USRAv8i8_shift
+    2149060756U,	// USUBLv16i8_v8i16
+    2685146372U,	// USUBLv2i32_v2i64
+    3222541572U,	// USUBLv4i16_v4i32
+    1074532500U,	// USUBLv4i32_v2i64
+    1611927700U,	// USUBLv8i16_v4i32
+    3759674628U,	// USUBLv8i8_v8i16
+    1612190125U,	// USUBWv16i8_v8i16
+    537663920U,	// USUBWv2i32_v2i64
+    1075059120U,	// USUBWv4i16_v4i32
+    537661869U,	// USUBWv4i32_v2i64
+    1075057069U,	// USUBWv8i16_v4i32
+    1612192176U,	// USUBWv8i8_v8i16
+    2147487782U,	// UZP1v16i8
+    2684882982U,	// UZP1v2i32
+    537661478U,	// UZP1v2i64
+    3222278182U,	// UZP1v4i16
+    1075056678U,	// UZP1v4i32
+    1612189734U,	// UZP1v8i16
+    3759935526U,	// UZP1v8i8
+    2147488147U,	// UZP2v16i8
+    2684883347U,	// UZP2v2i32
+    537661843U,	// UZP2v2i64
+    3222278547U,	// UZP2v4i16
+    1075057043U,	// UZP2v4i32
+    1612190099U,	// UZP2v8i16
+    3759935891U,	// UZP2v8i8
+    3254792536U,	// XTNv16i8
+    1611142779U,	// XTNv2i32
+    2685408891U,	// XTNv4i16
+    1645490520U,	// XTNv4i32
+    2719494488U,	// XTNv8i16
+    3223066235U,	// XTNv8i8
+    2147487776U,	// ZIP1v16i8
+    2684882976U,	// ZIP1v2i32
+    537661472U,	// ZIP1v2i64
+    3222278176U,	// ZIP1v4i16
+    1075056672U,	// ZIP1v4i32
+    1612189728U,	// ZIP1v8i16
+    3759935520U,	// ZIP1v8i8
+    2147488141U,	// ZIP2v16i8
+    2684883341U,	// ZIP2v2i32
+    537661837U,	// ZIP2v2i64
+    3222278541U,	// ZIP2v4i16
+    1075057037U,	// ZIP2v4i32
+    1612190093U,	// ZIP2v8i16
+    3759935885U,	// ZIP2v8i8
+    0U
+  };
+
+  static const uint32_t OpInfo2[] = {
+    0U,	// PHI
+    0U,	// INLINEASM
+    0U,	// CFI_INSTRUCTION
+    0U,	// EH_LABEL
+    0U,	// GC_LABEL
+    0U,	// KILL
+    0U,	// EXTRACT_SUBREG
+    0U,	// INSERT_SUBREG
+    0U,	// IMPLICIT_DEF
+    0U,	// SUBREG_TO_REG
+    0U,	// COPY_TO_REGCLASS
+    0U,	// DBG_VALUE
+    0U,	// REG_SEQUENCE
+    0U,	// COPY
+    0U,	// BUNDLE
+    0U,	// LIFETIME_START
+    0U,	// LIFETIME_END
+    0U,	// STACKMAP
+    0U,	// PATCHPOINT
+    0U,	// LOAD_STACK_GUARD
+    0U,	// ABSv16i8
+    0U,	// ABSv1i64
+    0U,	// ABSv2i32
+    0U,	// ABSv2i64
+    0U,	// ABSv4i16
+    0U,	// ABSv4i32
+    0U,	// ABSv8i16
+    0U,	// ABSv8i8
+    1U,	// ADCSWr
+    1U,	// ADCSXr
+    1U,	// ADCWr
+    1U,	// ADCXr
+    265U,	// ADDHNv2i64_v2i32
+    273U,	// ADDHNv2i64_v4i32
+    521U,	// ADDHNv4i32_v4i16
+    529U,	// ADDHNv4i32_v8i16
+    785U,	// ADDHNv8i16_v16i8
+    777U,	// ADDHNv8i16_v8i8
+    1033U,	// ADDPv16i8
+    1289U,	// ADDPv2i32
+    265U,	// ADDPv2i64
+    0U,	// ADDPv2i64p
+    1545U,	// ADDPv4i16
+    521U,	// ADDPv4i32
+    777U,	// ADDPv8i16
+    1801U,	// ADDPv8i8
+    25U,	// ADDSWri
+    0U,	// ADDSWrr
+    33U,	// ADDSWrs
+    41U,	// ADDSWrx
+    25U,	// ADDSXri
+    0U,	// ADDSXrr
+    33U,	// ADDSXrs
+    41U,	// ADDSXrx
+    2049U,	// ADDSXrx64
+    0U,	// ADDVv16i8v
+    0U,	// ADDVv4i16v
+    0U,	// ADDVv4i32v
+    0U,	// ADDVv8i16v
+    0U,	// ADDVv8i8v
+    25U,	// ADDWri
+    0U,	// ADDWrr
+    33U,	// ADDWrs
+    41U,	// ADDWrx
+    25U,	// ADDXri
+    0U,	// ADDXrr
+    33U,	// ADDXrs
+    41U,	// ADDXrx
+    2049U,	// ADDXrx64
+    1033U,	// ADDv16i8
+    1U,	// ADDv1i64
+    1289U,	// ADDv2i32
+    265U,	// ADDv2i64
+    1545U,	// ADDv4i16
+    521U,	// ADDv4i32
+    777U,	// ADDv8i16
+    1801U,	// ADDv8i8
+    0U,	// ADJCALLSTACKDOWN
+    0U,	// ADJCALLSTACKUP
+    0U,	// ADR
+    0U,	// ADRP
+    0U,	// AESDrr
+    0U,	// AESErr
+    0U,	// AESIMCrr
+    0U,	// AESMCrr
+    49U,	// ANDSWri
+    0U,	// ANDSWrr
+    33U,	// ANDSWrs
+    57U,	// ANDSXri
+    0U,	// ANDSXrr
+    33U,	// ANDSXrs
+    49U,	// ANDWri
+    0U,	// ANDWrr
+    33U,	// ANDWrs
+    57U,	// ANDXri
+    0U,	// ANDXrr
+    33U,	// ANDXrs
+    1033U,	// ANDv16i8
+    1801U,	// ANDv8i8
+    1U,	// ASRVWr
+    1U,	// ASRVXr
+    0U,	// B
+    2369U,	// BFMWri
+    2369U,	// BFMXri
+    0U,	// BICSWrr
+    33U,	// BICSWrs
+    0U,	// BICSXrr
+    33U,	// BICSXrs
+    0U,	// BICWrr
+    33U,	// BICWrs
+    0U,	// BICXrr
+    33U,	// BICXrs
+    1033U,	// BICv16i8
+    0U,	// BICv2i32
+    0U,	// BICv4i16
+    0U,	// BICv4i32
+    0U,	// BICv8i16
+    1801U,	// BICv8i8
+    1033U,	// BIFv16i8
+    1801U,	// BIFv8i8
+    1041U,	// BITv16i8
+    1809U,	// BITv8i8
+    0U,	// BL
+    0U,	// BLR
+    0U,	// BR
+    0U,	// BRK
+    1041U,	// BSLv16i8
+    1809U,	// BSLv8i8
+    0U,	// Bcc
+    0U,	// CBNZW
+    0U,	// CBNZX
+    0U,	// CBZW
+    0U,	// CBZX
+    10497U,	// CCMNWi
+    10497U,	// CCMNWr
+    10497U,	// CCMNXi
+    10497U,	// CCMNXr
+    10497U,	// CCMPWi
+    10497U,	// CCMPWr
+    10497U,	// CCMPXi
+    10497U,	// CCMPXr
+    0U,	// CLREX
+    0U,	// CLSWr
+    0U,	// CLSXr
+    0U,	// CLSv16i8
+    0U,	// CLSv2i32
+    0U,	// CLSv4i16
+    0U,	// CLSv4i32
+    0U,	// CLSv8i16
+    0U,	// CLSv8i8
+    0U,	// CLZWr
+    0U,	// CLZXr
+    0U,	// CLZv16i8
+    0U,	// CLZv2i32
+    0U,	// CLZv4i16
+    0U,	// CLZv4i32
+    0U,	// CLZv8i16
+    0U,	// CLZv8i8
+    1033U,	// CMEQv16i8
+    2U,	// CMEQv16i8rz
+    1U,	// CMEQv1i64
+    2U,	// CMEQv1i64rz
+    1289U,	// CMEQv2i32
+    2U,	// CMEQv2i32rz
+    265U,	// CMEQv2i64
+    2U,	// CMEQv2i64rz
+    1545U,	// CMEQv4i16
+    2U,	// CMEQv4i16rz
+    521U,	// CMEQv4i32
+    2U,	// CMEQv4i32rz
+    777U,	// CMEQv8i16
+    2U,	// CMEQv8i16rz
+    1801U,	// CMEQv8i8
+    2U,	// CMEQv8i8rz
+    1033U,	// CMGEv16i8
+    2U,	// CMGEv16i8rz
+    1U,	// CMGEv1i64
+    2U,	// CMGEv1i64rz
+    1289U,	// CMGEv2i32
+    2U,	// CMGEv2i32rz
+    265U,	// CMGEv2i64
+    2U,	// CMGEv2i64rz
+    1545U,	// CMGEv4i16
+    2U,	// CMGEv4i16rz
+    521U,	// CMGEv4i32
+    2U,	// CMGEv4i32rz
+    777U,	// CMGEv8i16
+    2U,	// CMGEv8i16rz
+    1801U,	// CMGEv8i8
+    2U,	// CMGEv8i8rz
+    1033U,	// CMGTv16i8
+    2U,	// CMGTv16i8rz
+    1U,	// CMGTv1i64
+    2U,	// CMGTv1i64rz
+    1289U,	// CMGTv2i32
+    2U,	// CMGTv2i32rz
+    265U,	// CMGTv2i64
+    2U,	// CMGTv2i64rz
+    1545U,	// CMGTv4i16
+    2U,	// CMGTv4i16rz
+    521U,	// CMGTv4i32
+    2U,	// CMGTv4i32rz
+    777U,	// CMGTv8i16
+    2U,	// CMGTv8i16rz
+    1801U,	// CMGTv8i8
+    2U,	// CMGTv8i8rz
+    1033U,	// CMHIv16i8
+    1U,	// CMHIv1i64
+    1289U,	// CMHIv2i32
+    265U,	// CMHIv2i64
+    1545U,	// CMHIv4i16
+    521U,	// CMHIv4i32
+    777U,	// CMHIv8i16
+    1801U,	// CMHIv8i8
+    1033U,	// CMHSv16i8
+    1U,	// CMHSv1i64
+    1289U,	// CMHSv2i32
+    265U,	// CMHSv2i64
+    1545U,	// CMHSv4i16
+    521U,	// CMHSv4i32
+    777U,	// CMHSv8i16
+    1801U,	// CMHSv8i8
+    2U,	// CMLEv16i8rz
+    2U,	// CMLEv1i64rz
+    2U,	// CMLEv2i32rz
+    2U,	// CMLEv2i64rz
+    2U,	// CMLEv4i16rz
+    2U,	// CMLEv4i32rz
+    2U,	// CMLEv8i16rz
+    2U,	// CMLEv8i8rz
+    2U,	// CMLTv16i8rz
+    2U,	// CMLTv1i64rz
+    2U,	// CMLTv2i32rz
+    2U,	// CMLTv2i64rz
+    2U,	// CMLTv4i16rz
+    2U,	// CMLTv4i32rz
+    2U,	// CMLTv8i16rz
+    2U,	// CMLTv8i8rz
+    1033U,	// CMTSTv16i8
+    1U,	// CMTSTv1i64
+    1289U,	// CMTSTv2i32
+    265U,	// CMTSTv2i64
+    1545U,	// CMTSTv4i16
+    521U,	// CMTSTv4i32
+    777U,	// CMTSTv8i16
+    1801U,	// CMTSTv8i8
+    0U,	// CNTv16i8
+    0U,	// CNTv8i8
+    75U,	// CPYi16
+    75U,	// CPYi32
+    75U,	// CPYi64
+    75U,	// CPYi8
+    1U,	// CRC32Brr
+    1U,	// CRC32CBrr
+    1U,	// CRC32CHrr
+    1U,	// CRC32CWrr
+    1U,	// CRC32CXrr
+    1U,	// CRC32Hrr
+    1U,	// CRC32Wrr
+    1U,	// CRC32Xrr
+    10497U,	// CSELWr
+    10497U,	// CSELXr
+    10497U,	// CSINCWr
+    10497U,	// CSINCXr
+    10497U,	// CSINVWr
+    10497U,	// CSINVXr
+    10497U,	// CSNEGWr
+    10497U,	// CSNEGXr
+    0U,	// DCPS1
+    0U,	// DCPS2
+    0U,	// DCPS3
+    0U,	// DMB
+    0U,	// DRPS
+    0U,	// DSB
+    0U,	// DUPv16i8gpr
+    75U,	// DUPv16i8lane
+    0U,	// DUPv2i32gpr
+    75U,	// DUPv2i32lane
+    0U,	// DUPv2i64gpr
+    75U,	// DUPv2i64lane
+    0U,	// DUPv4i16gpr
+    75U,	// DUPv4i16lane
+    0U,	// DUPv4i32gpr
+    75U,	// DUPv4i32lane
+    0U,	// DUPv8i16gpr
+    75U,	// DUPv8i16lane
+    0U,	// DUPv8i8gpr
+    75U,	// DUPv8i8lane
+    0U,	// EONWrr
+    33U,	// EONWrs
+    0U,	// EONXrr
+    33U,	// EONXrs
+    49U,	// EORWri
+    0U,	// EORWrr
+    33U,	// EORWrs
+    57U,	// EORXri
+    0U,	// EORXrr
+    33U,	// EORXrs
+    1033U,	// EORv16i8
+    1801U,	// EORv8i8
+    0U,	// ERET
+    18689U,	// EXTRWrri
+    18689U,	// EXTRXrri
+    2569U,	// EXTv16i8
+    2825U,	// EXTv8i8
+    0U,	// F128CSEL
+    1U,	// FABD32
+    1U,	// FABD64
+    1289U,	// FABDv2f32
+    265U,	// FABDv2f64
+    521U,	// FABDv4f32
+    0U,	// FABSDr
+    0U,	// FABSSr
+    0U,	// FABSv2f32
+    0U,	// FABSv2f64
+    0U,	// FABSv4f32
+    1U,	// FACGE32
+    1U,	// FACGE64
+    1289U,	// FACGEv2f32
+    265U,	// FACGEv2f64
+    521U,	// FACGEv4f32
+    1U,	// FACGT32
+    1U,	// FACGT64
+    1289U,	// FACGTv2f32
+    265U,	// FACGTv2f64
+    521U,	// FACGTv4f32
+    1U,	// FADDDrr
+    1289U,	// FADDPv2f32
+    265U,	// FADDPv2f64
+    0U,	// FADDPv2i32p
+    0U,	// FADDPv2i64p
+    521U,	// FADDPv4f32
+    1U,	// FADDSrr
+    1289U,	// FADDv2f32
+    265U,	// FADDv2f64
+    521U,	// FADDv4f32
+    10497U,	// FCCMPDrr
+    10497U,	// FCCMPEDrr
+    10497U,	// FCCMPESrr
+    10497U,	// FCCMPSrr
+    1U,	// FCMEQ32
+    1U,	// FCMEQ64
+    3U,	// FCMEQv1i32rz
+    3U,	// FCMEQv1i64rz
+    1289U,	// FCMEQv2f32
+    265U,	// FCMEQv2f64
+    3U,	// FCMEQv2i32rz
+    3U,	// FCMEQv2i64rz
+    521U,	// FCMEQv4f32
+    3U,	// FCMEQv4i32rz
+    1U,	// FCMGE32
+    1U,	// FCMGE64
+    3U,	// FCMGEv1i32rz
+    3U,	// FCMGEv1i64rz
+    1289U,	// FCMGEv2f32
+    265U,	// FCMGEv2f64
+    3U,	// FCMGEv2i32rz
+    3U,	// FCMGEv2i64rz
+    521U,	// FCMGEv4f32
+    3U,	// FCMGEv4i32rz
+    1U,	// FCMGT32
+    1U,	// FCMGT64
+    3U,	// FCMGTv1i32rz
+    3U,	// FCMGTv1i64rz
+    1289U,	// FCMGTv2f32
+    265U,	// FCMGTv2f64
+    3U,	// FCMGTv2i32rz
+    3U,	// FCMGTv2i64rz
+    521U,	// FCMGTv4f32
+    3U,	// FCMGTv4i32rz
+    3U,	// FCMLEv1i32rz
+    3U,	// FCMLEv1i64rz
+    3U,	// FCMLEv2i32rz
+    3U,	// FCMLEv2i64rz
+    3U,	// FCMLEv4i32rz
+    3U,	// FCMLTv1i32rz
+    3U,	// FCMLTv1i64rz
+    3U,	// FCMLTv2i32rz
+    3U,	// FCMLTv2i64rz
+    3U,	// FCMLTv4i32rz
+    0U,	// FCMPDri
+    0U,	// FCMPDrr
+    0U,	// FCMPEDri
+    0U,	// FCMPEDrr
+    0U,	// FCMPESri
+    0U,	// FCMPESrr
+    0U,	// FCMPSri
+    0U,	// FCMPSrr
+    10497U,	// FCSELDrrr
+    10497U,	// FCSELSrrr
+    0U,	// FCVTASUWDr
+    0U,	// FCVTASUWSr
+    0U,	// FCVTASUXDr
+    0U,	// FCVTASUXSr
+    0U,	// FCVTASv1i32
+    0U,	// FCVTASv1i64
+    0U,	// FCVTASv2f32
+    0U,	// FCVTASv2f64
+    0U,	// FCVTASv4f32
+    0U,	// FCVTAUUWDr
+    0U,	// FCVTAUUWSr
+    0U,	// FCVTAUUXDr
+    0U,	// FCVTAUUXSr
+    0U,	// FCVTAUv1i32
+    0U,	// FCVTAUv1i64
+    0U,	// FCVTAUv2f32
+    0U,	// FCVTAUv2f64
+    0U,	// FCVTAUv4f32
+    0U,	// FCVTDHr
+    0U,	// FCVTDSr
+    0U,	// FCVTHDr
+    0U,	// FCVTHSr
+    0U,	// FCVTLv2i32
+    0U,	// FCVTLv4i16
+    0U,	// FCVTLv4i32
+    0U,	// FCVTLv8i16
+    0U,	// FCVTMSUWDr
+    0U,	// FCVTMSUWSr
+    0U,	// FCVTMSUXDr
+    0U,	// FCVTMSUXSr
+    0U,	// FCVTMSv1i32
+    0U,	// FCVTMSv1i64
+    0U,	// FCVTMSv2f32
+    0U,	// FCVTMSv2f64
+    0U,	// FCVTMSv4f32
+    0U,	// FCVTMUUWDr
+    0U,	// FCVTMUUWSr
+    0U,	// FCVTMUUXDr
+    0U,	// FCVTMUUXSr
+    0U,	// FCVTMUv1i32
+    0U,	// FCVTMUv1i64
+    0U,	// FCVTMUv2f32
+    0U,	// FCVTMUv2f64
+    0U,	// FCVTMUv4f32
+    0U,	// FCVTNSUWDr
+    0U,	// FCVTNSUWSr
+    0U,	// FCVTNSUXDr
+    0U,	// FCVTNSUXSr
+    0U,	// FCVTNSv1i32
+    0U,	// FCVTNSv1i64
+    0U,	// FCVTNSv2f32
+    0U,	// FCVTNSv2f64
+    0U,	// FCVTNSv4f32
+    0U,	// FCVTNUUWDr
+    0U,	// FCVTNUUWSr
+    0U,	// FCVTNUUXDr
+    0U,	// FCVTNUUXSr
+    0U,	// FCVTNUv1i32
+    0U,	// FCVTNUv1i64
+    0U,	// FCVTNUv2f32
+    0U,	// FCVTNUv2f64
+    0U,	// FCVTNUv4f32
+    0U,	// FCVTNv2i32
+    0U,	// FCVTNv4i16
+    0U,	// FCVTNv4i32
+    0U,	// FCVTNv8i16
+    0U,	// FCVTPSUWDr
+    0U,	// FCVTPSUWSr
+    0U,	// FCVTPSUXDr
+    0U,	// FCVTPSUXSr
+    0U,	// FCVTPSv1i32
+    0U,	// FCVTPSv1i64
+    0U,	// FCVTPSv2f32
+    0U,	// FCVTPSv2f64
+    0U,	// FCVTPSv4f32
+    0U,	// FCVTPUUWDr
+    0U,	// FCVTPUUWSr
+    0U,	// FCVTPUUXDr
+    0U,	// FCVTPUUXSr
+    0U,	// FCVTPUv1i32
+    0U,	// FCVTPUv1i64
+    0U,	// FCVTPUv2f32
+    0U,	// FCVTPUv2f64
+    0U,	// FCVTPUv4f32
+    0U,	// FCVTSDr
+    0U,	// FCVTSHr
+    0U,	// FCVTXNv1i64
+    0U,	// FCVTXNv2f32
+    0U,	// FCVTXNv4f32
+    1U,	// FCVTZSSWDri
+    1U,	// FCVTZSSWSri
+    1U,	// FCVTZSSXDri
+    1U,	// FCVTZSSXSri
+    0U,	// FCVTZSUWDr
+    0U,	// FCVTZSUWSr
+    0U,	// FCVTZSUXDr
+    0U,	// FCVTZSUXSr
+    1U,	// FCVTZS_IntSWDri
+    1U,	// FCVTZS_IntSWSri
+    1U,	// FCVTZS_IntSXDri
+    1U,	// FCVTZS_IntSXSri
+    0U,	// FCVTZS_IntUWDr
+    0U,	// FCVTZS_IntUWSr
+    0U,	// FCVTZS_IntUXDr
+    0U,	// FCVTZS_IntUXSr
+    0U,	// FCVTZS_Intv2f32
+    0U,	// FCVTZS_Intv2f64
+    0U,	// FCVTZS_Intv4f32
+    1U,	// FCVTZSd
+    1U,	// FCVTZSs
+    0U,	// FCVTZSv1i32
+    0U,	// FCVTZSv1i64
+    0U,	// FCVTZSv2f32
+    0U,	// FCVTZSv2f64
+    1U,	// FCVTZSv2i32_shift
+    1U,	// FCVTZSv2i64_shift
+    0U,	// FCVTZSv4f32
+    1U,	// FCVTZSv4i32_shift
+    1U,	// FCVTZUSWDri
+    1U,	// FCVTZUSWSri
+    1U,	// FCVTZUSXDri
+    1U,	// FCVTZUSXSri
+    0U,	// FCVTZUUWDr
+    0U,	// FCVTZUUWSr
+    0U,	// FCVTZUUXDr
+    0U,	// FCVTZUUXSr
+    1U,	// FCVTZU_IntSWDri
+    1U,	// FCVTZU_IntSWSri
+    1U,	// FCVTZU_IntSXDri
+    1U,	// FCVTZU_IntSXSri
+    0U,	// FCVTZU_IntUWDr
+    0U,	// FCVTZU_IntUWSr
+    0U,	// FCVTZU_IntUXDr
+    0U,	// FCVTZU_IntUXSr
+    0U,	// FCVTZU_Intv2f32
+    0U,	// FCVTZU_Intv2f64
+    0U,	// FCVTZU_Intv4f32
+    1U,	// FCVTZUd
+    1U,	// FCVTZUs
+    0U,	// FCVTZUv1i32
+    0U,	// FCVTZUv1i64
+    0U,	// FCVTZUv2f32
+    0U,	// FCVTZUv2f64
+    1U,	// FCVTZUv2i32_shift
+    1U,	// FCVTZUv2i64_shift
+    0U,	// FCVTZUv4f32
+    1U,	// FCVTZUv4i32_shift
+    1U,	// FDIVDrr
+    1U,	// FDIVSrr
+    1289U,	// FDIVv2f32
+    265U,	// FDIVv2f64
+    521U,	// FDIVv4f32
+    18689U,	// FMADDDrrr
+    18689U,	// FMADDSrrr
+    1U,	// FMAXDrr
+    1U,	// FMAXNMDrr
+    1289U,	// FMAXNMPv2f32
+    265U,	// FMAXNMPv2f64
+    0U,	// FMAXNMPv2i32p
+    0U,	// FMAXNMPv2i64p
+    521U,	// FMAXNMPv4f32
+    1U,	// FMAXNMSrr
+    0U,	// FMAXNMVv4i32v
+    1289U,	// FMAXNMv2f32
+    265U,	// FMAXNMv2f64
+    521U,	// FMAXNMv4f32
+    1289U,	// FMAXPv2f32
+    265U,	// FMAXPv2f64
+    0U,	// FMAXPv2i32p
+    0U,	// FMAXPv2i64p
+    521U,	// FMAXPv4f32
+    1U,	// FMAXSrr
+    0U,	// FMAXVv4i32v
+    1289U,	// FMAXv2f32
+    265U,	// FMAXv2f64
+    521U,	// FMAXv4f32
+    1U,	// FMINDrr
+    1U,	// FMINNMDrr
+    1289U,	// FMINNMPv2f32
+    265U,	// FMINNMPv2f64
+    0U,	// FMINNMPv2i32p
+    0U,	// FMINNMPv2i64p
+    521U,	// FMINNMPv4f32
+    1U,	// FMINNMSrr
+    0U,	// FMINNMVv4i32v
+    1289U,	// FMINNMv2f32
+    265U,	// FMINNMv2f64
+    521U,	// FMINNMv4f32
+    1289U,	// FMINPv2f32
+    265U,	// FMINPv2f64
+    0U,	// FMINPv2i32p
+    0U,	// FMINPv2i64p
+    521U,	// FMINPv4f32
+    1U,	// FMINSrr
+    0U,	// FMINVv4i32v
+    1289U,	// FMINv2f32
+    265U,	// FMINv2f64
+    521U,	// FMINv4f32
+    27665U,	// FMLAv1i32_indexed
+    27921U,	// FMLAv1i64_indexed
+    1297U,	// FMLAv2f32
+    273U,	// FMLAv2f64
+    27665U,	// FMLAv2i32_indexed
+    27921U,	// FMLAv2i64_indexed
+    529U,	// FMLAv4f32
+    27665U,	// FMLAv4i32_indexed
+    27665U,	// FMLSv1i32_indexed
+    27921U,	// FMLSv1i64_indexed
+    1297U,	// FMLSv2f32
+    273U,	// FMLSv2f64
+    27665U,	// FMLSv2i32_indexed
+    27921U,	// FMLSv2i64_indexed
+    529U,	// FMLSv4f32
+    27665U,	// FMLSv4i32_indexed
+    75U,	// FMOVDXHighr
+    0U,	// FMOVDXr
+    0U,	// FMOVDi
+    0U,	// FMOVDr
+    0U,	// FMOVSWr
+    0U,	// FMOVSi
+    0U,	// FMOVSr
+    0U,	// FMOVWSr
+    0U,	// FMOVXDHighr
+    0U,	// FMOVXDr
+    0U,	// FMOVv2f32_ns
+    0U,	// FMOVv2f64_ns
+    0U,	// FMOVv4f32_ns
+    18689U,	// FMSUBDrrr
+    18689U,	// FMSUBSrrr
+    1U,	// FMULDrr
+    1U,	// FMULSrr
+    1U,	// FMULX32
+    1U,	// FMULX64
+    35849U,	// FMULXv1i32_indexed
+    36105U,	// FMULXv1i64_indexed
+    1289U,	// FMULXv2f32
+    265U,	// FMULXv2f64
+    35849U,	// FMULXv2i32_indexed
+    36105U,	// FMULXv2i64_indexed
+    521U,	// FMULXv4f32
+    35849U,	// FMULXv4i32_indexed
+    35849U,	// FMULv1i32_indexed
+    36105U,	// FMULv1i64_indexed
+    1289U,	// FMULv2f32
+    265U,	// FMULv2f64
+    35849U,	// FMULv2i32_indexed
+    36105U,	// FMULv2i64_indexed
+    521U,	// FMULv4f32
+    35849U,	// FMULv4i32_indexed
+    0U,	// FNEGDr
+    0U,	// FNEGSr
+    0U,	// FNEGv2f32
+    0U,	// FNEGv2f64
+    0U,	// FNEGv4f32
+    18689U,	// FNMADDDrrr
+    18689U,	// FNMADDSrrr
+    18689U,	// FNMSUBDrrr
+    18689U,	// FNMSUBSrrr
+    1U,	// FNMULDrr
+    1U,	// FNMULSrr
+    0U,	// FRECPEv1i32
+    0U,	// FRECPEv1i64
+    0U,	// FRECPEv2f32
+    0U,	// FRECPEv2f64
+    0U,	// FRECPEv4f32
+    1U,	// FRECPS32
+    1U,	// FRECPS64
+    1289U,	// FRECPSv2f32
+    265U,	// FRECPSv2f64
+    521U,	// FRECPSv4f32
+    0U,	// FRECPXv1i32
+    0U,	// FRECPXv1i64
+    0U,	// FRINTADr
+    0U,	// FRINTASr
+    0U,	// FRINTAv2f32
+    0U,	// FRINTAv2f64
+    0U,	// FRINTAv4f32
+    0U,	// FRINTIDr
+    0U,	// FRINTISr
+    0U,	// FRINTIv2f32
+    0U,	// FRINTIv2f64
+    0U,	// FRINTIv4f32
+    0U,	// FRINTMDr
+    0U,	// FRINTMSr
+    0U,	// FRINTMv2f32
+    0U,	// FRINTMv2f64
+    0U,	// FRINTMv4f32
+    0U,	// FRINTNDr
+    0U,	// FRINTNSr
+    0U,	// FRINTNv2f32
+    0U,	// FRINTNv2f64
+    0U,	// FRINTNv4f32
+    0U,	// FRINTPDr
+    0U,	// FRINTPSr
+    0U,	// FRINTPv2f32
+    0U,	// FRINTPv2f64
+    0U,	// FRINTPv4f32
+    0U,	// FRINTXDr
+    0U,	// FRINTXSr
+    0U,	// FRINTXv2f32
+    0U,	// FRINTXv2f64
+    0U,	// FRINTXv4f32
+    0U,	// FRINTZDr
+    0U,	// FRINTZSr
+    0U,	// FRINTZv2f32
+    0U,	// FRINTZv2f64
+    0U,	// FRINTZv4f32
+    0U,	// FRSQRTEv1i32
+    0U,	// FRSQRTEv1i64
+    0U,	// FRSQRTEv2f32
+    0U,	// FRSQRTEv2f64
+    0U,	// FRSQRTEv4f32
+    1U,	// FRSQRTS32
+    1U,	// FRSQRTS64
+    1289U,	// FRSQRTSv2f32
+    265U,	// FRSQRTSv2f64
+    521U,	// FRSQRTSv4f32
+    0U,	// FSQRTDr
+    0U,	// FSQRTSr
+    0U,	// FSQRTv2f32
+    0U,	// FSQRTv2f64
+    0U,	// FSQRTv4f32
+    1U,	// FSUBDrr
+    1U,	// FSUBSrr
+    1289U,	// FSUBv2f32
+    265U,	// FSUBv2f64
+    521U,	// FSUBv4f32
+    0U,	// HINT
+    0U,	// HLT
+    0U,	// HVC
+    0U,	// INSvi16gpr
+    83U,	// INSvi16lane
+    0U,	// INSvi32gpr
+    83U,	// INSvi32lane
+    0U,	// INSvi64gpr
+    83U,	// INSvi64lane
+    0U,	// INSvi8gpr
+    83U,	// INSvi8lane
+    0U,	// ISB
+    0U,	// LD1Fourv16b
+    0U,	// LD1Fourv16b_POST
+    0U,	// LD1Fourv1d
+    0U,	// LD1Fourv1d_POST
+    0U,	// LD1Fourv2d
+    0U,	// LD1Fourv2d_POST
+    0U,	// LD1Fourv2s
+    0U,	// LD1Fourv2s_POST
+    0U,	// LD1Fourv4h
+    0U,	// LD1Fourv4h_POST
+    0U,	// LD1Fourv4s
+    0U,	// LD1Fourv4s_POST
+    0U,	// LD1Fourv8b
+    0U,	// LD1Fourv8b_POST
+    0U,	// LD1Fourv8h
+    0U,	// LD1Fourv8h_POST
+    0U,	// LD1Onev16b
+    0U,	// LD1Onev16b_POST
+    0U,	// LD1Onev1d
+    0U,	// LD1Onev1d_POST
+    0U,	// LD1Onev2d
+    0U,	// LD1Onev2d_POST
+    0U,	// LD1Onev2s
+    0U,	// LD1Onev2s_POST
+    0U,	// LD1Onev4h
+    0U,	// LD1Onev4h_POST
+    0U,	// LD1Onev4s
+    0U,	// LD1Onev4s_POST
+    0U,	// LD1Onev8b
+    0U,	// LD1Onev8b_POST
+    0U,	// LD1Onev8h
+    0U,	// LD1Onev8h_POST
+    0U,	// LD1Rv16b
+    0U,	// LD1Rv16b_POST
+    0U,	// LD1Rv1d
+    0U,	// LD1Rv1d_POST
+    0U,	// LD1Rv2d
+    0U,	// LD1Rv2d_POST
+    0U,	// LD1Rv2s
+    0U,	// LD1Rv2s_POST
+    0U,	// LD1Rv4h
+    0U,	// LD1Rv4h_POST
+    0U,	// LD1Rv4s
+    0U,	// LD1Rv4s_POST
+    0U,	// LD1Rv8b
+    0U,	// LD1Rv8b_POST
+    0U,	// LD1Rv8h
+    0U,	// LD1Rv8h_POST
+    0U,	// LD1Threev16b
+    0U,	// LD1Threev16b_POST
+    0U,	// LD1Threev1d
+    0U,	// LD1Threev1d_POST
+    0U,	// LD1Threev2d
+    0U,	// LD1Threev2d_POST
+    0U,	// LD1Threev2s
+    0U,	// LD1Threev2s_POST
+    0U,	// LD1Threev4h
+    0U,	// LD1Threev4h_POST
+    0U,	// LD1Threev4s
+    0U,	// LD1Threev4s_POST
+    0U,	// LD1Threev8b
+    0U,	// LD1Threev8b_POST
+    0U,	// LD1Threev8h
+    0U,	// LD1Threev8h_POST
+    0U,	// LD1Twov16b
+    0U,	// LD1Twov16b_POST
+    0U,	// LD1Twov1d
+    0U,	// LD1Twov1d_POST
+    0U,	// LD1Twov2d
+    0U,	// LD1Twov2d_POST
+    0U,	// LD1Twov2s
+    0U,	// LD1Twov2s_POST
+    0U,	// LD1Twov4h
+    0U,	// LD1Twov4h_POST
+    0U,	// LD1Twov4s
+    0U,	// LD1Twov4s_POST
+    0U,	// LD1Twov8b
+    0U,	// LD1Twov8b_POST
+    0U,	// LD1Twov8h
+    0U,	// LD1Twov8h_POST
+    0U,	// LD1i16
+    0U,	// LD1i16_POST
+    0U,	// LD1i32
+    0U,	// LD1i32_POST
+    0U,	// LD1i64
+    0U,	// LD1i64_POST
+    0U,	// LD1i8
+    0U,	// LD1i8_POST
+    0U,	// LD2Rv16b
+    0U,	// LD2Rv16b_POST
+    0U,	// LD2Rv1d
+    0U,	// LD2Rv1d_POST
+    0U,	// LD2Rv2d
+    0U,	// LD2Rv2d_POST
+    0U,	// LD2Rv2s
+    0U,	// LD2Rv2s_POST
+    0U,	// LD2Rv4h
+    0U,	// LD2Rv4h_POST
+    0U,	// LD2Rv4s
+    0U,	// LD2Rv4s_POST
+    0U,	// LD2Rv8b
+    0U,	// LD2Rv8b_POST
+    0U,	// LD2Rv8h
+    0U,	// LD2Rv8h_POST
+    0U,	// LD2Twov16b
+    0U,	// LD2Twov16b_POST
+    0U,	// LD2Twov2d
+    0U,	// LD2Twov2d_POST
+    0U,	// LD2Twov2s
+    0U,	// LD2Twov2s_POST
+    0U,	// LD2Twov4h
+    0U,	// LD2Twov4h_POST
+    0U,	// LD2Twov4s
+    0U,	// LD2Twov4s_POST
+    0U,	// LD2Twov8b
+    0U,	// LD2Twov8b_POST
+    0U,	// LD2Twov8h
+    0U,	// LD2Twov8h_POST
+    0U,	// LD2i16
+    0U,	// LD2i16_POST
+    0U,	// LD2i32
+    0U,	// LD2i32_POST
+    0U,	// LD2i64
+    0U,	// LD2i64_POST
+    0U,	// LD2i8
+    0U,	// LD2i8_POST
+    0U,	// LD3Rv16b
+    0U,	// LD3Rv16b_POST
+    0U,	// LD3Rv1d
+    0U,	// LD3Rv1d_POST
+    0U,	// LD3Rv2d
+    0U,	// LD3Rv2d_POST
+    0U,	// LD3Rv2s
+    0U,	// LD3Rv2s_POST
+    0U,	// LD3Rv4h
+    0U,	// LD3Rv4h_POST
+    0U,	// LD3Rv4s
+    0U,	// LD3Rv4s_POST
+    0U,	// LD3Rv8b
+    0U,	// LD3Rv8b_POST
+    0U,	// LD3Rv8h
+    0U,	// LD3Rv8h_POST
+    0U,	// LD3Threev16b
+    0U,	// LD3Threev16b_POST
+    0U,	// LD3Threev2d
+    0U,	// LD3Threev2d_POST
+    0U,	// LD3Threev2s
+    0U,	// LD3Threev2s_POST
+    0U,	// LD3Threev4h
+    0U,	// LD3Threev4h_POST
+    0U,	// LD3Threev4s
+    0U,	// LD3Threev4s_POST
+    0U,	// LD3Threev8b
+    0U,	// LD3Threev8b_POST
+    0U,	// LD3Threev8h
+    0U,	// LD3Threev8h_POST
+    0U,	// LD3i16
+    0U,	// LD3i16_POST
+    0U,	// LD3i32
+    0U,	// LD3i32_POST
+    0U,	// LD3i64
+    0U,	// LD3i64_POST
+    0U,	// LD3i8
+    0U,	// LD3i8_POST
+    0U,	// LD4Fourv16b
+    0U,	// LD4Fourv16b_POST
+    0U,	// LD4Fourv2d
+    0U,	// LD4Fourv2d_POST
+    0U,	// LD4Fourv2s
+    0U,	// LD4Fourv2s_POST
+    0U,	// LD4Fourv4h
+    0U,	// LD4Fourv4h_POST
+    0U,	// LD4Fourv4s
+    0U,	// LD4Fourv4s_POST
+    0U,	// LD4Fourv8b
+    0U,	// LD4Fourv8b_POST
+    0U,	// LD4Fourv8h
+    0U,	// LD4Fourv8h_POST
+    0U,	// LD4Rv16b
+    0U,	// LD4Rv16b_POST
+    0U,	// LD4Rv1d
+    0U,	// LD4Rv1d_POST
+    0U,	// LD4Rv2d
+    0U,	// LD4Rv2d_POST
+    0U,	// LD4Rv2s
+    0U,	// LD4Rv2s_POST
+    0U,	// LD4Rv4h
+    0U,	// LD4Rv4h_POST
+    0U,	// LD4Rv4s
+    0U,	// LD4Rv4s_POST
+    0U,	// LD4Rv8b
+    0U,	// LD4Rv8b_POST
+    0U,	// LD4Rv8h
+    0U,	// LD4Rv8h_POST
+    0U,	// LD4i16
+    0U,	// LD4i16_POST
+    0U,	// LD4i32
+    0U,	// LD4i32_POST
+    0U,	// LD4i64
+    0U,	// LD4i64_POST
+    0U,	// LD4i8
+    0U,	// LD4i8_POST
+    4U,	// LDARB
+    4U,	// LDARH
+    4U,	// LDARW
+    4U,	// LDARX
+    3588U,	// LDAXPW
+    3588U,	// LDAXPX
+    4U,	// LDAXRB
+    4U,	// LDAXRH
+    4U,	// LDAXRW
+    4U,	// LDAXRX
+    43268U,	// LDNPDi
+    51460U,	// LDNPQi
+    59652U,	// LDNPSi
+    59652U,	// LDNPWi
+    43268U,	// LDNPXi
+    43268U,	// LDPDi
+    69444U,	// LDPDpost
+    330052U,	// LDPDpre
+    51460U,	// LDPQi
+    77636U,	// LDPQpost
+    338244U,	// LDPQpre
+    59652U,	// LDPSWi
+    85828U,	// LDPSWpost
+    346436U,	// LDPSWpre
+    59652U,	// LDPSi
+    85828U,	// LDPSpost
+    346436U,	// LDPSpre
+    59652U,	// LDPWi
+    85828U,	// LDPWpost
+    346436U,	// LDPWpre
+    43268U,	// LDPXi
+    69444U,	// LDPXpost
+    330052U,	// LDPXpre
+    4U,	// LDRBBpost
+    4161U,	// LDRBBpre
+    92417U,	// LDRBBroW
+    100609U,	// LDRBBroX
+    89U,	// LDRBBui
+    4U,	// LDRBpost
+    4161U,	// LDRBpre
+    92417U,	// LDRBroW
+    100609U,	// LDRBroX
+    89U,	// LDRBui
+    0U,	// LDRDl
+    4U,	// LDRDpost
+    4161U,	// LDRDpre
+    108801U,	// LDRDroW
+    116993U,	// LDRDroX
+    97U,	// LDRDui
+    4U,	// LDRHHpost
+    4161U,	// LDRHHpre
+    125185U,	// LDRHHroW
+    133377U,	// LDRHHroX
+    105U,	// LDRHHui
+    4U,	// LDRHpost
+    4161U,	// LDRHpre
+    125185U,	// LDRHroW
+    133377U,	// LDRHroX
+    105U,	// LDRHui
+    0U,	// LDRQl
+    4U,	// LDRQpost
+    4161U,	// LDRQpre
+    141569U,	// LDRQroW
+    149761U,	// LDRQroX
+    113U,	// LDRQui
+    4U,	// LDRSBWpost
+    4161U,	// LDRSBWpre
+    92417U,	// LDRSBWroW
+    100609U,	// LDRSBWroX
+    89U,	// LDRSBWui
+    4U,	// LDRSBXpost
+    4161U,	// LDRSBXpre
+    92417U,	// LDRSBXroW
+    100609U,	// LDRSBXroX
+    89U,	// LDRSBXui
+    4U,	// LDRSHWpost
+    4161U,	// LDRSHWpre
+    125185U,	// LDRSHWroW
+    133377U,	// LDRSHWroX
+    105U,	// LDRSHWui
+    4U,	// LDRSHXpost
+    4161U,	// LDRSHXpre
+    125185U,	// LDRSHXroW
+    133377U,	// LDRSHXroX
+    105U,	// LDRSHXui
+    0U,	// LDRSWl
+    4U,	// LDRSWpost
+    4161U,	// LDRSWpre
+    157953U,	// LDRSWroW
+    166145U,	// LDRSWroX
+    121U,	// LDRSWui
+    0U,	// LDRSl
+    4U,	// LDRSpost
+    4161U,	// LDRSpre
+    157953U,	// LDRSroW
+    166145U,	// LDRSroX
+    121U,	// LDRSui
+    0U,	// LDRWl
+    4U,	// LDRWpost
+    4161U,	// LDRWpre
+    157953U,	// LDRWroW
+    166145U,	// LDRWroX
+    121U,	// LDRWui
+    0U,	// LDRXl
+    4U,	// LDRXpost
+    4161U,	// LDRXpre
+    108801U,	// LDRXroW
+    116993U,	// LDRXroX
+    97U,	// LDRXui
+    3585U,	// LDTRBi
+    3585U,	// LDTRHi
+    3585U,	// LDTRSBWi
+    3585U,	// LDTRSBXi
+    3585U,	// LDTRSHWi
+    3585U,	// LDTRSHXi
+    3585U,	// LDTRSWi
+    3585U,	// LDTRWi
+    3585U,	// LDTRXi
+    3585U,	// LDURBBi
+    3585U,	// LDURBi
+    3585U,	// LDURDi
+    3585U,	// LDURHHi
+    3585U,	// LDURHi
+    3585U,	// LDURQi
+    3585U,	// LDURSBWi
+    3585U,	// LDURSBXi
+    3585U,	// LDURSHWi
+    3585U,	// LDURSHXi
+    3585U,	// LDURSWi
+    3585U,	// LDURSi
+    3585U,	// LDURWi
+    3585U,	// LDURXi
+    3588U,	// LDXPW
+    3588U,	// LDXPX
+    4U,	// LDXRB
+    4U,	// LDXRH
+    4U,	// LDXRW
+    4U,	// LDXRX
+    0U,	// LOADgot
+    1U,	// LSLVWr
+    1U,	// LSLVXr
+    1U,	// LSRVWr
+    1U,	// LSRVXr
+    18689U,	// MADDWrrr
+    18689U,	// MADDXrrr
+    1041U,	// MLAv16i8
+    1297U,	// MLAv2i32
+    27665U,	// MLAv2i32_indexed
+    1553U,	// MLAv4i16
+    28945U,	// MLAv4i16_indexed
+    529U,	// MLAv4i32
+    27665U,	// MLAv4i32_indexed
+    785U,	// MLAv8i16
+    28945U,	// MLAv8i16_indexed
+    1809U,	// MLAv8i8
+    1041U,	// MLSv16i8
+    1297U,	// MLSv2i32
+    27665U,	// MLSv2i32_indexed
+    1553U,	// MLSv4i16
+    28945U,	// MLSv4i16_indexed
+    529U,	// MLSv4i32
+    27665U,	// MLSv4i32_indexed
+    785U,	// MLSv8i16
+    28945U,	// MLSv8i16_indexed
+    1809U,	// MLSv8i8
+    0U,	// MOVID
+    0U,	// MOVIv16b_ns
+    0U,	// MOVIv2d_ns
+    4U,	// MOVIv2i32
+    4U,	// MOVIv2s_msl
+    4U,	// MOVIv4i16
+    4U,	// MOVIv4i32
+    4U,	// MOVIv4s_msl
+    0U,	// MOVIv8b_ns
+    4U,	// MOVIv8i16
+    0U,	// MOVKWi
+    0U,	// MOVKXi
+    4U,	// MOVNWi
+    4U,	// MOVNXi
+    4U,	// MOVZWi
+    4U,	// MOVZXi
+    0U,	// MOVaddr
+    0U,	// MOVaddrBA
+    0U,	// MOVaddrCP
+    0U,	// MOVaddrEXT
+    0U,	// MOVaddrJT
+    0U,	// MOVaddrTLS
+    0U,	// MOVi32imm
+    0U,	// MOVi64imm
+    0U,	// MRS
+    0U,	// MSR
+    0U,	// MSRpstate
+    18689U,	// MSUBWrrr
+    18689U,	// MSUBXrrr
+    1033U,	// MULv16i8
+    1289U,	// MULv2i32
+    35849U,	// MULv2i32_indexed
+    1545U,	// MULv4i16
+    37129U,	// MULv4i16_indexed
+    521U,	// MULv4i32
+    35849U,	// MULv4i32_indexed
+    777U,	// MULv8i16
+    37129U,	// MULv8i16_indexed
+    1801U,	// MULv8i8
+    4U,	// MVNIv2i32
+    4U,	// MVNIv2s_msl
+    4U,	// MVNIv4i16
+    4U,	// MVNIv4i32
+    4U,	// MVNIv4s_msl
+    4U,	// MVNIv8i16
+    0U,	// NEGv16i8
+    0U,	// NEGv1i64
+    0U,	// NEGv2i32
+    0U,	// NEGv2i64
+    0U,	// NEGv4i16
+    0U,	// NEGv4i32
+    0U,	// NEGv8i16
+    0U,	// NEGv8i8
+    0U,	// NOTv16i8
+    0U,	// NOTv8i8
+    0U,	// ORNWrr
+    33U,	// ORNWrs
+    0U,	// ORNXrr
+    33U,	// ORNXrs
+    1033U,	// ORNv16i8
+    1801U,	// ORNv8i8
+    49U,	// ORRWri
+    0U,	// ORRWrr
+    33U,	// ORRWrs
+    57U,	// ORRXri
+    0U,	// ORRXrr
+    33U,	// ORRXrs
+    1033U,	// ORRv16i8
+    0U,	// ORRv2i32
+    0U,	// ORRv4i16
+    0U,	// ORRv4i32
+    0U,	// ORRv8i16
+    1801U,	// ORRv8i8
+    1033U,	// PMULLv16i8
+    0U,	// PMULLv1i64
+    0U,	// PMULLv2i64
+    1801U,	// PMULLv8i8
+    1033U,	// PMULv16i8
+    1801U,	// PMULv8i8
+    0U,	// PRFMl
+    108801U,	// PRFMroW
+    116993U,	// PRFMroX
+    97U,	// PRFMui
+    3585U,	// PRFUMi
+    265U,	// RADDHNv2i64_v2i32
+    273U,	// RADDHNv2i64_v4i32
+    521U,	// RADDHNv4i32_v4i16
+    529U,	// RADDHNv4i32_v8i16
+    785U,	// RADDHNv8i16_v16i8
+    777U,	// RADDHNv8i16_v8i8
+    0U,	// RBITWr
+    0U,	// RBITXr
+    0U,	// RBITv16i8
+    0U,	// RBITv8i8
+    0U,	// RET
+    0U,	// RET_ReallyLR
+    0U,	// REV16Wr
+    0U,	// REV16Xr
+    0U,	// REV16v16i8
+    0U,	// REV16v8i8
+    0U,	// REV32Xr
+    0U,	// REV32v16i8
+    0U,	// REV32v4i16
+    0U,	// REV32v8i16
+    0U,	// REV32v8i8
+    0U,	// REV64v16i8
+    0U,	// REV64v2i32
+    0U,	// REV64v4i16
+    0U,	// REV64v4i32
+    0U,	// REV64v8i16
+    0U,	// REV64v8i8
+    0U,	// REVWr
+    0U,	// REVXr
+    1U,	// RORVWr
+    1U,	// RORVXr
+    65U,	// RSHRNv16i8_shift
+    1U,	// RSHRNv2i32_shift
+    1U,	// RSHRNv4i16_shift
+    65U,	// RSHRNv4i32_shift
+    65U,	// RSHRNv8i16_shift
+    1U,	// RSHRNv8i8_shift
+    265U,	// RSUBHNv2i64_v2i32
+    273U,	// RSUBHNv2i64_v4i32
+    521U,	// RSUBHNv4i32_v4i16
+    529U,	// RSUBHNv4i32_v8i16
+    785U,	// RSUBHNv8i16_v16i8
+    777U,	// RSUBHNv8i16_v8i8
+    1041U,	// SABALv16i8_v8i16
+    1297U,	// SABALv2i32_v2i64
+    1553U,	// SABALv4i16_v4i32
+    529U,	// SABALv4i32_v2i64
+    785U,	// SABALv8i16_v4i32
+    1809U,	// SABALv8i8_v8i16
+    1041U,	// SABAv16i8
+    1297U,	// SABAv2i32
+    1553U,	// SABAv4i16
+    529U,	// SABAv4i32
+    785U,	// SABAv8i16
+    1809U,	// SABAv8i8
+    1033U,	// SABDLv16i8_v8i16
+    1289U,	// SABDLv2i32_v2i64
+    1545U,	// SABDLv4i16_v4i32
+    521U,	// SABDLv4i32_v2i64
+    777U,	// SABDLv8i16_v4i32
+    1801U,	// SABDLv8i8_v8i16
+    1033U,	// SABDv16i8
+    1289U,	// SABDv2i32
+    1545U,	// SABDv4i16
+    521U,	// SABDv4i32
+    777U,	// SABDv8i16
+    1801U,	// SABDv8i8
+    0U,	// SADALPv16i8_v8i16
+    0U,	// SADALPv2i32_v1i64
+    0U,	// SADALPv4i16_v2i32
+    0U,	// SADALPv4i32_v2i64
+    0U,	// SADALPv8i16_v4i32
+    0U,	// SADALPv8i8_v4i16
+    0U,	// SADDLPv16i8_v8i16
+    0U,	// SADDLPv2i32_v1i64
+    0U,	// SADDLPv4i16_v2i32
+    0U,	// SADDLPv4i32_v2i64
+    0U,	// SADDLPv8i16_v4i32
+    0U,	// SADDLPv8i8_v4i16
+    0U,	// SADDLVv16i8v
+    0U,	// SADDLVv4i16v
+    0U,	// SADDLVv4i32v
+    0U,	// SADDLVv8i16v
+    0U,	// SADDLVv8i8v
+    1033U,	// SADDLv16i8_v8i16
+    1289U,	// SADDLv2i32_v2i64
+    1545U,	// SADDLv4i16_v4i32
+    521U,	// SADDLv4i32_v2i64
+    777U,	// SADDLv8i16_v4i32
+    1801U,	// SADDLv8i8_v8i16
+    1033U,	// SADDWv16i8_v8i16
+    1289U,	// SADDWv2i32_v2i64
+    1545U,	// SADDWv4i16_v4i32
+    521U,	// SADDWv4i32_v2i64
+    777U,	// SADDWv8i16_v4i32
+    1801U,	// SADDWv8i8_v8i16
+    1U,	// SBCSWr
+    1U,	// SBCSXr
+    1U,	// SBCWr
+    1U,	// SBCXr
+    18689U,	// SBFMWri
+    18689U,	// SBFMXri
+    1U,	// SCVTFSWDri
+    1U,	// SCVTFSWSri
+    1U,	// SCVTFSXDri
+    1U,	// SCVTFSXSri
+    0U,	// SCVTFUWDri
+    0U,	// SCVTFUWSri
+    0U,	// SCVTFUXDri
+    0U,	// SCVTFUXSri
+    1U,	// SCVTFd
+    1U,	// SCVTFs
+    0U,	// SCVTFv1i32
+    0U,	// SCVTFv1i64
+    0U,	// SCVTFv2f32
+    0U,	// SCVTFv2f64
+    1U,	// SCVTFv2i32_shift
+    1U,	// SCVTFv2i64_shift
+    0U,	// SCVTFv4f32
+    1U,	// SCVTFv4i32_shift
+    1U,	// SDIVWr
+    1U,	// SDIVXr
+    1U,	// SDIV_IntWr
+    1U,	// SDIV_IntXr
+    529U,	// SHA1Crrr
+    0U,	// SHA1Hrr
+    529U,	// SHA1Mrrr
+    529U,	// SHA1Prrr
+    529U,	// SHA1SU0rrr
+    0U,	// SHA1SU1rr
+    529U,	// SHA256H2rrr
+    529U,	// SHA256Hrrr
+    0U,	// SHA256SU0rr
+    529U,	// SHA256SU1rrr
+    1033U,	// SHADDv16i8
+    1289U,	// SHADDv2i32
+    1545U,	// SHADDv4i16
+    521U,	// SHADDv4i32
+    777U,	// SHADDv8i16
+    1801U,	// SHADDv8i8
+    4U,	// SHLLv16i8
+    4U,	// SHLLv2i32
+    4U,	// SHLLv4i16
+    4U,	// SHLLv4i32
+    5U,	// SHLLv8i16
+    5U,	// SHLLv8i8
+    1U,	// SHLd
+    1U,	// SHLv16i8_shift
+    1U,	// SHLv2i32_shift
+    1U,	// SHLv2i64_shift
+    1U,	// SHLv4i16_shift
+    1U,	// SHLv4i32_shift
+    1U,	// SHLv8i16_shift
+    1U,	// SHLv8i8_shift
+    65U,	// SHRNv16i8_shift
+    1U,	// SHRNv2i32_shift
+    1U,	// SHRNv4i16_shift
+    65U,	// SHRNv4i32_shift
+    65U,	// SHRNv8i16_shift
+    1U,	// SHRNv8i8_shift
+    1033U,	// SHSUBv16i8
+    1289U,	// SHSUBv2i32
+    1545U,	// SHSUBv4i16
+    521U,	// SHSUBv4i32
+    777U,	// SHSUBv8i16
+    1801U,	// SHSUBv8i8
+    65U,	// SLId
+    65U,	// SLIv16i8_shift
+    65U,	// SLIv2i32_shift
+    65U,	// SLIv2i64_shift
+    65U,	// SLIv4i16_shift
+    65U,	// SLIv4i32_shift
+    65U,	// SLIv8i16_shift
+    65U,	// SLIv8i8_shift
+    18689U,	// SMADDLrrr
+    1033U,	// SMAXPv16i8
+    1289U,	// SMAXPv2i32
+    1545U,	// SMAXPv4i16
+    521U,	// SMAXPv4i32
+    777U,	// SMAXPv8i16
+    1801U,	// SMAXPv8i8
+    0U,	// SMAXVv16i8v
+    0U,	// SMAXVv4i16v
+    0U,	// SMAXVv4i32v
+    0U,	// SMAXVv8i16v
+    0U,	// SMAXVv8i8v
+    1033U,	// SMAXv16i8
+    1289U,	// SMAXv2i32
+    1545U,	// SMAXv4i16
+    521U,	// SMAXv4i32
+    777U,	// SMAXv8i16
+    1801U,	// SMAXv8i8
+    0U,	// SMC
+    1033U,	// SMINPv16i8
+    1289U,	// SMINPv2i32
+    1545U,	// SMINPv4i16
+    521U,	// SMINPv4i32
+    777U,	// SMINPv8i16
+    1801U,	// SMINPv8i8
+    0U,	// SMINVv16i8v
+    0U,	// SMINVv4i16v
+    0U,	// SMINVv4i32v
+    0U,	// SMINVv8i16v
+    0U,	// SMINVv8i8v
+    1033U,	// SMINv16i8
+    1289U,	// SMINv2i32
+    1545U,	// SMINv4i16
+    521U,	// SMINv4i32
+    777U,	// SMINv8i16
+    1801U,	// SMINv8i8
+    1041U,	// SMLALv16i8_v8i16
+    27665U,	// SMLALv2i32_indexed
+    1297U,	// SMLALv2i32_v2i64
+    28945U,	// SMLALv4i16_indexed
+    1553U,	// SMLALv4i16_v4i32
+    27665U,	// SMLALv4i32_indexed
+    529U,	// SMLALv4i32_v2i64
+    28945U,	// SMLALv8i16_indexed
+    785U,	// SMLALv8i16_v4i32
+    1809U,	// SMLALv8i8_v8i16
+    1041U,	// SMLSLv16i8_v8i16
+    27665U,	// SMLSLv2i32_indexed
+    1297U,	// SMLSLv2i32_v2i64
+    28945U,	// SMLSLv4i16_indexed
+    1553U,	// SMLSLv4i16_v4i32
+    27665U,	// SMLSLv4i32_indexed
+    529U,	// SMLSLv4i32_v2i64
+    28945U,	// SMLSLv8i16_indexed
+    785U,	// SMLSLv8i16_v4i32
+    1809U,	// SMLSLv8i8_v8i16
+    75U,	// SMOVvi16to32
+    75U,	// SMOVvi16to64
+    75U,	// SMOVvi32to64
+    75U,	// SMOVvi8to32
+    75U,	// SMOVvi8to64
+    18689U,	// SMSUBLrrr
+    1U,	// SMULHrr
+    1033U,	// SMULLv16i8_v8i16
+    35849U,	// SMULLv2i32_indexed
+    1289U,	// SMULLv2i32_v2i64
+    37129U,	// SMULLv4i16_indexed
+    1545U,	// SMULLv4i16_v4i32
+    35849U,	// SMULLv4i32_indexed
+    521U,	// SMULLv4i32_v2i64
+    37129U,	// SMULLv8i16_indexed
+    777U,	// SMULLv8i16_v4i32
+    1801U,	// SMULLv8i8_v8i16
+    0U,	// SQABSv16i8
+    0U,	// SQABSv1i16
+    0U,	// SQABSv1i32
+    0U,	// SQABSv1i64
+    0U,	// SQABSv1i8
+    0U,	// SQABSv2i32
+    0U,	// SQABSv2i64
+    0U,	// SQABSv4i16
+    0U,	// SQABSv4i32
+    0U,	// SQABSv8i16
+    0U,	// SQABSv8i8
+    1033U,	// SQADDv16i8
+    1U,	// SQADDv1i16
+    1U,	// SQADDv1i32
+    1U,	// SQADDv1i64
+    1U,	// SQADDv1i8
+    1289U,	// SQADDv2i32
+    265U,	// SQADDv2i64
+    1545U,	// SQADDv4i16
+    521U,	// SQADDv4i32
+    777U,	// SQADDv8i16
+    1801U,	// SQADDv8i8
+    65U,	// SQDMLALi16
+    65U,	// SQDMLALi32
+    28945U,	// SQDMLALv1i32_indexed
+    27665U,	// SQDMLALv1i64_indexed
+    27665U,	// SQDMLALv2i32_indexed
+    1297U,	// SQDMLALv2i32_v2i64
+    28945U,	// SQDMLALv4i16_indexed
+    1553U,	// SQDMLALv4i16_v4i32
+    27665U,	// SQDMLALv4i32_indexed
+    529U,	// SQDMLALv4i32_v2i64
+    28945U,	// SQDMLALv8i16_indexed
+    785U,	// SQDMLALv8i16_v4i32
+    65U,	// SQDMLSLi16
+    65U,	// SQDMLSLi32
+    28945U,	// SQDMLSLv1i32_indexed
+    27665U,	// SQDMLSLv1i64_indexed
+    27665U,	// SQDMLSLv2i32_indexed
+    1297U,	// SQDMLSLv2i32_v2i64
+    28945U,	// SQDMLSLv4i16_indexed
+    1553U,	// SQDMLSLv4i16_v4i32
+    27665U,	// SQDMLSLv4i32_indexed
+    529U,	// SQDMLSLv4i32_v2i64
+    28945U,	// SQDMLSLv8i16_indexed
+    785U,	// SQDMLSLv8i16_v4i32
+    1U,	// SQDMULHv1i16
+    37129U,	// SQDMULHv1i16_indexed
+    1U,	// SQDMULHv1i32
+    35849U,	// SQDMULHv1i32_indexed
+    1289U,	// SQDMULHv2i32
+    35849U,	// SQDMULHv2i32_indexed
+    1545U,	// SQDMULHv4i16
+    37129U,	// SQDMULHv4i16_indexed
+    521U,	// SQDMULHv4i32
+    35849U,	// SQDMULHv4i32_indexed
+    777U,	// SQDMULHv8i16
+    37129U,	// SQDMULHv8i16_indexed
+    1U,	// SQDMULLi16
+    1U,	// SQDMULLi32
+    37129U,	// SQDMULLv1i32_indexed
+    35849U,	// SQDMULLv1i64_indexed
+    35849U,	// SQDMULLv2i32_indexed
+    1289U,	// SQDMULLv2i32_v2i64
+    37129U,	// SQDMULLv4i16_indexed
+    1545U,	// SQDMULLv4i16_v4i32
+    35849U,	// SQDMULLv4i32_indexed
+    521U,	// SQDMULLv4i32_v2i64
+    37129U,	// SQDMULLv8i16_indexed
+    777U,	// SQDMULLv8i16_v4i32
+    0U,	// SQNEGv16i8
+    0U,	// SQNEGv1i16
+    0U,	// SQNEGv1i32
+    0U,	// SQNEGv1i64
+    0U,	// SQNEGv1i8
+    0U,	// SQNEGv2i32
+    0U,	// SQNEGv2i64
+    0U,	// SQNEGv4i16
+    0U,	// SQNEGv4i32
+    0U,	// SQNEGv8i16
+    0U,	// SQNEGv8i8
+    1U,	// SQRDMULHv1i16
+    37129U,	// SQRDMULHv1i16_indexed
+    1U,	// SQRDMULHv1i32
+    35849U,	// SQRDMULHv1i32_indexed
+    1289U,	// SQRDMULHv2i32
+    35849U,	// SQRDMULHv2i32_indexed
+    1545U,	// SQRDMULHv4i16
+    37129U,	// SQRDMULHv4i16_indexed
+    521U,	// SQRDMULHv4i32
+    35849U,	// SQRDMULHv4i32_indexed
+    777U,	// SQRDMULHv8i16
+    37129U,	// SQRDMULHv8i16_indexed
+    1033U,	// SQRSHLv16i8
+    1U,	// SQRSHLv1i16
+    1U,	// SQRSHLv1i32
+    1U,	// SQRSHLv1i64
+    1U,	// SQRSHLv1i8
+    1289U,	// SQRSHLv2i32
+    265U,	// SQRSHLv2i64
+    1545U,	// SQRSHLv4i16
+    521U,	// SQRSHLv4i32
+    777U,	// SQRSHLv8i16
+    1801U,	// SQRSHLv8i8
+    1U,	// SQRSHRNb
+    1U,	// SQRSHRNh
+    1U,	// SQRSHRNs
+    65U,	// SQRSHRNv16i8_shift
+    1U,	// SQRSHRNv2i32_shift
+    1U,	// SQRSHRNv4i16_shift
+    65U,	// SQRSHRNv4i32_shift
+    65U,	// SQRSHRNv8i16_shift
+    1U,	// SQRSHRNv8i8_shift
+    1U,	// SQRSHRUNb
+    1U,	// SQRSHRUNh
+    1U,	// SQRSHRUNs
+    65U,	// SQRSHRUNv16i8_shift
+    1U,	// SQRSHRUNv2i32_shift
+    1U,	// SQRSHRUNv4i16_shift
+    65U,	// SQRSHRUNv4i32_shift
+    65U,	// SQRSHRUNv8i16_shift
+    1U,	// SQRSHRUNv8i8_shift
+    1U,	// SQSHLUb
+    1U,	// SQSHLUd
+    1U,	// SQSHLUh
+    1U,	// SQSHLUs
+    1U,	// SQSHLUv16i8_shift
+    1U,	// SQSHLUv2i32_shift
+    1U,	// SQSHLUv2i64_shift
+    1U,	// SQSHLUv4i16_shift
+    1U,	// SQSHLUv4i32_shift
+    1U,	// SQSHLUv8i16_shift
+    1U,	// SQSHLUv8i8_shift
+    1U,	// SQSHLb
+    1U,	// SQSHLd
+    1U,	// SQSHLh
+    1U,	// SQSHLs
+    1033U,	// SQSHLv16i8
+    1U,	// SQSHLv16i8_shift
+    1U,	// SQSHLv1i16
+    1U,	// SQSHLv1i32
+    1U,	// SQSHLv1i64
+    1U,	// SQSHLv1i8
+    1289U,	// SQSHLv2i32
+    1U,	// SQSHLv2i32_shift
+    265U,	// SQSHLv2i64
+    1U,	// SQSHLv2i64_shift
+    1545U,	// SQSHLv4i16
+    1U,	// SQSHLv4i16_shift
+    521U,	// SQSHLv4i32
+    1U,	// SQSHLv4i32_shift
+    777U,	// SQSHLv8i16
+    1U,	// SQSHLv8i16_shift
+    1801U,	// SQSHLv8i8
+    1U,	// SQSHLv8i8_shift
+    1U,	// SQSHRNb
+    1U,	// SQSHRNh
+    1U,	// SQSHRNs
+    65U,	// SQSHRNv16i8_shift
+    1U,	// SQSHRNv2i32_shift
+    1U,	// SQSHRNv4i16_shift
+    65U,	// SQSHRNv4i32_shift
+    65U,	// SQSHRNv8i16_shift
+    1U,	// SQSHRNv8i8_shift
+    1U,	// SQSHRUNb
+    1U,	// SQSHRUNh
+    1U,	// SQSHRUNs
+    65U,	// SQSHRUNv16i8_shift
+    1U,	// SQSHRUNv2i32_shift
+    1U,	// SQSHRUNv4i16_shift
+    65U,	// SQSHRUNv4i32_shift
+    65U,	// SQSHRUNv8i16_shift
+    1U,	// SQSHRUNv8i8_shift
+    1033U,	// SQSUBv16i8
+    1U,	// SQSUBv1i16
+    1U,	// SQSUBv1i32
+    1U,	// SQSUBv1i64
+    1U,	// SQSUBv1i8
+    1289U,	// SQSUBv2i32
+    265U,	// SQSUBv2i64
+    1545U,	// SQSUBv4i16
+    521U,	// SQSUBv4i32
+    777U,	// SQSUBv8i16
+    1801U,	// SQSUBv8i8
+    0U,	// SQXTNv16i8
+    0U,	// SQXTNv1i16
+    0U,	// SQXTNv1i32
+    0U,	// SQXTNv1i8
+    0U,	// SQXTNv2i32
+    0U,	// SQXTNv4i16
+    0U,	// SQXTNv4i32
+    0U,	// SQXTNv8i16
+    0U,	// SQXTNv8i8
+    0U,	// SQXTUNv16i8
+    0U,	// SQXTUNv1i16
+    0U,	// SQXTUNv1i32
+    0U,	// SQXTUNv1i8
+    0U,	// SQXTUNv2i32
+    0U,	// SQXTUNv4i16
+    0U,	// SQXTUNv4i32
+    0U,	// SQXTUNv8i16
+    0U,	// SQXTUNv8i8
+    1033U,	// SRHADDv16i8
+    1289U,	// SRHADDv2i32
+    1545U,	// SRHADDv4i16
+    521U,	// SRHADDv4i32
+    777U,	// SRHADDv8i16
+    1801U,	// SRHADDv8i8
+    65U,	// SRId
+    65U,	// SRIv16i8_shift
+    65U,	// SRIv2i32_shift
+    65U,	// SRIv2i64_shift
+    65U,	// SRIv4i16_shift
+    65U,	// SRIv4i32_shift
+    65U,	// SRIv8i16_shift
+    65U,	// SRIv8i8_shift
+    1033U,	// SRSHLv16i8
+    1U,	// SRSHLv1i64
+    1289U,	// SRSHLv2i32
+    265U,	// SRSHLv2i64
+    1545U,	// SRSHLv4i16
+    521U,	// SRSHLv4i32
+    777U,	// SRSHLv8i16
+    1801U,	// SRSHLv8i8
+    1U,	// SRSHRd
+    1U,	// SRSHRv16i8_shift
+    1U,	// SRSHRv2i32_shift
+    1U,	// SRSHRv2i64_shift
+    1U,	// SRSHRv4i16_shift
+    1U,	// SRSHRv4i32_shift
+    1U,	// SRSHRv8i16_shift
+    1U,	// SRSHRv8i8_shift
+    65U,	// SRSRAd
+    65U,	// SRSRAv16i8_shift
+    65U,	// SRSRAv2i32_shift
+    65U,	// SRSRAv2i64_shift
+    65U,	// SRSRAv4i16_shift
+    65U,	// SRSRAv4i32_shift
+    65U,	// SRSRAv8i16_shift
+    65U,	// SRSRAv8i8_shift
+    1U,	// SSHLLv16i8_shift
+    1U,	// SSHLLv2i32_shift
+    1U,	// SSHLLv4i16_shift
+    1U,	// SSHLLv4i32_shift
+    1U,	// SSHLLv8i16_shift
+    1U,	// SSHLLv8i8_shift
+    1033U,	// SSHLv16i8
+    1U,	// SSHLv1i64
+    1289U,	// SSHLv2i32
+    265U,	// SSHLv2i64
+    1545U,	// SSHLv4i16
+    521U,	// SSHLv4i32
+    777U,	// SSHLv8i16
+    1801U,	// SSHLv8i8
+    1U,	// SSHRd
+    1U,	// SSHRv16i8_shift
+    1U,	// SSHRv2i32_shift
+    1U,	// SSHRv2i64_shift
+    1U,	// SSHRv4i16_shift
+    1U,	// SSHRv4i32_shift
+    1U,	// SSHRv8i16_shift
+    1U,	// SSHRv8i8_shift
+    65U,	// SSRAd
+    65U,	// SSRAv16i8_shift
+    65U,	// SSRAv2i32_shift
+    65U,	// SSRAv2i64_shift
+    65U,	// SSRAv4i16_shift
+    65U,	// SSRAv4i32_shift
+    65U,	// SSRAv8i16_shift
+    65U,	// SSRAv8i8_shift
+    1033U,	// SSUBLv16i8_v8i16
+    1289U,	// SSUBLv2i32_v2i64
+    1545U,	// SSUBLv4i16_v4i32
+    521U,	// SSUBLv4i32_v2i64
+    777U,	// SSUBLv8i16_v4i32
+    1801U,	// SSUBLv8i8_v8i16
+    1033U,	// SSUBWv16i8_v8i16
+    1289U,	// SSUBWv2i32_v2i64
+    1545U,	// SSUBWv4i16_v4i32
+    521U,	// SSUBWv4i32_v2i64
+    777U,	// SSUBWv8i16_v4i32
+    1801U,	// SSUBWv8i8_v8i16
+    0U,	// ST1Fourv16b
+    0U,	// ST1Fourv16b_POST
+    0U,	// ST1Fourv1d
+    0U,	// ST1Fourv1d_POST
+    0U,	// ST1Fourv2d
+    0U,	// ST1Fourv2d_POST
+    0U,	// ST1Fourv2s
+    0U,	// ST1Fourv2s_POST
+    0U,	// ST1Fourv4h
+    0U,	// ST1Fourv4h_POST
+    0U,	// ST1Fourv4s
+    0U,	// ST1Fourv4s_POST
+    0U,	// ST1Fourv8b
+    0U,	// ST1Fourv8b_POST
+    0U,	// ST1Fourv8h
+    0U,	// ST1Fourv8h_POST
+    0U,	// ST1Onev16b
+    0U,	// ST1Onev16b_POST
+    0U,	// ST1Onev1d
+    0U,	// ST1Onev1d_POST
+    0U,	// ST1Onev2d
+    0U,	// ST1Onev2d_POST
+    0U,	// ST1Onev2s
+    0U,	// ST1Onev2s_POST
+    0U,	// ST1Onev4h
+    0U,	// ST1Onev4h_POST
+    0U,	// ST1Onev4s
+    0U,	// ST1Onev4s_POST
+    0U,	// ST1Onev8b
+    0U,	// ST1Onev8b_POST
+    0U,	// ST1Onev8h
+    0U,	// ST1Onev8h_POST
+    0U,	// ST1Threev16b
+    0U,	// ST1Threev16b_POST
+    0U,	// ST1Threev1d
+    0U,	// ST1Threev1d_POST
+    0U,	// ST1Threev2d
+    0U,	// ST1Threev2d_POST
+    0U,	// ST1Threev2s
+    0U,	// ST1Threev2s_POST
+    0U,	// ST1Threev4h
+    0U,	// ST1Threev4h_POST
+    0U,	// ST1Threev4s
+    0U,	// ST1Threev4s_POST
+    0U,	// ST1Threev8b
+    0U,	// ST1Threev8b_POST
+    0U,	// ST1Threev8h
+    0U,	// ST1Threev8h_POST
+    0U,	// ST1Twov16b
+    0U,	// ST1Twov16b_POST
+    0U,	// ST1Twov1d
+    0U,	// ST1Twov1d_POST
+    0U,	// ST1Twov2d
+    0U,	// ST1Twov2d_POST
+    0U,	// ST1Twov2s
+    0U,	// ST1Twov2s_POST
+    0U,	// ST1Twov4h
+    0U,	// ST1Twov4h_POST
+    0U,	// ST1Twov4s
+    0U,	// ST1Twov4s_POST
+    0U,	// ST1Twov8b
+    0U,	// ST1Twov8b_POST
+    0U,	// ST1Twov8h
+    0U,	// ST1Twov8h_POST
+    0U,	// ST1i16
+    0U,	// ST1i16_POST
+    0U,	// ST1i32
+    0U,	// ST1i32_POST
+    0U,	// ST1i64
+    0U,	// ST1i64_POST
+    0U,	// ST1i8
+    0U,	// ST1i8_POST
+    0U,	// ST2Twov16b
+    0U,	// ST2Twov16b_POST
+    0U,	// ST2Twov2d
+    0U,	// ST2Twov2d_POST
+    0U,	// ST2Twov2s
+    0U,	// ST2Twov2s_POST
+    0U,	// ST2Twov4h
+    0U,	// ST2Twov4h_POST
+    0U,	// ST2Twov4s
+    0U,	// ST2Twov4s_POST
+    0U,	// ST2Twov8b
+    0U,	// ST2Twov8b_POST
+    0U,	// ST2Twov8h
+    0U,	// ST2Twov8h_POST
+    0U,	// ST2i16
+    0U,	// ST2i16_POST
+    0U,	// ST2i32
+    0U,	// ST2i32_POST
+    0U,	// ST2i64
+    0U,	// ST2i64_POST
+    0U,	// ST2i8
+    0U,	// ST2i8_POST
+    0U,	// ST3Threev16b
+    0U,	// ST3Threev16b_POST
+    0U,	// ST3Threev2d
+    0U,	// ST3Threev2d_POST
+    0U,	// ST3Threev2s
+    0U,	// ST3Threev2s_POST
+    0U,	// ST3Threev4h
+    0U,	// ST3Threev4h_POST
+    0U,	// ST3Threev4s
+    0U,	// ST3Threev4s_POST
+    0U,	// ST3Threev8b
+    0U,	// ST3Threev8b_POST
+    0U,	// ST3Threev8h
+    0U,	// ST3Threev8h_POST
+    0U,	// ST3i16
+    0U,	// ST3i16_POST
+    0U,	// ST3i32
+    0U,	// ST3i32_POST
+    0U,	// ST3i64
+    0U,	// ST3i64_POST
+    0U,	// ST3i8
+    0U,	// ST3i8_POST
+    0U,	// ST4Fourv16b
+    0U,	// ST4Fourv16b_POST
+    0U,	// ST4Fourv2d
+    0U,	// ST4Fourv2d_POST
+    0U,	// ST4Fourv2s
+    0U,	// ST4Fourv2s_POST
+    0U,	// ST4Fourv4h
+    0U,	// ST4Fourv4h_POST
+    0U,	// ST4Fourv4s
+    0U,	// ST4Fourv4s_POST
+    0U,	// ST4Fourv8b
+    0U,	// ST4Fourv8b_POST
+    0U,	// ST4Fourv8h
+    0U,	// ST4Fourv8h_POST
+    0U,	// ST4i16
+    0U,	// ST4i16_POST
+    0U,	// ST4i32
+    0U,	// ST4i32_POST
+    0U,	// ST4i64
+    0U,	// ST4i64_POST
+    0U,	// ST4i8
+    0U,	// ST4i8_POST
+    4U,	// STLRB
+    4U,	// STLRH
+    4U,	// STLRW
+    4U,	// STLRX
+    4609U,	// STLXPW
+    4609U,	// STLXPX
+    3588U,	// STLXRB
+    3588U,	// STLXRH
+    3588U,	// STLXRW
+    3588U,	// STLXRX
+    43268U,	// STNPDi
+    51460U,	// STNPQi
+    59652U,	// STNPSi
+    59652U,	// STNPWi
+    43268U,	// STNPXi
+    43268U,	// STPDi
+    69444U,	// STPDpost
+    330052U,	// STPDpre
+    51460U,	// STPQi
+    77636U,	// STPQpost
+    338244U,	// STPQpre
+    59652U,	// STPSi
+    85828U,	// STPSpost
+    346436U,	// STPSpre
+    59652U,	// STPWi
+    85828U,	// STPWpost
+    346436U,	// STPWpre
+    43268U,	// STPXi
+    69444U,	// STPXpost
+    330052U,	// STPXpre
+    4U,	// STRBBpost
+    4161U,	// STRBBpre
+    92417U,	// STRBBroW
+    100609U,	// STRBBroX
+    89U,	// STRBBui
+    4U,	// STRBpost
+    4161U,	// STRBpre
+    92417U,	// STRBroW
+    100609U,	// STRBroX
+    89U,	// STRBui
+    4U,	// STRDpost
+    4161U,	// STRDpre
+    108801U,	// STRDroW
+    116993U,	// STRDroX
+    97U,	// STRDui
+    4U,	// STRHHpost
+    4161U,	// STRHHpre
+    125185U,	// STRHHroW
+    133377U,	// STRHHroX
+    105U,	// STRHHui
+    4U,	// STRHpost
+    4161U,	// STRHpre
+    125185U,	// STRHroW
+    133377U,	// STRHroX
+    105U,	// STRHui
+    4U,	// STRQpost
+    4161U,	// STRQpre
+    141569U,	// STRQroW
+    149761U,	// STRQroX
+    113U,	// STRQui
+    4U,	// STRSpost
+    4161U,	// STRSpre
+    157953U,	// STRSroW
+    166145U,	// STRSroX
+    121U,	// STRSui
+    4U,	// STRWpost
+    4161U,	// STRWpre
+    157953U,	// STRWroW
+    166145U,	// STRWroX
+    121U,	// STRWui
+    4U,	// STRXpost
+    4161U,	// STRXpre
+    108801U,	// STRXroW
+    116993U,	// STRXroX
+    97U,	// STRXui
+    3585U,	// STTRBi
+    3585U,	// STTRHi
+    3585U,	// STTRWi
+    3585U,	// STTRXi
+    3585U,	// STURBBi
+    3585U,	// STURBi
+    3585U,	// STURDi
+    3585U,	// STURHHi
+    3585U,	// STURHi
+    3585U,	// STURQi
+    3585U,	// STURSi
+    3585U,	// STURWi
+    3585U,	// STURXi
+    4609U,	// STXPW
+    4609U,	// STXPX
+    3588U,	// STXRB
+    3588U,	// STXRH
+    3588U,	// STXRW
+    3588U,	// STXRX
+    265U,	// SUBHNv2i64_v2i32
+    273U,	// SUBHNv2i64_v4i32
+    521U,	// SUBHNv4i32_v4i16
+    529U,	// SUBHNv4i32_v8i16
+    785U,	// SUBHNv8i16_v16i8
+    777U,	// SUBHNv8i16_v8i8
+    25U,	// SUBSWri
+    0U,	// SUBSWrr
+    33U,	// SUBSWrs
+    41U,	// SUBSWrx
+    25U,	// SUBSXri
+    0U,	// SUBSXrr
+    33U,	// SUBSXrs
+    41U,	// SUBSXrx
+    2049U,	// SUBSXrx64
+    25U,	// SUBWri
+    0U,	// SUBWrr
+    33U,	// SUBWrs
+    41U,	// SUBWrx
+    25U,	// SUBXri
+    0U,	// SUBXrr
+    33U,	// SUBXrs
+    41U,	// SUBXrx
+    2049U,	// SUBXrx64
+    1033U,	// SUBv16i8
+    1U,	// SUBv1i64
+    1289U,	// SUBv2i32
+    265U,	// SUBv2i64
+    1545U,	// SUBv4i16
+    521U,	// SUBv4i32
+    777U,	// SUBv8i16
+    1801U,	// SUBv8i8
+    0U,	// SUQADDv16i8
+    0U,	// SUQADDv1i16
+    0U,	// SUQADDv1i32
+    0U,	// SUQADDv1i64
+    0U,	// SUQADDv1i8
+    0U,	// SUQADDv2i32
+    0U,	// SUQADDv2i64
+    0U,	// SUQADDv4i16
+    0U,	// SUQADDv4i32
+    0U,	// SUQADDv8i16
+    0U,	// SUQADDv8i8
+    0U,	// SVC
+    129U,	// SYSLxt
+    0U,	// SYSxt
+    0U,	// TBLv16i8Four
+    0U,	// TBLv16i8One
+    0U,	// TBLv16i8Three
+    0U,	// TBLv16i8Two
+    0U,	// TBLv8i8Four
+    0U,	// TBLv8i8One
+    0U,	// TBLv8i8Three
+    0U,	// TBLv8i8Two
+    137U,	// TBNZW
+    137U,	// TBNZX
+    0U,	// TBXv16i8Four
+    0U,	// TBXv16i8One
+    0U,	// TBXv16i8Three
+    0U,	// TBXv16i8Two
+    0U,	// TBXv8i8Four
+    0U,	// TBXv8i8One
+    0U,	// TBXv8i8Three
+    0U,	// TBXv8i8Two
+    137U,	// TBZW
+    137U,	// TBZX
+    0U,	// TCRETURNdi
+    0U,	// TCRETURNri
+    0U,	// TLSDESCCALL
+    0U,	// TLSDESC_BLR
+    1033U,	// TRN1v16i8
+    1289U,	// TRN1v2i32
+    265U,	// TRN1v2i64
+    1545U,	// TRN1v4i16
+    521U,	// TRN1v4i32
+    777U,	// TRN1v8i16
+    1801U,	// TRN1v8i8
+    1033U,	// TRN2v16i8
+    1289U,	// TRN2v2i32
+    265U,	// TRN2v2i64
+    1545U,	// TRN2v4i16
+    521U,	// TRN2v4i32
+    777U,	// TRN2v8i16
+    1801U,	// TRN2v8i8
+    1041U,	// UABALv16i8_v8i16
+    1297U,	// UABALv2i32_v2i64
+    1553U,	// UABALv4i16_v4i32
+    529U,	// UABALv4i32_v2i64
+    785U,	// UABALv8i16_v4i32
+    1809U,	// UABALv8i8_v8i16
+    1041U,	// UABAv16i8
+    1297U,	// UABAv2i32
+    1553U,	// UABAv4i16
+    529U,	// UABAv4i32
+    785U,	// UABAv8i16
+    1809U,	// UABAv8i8
+    1033U,	// UABDLv16i8_v8i16
+    1289U,	// UABDLv2i32_v2i64
+    1545U,	// UABDLv4i16_v4i32
+    521U,	// UABDLv4i32_v2i64
+    777U,	// UABDLv8i16_v4i32
+    1801U,	// UABDLv8i8_v8i16
+    1033U,	// UABDv16i8
+    1289U,	// UABDv2i32
+    1545U,	// UABDv4i16
+    521U,	// UABDv4i32
+    777U,	// UABDv8i16
+    1801U,	// UABDv8i8
+    0U,	// UADALPv16i8_v8i16
+    0U,	// UADALPv2i32_v1i64
+    0U,	// UADALPv4i16_v2i32
+    0U,	// UADALPv4i32_v2i64
+    0U,	// UADALPv8i16_v4i32
+    0U,	// UADALPv8i8_v4i16
+    0U,	// UADDLPv16i8_v8i16
+    0U,	// UADDLPv2i32_v1i64
+    0U,	// UADDLPv4i16_v2i32
+    0U,	// UADDLPv4i32_v2i64
+    0U,	// UADDLPv8i16_v4i32
+    0U,	// UADDLPv8i8_v4i16
+    0U,	// UADDLVv16i8v
+    0U,	// UADDLVv4i16v
+    0U,	// UADDLVv4i32v
+    0U,	// UADDLVv8i16v
+    0U,	// UADDLVv8i8v
+    1033U,	// UADDLv16i8_v8i16
+    1289U,	// UADDLv2i32_v2i64
+    1545U,	// UADDLv4i16_v4i32
+    521U,	// UADDLv4i32_v2i64
+    777U,	// UADDLv8i16_v4i32
+    1801U,	// UADDLv8i8_v8i16
+    1033U,	// UADDWv16i8_v8i16
+    1289U,	// UADDWv2i32_v2i64
+    1545U,	// UADDWv4i16_v4i32
+    521U,	// UADDWv4i32_v2i64
+    777U,	// UADDWv8i16_v4i32
+    1801U,	// UADDWv8i8_v8i16
+    18689U,	// UBFMWri
+    18689U,	// UBFMXri
+    1U,	// UCVTFSWDri
+    1U,	// UCVTFSWSri
+    1U,	// UCVTFSXDri
+    1U,	// UCVTFSXSri
+    0U,	// UCVTFUWDri
+    0U,	// UCVTFUWSri
+    0U,	// UCVTFUXDri
+    0U,	// UCVTFUXSri
+    1U,	// UCVTFd
+    1U,	// UCVTFs
+    0U,	// UCVTFv1i32
+    0U,	// UCVTFv1i64
+    0U,	// UCVTFv2f32
+    0U,	// UCVTFv2f64
+    1U,	// UCVTFv2i32_shift
+    1U,	// UCVTFv2i64_shift
+    0U,	// UCVTFv4f32
+    1U,	// UCVTFv4i32_shift
+    1U,	// UDIVWr
+    1U,	// UDIVXr
+    1U,	// UDIV_IntWr
+    1U,	// UDIV_IntXr
+    1033U,	// UHADDv16i8
+    1289U,	// UHADDv2i32
+    1545U,	// UHADDv4i16
+    521U,	// UHADDv4i32
+    777U,	// UHADDv8i16
+    1801U,	// UHADDv8i8
+    1033U,	// UHSUBv16i8
+    1289U,	// UHSUBv2i32
+    1545U,	// UHSUBv4i16
+    521U,	// UHSUBv4i32
+    777U,	// UHSUBv8i16
+    1801U,	// UHSUBv8i8
+    18689U,	// UMADDLrrr
+    1033U,	// UMAXPv16i8
+    1289U,	// UMAXPv2i32
+    1545U,	// UMAXPv4i16
+    521U,	// UMAXPv4i32
+    777U,	// UMAXPv8i16
+    1801U,	// UMAXPv8i8
+    0U,	// UMAXVv16i8v
+    0U,	// UMAXVv4i16v
+    0U,	// UMAXVv4i32v
+    0U,	// UMAXVv8i16v
+    0U,	// UMAXVv8i8v
+    1033U,	// UMAXv16i8
+    1289U,	// UMAXv2i32
+    1545U,	// UMAXv4i16
+    521U,	// UMAXv4i32
+    777U,	// UMAXv8i16
+    1801U,	// UMAXv8i8
+    1033U,	// UMINPv16i8
+    1289U,	// UMINPv2i32
+    1545U,	// UMINPv4i16
+    521U,	// UMINPv4i32
+    777U,	// UMINPv8i16
+    1801U,	// UMINPv8i8
+    0U,	// UMINVv16i8v
+    0U,	// UMINVv4i16v
+    0U,	// UMINVv4i32v
+    0U,	// UMINVv8i16v
+    0U,	// UMINVv8i8v
+    1033U,	// UMINv16i8
+    1289U,	// UMINv2i32
+    1545U,	// UMINv4i16
+    521U,	// UMINv4i32
+    777U,	// UMINv8i16
+    1801U,	// UMINv8i8
+    1041U,	// UMLALv16i8_v8i16
+    27665U,	// UMLALv2i32_indexed
+    1297U,	// UMLALv2i32_v2i64
+    28945U,	// UMLALv4i16_indexed
+    1553U,	// UMLALv4i16_v4i32
+    27665U,	// UMLALv4i32_indexed
+    529U,	// UMLALv4i32_v2i64
+    28945U,	// UMLALv8i16_indexed
+    785U,	// UMLALv8i16_v4i32
+    1809U,	// UMLALv8i8_v8i16
+    1041U,	// UMLSLv16i8_v8i16
+    27665U,	// UMLSLv2i32_indexed
+    1297U,	// UMLSLv2i32_v2i64
+    28945U,	// UMLSLv4i16_indexed
+    1553U,	// UMLSLv4i16_v4i32
+    27665U,	// UMLSLv4i32_indexed
+    529U,	// UMLSLv4i32_v2i64
+    28945U,	// UMLSLv8i16_indexed
+    785U,	// UMLSLv8i16_v4i32
+    1809U,	// UMLSLv8i8_v8i16
+    75U,	// UMOVvi16
+    75U,	// UMOVvi32
+    75U,	// UMOVvi64
+    75U,	// UMOVvi8
+    18689U,	// UMSUBLrrr
+    1U,	// UMULHrr
+    1033U,	// UMULLv16i8_v8i16
+    35849U,	// UMULLv2i32_indexed
+    1289U,	// UMULLv2i32_v2i64
+    37129U,	// UMULLv4i16_indexed
+    1545U,	// UMULLv4i16_v4i32
+    35849U,	// UMULLv4i32_indexed
+    521U,	// UMULLv4i32_v2i64
+    37129U,	// UMULLv8i16_indexed
+    777U,	// UMULLv8i16_v4i32
+    1801U,	// UMULLv8i8_v8i16
+    1033U,	// UQADDv16i8
+    1U,	// UQADDv1i16
+    1U,	// UQADDv1i32
+    1U,	// UQADDv1i64
+    1U,	// UQADDv1i8
+    1289U,	// UQADDv2i32
+    265U,	// UQADDv2i64
+    1545U,	// UQADDv4i16
+    521U,	// UQADDv4i32
+    777U,	// UQADDv8i16
+    1801U,	// UQADDv8i8
+    1033U,	// UQRSHLv16i8
+    1U,	// UQRSHLv1i16
+    1U,	// UQRSHLv1i32
+    1U,	// UQRSHLv1i64
+    1U,	// UQRSHLv1i8
+    1289U,	// UQRSHLv2i32
+    265U,	// UQRSHLv2i64
+    1545U,	// UQRSHLv4i16
+    521U,	// UQRSHLv4i32
+    777U,	// UQRSHLv8i16
+    1801U,	// UQRSHLv8i8
+    1U,	// UQRSHRNb
+    1U,	// UQRSHRNh
+    1U,	// UQRSHRNs
+    65U,	// UQRSHRNv16i8_shift
+    1U,	// UQRSHRNv2i32_shift
+    1U,	// UQRSHRNv4i16_shift
+    65U,	// UQRSHRNv4i32_shift
+    65U,	// UQRSHRNv8i16_shift
+    1U,	// UQRSHRNv8i8_shift
+    1U,	// UQSHLb
+    1U,	// UQSHLd
+    1U,	// UQSHLh
+    1U,	// UQSHLs
+    1033U,	// UQSHLv16i8
+    1U,	// UQSHLv16i8_shift
+    1U,	// UQSHLv1i16
+    1U,	// UQSHLv1i32
+    1U,	// UQSHLv1i64
+    1U,	// UQSHLv1i8
+    1289U,	// UQSHLv2i32
+    1U,	// UQSHLv2i32_shift
+    265U,	// UQSHLv2i64
+    1U,	// UQSHLv2i64_shift
+    1545U,	// UQSHLv4i16
+    1U,	// UQSHLv4i16_shift
+    521U,	// UQSHLv4i32
+    1U,	// UQSHLv4i32_shift
+    777U,	// UQSHLv8i16
+    1U,	// UQSHLv8i16_shift
+    1801U,	// UQSHLv8i8
+    1U,	// UQSHLv8i8_shift
+    1U,	// UQSHRNb
+    1U,	// UQSHRNh
+    1U,	// UQSHRNs
+    65U,	// UQSHRNv16i8_shift
+    1U,	// UQSHRNv2i32_shift
+    1U,	// UQSHRNv4i16_shift
+    65U,	// UQSHRNv4i32_shift
+    65U,	// UQSHRNv8i16_shift
+    1U,	// UQSHRNv8i8_shift
+    1033U,	// UQSUBv16i8
+    1U,	// UQSUBv1i16
+    1U,	// UQSUBv1i32
+    1U,	// UQSUBv1i64
+    1U,	// UQSUBv1i8
+    1289U,	// UQSUBv2i32
+    265U,	// UQSUBv2i64
+    1545U,	// UQSUBv4i16
+    521U,	// UQSUBv4i32
+    777U,	// UQSUBv8i16
+    1801U,	// UQSUBv8i8
+    0U,	// UQXTNv16i8
+    0U,	// UQXTNv1i16
+    0U,	// UQXTNv1i32
+    0U,	// UQXTNv1i8
+    0U,	// UQXTNv2i32
+    0U,	// UQXTNv4i16
+    0U,	// UQXTNv4i32
+    0U,	// UQXTNv8i16
+    0U,	// UQXTNv8i8
+    0U,	// URECPEv2i32
+    0U,	// URECPEv4i32
+    1033U,	// URHADDv16i8
+    1289U,	// URHADDv2i32
+    1545U,	// URHADDv4i16
+    521U,	// URHADDv4i32
+    777U,	// URHADDv8i16
+    1801U,	// URHADDv8i8
+    1033U,	// URSHLv16i8
+    1U,	// URSHLv1i64
+    1289U,	// URSHLv2i32
+    265U,	// URSHLv2i64
+    1545U,	// URSHLv4i16
+    521U,	// URSHLv4i32
+    777U,	// URSHLv8i16
+    1801U,	// URSHLv8i8
+    1U,	// URSHRd
+    1U,	// URSHRv16i8_shift
+    1U,	// URSHRv2i32_shift
+    1U,	// URSHRv2i64_shift
+    1U,	// URSHRv4i16_shift
+    1U,	// URSHRv4i32_shift
+    1U,	// URSHRv8i16_shift
+    1U,	// URSHRv8i8_shift
+    0U,	// URSQRTEv2i32
+    0U,	// URSQRTEv4i32
+    65U,	// URSRAd
+    65U,	// URSRAv16i8_shift
+    65U,	// URSRAv2i32_shift
+    65U,	// URSRAv2i64_shift
+    65U,	// URSRAv4i16_shift
+    65U,	// URSRAv4i32_shift
+    65U,	// URSRAv8i16_shift
+    65U,	// URSRAv8i8_shift
+    1U,	// USHLLv16i8_shift
+    1U,	// USHLLv2i32_shift
+    1U,	// USHLLv4i16_shift
+    1U,	// USHLLv4i32_shift
+    1U,	// USHLLv8i16_shift
+    1U,	// USHLLv8i8_shift
+    1033U,	// USHLv16i8
+    1U,	// USHLv1i64
+    1289U,	// USHLv2i32
+    265U,	// USHLv2i64
+    1545U,	// USHLv4i16
+    521U,	// USHLv4i32
+    777U,	// USHLv8i16
+    1801U,	// USHLv8i8
+    1U,	// USHRd
+    1U,	// USHRv16i8_shift
+    1U,	// USHRv2i32_shift
+    1U,	// USHRv2i64_shift
+    1U,	// USHRv4i16_shift
+    1U,	// USHRv4i32_shift
+    1U,	// USHRv8i16_shift
+    1U,	// USHRv8i8_shift
+    0U,	// USQADDv16i8
+    0U,	// USQADDv1i16
+    0U,	// USQADDv1i32
+    0U,	// USQADDv1i64
+    0U,	// USQADDv1i8
+    0U,	// USQADDv2i32
+    0U,	// USQADDv2i64
+    0U,	// USQADDv4i16
+    0U,	// USQADDv4i32
+    0U,	// USQADDv8i16
+    0U,	// USQADDv8i8
+    65U,	// USRAd
+    65U,	// USRAv16i8_shift
+    65U,	// USRAv2i32_shift
+    65U,	// USRAv2i64_shift
+    65U,	// USRAv4i16_shift
+    65U,	// USRAv4i32_shift
+    65U,	// USRAv8i16_shift
+    65U,	// USRAv8i8_shift
+    1033U,	// USUBLv16i8_v8i16
+    1289U,	// USUBLv2i32_v2i64
+    1545U,	// USUBLv4i16_v4i32
+    521U,	// USUBLv4i32_v2i64
+    777U,	// USUBLv8i16_v4i32
+    1801U,	// USUBLv8i8_v8i16
+    1033U,	// USUBWv16i8_v8i16
+    1289U,	// USUBWv2i32_v2i64
+    1545U,	// USUBWv4i16_v4i32
+    521U,	// USUBWv4i32_v2i64
+    777U,	// USUBWv8i16_v4i32
+    1801U,	// USUBWv8i8_v8i16
+    1033U,	// UZP1v16i8
+    1289U,	// UZP1v2i32
+    265U,	// UZP1v2i64
+    1545U,	// UZP1v4i16
+    521U,	// UZP1v4i32
+    777U,	// UZP1v8i16
+    1801U,	// UZP1v8i8
+    1033U,	// UZP2v16i8
+    1289U,	// UZP2v2i32
+    265U,	// UZP2v2i64
+    1545U,	// UZP2v4i16
+    521U,	// UZP2v4i32
+    777U,	// UZP2v8i16
+    1801U,	// UZP2v8i8
+    0U,	// XTNv16i8
+    0U,	// XTNv2i32
+    0U,	// XTNv4i16
+    0U,	// XTNv4i32
+    0U,	// XTNv8i16
+    0U,	// XTNv8i8
+    1033U,	// ZIP1v16i8
+    1289U,	// ZIP1v2i32
+    265U,	// ZIP1v2i64
+    1545U,	// ZIP1v4i16
+    521U,	// ZIP1v4i32
+    777U,	// ZIP1v8i16
+    1801U,	// ZIP1v8i8
+    1033U,	// ZIP2v16i8
+    1289U,	// ZIP2v2i32
+    265U,	// ZIP2v2i64
+    1545U,	// ZIP2v4i16
+    521U,	// ZIP2v4i32
+    777U,	// ZIP2v8i16
+    1801U,	// ZIP2v8i8
+    0U
+  };
+
+#ifndef CAPSTONE_DIET
+  static char AsmStrs[] = {
+  /* 0 */ 's', 'h', 'a', '1', 's', 'u', '0', 9, 0,
+  /* 9 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '0', 9, 0,
+  /* 20 */ 'l', 'd', '1', 9, 0,
+  /* 25 */ 't', 'r', 'n', '1', 9, 0,
+  /* 31 */ 'z', 'i', 'p', '1', 9, 0,
+  /* 37 */ 'u', 'z', 'p', '1', 9, 0,
+  /* 43 */ 'd', 'c', 'p', 's', '1', 9, 0,
+  /* 50 */ 's', 't', '1', 9, 0,
+  /* 55 */ 's', 'h', 'a', '1', 's', 'u', '1', 9, 0,
+  /* 64 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '1', 9, 0,
+  /* 75 */ 'r', 'e', 'v', '3', '2', 9, 0,
+  /* 82 */ 'l', 'd', '2', 9, 0,
+  /* 87 */ 's', 'h', 'a', '2', '5', '6', 'h', '2', 9, 0,
+  /* 97 */ 's', 'a', 'b', 'a', 'l', '2', 9, 0,
+  /* 105 */ 'u', 'a', 'b', 'a', 'l', '2', 9, 0,
+  /* 113 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', '2', 9, 0,
+  /* 123 */ 's', 'm', 'l', 'a', 'l', '2', 9, 0,
+  /* 131 */ 'u', 'm', 'l', 'a', 'l', '2', 9, 0,
+  /* 139 */ 's', 's', 'u', 'b', 'l', '2', 9, 0,
+  /* 147 */ 'u', 's', 'u', 'b', 'l', '2', 9, 0,
+  /* 155 */ 's', 'a', 'b', 'd', 'l', '2', 9, 0,
+  /* 163 */ 'u', 'a', 'b', 'd', 'l', '2', 9, 0,
+  /* 171 */ 's', 'a', 'd', 'd', 'l', '2', 9, 0,
+  /* 179 */ 'u', 'a', 'd', 'd', 'l', '2', 9, 0,
+  /* 187 */ 's', 's', 'h', 'l', 'l', '2', 9, 0,
+  /* 195 */ 'u', 's', 'h', 'l', 'l', '2', 9, 0,
+  /* 203 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', '2', 9, 0,
+  /* 213 */ 'p', 'm', 'u', 'l', 'l', '2', 9, 0,
+  /* 221 */ 's', 'm', 'u', 'l', 'l', '2', 9, 0,
+  /* 229 */ 'u', 'm', 'u', 'l', 'l', '2', 9, 0,
+  /* 237 */ 's', 'q', 'd', 'm', 'l', 's', 'l', '2', 9, 0,
+  /* 247 */ 's', 'm', 'l', 's', 'l', '2', 9, 0,
+  /* 255 */ 'u', 'm', 'l', 's', 'l', '2', 9, 0,
+  /* 263 */ 'f', 'c', 'v', 't', 'l', '2', 9, 0,
+  /* 271 */ 'r', 's', 'u', 'b', 'h', 'n', '2', 9, 0,
+  /* 280 */ 'r', 'a', 'd', 'd', 'h', 'n', '2', 9, 0,
+  /* 289 */ 's', 'q', 's', 'h', 'r', 'n', '2', 9, 0,
+  /* 298 */ 'u', 'q', 's', 'h', 'r', 'n', '2', 9, 0,
+  /* 307 */ 's', 'q', 'r', 's', 'h', 'r', 'n', '2', 9, 0,
+  /* 317 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', '2', 9, 0,
+  /* 327 */ 't', 'r', 'n', '2', 9, 0,
+  /* 333 */ 'f', 'c', 'v', 't', 'n', '2', 9, 0,
+  /* 341 */ 's', 'q', 'x', 't', 'n', '2', 9, 0,
+  /* 349 */ 'u', 'q', 'x', 't', 'n', '2', 9, 0,
+  /* 357 */ 's', 'q', 's', 'h', 'r', 'u', 'n', '2', 9, 0,
+  /* 367 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', '2', 9, 0,
+  /* 378 */ 's', 'q', 'x', 't', 'u', 'n', '2', 9, 0,
+  /* 387 */ 'f', 'c', 'v', 't', 'x', 'n', '2', 9, 0,
+  /* 396 */ 'z', 'i', 'p', '2', 9, 0,
+  /* 402 */ 'u', 'z', 'p', '2', 9, 0,
+  /* 408 */ 'd', 'c', 'p', 's', '2', 9, 0,
+  /* 415 */ 's', 't', '2', 9, 0,
+  /* 420 */ 's', 's', 'u', 'b', 'w', '2', 9, 0,
+  /* 428 */ 'u', 's', 'u', 'b', 'w', '2', 9, 0,
+  /* 436 */ 's', 'a', 'd', 'd', 'w', '2', 9, 0,
+  /* 444 */ 'u', 'a', 'd', 'd', 'w', '2', 9, 0,
+  /* 452 */ 'l', 'd', '3', 9, 0,
+  /* 457 */ 'd', 'c', 'p', 's', '3', 9, 0,
+  /* 464 */ 's', 't', '3', 9, 0,
+  /* 469 */ 'r', 'e', 'v', '6', '4', 9, 0,
+  /* 476 */ 'l', 'd', '4', 9, 0,
+  /* 481 */ 's', 't', '4', 9, 0,
+  /* 486 */ 'r', 'e', 'v', '1', '6', 9, 0,
+  /* 493 */ 's', 'a', 'b', 'a', 9, 0,
+  /* 499 */ 'u', 'a', 'b', 'a', 9, 0,
+  /* 505 */ 'f', 'm', 'l', 'a', 9, 0,
+  /* 511 */ 's', 'r', 's', 'r', 'a', 9, 0,
+  /* 518 */ 'u', 'r', 's', 'r', 'a', 9, 0,
+  /* 525 */ 's', 's', 'r', 'a', 9, 0,
+  /* 531 */ 'u', 's', 'r', 'a', 9, 0,
+  /* 537 */ 'f', 'r', 'i', 'n', 't', 'a', 9, 0,
+  /* 545 */ 'c', 'r', 'c', '3', '2', 'b', 9, 0,
+  /* 553 */ 'c', 'r', 'c', '3', '2', 'c', 'b', 9, 0,
+  /* 562 */ 'd', 'm', 'b', 9, 0,
+  /* 567 */ 'l', 'd', 'a', 'r', 'b', 9, 0,
+  /* 574 */ 'l', 'd', 'r', 'b', 9, 0,
+  /* 580 */ 's', 't', 'l', 'r', 'b', 9, 0,
+  /* 587 */ 'l', 'd', 't', 'r', 'b', 9, 0,
+  /* 594 */ 's', 't', 'r', 'b', 9, 0,
+  /* 600 */ 's', 't', 't', 'r', 'b', 9, 0,
+  /* 607 */ 'l', 'd', 'u', 'r', 'b', 9, 0,
+  /* 614 */ 's', 't', 'u', 'r', 'b', 9, 0,
+  /* 621 */ 'l', 'd', 'a', 'x', 'r', 'b', 9, 0,
+  /* 629 */ 'l', 'd', 'x', 'r', 'b', 9, 0,
+  /* 636 */ 's', 't', 'l', 'x', 'r', 'b', 9, 0,
+  /* 644 */ 's', 't', 'x', 'r', 'b', 9, 0,
+  /* 651 */ 'd', 's', 'b', 9, 0,
+  /* 656 */ 'i', 's', 'b', 9, 0,
+  /* 661 */ 'l', 'd', 'r', 's', 'b', 9, 0,
+  /* 668 */ 'l', 'd', 't', 'r', 's', 'b', 9, 0,
+  /* 676 */ 'l', 'd', 'u', 'r', 's', 'b', 9, 0,
+  /* 684 */ 'f', 's', 'u', 'b', 9, 0,
+  /* 690 */ 's', 'h', 's', 'u', 'b', 9, 0,
+  /* 697 */ 'u', 'h', 's', 'u', 'b', 9, 0,
+  /* 704 */ 'f', 'm', 's', 'u', 'b', 9, 0,
+  /* 711 */ 'f', 'n', 'm', 's', 'u', 'b', 9, 0,
+  /* 719 */ 's', 'q', 's', 'u', 'b', 9, 0,
+  /* 726 */ 'u', 'q', 's', 'u', 'b', 9, 0,
+  /* 733 */ 's', 'h', 'a', '1', 'c', 9, 0,
+  /* 740 */ 's', 'b', 'c', 9, 0,
+  /* 745 */ 'a', 'd', 'c', 9, 0,
+  /* 750 */ 'b', 'i', 'c', 9, 0,
+  /* 755 */ 'a', 'e', 's', 'i', 'm', 'c', 9, 0,
+  /* 763 */ 'a', 'e', 's', 'm', 'c', 9, 0,
+  /* 770 */ 'c', 's', 'i', 'n', 'c', 9, 0,
+  /* 777 */ 'h', 'v', 'c', 9, 0,
+  /* 782 */ 's', 'v', 'c', 9, 0,
+  /* 787 */ 'f', 'a', 'b', 'd', 9, 0,
+  /* 793 */ 's', 'a', 'b', 'd', 9, 0,
+  /* 799 */ 'u', 'a', 'b', 'd', 9, 0,
+  /* 805 */ 'f', 'a', 'd', 'd', 9, 0,
+  /* 811 */ 's', 'r', 'h', 'a', 'd', 'd', 9, 0,
+  /* 819 */ 'u', 'r', 'h', 'a', 'd', 'd', 9, 0,
+  /* 827 */ 's', 'h', 'a', 'd', 'd', 9, 0,
+  /* 834 */ 'u', 'h', 'a', 'd', 'd', 9, 0,
+  /* 841 */ 'f', 'm', 'a', 'd', 'd', 9, 0,
+  /* 848 */ 'f', 'n', 'm', 'a', 'd', 'd', 9, 0,
+  /* 856 */ 'u', 's', 'q', 'a', 'd', 'd', 9, 0,
+  /* 864 */ 's', 'u', 'q', 'a', 'd', 'd', 9, 0,
+  /* 872 */ 'a', 'n', 'd', 9, 0,
+  /* 877 */ 'a', 'e', 's', 'd', 9, 0,
+  /* 883 */ 'f', 'a', 'c', 'g', 'e', 9, 0,
+  /* 890 */ 'f', 'c', 'm', 'g', 'e', 9, 0,
+  /* 897 */ 'f', 'c', 'm', 'l', 'e', 9, 0,
+  /* 904 */ 'f', 'r', 'e', 'c', 'p', 'e', 9, 0,
+  /* 912 */ 'u', 'r', 'e', 'c', 'p', 'e', 9, 0,
+  /* 920 */ 'f', 'c', 'c', 'm', 'p', 'e', 9, 0,
+  /* 928 */ 'f', 'c', 'm', 'p', 'e', 9, 0,
+  /* 935 */ 'a', 'e', 's', 'e', 9, 0,
+  /* 941 */ 'f', 'r', 's', 'q', 'r', 't', 'e', 9, 0,
+  /* 950 */ 'u', 'r', 's', 'q', 'r', 't', 'e', 9, 0,
+  /* 959 */ 'b', 'i', 'f', 9, 0,
+  /* 964 */ 's', 'c', 'v', 't', 'f', 9, 0,
+  /* 971 */ 'u', 'c', 'v', 't', 'f', 9, 0,
+  /* 978 */ 'f', 'n', 'e', 'g', 9, 0,
+  /* 984 */ 's', 'q', 'n', 'e', 'g', 9, 0,
+  /* 991 */ 'c', 's', 'n', 'e', 'g', 9, 0,
+  /* 998 */ 's', 'h', 'a', '1', 'h', 9, 0,
+  /* 1005 */ 'c', 'r', 'c', '3', '2', 'h', 9, 0,
+  /* 1013 */ 's', 'h', 'a', '2', '5', '6', 'h', 9, 0,
+  /* 1022 */ 'c', 'r', 'c', '3', '2', 'c', 'h', 9, 0,
+  /* 1031 */ 's', 'q', 'd', 'm', 'u', 'l', 'h', 9, 0,
+  /* 1040 */ 's', 'q', 'r', 'd', 'm', 'u', 'l', 'h', 9, 0,
+  /* 1050 */ 's', 'm', 'u', 'l', 'h', 9, 0,
+  /* 1057 */ 'u', 'm', 'u', 'l', 'h', 9, 0,
+  /* 1064 */ 'l', 'd', 'a', 'r', 'h', 9, 0,
+  /* 1071 */ 'l', 'd', 'r', 'h', 9, 0,
+  /* 1077 */ 's', 't', 'l', 'r', 'h', 9, 0,
+  /* 1084 */ 'l', 'd', 't', 'r', 'h', 9, 0,
+  /* 1091 */ 's', 't', 'r', 'h', 9, 0,
+  /* 1097 */ 's', 't', 't', 'r', 'h', 9, 0,
+  /* 1104 */ 'l', 'd', 'u', 'r', 'h', 9, 0,
+  /* 1111 */ 's', 't', 'u', 'r', 'h', 9, 0,
+  /* 1118 */ 'l', 'd', 'a', 'x', 'r', 'h', 9, 0,
+  /* 1126 */ 'l', 'd', 'x', 'r', 'h', 9, 0,
+  /* 1133 */ 's', 't', 'l', 'x', 'r', 'h', 9, 0,
+  /* 1141 */ 's', 't', 'x', 'r', 'h', 9, 0,
+  /* 1148 */ 'l', 'd', 'r', 's', 'h', 9, 0,
+  /* 1155 */ 'l', 'd', 't', 'r', 's', 'h', 9, 0,
+  /* 1163 */ 'l', 'd', 'u', 'r', 's', 'h', 9, 0,
+  /* 1171 */ 'c', 'm', 'h', 'i', 9, 0,
+  /* 1177 */ 's', 'l', 'i', 9, 0,
+  /* 1182 */ 'm', 'v', 'n', 'i', 9, 0,
+  /* 1188 */ 's', 'r', 'i', 9, 0,
+  /* 1193 */ 'f', 'r', 'i', 'n', 't', 'i', 9, 0,
+  /* 1201 */ 'm', 'o', 'v', 'i', 9, 0,
+  /* 1207 */ 'b', 'r', 'k', 9, 0,
+  /* 1212 */ 'm', 'o', 'v', 'k', 9, 0,
+  /* 1218 */ 's', 'a', 'b', 'a', 'l', 9, 0,
+  /* 1225 */ 'u', 'a', 'b', 'a', 'l', 9, 0,
+  /* 1232 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', 9, 0,
+  /* 1241 */ 's', 'm', 'l', 'a', 'l', 9, 0,
+  /* 1248 */ 'u', 'm', 'l', 'a', 'l', 9, 0,
+  /* 1255 */ 't', 'b', 'l', 9, 0,
+  /* 1260 */ 's', 'm', 's', 'u', 'b', 'l', 9, 0,
+  /* 1268 */ 'u', 'm', 's', 'u', 'b', 'l', 9, 0,
+  /* 1276 */ 's', 's', 'u', 'b', 'l', 9, 0,
+  /* 1283 */ 'u', 's', 'u', 'b', 'l', 9, 0,
+  /* 1290 */ 's', 'a', 'b', 'd', 'l', 9, 0,
+  /* 1297 */ 'u', 'a', 'b', 'd', 'l', 9, 0,
+  /* 1304 */ 's', 'm', 'a', 'd', 'd', 'l', 9, 0,
+  /* 1312 */ 'u', 'm', 'a', 'd', 'd', 'l', 9, 0,
+  /* 1320 */ 's', 'a', 'd', 'd', 'l', 9, 0,
+  /* 1327 */ 'u', 'a', 'd', 'd', 'l', 9, 0,
+  /* 1334 */ 'f', 'c', 's', 'e', 'l', 9, 0,
+  /* 1341 */ 's', 'q', 's', 'h', 'l', 9, 0,
+  /* 1348 */ 'u', 'q', 's', 'h', 'l', 9, 0,
+  /* 1355 */ 's', 'q', 'r', 's', 'h', 'l', 9, 0,
+  /* 1363 */ 'u', 'q', 'r', 's', 'h', 'l', 9, 0,
+  /* 1371 */ 's', 'r', 's', 'h', 'l', 9, 0,
+  /* 1378 */ 'u', 'r', 's', 'h', 'l', 9, 0,
+  /* 1385 */ 's', 's', 'h', 'l', 9, 0,
+  /* 1391 */ 'u', 's', 'h', 'l', 9, 0,
+  /* 1397 */ 's', 's', 'h', 'l', 'l', 9, 0,
+  /* 1404 */ 'u', 's', 'h', 'l', 'l', 9, 0,
+  /* 1411 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', 9, 0,
+  /* 1420 */ 'p', 'm', 'u', 'l', 'l', 9, 0,
+  /* 1427 */ 's', 'm', 'u', 'l', 'l', 9, 0,
+  /* 1434 */ 'u', 'm', 'u', 'l', 'l', 9, 0,
+  /* 1441 */ 'b', 's', 'l', 9, 0,
+  /* 1446 */ 's', 'q', 'd', 'm', 'l', 's', 'l', 9, 0,
+  /* 1455 */ 's', 'm', 'l', 's', 'l', 9, 0,
+  /* 1462 */ 'u', 'm', 'l', 's', 'l', 9, 0,
+  /* 1469 */ 's', 'y', 's', 'l', 9, 0,
+  /* 1475 */ 'f', 'c', 'v', 't', 'l', 9, 0,
+  /* 1482 */ 'f', 'm', 'u', 'l', 9, 0,
+  /* 1488 */ 'f', 'n', 'm', 'u', 'l', 9, 0,
+  /* 1495 */ 'p', 'm', 'u', 'l', 9, 0,
+  /* 1501 */ 's', 'h', 'a', '1', 'm', 9, 0,
+  /* 1508 */ 's', 'b', 'f', 'm', 9, 0,
+  /* 1514 */ 'u', 'b', 'f', 'm', 9, 0,
+  /* 1520 */ 'p', 'r', 'f', 'm', 9, 0,
+  /* 1526 */ 'f', 'm', 'i', 'n', 'n', 'm', 9, 0,
+  /* 1534 */ 'f', 'm', 'a', 'x', 'n', 'm', 9, 0,
+  /* 1542 */ 'f', 'r', 'i', 'n', 't', 'm', 9, 0,
+  /* 1550 */ 'p', 'r', 'f', 'u', 'm', 9, 0,
+  /* 1557 */ 'r', 's', 'u', 'b', 'h', 'n', 9, 0,
+  /* 1565 */ 'r', 'a', 'd', 'd', 'h', 'n', 9, 0,
+  /* 1573 */ 'f', 'm', 'i', 'n', 9, 0,
+  /* 1579 */ 's', 'm', 'i', 'n', 9, 0,
+  /* 1585 */ 'u', 'm', 'i', 'n', 9, 0,
+  /* 1591 */ 'c', 'c', 'm', 'n', 9, 0,
+  /* 1597 */ 'e', 'o', 'n', 9, 0,
+  /* 1602 */ 's', 'q', 's', 'h', 'r', 'n', 9, 0,
+  /* 1610 */ 'u', 'q', 's', 'h', 'r', 'n', 9, 0,
+  /* 1618 */ 's', 'q', 'r', 's', 'h', 'r', 'n', 9, 0,
+  /* 1627 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', 9, 0,
+  /* 1636 */ 'o', 'r', 'n', 9, 0,
+  /* 1641 */ 'f', 'r', 'i', 'n', 't', 'n', 9, 0,
+  /* 1649 */ 'f', 'c', 'v', 't', 'n', 9, 0,
+  /* 1656 */ 's', 'q', 'x', 't', 'n', 9, 0,
+  /* 1663 */ 'u', 'q', 'x', 't', 'n', 9, 0,
+  /* 1670 */ 's', 'q', 's', 'h', 'r', 'u', 'n', 9, 0,
+  /* 1679 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', 9, 0,
+  /* 1689 */ 's', 'q', 'x', 't', 'u', 'n', 9, 0,
+  /* 1697 */ 'm', 'o', 'v', 'n', 9, 0,
+  /* 1703 */ 'f', 'c', 'v', 't', 'x', 'n', 9, 0,
+  /* 1711 */ 's', 'h', 'a', '1', 'p', 9, 0,
+  /* 1718 */ 'f', 'a', 'd', 'd', 'p', 9, 0,
+  /* 1725 */ 'l', 'd', 'p', 9, 0,
+  /* 1730 */ 's', 'a', 'd', 'a', 'l', 'p', 9, 0,
+  /* 1738 */ 'u', 'a', 'd', 'a', 'l', 'p', 9, 0,
+  /* 1746 */ 's', 'a', 'd', 'd', 'l', 'p', 9, 0,
+  /* 1754 */ 'u', 'a', 'd', 'd', 'l', 'p', 9, 0,
+  /* 1762 */ 'f', 'c', 'c', 'm', 'p', 9, 0,
+  /* 1769 */ 'f', 'c', 'm', 'p', 9, 0,
+  /* 1775 */ 'f', 'm', 'i', 'n', 'n', 'm', 'p', 9, 0,
+  /* 1784 */ 'f', 'm', 'a', 'x', 'n', 'm', 'p', 9, 0,
+  /* 1793 */ 'l', 'd', 'n', 'p', 9, 0,
+  /* 1799 */ 'f', 'm', 'i', 'n', 'p', 9, 0,
+  /* 1806 */ 's', 'm', 'i', 'n', 'p', 9, 0,
+  /* 1813 */ 'u', 'm', 'i', 'n', 'p', 9, 0,
+  /* 1820 */ 's', 't', 'n', 'p', 9, 0,
+  /* 1826 */ 'a', 'd', 'r', 'p', 9, 0,
+  /* 1832 */ 'f', 'r', 'i', 'n', 't', 'p', 9, 0,
+  /* 1840 */ 's', 't', 'p', 9, 0,
+  /* 1845 */ 'd', 'u', 'p', 9, 0,
+  /* 1850 */ 'l', 'd', 'a', 'x', 'p', 9, 0,
+  /* 1857 */ 'f', 'm', 'a', 'x', 'p', 9, 0,
+  /* 1864 */ 's', 'm', 'a', 'x', 'p', 9, 0,
+  /* 1871 */ 'u', 'm', 'a', 'x', 'p', 9, 0,
+  /* 1878 */ 'l', 'd', 'x', 'p', 9, 0,
+  /* 1884 */ 's', 't', 'l', 'x', 'p', 9, 0,
+  /* 1891 */ 's', 't', 'x', 'p', 9, 0,
+  /* 1897 */ 'f', 'c', 'm', 'e', 'q', 9, 0,
+  /* 1904 */ 'l', 'd', '1', 'r', 9, 0,
+  /* 1910 */ 'l', 'd', '2', 'r', 9, 0,
+  /* 1916 */ 'l', 'd', '3', 'r', 9, 0,
+  /* 1922 */ 'l', 'd', '4', 'r', 9, 0,
+  /* 1928 */ 'l', 'd', 'a', 'r', 9, 0,
+  /* 1934 */ 'b', 'r', 9, 0,
+  /* 1938 */ 'a', 'd', 'r', 9, 0,
+  /* 1943 */ 'l', 'd', 'r', 9, 0,
+  /* 1948 */ 's', 'r', 's', 'h', 'r', 9, 0,
+  /* 1955 */ 'u', 'r', 's', 'h', 'r', 9, 0,
+  /* 1962 */ 's', 's', 'h', 'r', 9, 0,
+  /* 1968 */ 'u', 's', 'h', 'r', 9, 0,
+  /* 1974 */ 'b', 'l', 'r', 9, 0,
+  /* 1979 */ 's', 't', 'l', 'r', 9, 0,
+  /* 1985 */ 'e', 'o', 'r', 9, 0,
+  /* 1990 */ 'r', 'o', 'r', 9, 0,
+  /* 1995 */ 'o', 'r', 'r', 9, 0,
+  /* 2000 */ 'a', 's', 'r', 9, 0,
+  /* 2005 */ 'l', 's', 'r', 9, 0,
+  /* 2010 */ 'm', 's', 'r', 9, 0,
+  /* 2015 */ 'l', 'd', 't', 'r', 9, 0,
+  /* 2021 */ 's', 't', 'r', 9, 0,
+  /* 2026 */ 's', 't', 't', 'r', 9, 0,
+  /* 2032 */ 'e', 'x', 't', 'r', 9, 0,
+  /* 2038 */ 'l', 'd', 'u', 'r', 9, 0,
+  /* 2044 */ 's', 't', 'u', 'r', 9, 0,
+  /* 2050 */ 'l', 'd', 'a', 'x', 'r', 9, 0,
+  /* 2057 */ 'l', 'd', 'x', 'r', 9, 0,
+  /* 2063 */ 's', 't', 'l', 'x', 'r', 9, 0,
+  /* 2070 */ 's', 't', 'x', 'r', 9, 0,
+  /* 2076 */ 'f', 'c', 'v', 't', 'a', 's', 9, 0,
+  /* 2084 */ 'f', 'a', 'b', 's', 9, 0,
+  /* 2090 */ 's', 'q', 'a', 'b', 's', 9, 0,
+  /* 2097 */ 's', 'u', 'b', 's', 9, 0,
+  /* 2103 */ 's', 'b', 'c', 's', 9, 0,
+  /* 2109 */ 'a', 'd', 'c', 's', 9, 0,
+  /* 2115 */ 'b', 'i', 'c', 's', 9, 0,
+  /* 2121 */ 'a', 'd', 'd', 's', 9, 0,
+  /* 2127 */ 'a', 'n', 'd', 's', 9, 0,
+  /* 2133 */ 'c', 'm', 'h', 's', 9, 0,
+  /* 2139 */ 'c', 'l', 's', 9, 0,
+  /* 2144 */ 'f', 'm', 'l', 's', 9, 0,
+  /* 2150 */ 'f', 'c', 'v', 't', 'm', 's', 9, 0,
+  /* 2158 */ 'i', 'n', 's', 9, 0,
+  /* 2163 */ 'f', 'c', 'v', 't', 'n', 's', 9, 0,
+  /* 2171 */ 'f', 'r', 'e', 'c', 'p', 's', 9, 0,
+  /* 2179 */ 'f', 'c', 'v', 't', 'p', 's', 9, 0,
+  /* 2187 */ 'm', 'r', 's', 9, 0,
+  /* 2192 */ 'f', 'r', 's', 'q', 'r', 't', 's', 9, 0,
+  /* 2201 */ 's', 'y', 's', 9, 0,
+  /* 2206 */ 'f', 'c', 'v', 't', 'z', 's', 9, 0,
+  /* 2214 */ 'r', 'e', 't', 9, 0,
+  /* 2219 */ 'f', 'a', 'c', 'g', 't', 9, 0,
+  /* 2226 */ 'f', 'c', 'm', 'g', 't', 9, 0,
+  /* 2233 */ 'r', 'b', 'i', 't', 9, 0,
+  /* 2239 */ 'h', 'l', 't', 9, 0,
+  /* 2244 */ 'f', 'c', 'm', 'l', 't', 9, 0,
+  /* 2251 */ 'c', 'n', 't', 9, 0,
+  /* 2256 */ 'n', 'o', 't', 9, 0,
+  /* 2261 */ 'f', 's', 'q', 'r', 't', 9, 0,
+  /* 2268 */ 'c', 'm', 't', 's', 't', 9, 0,
+  /* 2275 */ 'f', 'c', 'v', 't', 9, 0,
+  /* 2281 */ 'e', 'x', 't', 9, 0,
+  /* 2286 */ 'f', 'c', 'v', 't', 'a', 'u', 9, 0,
+  /* 2294 */ 's', 'q', 's', 'h', 'l', 'u', 9, 0,
+  /* 2302 */ 'f', 'c', 'v', 't', 'm', 'u', 9, 0,
+  /* 2310 */ 'f', 'c', 'v', 't', 'n', 'u', 9, 0,
+  /* 2318 */ 'f', 'c', 'v', 't', 'p', 'u', 9, 0,
+  /* 2326 */ 'f', 'c', 'v', 't', 'z', 'u', 9, 0,
+  /* 2334 */ 'a', 'd', 'd', 'v', 9, 0,
+  /* 2340 */ 'r', 'e', 'v', 9, 0,
+  /* 2345 */ 'f', 'd', 'i', 'v', 9, 0,
+  /* 2351 */ 's', 'd', 'i', 'v', 9, 0,
+  /* 2357 */ 'u', 'd', 'i', 'v', 9, 0,
+  /* 2363 */ 's', 'a', 'd', 'd', 'l', 'v', 9, 0,
+  /* 2371 */ 'u', 'a', 'd', 'd', 'l', 'v', 9, 0,
+  /* 2379 */ 'f', 'm', 'i', 'n', 'n', 'm', 'v', 9, 0,
+  /* 2388 */ 'f', 'm', 'a', 'x', 'n', 'm', 'v', 9, 0,
+  /* 2397 */ 'f', 'm', 'i', 'n', 'v', 9, 0,
+  /* 2404 */ 's', 'm', 'i', 'n', 'v', 9, 0,
+  /* 2411 */ 'u', 'm', 'i', 'n', 'v', 9, 0,
+  /* 2418 */ 'c', 's', 'i', 'n', 'v', 9, 0,
+  /* 2425 */ 'f', 'm', 'o', 'v', 9, 0,
+  /* 2431 */ 's', 'm', 'o', 'v', 9, 0,
+  /* 2437 */ 'u', 'm', 'o', 'v', 9, 0,
+  /* 2443 */ 'f', 'm', 'a', 'x', 'v', 9, 0,
+  /* 2450 */ 's', 'm', 'a', 'x', 'v', 9, 0,
+  /* 2457 */ 'u', 'm', 'a', 'x', 'v', 9, 0,
+  /* 2464 */ 'c', 'r', 'c', '3', '2', 'w', 9, 0,
+  /* 2472 */ 's', 's', 'u', 'b', 'w', 9, 0,
+  /* 2479 */ 'u', 's', 'u', 'b', 'w', 9, 0,
+  /* 2486 */ 'c', 'r', 'c', '3', '2', 'c', 'w', 9, 0,
+  /* 2495 */ 's', 'a', 'd', 'd', 'w', 9, 0,
+  /* 2502 */ 'u', 'a', 'd', 'd', 'w', 9, 0,
+  /* 2509 */ 'l', 'd', 'p', 's', 'w', 9, 0,
+  /* 2516 */ 'l', 'd', 'r', 's', 'w', 9, 0,
+  /* 2523 */ 'l', 'd', 't', 'r', 's', 'w', 9, 0,
+  /* 2531 */ 'l', 'd', 'u', 'r', 's', 'w', 9, 0,
+  /* 2539 */ 'c', 'r', 'c', '3', '2', 'x', 9, 0,
+  /* 2547 */ 'f', 'm', 'a', 'x', 9, 0,
+  /* 2553 */ 's', 'm', 'a', 'x', 9, 0,
+  /* 2559 */ 'u', 'm', 'a', 'x', 9, 0,
+  /* 2565 */ 't', 'b', 'x', 9, 0,
+  /* 2570 */ 'c', 'r', 'c', '3', '2', 'c', 'x', 9, 0,
+  /* 2579 */ 'c', 'l', 'r', 'e', 'x', 9, 0,
+  /* 2586 */ 'f', 'm', 'u', 'l', 'x', 9, 0,
+  /* 2593 */ 'f', 'r', 'e', 'c', 'p', 'x', 9, 0,
+  /* 2601 */ 'f', 'r', 'i', 'n', 't', 'x', 9, 0,
+  /* 2609 */ 'c', 'b', 'z', 9, 0,
+  /* 2614 */ 't', 'b', 'z', 9, 0,
+  /* 2619 */ 'c', 'l', 'z', 9, 0,
+  /* 2624 */ 'c', 'b', 'n', 'z', 9, 0,
+  /* 2630 */ 't', 'b', 'n', 'z', 9, 0,
+  /* 2636 */ 'f', 'r', 'i', 'n', 't', 'z', 9, 0,
+  /* 2644 */ 'm', 'o', 'v', 'z', 9, 0,
+  /* 2650 */ '.', 't', 'l', 's', 'd', 'e', 's', 'c', 'c', 'a', 'l', 'l', 32, 0,
+  /* 2664 */ 'h', 'i', 'n', 't', 32, 0,
+  /* 2670 */ 'b', '.', 0,
+  /* 2673 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
+  /* 2686 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
+  /* 2693 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
+  /* 2703 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
+  /* 2718 */ 'd', 'r', 'p', 's', 0,
+  /* 2723 */ 'e', 'r', 'e', 't', 0,
+  };
+#endif
+
+  // Emit the opcode for the instruction.
+  uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)];
+  uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)];
+  uint64_t Bits = (Bits2 << 32) | Bits1;
+  // assert(Bits != 0 && "Cannot print this instruction.");
+#ifndef CAPSTONE_DIET
+  SStream_concat0(O, AsmStrs+(Bits & 4095)-1);
+#endif
+
+
+  // Fragment 0 encoded into 6 bits for 40 unique commands.
+  //printf("Frag-0: %"PRIu64"\n", (Bits >> 12) & 63);
+  switch ((Bits >> 12) & 63) {
+  default:   // unreachable.
+  case 0:
+    // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, DRPS, ERET
+    return;
+    break;
+  case 1:
+    // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A...
+    printVRegOperand(MI, 0, O); 
+    break;
+  case 2:
+    // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPv2i64p, ADDSWri, ADDSWrs, ...
+    printOperand(MI, 0, O); 
+    break;
+  case 3:
+    // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ...
+    printVRegOperand(MI, 1, O); 
+    break;
+  case 4:
+    // B, BL
+    printAlignedLabel(MI, 0, O); 
+    return;
+    break;
+  case 5:
+    // BRK, DCPS1, DCPS2, DCPS3, HINT, HLT, HVC, SMC, SVC
+    printHexImm(MI, 0, O); 
+    return;
+    break;
+  case 6:
+    // Bcc
+    printCondCode(MI, 0, O); 
+    SStream_concat0(O, "\t"); 
+    printAlignedLabel(MI, 1, O); 
+    return;
+    break;
+  case 7:
+    // DMB, DSB, ISB
+    printBarrierOption(MI, 0, O); 
+    return;
+    break;
+  case 8:
+    // FMLAv1i32_indexed, FMLAv1i64_indexed, FMLSv1i32_indexed, FMLSv1i64_ind...
+    printOperand(MI, 1, O); 
+    break;
+  case 9:
+    // LD1Fourv16b, LD1Onev16b, LD1Rv16b, LD1Threev16b, LD1Twov16b, LD2Rv16b,...
+    printTypedVectorList(MI, 0, O, 16, 'b', MRI); 
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 1, O); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 10:
+    // LD1Fourv16b_POST, LD1Onev16b_POST, LD1Rv16b_POST, LD1Threev16b_POST, L...
+    printTypedVectorList(MI, 1, O, 16, 'b', MRI); 
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 2, O); 
+    SStream_concat0(O, "], "); 
+    set_mem_access(MI, false);
+    break;
+  case 11:
+    // LD1Fourv1d, LD1Onev1d, LD1Rv1d, LD1Threev1d, LD1Twov1d, LD2Rv1d, LD3Rv...
+    printTypedVectorList(MI, 0, O, 1, 'd', MRI); 
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 1, O); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 12:
+    // LD1Fourv1d_POST, LD1Onev1d_POST, LD1Rv1d_POST, LD1Threev1d_POST, LD1Tw...
+    printTypedVectorList(MI, 1, O, 1, 'd', MRI); 
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 2, O); 
+    SStream_concat0(O, "], "); 
+    set_mem_access(MI, false);
+    break;
+  case 13:
+    // LD1Fourv2d, LD1Onev2d, LD1Rv2d, LD1Threev2d, LD1Twov2d, LD2Rv2d, LD2Tw...
+    printTypedVectorList(MI, 0, O, 2, 'd', MRI); 
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 1, O); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 14:
+    // LD1Fourv2d_POST, LD1Onev2d_POST, LD1Rv2d_POST, LD1Threev2d_POST, LD1Tw...
+    printTypedVectorList(MI, 1, O, 2, 'd', MRI); 
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 2, O); 
+    SStream_concat0(O, "], "); 
+    set_mem_access(MI, false);
+    break;
+  case 15:
+    // LD1Fourv2s, LD1Onev2s, LD1Rv2s, LD1Threev2s, LD1Twov2s, LD2Rv2s, LD2Tw...
+    printTypedVectorList(MI, 0, O, 2, 's', MRI); 
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 1, O); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 16:
+    // LD1Fourv2s_POST, LD1Onev2s_POST, LD1Rv2s_POST, LD1Threev2s_POST, LD1Tw...
+    printTypedVectorList(MI, 1, O, 2, 's', MRI); 
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 2, O); 
+    SStream_concat0(O, "], "); 
+    set_mem_access(MI, false);
+    break;
+  case 17:
+    // LD1Fourv4h, LD1Onev4h, LD1Rv4h, LD1Threev4h, LD1Twov4h, LD2Rv4h, LD2Tw...
+    printTypedVectorList(MI, 0, O, 4, 'h', MRI); 
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 1, O); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 18:
+    // LD1Fourv4h_POST, LD1Onev4h_POST, LD1Rv4h_POST, LD1Threev4h_POST, LD1Tw...
+    printTypedVectorList(MI, 1, O, 4, 'h', MRI); 
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 2, O); 
+    SStream_concat0(O, "], "); 
+    set_mem_access(MI, false);
+    break;
+  case 19:
+    // LD1Fourv4s, LD1Onev4s, LD1Rv4s, LD1Threev4s, LD1Twov4s, LD2Rv4s, LD2Tw...
+    printTypedVectorList(MI, 0, O, 4, 's', MRI); 
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 1, O); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 20:
+    // LD1Fourv4s_POST, LD1Onev4s_POST, LD1Rv4s_POST, LD1Threev4s_POST, LD1Tw...
+    printTypedVectorList(MI, 1, O, 4, 's', MRI); 
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 2, O); 
+    SStream_concat0(O, "], "); 
+    set_mem_access(MI, false);
+    break;
+  case 21:
+    // LD1Fourv8b, LD1Onev8b, LD1Rv8b, LD1Threev8b, LD1Twov8b, LD2Rv8b, LD2Tw...
+    printTypedVectorList(MI, 0, O, 8, 'b', MRI); 
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 1, O); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 22:
+    // LD1Fourv8b_POST, LD1Onev8b_POST, LD1Rv8b_POST, LD1Threev8b_POST, LD1Tw...
+    printTypedVectorList(MI, 1, O, 8, 'b', MRI); 
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 2, O); 
+    SStream_concat0(O, "], "); 
+    set_mem_access(MI, false);
+    break;
+  case 23:
+    // LD1Fourv8h, LD1Onev8h, LD1Rv8h, LD1Threev8h, LD1Twov8h, LD2Rv8h, LD2Tw...
+    printTypedVectorList(MI, 0, O, 8, 'h', MRI); 
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 1, O); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 24:
+    // LD1Fourv8h_POST, LD1Onev8h_POST, LD1Rv8h_POST, LD1Threev8h_POST, LD1Tw...
+    printTypedVectorList(MI, 1, O, 8, 'h', MRI); 
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 2, O); 
+    SStream_concat0(O, "], "); 
+    set_mem_access(MI, false);
+    break;
+  case 25:
+    // LD1i16, LD2i16, LD3i16, LD4i16, ST1i16_POST, ST2i16_POST, ST3i16_POST,...
+    printTypedVectorList(MI, 1, O, 0, 'h', MRI); 
+    printVectorIndex(MI, 2, O); 
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 3, O); 
+    break;
+  case 26:
+    // LD1i16_POST, LD2i16_POST, LD3i16_POST, LD4i16_POST
+    printTypedVectorList(MI, 2, O, 0, 'h', MRI); 
+    printVectorIndex(MI, 3, O); 
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 4, O); 
+    SStream_concat0(O, "], "); 
+    set_mem_access(MI, false);
+    break;
+  case 27:
+    // LD1i32, LD2i32, LD3i32, LD4i32, ST1i32_POST, ST2i32_POST, ST3i32_POST,...
+    printTypedVectorList(MI, 1, O, 0, 's', MRI); 
+    printVectorIndex(MI, 2, O); 
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 3, O); 
+    break;
+  case 28:
+    // LD1i32_POST, LD2i32_POST, LD3i32_POST, LD4i32_POST
+    printTypedVectorList(MI, 2, O, 0, 's', MRI); 
+    printVectorIndex(MI, 3, O); 
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 4, O); 
+    SStream_concat0(O, "], "); 
+    set_mem_access(MI, false);
+    break;
+  case 29:
+    // LD1i64, LD2i64, LD3i64, LD4i64, ST1i64_POST, ST2i64_POST, ST3i64_POST,...
+    printTypedVectorList(MI, 1, O, 0, 'd', MRI); 
+    printVectorIndex(MI, 2, O); 
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 3, O); 
+    break;
+  case 30:
+    // LD1i64_POST, LD2i64_POST, LD3i64_POST, LD4i64_POST
+    printTypedVectorList(MI, 2, O, 0, 'd', MRI); 
+    printVectorIndex(MI, 3, O); 
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 4, O); 
+    SStream_concat0(O, "], "); 
+    set_mem_access(MI, false);
+    break;
+  case 31:
+    // LD1i8, LD2i8, LD3i8, LD4i8, ST1i8_POST, ST2i8_POST, ST3i8_POST, ST4i8_...
+    printTypedVectorList(MI, 1, O, 0, 'b', MRI); 
+    printVectorIndex(MI, 2, O); 
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 3, O); 
+    break;
+  case 32:
+    // LD1i8_POST, LD2i8_POST, LD3i8_POST, LD4i8_POST
+    printTypedVectorList(MI, 2, O, 0, 'b', MRI); 
+    printVectorIndex(MI, 3, O); 
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 4, O); 
+    SStream_concat0(O, "], "); 
+    set_mem_access(MI, false);
+    break;
+  case 33:
+    // MSR
+    printMSRSystemRegister(MI, 0, O); 
+    SStream_concat0(O, ", "); 
+    printOperand(MI, 1, O); 
+    return;
+    break;
+  case 34:
+    // MSRpstate
+    printSystemPStateField(MI, 0, O); 
+    SStream_concat0(O, ", "); 
+    printOperand(MI, 1, O); 
+    return;
+    break;
+  case 35:
+    // PRFMl, PRFMroW, PRFMroX, PRFMui, PRFUMi
+    printPrefetchOp(MI, 0, O); 
+    break;
+  case 36:
+    // ST1i16, ST2i16, ST3i16, ST4i16
+    printTypedVectorList(MI, 0, O, 0, 'h', MRI); 
+    printVectorIndex(MI, 1, O); 
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 2, O); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 37:
+    // ST1i32, ST2i32, ST3i32, ST4i32
+    printTypedVectorList(MI, 0, O, 0, 's', MRI); 
+    printVectorIndex(MI, 1, O); 
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 2, O); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 38:
+    // ST1i64, ST2i64, ST3i64, ST4i64
+    printTypedVectorList(MI, 0, O, 0, 'd', MRI); 
+    printVectorIndex(MI, 1, O); 
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 2, O); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 39:
+    // ST1i8, ST2i8, ST3i8, ST4i8
+    printTypedVectorList(MI, 0, O, 0, 'b', MRI); 
+    printVectorIndex(MI, 1, O); 
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 2, O); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  }
+
+
+  // Fragment 1 encoded into 6 bits for 41 unique commands.
+  //printf("Frag-1: %"PRIu64"\n", (Bits >> 18) & 63);
+  switch ((Bits >> 18) & 63) {
+  default:   // unreachable.
+  case 0:
+    // ABSv16i8, ADDHNv8i16_v16i8, ADDPv16i8, ADDv16i8, AESDrr, AESErr, AESIM...
+    SStream_concat0(O, ".16b, "); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B);
+    break;
+  case 1:
+    // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPv2i64p, ADDSWri, ADDSWrs, ...
+    SStream_concat0(O, ", "); 
+    break;
+  case 2:
+    // ABSv2i32, ADDHNv2i64_v2i32, ADDPv2i32, ADDv2i32, BICv2i32, CLSv2i32, C...
+    SStream_concat0(O, ".2s, "); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S);
+    break;
+  case 3:
+    // ABSv2i64, ADDPv2i64, ADDv2i64, CMEQv2i64, CMEQv2i64rz, CMGEv2i64, CMGE...
+    SStream_concat0(O, ".2d, "); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D);
+    break;
+  case 4:
+    // ABSv4i16, ADDHNv4i32_v4i16, ADDPv4i16, ADDv4i16, BICv4i16, CLSv4i16, C...
+    SStream_concat0(O, ".4h, "); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H);
+    break;
+  case 5:
+    // ABSv4i32, ADDHNv2i64_v4i32, ADDPv4i32, ADDv4i32, BICv4i32, CLSv4i32, C...
+    SStream_concat0(O, ".4s, "); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S);
+    break;
+  case 6:
+    // ABSv8i16, ADDHNv4i32_v8i16, ADDPv8i16, ADDv8i16, BICv8i16, CLSv8i16, C...
+    SStream_concat0(O, ".8h, "); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H);
+    break;
+  case 7:
+    // ABSv8i8, ADDHNv8i16_v8i8, ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8...
+    SStream_concat0(O, ".8b, "); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B);
+    break;
+  case 8:
+    // BLR, BR, CLREX, RET, TLSDESCCALL
+    return;
+    break;
+  case 9:
+    // FCMPDri, FCMPEDri, FCMPESri, FCMPSri
+    SStream_concat0(O, ", #0.0");
+	arm64_op_addFP(MI, 0.0);
+    return;
+    break;
+  case 10:
+    // FMOVXDHighr, INSvi64gpr, INSvi64lane
+    SStream_concat0(O, ".d");
+	arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_D);
+    printVectorIndex(MI, 2, O); 
+    SStream_concat0(O, ", "); 
+    break;
+  case 11:
+    // INSvi16gpr, INSvi16lane
+    SStream_concat0(O, ".h");
+	arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_H);
+    printVectorIndex(MI, 2, O); 
+    SStream_concat0(O, ", "); 
+    break;
+  case 12:
+    // INSvi32gpr, INSvi32lane
+    SStream_concat0(O, ".s");
+	arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_S);
+    printVectorIndex(MI, 2, O); 
+    SStream_concat0(O, ", "); 
+    break;
+  case 13:
+    // INSvi8gpr, INSvi8lane
+    SStream_concat0(O, ".b");
+	arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_B);
+    printVectorIndex(MI, 2, O); 
+    SStream_concat0(O, ", "); 
+    break;
+  case 14:
+    // LD1Fourv16b_POST, LD1Fourv2d_POST, LD1Fourv4s_POST, LD1Fourv8h_POST, L...
+    printPostIncOperand2(MI, 3, O, 64); 
+    return;
+    break;
+  case 15:
+    // LD1Fourv1d_POST, LD1Fourv2s_POST, LD1Fourv4h_POST, LD1Fourv8b_POST, LD...
+    printPostIncOperand2(MI, 3, O, 32); 
+    return;
+    break;
+  case 16:
+    // LD1Onev16b_POST, LD1Onev2d_POST, LD1Onev4s_POST, LD1Onev8h_POST, LD1Tw...
+    printPostIncOperand2(MI, 3, O, 16); 
+    return;
+    break;
+  case 17:
+    // LD1Onev1d_POST, LD1Onev2s_POST, LD1Onev4h_POST, LD1Onev8b_POST, LD1Rv1...
+    printPostIncOperand2(MI, 3, O, 8); 
+    return;
+    break;
+  case 18:
+    // LD1Rv16b_POST, LD1Rv8b_POST
+    printPostIncOperand2(MI, 3, O, 1); 
+    return;
+    break;
+  case 19:
+    // LD1Rv2s_POST, LD1Rv4s_POST, LD2Rv4h_POST, LD2Rv8h_POST, LD4Rv16b_POST,...
+    printPostIncOperand2(MI, 3, O, 4); 
+    return;
+    break;
+  case 20:
+    // LD1Rv4h_POST, LD1Rv8h_POST, LD2Rv16b_POST, LD2Rv8b_POST
+    printPostIncOperand2(MI, 3, O, 2); 
+    return;
+    break;
+  case 21:
+    // LD1Threev16b_POST, LD1Threev2d_POST, LD1Threev4s_POST, LD1Threev8h_POS...
+    printPostIncOperand2(MI, 3, O, 48); 
+    return;
+    break;
+  case 22:
+    // LD1Threev1d_POST, LD1Threev2s_POST, LD1Threev4h_POST, LD1Threev8b_POST...
+    printPostIncOperand2(MI, 3, O, 24); 
+    return;
+    break;
+  case 23:
+    // LD1i16, LD1i32, LD1i64, LD1i8, LD2i16, LD2i32, LD2i64, LD2i8, LD3i16, ...
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 24:
+    // LD1i16_POST, LD2i8_POST
+    printPostIncOperand2(MI, 5, O, 2); 
+    return;
+    break;
+  case 25:
+    // LD1i32_POST, LD2i16_POST, LD4i8_POST
+    printPostIncOperand2(MI, 5, O, 4); 
+    return;
+    break;
+  case 26:
+    // LD1i64_POST, LD2i32_POST, LD4i16_POST
+    printPostIncOperand2(MI, 5, O, 8); 
+    return;
+    break;
+  case 27:
+    // LD1i8_POST
+    printPostIncOperand2(MI, 5, O, 1); 
+    return;
+    break;
+  case 28:
+    // LD2i64_POST, LD4i32_POST
+    printPostIncOperand2(MI, 5, O, 16); 
+    return;
+    break;
+  case 29:
+    // LD3Rv16b_POST, LD3Rv8b_POST
+    printPostIncOperand2(MI, 3, O, 3); 
+    return;
+    break;
+  case 30:
+    // LD3Rv2s_POST, LD3Rv4s_POST
+    printPostIncOperand2(MI, 3, O, 12); 
+    return;
+    break;
+  case 31:
+    // LD3Rv4h_POST, LD3Rv8h_POST
+    printPostIncOperand2(MI, 3, O, 6); 
+    return;
+    break;
+  case 32:
+    // LD3i16_POST
+    printPostIncOperand2(MI, 5, O, 6); 
+    return;
+    break;
+  case 33:
+    // LD3i32_POST
+    printPostIncOperand2(MI, 5, O, 12); 
+    return;
+    break;
+  case 34:
+    // LD3i64_POST
+    printPostIncOperand2(MI, 5, O, 24); 
+    return;
+    break;
+  case 35:
+    // LD3i8_POST
+    printPostIncOperand2(MI, 5, O, 3); 
+    return;
+    break;
+  case 36:
+    // LD4i64_POST
+    printPostIncOperand2(MI, 5, O, 32); 
+    return;
+    break;
+  case 37:
+    // LDARB, LDARH, LDARW, LDARX, LDAXRB, LDAXRH, LDAXRW, LDAXRX, LDRBBpost,...
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    break;
+  case 38:
+    // PMULLv1i64, PMULLv2i64
+    SStream_concat0(O, ".1q, ");
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1Q);
+    printVRegOperand(MI, 1, O); 
+    break;
+  case 39:
+    // SADALPv2i32_v1i64, SADDLPv2i32_v1i64, UADALPv2i32_v1i64, UADDLPv2i32_v...
+    SStream_concat0(O, ".1d, ");
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D);
+    break;
+  case 40:
+    // ST1i16_POST, ST1i32_POST, ST1i64_POST, ST1i8_POST, ST2i16_POST, ST2i32...
+    SStream_concat0(O, "], "); 
+    set_mem_access(MI, false);
+    break;
+  }
+
+
+  // Fragment 2 encoded into 5 bits for 28 unique commands.
+  //printf("Frag-2: %"PRIu64"\n", (Bits >> 24) & 31);
+  switch ((Bits >> 24) & 31) {
+  default:   // unreachable.
+  case 0:
+    // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A...
+    printVRegOperand(MI, 1, O); 
+    break;
+  case 1:
+    // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDSWri, ADDSWrs, ADDSWrx, ADD...
+    printOperand(MI, 1, O); 
+    break;
+  case 2:
+    // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ...
+    printVRegOperand(MI, 2, O); 
+    break;
+  case 3:
+    // ADRP
+    printAdrpLabel(MI, 1, O); 
+    return;
+    break;
+  case 4:
+    // BFMWri, BFMXri, FMLAv1i32_indexed, FMLAv1i64_indexed, FMLSv1i32_indexe...
+    printOperand(MI, 2, O); 
+    break;
+  case 5:
+    // BICv2i32, BICv4i16, BICv4i32, BICv8i16, MOVKWi, MOVKXi, ORRv2i32, ORRv...
+    printHexImm(MI, 2, O); 
+    printShifter(MI, 3, O); 
+    return;
+    break;
+  case 6:
+    // CBNZW, CBNZX, CBZW, CBZX, LDRDl, LDRQl, LDRSWl, LDRSl, LDRWl, LDRXl, P...
+    printAlignedLabel(MI, 1, O); 
+    return;
+    break;
+  case 7:
+    // FMOVDi, FMOVSi, FMOVv2f32_ns, FMOVv2f64_ns, FMOVv4f32_ns
+    printFPImmOperand(MI, 1, O); 
+    return;
+    break;
+  case 8:
+    // INSvi16gpr, INSvi32gpr, INSvi64gpr, INSvi8gpr
+    printOperand(MI, 3, O); 
+    return;
+    break;
+  case 9:
+    // INSvi16lane, INSvi32lane, INSvi64lane, INSvi8lane
+    printVRegOperand(MI, 3, O); 
+    break;
+  case 10:
+    // MOVID, MOVIv2d_ns
+    printSIMDType10Operand(MI, 1, O); 
+    return;
+    break;
+  case 11:
+    // MOVIv16b_ns, MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl...
+    printHexImm(MI, 1, O); 
+    break;
+  case 12:
+    // MRS
+    printMRSSystemRegister(MI, 1, O); 
+    return;
+    break;
+  case 13:
+    // PMULLv1i64
+    SStream_concat0(O, ".1d, "); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D);
+    printVRegOperand(MI, 2, O); 
+    SStream_concat0(O, ".1d"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D);
+    return;
+    break;
+  case 14:
+    // PMULLv2i64
+    SStream_concat0(O, ".2d, "); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D);
+    printVRegOperand(MI, 2, O); 
+    SStream_concat0(O, ".2d"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D);
+    return;
+    break;
+  case 15:
+    // ST1i16_POST, ST2i8_POST
+    printPostIncOperand2(MI, 4, O, 2); 
+    return;
+    break;
+  case 16:
+    // ST1i32_POST, ST2i16_POST, ST4i8_POST
+    printPostIncOperand2(MI, 4, O, 4); 
+    return;
+    break;
+  case 17:
+    // ST1i64_POST, ST2i32_POST, ST4i16_POST
+    printPostIncOperand2(MI, 4, O, 8); 
+    return;
+    break;
+  case 18:
+    // ST1i8_POST
+    printPostIncOperand2(MI, 4, O, 1); 
+    return;
+    break;
+  case 19:
+    // ST2i64_POST, ST4i32_POST
+    printPostIncOperand2(MI, 4, O, 16); 
+    return;
+    break;
+  case 20:
+    // ST3i16_POST
+    printPostIncOperand2(MI, 4, O, 6); 
+    return;
+    break;
+  case 21:
+    // ST3i32_POST
+    printPostIncOperand2(MI, 4, O, 12); 
+    return;
+    break;
+  case 22:
+    // ST3i64_POST
+    printPostIncOperand2(MI, 4, O, 24); 
+    return;
+    break;
+  case 23:
+    // ST3i8_POST
+    printPostIncOperand2(MI, 4, O, 3); 
+    return;
+    break;
+  case 24:
+    // ST4i64_POST
+    printPostIncOperand2(MI, 4, O, 32); 
+    return;
+    break;
+  case 25:
+    // SYSxt
+    printSysCROperand(MI, 1, O); 
+    SStream_concat0(O, ", "); 
+    printSysCROperand(MI, 2, O); 
+    SStream_concat0(O, ", "); 
+    printOperand(MI, 3, O); 
+    SStream_concat0(O, ", "); 
+    printOperand(MI, 4, O); 
+    return;
+    break;
+  case 26:
+    // TBLv16i8Four, TBLv16i8One, TBLv16i8Three, TBLv16i8Two, TBLv8i8Four, TB...
+    printTypedVectorList(MI, 1, O, 16, 'b', MRI); 
+    SStream_concat0(O, ", "); 
+    printVRegOperand(MI, 2, O); 
+    break;
+  case 27:
+    // TBXv16i8Four, TBXv16i8One, TBXv16i8Three, TBXv16i8Two, TBXv8i8Four, TB...
+    printTypedVectorList(MI, 2, O, 16, 'b', MRI); 
+    SStream_concat0(O, ", "); 
+    printVRegOperand(MI, 3, O); 
+    break;
+  }
+
+
+  // Fragment 3 encoded into 6 bits for 42 unique commands.
+  //printf("Frag-3: %"PRIu64"\n", (Bits >> 29) & 63);
+  switch ((Bits >> 29) & 63) {
+  default:   // unreachable.
+  case 0:
+    // ABSv16i8, ADDVv16i8v, AESDrr, AESErr, AESIMCrr, AESMCrr, CLSv16i8, CLZ...
+    SStream_concat0(O, ".16b"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B);
+    return;
+    break;
+  case 1:
+    // ABSv1i64, ADR, CLSWr, CLSXr, CLZWr, CLZXr, DUPv16i8gpr, DUPv2i32gpr, D...
+    return;
+    break;
+  case 2:
+    // ABSv2i32, CLSv2i32, CLZv2i32, FABSv2f32, FADDPv2i32p, FCVTASv2f32, FCV...
+    SStream_concat0(O, ".2s"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S);
+    return;
+    break;
+  case 3:
+    // ABSv2i64, ADDPv2i64p, FABSv2f64, FADDPv2i64p, FCVTASv2f64, FCVTAUv2f64...
+    SStream_concat0(O, ".2d"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D);
+    return;
+    break;
+  case 4:
+    // ABSv4i16, ADDVv4i16v, CLSv4i16, CLZv4i16, FCVTLv4i16, NEGv4i16, REV32v...
+    SStream_concat0(O, ".4h"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H);
+    return;
+    break;
+  case 5:
+    // ABSv4i32, ADDVv4i32v, CLSv4i32, CLZv4i32, FABSv4f32, FCVTASv4f32, FCVT...
+    SStream_concat0(O, ".4s"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S);
+    return;
+    break;
+  case 6:
+    // ABSv8i16, ADDVv8i16v, CLSv8i16, CLZv8i16, FCVTLv8i16, NEGv8i16, REV32v...
+    SStream_concat0(O, ".8h"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H);
+    return;
+    break;
+  case 7:
+    // ABSv8i8, ADDVv8i8v, CLSv8i8, CLZv8i8, CNTv8i8, NEGv8i8, NOTv8i8, RBITv...
+    SStream_concat0(O, ".8b"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B);
+    return;
+    break;
+  case 8:
+    // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDSWri, ADDSWrs, ADDSWrx, ADDSXri, ADDS...
+    SStream_concat0(O, ", "); 
+    break;
+  case 9:
+    // ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM...
+    SStream_concat0(O, ".2d, "); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D);
+    break;
+  case 10:
+    // ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM...
+    SStream_concat0(O, ".4s, "); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S);
+    break;
+  case 11:
+    // ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, CMEQv8i16, CMG...
+    SStream_concat0(O, ".8h, "); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H);
+    break;
+  case 12:
+    // ADDPv16i8, ADDv16i8, ANDv16i8, BICv16i8, BIFv16i8, BITv16i8, BSLv16i8,...
+    SStream_concat0(O, ".16b, "); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B);
+    break;
+  case 13:
+    // ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv...
+    SStream_concat0(O, ".2s, "); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S);
+    break;
+  case 14:
+    // ADDPv4i16, ADDv4i16, CMEQv4i16, CMGEv4i16, CMGTv4i16, CMHIv4i16, CMHSv...
+    SStream_concat0(O, ".4h, "); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H);
+    break;
+  case 15:
+    // ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8...
+    SStream_concat0(O, ".8b, "); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B);
+    break;
+  case 16:
+    // CMEQv16i8rz, CMGEv16i8rz, CMGTv16i8rz, CMLEv16i8rz, CMLTv16i8rz
+    SStream_concat0(O, ".16b, #0"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B);
+	arm64_op_addFP(MI, 0.0);
+    return;
+    break;
+  case 17:
+    // CMEQv1i64rz, CMGEv1i64rz, CMGTv1i64rz, CMLEv1i64rz, CMLTv1i64rz
+    SStream_concat0(O, ", #0"); 
+	arm64_op_addImm(MI, 0);
+    return;
+    break;
+  case 18:
+    // CMEQv2i32rz, CMGEv2i32rz, CMGTv2i32rz, CMLEv2i32rz, CMLTv2i32rz
+    SStream_concat0(O, ".2s, #0"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S);
+	arm64_op_addImm(MI, 0);
+    return;
+    break;
+  case 19:
+    // CMEQv2i64rz, CMGEv2i64rz, CMGTv2i64rz, CMLEv2i64rz, CMLTv2i64rz
+    SStream_concat0(O, ".2d, #0"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D);
+	arm64_op_addImm(MI, 0);
+    return;
+    break;
+  case 20:
+    // CMEQv4i16rz, CMGEv4i16rz, CMGTv4i16rz, CMLEv4i16rz, CMLTv4i16rz
+    SStream_concat0(O, ".4h, #0"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H);
+	arm64_op_addImm(MI, 0);
+    return;
+    break;
+  case 21:
+    // CMEQv4i32rz, CMGEv4i32rz, CMGTv4i32rz, CMLEv4i32rz, CMLTv4i32rz
+    SStream_concat0(O, ".4s, #0"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S);
+	arm64_op_addImm(MI, 0);
+    return;
+    break;
+  case 22:
+    // CMEQv8i16rz, CMGEv8i16rz, CMGTv8i16rz, CMLEv8i16rz, CMLTv8i16rz
+    SStream_concat0(O, ".8h, #0"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H);
+	arm64_op_addImm(MI, 0);
+    return;
+    break;
+  case 23:
+    // CMEQv8i8rz, CMGEv8i8rz, CMGTv8i8rz, CMLEv8i8rz, CMLTv8i8rz
+    SStream_concat0(O, ".8b, #0"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B);
+	arm64_op_addImm(MI, 0);
+    return;
+    break;
+  case 24:
+    // CPYi16, DUPv4i16lane, DUPv8i16lane, INSvi16lane, SMOVvi16to32, SMOVvi1...
+    SStream_concat0(O, ".h"); 
+	arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_H);
+    break;
+  case 25:
+    // CPYi32, DUPv2i32lane, DUPv4i32lane, INSvi32lane, SMOVvi32to64, UMOVvi3...
+    SStream_concat0(O, ".s"); 
+	arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_S);
+    break;
+  case 26:
+    // CPYi64, DUPv2i64lane, FMOVDXHighr, INSvi64lane, UMOVvi64
+    SStream_concat0(O, ".d"); 
+	arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_D);
+    break;
+  case 27:
+    // CPYi8, DUPv16i8lane, DUPv8i8lane, INSvi8lane, SMOVvi8to32, SMOVvi8to64...
+    SStream_concat0(O, ".b"); 
+	arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_B);
+    break;
+  case 28:
+    // FCMEQv1i32rz, FCMEQv1i64rz, FCMGEv1i32rz, FCMGEv1i64rz, FCMGTv1i32rz, ...
+    SStream_concat0(O, ", #0.0"); 
+	arm64_op_addFP(MI, 0.0);
+    return;
+    break;
+  case 29:
+    // FCMEQv2i32rz, FCMGEv2i32rz, FCMGTv2i32rz, FCMLEv2i32rz, FCMLTv2i32rz
+    SStream_concat0(O, ".2s, #0.0"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S);
+	arm64_op_addFP(MI, 0.0);
+    return;
+    break;
+  case 30:
+    // FCMEQv2i64rz, FCMGEv2i64rz, FCMGTv2i64rz, FCMLEv2i64rz, FCMLTv2i64rz
+    SStream_concat0(O, ".2d, #0.0"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D);
+	arm64_op_addFP(MI, 0.0);
+    return;
+    break;
+  case 31:
+    // FCMEQv4i32rz, FCMGEv4i32rz, FCMGTv4i32rz, FCMLEv4i32rz, FCMLTv4i32rz
+    SStream_concat0(O, ".4s, #0.0"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S);
+	arm64_op_addFP(MI, 0.0);
+    return;
+    break;
+  case 32:
+    // LDARB, LDARH, LDARW, LDARX, LDAXRB, LDAXRH, LDAXRW, LDAXRX, LDXRB, LDX...
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 33:
+    // LDAXPW, LDAXPX, LDNPDi, LDNPQi, LDNPSi, LDNPWi, LDNPXi, LDPDi, LDPDpos...
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    break;
+  case 34:
+    // LDRBBpost, LDRBpost, LDRDpost, LDRHHpost, LDRHpost, LDRQpost, LDRSBWpo...
+    SStream_concat0(O, "], "); 
+    set_mem_access(MI, false);
+    printOperand(MI, 3, O); 
+    return;
+    break;
+  case 35:
+    // MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl, MOVIv8i16, ...
+    printShifter(MI, 2, O); 
+    return;
+    break;
+  case 36:
+    // SHLLv16i8
+    SStream_concat0(O, ".16b, #8"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B);
+	arm64_op_addImm(MI, 8);
+    return;
+    break;
+  case 37:
+    // SHLLv2i32
+    SStream_concat0(O, ".2s, #32"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S);
+	arm64_op_addImm(MI, 32);
+    return;
+    break;
+  case 38:
+    // SHLLv4i16
+    SStream_concat0(O, ".4h, #16"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H);
+	arm64_op_addImm(MI, 16);
+    return;
+    break;
+  case 39:
+    // SHLLv4i32
+    SStream_concat0(O, ".4s, #32"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S);
+	arm64_op_addImm(MI, 32);
+    return;
+    break;
+  case 40:
+    // SHLLv8i16
+    SStream_concat0(O, ".8h, #16"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H);
+	arm64_op_addImm(MI, 16);
+    return;
+    break;
+  case 41:
+    // SHLLv8i8
+    SStream_concat0(O, ".8b, #8"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B);
+	arm64_op_addImm(MI, 8);
+    return;
+    break;
+  }
+
+
+  // Fragment 4 encoded into 5 bits for 18 unique commands.
+  //printf("Frag-4: %"PRIu64"\n", (Bits >> 35) & 31);
+  switch ((Bits >> 35) & 31) {
+  default:   // unreachable.
+  case 0:
+    // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDSXrx64, ADDXrx64, ADDv1i64, ASRVWr, A...
+    printOperand(MI, 2, O); 
+    break;
+  case 1:
+    // ADDHNv2i64_v2i32, ADDHNv4i32_v4i16, ADDHNv8i16_v8i8, ADDPv16i8, ADDPv2...
+    printVRegOperand(MI, 2, O); 
+    break;
+  case 2:
+    // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, BITv16i8, BITv8i...
+    printVRegOperand(MI, 3, O); 
+    break;
+  case 3:
+    // ADDSWri, ADDSXri, ADDWri, ADDXri, SUBSWri, SUBSXri, SUBWri, SUBXri
+    printAddSubImm(MI, 2, O); 
+    return;
+    break;
+  case 4:
+    // ADDSWrs, ADDSXrs, ADDWrs, ADDXrs, ANDSWrs, ANDSXrs, ANDWrs, ANDXrs, BI...
+    printShiftedRegister(MI, 2, O); 
+    return;
+    break;
+  case 5:
+    // ADDSWrx, ADDSXrx, ADDWrx, ADDXrx, SUBSWrx, SUBSXrx, SUBWrx, SUBXrx
+    printExtendedRegister(MI, 2, O); 
+    return;
+    break;
+  case 6:
+    // ANDSWri, ANDWri, EORWri, ORRWri
+    printLogicalImm32(MI, 2, O); 
+    return;
+    break;
+  case 7:
+    // ANDSXri, ANDXri, EORXri, ORRXri
+    printLogicalImm64(MI, 2, O); 
+    return;
+    break;
+  case 8:
+    // BFMWri, BFMXri, LDPDpost, LDPDpre, LDPQpost, LDPQpre, LDPSWpost, LDPSW...
+    printOperand(MI, 3, O); 
+    break;
+  case 9:
+    // CPYi16, CPYi32, CPYi64, CPYi8, DUPv16i8lane, DUPv2i32lane, DUPv2i64lan...
+    printVectorIndex(MI, 2, O); 
+    return;
+    break;
+  case 10:
+    // INSvi16lane, INSvi32lane, INSvi64lane, INSvi8lane
+    printVectorIndex(MI, 4, O); 
+    return;
+    break;
+  case 11:
+    // LDRBBui, LDRBui, LDRSBWui, LDRSBXui, STRBBui, STRBui
+    printUImm12Offset2(MI, 2, O, 1); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 12:
+    // LDRDui, LDRXui, PRFMui, STRDui, STRXui
+    printUImm12Offset2(MI, 2, O, 8); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 13:
+    // LDRHHui, LDRHui, LDRSHWui, LDRSHXui, STRHHui, STRHui
+    printUImm12Offset2(MI, 2, O, 2); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 14:
+    // LDRQui, STRQui
+    printUImm12Offset2(MI, 2, O, 16); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 15:
+    // LDRSWui, LDRSui, LDRWui, STRSui, STRWui
+    printUImm12Offset2(MI, 2, O, 4); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 16:
+    // SYSLxt
+    printSysCROperand(MI, 2, O); 
+    SStream_concat0(O, ", "); 
+    printSysCROperand(MI, 3, O); 
+    SStream_concat0(O, ", "); 
+    printOperand(MI, 4, O); 
+    return;
+    break;
+  case 17:
+    // TBNZW, TBNZX, TBZW, TBZX
+    printAlignedLabel(MI, 2, O); 
+    return;
+    break;
+  }
+
+
+  // Fragment 5 encoded into 5 bits for 19 unique commands.
+  //printf("Frag-5: %"PRIu64"\n", (Bits >> 40) & 31);
+  switch ((Bits >> 40) & 31) {
+  default:   // unreachable.
+  case 0:
+    // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDv1i64, ASRVWr, ASRVXr, CMEQv1i64, CMG...
+    return;
+    break;
+  case 1:
+    // ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM...
+    SStream_concat0(O, ".2d"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D);
+    return;
+    break;
+  case 2:
+    // ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM...
+    SStream_concat0(O, ".4s"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S);
+    return;
+    break;
+  case 3:
+    // ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, CMEQv8i16, CMG...
+    SStream_concat0(O, ".8h"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H);
+    return;
+    break;
+  case 4:
+    // ADDPv16i8, ADDv16i8, ANDv16i8, BICv16i8, BIFv16i8, BITv16i8, BSLv16i8,...
+    SStream_concat0(O, ".16b"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B);
+    return;
+    break;
+  case 5:
+    // ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv...
+    SStream_concat0(O, ".2s"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S);
+    return;
+    break;
+  case 6:
+    // ADDPv4i16, ADDv4i16, CMEQv4i16, CMGEv4i16, CMGTv4i16, CMHIv4i16, CMHSv...
+    SStream_concat0(O, ".4h"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H);
+    return;
+    break;
+  case 7:
+    // ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8...
+    SStream_concat0(O, ".8b"); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B);
+    return;
+    break;
+  case 8:
+    // ADDSXrx64, ADDXrx64, SUBSXrx64, SUBXrx64
+    printArithExtend(MI, 3, O); 
+    return;
+    break;
+  case 9:
+    // BFMWri, BFMXri, CCMNWi, CCMNWr, CCMNXi, CCMNXr, CCMPWi, CCMPWr, CCMPXi...
+    SStream_concat0(O, ", "); 
+    break;
+  case 10:
+    // EXTv16i8
+    SStream_concat0(O, ".16b, "); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B);
+    printOperand(MI, 3, O); 
+    return;
+    break;
+  case 11:
+    // EXTv8i8
+    SStream_concat0(O, ".8b, "); 
+	arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B);
+    printOperand(MI, 3, O); 
+    return;
+    break;
+  case 12:
+    // FMLAv1i32_indexed, FMLAv2i32_indexed, FMLAv4i32_indexed, FMLSv1i32_ind...
+    SStream_concat0(O, ".s"); 
+	arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_S);
+    break;
+  case 13:
+    // FMLAv1i64_indexed, FMLAv2i64_indexed, FMLSv1i64_indexed, FMLSv2i64_ind...
+    SStream_concat0(O, ".d"); 
+	arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_D);
+    break;
+  case 14:
+    // LDAXPW, LDAXPX, LDTRBi, LDTRHi, LDTRSBWi, LDTRSBXi, LDTRSHWi, LDTRSHXi...
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 15:
+    // LDPDpost, LDPQpost, LDPSWpost, LDPSpost, LDPWpost, LDPXpost, STPDpost,...
+    SStream_concat0(O, "], "); 
+    set_mem_access(MI, false);
+    break;
+  case 16:
+    // LDRBBpre, LDRBpre, LDRDpre, LDRHHpre, LDRHpre, LDRQpre, LDRSBWpre, LDR...
+    SStream_concat0(O, "]!"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 17:
+    // MLAv4i16_indexed, MLAv8i16_indexed, MLSv4i16_indexed, MLSv8i16_indexed...
+    SStream_concat0(O, ".h"); 
+	arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_H);
+    break;
+  case 18:
+    // STLXPW, STLXPX, STXPW, STXPX
+    SStream_concat0(O, ", ["); 
+    set_mem_access(MI, true);
+    printOperand(MI, 3, O); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  }
+
+
+  // Fragment 6 encoded into 5 bits for 21 unique commands.
+  //printf("Frag-6: %"PRIu64"\n", (Bits >> 45) & 31);
+  switch ((Bits >> 45) & 31) {
+  default:   // unreachable.
+  case 0:
+    // BFMWri, BFMXri
+    printOperand(MI, 4, O); 
+    return;
+    break;
+  case 1:
+    // CCMNWi, CCMNWr, CCMNXi, CCMNXr, CCMPWi, CCMPWr, CCMPXi, CCMPXr, CSELWr...
+    printCondCode(MI, 3, O); 
+    return;
+    break;
+  case 2:
+    // EXTRWrri, EXTRXrri, FMADDDrrr, FMADDSrrr, FMSUBDrrr, FMSUBSrrr, FNMADD...
+    printOperand(MI, 3, O); 
+    return;
+    break;
+  case 3:
+    // FMLAv1i32_indexed, FMLAv1i64_indexed, FMLAv2i32_indexed, FMLAv2i64_ind...
+    printVectorIndex(MI, 4, O); 
+    return;
+    break;
+  case 4:
+    // FMULXv1i32_indexed, FMULXv1i64_indexed, FMULXv2i32_indexed, FMULXv2i64...
+    printVectorIndex(MI, 3, O); 
+    return;
+    break;
+  case 5:
+    // LDNPDi, LDNPXi, LDPDi, LDPXi, STNPDi, STNPXi, STPDi, STPXi
+    printImmScale(MI, 3, O, 8); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 6:
+    // LDNPQi, LDPQi, STNPQi, STPQi
+    printImmScale(MI, 3, O, 16); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 7:
+    // LDNPSi, LDNPWi, LDPSWi, LDPSi, LDPWi, STNPSi, STNPWi, STPSi, STPWi
+    printImmScale(MI, 3, O, 4); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 8:
+    // LDPDpost, LDPDpre, LDPXpost, LDPXpre, STPDpost, STPDpre, STPXpost, STP...
+    printImmScale(MI, 4, O, 8); 
+    break;
+  case 9:
+    // LDPQpost, LDPQpre, STPQpost, STPQpre
+    printImmScale(MI, 4, O, 16); 
+    break;
+  case 10:
+    // LDPSWpost, LDPSWpre, LDPSpost, LDPSpre, LDPWpost, LDPWpre, STPSpost, S...
+    printImmScale(MI, 4, O, 4); 
+    break;
+  case 11:
+    // LDRBBroW, LDRBroW, LDRSBWroW, LDRSBXroW, STRBBroW, STRBroW
+    printMemExtend(MI, 3, O, 'w', 8); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 12:
+    // LDRBBroX, LDRBroX, LDRSBWroX, LDRSBXroX, STRBBroX, STRBroX
+    printMemExtend(MI, 3, O, 'x', 8); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 13:
+    // LDRDroW, LDRXroW, PRFMroW, STRDroW, STRXroW
+    printMemExtend(MI, 3, O, 'w', 64); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 14:
+    // LDRDroX, LDRXroX, PRFMroX, STRDroX, STRXroX
+    printMemExtend(MI, 3, O, 'x', 64); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 15:
+    // LDRHHroW, LDRHroW, LDRSHWroW, LDRSHXroW, STRHHroW, STRHroW
+    printMemExtend(MI, 3, O, 'w', 16); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 16:
+    // LDRHHroX, LDRHroX, LDRSHWroX, LDRSHXroX, STRHHroX, STRHroX
+    printMemExtend(MI, 3, O, 'x', 16); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 17:
+    // LDRQroW, STRQroW
+    printMemExtend(MI, 3, O, 'w', 128); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 18:
+    // LDRQroX, STRQroX
+    printMemExtend(MI, 3, O, 'x', 128); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 19:
+    // LDRSWroW, LDRSroW, LDRWroW, STRSroW, STRWroW
+    printMemExtend(MI, 3, O, 'w', 32); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  case 20:
+    // LDRSWroX, LDRSroX, LDRWroX, STRSroX, STRWroX
+    printMemExtend(MI, 3, O, 'x', 32); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false);
+    return;
+    break;
+  }
+
+
+  // Fragment 7 encoded into 1 bits for 2 unique commands.
+  //printf("Frag-7: %"PRIu64"\n", (Bits >> 50) & 1);
+  if ((Bits >> 50) & 1) {
+    // LDPDpre, LDPQpre, LDPSWpre, LDPSpre, LDPWpre, LDPXpre, STPDpre, STPQpr...
+    SStream_concat0(O, "]!"); 
+    set_mem_access(MI, false);
+    return;
+  } else {
+    // LDPDpost, LDPQpost, LDPSWpost, LDPSpost, LDPWpost, LDPXpost, STPDpost,...
+    return;
+  }
+}
+
+
+/// getRegisterName - This method is automatically generated by tblgen
+/// from the register set description.  This returns the assembler name
+/// for the specified register.
+static char *getRegisterName(unsigned RegNo, int AltIdx)
+{
+  // assert(RegNo && RegNo < 420 && "Invalid register number!");
+
+#ifndef CAPSTONE_DIET
+  static char AsmStrsNoRegAltName[] = {
+  /* 0 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
+  /* 13 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
+  /* 26 */ 'b', '1', '0', 0,
+  /* 30 */ 'd', '1', '0', 0,
+  /* 34 */ 'h', '1', '0', 0,
+  /* 38 */ 'q', '1', '0', 0,
+  /* 42 */ 's', '1', '0', 0,
+  /* 46 */ 'w', '1', '0', 0,
+  /* 50 */ 'x', '1', '0', 0,
+  /* 54 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0,
+  /* 70 */ 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', 0,
+  /* 86 */ 'b', '2', '0', 0,
+  /* 90 */ 'd', '2', '0', 0,
+  /* 94 */ 'h', '2', '0', 0,
+  /* 98 */ 'q', '2', '0', 0,
+  /* 102 */ 's', '2', '0', 0,
+  /* 106 */ 'w', '2', '0', 0,
+  /* 110 */ 'x', '2', '0', 0,
+  /* 114 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0,
+  /* 130 */ 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', 0,
+  /* 146 */ 'b', '3', '0', 0,
+  /* 150 */ 'd', '3', '0', 0,
+  /* 154 */ 'h', '3', '0', 0,
+  /* 158 */ 'q', '3', '0', 0,
+  /* 162 */ 's', '3', '0', 0,
+  /* 166 */ 'w', '3', '0', 0,
+  /* 170 */ 'x', '3', '0', 0,
+  /* 174 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', 0,
+  /* 189 */ 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', 0,
+  /* 204 */ 'b', '0', 0,
+  /* 207 */ 'd', '0', 0,
+  /* 210 */ 'h', '0', 0,
+  /* 213 */ 'q', '0', 0,
+  /* 216 */ 's', '0', 0,
+  /* 219 */ 'w', '0', 0,
+  /* 222 */ 'x', '0', 0,
+  /* 225 */ 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0,
+  /* 239 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0,
+  /* 253 */ 'b', '1', '1', 0,
+  /* 257 */ 'd', '1', '1', 0,
+  /* 261 */ 'h', '1', '1', 0,
+  /* 265 */ 'q', '1', '1', 0,
+  /* 269 */ 's', '1', '1', 0,
+  /* 273 */ 'w', '1', '1', 0,
+  /* 277 */ 'x', '1', '1', 0,
+  /* 281 */ 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0,
+  /* 297 */ 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', 0,
+  /* 313 */ 'b', '2', '1', 0,
+  /* 317 */ 'd', '2', '1', 0,
+  /* 321 */ 'h', '2', '1', 0,
+  /* 325 */ 'q', '2', '1', 0,
+  /* 329 */ 's', '2', '1', 0,
+  /* 333 */ 'w', '2', '1', 0,
+  /* 337 */ 'x', '2', '1', 0,
+  /* 341 */ 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0,
+  /* 357 */ 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', 0,
+  /* 373 */ 'b', '3', '1', 0,
+  /* 377 */ 'd', '3', '1', 0,
+  /* 381 */ 'h', '3', '1', 0,
+  /* 385 */ 'q', '3', '1', 0,
+  /* 389 */ 's', '3', '1', 0,
+  /* 393 */ 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', 0,
+  /* 407 */ 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', 0,
+  /* 421 */ 'b', '1', 0,
+  /* 424 */ 'd', '1', 0,
+  /* 427 */ 'h', '1', 0,
+  /* 430 */ 'q', '1', 0,
+  /* 433 */ 's', '1', 0,
+  /* 436 */ 'w', '1', 0,
+  /* 439 */ 'x', '1', 0,
+  /* 442 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0,
+  /* 457 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0,
+  /* 472 */ 'b', '1', '2', 0,
+  /* 476 */ 'd', '1', '2', 0,
+  /* 480 */ 'h', '1', '2', 0,
+  /* 484 */ 'q', '1', '2', 0,
+  /* 488 */ 's', '1', '2', 0,
+  /* 492 */ 'w', '1', '2', 0,
+  /* 496 */ 'x', '1', '2', 0,
+  /* 500 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0,
+  /* 516 */ 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', 0,
+  /* 532 */ 'b', '2', '2', 0,
+  /* 536 */ 'd', '2', '2', 0,
+  /* 540 */ 'h', '2', '2', 0,
+  /* 544 */ 'q', '2', '2', 0,
+  /* 548 */ 's', '2', '2', 0,
+  /* 552 */ 'w', '2', '2', 0,
+  /* 556 */ 'x', '2', '2', 0,
+  /* 560 */ 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', '_', 'D', '2', 0,
+  /* 573 */ 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', 0,
+  /* 586 */ 'b', '2', 0,
+  /* 589 */ 'd', '2', 0,
+  /* 592 */ 'h', '2', 0,
+  /* 595 */ 'q', '2', 0,
+  /* 598 */ 's', '2', 0,
+  /* 601 */ 'w', '2', 0,
+  /* 604 */ 'x', '2', 0,
+  /* 607 */ 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0,
+  /* 623 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0,
+  /* 639 */ 'b', '1', '3', 0,
+  /* 643 */ 'd', '1', '3', 0,
+  /* 647 */ 'h', '1', '3', 0,
+  /* 651 */ 'q', '1', '3', 0,
+  /* 655 */ 's', '1', '3', 0,
+  /* 659 */ 'w', '1', '3', 0,
+  /* 663 */ 'x', '1', '3', 0,
+  /* 667 */ 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0,
+  /* 683 */ 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', 0,
+  /* 699 */ 'b', '2', '3', 0,
+  /* 703 */ 'd', '2', '3', 0,
+  /* 707 */ 'h', '2', '3', 0,
+  /* 711 */ 'q', '2', '3', 0,
+  /* 715 */ 's', '2', '3', 0,
+  /* 719 */ 'w', '2', '3', 0,
+  /* 723 */ 'x', '2', '3', 0,
+  /* 727 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', '_', 'D', '3', 0,
+  /* 739 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0,
+  /* 751 */ 'b', '3', 0,
+  /* 754 */ 'd', '3', 0,
+  /* 757 */ 'h', '3', 0,
+  /* 760 */ 'q', '3', 0,
+  /* 763 */ 's', '3', 0,
+  /* 766 */ 'w', '3', 0,
+  /* 769 */ 'x', '3', 0,
+  /* 772 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0,
+  /* 788 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0,
+  /* 804 */ 'b', '1', '4', 0,
+  /* 808 */ 'd', '1', '4', 0,
+  /* 812 */ 'h', '1', '4', 0,
+  /* 816 */ 'q', '1', '4', 0,
+  /* 820 */ 's', '1', '4', 0,
+  /* 824 */ 'w', '1', '4', 0,
+  /* 828 */ 'x', '1', '4', 0,
+  /* 832 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0,
+  /* 848 */ 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', 0,
+  /* 864 */ 'b', '2', '4', 0,
+  /* 868 */ 'd', '2', '4', 0,
+  /* 872 */ 'h', '2', '4', 0,
+  /* 876 */ 'q', '2', '4', 0,
+  /* 880 */ 's', '2', '4', 0,
+  /* 884 */ 'w', '2', '4', 0,
+  /* 888 */ 'x', '2', '4', 0,
+  /* 892 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0,
+  /* 904 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0,
+  /* 916 */ 'b', '4', 0,
+  /* 919 */ 'd', '4', 0,
+  /* 922 */ 'h', '4', 0,
+  /* 925 */ 'q', '4', 0,
+  /* 928 */ 's', '4', 0,
+  /* 931 */ 'w', '4', 0,
+  /* 934 */ 'x', '4', 0,
+  /* 937 */ 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0,
+  /* 953 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0,
+  /* 969 */ 'b', '1', '5', 0,
+  /* 973 */ 'd', '1', '5', 0,
+  /* 977 */ 'h', '1', '5', 0,
+  /* 981 */ 'q', '1', '5', 0,
+  /* 985 */ 's', '1', '5', 0,
+  /* 989 */ 'w', '1', '5', 0,
+  /* 993 */ 'x', '1', '5', 0,
+  /* 997 */ 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0,
+  /* 1013 */ 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', 0,
+  /* 1029 */ 'b', '2', '5', 0,
+  /* 1033 */ 'd', '2', '5', 0,
+  /* 1037 */ 'h', '2', '5', 0,
+  /* 1041 */ 'q', '2', '5', 0,
+  /* 1045 */ 's', '2', '5', 0,
+  /* 1049 */ 'w', '2', '5', 0,
+  /* 1053 */ 'x', '2', '5', 0,
+  /* 1057 */ 'D', '2', '_', 'D', '3', '_', 'D', '4', '_', 'D', '5', 0,
+  /* 1069 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0,
+  /* 1081 */ 'b', '5', 0,
+  /* 1084 */ 'd', '5', 0,
+  /* 1087 */ 'h', '5', 0,
+  /* 1090 */ 'q', '5', 0,
+  /* 1093 */ 's', '5', 0,
+  /* 1096 */ 'w', '5', 0,
+  /* 1099 */ 'x', '5', 0,
+  /* 1102 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0,
+  /* 1118 */ 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', 0,
+  /* 1134 */ 'b', '1', '6', 0,
+  /* 1138 */ 'd', '1', '6', 0,
+  /* 1142 */ 'h', '1', '6', 0,
+  /* 1146 */ 'q', '1', '6', 0,
+  /* 1150 */ 's', '1', '6', 0,
+  /* 1154 */ 'w', '1', '6', 0,
+  /* 1158 */ 'x', '1', '6', 0,
+  /* 1162 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0,
+  /* 1178 */ 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', 0,
+  /* 1194 */ 'b', '2', '6', 0,
+  /* 1198 */ 'd', '2', '6', 0,
+  /* 1202 */ 'h', '2', '6', 0,
+  /* 1206 */ 'q', '2', '6', 0,
+  /* 1210 */ 's', '2', '6', 0,
+  /* 1214 */ 'w', '2', '6', 0,
+  /* 1218 */ 'x', '2', '6', 0,
+  /* 1222 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0,
+  /* 1234 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0,
+  /* 1246 */ 'b', '6', 0,
+  /* 1249 */ 'd', '6', 0,
+  /* 1252 */ 'h', '6', 0,
+  /* 1255 */ 'q', '6', 0,
+  /* 1258 */ 's', '6', 0,
+  /* 1261 */ 'w', '6', 0,
+  /* 1264 */ 'x', '6', 0,
+  /* 1267 */ 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0,
+  /* 1283 */ 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', 0,
+  /* 1299 */ 'b', '1', '7', 0,
+  /* 1303 */ 'd', '1', '7', 0,
+  /* 1307 */ 'h', '1', '7', 0,
+  /* 1311 */ 'q', '1', '7', 0,
+  /* 1315 */ 's', '1', '7', 0,
+  /* 1319 */ 'w', '1', '7', 0,
+  /* 1323 */ 'x', '1', '7', 0,
+  /* 1327 */ 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0,
+  /* 1343 */ 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', 0,
+  /* 1359 */ 'b', '2', '7', 0,
+  /* 1363 */ 'd', '2', '7', 0,
+  /* 1367 */ 'h', '2', '7', 0,
+  /* 1371 */ 'q', '2', '7', 0,
+  /* 1375 */ 's', '2', '7', 0,
+  /* 1379 */ 'w', '2', '7', 0,
+  /* 1383 */ 'x', '2', '7', 0,
+  /* 1387 */ 'D', '4', '_', 'D', '5', '_', 'D', '6', '_', 'D', '7', 0,
+  /* 1399 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0,
+  /* 1411 */ 'b', '7', 0,
+  /* 1414 */ 'd', '7', 0,
+  /* 1417 */ 'h', '7', 0,
+  /* 1420 */ 'q', '7', 0,
+  /* 1423 */ 's', '7', 0,
+  /* 1426 */ 'w', '7', 0,
+  /* 1429 */ 'x', '7', 0,
+  /* 1432 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0,
+  /* 1448 */ 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', 0,
+  /* 1464 */ 'b', '1', '8', 0,
+  /* 1468 */ 'd', '1', '8', 0,
+  /* 1472 */ 'h', '1', '8', 0,
+  /* 1476 */ 'q', '1', '8', 0,
+  /* 1480 */ 's', '1', '8', 0,
+  /* 1484 */ 'w', '1', '8', 0,
+  /* 1488 */ 'x', '1', '8', 0,
+  /* 1492 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0,
+  /* 1508 */ 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', 0,
+  /* 1524 */ 'b', '2', '8', 0,
+  /* 1528 */ 'd', '2', '8', 0,
+  /* 1532 */ 'h', '2', '8', 0,
+  /* 1536 */ 'q', '2', '8', 0,
+  /* 1540 */ 's', '2', '8', 0,
+  /* 1544 */ 'w', '2', '8', 0,
+  /* 1548 */ 'x', '2', '8', 0,
+  /* 1552 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0,
+  /* 1564 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0,
+  /* 1576 */ 'b', '8', 0,
+  /* 1579 */ 'd', '8', 0,
+  /* 1582 */ 'h', '8', 0,
+  /* 1585 */ 'q', '8', 0,
+  /* 1588 */ 's', '8', 0,
+  /* 1591 */ 'w', '8', 0,
+  /* 1594 */ 'x', '8', 0,
+  /* 1597 */ 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0,
+  /* 1613 */ 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', 0,
+  /* 1629 */ 'b', '1', '9', 0,
+  /* 1633 */ 'd', '1', '9', 0,
+  /* 1637 */ 'h', '1', '9', 0,
+  /* 1641 */ 'q', '1', '9', 0,
+  /* 1645 */ 's', '1', '9', 0,
+  /* 1649 */ 'w', '1', '9', 0,
+  /* 1653 */ 'x', '1', '9', 0,
+  /* 1657 */ 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0,
+  /* 1673 */ 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', 0,
+  /* 1689 */ 'b', '2', '9', 0,
+  /* 1693 */ 'd', '2', '9', 0,
+  /* 1697 */ 'h', '2', '9', 0,
+  /* 1701 */ 'q', '2', '9', 0,
+  /* 1705 */ 's', '2', '9', 0,
+  /* 1709 */ 'w', '2', '9', 0,
+  /* 1713 */ 'x', '2', '9', 0,
+  /* 1717 */ 'D', '6', '_', 'D', '7', '_', 'D', '8', '_', 'D', '9', 0,
+  /* 1729 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0,
+  /* 1741 */ 'b', '9', 0,
+  /* 1744 */ 'd', '9', 0,
+  /* 1747 */ 'h', '9', 0,
+  /* 1750 */ 'q', '9', 0,
+  /* 1753 */ 's', '9', 0,
+  /* 1756 */ 'w', '9', 0,
+  /* 1759 */ 'x', '9', 0,
+  /* 1762 */ 'w', 's', 'p', 0,
+  /* 1766 */ 'w', 'z', 'r', 0,
+  /* 1770 */ 'x', 'z', 'r', 0,
+  /* 1774 */ 'n', 'z', 'c', 'v', 0,
+  };
+
+  static const uint32_t RegAsmOffsetNoRegAltName[] = {
+    1713, 170, 1774, 1763, 1762, 1766, 1770, 204, 421, 586, 751, 916, 1081, 1246, 
+    1411, 1576, 1741, 26, 253, 472, 639, 804, 969, 1134, 1299, 1464, 1629, 86, 
+    313, 532, 699, 864, 1029, 1194, 1359, 1524, 1689, 146, 373, 207, 424, 589, 
+    754, 919, 1084, 1249, 1414, 1579, 1744, 30, 257, 476, 643, 808, 973, 1138, 
+    1303, 1468, 1633, 90, 317, 536, 703, 868, 1033, 1198, 1363, 1528, 1693, 150, 
+    377, 210, 427, 592, 757, 922, 1087, 1252, 1417, 1582, 1747, 34, 261, 480, 
+    647, 812, 977, 1142, 1307, 1472, 1637, 94, 321, 540, 707, 872, 1037, 1202, 
+    1367, 1532, 1697, 154, 381, 213, 430, 595, 760, 925, 1090, 1255, 1420, 1585, 
+    1750, 38, 265, 484, 651, 816, 981, 1146, 1311, 1476, 1641, 98, 325, 544, 
+    711, 876, 1041, 1206, 1371, 1536, 1701, 158, 385, 216, 433, 598, 763, 928, 
+    1093, 1258, 1423, 1588, 1753, 42, 269, 488, 655, 820, 985, 1150, 1315, 1480, 
+    1645, 102, 329, 548, 715, 880, 1045, 1210, 1375, 1540, 1705, 162, 389, 219, 
+    436, 601, 766, 931, 1096, 1261, 1426, 1591, 1756, 46, 273, 492, 659, 824, 
+    989, 1154, 1319, 1484, 1649, 106, 333, 552, 719, 884, 1049, 1214, 1379, 1544, 
+    1709, 166, 222, 439, 604, 769, 934, 1099, 1264, 1429, 1594, 1759, 50, 277, 
+    496, 663, 828, 993, 1158, 1323, 1488, 1653, 110, 337, 556, 723, 888, 1053, 
+    1218, 1383, 1548, 401, 567, 733, 898, 1063, 1228, 1393, 1558, 1723, 6, 231, 
+    449, 615, 780, 945, 1110, 1275, 1440, 1605, 62, 289, 508, 675, 840, 1005, 
+    1170, 1335, 1500, 1665, 122, 349, 182, 727, 892, 1057, 1222, 1387, 1552, 1717, 
+    0, 225, 442, 607, 772, 937, 1102, 1267, 1432, 1597, 54, 281, 500, 667, 
+    832, 997, 1162, 1327, 1492, 1657, 114, 341, 174, 393, 560, 564, 730, 895, 
+    1060, 1225, 1390, 1555, 1720, 3, 228, 445, 611, 776, 941, 1106, 1271, 1436, 
+    1601, 58, 285, 504, 671, 836, 1001, 1166, 1331, 1496, 1661, 118, 345, 178, 
+    397, 415, 580, 745, 910, 1075, 1240, 1405, 1570, 1735, 19, 245, 464, 631, 
+    796, 961, 1126, 1291, 1456, 1621, 78, 305, 524, 691, 856, 1021, 1186, 1351, 
+    1516, 1681, 138, 365, 197, 739, 904, 1069, 1234, 1399, 1564, 1729, 13, 239, 
+    457, 623, 788, 953, 1118, 1283, 1448, 1613, 70, 297, 516, 683, 848, 1013, 
+    1178, 1343, 1508, 1673, 130, 357, 189, 407, 573, 577, 742, 907, 1072, 1237, 
+    1402, 1567, 1732, 16, 242, 460, 627, 792, 957, 1122, 1287, 1452, 1617, 74, 
+    301, 520, 687, 852, 1017, 1182, 1347, 1512, 1677, 134, 361, 193, 411, 
+  };
+
+  static char AsmStrsvreg[] = {
+  /* 0 */ 'v', '1', '0', 0,
+  /* 4 */ 'v', '2', '0', 0,
+  /* 8 */ 'v', '3', '0', 0,
+  /* 12 */ 'v', '0', 0,
+  /* 15 */ 'v', '1', '1', 0,
+  /* 19 */ 'v', '2', '1', 0,
+  /* 23 */ 'v', '3', '1', 0,
+  /* 27 */ 'v', '1', 0,
+  /* 30 */ 'v', '1', '2', 0,
+  /* 34 */ 'v', '2', '2', 0,
+  /* 38 */ 'v', '2', 0,
+  /* 41 */ 'v', '1', '3', 0,
+  /* 45 */ 'v', '2', '3', 0,
+  /* 49 */ 'v', '3', 0,
+  /* 52 */ 'v', '1', '4', 0,
+  /* 56 */ 'v', '2', '4', 0,
+  /* 60 */ 'v', '4', 0,
+  /* 63 */ 'v', '1', '5', 0,
+  /* 67 */ 'v', '2', '5', 0,
+  /* 71 */ 'v', '5', 0,
+  /* 74 */ 'v', '1', '6', 0,
+  /* 78 */ 'v', '2', '6', 0,
+  /* 82 */ 'v', '6', 0,
+  /* 85 */ 'v', '1', '7', 0,
+  /* 89 */ 'v', '2', '7', 0,
+  /* 93 */ 'v', '7', 0,
+  /* 96 */ 'v', '1', '8', 0,
+  /* 100 */ 'v', '2', '8', 0,
+  /* 104 */ 'v', '8', 0,
+  /* 107 */ 'v', '1', '9', 0,
+  /* 111 */ 'v', '2', '9', 0,
+  /* 115 */ 'v', '9', 0,
+  };
+
+  static const uint32_t RegAsmOffsetvreg[] = {
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 12, 27, 38, 
+    49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 
+    85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 
+    23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, 
+    115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 
+    45, 56, 67, 78, 89, 100, 111, 8, 23, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 
+    15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 
+    67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 
+    93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 
+    19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 
+    49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 
+    85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 
+    23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 
+    41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 
+    89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 
+    115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 
+    45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 
+    71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 
+    107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 
+  };
+
+  const uint32_t *RegAsmOffset;
+  char *AsmStrs;
+
+  switch(AltIdx) {
+  default: // llvm_unreachable("Invalid register alt name index!");
+  case AArch64_NoRegAltName:
+    AsmStrs = AsmStrsNoRegAltName;
+    RegAsmOffset = RegAsmOffsetNoRegAltName;
+    break;
+  case AArch64_vreg:
+    AsmStrs = AsmStrsvreg;
+    RegAsmOffset = RegAsmOffsetvreg;
+    break;
+  }
+  //int i;
+  //for (i = 0; i < sizeof(RegAsmOffsetNoRegAltName)/4; i++)
+  //     printf("%s = %u\n", AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[i], i + 1);
+  //printf("*************************\n");
+  //for (i = 0; i < sizeof(RegAsmOffsetvreg)/4; i++)
+  //     printf("%s = %u\n", AsmStrsvreg+RegAsmOffsetvreg[i], i + 1);
+  //printf("-------------------------\n");
+  return AsmStrs+RegAsmOffset[RegNo-1];
+#else
+  return NULL;
+#endif
+}
+
+#ifdef PRINT_ALIAS_INSTR
+#undef PRINT_ALIAS_INSTR
+
+static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx,
+  unsigned PrintMethodIdx, SStream *OS, MCRegisterInfo *MRI)
+{
+  // printf(">>>> Method: %u, opIdx: %x\n", PrintMethodIdx, OpIdx);
+  switch (PrintMethodIdx) {
+  default:
+    // llvm_unreachable("Unknown PrintMethod kind");
+    break;
+  case 0:
+    printAddSubImm(MI, OpIdx, OS);
+    break;
+  case 1:
+    printShifter(MI, OpIdx, OS);
+    break;
+  case 2:
+    printArithExtend(MI, OpIdx, OS);
+    break;
+  case 3:
+    printLogicalImm32(MI, OpIdx, OS);
+    break;
+  case 4:
+    printLogicalImm64(MI, OpIdx, OS);
+    break;
+  case 5:
+    printVRegOperand(MI, OpIdx, OS);
+    break;
+  case 6:
+    printHexImm(MI, OpIdx, OS);
+    break;
+  case 7:
+    printInverseCondCode(MI, OpIdx, OS);
+    break;
+  case 8:
+    printVectorIndex(MI, OpIdx, OS);
+    break;
+  case 9:
+    printTypedVectorList(MI, OpIdx, OS, 16, 'b', MRI);
+    break;
+  case 10:
+    printTypedVectorList(MI, OpIdx, OS, 1, 'd', MRI);
+    break;
+  case 11:
+    printTypedVectorList(MI, OpIdx, OS, 2, 'd', MRI);
+    break;
+  case 12:
+    printTypedVectorList(MI, OpIdx, OS, 2, 's', MRI);
+    break;
+  case 13:
+    printTypedVectorList(MI, OpIdx, OS, 4, 'h', MRI);
+    break;
+  case 14:
+    printTypedVectorList(MI, OpIdx, OS, 4, 's', MRI);
+    break;
+  case 15:
+    printTypedVectorList(MI, OpIdx, OS, 8, 'b', MRI);
+    break;
+  case 16:
+    printTypedVectorList(MI, OpIdx, OS, 8, 'h', MRI);
+    break;
+  case 17:
+    printTypedVectorList(MI, OpIdx, OS, 0, 'h', MRI);
+    break;
+  case 18:
+    printTypedVectorList(MI, OpIdx, OS, 0, 's', MRI);
+    break;
+  case 19:
+    printTypedVectorList(MI, OpIdx, OS, 0, 'd', MRI);
+    break;
+  case 20:
+    printTypedVectorList(MI, OpIdx, OS, 0, 'b', MRI);
+    break;
+  case 21:
+    printPrefetchOp(MI, OpIdx, OS);
+    break;
+  case 22:
+    printSysCROperand(MI, OpIdx, OS);
+    break;
+  }
+}
+
+static bool AArch64InstPrinterValidateMCOperand(
+       MCOperand *MCOp, unsigned PredicateIndex)
+{
+  switch (PredicateIndex) {
+  default:
+    // llvm_unreachable("Unknown MCOperandPredicate kind");
+  case 1: {
+    return (MCOperand_isImm(MCOp) &&
+           MCOperand_getImm(MCOp) != ARM64_CC_AL &&
+           MCOperand_getImm(MCOp) != ARM64_CC_NV);
+    }
+  }
+}
+
+static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
+{
+  #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
+  const char *AsmString;
+  char *tmp, *AsmMnem, *AsmOps, *c;
+  int OpIdx, PrintMethodIdx;
+  MCRegisterInfo *MRI = (MCRegisterInfo *)info;
+  switch (MCInst_getOpcode(MI)) {
+  default: return NULL;
+  case AArch64_ADDSWri:
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1)) {
+      // (ADDSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm)
+      AsmString = "cmn $\x02, $\xFF\x03\x01";
+      break;
+    }
+    return NULL;
+  case AArch64_ADDSWrs:
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+      // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, 0)
+      AsmString = "cmn $\x02, $\x03";
+      break;
+    }
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) {
+      // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh)
+      AsmString = "cmn $\x02, $\x03$\xFF\x04\x02";
+      break;
+    }
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+      // (ADDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0)
+      AsmString = "adds $\x01, $\x02, $\x03";
+      break;
+    }
+    return NULL;
+  case AArch64_ADDSWrx:
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) {
+      // (ADDSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16)
+      AsmString = "cmn $\x02, $\x03";
+      break;
+    }
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) {
+      // (ADDSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh)
+      AsmString = "cmn $\x02, $\x03$\xFF\x04\x03";
+      break;
+    }
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) {
+      // (ADDSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16)
+      AsmString = "adds $\x01, $\x02, $\x03";
+      break;
+    }
+    return NULL;
+  case AArch64_ADDSXri:
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1)) {
+      // (ADDSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm)
+      AsmString = "cmn $\x02, $\xFF\x03\x01";
+      break;
+    }
+    return NULL;
+  case AArch64_ADDSXrs:
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+      // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, 0)
+      AsmString = "cmn $\x02, $\x03";
+      break;
+    }
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) {
+      // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh)
+      AsmString = "cmn $\x02, $\x03$\xFF\x04\x02";
+      break;
+    }
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+      // (ADDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0)
+      AsmString = "adds $\x01, $\x02, $\x03";
+      break;
+    }
+    return NULL;
+  case AArch64_ADDSXrx:
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) {
+      // (ADDSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh)
+      AsmString = "cmn $\x02, $\x03$\xFF\x04\x03";
+      break;
+    }
+    return NULL;
+  case AArch64_ADDSXrx64:
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) {
+      // (ADDSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24)
+      AsmString = "cmn $\x02, $\x03";
+      break;
+    }
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) {
+      // (ADDSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh)
+      AsmString = "cmn $\x02, $\x03$\xFF\x04\x03";
+      break;
+    }
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) {
+      // (ADDSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24)
+      AsmString = "adds $\x01, $\x02, $\x03";
+      break;
+    }
+    return NULL;
+  case AArch64_ADDWri:
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 0) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 &&
+        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+      // (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)
+      AsmString = "mov $\x01, $\x02";
+      break;
+    }
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 0) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 &&
+        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+      // (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)
+      AsmString = "mov $\x01, $\x02";
+      break;
+    }
+    return NULL;
+  case AArch64_ADDWrs:
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+      // (ADDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0)
+      AsmString = "add $\x01, $\x02, $\x03";
+      break;
+    }
+    return NULL;
+  case AArch64_ADDWrx:
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 0) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) {
+      // (ADDWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16)
+      AsmString = "add $\x01, $\x02, $\x03";
+      break;
+    }
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 0) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) {
+      // (ADDWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16)
+      AsmString = "add $\x01, $\x02, $\x03";
+      break;
+    }
+    return NULL;
+  case AArch64_ADDXri:
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 0) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 &&
+        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+      // (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)
+      AsmString = "mov $\x01, $\x02";
+      break;
+    }
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 &&
+        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+      // (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)
+      AsmString = "mov $\x01, $\x02";
+      break;
+    }
+    return NULL;
+  case AArch64_ADDXrs:
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+      // (ADDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0)
+      AsmString = "add $\x01, $\x02, $\x03";
+      break;
+    }
+    return NULL;
+  case AArch64_ADDXrx64:
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 0) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) {
+      // (ADDXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24)
+      AsmString = "add $\x01, $\x02, $\x03";
+      break;
+    }
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) {
+      // (ADDXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24)
+      AsmString = "add $\x01, $\x02, $\x03";
+      break;
+    }
+    return NULL;
+  case AArch64_ANDSWri:
+    if (MCInst_getNumOperands(MI) == 3 &&
+        MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1)) {
+      // (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2)
+      AsmString = "tst $\x02, $\xFF\x03\x04";
+      break;
+    }
+    return NULL;
+  case AArch64_ANDSWrs:
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+      // (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0)
+      AsmString = "tst $\x02, $\x03";
+      break;
+    }
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) {
+      // (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh)
+      AsmString = "tst $\x02, $\x03$\xFF\x04\x02";
+      break;
+    }
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+      // (ANDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0)
+      AsmString = "ands $\x01, $\x02, $\x03";
+      break;
+    }
+    return NULL;
+  case AArch64_ANDSXri:
+    if (MCInst_getNumOperands(MI) == 3 &&
+        MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1)) {
+      // (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2)
+      AsmString = "tst $\x02, $\xFF\x03\x05";
+      break;
+    }
+    return NULL;
+  case AArch64_ANDSXrs:
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+      // (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0)
+      AsmString = "tst $\x02, $\x03";
+      break;
+    }
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) {
+      // (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh)
+      AsmString = "tst $\x02, $\x03$\xFF\x04\x02";
+      break;
+    }
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+      // (ANDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0)
+      AsmString = "ands $\x01, $\x02, $\x03";
+      break;
+    }
+    return NULL;
+  case AArch64_ANDWrs:
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+      // (ANDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0)
+      AsmString = "and $\x01, $\x02, $\x03";
+      break;
+    }
+    return NULL;
+  case AArch64_ANDXrs:
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+      // (ANDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0)
+      AsmString = "and $\x01, $\x02, $\x03";
+      break;
+    }
+    return NULL;
+  case AArch64_BICSWrs:
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+      // (BICSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0)
+      AsmString = "bics $\x01, $\x02, $\x03";
+      break;
+    }
+    return NULL;
+  case AArch64_BICSXrs:
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+      // (BICSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0)
+      AsmString = "bics $\x01, $\x02, $\x03";
+      break;
+    }
+    return NULL;
+  case AArch64_BICWrs:
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+      // (BICWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0)
+      AsmString = "bic $\x01, $\x02, $\x03";
+      break;
+    }
+    return NULL;
+  case AArch64_BICXrs:
+    if (MCInst_getNumOperands(MI) == 4 &&
+        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+        GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+      // (BICXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0)
+      AsmString = "bic $\x01, $\x02, $\x03";
+      break;
+    }
+    return NULL;
+  case AArch64_BICv2i32:
+    if (MCInst_getNumOperands(MI) == 3 &&
+        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+        GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+      // (BICv2i32 V64:$Vd, imm0_255:$imm, 0)
+      AsmString = "bic $\xFF\x01\x06.2s, $\xFF\x02\x07";
+      break;
+    }
+    return NULL;
+  case AArch64_BICv4i16:
+    if (MCInst_getNumOperands(MI) == 3 &&
+        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+        GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) &&
+        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+      // (BICv4i16 V64:$Vd, imm0_255:$imm, 0)
+      AsmString = "bic $\xFF\x01\x06.4h, $\xFF\x02\x07";
+      break;
+    }
+    return NULL;
+  case AArch64_BICv4i32:
+    if (MCInst_getNumOperands(MI) == 3 &&
+        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+        GE