Update Android.bp for XNNPACK following latest update (06acbb)
Test: mm
Change-Id: I939a0aebe661a7264ffe34f068046d6b20f5aa44
diff --git a/Android.bp b/Android.bp
index 16b757e..7c90c1b 100644
--- a/Android.bp
+++ b/Android.bp
@@ -43,18 +43,18 @@
"src/operators/fully-connected-nc.c",
"src/operators/global-average-pooling-ncw.c",
"src/operators/global-average-pooling-nwc.c",
- "src/operators/leaky-relu-nc.c",
+ "src/operators/lut-elementwise-nc.c",
"src/operators/max-pooling-nhwc.c",
"src/operators/prelu-nc.c",
"src/operators/resize-bilinear-nchw.c",
"src/operators/resize-bilinear-nhwc.c",
- "src/operators/sigmoid-nc.c",
"src/operators/softmax-nc.c",
"src/operators/unary-elementwise-nc.c",
"src/operators/unpooling-nhwc.c",
]
LOGGING_SRCS = [
+ "src/datatype-strings.c",
"src/operator-strings.c",
"src/subgraph-strings.c",
]
@@ -67,6 +67,7 @@
"src/subgraph/bankers-rounding.c",
"src/subgraph/ceiling.c",
"src/subgraph/clamp.c",
+ "src/subgraph/convert.c",
"src/subgraph/convolution-2d.c",
"src/subgraph/deconvolution-2d.c",
"src/subgraph/depth-to-space.c",
@@ -106,18 +107,450 @@
"src/tables/exp2minus-k-over-2048.c",
]
-SCALAR_UKERNELS = [
+PROD_SCALAR_PORTABLE_MICROKERNEL_SRCS = [
+ "src/params-init.c",
+ "src/u8-lut32norm/scalar.c",
+ "src/x8-lut/gen/lut-scalar-x4.c",
+ "src/x32-depthtospace2d-chw2hwc/scalar.c",
+ "src/xx-copy/memcpy.c",
+]
+
+PROD_SCALAR_AARCH32_MICROKERNEL_SRCS = [
+ "src/f16-f32-vcvt/gen/vcvt-scalar-x4.c",
"src/f32-argmaxpool/4x-scalar-c1.c",
"src/f32-argmaxpool/9p8x-scalar-c1.c",
"src/f32-argmaxpool/9x-scalar-c1.c",
"src/f32-avgpool/9p8x-minmax-scalar-c1.c",
"src/f32-avgpool/9x-minmax-scalar-c1.c",
- "src/f32-clamp/gen/scalar-x1.c",
- "src/f32-clamp/gen/scalar-x2.c",
- "src/f32-clamp/gen/scalar-x4.c",
"src/f32-conv-hwc/3x3s2p0p1c3x4-scalar-1x1.c",
"src/f32-conv-hwc/3x3s2p1c3x4-scalar-1x1.c",
"src/f32-conv-hwc2chw/3x3s2p1c3x4-scalar-1x1.c",
+ "src/f32-dwconv/gen/up1x3-minmax-scalar-acc2.c",
+ "src/f32-dwconv/gen/up1x3-scalar-acc2.c",
+ "src/f32-dwconv/gen/up1x4-minmax-scalar-acc2.c",
+ "src/f32-dwconv/gen/up1x4-scalar-acc2.c",
+ "src/f32-dwconv/gen/up1x9-minmax-scalar-acc2.c",
+ "src/f32-dwconv/gen/up1x9-scalar-acc2.c",
+ "src/f32-dwconv/gen/up1x25-minmax-scalar-acc2.c",
+ "src/f32-dwconv/gen/up1x25-scalar-acc2.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-scalar-4x1.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-scalar-2x1-acc2.c",
+ "src/f32-dwconv2d-chw/gen/5x5p2-minmax-scalar-2x1-acc2.c",
+ "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-2x1-acc2.c",
+ "src/f32-f16-vcvt/gen/vcvt-scalar-fabsf-x2.c",
+ "src/f32-gavgpool-cw/scalar-x1.c",
+ "src/f32-gavgpool/7p7x-minmax-scalar-c1.c",
+ "src/f32-gavgpool/7x-minmax-scalar-c1.c",
+ "src/f32-gemm/gen/1x4-minmax-scalar.c",
+ "src/f32-gemm/gen/1x4-relu-scalar.c",
+ "src/f32-gemm/gen/1x4-scalar.c",
+ "src/f32-gemm/gen/4x2-minmax-scalar.c",
+ "src/f32-gemm/gen/4x2-scalar.c",
+ "src/f32-gemm/gen/4x4-minmax-scalar.c",
+ "src/f32-gemm/gen/4x4-relu-scalar.c",
+ "src/f32-gemm/gen/4x4-scalar.c",
+ "src/f32-ibilinear-chw/gen/scalar-p4.c",
+ "src/f32-ibilinear/gen/scalar-c2.c",
+ "src/f32-igemm/gen/1x4-minmax-scalar.c",
+ "src/f32-igemm/gen/1x4-relu-scalar.c",
+ "src/f32-igemm/gen/1x4-scalar.c",
+ "src/f32-igemm/gen/4x2-minmax-scalar.c",
+ "src/f32-igemm/gen/4x2-scalar.c",
+ "src/f32-igemm/gen/4x4-minmax-scalar.c",
+ "src/f32-igemm/gen/4x4-relu-scalar.c",
+ "src/f32-igemm/gen/4x4-scalar.c",
+ "src/f32-maxpool/9p8x-minmax-scalar-c1.c",
+ "src/f32-pavgpool/9p8x-minmax-scalar-c1.c",
+ "src/f32-pavgpool/9x-minmax-scalar-c1.c",
+ "src/f32-prelu/gen/scalar-2x4.c",
+ "src/f32-qs8-vcvt/gen/vcvt-scalar-imagic-x4.c",
+ "src/f32-qu8-vcvt/gen/vcvt-scalar-imagic-x4.c",
+ "src/f32-raddstoreexpminusmax/gen/scalar-rr2-p5-x4-acc2.c",
+ "src/f32-rmax/scalar.c",
+ "src/f32-spmm/gen/8x1-minmax-scalar.c",
+ "src/f32-spmm/gen/8x2-minmax-scalar.c",
+ "src/f32-spmm/gen/8x4-minmax-scalar.c",
+ "src/f32-vbinary/gen/vadd-minmax-scalar-x8.c",
+ "src/f32-vbinary/gen/vaddc-minmax-scalar-x8.c",
+ "src/f32-vbinary/gen/vdiv-minmax-scalar-x2.c",
+ "src/f32-vbinary/gen/vdivc-minmax-scalar-x2.c",
+ "src/f32-vbinary/gen/vmax-scalar-x8.c",
+ "src/f32-vbinary/gen/vmaxc-scalar-x8.c",
+ "src/f32-vbinary/gen/vmin-scalar-x8.c",
+ "src/f32-vbinary/gen/vminc-scalar-x8.c",
+ "src/f32-vbinary/gen/vmul-minmax-scalar-x8.c",
+ "src/f32-vbinary/gen/vmulc-minmax-scalar-x8.c",
+ "src/f32-vbinary/gen/vrdivc-minmax-scalar-x2.c",
+ "src/f32-vbinary/gen/vrsubc-minmax-scalar-x8.c",
+ "src/f32-vbinary/gen/vsqrdiff-scalar-x8.c",
+ "src/f32-vbinary/gen/vsqrdiffc-scalar-x8.c",
+ "src/f32-vbinary/gen/vsub-minmax-scalar-x8.c",
+ "src/f32-vbinary/gen/vsubc-minmax-scalar-x8.c",
+ "src/f32-vclamp/gen/vclamp-scalar-x4.c",
+ "src/f32-velu/gen/velu-scalar-rr2-lut16-p3-x4.c",
+ "src/f32-vhswish/gen/vhswish-scalar-x4.c",
+ "src/f32-vlrelu/gen/vlrelu-scalar-x4.c",
+ "src/f32-vmulcaddc/gen/c1-minmax-scalar-2x.c",
+ "src/f32-vrelu/gen/vrelu-scalar-x8.c",
+ "src/f32-vrnd/gen/vrndd-scalar-libm-x1.c",
+ "src/f32-vrnd/gen/vrndne-scalar-libm-x1.c",
+ "src/f32-vrnd/gen/vrndu-scalar-libm-x1.c",
+ "src/f32-vrnd/gen/vrndz-scalar-libm-x1.c",
+ "src/f32-vsigmoid/gen/vsigmoid-scalar-rr2-lut64-p2-div-x2.c",
+ "src/f32-vsqrt/gen/scalar-sqrt-x1.c",
+ "src/f32-vunary/gen/vabs-scalar-x4.c",
+ "src/f32-vunary/gen/vneg-scalar-x4.c",
+ "src/f32-vunary/gen/vsqr-scalar-x4.c",
+ "src/qc8-dwconv/gen/up2x9-minmax-fp32-scalar-fmagic.c",
+ "src/qc8-dwconv/gen/up2x25-minmax-fp32-scalar-fmagic.c",
+ "src/qc8-gemm/gen/1x2-minmax-fp32-scalar-fmagic.c",
+ "src/qc8-gemm/gen/2x2-minmax-fp32-scalar-fmagic.c",
+ "src/qc8-igemm/gen/1x2-minmax-fp32-scalar-fmagic.c",
+ "src/qc8-igemm/gen/2x2-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-dwconv/gen/up1x9-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-dwconv/gen/up1x25-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-f32-vcvt/gen/vcvt-scalar-x4.c",
+ "src/qs8-gavgpool/gen/7p7x-minmax-fp32-scalar-imagic-c1.c",
+ "src/qs8-gavgpool/gen/7x-minmax-fp32-scalar-imagic-c1.c",
+ "src/qs8-gemm/gen/1x2-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-gemm/gen/2x2-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-igemm/gen/1x2-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-igemm/gen/2x2-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-vadd/gen/minmax-scalar-x1.c",
+ "src/qs8-vaddc/gen/minmax-scalar-x1.c",
+ "src/qs8-vmul/gen/minmax-fp32-scalar-x4.c",
+ "src/qs8-vmulc/gen/minmax-fp32-scalar-x4.c",
+ "src/qu8-avgpool/9p8x-minmax-scalar-c1.c",
+ "src/qu8-avgpool/9x-minmax-scalar-c1.c",
+ "src/qu8-dwconv/gen/up1x9-minmax-fp32-scalar-fmagic.c",
+ "src/qu8-dwconv/gen/up1x25-minmax-fp32-scalar-fmagic.c",
+ "src/qu8-f32-vcvt/gen/vcvt-scalar-x4.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-scalar-imagic-c1.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-scalar-imagic-c1.c",
+ "src/qu8-gemm/gen/1x2-minmax-fp32-scalar-fmagic.c",
+ "src/qu8-gemm/gen/2x2-minmax-fp32-scalar-fmagic.c",
+ "src/qu8-igemm/gen/1x2-minmax-fp32-scalar-fmagic.c",
+ "src/qu8-igemm/gen/2x2-minmax-fp32-scalar-fmagic.c",
+ "src/qu8-vadd/gen/minmax-scalar-x1.c",
+ "src/qu8-vaddc/gen/minmax-scalar-x1.c",
+ "src/qu8-vmul/gen/minmax-fp32-scalar-x4.c",
+ "src/qu8-vmulc/gen/minmax-fp32-scalar-x4.c",
+ "src/s8-ibilinear/gen/scalar-c1.c",
+ "src/s8-maxpool/9p8x-minmax-scalar-c1.c",
+ "src/s8-vclamp/scalar-x4.c",
+ "src/u8-ibilinear/gen/scalar-c1.c",
+ "src/u8-maxpool/9p8x-minmax-scalar-c1.c",
+ "src/u8-rmax/scalar.c",
+ "src/u8-vclamp/scalar-x4.c",
+ "src/x8-zip/x2-scalar.c",
+ "src/x8-zip/x3-scalar.c",
+ "src/x8-zip/x4-scalar.c",
+ "src/x8-zip/xm-scalar.c",
+ "src/x32-packx/x2-scalar.c",
+ "src/x32-packx/x3-scalar.c",
+ "src/x32-packx/x4-scalar.c",
+ "src/x32-unpool/scalar.c",
+ "src/x32-zip/x2-scalar.c",
+ "src/x32-zip/x3-scalar.c",
+ "src/x32-zip/x4-scalar.c",
+ "src/x32-zip/xm-scalar.c",
+ "src/xx-fill/scalar-x16.c",
+ "src/xx-pad/scalar.c",
+]
+
+PROD_SCALAR_WASM_MICROKERNEL_SRCS = [
+ "src/f16-f32-vcvt/gen/vcvt-scalar-x1.c",
+ "src/f32-argmaxpool/4x-scalar-c1.c",
+ "src/f32-argmaxpool/9p8x-scalar-c1.c",
+ "src/f32-argmaxpool/9x-scalar-c1.c",
+ "src/f32-avgpool/9p8x-minmax-scalar-c1.c",
+ "src/f32-avgpool/9x-minmax-scalar-c1.c",
+ "src/f32-conv-hwc/3x3s2p0p1c3x4-scalar-1x1.c",
+ "src/f32-conv-hwc/3x3s2p1c3x4-scalar-1x1.c",
+ "src/f32-conv-hwc2chw/3x3s2p1c3x4-scalar-1x1.c",
+ "src/f32-dwconv/gen/up1x3-minmax-scalar-acc2.c",
+ "src/f32-dwconv/gen/up1x3-scalar-acc2.c",
+ "src/f32-dwconv/gen/up1x4-minmax-scalar-acc2.c",
+ "src/f32-dwconv/gen/up1x4-scalar-acc2.c",
+ "src/f32-dwconv/gen/up1x9-minmax-scalar-acc2.c",
+ "src/f32-dwconv/gen/up1x9-scalar-acc2.c",
+ "src/f32-dwconv/gen/up1x25-minmax-scalar-acc2.c",
+ "src/f32-dwconv/gen/up1x25-scalar-acc2.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-scalar-2x1-acc2.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-scalar-1x1-acc2.c",
+ "src/f32-dwconv2d-chw/gen/5x5p2-minmax-scalar-1x1-acc5.c",
+ "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-1x1-acc5.c",
+ "src/f32-f16-vcvt/gen/vcvt-scalar-bitcast-x4.c",
+ "src/f32-gavgpool-cw/scalar-x1.c",
+ "src/f32-gavgpool/7p7x-minmax-scalar-c1.c",
+ "src/f32-gavgpool/7x-minmax-scalar-c1.c",
+ "src/f32-gemm/gen/2x4-minmax-scalar.c",
+ "src/f32-gemm/gen/2x4-relu-scalar.c",
+ "src/f32-gemm/gen/2x4-scalar.c",
+ "src/f32-ibilinear-chw/gen/scalar-p4.c",
+ "src/f32-ibilinear/gen/scalar-c2.c",
+ "src/f32-igemm/gen/2x4-minmax-scalar.c",
+ "src/f32-igemm/gen/2x4-relu-scalar.c",
+ "src/f32-igemm/gen/2x4-scalar.c",
+ "src/f32-maxpool/9p8x-minmax-scalar-c1.c",
+ "src/f32-pavgpool/9p8x-minmax-scalar-c1.c",
+ "src/f32-pavgpool/9x-minmax-scalar-c1.c",
+ "src/f32-prelu/gen/scalar-2x4.c",
+ "src/f32-qs8-vcvt/gen/vcvt-scalar-imagic-x1.c",
+ "src/f32-qu8-vcvt/gen/vcvt-scalar-imagic-x1.c",
+ "src/f32-raddstoreexpminusmax/gen/scalar-rr2-p5-x4-acc2.c",
+ "src/f32-rmax/scalar.c",
+ "src/f32-spmm/gen/8x1-minmax-scalar.c",
+ "src/f32-spmm/gen/8x2-minmax-scalar.c",
+ "src/f32-spmm/gen/8x4-minmax-scalar.c",
+ "src/f32-vbinary/gen/vadd-minmax-scalar-x8.c",
+ "src/f32-vbinary/gen/vaddc-minmax-scalar-x8.c",
+ "src/f32-vbinary/gen/vdiv-minmax-scalar-x8.c",
+ "src/f32-vbinary/gen/vdivc-minmax-scalar-x8.c",
+ "src/f32-vbinary/gen/vmax-scalar-x8.c",
+ "src/f32-vbinary/gen/vmaxc-scalar-x8.c",
+ "src/f32-vbinary/gen/vmin-scalar-x8.c",
+ "src/f32-vbinary/gen/vminc-scalar-x8.c",
+ "src/f32-vbinary/gen/vmul-minmax-scalar-x8.c",
+ "src/f32-vbinary/gen/vmulc-minmax-scalar-x8.c",
+ "src/f32-vbinary/gen/vrdivc-minmax-scalar-x8.c",
+ "src/f32-vbinary/gen/vrsubc-minmax-scalar-x8.c",
+ "src/f32-vbinary/gen/vsqrdiff-scalar-x8.c",
+ "src/f32-vbinary/gen/vsqrdiffc-scalar-x8.c",
+ "src/f32-vbinary/gen/vsub-minmax-scalar-x8.c",
+ "src/f32-vbinary/gen/vsubc-minmax-scalar-x8.c",
+ "src/f32-vclamp/gen/vclamp-scalar-x4.c",
+ "src/f32-velu/gen/velu-scalar-rr2-lut16-p3-x2.c",
+ "src/f32-vhswish/gen/vhswish-scalar-x4.c",
+ "src/f32-vlrelu/gen/vlrelu-scalar-x4.c",
+ "src/f32-vmulcaddc/gen/c1-minmax-scalar-2x.c",
+ "src/f32-vrelu/gen/vrelu-scalar-x8.c",
+ "src/f32-vrnd/gen/vrndd-scalar-libm-x4.c",
+ "src/f32-vrnd/gen/vrndne-scalar-libm-x4.c",
+ "src/f32-vrnd/gen/vrndu-scalar-libm-x4.c",
+ "src/f32-vrnd/gen/vrndz-scalar-libm-x4.c",
+ "src/f32-vsigmoid/gen/vsigmoid-scalar-rr2-lut64-p2-div-x2.c",
+ "src/f32-vsqrt/gen/scalar-sqrt-x1.c",
+ "src/f32-vunary/gen/vabs-scalar-x4.c",
+ "src/f32-vunary/gen/vneg-scalar-x4.c",
+ "src/f32-vunary/gen/vsqr-scalar-x4.c",
+ "src/qc8-dwconv/gen/up1x25-minmax-fp32-scalar-imagic.c",
+ "src/qc8-dwconv/gen/up2x9-minmax-fp32-scalar-imagic.c",
+ "src/qc8-gemm/gen/1x2-minmax-fp32-scalar-imagic.c",
+ "src/qc8-gemm/gen/2x2-minmax-fp32-scalar-imagic.c",
+ "src/qc8-igemm/gen/1x2-minmax-fp32-scalar-imagic.c",
+ "src/qc8-igemm/gen/2x2-minmax-fp32-scalar-imagic.c",
+ "src/qs8-dwconv/gen/up1x25-minmax-fp32-scalar-imagic.c",
+ "src/qs8-dwconv/gen/up2x9-minmax-fp32-scalar-imagic.c",
+ "src/qs8-f32-vcvt/gen/vcvt-scalar-x1.c",
+ "src/qs8-gavgpool/gen/7p7x-minmax-fp32-scalar-imagic-c4.c",
+ "src/qs8-gavgpool/gen/7x-minmax-fp32-scalar-imagic-c4.c",
+ "src/qs8-gemm/gen/1x2-minmax-fp32-scalar-imagic.c",
+ "src/qs8-gemm/gen/2x2-minmax-fp32-scalar-imagic.c",
+ "src/qs8-igemm/gen/1x2-minmax-fp32-scalar-imagic.c",
+ "src/qs8-igemm/gen/2x2-minmax-fp32-scalar-imagic.c",
+ "src/qs8-vadd/gen/minmax-scalar-x4.c",
+ "src/qs8-vaddc/gen/minmax-scalar-x4.c",
+ "src/qs8-vmul/gen/minmax-fp32-scalar-x4.c",
+ "src/qs8-vmulc/gen/minmax-fp32-scalar-x4.c",
+ "src/qu8-avgpool/9p8x-minmax-scalar-c1.c",
+ "src/qu8-avgpool/9x-minmax-scalar-c1.c",
+ "src/qu8-dwconv/gen/up1x25-minmax-fp32-scalar-imagic.c",
+ "src/qu8-dwconv/gen/up2x9-minmax-fp32-scalar-imagic.c",
+ "src/qu8-f32-vcvt/gen/vcvt-scalar-x1.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-scalar-imagic-c4.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-scalar-imagic-c4.c",
+ "src/qu8-gemm/gen/1x2-minmax-fp32-scalar-imagic.c",
+ "src/qu8-gemm/gen/2x2-minmax-fp32-scalar-imagic.c",
+ "src/qu8-igemm/gen/1x2-minmax-fp32-scalar-imagic.c",
+ "src/qu8-igemm/gen/2x2-minmax-fp32-scalar-imagic.c",
+ "src/qu8-vadd/gen/minmax-scalar-x4.c",
+ "src/qu8-vaddc/gen/minmax-scalar-x4.c",
+ "src/qu8-vmul/gen/minmax-fp32-scalar-x4.c",
+ "src/qu8-vmulc/gen/minmax-fp32-scalar-x4.c",
+ "src/s8-ibilinear/gen/scalar-c1.c",
+ "src/s8-maxpool/9p8x-minmax-scalar-c1.c",
+ "src/s8-vclamp/scalar-x4.c",
+ "src/u8-ibilinear/gen/scalar-c1.c",
+ "src/u8-maxpool/9p8x-minmax-scalar-c1.c",
+ "src/u8-rmax/scalar.c",
+ "src/u8-vclamp/scalar-x4.c",
+ "src/x8-zip/x2-scalar.c",
+ "src/x8-zip/x3-scalar.c",
+ "src/x8-zip/x4-scalar.c",
+ "src/x8-zip/xm-scalar.c",
+ "src/x32-packx/x2-scalar.c",
+ "src/x32-packx/x3-scalar.c",
+ "src/x32-packx/x4-scalar.c",
+ "src/x32-unpool/scalar.c",
+ "src/x32-zip/x2-scalar.c",
+ "src/x32-zip/x3-scalar.c",
+ "src/x32-zip/x4-scalar.c",
+ "src/x32-zip/xm-scalar.c",
+ "src/xx-fill/scalar-x16.c",
+ "src/xx-pad/scalar.c",
+]
+
+PROD_SCALAR_RISCV_MICROKERNEL_SRCS = [
+ "src/f16-f32-vcvt/gen/vcvt-scalar-x4.c",
+ "src/f32-argmaxpool/4x-scalar-c1.c",
+ "src/f32-argmaxpool/9p8x-scalar-c1.c",
+ "src/f32-argmaxpool/9x-scalar-c1.c",
+ "src/f32-avgpool/9p8x-minmax-scalar-c1.c",
+ "src/f32-avgpool/9x-minmax-scalar-c1.c",
+ "src/f32-conv-hwc/3x3s2p0p1c3x4-scalar-1x1.c",
+ "src/f32-conv-hwc/3x3s2p1c3x4-scalar-1x1.c",
+ "src/f32-conv-hwc2chw/3x3s2p1c3x4-scalar-1x1.c",
+ "src/f32-dwconv/gen/up1x3-minmax-scalar-acc2.c",
+ "src/f32-dwconv/gen/up1x3-scalar-acc2.c",
+ "src/f32-dwconv/gen/up1x4-minmax-scalar-acc2.c",
+ "src/f32-dwconv/gen/up1x4-scalar-acc2.c",
+ "src/f32-dwconv/gen/up1x9-minmax-scalar-acc2.c",
+ "src/f32-dwconv/gen/up1x9-scalar-acc2.c",
+ "src/f32-dwconv/gen/up1x25-minmax-scalar-acc2.c",
+ "src/f32-dwconv/gen/up1x25-scalar-acc2.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-scalar-2x1-acc2.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-scalar-1x1-acc2.c",
+ "src/f32-dwconv2d-chw/gen/5x5p2-minmax-scalar-1x1-acc5.c",
+ "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-1x1-acc5.c",
+ "src/f32-f16-vcvt/gen/vcvt-scalar-fabsf-x2.c",
+ "src/f32-gavgpool-cw/scalar-x1.c",
+ "src/f32-gavgpool/7p7x-minmax-scalar-c1.c",
+ "src/f32-gavgpool/7x-minmax-scalar-c1.c",
+ "src/f32-gemm/gen/1x4-minmax-scalar.c",
+ "src/f32-gemm/gen/1x4-relu-scalar.c",
+ "src/f32-gemm/gen/1x4-scalar.c",
+ "src/f32-gemm/gen/4x2-minmax-scalar.c",
+ "src/f32-gemm/gen/4x2-scalar.c",
+ "src/f32-gemm/gen/4x4-minmax-scalar.c",
+ "src/f32-gemm/gen/4x4-relu-scalar.c",
+ "src/f32-gemm/gen/4x4-scalar.c",
+ "src/f32-ibilinear-chw/gen/scalar-p4.c",
+ "src/f32-ibilinear/gen/scalar-c2.c",
+ "src/f32-igemm/gen/1x4-minmax-scalar.c",
+ "src/f32-igemm/gen/1x4-relu-scalar.c",
+ "src/f32-igemm/gen/1x4-scalar.c",
+ "src/f32-igemm/gen/4x2-minmax-scalar.c",
+ "src/f32-igemm/gen/4x2-scalar.c",
+ "src/f32-igemm/gen/4x4-minmax-scalar.c",
+ "src/f32-igemm/gen/4x4-relu-scalar.c",
+ "src/f32-igemm/gen/4x4-scalar.c",
+ "src/f32-maxpool/9p8x-minmax-scalar-c1.c",
+ "src/f32-pavgpool/9p8x-minmax-scalar-c1.c",
+ "src/f32-pavgpool/9x-minmax-scalar-c1.c",
+ "src/f32-prelu/gen/scalar-2x4.c",
+ "src/f32-qs8-vcvt/gen/vcvt-scalar-lrintf-x4.c",
+ "src/f32-qu8-vcvt/gen/vcvt-scalar-lrintf-x4.c",
+ "src/f32-raddstoreexpminusmax/gen/scalar-rr2-p5-x4-acc2.c",
+ "src/f32-rmax/scalar.c",
+ "src/f32-spmm/gen/8x1-minmax-scalar.c",
+ "src/f32-spmm/gen/8x2-minmax-scalar.c",
+ "src/f32-spmm/gen/8x4-minmax-scalar.c",
+ "src/f32-vbinary/gen/vadd-minmax-scalar-x8.c",
+ "src/f32-vbinary/gen/vaddc-minmax-scalar-x8.c",
+ "src/f32-vbinary/gen/vdiv-minmax-scalar-x2.c",
+ "src/f32-vbinary/gen/vdivc-minmax-scalar-x2.c",
+ "src/f32-vbinary/gen/vmax-scalar-x8.c",
+ "src/f32-vbinary/gen/vmaxc-scalar-x8.c",
+ "src/f32-vbinary/gen/vmin-scalar-x8.c",
+ "src/f32-vbinary/gen/vminc-scalar-x8.c",
+ "src/f32-vbinary/gen/vmul-minmax-scalar-x8.c",
+ "src/f32-vbinary/gen/vmulc-minmax-scalar-x8.c",
+ "src/f32-vbinary/gen/vrdivc-minmax-scalar-x2.c",
+ "src/f32-vbinary/gen/vrsubc-minmax-scalar-x8.c",
+ "src/f32-vbinary/gen/vsqrdiff-scalar-x8.c",
+ "src/f32-vbinary/gen/vsqrdiffc-scalar-x8.c",
+ "src/f32-vbinary/gen/vsub-minmax-scalar-x8.c",
+ "src/f32-vbinary/gen/vsubc-minmax-scalar-x8.c",
+ "src/f32-vclamp/gen/vclamp-scalar-x4.c",
+ "src/f32-velu/gen/velu-scalar-rr2-lut16-p3-x4.c",
+ "src/f32-vhswish/gen/vhswish-scalar-x4.c",
+ "src/f32-vlrelu/gen/vlrelu-scalar-x4.c",
+ "src/f32-vmulcaddc/gen/c1-minmax-scalar-2x.c",
+ "src/f32-vrelu/gen/vrelu-scalar-x8.c",
+ "src/f32-vrnd/gen/vrndd-scalar-libm-x1.c",
+ "src/f32-vrnd/gen/vrndne-scalar-libm-x1.c",
+ "src/f32-vrnd/gen/vrndu-scalar-libm-x1.c",
+ "src/f32-vrnd/gen/vrndz-scalar-libm-x1.c",
+ "src/f32-vsigmoid/gen/vsigmoid-scalar-rr2-lut64-p2-div-x2.c",
+ "src/f32-vsqrt/gen/scalar-sqrt-x1.c",
+ "src/f32-vunary/gen/vabs-scalar-x4.c",
+ "src/f32-vunary/gen/vneg-scalar-x4.c",
+ "src/f32-vunary/gen/vsqr-scalar-x4.c",
+ "src/qc8-dwconv/gen/up2x9-minmax-fp32-scalar-lrintf.c",
+ "src/qc8-dwconv/gen/up2x25-minmax-fp32-scalar-lrintf.c",
+ "src/qc8-gemm/gen/1x4-minmax-fp32-scalar-lrintf.c",
+ "src/qc8-gemm/gen/3x4-minmax-fp32-scalar-lrintf.c",
+ "src/qc8-igemm/gen/1x4-minmax-fp32-scalar-lrintf.c",
+ "src/qc8-igemm/gen/3x4-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-dwconv/gen/up2x9-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-dwconv/gen/up2x25-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-f32-vcvt/gen/vcvt-scalar-x4.c",
+ "src/qs8-gavgpool/gen/7p7x-minmax-fp32-scalar-imagic-c1.c",
+ "src/qs8-gavgpool/gen/7x-minmax-fp32-scalar-imagic-c1.c",
+ "src/qs8-gemm/gen/1x4-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-gemm/gen/3x4-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-igemm/gen/1x4-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-igemm/gen/3x4-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-vadd/gen/minmax-scalar-x4.c",
+ "src/qs8-vaddc/gen/minmax-scalar-x4.c",
+ "src/qs8-vmul/gen/minmax-fp32-scalar-x4.c",
+ "src/qs8-vmulc/gen/minmax-fp32-scalar-x4.c",
+ "src/qu8-avgpool/9p8x-minmax-scalar-c1.c",
+ "src/qu8-avgpool/9x-minmax-scalar-c1.c",
+ "src/qu8-dwconv/gen/up2x9-minmax-fp32-scalar-lrintf.c",
+ "src/qu8-dwconv/gen/up2x25-minmax-fp32-scalar-lrintf.c",
+ "src/qu8-f32-vcvt/gen/vcvt-scalar-x4.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-scalar-imagic-c1.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-scalar-imagic-c1.c",
+ "src/qu8-gemm/gen/1x4-minmax-fp32-scalar-lrintf.c",
+ "src/qu8-gemm/gen/3x4-minmax-fp32-scalar-lrintf.c",
+ "src/qu8-igemm/gen/1x4-minmax-fp32-scalar-lrintf.c",
+ "src/qu8-igemm/gen/3x4-minmax-fp32-scalar-lrintf.c",
+ "src/qu8-vadd/gen/minmax-scalar-x4.c",
+ "src/qu8-vaddc/gen/minmax-scalar-x4.c",
+ "src/qu8-vmul/gen/minmax-fp32-scalar-x4.c",
+ "src/qu8-vmulc/gen/minmax-fp32-scalar-x4.c",
+ "src/s8-ibilinear/gen/scalar-c1.c",
+ "src/s8-maxpool/9p8x-minmax-scalar-c1.c",
+ "src/s8-vclamp/scalar-x4.c",
+ "src/u8-ibilinear/gen/scalar-c1.c",
+ "src/u8-maxpool/9p8x-minmax-scalar-c1.c",
+ "src/u8-rmax/scalar.c",
+ "src/u8-vclamp/scalar-x4.c",
+ "src/x8-zip/x2-scalar.c",
+ "src/x8-zip/x3-scalar.c",
+ "src/x8-zip/x4-scalar.c",
+ "src/x8-zip/xm-scalar.c",
+ "src/x32-packx/x2-scalar.c",
+ "src/x32-packx/x3-scalar.c",
+ "src/x32-packx/x4-scalar.c",
+ "src/x32-unpool/scalar.c",
+ "src/x32-zip/x2-scalar.c",
+ "src/x32-zip/x3-scalar.c",
+ "src/x32-zip/x4-scalar.c",
+ "src/x32-zip/xm-scalar.c",
+ "src/xx-fill/scalar-x16.c",
+ "src/xx-pad/scalar.c",
+]
+
+ALL_SCALAR_MICROKERNEL_SRCS = [
+ "src/f16-f32-vcvt/gen/vcvt-scalar-x1.c",
+ "src/f16-f32-vcvt/gen/vcvt-scalar-x2.c",
+ "src/f16-f32-vcvt/gen/vcvt-scalar-x3.c",
+ "src/f16-f32-vcvt/gen/vcvt-scalar-x4.c",
+ "src/f32-argmaxpool/4x-scalar-c1.c",
+ "src/f32-argmaxpool/9p8x-scalar-c1.c",
+ "src/f32-argmaxpool/9x-scalar-c1.c",
+ "src/f32-avgpool/9p8x-minmax-scalar-c1.c",
+ "src/f32-avgpool/9x-minmax-scalar-c1.c",
+ "src/f32-conv-hwc/3x3s2p0p1c3x4-scalar-1x1.c",
+ "src/f32-conv-hwc/3x3s2p1c3x4-scalar-1x1.c",
+ "src/f32-conv-hwc2chw/3x3s2p1c3x4-scalar-1x1.c",
+ "src/f32-dwconv/gen/up1x3-minmax-scalar-acc2.c",
+ "src/f32-dwconv/gen/up1x3-minmax-scalar.c",
+ "src/f32-dwconv/gen/up1x3-scalar-acc2.c",
+ "src/f32-dwconv/gen/up1x3-scalar.c",
"src/f32-dwconv/gen/up1x4-minmax-scalar-acc2.c",
"src/f32-dwconv/gen/up1x4-minmax-scalar.c",
"src/f32-dwconv/gen/up1x4-scalar-acc2.c",
@@ -130,6 +563,10 @@
"src/f32-dwconv/gen/up1x25-minmax-scalar.c",
"src/f32-dwconv/gen/up1x25-scalar-acc2.c",
"src/f32-dwconv/gen/up1x25-scalar.c",
+ "src/f32-dwconv/gen/up2x3-minmax-scalar-acc2.c",
+ "src/f32-dwconv/gen/up2x3-minmax-scalar.c",
+ "src/f32-dwconv/gen/up2x3-scalar-acc2.c",
+ "src/f32-dwconv/gen/up2x3-scalar.c",
"src/f32-dwconv/gen/up2x4-minmax-scalar-acc2.c",
"src/f32-dwconv/gen/up2x4-minmax-scalar.c",
"src/f32-dwconv/gen/up2x4-scalar-acc2.c",
@@ -180,6 +617,14 @@
"src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-2x1.c",
"src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-3x1-acc2.c",
"src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-3x1.c",
+ "src/f32-f16-vcvt/gen/vcvt-scalar-bitcast-x1.c",
+ "src/f32-f16-vcvt/gen/vcvt-scalar-bitcast-x2.c",
+ "src/f32-f16-vcvt/gen/vcvt-scalar-bitcast-x3.c",
+ "src/f32-f16-vcvt/gen/vcvt-scalar-bitcast-x4.c",
+ "src/f32-f16-vcvt/gen/vcvt-scalar-fabsf-x1.c",
+ "src/f32-f16-vcvt/gen/vcvt-scalar-fabsf-x2.c",
+ "src/f32-f16-vcvt/gen/vcvt-scalar-fabsf-x3.c",
+ "src/f32-f16-vcvt/gen/vcvt-scalar-fabsf-x4.c",
"src/f32-gavgpool-cw/scalar-x1.c",
"src/f32-gavgpool/7p7x-minmax-scalar-c1.c",
"src/f32-gavgpool/7x-minmax-scalar-c1.c",
@@ -198,9 +643,6 @@
"src/f32-gemm/gen/4x4-minmax-scalar.c",
"src/f32-gemm/gen/4x4-relu-scalar.c",
"src/f32-gemm/gen/4x4-scalar.c",
- "src/f32-hswish/gen/hswish-scalar-x1.c",
- "src/f32-hswish/gen/hswish-scalar-x2.c",
- "src/f32-hswish/gen/hswish-scalar-x4.c",
"src/f32-ibilinear-chw/gen/scalar-p1.c",
"src/f32-ibilinear-chw/gen/scalar-p2.c",
"src/f32-ibilinear-chw/gen/scalar-p4.c",
@@ -228,32 +670,43 @@
"src/f32-ppmm/gen/4x4-minmax-scalar.c",
"src/f32-prelu/gen/scalar-2x1.c",
"src/f32-prelu/gen/scalar-2x4.c",
- "src/f32-raddstoreexpminusmax/gen/scalar-lut64-p2-x1.c",
- "src/f32-raddstoreexpminusmax/gen/scalar-lut64-p2-x2-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/scalar-lut64-p2-x2.c",
- "src/f32-raddstoreexpminusmax/gen/scalar-lut64-p2-x4-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/scalar-lut64-p2-x4-acc4.c",
- "src/f32-raddstoreexpminusmax/gen/scalar-lut64-p2-x4.c",
- "src/f32-raddstoreexpminusmax/gen/scalar-p5-x1.c",
- "src/f32-raddstoreexpminusmax/gen/scalar-p5-x2-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/scalar-p5-x2.c",
- "src/f32-raddstoreexpminusmax/gen/scalar-p5-x4-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/scalar-p5-x4-acc4.c",
- "src/f32-raddstoreexpminusmax/gen/scalar-p5-x4.c",
- "src/f32-relu/gen/scalar-x1.c",
- "src/f32-relu/gen/scalar-x2.c",
- "src/f32-relu/gen/scalar-x4.c",
- "src/f32-relu/gen/scalar-x8.c",
+ "src/f32-qs8-vcvt/gen/vcvt-scalar-fmagic-x1.c",
+ "src/f32-qs8-vcvt/gen/vcvt-scalar-fmagic-x2.c",
+ "src/f32-qs8-vcvt/gen/vcvt-scalar-fmagic-x3.c",
+ "src/f32-qs8-vcvt/gen/vcvt-scalar-fmagic-x4.c",
+ "src/f32-qs8-vcvt/gen/vcvt-scalar-imagic-x1.c",
+ "src/f32-qs8-vcvt/gen/vcvt-scalar-imagic-x2.c",
+ "src/f32-qs8-vcvt/gen/vcvt-scalar-imagic-x3.c",
+ "src/f32-qs8-vcvt/gen/vcvt-scalar-imagic-x4.c",
+ "src/f32-qs8-vcvt/gen/vcvt-scalar-lrintf-x1.c",
+ "src/f32-qs8-vcvt/gen/vcvt-scalar-lrintf-x2.c",
+ "src/f32-qs8-vcvt/gen/vcvt-scalar-lrintf-x3.c",
+ "src/f32-qs8-vcvt/gen/vcvt-scalar-lrintf-x4.c",
+ "src/f32-qu8-vcvt/gen/vcvt-scalar-fmagic-x1.c",
+ "src/f32-qu8-vcvt/gen/vcvt-scalar-fmagic-x2.c",
+ "src/f32-qu8-vcvt/gen/vcvt-scalar-fmagic-x3.c",
+ "src/f32-qu8-vcvt/gen/vcvt-scalar-fmagic-x4.c",
+ "src/f32-qu8-vcvt/gen/vcvt-scalar-imagic-x1.c",
+ "src/f32-qu8-vcvt/gen/vcvt-scalar-imagic-x2.c",
+ "src/f32-qu8-vcvt/gen/vcvt-scalar-imagic-x3.c",
+ "src/f32-qu8-vcvt/gen/vcvt-scalar-imagic-x4.c",
+ "src/f32-qu8-vcvt/gen/vcvt-scalar-lrintf-x1.c",
+ "src/f32-qu8-vcvt/gen/vcvt-scalar-lrintf-x2.c",
+ "src/f32-qu8-vcvt/gen/vcvt-scalar-lrintf-x3.c",
+ "src/f32-qu8-vcvt/gen/vcvt-scalar-lrintf-x4.c",
+ "src/f32-raddstoreexpminusmax/gen/scalar-rr2-lut64-p2-x1.c",
+ "src/f32-raddstoreexpminusmax/gen/scalar-rr2-lut64-p2-x2-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/scalar-rr2-lut64-p2-x2.c",
+ "src/f32-raddstoreexpminusmax/gen/scalar-rr2-lut64-p2-x4-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/scalar-rr2-lut64-p2-x4-acc4.c",
+ "src/f32-raddstoreexpminusmax/gen/scalar-rr2-lut64-p2-x4.c",
+ "src/f32-raddstoreexpminusmax/gen/scalar-rr2-p5-x1.c",
+ "src/f32-raddstoreexpminusmax/gen/scalar-rr2-p5-x2-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/scalar-rr2-p5-x2.c",
+ "src/f32-raddstoreexpminusmax/gen/scalar-rr2-p5-x4-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/scalar-rr2-p5-x4-acc4.c",
+ "src/f32-raddstoreexpminusmax/gen/scalar-rr2-p5-x4.c",
"src/f32-rmax/scalar.c",
- "src/f32-sigmoid/gen/scalar-lut64-p2-div-x1.c",
- "src/f32-sigmoid/gen/scalar-lut64-p2-div-x2.c",
- "src/f32-sigmoid/gen/scalar-lut64-p2-div-x4.c",
- "src/f32-sigmoid/gen/scalar-lut2048-p1-div-x1.c",
- "src/f32-sigmoid/gen/scalar-lut2048-p1-div-x2.c",
- "src/f32-sigmoid/gen/scalar-lut2048-p1-div-x4.c",
- "src/f32-sigmoid/gen/scalar-p5-div-x1.c",
- "src/f32-sigmoid/gen/scalar-p5-div-x2.c",
- "src/f32-sigmoid/gen/scalar-p5-div-x4.c",
"src/f32-spmm/gen/1x1-minmax-scalar-pipelined.c",
"src/f32-spmm/gen/1x1-minmax-scalar.c",
"src/f32-spmm/gen/2x1-minmax-scalar-pipelined.c",
@@ -408,6 +861,9 @@
"src/f32-vbinary/gen/vsubc-scalar-x2.c",
"src/f32-vbinary/gen/vsubc-scalar-x4.c",
"src/f32-vbinary/gen/vsubc-scalar-x8.c",
+ "src/f32-vclamp/gen/vclamp-scalar-x1.c",
+ "src/f32-vclamp/gen/vclamp-scalar-x2.c",
+ "src/f32-vclamp/gen/vclamp-scalar-x4.c",
"src/f32-velu/gen/velu-scalar-rr2-lut16-p3-x1.c",
"src/f32-velu/gen/velu-scalar-rr2-lut16-p3-x2.c",
"src/f32-velu/gen/velu-scalar-rr2-lut16-p3-x3.c",
@@ -420,12 +876,19 @@
"src/f32-velu/gen/velu-scalar-rr2-p6-x4.c",
"src/f32-velu/gen/velu-scalar-rr2-p6-x5.c",
"src/f32-velu/gen/velu-scalar-rr2-p6-x6.c",
+ "src/f32-vhswish/gen/vhswish-scalar-x1.c",
+ "src/f32-vhswish/gen/vhswish-scalar-x2.c",
+ "src/f32-vhswish/gen/vhswish-scalar-x4.c",
"src/f32-vlrelu/gen/vlrelu-scalar-x1.c",
"src/f32-vlrelu/gen/vlrelu-scalar-x2.c",
"src/f32-vlrelu/gen/vlrelu-scalar-x4.c",
"src/f32-vmulcaddc/gen/c1-minmax-scalar-2x.c",
"src/f32-vmulcaddc/gen/c2-minmax-scalar-2x.c",
"src/f32-vmulcaddc/gen/c4-minmax-scalar-2x.c",
+ "src/f32-vrelu/gen/vrelu-scalar-x1.c",
+ "src/f32-vrelu/gen/vrelu-scalar-x2.c",
+ "src/f32-vrelu/gen/vrelu-scalar-x4.c",
+ "src/f32-vrelu/gen/vrelu-scalar-x8.c",
"src/f32-vrnd/gen/vrndd-scalar-libm-x1.c",
"src/f32-vrnd/gen/vrndd-scalar-libm-x2.c",
"src/f32-vrnd/gen/vrndd-scalar-libm-x4.c",
@@ -438,6 +901,15 @@
"src/f32-vrnd/gen/vrndz-scalar-libm-x1.c",
"src/f32-vrnd/gen/vrndz-scalar-libm-x2.c",
"src/f32-vrnd/gen/vrndz-scalar-libm-x4.c",
+ "src/f32-vsigmoid/gen/vsigmoid-scalar-rr2-lut64-p2-div-x1.c",
+ "src/f32-vsigmoid/gen/vsigmoid-scalar-rr2-lut64-p2-div-x2.c",
+ "src/f32-vsigmoid/gen/vsigmoid-scalar-rr2-lut64-p2-div-x4.c",
+ "src/f32-vsigmoid/gen/vsigmoid-scalar-rr2-lut2048-p1-div-x1.c",
+ "src/f32-vsigmoid/gen/vsigmoid-scalar-rr2-lut2048-p1-div-x2.c",
+ "src/f32-vsigmoid/gen/vsigmoid-scalar-rr2-lut2048-p1-div-x4.c",
+ "src/f32-vsigmoid/gen/vsigmoid-scalar-rr2-p5-div-x1.c",
+ "src/f32-vsigmoid/gen/vsigmoid-scalar-rr2-p5-div-x2.c",
+ "src/f32-vsigmoid/gen/vsigmoid-scalar-rr2-p5-div-x4.c",
"src/f32-vsqrt/gen/scalar-sqrt-x1.c",
"src/f32-vsqrt/gen/scalar-sqrt-x2.c",
"src/f32-vsqrt/gen/scalar-sqrt-x4.c",
@@ -450,6 +922,8 @@
"src/f32-vunary/gen/vsqr-scalar-x1.c",
"src/f32-vunary/gen/vsqr-scalar-x2.c",
"src/f32-vunary/gen/vsqr-scalar-x4.c",
+ "src/math/cvt-f32-f16-scalar-bitcast.c",
+ "src/math/cvt-f32-f16-scalar-fabsf.c",
"src/math/expm1minus-scalar-rr2-lut4-p4.c",
"src/math/expm1minus-scalar-rr2-lut8-p3.c",
"src/math/expm1minus-scalar-rr2-lut8-p4.c",
@@ -475,60 +949,1778 @@
"src/math/sigmoid-scalar-rr2-lut64-p2-div.c",
"src/math/sigmoid-scalar-rr2-lut2048-p1-div.c",
"src/math/sigmoid-scalar-rr2-p5-div.c",
+ "src/params-init.c",
+ "src/qc8-dwconv/gen/up1x9-minmax-fp32-scalar-fmagic.c",
+ "src/qc8-dwconv/gen/up1x9-minmax-fp32-scalar-imagic.c",
+ "src/qc8-dwconv/gen/up1x9-minmax-fp32-scalar-lrintf.c",
+ "src/qc8-dwconv/gen/up1x25-minmax-fp32-scalar-fmagic.c",
+ "src/qc8-dwconv/gen/up1x25-minmax-fp32-scalar-imagic.c",
+ "src/qc8-dwconv/gen/up1x25-minmax-fp32-scalar-lrintf.c",
+ "src/qc8-dwconv/gen/up2x9-minmax-fp32-scalar-fmagic.c",
+ "src/qc8-dwconv/gen/up2x9-minmax-fp32-scalar-imagic.c",
+ "src/qc8-dwconv/gen/up2x9-minmax-fp32-scalar-lrintf.c",
+ "src/qc8-dwconv/gen/up2x25-minmax-fp32-scalar-fmagic.c",
+ "src/qc8-dwconv/gen/up2x25-minmax-fp32-scalar-imagic.c",
+ "src/qc8-dwconv/gen/up2x25-minmax-fp32-scalar-lrintf.c",
+ "src/qc8-dwconv/gen/up4x9-minmax-fp32-scalar-fmagic.c",
+ "src/qc8-dwconv/gen/up4x9-minmax-fp32-scalar-imagic.c",
+ "src/qc8-dwconv/gen/up4x9-minmax-fp32-scalar-lrintf.c",
+ "src/qc8-dwconv/gen/up4x25-minmax-fp32-scalar-fmagic.c",
+ "src/qc8-dwconv/gen/up4x25-minmax-fp32-scalar-imagic.c",
+ "src/qc8-dwconv/gen/up4x25-minmax-fp32-scalar-lrintf.c",
+ "src/qc8-gemm/gen/1x2-minmax-fp32-scalar-fmagic.c",
+ "src/qc8-gemm/gen/1x2-minmax-fp32-scalar-imagic.c",
+ "src/qc8-gemm/gen/1x2-minmax-fp32-scalar-lrintf.c",
+ "src/qc8-gemm/gen/1x4-minmax-fp32-scalar-fmagic.c",
+ "src/qc8-gemm/gen/1x4-minmax-fp32-scalar-imagic.c",
+ "src/qc8-gemm/gen/1x4-minmax-fp32-scalar-lrintf.c",
+ "src/qc8-gemm/gen/2x2-minmax-fp32-scalar-fmagic.c",
+ "src/qc8-gemm/gen/2x2-minmax-fp32-scalar-imagic.c",
+ "src/qc8-gemm/gen/2x2-minmax-fp32-scalar-lrintf.c",
+ "src/qc8-gemm/gen/2x4-minmax-fp32-scalar-fmagic.c",
+ "src/qc8-gemm/gen/2x4-minmax-fp32-scalar-imagic.c",
+ "src/qc8-gemm/gen/2x4-minmax-fp32-scalar-lrintf.c",
+ "src/qc8-gemm/gen/3x2-minmax-fp32-scalar-fmagic.c",
+ "src/qc8-gemm/gen/3x2-minmax-fp32-scalar-imagic.c",
+ "src/qc8-gemm/gen/3x2-minmax-fp32-scalar-lrintf.c",
+ "src/qc8-gemm/gen/3x4-minmax-fp32-scalar-fmagic.c",
+ "src/qc8-gemm/gen/3x4-minmax-fp32-scalar-imagic.c",
+ "src/qc8-gemm/gen/3x4-minmax-fp32-scalar-lrintf.c",
+ "src/qc8-gemm/gen/4x2-minmax-fp32-scalar-fmagic.c",
+ "src/qc8-gemm/gen/4x2-minmax-fp32-scalar-imagic.c",
+ "src/qc8-gemm/gen/4x2-minmax-fp32-scalar-lrintf.c",
+ "src/qc8-gemm/gen/4x4-minmax-fp32-scalar-fmagic.c",
+ "src/qc8-gemm/gen/4x4-minmax-fp32-scalar-imagic.c",
+ "src/qc8-gemm/gen/4x4-minmax-fp32-scalar-lrintf.c",
+ "src/qc8-igemm/gen/1x2-minmax-fp32-scalar-fmagic.c",
+ "src/qc8-igemm/gen/1x2-minmax-fp32-scalar-imagic.c",
+ "src/qc8-igemm/gen/1x2-minmax-fp32-scalar-lrintf.c",
+ "src/qc8-igemm/gen/1x4-minmax-fp32-scalar-fmagic.c",
+ "src/qc8-igemm/gen/1x4-minmax-fp32-scalar-imagic.c",
+ "src/qc8-igemm/gen/1x4-minmax-fp32-scalar-lrintf.c",
+ "src/qc8-igemm/gen/2x2-minmax-fp32-scalar-fmagic.c",
+ "src/qc8-igemm/gen/2x2-minmax-fp32-scalar-imagic.c",
+ "src/qc8-igemm/gen/2x2-minmax-fp32-scalar-lrintf.c",
+ "src/qc8-igemm/gen/2x4-minmax-fp32-scalar-fmagic.c",
+ "src/qc8-igemm/gen/2x4-minmax-fp32-scalar-imagic.c",
+ "src/qc8-igemm/gen/2x4-minmax-fp32-scalar-lrintf.c",
+ "src/qc8-igemm/gen/3x2-minmax-fp32-scalar-fmagic.c",
+ "src/qc8-igemm/gen/3x2-minmax-fp32-scalar-imagic.c",
+ "src/qc8-igemm/gen/3x2-minmax-fp32-scalar-lrintf.c",
+ "src/qc8-igemm/gen/3x4-minmax-fp32-scalar-fmagic.c",
+ "src/qc8-igemm/gen/3x4-minmax-fp32-scalar-imagic.c",
+ "src/qc8-igemm/gen/3x4-minmax-fp32-scalar-lrintf.c",
+ "src/qc8-igemm/gen/4x2-minmax-fp32-scalar-fmagic.c",
+ "src/qc8-igemm/gen/4x2-minmax-fp32-scalar-imagic.c",
+ "src/qc8-igemm/gen/4x2-minmax-fp32-scalar-lrintf.c",
+ "src/qc8-igemm/gen/4x4-minmax-fp32-scalar-fmagic.c",
+ "src/qc8-igemm/gen/4x4-minmax-fp32-scalar-imagic.c",
+ "src/qc8-igemm/gen/4x4-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-dwconv/gen/up1x9-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-dwconv/gen/up1x9-minmax-fp32-scalar-imagic.c",
+ "src/qs8-dwconv/gen/up1x9-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-dwconv/gen/up1x25-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-dwconv/gen/up1x25-minmax-fp32-scalar-imagic.c",
+ "src/qs8-dwconv/gen/up1x25-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-dwconv/gen/up2x9-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-dwconv/gen/up2x9-minmax-fp32-scalar-imagic.c",
+ "src/qs8-dwconv/gen/up2x9-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-dwconv/gen/up2x25-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-dwconv/gen/up2x25-minmax-fp32-scalar-imagic.c",
+ "src/qs8-dwconv/gen/up2x25-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-dwconv/gen/up4x9-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-dwconv/gen/up4x9-minmax-fp32-scalar-imagic.c",
+ "src/qs8-dwconv/gen/up4x9-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-dwconv/gen/up4x25-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-dwconv/gen/up4x25-minmax-fp32-scalar-imagic.c",
+ "src/qs8-dwconv/gen/up4x25-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-f32-vcvt/gen/vcvt-scalar-x1.c",
+ "src/qs8-f32-vcvt/gen/vcvt-scalar-x2.c",
+ "src/qs8-f32-vcvt/gen/vcvt-scalar-x3.c",
+ "src/qs8-f32-vcvt/gen/vcvt-scalar-x4.c",
+ "src/qs8-gavgpool/gen/7p7x-minmax-fp32-scalar-fmagic-c1.c",
+ "src/qs8-gavgpool/gen/7p7x-minmax-fp32-scalar-fmagic-c2.c",
+ "src/qs8-gavgpool/gen/7p7x-minmax-fp32-scalar-fmagic-c4.c",
+ "src/qs8-gavgpool/gen/7p7x-minmax-fp32-scalar-imagic-c1.c",
+ "src/qs8-gavgpool/gen/7p7x-minmax-fp32-scalar-imagic-c2.c",
+ "src/qs8-gavgpool/gen/7p7x-minmax-fp32-scalar-imagic-c4.c",
+ "src/qs8-gavgpool/gen/7p7x-minmax-fp32-scalar-lrintf-c1.c",
+ "src/qs8-gavgpool/gen/7p7x-minmax-fp32-scalar-lrintf-c2.c",
+ "src/qs8-gavgpool/gen/7p7x-minmax-fp32-scalar-lrintf-c4.c",
+ "src/qs8-gavgpool/gen/7x-minmax-fp32-scalar-fmagic-c1.c",
+ "src/qs8-gavgpool/gen/7x-minmax-fp32-scalar-fmagic-c2.c",
+ "src/qs8-gavgpool/gen/7x-minmax-fp32-scalar-fmagic-c4.c",
+ "src/qs8-gavgpool/gen/7x-minmax-fp32-scalar-imagic-c1.c",
+ "src/qs8-gavgpool/gen/7x-minmax-fp32-scalar-imagic-c2.c",
+ "src/qs8-gavgpool/gen/7x-minmax-fp32-scalar-imagic-c4.c",
+ "src/qs8-gavgpool/gen/7x-minmax-fp32-scalar-lrintf-c1.c",
+ "src/qs8-gavgpool/gen/7x-minmax-fp32-scalar-lrintf-c2.c",
+ "src/qs8-gavgpool/gen/7x-minmax-fp32-scalar-lrintf-c4.c",
+ "src/qs8-gemm/gen/1x2-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-gemm/gen/1x2-minmax-fp32-scalar-imagic.c",
+ "src/qs8-gemm/gen/1x2-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-gemm/gen/1x4-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-gemm/gen/1x4-minmax-fp32-scalar-imagic.c",
+ "src/qs8-gemm/gen/1x4-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-gemm/gen/2x2-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-gemm/gen/2x2-minmax-fp32-scalar-imagic.c",
+ "src/qs8-gemm/gen/2x2-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-gemm/gen/2x4-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-gemm/gen/2x4-minmax-fp32-scalar-imagic.c",
+ "src/qs8-gemm/gen/2x4-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-gemm/gen/3x2-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-gemm/gen/3x2-minmax-fp32-scalar-imagic.c",
+ "src/qs8-gemm/gen/3x2-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-gemm/gen/3x4-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-gemm/gen/3x4-minmax-fp32-scalar-imagic.c",
+ "src/qs8-gemm/gen/3x4-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-gemm/gen/4x2-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-gemm/gen/4x2-minmax-fp32-scalar-imagic.c",
+ "src/qs8-gemm/gen/4x2-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-gemm/gen/4x4-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-gemm/gen/4x4-minmax-fp32-scalar-imagic.c",
+ "src/qs8-gemm/gen/4x4-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-igemm/gen/1x2-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-igemm/gen/1x2-minmax-fp32-scalar-imagic.c",
+ "src/qs8-igemm/gen/1x2-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-igemm/gen/1x4-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-igemm/gen/1x4-minmax-fp32-scalar-imagic.c",
+ "src/qs8-igemm/gen/1x4-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-igemm/gen/2x2-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-igemm/gen/2x2-minmax-fp32-scalar-imagic.c",
+ "src/qs8-igemm/gen/2x2-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-igemm/gen/2x4-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-igemm/gen/2x4-minmax-fp32-scalar-imagic.c",
+ "src/qs8-igemm/gen/2x4-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-igemm/gen/3x2-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-igemm/gen/3x2-minmax-fp32-scalar-imagic.c",
+ "src/qs8-igemm/gen/3x2-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-igemm/gen/3x4-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-igemm/gen/3x4-minmax-fp32-scalar-imagic.c",
+ "src/qs8-igemm/gen/3x4-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-igemm/gen/4x2-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-igemm/gen/4x2-minmax-fp32-scalar-imagic.c",
+ "src/qs8-igemm/gen/4x2-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-igemm/gen/4x4-minmax-fp32-scalar-fmagic.c",
+ "src/qs8-igemm/gen/4x4-minmax-fp32-scalar-imagic.c",
+ "src/qs8-igemm/gen/4x4-minmax-fp32-scalar-lrintf.c",
+ "src/qs8-requantization/fp32-scalar-fmagic.c",
"src/qs8-requantization/fp32-scalar-lrintf.c",
- "src/qs8-requantization/fp32-scalar-magic.c",
- "src/qs8-requantization/precise-scalar-signed64.c",
- "src/qs8-requantization/precise-scalar-unsigned32.c",
- "src/qs8-requantization/precise-scalar-unsigned64.c",
- "src/qs8-requantization/q31-scalar.c",
+ "src/qs8-requantization/gemmlowp-scalar.c",
+ "src/qs8-requantization/rndna-scalar-signed64.c",
+ "src/qs8-requantization/rndna-scalar-unsigned32.c",
+ "src/qs8-requantization/rndna-scalar-unsigned64.c",
+ "src/qs8-requantization/rndnu-scalar.c",
+ "src/qs8-vadd/gen/minmax-scalar-x1.c",
+ "src/qs8-vadd/gen/minmax-scalar-x2.c",
+ "src/qs8-vadd/gen/minmax-scalar-x4.c",
+ "src/qs8-vaddc/gen/minmax-scalar-x1.c",
+ "src/qs8-vaddc/gen/minmax-scalar-x2.c",
+ "src/qs8-vaddc/gen/minmax-scalar-x4.c",
+ "src/qs8-vmul/gen/minmax-fp32-scalar-x1.c",
+ "src/qs8-vmul/gen/minmax-fp32-scalar-x2.c",
+ "src/qs8-vmul/gen/minmax-fp32-scalar-x4.c",
+ "src/qs8-vmulc/gen/minmax-fp32-scalar-x1.c",
+ "src/qs8-vmulc/gen/minmax-fp32-scalar-x2.c",
+ "src/qs8-vmulc/gen/minmax-fp32-scalar-x4.c",
"src/qu8-avgpool/9p8x-minmax-scalar-c1.c",
"src/qu8-avgpool/9x-minmax-scalar-c1.c",
- "src/qu8-dwconv/up1x9-minmax-scalar.c",
- "src/qu8-gavgpool/7p7x-minmax-scalar-c1.c",
- "src/qu8-gavgpool/7x-minmax-scalar-c1.c",
- "src/qu8-gemm/2x2-minmax-scalar.c",
- "src/qu8-igemm/2x2-minmax-scalar.c",
+ "src/qu8-dwconv/gen/up1x9-minmax-fp32-scalar-fmagic.c",
+ "src/qu8-dwconv/gen/up1x9-minmax-fp32-scalar-imagic.c",
+ "src/qu8-dwconv/gen/up1x9-minmax-fp32-scalar-lrintf.c",
+ "src/qu8-dwconv/gen/up1x25-minmax-fp32-scalar-fmagic.c",
+ "src/qu8-dwconv/gen/up1x25-minmax-fp32-scalar-imagic.c",
+ "src/qu8-dwconv/gen/up1x25-minmax-fp32-scalar-lrintf.c",
+ "src/qu8-dwconv/gen/up2x9-minmax-fp32-scalar-fmagic.c",
+ "src/qu8-dwconv/gen/up2x9-minmax-fp32-scalar-imagic.c",
+ "src/qu8-dwconv/gen/up2x9-minmax-fp32-scalar-lrintf.c",
+ "src/qu8-dwconv/gen/up2x25-minmax-fp32-scalar-fmagic.c",
+ "src/qu8-dwconv/gen/up2x25-minmax-fp32-scalar-imagic.c",
+ "src/qu8-dwconv/gen/up2x25-minmax-fp32-scalar-lrintf.c",
+ "src/qu8-dwconv/gen/up4x9-minmax-fp32-scalar-fmagic.c",
+ "src/qu8-dwconv/gen/up4x9-minmax-fp32-scalar-imagic.c",
+ "src/qu8-dwconv/gen/up4x9-minmax-fp32-scalar-lrintf.c",
+ "src/qu8-dwconv/gen/up4x25-minmax-fp32-scalar-fmagic.c",
+ "src/qu8-dwconv/gen/up4x25-minmax-fp32-scalar-imagic.c",
+ "src/qu8-dwconv/gen/up4x25-minmax-fp32-scalar-lrintf.c",
+ "src/qu8-f32-vcvt/gen/vcvt-scalar-x1.c",
+ "src/qu8-f32-vcvt/gen/vcvt-scalar-x2.c",
+ "src/qu8-f32-vcvt/gen/vcvt-scalar-x3.c",
+ "src/qu8-f32-vcvt/gen/vcvt-scalar-x4.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-scalar-fmagic-c1.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-scalar-fmagic-c2.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-scalar-fmagic-c4.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-scalar-imagic-c1.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-scalar-imagic-c2.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-scalar-imagic-c4.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-scalar-lrintf-c1.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-scalar-lrintf-c2.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-scalar-lrintf-c4.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-scalar-fmagic-c1.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-scalar-fmagic-c2.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-scalar-fmagic-c4.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-scalar-imagic-c1.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-scalar-imagic-c2.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-scalar-imagic-c4.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-scalar-lrintf-c1.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-scalar-lrintf-c2.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-scalar-lrintf-c4.c",
+ "src/qu8-gemm/gen/1x2-minmax-fp32-scalar-fmagic.c",
+ "src/qu8-gemm/gen/1x2-minmax-fp32-scalar-imagic.c",
+ "src/qu8-gemm/gen/1x2-minmax-fp32-scalar-lrintf.c",
+ "src/qu8-gemm/gen/1x4-minmax-fp32-scalar-fmagic.c",
+ "src/qu8-gemm/gen/1x4-minmax-fp32-scalar-imagic.c",
+ "src/qu8-gemm/gen/1x4-minmax-fp32-scalar-lrintf.c",
+ "src/qu8-gemm/gen/2x2-minmax-fp32-scalar-fmagic.c",
+ "src/qu8-gemm/gen/2x2-minmax-fp32-scalar-imagic.c",
+ "src/qu8-gemm/gen/2x2-minmax-fp32-scalar-lrintf.c",
+ "src/qu8-gemm/gen/2x4-minmax-fp32-scalar-fmagic.c",
+ "src/qu8-gemm/gen/2x4-minmax-fp32-scalar-imagic.c",
+ "src/qu8-gemm/gen/2x4-minmax-fp32-scalar-lrintf.c",
+ "src/qu8-gemm/gen/3x2-minmax-fp32-scalar-fmagic.c",
+ "src/qu8-gemm/gen/3x2-minmax-fp32-scalar-imagic.c",
+ "src/qu8-gemm/gen/3x2-minmax-fp32-scalar-lrintf.c",
+ "src/qu8-gemm/gen/3x4-minmax-fp32-scalar-fmagic.c",
+ "src/qu8-gemm/gen/3x4-minmax-fp32-scalar-imagic.c",
+ "src/qu8-gemm/gen/3x4-minmax-fp32-scalar-lrintf.c",
+ "src/qu8-gemm/gen/4x2-minmax-fp32-scalar-fmagic.c",
+ "src/qu8-gemm/gen/4x2-minmax-fp32-scalar-imagic.c",
+ "src/qu8-gemm/gen/4x2-minmax-fp32-scalar-lrintf.c",
+ "src/qu8-gemm/gen/4x4-minmax-fp32-scalar-fmagic.c",
+ "src/qu8-gemm/gen/4x4-minmax-fp32-scalar-imagic.c",
+ "src/qu8-gemm/gen/4x4-minmax-fp32-scalar-lrintf.c",
+ "src/qu8-igemm/gen/1x2-minmax-fp32-scalar-fmagic.c",
+ "src/qu8-igemm/gen/1x2-minmax-fp32-scalar-imagic.c",
+ "src/qu8-igemm/gen/1x2-minmax-fp32-scalar-lrintf.c",
+ "src/qu8-igemm/gen/1x4-minmax-fp32-scalar-fmagic.c",
+ "src/qu8-igemm/gen/1x4-minmax-fp32-scalar-imagic.c",
+ "src/qu8-igemm/gen/1x4-minmax-fp32-scalar-lrintf.c",
+ "src/qu8-igemm/gen/2x2-minmax-fp32-scalar-fmagic.c",
+ "src/qu8-igemm/gen/2x2-minmax-fp32-scalar-imagic.c",
+ "src/qu8-igemm/gen/2x2-minmax-fp32-scalar-lrintf.c",
+ "src/qu8-igemm/gen/2x4-minmax-fp32-scalar-fmagic.c",
+ "src/qu8-igemm/gen/2x4-minmax-fp32-scalar-imagic.c",
+ "src/qu8-igemm/gen/2x4-minmax-fp32-scalar-lrintf.c",
+ "src/qu8-igemm/gen/3x2-minmax-fp32-scalar-fmagic.c",
+ "src/qu8-igemm/gen/3x2-minmax-fp32-scalar-imagic.c",
+ "src/qu8-igemm/gen/3x2-minmax-fp32-scalar-lrintf.c",
+ "src/qu8-igemm/gen/3x4-minmax-fp32-scalar-fmagic.c",
+ "src/qu8-igemm/gen/3x4-minmax-fp32-scalar-imagic.c",
+ "src/qu8-igemm/gen/3x4-minmax-fp32-scalar-lrintf.c",
+ "src/qu8-igemm/gen/4x2-minmax-fp32-scalar-fmagic.c",
+ "src/qu8-igemm/gen/4x2-minmax-fp32-scalar-imagic.c",
+ "src/qu8-igemm/gen/4x2-minmax-fp32-scalar-lrintf.c",
+ "src/qu8-igemm/gen/4x4-minmax-fp32-scalar-fmagic.c",
+ "src/qu8-igemm/gen/4x4-minmax-fp32-scalar-imagic.c",
+ "src/qu8-igemm/gen/4x4-minmax-fp32-scalar-lrintf.c",
+ "src/qu8-requantization/fp32-scalar-fmagic.c",
"src/qu8-requantization/fp32-scalar-lrintf.c",
- "src/qu8-requantization/fp32-scalar-magic.c",
- "src/qu8-requantization/precise-scalar-signed64.c",
- "src/qu8-requantization/precise-scalar-unsigned32.c",
- "src/qu8-requantization/precise-scalar-unsigned64.c",
- "src/qu8-requantization/q31-scalar.c",
- "src/qu8-vadd/minmax-scalar.c",
- "src/u8-clamp/scalar-x4.c",
+ "src/qu8-requantization/gemmlowp-scalar.c",
+ "src/qu8-requantization/rndna-scalar-signed64.c",
+ "src/qu8-requantization/rndna-scalar-unsigned32.c",
+ "src/qu8-requantization/rndna-scalar-unsigned64.c",
+ "src/qu8-vadd/gen/minmax-scalar-x1.c",
+ "src/qu8-vadd/gen/minmax-scalar-x2.c",
+ "src/qu8-vadd/gen/minmax-scalar-x4.c",
+ "src/qu8-vaddc/gen/minmax-scalar-x1.c",
+ "src/qu8-vaddc/gen/minmax-scalar-x2.c",
+ "src/qu8-vaddc/gen/minmax-scalar-x4.c",
+ "src/qu8-vmul/gen/minmax-fp32-scalar-x1.c",
+ "src/qu8-vmul/gen/minmax-fp32-scalar-x2.c",
+ "src/qu8-vmul/gen/minmax-fp32-scalar-x4.c",
+ "src/qu8-vmulc/gen/minmax-fp32-scalar-x1.c",
+ "src/qu8-vmulc/gen/minmax-fp32-scalar-x2.c",
+ "src/qu8-vmulc/gen/minmax-fp32-scalar-x4.c",
+ "src/s8-ibilinear/gen/scalar-c1.c",
+ "src/s8-ibilinear/gen/scalar-c2.c",
+ "src/s8-ibilinear/gen/scalar-c4.c",
+ "src/s8-maxpool/9p8x-minmax-scalar-c1.c",
+ "src/s8-vclamp/scalar-x4.c",
+ "src/u8-ibilinear/gen/scalar-c1.c",
+ "src/u8-ibilinear/gen/scalar-c2.c",
+ "src/u8-ibilinear/gen/scalar-c4.c",
"src/u8-lut32norm/scalar.c",
"src/u8-maxpool/9p8x-minmax-scalar-c1.c",
"src/u8-rmax/scalar.c",
- "src/x8-lut/scalar.c",
+ "src/u8-vclamp/scalar-x4.c",
+ "src/x8-lut/gen/lut-scalar-x1.c",
+ "src/x8-lut/gen/lut-scalar-x2.c",
+ "src/x8-lut/gen/lut-scalar-x4.c",
+ "src/x8-lut/gen/lut-scalar-x8.c",
+ "src/x8-lut/gen/lut-scalar-x16.c",
+ "src/x8-transpose/gen/1x2-scalar-int.c",
+ "src/x8-transpose/gen/1x4-scalar-int.c",
+ "src/x8-transpose/gen/2x1-scalar-int.c",
+ "src/x8-transpose/gen/2x2-scalar-int.c",
+ "src/x8-transpose/gen/2x4-scalar-int.c",
+ "src/x8-transpose/gen/4x1-scalar-int.c",
+ "src/x8-transpose/gen/4x2-scalar-int.c",
+ "src/x8-transpose/gen/4x4-scalar-int.c",
"src/x8-zip/x2-scalar.c",
"src/x8-zip/x3-scalar.c",
"src/x8-zip/x4-scalar.c",
"src/x8-zip/xm-scalar.c",
+ "src/x16-transpose/gen/1x2-scalar-int.c",
+ "src/x16-transpose/gen/1x4-scalar-int.c",
+ "src/x16-transpose/gen/2x1-scalar-int.c",
+ "src/x16-transpose/gen/2x2-scalar-int.c",
+ "src/x16-transpose/gen/2x4-scalar-int.c",
+ "src/x16-transpose/gen/4x1-scalar-int.c",
+ "src/x16-transpose/gen/4x2-scalar-int.c",
+ "src/x16-transpose/gen/4x4-scalar-int.c",
"src/x32-depthtospace2d-chw2hwc/scalar.c",
- "src/x32-fill/scalar-float.c",
- "src/x32-fill/scalar-int.c",
"src/x32-packx/x2-scalar.c",
"src/x32-packx/x3-scalar.c",
"src/x32-packx/x4-scalar.c",
- "src/x32-pad/scalar-float.c",
- "src/x32-pad/scalar-int.c",
+ "src/x32-transpose/gen/1x2-scalar-float.c",
+ "src/x32-transpose/gen/1x2-scalar-int.c",
+ "src/x32-transpose/gen/1x4-scalar-float.c",
+ "src/x32-transpose/gen/1x4-scalar-int.c",
+ "src/x32-transpose/gen/2x1-scalar-float.c",
+ "src/x32-transpose/gen/2x1-scalar-int.c",
+ "src/x32-transpose/gen/2x2-scalar-float.c",
+ "src/x32-transpose/gen/2x2-scalar-int.c",
+ "src/x32-transpose/gen/2x4-scalar-float.c",
+ "src/x32-transpose/gen/2x4-scalar-int.c",
+ "src/x32-transpose/gen/4x1-scalar-float.c",
+ "src/x32-transpose/gen/4x1-scalar-int.c",
+ "src/x32-transpose/gen/4x2-scalar-float.c",
+ "src/x32-transpose/gen/4x2-scalar-int.c",
+ "src/x32-transpose/gen/4x4-scalar-float.c",
+ "src/x32-transpose/gen/4x4-scalar-int.c",
"src/x32-unpool/scalar.c",
"src/x32-zip/x2-scalar.c",
"src/x32-zip/x3-scalar.c",
"src/x32-zip/x4-scalar.c",
"src/x32-zip/xm-scalar.c",
+ "src/x64-transpose/gen/1x2-scalar-float.c",
+ "src/x64-transpose/gen/1x2-scalar-int.c",
+ "src/x64-transpose/gen/2x1-scalar-float.c",
+ "src/x64-transpose/gen/2x1-scalar-int.c",
+ "src/x64-transpose/gen/2x2-scalar-float.c",
+ "src/x64-transpose/gen/2x2-scalar-int.c",
+ "src/x64-transpose/gen/4x1-scalar-float.c",
+ "src/x64-transpose/gen/4x1-scalar-int.c",
+ "src/x64-transpose/gen/4x2-scalar-float.c",
+ "src/x64-transpose/gen/4x2-scalar-int.c",
"src/xx-copy/memcpy.c",
+ "src/xx-fill/scalar-x16.c",
+ "src/xx-pad/scalar.c",
+]
+
+ALL_WASM_MICROKERNEL_SRCS = [
+ "src/f32-avgpool/9p8x-minmax-wasm-c1.c",
+ "src/f32-avgpool/9x-minmax-wasm-c1.c",
+ "src/f32-dwconv/gen/up1x3-minmax-wasm-acc2.c",
+ "src/f32-dwconv/gen/up1x3-minmax-wasm.c",
+ "src/f32-dwconv/gen/up1x3-wasm-acc2.c",
+ "src/f32-dwconv/gen/up1x3-wasm.c",
+ "src/f32-dwconv/gen/up1x4-minmax-wasm-acc2.c",
+ "src/f32-dwconv/gen/up1x4-minmax-wasm.c",
+ "src/f32-dwconv/gen/up1x4-wasm-acc2.c",
+ "src/f32-dwconv/gen/up1x4-wasm.c",
+ "src/f32-dwconv/gen/up1x9-minmax-wasm-acc2.c",
+ "src/f32-dwconv/gen/up1x9-minmax-wasm.c",
+ "src/f32-dwconv/gen/up1x9-wasm-acc2.c",
+ "src/f32-dwconv/gen/up1x9-wasm.c",
+ "src/f32-dwconv/gen/up1x25-minmax-wasm-acc2.c",
+ "src/f32-dwconv/gen/up1x25-minmax-wasm.c",
+ "src/f32-dwconv/gen/up1x25-wasm-acc2.c",
+ "src/f32-dwconv/gen/up1x25-wasm.c",
+ "src/f32-dwconv/gen/up2x3-minmax-wasm-acc2.c",
+ "src/f32-dwconv/gen/up2x3-minmax-wasm.c",
+ "src/f32-dwconv/gen/up2x3-wasm-acc2.c",
+ "src/f32-dwconv/gen/up2x3-wasm.c",
+ "src/f32-dwconv/gen/up2x4-minmax-wasm-acc2.c",
+ "src/f32-dwconv/gen/up2x4-minmax-wasm.c",
+ "src/f32-dwconv/gen/up2x4-wasm-acc2.c",
+ "src/f32-dwconv/gen/up2x4-wasm.c",
+ "src/f32-dwconv/gen/up2x9-minmax-wasm-acc2.c",
+ "src/f32-dwconv/gen/up2x9-minmax-wasm.c",
+ "src/f32-dwconv/gen/up2x9-wasm-acc2.c",
+ "src/f32-dwconv/gen/up2x9-wasm.c",
+ "src/f32-dwconv/gen/up2x25-minmax-wasm-acc2.c",
+ "src/f32-dwconv/gen/up2x25-minmax-wasm.c",
+ "src/f32-dwconv/gen/up2x25-wasm-acc2.c",
+ "src/f32-dwconv/gen/up2x25-wasm.c",
+ "src/f32-gavgpool/7p7x-minmax-wasm-c1.c",
+ "src/f32-gavgpool/7x-minmax-wasm-c1.c",
+ "src/f32-gemm/gen-inc/1x4inc-minmax-wasm.c",
+ "src/f32-gemm/gen-inc/2x4inc-minmax-wasm.c",
+ "src/f32-gemm/gen-inc/4x4inc-minmax-wasm.c",
+ "src/f32-gemm/gen/1x4-minmax-wasm.c",
+ "src/f32-gemm/gen/1x4-relu-wasm.c",
+ "src/f32-gemm/gen/1x4-wasm.c",
+ "src/f32-gemm/gen/2x4-minmax-wasm.c",
+ "src/f32-gemm/gen/2x4-relu-wasm.c",
+ "src/f32-gemm/gen/2x4-wasm.c",
+ "src/f32-gemm/gen/4x2-minmax-wasm.c",
+ "src/f32-gemm/gen/4x2-relu-wasm.c",
+ "src/f32-gemm/gen/4x2-wasm.c",
+ "src/f32-gemm/gen/4x4-minmax-wasm.c",
+ "src/f32-gemm/gen/4x4-relu-wasm.c",
+ "src/f32-gemm/gen/4x4-wasm.c",
+ "src/f32-igemm/gen/1x4-minmax-wasm.c",
+ "src/f32-igemm/gen/1x4-relu-wasm.c",
+ "src/f32-igemm/gen/1x4-wasm.c",
+ "src/f32-igemm/gen/2x4-minmax-wasm.c",
+ "src/f32-igemm/gen/2x4-relu-wasm.c",
+ "src/f32-igemm/gen/2x4-wasm.c",
+ "src/f32-igemm/gen/4x2-minmax-wasm.c",
+ "src/f32-igemm/gen/4x2-relu-wasm.c",
+ "src/f32-igemm/gen/4x2-wasm.c",
+ "src/f32-igemm/gen/4x4-minmax-wasm.c",
+ "src/f32-igemm/gen/4x4-relu-wasm.c",
+ "src/f32-igemm/gen/4x4-wasm.c",
+ "src/f32-maxpool/9p8x-minmax-wasm-c1.c",
+ "src/f32-pavgpool/9p8x-minmax-wasm-c1.c",
+ "src/f32-pavgpool/9x-minmax-wasm-c1.c",
+ "src/f32-prelu/gen/wasm-2x1.c",
+ "src/f32-prelu/gen/wasm-2x4.c",
+ "src/f32-qs8-vcvt/gen/vcvt-wasm-fmagic-x1.c",
+ "src/f32-qs8-vcvt/gen/vcvt-wasm-fmagic-x2.c",
+ "src/f32-qs8-vcvt/gen/vcvt-wasm-fmagic-x3.c",
+ "src/f32-qs8-vcvt/gen/vcvt-wasm-fmagic-x4.c",
+ "src/f32-qu8-vcvt/gen/vcvt-wasm-fmagic-x1.c",
+ "src/f32-qu8-vcvt/gen/vcvt-wasm-fmagic-x2.c",
+ "src/f32-qu8-vcvt/gen/vcvt-wasm-fmagic-x3.c",
+ "src/f32-qu8-vcvt/gen/vcvt-wasm-fmagic-x4.c",
+ "src/f32-vbinary/gen/vadd-minmax-wasm-x1.c",
+ "src/f32-vbinary/gen/vadd-minmax-wasm-x2.c",
+ "src/f32-vbinary/gen/vadd-minmax-wasm-x4.c",
+ "src/f32-vbinary/gen/vadd-minmax-wasm-x8.c",
+ "src/f32-vbinary/gen/vadd-relu-wasm-x1.c",
+ "src/f32-vbinary/gen/vadd-relu-wasm-x2.c",
+ "src/f32-vbinary/gen/vadd-relu-wasm-x4.c",
+ "src/f32-vbinary/gen/vadd-relu-wasm-x8.c",
+ "src/f32-vbinary/gen/vaddc-minmax-wasm-x1.c",
+ "src/f32-vbinary/gen/vaddc-minmax-wasm-x2.c",
+ "src/f32-vbinary/gen/vaddc-minmax-wasm-x4.c",
+ "src/f32-vbinary/gen/vaddc-minmax-wasm-x8.c",
+ "src/f32-vbinary/gen/vaddc-relu-wasm-x1.c",
+ "src/f32-vbinary/gen/vaddc-relu-wasm-x2.c",
+ "src/f32-vbinary/gen/vaddc-relu-wasm-x4.c",
+ "src/f32-vbinary/gen/vaddc-relu-wasm-x8.c",
+ "src/f32-vbinary/gen/vdiv-minmax-wasm-x1.c",
+ "src/f32-vbinary/gen/vdiv-minmax-wasm-x2.c",
+ "src/f32-vbinary/gen/vdiv-minmax-wasm-x4.c",
+ "src/f32-vbinary/gen/vdiv-minmax-wasm-x8.c",
+ "src/f32-vbinary/gen/vdiv-relu-wasm-x1.c",
+ "src/f32-vbinary/gen/vdiv-relu-wasm-x2.c",
+ "src/f32-vbinary/gen/vdiv-relu-wasm-x4.c",
+ "src/f32-vbinary/gen/vdiv-relu-wasm-x8.c",
+ "src/f32-vbinary/gen/vdivc-minmax-wasm-x1.c",
+ "src/f32-vbinary/gen/vdivc-minmax-wasm-x2.c",
+ "src/f32-vbinary/gen/vdivc-minmax-wasm-x4.c",
+ "src/f32-vbinary/gen/vdivc-minmax-wasm-x8.c",
+ "src/f32-vbinary/gen/vdivc-relu-wasm-x1.c",
+ "src/f32-vbinary/gen/vdivc-relu-wasm-x2.c",
+ "src/f32-vbinary/gen/vdivc-relu-wasm-x4.c",
+ "src/f32-vbinary/gen/vdivc-relu-wasm-x8.c",
+ "src/f32-vbinary/gen/vmax-wasm-x1.c",
+ "src/f32-vbinary/gen/vmax-wasm-x2.c",
+ "src/f32-vbinary/gen/vmax-wasm-x4.c",
+ "src/f32-vbinary/gen/vmax-wasm-x8.c",
+ "src/f32-vbinary/gen/vmaxc-wasm-x1.c",
+ "src/f32-vbinary/gen/vmaxc-wasm-x2.c",
+ "src/f32-vbinary/gen/vmaxc-wasm-x4.c",
+ "src/f32-vbinary/gen/vmaxc-wasm-x8.c",
+ "src/f32-vbinary/gen/vmin-wasm-x1.c",
+ "src/f32-vbinary/gen/vmin-wasm-x2.c",
+ "src/f32-vbinary/gen/vmin-wasm-x4.c",
+ "src/f32-vbinary/gen/vmin-wasm-x8.c",
+ "src/f32-vbinary/gen/vminc-wasm-x1.c",
+ "src/f32-vbinary/gen/vminc-wasm-x2.c",
+ "src/f32-vbinary/gen/vminc-wasm-x4.c",
+ "src/f32-vbinary/gen/vminc-wasm-x8.c",
+ "src/f32-vbinary/gen/vmul-minmax-wasm-x1.c",
+ "src/f32-vbinary/gen/vmul-minmax-wasm-x2.c",
+ "src/f32-vbinary/gen/vmul-minmax-wasm-x4.c",
+ "src/f32-vbinary/gen/vmul-minmax-wasm-x8.c",
+ "src/f32-vbinary/gen/vmul-relu-wasm-x1.c",
+ "src/f32-vbinary/gen/vmul-relu-wasm-x2.c",
+ "src/f32-vbinary/gen/vmul-relu-wasm-x4.c",
+ "src/f32-vbinary/gen/vmul-relu-wasm-x8.c",
+ "src/f32-vbinary/gen/vmulc-minmax-wasm-x1.c",
+ "src/f32-vbinary/gen/vmulc-minmax-wasm-x2.c",
+ "src/f32-vbinary/gen/vmulc-minmax-wasm-x4.c",
+ "src/f32-vbinary/gen/vmulc-minmax-wasm-x8.c",
+ "src/f32-vbinary/gen/vmulc-relu-wasm-x1.c",
+ "src/f32-vbinary/gen/vmulc-relu-wasm-x2.c",
+ "src/f32-vbinary/gen/vmulc-relu-wasm-x4.c",
+ "src/f32-vbinary/gen/vmulc-relu-wasm-x8.c",
+ "src/f32-vbinary/gen/vrdivc-minmax-wasm-x1.c",
+ "src/f32-vbinary/gen/vrdivc-minmax-wasm-x2.c",
+ "src/f32-vbinary/gen/vrdivc-minmax-wasm-x4.c",
+ "src/f32-vbinary/gen/vrdivc-minmax-wasm-x8.c",
+ "src/f32-vbinary/gen/vrdivc-relu-wasm-x1.c",
+ "src/f32-vbinary/gen/vrdivc-relu-wasm-x2.c",
+ "src/f32-vbinary/gen/vrdivc-relu-wasm-x4.c",
+ "src/f32-vbinary/gen/vrdivc-relu-wasm-x8.c",
+ "src/f32-vbinary/gen/vrsubc-minmax-wasm-x1.c",
+ "src/f32-vbinary/gen/vrsubc-minmax-wasm-x2.c",
+ "src/f32-vbinary/gen/vrsubc-minmax-wasm-x4.c",
+ "src/f32-vbinary/gen/vrsubc-minmax-wasm-x8.c",
+ "src/f32-vbinary/gen/vrsubc-relu-wasm-x1.c",
+ "src/f32-vbinary/gen/vrsubc-relu-wasm-x2.c",
+ "src/f32-vbinary/gen/vrsubc-relu-wasm-x4.c",
+ "src/f32-vbinary/gen/vrsubc-relu-wasm-x8.c",
+ "src/f32-vbinary/gen/vsub-minmax-wasm-x1.c",
+ "src/f32-vbinary/gen/vsub-minmax-wasm-x2.c",
+ "src/f32-vbinary/gen/vsub-minmax-wasm-x4.c",
+ "src/f32-vbinary/gen/vsub-minmax-wasm-x8.c",
+ "src/f32-vbinary/gen/vsub-relu-wasm-x1.c",
+ "src/f32-vbinary/gen/vsub-relu-wasm-x2.c",
+ "src/f32-vbinary/gen/vsub-relu-wasm-x4.c",
+ "src/f32-vbinary/gen/vsub-relu-wasm-x8.c",
+ "src/f32-vbinary/gen/vsubc-minmax-wasm-x1.c",
+ "src/f32-vbinary/gen/vsubc-minmax-wasm-x2.c",
+ "src/f32-vbinary/gen/vsubc-minmax-wasm-x4.c",
+ "src/f32-vbinary/gen/vsubc-minmax-wasm-x8.c",
+ "src/f32-vbinary/gen/vsubc-relu-wasm-x1.c",
+ "src/f32-vbinary/gen/vsubc-relu-wasm-x2.c",
+ "src/f32-vbinary/gen/vsubc-relu-wasm-x4.c",
+ "src/f32-vbinary/gen/vsubc-relu-wasm-x8.c",
+ "src/f32-vclamp/gen/vclamp-wasm-x1.c",
+ "src/f32-vclamp/gen/vclamp-wasm-x2.c",
+ "src/f32-vclamp/gen/vclamp-wasm-x4.c",
+ "src/f32-velu/gen/velu-wasm-rr2-lut16-p3-x1.c",
+ "src/f32-velu/gen/velu-wasm-rr2-lut16-p3-x2.c",
+ "src/f32-velu/gen/velu-wasm-rr2-lut16-p3-x3.c",
+ "src/f32-velu/gen/velu-wasm-rr2-lut16-p3-x4.c",
+ "src/f32-velu/gen/velu-wasm-rr2-lut16-p3-x5.c",
+ "src/f32-velu/gen/velu-wasm-rr2-lut16-p3-x6.c",
+ "src/f32-velu/gen/velu-wasm-rr2-p6-x1.c",
+ "src/f32-velu/gen/velu-wasm-rr2-p6-x2.c",
+ "src/f32-velu/gen/velu-wasm-rr2-p6-x3.c",
+ "src/f32-velu/gen/velu-wasm-rr2-p6-x4.c",
+ "src/f32-velu/gen/velu-wasm-rr2-p6-x5.c",
+ "src/f32-velu/gen/velu-wasm-rr2-p6-x6.c",
+ "src/f32-vhswish/gen/vhswish-wasm-x1.c",
+ "src/f32-vhswish/gen/vhswish-wasm-x2.c",
+ "src/f32-vhswish/gen/vhswish-wasm-x4.c",
+ "src/f32-vlrelu/gen/vlrelu-wasm-x1.c",
+ "src/f32-vlrelu/gen/vlrelu-wasm-x2.c",
+ "src/f32-vlrelu/gen/vlrelu-wasm-x4.c",
+ "src/f32-vmulcaddc/gen/c1-minmax-wasm-2x.c",
+ "src/f32-vmulcaddc/gen/c2-minmax-wasm-2x.c",
+ "src/f32-vmulcaddc/gen/c4-minmax-wasm-2x.c",
+ "src/f32-vrelu/gen/vrelu-wasm-x1.c",
+ "src/f32-vrelu/gen/vrelu-wasm-x2.c",
+ "src/f32-vrelu/gen/vrelu-wasm-x4.c",
+ "src/f32-vrelu/gen/vrelu-wasm-x8.c",
+ "src/qc8-dwconv/gen/up1x9-minmax-fp32-wasm-fmagic.c",
+ "src/qc8-dwconv/gen/up1x25-minmax-fp32-wasm-fmagic.c",
+ "src/qc8-dwconv/gen/up2x9-minmax-fp32-wasm-fmagic.c",
+ "src/qc8-dwconv/gen/up2x25-minmax-fp32-wasm-fmagic.c",
+ "src/qc8-dwconv/gen/up4x9-minmax-fp32-wasm-fmagic.c",
+ "src/qc8-dwconv/gen/up4x25-minmax-fp32-wasm-fmagic.c",
+ "src/qc8-gemm/gen/1x2-minmax-fp32-wasm-fmagic.c",
+ "src/qc8-gemm/gen/1x4-minmax-fp32-wasm-fmagic.c",
+ "src/qc8-gemm/gen/2x2-minmax-fp32-wasm-fmagic.c",
+ "src/qc8-gemm/gen/2x4-minmax-fp32-wasm-fmagic.c",
+ "src/qc8-gemm/gen/3x2-minmax-fp32-wasm-fmagic.c",
+ "src/qc8-gemm/gen/3x4-minmax-fp32-wasm-fmagic.c",
+ "src/qc8-gemm/gen/4x2-minmax-fp32-wasm-fmagic.c",
+ "src/qc8-gemm/gen/4x4-minmax-fp32-wasm-fmagic.c",
+ "src/qc8-igemm/gen/1x2-minmax-fp32-wasm-fmagic.c",
+ "src/qc8-igemm/gen/1x4-minmax-fp32-wasm-fmagic.c",
+ "src/qc8-igemm/gen/2x2-minmax-fp32-wasm-fmagic.c",
+ "src/qc8-igemm/gen/2x4-minmax-fp32-wasm-fmagic.c",
+ "src/qc8-igemm/gen/3x2-minmax-fp32-wasm-fmagic.c",
+ "src/qc8-igemm/gen/3x4-minmax-fp32-wasm-fmagic.c",
+ "src/qc8-igemm/gen/4x2-minmax-fp32-wasm-fmagic.c",
+ "src/qc8-igemm/gen/4x4-minmax-fp32-wasm-fmagic.c",
+ "src/qs8-dwconv/gen/up1x9-minmax-fp32-wasm-fmagic.c",
+ "src/qs8-dwconv/gen/up1x25-minmax-fp32-wasm-fmagic.c",
+ "src/qs8-dwconv/gen/up2x9-minmax-fp32-wasm-fmagic.c",
+ "src/qs8-dwconv/gen/up2x25-minmax-fp32-wasm-fmagic.c",
+ "src/qs8-dwconv/gen/up4x9-minmax-fp32-wasm-fmagic.c",
+ "src/qs8-dwconv/gen/up4x25-minmax-fp32-wasm-fmagic.c",
+ "src/qs8-gemm/gen/1x2-minmax-fp32-wasm-fmagic.c",
+ "src/qs8-gemm/gen/1x4-minmax-fp32-wasm-fmagic.c",
+ "src/qs8-gemm/gen/2x2-minmax-fp32-wasm-fmagic.c",
+ "src/qs8-gemm/gen/2x4-minmax-fp32-wasm-fmagic.c",
+ "src/qs8-gemm/gen/3x2-minmax-fp32-wasm-fmagic.c",
+ "src/qs8-gemm/gen/3x4-minmax-fp32-wasm-fmagic.c",
+ "src/qs8-gemm/gen/4x2-minmax-fp32-wasm-fmagic.c",
+ "src/qs8-gemm/gen/4x4-minmax-fp32-wasm-fmagic.c",
+ "src/qs8-igemm/gen/1x2-minmax-fp32-wasm-fmagic.c",
+ "src/qs8-igemm/gen/1x4-minmax-fp32-wasm-fmagic.c",
+ "src/qs8-igemm/gen/2x2-minmax-fp32-wasm-fmagic.c",
+ "src/qs8-igemm/gen/2x4-minmax-fp32-wasm-fmagic.c",
+ "src/qs8-igemm/gen/3x2-minmax-fp32-wasm-fmagic.c",
+ "src/qs8-igemm/gen/3x4-minmax-fp32-wasm-fmagic.c",
+ "src/qs8-igemm/gen/4x2-minmax-fp32-wasm-fmagic.c",
+ "src/qs8-igemm/gen/4x4-minmax-fp32-wasm-fmagic.c",
+ "src/qu8-dwconv/gen/up1x9-minmax-fp32-wasm-fmagic.c",
+ "src/qu8-dwconv/gen/up1x25-minmax-fp32-wasm-fmagic.c",
+ "src/qu8-dwconv/gen/up2x9-minmax-fp32-wasm-fmagic.c",
+ "src/qu8-dwconv/gen/up2x25-minmax-fp32-wasm-fmagic.c",
+ "src/qu8-dwconv/gen/up4x9-minmax-fp32-wasm-fmagic.c",
+ "src/qu8-dwconv/gen/up4x25-minmax-fp32-wasm-fmagic.c",
+ "src/qu8-gemm/gen/1x2-minmax-fp32-wasm-fmagic.c",
+ "src/qu8-gemm/gen/1x4-minmax-fp32-wasm-fmagic.c",
+ "src/qu8-gemm/gen/2x2-minmax-fp32-wasm-fmagic.c",
+ "src/qu8-gemm/gen/2x4-minmax-fp32-wasm-fmagic.c",
+ "src/qu8-gemm/gen/3x2-minmax-fp32-wasm-fmagic.c",
+ "src/qu8-gemm/gen/3x4-minmax-fp32-wasm-fmagic.c",
+ "src/qu8-gemm/gen/4x2-minmax-fp32-wasm-fmagic.c",
+ "src/qu8-gemm/gen/4x4-minmax-fp32-wasm-fmagic.c",
+ "src/qu8-igemm/gen/1x2-minmax-fp32-wasm-fmagic.c",
+ "src/qu8-igemm/gen/1x4-minmax-fp32-wasm-fmagic.c",
+ "src/qu8-igemm/gen/2x2-minmax-fp32-wasm-fmagic.c",
+ "src/qu8-igemm/gen/2x4-minmax-fp32-wasm-fmagic.c",
+ "src/qu8-igemm/gen/3x2-minmax-fp32-wasm-fmagic.c",
+ "src/qu8-igemm/gen/3x4-minmax-fp32-wasm-fmagic.c",
+ "src/qu8-igemm/gen/4x2-minmax-fp32-wasm-fmagic.c",
+ "src/qu8-igemm/gen/4x4-minmax-fp32-wasm-fmagic.c",
+]
+
+ALL_WASMSIMD_MICROKERNEL_SRCS = [
+ "src/f16-f32-vcvt/gen/vcvt-wasmsimd-int16-x8.c",
+ "src/f16-f32-vcvt/gen/vcvt-wasmsimd-int16-x16.c",
+ "src/f16-f32-vcvt/gen/vcvt-wasmsimd-int16-x24.c",
+ "src/f16-f32-vcvt/gen/vcvt-wasmsimd-int16-x32.c",
+ "src/f16-f32-vcvt/gen/vcvt-wasmsimd-int32-x8.c",
+ "src/f16-f32-vcvt/gen/vcvt-wasmsimd-int32-x16.c",
+ "src/f16-f32-vcvt/gen/vcvt-wasmsimd-int32-x24.c",
+ "src/f16-f32-vcvt/gen/vcvt-wasmsimd-int32-x32.c",
+ "src/f32-argmaxpool/4x-wasmsimd-c4.c",
+ "src/f32-argmaxpool/9p8x-wasmsimd-c4.c",
+ "src/f32-argmaxpool/9x-wasmsimd-c4.c",
+ "src/f32-avgpool/9p8x-minmax-wasmsimd-arm-c4.c",
+ "src/f32-avgpool/9p8x-minmax-wasmsimd-x86-c4.c",
+ "src/f32-avgpool/9x-minmax-wasmsimd-arm-c4.c",
+ "src/f32-avgpool/9x-minmax-wasmsimd-x86-c4.c",
+ "src/f32-conv-hwc2chw/3x3s2p1c3x4-wasmsimd-2x2.c",
+ "src/f32-dwconv/gen/up4x3-minmax-wasmsimd-arm-acc2.c",
+ "src/f32-dwconv/gen/up4x3-minmax-wasmsimd-arm.c",
+ "src/f32-dwconv/gen/up4x3-minmax-wasmsimd-x86-acc2.c",
+ "src/f32-dwconv/gen/up4x3-minmax-wasmsimd-x86.c",
+ "src/f32-dwconv/gen/up4x3-wasmsimd.c",
+ "src/f32-dwconv/gen/up4x4-minmax-wasmsimd-arm-acc2.c",
+ "src/f32-dwconv/gen/up4x4-minmax-wasmsimd-arm.c",
+ "src/f32-dwconv/gen/up4x4-minmax-wasmsimd-x86-acc2.c",
+ "src/f32-dwconv/gen/up4x4-minmax-wasmsimd-x86.c",
+ "src/f32-dwconv/gen/up4x4-wasmsimd.c",
+ "src/f32-dwconv/gen/up4x9-minmax-wasmsimd-arm-acc2.c",
+ "src/f32-dwconv/gen/up4x9-minmax-wasmsimd-arm.c",
+ "src/f32-dwconv/gen/up4x9-minmax-wasmsimd-x86-acc2.c",
+ "src/f32-dwconv/gen/up4x9-minmax-wasmsimd-x86.c",
+ "src/f32-dwconv/gen/up4x9-wasmsimd.c",
+ "src/f32-dwconv/gen/up4x25-minmax-wasmsimd-arm-acc2.c",
+ "src/f32-dwconv/gen/up4x25-minmax-wasmsimd-arm.c",
+ "src/f32-dwconv/gen/up4x25-minmax-wasmsimd-x86-acc2.c",
+ "src/f32-dwconv/gen/up4x25-minmax-wasmsimd-x86.c",
+ "src/f32-dwconv/gen/up4x25-wasmsimd.c",
+ "src/f32-dwconv/gen/up8x3-minmax-wasmsimd-arm-acc2.c",
+ "src/f32-dwconv/gen/up8x3-minmax-wasmsimd-arm.c",
+ "src/f32-dwconv/gen/up8x3-minmax-wasmsimd-x86-acc2.c",
+ "src/f32-dwconv/gen/up8x3-minmax-wasmsimd-x86.c",
+ "src/f32-dwconv/gen/up8x3-wasmsimd.c",
+ "src/f32-dwconv/gen/up8x4-minmax-wasmsimd-arm-acc2.c",
+ "src/f32-dwconv/gen/up8x4-minmax-wasmsimd-arm.c",
+ "src/f32-dwconv/gen/up8x4-minmax-wasmsimd-x86-acc2.c",
+ "src/f32-dwconv/gen/up8x4-minmax-wasmsimd-x86.c",
+ "src/f32-dwconv/gen/up8x4-wasmsimd.c",
+ "src/f32-dwconv/gen/up8x9-minmax-wasmsimd-arm-acc2.c",
+ "src/f32-dwconv/gen/up8x9-minmax-wasmsimd-arm.c",
+ "src/f32-dwconv/gen/up8x9-minmax-wasmsimd-x86-acc2.c",
+ "src/f32-dwconv/gen/up8x9-minmax-wasmsimd-x86.c",
+ "src/f32-dwconv/gen/up8x9-wasmsimd.c",
+ "src/f32-dwconv/gen/up8x25-minmax-wasmsimd-arm-acc2.c",
+ "src/f32-dwconv/gen/up8x25-minmax-wasmsimd-arm.c",
+ "src/f32-dwconv/gen/up8x25-minmax-wasmsimd-x86-acc2.c",
+ "src/f32-dwconv/gen/up8x25-minmax-wasmsimd-x86.c",
+ "src/f32-dwconv/gen/up8x25-wasmsimd.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-loadsplat-1x4-acc2.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-loadsplat-1x4-acc3.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-loadsplat-1x4-acc4.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-loadsplat-1x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-loadsplat-2x4-acc2.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-loadsplat-2x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-loadsplat-3x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-loadsplat-4x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-loadsplat-5x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-loadsplat-6x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-splat-1x4-acc2.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-splat-1x4-acc3.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-splat-1x4-acc4.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-splat-1x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-splat-2x4-acc2.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-splat-2x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-splat-3x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-splat-4x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-splat-5x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-splat-6x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-loadsplat-1x4-acc2.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-loadsplat-1x4-acc3.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-loadsplat-1x4-acc4.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-loadsplat-1x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-loadsplat-2x4-acc2.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-loadsplat-2x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-loadsplat-3x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-loadsplat-4x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-loadsplat-5x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-loadsplat-6x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-splat-1x4-acc2.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-splat-1x4-acc3.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-splat-1x4-acc4.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-splat-1x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-splat-2x4-acc2.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-splat-2x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-splat-3x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-splat-4x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-splat-5x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-splat-6x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-loadsplat-1x4-acc2.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-loadsplat-1x4-acc3.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-loadsplat-1x4-acc4.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-loadsplat-1x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-loadsplat-2x4-acc2.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-loadsplat-2x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-loadsplat-3x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-loadsplat-4x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-splat-1x4-acc2.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-splat-1x4-acc3.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-splat-1x4-acc4.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-splat-1x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-splat-2x4-acc2.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-splat-2x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-splat-3x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-splat-4x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-loadsplat-1x4-acc2.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-loadsplat-1x4-acc3.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-loadsplat-1x4-acc4.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-loadsplat-1x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-loadsplat-2x4-acc2.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-loadsplat-2x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-loadsplat-3x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-loadsplat-4x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-splat-1x4-acc2.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-splat-1x4-acc3.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-splat-1x4-acc4.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-splat-1x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-splat-2x4-acc2.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-splat-2x4.c",
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+ "src/qs8-gemm/gen/2x4c8-xw-minmax-fp32-wasmsimd-dot16x2.c",
+ "src/qs8-gemm/gen/2x4c8-xw-minmax-fp32-wasmsimd-mul16.c",
+ "src/qs8-gemm/gen/3x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qs8-gemm/gen/3x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qs8-gemm/gen/3x4c2-xw-minmax-fp32-wasmsimd-dot16x2.c",
+ "src/qs8-gemm/gen/3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qs8-gemm/gen/3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qs8-gemm/gen/3x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qs8-gemm/gen/3x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qs8-gemm/gen/3x4c8-minmax-fp32-wasmsimd-mul16-ld64.c",
+ "src/qs8-gemm/gen/3x4c8-minmax-fp32-wasmsimd-mul16-ld128.c",
+ "src/qs8-gemm/gen/3x4c8-xw-minmax-fp32-wasmsimd-dot16x2.c",
+ "src/qs8-gemm/gen/3x4c8-xw-minmax-fp32-wasmsimd-mul16.c",
+ "src/qs8-gemm/gen/4x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qs8-gemm/gen/4x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qs8-gemm/gen/4x4c2-xw-minmax-fp32-wasmsimd-dot16x2.c",
+ "src/qs8-gemm/gen/4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qs8-gemm/gen/4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qs8-gemm/gen/4x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qs8-gemm/gen/4x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qs8-gemm/gen/4x4c8-xw-minmax-fp32-wasmsimd-dot16x2.c",
+ "src/qs8-igemm/gen/1x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qs8-igemm/gen/1x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qs8-igemm/gen/1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qs8-igemm/gen/1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qs8-igemm/gen/1x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qs8-igemm/gen/1x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qs8-igemm/gen/1x4c8-minmax-fp32-wasmsimd-mul16-ld64.c",
+ "src/qs8-igemm/gen/1x4c8-minmax-fp32-wasmsimd-mul16-ld128.c",
+ "src/qs8-igemm/gen/2x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qs8-igemm/gen/2x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qs8-igemm/gen/2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qs8-igemm/gen/2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qs8-igemm/gen/2x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qs8-igemm/gen/2x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qs8-igemm/gen/2x4c8-minmax-fp32-wasmsimd-mul16-ld64.c",
+ "src/qs8-igemm/gen/2x4c8-minmax-fp32-wasmsimd-mul16-ld128.c",
+ "src/qs8-igemm/gen/3x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qs8-igemm/gen/3x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qs8-igemm/gen/3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qs8-igemm/gen/3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qs8-igemm/gen/3x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qs8-igemm/gen/3x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qs8-igemm/gen/3x4c8-minmax-fp32-wasmsimd-mul16-ld64.c",
+ "src/qs8-igemm/gen/3x4c8-minmax-fp32-wasmsimd-mul16-ld128.c",
+ "src/qs8-igemm/gen/4x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qs8-igemm/gen/4x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qs8-igemm/gen/4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qs8-igemm/gen/4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qs8-igemm/gen/4x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qs8-igemm/gen/4x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qs8-requantization/fp32-wasmsimd.c",
+ "src/qs8-requantization/gemmlowp-wasmsimd.c",
+ "src/qs8-vadd/gen/minmax-wasmsimd-x8.c",
+ "src/qs8-vadd/gen/minmax-wasmsimd-x16.c",
+ "src/qs8-vadd/gen/minmax-wasmsimd-x24.c",
+ "src/qs8-vadd/gen/minmax-wasmsimd-x32.c",
+ "src/qs8-vaddc/gen/minmax-wasmsimd-x8.c",
+ "src/qs8-vaddc/gen/minmax-wasmsimd-x16.c",
+ "src/qs8-vaddc/gen/minmax-wasmsimd-x24.c",
+ "src/qs8-vaddc/gen/minmax-wasmsimd-x32.c",
+ "src/qs8-vmul/gen/minmax-fp32-wasmsimd-mul32-ld64-x8.c",
+ "src/qs8-vmul/gen/minmax-fp32-wasmsimd-mul32-ld64-x16.c",
+ "src/qs8-vmulc/gen/minmax-fp32-wasmsimd-mul32-ld64-x8.c",
+ "src/qs8-vmulc/gen/minmax-fp32-wasmsimd-mul32-ld64-x16.c",
+ "src/qu8-dwconv/gen/up8x9-minmax-fp32-wasmsimd-mul16.c",
+ "src/qu8-dwconv/gen/up8x25-minmax-fp32-wasmsimd-mul16.c",
+ "src/qu8-dwconv/gen/up16x9-minmax-fp32-wasmsimd-mul16.c",
+ "src/qu8-dwconv/gen/up16x25-minmax-fp32-wasmsimd-mul16.c",
+ "src/qu8-dwconv/gen/up24x9-minmax-fp32-wasmsimd-mul16.c",
+ "src/qu8-dwconv/gen/up24x25-minmax-fp32-wasmsimd-mul16.c",
+ "src/qu8-f32-vcvt/gen/vcvt-wasmsimd-x8.c",
+ "src/qu8-f32-vcvt/gen/vcvt-wasmsimd-x16.c",
+ "src/qu8-f32-vcvt/gen/vcvt-wasmsimd-x24.c",
+ "src/qu8-f32-vcvt/gen/vcvt-wasmsimd-x32.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-wasmsimd-c8.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-wasmsimd-c16.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-wasmsimd-c24.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-wasmsimd-c32.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-wasmsimd-c8.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-wasmsimd-c16.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-wasmsimd-c24.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-wasmsimd-c32.c",
+ "src/qu8-gemm/gen/1x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qu8-gemm/gen/1x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qu8-gemm/gen/1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qu8-gemm/gen/1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qu8-gemm/gen/1x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qu8-gemm/gen/1x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qu8-gemm/gen/1x4c8-minmax-fp32-wasmsimd-mul32-ld64.c",
+ "src/qu8-gemm/gen/1x4c8-minmax-fp32-wasmsimd-mul32-ld128.c",
+ "src/qu8-gemm/gen/2x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qu8-gemm/gen/2x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qu8-gemm/gen/2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qu8-gemm/gen/2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qu8-gemm/gen/2x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qu8-gemm/gen/2x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qu8-gemm/gen/2x4c8-minmax-fp32-wasmsimd-mul32-ld64.c",
+ "src/qu8-gemm/gen/2x4c8-minmax-fp32-wasmsimd-mul32-ld128.c",
+ "src/qu8-gemm/gen/3x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qu8-gemm/gen/3x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qu8-gemm/gen/3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qu8-gemm/gen/3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qu8-gemm/gen/3x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qu8-gemm/gen/3x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qu8-gemm/gen/3x4c8-minmax-fp32-wasmsimd-mul32-ld64.c",
+ "src/qu8-gemm/gen/3x4c8-minmax-fp32-wasmsimd-mul32-ld128.c",
+ "src/qu8-gemm/gen/4x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qu8-gemm/gen/4x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qu8-gemm/gen/4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qu8-gemm/gen/4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qu8-gemm/gen/4x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qu8-gemm/gen/4x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qu8-igemm/gen/1x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qu8-igemm/gen/1x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qu8-igemm/gen/1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qu8-igemm/gen/1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qu8-igemm/gen/1x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qu8-igemm/gen/1x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qu8-igemm/gen/1x4c8-minmax-fp32-wasmsimd-mul32-ld64.c",
+ "src/qu8-igemm/gen/1x4c8-minmax-fp32-wasmsimd-mul32-ld128.c",
+ "src/qu8-igemm/gen/2x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qu8-igemm/gen/2x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qu8-igemm/gen/2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qu8-igemm/gen/2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qu8-igemm/gen/2x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qu8-igemm/gen/2x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qu8-igemm/gen/2x4c8-minmax-fp32-wasmsimd-mul32-ld64.c",
+ "src/qu8-igemm/gen/2x4c8-minmax-fp32-wasmsimd-mul32-ld128.c",
+ "src/qu8-igemm/gen/3x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qu8-igemm/gen/3x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qu8-igemm/gen/3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qu8-igemm/gen/3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qu8-igemm/gen/3x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qu8-igemm/gen/3x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qu8-igemm/gen/3x4c8-minmax-fp32-wasmsimd-mul32-ld64.c",
+ "src/qu8-igemm/gen/3x4c8-minmax-fp32-wasmsimd-mul32-ld128.c",
+ "src/qu8-igemm/gen/4x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qu8-igemm/gen/4x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qu8-igemm/gen/4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qu8-igemm/gen/4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qu8-igemm/gen/4x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
+ "src/qu8-igemm/gen/4x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
+ "src/qu8-requantization/fp32-wasmsimd.c",
+ "src/qu8-requantization/gemmlowp-wasmsimd.c",
+ "src/qu8-vadd/gen/minmax-wasmsimd-x8.c",
+ "src/qu8-vadd/gen/minmax-wasmsimd-x16.c",
+ "src/qu8-vadd/gen/minmax-wasmsimd-x32.c",
+ "src/qu8-vaddc/gen/minmax-wasmsimd-x8.c",
+ "src/qu8-vaddc/gen/minmax-wasmsimd-x16.c",
+ "src/qu8-vaddc/gen/minmax-wasmsimd-x32.c",
+ "src/qu8-vmul/gen/minmax-fp32-wasmsimd-mul32-ld64-x8.c",
+ "src/qu8-vmul/gen/minmax-fp32-wasmsimd-mul32-ld64-x16.c",
+ "src/qu8-vmulc/gen/minmax-fp32-wasmsimd-mul32-ld64-x8.c",
+ "src/qu8-vmulc/gen/minmax-fp32-wasmsimd-mul32-ld64-x16.c",
+ "src/s8-ibilinear/gen/wasmsimd-dot16x2-c8.c",
+ "src/s8-ibilinear/gen/wasmsimd-dot16x2-c16.c",
+ "src/s8-ibilinear/gen/wasmsimd-mul32-c8.c",
+ "src/s8-ibilinear/gen/wasmsimd-mul32-c16.c",
+ "src/s8-maxpool/9p8x-minmax-wasmsimd-c16.c",
+ "src/s8-vclamp/wasmsimd-x64.c",
+ "src/u8-ibilinear/gen/wasmsimd-dot16x2-c8.c",
+ "src/u8-ibilinear/gen/wasmsimd-dot16x2-c16.c",
+ "src/u8-ibilinear/gen/wasmsimd-mul32-c8.c",
+ "src/u8-ibilinear/gen/wasmsimd-mul32-c16.c",
+ "src/u8-maxpool/9p8x-minmax-wasmsimd-c16.c",
+ "src/u8-vclamp/wasmsimd-x64.c",
+ "src/x8-lut/gen/lut-wasmsimd-x16.c",
+ "src/x8-lut/gen/lut-wasmsimd-x32.c",
+ "src/x8-lut/gen/lut-wasmsimd-x48.c",
+ "src/x8-lut/gen/lut-wasmsimd-x64.c",
+ "src/x32-packx/x4-wasmsimd.c",
+ "src/x32-transpose/4x4-wasmsimd.c",
+ "src/x32-unpool/wasmsimd.c",
+ "src/x32-zip/x2-wasmsimd.c",
+ "src/x32-zip/x3-wasmsimd.c",
+ "src/x32-zip/x4-wasmsimd.c",
+ "src/x32-zip/xm-wasmsimd.c",
+ "src/xx-fill/wasmsimd-x64.c",
+ "src/xx-pad/wasmsimd.c",
]
// ISA-specific micro-kernels
-NEON_UKERNELS = [
+PROD_NEON_MICROKERNEL_SRCS = [
+ "src/f16-f32-vcvt/gen/vcvt-neon-int16-x16.c",
"src/f32-argmaxpool/4x-neon-c4.c",
"src/f32-argmaxpool/9p8x-neon-c4.c",
"src/f32-argmaxpool/9x-neon-c4.c",
"src/f32-avgpool/9p8x-minmax-neon-c4.c",
"src/f32-avgpool/9x-minmax-neon-c4.c",
- "src/f32-clamp/gen/neon-x4.c",
- "src/f32-clamp/gen/neon-x8.c",
+ "src/f32-conv-hwc2chw/3x3s2p1c3x4-neon-2x2.c",
+ "src/f32-dwconv/gen/up8x3-minmax-neon.c",
+ "src/f32-dwconv/gen/up8x4-minmax-neon.c",
+ "src/f32-dwconv/gen/up8x9-minmax-neon.c",
+ "src/f32-dwconv/gen/up8x25-minmax-neon-acc2.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-2x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neon-1x4.c",
+ "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-1x4.c",
+ "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neon-1x4.c",
+ "src/f32-f16-vcvt/gen/vcvt-neon-x8.c",
+ "src/f32-gavgpool-cw/neon-x4.c",
+ "src/f32-gavgpool/7p7x-minmax-neon-c4.c",
+ "src/f32-gavgpool/7x-minmax-neon-c4.c",
+ "src/f32-gemm/gen/1x8-minmax-neon-lane-ld64.c",
+ "src/f32-gemm/gen/4x2-minmax-neon-lane-ld64.c",
+ "src/f32-gemm/gen/4x8-minmax-neon-lane-ld64.c",
+ "src/f32-ibilinear-chw/gen/neon-p8.c",
+ "src/f32-ibilinear/gen/neon-c8.c",
+ "src/f32-igemm/gen/1x8-minmax-neon-lane-ld64.c",
+ "src/f32-igemm/gen/4x2-minmax-neon-lane-ld64.c",
+ "src/f32-igemm/gen/4x8-minmax-neon-lane-ld64.c",
+ "src/f32-maxpool/9p8x-minmax-neon-c4.c",
+ "src/f32-pavgpool/9p8x-minmax-neon-c4.c",
+ "src/f32-pavgpool/9x-minmax-neon-c4.c",
+ "src/f32-prelu/gen/neon-2x8.c",
+ "src/f32-qs8-vcvt/gen/vcvt-neon-x32.c",
+ "src/f32-qu8-vcvt/gen/vcvt-neon-x32.c",
+ "src/f32-raddstoreexpminusmax/gen/neon-rr2-lut64-p2-x8.c",
+ "src/f32-rmax/neon.c",
+ "src/f32-spmm/gen/32x1-minmax-neon.c",
+ "src/f32-vbinary/gen/vadd-minmax-neon-x8.c",
+ "src/f32-vbinary/gen/vaddc-minmax-neon-x8.c",
+ "src/f32-vbinary/gen/vmax-neon-x8.c",
+ "src/f32-vbinary/gen/vmaxc-neon-x8.c",
+ "src/f32-vbinary/gen/vmin-neon-x8.c",
+ "src/f32-vbinary/gen/vminc-neon-x8.c",
+ "src/f32-vbinary/gen/vmul-minmax-neon-x8.c",
+ "src/f32-vbinary/gen/vmulc-minmax-neon-x8.c",
+ "src/f32-vbinary/gen/vrsubc-minmax-neon-x8.c",
+ "src/f32-vbinary/gen/vsqrdiff-neon-x8.c",
+ "src/f32-vbinary/gen/vsqrdiffc-neon-x8.c",
+ "src/f32-vbinary/gen/vsub-minmax-neon-x8.c",
+ "src/f32-vbinary/gen/vsubc-minmax-neon-x8.c",
+ "src/f32-vclamp/gen/vclamp-neon-x8.c",
+ "src/f32-velu/gen/velu-neon-rr2-lut16-p3-x8.c",
+ "src/f32-vhswish/gen/vhswish-neon-x16.c",
+ "src/f32-vlrelu/gen/vlrelu-neon-x8.c",
+ "src/f32-vmulcaddc/gen/c4-minmax-neon-2x.c",
+ "src/f32-vrnd/gen/vrndd-neon-x8.c",
+ "src/f32-vrnd/gen/vrndne-neon-x8.c",
+ "src/f32-vrnd/gen/vrndu-neon-x8.c",
+ "src/f32-vrnd/gen/vrndz-neon-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut64-p2-nr2recps-x8.c",
+ "src/f32-vunary/gen/vabs-neon-x8.c",
+ "src/f32-vunary/gen/vneg-neon-x8.c",
+ "src/f32-vunary/gen/vsqr-neon-x8.c",
+ "src/qc8-dwconv/gen/up8x25-minmax-fp32-neon-mla8-ld64.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-neon-mla8-ld64.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-neon-mla8-ld64.c",
+ "src/qc8-gemm/gen/1x8-minmax-fp32-neon-mlal-lane.c",
+ "src/qc8-gemm/gen/1x8c2s4-minmax-fp32-neon-mlal.c",
+ "src/qc8-gemm/gen/2x8c2s4-minmax-fp32-neon-mlal.c",
+ "src/qc8-igemm/gen/1x8-minmax-fp32-neon-mlal-lane.c",
+ "src/qc8-igemm/gen/1x8c2s4-minmax-fp32-neon-mlal.c",
+ "src/qc8-igemm/gen/2x8c2s4-minmax-fp32-neon-mlal.c",
+ "src/qs8-dwconv/gen/up8x25-minmax-rndnu-neon-mla8-ld64.c",
+ "src/qs8-dwconv/gen/up16x9-minmax-rndnu-neon-mla8-ld64.c",
+ "src/qs8-dwconv/gen/up16x25-minmax-rndnu-neon-mla8-ld64.c",
+ "src/qs8-f32-vcvt/gen/vcvt-neon-x32.c",
+ "src/qs8-gavgpool/gen/7p7x-minmax-rndnu-neon-c8.c",
+ "src/qs8-gavgpool/gen/7x-minmax-rndnu-neon-c8.c",
+ "src/qs8-gemm/gen/1x8-minmax-rndnu-neon-mlal-lane.c",
+ "src/qs8-gemm/gen/1x8c2s4-minmax-rndnu-neon-mlal.c",
+ "src/qs8-gemm/gen/1x16-minmax-rndnu-neon-mlal-lane.c",
+ "src/qs8-gemm/gen/2x8c2s4-minmax-rndnu-neon-mlal.c",
+ "src/qs8-igemm/gen/1x8-minmax-rndnu-neon-mlal-lane.c",
+ "src/qs8-igemm/gen/1x8c2s4-minmax-rndnu-neon-mlal.c",
+ "src/qs8-igemm/gen/1x16-minmax-rndnu-neon-mlal-lane.c",
+ "src/qs8-igemm/gen/2x8c2s4-minmax-rndnu-neon-mlal.c",
+ "src/qs8-vadd/gen/minmax-neon-ld64-x16.c",
+ "src/qs8-vadd/gen/minmax-neon-ld64-x32.c",
+ "src/qs8-vaddc/gen/minmax-neon-ld64-x16.c",
+ "src/qs8-vaddc/gen/minmax-neon-ld64-x32.c",
+ "src/qs8-vmul/gen/minmax-rndnu-neon-ld64-x16.c",
+ "src/qs8-vmulc/gen/minmax-rndnu-neon-ld64-x16.c",
+ "src/qu8-avgpool/9p8x-minmax-neon-c8.c",
+ "src/qu8-avgpool/9x-minmax-neon-c8.c",
+ "src/qu8-dwconv/gen/up8x25-minmax-rndnu-neon-mul8.c",
+ "src/qu8-dwconv/gen/up16x9-minmax-rndnu-neon-mul8.c",
+ "src/qu8-f32-vcvt/gen/vcvt-neon-x32.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-rndnu-neon-c8.c",
+ "src/qu8-gavgpool/gen/7x-minmax-rndnu-neon-c8.c",
+ "src/qu8-gemm/gen/1x8-minmax-rndnu-neon-mlal-lane.c",
+ "src/qu8-gemm/gen/1x16-minmax-rndnu-neon-mlal-lane.c",
+ "src/qu8-gemm/gen/3x8-minmax-rndnu-neon-mlal-lane.c",
+ "src/qu8-gemm/gen/4x16-minmax-rndnu-neon-mlal-lane.c",
+ "src/qu8-igemm/gen/1x8-minmax-rndnu-neon-mlal-lane.c",
+ "src/qu8-igemm/gen/1x16-minmax-rndnu-neon-mlal-lane.c",
+ "src/qu8-igemm/gen/3x8-minmax-rndnu-neon-mlal-lane.c",
+ "src/qu8-igemm/gen/4x16-minmax-rndnu-neon-mlal-lane.c",
+ "src/qu8-vadd/gen/minmax-neon-ld64-x16.c",
+ "src/qu8-vadd/gen/minmax-neon-ld64-x32.c",
+ "src/qu8-vaddc/gen/minmax-neon-ld64-x16.c",
+ "src/qu8-vaddc/gen/minmax-neon-ld64-x32.c",
+ "src/qu8-vmul/gen/minmax-rndnu-neon-ld64-x16.c",
+ "src/qu8-vmulc/gen/minmax-rndnu-neon-ld64-x16.c",
+ "src/s8-ibilinear/gen/neon-c8.c",
+ "src/s8-ibilinear/gen/neon-c16.c",
+ "src/s8-maxpool/9p8x-minmax-neon-c16.c",
+ "src/s8-vclamp/neon-x64.c",
+ "src/u8-ibilinear/gen/neon-c8.c",
+ "src/u8-ibilinear/gen/neon-c16.c",
+ "src/u8-maxpool/9p8x-minmax-neon-c16.c",
+ "src/u8-rmax/neon.c",
+ "src/u8-vclamp/neon-x64.c",
+ "src/x8-zip/x2-neon.c",
+ "src/x8-zip/x3-neon.c",
+ "src/x8-zip/x4-neon.c",
+ "src/x8-zip/xm-neon.c",
+ "src/x32-packx/x4-neon-st4.c",
+ "src/x32-unpool/neon.c",
+ "src/x32-zip/x2-neon.c",
+ "src/x32-zip/x3-neon.c",
+ "src/x32-zip/x4-neon.c",
+ "src/x32-zip/xm-neon.c",
+ "src/xx-fill/neon-x64.c",
+ "src/xx-pad/neon.c",
+]
+
+ALL_NEON_MICROKERNEL_SRCS = [
+ "src/f16-f32-vcvt/gen/vcvt-neon-int16-x8.c",
+ "src/f16-f32-vcvt/gen/vcvt-neon-int16-x16.c",
+ "src/f16-f32-vcvt/gen/vcvt-neon-int16-x24.c",
+ "src/f16-f32-vcvt/gen/vcvt-neon-int16-x32.c",
+ "src/f16-f32-vcvt/gen/vcvt-neon-int32-x8.c",
+ "src/f16-f32-vcvt/gen/vcvt-neon-int32-x16.c",
+ "src/f16-f32-vcvt/gen/vcvt-neon-int32-x24.c",
+ "src/f16-f32-vcvt/gen/vcvt-neon-int32-x32.c",
+ "src/f32-argmaxpool/4x-neon-c4.c",
+ "src/f32-argmaxpool/9p8x-neon-c4.c",
+ "src/f32-argmaxpool/9x-neon-c4.c",
+ "src/f32-avgpool/9p8x-minmax-neon-c4.c",
+ "src/f32-avgpool/9x-minmax-neon-c4.c",
"src/f32-conv-hwc/gen/3x3s2p0p1c3x4-neon-2x1.c",
"src/f32-conv-hwc/gen/3x3s2p0p1c3x4-neon-2x2.c",
"src/f32-conv-hwc/gen/3x3s2p0p1c3x8-neon-2x1.c",
@@ -538,12 +2730,16 @@
"src/f32-conv-hwc/gen/3x3s2p1c3x8-neon-2x1.c",
"src/f32-conv-hwc/gen/3x3s2p1c3x8-neon-2x2.c",
"src/f32-conv-hwc2chw/3x3s2p1c3x4-neon-2x2.c",
+ "src/f32-dwconv/gen/up4x3-minmax-neon-acc2.c",
+ "src/f32-dwconv/gen/up4x3-minmax-neon.c",
"src/f32-dwconv/gen/up4x4-minmax-neon-acc2.c",
"src/f32-dwconv/gen/up4x4-minmax-neon.c",
"src/f32-dwconv/gen/up4x9-minmax-neon-acc2.c",
"src/f32-dwconv/gen/up4x9-minmax-neon.c",
"src/f32-dwconv/gen/up4x25-minmax-neon-acc2.c",
"src/f32-dwconv/gen/up4x25-minmax-neon.c",
+ "src/f32-dwconv/gen/up8x3-minmax-neon-acc2.c",
+ "src/f32-dwconv/gen/up8x3-minmax-neon.c",
"src/f32-dwconv/gen/up8x4-minmax-neon-acc2.c",
"src/f32-dwconv/gen/up8x4-minmax-neon.c",
"src/f32-dwconv/gen/up8x9-minmax-neon-acc2.c",
@@ -591,6 +2787,10 @@
"src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neon-2x4.c",
"src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neon-3x4-acc2.c",
"src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neon-3x4.c",
+ "src/f32-f16-vcvt/gen/vcvt-neon-x8.c",
+ "src/f32-f16-vcvt/gen/vcvt-neon-x16.c",
+ "src/f32-f16-vcvt/gen/vcvt-neon-x24.c",
+ "src/f32-f16-vcvt/gen/vcvt-neon-x32.c",
"src/f32-gavgpool-cw/neon-x4.c",
"src/f32-gavgpool/7p7x-minmax-neon-c4.c",
"src/f32-gavgpool/7x-minmax-neon-c4.c",
@@ -625,9 +2825,6 @@
"src/f32-gemm/gen/6x8-minmax-neon-lane-ld128.c",
"src/f32-gemm/gen/6x8s4-minmax-neon.c",
"src/f32-gemm/gen/8x8s4-minmax-neon.c",
- "src/f32-hswish/gen/hswish-neon-x4.c",
- "src/f32-hswish/gen/hswish-neon-x8.c",
- "src/f32-hswish/gen/hswish-neon-x16.c",
"src/f32-ibilinear-chw/gen/neon-p4.c",
"src/f32-ibilinear-chw/gen/neon-p8.c",
"src/f32-ibilinear/gen/neon-c4.c",
@@ -662,51 +2859,39 @@
"src/f32-prelu/gen/neon-4x4.c",
"src/f32-prelu/gen/neon-4x8.c",
"src/f32-prelu/gen/neon-4x16.c",
- "src/f32-raddstoreexpminusmax/gen/neon-lut64-p2-x4.c",
- "src/f32-raddstoreexpminusmax/gen/neon-lut64-p2-x8-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/neon-lut64-p2-x8.c",
- "src/f32-raddstoreexpminusmax/gen/neon-lut64-p2-x12-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/neon-lut64-p2-x12-acc3.c",
- "src/f32-raddstoreexpminusmax/gen/neon-lut64-p2-x12.c",
- "src/f32-raddstoreexpminusmax/gen/neon-lut64-p2-x16-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/neon-lut64-p2-x16-acc4.c",
- "src/f32-raddstoreexpminusmax/gen/neon-lut64-p2-x16.c",
- "src/f32-raddstoreexpminusmax/gen/neon-lut64-p2-x20-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/neon-lut64-p2-x20-acc5.c",
- "src/f32-raddstoreexpminusmax/gen/neon-lut64-p2-x20.c",
- "src/f32-raddstoreexpminusmax/gen/neon-p5-x4.c",
- "src/f32-raddstoreexpminusmax/gen/neon-p5-x8-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/neon-p5-x8.c",
- "src/f32-raddstoreexpminusmax/gen/neon-p5-x12-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/neon-p5-x12-acc3.c",
- "src/f32-raddstoreexpminusmax/gen/neon-p5-x12.c",
- "src/f32-raddstoreexpminusmax/gen/neon-p5-x16-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/neon-p5-x16-acc4.c",
- "src/f32-raddstoreexpminusmax/gen/neon-p5-x16.c",
- "src/f32-raddstoreexpminusmax/gen/neon-p5-x20-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/neon-p5-x20-acc5.c",
- "src/f32-raddstoreexpminusmax/gen/neon-p5-x20.c",
- "src/f32-relu/gen/neon-x4.c",
- "src/f32-relu/gen/neon-x8.c",
+ "src/f32-qs8-vcvt/gen/vcvt-neon-x8.c",
+ "src/f32-qs8-vcvt/gen/vcvt-neon-x16.c",
+ "src/f32-qs8-vcvt/gen/vcvt-neon-x24.c",
+ "src/f32-qs8-vcvt/gen/vcvt-neon-x32.c",
+ "src/f32-qu8-vcvt/gen/vcvt-neon-x8.c",
+ "src/f32-qu8-vcvt/gen/vcvt-neon-x16.c",
+ "src/f32-qu8-vcvt/gen/vcvt-neon-x24.c",
+ "src/f32-qu8-vcvt/gen/vcvt-neon-x32.c",
+ "src/f32-raddstoreexpminusmax/gen/neon-rr2-lut64-p2-x4.c",
+ "src/f32-raddstoreexpminusmax/gen/neon-rr2-lut64-p2-x8-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/neon-rr2-lut64-p2-x8.c",
+ "src/f32-raddstoreexpminusmax/gen/neon-rr2-lut64-p2-x12-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/neon-rr2-lut64-p2-x12-acc3.c",
+ "src/f32-raddstoreexpminusmax/gen/neon-rr2-lut64-p2-x12.c",
+ "src/f32-raddstoreexpminusmax/gen/neon-rr2-lut64-p2-x16-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/neon-rr2-lut64-p2-x16-acc4.c",
+ "src/f32-raddstoreexpminusmax/gen/neon-rr2-lut64-p2-x16.c",
+ "src/f32-raddstoreexpminusmax/gen/neon-rr2-lut64-p2-x20-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/neon-rr2-lut64-p2-x20-acc5.c",
+ "src/f32-raddstoreexpminusmax/gen/neon-rr2-lut64-p2-x20.c",
+ "src/f32-raddstoreexpminusmax/gen/neon-rr2-p5-x4.c",
+ "src/f32-raddstoreexpminusmax/gen/neon-rr2-p5-x8-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/neon-rr2-p5-x8.c",
+ "src/f32-raddstoreexpminusmax/gen/neon-rr2-p5-x12-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/neon-rr2-p5-x12-acc3.c",
+ "src/f32-raddstoreexpminusmax/gen/neon-rr2-p5-x12.c",
+ "src/f32-raddstoreexpminusmax/gen/neon-rr2-p5-x16-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/neon-rr2-p5-x16-acc4.c",
+ "src/f32-raddstoreexpminusmax/gen/neon-rr2-p5-x16.c",
+ "src/f32-raddstoreexpminusmax/gen/neon-rr2-p5-x20-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/neon-rr2-p5-x20-acc5.c",
+ "src/f32-raddstoreexpminusmax/gen/neon-rr2-p5-x20.c",
"src/f32-rmax/neon.c",
- "src/f32-sigmoid/gen/neon-rr2-lut64-p2-nr2recps-x4.c",
- "src/f32-sigmoid/gen/neon-rr2-lut64-p2-nr2recps-x8.c",
- "src/f32-sigmoid/gen/neon-rr2-lut64-p2-nr2recps-x12.c",
- "src/f32-sigmoid/gen/neon-rr2-lut64-p2-nr2recps-x16.c",
- "src/f32-sigmoid/gen/neon-rr2-lut64-p2-nr2recps-x20.c",
- "src/f32-sigmoid/gen/neon-rr2-lut64-p2-nr2recps-x24.c",
- "src/f32-sigmoid/gen/neon-rr2-lut2048-p1-nr2recps-x4.c",
- "src/f32-sigmoid/gen/neon-rr2-lut2048-p1-nr2recps-x8.c",
- "src/f32-sigmoid/gen/neon-rr2-lut2048-p1-nr2recps-x12.c",
- "src/f32-sigmoid/gen/neon-rr2-lut2048-p1-nr2recps-x16.c",
- "src/f32-sigmoid/gen/neon-rr2-lut2048-p1-nr2recps-x20.c",
- "src/f32-sigmoid/gen/neon-rr2-lut2048-p1-nr2recps-x24.c",
- "src/f32-sigmoid/gen/neon-rr2-p5-nr2recps-x4.c",
- "src/f32-sigmoid/gen/neon-rr2-p5-nr2recps-x8.c",
- "src/f32-sigmoid/gen/neon-rr2-p5-nr2recps-x12.c",
- "src/f32-sigmoid/gen/neon-rr2-p5-nr2recps-x16.c",
- "src/f32-sigmoid/gen/neon-rr2-p5-nr2recps-x20.c",
- "src/f32-sigmoid/gen/neon-rr2-p5-nr2recps-x24.c",
"src/f32-spmm/gen/4x1-minmax-neon-pipelined.c",
"src/f32-spmm/gen/4x1-minmax-neon-x2.c",
"src/f32-spmm/gen/4x1-minmax-neon.c",
@@ -746,6 +2931,8 @@
"src/f32-vbinary/gen/vsub-minmax-neon-x8.c",
"src/f32-vbinary/gen/vsubc-minmax-neon-x4.c",
"src/f32-vbinary/gen/vsubc-minmax-neon-x8.c",
+ "src/f32-vclamp/gen/vclamp-neon-x4.c",
+ "src/f32-vclamp/gen/vclamp-neon-x8.c",
"src/f32-velu/gen/velu-neon-rr2-lut16-p3-x4.c",
"src/f32-velu/gen/velu-neon-rr2-lut16-p3-x8.c",
"src/f32-velu/gen/velu-neon-rr2-lut16-p3-x12.c",
@@ -758,10 +2945,15 @@
"src/f32-velu/gen/velu-neon-rr2-p6-x16.c",
"src/f32-velu/gen/velu-neon-rr2-p6-x20.c",
"src/f32-velu/gen/velu-neon-rr2-p6-x24.c",
+ "src/f32-vhswish/gen/vhswish-neon-x4.c",
+ "src/f32-vhswish/gen/vhswish-neon-x8.c",
+ "src/f32-vhswish/gen/vhswish-neon-x16.c",
"src/f32-vlrelu/gen/vlrelu-neon-x4.c",
"src/f32-vlrelu/gen/vlrelu-neon-x8.c",
"src/f32-vmulcaddc/gen/c4-minmax-neon-2x.c",
"src/f32-vmulcaddc/gen/c8-minmax-neon-2x.c",
+ "src/f32-vrelu/gen/vrelu-neon-x4.c",
+ "src/f32-vrelu/gen/vrelu-neon-x8.c",
"src/f32-vrnd/gen/vrndd-neon-x4.c",
"src/f32-vrnd/gen/vrndd-neon-x8.c",
"src/f32-vrnd/gen/vrndne-neon-x4.c",
@@ -770,12 +2962,35 @@
"src/f32-vrnd/gen/vrndu-neon-x8.c",
"src/f32-vrnd/gen/vrndz-neon-x4.c",
"src/f32-vrnd/gen/vrndz-neon-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut64-p2-nr2recps-x4.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut64-p2-nr2recps-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut64-p2-nr2recps-x12.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut64-p2-nr2recps-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut64-p2-nr2recps-x20.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut64-p2-nr2recps-x24.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut2048-p1-nr2recps-x4.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut2048-p1-nr2recps-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut2048-p1-nr2recps-x12.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut2048-p1-nr2recps-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut2048-p1-nr2recps-x20.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut2048-p1-nr2recps-x24.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-p5-nr2recps-x4.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-p5-nr2recps-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-p5-nr2recps-x12.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-p5-nr2recps-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-p5-nr2recps-x20.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-p5-nr2recps-x24.c",
"src/f32-vunary/gen/vabs-neon-x4.c",
"src/f32-vunary/gen/vabs-neon-x8.c",
"src/f32-vunary/gen/vneg-neon-x4.c",
"src/f32-vunary/gen/vneg-neon-x8.c",
"src/f32-vunary/gen/vsqr-neon-x4.c",
"src/f32-vunary/gen/vsqr-neon-x8.c",
+ "src/math/cvt-f16-f32-neon-int16.c",
+ "src/math/cvt-f16-f32-neon-int32.c",
+ "src/math/cvt-f32-f16-neon.c",
+ "src/math/cvt-f32-qs8-neon.c",
+ "src/math/cvt-f32-qu8-neon.c",
"src/math/expm1minus-neon-rr2-lut16-p3.c",
"src/math/expm1minus-neon-rr2-p6.c",
"src/math/roundd-neon-addsub.c",
@@ -791,184 +3006,823 @@
"src/math/sqrt-neon-nr1rsqrts.c",
"src/math/sqrt-neon-nr2rsqrts.c",
"src/math/sqrt-neon-nr3rsqrts.c",
- "src/qs8-dwconv/gen/up8x9-minmax-neon-mul16.c",
- "src/qs8-dwconv/gen/up16x9-minmax-neon-mul16.c",
- "src/qs8-dwconv/gen/up24x9-minmax-neon-mul16.c",
- "src/qs8-dwconv/gen/up32x9-minmax-neon-mul16.c",
- "src/qs8-gavgpool/gen/7p7x-minmax-neon-c8-acc2.c",
- "src/qs8-gavgpool/gen/7p7x-minmax-neon-c16-acc2.c",
- "src/qs8-gavgpool/gen/7p7x-minmax-neon-c24-acc2.c",
- "src/qs8-gavgpool/gen/7p7x-minmax-neon-c32-acc2.c",
- "src/qs8-gavgpool/gen/7x-minmax-neon-c8-acc2.c",
- "src/qs8-gavgpool/gen/7x-minmax-neon-c16-acc2.c",
- "src/qs8-gavgpool/gen/7x-minmax-neon-c24-acc2.c",
- "src/qs8-gavgpool/gen/7x-minmax-neon-c32-acc2.c",
- "src/qs8-gemm/gen/1x8-minmax-neon-mlal-lane.c",
- "src/qs8-gemm/gen/1x8-minmax-neon-mull-addw-dup.c",
- "src/qs8-gemm/gen/1x8c2-minmax-neon-mlal-padal-dup.c",
- "src/qs8-gemm/gen/1x8c2-minmax-neon-mull-padal-dup.c",
- "src/qs8-gemm/gen/1x8c8-minmax-neon-mlal-padal.c",
- "src/qs8-gemm/gen/1x8c8-minmax-neon-mull-padal.c",
- "src/qs8-gemm/gen/1x8c16-minmax-neon-mlal-padal.c",
- "src/qs8-gemm/gen/1x16-minmax-neon-mlal-lane.c",
- "src/qs8-gemm/gen/1x16-minmax-neon-mull-addw-dup.c",
- "src/qs8-gemm/gen/1x16c2-minmax-neon-mlal-padal-dup.c",
- "src/qs8-gemm/gen/1x16c2-minmax-neon-mull-padal-dup.c",
- "src/qs8-gemm/gen/1x16c8-minmax-neon-mlal-padal.c",
- "src/qs8-gemm/gen/1x16c8-minmax-neon-mull-padal.c",
- "src/qs8-gemm/gen/1x16c16-minmax-neon-mlal-padal.c",
- "src/qs8-gemm/gen/2x8-minmax-neon-mlal-lane.c",
- "src/qs8-gemm/gen/2x8-minmax-neon-mull-addw-dup.c",
- "src/qs8-gemm/gen/2x8c2-minmax-neon-mlal-padal-dup.c",
- "src/qs8-gemm/gen/2x8c2-minmax-neon-mull-padal-dup.c",
- "src/qs8-gemm/gen/2x8c8-minmax-neon-mlal-padal.c",
- "src/qs8-gemm/gen/2x8c8-minmax-neon-mull-padal.c",
- "src/qs8-gemm/gen/2x8c16-minmax-neon-mlal-padal.c",
- "src/qs8-gemm/gen/2x16-minmax-neon-mlal-lane.c",
- "src/qs8-gemm/gen/2x16-minmax-neon-mull-addw-dup.c",
- "src/qs8-gemm/gen/2x16c2-minmax-neon-mlal-padal-dup.c",
- "src/qs8-gemm/gen/2x16c2-minmax-neon-mull-padal-dup.c",
- "src/qs8-gemm/gen/2x16c8-minmax-neon-mlal-padal.c",
- "src/qs8-gemm/gen/2x16c8-minmax-neon-mull-padal.c",
- "src/qs8-gemm/gen/2x16c16-minmax-neon-mlal-padal.c",
- "src/qs8-gemm/gen/3x8-minmax-neon-mlal-lane.c",
- "src/qs8-gemm/gen/3x8-minmax-neon-mull-addw-dup.c",
- "src/qs8-gemm/gen/3x8c2-minmax-neon-mlal-padal-dup.c",
- "src/qs8-gemm/gen/3x8c2-minmax-neon-mull-padal-dup.c",
- "src/qs8-gemm/gen/3x8c8-minmax-neon-mlal-padal.c",
- "src/qs8-gemm/gen/3x8c8-minmax-neon-mull-padal.c",
- "src/qs8-gemm/gen/3x8c16-minmax-neon-mlal-padal.c",
- "src/qs8-gemm/gen/3x16-minmax-neon-mlal-lane.c",
- "src/qs8-gemm/gen/3x16-minmax-neon-mull-addw-dup.c",
- "src/qs8-gemm/gen/3x16c2-minmax-neon-mlal-padal-dup.c",
- "src/qs8-gemm/gen/3x16c2-minmax-neon-mull-padal-dup.c",
- "src/qs8-gemm/gen/3x16c8-minmax-neon-mlal-padal.c",
- "src/qs8-gemm/gen/3x16c8-minmax-neon-mull-padal.c",
- "src/qs8-gemm/gen/3x16c16-minmax-neon-mlal-padal.c",
- "src/qs8-gemm/gen/4x8-minmax-neon-mlal-lane.c",
- "src/qs8-gemm/gen/4x8-minmax-neon-mull-addw-dup.c",
- "src/qs8-gemm/gen/4x8c2-minmax-neon-mlal-padal-dup.c",
- "src/qs8-gemm/gen/4x8c2-minmax-neon-mull-padal-dup.c",
- "src/qs8-gemm/gen/4x8c8-minmax-neon-mlal-padal.c",
- "src/qs8-gemm/gen/4x8c8-minmax-neon-mull-padal.c",
- "src/qs8-gemm/gen/4x8c16-minmax-neon-mlal-padal.c",
- "src/qs8-gemm/gen/4x16-minmax-neon-mlal-lane.c",
- "src/qs8-gemm/gen/4x16-minmax-neon-mull-addw-dup.c",
- "src/qs8-gemm/gen/4x16c2-minmax-neon-mlal-padal-dup.c",
- "src/qs8-gemm/gen/4x16c2-minmax-neon-mull-padal-dup.c",
- "src/qs8-gemm/gen/4x16c8-minmax-neon-mlal-padal.c",
- "src/qs8-gemm/gen/4x16c8-minmax-neon-mull-padal.c",
- "src/qs8-gemm/gen/4x16c16-minmax-neon-mlal-padal.c",
- "src/qs8-igemm/gen/1x8-minmax-neon-mlal-lane.c",
- "src/qs8-igemm/gen/1x8-minmax-neon-mull-addw-dup.c",
- "src/qs8-igemm/gen/1x8c2-minmax-neon-mlal-padal-dup.c",
- "src/qs8-igemm/gen/1x8c2-minmax-neon-mull-padal-dup.c",
- "src/qs8-igemm/gen/1x8c8-minmax-neon-mlal-padal.c",
- "src/qs8-igemm/gen/1x8c8-minmax-neon-mull-padal.c",
- "src/qs8-igemm/gen/1x8c16-minmax-neon-mlal-padal.c",
- "src/qs8-igemm/gen/1x16-minmax-neon-mlal-lane.c",
- "src/qs8-igemm/gen/1x16-minmax-neon-mull-addw-dup.c",
- "src/qs8-igemm/gen/1x16c2-minmax-neon-mlal-padal-dup.c",
- "src/qs8-igemm/gen/1x16c2-minmax-neon-mull-padal-dup.c",
- "src/qs8-igemm/gen/1x16c8-minmax-neon-mlal-padal.c",
- "src/qs8-igemm/gen/1x16c8-minmax-neon-mull-padal.c",
- "src/qs8-igemm/gen/1x16c16-minmax-neon-mlal-padal.c",
- "src/qs8-igemm/gen/2x8-minmax-neon-mlal-lane.c",
- "src/qs8-igemm/gen/2x8-minmax-neon-mull-addw-dup.c",
- "src/qs8-igemm/gen/2x8c2-minmax-neon-mlal-padal-dup.c",
- "src/qs8-igemm/gen/2x8c2-minmax-neon-mull-padal-dup.c",
- "src/qs8-igemm/gen/2x8c8-minmax-neon-mlal-padal.c",
- "src/qs8-igemm/gen/2x8c8-minmax-neon-mull-padal.c",
- "src/qs8-igemm/gen/2x8c16-minmax-neon-mlal-padal.c",
- "src/qs8-igemm/gen/2x16-minmax-neon-mlal-lane.c",
- "src/qs8-igemm/gen/2x16-minmax-neon-mull-addw-dup.c",
- "src/qs8-igemm/gen/2x16c2-minmax-neon-mlal-padal-dup.c",
- "src/qs8-igemm/gen/2x16c2-minmax-neon-mull-padal-dup.c",
- "src/qs8-igemm/gen/2x16c8-minmax-neon-mlal-padal.c",
- "src/qs8-igemm/gen/2x16c8-minmax-neon-mull-padal.c",
- "src/qs8-igemm/gen/2x16c16-minmax-neon-mlal-padal.c",
- "src/qs8-igemm/gen/3x8-minmax-neon-mlal-lane.c",
- "src/qs8-igemm/gen/3x8-minmax-neon-mull-addw-dup.c",
- "src/qs8-igemm/gen/3x8c2-minmax-neon-mlal-padal-dup.c",
- "src/qs8-igemm/gen/3x8c2-minmax-neon-mull-padal-dup.c",
- "src/qs8-igemm/gen/3x8c8-minmax-neon-mlal-padal.c",
- "src/qs8-igemm/gen/3x8c8-minmax-neon-mull-padal.c",
- "src/qs8-igemm/gen/3x8c16-minmax-neon-mlal-padal.c",
- "src/qs8-igemm/gen/3x16-minmax-neon-mlal-lane.c",
- "src/qs8-igemm/gen/3x16-minmax-neon-mull-addw-dup.c",
- "src/qs8-igemm/gen/3x16c2-minmax-neon-mlal-padal-dup.c",
- "src/qs8-igemm/gen/3x16c2-minmax-neon-mull-padal-dup.c",
- "src/qs8-igemm/gen/3x16c8-minmax-neon-mlal-padal.c",
- "src/qs8-igemm/gen/3x16c8-minmax-neon-mull-padal.c",
- "src/qs8-igemm/gen/3x16c16-minmax-neon-mlal-padal.c",
- "src/qs8-igemm/gen/4x8-minmax-neon-mlal-lane.c",
- "src/qs8-igemm/gen/4x8-minmax-neon-mull-addw-dup.c",
- "src/qs8-igemm/gen/4x8c2-minmax-neon-mlal-padal-dup.c",
- "src/qs8-igemm/gen/4x8c2-minmax-neon-mull-padal-dup.c",
- "src/qs8-igemm/gen/4x8c8-minmax-neon-mlal-padal.c",
- "src/qs8-igemm/gen/4x8c8-minmax-neon-mull-padal.c",
- "src/qs8-igemm/gen/4x8c16-minmax-neon-mlal-padal.c",
- "src/qs8-igemm/gen/4x16-minmax-neon-mlal-lane.c",
- "src/qs8-igemm/gen/4x16-minmax-neon-mull-addw-dup.c",
- "src/qs8-igemm/gen/4x16c2-minmax-neon-mlal-padal-dup.c",
- "src/qs8-igemm/gen/4x16c2-minmax-neon-mull-padal-dup.c",
- "src/qs8-igemm/gen/4x16c8-minmax-neon-mlal-padal.c",
- "src/qs8-igemm/gen/4x16c8-minmax-neon-mull-padal.c",
- "src/qs8-igemm/gen/4x16c16-minmax-neon-mlal-padal.c",
+ "src/qc8-dwconv/gen/up8x9-minmax-fp32-neon-mla8-ld64.c",
+ "src/qc8-dwconv/gen/up8x9-minmax-fp32-neon-mul8-ld64.c",
+ "src/qc8-dwconv/gen/up8x9-minmax-fp32-neon-mul16.c",
+ "src/qc8-dwconv/gen/up8x25-minmax-fp32-neon-mla8-ld64.c",
+ "src/qc8-dwconv/gen/up8x25-minmax-fp32-neon-mul8-ld64.c",
+ "src/qc8-dwconv/gen/up8x25-minmax-fp32-neon-mul16.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-neon-mla8-ld64.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-neon-mla8-ld128.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-neon-mul8-ld64.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-neon-mul8-ld128.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-neon-mul16.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-neon-mla8-ld64.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-neon-mla8-ld128.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-neon-mul8-ld64.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-neon-mul8-ld128.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-neon-mul16.c",
+ "src/qc8-dwconv/gen/up24x9-minmax-fp32-neon-mul16.c",
+ "src/qc8-dwconv/gen/up24x25-minmax-fp32-neon-mul16.c",
+ "src/qc8-dwconv/gen/up32x9-minmax-fp32-neon-mul16.c",
+ "src/qc8-dwconv/gen/up32x25-minmax-fp32-neon-mul16.c",
+ "src/qc8-gemm/gen/1x8-minmax-fp32-neon-mlal-lane-prfm.c",
+ "src/qc8-gemm/gen/1x8-minmax-fp32-neon-mlal-lane.c",
+ "src/qc8-gemm/gen/1x8c2-minmax-fp32-neon-mlal-dup.c",
+ "src/qc8-gemm/gen/1x8c2-minmax-fp32-neon-mlal-ld1r.c",
+ "src/qc8-gemm/gen/1x8c2-minmax-fp32-neon-mlal-ld2r.c",
+ "src/qc8-gemm/gen/1x8c2-minmax-fp32-neon-mlal-ld4r.c",
+ "src/qc8-gemm/gen/1x8c2s4-minmax-fp32-neon-mlal.c",
+ "src/qc8-gemm/gen/1x8c4-minmax-fp32-neon-mlal-dup.c",
+ "src/qc8-gemm/gen/1x8c4-minmax-fp32-neon-mlal-ld1r.c",
+ "src/qc8-gemm/gen/1x8c4-minmax-fp32-neon-mlal-ld2r.c",
+ "src/qc8-gemm/gen/1x8c4s2-minmax-fp32-neon-mlal.c",
+ "src/qc8-gemm/gen/1x8c8-minmax-fp32-neon-mlal.c",
+ "src/qc8-gemm/gen/1x16-minmax-fp32-neon-mlal-lane-prfm.c",
+ "src/qc8-gemm/gen/1x16-minmax-fp32-neon-mlal-lane.c",
+ "src/qc8-gemm/gen/2x8-minmax-fp32-neon-mlal-lane-prfm.c",
+ "src/qc8-gemm/gen/2x8-minmax-fp32-neon-mlal-lane.c",
+ "src/qc8-gemm/gen/2x8c2-minmax-fp32-neon-mlal-dup.c",
+ "src/qc8-gemm/gen/2x8c2-minmax-fp32-neon-mlal-ld1r.c",
+ "src/qc8-gemm/gen/2x8c2-minmax-fp32-neon-mlal-ld2r.c",
+ "src/qc8-gemm/gen/2x8c2-minmax-fp32-neon-mlal-ld4r.c",
+ "src/qc8-gemm/gen/2x8c2s4-minmax-fp32-neon-mlal.c",
+ "src/qc8-gemm/gen/2x8c4-minmax-fp32-neon-mlal-dup.c",
+ "src/qc8-gemm/gen/2x8c4-minmax-fp32-neon-mlal-ld1r.c",
+ "src/qc8-gemm/gen/2x8c4-minmax-fp32-neon-mlal-ld2r.c",
+ "src/qc8-gemm/gen/2x8c4s2-minmax-fp32-neon-mlal.c",
+ "src/qc8-gemm/gen/2x8c8-minmax-fp32-neon-mlal.c",
+ "src/qc8-gemm/gen/2x16-minmax-fp32-neon-mlal-lane-prfm.c",
+ "src/qc8-gemm/gen/2x16-minmax-fp32-neon-mlal-lane.c",
+ "src/qc8-gemm/gen/3x8-minmax-fp32-neon-mlal-lane-prfm.c",
+ "src/qc8-gemm/gen/3x8-minmax-fp32-neon-mlal-lane.c",
+ "src/qc8-gemm/gen/3x16-minmax-fp32-neon-mlal-lane-prfm.c",
+ "src/qc8-gemm/gen/3x16-minmax-fp32-neon-mlal-lane.c",
+ "src/qc8-gemm/gen/4x8-minmax-fp32-neon-mlal-lane-prfm.c",
+ "src/qc8-gemm/gen/4x8-minmax-fp32-neon-mlal-lane.c",
+ "src/qc8-gemm/gen/4x16-minmax-fp32-neon-mlal-lane-prfm.c",
+ "src/qc8-gemm/gen/4x16-minmax-fp32-neon-mlal-lane.c",
+ "src/qc8-gemm/gen/6x8-minmax-fp32-neon-mlal-lane-prfm.c",
+ "src/qc8-gemm/gen/6x8-minmax-fp32-neon-mlal-lane.c",
+ "src/qc8-gemm/gen/6x16-minmax-fp32-neon-mlal-lane-prfm.c",
+ "src/qc8-gemm/gen/6x16-minmax-fp32-neon-mlal-lane.c",
+ "src/qc8-igemm/gen/1x8-minmax-fp32-neon-mlal-lane-prfm.c",
+ "src/qc8-igemm/gen/1x8-minmax-fp32-neon-mlal-lane.c",
+ "src/qc8-igemm/gen/1x8c2-minmax-fp32-neon-mlal-dup.c",
+ "src/qc8-igemm/gen/1x8c2-minmax-fp32-neon-mlal-ld1r.c",
+ "src/qc8-igemm/gen/1x8c2-minmax-fp32-neon-mlal-ld2r.c",
+ "src/qc8-igemm/gen/1x8c2-minmax-fp32-neon-mlal-ld4r.c",
+ "src/qc8-igemm/gen/1x8c2s4-minmax-fp32-neon-mlal.c",
+ "src/qc8-igemm/gen/1x8c4-minmax-fp32-neon-mlal-dup.c",
+ "src/qc8-igemm/gen/1x8c4-minmax-fp32-neon-mlal-ld1r.c",
+ "src/qc8-igemm/gen/1x8c4-minmax-fp32-neon-mlal-ld2r.c",
+ "src/qc8-igemm/gen/1x8c4s2-minmax-fp32-neon-mlal.c",
+ "src/qc8-igemm/gen/1x8c8-minmax-fp32-neon-mlal.c",
+ "src/qc8-igemm/gen/1x16-minmax-fp32-neon-mlal-lane-prfm.c",
+ "src/qc8-igemm/gen/1x16-minmax-fp32-neon-mlal-lane.c",
+ "src/qc8-igemm/gen/2x8-minmax-fp32-neon-mlal-lane-prfm.c",
+ "src/qc8-igemm/gen/2x8-minmax-fp32-neon-mlal-lane.c",
+ "src/qc8-igemm/gen/2x8c2-minmax-fp32-neon-mlal-dup.c",
+ "src/qc8-igemm/gen/2x8c2-minmax-fp32-neon-mlal-ld1r.c",
+ "src/qc8-igemm/gen/2x8c2-minmax-fp32-neon-mlal-ld2r.c",
+ "src/qc8-igemm/gen/2x8c2-minmax-fp32-neon-mlal-ld4r.c",
+ "src/qc8-igemm/gen/2x8c2s4-minmax-fp32-neon-mlal.c",
+ "src/qc8-igemm/gen/2x8c4-minmax-fp32-neon-mlal-dup.c",
+ "src/qc8-igemm/gen/2x8c4-minmax-fp32-neon-mlal-ld1r.c",
+ "src/qc8-igemm/gen/2x8c4-minmax-fp32-neon-mlal-ld2r.c",
+ "src/qc8-igemm/gen/2x8c4s2-minmax-fp32-neon-mlal.c",
+ "src/qc8-igemm/gen/2x8c8-minmax-fp32-neon-mlal.c",
+ "src/qc8-igemm/gen/2x16-minmax-fp32-neon-mlal-lane-prfm.c",
+ "src/qc8-igemm/gen/2x16-minmax-fp32-neon-mlal-lane.c",
+ "src/qc8-igemm/gen/3x8-minmax-fp32-neon-mlal-lane-prfm.c",
+ "src/qc8-igemm/gen/3x8-minmax-fp32-neon-mlal-lane.c",
+ "src/qc8-igemm/gen/3x16-minmax-fp32-neon-mlal-lane-prfm.c",
+ "src/qc8-igemm/gen/3x16-minmax-fp32-neon-mlal-lane.c",
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+ "src/qs8-igemm/gen/3x16c4-minmax-rndnu-neon-mull-dup.c",
+ "src/qs8-igemm/gen/3x16c4-minmax-rndnu-neon-mull-ld1r.c",
+ "src/qs8-igemm/gen/3x16c4-minmax-rndnu-neon-mull-ld2r.c",
+ "src/qs8-igemm/gen/3x16c4s2-minmax-rndnu-neon-mlal.c",
+ "src/qs8-igemm/gen/3x16c4s2-minmax-rndnu-neon-mull.c",
+ "src/qs8-igemm/gen/3x16c8-minmax-rndnu-neon-mlal.c",
+ "src/qs8-igemm/gen/3x16c8-minmax-rndnu-neon-mull.c",
+ "src/qs8-igemm/gen/3x16c16-minmax-rndnu-neon-mlal.c",
+ "src/qs8-igemm/gen/4x8-minmax-rndnu-neon-mlal-lane-prfm.c",
+ "src/qs8-igemm/gen/4x8-minmax-rndnu-neon-mlal-lane.c",
+ "src/qs8-igemm/gen/4x8-minmax-rndnu-neon-mull-addw-dup.c",
+ "src/qs8-igemm/gen/4x8c2-minmax-rndnu-neon-mlal-dup.c",
+ "src/qs8-igemm/gen/4x8c2-minmax-rndnu-neon-mlal-ld1r.c",
+ "src/qs8-igemm/gen/4x8c2-minmax-rndnu-neon-mlal-ld2r.c",
+ "src/qs8-igemm/gen/4x8c2-minmax-rndnu-neon-mlal-ld4r.c",
+ "src/qs8-igemm/gen/4x8c2-minmax-rndnu-neon-mull-dup.c",
+ "src/qs8-igemm/gen/4x8c2-minmax-rndnu-neon-mull-ld1r.c",
+ "src/qs8-igemm/gen/4x8c2-minmax-rndnu-neon-mull-ld2r.c",
+ "src/qs8-igemm/gen/4x8c2-minmax-rndnu-neon-mull-ld4r.c",
+ "src/qs8-igemm/gen/4x8c2s4-minmax-rndnu-neon-mlal.c",
+ "src/qs8-igemm/gen/4x8c2s4-minmax-rndnu-neon-mull.c",
+ "src/qs8-igemm/gen/4x8c4-minmax-rndnu-neon-mlal-dup.c",
+ "src/qs8-igemm/gen/4x8c4-minmax-rndnu-neon-mlal-ld1r.c",
+ "src/qs8-igemm/gen/4x8c4-minmax-rndnu-neon-mlal-ld2r.c",
+ "src/qs8-igemm/gen/4x8c4-minmax-rndnu-neon-mull-dup.c",
+ "src/qs8-igemm/gen/4x8c4-minmax-rndnu-neon-mull-ld1r.c",
+ "src/qs8-igemm/gen/4x8c4-minmax-rndnu-neon-mull-ld2r.c",
+ "src/qs8-igemm/gen/4x8c4s2-minmax-rndnu-neon-mlal.c",
+ "src/qs8-igemm/gen/4x8c4s2-minmax-rndnu-neon-mull.c",
+ "src/qs8-igemm/gen/4x8c8-minmax-rndnu-neon-mlal.c",
+ "src/qs8-igemm/gen/4x8c8-minmax-rndnu-neon-mull.c",
+ "src/qs8-igemm/gen/4x8c16-minmax-rndnu-neon-mlal.c",
+ "src/qs8-igemm/gen/4x16-minmax-fp32-neon-mlal-lane.c",
+ "src/qs8-igemm/gen/4x16-minmax-rndnu-neon-mlal-lane-prfm.c",
+ "src/qs8-igemm/gen/4x16-minmax-rndnu-neon-mlal-lane.c",
+ "src/qs8-igemm/gen/4x16-minmax-rndnu-neon-mull-addw-dup.c",
+ "src/qs8-igemm/gen/4x16c2-minmax-rndnu-neon-mlal-dup.c",
+ "src/qs8-igemm/gen/4x16c2-minmax-rndnu-neon-mlal-ld1r.c",
+ "src/qs8-igemm/gen/4x16c2-minmax-rndnu-neon-mlal-ld2r.c",
+ "src/qs8-igemm/gen/4x16c2-minmax-rndnu-neon-mlal-ld4r.c",
+ "src/qs8-igemm/gen/4x16c2-minmax-rndnu-neon-mull-dup.c",
+ "src/qs8-igemm/gen/4x16c2-minmax-rndnu-neon-mull-ld1r.c",
+ "src/qs8-igemm/gen/4x16c2-minmax-rndnu-neon-mull-ld2r.c",
+ "src/qs8-igemm/gen/4x16c2-minmax-rndnu-neon-mull-ld4r.c",
+ "src/qs8-igemm/gen/4x16c2s4-minmax-rndnu-neon-mlal.c",
+ "src/qs8-igemm/gen/4x16c2s4-minmax-rndnu-neon-mull.c",
+ "src/qs8-igemm/gen/4x16c4-minmax-rndnu-neon-mlal-dup.c",
+ "src/qs8-igemm/gen/4x16c4-minmax-rndnu-neon-mlal-ld1r.c",
+ "src/qs8-igemm/gen/4x16c4-minmax-rndnu-neon-mlal-ld2r.c",
+ "src/qs8-igemm/gen/4x16c4-minmax-rndnu-neon-mull-dup.c",
+ "src/qs8-igemm/gen/4x16c4-minmax-rndnu-neon-mull-ld1r.c",
+ "src/qs8-igemm/gen/4x16c4-minmax-rndnu-neon-mull-ld2r.c",
+ "src/qs8-igemm/gen/4x16c4s2-minmax-rndnu-neon-mlal.c",
+ "src/qs8-igemm/gen/4x16c4s2-minmax-rndnu-neon-mull.c",
+ "src/qs8-igemm/gen/4x16c8-minmax-rndnu-neon-mlal.c",
+ "src/qs8-igemm/gen/4x16c8-minmax-rndnu-neon-mull.c",
+ "src/qs8-igemm/gen/4x16c16-minmax-rndnu-neon-mlal.c",
+ "src/qs8-igemm/gen/6x8-minmax-rndnu-neon-mlal-lane-prfm.c",
+ "src/qs8-igemm/gen/6x8-minmax-rndnu-neon-mlal-lane.c",
+ "src/qs8-igemm/gen/6x16-minmax-rndnu-neon-mlal-lane-prfm.c",
+ "src/qs8-igemm/gen/6x16-minmax-rndnu-neon-mlal-lane.c",
"src/qs8-requantization/fp32-neon.c",
- "src/qs8-requantization/precise-neon.c",
- "src/qs8-requantization/q31-neon.c",
+ "src/qs8-requantization/gemmlowp-neon.c",
+ "src/qs8-requantization/rndna-neon.c",
+ "src/qs8-requantization/rndnu-neon-mull.c",
+ "src/qs8-requantization/rndnu-neon-qdmulh.c",
"src/qs8-vadd/gen/minmax-neon-ld64-x8.c",
"src/qs8-vadd/gen/minmax-neon-ld64-x16.c",
"src/qs8-vadd/gen/minmax-neon-ld64-x24.c",
"src/qs8-vadd/gen/minmax-neon-ld64-x32.c",
+ "src/qs8-vadd/gen/minmax-neon-ld128-x16.c",
+ "src/qs8-vadd/gen/minmax-neon-ld128-x32.c",
"src/qs8-vaddc/gen/minmax-neon-ld64-x8.c",
"src/qs8-vaddc/gen/minmax-neon-ld64-x16.c",
"src/qs8-vaddc/gen/minmax-neon-ld64-x24.c",
"src/qs8-vaddc/gen/minmax-neon-ld64-x32.c",
+ "src/qs8-vaddc/gen/minmax-neon-ld128-x16.c",
+ "src/qs8-vaddc/gen/minmax-neon-ld128-x32.c",
+ "src/qs8-vmul/gen/minmax-fp32-neon-ld64-x8.c",
+ "src/qs8-vmul/gen/minmax-fp32-neon-ld64-x16.c",
+ "src/qs8-vmul/gen/minmax-fp32-neon-ld128-x16.c",
+ "src/qs8-vmul/gen/minmax-rndnu-neon-ld64-x8.c",
+ "src/qs8-vmul/gen/minmax-rndnu-neon-ld64-x16.c",
+ "src/qs8-vmul/gen/minmax-rndnu-neon-ld128-x16.c",
+ "src/qs8-vmulc/gen/minmax-fp32-neon-ld64-x8.c",
+ "src/qs8-vmulc/gen/minmax-fp32-neon-ld64-x16.c",
+ "src/qs8-vmulc/gen/minmax-fp32-neon-ld128-x16.c",
+ "src/qs8-vmulc/gen/minmax-rndnu-neon-ld64-x8.c",
+ "src/qs8-vmulc/gen/minmax-rndnu-neon-ld64-x16.c",
+ "src/qs8-vmulc/gen/minmax-rndnu-neon-ld128-x16.c",
"src/qu8-avgpool/9p8x-minmax-neon-c8.c",
"src/qu8-avgpool/9x-minmax-neon-c8.c",
- "src/qu8-dwconv/up8x9-minmax-neon.c",
- "src/qu8-gavgpool/7p7x-minmax-neon-c8.c",
- "src/qu8-gavgpool/7x-minmax-neon-c8.c",
- "src/qu8-gemm/4x8-minmax-neon.c",
- "src/qu8-gemm/8x8-minmax-neon.c",
- "src/qu8-igemm/4x8-minmax-neon.c",
- "src/qu8-igemm/8x8-minmax-neon.c",
+ "src/qu8-dwconv/gen/up8x9-minmax-fp32-neon-mul16.c",
+ "src/qu8-dwconv/gen/up8x9-minmax-rndnu-neon-mul8.c",
+ "src/qu8-dwconv/gen/up8x9-minmax-rndnu-neon-mul16.c",
+ "src/qu8-dwconv/gen/up8x25-minmax-fp32-neon-mul16.c",
+ "src/qu8-dwconv/gen/up8x25-minmax-rndnu-neon-mul8.c",
+ "src/qu8-dwconv/gen/up8x25-minmax-rndnu-neon-mul16.c",
+ "src/qu8-dwconv/gen/up16x9-minmax-fp32-neon-mul16.c",
+ "src/qu8-dwconv/gen/up16x9-minmax-rndnu-neon-mul8.c",
+ "src/qu8-dwconv/gen/up16x9-minmax-rndnu-neon-mul16.c",
+ "src/qu8-dwconv/gen/up16x25-minmax-fp32-neon-mul16.c",
+ "src/qu8-dwconv/gen/up16x25-minmax-rndnu-neon-mul8.c",
+ "src/qu8-dwconv/gen/up16x25-minmax-rndnu-neon-mul16.c",
+ "src/qu8-dwconv/gen/up24x9-minmax-fp32-neon-mul16.c",
+ "src/qu8-dwconv/gen/up24x9-minmax-rndnu-neon-mul8.c",
+ "src/qu8-dwconv/gen/up24x9-minmax-rndnu-neon-mul16.c",
+ "src/qu8-dwconv/gen/up24x25-minmax-fp32-neon-mul16.c",
+ "src/qu8-dwconv/gen/up24x25-minmax-rndnu-neon-mul8.c",
+ "src/qu8-dwconv/gen/up24x25-minmax-rndnu-neon-mul16.c",
+ "src/qu8-dwconv/gen/up32x9-minmax-fp32-neon-mul16.c",
+ "src/qu8-dwconv/gen/up32x9-minmax-rndnu-neon-mul8.c",
+ "src/qu8-dwconv/gen/up32x9-minmax-rndnu-neon-mul16.c",
+ "src/qu8-dwconv/gen/up32x25-minmax-fp32-neon-mul16.c",
+ "src/qu8-dwconv/gen/up32x25-minmax-rndnu-neon-mul8.c",
+ "src/qu8-dwconv/gen/up32x25-minmax-rndnu-neon-mul16.c",
+ "src/qu8-f32-vcvt/gen/vcvt-neon-x8.c",
+ "src/qu8-f32-vcvt/gen/vcvt-neon-x16.c",
+ "src/qu8-f32-vcvt/gen/vcvt-neon-x24.c",
+ "src/qu8-f32-vcvt/gen/vcvt-neon-x32.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-neon-c8.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-neon-c16.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-neon-c24.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-neon-c32.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-rndnu-neon-c8.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-rndnu-neon-c16.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-rndnu-neon-c24.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-rndnu-neon-c32.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-neon-c8.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-neon-c16.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-neon-c24.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-neon-c32.c",
+ "src/qu8-gavgpool/gen/7x-minmax-rndnu-neon-c8.c",
+ "src/qu8-gavgpool/gen/7x-minmax-rndnu-neon-c16.c",
+ "src/qu8-gavgpool/gen/7x-minmax-rndnu-neon-c24.c",
+ "src/qu8-gavgpool/gen/7x-minmax-rndnu-neon-c32.c",
+ "src/qu8-gemm/gen/1x8-minmax-fp32-neon-mlal-lane.c",
+ "src/qu8-gemm/gen/1x8-minmax-rndnu-neon-mlal-lane.c",
+ "src/qu8-gemm/gen/1x16-minmax-fp32-neon-mlal-lane.c",
+ "src/qu8-gemm/gen/1x16-minmax-rndnu-neon-mlal-lane.c",
+ "src/qu8-gemm/gen/2x8-minmax-rndnu-neon-mlal-lane.c",
+ "src/qu8-gemm/gen/2x16-minmax-rndnu-neon-mlal-lane.c",
+ "src/qu8-gemm/gen/3x8-minmax-rndnu-neon-mlal-lane.c",
+ "src/qu8-gemm/gen/3x16-minmax-rndnu-neon-mlal-lane.c",
+ "src/qu8-gemm/gen/4x8-minmax-fp32-neon-mlal-lane.c",
+ "src/qu8-gemm/gen/4x8-minmax-rndnu-neon-mlal-lane.c",
+ "src/qu8-gemm/gen/4x16-minmax-fp32-neon-mlal-lane.c",
+ "src/qu8-gemm/gen/4x16-minmax-rndnu-neon-mlal-lane.c",
+ "src/qu8-gemm/gen/6x8-minmax-rndnu-neon-mlal-lane.c",
+ "src/qu8-gemm/gen/6x16-minmax-rndnu-neon-mlal-lane.c",
+ "src/qu8-igemm/gen/1x8-minmax-fp32-neon-mlal-lane.c",
+ "src/qu8-igemm/gen/1x8-minmax-rndnu-neon-mlal-lane.c",
+ "src/qu8-igemm/gen/1x16-minmax-fp32-neon-mlal-lane.c",
+ "src/qu8-igemm/gen/1x16-minmax-rndnu-neon-mlal-lane.c",
+ "src/qu8-igemm/gen/2x8-minmax-rndnu-neon-mlal-lane.c",
+ "src/qu8-igemm/gen/2x16-minmax-rndnu-neon-mlal-lane.c",
+ "src/qu8-igemm/gen/3x8-minmax-rndnu-neon-mlal-lane.c",
+ "src/qu8-igemm/gen/3x16-minmax-rndnu-neon-mlal-lane.c",
+ "src/qu8-igemm/gen/4x8-minmax-fp32-neon-mlal-lane.c",
+ "src/qu8-igemm/gen/4x8-minmax-rndnu-neon-mlal-lane.c",
+ "src/qu8-igemm/gen/4x16-minmax-fp32-neon-mlal-lane.c",
+ "src/qu8-igemm/gen/4x16-minmax-rndnu-neon-mlal-lane.c",
+ "src/qu8-igemm/gen/6x8-minmax-rndnu-neon-mlal-lane.c",
+ "src/qu8-igemm/gen/6x16-minmax-rndnu-neon-mlal-lane.c",
"src/qu8-requantization/fp32-neon.c",
- "src/qu8-requantization/precise-neon.c",
- "src/qu8-requantization/q31-neon.c",
- "src/qu8-vadd/minmax-neon.c",
- "src/u8-clamp/neon-x64.c",
+ "src/qu8-requantization/gemmlowp-neon.c",
+ "src/qu8-requantization/rndna-neon.c",
+ "src/qu8-vadd/gen/minmax-neon-ld64-x8.c",
+ "src/qu8-vadd/gen/minmax-neon-ld64-x16.c",
+ "src/qu8-vadd/gen/minmax-neon-ld64-x32.c",
+ "src/qu8-vadd/gen/minmax-neon-ld128-x16.c",
+ "src/qu8-vaddc/gen/minmax-neon-ld64-x8.c",
+ "src/qu8-vaddc/gen/minmax-neon-ld64-x16.c",
+ "src/qu8-vaddc/gen/minmax-neon-ld64-x32.c",
+ "src/qu8-vaddc/gen/minmax-neon-ld128-x16.c",
+ "src/qu8-vmul/gen/minmax-fp32-neon-ld64-x8.c",
+ "src/qu8-vmul/gen/minmax-fp32-neon-ld64-x16.c",
+ "src/qu8-vmul/gen/minmax-fp32-neon-ld128-x16.c",
+ "src/qu8-vmul/gen/minmax-rndnu-neon-ld64-x8.c",
+ "src/qu8-vmul/gen/minmax-rndnu-neon-ld64-x16.c",
+ "src/qu8-vmul/gen/minmax-rndnu-neon-ld128-x16.c",
+ "src/qu8-vmulc/gen/minmax-fp32-neon-ld64-x8.c",
+ "src/qu8-vmulc/gen/minmax-fp32-neon-ld64-x16.c",
+ "src/qu8-vmulc/gen/minmax-fp32-neon-ld128-x16.c",
+ "src/qu8-vmulc/gen/minmax-rndnu-neon-ld64-x8.c",
+ "src/qu8-vmulc/gen/minmax-rndnu-neon-ld64-x16.c",
+ "src/qu8-vmulc/gen/minmax-rndnu-neon-ld128-x16.c",
+ "src/s8-ibilinear/gen/neon-c8.c",
+ "src/s8-ibilinear/gen/neon-c16.c",
+ "src/s8-maxpool/9p8x-minmax-neon-c16.c",
+ "src/s8-vclamp/neon-x64.c",
+ "src/u8-ibilinear/gen/neon-c8.c",
+ "src/u8-ibilinear/gen/neon-c16.c",
"src/u8-maxpool/9p8x-minmax-neon-c16.c",
"src/u8-rmax/neon.c",
+ "src/u8-vclamp/neon-x64.c",
+ "src/x8-transpose/gen/16x16-reuse-dec-zip-neon.c",
+ "src/x8-transpose/gen/16x16-reuse-mov-zip-neon.c",
+ "src/x8-transpose/gen/16x16-reuse-switch-zip-neon.c",
"src/x8-zip/x2-neon.c",
"src/x8-zip/x3-neon.c",
"src/x8-zip/x4-neon.c",
"src/x8-zip/xm-neon.c",
- "src/x32-fill/neon.c",
+ "src/x16-transpose/gen/8x8-multi-dec-zip-neon.c",
+ "src/x16-transpose/gen/8x8-multi-mov-zip-neon.c",
+ "src/x16-transpose/gen/8x8-multi-switch-zip-neon.c",
+ "src/x16-transpose/gen/8x8-reuse-dec-zip-neon.c",
+ "src/x16-transpose/gen/8x8-reuse-mov-zip-neon.c",
+ "src/x16-transpose/gen/8x8-reuse-multi-zip-neon.c",
+ "src/x16-transpose/gen/8x8-reuse-switch-zip-neon.c",
"src/x32-packx/x4-neon-st4.c",
- "src/x32-pad/neon.c",
+ "src/x32-transpose/gen/4x4-multi-dec-zip-neon.c",
+ "src/x32-transpose/gen/4x4-multi-mov-zip-neon.c",
+ "src/x32-transpose/gen/4x4-multi-multi-zip-neon.c",
+ "src/x32-transpose/gen/4x4-multi-switch-zip-neon.c",
+ "src/x32-transpose/gen/4x4-reuse-dec-zip-neon.c",
+ "src/x32-transpose/gen/4x4-reuse-mov-zip-neon.c",
+ "src/x32-transpose/gen/4x4-reuse-multi-zip-neon.c",
+ "src/x32-transpose/gen/4x4-reuse-switch-zip-neon.c",
"src/x32-unpool/neon.c",
"src/x32-zip/x2-neon.c",
"src/x32-zip/x3-neon.c",
"src/x32-zip/x4-neon.c",
"src/x32-zip/xm-neon.c",
+ "src/xx-fill/neon-x64.c",
+ "src/xx-pad/neon.c",
]
-NEONFMA_UKERNELS = [
+PROD_NEONFP16_MICROKERNEL_SRCS = [
+ "src/f16-f32-vcvt/gen/vcvt-neonfp16-x16.c",
+ "src/f32-f16-vcvt/gen/vcvt-neonfp16-x16.c",
+]
+
+ALL_NEONFP16_MICROKERNEL_SRCS = [
+ "src/f16-f32-vcvt/gen/vcvt-neonfp16-x8.c",
+ "src/f16-f32-vcvt/gen/vcvt-neonfp16-x16.c",
+ "src/f32-f16-vcvt/gen/vcvt-neonfp16-x8.c",
+ "src/f32-f16-vcvt/gen/vcvt-neonfp16-x16.c",
+ "src/math/cvt-f16-f32-neonfp16.c",
+ "src/math/cvt-f32-f16-neonfp16.c",
+]
+
+PROD_NEONFMA_MICROKERNEL_SRCS = [
+ "src/f32-dwconv/gen/up8x3-minmax-neonfma.c",
+ "src/f32-dwconv/gen/up8x4-minmax-neonfma.c",
+ "src/f32-dwconv/gen/up8x9-minmax-neonfma.c",
+ "src/f32-dwconv/gen/up8x25-minmax-neonfma-acc2.c",
+ "src/f32-gemm/gen/1x8s4-minmax-neonfma.c",
+ "src/f32-gemm/gen/6x8s4-minmax-neonfma.c",
+ "src/f32-ibilinear-chw/gen/neonfma-p8.c",
+ "src/f32-ibilinear/gen/neonfma-c8.c",
+ "src/f32-igemm/gen/1x8s4-minmax-neonfma.c",
+ "src/f32-igemm/gen/6x8s4-minmax-neonfma.c",
+ "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-lut64-p2-x16.c",
+ "src/f32-spmm/gen/32x1-minmax-neonfma-pipelined.c",
+ "src/f32-velu/gen/velu-neonfma-rr1-lut16-p3-x16.c",
+ "src/f32-velu/gen/velu-neonfma-rr1-p6-x8.c",
+ "src/f32-vmulcaddc/gen/c4-minmax-neonfma-2x.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2recps-x16.c",
+]
+
+ALL_NEONFMA_MICROKERNEL_SRCS = [
+ "src/f32-dwconv/gen/up4x3-minmax-neonfma-acc2.c",
+ "src/f32-dwconv/gen/up4x3-minmax-neonfma.c",
"src/f32-dwconv/gen/up4x4-minmax-neonfma-acc2.c",
"src/f32-dwconv/gen/up4x4-minmax-neonfma.c",
"src/f32-dwconv/gen/up4x9-minmax-neonfma-acc2.c",
"src/f32-dwconv/gen/up4x9-minmax-neonfma.c",
"src/f32-dwconv/gen/up4x25-minmax-neonfma-acc2.c",
"src/f32-dwconv/gen/up4x25-minmax-neonfma.c",
+ "src/f32-dwconv/gen/up8x3-minmax-neonfma-acc2.c",
+ "src/f32-dwconv/gen/up8x3-minmax-neonfma.c",
"src/f32-dwconv/gen/up8x4-minmax-neonfma-acc2.c",
"src/f32-dwconv/gen/up8x4-minmax-neonfma.c",
"src/f32-dwconv/gen/up8x9-minmax-neonfma-acc2.c",
"src/f32-dwconv/gen/up8x9-minmax-neonfma.c",
"src/f32-dwconv/gen/up8x25-minmax-neonfma-acc2.c",
"src/f32-dwconv/gen/up8x25-minmax-neonfma.c",
+ "src/f32-dwconv/gen/up16x3-minmax-neon-acc2.c",
+ "src/f32-dwconv/gen/up16x3-minmax-neon.c",
+ "src/f32-dwconv/gen/up16x3-minmax-neonfma-acc2.c",
+ "src/f32-dwconv/gen/up16x3-minmax-neonfma.c",
+ "src/f32-dwconv/gen/up16x4-minmax-neon-acc2.c",
+ "src/f32-dwconv/gen/up16x4-minmax-neon.c",
+ "src/f32-dwconv/gen/up16x4-minmax-neonfma-acc2.c",
+ "src/f32-dwconv/gen/up16x4-minmax-neonfma.c",
+ "src/f32-dwconv/gen/up16x9-minmax-neon-acc2.c",
+ "src/f32-dwconv/gen/up16x9-minmax-neon.c",
+ "src/f32-dwconv/gen/up16x9-minmax-neonfma-acc2.c",
+ "src/f32-dwconv/gen/up16x9-minmax-neonfma.c",
+ "src/f32-dwconv/gen/up16x25-minmax-neon-acc2.c",
+ "src/f32-dwconv/gen/up16x25-minmax-neon.c",
+ "src/f32-dwconv/gen/up16x25-minmax-neonfma-acc2.c",
+ "src/f32-dwconv/gen/up16x25-minmax-neonfma.c",
"src/f32-gemm/gen-inc/1x8inc-minmax-neonfma-dup-ld64.c",
"src/f32-gemm/gen-inc/1x8s4inc-minmax-neonfma.c",
"src/f32-gemm/gen-inc/4x8inc-minmax-neonfma-dup-ld64.c",
@@ -1002,84 +3856,30 @@
"src/f32-igemm/gen/8x8s4-minmax-neonfma.c",
"src/f32-ppmm/gen/4x8-minmax-neonfma.c",
"src/f32-ppmm/gen/8x8-minmax-neonfma.c",
- "src/f32-raddstoreexpminusmax/gen/neonfma-lut64-p2-x4.c",
- "src/f32-raddstoreexpminusmax/gen/neonfma-lut64-p2-x8-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/neonfma-lut64-p2-x8.c",
- "src/f32-raddstoreexpminusmax/gen/neonfma-lut64-p2-x12-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/neonfma-lut64-p2-x12-acc3.c",
- "src/f32-raddstoreexpminusmax/gen/neonfma-lut64-p2-x12.c",
- "src/f32-raddstoreexpminusmax/gen/neonfma-lut64-p2-x16-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/neonfma-lut64-p2-x16-acc4.c",
- "src/f32-raddstoreexpminusmax/gen/neonfma-lut64-p2-x16.c",
- "src/f32-raddstoreexpminusmax/gen/neonfma-lut64-p2-x20-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/neonfma-lut64-p2-x20-acc5.c",
- "src/f32-raddstoreexpminusmax/gen/neonfma-lut64-p2-x20.c",
- "src/f32-raddstoreexpminusmax/gen/neonfma-p5-x4.c",
- "src/f32-raddstoreexpminusmax/gen/neonfma-p5-x8-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/neonfma-p5-x8.c",
- "src/f32-raddstoreexpminusmax/gen/neonfma-p5-x12-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/neonfma-p5-x12-acc3.c",
- "src/f32-raddstoreexpminusmax/gen/neonfma-p5-x12.c",
- "src/f32-raddstoreexpminusmax/gen/neonfma-p5-x16-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/neonfma-p5-x16-acc4.c",
- "src/f32-raddstoreexpminusmax/gen/neonfma-p5-x16.c",
- "src/f32-raddstoreexpminusmax/gen/neonfma-p5-x20-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/neonfma-p5-x20-acc5.c",
- "src/f32-raddstoreexpminusmax/gen/neonfma-p5-x20.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut64-p2-nr1recps1fma-x4.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut64-p2-nr1recps1fma-x8.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut64-p2-nr1recps1fma-x12.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut64-p2-nr1recps1fma-x16.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut64-p2-nr1recps1fma-x20.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut64-p2-nr1recps1fma-x24.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut64-p2-nr2fma-x4.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut64-p2-nr2fma-x8.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut64-p2-nr2fma-x12.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut64-p2-nr2fma-x16.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut64-p2-nr2fma-x20.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut64-p2-nr2fma-x24.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut64-p2-nr2recps-x4.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut64-p2-nr2recps-x8.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut64-p2-nr2recps-x12.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut64-p2-nr2recps-x16.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut64-p2-nr2recps-x20.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut64-p2-nr2recps-x24.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut2048-p1-nr1recps1fma-x4.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut2048-p1-nr1recps1fma-x8.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut2048-p1-nr1recps1fma-x12.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut2048-p1-nr1recps1fma-x16.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut2048-p1-nr1recps1fma-x20.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut2048-p1-nr1recps1fma-x24.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut2048-p1-nr2fma-x4.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut2048-p1-nr2fma-x8.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut2048-p1-nr2fma-x12.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut2048-p1-nr2fma-x16.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut2048-p1-nr2fma-x20.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut2048-p1-nr2fma-x24.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut2048-p1-nr2recps-x4.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut2048-p1-nr2recps-x8.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut2048-p1-nr2recps-x12.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut2048-p1-nr2recps-x16.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut2048-p1-nr2recps-x20.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut2048-p1-nr2recps-x24.c",
- "src/f32-sigmoid/gen/neonfma-rr1-p5-nr1recps1fma-x4.c",
- "src/f32-sigmoid/gen/neonfma-rr1-p5-nr1recps1fma-x8.c",
- "src/f32-sigmoid/gen/neonfma-rr1-p5-nr1recps1fma-x12.c",
- "src/f32-sigmoid/gen/neonfma-rr1-p5-nr1recps1fma-x16.c",
- "src/f32-sigmoid/gen/neonfma-rr1-p5-nr1recps1fma-x20.c",
- "src/f32-sigmoid/gen/neonfma-rr1-p5-nr1recps1fma-x24.c",
- "src/f32-sigmoid/gen/neonfma-rr1-p5-nr2fma-x4.c",
- "src/f32-sigmoid/gen/neonfma-rr1-p5-nr2fma-x8.c",
- "src/f32-sigmoid/gen/neonfma-rr1-p5-nr2fma-x12.c",
- "src/f32-sigmoid/gen/neonfma-rr1-p5-nr2fma-x16.c",
- "src/f32-sigmoid/gen/neonfma-rr1-p5-nr2fma-x20.c",
- "src/f32-sigmoid/gen/neonfma-rr1-p5-nr2fma-x24.c",
- "src/f32-sigmoid/gen/neonfma-rr1-p5-nr2recps-x4.c",
- "src/f32-sigmoid/gen/neonfma-rr1-p5-nr2recps-x8.c",
- "src/f32-sigmoid/gen/neonfma-rr1-p5-nr2recps-x12.c",
- "src/f32-sigmoid/gen/neonfma-rr1-p5-nr2recps-x16.c",
- "src/f32-sigmoid/gen/neonfma-rr1-p5-nr2recps-x20.c",
- "src/f32-sigmoid/gen/neonfma-rr1-p5-nr2recps-x24.c",
+ "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-lut64-p2-x4.c",
+ "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-lut64-p2-x8-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-lut64-p2-x8.c",
+ "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-lut64-p2-x12-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-lut64-p2-x12-acc3.c",
+ "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-lut64-p2-x12.c",
+ "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-lut64-p2-x16-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-lut64-p2-x16-acc4.c",
+ "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-lut64-p2-x16.c",
+ "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-lut64-p2-x20-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-lut64-p2-x20-acc5.c",
+ "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-lut64-p2-x20.c",
+ "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-p5-x4.c",
+ "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-p5-x8-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-p5-x8.c",
+ "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-p5-x12-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-p5-x12-acc3.c",
+ "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-p5-x12.c",
+ "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-p5-x16-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-p5-x16-acc4.c",
+ "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-p5-x16.c",
+ "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-p5-x20-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-p5-x20-acc5.c",
+ "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-p5-x20.c",
"src/f32-spmm/gen/4x1-minmax-neonfma-pipelined.c",
"src/f32-spmm/gen/4x1-minmax-neonfma-x2.c",
"src/f32-spmm/gen/4x1-minmax-neonfma.c",
@@ -1107,6 +3907,60 @@
"src/f32-velu/gen/velu-neonfma-rr1-p6-x24.c",
"src/f32-vmulcaddc/gen/c4-minmax-neonfma-2x.c",
"src/f32-vmulcaddc/gen/c8-minmax-neonfma-2x.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-x4.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-x12.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-x20.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-x24.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2fma-x4.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2fma-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2fma-x12.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2fma-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2fma-x20.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2fma-x24.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2recps-x4.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2recps-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2recps-x12.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2recps-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2recps-x20.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2recps-x24.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-x4.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-x12.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-x20.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-x24.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-x4.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-x12.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-x20.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-x24.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-x4.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-x12.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-x20.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-x24.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr1recps1fma-x4.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr1recps1fma-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr1recps1fma-x12.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr1recps1fma-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr1recps1fma-x20.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr1recps1fma-x24.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2fma-x4.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2fma-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2fma-x12.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2fma-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2fma-x20.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2fma-x24.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2recps-x4.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2recps-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2recps-x12.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2recps-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2recps-x20.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2recps-x24.c",
"src/f32-vsqrt/gen/neonfma-nr1rsqrts1fma1adj-x4.c",
"src/f32-vsqrt/gen/neonfma-nr1rsqrts1fma1adj-x8.c",
"src/f32-vsqrt/gen/neonfma-nr1rsqrts1fma1adj-x12.c",
@@ -1159,7 +4013,28 @@
"src/math/sqrt-neonfma-nr3fma.c",
]
-AARCH64_NEONFMA_UKERNELS = [
+PROD_AARCH64_NEON_MICROKERNEL_SRCS = [
+ "src/f32-conv-hwc2chw/3x3s2p1c3x4-neonfma-2x2.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neonfma-3x4.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neonfma-2x4-acc2.c",
+ "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-4x4.c",
+ "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neonfma-1x4-acc2.c",
+ "src/f32-gemm/gen/1x8-minmax-neonfma-lane-ld64.c",
+ "src/f32-gemm/gen/4x2-minmax-neonfma-lane-ld64.c",
+ "src/f32-gemm/gen/6x8-minmax-neonfma-lane-ld64.c",
+ "src/f32-igemm/gen/1x8-minmax-neonfma-lane-ld64.c",
+ "src/f32-igemm/gen/4x2-minmax-neonfma-lane-ld64.c",
+ "src/f32-igemm/gen/6x8-minmax-neonfma-lane-ld64.c",
+ "src/f32-spmm/gen/32x2-minmax-neonfma.c",
+ "src/f32-spmm/gen/32x4-minmax-neonfma.c",
+ "src/f32-vbinary/gen/vdiv-minmax-neon-x8.c",
+ "src/f32-vbinary/gen/vdivc-minmax-neon-x8.c",
+ "src/f32-vbinary/gen/vrdivc-minmax-neon-x8.c",
+ "src/f32-vsqrt/gen/neon-sqrt-x4.c",
+ "src/x8-lut/gen/lut-neon-tbx128x4-x64.c",
+]
+
+ALL_AARCH64_NEON_MICROKERNEL_SRCS = [
"src/f32-conv-hwc/gen/3x3s2p0p1c3x4-neonfma-2x1.c",
"src/f32-conv-hwc/gen/3x3s2p0p1c3x4-neonfma-2x2.c",
"src/f32-conv-hwc/gen/3x3s2p0p1c3x8-neonfma-2x1.c",
@@ -1230,24 +4105,6 @@
"src/f32-igemm/gen/4x8-minmax-neonfma-lane-ld128.c",
"src/f32-igemm/gen/6x8-minmax-neonfma-lane-ld64.c",
"src/f32-igemm/gen/6x8-minmax-neonfma-lane-ld128.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut64-p2-div-x4.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut64-p2-div-x8.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut64-p2-div-x12.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut64-p2-div-x16.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut64-p2-div-x20.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut64-p2-div-x24.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut2048-p1-div-x4.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut2048-p1-div-x8.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut2048-p1-div-x12.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut2048-p1-div-x16.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut2048-p1-div-x20.c",
- "src/f32-sigmoid/gen/neonfma-rr1-lut2048-p1-div-x24.c",
- "src/f32-sigmoid/gen/neonfma-rr1-p5-div-x4.c",
- "src/f32-sigmoid/gen/neonfma-rr1-p5-div-x8.c",
- "src/f32-sigmoid/gen/neonfma-rr1-p5-div-x12.c",
- "src/f32-sigmoid/gen/neonfma-rr1-p5-div-x16.c",
- "src/f32-sigmoid/gen/neonfma-rr1-p5-div-x20.c",
- "src/f32-sigmoid/gen/neonfma-rr1-p5-div-x24.c",
"src/f32-spmm/gen/4x2-minmax-neonfma.c",
"src/f32-spmm/gen/4x4-minmax-neonfma.c",
"src/f32-spmm/gen/8x2-minmax-neonfma.c",
@@ -1264,6 +4121,24 @@
"src/f32-vbinary/gen/vdivc-minmax-neon-x8.c",
"src/f32-vbinary/gen/vrdivc-minmax-neon-x4.c",
"src/f32-vbinary/gen/vrdivc-minmax-neon-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-div-x4.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-div-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-div-x12.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-div-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-div-x20.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-div-x24.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-div-x4.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-div-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-div-x12.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-div-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-div-x20.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-div-x24.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-div-x4.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-div-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-div-x12.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-div-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-div-x20.c",
+ "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-div-x24.c",
"src/f32-vsqrt/gen/neon-sqrt-x4.c",
"src/f32-vsqrt/gen/neon-sqrt-x8.c",
"src/math/sigmoid-neonfma-rr1-lut64-p2-div.c",
@@ -1272,9 +4147,50 @@
"src/math/sigmoid-neonfma-rr2-lut64-p2-div.c",
"src/math/sigmoid-neonfma-rr2-lut2048-p1-div.c",
"src/math/sigmoid-neonfma-rr2-p5-div.c",
+ "src/x8-lut/gen/lut-neon-tbx128x4-x16.c",
+ "src/x8-lut/gen/lut-neon-tbx128x4-x32.c",
+ "src/x8-lut/gen/lut-neon-tbx128x4-x48.c",
+ "src/x8-lut/gen/lut-neon-tbx128x4-x64.c",
+ "src/x32-transpose/4x4-aarch64-tbl.c",
]
-NEONV8_UKERNELS = [
+PROD_NEONV8_MICROKERNEL_SRCS = [
+ "src/f32-qs8-vcvt/gen/vcvt-neonv8-x32.c",
+ "src/f32-qu8-vcvt/gen/vcvt-neonv8-x32.c",
+ "src/f32-vrnd/gen/vrndd-neonv8-x8.c",
+ "src/f32-vrnd/gen/vrndne-neonv8-x8.c",
+ "src/f32-vrnd/gen/vrndu-neonv8-x8.c",
+ "src/f32-vrnd/gen/vrndz-neonv8-x8.c",
+ "src/qc8-dwconv/gen/up8x25-minmax-fp32-neonv8-mla8-ld64.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-neonv8-mla8-ld64.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-neonv8-mla8-ld64.c",
+ "src/qc8-gemm/gen/1x8-minmax-fp32-neonv8-mlal-lane-prfm.c",
+ "src/qc8-gemm/gen/1x8-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qc8-gemm/gen/1x8c2s4-minmax-fp32-neonv8-mlal.c",
+ "src/qc8-gemm/gen/1x8c8-minmax-fp32-neonv8-mlal.c",
+ "src/qc8-gemm/gen/1x16-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qc8-gemm/gen/2x8c2s4-minmax-fp32-neonv8-mlal.c",
+ "src/qc8-gemm/gen/2x8c8-minmax-fp32-neonv8-mlal.c",
+ "src/qc8-gemm/gen/4x16-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qc8-igemm/gen/1x8-minmax-fp32-neonv8-mlal-lane-prfm.c",
+ "src/qc8-igemm/gen/1x8-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qc8-igemm/gen/1x8c2s4-minmax-fp32-neonv8-mlal.c",
+ "src/qc8-igemm/gen/1x8c8-minmax-fp32-neonv8-mlal.c",
+ "src/qc8-igemm/gen/1x16-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qc8-igemm/gen/2x8c2s4-minmax-fp32-neonv8-mlal.c",
+ "src/qc8-igemm/gen/2x8c8-minmax-fp32-neonv8-mlal.c",
+ "src/qc8-igemm/gen/4x16-minmax-fp32-neonv8-mlal-lane.c",
+]
+
+ALL_NEONV8_MICROKERNEL_SRCS = [
+ "src/f32-qs8-vcvt/gen/vcvt-neonv8-x8.c",
+ "src/f32-qs8-vcvt/gen/vcvt-neonv8-x16.c",
+ "src/f32-qs8-vcvt/gen/vcvt-neonv8-x24.c",
+ "src/f32-qs8-vcvt/gen/vcvt-neonv8-x32.c",
+ "src/f32-qu8-vcvt/gen/vcvt-neonv8-x8.c",
+ "src/f32-qu8-vcvt/gen/vcvt-neonv8-x16.c",
+ "src/f32-qu8-vcvt/gen/vcvt-neonv8-x24.c",
+ "src/f32-qu8-vcvt/gen/vcvt-neonv8-x32.c",
"src/f32-vrnd/gen/vrndd-neonv8-x4.c",
"src/f32-vrnd/gen/vrndd-neonv8-x8.c",
"src/f32-vrnd/gen/vrndne-neonv8-x4.c",
@@ -1283,15 +4199,227 @@
"src/f32-vrnd/gen/vrndu-neonv8-x8.c",
"src/f32-vrnd/gen/vrndz-neonv8-x4.c",
"src/f32-vrnd/gen/vrndz-neonv8-x8.c",
+ "src/math/cvt-f32-qs8-neonv8.c",
+ "src/math/cvt-f32-qu8-neonv8.c",
"src/math/roundd-neonv8.c",
"src/math/roundne-neonv8.c",
"src/math/roundu-neonv8.c",
"src/math/roundz-neonv8.c",
+ "src/qc8-dwconv/gen/up8x9-minmax-fp32-neonv8-mla8-ld64.c",
+ "src/qc8-dwconv/gen/up8x9-minmax-fp32-neonv8-mul8-ld64.c",
+ "src/qc8-dwconv/gen/up8x9-minmax-fp32-neonv8-mul16.c",
+ "src/qc8-dwconv/gen/up8x25-minmax-fp32-neonv8-mla8-ld64.c",
+ "src/qc8-dwconv/gen/up8x25-minmax-fp32-neonv8-mul8-ld64.c",
+ "src/qc8-dwconv/gen/up8x25-minmax-fp32-neonv8-mul16.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-neonv8-mla8-ld64.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-neonv8-mla8-ld128.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-neonv8-mul8-ld64.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-neonv8-mul8-ld128.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-neonv8-mul16.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-neonv8-mla8-ld64.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-neonv8-mla8-ld128.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-neonv8-mul8-ld64.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-neonv8-mul8-ld128.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-neonv8-mul16.c",
+ "src/qc8-dwconv/gen/up24x9-minmax-fp32-neonv8-mul16.c",
+ "src/qc8-dwconv/gen/up24x25-minmax-fp32-neonv8-mul16.c",
+ "src/qc8-dwconv/gen/up32x9-minmax-fp32-neonv8-mul16.c",
+ "src/qc8-dwconv/gen/up32x25-minmax-fp32-neonv8-mul16.c",
+ "src/qc8-gemm/gen/1x8-minmax-fp32-neonv8-mlal-lane-prfm.c",
+ "src/qc8-gemm/gen/1x8-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qc8-gemm/gen/1x8c2-minmax-fp32-neonv8-mlal-dup.c",
+ "src/qc8-gemm/gen/1x8c2-minmax-fp32-neonv8-mlal-ld1r.c",
+ "src/qc8-gemm/gen/1x8c2-minmax-fp32-neonv8-mlal-ld2r.c",
+ "src/qc8-gemm/gen/1x8c2-minmax-fp32-neonv8-mlal-ld4r.c",
+ "src/qc8-gemm/gen/1x8c2s4-minmax-fp32-neonv8-mlal.c",
+ "src/qc8-gemm/gen/1x8c4-minmax-fp32-neonv8-mlal-dup.c",
+ "src/qc8-gemm/gen/1x8c4-minmax-fp32-neonv8-mlal-ld1r.c",
+ "src/qc8-gemm/gen/1x8c4-minmax-fp32-neonv8-mlal-ld2r.c",
+ "src/qc8-gemm/gen/1x8c4s2-minmax-fp32-neonv8-mlal.c",
+ "src/qc8-gemm/gen/1x8c8-minmax-fp32-neonv8-mlal.c",
+ "src/qc8-gemm/gen/1x16-minmax-fp32-neonv8-mlal-lane-prfm.c",
+ "src/qc8-gemm/gen/1x16-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qc8-gemm/gen/2x8-minmax-fp32-neonv8-mlal-lane-prfm.c",
+ "src/qc8-gemm/gen/2x8-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qc8-gemm/gen/2x8c2-minmax-fp32-neonv8-mlal-dup.c",
+ "src/qc8-gemm/gen/2x8c2-minmax-fp32-neonv8-mlal-ld1r.c",
+ "src/qc8-gemm/gen/2x8c2-minmax-fp32-neonv8-mlal-ld2r.c",
+ "src/qc8-gemm/gen/2x8c2-minmax-fp32-neonv8-mlal-ld4r.c",
+ "src/qc8-gemm/gen/2x8c2s4-minmax-fp32-neonv8-mlal.c",
+ "src/qc8-gemm/gen/2x8c4-minmax-fp32-neonv8-mlal-dup.c",
+ "src/qc8-gemm/gen/2x8c4-minmax-fp32-neonv8-mlal-ld1r.c",
+ "src/qc8-gemm/gen/2x8c4-minmax-fp32-neonv8-mlal-ld2r.c",
+ "src/qc8-gemm/gen/2x8c4s2-minmax-fp32-neonv8-mlal.c",
+ "src/qc8-gemm/gen/2x8c8-minmax-fp32-neonv8-mlal.c",
+ "src/qc8-gemm/gen/2x16-minmax-fp32-neonv8-mlal-lane-prfm.c",
+ "src/qc8-gemm/gen/2x16-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qc8-gemm/gen/3x8-minmax-fp32-neonv8-mlal-lane-prfm.c",
+ "src/qc8-gemm/gen/3x8-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qc8-gemm/gen/3x16-minmax-fp32-neonv8-mlal-lane-prfm.c",
+ "src/qc8-gemm/gen/3x16-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qc8-gemm/gen/4x8-minmax-fp32-neonv8-mlal-lane-prfm.c",
+ "src/qc8-gemm/gen/4x8-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qc8-gemm/gen/4x16-minmax-fp32-neonv8-mlal-lane-prfm.c",
+ "src/qc8-gemm/gen/4x16-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qc8-gemm/gen/6x8-minmax-fp32-neonv8-mlal-lane-prfm.c",
+ "src/qc8-gemm/gen/6x8-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qc8-gemm/gen/6x16-minmax-fp32-neonv8-mlal-lane-prfm.c",
+ "src/qc8-gemm/gen/6x16-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qc8-igemm/gen/1x8-minmax-fp32-neonv8-mlal-lane-prfm.c",
+ "src/qc8-igemm/gen/1x8-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qc8-igemm/gen/1x8c2-minmax-fp32-neonv8-mlal-dup.c",
+ "src/qc8-igemm/gen/1x8c2-minmax-fp32-neonv8-mlal-ld1r.c",
+ "src/qc8-igemm/gen/1x8c2-minmax-fp32-neonv8-mlal-ld2r.c",
+ "src/qc8-igemm/gen/1x8c2-minmax-fp32-neonv8-mlal-ld4r.c",
+ "src/qc8-igemm/gen/1x8c2s4-minmax-fp32-neonv8-mlal.c",
+ "src/qc8-igemm/gen/1x8c4-minmax-fp32-neonv8-mlal-dup.c",
+ "src/qc8-igemm/gen/1x8c4-minmax-fp32-neonv8-mlal-ld1r.c",
+ "src/qc8-igemm/gen/1x8c4-minmax-fp32-neonv8-mlal-ld2r.c",
+ "src/qc8-igemm/gen/1x8c4s2-minmax-fp32-neonv8-mlal.c",
+ "src/qc8-igemm/gen/1x8c8-minmax-fp32-neonv8-mlal.c",
+ "src/qc8-igemm/gen/1x16-minmax-fp32-neonv8-mlal-lane-prfm.c",
+ "src/qc8-igemm/gen/1x16-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qc8-igemm/gen/2x8-minmax-fp32-neonv8-mlal-lane-prfm.c",
+ "src/qc8-igemm/gen/2x8-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qc8-igemm/gen/2x8c2-minmax-fp32-neonv8-mlal-dup.c",
+ "src/qc8-igemm/gen/2x8c2-minmax-fp32-neonv8-mlal-ld1r.c",
+ "src/qc8-igemm/gen/2x8c2-minmax-fp32-neonv8-mlal-ld2r.c",
+ "src/qc8-igemm/gen/2x8c2-minmax-fp32-neonv8-mlal-ld4r.c",
+ "src/qc8-igemm/gen/2x8c2s4-minmax-fp32-neonv8-mlal.c",
+ "src/qc8-igemm/gen/2x8c4-minmax-fp32-neonv8-mlal-dup.c",
+ "src/qc8-igemm/gen/2x8c4-minmax-fp32-neonv8-mlal-ld1r.c",
+ "src/qc8-igemm/gen/2x8c4-minmax-fp32-neonv8-mlal-ld2r.c",
+ "src/qc8-igemm/gen/2x8c4s2-minmax-fp32-neonv8-mlal.c",
+ "src/qc8-igemm/gen/2x8c8-minmax-fp32-neonv8-mlal.c",
+ "src/qc8-igemm/gen/2x16-minmax-fp32-neonv8-mlal-lane-prfm.c",
+ "src/qc8-igemm/gen/2x16-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qc8-igemm/gen/3x8-minmax-fp32-neonv8-mlal-lane-prfm.c",
+ "src/qc8-igemm/gen/3x8-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qc8-igemm/gen/3x16-minmax-fp32-neonv8-mlal-lane-prfm.c",
+ "src/qc8-igemm/gen/3x16-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qc8-igemm/gen/4x8-minmax-fp32-neonv8-mlal-lane-prfm.c",
+ "src/qc8-igemm/gen/4x8-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qc8-igemm/gen/4x16-minmax-fp32-neonv8-mlal-lane-prfm.c",
+ "src/qc8-igemm/gen/4x16-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qc8-igemm/gen/6x8-minmax-fp32-neonv8-mlal-lane-prfm.c",
+ "src/qc8-igemm/gen/6x8-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qc8-igemm/gen/6x16-minmax-fp32-neonv8-mlal-lane-prfm.c",
+ "src/qc8-igemm/gen/6x16-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qs8-dwconv/gen/up8x9-minmax-fp32-neonv8-mul16.c",
+ "src/qs8-dwconv/gen/up8x25-minmax-fp32-neonv8-mul16.c",
+ "src/qs8-dwconv/gen/up16x9-minmax-fp32-neonv8-mul16.c",
+ "src/qs8-dwconv/gen/up16x25-minmax-fp32-neonv8-mul16.c",
+ "src/qs8-dwconv/gen/up24x9-minmax-fp32-neonv8-mul16.c",
+ "src/qs8-dwconv/gen/up24x25-minmax-fp32-neonv8-mul16.c",
+ "src/qs8-dwconv/gen/up32x9-minmax-fp32-neonv8-mul16.c",
+ "src/qs8-dwconv/gen/up32x25-minmax-fp32-neonv8-mul16.c",
+ "src/qs8-gavgpool/gen/7p7x-minmax-fp32-neonv8-c8.c",
+ "src/qs8-gavgpool/gen/7p7x-minmax-fp32-neonv8-c16.c",
+ "src/qs8-gavgpool/gen/7p7x-minmax-fp32-neonv8-c24.c",
+ "src/qs8-gavgpool/gen/7p7x-minmax-fp32-neonv8-c32.c",
+ "src/qs8-gavgpool/gen/7x-minmax-fp32-neonv8-c8.c",
+ "src/qs8-gavgpool/gen/7x-minmax-fp32-neonv8-c16.c",
+ "src/qs8-gavgpool/gen/7x-minmax-fp32-neonv8-c24.c",
+ "src/qs8-gavgpool/gen/7x-minmax-fp32-neonv8-c32.c",
+ "src/qs8-gemm/gen/1x8c2-minmax-fp32-neonv8-mlal-dup.c",
+ "src/qs8-gemm/gen/1x8c2-minmax-fp32-neonv8-mlal-ld1r.c",
+ "src/qs8-gemm/gen/1x8c2-minmax-fp32-neonv8-mlal-ld2r.c",
+ "src/qs8-gemm/gen/1x8c2-minmax-fp32-neonv8-mlal-ld4r.c",
+ "src/qs8-gemm/gen/1x8c2s4-minmax-fp32-neonv8-mlal.c",
+ "src/qs8-gemm/gen/1x8c4-minmax-fp32-neonv8-mlal-dup.c",
+ "src/qs8-gemm/gen/1x8c4-minmax-fp32-neonv8-mlal-ld1r.c",
+ "src/qs8-gemm/gen/1x8c4-minmax-fp32-neonv8-mlal-ld2r.c",
+ "src/qs8-gemm/gen/1x8c4s2-minmax-fp32-neonv8-mlal.c",
+ "src/qs8-gemm/gen/1x8c8-minmax-fp32-neonv8-mlal.c",
+ "src/qs8-gemm/gen/1x16-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qs8-gemm/gen/2x8c2-minmax-fp32-neonv8-mlal-dup.c",
+ "src/qs8-gemm/gen/2x8c2-minmax-fp32-neonv8-mlal-ld1r.c",
+ "src/qs8-gemm/gen/2x8c2-minmax-fp32-neonv8-mlal-ld2r.c",
+ "src/qs8-gemm/gen/2x8c2-minmax-fp32-neonv8-mlal-ld4r.c",
+ "src/qs8-gemm/gen/2x8c2s4-minmax-fp32-neonv8-mlal.c",
+ "src/qs8-gemm/gen/2x8c4-minmax-fp32-neonv8-mlal-dup.c",
+ "src/qs8-gemm/gen/2x8c4-minmax-fp32-neonv8-mlal-ld1r.c",
+ "src/qs8-gemm/gen/2x8c4-minmax-fp32-neonv8-mlal-ld2r.c",
+ "src/qs8-gemm/gen/2x8c4s2-minmax-fp32-neonv8-mlal.c",
+ "src/qs8-gemm/gen/2x8c8-minmax-fp32-neonv8-mlal.c",
+ "src/qs8-gemm/gen/4x16-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qs8-igemm/gen/1x8c2-minmax-fp32-neonv8-mlal-dup.c",
+ "src/qs8-igemm/gen/1x8c2-minmax-fp32-neonv8-mlal-ld1r.c",
+ "src/qs8-igemm/gen/1x8c2-minmax-fp32-neonv8-mlal-ld2r.c",
+ "src/qs8-igemm/gen/1x8c2-minmax-fp32-neonv8-mlal-ld4r.c",
+ "src/qs8-igemm/gen/1x8c2s4-minmax-fp32-neonv8-mlal.c",
+ "src/qs8-igemm/gen/1x8c4-minmax-fp32-neonv8-mlal-dup.c",
+ "src/qs8-igemm/gen/1x8c4-minmax-fp32-neonv8-mlal-ld1r.c",
+ "src/qs8-igemm/gen/1x8c4-minmax-fp32-neonv8-mlal-ld2r.c",
+ "src/qs8-igemm/gen/1x8c4s2-minmax-fp32-neonv8-mlal.c",
+ "src/qs8-igemm/gen/1x8c8-minmax-fp32-neonv8-mlal.c",
+ "src/qs8-igemm/gen/1x16-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qs8-igemm/gen/2x8c2-minmax-fp32-neonv8-mlal-dup.c",
+ "src/qs8-igemm/gen/2x8c2-minmax-fp32-neonv8-mlal-ld1r.c",
+ "src/qs8-igemm/gen/2x8c2-minmax-fp32-neonv8-mlal-ld2r.c",
+ "src/qs8-igemm/gen/2x8c2-minmax-fp32-neonv8-mlal-ld4r.c",
+ "src/qs8-igemm/gen/2x8c2s4-minmax-fp32-neonv8-mlal.c",
+ "src/qs8-igemm/gen/2x8c4-minmax-fp32-neonv8-mlal-dup.c",
+ "src/qs8-igemm/gen/2x8c4-minmax-fp32-neonv8-mlal-ld1r.c",
+ "src/qs8-igemm/gen/2x8c4-minmax-fp32-neonv8-mlal-ld2r.c",
+ "src/qs8-igemm/gen/2x8c4s2-minmax-fp32-neonv8-mlal.c",
+ "src/qs8-igemm/gen/2x8c8-minmax-fp32-neonv8-mlal.c",
+ "src/qs8-igemm/gen/4x16-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qs8-vmul/gen/minmax-fp32-neonv8-ld64-x8.c",
+ "src/qs8-vmul/gen/minmax-fp32-neonv8-ld64-x16.c",
+ "src/qs8-vmul/gen/minmax-fp32-neonv8-ld128-x16.c",
+ "src/qs8-vmulc/gen/minmax-fp32-neonv8-ld64-x8.c",
+ "src/qs8-vmulc/gen/minmax-fp32-neonv8-ld64-x16.c",
+ "src/qs8-vmulc/gen/minmax-fp32-neonv8-ld128-x16.c",
+ "src/qu8-dwconv/gen/up8x9-minmax-fp32-neonv8-mul16.c",
+ "src/qu8-dwconv/gen/up8x25-minmax-fp32-neonv8-mul16.c",
+ "src/qu8-dwconv/gen/up16x9-minmax-fp32-neonv8-mul16.c",
+ "src/qu8-dwconv/gen/up16x25-minmax-fp32-neonv8-mul16.c",
+ "src/qu8-dwconv/gen/up24x9-minmax-fp32-neonv8-mul16.c",
+ "src/qu8-dwconv/gen/up24x25-minmax-fp32-neonv8-mul16.c",
+ "src/qu8-dwconv/gen/up32x9-minmax-fp32-neonv8-mul16.c",
+ "src/qu8-dwconv/gen/up32x25-minmax-fp32-neonv8-mul16.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-neonv8-c8.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-neonv8-c16.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-neonv8-c24.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-neonv8-c32.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-neonv8-c8.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-neonv8-c16.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-neonv8-c24.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-neonv8-c32.c",
+ "src/qu8-gemm/gen/1x16-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qu8-gemm/gen/4x16-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qu8-igemm/gen/1x16-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qu8-igemm/gen/4x16-minmax-fp32-neonv8-mlal-lane.c",
+ "src/qu8-vmul/gen/minmax-fp32-neonv8-ld64-x8.c",
+ "src/qu8-vmul/gen/minmax-fp32-neonv8-ld64-x16.c",
+ "src/qu8-vmul/gen/minmax-fp32-neonv8-ld128-x16.c",
+ "src/qu8-vmulc/gen/minmax-fp32-neonv8-ld64-x8.c",
+ "src/qu8-vmulc/gen/minmax-fp32-neonv8-ld64-x16.c",
+ "src/qu8-vmulc/gen/minmax-fp32-neonv8-ld128-x16.c",
]
-AARCH64_NEONFP16ARITH_UKERNELS = [
- "src/f16-clamp/gen/neonfp16arith-x8.c",
- "src/f16-clamp/gen/neonfp16arith-x16.c",
+PROD_AARCH64_NEONFP16ARITH_MICROKERNEL_SRCS = [
+ "src/f16-dwconv/gen/up8x25-minmax-neonfp16arith-acc2.c",
+ "src/f16-dwconv/gen/up16x4-minmax-neonfp16arith.c",
+ "src/f16-dwconv/gen/up16x9-minmax-neonfp16arith.c",
+ "src/f16-gavgpool/gen/7p7x-minmax-neonfp16arith-c8.c",
+ "src/f16-gavgpool/gen/7x-minmax-neonfp16arith-c8.c",
+ "src/f16-gemm/gen/1x16-minmax-neonfp16arith-ld64.c",
+ "src/f16-gemm/gen/6x16-minmax-neonfp16arith-ld64.c",
+ "src/f16-igemm/gen/1x16-minmax-neonfp16arith-ld64.c",
+ "src/f16-igemm/gen/6x16-minmax-neonfp16arith-ld64.c",
+ "src/f16-maxpool/9p8x-minmax-neonfp16arith-c8.c",
+ "src/f16-prelu/gen/neonfp16arith-2x16.c",
+ "src/f16-vbinary/gen/vadd-minmax-neonfp16arith-x16.c",
+ "src/f16-vbinary/gen/vaddc-minmax-neonfp16arith-x16.c",
+ "src/f16-vbinary/gen/vmul-minmax-neonfp16arith-x16.c",
+ "src/f16-vbinary/gen/vmulc-minmax-neonfp16arith-x16.c",
+ "src/f16-vhswish/gen/vhswish-neonfp16arith-x16.c",
+ "src/f16-vmulcaddc/gen/c8-minmax-neonfp16arith-2x.c",
+]
+
+ALL_AARCH64_NEONFP16ARITH_MICROKERNEL_SRCS = [
"src/f16-dwconv/gen/up8x4-minmax-neonfp16arith-acc2.c",
"src/f16-dwconv/gen/up8x4-minmax-neonfp16arith.c",
"src/f16-dwconv/gen/up8x9-minmax-neonfp16arith-acc2.c",
@@ -1304,8 +4432,20 @@
"src/f16-dwconv/gen/up16x9-minmax-neonfp16arith.c",
"src/f16-dwconv/gen/up16x25-minmax-neonfp16arith-acc2.c",
"src/f16-dwconv/gen/up16x25-minmax-neonfp16arith.c",
- "src/f16-gavgpool/7p7x-minmax-neonfp16arith-c8.c",
- "src/f16-gavgpool/7x-minmax-neonfp16arith-c8.c",
+ "src/f16-dwconv/gen/up32x4-minmax-neonfp16arith-acc2.c",
+ "src/f16-dwconv/gen/up32x4-minmax-neonfp16arith.c",
+ "src/f16-dwconv/gen/up32x9-minmax-neonfp16arith-acc2.c",
+ "src/f16-dwconv/gen/up32x9-minmax-neonfp16arith.c",
+ "src/f16-dwconv/gen/up32x25-minmax-neonfp16arith-acc2.c",
+ "src/f16-dwconv/gen/up32x25-minmax-neonfp16arith.c",
+ "src/f16-gavgpool/gen/7p7x-minmax-neonfp16arith-c8.c",
+ "src/f16-gavgpool/gen/7p7x-minmax-neonfp16arith-c16.c",
+ "src/f16-gavgpool/gen/7p7x-minmax-neonfp16arith-c24.c",
+ "src/f16-gavgpool/gen/7p7x-minmax-neonfp16arith-c32.c",
+ "src/f16-gavgpool/gen/7x-minmax-neonfp16arith-c8.c",
+ "src/f16-gavgpool/gen/7x-minmax-neonfp16arith-c16.c",
+ "src/f16-gavgpool/gen/7x-minmax-neonfp16arith-c24.c",
+ "src/f16-gavgpool/gen/7x-minmax-neonfp16arith-c32.c",
"src/f16-gemm/gen-inc/1x8inc-minmax-neonfp16arith-ld64.c",
"src/f16-gemm/gen-inc/1x16inc-minmax-neonfp16arith-ld64.c",
"src/f16-gemm/gen-inc/4x8inc-minmax-neonfp16arith-ld64.c",
@@ -1322,8 +4462,6 @@
"src/f16-gemm/gen/6x16-minmax-neonfp16arith-ld64.c",
"src/f16-gemm/gen/8x8-minmax-neonfp16arith-ld64.c",
"src/f16-gemm/gen/8x16-minmax-neonfp16arith-ld64.c",
- "src/f16-hswish/gen/hswish-neonfp16arith-x8.c",
- "src/f16-hswish/gen/hswish-neonfp16arith-x16.c",
"src/f16-igemm/gen/1x8-minmax-neonfp16arith-ld64.c",
"src/f16-igemm/gen/1x16-minmax-neonfp16arith-ld64.c",
"src/f16-igemm/gen/4x8-minmax-neonfp16arith-ld64.c",
@@ -1332,10 +4470,9 @@
"src/f16-igemm/gen/6x16-minmax-neonfp16arith-ld64.c",
"src/f16-igemm/gen/8x8-minmax-neonfp16arith-ld64.c",
"src/f16-igemm/gen/8x16-minmax-neonfp16arith-ld64.c",
+ "src/f16-maxpool/9p8x-minmax-neonfp16arith-c8.c",
"src/f16-prelu/gen/neonfp16arith-2x8.c",
"src/f16-prelu/gen/neonfp16arith-2x16.c",
- "src/f16-relu/gen/neonfp16arith-x8.c",
- "src/f16-relu/gen/neonfp16arith-x16.c",
"src/f16-spmm/gen/8x1-minmax-neonfp16arith-x2.c",
"src/f16-spmm/gen/8x1-minmax-neonfp16arith.c",
"src/f16-spmm/gen/16x1-minmax-neonfp16arith-x2.c",
@@ -1372,42 +4509,188 @@
"src/f16-vbinary/gen/vsub-minmax-neonfp16arith-x16.c",
"src/f16-vbinary/gen/vsubc-minmax-neonfp16arith-x8.c",
"src/f16-vbinary/gen/vsubc-minmax-neonfp16arith-x16.c",
+ "src/f16-vclamp/gen/vclamp-neonfp16arith-x8.c",
+ "src/f16-vclamp/gen/vclamp-neonfp16arith-x16.c",
+ "src/f16-vhswish/gen/vhswish-neonfp16arith-x8.c",
+ "src/f16-vhswish/gen/vhswish-neonfp16arith-x16.c",
"src/f16-vmulcaddc/gen/c8-minmax-neonfp16arith-2x.c",
"src/f16-vmulcaddc/gen/c16-minmax-neonfp16arith-2x.c",
]
-NEONDOT_UKERNELS = [
- "src/qs8-gemm/gen/1x8c4-minmax-neondot.c",
- "src/qs8-gemm/gen/1x16c4-minmax-neondot.c",
- "src/qs8-gemm/gen/4x8c4-minmax-neondot.c",
- "src/qs8-gemm/gen/4x16c4-minmax-neondot.c",
- "src/qs8-gemm/gen/6x8c4-minmax-neondot.c",
- "src/qs8-gemm/gen/6x16c4-minmax-neondot.c",
- "src/qs8-gemm/gen/8x8c4-minmax-neondot.c",
- "src/qs8-gemm/gen/8x16c4-minmax-neondot.c",
- "src/qs8-igemm/gen/1x8c4-minmax-neondot.c",
- "src/qs8-igemm/gen/1x16c4-minmax-neondot.c",
- "src/qs8-igemm/gen/4x8c4-minmax-neondot.c",
- "src/qs8-igemm/gen/4x16c4-minmax-neondot.c",
- "src/qs8-igemm/gen/6x8c4-minmax-neondot.c",
- "src/qs8-igemm/gen/6x16c4-minmax-neondot.c",
- "src/qs8-igemm/gen/8x8c4-minmax-neondot.c",
- "src/qs8-igemm/gen/8x16c4-minmax-neondot.c",
+PROD_NEONDOT_MICROKERNEL_SRCS = [
+ "src/qc8-gemm/gen/1x8c4-minmax-fp32-neondot.c",
+ "src/qc8-gemm/gen/1x16c4-minmax-fp32-neondot.c",
+ "src/qc8-gemm/gen/4x8c4-minmax-fp32-neondot.c",
+ "src/qc8-gemm/gen/4x16c4-minmax-fp32-neondot.c",
+ "src/qc8-igemm/gen/1x8c4-minmax-fp32-neondot.c",
+ "src/qc8-igemm/gen/1x16c4-minmax-fp32-neondot.c",
+ "src/qc8-igemm/gen/4x8c4-minmax-fp32-neondot.c",
+ "src/qc8-igemm/gen/4x16c4-minmax-fp32-neondot.c",
+ "src/qs8-gemm/gen/1x8c4-minmax-rndnu-neondot.c",
+ "src/qs8-gemm/gen/1x16c4-minmax-rndnu-neondot.c",
+ "src/qs8-gemm/gen/4x8c4-minmax-rndnu-neondot.c",
+ "src/qs8-gemm/gen/4x16c4-minmax-rndnu-neondot.c",
+ "src/qs8-igemm/gen/1x8c4-minmax-rndnu-neondot.c",
+ "src/qs8-igemm/gen/1x16c4-minmax-rndnu-neondot.c",
+ "src/qs8-igemm/gen/4x8c4-minmax-rndnu-neondot.c",
+ "src/qs8-igemm/gen/4x16c4-minmax-rndnu-neondot.c",
+ "src/qu8-gemm/gen/1x8c4-minmax-rndnu-neondot.c",
+ "src/qu8-gemm/gen/1x16c4-minmax-rndnu-neondot.c",
+ "src/qu8-gemm/gen/4x8c4-minmax-rndnu-neondot.c",
+ "src/qu8-gemm/gen/4x16c4-minmax-rndnu-neondot.c",
+ "src/qu8-igemm/gen/1x8c4-minmax-rndnu-neondot.c",
+ "src/qu8-igemm/gen/1x16c4-minmax-rndnu-neondot.c",
+ "src/qu8-igemm/gen/4x8c4-minmax-rndnu-neondot.c",
+ "src/qu8-igemm/gen/4x16c4-minmax-rndnu-neondot.c",
]
-SSE_UKERNELS = [
+ALL_NEONDOT_MICROKERNEL_SRCS = [
+ "src/qc8-gemm/gen/1x8c4-minmax-fp32-neondot.c",
+ "src/qc8-gemm/gen/1x16c4-minmax-fp32-neondot.c",
+ "src/qc8-gemm/gen/4x8c4-minmax-fp32-neondot.c",
+ "src/qc8-gemm/gen/4x16c4-minmax-fp32-neondot.c",
+ "src/qc8-gemm/gen/6x8c4-minmax-fp32-neondot.c",
+ "src/qc8-gemm/gen/6x16c4-minmax-fp32-neondot.c",
+ "src/qc8-gemm/gen/8x8c4-minmax-fp32-neondot.c",
+ "src/qc8-gemm/gen/8x16c4-minmax-fp32-neondot.c",
+ "src/qc8-igemm/gen/1x8c4-minmax-fp32-neondot.c",
+ "src/qc8-igemm/gen/1x16c4-minmax-fp32-neondot.c",
+ "src/qc8-igemm/gen/4x8c4-minmax-fp32-neondot.c",
+ "src/qc8-igemm/gen/4x16c4-minmax-fp32-neondot.c",
+ "src/qc8-igemm/gen/6x8c4-minmax-fp32-neondot.c",
+ "src/qc8-igemm/gen/6x16c4-minmax-fp32-neondot.c",
+ "src/qc8-igemm/gen/8x8c4-minmax-fp32-neondot.c",
+ "src/qc8-igemm/gen/8x16c4-minmax-fp32-neondot.c",
+ "src/qs8-gemm/gen/1x8c4-minmax-fp32-neondot.c",
+ "src/qs8-gemm/gen/1x8c4-minmax-rndnu-neondot.c",
+ "src/qs8-gemm/gen/1x16c4-minmax-rndnu-neondot.c",
+ "src/qs8-gemm/gen/4x8c4-minmax-rndnu-neondot.c",
+ "src/qs8-gemm/gen/4x16c4-minmax-rndnu-neondot.c",
+ "src/qs8-gemm/gen/6x8c4-minmax-rndnu-neondot.c",
+ "src/qs8-gemm/gen/6x16c4-minmax-rndnu-neondot.c",
+ "src/qs8-gemm/gen/8x8c4-minmax-rndnu-neondot.c",
+ "src/qs8-gemm/gen/8x16c4-minmax-rndnu-neondot.c",
+ "src/qs8-igemm/gen/1x8c4-minmax-fp32-neondot.c",
+ "src/qs8-igemm/gen/1x8c4-minmax-rndnu-neondot.c",
+ "src/qs8-igemm/gen/1x16c4-minmax-rndnu-neondot.c",
+ "src/qs8-igemm/gen/4x8c4-minmax-rndnu-neondot.c",
+ "src/qs8-igemm/gen/4x16c4-minmax-rndnu-neondot.c",
+ "src/qs8-igemm/gen/6x8c4-minmax-rndnu-neondot.c",
+ "src/qs8-igemm/gen/6x16c4-minmax-rndnu-neondot.c",
+ "src/qs8-igemm/gen/8x8c4-minmax-rndnu-neondot.c",
+ "src/qs8-igemm/gen/8x16c4-minmax-rndnu-neondot.c",
+ "src/qu8-gemm/gen/1x8c4-minmax-rndnu-neondot.c",
+ "src/qu8-gemm/gen/1x16c4-minmax-fp32-neondot.c",
+ "src/qu8-gemm/gen/1x16c4-minmax-rndnu-neondot.c",
+ "src/qu8-gemm/gen/1x32c4-minmax-rndnu-neondot.c",
+ "src/qu8-gemm/gen/2x8c4-minmax-rndnu-neondot.c",
+ "src/qu8-gemm/gen/2x16c4-minmax-fp32-neondot.c",
+ "src/qu8-gemm/gen/2x16c4-minmax-rndnu-neondot.c",
+ "src/qu8-gemm/gen/2x32c4-minmax-rndnu-neondot.c",
+ "src/qu8-gemm/gen/3x8c4-minmax-rndnu-neondot.c",
+ "src/qu8-gemm/gen/3x16c4-minmax-rndnu-neondot.c",
+ "src/qu8-gemm/gen/3x32c4-minmax-rndnu-neondot.c",
+ "src/qu8-gemm/gen/4x8c4-minmax-rndnu-neondot.c",
+ "src/qu8-gemm/gen/4x16c4-minmax-fp32-neondot.c",
+ "src/qu8-gemm/gen/4x16c4-minmax-rndnu-neondot.c",
+ "src/qu8-gemm/gen/5x8c4-minmax-rndnu-neondot.c",
+ "src/qu8-gemm/gen/5x16c4-minmax-rndnu-neondot.c",
+ "src/qu8-gemm/gen/6x8c4-minmax-rndnu-neondot.c",
+ "src/qu8-gemm/gen/6x16c4-minmax-rndnu-neondot.c",
+ "src/qu8-gemm/gen/8x8c4-minmax-rndnu-neondot.c",
+ "src/qu8-gemm/gen/8x16c4-minmax-rndnu-neondot.c",
+ "src/qu8-igemm/gen/1x8c4-minmax-rndnu-neondot.c",
+ "src/qu8-igemm/gen/1x16c4-minmax-fp32-neondot.c",
+ "src/qu8-igemm/gen/1x16c4-minmax-rndnu-neondot.c",
+ "src/qu8-igemm/gen/1x32c4-minmax-rndnu-neondot.c",
+ "src/qu8-igemm/gen/2x8c4-minmax-rndnu-neondot.c",
+ "src/qu8-igemm/gen/2x16c4-minmax-fp32-neondot.c",
+ "src/qu8-igemm/gen/2x16c4-minmax-rndnu-neondot.c",
+ "src/qu8-igemm/gen/2x32c4-minmax-rndnu-neondot.c",
+ "src/qu8-igemm/gen/3x8c4-minmax-rndnu-neondot.c",
+ "src/qu8-igemm/gen/3x16c4-minmax-rndnu-neondot.c",
+ "src/qu8-igemm/gen/3x32c4-minmax-rndnu-neondot.c",
+ "src/qu8-igemm/gen/4x8c4-minmax-rndnu-neondot.c",
+ "src/qu8-igemm/gen/4x16c4-minmax-fp32-neondot.c",
+ "src/qu8-igemm/gen/4x16c4-minmax-rndnu-neondot.c",
+ "src/qu8-igemm/gen/5x8c4-minmax-rndnu-neondot.c",
+ "src/qu8-igemm/gen/5x16c4-minmax-rndnu-neondot.c",
+ "src/qu8-igemm/gen/6x8c4-minmax-rndnu-neondot.c",
+ "src/qu8-igemm/gen/6x16c4-minmax-rndnu-neondot.c",
+ "src/qu8-igemm/gen/8x8c4-minmax-rndnu-neondot.c",
+ "src/qu8-igemm/gen/8x16c4-minmax-rndnu-neondot.c",
+]
+
+PROD_SSE_MICROKERNEL_SRCS = [
"src/f32-avgpool/9p8x-minmax-sse-c4.c",
"src/f32-avgpool/9x-minmax-sse-c4.c",
- "src/f32-clamp/gen/sse-x4.c",
- "src/f32-clamp/gen/sse-x8.c",
+ "src/f32-conv-hwc2chw/3x3s2p1c3x4-sse-2x2.c",
+ "src/f32-dwconv/gen/up8x3-minmax-sse.c",
+ "src/f32-dwconv/gen/up8x4-minmax-sse.c",
+ "src/f32-dwconv/gen/up8x9-minmax-sse.c",
+ "src/f32-dwconv/gen/up8x25-minmax-sse.c",
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-sse-2x4-acc2.c",
+ "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-sse-1x4-acc3.c",
+ "src/f32-dwconv2d-chw/gen/5x5p2-minmax-sse-4x4.c",
+ "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-sse-2x4.c",
+ "src/f32-gavgpool-cw/sse-x4.c",
+ "src/f32-gavgpool/7p7x-minmax-sse-c4.c",
+ "src/f32-gavgpool/7x-minmax-sse-c4.c",
+ "src/f32-gemm/gen/1x8-minmax-sse-load1.c",
+ "src/f32-gemm/gen/4x2c4-minmax-sse.c",
+ "src/f32-gemm/gen/4x8-minmax-sse-load1.c",
+ "src/f32-ibilinear-chw/gen/sse-p8.c",
+ "src/f32-ibilinear/gen/sse-c8.c",
+ "src/f32-igemm/gen/1x8-minmax-sse-load1.c",
+ "src/f32-igemm/gen/4x2c4-minmax-sse.c",
+ "src/f32-igemm/gen/4x8-minmax-sse-load1.c",
+ "src/f32-maxpool/9p8x-minmax-sse-c4.c",
+ "src/f32-pavgpool/9p8x-minmax-sse-c4.c",
+ "src/f32-pavgpool/9x-minmax-sse-c4.c",
+ "src/f32-rmax/sse.c",
+ "src/f32-spmm/gen/32x1-minmax-sse.c",
+ "src/f32-vbinary/gen/vadd-minmax-sse-x8.c",
+ "src/f32-vbinary/gen/vaddc-minmax-sse-x8.c",
+ "src/f32-vbinary/gen/vdiv-minmax-sse-x8.c",
+ "src/f32-vbinary/gen/vdivc-minmax-sse-x8.c",
+ "src/f32-vbinary/gen/vmax-sse-x8.c",
+ "src/f32-vbinary/gen/vmaxc-sse-x8.c",
+ "src/f32-vbinary/gen/vmin-sse-x8.c",
+ "src/f32-vbinary/gen/vminc-sse-x8.c",
+ "src/f32-vbinary/gen/vmul-minmax-sse-x8.c",
+ "src/f32-vbinary/gen/vmulc-minmax-sse-x8.c",
+ "src/f32-vbinary/gen/vrdivc-minmax-sse-x8.c",
+ "src/f32-vbinary/gen/vrsubc-minmax-sse-x8.c",
+ "src/f32-vbinary/gen/vsqrdiff-sse-x8.c",
+ "src/f32-vbinary/gen/vsqrdiffc-sse-x8.c",
+ "src/f32-vbinary/gen/vsub-minmax-sse-x8.c",
+ "src/f32-vbinary/gen/vsubc-minmax-sse-x8.c",
+ "src/f32-vclamp/gen/vclamp-sse-x8.c",
+ "src/f32-vhswish/gen/vhswish-sse-x8.c",
+ "src/f32-vlrelu/gen/vlrelu-sse-x8.c",
+ "src/f32-vmulcaddc/gen/c4-minmax-sse-2x.c",
+ "src/f32-vsqrt/gen/sse-sqrt-x4.c",
+ "src/f32-vunary/gen/vabs-sse-x8.c",
+ "src/f32-vunary/gen/vneg-sse-x8.c",
+ "src/f32-vunary/gen/vsqr-sse-x8.c",
+ "src/x32-packx/x4-sse.c",
+]
+
+ALL_SSE_MICROKERNEL_SRCS = [
+ "src/f32-avgpool/9p8x-minmax-sse-c4.c",
+ "src/f32-avgpool/9x-minmax-sse-c4.c",
"src/f32-conv-hwc2chw/3x3s2p1c3x4-sse-1x1.c",
"src/f32-conv-hwc2chw/3x3s2p1c3x4-sse-2x2.c",
+ "src/f32-dwconv/gen/up4x3-minmax-sse-acc2.c",
+ "src/f32-dwconv/gen/up4x3-minmax-sse.c",
"src/f32-dwconv/gen/up4x4-minmax-sse-acc2.c",
"src/f32-dwconv/gen/up4x4-minmax-sse.c",
"src/f32-dwconv/gen/up4x9-minmax-sse-acc2.c",
"src/f32-dwconv/gen/up4x9-minmax-sse.c",
"src/f32-dwconv/gen/up4x25-minmax-sse-acc2.c",
"src/f32-dwconv/gen/up4x25-minmax-sse.c",
+ "src/f32-dwconv/gen/up8x3-minmax-sse-acc2.c",
+ "src/f32-dwconv/gen/up8x3-minmax-sse.c",
"src/f32-dwconv/gen/up8x4-minmax-sse-acc2.c",
"src/f32-dwconv/gen/up8x4-minmax-sse.c",
"src/f32-dwconv/gen/up8x9-minmax-sse-acc2.c",
@@ -1483,8 +4766,8 @@
"src/f32-gemm/gen/5x8-minmax-sse-dup.c",
"src/f32-gemm/gen/5x8-minmax-sse-load1.c",
"src/f32-gemm/gen/5x8s4-minmax-sse.c",
- "src/f32-hswish/gen/hswish-sse-x4.c",
- "src/f32-hswish/gen/hswish-sse-x8.c",
+ "src/f32-ibilinear-chw/gen/sse-p4.c",
+ "src/f32-ibilinear-chw/gen/sse-p8.c",
"src/f32-ibilinear/gen/sse-c4.c",
"src/f32-ibilinear/gen/sse-c8.c",
"src/f32-igemm/gen/1x8-minmax-sse-dup.c",
@@ -1506,8 +4789,6 @@
"src/f32-ppmm/gen/4x8-minmax-sse.c",
"src/f32-prelu/gen/sse-2x4.c",
"src/f32-prelu/gen/sse-2x8.c",
- "src/f32-relu/gen/sse-x4.c",
- "src/f32-relu/gen/sse-x8.c",
"src/f32-rmax/sse.c",
"src/f32-spmm/gen/4x1-minmax-sse.c",
"src/f32-spmm/gen/8x1-minmax-sse.c",
@@ -1545,10 +4826,16 @@
"src/f32-vbinary/gen/vsub-minmax-sse-x8.c",
"src/f32-vbinary/gen/vsubc-minmax-sse-x4.c",
"src/f32-vbinary/gen/vsubc-minmax-sse-x8.c",
+ "src/f32-vclamp/gen/vclamp-sse-x4.c",
+ "src/f32-vclamp/gen/vclamp-sse-x8.c",
+ "src/f32-vhswish/gen/vhswish-sse-x4.c",
+ "src/f32-vhswish/gen/vhswish-sse-x8.c",
"src/f32-vlrelu/gen/vlrelu-sse-x4.c",
"src/f32-vlrelu/gen/vlrelu-sse-x8.c",
"src/f32-vmulcaddc/gen/c4-minmax-sse-2x.c",
"src/f32-vmulcaddc/gen/c8-minmax-sse-2x.c",
+ "src/f32-vrelu/gen/vrelu-sse-x4.c",
+ "src/f32-vrelu/gen/vrelu-sse-x8.c",
"src/f32-vsqrt/gen/sse-sqrt-x4.c",
"src/f32-vsqrt/gen/sse-sqrt-x8.c",
"src/f32-vunary/gen/vabs-sse-x4.c",
@@ -1564,15 +4851,97 @@
"src/math/sqrt-sse-hh1mac.c",
"src/math/sqrt-sse-nr1mac.c",
"src/math/sqrt-sse-nr2mac.c",
- "src/x32-fill/sse.c",
"src/x32-packx/x4-sse.c",
- "src/x32-pad/sse.c",
+ "src/x32-transpose/4x4-sse.c",
]
-SSE2_UKERNELS = [
+PROD_SSE2_MICROKERNEL_SRCS = [
+ "src/f16-f32-vcvt/gen/vcvt-sse2-int16-x32.c",
"src/f32-argmaxpool/4x-sse2-c4.c",
"src/f32-argmaxpool/9p8x-sse2-c4.c",
"src/f32-argmaxpool/9x-sse2-c4.c",
+ "src/f32-f16-vcvt/gen/vcvt-sse2-x16.c",
+ "src/f32-prelu/gen/sse2-2x8.c",
+ "src/f32-qs8-vcvt/gen/vcvt-sse2-x32.c",
+ "src/f32-qu8-vcvt/gen/vcvt-sse2-x32.c",
+ "src/f32-raddstoreexpminusmax/gen/sse2-rr2-p5-x20-acc2.c",
+ "src/f32-velu/gen/velu-sse2-rr2-lut16-p3-x12.c",
+ "src/f32-vlrelu/gen/vlrelu-sse2-x8.c",
+ "src/f32-vrnd/gen/vrndd-sse2-x8.c",
+ "src/f32-vrnd/gen/vrndne-sse2-x8.c",
+ "src/f32-vrnd/gen/vrndu-sse2-x8.c",
+ "src/f32-vrnd/gen/vrndz-sse2-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-sse2-rr2-lut64-p2-div-x8.c",
+ "src/qc8-dwconv/gen/up8x9-minmax-fp32-sse2-mul16.c",
+ "src/qc8-dwconv/gen/up8x25-minmax-fp32-sse2-mul16.c",
+ "src/qc8-gemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qc8-gemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qc8-igemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qc8-igemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qs8-dwconv/gen/up8x9-minmax-fp32-sse2-mul16-add16.c",
+ "src/qs8-dwconv/gen/up8x25-minmax-fp32-sse2-mul16-add16.c",
+ "src/qs8-f32-vcvt/gen/vcvt-sse2-x32.c",
+ "src/qs8-gavgpool/gen/7p7x-minmax-fp32-sse2-c8.c",
+ "src/qs8-gavgpool/gen/7x-minmax-fp32-sse2-c8.c",
+ "src/qs8-gemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qs8-gemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qs8-igemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qs8-igemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qs8-vadd/gen/minmax-sse2-mul16-ld64-x8.c",
+ "src/qs8-vaddc/gen/minmax-sse2-mul16-ld64-x8.c",
+ "src/qs8-vmul/gen/minmax-fp32-sse2-mul16-ld64-x8.c",
+ "src/qs8-vmulc/gen/minmax-fp32-sse2-mul16-ld64-x8.c",
+ "src/qu8-avgpool/9p8x-minmax-sse2-c8.c",
+ "src/qu8-avgpool/9x-minmax-sse2-c8.c",
+ "src/qu8-dwconv/gen/up8x9-minmax-fp32-sse2-mul16.c",
+ "src/qu8-dwconv/gen/up8x25-minmax-fp32-sse2-mul16.c",
+ "src/qu8-f32-vcvt/gen/vcvt-sse2-x32.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-sse2-c8.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-sse2-c8.c",
+ "src/qu8-gemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qu8-gemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qu8-igemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qu8-igemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qu8-vadd/gen/minmax-sse2-mul16-ld64-x8.c",
+ "src/qu8-vaddc/gen/minmax-sse2-mul16-ld64-x8.c",
+ "src/qu8-vmul/gen/minmax-fp32-sse2-mul16-ld64-x8.c",
+ "src/qu8-vmulc/gen/minmax-fp32-sse2-mul16-ld64-x8.c",
+ "src/s8-ibilinear/gen/sse2-c8.c",
+ "src/s8-maxpool/9p8x-minmax-sse2-c16.c",
+ "src/s8-vclamp/sse2-x64.c",
+ "src/u8-ibilinear/gen/sse2-c8.c",
+ "src/u8-maxpool/9p8x-minmax-sse2-c16.c",
+ "src/u8-rmax/sse2.c",
+ "src/u8-vclamp/sse2-x64.c",
+ "src/x8-zip/x2-sse2.c",
+ "src/x8-zip/x3-sse2.c",
+ "src/x8-zip/x4-sse2.c",
+ "src/x8-zip/xm-sse2.c",
+ "src/x32-unpool/sse2.c",
+ "src/x32-zip/x2-sse2.c",
+ "src/x32-zip/x3-sse2.c",
+ "src/x32-zip/x4-sse2.c",
+ "src/x32-zip/xm-sse2.c",
+ "src/xx-fill/sse2-x64.c",
+ "src/xx-pad/sse2.c",
+]
+
+ALL_SSE2_MICROKERNEL_SRCS = [
+ "src/f16-f32-vcvt/gen/vcvt-sse2-int16-x8.c",
+ "src/f16-f32-vcvt/gen/vcvt-sse2-int16-x16.c",
+ "src/f16-f32-vcvt/gen/vcvt-sse2-int16-x24.c",
+ "src/f16-f32-vcvt/gen/vcvt-sse2-int16-x32.c",
+ "src/f16-f32-vcvt/gen/vcvt-sse2-int32-x8.c",
+ "src/f16-f32-vcvt/gen/vcvt-sse2-int32-x16.c",
+ "src/f16-f32-vcvt/gen/vcvt-sse2-int32-x24.c",
+ "src/f16-f32-vcvt/gen/vcvt-sse2-int32-x32.c",
+ "src/f32-argmaxpool/4x-sse2-c4.c",
+ "src/f32-argmaxpool/9p8x-sse2-c4.c",
+ "src/f32-argmaxpool/9x-sse2-c4.c",
+ "src/f32-f16-vcvt/gen/vcvt-sse2-x8.c",
+ "src/f32-f16-vcvt/gen/vcvt-sse2-x16.c",
+ "src/f32-f16-vcvt/gen/vcvt-sse2-x24.c",
+ "src/f32-f16-vcvt/gen/vcvt-sse2-x32.c",
"src/f32-gemm/gen-inc/1x8inc-minmax-sse2-dup.c",
"src/f32-gemm/gen-inc/3x8inc-minmax-sse2-dup.c",
"src/f32-gemm/gen-inc/4x8inc-minmax-sse2-dup.c",
@@ -1587,30 +4956,26 @@
"src/f32-igemm/gen/5x8-minmax-sse2-dup.c",
"src/f32-prelu/gen/sse2-2x4.c",
"src/f32-prelu/gen/sse2-2x8.c",
- "src/f32-raddstoreexpminusmax/gen/sse2-p5-x4.c",
- "src/f32-raddstoreexpminusmax/gen/sse2-p5-x8-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/sse2-p5-x8.c",
- "src/f32-raddstoreexpminusmax/gen/sse2-p5-x12-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/sse2-p5-x12-acc3.c",
- "src/f32-raddstoreexpminusmax/gen/sse2-p5-x12.c",
- "src/f32-raddstoreexpminusmax/gen/sse2-p5-x16-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/sse2-p5-x16-acc4.c",
- "src/f32-raddstoreexpminusmax/gen/sse2-p5-x16.c",
- "src/f32-raddstoreexpminusmax/gen/sse2-p5-x20-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/sse2-p5-x20-acc5.c",
- "src/f32-raddstoreexpminusmax/gen/sse2-p5-x20.c",
- "src/f32-sigmoid/gen/sse2-lut64-p2-div-x4.c",
- "src/f32-sigmoid/gen/sse2-lut64-p2-div-x8.c",
- "src/f32-sigmoid/gen/sse2-lut64-p2-div-x12.c",
- "src/f32-sigmoid/gen/sse2-lut64-p2-div-x16.c",
- "src/f32-sigmoid/gen/sse2-lut64-p2-div-x20.c",
- "src/f32-sigmoid/gen/sse2-lut64-p2-div-x24.c",
- "src/f32-sigmoid/gen/sse2-p5-div-x4.c",
- "src/f32-sigmoid/gen/sse2-p5-div-x8.c",
- "src/f32-sigmoid/gen/sse2-p5-div-x12.c",
- "src/f32-sigmoid/gen/sse2-p5-div-x16.c",
- "src/f32-sigmoid/gen/sse2-p5-div-x20.c",
- "src/f32-sigmoid/gen/sse2-p5-div-x24.c",
+ "src/f32-qs8-vcvt/gen/vcvt-sse2-x8.c",
+ "src/f32-qs8-vcvt/gen/vcvt-sse2-x16.c",
+ "src/f32-qs8-vcvt/gen/vcvt-sse2-x24.c",
+ "src/f32-qs8-vcvt/gen/vcvt-sse2-x32.c",
+ "src/f32-qu8-vcvt/gen/vcvt-sse2-x8.c",
+ "src/f32-qu8-vcvt/gen/vcvt-sse2-x16.c",
+ "src/f32-qu8-vcvt/gen/vcvt-sse2-x24.c",
+ "src/f32-qu8-vcvt/gen/vcvt-sse2-x32.c",
+ "src/f32-raddstoreexpminusmax/gen/sse2-rr2-p5-x4.c",
+ "src/f32-raddstoreexpminusmax/gen/sse2-rr2-p5-x8-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/sse2-rr2-p5-x8.c",
+ "src/f32-raddstoreexpminusmax/gen/sse2-rr2-p5-x12-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/sse2-rr2-p5-x12-acc3.c",
+ "src/f32-raddstoreexpminusmax/gen/sse2-rr2-p5-x12.c",
+ "src/f32-raddstoreexpminusmax/gen/sse2-rr2-p5-x16-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/sse2-rr2-p5-x16-acc4.c",
+ "src/f32-raddstoreexpminusmax/gen/sse2-rr2-p5-x16.c",
+ "src/f32-raddstoreexpminusmax/gen/sse2-rr2-p5-x20-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/sse2-rr2-p5-x20-acc5.c",
+ "src/f32-raddstoreexpminusmax/gen/sse2-rr2-p5-x20.c",
"src/f32-velu/gen/velu-sse2-rr2-lut16-p3-x4.c",
"src/f32-velu/gen/velu-sse2-rr2-lut16-p3-x8.c",
"src/f32-velu/gen/velu-sse2-rr2-lut16-p3-x12.c",
@@ -1633,6 +4998,21 @@
"src/f32-vrnd/gen/vrndu-sse2-x8.c",
"src/f32-vrnd/gen/vrndz-sse2-x4.c",
"src/f32-vrnd/gen/vrndz-sse2-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-sse2-rr2-lut64-p2-div-x4.c",
+ "src/f32-vsigmoid/gen/vsigmoid-sse2-rr2-lut64-p2-div-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-sse2-rr2-lut64-p2-div-x12.c",
+ "src/f32-vsigmoid/gen/vsigmoid-sse2-rr2-lut64-p2-div-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-sse2-rr2-lut64-p2-div-x20.c",
+ "src/f32-vsigmoid/gen/vsigmoid-sse2-rr2-lut64-p2-div-x24.c",
+ "src/f32-vsigmoid/gen/vsigmoid-sse2-rr2-p5-div-x4.c",
+ "src/f32-vsigmoid/gen/vsigmoid-sse2-rr2-p5-div-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-sse2-rr2-p5-div-x12.c",
+ "src/f32-vsigmoid/gen/vsigmoid-sse2-rr2-p5-div-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-sse2-rr2-p5-div-x20.c",
+ "src/f32-vsigmoid/gen/vsigmoid-sse2-rr2-p5-div-x24.c",
+ "src/math/cvt-f16-f32-sse2-int16.c",
+ "src/math/cvt-f16-f32-sse2-int32.c",
+ "src/math/cvt-f32-f16-sse2.c",
"src/math/exp-sse2-rr2-lut64-p2.c",
"src/math/exp-sse2-rr2-p5.c",
"src/math/expm1minus-sse2-rr2-lut16-p3.c",
@@ -1648,43 +5028,102 @@
"src/math/sigmoid-sse2-rr2-p5-div.c",
"src/math/sigmoid-sse2-rr2-p5-nr1.c",
"src/math/sigmoid-sse2-rr2-p5-nr2.c",
- "src/qs8-dwconv/gen/up8x9-minmax-sse2-mul16.c",
- "src/qs8-dwconv/gen/up16x9-minmax-sse2-mul16.c",
- "src/qs8-dwconv/gen/up24x9-minmax-sse2-mul16.c",
- "src/qs8-gavgpool/gen/7p7x-minmax-sse2-c8-acc2.c",
- "src/qs8-gavgpool/gen/7p7x-minmax-sse2-c16-acc2.c",
- "src/qs8-gavgpool/gen/7p7x-minmax-sse2-c24-acc2.c",
- "src/qs8-gavgpool/gen/7x-minmax-sse2-c8-acc2.c",
- "src/qs8-gavgpool/gen/7x-minmax-sse2-c16-acc2.c",
- "src/qs8-gavgpool/gen/7x-minmax-sse2-c24-acc2.c",
- "src/qs8-gemm/gen/1x4c2-minmax-sse2-ld64.c",
- "src/qs8-gemm/gen/1x4c2-minmax-sse2-ld128.c",
- "src/qs8-gemm/gen/1x4c2-xw-minmax-sse2.c",
- "src/qs8-gemm/gen/1x4c8-minmax-sse2-ld64.c",
- "src/qs8-gemm/gen/1x4c8-minmax-sse2-ld128.c",
- "src/qs8-gemm/gen/1x4c8-xw-minmax-sse2.c",
- "src/qs8-gemm/gen/2x4c8-minmax-sse2-ld64.c",
- "src/qs8-gemm/gen/2x4c8-minmax-sse2-ld128.c",
- "src/qs8-gemm/gen/2x4c8-xw-minmax-sse2.c",
- "src/qs8-gemm/gen/3x4c8-minmax-sse2-ld64.c",
- "src/qs8-gemm/gen/3x4c8-minmax-sse2-ld128.c",
- "src/qs8-gemm/gen/3x4c8-xw-minmax-sse2.c",
- "src/qs8-gemm/gen/4x4c2-minmax-sse2-ld64.c",
- "src/qs8-gemm/gen/4x4c2-minmax-sse2-ld128.c",
- "src/qs8-gemm/gen/4x4c2-xw-minmax-sse2.c",
- "src/qs8-igemm/gen/1x4c2-minmax-sse2-ld64.c",
- "src/qs8-igemm/gen/1x4c2-minmax-sse2-ld128.c",
- "src/qs8-igemm/gen/1x4c8-minmax-sse2-ld64.c",
- "src/qs8-igemm/gen/1x4c8-minmax-sse2-ld128.c",
- "src/qs8-igemm/gen/2x4c8-minmax-sse2-ld64.c",
- "src/qs8-igemm/gen/2x4c8-minmax-sse2-ld128.c",
- "src/qs8-igemm/gen/3x4c8-minmax-sse2-ld64.c",
- "src/qs8-igemm/gen/3x4c8-minmax-sse2-ld128.c",
- "src/qs8-igemm/gen/4x4c2-minmax-sse2-ld64.c",
- "src/qs8-igemm/gen/4x4c2-minmax-sse2-ld128.c",
+ "src/qc8-dwconv/gen/up8x9-minmax-fp32-sse2-mul16-add16.c",
+ "src/qc8-dwconv/gen/up8x9-minmax-fp32-sse2-mul16.c",
+ "src/qc8-dwconv/gen/up8x25-minmax-fp32-sse2-mul16-add16.c",
+ "src/qc8-dwconv/gen/up8x25-minmax-fp32-sse2-mul16.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-sse2-mul16-add16.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-sse2-mul16.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-sse2-mul16-add16.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-sse2-mul16.c",
+ "src/qc8-dwconv/gen/up24x9-minmax-fp32-sse2-mul16.c",
+ "src/qc8-dwconv/gen/up24x25-minmax-fp32-sse2-mul16.c",
+ "src/qc8-gemm/gen/1x4c2-minmax-fp32-sse2-ld64.c",
+ "src/qc8-gemm/gen/1x4c2-minmax-fp32-sse2-ld128.c",
+ "src/qc8-gemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qc8-gemm/gen/1x4c8-minmax-fp32-sse2-ld128.c",
+ "src/qc8-gemm/gen/2x4c2-minmax-fp32-sse2-ld64.c",
+ "src/qc8-gemm/gen/2x4c2-minmax-fp32-sse2-ld128.c",
+ "src/qc8-gemm/gen/2x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qc8-gemm/gen/2x4c8-minmax-fp32-sse2-ld128.c",
+ "src/qc8-gemm/gen/3x4c2-minmax-fp32-sse2-ld64.c",
+ "src/qc8-gemm/gen/3x4c2-minmax-fp32-sse2-ld128.c",
+ "src/qc8-gemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qc8-gemm/gen/3x4c8-minmax-fp32-sse2-ld128.c",
+ "src/qc8-gemm/gen/4x4c2-minmax-fp32-sse2-ld64.c",
+ "src/qc8-gemm/gen/4x4c2-minmax-fp32-sse2-ld128.c",
+ "src/qc8-igemm/gen/1x4c2-minmax-fp32-sse2-ld64.c",
+ "src/qc8-igemm/gen/1x4c2-minmax-fp32-sse2-ld128.c",
+ "src/qc8-igemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qc8-igemm/gen/1x4c8-minmax-fp32-sse2-ld128.c",
+ "src/qc8-igemm/gen/2x4c2-minmax-fp32-sse2-ld64.c",
+ "src/qc8-igemm/gen/2x4c2-minmax-fp32-sse2-ld128.c",
+ "src/qc8-igemm/gen/2x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qc8-igemm/gen/2x4c8-minmax-fp32-sse2-ld128.c",
+ "src/qc8-igemm/gen/3x4c2-minmax-fp32-sse2-ld64.c",
+ "src/qc8-igemm/gen/3x4c2-minmax-fp32-sse2-ld128.c",
+ "src/qc8-igemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qc8-igemm/gen/3x4c8-minmax-fp32-sse2-ld128.c",
+ "src/qc8-igemm/gen/4x4c2-minmax-fp32-sse2-ld64.c",
+ "src/qc8-igemm/gen/4x4c2-minmax-fp32-sse2-ld128.c",
+ "src/qs8-dwconv/gen/up8x9-minmax-fp32-sse2-mul16-add16.c",
+ "src/qs8-dwconv/gen/up8x9-minmax-fp32-sse2-mul16.c",
+ "src/qs8-dwconv/gen/up8x25-minmax-fp32-sse2-mul16-add16.c",
+ "src/qs8-dwconv/gen/up8x25-minmax-fp32-sse2-mul16.c",
+ "src/qs8-dwconv/gen/up16x9-minmax-fp32-sse2-mul16-add16.c",
+ "src/qs8-dwconv/gen/up16x9-minmax-fp32-sse2-mul16.c",
+ "src/qs8-dwconv/gen/up16x25-minmax-fp32-sse2-mul16-add16.c",
+ "src/qs8-dwconv/gen/up16x25-minmax-fp32-sse2-mul16.c",
+ "src/qs8-dwconv/gen/up24x9-minmax-fp32-sse2-mul16.c",
+ "src/qs8-dwconv/gen/up24x25-minmax-fp32-sse2-mul16.c",
+ "src/qs8-f32-vcvt/gen/vcvt-sse2-x8.c",
+ "src/qs8-f32-vcvt/gen/vcvt-sse2-x16.c",
+ "src/qs8-f32-vcvt/gen/vcvt-sse2-x24.c",
+ "src/qs8-f32-vcvt/gen/vcvt-sse2-x32.c",
+ "src/qs8-gavgpool/gen/7p7x-minmax-fp32-sse2-c8.c",
+ "src/qs8-gavgpool/gen/7p7x-minmax-fp32-sse2-c16.c",
+ "src/qs8-gavgpool/gen/7p7x-minmax-fp32-sse2-c24.c",
+ "src/qs8-gavgpool/gen/7x-minmax-fp32-sse2-c8.c",
+ "src/qs8-gavgpool/gen/7x-minmax-fp32-sse2-c16.c",
+ "src/qs8-gavgpool/gen/7x-minmax-fp32-sse2-c24.c",
+ "src/qs8-gemm/gen/1x4c2-minmax-fp32-sse2-ld64.c",
+ "src/qs8-gemm/gen/1x4c2-minmax-fp32-sse2-ld128.c",
+ "src/qs8-gemm/gen/1x4c2-xw-minmax-fp32-sse2.c",
+ "src/qs8-gemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qs8-gemm/gen/1x4c8-minmax-fp32-sse2-ld128.c",
+ "src/qs8-gemm/gen/1x4c8-xw-minmax-fp32-sse2.c",
+ "src/qs8-gemm/gen/2x4c2-minmax-fp32-sse2-ld64.c",
+ "src/qs8-gemm/gen/2x4c2-minmax-fp32-sse2-ld128.c",
+ "src/qs8-gemm/gen/2x4c2-xw-minmax-fp32-sse2.c",
+ "src/qs8-gemm/gen/2x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qs8-gemm/gen/2x4c8-minmax-fp32-sse2-ld128.c",
+ "src/qs8-gemm/gen/2x4c8-xw-minmax-fp32-sse2.c",
+ "src/qs8-gemm/gen/3x4c2-minmax-fp32-sse2-ld64.c",
+ "src/qs8-gemm/gen/3x4c2-minmax-fp32-sse2-ld128.c",
+ "src/qs8-gemm/gen/3x4c2-xw-minmax-fp32-sse2.c",
+ "src/qs8-gemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qs8-gemm/gen/3x4c8-minmax-fp32-sse2-ld128.c",
+ "src/qs8-gemm/gen/3x4c8-xw-minmax-fp32-sse2.c",
+ "src/qs8-gemm/gen/4x4c2-minmax-fp32-sse2-ld64.c",
+ "src/qs8-gemm/gen/4x4c2-minmax-fp32-sse2-ld128.c",
+ "src/qs8-gemm/gen/4x4c2-xw-minmax-fp32-sse2.c",
+ "src/qs8-igemm/gen/1x4c2-minmax-fp32-sse2-ld64.c",
+ "src/qs8-igemm/gen/1x4c2-minmax-fp32-sse2-ld128.c",
+ "src/qs8-igemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qs8-igemm/gen/1x4c8-minmax-fp32-sse2-ld128.c",
+ "src/qs8-igemm/gen/2x4c2-minmax-fp32-sse2-ld64.c",
+ "src/qs8-igemm/gen/2x4c2-minmax-fp32-sse2-ld128.c",
+ "src/qs8-igemm/gen/2x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qs8-igemm/gen/2x4c8-minmax-fp32-sse2-ld128.c",
+ "src/qs8-igemm/gen/3x4c2-minmax-fp32-sse2-ld64.c",
+ "src/qs8-igemm/gen/3x4c2-minmax-fp32-sse2-ld128.c",
+ "src/qs8-igemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qs8-igemm/gen/3x4c8-minmax-fp32-sse2-ld128.c",
+ "src/qs8-igemm/gen/4x4c2-minmax-fp32-sse2-ld64.c",
+ "src/qs8-igemm/gen/4x4c2-minmax-fp32-sse2-ld128.c",
"src/qs8-requantization/fp32-sse2.c",
- "src/qs8-requantization/precise-sse2.c",
- "src/qs8-requantization/q31-sse2.c",
+ "src/qs8-requantization/gemmlowp-sse2.c",
+ "src/qs8-requantization/rndna-sse2.c",
"src/qs8-vadd/gen/minmax-sse2-mul16-ld64-x8.c",
"src/qs8-vadd/gen/minmax-sse2-mul16-ld64-x16.c",
"src/qs8-vadd/gen/minmax-sse2-mul16-ld64-x24.c",
@@ -1693,33 +5132,112 @@
"src/qs8-vaddc/gen/minmax-sse2-mul16-ld64-x16.c",
"src/qs8-vaddc/gen/minmax-sse2-mul16-ld64-x24.c",
"src/qs8-vaddc/gen/minmax-sse2-mul16-ld64-x32.c",
+ "src/qs8-vmul/gen/minmax-fp32-sse2-mul16-ld64-x8.c",
+ "src/qs8-vmul/gen/minmax-fp32-sse2-mul16-ld64-x16.c",
+ "src/qs8-vmulc/gen/minmax-fp32-sse2-mul16-ld64-x8.c",
+ "src/qs8-vmulc/gen/minmax-fp32-sse2-mul16-ld64-x16.c",
"src/qu8-avgpool/9p8x-minmax-sse2-c8.c",
"src/qu8-avgpool/9x-minmax-sse2-c8.c",
- "src/qu8-dwconv/up8x9-minmax-sse2.c",
- "src/qu8-gavgpool/7p7x-minmax-sse2-c8.c",
- "src/qu8-gavgpool/7x-minmax-sse2-c8.c",
- "src/qu8-gemm/2x4c8-minmax-sse2.c",
- "src/qu8-gemm/4x4c2-minmax-sse2.c",
- "src/qu8-igemm/4x4c2-minmax-sse2.c",
+ "src/qu8-dwconv/gen/up8x9-minmax-fp32-sse2-mul16.c",
+ "src/qu8-dwconv/gen/up8x25-minmax-fp32-sse2-mul16.c",
+ "src/qu8-dwconv/gen/up16x9-minmax-fp32-sse2-mul16.c",
+ "src/qu8-dwconv/gen/up16x25-minmax-fp32-sse2-mul16.c",
+ "src/qu8-f32-vcvt/gen/vcvt-sse2-x8.c",
+ "src/qu8-f32-vcvt/gen/vcvt-sse2-x16.c",
+ "src/qu8-f32-vcvt/gen/vcvt-sse2-x24.c",
+ "src/qu8-f32-vcvt/gen/vcvt-sse2-x32.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-sse2-c8.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-sse2-c16.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-sse2-c24.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-sse2-c8.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-sse2-c16.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-sse2-c24.c",
+ "src/qu8-gemm/gen/1x4c2-minmax-fp32-sse2-ld64.c",
+ "src/qu8-gemm/gen/1x4c2-minmax-fp32-sse2-ld128.c",
+ "src/qu8-gemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qu8-gemm/gen/1x4c8-minmax-fp32-sse2-ld128.c",
+ "src/qu8-gemm/gen/2x4c2-minmax-fp32-sse2-ld64.c",
+ "src/qu8-gemm/gen/2x4c2-minmax-fp32-sse2-ld128.c",
+ "src/qu8-gemm/gen/2x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qu8-gemm/gen/2x4c8-minmax-fp32-sse2-ld128.c",
+ "src/qu8-gemm/gen/3x4c2-minmax-fp32-sse2-ld64.c",
+ "src/qu8-gemm/gen/3x4c2-minmax-fp32-sse2-ld128.c",
+ "src/qu8-gemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qu8-gemm/gen/3x4c8-minmax-fp32-sse2-ld128.c",
+ "src/qu8-gemm/gen/4x4c2-minmax-fp32-sse2-ld64.c",
+ "src/qu8-gemm/gen/4x4c2-minmax-fp32-sse2-ld128.c",
+ "src/qu8-igemm/gen/1x4c2-minmax-fp32-sse2-ld64.c",
+ "src/qu8-igemm/gen/1x4c2-minmax-fp32-sse2-ld128.c",
+ "src/qu8-igemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qu8-igemm/gen/1x4c8-minmax-fp32-sse2-ld128.c",
+ "src/qu8-igemm/gen/2x4c2-minmax-fp32-sse2-ld64.c",
+ "src/qu8-igemm/gen/2x4c2-minmax-fp32-sse2-ld128.c",
+ "src/qu8-igemm/gen/2x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qu8-igemm/gen/2x4c8-minmax-fp32-sse2-ld128.c",
+ "src/qu8-igemm/gen/3x4c2-minmax-fp32-sse2-ld64.c",
+ "src/qu8-igemm/gen/3x4c2-minmax-fp32-sse2-ld128.c",
+ "src/qu8-igemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
+ "src/qu8-igemm/gen/3x4c8-minmax-fp32-sse2-ld128.c",
+ "src/qu8-igemm/gen/4x4c2-minmax-fp32-sse2-ld64.c",
+ "src/qu8-igemm/gen/4x4c2-minmax-fp32-sse2-ld128.c",
"src/qu8-requantization/fp32-sse2.c",
- "src/qu8-requantization/precise-sse2.c",
- "src/qu8-requantization/q31-sse2.c",
- "src/qu8-vadd/minmax-sse2.c",
- "src/u8-clamp/sse2-x64.c",
+ "src/qu8-requantization/gemmlowp-sse2.c",
+ "src/qu8-requantization/rndna-sse2.c",
+ "src/qu8-vadd/gen/minmax-sse2-mul16-ld64-x8.c",
+ "src/qu8-vadd/gen/minmax-sse2-mul16-ld64-x16.c",
+ "src/qu8-vaddc/gen/minmax-sse2-mul16-ld64-x8.c",
+ "src/qu8-vaddc/gen/minmax-sse2-mul16-ld64-x16.c",
+ "src/qu8-vmul/gen/minmax-fp32-sse2-mul16-ld64-x8.c",
+ "src/qu8-vmul/gen/minmax-fp32-sse2-mul16-ld64-x16.c",
+ "src/qu8-vmulc/gen/minmax-fp32-sse2-mul16-ld64-x8.c",
+ "src/qu8-vmulc/gen/minmax-fp32-sse2-mul16-ld64-x16.c",
+ "src/s8-ibilinear/gen/sse2-c8.c",
+ "src/s8-ibilinear/gen/sse2-c16.c",
+ "src/s8-maxpool/9p8x-minmax-sse2-c16.c",
+ "src/s8-vclamp/sse2-x64.c",
+ "src/u8-ibilinear/gen/sse2-c8.c",
+ "src/u8-ibilinear/gen/sse2-c16.c",
"src/u8-maxpool/9p8x-minmax-sse2-c16.c",
"src/u8-rmax/sse2.c",
+ "src/u8-vclamp/sse2-x64.c",
+ "src/x8-transpose/gen/16x16-reuse-mov-sse2.c",
+ "src/x8-transpose/gen/16x16-reuse-switch-sse2.c",
"src/x8-zip/x2-sse2.c",
"src/x8-zip/x3-sse2.c",
"src/x8-zip/x4-sse2.c",
"src/x8-zip/xm-sse2.c",
+ "src/x16-transpose/4x8-sse2.c",
+ "src/x16-transpose/gen/8x8-multi-mov-sse2.c",
+ "src/x16-transpose/gen/8x8-multi-switch-sse2.c",
+ "src/x16-transpose/gen/8x8-reuse-mov-sse2.c",
+ "src/x16-transpose/gen/8x8-reuse-multi-sse2.c",
+ "src/x16-transpose/gen/8x8-reuse-switch-sse2.c",
+ "src/x32-transpose/gen/4x4-multi-mov-sse2.c",
+ "src/x32-transpose/gen/4x4-multi-multi-sse2.c",
+ "src/x32-transpose/gen/4x4-multi-switch-sse2.c",
+ "src/x32-transpose/gen/4x4-reuse-mov-sse2.c",
+ "src/x32-transpose/gen/4x4-reuse-multi-sse2.c",
+ "src/x32-transpose/gen/4x4-reuse-switch-sse2.c",
"src/x32-unpool/sse2.c",
"src/x32-zip/x2-sse2.c",
"src/x32-zip/x3-sse2.c",
"src/x32-zip/x4-sse2.c",
"src/x32-zip/xm-sse2.c",
+ "src/x64-transpose/gen/2x2-multi-mov-sse2.c",
+ "src/x64-transpose/gen/2x2-multi-multi-sse2.c",
+ "src/x64-transpose/gen/2x2-multi-switch-sse2.c",
+ "src/x64-transpose/gen/2x2-reuse-mov-sse2.c",
+ "src/x64-transpose/gen/2x2-reuse-multi-sse2.c",
+ "src/x64-transpose/gen/2x2-reuse-switch-sse2.c",
+ "src/xx-fill/sse2-x64.c",
+ "src/xx-pad/sse2.c",
]
-SSSE3_UKERNELS = [
+PROD_SSSE3_MICROKERNEL_SRCS = [
+ "src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-2x4-acc2.c",
+]
+
+ALL_SSSE3_MICROKERNEL_SRCS = [
"src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-1x4-acc2.c",
"src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-1x4-acc3.c",
"src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-1x4-acc4.c",
@@ -1730,61 +5248,97 @@
"src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-4x4.c",
"src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-5x4.c",
"src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-6x4.c",
- "src/qs8-dwconv/gen/up8x9-minmax-ssse3-mul16.c",
- "src/qs8-dwconv/gen/up16x9-minmax-ssse3-mul16.c",
- "src/qs8-dwconv/gen/up24x9-minmax-ssse3-mul16.c",
- "src/qs8-gavgpool/gen/7p7x-minmax-ssse3-c8-acc2.c",
- "src/qs8-gavgpool/gen/7p7x-minmax-ssse3-c16-acc2.c",
- "src/qs8-gavgpool/gen/7p7x-minmax-ssse3-c24-acc2.c",
- "src/qs8-gavgpool/gen/7x-minmax-ssse3-c8-acc2.c",
- "src/qs8-gavgpool/gen/7x-minmax-ssse3-c16-acc2.c",
- "src/qs8-gavgpool/gen/7x-minmax-ssse3-c24-acc2.c",
- "src/qs8-gemm/gen/1x4c2-minmax-ssse3-ld64.c",
- "src/qs8-gemm/gen/1x4c2-minmax-ssse3-ld128.c",
- "src/qs8-gemm/gen/1x4c2-xw-minmax-ssse3.c",
- "src/qs8-gemm/gen/1x4c8-minmax-ssse3-ld64.c",
- "src/qs8-gemm/gen/1x4c8-minmax-ssse3-ld128.c",
- "src/qs8-gemm/gen/1x4c8-xw-minmax-ssse3.c",
- "src/qs8-gemm/gen/2x4c8-minmax-ssse3-ld64.c",
- "src/qs8-gemm/gen/2x4c8-minmax-ssse3-ld128.c",
- "src/qs8-gemm/gen/2x4c8-xw-minmax-ssse3.c",
- "src/qs8-gemm/gen/3x4c8-minmax-ssse3-ld64.c",
- "src/qs8-gemm/gen/3x4c8-minmax-ssse3-ld128.c",
- "src/qs8-gemm/gen/3x4c8-xw-minmax-ssse3.c",
- "src/qs8-gemm/gen/4x4c2-minmax-ssse3-ld64.c",
- "src/qs8-gemm/gen/4x4c2-minmax-ssse3-ld128.c",
- "src/qs8-gemm/gen/4x4c2-xw-minmax-ssse3.c",
- "src/qs8-igemm/gen/1x4c2-minmax-ssse3-ld64.c",
- "src/qs8-igemm/gen/1x4c2-minmax-ssse3-ld128.c",
- "src/qs8-igemm/gen/1x4c8-minmax-ssse3-ld64.c",
- "src/qs8-igemm/gen/1x4c8-minmax-ssse3-ld128.c",
- "src/qs8-igemm/gen/2x4c8-minmax-ssse3-ld64.c",
- "src/qs8-igemm/gen/2x4c8-minmax-ssse3-ld128.c",
- "src/qs8-igemm/gen/3x4c8-minmax-ssse3-ld64.c",
- "src/qs8-igemm/gen/3x4c8-minmax-ssse3-ld128.c",
- "src/qs8-igemm/gen/4x4c2-minmax-ssse3-ld64.c",
- "src/qs8-igemm/gen/4x4c2-minmax-ssse3-ld128.c",
- "src/qs8-requantization/precise-ssse3.c",
- "src/qs8-requantization/q31-ssse3.c",
- "src/qu8-requantization/precise-ssse3.c",
- "src/qu8-requantization/q31-ssse3.c",
+ "src/qs8-gemm/gen/1x4c8-minmax-fp32-ssse3-ld64.c",
+ "src/qs8-gemm/gen/1x4c8-minmax-fp32-ssse3-ld128.c",
+ "src/qs8-gemm/gen/1x4c8-xw-minmax-fp32-ssse3.c",
+ "src/qs8-gemm/gen/2x4c8-minmax-fp32-ssse3-ld64.c",
+ "src/qs8-gemm/gen/2x4c8-minmax-fp32-ssse3-ld128.c",
+ "src/qs8-gemm/gen/2x4c8-xw-minmax-fp32-ssse3.c",
+ "src/qs8-gemm/gen/3x4c8-minmax-fp32-ssse3-ld64.c",
+ "src/qs8-gemm/gen/3x4c8-minmax-fp32-ssse3-ld128.c",
+ "src/qs8-gemm/gen/3x4c8-xw-minmax-fp32-ssse3.c",
+ "src/qs8-igemm/gen/1x4c8-minmax-fp32-ssse3-ld64.c",
+ "src/qs8-igemm/gen/1x4c8-minmax-fp32-ssse3-ld128.c",
+ "src/qs8-igemm/gen/2x4c8-minmax-fp32-ssse3-ld64.c",
+ "src/qs8-igemm/gen/2x4c8-minmax-fp32-ssse3-ld128.c",
+ "src/qs8-igemm/gen/3x4c8-minmax-fp32-ssse3-ld64.c",
+ "src/qs8-igemm/gen/3x4c8-minmax-fp32-ssse3-ld128.c",
+ "src/qs8-requantization/gemmlowp-ssse3.c",
+ "src/qs8-requantization/rndna-ssse3.c",
+ "src/qu8-requantization/gemmlowp-ssse3.c",
+ "src/qu8-requantization/rndna-ssse3.c",
+ "src/x8-lut/gen/lut-ssse3-x16.c",
+ "src/x8-lut/gen/lut-ssse3-x32.c",
]
-SSE41_UKERNELS = [
+PROD_SSE41_MICROKERNEL_SRCS = [
+ "src/f16-f32-vcvt/gen/vcvt-sse41-int16-x16.c",
+ "src/f32-f16-vcvt/gen/vcvt-sse41-x8.c",
+ "src/f32-prelu/gen/sse41-2x8.c",
+ "src/f32-qs8-vcvt/gen/vcvt-sse41-x32.c",
+ "src/f32-vlrelu/gen/vlrelu-sse41-x8.c",
+ "src/f32-vrnd/gen/vrndd-sse41-x8.c",
+ "src/f32-vrnd/gen/vrndne-sse41-x8.c",
+ "src/f32-vrnd/gen/vrndu-sse41-x8.c",
+ "src/f32-vrnd/gen/vrndz-sse41-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-sse41-rr2-lut64-p2-div-x8.c",
+ "src/qc8-dwconv/gen/up8x9-minmax-fp32-sse41-mul16.c",
+ "src/qc8-dwconv/gen/up8x25-minmax-fp32-sse41-mul16.c",
+ "src/qc8-gemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qc8-gemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qc8-igemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qc8-igemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qs8-dwconv/gen/up8x9-minmax-fp32-sse41-mul16-add16.c",
+ "src/qs8-dwconv/gen/up8x25-minmax-fp32-sse41-mul16-add16.c",
+ "src/qs8-f32-vcvt/gen/vcvt-sse41-x16.c",
+ "src/qs8-gavgpool/gen/7p7x-minmax-fp32-sse41-c8.c",
+ "src/qs8-gavgpool/gen/7x-minmax-fp32-sse41-c8.c",
+ "src/qs8-gemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qs8-gemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qs8-igemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qs8-igemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qs8-vadd/gen/minmax-sse41-mul16-ld64-x8.c",
+ "src/qs8-vaddc/gen/minmax-sse41-mul16-ld64-x8.c",
+ "src/qs8-vmul/gen/minmax-fp32-sse41-mul16-ld64-x16.c",
+ "src/qs8-vmulc/gen/minmax-fp32-sse41-mul16-ld64-x16.c",
+ "src/qu8-dwconv/gen/up8x9-minmax-fp32-sse41-mul16.c",
+ "src/qu8-dwconv/gen/up8x25-minmax-fp32-sse41-mul16.c",
+ "src/qu8-f32-vcvt/gen/vcvt-sse41-x16.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-sse41-c8.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-sse41-c8.c",
+ "src/qu8-gemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qu8-gemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qu8-igemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qu8-igemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qu8-vadd/gen/minmax-sse41-mul16-ld64-x8.c",
+ "src/qu8-vaddc/gen/minmax-sse41-mul16-ld64-x8.c",
+ "src/qu8-vmul/gen/minmax-fp32-sse41-mul16-ld64-x16.c",
+ "src/qu8-vmulc/gen/minmax-fp32-sse41-mul16-ld64-x16.c",
+ "src/s8-ibilinear/gen/sse41-c16.c",
+ "src/s8-maxpool/9p8x-minmax-sse41-c16.c",
+ "src/s8-vclamp/sse41-x64.c",
+ "src/u8-ibilinear/gen/sse41-c16.c",
+]
+
+ALL_SSE41_MICROKERNEL_SRCS = [
+ "src/f16-f32-vcvt/gen/vcvt-sse41-int16-x8.c",
+ "src/f16-f32-vcvt/gen/vcvt-sse41-int16-x16.c",
+ "src/f16-f32-vcvt/gen/vcvt-sse41-int16-x24.c",
+ "src/f16-f32-vcvt/gen/vcvt-sse41-int16-x32.c",
+ "src/f16-f32-vcvt/gen/vcvt-sse41-int32-x8.c",
+ "src/f16-f32-vcvt/gen/vcvt-sse41-int32-x16.c",
+ "src/f16-f32-vcvt/gen/vcvt-sse41-int32-x24.c",
+ "src/f16-f32-vcvt/gen/vcvt-sse41-int32-x32.c",
+ "src/f32-f16-vcvt/gen/vcvt-sse41-x8.c",
+ "src/f32-f16-vcvt/gen/vcvt-sse41-x16.c",
+ "src/f32-f16-vcvt/gen/vcvt-sse41-x24.c",
+ "src/f32-f16-vcvt/gen/vcvt-sse41-x32.c",
"src/f32-prelu/gen/sse41-2x4.c",
"src/f32-prelu/gen/sse41-2x8.c",
- "src/f32-sigmoid/gen/sse41-lut64-p2-div-x4.c",
- "src/f32-sigmoid/gen/sse41-lut64-p2-div-x8.c",
- "src/f32-sigmoid/gen/sse41-lut64-p2-div-x12.c",
- "src/f32-sigmoid/gen/sse41-lut64-p2-div-x16.c",
- "src/f32-sigmoid/gen/sse41-lut64-p2-div-x20.c",
- "src/f32-sigmoid/gen/sse41-lut64-p2-div-x24.c",
- "src/f32-sigmoid/gen/sse41-p5-div-x4.c",
- "src/f32-sigmoid/gen/sse41-p5-div-x8.c",
- "src/f32-sigmoid/gen/sse41-p5-div-x12.c",
- "src/f32-sigmoid/gen/sse41-p5-div-x16.c",
- "src/f32-sigmoid/gen/sse41-p5-div-x20.c",
- "src/f32-sigmoid/gen/sse41-p5-div-x24.c",
+ "src/f32-qs8-vcvt/gen/vcvt-sse41-x8.c",
+ "src/f32-qs8-vcvt/gen/vcvt-sse41-x16.c",
+ "src/f32-qs8-vcvt/gen/vcvt-sse41-x24.c",
+ "src/f32-qs8-vcvt/gen/vcvt-sse41-x32.c",
"src/f32-velu/gen/velu-sse41-rr2-lut16-p3-x4.c",
"src/f32-velu/gen/velu-sse41-rr2-lut16-p3-x8.c",
"src/f32-velu/gen/velu-sse41-rr2-lut16-p3-x12.c",
@@ -1807,47 +5361,135 @@
"src/f32-vrnd/gen/vrndu-sse41-x8.c",
"src/f32-vrnd/gen/vrndz-sse41-x4.c",
"src/f32-vrnd/gen/vrndz-sse41-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-sse41-rr2-lut64-p2-div-x4.c",
+ "src/f32-vsigmoid/gen/vsigmoid-sse41-rr2-lut64-p2-div-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-sse41-rr2-lut64-p2-div-x12.c",
+ "src/f32-vsigmoid/gen/vsigmoid-sse41-rr2-lut64-p2-div-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-sse41-rr2-lut64-p2-div-x20.c",
+ "src/f32-vsigmoid/gen/vsigmoid-sse41-rr2-lut64-p2-div-x24.c",
+ "src/f32-vsigmoid/gen/vsigmoid-sse41-rr2-p5-div-x4.c",
+ "src/f32-vsigmoid/gen/vsigmoid-sse41-rr2-p5-div-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-sse41-rr2-p5-div-x12.c",
+ "src/f32-vsigmoid/gen/vsigmoid-sse41-rr2-p5-div-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-sse41-rr2-p5-div-x20.c",
+ "src/f32-vsigmoid/gen/vsigmoid-sse41-rr2-p5-div-x24.c",
+ "src/math/cvt-f16-f32-sse41-int16.c",
+ "src/math/cvt-f16-f32-sse41-int32.c",
+ "src/math/cvt-f32-f16-sse41.c",
"src/math/roundd-sse41.c",
"src/math/roundne-sse41.c",
"src/math/roundu-sse41.c",
"src/math/roundz-sse41.c",
- "src/qs8-dwconv/gen/up8x9-minmax-sse41-mul16.c",
- "src/qs8-dwconv/gen/up16x9-minmax-sse41-mul16.c",
- "src/qs8-dwconv/gen/up24x9-minmax-sse41-mul16.c",
- "src/qs8-gavgpool/gen/7p7x-minmax-sse41-c8-acc2.c",
- "src/qs8-gavgpool/gen/7p7x-minmax-sse41-c16-acc2.c",
- "src/qs8-gavgpool/gen/7p7x-minmax-sse41-c24-acc2.c",
- "src/qs8-gavgpool/gen/7x-minmax-sse41-c8-acc2.c",
- "src/qs8-gavgpool/gen/7x-minmax-sse41-c16-acc2.c",
- "src/qs8-gavgpool/gen/7x-minmax-sse41-c24-acc2.c",
- "src/qs8-gemm/gen/1x4c2-minmax-sse41-ld64.c",
- "src/qs8-gemm/gen/1x4c2-minmax-sse41-ld128.c",
- "src/qs8-gemm/gen/1x4c2-xw-minmax-sse41.c",
- "src/qs8-gemm/gen/1x4c8-minmax-sse41-ld64.c",
- "src/qs8-gemm/gen/1x4c8-minmax-sse41-ld128.c",
- "src/qs8-gemm/gen/1x4c8-xw-minmax-sse41.c",
- "src/qs8-gemm/gen/2x4c8-minmax-sse41-ld64.c",
- "src/qs8-gemm/gen/2x4c8-minmax-sse41-ld128.c",
- "src/qs8-gemm/gen/2x4c8-xw-minmax-sse41.c",
- "src/qs8-gemm/gen/3x4c8-minmax-sse41-ld64.c",
- "src/qs8-gemm/gen/3x4c8-minmax-sse41-ld128.c",
- "src/qs8-gemm/gen/3x4c8-xw-minmax-sse41.c",
- "src/qs8-gemm/gen/4x4c2-minmax-sse41-ld64.c",
- "src/qs8-gemm/gen/4x4c2-minmax-sse41-ld128.c",
- "src/qs8-gemm/gen/4x4c2-xw-minmax-sse41.c",
- "src/qs8-igemm/gen/1x4c2-minmax-sse41-ld64.c",
- "src/qs8-igemm/gen/1x4c2-minmax-sse41-ld128.c",
- "src/qs8-igemm/gen/1x4c8-minmax-sse41-ld64.c",
- "src/qs8-igemm/gen/1x4c8-minmax-sse41-ld128.c",
- "src/qs8-igemm/gen/2x4c8-minmax-sse41-ld64.c",
- "src/qs8-igemm/gen/2x4c8-minmax-sse41-ld128.c",
- "src/qs8-igemm/gen/3x4c8-minmax-sse41-ld64.c",
- "src/qs8-igemm/gen/3x4c8-minmax-sse41-ld128.c",
- "src/qs8-igemm/gen/4x4c2-minmax-sse41-ld64.c",
- "src/qs8-igemm/gen/4x4c2-minmax-sse41-ld128.c",
+ "src/qc8-dwconv/gen/up8x9-minmax-fp32-sse41-mul16-add16.c",
+ "src/qc8-dwconv/gen/up8x9-minmax-fp32-sse41-mul16.c",
+ "src/qc8-dwconv/gen/up8x9-minmax-fp32-sse41-mul32.c",
+ "src/qc8-dwconv/gen/up8x25-minmax-fp32-sse41-mul16-add16.c",
+ "src/qc8-dwconv/gen/up8x25-minmax-fp32-sse41-mul16.c",
+ "src/qc8-dwconv/gen/up8x25-minmax-fp32-sse41-mul32.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-sse41-mul16-add16.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-sse41-mul16.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-sse41-mul32.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-sse41-mul16-add16.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-sse41-mul16.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-sse41-mul32.c",
+ "src/qc8-dwconv/gen/up24x9-minmax-fp32-sse41-mul16.c",
+ "src/qc8-dwconv/gen/up24x9-minmax-fp32-sse41-mul32.c",
+ "src/qc8-dwconv/gen/up24x25-minmax-fp32-sse41-mul16.c",
+ "src/qc8-dwconv/gen/up24x25-minmax-fp32-sse41-mul32.c",
+ "src/qc8-gemm/gen/1x4c2-minmax-fp32-sse41-ld64.c",
+ "src/qc8-gemm/gen/1x4c2-minmax-fp32-sse41-ld128.c",
+ "src/qc8-gemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qc8-gemm/gen/1x4c8-minmax-fp32-sse41-ld128.c",
+ "src/qc8-gemm/gen/2x4c2-minmax-fp32-sse41-ld64.c",
+ "src/qc8-gemm/gen/2x4c2-minmax-fp32-sse41-ld128.c",
+ "src/qc8-gemm/gen/2x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qc8-gemm/gen/2x4c8-minmax-fp32-sse41-ld128.c",
+ "src/qc8-gemm/gen/3x4c2-minmax-fp32-sse41-ld64.c",
+ "src/qc8-gemm/gen/3x4c2-minmax-fp32-sse41-ld128.c",
+ "src/qc8-gemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qc8-gemm/gen/3x4c8-minmax-fp32-sse41-ld128.c",
+ "src/qc8-gemm/gen/4x4c2-minmax-fp32-sse41-ld64.c",
+ "src/qc8-gemm/gen/4x4c2-minmax-fp32-sse41-ld128.c",
+ "src/qc8-igemm/gen/1x4c2-minmax-fp32-sse41-ld64.c",
+ "src/qc8-igemm/gen/1x4c2-minmax-fp32-sse41-ld128.c",
+ "src/qc8-igemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qc8-igemm/gen/1x4c8-minmax-fp32-sse41-ld128.c",
+ "src/qc8-igemm/gen/2x4c2-minmax-fp32-sse41-ld64.c",
+ "src/qc8-igemm/gen/2x4c2-minmax-fp32-sse41-ld128.c",
+ "src/qc8-igemm/gen/2x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qc8-igemm/gen/2x4c8-minmax-fp32-sse41-ld128.c",
+ "src/qc8-igemm/gen/3x4c2-minmax-fp32-sse41-ld64.c",
+ "src/qc8-igemm/gen/3x4c2-minmax-fp32-sse41-ld128.c",
+ "src/qc8-igemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qc8-igemm/gen/3x4c8-minmax-fp32-sse41-ld128.c",
+ "src/qc8-igemm/gen/4x4c2-minmax-fp32-sse41-ld64.c",
+ "src/qc8-igemm/gen/4x4c2-minmax-fp32-sse41-ld128.c",
+ "src/qs8-dwconv/gen/up8x9-minmax-fp32-sse41-mul16-add16.c",
+ "src/qs8-dwconv/gen/up8x9-minmax-fp32-sse41-mul16.c",
+ "src/qs8-dwconv/gen/up8x9-minmax-fp32-sse41-mul32.c",
+ "src/qs8-dwconv/gen/up8x25-minmax-fp32-sse41-mul16-add16.c",
+ "src/qs8-dwconv/gen/up8x25-minmax-fp32-sse41-mul16.c",
+ "src/qs8-dwconv/gen/up8x25-minmax-fp32-sse41-mul32.c",
+ "src/qs8-dwconv/gen/up16x9-minmax-fp32-sse41-mul16-add16.c",
+ "src/qs8-dwconv/gen/up16x9-minmax-fp32-sse41-mul16.c",
+ "src/qs8-dwconv/gen/up16x9-minmax-fp32-sse41-mul32.c",
+ "src/qs8-dwconv/gen/up16x25-minmax-fp32-sse41-mul16-add16.c",
+ "src/qs8-dwconv/gen/up16x25-minmax-fp32-sse41-mul16.c",
+ "src/qs8-dwconv/gen/up16x25-minmax-fp32-sse41-mul32.c",
+ "src/qs8-dwconv/gen/up24x9-minmax-fp32-sse41-mul16.c",
+ "src/qs8-dwconv/gen/up24x9-minmax-fp32-sse41-mul32.c",
+ "src/qs8-dwconv/gen/up24x25-minmax-fp32-sse41-mul16.c",
+ "src/qs8-dwconv/gen/up24x25-minmax-fp32-sse41-mul32.c",
+ "src/qs8-f32-vcvt/gen/vcvt-sse41-x8.c",
+ "src/qs8-f32-vcvt/gen/vcvt-sse41-x16.c",
+ "src/qs8-f32-vcvt/gen/vcvt-sse41-x24.c",
+ "src/qs8-f32-vcvt/gen/vcvt-sse41-x32.c",
+ "src/qs8-gavgpool/gen/7p7x-minmax-fp32-sse41-c8.c",
+ "src/qs8-gavgpool/gen/7p7x-minmax-fp32-sse41-c16.c",
+ "src/qs8-gavgpool/gen/7p7x-minmax-fp32-sse41-c24.c",
+ "src/qs8-gavgpool/gen/7x-minmax-fp32-sse41-c8.c",
+ "src/qs8-gavgpool/gen/7x-minmax-fp32-sse41-c16.c",
+ "src/qs8-gavgpool/gen/7x-minmax-fp32-sse41-c24.c",
+ "src/qs8-gemm/gen/1x4c2-minmax-fp32-sse41-ld64.c",
+ "src/qs8-gemm/gen/1x4c2-minmax-fp32-sse41-ld128.c",
+ "src/qs8-gemm/gen/1x4c2-xw-minmax-fp32-sse41.c",
+ "src/qs8-gemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qs8-gemm/gen/1x4c8-minmax-fp32-sse41-ld128.c",
+ "src/qs8-gemm/gen/1x4c8-xw-minmax-fp32-sse41.c",
+ "src/qs8-gemm/gen/2x4c2-minmax-fp32-sse41-ld64.c",
+ "src/qs8-gemm/gen/2x4c2-minmax-fp32-sse41-ld128.c",
+ "src/qs8-gemm/gen/2x4c2-xw-minmax-fp32-sse41.c",
+ "src/qs8-gemm/gen/2x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qs8-gemm/gen/2x4c8-minmax-fp32-sse41-ld128.c",
+ "src/qs8-gemm/gen/2x4c8-xw-minmax-fp32-sse41.c",
+ "src/qs8-gemm/gen/3x4c2-minmax-fp32-sse41-ld64.c",
+ "src/qs8-gemm/gen/3x4c2-minmax-fp32-sse41-ld128.c",
+ "src/qs8-gemm/gen/3x4c2-xw-minmax-fp32-sse41.c",
+ "src/qs8-gemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qs8-gemm/gen/3x4c8-minmax-fp32-sse41-ld128.c",
+ "src/qs8-gemm/gen/3x4c8-xw-minmax-fp32-sse41.c",
+ "src/qs8-gemm/gen/4x4c2-minmax-fp32-sse41-ld64.c",
+ "src/qs8-gemm/gen/4x4c2-minmax-fp32-sse41-ld128.c",
+ "src/qs8-gemm/gen/4x4c2-xw-minmax-fp32-sse41.c",
+ "src/qs8-igemm/gen/1x4c2-minmax-fp32-sse41-ld64.c",
+ "src/qs8-igemm/gen/1x4c2-minmax-fp32-sse41-ld128.c",
+ "src/qs8-igemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qs8-igemm/gen/1x4c8-minmax-fp32-sse41-ld128.c",
+ "src/qs8-igemm/gen/2x4c2-minmax-fp32-sse41-ld64.c",
+ "src/qs8-igemm/gen/2x4c2-minmax-fp32-sse41-ld128.c",
+ "src/qs8-igemm/gen/2x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qs8-igemm/gen/2x4c8-minmax-fp32-sse41-ld128.c",
+ "src/qs8-igemm/gen/3x4c2-minmax-fp32-sse41-ld64.c",
+ "src/qs8-igemm/gen/3x4c2-minmax-fp32-sse41-ld128.c",
+ "src/qs8-igemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qs8-igemm/gen/3x4c8-minmax-fp32-sse41-ld128.c",
+ "src/qs8-igemm/gen/4x4c2-minmax-fp32-sse41-ld64.c",
+ "src/qs8-igemm/gen/4x4c2-minmax-fp32-sse41-ld128.c",
"src/qs8-requantization/fp32-sse4.c",
- "src/qs8-requantization/precise-sse4.c",
- "src/qs8-requantization/q31-sse4.c",
+ "src/qs8-requantization/gemmlowp-sse4.c",
+ "src/qs8-requantization/rndna-sse4.c",
+ "src/qs8-requantization/rndnu-sse4-sra.c",
+ "src/qs8-requantization/rndnu-sse4-srl.c",
"src/qs8-vadd/gen/minmax-sse41-mul16-ld64-x8.c",
"src/qs8-vadd/gen/minmax-sse41-mul16-ld64-x16.c",
"src/qs8-vadd/gen/minmax-sse41-mul16-ld64-x24.c",
@@ -1864,25 +5506,181 @@
"src/qs8-vaddc/gen/minmax-sse41-mul32-ld32-x16.c",
"src/qs8-vaddc/gen/minmax-sse41-mul32-ld32-x24.c",
"src/qs8-vaddc/gen/minmax-sse41-mul32-ld32-x32.c",
- "src/qu8-requantization/precise-sse4.c",
- "src/qu8-requantization/q31-sse4.c",
+ "src/qs8-vmul/gen/minmax-fp32-sse41-mul16-ld64-x8.c",
+ "src/qs8-vmul/gen/minmax-fp32-sse41-mul16-ld64-x16.c",
+ "src/qs8-vmulc/gen/minmax-fp32-sse41-mul16-ld64-x8.c",
+ "src/qs8-vmulc/gen/minmax-fp32-sse41-mul16-ld64-x16.c",
+ "src/qu8-dwconv/gen/up8x9-minmax-fp32-sse41-mul16.c",
+ "src/qu8-dwconv/gen/up8x9-minmax-fp32-sse41-mul32.c",
+ "src/qu8-dwconv/gen/up8x25-minmax-fp32-sse41-mul16.c",
+ "src/qu8-dwconv/gen/up8x25-minmax-fp32-sse41-mul32.c",
+ "src/qu8-dwconv/gen/up16x9-minmax-fp32-sse41-mul16.c",
+ "src/qu8-dwconv/gen/up16x9-minmax-fp32-sse41-mul32.c",
+ "src/qu8-dwconv/gen/up16x25-minmax-fp32-sse41-mul16.c",
+ "src/qu8-dwconv/gen/up16x25-minmax-fp32-sse41-mul32.c",
+ "src/qu8-f32-vcvt/gen/vcvt-sse41-x8.c",
+ "src/qu8-f32-vcvt/gen/vcvt-sse41-x16.c",
+ "src/qu8-f32-vcvt/gen/vcvt-sse41-x24.c",
+ "src/qu8-f32-vcvt/gen/vcvt-sse41-x32.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-sse41-c8.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-sse41-c16.c",
+ "src/qu8-gavgpool/gen/7p7x-minmax-fp32-sse41-c24.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-sse41-c8.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-sse41-c16.c",
+ "src/qu8-gavgpool/gen/7x-minmax-fp32-sse41-c24.c",
+ "src/qu8-gemm/gen/1x4c2-minmax-fp32-sse41-ld64.c",
+ "src/qu8-gemm/gen/1x4c2-minmax-fp32-sse41-ld128.c",
+ "src/qu8-gemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qu8-gemm/gen/1x4c8-minmax-fp32-sse41-ld128.c",
+ "src/qu8-gemm/gen/2x4c2-minmax-fp32-sse41-ld64.c",
+ "src/qu8-gemm/gen/2x4c2-minmax-fp32-sse41-ld128.c",
+ "src/qu8-gemm/gen/2x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qu8-gemm/gen/2x4c8-minmax-fp32-sse41-ld128.c",
+ "src/qu8-gemm/gen/3x4c2-minmax-fp32-sse41-ld64.c",
+ "src/qu8-gemm/gen/3x4c2-minmax-fp32-sse41-ld128.c",
+ "src/qu8-gemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qu8-gemm/gen/3x4c8-minmax-fp32-sse41-ld128.c",
+ "src/qu8-gemm/gen/4x4c2-minmax-fp32-sse41-ld64.c",
+ "src/qu8-gemm/gen/4x4c2-minmax-fp32-sse41-ld128.c",
+ "src/qu8-igemm/gen/1x4c2-minmax-fp32-sse41-ld64.c",
+ "src/qu8-igemm/gen/1x4c2-minmax-fp32-sse41-ld128.c",
+ "src/qu8-igemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qu8-igemm/gen/1x4c8-minmax-fp32-sse41-ld128.c",
+ "src/qu8-igemm/gen/2x4c2-minmax-fp32-sse41-ld64.c",
+ "src/qu8-igemm/gen/2x4c2-minmax-fp32-sse41-ld128.c",
+ "src/qu8-igemm/gen/2x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qu8-igemm/gen/2x4c8-minmax-fp32-sse41-ld128.c",
+ "src/qu8-igemm/gen/3x4c2-minmax-fp32-sse41-ld64.c",
+ "src/qu8-igemm/gen/3x4c2-minmax-fp32-sse41-ld128.c",
+ "src/qu8-igemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
+ "src/qu8-igemm/gen/3x4c8-minmax-fp32-sse41-ld128.c",
+ "src/qu8-igemm/gen/4x4c2-minmax-fp32-sse41-ld64.c",
+ "src/qu8-igemm/gen/4x4c2-minmax-fp32-sse41-ld128.c",
+ "src/qu8-requantization/gemmlowp-sse4.c",
+ "src/qu8-requantization/rndna-sse4.c",
+ "src/qu8-vadd/gen/minmax-sse41-mul16-ld64-x8.c",
+ "src/qu8-vadd/gen/minmax-sse41-mul16-ld64-x16.c",
+ "src/qu8-vadd/gen/minmax-sse41-mul32-ld32-x8.c",
+ "src/qu8-vadd/gen/minmax-sse41-mul32-ld32-x16.c",
+ "src/qu8-vaddc/gen/minmax-sse41-mul16-ld64-x8.c",
+ "src/qu8-vaddc/gen/minmax-sse41-mul16-ld64-x16.c",
+ "src/qu8-vaddc/gen/minmax-sse41-mul32-ld32-x8.c",
+ "src/qu8-vaddc/gen/minmax-sse41-mul32-ld32-x16.c",
+ "src/qu8-vmul/gen/minmax-fp32-sse41-mul16-ld64-x8.c",
+ "src/qu8-vmul/gen/minmax-fp32-sse41-mul16-ld64-x16.c",
+ "src/qu8-vmulc/gen/minmax-fp32-sse41-mul16-ld64-x8.c",
+ "src/qu8-vmulc/gen/minmax-fp32-sse41-mul16-ld64-x16.c",
+ "src/s8-ibilinear/gen/sse41-c8.c",
+ "src/s8-ibilinear/gen/sse41-c16.c",
+ "src/s8-maxpool/9p8x-minmax-sse41-c16.c",
+ "src/s8-vclamp/sse41-x64.c",
+ "src/u8-ibilinear/gen/sse41-c8.c",
+ "src/u8-ibilinear/gen/sse41-c16.c",
]
-AVX_UKERNELS = [
- "src/f32-clamp/gen/avx-x8.c",
- "src/f32-clamp/gen/avx-x16.c",
+PROD_AVX_MICROKERNEL_SRCS = [
+ "src/f16-f32-vcvt/gen/vcvt-avx-int16-x16.c",
+ "src/f32-dwconv/gen/up8x25-minmax-avx.c",
+ "src/f32-dwconv/gen/up16x3-minmax-avx.c",
+ "src/f32-dwconv/gen/up16x4-minmax-avx.c",
+ "src/f32-dwconv/gen/up16x9-minmax-avx.c",
+ "src/f32-f16-vcvt/gen/vcvt-avx-x24.c",
+ "src/f32-gemm/gen/1x16-minmax-avx-broadcast.c",
+ "src/f32-gemm/gen/5x16-minmax-avx-broadcast.c",
+ "src/f32-igemm/gen/1x16-minmax-avx-broadcast.c",
+ "src/f32-igemm/gen/5x16-minmax-avx-broadcast.c",
+ "src/f32-prelu/gen/avx-2x16.c",
+ "src/f32-qs8-vcvt/gen/vcvt-avx-x32.c",
+ "src/f32-qu8-vcvt/gen/vcvt-avx-x32.c",
+ "src/f32-vbinary/gen/vadd-minmax-avx-x16.c",
+ "src/f32-vbinary/gen/vaddc-minmax-avx-x16.c",
+ "src/f32-vbinary/gen/vdiv-minmax-avx-x16.c",
+ "src/f32-vbinary/gen/vdivc-minmax-avx-x16.c",
+ "src/f32-vbinary/gen/vmax-avx-x16.c",
+ "src/f32-vbinary/gen/vmaxc-avx-x16.c",
+ "src/f32-vbinary/gen/vmin-avx-x16.c",
+ "src/f32-vbinary/gen/vminc-avx-x16.c",
+ "src/f32-vbinary/gen/vmul-minmax-avx-x16.c",
+ "src/f32-vbinary/gen/vmulc-minmax-avx-x16.c",
+ "src/f32-vbinary/gen/vrdivc-minmax-avx-x16.c",
+ "src/f32-vbinary/gen/vrsubc-minmax-avx-x16.c",
+ "src/f32-vbinary/gen/vsqrdiff-avx-x16.c",
+ "src/f32-vbinary/gen/vsqrdiffc-avx-x16.c",
+ "src/f32-vbinary/gen/vsub-minmax-avx-x16.c",
+ "src/f32-vbinary/gen/vsubc-minmax-avx-x16.c",
+ "src/f32-vclamp/gen/vclamp-avx-x16.c",
+ "src/f32-velu/gen/velu-avx-rr2-lut4-p4-perm-x32.c",
+ "src/f32-vhswish/gen/vhswish-avx-x16.c",
+ "src/f32-vlrelu/gen/vlrelu-avx-x16.c",
+ "src/f32-vrnd/gen/vrndd-avx-x16.c",
+ "src/f32-vrnd/gen/vrndne-avx-x16.c",
+ "src/f32-vrnd/gen/vrndu-avx-x16.c",
+ "src/f32-vrnd/gen/vrndz-avx-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x40.c",
+ "src/f32-vsqrt/gen/avx-sqrt-x8.c",
+ "src/f32-vunary/gen/vabs-avx-x16.c",
+ "src/f32-vunary/gen/vneg-avx-x16.c",
+ "src/f32-vunary/gen/vsqr-avx-x16.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx-mul16-add16.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx-mul16-add16.c",
+ "src/qc8-gemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
+ "src/qc8-gemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
+ "src/qc8-igemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
+ "src/qc8-igemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
+ "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx-mul16-add16.c",
+ "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx-mul16-add16.c",
+ "src/qs8-f32-vcvt/gen/vcvt-avx-x32.c",
+ "src/qs8-gemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
+ "src/qs8-gemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
+ "src/qs8-igemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
+ "src/qs8-igemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
+ "src/qs8-vadd/gen/minmax-avx-mul32-ld32-x8.c",
+ "src/qs8-vaddc/gen/minmax-avx-mul32-ld32-x8.c",
+ "src/qs8-vmul/gen/minmax-fp32-avx-mul16-ld64-x16.c",
+ "src/qs8-vmulc/gen/minmax-fp32-avx-mul16-ld64-x16.c",
+ "src/qu8-dwconv/gen/up16x9-minmax-fp32-avx-mul16.c",
+ "src/qu8-dwconv/gen/up16x25-minmax-fp32-avx-mul16.c",
+ "src/qu8-f32-vcvt/gen/vcvt-avx-x32.c",
+ "src/qu8-gemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
+ "src/qu8-gemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
+ "src/qu8-igemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
+ "src/qu8-igemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
+ "src/qu8-vadd/gen/minmax-avx-mul32-ld32-x8.c",
+ "src/qu8-vaddc/gen/minmax-avx-mul32-ld32-x8.c",
+ "src/qu8-vmul/gen/minmax-fp32-avx-mul16-ld64-x16.c",
+ "src/qu8-vmulc/gen/minmax-fp32-avx-mul16-ld64-x16.c",
+ "src/x8-lut/gen/lut-avx-x64.c",
+]
+
+ALL_AVX_MICROKERNEL_SRCS = [
+ "src/f16-f32-vcvt/gen/vcvt-avx-int16-x8.c",
+ "src/f16-f32-vcvt/gen/vcvt-avx-int16-x16.c",
+ "src/f16-f32-vcvt/gen/vcvt-avx-int16-x24.c",
+ "src/f16-f32-vcvt/gen/vcvt-avx-int16-x32.c",
+ "src/f16-f32-vcvt/gen/vcvt-avx-int32-x8.c",
+ "src/f16-f32-vcvt/gen/vcvt-avx-int32-x16.c",
+ "src/f16-f32-vcvt/gen/vcvt-avx-int32-x24.c",
+ "src/f16-f32-vcvt/gen/vcvt-avx-int32-x32.c",
+ "src/f32-dwconv/gen/up8x3-minmax-avx-acc2.c",
+ "src/f32-dwconv/gen/up8x3-minmax-avx.c",
"src/f32-dwconv/gen/up8x4-minmax-avx-acc2.c",
"src/f32-dwconv/gen/up8x4-minmax-avx.c",
"src/f32-dwconv/gen/up8x9-minmax-avx-acc2.c",
"src/f32-dwconv/gen/up8x9-minmax-avx.c",
"src/f32-dwconv/gen/up8x25-minmax-avx-acc2.c",
"src/f32-dwconv/gen/up8x25-minmax-avx.c",
+ "src/f32-dwconv/gen/up16x3-minmax-avx-acc2.c",
+ "src/f32-dwconv/gen/up16x3-minmax-avx.c",
"src/f32-dwconv/gen/up16x4-minmax-avx-acc2.c",
"src/f32-dwconv/gen/up16x4-minmax-avx.c",
"src/f32-dwconv/gen/up16x9-minmax-avx-acc2.c",
"src/f32-dwconv/gen/up16x9-minmax-avx.c",
"src/f32-dwconv/gen/up16x25-minmax-avx-acc2.c",
"src/f32-dwconv/gen/up16x25-minmax-avx.c",
+ "src/f32-f16-vcvt/gen/vcvt-avx-x8.c",
+ "src/f32-f16-vcvt/gen/vcvt-avx-x16.c",
+ "src/f32-f16-vcvt/gen/vcvt-avx-x24.c",
+ "src/f32-f16-vcvt/gen/vcvt-avx-x32.c",
"src/f32-gemm/gen-inc/1x8inc-minmax-avx-broadcast.c",
"src/f32-gemm/gen-inc/1x16inc-minmax-avx-broadcast.c",
"src/f32-gemm/gen-inc/3x16inc-minmax-avx-broadcast.c",
@@ -1901,8 +5699,6 @@
"src/f32-gemm/gen/5x16-minmax-avx-broadcast.c",
"src/f32-gemm/gen/6x8-minmax-avx-broadcast.c",
"src/f32-gemm/gen/7x8-minmax-avx-broadcast.c",
- "src/f32-hswish/gen/hswish-avx-x8.c",
- "src/f32-hswish/gen/hswish-avx-x16.c",
"src/f32-igemm/gen/1x8-minmax-avx-broadcast.c",
"src/f32-igemm/gen/1x16-minmax-avx-broadcast.c",
"src/f32-igemm/gen/3x16-minmax-avx-broadcast.c",
@@ -1914,29 +5710,15 @@
"src/f32-igemm/gen/7x8-minmax-avx-broadcast.c",
"src/f32-prelu/gen/avx-2x8.c",
"src/f32-prelu/gen/avx-2x16.c",
- "src/f32-relu/gen/avx-x8.c",
- "src/f32-relu/gen/avx-x16.c",
+ "src/f32-qs8-vcvt/gen/vcvt-avx-x8.c",
+ "src/f32-qs8-vcvt/gen/vcvt-avx-x16.c",
+ "src/f32-qs8-vcvt/gen/vcvt-avx-x24.c",
+ "src/f32-qs8-vcvt/gen/vcvt-avx-x32.c",
+ "src/f32-qu8-vcvt/gen/vcvt-avx-x8.c",
+ "src/f32-qu8-vcvt/gen/vcvt-avx-x16.c",
+ "src/f32-qu8-vcvt/gen/vcvt-avx-x24.c",
+ "src/f32-qu8-vcvt/gen/vcvt-avx-x32.c",
"src/f32-rmax/avx.c",
- "src/f32-sigmoid/gen/avx-rr2-p5-div-x8.c",
- "src/f32-sigmoid/gen/avx-rr2-p5-div-x16.c",
- "src/f32-sigmoid/gen/avx-rr2-p5-div-x24.c",
- "src/f32-sigmoid/gen/avx-rr2-p5-div-x32.c",
- "src/f32-sigmoid/gen/avx-rr2-p5-div-x40.c",
- "src/f32-sigmoid/gen/avx-rr2-p5-div-x48.c",
- "src/f32-sigmoid/gen/avx-rr2-p5-div-x56.c",
- "src/f32-sigmoid/gen/avx-rr2-p5-div-x64.c",
- "src/f32-sigmoid/gen/avx-rr2-p5-div-x72.c",
- "src/f32-sigmoid/gen/avx-rr2-p5-div-x80.c",
- "src/f32-sigmoid/gen/avx-rr2-p5-nr2-x8.c",
- "src/f32-sigmoid/gen/avx-rr2-p5-nr2-x16.c",
- "src/f32-sigmoid/gen/avx-rr2-p5-nr2-x24.c",
- "src/f32-sigmoid/gen/avx-rr2-p5-nr2-x32.c",
- "src/f32-sigmoid/gen/avx-rr2-p5-nr2-x40.c",
- "src/f32-sigmoid/gen/avx-rr2-p5-nr2-x48.c",
- "src/f32-sigmoid/gen/avx-rr2-p5-nr2-x56.c",
- "src/f32-sigmoid/gen/avx-rr2-p5-nr2-x64.c",
- "src/f32-sigmoid/gen/avx-rr2-p5-nr2-x72.c",
- "src/f32-sigmoid/gen/avx-rr2-p5-nr2-x80.c",
"src/f32-vbinary/gen/vadd-minmax-avx-x8.c",
"src/f32-vbinary/gen/vadd-minmax-avx-x16.c",
"src/f32-vbinary/gen/vaddc-minmax-avx-x8.c",
@@ -1969,6 +5751,8 @@
"src/f32-vbinary/gen/vsub-minmax-avx-x16.c",
"src/f32-vbinary/gen/vsubc-minmax-avx-x8.c",
"src/f32-vbinary/gen/vsubc-minmax-avx-x16.c",
+ "src/f32-vclamp/gen/vclamp-avx-x8.c",
+ "src/f32-vclamp/gen/vclamp-avx-x16.c",
"src/f32-velu/gen/velu-avx-rr2-lut4-p4-perm-x8.c",
"src/f32-velu/gen/velu-avx-rr2-lut4-p4-perm-x16.c",
"src/f32-velu/gen/velu-avx-rr2-lut4-p4-perm-x24.c",
@@ -1987,8 +5771,12 @@
"src/f32-velu/gen/velu-avx-rr2-p6-x32.c",
"src/f32-velu/gen/velu-avx-rr2-p6-x40.c",
"src/f32-velu/gen/velu-avx-rr2-p6-x48.c",
+ "src/f32-vhswish/gen/vhswish-avx-x8.c",
+ "src/f32-vhswish/gen/vhswish-avx-x16.c",
"src/f32-vlrelu/gen/vlrelu-avx-x8.c",
"src/f32-vlrelu/gen/vlrelu-avx-x16.c",
+ "src/f32-vrelu/gen/vrelu-avx-x8.c",
+ "src/f32-vrelu/gen/vrelu-avx-x16.c",
"src/f32-vrnd/gen/vrndd-avx-x8.c",
"src/f32-vrnd/gen/vrndd-avx-x16.c",
"src/f32-vrnd/gen/vrndne-avx-x8.c",
@@ -1997,7 +5785,26 @@
"src/f32-vrnd/gen/vrndu-avx-x16.c",
"src/f32-vrnd/gen/vrndz-avx-x8.c",
"src/f32-vrnd/gen/vrndz-avx-x16.c",
- "src/f32-vscale/avx-x32.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x24.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x32.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x40.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x48.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x56.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x64.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x72.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x80.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x24.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x32.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x40.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x48.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x56.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x64.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x72.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x80.c",
"src/f32-vsqrt/gen/avx-sqrt-x8.c",
"src/f32-vsqrt/gen/avx-sqrt-x16.c",
"src/f32-vunary/gen/vabs-avx-x8.c",
@@ -2014,34 +5821,358 @@
"src/math/sigmoid-avx-rr2-p5-div.c",
"src/math/sigmoid-avx-rr2-p5-nr1.c",
"src/math/sigmoid-avx-rr2-p5-nr2.c",
+ "src/qc8-dwconv/gen/up8x9-minmax-fp32-avx-mul16-add16.c",
+ "src/qc8-dwconv/gen/up8x9-minmax-fp32-avx-mul16.c",
+ "src/qc8-dwconv/gen/up8x9-minmax-fp32-avx-mul32.c",
+ "src/qc8-dwconv/gen/up8x25-minmax-fp32-avx-mul16-add16.c",
+ "src/qc8-dwconv/gen/up8x25-minmax-fp32-avx-mul16.c",
+ "src/qc8-dwconv/gen/up8x25-minmax-fp32-avx-mul32.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx-mul16-add16.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx-mul16.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx-mul32.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx-mul16-add16.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx-mul16.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx-mul32.c",
+ "src/qc8-dwconv/gen/up24x9-minmax-fp32-avx-mul16.c",
+ "src/qc8-dwconv/gen/up24x9-minmax-fp32-avx-mul32.c",
+ "src/qc8-dwconv/gen/up24x25-minmax-fp32-avx-mul16.c",
+ "src/qc8-dwconv/gen/up24x25-minmax-fp32-avx-mul32.c",
+ "src/qc8-gemm/gen/1x4c2-minmax-fp32-avx-ld64.c",
+ "src/qc8-gemm/gen/1x4c2-minmax-fp32-avx-ld128.c",
+ "src/qc8-gemm/gen/1x4c8-minmax-fp32-avx-ld64.c",
+ "src/qc8-gemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
+ "src/qc8-gemm/gen/2x4c2-minmax-fp32-avx-ld64.c",
+ "src/qc8-gemm/gen/2x4c2-minmax-fp32-avx-ld128.c",
+ "src/qc8-gemm/gen/2x4c8-minmax-fp32-avx-ld64.c",
+ "src/qc8-gemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
+ "src/qc8-gemm/gen/3x4c2-minmax-fp32-avx-ld64.c",
+ "src/qc8-gemm/gen/3x4c2-minmax-fp32-avx-ld128.c",
+ "src/qc8-gemm/gen/3x4c8-minmax-fp32-avx-ld64.c",
+ "src/qc8-gemm/gen/3x4c8-minmax-fp32-avx-ld128.c",
+ "src/qc8-gemm/gen/4x4c2-minmax-fp32-avx-ld64.c",
+ "src/qc8-gemm/gen/4x4c2-minmax-fp32-avx-ld128.c",
+ "src/qc8-igemm/gen/1x4c2-minmax-fp32-avx-ld64.c",
+ "src/qc8-igemm/gen/1x4c2-minmax-fp32-avx-ld128.c",
+ "src/qc8-igemm/gen/1x4c8-minmax-fp32-avx-ld64.c",
+ "src/qc8-igemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
+ "src/qc8-igemm/gen/2x4c2-minmax-fp32-avx-ld64.c",
+ "src/qc8-igemm/gen/2x4c2-minmax-fp32-avx-ld128.c",
+ "src/qc8-igemm/gen/2x4c8-minmax-fp32-avx-ld64.c",
+ "src/qc8-igemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
+ "src/qc8-igemm/gen/3x4c2-minmax-fp32-avx-ld64.c",
+ "src/qc8-igemm/gen/3x4c2-minmax-fp32-avx-ld128.c",
+ "src/qc8-igemm/gen/3x4c8-minmax-fp32-avx-ld64.c",
+ "src/qc8-igemm/gen/3x4c8-minmax-fp32-avx-ld128.c",
+ "src/qc8-igemm/gen/4x4c2-minmax-fp32-avx-ld64.c",
+ "src/qc8-igemm/gen/4x4c2-minmax-fp32-avx-ld128.c",
+ "src/qs8-dwconv/gen/up8x9-minmax-fp32-avx-mul16-add16.c",
+ "src/qs8-dwconv/gen/up8x9-minmax-fp32-avx-mul16.c",
+ "src/qs8-dwconv/gen/up8x9-minmax-fp32-avx-mul32.c",
+ "src/qs8-dwconv/gen/up8x25-minmax-fp32-avx-mul16-add16.c",
+ "src/qs8-dwconv/gen/up8x25-minmax-fp32-avx-mul16.c",
+ "src/qs8-dwconv/gen/up8x25-minmax-fp32-avx-mul32.c",
+ "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx-mul16-add16.c",
+ "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx-mul16.c",
+ "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx-mul32.c",
+ "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx-mul16-add16.c",
+ "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx-mul16.c",
+ "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx-mul32.c",
+ "src/qs8-dwconv/gen/up24x9-minmax-fp32-avx-mul16.c",
+ "src/qs8-dwconv/gen/up24x9-minmax-fp32-avx-mul32.c",
+ "src/qs8-dwconv/gen/up24x25-minmax-fp32-avx-mul16.c",
+ "src/qs8-dwconv/gen/up24x25-minmax-fp32-avx-mul32.c",
+ "src/qs8-f32-vcvt/gen/vcvt-avx-x8.c",
+ "src/qs8-f32-vcvt/gen/vcvt-avx-x16.c",
+ "src/qs8-f32-vcvt/gen/vcvt-avx-x24.c",
+ "src/qs8-f32-vcvt/gen/vcvt-avx-x32.c",
+ "src/qs8-gemm/gen/1x4c2-minmax-fp32-avx-ld64.c",
+ "src/qs8-gemm/gen/1x4c2-minmax-fp32-avx-ld128.c",
+ "src/qs8-gemm/gen/1x4c2-xw-minmax-fp32-avx.c",
+ "src/qs8-gemm/gen/1x4c8-minmax-fp32-avx-ld64.c",
+ "src/qs8-gemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
+ "src/qs8-gemm/gen/1x4c8-xw-minmax-fp32-avx.c",
+ "src/qs8-gemm/gen/2x4c2-minmax-fp32-avx-ld64.c",
+ "src/qs8-gemm/gen/2x4c2-minmax-fp32-avx-ld128.c",
+ "src/qs8-gemm/gen/2x4c2-xw-minmax-fp32-avx.c",
+ "src/qs8-gemm/gen/2x4c8-minmax-fp32-avx-ld64.c",
+ "src/qs8-gemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
+ "src/qs8-gemm/gen/2x4c8-xw-minmax-fp32-avx.c",
+ "src/qs8-gemm/gen/3x4c2-minmax-fp32-avx-ld64.c",
+ "src/qs8-gemm/gen/3x4c2-minmax-fp32-avx-ld128.c",
+ "src/qs8-gemm/gen/3x4c2-xw-minmax-fp32-avx.c",
+ "src/qs8-gemm/gen/3x4c8-minmax-fp32-avx-ld64.c",
+ "src/qs8-gemm/gen/3x4c8-minmax-fp32-avx-ld128.c",
+ "src/qs8-gemm/gen/3x4c8-xw-minmax-fp32-avx.c",
+ "src/qs8-gemm/gen/4x4c2-minmax-fp32-avx-ld64.c",
+ "src/qs8-gemm/gen/4x4c2-minmax-fp32-avx-ld128.c",
+ "src/qs8-gemm/gen/4x4c2-xw-minmax-fp32-avx.c",
+ "src/qs8-igemm/gen/1x4c2-minmax-fp32-avx-ld64.c",
+ "src/qs8-igemm/gen/1x4c2-minmax-fp32-avx-ld128.c",
+ "src/qs8-igemm/gen/1x4c8-minmax-fp32-avx-ld64.c",
+ "src/qs8-igemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
+ "src/qs8-igemm/gen/2x4c2-minmax-fp32-avx-ld64.c",
+ "src/qs8-igemm/gen/2x4c2-minmax-fp32-avx-ld128.c",
+ "src/qs8-igemm/gen/2x4c8-minmax-fp32-avx-ld64.c",
+ "src/qs8-igemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
+ "src/qs8-igemm/gen/3x4c2-minmax-fp32-avx-ld64.c",
+ "src/qs8-igemm/gen/3x4c2-minmax-fp32-avx-ld128.c",
+ "src/qs8-igemm/gen/3x4c8-minmax-fp32-avx-ld64.c",
+ "src/qs8-igemm/gen/3x4c8-minmax-fp32-avx-ld128.c",
+ "src/qs8-igemm/gen/4x4c2-minmax-fp32-avx-ld64.c",
+ "src/qs8-igemm/gen/4x4c2-minmax-fp32-avx-ld128.c",
+ "src/qs8-vadd/gen/minmax-avx-mul16-ld64-x8.c",
+ "src/qs8-vadd/gen/minmax-avx-mul16-ld64-x16.c",
+ "src/qs8-vadd/gen/minmax-avx-mul16-ld64-x24.c",
+ "src/qs8-vadd/gen/minmax-avx-mul16-ld64-x32.c",
+ "src/qs8-vadd/gen/minmax-avx-mul32-ld32-x8.c",
+ "src/qs8-vadd/gen/minmax-avx-mul32-ld32-x16.c",
+ "src/qs8-vadd/gen/minmax-avx-mul32-ld32-x24.c",
+ "src/qs8-vadd/gen/minmax-avx-mul32-ld32-x32.c",
+ "src/qs8-vaddc/gen/minmax-avx-mul16-ld64-x8.c",
+ "src/qs8-vaddc/gen/minmax-avx-mul16-ld64-x16.c",
+ "src/qs8-vaddc/gen/minmax-avx-mul16-ld64-x24.c",
+ "src/qs8-vaddc/gen/minmax-avx-mul16-ld64-x32.c",
+ "src/qs8-vaddc/gen/minmax-avx-mul32-ld32-x8.c",
+ "src/qs8-vaddc/gen/minmax-avx-mul32-ld32-x16.c",
+ "src/qs8-vaddc/gen/minmax-avx-mul32-ld32-x24.c",
+ "src/qs8-vaddc/gen/minmax-avx-mul32-ld32-x32.c",
+ "src/qs8-vmul/gen/minmax-fp32-avx-mul16-ld64-x8.c",
+ "src/qs8-vmul/gen/minmax-fp32-avx-mul16-ld64-x16.c",
+ "src/qs8-vmulc/gen/minmax-fp32-avx-mul16-ld64-x8.c",
+ "src/qs8-vmulc/gen/minmax-fp32-avx-mul16-ld64-x16.c",
+ "src/qu8-dwconv/gen/up8x9-minmax-fp32-avx-mul16.c",
+ "src/qu8-dwconv/gen/up8x9-minmax-fp32-avx-mul32.c",
+ "src/qu8-dwconv/gen/up8x25-minmax-fp32-avx-mul16.c",
+ "src/qu8-dwconv/gen/up8x25-minmax-fp32-avx-mul32.c",
+ "src/qu8-dwconv/gen/up16x9-minmax-fp32-avx-mul16.c",
+ "src/qu8-dwconv/gen/up16x9-minmax-fp32-avx-mul32.c",
+ "src/qu8-dwconv/gen/up16x25-minmax-fp32-avx-mul16.c",
+ "src/qu8-dwconv/gen/up16x25-minmax-fp32-avx-mul32.c",
+ "src/qu8-f32-vcvt/gen/vcvt-avx-x8.c",
+ "src/qu8-f32-vcvt/gen/vcvt-avx-x16.c",
+ "src/qu8-f32-vcvt/gen/vcvt-avx-x24.c",
+ "src/qu8-f32-vcvt/gen/vcvt-avx-x32.c",
+ "src/qu8-gemm/gen/1x4c2-minmax-fp32-avx-ld64.c",
+ "src/qu8-gemm/gen/1x4c2-minmax-fp32-avx-ld128.c",
+ "src/qu8-gemm/gen/1x4c8-minmax-fp32-avx-ld64.c",
+ "src/qu8-gemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
+ "src/qu8-gemm/gen/2x4c2-minmax-fp32-avx-ld64.c",
+ "src/qu8-gemm/gen/2x4c2-minmax-fp32-avx-ld128.c",
+ "src/qu8-gemm/gen/2x4c8-minmax-fp32-avx-ld64.c",
+ "src/qu8-gemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
+ "src/qu8-gemm/gen/3x4c2-minmax-fp32-avx-ld64.c",
+ "src/qu8-gemm/gen/3x4c2-minmax-fp32-avx-ld128.c",
+ "src/qu8-gemm/gen/3x4c8-minmax-fp32-avx-ld64.c",
+ "src/qu8-gemm/gen/3x4c8-minmax-fp32-avx-ld128.c",
+ "src/qu8-gemm/gen/4x4c2-minmax-fp32-avx-ld64.c",
+ "src/qu8-gemm/gen/4x4c2-minmax-fp32-avx-ld128.c",
+ "src/qu8-igemm/gen/1x4c2-minmax-fp32-avx-ld64.c",
+ "src/qu8-igemm/gen/1x4c2-minmax-fp32-avx-ld128.c",
+ "src/qu8-igemm/gen/1x4c8-minmax-fp32-avx-ld64.c",
+ "src/qu8-igemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
+ "src/qu8-igemm/gen/2x4c2-minmax-fp32-avx-ld64.c",
+ "src/qu8-igemm/gen/2x4c2-minmax-fp32-avx-ld128.c",
+ "src/qu8-igemm/gen/2x4c8-minmax-fp32-avx-ld64.c",
+ "src/qu8-igemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
+ "src/qu8-igemm/gen/3x4c2-minmax-fp32-avx-ld64.c",
+ "src/qu8-igemm/gen/3x4c2-minmax-fp32-avx-ld128.c",
+ "src/qu8-igemm/gen/3x4c8-minmax-fp32-avx-ld64.c",
+ "src/qu8-igemm/gen/3x4c8-minmax-fp32-avx-ld128.c",
+ "src/qu8-igemm/gen/4x4c2-minmax-fp32-avx-ld64.c",
+ "src/qu8-igemm/gen/4x4c2-minmax-fp32-avx-ld128.c",
+ "src/qu8-vadd/gen/minmax-avx-mul16-ld64-x8.c",
+ "src/qu8-vadd/gen/minmax-avx-mul16-ld64-x16.c",
+ "src/qu8-vadd/gen/minmax-avx-mul32-ld32-x8.c",
+ "src/qu8-vadd/gen/minmax-avx-mul32-ld32-x16.c",
+ "src/qu8-vaddc/gen/minmax-avx-mul16-ld64-x8.c",
+ "src/qu8-vaddc/gen/minmax-avx-mul16-ld64-x16.c",
+ "src/qu8-vaddc/gen/minmax-avx-mul32-ld32-x8.c",
+ "src/qu8-vaddc/gen/minmax-avx-mul32-ld32-x16.c",
+ "src/qu8-vmul/gen/minmax-fp32-avx-mul16-ld64-x8.c",
+ "src/qu8-vmul/gen/minmax-fp32-avx-mul16-ld64-x16.c",
+ "src/qu8-vmulc/gen/minmax-fp32-avx-mul16-ld64-x8.c",
+ "src/qu8-vmulc/gen/minmax-fp32-avx-mul16-ld64-x16.c",
+ "src/x8-lut/gen/lut-avx-x16.c",
+ "src/x8-lut/gen/lut-avx-x32.c",
+ "src/x8-lut/gen/lut-avx-x48.c",
+ "src/x8-lut/gen/lut-avx-x64.c",
]
-XOP_UKERNELS = [
- "src/qs8-gemm/gen/1x4c2-minmax-xop-ld64.c",
- "src/qs8-gemm/gen/1x4c2-minmax-xop-ld128.c",
- "src/qs8-gemm/gen/1x4c2-xw-minmax-xop.c",
- "src/qs8-gemm/gen/1x4c8-minmax-xop-ld64.c",
- "src/qs8-gemm/gen/1x4c8-minmax-xop-ld128.c",
- "src/qs8-gemm/gen/1x4c8-xw-minmax-xop.c",
- "src/qs8-gemm/gen/2x4c8-minmax-xop-ld64.c",
- "src/qs8-gemm/gen/2x4c8-minmax-xop-ld128.c",
- "src/qs8-gemm/gen/2x4c8-xw-minmax-xop.c",
- "src/qs8-gemm/gen/3x4c8-minmax-xop-ld64.c",
- "src/qs8-gemm/gen/3x4c8-minmax-xop-ld128.c",
- "src/qs8-gemm/gen/3x4c8-xw-minmax-xop.c",
- "src/qs8-gemm/gen/4x4c2-minmax-xop-ld64.c",
- "src/qs8-gemm/gen/4x4c2-minmax-xop-ld128.c",
- "src/qs8-gemm/gen/4x4c2-xw-minmax-xop.c",
- "src/qs8-igemm/gen/1x4c2-minmax-xop-ld64.c",
- "src/qs8-igemm/gen/1x4c2-minmax-xop-ld128.c",
- "src/qs8-igemm/gen/1x4c8-minmax-xop-ld64.c",
- "src/qs8-igemm/gen/1x4c8-minmax-xop-ld128.c",
- "src/qs8-igemm/gen/2x4c8-minmax-xop-ld64.c",
- "src/qs8-igemm/gen/2x4c8-minmax-xop-ld128.c",
- "src/qs8-igemm/gen/3x4c8-minmax-xop-ld64.c",
- "src/qs8-igemm/gen/3x4c8-minmax-xop-ld128.c",
- "src/qs8-igemm/gen/4x4c2-minmax-xop-ld64.c",
- "src/qs8-igemm/gen/4x4c2-minmax-xop-ld128.c",
+PROD_F16C_MICROKERNEL_SRCS = [
+ "src/f16-f32-vcvt/gen/vcvt-f16c-x16.c",
+ "src/f16-gavgpool/gen/7p7x-minmax-f16c-c8.c",
+ "src/f16-gavgpool/gen/7x-minmax-f16c-c8.c",
+ "src/f16-maxpool/9p8x-minmax-f16c-c8.c",
+ "src/f16-prelu/gen/f16c-2x16.c",
+ "src/f16-vbinary/gen/vadd-minmax-f16c-x16.c",
+ "src/f16-vbinary/gen/vaddc-minmax-f16c-x16.c",
+ "src/f16-vbinary/gen/vmul-minmax-f16c-x16.c",
+ "src/f16-vbinary/gen/vmulc-minmax-f16c-x16.c",
+ "src/f16-vhswish/gen/vhswish-f16c-x16.c",
+ "src/f32-f16-vcvt/gen/vcvt-f16c-x16.c",
+]
+
+ALL_F16C_MICROKERNEL_SRCS = [
+ "src/f16-f32-vcvt/gen/vcvt-f16c-x8.c",
+ "src/f16-f32-vcvt/gen/vcvt-f16c-x16.c",
+ "src/f16-gavgpool/gen/7p7x-minmax-f16c-c8.c",
+ "src/f16-gavgpool/gen/7p7x-minmax-f16c-c16.c",
+ "src/f16-gavgpool/gen/7p7x-minmax-f16c-c24.c",
+ "src/f16-gavgpool/gen/7p7x-minmax-f16c-c32.c",
+ "src/f16-gavgpool/gen/7x-minmax-f16c-c8.c",
+ "src/f16-gavgpool/gen/7x-minmax-f16c-c16.c",
+ "src/f16-gavgpool/gen/7x-minmax-f16c-c24.c",
+ "src/f16-gavgpool/gen/7x-minmax-f16c-c32.c",
+ "src/f16-maxpool/9p8x-minmax-f16c-c8.c",
+ "src/f16-prelu/gen/f16c-2x8.c",
+ "src/f16-prelu/gen/f16c-2x16.c",
+ "src/f16-vbinary/gen/vadd-minmax-f16c-x8.c",
+ "src/f16-vbinary/gen/vadd-minmax-f16c-x16.c",
+ "src/f16-vbinary/gen/vaddc-minmax-f16c-x8.c",
+ "src/f16-vbinary/gen/vaddc-minmax-f16c-x16.c",
+ "src/f16-vbinary/gen/vdiv-minmax-f16c-x8.c",
+ "src/f16-vbinary/gen/vdiv-minmax-f16c-x16.c",
+ "src/f16-vbinary/gen/vdivc-minmax-f16c-x8.c",
+ "src/f16-vbinary/gen/vdivc-minmax-f16c-x16.c",
+ "src/f16-vbinary/gen/vmax-f16c-x8.c",
+ "src/f16-vbinary/gen/vmax-f16c-x16.c",
+ "src/f16-vbinary/gen/vmaxc-f16c-x8.c",
+ "src/f16-vbinary/gen/vmaxc-f16c-x16.c",
+ "src/f16-vbinary/gen/vmin-f16c-x8.c",
+ "src/f16-vbinary/gen/vmin-f16c-x16.c",
+ "src/f16-vbinary/gen/vminc-f16c-x8.c",
+ "src/f16-vbinary/gen/vminc-f16c-x16.c",
+ "src/f16-vbinary/gen/vmul-minmax-f16c-x8.c",
+ "src/f16-vbinary/gen/vmul-minmax-f16c-x16.c",
+ "src/f16-vbinary/gen/vmulc-minmax-f16c-x8.c",
+ "src/f16-vbinary/gen/vmulc-minmax-f16c-x16.c",
+ "src/f16-vbinary/gen/vrdivc-minmax-f16c-x8.c",
+ "src/f16-vbinary/gen/vrdivc-minmax-f16c-x16.c",
+ "src/f16-vbinary/gen/vrsubc-minmax-f16c-x8.c",
+ "src/f16-vbinary/gen/vrsubc-minmax-f16c-x16.c",
+ "src/f16-vbinary/gen/vsub-minmax-f16c-x8.c",
+ "src/f16-vbinary/gen/vsub-minmax-f16c-x16.c",
+ "src/f16-vbinary/gen/vsubc-minmax-f16c-x8.c",
+ "src/f16-vbinary/gen/vsubc-minmax-f16c-x16.c",
+ "src/f16-vclamp/gen/vclamp-f16c-x8.c",
+ "src/f16-vclamp/gen/vclamp-f16c-x16.c",
+ "src/f16-vhswish/gen/vhswish-f16c-x8.c",
+ "src/f16-vhswish/gen/vhswish-f16c-x16.c",
+ "src/f32-f16-vcvt/gen/vcvt-f16c-x8.c",
+ "src/f32-f16-vcvt/gen/vcvt-f16c-x16.c",
+ "src/math/cvt-f16-f32-f16c.c",
+ "src/math/cvt-f32-f16-f16c.c",
+]
+
+PROD_XOP_MICROKERNEL_SRCS = [
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-xop-mul16-add16.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-xop-mul16-add16.c",
+ "src/qc8-gemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
+ "src/qc8-gemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
+ "src/qc8-igemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
+ "src/qc8-igemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
+ "src/qs8-dwconv/gen/up16x9-minmax-fp32-xop-mul16-add16.c",
+ "src/qs8-dwconv/gen/up16x25-minmax-fp32-xop-mul16-add16.c",
+ "src/qs8-gemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
+ "src/qs8-gemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
+ "src/qs8-igemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
+ "src/qs8-igemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
+ "src/qs8-vadd/gen/minmax-xop-mul32-ld32-x8.c",
+ "src/qs8-vaddc/gen/minmax-xop-mul32-ld32-x8.c",
+ "src/qu8-dwconv/gen/up16x9-minmax-fp32-xop-mul32.c",
+ "src/qu8-dwconv/gen/up16x25-minmax-fp32-xop-mul32.c",
+ "src/qu8-gemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
+ "src/qu8-gemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
+ "src/qu8-igemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
+ "src/qu8-igemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
+ "src/qu8-vadd/gen/minmax-xop-mul32-ld32-x8.c",
+ "src/qu8-vaddc/gen/minmax-xop-mul32-ld32-x8.c",
+]
+
+ALL_XOP_MICROKERNEL_SRCS = [
+ "src/qc8-dwconv/gen/up8x9-minmax-fp32-xop-mul16-add16.c",
+ "src/qc8-dwconv/gen/up8x9-minmax-fp32-xop-mul32.c",
+ "src/qc8-dwconv/gen/up8x25-minmax-fp32-xop-mul16-add16.c",
+ "src/qc8-dwconv/gen/up8x25-minmax-fp32-xop-mul32.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-xop-mul16-add16.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-xop-mul32.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-xop-mul16-add16.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-xop-mul32.c",
+ "src/qc8-dwconv/gen/up24x9-minmax-fp32-xop-mul32.c",
+ "src/qc8-dwconv/gen/up24x25-minmax-fp32-xop-mul32.c",
+ "src/qc8-gemm/gen/1x4c2-minmax-fp32-xop-ld64.c",
+ "src/qc8-gemm/gen/1x4c2-minmax-fp32-xop-ld128.c",
+ "src/qc8-gemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
+ "src/qc8-gemm/gen/1x4c8-minmax-fp32-xop-ld128.c",
+ "src/qc8-gemm/gen/2x4c2-minmax-fp32-xop-ld64.c",
+ "src/qc8-gemm/gen/2x4c2-minmax-fp32-xop-ld128.c",
+ "src/qc8-gemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
+ "src/qc8-gemm/gen/2x4c8-minmax-fp32-xop-ld128.c",
+ "src/qc8-gemm/gen/3x4c2-minmax-fp32-xop-ld64.c",
+ "src/qc8-gemm/gen/3x4c2-minmax-fp32-xop-ld128.c",
+ "src/qc8-gemm/gen/3x4c8-minmax-fp32-xop-ld64.c",
+ "src/qc8-gemm/gen/3x4c8-minmax-fp32-xop-ld128.c",
+ "src/qc8-gemm/gen/4x4c2-minmax-fp32-xop-ld64.c",
+ "src/qc8-gemm/gen/4x4c2-minmax-fp32-xop-ld128.c",
+ "src/qc8-igemm/gen/1x4c2-minmax-fp32-xop-ld64.c",
+ "src/qc8-igemm/gen/1x4c2-minmax-fp32-xop-ld128.c",
+ "src/qc8-igemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
+ "src/qc8-igemm/gen/1x4c8-minmax-fp32-xop-ld128.c",
+ "src/qc8-igemm/gen/2x4c2-minmax-fp32-xop-ld64.c",
+ "src/qc8-igemm/gen/2x4c2-minmax-fp32-xop-ld128.c",
+ "src/qc8-igemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
+ "src/qc8-igemm/gen/2x4c8-minmax-fp32-xop-ld128.c",
+ "src/qc8-igemm/gen/3x4c2-minmax-fp32-xop-ld64.c",
+ "src/qc8-igemm/gen/3x4c2-minmax-fp32-xop-ld128.c",
+ "src/qc8-igemm/gen/3x4c8-minmax-fp32-xop-ld64.c",
+ "src/qc8-igemm/gen/3x4c8-minmax-fp32-xop-ld128.c",
+ "src/qc8-igemm/gen/4x4c2-minmax-fp32-xop-ld64.c",
+ "src/qc8-igemm/gen/4x4c2-minmax-fp32-xop-ld128.c",
+ "src/qs8-dwconv/gen/up8x9-minmax-fp32-xop-mul16-add16.c",
+ "src/qs8-dwconv/gen/up8x9-minmax-fp32-xop-mul32.c",
+ "src/qs8-dwconv/gen/up8x25-minmax-fp32-xop-mul16-add16.c",
+ "src/qs8-dwconv/gen/up8x25-minmax-fp32-xop-mul32.c",
+ "src/qs8-dwconv/gen/up16x9-minmax-fp32-xop-mul16-add16.c",
+ "src/qs8-dwconv/gen/up16x9-minmax-fp32-xop-mul32.c",
+ "src/qs8-dwconv/gen/up16x25-minmax-fp32-xop-mul16-add16.c",
+ "src/qs8-dwconv/gen/up16x25-minmax-fp32-xop-mul32.c",
+ "src/qs8-dwconv/gen/up24x9-minmax-fp32-xop-mul32.c",
+ "src/qs8-dwconv/gen/up24x25-minmax-fp32-xop-mul32.c",
+ "src/qs8-gemm/gen/1x4c2-minmax-fp32-xop-ld64.c",
+ "src/qs8-gemm/gen/1x4c2-minmax-fp32-xop-ld128.c",
+ "src/qs8-gemm/gen/1x4c2-xw-minmax-fp32-xop.c",
+ "src/qs8-gemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
+ "src/qs8-gemm/gen/1x4c8-minmax-fp32-xop-ld128.c",
+ "src/qs8-gemm/gen/1x4c8-xw-minmax-fp32-xop.c",
+ "src/qs8-gemm/gen/2x4c2-minmax-fp32-xop-ld64.c",
+ "src/qs8-gemm/gen/2x4c2-minmax-fp32-xop-ld128.c",
+ "src/qs8-gemm/gen/2x4c2-xw-minmax-fp32-xop.c",
+ "src/qs8-gemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
+ "src/qs8-gemm/gen/2x4c8-minmax-fp32-xop-ld128.c",
+ "src/qs8-gemm/gen/2x4c8-xw-minmax-fp32-xop.c",
+ "src/qs8-gemm/gen/3x4c2-minmax-fp32-xop-ld64.c",
+ "src/qs8-gemm/gen/3x4c2-minmax-fp32-xop-ld128.c",
+ "src/qs8-gemm/gen/3x4c2-xw-minmax-fp32-xop.c",
+ "src/qs8-gemm/gen/3x4c8-minmax-fp32-xop-ld64.c",
+ "src/qs8-gemm/gen/3x4c8-minmax-fp32-xop-ld128.c",
+ "src/qs8-gemm/gen/3x4c8-xw-minmax-fp32-xop.c",
+ "src/qs8-gemm/gen/4x4c2-minmax-fp32-xop-ld64.c",
+ "src/qs8-gemm/gen/4x4c2-minmax-fp32-xop-ld128.c",
+ "src/qs8-gemm/gen/4x4c2-xw-minmax-fp32-xop.c",
+ "src/qs8-igemm/gen/1x4c2-minmax-fp32-xop-ld64.c",
+ "src/qs8-igemm/gen/1x4c2-minmax-fp32-xop-ld128.c",
+ "src/qs8-igemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
+ "src/qs8-igemm/gen/1x4c8-minmax-fp32-xop-ld128.c",
+ "src/qs8-igemm/gen/2x4c2-minmax-fp32-xop-ld64.c",
+ "src/qs8-igemm/gen/2x4c2-minmax-fp32-xop-ld128.c",
+ "src/qs8-igemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
+ "src/qs8-igemm/gen/2x4c8-minmax-fp32-xop-ld128.c",
+ "src/qs8-igemm/gen/3x4c2-minmax-fp32-xop-ld64.c",
+ "src/qs8-igemm/gen/3x4c2-minmax-fp32-xop-ld128.c",
+ "src/qs8-igemm/gen/3x4c8-minmax-fp32-xop-ld64.c",
+ "src/qs8-igemm/gen/3x4c8-minmax-fp32-xop-ld128.c",
+ "src/qs8-igemm/gen/4x4c2-minmax-fp32-xop-ld64.c",
+ "src/qs8-igemm/gen/4x4c2-minmax-fp32-xop-ld128.c",
"src/qs8-vadd/gen/minmax-xop-mul32-ld32-x8.c",
"src/qs8-vadd/gen/minmax-xop-mul32-ld32-x16.c",
"src/qs8-vadd/gen/minmax-xop-mul32-ld32-x24.c",
@@ -2050,15 +6181,95 @@
"src/qs8-vaddc/gen/minmax-xop-mul32-ld32-x16.c",
"src/qs8-vaddc/gen/minmax-xop-mul32-ld32-x24.c",
"src/qs8-vaddc/gen/minmax-xop-mul32-ld32-x32.c",
+ "src/qu8-dwconv/gen/up8x9-minmax-fp32-xop-mul32.c",
+ "src/qu8-dwconv/gen/up8x25-minmax-fp32-xop-mul32.c",
+ "src/qu8-dwconv/gen/up16x9-minmax-fp32-xop-mul32.c",
+ "src/qu8-dwconv/gen/up16x25-minmax-fp32-xop-mul32.c",
+ "src/qu8-gemm/gen/1x4c2-minmax-fp32-xop-ld64.c",
+ "src/qu8-gemm/gen/1x4c2-minmax-fp32-xop-ld128.c",
+ "src/qu8-gemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
+ "src/qu8-gemm/gen/1x4c8-minmax-fp32-xop-ld128.c",
+ "src/qu8-gemm/gen/2x4c2-minmax-fp32-xop-ld64.c",
+ "src/qu8-gemm/gen/2x4c2-minmax-fp32-xop-ld128.c",
+ "src/qu8-gemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
+ "src/qu8-gemm/gen/2x4c8-minmax-fp32-xop-ld128.c",
+ "src/qu8-gemm/gen/3x4c2-minmax-fp32-xop-ld64.c",
+ "src/qu8-gemm/gen/3x4c2-minmax-fp32-xop-ld128.c",
+ "src/qu8-gemm/gen/3x4c8-minmax-fp32-xop-ld64.c",
+ "src/qu8-gemm/gen/3x4c8-minmax-fp32-xop-ld128.c",
+ "src/qu8-gemm/gen/4x4c2-minmax-fp32-xop-ld64.c",
+ "src/qu8-gemm/gen/4x4c2-minmax-fp32-xop-ld128.c",
+ "src/qu8-igemm/gen/1x4c2-minmax-fp32-xop-ld64.c",
+ "src/qu8-igemm/gen/1x4c2-minmax-fp32-xop-ld128.c",
+ "src/qu8-igemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
+ "src/qu8-igemm/gen/1x4c8-minmax-fp32-xop-ld128.c",
+ "src/qu8-igemm/gen/2x4c2-minmax-fp32-xop-ld64.c",
+ "src/qu8-igemm/gen/2x4c2-minmax-fp32-xop-ld128.c",
+ "src/qu8-igemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
+ "src/qu8-igemm/gen/2x4c8-minmax-fp32-xop-ld128.c",
+ "src/qu8-igemm/gen/3x4c2-minmax-fp32-xop-ld64.c",
+ "src/qu8-igemm/gen/3x4c2-minmax-fp32-xop-ld128.c",
+ "src/qu8-igemm/gen/3x4c8-minmax-fp32-xop-ld64.c",
+ "src/qu8-igemm/gen/3x4c8-minmax-fp32-xop-ld128.c",
+ "src/qu8-igemm/gen/4x4c2-minmax-fp32-xop-ld64.c",
+ "src/qu8-igemm/gen/4x4c2-minmax-fp32-xop-ld128.c",
+ "src/qu8-vadd/gen/minmax-xop-mul32-ld32-x8.c",
+ "src/qu8-vadd/gen/minmax-xop-mul32-ld32-x16.c",
+ "src/qu8-vaddc/gen/minmax-xop-mul32-ld32-x8.c",
+ "src/qu8-vaddc/gen/minmax-xop-mul32-ld32-x16.c",
]
-FMA3_UKERNELS = [
+PROD_FMA3_MICROKERNEL_SRCS = [
+ "src/f16-dwconv/gen/up8x25-minmax-fma3-acc2.c",
+ "src/f16-dwconv/gen/up16x4-minmax-fma3.c",
+ "src/f16-dwconv/gen/up16x9-minmax-fma3.c",
+ "src/f16-vmulcaddc/gen/c8-minmax-fma3-2x.c",
+ "src/f32-dwconv/gen/up8x25-minmax-fma3.c",
+ "src/f32-dwconv/gen/up16x3-minmax-fma3.c",
+ "src/f32-dwconv/gen/up16x4-minmax-fma3.c",
+ "src/f32-dwconv/gen/up16x9-minmax-fma3.c",
+ "src/f32-gemm/gen/1x16-minmax-fma3-broadcast.c",
+ "src/f32-gemm/gen/1x16s4-minmax-fma3-broadcast.c",
+ "src/f32-gemm/gen/4x16s4-minmax-fma3-broadcast.c",
+ "src/f32-gemm/gen/5x16-minmax-fma3-broadcast.c",
+ "src/f32-igemm/gen/1x16-minmax-fma3-broadcast.c",
+ "src/f32-igemm/gen/1x16s4-minmax-fma3-broadcast.c",
+ "src/f32-igemm/gen/4x16s4-minmax-fma3-broadcast.c",
+ "src/f32-igemm/gen/5x16-minmax-fma3-broadcast.c",
+ "src/f32-vhswish/gen/vhswish-fma3-x16.c",
+]
+
+ALL_FMA3_MICROKERNEL_SRCS = [
+ "src/f16-dwconv/gen/up8x4-minmax-fma3-acc2.c",
+ "src/f16-dwconv/gen/up8x4-minmax-fma3.c",
+ "src/f16-dwconv/gen/up8x9-minmax-fma3-acc2.c",
+ "src/f16-dwconv/gen/up8x9-minmax-fma3.c",
+ "src/f16-dwconv/gen/up8x25-minmax-fma3-acc2.c",
+ "src/f16-dwconv/gen/up8x25-minmax-fma3.c",
+ "src/f16-dwconv/gen/up16x4-minmax-fma3-acc2.c",
+ "src/f16-dwconv/gen/up16x4-minmax-fma3.c",
+ "src/f16-dwconv/gen/up16x9-minmax-fma3-acc2.c",
+ "src/f16-dwconv/gen/up16x9-minmax-fma3.c",
+ "src/f16-dwconv/gen/up16x25-minmax-fma3-acc2.c",
+ "src/f16-dwconv/gen/up16x25-minmax-fma3.c",
+ "src/f16-dwconv/gen/up32x4-minmax-fma3-acc2.c",
+ "src/f16-dwconv/gen/up32x4-minmax-fma3.c",
+ "src/f16-dwconv/gen/up32x9-minmax-fma3-acc2.c",
+ "src/f16-dwconv/gen/up32x9-minmax-fma3.c",
+ "src/f16-dwconv/gen/up32x25-minmax-fma3-acc2.c",
+ "src/f16-dwconv/gen/up32x25-minmax-fma3.c",
+ "src/f16-vmulcaddc/gen/c8-minmax-fma3-2x.c",
+ "src/f16-vmulcaddc/gen/c16-minmax-fma3-2x.c",
+ "src/f32-dwconv/gen/up8x3-minmax-fma3-acc2.c",
+ "src/f32-dwconv/gen/up8x3-minmax-fma3.c",
"src/f32-dwconv/gen/up8x4-minmax-fma3-acc2.c",
"src/f32-dwconv/gen/up8x4-minmax-fma3.c",
"src/f32-dwconv/gen/up8x9-minmax-fma3-acc2.c",
"src/f32-dwconv/gen/up8x9-minmax-fma3.c",
"src/f32-dwconv/gen/up8x25-minmax-fma3-acc2.c",
"src/f32-dwconv/gen/up8x25-minmax-fma3.c",
+ "src/f32-dwconv/gen/up16x3-minmax-fma3-acc2.c",
+ "src/f32-dwconv/gen/up16x3-minmax-fma3.c",
"src/f32-dwconv/gen/up16x4-minmax-fma3-acc2.c",
"src/f32-dwconv/gen/up16x4-minmax-fma3.c",
"src/f32-dwconv/gen/up16x9-minmax-fma3-acc2.c",
@@ -2093,8 +6304,6 @@
"src/f32-gemm/gen/6x8-minmax-fma3-broadcast.c",
"src/f32-gemm/gen/7x8-minmax-fma3-broadcast.c",
"src/f32-gemm/gen/8x8-minmax-fma3-broadcast.c",
- "src/f32-hswish/gen/hswish-fma3-x8.c",
- "src/f32-hswish/gen/hswish-fma3-x16.c",
"src/f32-igemm/gen/1x8-minmax-fma3-broadcast.c",
"src/f32-igemm/gen/1x16-minmax-fma3-broadcast.c",
"src/f32-igemm/gen/1x16s4-minmax-fma3-broadcast.c",
@@ -2109,6 +6318,8 @@
"src/f32-igemm/gen/6x8-minmax-fma3-broadcast.c",
"src/f32-igemm/gen/7x8-minmax-fma3-broadcast.c",
"src/f32-igemm/gen/8x8-minmax-fma3-broadcast.c",
+ "src/f32-vhswish/gen/vhswish-fma3-x8.c",
+ "src/f32-vhswish/gen/vhswish-fma3-x16.c",
"src/f32-vsqrt/gen/fma3-nr1fma1adj-x8.c",
"src/f32-vsqrt/gen/fma3-nr1fma1adj-x16.c",
"src/f32-vsqrt/gen/fma3-nr1fma1adj-x24.c",
@@ -2122,7 +6333,69 @@
"src/math/sqrt-fma3-nr2fma.c",
]
-AVX2_UKERNELS = [
+PROD_AVX2_MICROKERNEL_SRCS = [
+ "src/f16-gemm/gen/1x16-minmax-avx2-broadcast.c",
+ "src/f16-gemm/gen/4x16-minmax-avx2-broadcast.c",
+ "src/f16-igemm/gen/1x16-minmax-avx2-broadcast.c",
+ "src/f16-igemm/gen/4x16-minmax-avx2-broadcast.c",
+ "src/f32-qs8-vcvt/gen/vcvt-avx2-x64.c",
+ "src/f32-qu8-vcvt/gen/vcvt-avx2-x64.c",
+ "src/f32-velu/gen/velu-avx2-rr1-lut4-p4-perm-x56.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x40.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx2-mul32.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx2-mul32.c",
+ "src/qc8-gemm/gen/1x8c8-minmax-fp32-avx2.c",
+ "src/qc8-gemm/gen/3x8c8-minmax-fp32-avx2.c",
+ "src/qc8-igemm/gen/1x8c8-minmax-fp32-avx2.c",
+ "src/qc8-igemm/gen/3x8c8-minmax-fp32-avx2.c",
+ "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx2-mul32.c",
+ "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx2-mul32.c",
+ "src/qs8-f32-vcvt/gen/vcvt-avx2-x16.c",
+ "src/qs8-gemm/gen/1x8c8-minmax-fp32-avx2.c",
+ "src/qs8-gemm/gen/3x8c8-minmax-fp32-avx2.c",
+ "src/qs8-igemm/gen/1x8c8-minmax-fp32-avx2.c",
+ "src/qs8-igemm/gen/3x8c8-minmax-fp32-avx2.c",
+ "src/qs8-vadd/gen/minmax-avx2-mul32-ld64-x16.c",
+ "src/qs8-vaddc/gen/minmax-avx2-mul32-ld64-x16.c",
+ "src/qu8-dwconv/gen/up16x9-minmax-fp32-avx2-mul32.c",
+ "src/qu8-dwconv/gen/up16x25-minmax-fp32-avx2-mul32.c",
+ "src/qu8-f32-vcvt/gen/vcvt-avx2-x16.c",
+ "src/qu8-gemm/gen/1x8c8-minmax-fp32-avx2.c",
+ "src/qu8-gemm/gen/3x8c8-minmax-fp32-avx2.c",
+ "src/qu8-igemm/gen/1x8c8-minmax-fp32-avx2.c",
+ "src/qu8-igemm/gen/3x8c8-minmax-fp32-avx2.c",
+ "src/qu8-vadd/gen/minmax-avx2-mul32-ld64-x16.c",
+ "src/qu8-vaddc/gen/minmax-avx2-mul32-ld64-x16.c",
+ "src/x8-lut/gen/lut-avx2-x128.c",
+]
+
+ALL_AVX2_MICROKERNEL_SRCS = [
+ "src/f16-gemm/gen/1x8-minmax-avx2-broadcast.c",
+ "src/f16-gemm/gen/1x16-minmax-avx2-broadcast.c",
+ "src/f16-gemm/gen/3x16-minmax-avx2-broadcast.c",
+ "src/f16-gemm/gen/4x8-minmax-avx2-broadcast.c",
+ "src/f16-gemm/gen/4x16-minmax-avx2-broadcast.c",
+ "src/f16-gemm/gen/5x8-minmax-avx2-broadcast.c",
+ "src/f16-gemm/gen/5x16-minmax-avx2-broadcast.c",
+ "src/f16-gemm/gen/6x8-minmax-avx2-broadcast.c",
+ "src/f16-gemm/gen/7x8-minmax-avx2-broadcast.c",
+ "src/f16-igemm/gen/1x8-minmax-avx2-broadcast.c",
+ "src/f16-igemm/gen/1x16-minmax-avx2-broadcast.c",
+ "src/f16-igemm/gen/3x16-minmax-avx2-broadcast.c",
+ "src/f16-igemm/gen/4x8-minmax-avx2-broadcast.c",
+ "src/f16-igemm/gen/4x16-minmax-avx2-broadcast.c",
+ "src/f16-igemm/gen/5x8-minmax-avx2-broadcast.c",
+ "src/f16-igemm/gen/5x16-minmax-avx2-broadcast.c",
+ "src/f16-igemm/gen/6x8-minmax-avx2-broadcast.c",
+ "src/f16-igemm/gen/7x8-minmax-avx2-broadcast.c",
+ "src/f32-qs8-vcvt/gen/vcvt-avx2-x16.c",
+ "src/f32-qs8-vcvt/gen/vcvt-avx2-x32.c",
+ "src/f32-qs8-vcvt/gen/vcvt-avx2-x48.c",
+ "src/f32-qs8-vcvt/gen/vcvt-avx2-x64.c",
+ "src/f32-qu8-vcvt/gen/vcvt-avx2-x16.c",
+ "src/f32-qu8-vcvt/gen/vcvt-avx2-x32.c",
+ "src/f32-qu8-vcvt/gen/vcvt-avx2-x48.c",
+ "src/f32-qu8-vcvt/gen/vcvt-avx2-x64.c",
"src/f32-raddexpminusmax/gen/avx2-p5-x64-acc2.c",
"src/f32-raddexpminusmax/gen/avx2-p5-x64-acc4.c",
"src/f32-raddexpminusmax/gen/avx2-p5-x64.c",
@@ -2147,48 +6420,18 @@
"src/f32-raddextexp/gen/avx2-p5-x96-acc3.c",
"src/f32-raddextexp/gen/avx2-p5-x96-acc6.c",
"src/f32-raddextexp/gen/avx2-p5-x96.c",
- "src/f32-raddstoreexpminusmax/gen/avx2-p5-x64-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/avx2-p5-x64-acc4.c",
- "src/f32-raddstoreexpminusmax/gen/avx2-p5-x64.c",
- "src/f32-raddstoreexpminusmax/gen/avx2-p5-x72-acc3.c",
- "src/f32-raddstoreexpminusmax/gen/avx2-p5-x72.c",
- "src/f32-raddstoreexpminusmax/gen/avx2-p5-x80-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/avx2-p5-x80-acc5.c",
- "src/f32-raddstoreexpminusmax/gen/avx2-p5-x80.c",
- "src/f32-raddstoreexpminusmax/gen/avx2-p5-x96-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/avx2-p5-x96-acc3.c",
- "src/f32-raddstoreexpminusmax/gen/avx2-p5-x96-acc6.c",
- "src/f32-raddstoreexpminusmax/gen/avx2-p5-x96.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-div-x8.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-div-x16.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-div-x24.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-div-x32.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-div-x40.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-div-x48.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-div-x56.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-div-x64.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-div-x72.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-div-x80.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-nr1fma-x8.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-nr1fma-x16.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-nr1fma-x24.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-nr1fma-x32.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-nr1fma-x40.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-nr1fma-x48.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-nr1fma-x56.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-nr1fma-x64.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-nr1fma-x72.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-nr1fma-x80.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-nr2fma-x8.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-nr2fma-x16.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-nr2fma-x24.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-nr2fma-x32.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-nr2fma-x40.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-nr2fma-x48.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-nr2fma-x56.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-nr2fma-x64.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-nr2fma-x72.c",
- "src/f32-sigmoid/gen/avx2-rr1-p5-nr2fma-x80.c",
+ "src/f32-raddstoreexpminusmax/gen/avx2-rr1-p5-x64-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/avx2-rr1-p5-x64-acc4.c",
+ "src/f32-raddstoreexpminusmax/gen/avx2-rr1-p5-x64.c",
+ "src/f32-raddstoreexpminusmax/gen/avx2-rr1-p5-x72-acc3.c",
+ "src/f32-raddstoreexpminusmax/gen/avx2-rr1-p5-x72.c",
+ "src/f32-raddstoreexpminusmax/gen/avx2-rr1-p5-x80-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/avx2-rr1-p5-x80-acc5.c",
+ "src/f32-raddstoreexpminusmax/gen/avx2-rr1-p5-x80.c",
+ "src/f32-raddstoreexpminusmax/gen/avx2-rr1-p5-x96-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/avx2-rr1-p5-x96-acc3.c",
+ "src/f32-raddstoreexpminusmax/gen/avx2-rr1-p5-x96-acc6.c",
+ "src/f32-raddstoreexpminusmax/gen/avx2-rr1-p5-x96.c",
"src/f32-velu/gen/velu-avx2-rr1-lut4-p4-perm-x8.c",
"src/f32-velu/gen/velu-avx2-rr1-lut4-p4-perm-x16.c",
"src/f32-velu/gen/velu-avx2-rr1-lut4-p4-perm-x24.c",
@@ -2253,6 +6496,36 @@
"src/f32-vscaleextexp/gen/avx2-p5-x80.c",
"src/f32-vscaleextexp/gen/avx2-p5-x88.c",
"src/f32-vscaleextexp/gen/avx2-p5-x96.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x24.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x32.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x40.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x48.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x56.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x64.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x72.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x80.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x24.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x32.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x40.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x48.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x56.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x64.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x72.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x80.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x8.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x24.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x32.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x40.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x48.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x56.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x64.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x72.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x80.c",
"src/math/exp-avx2-rr2-lut8-p3-perm.c",
"src/math/exp-avx2-rr2-lut8-p4-perm.c",
"src/math/exp-avx2-rr2-p5.c",
@@ -2260,6 +6533,7 @@
"src/math/expm1minus-avx2-rr1-lut8-p4-perm.c",
"src/math/expm1minus-avx2-rr1-lut16-p3-gather.c",
"src/math/expm1minus-avx2-rr1-p6.c",
+ "src/math/expminus-avx2-rr1-p5.c",
"src/math/expminus-avx2-rr2-p5.c",
"src/math/extexp-avx2-p5.c",
"src/math/sigmoid-avx2-rr1-lut64-p2-gather-div.c",
@@ -2276,21 +6550,68 @@
"src/math/sigmoid-avx2-rr2-p5-div.c",
"src/math/sigmoid-avx2-rr2-p5-nr1fma.c",
"src/math/sigmoid-avx2-rr2-p5-nr2fma.c",
- "src/qs8-dwconv/gen/up8x9-minmax-avx2-mul32.c",
- "src/qs8-dwconv/gen/up16x9-minmax-avx2-mul16.c",
- "src/qs8-dwconv/gen/up16x9-minmax-avx2-mul32.c",
- "src/qs8-dwconv/gen/up24x9-minmax-avx2-mul32.c",
- "src/qs8-dwconv/gen/up32x9-minmax-avx2-mul16.c",
- "src/qs8-dwconv/gen/up32x9-minmax-avx2-mul32.c",
- "src/qs8-gemm/gen/1x8c8-minmax-avx2.c",
- "src/qs8-gemm/gen/1x8c8-xw-minmax-avx2.c",
- "src/qs8-gemm/gen/2x8c8-minmax-avx2.c",
- "src/qs8-gemm/gen/2x8c8-xw-minmax-avx2.c",
- "src/qs8-gemm/gen/3x8c8-minmax-avx2.c",
- "src/qs8-gemm/gen/3x8c8-xw-minmax-avx2.c",
- "src/qs8-igemm/gen/1x8c8-minmax-avx2.c",
- "src/qs8-igemm/gen/2x8c8-minmax-avx2.c",
- "src/qs8-igemm/gen/3x8c8-minmax-avx2.c",
+ "src/qc8-dwconv/gen/up8x9-minmax-fp32-avx2-mul32.c",
+ "src/qc8-dwconv/gen/up8x25-minmax-fp32-avx2-mul32.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx2-mul16-add16-vpunpck.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx2-mul16-vpmovsx.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx2-mul16-vpunpck.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx2-mul32.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx2-mul16-add16-vpunpck.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx2-mul16-vpmovsx.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx2-mul16-vpunpck.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx2-mul32.c",
+ "src/qc8-dwconv/gen/up24x9-minmax-fp32-avx2-mul32.c",
+ "src/qc8-dwconv/gen/up24x25-minmax-fp32-avx2-mul32.c",
+ "src/qc8-dwconv/gen/up32x9-minmax-fp32-avx2-mul16-add16-vpunpck.c",
+ "src/qc8-dwconv/gen/up32x9-minmax-fp32-avx2-mul16-vpmovsx.c",
+ "src/qc8-dwconv/gen/up32x9-minmax-fp32-avx2-mul16-vpunpck.c",
+ "src/qc8-dwconv/gen/up32x9-minmax-fp32-avx2-mul32.c",
+ "src/qc8-dwconv/gen/up32x25-minmax-fp32-avx2-mul16-add16-vpunpck.c",
+ "src/qc8-dwconv/gen/up32x25-minmax-fp32-avx2-mul16-vpmovsx.c",
+ "src/qc8-dwconv/gen/up32x25-minmax-fp32-avx2-mul16-vpunpck.c",
+ "src/qc8-dwconv/gen/up32x25-minmax-fp32-avx2-mul32.c",
+ "src/qc8-gemm/gen/1x8c8-minmax-fp32-avx2.c",
+ "src/qc8-gemm/gen/1x8c8-xw-minmax-fp32-avx2.c",
+ "src/qc8-gemm/gen/2x8c8-minmax-fp32-avx2.c",
+ "src/qc8-gemm/gen/2x8c8-xw-minmax-fp32-avx2.c",
+ "src/qc8-gemm/gen/3x8c8-minmax-fp32-avx2.c",
+ "src/qc8-gemm/gen/3x8c8-xw-minmax-fp32-avx2.c",
+ "src/qc8-igemm/gen/1x8c8-minmax-fp32-avx2.c",
+ "src/qc8-igemm/gen/2x8c8-minmax-fp32-avx2.c",
+ "src/qc8-igemm/gen/3x8c8-minmax-fp32-avx2.c",
+ "src/qs8-dwconv/gen/up8x9-minmax-fp32-avx2-mul32.c",
+ "src/qs8-dwconv/gen/up8x25-minmax-fp32-avx2-mul32.c",
+ "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx2-mul16-add16-vpunpck.c",
+ "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx2-mul16-vpmovsx.c",
+ "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx2-mul16-vpunpck.c",
+ "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx2-mul32.c",
+ "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx2-mul16-add16-vpunpck.c",
+ "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx2-mul16-vpmovsx.c",
+ "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx2-mul16-vpunpck.c",
+ "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx2-mul32.c",
+ "src/qs8-dwconv/gen/up24x9-minmax-fp32-avx2-mul32.c",
+ "src/qs8-dwconv/gen/up24x25-minmax-fp32-avx2-mul32.c",
+ "src/qs8-dwconv/gen/up32x9-minmax-fp32-avx2-mul16-add16-vpunpck.c",
+ "src/qs8-dwconv/gen/up32x9-minmax-fp32-avx2-mul16-vpmovsx.c",
+ "src/qs8-dwconv/gen/up32x9-minmax-fp32-avx2-mul16-vpunpck.c",
+ "src/qs8-dwconv/gen/up32x9-minmax-fp32-avx2-mul32.c",
+ "src/qs8-dwconv/gen/up32x25-minmax-fp32-avx2-mul16-add16-vpunpck.c",
+ "src/qs8-dwconv/gen/up32x25-minmax-fp32-avx2-mul16-vpmovsx.c",
+ "src/qs8-dwconv/gen/up32x25-minmax-fp32-avx2-mul16-vpunpck.c",
+ "src/qs8-dwconv/gen/up32x25-minmax-fp32-avx2-mul32.c",
+ "src/qs8-f32-vcvt/gen/vcvt-avx2-x8.c",
+ "src/qs8-f32-vcvt/gen/vcvt-avx2-x16.c",
+ "src/qs8-f32-vcvt/gen/vcvt-avx2-x24.c",
+ "src/qs8-f32-vcvt/gen/vcvt-avx2-x32.c",
+ "src/qs8-gemm/gen/1x8c8-minmax-fp32-avx2.c",
+ "src/qs8-gemm/gen/1x8c8-xw-minmax-fp32-avx2.c",
+ "src/qs8-gemm/gen/2x8c8-minmax-fp32-avx2.c",
+ "src/qs8-gemm/gen/2x8c8-xw-minmax-fp32-avx2.c",
+ "src/qs8-gemm/gen/3x8c8-minmax-fp32-avx2.c",
+ "src/qs8-gemm/gen/3x8c8-xw-minmax-fp32-avx2.c",
+ "src/qs8-igemm/gen/1x8c8-minmax-fp32-avx2.c",
+ "src/qs8-igemm/gen/2x8c8-minmax-fp32-avx2.c",
+ "src/qs8-igemm/gen/3x8c8-minmax-fp32-avx2.c",
"src/qs8-vadd/gen/minmax-avx2-mul32-ld64-x8.c",
"src/qs8-vadd/gen/minmax-avx2-mul32-ld64-x16.c",
"src/qs8-vadd/gen/minmax-avx2-mul32-ld64-x24.c",
@@ -2299,17 +6620,83 @@
"src/qs8-vaddc/gen/minmax-avx2-mul32-ld64-x16.c",
"src/qs8-vaddc/gen/minmax-avx2-mul32-ld64-x24.c",
"src/qs8-vaddc/gen/minmax-avx2-mul32-ld64-x32.c",
+ "src/qu8-dwconv/gen/up8x9-minmax-fp32-avx2-mul32.c",
+ "src/qu8-dwconv/gen/up8x25-minmax-fp32-avx2-mul32.c",
+ "src/qu8-dwconv/gen/up16x9-minmax-fp32-avx2-mul32.c",
+ "src/qu8-dwconv/gen/up16x25-minmax-fp32-avx2-mul32.c",
+ "src/qu8-dwconv/gen/up32x9-minmax-fp32-avx2-mul32.c",
+ "src/qu8-dwconv/gen/up32x25-minmax-fp32-avx2-mul32.c",
+ "src/qu8-f32-vcvt/gen/vcvt-avx2-x8.c",
+ "src/qu8-f32-vcvt/gen/vcvt-avx2-x16.c",
+ "src/qu8-f32-vcvt/gen/vcvt-avx2-x24.c",
+ "src/qu8-f32-vcvt/gen/vcvt-avx2-x32.c",
+ "src/qu8-gemm/gen/1x8c8-minmax-fp32-avx2.c",
+ "src/qu8-gemm/gen/2x8c8-minmax-fp32-avx2.c",
+ "src/qu8-gemm/gen/3x8c8-minmax-fp32-avx2.c",
+ "src/qu8-igemm/gen/1x8c8-minmax-fp32-avx2.c",
+ "src/qu8-igemm/gen/2x8c8-minmax-fp32-avx2.c",
+ "src/qu8-igemm/gen/3x8c8-minmax-fp32-avx2.c",
+ "src/qu8-vadd/gen/minmax-avx2-mul32-ld64-x8.c",
+ "src/qu8-vadd/gen/minmax-avx2-mul32-ld64-x16.c",
+ "src/qu8-vaddc/gen/minmax-avx2-mul32-ld64-x8.c",
+ "src/qu8-vaddc/gen/minmax-avx2-mul32-ld64-x16.c",
+ "src/x8-lut/gen/lut-avx2-x32.c",
+ "src/x8-lut/gen/lut-avx2-x64.c",
+ "src/x8-lut/gen/lut-avx2-x96.c",
+ "src/x8-lut/gen/lut-avx2-x128.c",
]
-AVX512F_UKERNELS = [
- "src/f32-clamp/gen/avx512f-x16.c",
- "src/f32-clamp/gen/avx512f-x32.c",
+PROD_AVX512F_MICROKERNEL_SRCS = [
+ "src/f32-dwconv/gen/up16x3-minmax-avx512f.c",
+ "src/f32-dwconv/gen/up16x4-minmax-avx512f.c",
+ "src/f32-dwconv/gen/up16x9-minmax-avx512f.c",
+ "src/f32-dwconv/gen/up16x25-minmax-avx512f.c",
+ "src/f32-gemm/gen/1x16-minmax-avx512f-broadcast.c",
+ "src/f32-gemm/gen/7x16-minmax-avx512f-broadcast.c",
+ "src/f32-igemm/gen/1x16-minmax-avx512f-broadcast.c",
+ "src/f32-igemm/gen/7x16-minmax-avx512f-broadcast.c",
+ "src/f32-prelu/gen/avx512f-2x16.c",
+ "src/f32-vbinary/gen/vadd-minmax-avx512f-x32.c",
+ "src/f32-vbinary/gen/vaddc-minmax-avx512f-x32.c",
+ "src/f32-vbinary/gen/vdiv-minmax-avx512f-x32.c",
+ "src/f32-vbinary/gen/vdivc-minmax-avx512f-x32.c",
+ "src/f32-vbinary/gen/vmax-avx512f-x32.c",
+ "src/f32-vbinary/gen/vmaxc-avx512f-x32.c",
+ "src/f32-vbinary/gen/vmin-avx512f-x32.c",
+ "src/f32-vbinary/gen/vminc-avx512f-x32.c",
+ "src/f32-vbinary/gen/vmul-minmax-avx512f-x32.c",
+ "src/f32-vbinary/gen/vmulc-minmax-avx512f-x32.c",
+ "src/f32-vbinary/gen/vrdivc-minmax-avx512f-x32.c",
+ "src/f32-vbinary/gen/vrsubc-minmax-avx512f-x32.c",
+ "src/f32-vbinary/gen/vsqrdiff-avx512f-x32.c",
+ "src/f32-vbinary/gen/vsqrdiffc-avx512f-x32.c",
+ "src/f32-vbinary/gen/vsub-minmax-avx512f-x32.c",
+ "src/f32-vbinary/gen/vsubc-minmax-avx512f-x32.c",
+ "src/f32-vclamp/gen/vclamp-avx512f-x16.c",
+ "src/f32-velu/gen/velu-avx512f-rr1-lut16-p3-perm-x64.c",
+ "src/f32-vhswish/gen/vhswish-avx512f-x16.c",
+ "src/f32-vlrelu/gen/vlrelu-avx512f-x16.c",
+ "src/f32-vrnd/gen/vrndd-avx512f-x16.c",
+ "src/f32-vrnd/gen/vrndne-avx512f-x16.c",
+ "src/f32-vrnd/gen/vrndu-avx512f-x16.c",
+ "src/f32-vrnd/gen/vrndz-avx512f-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x64.c",
+ "src/f32-vunary/gen/vabs-avx512f-x16.c",
+ "src/f32-vunary/gen/vneg-avx512f-x16.c",
+ "src/f32-vunary/gen/vsqr-avx512f-x16.c",
+]
+
+ALL_AVX512F_MICROKERNEL_SRCS = [
+ "src/f32-dwconv/gen/up16x3-minmax-avx512f-acc2.c",
+ "src/f32-dwconv/gen/up16x3-minmax-avx512f.c",
"src/f32-dwconv/gen/up16x4-minmax-avx512f-acc2.c",
"src/f32-dwconv/gen/up16x4-minmax-avx512f.c",
"src/f32-dwconv/gen/up16x9-minmax-avx512f-acc2.c",
"src/f32-dwconv/gen/up16x9-minmax-avx512f.c",
"src/f32-dwconv/gen/up16x25-minmax-avx512f-acc2.c",
"src/f32-dwconv/gen/up16x25-minmax-avx512f.c",
+ "src/f32-dwconv/gen/up32x3-minmax-avx512f-acc2.c",
+ "src/f32-dwconv/gen/up32x3-minmax-avx512f.c",
"src/f32-dwconv/gen/up32x4-minmax-avx512f-acc2.c",
"src/f32-dwconv/gen/up32x4-minmax-avx512f.c",
"src/f32-dwconv/gen/up32x9-minmax-avx512f-acc2.c",
@@ -2328,8 +6715,6 @@
"src/f32-gemm/gen/6x16-minmax-avx512f-broadcast.c",
"src/f32-gemm/gen/7x16-minmax-avx512f-broadcast.c",
"src/f32-gemm/gen/8x16-minmax-avx512f-broadcast.c",
- "src/f32-hswish/gen/hswish-avx512f-x16.c",
- "src/f32-hswish/gen/hswish-avx512f-x32.c",
"src/f32-igemm/gen/1x16-minmax-avx512f-broadcast.c",
"src/f32-igemm/gen/4x16-minmax-avx512f-broadcast.c",
"src/f32-igemm/gen/5x16-minmax-avx512f-broadcast.c",
@@ -2362,69 +6747,19 @@
"src/f32-raddextexp/gen/avx512f-p5-scalef-x192-acc3.c",
"src/f32-raddextexp/gen/avx512f-p5-scalef-x192-acc6.c",
"src/f32-raddextexp/gen/avx512f-p5-scalef-x192.c",
- "src/f32-raddstoreexpminusmax/gen/avx512f-p5-scalef-x128-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/avx512f-p5-scalef-x128-acc4.c",
- "src/f32-raddstoreexpminusmax/gen/avx512f-p5-scalef-x128.c",
- "src/f32-raddstoreexpminusmax/gen/avx512f-p5-scalef-x144-acc3.c",
- "src/f32-raddstoreexpminusmax/gen/avx512f-p5-scalef-x144.c",
- "src/f32-raddstoreexpminusmax/gen/avx512f-p5-scalef-x160-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/avx512f-p5-scalef-x160-acc5.c",
- "src/f32-raddstoreexpminusmax/gen/avx512f-p5-scalef-x160.c",
- "src/f32-raddstoreexpminusmax/gen/avx512f-p5-scalef-x192-acc2.c",
- "src/f32-raddstoreexpminusmax/gen/avx512f-p5-scalef-x192-acc3.c",
- "src/f32-raddstoreexpminusmax/gen/avx512f-p5-scalef-x192-acc6.c",
- "src/f32-raddstoreexpminusmax/gen/avx512f-p5-scalef-x192.c",
- "src/f32-relu/gen/avx512f-x16.c",
- "src/f32-relu/gen/avx512f-x32.c",
+ "src/f32-raddstoreexpminusmax/gen/avx512f-rr1-p5-scalef-x128-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/avx512f-rr1-p5-scalef-x128-acc4.c",
+ "src/f32-raddstoreexpminusmax/gen/avx512f-rr1-p5-scalef-x128.c",
+ "src/f32-raddstoreexpminusmax/gen/avx512f-rr1-p5-scalef-x144-acc3.c",
+ "src/f32-raddstoreexpminusmax/gen/avx512f-rr1-p5-scalef-x144.c",
+ "src/f32-raddstoreexpminusmax/gen/avx512f-rr1-p5-scalef-x160-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/avx512f-rr1-p5-scalef-x160-acc5.c",
+ "src/f32-raddstoreexpminusmax/gen/avx512f-rr1-p5-scalef-x160.c",
+ "src/f32-raddstoreexpminusmax/gen/avx512f-rr1-p5-scalef-x192-acc2.c",
+ "src/f32-raddstoreexpminusmax/gen/avx512f-rr1-p5-scalef-x192-acc3.c",
+ "src/f32-raddstoreexpminusmax/gen/avx512f-rr1-p5-scalef-x192-acc6.c",
+ "src/f32-raddstoreexpminusmax/gen/avx512f-rr1-p5-scalef-x192.c",
"src/f32-rmax/avx512f.c",
- "src/f32-sigmoid/gen/avx512f-rr1-lut16-p3-perm-scalef-div-x16.c",
- "src/f32-sigmoid/gen/avx512f-rr1-lut16-p3-perm-scalef-div-x32.c",
- "src/f32-sigmoid/gen/avx512f-rr1-lut16-p3-perm-scalef-div-x48.c",
- "src/f32-sigmoid/gen/avx512f-rr1-lut16-p3-perm-scalef-div-x64.c",
- "src/f32-sigmoid/gen/avx512f-rr1-lut16-p3-perm-scalef-div-x80.c",
- "src/f32-sigmoid/gen/avx512f-rr1-lut16-p3-perm-scalef-div-x96.c",
- "src/f32-sigmoid/gen/avx512f-rr1-lut16-p3-perm-scalef-div-x112.c",
- "src/f32-sigmoid/gen/avx512f-rr1-lut16-p3-perm-scalef-div-x128.c",
- "src/f32-sigmoid/gen/avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x16.c",
- "src/f32-sigmoid/gen/avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x32.c",
- "src/f32-sigmoid/gen/avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x48.c",
- "src/f32-sigmoid/gen/avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x64.c",
- "src/f32-sigmoid/gen/avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x80.c",
- "src/f32-sigmoid/gen/avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x96.c",
- "src/f32-sigmoid/gen/avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x112.c",
- "src/f32-sigmoid/gen/avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x128.c",
- "src/f32-sigmoid/gen/avx512f-rr1-p5-scalef-div-x16.c",
- "src/f32-sigmoid/gen/avx512f-rr1-p5-scalef-div-x32.c",
- "src/f32-sigmoid/gen/avx512f-rr1-p5-scalef-div-x48.c",
- "src/f32-sigmoid/gen/avx512f-rr1-p5-scalef-div-x64.c",
- "src/f32-sigmoid/gen/avx512f-rr1-p5-scalef-div-x80.c",
- "src/f32-sigmoid/gen/avx512f-rr1-p5-scalef-div-x96.c",
- "src/f32-sigmoid/gen/avx512f-rr1-p5-scalef-div-x112.c",
- "src/f32-sigmoid/gen/avx512f-rr1-p5-scalef-div-x128.c",
- "src/f32-sigmoid/gen/avx512f-rr1-p5-scalef-nr1fma-x16.c",
- "src/f32-sigmoid/gen/avx512f-rr1-p5-scalef-nr1fma-x32.c",
- "src/f32-sigmoid/gen/avx512f-rr1-p5-scalef-nr1fma-x48.c",
- "src/f32-sigmoid/gen/avx512f-rr1-p5-scalef-nr1fma-x64.c",
- "src/f32-sigmoid/gen/avx512f-rr1-p5-scalef-nr1fma-x80.c",
- "src/f32-sigmoid/gen/avx512f-rr1-p5-scalef-nr1fma-x96.c",
- "src/f32-sigmoid/gen/avx512f-rr1-p5-scalef-nr1fma-x112.c",
- "src/f32-sigmoid/gen/avx512f-rr1-p5-scalef-nr1fma-x128.c",
- "src/f32-sigmoid/gen/avx512f-rr2-lut32-p2-perm2-scalef-div-x16.c",
- "src/f32-sigmoid/gen/avx512f-rr2-lut32-p2-perm2-scalef-div-x32.c",
- "src/f32-sigmoid/gen/avx512f-rr2-lut32-p2-perm2-scalef-div-x48.c",
- "src/f32-sigmoid/gen/avx512f-rr2-lut32-p2-perm2-scalef-div-x64.c",
- "src/f32-sigmoid/gen/avx512f-rr2-lut32-p2-perm2-scalef-div-x80.c",
- "src/f32-sigmoid/gen/avx512f-rr2-lut32-p2-perm2-scalef-div-x96.c",
- "src/f32-sigmoid/gen/avx512f-rr2-lut32-p2-perm2-scalef-div-x112.c",
- "src/f32-sigmoid/gen/avx512f-rr2-lut32-p2-perm2-scalef-div-x128.c",
- "src/f32-sigmoid/gen/avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x16.c",
- "src/f32-sigmoid/gen/avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x32.c",
- "src/f32-sigmoid/gen/avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x48.c",
- "src/f32-sigmoid/gen/avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x64.c",
- "src/f32-sigmoid/gen/avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x80.c",
- "src/f32-sigmoid/gen/avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x96.c",
- "src/f32-sigmoid/gen/avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x112.c",
- "src/f32-sigmoid/gen/avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x128.c",
"src/f32-vbinary/gen/vadd-minmax-avx512f-x16.c",
"src/f32-vbinary/gen/vadd-minmax-avx512f-x32.c",
"src/f32-vbinary/gen/vaddc-minmax-avx512f-x16.c",
@@ -2457,6 +6792,8 @@
"src/f32-vbinary/gen/vsub-minmax-avx512f-x32.c",
"src/f32-vbinary/gen/vsubc-minmax-avx512f-x16.c",
"src/f32-vbinary/gen/vsubc-minmax-avx512f-x32.c",
+ "src/f32-vclamp/gen/vclamp-avx512f-x16.c",
+ "src/f32-vclamp/gen/vclamp-avx512f-x32.c",
"src/f32-velu/gen/velu-avx512f-rr1-lut16-p3-perm-x16.c",
"src/f32-velu/gen/velu-avx512f-rr1-lut16-p3-perm-x32.c",
"src/f32-velu/gen/velu-avx512f-rr1-lut16-p3-perm-x48.c",
@@ -2473,8 +6810,12 @@
"src/f32-velu/gen/velu-avx512f-rr1-p6-x96.c",
"src/f32-velu/gen/velu-avx512f-rr1-p6-x112.c",
"src/f32-velu/gen/velu-avx512f-rr1-p6-x128.c",
+ "src/f32-vhswish/gen/vhswish-avx512f-x16.c",
+ "src/f32-vhswish/gen/vhswish-avx512f-x32.c",
"src/f32-vlrelu/gen/vlrelu-avx512f-x16.c",
"src/f32-vlrelu/gen/vlrelu-avx512f-x32.c",
+ "src/f32-vrelu/gen/vrelu-avx512f-x16.c",
+ "src/f32-vrelu/gen/vrelu-avx512f-x32.c",
"src/f32-vrnd/gen/vrndd-avx512f-x16.c",
"src/f32-vrnd/gen/vrndd-avx512f-x32.c",
"src/f32-vrnd/gen/vrndne-avx512f-x16.c",
@@ -2483,7 +6824,6 @@
"src/f32-vrnd/gen/vrndu-avx512f-x32.c",
"src/f32-vrnd/gen/vrndz-avx512f-x16.c",
"src/f32-vrnd/gen/vrndz-avx512f-x32.c",
- "src/f32-vscale/avx512f-x64.c",
"src/f32-vscaleexpminusmax/gen/avx512f-p5-scalef-x16.c",
"src/f32-vscaleexpminusmax/gen/avx512f-p5-scalef-x32.c",
"src/f32-vscaleexpminusmax/gen/avx512f-p5-scalef-x48.c",
@@ -2508,6 +6848,54 @@
"src/f32-vscaleextexp/gen/avx512f-p5-scalef-x160.c",
"src/f32-vscaleextexp/gen/avx512f-p5-scalef-x176.c",
"src/f32-vscaleextexp/gen/avx512f-p5-scalef-x192.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x32.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x48.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x64.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x80.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x96.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x112.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x128.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x32.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x48.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x64.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x80.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x96.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x112.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x128.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-div-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-div-x32.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-div-x48.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-div-x64.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-div-x80.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-div-x96.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-div-x112.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-div-x128.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x32.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x48.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x64.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x80.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x96.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x112.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x128.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x32.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x48.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x64.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x80.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x96.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x112.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x128.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x16.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x32.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x48.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x64.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x80.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x96.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x112.c",
+ "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x128.c",
"src/f32-vsqrt/gen/avx512f-nr1fma1adj-x16.c",
"src/f32-vsqrt/gen/avx512f-nr1fma1adj-x32.c",
"src/f32-vsqrt/gen/avx512f-nr1fma1adj-x48.c",
@@ -2560,20 +6948,116 @@
"src/math/sqrt-avx512f-nr2fma.c",
]
-AVX512SKX_UKERNELS = [
- "src/qs8-dwconv/gen/up16x9-minmax-avx512skx-mul32.c",
- "src/qs8-dwconv/gen/up32x9-minmax-avx512skx-mul32.c",
- "src/qs8-gemm/gen/1x16c8-minmax-avx512skx.c",
- "src/qs8-gemm/gen/2x16c8-minmax-avx512skx.c",
- "src/qs8-gemm/gen/3x16c8-minmax-avx512skx.c",
- "src/qs8-gemm/gen/4x16c8-minmax-avx512skx.c",
- "src/qs8-igemm/gen/1x16c8-minmax-avx512skx.c",
- "src/qs8-igemm/gen/2x16c8-minmax-avx512skx.c",
- "src/qs8-igemm/gen/3x16c8-minmax-avx512skx.c",
- "src/qs8-igemm/gen/4x16c8-minmax-avx512skx.c",
+PROD_AVX512SKX_MICROKERNEL_SRCS = [
+ "src/f16-f32-vcvt/gen/vcvt-avx512skx-x16.c",
+ "src/f32-f16-vcvt/gen/vcvt-avx512skx-x16.c",
+ "src/f32-qs8-vcvt/gen/vcvt-avx512skx-x128.c",
+ "src/f32-qu8-vcvt/gen/vcvt-avx512skx-x128.c",
+ "src/qc8-dwconv/gen/up32x9-minmax-fp32-avx512skx-mul32.c",
+ "src/qc8-dwconv/gen/up32x25-minmax-fp32-avx512skx-mul32.c",
+ "src/qc8-gemm/gen/1x16c8-minmax-fp32-avx512skx.c",
+ "src/qc8-gemm/gen/4x16c8-minmax-fp32-avx512skx.c",
+ "src/qc8-igemm/gen/1x16c8-minmax-fp32-avx512skx.c",
+ "src/qc8-igemm/gen/4x16c8-minmax-fp32-avx512skx.c",
+ "src/qs8-dwconv/gen/up32x9-minmax-fp32-avx512skx-mul32.c",
+ "src/qs8-dwconv/gen/up32x25-minmax-fp32-avx512skx-mul32.c",
+ "src/qs8-f32-vcvt/gen/vcvt-avx512skx-x32.c",
+ "src/qs8-gemm/gen/1x16c8-minmax-fp32-avx512skx.c",
+ "src/qs8-gemm/gen/4x16c8-minmax-fp32-avx512skx.c",
+ "src/qs8-igemm/gen/1x16c8-minmax-fp32-avx512skx.c",
+ "src/qs8-igemm/gen/4x16c8-minmax-fp32-avx512skx.c",
+ "src/qs8-vadd/gen/minmax-avx512skx-mul32-ld128-x16.c",
+ "src/qs8-vaddc/gen/minmax-avx512skx-mul32-ld128-x16.c",
+ "src/qu8-dwconv/gen/up32x9-minmax-fp32-avx512skx-mul32.c",
+ "src/qu8-dwconv/gen/up32x25-minmax-fp32-avx512skx-mul32.c",
+ "src/qu8-f32-vcvt/gen/vcvt-avx512skx-x32.c",
+ "src/qu8-gemm/gen/1x16c8-minmax-fp32-avx512skx.c",
+ "src/qu8-gemm/gen/4x16c8-minmax-fp32-avx512skx.c",
+ "src/qu8-igemm/gen/1x16c8-minmax-fp32-avx512skx.c",
+ "src/qu8-igemm/gen/4x16c8-minmax-fp32-avx512skx.c",
+ "src/qu8-vadd/gen/minmax-avx512skx-mul32-ld128-x16.c",
+ "src/qu8-vaddc/gen/minmax-avx512skx-mul32-ld128-x16.c",
+ "src/x8-lut/gen/lut-avx512skx-vpshufb-x64.c",
]
-AARCH32_ASM_UKERNELS = [
+ALL_AVX512SKX_MICROKERNEL_SRCS = [
+ "src/f16-f32-vcvt/gen/vcvt-avx512skx-x16.c",
+ "src/f16-f32-vcvt/gen/vcvt-avx512skx-x32.c",
+ "src/f32-f16-vcvt/gen/vcvt-avx512skx-x16.c",
+ "src/f32-f16-vcvt/gen/vcvt-avx512skx-x32.c",
+ "src/f32-qs8-vcvt/gen/vcvt-avx512skx-x32.c",
+ "src/f32-qs8-vcvt/gen/vcvt-avx512skx-x64.c",
+ "src/f32-qs8-vcvt/gen/vcvt-avx512skx-x96.c",
+ "src/f32-qs8-vcvt/gen/vcvt-avx512skx-x128.c",
+ "src/f32-qu8-vcvt/gen/vcvt-avx512skx-x32.c",
+ "src/f32-qu8-vcvt/gen/vcvt-avx512skx-x64.c",
+ "src/f32-qu8-vcvt/gen/vcvt-avx512skx-x96.c",
+ "src/f32-qu8-vcvt/gen/vcvt-avx512skx-x128.c",
+ "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx512skx-mul32.c",
+ "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx512skx-mul32.c",
+ "src/qc8-dwconv/gen/up32x9-minmax-fp32-avx512skx-mul32.c",
+ "src/qc8-dwconv/gen/up32x25-minmax-fp32-avx512skx-mul32.c",
+ "src/qc8-gemm/gen/1x16c8-minmax-fp32-avx512skx.c",
+ "src/qc8-gemm/gen/2x16c8-minmax-fp32-avx512skx.c",
+ "src/qc8-gemm/gen/3x16c8-minmax-fp32-avx512skx.c",
+ "src/qc8-gemm/gen/4x16c8-minmax-fp32-avx512skx.c",
+ "src/qc8-igemm/gen/1x16c8-minmax-fp32-avx512skx.c",
+ "src/qc8-igemm/gen/2x16c8-minmax-fp32-avx512skx.c",
+ "src/qc8-igemm/gen/3x16c8-minmax-fp32-avx512skx.c",
+ "src/qc8-igemm/gen/4x16c8-minmax-fp32-avx512skx.c",
+ "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx512skx-mul32.c",
+ "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx512skx-mul32.c",
+ "src/qs8-dwconv/gen/up32x9-minmax-fp32-avx512skx-mul32.c",
+ "src/qs8-dwconv/gen/up32x25-minmax-fp32-avx512skx-mul32.c",
+ "src/qs8-f32-vcvt/gen/vcvt-avx512skx-x16.c",
+ "src/qs8-f32-vcvt/gen/vcvt-avx512skx-x32.c",
+ "src/qs8-f32-vcvt/gen/vcvt-avx512skx-x48.c",
+ "src/qs8-f32-vcvt/gen/vcvt-avx512skx-x64.c",
+ "src/qs8-gemm/gen/1x16c8-minmax-fp32-avx512skx.c",
+ "src/qs8-gemm/gen/2x16c8-minmax-fp32-avx512skx.c",
+ "src/qs8-gemm/gen/3x16c8-minmax-fp32-avx512skx.c",
+ "src/qs8-gemm/gen/4x16c8-minmax-fp32-avx512skx.c",
+ "src/qs8-igemm/gen/1x16c8-minmax-fp32-avx512skx.c",
+ "src/qs8-igemm/gen/2x16c8-minmax-fp32-avx512skx.c",
+ "src/qs8-igemm/gen/3x16c8-minmax-fp32-avx512skx.c",
+ "src/qs8-igemm/gen/4x16c8-minmax-fp32-avx512skx.c",
+ "src/qs8-vadd/gen/minmax-avx512skx-mul32-ld128-x16.c",
+ "src/qs8-vadd/gen/minmax-avx512skx-mul32-ld128-x32.c",
+ "src/qs8-vaddc/gen/minmax-avx512skx-mul32-ld128-x16.c",
+ "src/qs8-vaddc/gen/minmax-avx512skx-mul32-ld128-x32.c",
+ "src/qu8-dwconv/gen/up16x9-minmax-fp32-avx512skx-mul32.c",
+ "src/qu8-dwconv/gen/up16x25-minmax-fp32-avx512skx-mul32.c",
+ "src/qu8-dwconv/gen/up32x9-minmax-fp32-avx512skx-mul32.c",
+ "src/qu8-dwconv/gen/up32x25-minmax-fp32-avx512skx-mul32.c",
+ "src/qu8-f32-vcvt/gen/vcvt-avx512skx-x16.c",
+ "src/qu8-f32-vcvt/gen/vcvt-avx512skx-x32.c",
+ "src/qu8-f32-vcvt/gen/vcvt-avx512skx-x48.c",
+ "src/qu8-f32-vcvt/gen/vcvt-avx512skx-x64.c",
+ "src/qu8-gemm/gen/1x16c8-minmax-fp32-avx512skx.c",
+ "src/qu8-gemm/gen/2x16c8-minmax-fp32-avx512skx.c",
+ "src/qu8-gemm/gen/3x16c8-minmax-fp32-avx512skx.c",
+ "src/qu8-gemm/gen/4x16c8-minmax-fp32-avx512skx.c",
+ "src/qu8-igemm/gen/1x16c8-minmax-fp32-avx512skx.c",
+ "src/qu8-igemm/gen/2x16c8-minmax-fp32-avx512skx.c",
+ "src/qu8-igemm/gen/3x16c8-minmax-fp32-avx512skx.c",
+ "src/qu8-igemm/gen/4x16c8-minmax-fp32-avx512skx.c",
+ "src/qu8-vadd/gen/minmax-avx512skx-mul32-ld128-x16.c",
+ "src/qu8-vadd/gen/minmax-avx512skx-mul32-ld128-x32.c",
+ "src/qu8-vaddc/gen/minmax-avx512skx-mul32-ld128-x16.c",
+ "src/qu8-vaddc/gen/minmax-avx512skx-mul32-ld128-x32.c",
+ "src/x8-lut/gen/lut-avx512skx-vpshufb-x64.c",
+ "src/x8-lut/gen/lut-avx512skx-vpshufb-x128.c",
+ "src/x8-lut/gen/lut-avx512skx-vpshufb-x192.c",
+ "src/x8-lut/gen/lut-avx512skx-vpshufb-x256.c",
+]
+
+WASM32_ASM_MICROKERNEL_SRCS = [
+ "src/f32-vrelu/wasm_shr_x1.S",
+ "src/f32-vrelu/wasm_shr_x2.S",
+ "src/f32-vrelu/wasm_shr_x4.S",
+]
+
+AARCH32_ASM_MICROKERNEL_SRCS = [
"src/f32-gemm/4x4-aarch32-vfp-ld64.S",
"src/f32-gemm/4x4-minmax-aarch32-vfp-ld64.S",
"src/f32-gemm/4x8-minmax-aarch32-neon-cortex-a53.S",
@@ -2581,21 +7065,61 @@
"src/f32-gemm/gen/4x8-minmax-aarch32-neon-cortex-a7.S",
"src/f32-gemm/gen/4x8-minmax-aarch32-neon-cortex-a75.S",
"src/f32-gemm/gen/4x8-minmax-aarch32-neon-ld64.S",
- "src/f32-gemm/gen/4x8-minmax-aarch32-neon-pld-cortex-a75.S",
+ "src/f32-gemm/gen/4x8-minmax-aarch32-neon-prfm-cortex-a75.S",
"src/f32-igemm/4x8-minmax-aarch32-neon-cortex-a53.S",
"src/f32-igemm/4x8-minmax-aarch32-neon-cortex-a55.S",
"src/f32-igemm/gen/4x8-minmax-aarch32-neon-cortex-a7.S",
"src/f32-igemm/gen/4x8-minmax-aarch32-neon-cortex-a75.S",
"src/f32-igemm/gen/4x8-minmax-aarch32-neon-ld64.S",
- "src/f32-igemm/gen/4x8-minmax-aarch32-neon-pld-cortex-a75.S",
+ "src/f32-igemm/gen/4x8-minmax-aarch32-neon-prfm-cortex-a75.S",
+ "src/qc8-gemm/gen/4x8-minmax-fp32-aarch32-neon-mlal-lane-cortex-a7.S",
+ "src/qc8-gemm/gen/4x8-minmax-fp32-aarch32-neon-mlal-lane-cortex-a53.S",
+ "src/qc8-gemm/gen/4x8-minmax-fp32-aarch32-neon-mlal-lane-ld64.S",
+ "src/qc8-gemm/gen/4x8-minmax-fp32-aarch32-neon-mlal-lane-prfm-cortex-a7.S",
+ "src/qc8-gemm/gen/4x8-minmax-fp32-aarch32-neon-mlal-lane-prfm-cortex-a53.S",
+ "src/qc8-gemm/gen/4x8-minmax-fp32-aarch32-neon-mlal-lane-prfm-ld64.S",
+ "src/qc8-gemm/gen/4x8-minmax-fp32-aarch32-neonv8-mlal-lane-cortex-a53.S",
+ "src/qc8-gemm/gen/4x8-minmax-fp32-aarch32-neonv8-mlal-lane-ld64.S",
+ "src/qc8-gemm/gen/4x8-minmax-fp32-aarch32-neonv8-mlal-lane-prfm-cortex-a53.S",
+ "src/qc8-gemm/gen/4x8-minmax-fp32-aarch32-neonv8-mlal-lane-prfm-ld64.S",
+ "src/qc8-gemm/gen/4x8c4-minmax-fp32-aarch32-neondot-cortex-a55.S",
+ "src/qc8-gemm/gen/4x8c4-minmax-fp32-aarch32-neondot-ld64.S",
+ "src/qc8-igemm/gen/4x8-minmax-fp32-aarch32-neon-mlal-lane-ld64.S",
+ "src/qc8-igemm/gen/4x8-minmax-fp32-aarch32-neon-mlal-lane-prfm-ld64.S",
+ "src/qc8-igemm/gen/4x8-minmax-fp32-aarch32-neonv8-mlal-lane-ld64.S",
+ "src/qc8-igemm/gen/4x8-minmax-fp32-aarch32-neonv8-mlal-lane-prfm-ld64.S",
+ "src/qc8-igemm/gen/4x8c4-minmax-fp32-aarch32-neondot-cortex-a55.S",
+ "src/qc8-igemm/gen/4x8c4-minmax-fp32-aarch32-neondot-ld64.S",
+ "src/qs8-gemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-cortex-a7.S",
+ "src/qs8-gemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-cortex-a53.S",
+ "src/qs8-gemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-ld64.S",
+ "src/qs8-gemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-prfm-cortex-a7.S",
+ "src/qs8-gemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-prfm-cortex-a53.S",
+ "src/qs8-gemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-prfm-ld64.S",
+ "src/qs8-gemm/gen/4x8c4-minmax-rndnu-aarch32-neondot-cortex-a55.S",
+ "src/qs8-gemm/gen/4x8c4-minmax-rndnu-aarch32-neondot-ld64.S",
+ "src/qs8-igemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-ld64.S",
+ "src/qs8-igemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-prfm-ld64.S",
+ "src/qs8-igemm/gen/4x8c4-minmax-rndnu-aarch32-neondot-cortex-a55.S",
+ "src/qs8-igemm/gen/4x8c4-minmax-rndnu-aarch32-neondot-ld64.S",
+ "src/qu8-gemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-cortex-a7.S",
+ "src/qu8-gemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-cortex-a53.S",
+ "src/qu8-gemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-ld64.S",
+ "src/qu8-gemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-prfm-cortex-a7.S",
+ "src/qu8-gemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-prfm-cortex-a53.S",
+ "src/qu8-gemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-prfm-ld64.S",
+ "src/qu8-igemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-ld64.S",
+ "src/qu8-igemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-prfm-ld64.S",
]
-AARCH64_ASM_UKERNELS = [
+AARCH64_ASM_MICROKERNEL_SRCS = [
"src/f16-gemm/gen-inc/1x8inc-minmax-aarch64-neonfp16arith-ld64.S",
"src/f16-gemm/gen-inc/1x16inc-minmax-aarch64-neonfp16arith-ld32.S",
"src/f16-gemm/gen-inc/4x8inc-minmax-aarch64-neonfp16arith-ld64.S",
"src/f16-gemm/gen-inc/4x16inc-minmax-aarch64-neonfp16arith-ld32.S",
"src/f16-gemm/gen-inc/6x8inc-minmax-aarch64-neonfp16arith-ld64.S",
+ "src/f16-gemm/gen-inc/6x16inc-minmax-aarch64-neonfp16arith-cortex-a55.S",
+ "src/f16-gemm/gen-inc/6x16inc-minmax-aarch64-neonfp16arith-cortex-a75.S",
"src/f16-gemm/gen-inc/6x16inc-minmax-aarch64-neonfp16arith-ld32.S",
"src/f16-gemm/gen-inc/8x8inc-minmax-aarch64-neonfp16arith-ld64.S",
"src/f16-gemm/gen/1x8-minmax-aarch64-neonfp16arith-ld64.S",
@@ -2603,52 +7127,54 @@
"src/f16-gemm/gen/4x8-minmax-aarch64-neonfp16arith-ld64.S",
"src/f16-gemm/gen/4x16-minmax-aarch64-neonfp16arith-ld32.S",
"src/f16-gemm/gen/6x8-minmax-aarch64-neonfp16arith-ld64.S",
+ "src/f16-gemm/gen/6x16-minmax-aarch64-neonfp16arith-cortex-a55.S",
+ "src/f16-gemm/gen/6x16-minmax-aarch64-neonfp16arith-cortex-a75.S",
"src/f16-gemm/gen/6x16-minmax-aarch64-neonfp16arith-ld32.S",
"src/f16-gemm/gen/8x8-minmax-aarch64-neonfp16arith-ld64.S",
"src/f32-dwconv/up4x9-minmax-aarch64-neonfma-cortex-a55.S",
"src/f32-dwconv/up4x9-minmax-aarch64-neonfma.S",
"src/f32-gemm/gen-inc/1x8inc-minmax-aarch64-neonfma-cortex-a53.S",
- "src/f32-gemm/gen-inc/1x8inc-minmax-aarch64-neonfma-cortex-a57.S",
"src/f32-gemm/gen-inc/1x8inc-minmax-aarch64-neonfma-cortex-a75.S",
"src/f32-gemm/gen-inc/1x8inc-minmax-aarch64-neonfma-ld64.S",
+ "src/f32-gemm/gen-inc/1x8inc-minmax-aarch64-neonfma-prfm-cortex-a75.S",
"src/f32-gemm/gen-inc/1x12inc-minmax-aarch64-neonfma-cortex-a53.S",
"src/f32-gemm/gen-inc/4x8inc-minmax-aarch64-neonfma-cortex-a53.S",
"src/f32-gemm/gen-inc/4x8inc-minmax-aarch64-neonfma-cortex-a55.S",
- "src/f32-gemm/gen-inc/4x8inc-minmax-aarch64-neonfma-cortex-a57.S",
"src/f32-gemm/gen-inc/4x8inc-minmax-aarch64-neonfma-cortex-a75.S",
"src/f32-gemm/gen-inc/4x8inc-minmax-aarch64-neonfma-ld64.S",
"src/f32-gemm/gen-inc/4x8inc-minmax-aarch64-neonfma-ld128.S",
+ "src/f32-gemm/gen-inc/4x8inc-minmax-aarch64-neonfma-prfm-cortex-a75.S",
"src/f32-gemm/gen-inc/4x12inc-minmax-aarch64-neonfma-cortex-a53.S",
- "src/f32-gemm/gen-inc/5x8inc-minmax-aarch64-neonfma-cortex-a57.S",
"src/f32-gemm/gen-inc/5x8inc-minmax-aarch64-neonfma-cortex-a75.S",
+ "src/f32-gemm/gen-inc/5x8inc-minmax-aarch64-neonfma-prfm-cortex-a75.S",
"src/f32-gemm/gen-inc/6x8inc-minmax-aarch64-neonfma-cortex-a53.S",
"src/f32-gemm/gen-inc/6x8inc-minmax-aarch64-neonfma-cortex-a55.S",
- "src/f32-gemm/gen-inc/6x8inc-minmax-aarch64-neonfma-cortex-a57.S",
"src/f32-gemm/gen-inc/6x8inc-minmax-aarch64-neonfma-cortex-a73.S",
"src/f32-gemm/gen-inc/6x8inc-minmax-aarch64-neonfma-cortex-a75.S",
"src/f32-gemm/gen-inc/6x8inc-minmax-aarch64-neonfma-ld64.S",
"src/f32-gemm/gen-inc/6x8inc-minmax-aarch64-neonfma-ld128.S",
+ "src/f32-gemm/gen-inc/6x8inc-minmax-aarch64-neonfma-prfm-cortex-a75.S",
"src/f32-gemm/gen/1x8-minmax-aarch64-neonfma-cortex-a53.S",
- "src/f32-gemm/gen/1x8-minmax-aarch64-neonfma-cortex-a57.S",
"src/f32-gemm/gen/1x8-minmax-aarch64-neonfma-cortex-a75.S",
"src/f32-gemm/gen/1x8-minmax-aarch64-neonfma-ld64.S",
+ "src/f32-gemm/gen/1x8-minmax-aarch64-neonfma-prfm-cortex-a75.S",
"src/f32-gemm/gen/1x12-minmax-aarch64-neonfma-cortex-a53.S",
"src/f32-gemm/gen/4x8-minmax-aarch64-neonfma-cortex-a53.S",
"src/f32-gemm/gen/4x8-minmax-aarch64-neonfma-cortex-a55.S",
- "src/f32-gemm/gen/4x8-minmax-aarch64-neonfma-cortex-a57.S",
"src/f32-gemm/gen/4x8-minmax-aarch64-neonfma-cortex-a75.S",
"src/f32-gemm/gen/4x8-minmax-aarch64-neonfma-ld64.S",
"src/f32-gemm/gen/4x8-minmax-aarch64-neonfma-ld128.S",
+ "src/f32-gemm/gen/4x8-minmax-aarch64-neonfma-prfm-cortex-a75.S",
"src/f32-gemm/gen/4x12-minmax-aarch64-neonfma-cortex-a53.S",
- "src/f32-gemm/gen/5x8-minmax-aarch64-neonfma-cortex-a57.S",
"src/f32-gemm/gen/5x8-minmax-aarch64-neonfma-cortex-a75.S",
+ "src/f32-gemm/gen/5x8-minmax-aarch64-neonfma-prfm-cortex-a75.S",
"src/f32-gemm/gen/6x8-minmax-aarch64-neonfma-cortex-a53.S",
"src/f32-gemm/gen/6x8-minmax-aarch64-neonfma-cortex-a55.S",
- "src/f32-gemm/gen/6x8-minmax-aarch64-neonfma-cortex-a57.S",
"src/f32-gemm/gen/6x8-minmax-aarch64-neonfma-cortex-a73.S",
"src/f32-gemm/gen/6x8-minmax-aarch64-neonfma-cortex-a75.S",
"src/f32-gemm/gen/6x8-minmax-aarch64-neonfma-ld64.S",
"src/f32-gemm/gen/6x8-minmax-aarch64-neonfma-ld128.S",
+ "src/f32-gemm/gen/6x8-minmax-aarch64-neonfma-prfm-cortex-a75.S",
"src/f32-igemm/1x8-minmax-aarch64-neonfma-cortex-a53.S",
"src/f32-igemm/1x12-minmax-aarch64-neonfma-cortex-a53.S",
"src/f32-igemm/4x8-minmax-aarch64-neonfma-cortex-a53.S",
@@ -2657,26 +7183,182 @@
"src/f32-igemm/6x8-minmax-aarch64-neonfma-cortex-a53.S",
"src/f32-igemm/6x8-minmax-aarch64-neonfma-cortex-a55.S",
"src/f32-igemm/6x8-minmax-aarch64-neonfma-cortex-a73.S",
- "src/f32-igemm/gen/1x8-minmax-aarch64-neonfma-cortex-a57.S",
"src/f32-igemm/gen/1x8-minmax-aarch64-neonfma-cortex-a75.S",
- "src/f32-igemm/gen/4x8-minmax-aarch64-neonfma-cortex-a57.S",
+ "src/f32-igemm/gen/1x8-minmax-aarch64-neonfma-prfm-cortex-a75.S",
"src/f32-igemm/gen/4x8-minmax-aarch64-neonfma-cortex-a75.S",
- "src/f32-igemm/gen/5x8-minmax-aarch64-neonfma-cortex-a57.S",
+ "src/f32-igemm/gen/4x8-minmax-aarch64-neonfma-ld64.S",
+ "src/f32-igemm/gen/4x8-minmax-aarch64-neonfma-ld128.S",
+ "src/f32-igemm/gen/4x8-minmax-aarch64-neonfma-prfm-cortex-a75.S",
"src/f32-igemm/gen/5x8-minmax-aarch64-neonfma-cortex-a75.S",
- "src/f32-igemm/gen/6x8-minmax-aarch64-neonfma-cortex-a57.S",
+ "src/f32-igemm/gen/5x8-minmax-aarch64-neonfma-prfm-cortex-a75.S",
"src/f32-igemm/gen/6x8-minmax-aarch64-neonfma-cortex-a75.S",
- "src/qs8-gemm/1x16c4-aarch64-neondot-ld32.S",
- "src/qs8-gemm/1x16c4-aarch64-neondot-ld64.S",
- "src/qs8-gemm/2x8c8-aarch64-neon-mull-padal.S",
- "src/qs8-gemm/2x8c8-aarch64-neon-mlal-padal.S",
- "src/qs8-gemm/2x8c16-aarch64-neon-mlal-padal.S",
- "src/qs8-gemm/4x16c4-aarch64-neondot-cortex-a55.S",
- "src/qs8-gemm/4x16c4-aarch64-neondot-ld32.S",
- "src/qs8-gemm/4x16c4-aarch64-neondot-ld64.S",
- "src/qs8-igemm/2x8c8-aarch64-neon-mlal-padal.S",
- "src/qs8-igemm/2x8c16-aarch64-neon-mlal-padal.S",
- "src/qs8-igemm/4x16c4-aarch64-neondot-cortex-a55.S",
- "src/qs8-igemm/4x16c4-aarch64-neondot-ld64.S",
+ "src/f32-igemm/gen/6x8-minmax-aarch64-neonfma-ld64.S",
+ "src/f32-igemm/gen/6x8-minmax-aarch64-neonfma-ld128.S",
+ "src/f32-igemm/gen/6x8-minmax-aarch64-neonfma-prfm-cortex-a75.S",
+ "src/qc8-gemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal-cortex-a53.S",
+ "src/qc8-gemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal-prfm-cortex-a53.S",
+ "src/qc8-gemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal-prfm.S",
+ "src/qc8-gemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal.S",
+ "src/qc8-gemm/gen/1x16c4-minmax-fp32-aarch64-neondot-ld32.S",
+ "src/qc8-gemm/gen/1x16c4-minmax-fp32-aarch64-neondot-ld64.S",
+ "src/qc8-gemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal-cortex-a53.S",
+ "src/qc8-gemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal-prfm-cortex-a53.S",
+ "src/qc8-gemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal-prfm.S",
+ "src/qc8-gemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal.S",
+ "src/qc8-gemm/gen/2x8c8-minmax-fp32-aarch64-neon-mull.S",
+ "src/qc8-gemm/gen/2x8c16-minmax-fp32-aarch64-neon-mlal.S",
+ "src/qc8-gemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-cortex-a53.S",
+ "src/qc8-gemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-ld64.S",
+ "src/qc8-gemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-prfm-cortex-a53.S",
+ "src/qc8-gemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-prfm-ld64.S",
+ "src/qc8-gemm/gen/4x16c4-minmax-fp32-aarch64-neondot-cortex-a55.S",
+ "src/qc8-gemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld32.S",
+ "src/qc8-gemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld64.S",
+ "src/qc8-gemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld128.S",
+ "src/qc8-igemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal-cortex-a53.S",
+ "src/qc8-igemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal-prfm-cortex-a53.S",
+ "src/qc8-igemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal-prfm.S",
+ "src/qc8-igemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal.S",
+ "src/qc8-igemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal-cortex-a53.S",
+ "src/qc8-igemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal-prfm-cortex-a53.S",
+ "src/qc8-igemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal-prfm.S",
+ "src/qc8-igemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal.S",
+ "src/qc8-igemm/gen/2x8c16-minmax-fp32-aarch64-neon-mlal.S",
+ "src/qc8-igemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-cortex-a53.S",
+ "src/qc8-igemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-ld64.S",
+ "src/qc8-igemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-prfm-cortex-a53.S",
+ "src/qc8-igemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-prfm-ld64.S",
+ "src/qc8-igemm/gen/4x16c4-minmax-fp32-aarch64-neondot-cortex-a55.S",
+ "src/qc8-igemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld64.S",
+ "src/qc8-igemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld128.S",
+ "src/qs8-gemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal-cortex-a53.S",
+ "src/qs8-gemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal-prfm-cortex-a53.S",
+ "src/qs8-gemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal-prfm.S",
+ "src/qs8-gemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal.S",
+ "src/qs8-gemm/gen/1x8c8-minmax-rndnu-aarch64-neon-mlal-cortex-a53.S",
+ "src/qs8-gemm/gen/1x8c8-minmax-rndnu-aarch64-neon-mlal-prfm-cortex-a53.S",
+ "src/qs8-gemm/gen/1x8c8-minmax-rndnu-aarch64-neon-mlal-prfm.S",
+ "src/qs8-gemm/gen/1x8c8-minmax-rndnu-aarch64-neon-mlal.S",
+ "src/qs8-gemm/gen/1x16c4-minmax-fp32-aarch64-neondot-ld32.S",
+ "src/qs8-gemm/gen/1x16c4-minmax-fp32-aarch64-neondot-ld64.S",
+ "src/qs8-gemm/gen/1x16c4-minmax-rndnu-aarch64-neondot-ld32.S",
+ "src/qs8-gemm/gen/1x16c4-minmax-rndnu-aarch64-neondot-ld64.S",
+ "src/qs8-gemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal-cortex-a53.S",
+ "src/qs8-gemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal-prfm-cortex-a53.S",
+ "src/qs8-gemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal-prfm.S",
+ "src/qs8-gemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal.S",
+ "src/qs8-gemm/gen/2x8c8-minmax-fp32-aarch64-neon-mull.S",
+ "src/qs8-gemm/gen/2x8c8-minmax-rndnu-aarch64-neon-mlal-cortex-a53.S",
+ "src/qs8-gemm/gen/2x8c8-minmax-rndnu-aarch64-neon-mlal-prfm-cortex-a53.S",
+ "src/qs8-gemm/gen/2x8c8-minmax-rndnu-aarch64-neon-mlal-prfm.S",
+ "src/qs8-gemm/gen/2x8c8-minmax-rndnu-aarch64-neon-mlal.S",
+ "src/qs8-gemm/gen/2x8c8-minmax-rndnu-aarch64-neon-mull.S",
+ "src/qs8-gemm/gen/2x8c16-minmax-fp32-aarch64-neon-mlal.S",
+ "src/qs8-gemm/gen/2x8c16-minmax-rndnu-aarch64-neon-mlal.S",
+ "src/qs8-gemm/gen/4x8-minmax-rndnu-aarch64-neon-mlal-lane-ld64.S",
+ "src/qs8-gemm/gen/4x8-minmax-rndnu-aarch64-neon-mlal-lane-prfm-ld64.S",
+ "src/qs8-gemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-cortex-a53.S",
+ "src/qs8-gemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-ld64.S",
+ "src/qs8-gemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-prfm-cortex-a53.S",
+ "src/qs8-gemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-prfm-ld64.S",
+ "src/qs8-gemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-cortex-a53.S",
+ "src/qs8-gemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-ld64.S",
+ "src/qs8-gemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-prfm-cortex-a53.S",
+ "src/qs8-gemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-prfm-ld64.S",
+ "src/qs8-gemm/gen/4x16c4-minmax-fp32-aarch64-neondot-cortex-a55.S",
+ "src/qs8-gemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld32.S",
+ "src/qs8-gemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld64.S",
+ "src/qs8-gemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld128.S",
+ "src/qs8-gemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-cortex-a55.S",
+ "src/qs8-gemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-ld32.S",
+ "src/qs8-gemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-ld64.S",
+ "src/qs8-gemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-ld128.S",
+ "src/qs8-igemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal-cortex-a53.S",
+ "src/qs8-igemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal-prfm-cortex-a53.S",
+ "src/qs8-igemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal-prfm.S",
+ "src/qs8-igemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal.S",
+ "src/qs8-igemm/gen/1x8c8-minmax-rndnu-aarch64-neon-mlal-cortex-a53.S",
+ "src/qs8-igemm/gen/1x8c8-minmax-rndnu-aarch64-neon-mlal-prfm-cortex-a53.S",
+ "src/qs8-igemm/gen/1x8c8-minmax-rndnu-aarch64-neon-mlal-prfm.S",
+ "src/qs8-igemm/gen/1x8c8-minmax-rndnu-aarch64-neon-mlal.S",
+ "src/qs8-igemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal-cortex-a53.S",
+ "src/qs8-igemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal-prfm-cortex-a53.S",
+ "src/qs8-igemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal-prfm.S",
+ "src/qs8-igemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal.S",
+ "src/qs8-igemm/gen/2x8c8-minmax-rndnu-aarch64-neon-mlal-cortex-a53.S",
+ "src/qs8-igemm/gen/2x8c8-minmax-rndnu-aarch64-neon-mlal-prfm-cortex-a53.S",
+ "src/qs8-igemm/gen/2x8c8-minmax-rndnu-aarch64-neon-mlal-prfm.S",
+ "src/qs8-igemm/gen/2x8c8-minmax-rndnu-aarch64-neon-mlal.S",
+ "src/qs8-igemm/gen/2x8c16-minmax-fp32-aarch64-neon-mlal.S",
+ "src/qs8-igemm/gen/2x8c16-minmax-rndnu-aarch64-neon-mlal.S",
+ "src/qs8-igemm/gen/4x8-minmax-rndnu-aarch64-neon-mlal-lane-ld64.S",
+ "src/qs8-igemm/gen/4x8-minmax-rndnu-aarch64-neon-mlal-lane-prfm-ld64.S",
+ "src/qs8-igemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-cortex-a53.S",
+ "src/qs8-igemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-ld64.S",
+ "src/qs8-igemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-prfm-cortex-a53.S",
+ "src/qs8-igemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-prfm-ld64.S",
+ "src/qs8-igemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-cortex-a53.S",
+ "src/qs8-igemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-ld64.S",
+ "src/qs8-igemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-prfm-cortex-a53.S",
+ "src/qs8-igemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-prfm-ld64.S",
+ "src/qs8-igemm/gen/4x16c4-minmax-fp32-aarch64-neondot-cortex-a55.S",
+ "src/qs8-igemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld64.S",
+ "src/qs8-igemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld128.S",
+ "src/qs8-igemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-cortex-a55.S",
+ "src/qs8-igemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-ld64.S",
+ "src/qs8-igemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-ld128.S",
+ "src/qu8-gemm/gen/4x8c4-minmax-rndnu-aarch64-neondot-cortex-a55.S",
+ "src/qu8-gemm/gen/4x8c4-minmax-rndnu-aarch64-neondot-ld128.S",
+ "src/qu8-gemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-cortex-a53.S",
+ "src/qu8-gemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-cortex-a75.S",
+ "src/qu8-gemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-ld64.S",
+ "src/qu8-gemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-prfm-cortex-a53.S",
+ "src/qu8-gemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-prfm-cortex-a75.S",
+ "src/qu8-gemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-prfm-ld64.S",
+ "src/qu8-gemm/gen/4x16c4-minmax-fp32-aarch64-neondot-cortex-a55.S",
+ "src/qu8-gemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld128.S",
+ "src/qu8-gemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-cortex-a55.S",
+ "src/qu8-gemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-ld128.S",
+ "src/qu8-igemm/gen/4x8c4-minmax-rndnu-aarch64-neondot-cortex-a55.S",
+ "src/qu8-igemm/gen/4x8c4-minmax-rndnu-aarch64-neondot-ld128.S",
+ "src/qu8-igemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-cortex-a53.S",
+ "src/qu8-igemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-cortex-a75.S",
+ "src/qu8-igemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-ld64.S",
+ "src/qu8-igemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-prfm-cortex-a53.S",
+ "src/qu8-igemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-prfm-cortex-a75.S",
+ "src/qu8-igemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-prfm-ld64.S",
+ "src/qu8-igemm/gen/4x16c4-minmax-fp32-aarch64-neondot-cortex-a55.S",
+ "src/qu8-igemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld128.S",
+ "src/qu8-igemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-cortex-a55.S",
+ "src/qu8-igemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-ld128.S",
+]
+
+JIT_AARCH32_SRCS = [
+ "src/f32-gemm/4x8-aarch32-neon-cortex-a7.cc",
+ "src/f32-gemm/4x8-aarch32-neon-cortex-a53.cc",
+ "src/f32-gemm/4x8-aarch32-neon-cortex-a55.cc",
+ "src/f32-gemm/4x8-aarch32-neon-cortex-a75.cc",
+ "src/f32-gemm/4x8-aarch32-neon-ld64.cc",
+ "src/f32-igemm/4x8-aarch32-neon-cortex-a7.cc",
+ "src/f32-igemm/4x8-aarch32-neon-cortex-a53.cc",
+ "src/f32-igemm/4x8-aarch32-neon-cortex-a55.cc",
+ "src/f32-igemm/4x8-aarch32-neon-cortex-a75.cc",
+ "src/f32-igemm/4x8-aarch32-neon-ld64.cc",
+ "src/qc8-gemm/4x8-fp32-aarch32-neonv8-mlal-lane-ld64.cc",
+ "src/qc8-gemm/4x8c4-fp32-aarch32-neondot-ld64.cc",
+ "src/qc8-igemm/4x8-fp32-aarch32-neonv8-mlal-lane-ld64.cc",
+ "src/qc8-igemm/4x8c4-fp32-aarch32-neondot-ld64.cc",
+ "src/qs8-gemm/4x8-rndnu-aarch32-neon-mlal-lane-ld64.cc",
+ "src/qs8-gemm/4x8c4-rndnu-aarch32-neondot-ld64.cc",
+ "src/qs8-igemm/4x8-rndnu-aarch32-neon-mlal-lane-ld64.cc",
+ "src/qs8-igemm/4x8c4-rndnu-aarch32-neondot-ld64.cc",
+]
+
+JIT_AARCH64_SRCS = [
+ "src/f32-gemm/1x8-aarch64-neonfma-cortex-a75.cc",
+ "src/f32-gemm/6x8-aarch64-neonfma-cortex-a75.cc",
+ "src/f32-igemm/1x8-aarch64-neonfma-cortex-a75.cc",
+ "src/f32-igemm/6x8-aarch64-neonfma-cortex-a75.cc",
]
cc_defaults {
@@ -2694,6 +7376,7 @@
"-Wno-missing-field-initializers",
"-Wno-pointer-arith",
"-Wno-implicit-function-declaration",
+ "-Wno-ignored-qualifiers",
],
stl: "libc++_static",
}
@@ -2774,6 +7457,43 @@
}
cc_library_static {
+ name: "xnnpack_jit_memory",
+ defaults: ["xnnpack_internal_default"],
+ srcs: [
+ "src/jit/memory.c",
+ ],
+ static_libs: [
+ "libclog",
+ "libpthreadpool",
+ "xnnpack_logging_utils",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_jit",
+ defaults: ["xnnpack_internal_default"],
+ srcs: [
+ "src/jit/aarch32-assembler.cc",
+ "src/jit/aarch64-assembler.cc",
+ "src/jit/assembler.cc",
+ ],
+ arch: {
+ arm: {
+ srcs: JIT_AARCH32_SRCS,
+ },
+ arm64: {
+ srcs: JIT_AARCH64_SRCS,
+ },
+ },
+ static_libs: [
+ "libclog",
+ "libpthreadpool",
+ "xnnpack_jit_memory",
+ "xnnpack_logging_utils",
+ ],
+}
+
+cc_library_static {
name: "xnnpack_operator_run",
defaults: ["xnnpack_internal_default"],
srcs: [
@@ -2796,7 +7516,7 @@
name: "xnnpack_operators",
defaults: ["xnnpack_internal_default"],
srcs: OPERATOR_SRCS + [
- "src/memory.c",
+ "src/allocator.c",
"src/operator-delete.c",
],
header_libs: [
@@ -2808,16 +7528,18 @@
"libpthreadpool",
"xnnpack_logging_utils",
"xnnpack_packing",
+ "xnnpack_jit_memory",
],
whole_static_libs: [
"xnnpack_indirection",
+ "xnnpack_operator_run",
],
}
cc_library_static {
- name: "xnnpack_scalar_ukernels",
+ name: "xnnpack_scalar_bench_microkernels",
defaults: ["xnnpack_internal_default"],
- srcs: SCALAR_UKERNELS,
+ srcs: ALL_SCALAR_MICROKERNEL_SRCS,
header_libs: [
"fp16_headers",
"fxdiv_headers",
@@ -2829,18 +7551,44 @@
}
cc_library_static {
- name: "xnnpack_neon_ukernels",
+ name: "xnnpack_scalar_prod_microkernels",
defaults: ["xnnpack_internal_default"],
+ srcs: PROD_SCALAR_PORTABLE_MICROKERNEL_SRCS,
arch: {
arm: {
- srcs: NEON_UKERNELS,
+ srcs: PROD_SCALAR_AARCH32_MICROKERNEL_SRCS,
cflags: [
"-marm",
+ ],
+ },
+ arm64: {
+ srcs: PROD_SCALAR_AARCH32_MICROKERNEL_SRCS,
+ },
+ },
+ header_libs: [
+ "fp16_headers",
+ "fxdiv_headers",
+ ],
+ static_libs: [
+ "libpthreadpool",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_neon_bench_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ srcs: ALL_NEON_MICROKERNEL_SRCS,
+ arch: {
+ arm: {
+ cflags: [
+ "-marm",
+ "-march=armv7-a",
"-mfpu=neon",
],
},
arm64: {
- srcs: NEON_UKERNELS,
+ srcs: ALL_AARCH64_NEON_MICROKERNEL_SRCS,
},
x86: { enabled: false, },
x86_64: { enabled: false, },
@@ -2855,22 +7603,19 @@
}
cc_library_static {
- name: "xnnpack_neondot_ukernels",
+ name: "xnnpack_neon_prod_microkernels",
defaults: ["xnnpack_internal_default"],
+ srcs: PROD_NEON_MICROKERNEL_SRCS,
arch: {
arm: {
- srcs: NEONDOT_UKERNELS,
cflags: [
"-marm",
- "-march=armv8.2-a+dotprod",
- "-mfpu=neon-fp-armv8",
+ "-march=armv7-a",
+ "-mfpu=neon",
],
},
arm64: {
- srcs: NEONDOT_UKERNELS,
- cflags: [
- "-march=armv8.2-a+dotprod",
- ],
+ srcs: PROD_AARCH64_NEON_MICROKERNEL_SRCS,
},
x86: { enabled: false, },
x86_64: { enabled: false, },
@@ -2885,11 +7630,65 @@
}
cc_library_static {
- name: "xnnpack_neonfma_ukernels",
+ name: "xnnpack_neonfp16_bench_microkernels",
defaults: ["xnnpack_internal_default"],
arch: {
arm: {
- srcs: NEONFMA_UKERNELS,
+ srcs: ALL_NEONFP16_MICROKERNEL_SRCS,
+ cflags: [
+ "-marm",
+ "-march=armv7-a",
+ "-mfpu=neon-fp16",
+ ],
+ },
+ arm64: {
+ srcs: ALL_NEONFP16_MICROKERNEL_SRCS,
+ },
+ x86: { enabled: false, },
+ x86_64: { enabled: false, },
+ },
+ header_libs: [
+ "fp16_headers",
+ ],
+ static_libs: [
+ "libpthreadpool",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_neonfp16_prod_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: {
+ srcs: PROD_NEONFP16_MICROKERNEL_SRCS,
+ cflags: [
+ "-marm",
+ "-march=armv7-a",
+ "-mfpu=neon-fp16",
+ ],
+ },
+ arm64: {
+ srcs: PROD_NEONFP16_MICROKERNEL_SRCS,
+ },
+ x86: { enabled: false, },
+ x86_64: { enabled: false, },
+ },
+ header_libs: [
+ "fp16_headers",
+ ],
+ static_libs: [
+ "libpthreadpool",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_neonfma_bench_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: {
+ srcs: ALL_NEONFMA_MICROKERNEL_SRCS,
cflags: [
"-marm",
"-march=armv7-a",
@@ -2897,7 +7696,7 @@
],
},
arm64: {
- srcs: NEONFMA_UKERNELS + AARCH64_NEONFMA_UKERNELS,
+ srcs: ALL_NEONFMA_MICROKERNEL_SRCS,
},
x86: { enabled: false, },
x86_64: { enabled: false, },
@@ -2912,11 +7711,38 @@
}
cc_library_static {
- name: "xnnpack_neonv8_ukernels",
+ name: "xnnpack_neonfma_prod_microkernels",
defaults: ["xnnpack_internal_default"],
arch: {
arm: {
- srcs: NEONV8_UKERNELS,
+ srcs: PROD_NEONFMA_MICROKERNEL_SRCS,
+ cflags: [
+ "-marm",
+ "-march=armv7-a",
+ "-mfpu=neon-vfpv4",
+ ],
+ },
+ arm64: {
+ srcs: PROD_NEONFMA_MICROKERNEL_SRCS,
+ },
+ x86: { enabled: false, },
+ x86_64: { enabled: false, },
+ },
+ header_libs: [
+ "fp16_headers",
+ ],
+ static_libs: [
+ "libpthreadpool",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_neonv8_bench_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: {
+ srcs: ALL_NEONV8_MICROKERNEL_SRCS,
cflags: [
"-marm",
"-march=armv8-a",
@@ -2924,7 +7750,7 @@
],
},
arm64: {
- srcs: NEONV8_UKERNELS,
+ srcs: ALL_NEONV8_MICROKERNEL_SRCS,
},
x86: { enabled: false, },
x86_64: { enabled: false, },
@@ -2939,12 +7765,39 @@
}
cc_library_static {
- name: "xnnpack_neonfp16arith_ukernels",
+ name: "xnnpack_neonv8_prod_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: {
+ srcs: PROD_NEONV8_MICROKERNEL_SRCS,
+ cflags: [
+ "-marm",
+ "-march=armv8-a",
+ "-mfpu=neon-fp-armv8",
+ ],
+ },
+ arm64: {
+ srcs: PROD_NEONV8_MICROKERNEL_SRCS,
+ },
+ x86: { enabled: false, },
+ x86_64: { enabled: false, },
+ },
+ header_libs: [
+ "fp16_headers",
+ ],
+ static_libs: [
+ "libpthreadpool",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_neonfp16arith_bench_microkernels",
defaults: ["xnnpack_internal_default"],
arch: {
arm: { enabled: false, },
arm64: {
- srcs: AARCH64_NEONFP16ARITH_UKERNELS,
+ srcs: ALL_AARCH64_NEONFP16ARITH_MICROKERNEL_SRCS,
cflags: [
"-march=armv8.2-a+fp16",
],
@@ -2962,14 +7815,102 @@
}
cc_library_static {
- name: "xnnpack_asm_ukernels",
+ name: "xnnpack_neonfp16arith_prod_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: { enabled: false, },
+ arm64: {
+ srcs: PROD_AARCH64_NEONFP16ARITH_MICROKERNEL_SRCS,
+ cflags: [
+ "-march=armv8.2-a+fp16",
+ ],
+ },
+ x86: { enabled: false, },
+ x86_64: { enabled: false, },
+ },
+ header_libs: [
+ "fp16_headers",
+ ],
+ static_libs: [
+ "libpthreadpool",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_neondot_bench_microkernels",
defaults: ["xnnpack_internal_default"],
arch: {
arm: {
- srcs: AARCH32_ASM_UKERNELS,
+ srcs: ALL_NEONDOT_MICROKERNEL_SRCS,
+ cflags: [
+ "-marm",
+ "-march=armv8.2-a+dotprod",
+ "-mfpu=neon-fp-armv8",
+ ],
},
arm64: {
- srcs: AARCH64_ASM_UKERNELS,
+ srcs: ALL_NEONDOT_MICROKERNEL_SRCS,
+ cflags: [
+ "-march=armv8.2-a+dotprod",
+ ],
+ },
+ x86: { enabled: false, },
+ x86_64: { enabled: false, },
+ },
+ header_libs: [
+ "fp16_headers",
+ ],
+ static_libs: [
+ "libpthreadpool",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_neondot_prod_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: {
+ srcs: PROD_NEONDOT_MICROKERNEL_SRCS,
+ cflags: [
+ "-marm",
+ "-march=armv8.2-a+dotprod",
+ "-mfpu=neon-fp-armv8",
+ ],
+ },
+ arm64: {
+ srcs: PROD_NEONDOT_MICROKERNEL_SRCS,
+ cflags: [
+ "-march=armv8.2-a+dotprod",
+ ],
+ },
+ x86: { enabled: false, },
+ x86_64: { enabled: false, },
+ },
+ header_libs: [
+ "fp16_headers",
+ ],
+ static_libs: [
+ "libpthreadpool",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_asm_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: {
+ srcs: AARCH32_ASM_MICROKERNEL_SRCS,
+ clang_asflags: [
+ "-marm",
+ "-march=armv8.2-a+dotprod",
+ "-mfpu=neon-fp-armv8",
+ ],
+ },
+ arm64: {
+ srcs: AARCH64_ASM_MICROKERNEL_SRCS,
clang_asflags: [
"-march=armv8.2-a+fp16+dotprod",
],
@@ -2980,19 +7921,25 @@
}
cc_library_static {
- name: "xnnpack_sse2_ukernels",
+ name: "xnnpack_sse2_amalgam_microkernels",
defaults: ["xnnpack_internal_default"],
arch: {
arm: { enabled: false, },
arm64: { enabled: false, },
x86: {
- srcs: SSE_UKERNELS + SSE2_UKERNELS,
+ srcs: [
+ "src/amalgam/sse.c",
+ "src/amalgam/sse2.c",
+ ],
cflags: [
"-msse2",
],
},
x86_64: {
- srcs: SSE_UKERNELS + SSE2_UKERNELS,
+ srcs: [
+ "src/amalgam/sse.c",
+ "src/amalgam/sse2.c",
+ ],
cflags: [
"-msse2",
],
@@ -3008,19 +7955,79 @@
}
cc_library_static {
- name: "xnnpack_ssse3_ukernels",
+ name: "xnnpack_sse2_bench_microkernels",
defaults: ["xnnpack_internal_default"],
arch: {
arm: { enabled: false, },
arm64: { enabled: false, },
x86: {
- srcs: SSSE3_UKERNELS,
+ srcs: ALL_SSE_MICROKERNEL_SRCS + ALL_SSE2_MICROKERNEL_SRCS,
+ cflags: [
+ "-msse2",
+ ],
+ },
+ x86_64: {
+ srcs: ALL_SSE_MICROKERNEL_SRCS + ALL_SSE2_MICROKERNEL_SRCS,
+ cflags: [
+ "-msse2",
+ ],
+ },
+ },
+ header_libs: [
+ "fp16_headers",
+ ],
+ static_libs: [
+ "libpthreadpool",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_sse2_prod_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: { enabled: false, },
+ arm64: { enabled: false, },
+ x86: {
+ srcs: ALL_SSE_MICROKERNEL_SRCS + ALL_SSE2_MICROKERNEL_SRCS,
+ cflags: [
+ "-msse2",
+ ],
+ },
+ x86_64: {
+ srcs: ALL_SSE_MICROKERNEL_SRCS + ALL_SSE2_MICROKERNEL_SRCS,
+ cflags: [
+ "-msse2",
+ ],
+ },
+ },
+ header_libs: [
+ "fp16_headers",
+ ],
+ static_libs: [
+ "libpthreadpool",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_ssse3_amalgam_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: { enabled: false, },
+ arm64: { enabled: false, },
+ x86: {
+ srcs: [
+ "src/amalgam/ssse3.c",
+ ],
cflags: [
"-mssse3",
],
},
x86_64: {
- srcs: SSSE3_UKERNELS,
+ srcs: [
+ "src/amalgam/ssse3.c",
+ ],
cflags: [
"-mssse3",
],
@@ -3036,19 +8043,79 @@
}
cc_library_static {
- name: "xnnpack_sse41_ukernels",
+ name: "xnnpack_ssse3_bench_microkernels",
defaults: ["xnnpack_internal_default"],
arch: {
arm: { enabled: false, },
arm64: { enabled: false, },
x86: {
- srcs: SSE41_UKERNELS,
+ srcs: ALL_SSSE3_MICROKERNEL_SRCS,
+ cflags: [
+ "-mssse3",
+ ],
+ },
+ x86_64: {
+ srcs: ALL_SSSE3_MICROKERNEL_SRCS,
+ cflags: [
+ "-mssse3",
+ ],
+ },
+ },
+ header_libs: [
+ "fp16_headers",
+ ],
+ static_libs: [
+ "libpthreadpool",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_ssse3_prod_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: { enabled: false, },
+ arm64: { enabled: false, },
+ x86: {
+ srcs: PROD_SSSE3_MICROKERNEL_SRCS,
+ cflags: [
+ "-mssse3",
+ ],
+ },
+ x86_64: {
+ srcs: PROD_SSSE3_MICROKERNEL_SRCS,
+ cflags: [
+ "-mssse3",
+ ],
+ },
+ },
+ header_libs: [
+ "fp16_headers",
+ ],
+ static_libs: [
+ "libpthreadpool",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_sse41_amalgam_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: { enabled: false, },
+ arm64: { enabled: false, },
+ x86: {
+ srcs: [
+ "src/amalgam/sse41.c",
+ ],
cflags: [
"-msse4.1",
],
},
x86_64: {
- srcs: SSE41_UKERNELS,
+ srcs: [
+ "src/amalgam/sse41.c",
+ ],
cflags: [
"-msse4.1",
],
@@ -3064,19 +8131,79 @@
}
cc_library_static {
- name: "xnnpack_avx_ukernels",
+ name: "xnnpack_sse41_bench_microkernels",
defaults: ["xnnpack_internal_default"],
arch: {
arm: { enabled: false, },
arm64: { enabled: false, },
x86: {
- srcs: AVX_UKERNELS,
+ srcs: ALL_SSE41_MICROKERNEL_SRCS,
+ cflags: [
+ "-msse4.1",
+ ],
+ },
+ x86_64: {
+ srcs: ALL_SSE41_MICROKERNEL_SRCS,
+ cflags: [
+ "-msse4.1",
+ ],
+ },
+ },
+ header_libs: [
+ "fp16_headers",
+ ],
+ static_libs: [
+ "libpthreadpool",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_sse41_prod_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: { enabled: false, },
+ arm64: { enabled: false, },
+ x86: {
+ srcs: PROD_SSE41_MICROKERNEL_SRCS,
+ cflags: [
+ "-msse4.1",
+ ],
+ },
+ x86_64: {
+ srcs: PROD_SSE41_MICROKERNEL_SRCS,
+ cflags: [
+ "-msse4.1",
+ ],
+ },
+ },
+ header_libs: [
+ "fp16_headers",
+ ],
+ static_libs: [
+ "libpthreadpool",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_avx_amalgam_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: { enabled: false, },
+ arm64: { enabled: false, },
+ x86: {
+ srcs: [
+ "src/amalgam/avx.c",
+ ],
cflags: [
"-mavx",
],
},
x86_64: {
- srcs: AVX_UKERNELS,
+ srcs: [
+ "src/amalgam/avx.c",
+ ],
cflags: [
"-mavx",
],
@@ -3092,19 +8219,163 @@
}
cc_library_static {
- name: "xnnpack_xop_ukernels",
+ name: "xnnpack_avx_bench_microkernels",
defaults: ["xnnpack_internal_default"],
arch: {
arm: { enabled: false, },
arm64: { enabled: false, },
x86: {
- srcs: XOP_UKERNELS,
+ srcs: ALL_AVX_MICROKERNEL_SRCS,
+ cflags: [
+ "-mavx",
+ ],
+ },
+ x86_64: {
+ srcs: ALL_AVX_MICROKERNEL_SRCS,
+ cflags: [
+ "-mavx",
+ ],
+ },
+ },
+ header_libs: [
+ "fp16_headers",
+ ],
+ static_libs: [
+ "libpthreadpool",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_avx_prod_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: { enabled: false, },
+ arm64: { enabled: false, },
+ x86: {
+ srcs: PROD_AVX_MICROKERNEL_SRCS,
+ cflags: [
+ "-mavx",
+ ],
+ },
+ x86_64: {
+ srcs: PROD_AVX_MICROKERNEL_SRCS,
+ cflags: [
+ "-mavx",
+ ],
+ },
+ },
+ header_libs: [
+ "fp16_headers",
+ ],
+ static_libs: [
+ "libpthreadpool",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_f16c_amalgam_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: { enabled: false, },
+ arm64: { enabled: false, },
+ x86: {
+ srcs: [
+ "src/amalgam/f16c.c",
+ ],
+ cflags: [
+ "-mf16c",
+ ],
+ },
+ x86_64: {
+ srcs: [
+ "src/amalgam/f16c.c",
+ ],
+ cflags: [
+ "-mf16c",
+ ],
+ },
+ },
+ header_libs: [
+ "fp16_headers",
+ ],
+ static_libs: [
+ "libpthreadpool",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_f16c_bench_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: { enabled: false, },
+ arm64: { enabled: false, },
+ x86: {
+ srcs: ALL_F16C_MICROKERNEL_SRCS,
+ cflags: [
+ "-mf16c",
+ ],
+ },
+ x86_64: {
+ srcs: ALL_F16C_MICROKERNEL_SRCS,
+ cflags: [
+ "-mf16c",
+ ],
+ },
+ },
+ header_libs: [
+ "fp16_headers",
+ ],
+ static_libs: [
+ "libpthreadpool",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_f16c_prod_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: { enabled: false, },
+ arm64: { enabled: false, },
+ x86: {
+ srcs: PROD_F16C_MICROKERNEL_SRCS,
+ cflags: [
+ "-mf16c",
+ ],
+ },
+ x86_64: {
+ srcs: PROD_F16C_MICROKERNEL_SRCS,
+ cflags: [
+ "-mf16c",
+ ],
+ },
+ },
+ header_libs: [
+ "fp16_headers",
+ ],
+ static_libs: [
+ "libpthreadpool",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_xop_bench_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: { enabled: false, },
+ arm64: { enabled: false, },
+ x86: {
+ srcs: ALL_XOP_MICROKERNEL_SRCS,
cflags: [
"-mxop",
],
},
x86_64: {
- srcs: XOP_UKERNELS,
+ srcs: ALL_XOP_MICROKERNEL_SRCS,
cflags: [
"-mxop",
],
@@ -3120,20 +8391,54 @@
}
cc_library_static {
- name: "xnnpack_fma3_ukernels",
+ name: "xnnpack_xop_prod_microkernels",
defaults: ["xnnpack_internal_default"],
arch: {
arm: { enabled: false, },
arm64: { enabled: false, },
x86: {
- srcs: FMA3_UKERNELS,
+ srcs: PROD_XOP_MICROKERNEL_SRCS,
cflags: [
+ "-mxop",
+ ],
+ },
+ x86_64: {
+ srcs: PROD_XOP_MICROKERNEL_SRCS,
+ cflags: [
+ "-mxop",
+ ],
+ },
+ },
+ header_libs: [
+ "fp16_headers",
+ ],
+ static_libs: [
+ "libpthreadpool",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_fma3_amalgam_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: { enabled: false, },
+ arm64: { enabled: false, },
+ x86: {
+ srcs: [
+ "src/amalgam/fma3.c",
+ ],
+ cflags: [
+ "-mf16c",
"-mfma",
],
},
x86_64: {
- srcs: FMA3_UKERNELS,
+ srcs: [
+ "src/amalgam/fma3.c",
+ ],
cflags: [
+ "-mf16c",
"-mfma",
],
},
@@ -3148,21 +8453,87 @@
}
cc_library_static {
- name: "xnnpack_avx2_ukernels",
+ name: "xnnpack_fma3_bench_microkernels",
defaults: ["xnnpack_internal_default"],
arch: {
arm: { enabled: false, },
arm64: { enabled: false, },
x86: {
- srcs: AVX2_UKERNELS,
+ srcs: ALL_FMA3_MICROKERNEL_SRCS,
cflags: [
+ "-mf16c",
+ "-mfma",
+ ],
+ },
+ x86_64: {
+ srcs: ALL_FMA3_MICROKERNEL_SRCS,
+ cflags: [
+ "-mf16c",
+ "-mfma",
+ ],
+ },
+ },
+ header_libs: [
+ "fp16_headers",
+ ],
+ static_libs: [
+ "libpthreadpool",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_fma3_prod_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: { enabled: false, },
+ arm64: { enabled: false, },
+ x86: {
+ srcs: PROD_FMA3_MICROKERNEL_SRCS,
+ cflags: [
+ "-mf16c",
+ "-mfma",
+ ],
+ },
+ x86_64: {
+ srcs: PROD_FMA3_MICROKERNEL_SRCS,
+ cflags: [
+ "-mf16c",
+ "-mfma",
+ ],
+ },
+ },
+ header_libs: [
+ "fp16_headers",
+ ],
+ static_libs: [
+ "libpthreadpool",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_avx2_amalgam_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: { enabled: false, },
+ arm64: { enabled: false, },
+ x86: {
+ srcs: [
+ "src/amalgam/avx2.c",
+ ],
+ cflags: [
+ "-mf16c",
"-mfma",
"-mavx2",
],
},
x86_64: {
- srcs: AVX2_UKERNELS,
+ srcs: [
+ "src/amalgam/avx2.c",
+ ],
cflags: [
+ "-mf16c",
"-mfma",
"-mavx2",
],
@@ -3178,13 +8549,79 @@
}
cc_library_static {
- name: "xnnpack_avx512skx_ukernels",
+ name: "xnnpack_avx2_bench_microkernels",
defaults: ["xnnpack_internal_default"],
arch: {
arm: { enabled: false, },
arm64: { enabled: false, },
x86: {
- srcs: AVX512SKX_UKERNELS,
+ srcs: ALL_AVX2_MICROKERNEL_SRCS,
+ cflags: [
+ "-mf16c",
+ "-mfma",
+ "-mavx2",
+ ],
+ },
+ x86_64: {
+ srcs: ALL_AVX2_MICROKERNEL_SRCS,
+ cflags: [
+ "-mf16c",
+ "-mfma",
+ "-mavx2",
+ ],
+ },
+ },
+ header_libs: [
+ "fp16_headers",
+ ],
+ static_libs: [
+ "libpthreadpool",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_avx2_prod_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: { enabled: false, },
+ arm64: { enabled: false, },
+ x86: {
+ srcs: PROD_AVX2_MICROKERNEL_SRCS,
+ cflags: [
+ "-mf16c",
+ "-mfma",
+ "-mavx2",
+ ],
+ },
+ x86_64: {
+ srcs: PROD_AVX2_MICROKERNEL_SRCS,
+ cflags: [
+ "-mf16c",
+ "-mfma",
+ "-mavx2",
+ ],
+ },
+ },
+ header_libs: [
+ "fp16_headers",
+ ],
+ static_libs: [
+ "libpthreadpool",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_avx512skx_amalgam_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: { enabled: false, },
+ arm64: { enabled: false, },
+ x86: {
+ srcs: [
+ "src/amalgam/avx512skx.c",
+ ],
cflags: [
"-mavx512f",
"-mavx512cd",
@@ -3194,7 +8631,9 @@
],
},
x86_64: {
- srcs: AVX512SKX_UKERNELS,
+ srcs: [
+ "src/amalgam/avx512skx.c",
+ ],
cflags: [
"-mavx512f",
"-mavx512cd",
@@ -3214,19 +8653,95 @@
}
cc_library_static {
- name: "xnnpack_avx512f_ukernels",
+ name: "xnnpack_avx512skx_bench_microkernels",
defaults: ["xnnpack_internal_default"],
arch: {
arm: { enabled: false, },
arm64: { enabled: false, },
x86: {
- srcs: AVX512F_UKERNELS,
+ srcs: ALL_AVX512SKX_MICROKERNEL_SRCS,
+ cflags: [
+ "-mavx512f",
+ "-mavx512cd",
+ "-mavx512bw",
+ "-mavx512dq",
+ "-mavx512vl",
+ ],
+ },
+ x86_64: {
+ srcs: ALL_AVX512SKX_MICROKERNEL_SRCS,
+ cflags: [
+ "-mavx512f",
+ "-mavx512cd",
+ "-mavx512bw",
+ "-mavx512dq",
+ "-mavx512vl",
+ ],
+ },
+ },
+ header_libs: [
+ "fp16_headers",
+ ],
+ static_libs: [
+ "libpthreadpool",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_avx512skx_prod_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: { enabled: false, },
+ arm64: { enabled: false, },
+ x86: {
+ srcs: PROD_AVX512SKX_MICROKERNEL_SRCS,
+ cflags: [
+ "-mavx512f",
+ "-mavx512cd",
+ "-mavx512bw",
+ "-mavx512dq",
+ "-mavx512vl",
+ ],
+ },
+ x86_64: {
+ srcs: PROD_AVX512SKX_MICROKERNEL_SRCS,
+ cflags: [
+ "-mavx512f",
+ "-mavx512cd",
+ "-mavx512bw",
+ "-mavx512dq",
+ "-mavx512vl",
+ ],
+ },
+ },
+ header_libs: [
+ "fp16_headers",
+ ],
+ static_libs: [
+ "libpthreadpool",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_avx512f_amalgam_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: { enabled: false, },
+ arm64: { enabled: false, },
+ x86: {
+ srcs: [
+ "src/amalgam/avx512f.c",
+ ],
cflags: [
"-mavx512f",
],
},
x86_64: {
- srcs: AVX512F_UKERNELS,
+ srcs: [
+ "src/amalgam/avx512f.c",
+ ],
cflags: [
"-mavx512f",
],
@@ -3242,57 +8757,234 @@
}
cc_library_static {
- name: "xnnpack_ukernels",
+ name: "xnnpack_avx512f_bench_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: { enabled: false, },
+ arm64: { enabled: false, },
+ x86: {
+ srcs: ALL_AVX512F_MICROKERNEL_SRCS,
+ cflags: [
+ "-mavx512f",
+ ],
+ },
+ x86_64: {
+ srcs: ALL_AVX512F_MICROKERNEL_SRCS,
+ cflags: [
+ "-mavx512f",
+ ],
+ },
+ },
+ header_libs: [
+ "fp16_headers",
+ ],
+ static_libs: [
+ "libpthreadpool",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_avx512f_prod_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: { enabled: false, },
+ arm64: { enabled: false, },
+ x86: {
+ srcs: PROD_AVX512F_MICROKERNEL_SRCS,
+ cflags: [
+ "-mavx512f",
+ ],
+ },
+ x86_64: {
+ srcs: PROD_AVX512F_MICROKERNEL_SRCS,
+ cflags: [
+ "-mavx512f",
+ ],
+ },
+ },
+ header_libs: [
+ "fp16_headers",
+ ],
+ static_libs: [
+ "libpthreadpool",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_amalgam_microkernels",
defaults: ["xnnpack_internal_default"],
arch: {
arm: {
whole_static_libs: [
- "xnnpack_neon_ukernels",
- "xnnpack_neonfma_ukernels",
- "xnnpack_neonv8_ukernels",
- "xnnpack_neondot_ukernels",
- "xnnpack_asm_ukernels",
+ "xnnpack_neon_prod_microkernels",
+ "xnnpack_neonfp16_prod_microkernels",
+ "xnnpack_neonfma_prod_microkernels",
+ "xnnpack_neonv8_prod_microkernels",
+ "xnnpack_neondot_prod_microkernels",
+ "xnnpack_asm_microkernels",
],
},
arm64: {
whole_static_libs: [
- "xnnpack_neon_ukernels",
- "xnnpack_neonfma_ukernels",
- "xnnpack_neonv8_ukernels",
- "xnnpack_neonfp16arith_ukernels",
- "xnnpack_neondot_ukernels",
- "xnnpack_asm_ukernels",
+ "xnnpack_neon_prod_microkernels",
+ "xnnpack_neonfp16_prod_microkernels",
+ "xnnpack_neonfma_prod_microkernels",
+ "xnnpack_neonv8_prod_microkernels",
+ "xnnpack_neonfp16arith_prod_microkernels",
+ "xnnpack_neondot_prod_microkernels",
+ "xnnpack_asm_microkernels",
],
},
x86: {
whole_static_libs: [
- "xnnpack_sse2_ukernels",
- "xnnpack_ssse3_ukernels",
- "xnnpack_sse41_ukernels",
- "xnnpack_avx_ukernels",
- "xnnpack_xop_ukernels",
- "xnnpack_fma3_ukernels",
- "xnnpack_avx2_ukernels",
- "xnnpack_avx512f_ukernels",
- "xnnpack_avx512skx_ukernels",
+ "xnnpack_sse2_amalgam_microkernels",
+ "xnnpack_ssse3_amalgam_microkernels",
+ "xnnpack_sse41_amalgam_microkernels",
+ "xnnpack_avx_amalgam_microkernels",
+ "xnnpack_f16c_amalgam_microkernels",
+ "xnnpack_fma3_amalgam_microkernels",
+ "xnnpack_avx2_amalgam_microkernels",
+ "xnnpack_avx512f_amalgam_microkernels",
+ "xnnpack_avx512skx_amalgam_microkernels",
],
},
x86_64: {
whole_static_libs: [
- "xnnpack_sse2_ukernels",
- "xnnpack_ssse3_ukernels",
- "xnnpack_sse41_ukernels",
- "xnnpack_avx_ukernels",
- "xnnpack_xop_ukernels",
- "xnnpack_fma3_ukernels",
- "xnnpack_avx2_ukernels",
- "xnnpack_avx512f_ukernels",
- "xnnpack_avx512skx_ukernels",
+ "xnnpack_sse2_amalgam_microkernels",
+ "xnnpack_ssse3_amalgam_microkernels",
+ "xnnpack_sse41_amalgam_microkernels",
+ "xnnpack_avx_amalgam_microkernels",
+ "xnnpack_f16c_amalgam_microkernels",
+ "xnnpack_fma3_amalgam_microkernels",
+ "xnnpack_avx2_amalgam_microkernels",
+ "xnnpack_avx512f_amalgam_microkernels",
+ "xnnpack_avx512skx_amalgam_microkernels",
],
},
},
whole_static_libs: [
- "xnnpack_scalar_ukernels",
+ "xnnpack_scalar_prod_microkernels",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_bench_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: {
+ whole_static_libs: [
+ "xnnpack_neon_bench_microkernels",
+ "xnnpack_neonfp16_bench_microkernels",
+ "xnnpack_neonfma_bench_microkernels",
+ "xnnpack_neonv8_bench_microkernels",
+ "xnnpack_neondot_bench_microkernels",
+ "xnnpack_asm_microkernels",
+ ],
+ },
+ arm64: {
+ whole_static_libs: [
+ "xnnpack_neon_bench_microkernels",
+ "xnnpack_neonfp16_bench_microkernels",
+ "xnnpack_neonfma_bench_microkernels",
+ "xnnpack_neonv8_bench_microkernels",
+ "xnnpack_neondot_bench_microkernels",
+ "xnnpack_asm_microkernels",
+ ],
+ },
+ x86: {
+ whole_static_libs: [
+ "xnnpack_sse2_bench_microkernels",
+ "xnnpack_ssse3_bench_microkernels",
+ "xnnpack_sse41_bench_microkernels",
+ "xnnpack_avx_bench_microkernels",
+ "xnnpack_f16c_bench_microkernels",
+ "xnnpack_xop_bench_microkernels",
+ "xnnpack_fma3_bench_microkernels",
+ "xnnpack_avx2_bench_microkernels",
+ "xnnpack_avx512f_bench_microkernels",
+ "xnnpack_avx512skx_bench_microkernels",
+ ],
+ },
+ x86_64: {
+ whole_static_libs: [
+ "xnnpack_sse2_bench_microkernels",
+ "xnnpack_ssse3_bench_microkernels",
+ "xnnpack_sse41_bench_microkernels",
+ "xnnpack_avx_bench_microkernels",
+ "xnnpack_f16c_bench_microkernels",
+ "xnnpack_xop_bench_microkernels",
+ "xnnpack_fma3_bench_microkernels",
+ "xnnpack_avx2_bench_microkernels",
+ "xnnpack_avx512f_bench_microkernels",
+ "xnnpack_avx512skx_bench_microkernels",
+ ],
+ },
+ },
+ whole_static_libs: [
+ "xnnpack_scalar_bench_microkernels",
+ "xnnpack_tables",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_prod_microkernels",
+ defaults: ["xnnpack_internal_default"],
+ arch: {
+ arm: {
+ whole_static_libs: [
+ "xnnpack_neon_prod_microkernels",
+ "xnnpack_neonfp16_prod_microkernels",
+ "xnnpack_neonfma_prod_microkernels",
+ "xnnpack_neonv8_prod_microkernels",
+ "xnnpack_neondot_prod_microkernels",
+ "xnnpack_asm_microkernels",
+ ],
+ },
+ arm64: {
+ whole_static_libs: [
+ "xnnpack_neon_prod_microkernels",
+ "xnnpack_neonfp16_prod_microkernels",
+ "xnnpack_neonfma_prod_microkernels",
+ "xnnpack_neonv8_prod_microkernels",
+ "xnnpack_neonfp16arith_prod_microkernels",
+ "xnnpack_neondot_prod_microkernels",
+ "xnnpack_asm_microkernels",
+ ],
+ },
+ x86: {
+ whole_static_libs: [
+ "xnnpack_sse2_prod_microkernels",
+ "xnnpack_ssse3_prod_microkernels",
+ "xnnpack_sse41_prod_microkernels",
+ "xnnpack_avx_prod_microkernels",
+ "xnnpack_f16c_prod_microkernels",
+ "xnnpack_xop_prod_microkernels",
+ "xnnpack_fma3_prod_microkernels",
+ "xnnpack_avx2_prod_microkernels",
+ "xnnpack_avx512f_prod_microkernels",
+ "xnnpack_avx512skx_prod_microkernels",
+ ],
+ },
+ x86_64: {
+ whole_static_libs: [
+ "xnnpack_sse2_prod_microkernels",
+ "xnnpack_ssse3_prod_microkernels",
+ "xnnpack_sse41_prod_microkernels",
+ "xnnpack_avx_prod_microkernels",
+ "xnnpack_f16c_prod_microkernels",
+ "xnnpack_xop_prod_microkernels",
+ "xnnpack_fma3_prod_microkernels",
+ "xnnpack_avx2_prod_microkernels",
+ "xnnpack_avx512f_prod_microkernels",
+ "xnnpack_avx512skx_prod_microkernels",
+ ],
+ },
+ },
+ whole_static_libs: [
+ "xnnpack_scalar_prod_microkernels",
"xnnpack_tables",
],
}
@@ -3314,8 +9006,9 @@
"libclog",
"libcpuinfo",
"libpthreadpool",
- "xnnpack_ukernels",
- "xnnpack_operator_run",
+ "xnnpack_jit",
+ "xnnpack_jit_memory",
+ "xnnpack_prod_microkernels",
"xnnpack_operators",
"xnnpack_logging_utils",
"xnnpack_memory_planner",
@@ -3369,6 +9062,22 @@
}
cc_library_static {
+ name: "xnnpack_qc8_mobilenet_v1",
+ defaults: ["xnnpack_tests_default"],
+ srcs: [
+ "models/qc8-mobilenet-v1.cc",
+ ],
+}
+
+cc_library_static {
+ name: "xnnpack_qc8_mobilenet_v2",
+ defaults: ["xnnpack_tests_default"],
+ srcs: [
+ "models/qc8-mobilenet-v2.cc",
+ ],
+}
+
+cc_library_static {
name: "xnnpack_qs8_mobilenet_v1",
defaults: ["xnnpack_tests_default"],
srcs: [
@@ -3385,6 +9094,14 @@
}
cc_library_static {
+ name: "xnnpack_qu8_mobilenet_v2",
+ defaults: ["xnnpack_tests_default"],
+ srcs: [
+ "models/qu8-mobilenet-v2.cc",
+ ],
+}
+
+cc_library_static {
name: "xnnpack_mobilenet_v1_fp16",
defaults: ["xnnpack_tests_default"],
srcs: [
@@ -3486,6 +9203,8 @@
static_libs: [
"libcpuinfo",
"libgoogle-benchmark",
+ "xnnpack_qc8_mobilenet_v1",
+ "xnnpack_qc8_mobilenet_v2",
"xnnpack_qs8_mobilenet_v1",
"xnnpack_mobilenet_v1_fp32",
"xnnpack_mobilenet_v1_fp32_sparse",
@@ -3501,6 +9220,7 @@
"xnnpack_mobilenet_v3_small_fp32_sparse",
"xnnpack_mobilenet_v3_small_fp16",
"xnnpack_qu8_mobilenet_v1",
+ "xnnpack_qu8_mobilenet_v2",
],
}
