test/qu8-dwconv-minmax-fp32.yaml

# Copyright 2021 Google LLC
#
# This source code is licensed under the BSD-style license found in the
# LICENSE file in the root directory of this source tree.
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up8x9__sse2_mul16
  init: xnn_init_qu8_conv_minmax_fp32_sse2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up16x9__sse2_mul16
  init: xnn_init_qu8_conv_minmax_fp32_sse2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up8x9__sse41_mul16
  init: xnn_init_qu8_conv_minmax_fp32_sse2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up16x9__sse41_mul16
  init: xnn_init_qu8_conv_minmax_fp32_sse2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up8x9__avx_mul16
  init: xnn_init_qu8_conv_minmax_fp32_sse2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up16x9__avx_mul16
  init: xnn_init_qu8_conv_minmax_fp32_sse2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up8x9__sse41_mul32
  init: xnn_init_qu8_conv_minmax_fp32_sse2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up16x9__sse41_mul32
  init: xnn_init_qu8_conv_minmax_fp32_sse2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up8x9__avx_mul32
  init: xnn_init_qu8_conv_minmax_fp32_sse2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up16x9__avx_mul32
  init: xnn_init_qu8_conv_minmax_fp32_sse2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up8x9__xop_mul32
  init: xnn_init_qu8_conv_minmax_fp32_sse2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up16x9__xop_mul32
  init: xnn_init_qu8_conv_minmax_fp32_sse2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up8x9__avx2_mul32
  init: xnn_init_qu8_conv_minmax_fp32_avx2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up16x9__avx2_mul32
  init: xnn_init_qu8_conv_minmax_fp32_avx2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up32x9__avx2_mul32
  init: xnn_init_qu8_conv_minmax_fp32_avx2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up16x9__avx512skx_mul32
  init: xnn_init_qu8_conv_minmax_fp32_avx512_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up32x9__avx512skx_mul32
  init: xnn_init_qu8_conv_minmax_fp32_avx512_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up8x25__sse2_mul16
  init: xnn_init_qu8_conv_minmax_fp32_sse2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up16x25__sse2_mul16
  init: xnn_init_qu8_conv_minmax_fp32_sse2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up8x25__sse41_mul16
  init: xnn_init_qu8_conv_minmax_fp32_sse2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up16x25__sse41_mul16
  init: xnn_init_qu8_conv_minmax_fp32_sse2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up8x25__avx_mul16
  init: xnn_init_qu8_conv_minmax_fp32_sse2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up16x25__avx_mul16
  init: xnn_init_qu8_conv_minmax_fp32_sse2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up8x25__sse41_mul32
  init: xnn_init_qu8_conv_minmax_fp32_sse2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up16x25__sse41_mul32
  init: xnn_init_qu8_conv_minmax_fp32_sse2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up8x25__avx_mul32
  init: xnn_init_qu8_conv_minmax_fp32_sse2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up16x25__avx_mul32
  init: xnn_init_qu8_conv_minmax_fp32_sse2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up8x25__xop_mul32
  init: xnn_init_qu8_conv_minmax_fp32_sse2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up16x25__xop_mul32
  init: xnn_init_qu8_conv_minmax_fp32_sse2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up8x25__avx2_mul32
  init: xnn_init_qu8_conv_minmax_fp32_avx2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up16x25__avx2_mul32
  init: xnn_init_qu8_conv_minmax_fp32_avx2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up32x25__avx2_mul32
  init: xnn_init_qu8_conv_minmax_fp32_avx2_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up16x25__avx512skx_mul32
  init: xnn_init_qu8_conv_minmax_fp32_avx512_params
- name: xnn_qu8_dwconv_minmax_fp32_ukernel_up32x25__avx512skx_mul32
  init: xnn_init_qu8_conv_minmax_fp32_avx512_params