Rename some instruction/opcode types and utilities.
A lot of this is more about properties of opcodes as opposed to
inspecting instructions per se, and the new naming attempts to
make it clear what is being queried and what sort of data is being
returned.
Change-Id: Ice6f9f2ebf4f1cfa8c99597419aa13d1134a33b2
diff --git a/dexdump/DexDump.c b/dexdump/DexDump.c
index 257d63f..bc18213 100644
--- a/dexdump/DexDump.c
+++ b/dexdump/DexDump.c
@@ -708,7 +708,7 @@
u4 width;
/* TODO: Make the index *always* be in field B, to simplify this code. */
- switch (dexGetInstrFormat(pDecInsn->opcode)) {
+ switch (dexGetFormatFromOpcode(pDecInsn->opcode)) {
case kFmt20bc:
case kFmt21c:
case kFmt35c:
@@ -880,7 +880,7 @@
indexBufChars, sizeof(indexBufChars));
}
- switch (dexGetInstrFormat(pDecInsn->opcode)) {
+ switch (dexGetFormatFromOpcode(pDecInsn->opcode)) {
case kFmt10x: // op
break;
case kFmt12x: // op vA, vB
@@ -1075,11 +1075,11 @@
/*
* Note: This code parallels the function
- * dexGetInstrOrTableWidth() in InstrUtils.c, but this version
+ * dexGetWidthFromInstruction() in InstrUtils.c, but this version
* can deal with data in either endianness.
*
* TODO: Figure out if this really matters, and possibly change
- * this to just use dexGetInstrOrTableWidth().
+ * this to just use dexGetWidthFromInstruction().
*/
instr = get2LE((const u1*)insns);
if (instr == kPackedSwitchSignature) {
@@ -1094,7 +1094,7 @@
insnWidth = 4 + ((size * width) + 1) / 2;
} else {
Opcode opcode = dexOpcodeFromCodeUnit(instr);
- insnWidth = dexGetInstrWidth(opcode);
+ insnWidth = dexGetWidthFromOpcode(opcode);
if (insnWidth == 0) {
fprintf(stderr,
"GLITCH: zero-width instruction at idx=0x%04x\n", insnIdx);
diff --git a/libdex/InstrUtils.c b/libdex/InstrUtils.c
index 434c151..0550617 100644
--- a/libdex/InstrUtils.c
+++ b/libdex/InstrUtils.c
@@ -30,7 +30,7 @@
* use that opcode, in (16-bit) code units. Unimplemented opcodes as
* well as the "breakpoint" opcode have a width of zero.
*/
-static InstructionWidth gOpcodeWidthTable[kNumDalvikInstructions] = {
+static InstructionWidth gInstructionWidthTable[kNumDalvikInstructions] = {
// BEGIN(libdex-widths); GENERATED AUTOMATICALLY BY opcode-gen
1, 1, 2, 3, 1, 2, 3, 1, 2, 3, 1, 1, 1, 1, 1, 1,
1, 1, 1, 2, 3, 2, 2, 3, 5, 2, 2, 3, 2, 1, 1, 2,
@@ -320,7 +320,7 @@
* Table that maps each opcode to the instruction format associated
* that opcode.
*/
-static u1 gOpcodeFormatTable[kNumDalvikInstructions] = {
+static u1 gInstructionFormatTable[kNumDalvikInstructions] = {
// BEGIN(libdex-formats); GENERATED AUTOMATICALLY BY opcode-gen
kFmt10x, kFmt12x, kFmt22x, kFmt32x, kFmt12x, kFmt22x, kFmt32x,
kFmt12x, kFmt22x, kFmt32x, kFmt11x, kFmt11x, kFmt11x, kFmt11x,
@@ -366,7 +366,7 @@
* Table that maps each opcode to the index type implied by that
* opcode.
*/
-static u1 gOpcodeIndexTypeTable[kNumDalvikInstructions] = {
+static u1 gInstructionIndexTypeTable[kNumDalvikInstructions] = {
// BEGIN(libdex-index-types); GENERATED AUTOMATICALLY BY opcode-gen
kIndexNone, kIndexNone, kIndexNone,
kIndexNone, kIndexNone, kIndexNone,
@@ -461,10 +461,10 @@
* Global InstructionInfoTables struct.
*/
InstructionInfoTables gDexOpcodeInfo = {
- gOpcodeFormatTable,
- gOpcodeIndexTypeTable,
+ gInstructionFormatTable,
+ gInstructionIndexTypeTable,
gOpcodeFlagsTable,
- gOpcodeWidthTable
+ gInstructionWidthTable
};
/*
@@ -491,10 +491,10 @@
{
u2 inst = *insns;
Opcode opcode = dexOpcodeFromCodeUnit(inst);
- InstructionFormat format = dexGetInstrFormat(opcode);
+ InstructionFormat format = dexGetFormatFromOpcode(opcode);
pDec->opcode = opcode;
- pDec->indexType = dexGetInstrIndexType(opcode);
+ pDec->indexType = dexGetIndexTypeFromOpcode(opcode);
switch (format) {
case kFmt10x: // op
@@ -693,7 +693,7 @@
* works for special OP_NOP entries, including switch statement data tables
* and array data.
*/
-size_t dexGetInstrOrTableWidth(const u2* insns)
+size_t dexGetWidthFromInstruction(const u2* insns)
{
size_t width;
@@ -707,7 +707,7 @@
// The plus 1 is to round up for odd size and width.
width = 4 + (elemWidth * len + 1) / 2;
} else {
- width = dexGetInstrWidth(dexOpcodeFromCodeUnit(insns[0]));
+ width = dexGetWidthFromOpcode(dexOpcodeFromCodeUnit(insns[0]));
}
return width;
diff --git a/libdex/InstrUtils.h b/libdex/InstrUtils.h
index c6d81ab..3cbc146 100644
--- a/libdex/InstrUtils.h
+++ b/libdex/InstrUtils.h
@@ -72,7 +72,7 @@
* Types of indexed reference that are associated with opcodes whose
* formats include such an indexed reference (e.g., 21c and 35c).
*/
-typedef enum InstructionIndexType {
+typedef enum {
kIndexUnknown = 0,
kIndexNone, // has no index
kIndexVaries, // "It depends." Used for throw-verification-error
@@ -86,18 +86,18 @@
} InstructionIndexType;
/*
- * Instruction width implied by an opcode; a value in the range 0 to
- * 5. Note that there are special "pseudo-instructions" which are used
- * to encode switch and data tables, and these don't have a fixed width.
- * See dexGetInstrOrTableWidth(), below.
+ * Instruction width implied by an opcode's format; a value in the
+ * range 0 to 5. Note that there are special "pseudo-instructions"
+ * which are used to encode switch and data tables, and these don't
+ * have a fixed width. See dexGetWidthFromInstruction(), below.
*/
typedef u1 InstructionWidth;
/*
* Opcode control flow flags, used by the verifier and JIT.
*/
-typedef u1 InstructionFlags;
-enum InstructionFlagsBits {
+typedef u1 OpcodeFlags;
+enum OpcodeFlagsBits {
kInstrCanBranch = 1, // conditional or unconditional branch
kInstrCanContinue = 1 << 1, // flow can continue to next statement
kInstrCanSwitch = 1 << 2, // switch statement
@@ -117,9 +117,9 @@
* suffice.
*/
typedef struct InstructionInfoTables {
- u1* formats; /* InstructionFormat elements */
- u1* indexTypes; /* InstructionIndexType elements */
- InstructionFlags* flags;
+ u1* formats; /* InstructionFormat elements */
+ u1* indexTypes; /* InstructionIndexType elements */
+ OpcodeFlags* flags;
InstructionWidth* widths;
} InstructionInfoTables;
@@ -142,9 +142,9 @@
} DecodedInstruction;
/*
- * Return the width of the specified instruction, or 0 if not defined.
+ * Return the instruction width of the specified opcode, or 0 if not defined.
*/
-DEX_INLINE size_t dexGetInstrWidth(Opcode opcode)
+DEX_INLINE size_t dexGetWidthFromOpcode(Opcode opcode)
{
//assert(/*opcode >= 0 &&*/ opcode < kNumDalvikInstructions);
return gDexOpcodeInfo.widths[opcode];
@@ -155,12 +155,12 @@
* works for special OP_NOP entries, including switch statement data tables
* and array data.
*/
-size_t dexGetInstrOrTableWidth(const u2* insns);
+size_t dexGetWidthFromInstruction(const u2* insns);
/*
* Returns the flags for the specified opcode.
*/
-DEX_INLINE InstructionFlags dexGetInstrFlags(Opcode opcode)
+DEX_INLINE OpcodeFlags dexGetFlagsFromOpcode(Opcode opcode)
{
//assert(/*opcode >= 0 &&*/ opcode < kNumDalvikInstructions);
return gDexOpcodeInfo.flags[opcode];
@@ -169,7 +169,7 @@
/*
* Returns true if the given flags represent a goto (unconditional branch).
*/
-DEX_INLINE bool dexIsGoto(InstructionFlags flags)
+DEX_INLINE bool dexIsGoto(OpcodeFlags flags)
{
return (flags & (kInstrCanBranch | kInstrCanContinue)) == kInstrCanBranch;
}
@@ -177,7 +177,7 @@
/*
* Return the instruction format for the specified opcode.
*/
-DEX_INLINE InstructionFormat dexGetInstrFormat(Opcode opcode)
+DEX_INLINE InstructionFormat dexGetFormatFromOpcode(Opcode opcode)
{
//assert(/*opcode >= 0 &&*/ opcode < kNumDalvikInstructions);
return (InstructionFormat) gDexOpcodeInfo.formats[opcode];
@@ -186,7 +186,7 @@
/*
* Return the instruction index type for the specified opcode.
*/
-DEX_INLINE InstructionIndexType dexGetInstrIndexType(Opcode opcode)
+DEX_INLINE InstructionIndexType dexGetIndexTypeFromOpcode(Opcode opcode)
{
//assert(/*opcode >= 0 &&*/ opcode < kNumDalvikInstructions);
return (InstructionIndexType) gDexOpcodeInfo.indexTypes[opcode];
diff --git a/vm/analysis/CodeVerify.c b/vm/analysis/CodeVerify.c
index 0ed9c40..f53956e 100644
--- a/vm/analysis/CodeVerify.c
+++ b/vm/analysis/CodeVerify.c
@@ -3757,7 +3757,7 @@
* We can also return, in which case there is no successor instruction
* from this point.
*
- * The behavior can be determined from the InstructionFlags.
+ * The behavior can be determined from the OpcodeFlags.
*/
RegisterLine* workLine = ®Table->workLine;
@@ -3775,7 +3775,7 @@
#endif
dexDecodeInstruction(insns, &decInsn);
- int nextFlags = dexGetInstrFlags(decInsn.opcode);
+ int nextFlags = dexGetFlagsFromOpcode(decInsn.opcode);
/*
* Make a copy of the previous register state. If the instruction
diff --git a/vm/analysis/DexVerify.c b/vm/analysis/DexVerify.c
index 54a4e6b..a1f2db3 100644
--- a/vm/analysis/DexVerify.c
+++ b/vm/analysis/DexVerify.c
@@ -92,7 +92,7 @@
int i;
for (i = 0; i < (int) insnCount; /**/) {
- size_t width = dexGetInstrOrTableWidth(insns);
+ size_t width = dexGetWidthFromInstruction(insns);
if (width == 0) {
LOG_VFY_METH(meth, "VFY: invalid instruction (0x%04x)\n", *insns);
goto bail;
@@ -1202,7 +1202,7 @@
const int kGcMask = kInstrCanBranch | kInstrCanSwitch |
kInstrCanThrow | kInstrCanReturn;
- InstructionFlags opFlags = dexGetInstrFlags(decInsn.opcode);
+ OpcodeFlags opFlags = dexGetFlagsFromOpcode(decInsn.opcode);
if ((opFlags & kGcMask) != 0) {
/*
* This instruction is probably a GC point. Branch instructions
diff --git a/vm/analysis/Optimize.c b/vm/analysis/Optimize.c
index 1f99943..1ed47af 100644
--- a/vm/analysis/Optimize.c
+++ b/vm/analysis/Optimize.c
@@ -299,7 +299,7 @@
}
}
- width = dexGetInstrOrTableWidth(insns);
+ width = dexGetWidthFromInstruction(insns);
assert(width > 0);
insns += width;
diff --git a/vm/compiler/Frontend.c b/vm/compiler/Frontend.c
index 9015719..a44c489 100644
--- a/vm/compiler/Frontend.c
+++ b/vm/compiler/Frontend.c
@@ -34,7 +34,7 @@
if (opcode == OP_NOP && instr != 0) {
return 0;
} else {
- insnWidth = dexGetInstrWidth(opcode);
+ insnWidth = dexGetWidthFromOpcode(opcode);
if (insnWidth < 0) {
insnWidth = -insnWidth;
}
@@ -205,7 +205,7 @@
static int analyzeInlineTarget(DecodedInstruction *dalvikInsn, int attributes,
int offset)
{
- int flags = dexGetInstrFlags(dalvikInsn->opcode);
+ int flags = dexGetFlagsFromOpcode(dalvikInsn->opcode);
int dalvikOpcode = dalvikInsn->opcode;
if (flags & kInstrInvoke) {
@@ -569,7 +569,7 @@
dvmCompilerAppendMIR(curBB, insn);
cUnit.numInsts++;
- int flags = dexGetInstrFlags(insn->dalvikInsn.opcode);
+ int flags = dexGetFlagsFromOpcode(insn->dalvikInsn.opcode);
if (flags & kInstrInvoke) {
assert(numInsts == 1);
@@ -641,7 +641,7 @@
/* Link the taken and fallthrough blocks */
BasicBlock *searchBB;
- int flags = dexGetInstrFlags(lastInsn->dalvikInsn.opcode);
+ int flags = dexGetFlagsFromOpcode(lastInsn->dalvikInsn.opcode);
if (flags & kInstrInvoke) {
cUnit.hasInvoke = true;
@@ -1201,7 +1201,7 @@
* aligned to 4-byte boundary (alignment instruction to be
* inserted later.
*/
- if (dexGetInstrFlags(curBB->lastMIRInsn->dalvikInsn.opcode)
+ if (dexGetFlagsFromOpcode(curBB->lastMIRInsn->dalvikInsn.opcode)
& kInstrInvoke) {
newBB->isFallThroughFromInvoke = true;
}
diff --git a/vm/compiler/InlineTransformation.c b/vm/compiler/InlineTransformation.c
index a632d6c..0b1330f 100644
--- a/vm/compiler/InlineTransformation.c
+++ b/vm/compiler/InlineTransformation.c
@@ -85,7 +85,7 @@
/* Now setup the Dalvik instruction with converted src/dst registers */
newGetterMIR->dalvikInsn = getterInsn;
- newGetterMIR->width = dexGetInstrWidth(getterInsn.opcode);
+ newGetterMIR->width = dexGetWidthFromOpcode(getterInsn.opcode);
newGetterMIR->OptimizationFlags |= MIR_CALLEE;
@@ -164,7 +164,7 @@
/* Now setup the Dalvik instruction with converted src/dst registers */
newSetterMIR->dalvikInsn = setterInsn;
- newSetterMIR->width = dexGetInstrWidth(setterInsn.opcode);
+ newSetterMIR->width = dexGetWidthFromOpcode(setterInsn.opcode);
newSetterMIR->OptimizationFlags |= MIR_CALLEE;
@@ -296,7 +296,7 @@
continue;
MIR *lastMIRInsn = bb->lastMIRInsn;
int opcode = lastMIRInsn->dalvikInsn.opcode;
- int flags = dexGetInstrFlags(opcode);
+ int flags = dexGetFlagsFromOpcode(opcode);
/* No invoke - continue */
if ((flags & kInstrInvoke) == 0)
diff --git a/vm/compiler/Loop.c b/vm/compiler/Loop.c
index 13e133c..c03d6f5 100644
--- a/vm/compiler/Loop.c
+++ b/vm/compiler/Loop.c
@@ -311,7 +311,7 @@
/* Skip extended MIR instructions */
if (dInsn->opcode >= kNumDalvikInstructions) continue;
- int instrFlags = dexGetInstrFlags(dInsn->opcode);
+ int instrFlags = dexGetFlagsFromOpcode(dInsn->opcode);
/* Instruction is clean */
if ((instrFlags & kInstrCanThrow) == 0) continue;
diff --git a/vm/compiler/codegen/arm/CodegenDriver.c b/vm/compiler/codegen/arm/CodegenDriver.c
index 9892f56..55fee0e 100644
--- a/vm/compiler/codegen/arm/CodegenDriver.c
+++ b/vm/compiler/codegen/arm/CodegenDriver.c
@@ -1233,7 +1233,7 @@
*/
static void genInterpSingleStep(CompilationUnit *cUnit, MIR *mir)
{
- int flags = dexGetInstrFlags(mir->dalvikInsn.opcode);
+ int flags = dexGetFlagsFromOpcode(mir->dalvikInsn.opcode);
int flagsToCheck = kInstrCanBranch | kInstrCanSwitch | kInstrCanReturn |
kInstrCanThrow;
@@ -1283,7 +1283,7 @@
if (isEnter) {
/* Get dPC of next insn */
loadConstant(cUnit, r4PC, (int)(cUnit->method->insns + mir->offset +
- dexGetInstrWidth(OP_MONITOR_ENTER)));
+ dexGetWidthFromOpcode(OP_MONITOR_ENTER)));
#if defined(WITH_DEADLOCK_PREDICTION)
genDispatchToHandler(cUnit, TEMPLATE_MONITOR_ENTER_DEBUG);
#else
@@ -1297,7 +1297,7 @@
ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0);
loadConstant(cUnit, r0,
(int) (cUnit->method->insns + mir->offset +
- dexGetInstrWidth(OP_MONITOR_EXIT)));
+ dexGetWidthFromOpcode(OP_MONITOR_EXIT)));
genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON);
ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
target->defMask = ENCODE_ALL;
@@ -4097,7 +4097,7 @@
Opcode dalvikOpcode = mir->dalvikInsn.opcode;
- InstructionFormat dalvikFormat = dexGetInstrFormat(dalvikOpcode);
+ InstructionFormat dalvikFormat = dexGetFormatFromOpcode(dalvikOpcode);
char *note;
if (mir->OptimizationFlags & MIR_INLINED) {
note = " (I)";
diff --git a/vm/compiler/codegen/arm/Thumb2/Gen.c b/vm/compiler/codegen/arm/Thumb2/Gen.c
index f1f6df3..825b271 100644
--- a/vm/compiler/codegen/arm/Thumb2/Gen.c
+++ b/vm/compiler/codegen/arm/Thumb2/Gen.c
@@ -225,7 +225,7 @@
/* Get dPC of next insn */
loadConstant(cUnit, r4PC, (int)(cUnit->method->insns + mir->offset +
- dexGetInstrWidth(OP_MONITOR_ENTER)));
+ dexGetWidthFromOpcode(OP_MONITOR_ENTER)));
// Export PC (part 2)
newLIR3(cUnit, kThumb2StrRRI8Predec, r3, rFP,
sizeof(StackSaveArea) -
@@ -289,7 +289,7 @@
ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0);
loadConstant(cUnit, r0,
(int) (cUnit->method->insns + mir->offset +
- dexGetInstrWidth(OP_MONITOR_EXIT)));
+ dexGetWidthFromOpcode(OP_MONITOR_EXIT)));
genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON);
// Resume here
diff --git a/vm/interp/Jit.c b/vm/interp/Jit.c
index b266b24..3fafe6d 100644
--- a/vm/interp/Jit.c
+++ b/vm/interp/Jit.c
@@ -685,7 +685,7 @@
interpState->trace[currTraceRun].frag.isCode = true;
interpState->totalTraceLen++;
- interpState->currRunLen = dexGetInstrOrTableWidth(moveResultPC);
+ interpState->currRunLen = dexGetWidthFromInstruction(moveResultPC);
}
/*
@@ -750,8 +750,8 @@
#if defined(SHOW_TRACE)
LOGD("TraceGen: adding %s", dexGetOpcodeName(decInsn.opcode));
#endif
- flags = dexGetInstrFlags(decInsn.opcode);
- len = dexGetInstrOrTableWidth(lastPC);
+ flags = dexGetFlagsFromOpcode(decInsn.opcode);
+ len = dexGetWidthFromInstruction(lastPC);
offset = lastPC - interpState->method->insns;
assert((unsigned) offset <
dvmGetMethodInsnsSize(interpState->method));
diff --git a/vm/mterp/x86-atom/header.S b/vm/mterp/x86-atom/header.S
index 4c7c048..5b8303a 100644
--- a/vm/mterp/x86-atom/header.S
+++ b/vm/mterp/x86-atom/header.S
@@ -468,4 +468,4 @@
.long 0x80000000
.LintMax:
-.long 0x7FFFFFFF
\ No newline at end of file
+.long 0x7FFFFFFF
diff --git a/vm/native/dalvik_bytecode_OpcodeInfo.c b/vm/native/dalvik_bytecode_OpcodeInfo.c
index d5f22ca..cabd7b1 100644
--- a/vm/native/dalvik_bytecode_OpcodeInfo.c
+++ b/vm/native/dalvik_bytecode_OpcodeInfo.c
@@ -32,7 +32,7 @@
JValue* pResult)
{
jint opcode = (jint) args[0];
- int flags = dexGetInstrFlags(opcode);
+ int flags = dexGetFlagsFromOpcode(opcode);
bool result = (flags & kInstrInvoke) != 0;
RETURN_BOOLEAN(result);
}
