Update to allow x86-atom build for FI on Gingerbread
Also handles most TODO.txt items and contains some rewriting of the dispatch code.
Also adds a newline to the end of files that did not previously end with a newline.
Change-Id: Ifa627ac3d493447013524eb0be178b5b6d952612
diff --git a/vm/mterp/config-x86-atom b/vm/mterp/config-x86-atom
index ca880fd..e1c3f07 100644
--- a/vm/mterp/config-x86-atom
+++ b/vm/mterp/config-x86-atom
@@ -60,7 +60,6 @@
#op OP_APUT_SHORT c
#op OP_APUT_WIDE c
#op OP_ARRAY_LENGTH c
-#op OP_BREAKPOINT c
#op OP_CHECK_CAST c
#op OP_CMPG_DOUBLE c
#op OP_CMPG_FLOAT c
@@ -91,7 +90,6 @@
#op OP_DOUBLE_TO_FLOAT c
#op OP_DOUBLE_TO_INT c
#op OP_DOUBLE_TO_LONG c
-#op OP_EXECUTE_INLINE_RANGE c
#op OP_EXECUTE_INLINE c
#op OP_FILL_ARRAY_DATA c
#op OP_FILLED_NEW_ARRAY_RANGE c
@@ -259,19 +257,7 @@
#op OP_UNUSED_73 c
#op OP_UNUSED_79 c
#op OP_UNUSED_7A c
-#op OP_UNUSED_E3 c
-#op OP_UNUSED_E4 c
-#op OP_UNUSED_E5 c
-#op OP_UNUSED_E6 c
-#op OP_UNUSED_E7 c
-#op OP_UNUSED_E8 c
-#op OP_UNUSED_E9 c
-#op OP_UNUSED_EA c
-#op OP_UNUSED_EB c
#op OP_UNUSED_F1 c
-#op OP_UNUSED_FC c
-#op OP_UNUSED_FD c
-#op OP_UNUSED_FE c
#op OP_UNUSED_FF c
#op OP_USHR_INT_2ADDR c
#op OP_USHR_INT_LIT8 c
@@ -284,7 +270,10 @@
#op OP_XOR_INT c
#op OP_XOR_LONG_2ADDR c
#op OP_XOR_LONG c
+
# TODO: provide native implementations
+op OP_BREAKPOINT c
+op OP_EXECUTE_INLINE_RANGE c
op OP_IGET_VOLATILE c
op OP_IPUT_VOLATILE c
op OP_SGET_VOLATILE c
@@ -297,6 +286,7 @@
op OP_IPUT_WIDE_VOLATILE c
op OP_SGET_WIDE_VOLATILE c
op OP_SPUT_WIDE_VOLATILE c
+
op-end
# arch-specific entry point to interpreter
diff --git a/vm/mterp/out/InterpAsm-x86-atom.S b/vm/mterp/out/InterpAsm-x86-atom.S
index 4d9942d..9d384dd 100644
--- a/vm/mterp/out/InterpAsm-x86-atom.S
+++ b/vm/mterp/out/InterpAsm-x86-atom.S
@@ -295,44 +295,6 @@
jmp *dvmAsmInstructionJmpTable(,\_rFinish, 4)
.endm
- .macro FGETOP_JMP2 _rFinish
- movzbl 1(rPC), rINST
- jmp *dvmAsmInstructionJmpTable(,\_rFinish, 4)
- .endm
-
- .macro OLD_JMP_1 _count _rFinish
- movzbl (\_count*2)(rPC), \_rFinish
- shl $6, \_rFinish
- .endm
-
- .macro OLD_JMP_2 _rFinish
- addl $dvmAsmInstructionStart,\_rFinish
- .endm
-
- .macro OLD_JMP_3 _count
- addl $(\_count*2), rPC
- .endm
-
- .macro OLD_JMP_4 _rFinish
- movzbl 1(rPC), rINST
- jmp *\_rFinish
- .endm
-
- .macro OLD_JMP_A_1 _reg _rFinish
- movzbl (rPC, \_reg), \_rFinish
- shl $6, \_rFinish
- .endm
-
- .macro OLD_JMP_A_2 _rFinish
- addl $dvmAsmInstructionStart,\_rFinish
- .endm
-
- .macro OLD_JMP_A_3 _reg _rFinish
- addl \_reg, rPC
- movzbl 1(rPC, \_reg), rINST
- jmp *\_rFinish
- .endm
-
/*
* Macro pair attempts to speed up FETCH_INST, GET_INST_OPCODE and GOTO_OPCODE
* by using a jump table. _rFinish and _reg should must be the same register for
@@ -477,6 +439,7 @@
.LintMax:
.long 0x7FFFFFFF
+
.global dvmAsmInstructionStart
.type dvmAsmInstructionStart, %function
dvmAsmInstructionStart = .L_OP_NOP
@@ -570,6 +533,7 @@
GET_VREG rINST # rINST<- vB
SET_VREG rINST, %ecx # vA<- vB; %edx
FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_MOVE_FROM16: /* 0x02 */
@@ -692,6 +656,7 @@
movq (rFP, %edx, 4), %xmm0 # %xmm0<- vB
movq %xmm0, (rFP, rINST, 4) # vA<- vB
FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_MOVE_WIDE_FROM16: /* 0x05 */
@@ -835,6 +800,7 @@
SET_VREG rINST, %ecx # vA<- vB; %edx
FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_MOVE_OBJECT_FROM16: /* 0x08 */
@@ -1361,7 +1327,7 @@
*
* For: const/4
*
- * Description: Move the given literal value (right-sign-extended to 32
+ * Description: Move the given literal value (right-zero-extended to 32
* bits) into the specified register.
*
* Format: B|A|op (11n)
@@ -1371,12 +1337,12 @@
movl rINST, %edx # %edx<- BA
andl $15, rINST # rINST<- A
- FFETCH_ADV 1, %eax # %eax<- next i nstruction hi; fetch, advance
shl $24, %edx # %edx<- B000
- addl $2, rPC # update PC
sar $28, %edx # %edx<- right-zero-extended B
+ FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
SET_VREG %edx, rINST # vA<- %edx; literal
- FGETOP_JMP2 %eax # jump to next instruction; getop, jmp
+ FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_CONST_16: /* 0x13 */
@@ -1415,6 +1381,7 @@
FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
SET_VREG %edx rINST # vAA<- BBBB; literal
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_CONST: /* 0x14 */
@@ -1455,6 +1422,7 @@
FFETCH_ADV 3, %eax # %eax<- next instruction hi; fetch, advance
SET_VREG %ecx, rINST # vAA<- %ecx; literal
FGETOP_JMP 3, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_CONST_HIGH16: /* 0x15 */
@@ -1536,6 +1504,7 @@
movl %edx, (rFP, rINST, 4) # vAA<- ssssBBBB
movl %ecx, 4(rFP, rINST, 4) # vAA+1<- ssssssss
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_CONST_WIDE_32: /* 0x17 */
@@ -1579,6 +1548,7 @@
movl %edx, (rFP, rINST, 4) # vAA<- BBBBBBBB
movl %ecx, 4(rFP, rINST, 4) # vAA+1<- ssssssss
FGETOP_JMP 3, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_CONST_WIDE: /* 0x18 */
@@ -2046,10 +2016,10 @@
movl rINST, %eax # %eax<- BA
shr $4, %eax # %eax<- B
andl $15, rINST # rINST<- A
- FFETCH_ADV 1, %edx # %edx<- next instruction hi; fetch, advance
GET_VREG %eax # %eax<- vB
- testl %eax, %eax # check for null array object
+ cmp $0, %eax # check for null array object
je common_errNullObject # handle null array object
+ FFETCH_ADV 1, %edx # %edx<- next instruction hi; fetch, advance
movl offArrayObject_length(%eax), %eax # %eax<- array length
movl %eax, (rFP, rINST, 4) # vA<- %eax; array length
FGETOP_JMP 1, %edx # jump to next instruction; getop, jmp
@@ -2403,6 +2373,7 @@
*/
movl rGLUE, %eax # %eax<- pMterpGlue
+ EXPORT_PC # export the pc
GET_VREG rINST # rINST<- vAA
cmp $0, rINST # check for null
movl offGlue_self(%eax), %ecx # %ecx<- glue->self
@@ -2448,7 +2419,7 @@
movsbl rINSTbl, %edx # %edx<- +AA
shl $1, %edx # %edx is shifted for byte offset
- js common_periodicChecks2 # do check on backwards branch
+ js common_periodicChecks_backwardBranch # do check on backwards branch
FINISH_RB %edx, %ecx # jump to next instruction
/* ------------------------------ */
@@ -2487,7 +2458,7 @@
FETCHs 1, %edx # %edx<- ssssAAAA (sign-extended)
shl $1, %edx # %edx is doubled to get the byte offset
- js common_periodicChecks2 # do check on backwards branch
+ js common_periodicChecks_backwardBranch # do check on backwards branch
FINISH_RB %edx, %ecx # jump to next instruction
/* ------------------------------ */
@@ -2529,7 +2500,7 @@
shl $16, %ecx # prepare to create +AAAAAAAA
or %ecx, %edx # %edx<- +AAAAAAAA
shl $1, %edx # %edx is doubled to get the byte offset
- jc common_periodicChecks2 # do check on backwards branch
+ jle common_periodicChecks_backwardBranch # do check on backwards branch
FINISH_RB %edx, %ecx # jump to next instruction
/* ------------------------------ */
@@ -2582,7 +2553,7 @@
shl $1, %eax # shift for byte offset
movl %eax, %edx # %edx<- offset
lea 8(%esp), %esp
- jle common_periodicChecks2 # do backward branch
+ jle common_periodicChecks_backwardBranch # do backward branch
jmp .LOP_PACKED_SWITCH_finish
/* ------------------------------ */
@@ -2655,7 +2626,7 @@
shl $1, %eax # shift for byte offset
movl %eax, %edx # %edx<- offset
lea 8(%esp), %esp
- jle common_periodicChecks2 # do backward branch
+ jle common_periodicChecks_backwardBranch # do backward branch
jmp .LOP_SPARSE_SWITCH_finish
@@ -2702,15 +2673,9 @@
FETCH_BB 1, %ecx # %ecx<- BB
FETCH_CC 1, %edx # %edx<- CC
-
- flds (rFP, %edx, 4)
- flds (rFP, %ecx, 4)
-
- fucompp
- fnstsw %ax
- sahf
-
FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
+ movss (rFP, %ecx, 4), %xmm0 # %xmm0<- vBB
+ comiss (rFP, %edx, 4), %xmm0 # do comparison
ja .LOP_CMPL_FLOAT_greater
jp .LOP_CMPL_FLOAT_finalNan
jz .LOP_CMPL_FLOAT_final
@@ -2783,15 +2748,9 @@
FETCH_BB 1, %ecx # %ecx<- BB
FETCH_CC 1, %edx # %edx<- CC
-
- flds (rFP, %edx, 4)
- flds (rFP, %ecx, 4)
-
- fucompp
- fnstsw %ax
- sahf
-
FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
+ movss (rFP, %ecx, 4), %xmm0 # %xmm0<- vBB
+ comiss (rFP, %edx, 4), %xmm0 # do comparison
ja .LOP_CMPG_FLOAT_greater
jp .LOP_CMPG_FLOAT_finalNan
jz .LOP_CMPG_FLOAT_final
@@ -2865,15 +2824,9 @@
FETCH_BB 1, %ecx # %ecx<- BB
FETCH_CC 1, %edx # %edx<- CC
-
- fldl (rFP, %edx, 4)
- fldl (rFP, %ecx, 4)
-
- fucompp
- fnstsw %ax
- sahf
-
FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
+ movsd (rFP, %ecx, 4), %xmm0 # %xmm0<- vBB
+ comisd (rFP, %edx, 4), %xmm0 # do comparison
ja .LOP_CMPL_DOUBLE_greater
jp .LOP_CMPL_DOUBLE_finalNan
jz .LOP_CMPL_DOUBLE_final
@@ -2947,15 +2900,9 @@
FETCH_BB 1, %ecx # %ecx<- BB
FETCH_CC 1, %edx # %edx<- CC
-
- fldl (rFP, %edx, 4)
- fldl (rFP, %ecx, 4)
-
- fucompp
- fnstsw %ax
- sahf
-
FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
+ movsd (rFP, %ecx, 4), %xmm0 # %xmm0<- vBB
+ comisd (rFP, %edx, 4), %xmm0 # do comparison
ja .LOP_CMPG_DOUBLE_greater
jp .LOP_CMPG_DOUBLE_finalNan
jz .LOP_CMPG_DOUBLE_final
@@ -3078,7 +3025,7 @@
# comparison is true
FETCHs 1, %edx # %edx<- +CCCC, Branch offset
sal $1, %edx
- js common_periodicChecks2
+ js common_periodicChecks_backwardBranch
1:
FINISH_RB %edx, %ecx # jump to next instruction
@@ -3148,7 +3095,7 @@
# comparison is true
FETCHs 1, %edx # %edx<- +CCCC, Branch offset
sal $1, %edx
- js common_periodicChecks2
+ js common_periodicChecks_backwardBranch
1:
FINISH_RB %edx, %ecx # jump to next instruction
@@ -3218,7 +3165,7 @@
# comparison is true
FETCHs 1, %edx # %edx<- +CCCC, Branch offset
sal $1, %edx
- js common_periodicChecks2
+ js common_periodicChecks_backwardBranch
1:
FINISH_RB %edx, %ecx # jump to next instruction
@@ -3288,7 +3235,7 @@
# comparison is true
FETCHs 1, %edx # %edx<- +CCCC, Branch offset
sal $1, %edx
- js common_periodicChecks2
+ js common_periodicChecks_backwardBranch
1:
FINISH_RB %edx, %ecx # jump to next instruction
@@ -3358,7 +3305,7 @@
# comparison is true
FETCHs 1, %edx # %edx<- +CCCC, Branch offset
sal $1, %edx
- js common_periodicChecks2
+ js common_periodicChecks_backwardBranch
1:
FINISH_RB %edx, %ecx # jump to next instruction
@@ -3428,7 +3375,7 @@
# comparison is true
FETCHs 1, %edx # %edx<- +CCCC, Branch offset
sal $1, %edx
- js common_periodicChecks2
+ js common_periodicChecks_backwardBranch
1:
FINISH_RB %edx, %ecx # jump to next instruction
@@ -3497,7 +3444,7 @@
* Inline common_backwardBranch
*/
- js common_periodicChecks2 # jump on backwards branch
+ js common_periodicChecks_backwardBranch # jump on backwards branch
1:
FINISH_RB %edx, %ecx # jump to next instruction
@@ -3576,7 +3523,7 @@
* Inline common_backwardBranch
*/
- js common_periodicChecks2 # jump on backwards branch
+ js common_periodicChecks_backwardBranch # jump on backwards branch
1:
FINISH_RB %edx, %ecx # jump to next instruction
@@ -3655,7 +3602,7 @@
* Inline common_backwardBranch
*/
- js common_periodicChecks2 # jump on backwards branch
+ js common_periodicChecks_backwardBranch # jump on backwards branch
1:
FINISH_RB %edx, %ecx # jump to next instruction
@@ -3734,7 +3681,7 @@
* Inline common_backwardBranch
*/
- js common_periodicChecks2 # jump on backwards branch
+ js common_periodicChecks_backwardBranch # jump on backwards branch
1:
FINISH_RB %edx, %ecx # jump to next instruction
@@ -3813,7 +3760,7 @@
* Inline common_backwardBranch
*/
- js common_periodicChecks2 # jump on backwards branch
+ js common_periodicChecks_backwardBranch # jump on backwards branch
1:
FINISH_RB %edx, %ecx # jump to next instruction
@@ -3892,7 +3839,7 @@
* Inline common_backwardBranch
*/
- js common_periodicChecks2 # jump on backwards branch
+ js common_periodicChecks_backwardBranch # jump on backwards branch
1:
FINISH_RB %edx, %ecx # jump to next instruction
@@ -4299,6 +4246,7 @@
# with one instr was not faster
SET_VREG %edx rINST # vAA<- %edx; value
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_AGET_WIDE: /* 0x45 */
@@ -4346,6 +4294,7 @@
movq offArrayObject_contents(%ecx, %edx, 8), %xmm0 # %xmm0<- vBB[vCC]
movq %xmm0, (rFP, rINST, 4) # vAA<- %xmm0; value
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_AGET_OBJECT: /* 0x46 */
@@ -4423,6 +4372,7 @@
SET_VREG %edx rINST # vAA<- %edx; value
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_AGET_BOOLEAN: /* 0x47 */
@@ -4500,6 +4450,7 @@
SET_VREG %edx rINST # vAA<- %edx; value
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_AGET_BYTE: /* 0x48 */
@@ -4577,6 +4528,7 @@
SET_VREG %edx rINST # vAA<- %edx; value
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_AGET_CHAR: /* 0x49 */
@@ -4654,6 +4606,7 @@
SET_VREG %edx rINST # vAA<- %edx; value
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_AGET_SHORT: /* 0x4a */
@@ -4731,6 +4684,7 @@
SET_VREG %edx rINST # vAA<- %edx; value
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_APUT: /* 0x4b */
@@ -4784,6 +4738,7 @@
GET_VREG rINST # rINST<- vAA
movl rINST, offArrayObject_contents(%ecx) # vBB[vCC]<- rINSTx; value
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_APUT_WIDE: /* 0x4c */
@@ -4831,6 +4786,7 @@
movq (rFP, rINST, 4), %xmm0 # %xmm0<- vAA
movq %xmm0, offArrayObject_contents(%ecx, %edx, 8) # vBB[vCC]<- %xmm0; value
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_APUT_OBJECT: /* 0x4d */
@@ -4958,6 +4914,7 @@
movb rINSTbl, offArrayObject_contents(%ecx) # vBB[vCC]<- rINSTx; value
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_APUT_BYTE: /* 0x4f */
@@ -5032,6 +4989,7 @@
movb rINSTbl, offArrayObject_contents(%ecx) # vBB[vCC]<- rINSTx; value
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_APUT_CHAR: /* 0x50 */
@@ -5106,6 +5064,7 @@
movw rINSTw, offArrayObject_contents(%ecx) # vBB[vCC]<- rINSTx; value
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_APUT_SHORT: /* 0x51 */
@@ -5180,6 +5139,7 @@
movw rINSTw, offArrayObject_contents(%ecx) # vBB[vCC]<- rINSTx; value
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_IGET: /* 0x52 */
@@ -5804,26 +5764,6 @@
* limitations under the License.
*/
- /*
- * File: OP_IPUT_OBJECT.S
- */
-
-/* File: x86-atom/OP_IPUT.S */
- /* Copyright (C) 2008 The Android Open Source Project
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
/*
* File: OP_IPUT.S
*
@@ -5846,7 +5786,6 @@
* op vA, vB, field@CCCC
*/
-
movl rGLUE, %edx # %edx<- pMterpGlue
movl offGlue_methodClassDex(%edx), %edx # %edx<- pDvmDex
FETCH 1, %ecx # %ecx<- CCCC
@@ -5857,7 +5796,6 @@
movl rGLUE, %edx # %edx<- pMterpGlue
jmp .LOP_IPUT_OBJECT_finish
-
/* ------------------------------ */
.balign 64
.L_OP_IPUT_BOOLEAN: /* 0x5c */
@@ -6682,26 +6620,6 @@
/*
* File: OP_SPUT_OBJECT.S
- */
-
-/* File: x86-atom/OP_SPUT.S */
- /* Copyright (C) 2008 The Android Open Source Project
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
- /*
- * File: OP_SPUT.S
*
* Code: Generic 32-bit static field "put" operation. Uses no substitutions.
*
@@ -6720,12 +6638,11 @@
movl offGlue_methodClassDex(%edx), %ecx # %ecx<- pDvmDex
FETCH 1, %eax # %eax<- BBBB
movl offDvmDex_pResFields(%ecx), %ecx # %ecx<- pResFields
- cmp $0, (%ecx, %eax, 4) # check for null ptr; resolved StaticField ptr
- movl (%ecx, %eax, 4), %ecx # %ecx<- resolved StaticField ptr
+ cmp $0, (%ecx, %eax, 4) # check for null ptr; resolved StaticField
+ movl (%ecx, %eax, 4), %ecx # %ecx<- resolved StaticField
je .LOP_SPUT_OBJECT_resolve
jmp .LOP_SPUT_OBJECT_finish
-
/* ------------------------------ */
.balign 64
.L_OP_SPUT_BOOLEAN: /* 0x6a */
@@ -7950,6 +7867,7 @@
SET_VREG %ecx, rINST # vA<- result
FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_NOT_INT: /* 0x7c */
@@ -8017,6 +7935,7 @@
SET_VREG %ecx, rINST # vA<- result
FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_NEG_LONG: /* 0x7d */
@@ -8220,6 +8139,7 @@
SET_VREG %ecx, rINST # vA<- result
FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_NEG_DOUBLE: /* 0x80 */
@@ -8479,6 +8399,7 @@
SET_VREG rINST, %ecx # vA<- vB; %edx
FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_LONG_TO_FLOAT: /* 0x85 */
@@ -8896,6 +8817,7 @@
SET_VREG %ecx, rINST # vA<- result
FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_INT_TO_CHAR: /* 0x8e */
@@ -8963,6 +8885,7 @@
SET_VREG %ecx, rINST # vA<- result
FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_INT_TO_SHORT: /* 0x8f */
@@ -9030,6 +8953,7 @@
SET_VREG %ecx, rINST # vA<- result
FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_ADD_INT: /* 0x90 */
@@ -9085,17 +9009,14 @@
* Syntax: op vAA, vBB, vCC
*/
-
-
FETCH_BB 1, %ecx # %ecx<- BB
- OLD_JMP_1 2, %eax
- OLD_JMP_2 %eax
FETCH_CC 1, %edx # %edx<- CC
- OLD_JMP_3 2
+ FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
GET_VREG %ecx # %ecx<- vBB
- addl (rFP, %edx, 4), %ecx # %ecx<- vBB op vCC
+ GET_VREG %edx # %edx<- vCC
+ addl %edx, %ecx # %ecx<- vBB op vCC
SET_VREG %ecx, rINST # vAA<- %ecx; result
- OLD_JMP_4 %eax
+ FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
/* ------------------------------ */
@@ -9153,17 +9074,14 @@
* Syntax: op vAA, vBB, vCC
*/
-
-
FETCH_BB 1, %ecx # %ecx<- BB
- OLD_JMP_1 2, %eax
- OLD_JMP_2 %eax
FETCH_CC 1, %edx # %edx<- CC
- OLD_JMP_3 2
+ FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
GET_VREG %ecx # %ecx<- vBB
- subl (rFP, %edx, 4), %ecx # %ecx<- vBB op vCC
+ GET_VREG %edx # %edx<- vCC
+ subl %edx, %ecx # %ecx<- vBB op vCC
SET_VREG %ecx, rINST # vAA<- %ecx; result
- OLD_JMP_4 %eax
+ FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
/* ------------------------------ */
@@ -9187,10 +9105,33 @@
/*
* File: OP_MUL_INT.S
+ */
+
+/* File: x86-atom/binop.S */
+ /* Copyright (C) 2008 The Android Open Source Project
*
- * Code: 32-bit multiply operation. Performs "%ecx = %ecx * %edx"
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
*
- * Description: Perform a multiplication operation on two source registers
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ /*
+ * File: binop.S
+ *
+ * Code: Generic 32-bit binary operation. Provides an "instr" line to
+ * specify an instruction that performs "%ecx = %ecx op %edx"
+ *
+ * For: add-int, and-int, mul-int, or-int, sub-int, xor-int
+ *
+ * Description: Perform a binary operation on two source registers
* and store the result in a destination register.
*
* Format: AA|op CC|BB (23x)
@@ -9202,10 +9143,11 @@
FETCH_CC 1, %edx # %edx<- CC
FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
GET_VREG %ecx # %ecx<- vBB
- addl $4, rPC # update PC
- imul (rFP, %edx, 4), %ecx # %ecx<- vBB * vCC
+ GET_VREG %edx # %edx<- vCC
+ imul %edx, %ecx # %ecx<- vBB op vCC
SET_VREG %ecx, rINST # vAA<- %ecx; result
- FGETOP_JMP2 %eax # jump to next instruction; getop, jmp
+ FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
@@ -9263,29 +9205,25 @@
*/
-
- FETCH_CC 1, %ecx # %ecx<- CC
FETCH_BB 1, %eax # %eax<- BB
- GET_VREG %ecx # %ecx<- vCC
- testl %ecx, %ecx
+ FETCH_CC 1, %ecx # %ecx<- CC
GET_VREG %eax # %eax<- vBB
+ GET_VREG %ecx # %ecx<- vCC
+ cmp $0, %ecx # check for divide by zero
je common_errDivideByZero # handle divide by zero
cmpl $-1, %ecx # handle -1 special case divide error
- jnz .LOP_DIV_INT_continue
+ jne .LOP_DIV_INT_noerror
cmpl $0x80000000,%eax # handle min int special case divide error
je .LOP_DIV_INT_break
-.LOP_DIV_INT_continue:
+.LOP_DIV_INT_noerror:
cdq # sign-extend %eax to %edx
idiv %ecx # divide %edx:%eax by %ecx
.if 1
- FFETCH_ADV 2 %edx
SET_VREG %eax rINST # vAA<- %eax (quotient)
- FGETOP_JMP 2 %edx
.else
- FFETCH_ADV 2 %eax
- SET_VREG %edx rINST # vAA<- %edx (remainder)
- FGETOP_JMP 2 %eax
+ SET_VREG %edx rINST # vAA<- %edx (remainder)
.endif
+ jmp .LOP_DIV_INT_break2
/* ------------------------------ */
@@ -9344,29 +9282,25 @@
*/
-
- FETCH_CC 1, %ecx # %ecx<- CC
FETCH_BB 1, %eax # %eax<- BB
- GET_VREG %ecx # %ecx<- vCC
- testl %ecx, %ecx
+ FETCH_CC 1, %ecx # %ecx<- CC
GET_VREG %eax # %eax<- vBB
+ GET_VREG %ecx # %ecx<- vCC
+ cmp $0, %ecx # check for divide by zero
je common_errDivideByZero # handle divide by zero
cmpl $-1, %ecx # handle -1 special case divide error
- jnz .LOP_REM_INT_continue
+ jne .LOP_REM_INT_noerror
cmpl $0x80000000,%eax # handle min int special case divide error
je .LOP_REM_INT_break
-.LOP_REM_INT_continue:
+.LOP_REM_INT_noerror:
cdq # sign-extend %eax to %edx
idiv %ecx # divide %edx:%eax by %ecx
.if 0
- FFETCH_ADV 2 %edx
SET_VREG %eax rINST # vAA<- %eax (quotient)
- FGETOP_JMP 2 %edx
.else
- FFETCH_ADV 2 %eax
- SET_VREG %edx rINST # vAA<- %edx (remainder)
- FGETOP_JMP 2 %eax
+ SET_VREG %edx rINST # vAA<- %edx (remainder)
.endif
+ jmp .LOP_REM_INT_break2
/* ------------------------------ */
@@ -9424,17 +9358,14 @@
* Syntax: op vAA, vBB, vCC
*/
-
-
FETCH_BB 1, %ecx # %ecx<- BB
- OLD_JMP_1 2, %eax
- OLD_JMP_2 %eax
FETCH_CC 1, %edx # %edx<- CC
- OLD_JMP_3 2
+ FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
GET_VREG %ecx # %ecx<- vBB
- andl (rFP, %edx, 4), %ecx # %ecx<- vBB op vCC
+ GET_VREG %edx # %edx<- vCC
+ andl %edx, %ecx # %ecx<- vBB op vCC
SET_VREG %ecx, rINST # vAA<- %ecx; result
- OLD_JMP_4 %eax
+ FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
/* ------------------------------ */
@@ -9492,17 +9423,14 @@
* Syntax: op vAA, vBB, vCC
*/
-
-
FETCH_BB 1, %ecx # %ecx<- BB
- OLD_JMP_1 2, %eax
- OLD_JMP_2 %eax
FETCH_CC 1, %edx # %edx<- CC
- OLD_JMP_3 2
+ FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
GET_VREG %ecx # %ecx<- vBB
- or (rFP, %edx, 4), %ecx # %ecx<- vBB op vCC
+ GET_VREG %edx # %edx<- vCC
+ or %edx, %ecx # %ecx<- vBB op vCC
SET_VREG %ecx, rINST # vAA<- %ecx; result
- OLD_JMP_4 %eax
+ FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
/* ------------------------------ */
@@ -9560,17 +9488,14 @@
* Syntax: op vAA, vBB, vCC
*/
-
-
FETCH_BB 1, %ecx # %ecx<- BB
- OLD_JMP_1 2, %eax
- OLD_JMP_2 %eax
FETCH_CC 1, %edx # %edx<- CC
- OLD_JMP_3 2
+ FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
GET_VREG %ecx # %ecx<- vBB
- xor (rFP, %edx, 4), %ecx # %ecx<- vBB op vCC
+ GET_VREG %edx # %edx<- vCC
+ xor %edx, %ecx # %ecx<- vBB op vCC
SET_VREG %ecx, rINST # vAA<- %ecx; result
- OLD_JMP_4 %eax
+ FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
/* ------------------------------ */
@@ -9628,15 +9553,15 @@
* Syntax: op vAA, vBB, vCC
*/
- FETCH_CC 1, %ecx # %ecx<- CC
FETCH_BB 1, %edx # %edx<- BB
+ FETCH_CC 1, %ecx # %ecx<- CC
FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
- addl $4, rPC # update PC
- GET_VREG %ecx # %ecx<- vCC
GET_VREG %edx # %edx<- vBB
+ GET_VREG %ecx # %ecx<- vCC
sal %cl, %edx # %edx<- vBB op +CC
SET_VREG %edx, rINST # vAA<- %edx; result
- FGETOP_JMP2 %eax # jump to next instruction; getop, jmp
+ FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
@@ -9693,15 +9618,15 @@
* Syntax: op vAA, vBB, vCC
*/
- FETCH_CC 1, %ecx # %ecx<- CC
FETCH_BB 1, %edx # %edx<- BB
+ FETCH_CC 1, %ecx # %ecx<- CC
FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
- addl $4, rPC # update PC
- GET_VREG %ecx # %ecx<- vCC
GET_VREG %edx # %edx<- vBB
+ GET_VREG %ecx # %ecx<- vCC
sar %cl, %edx # %edx<- vBB op +CC
SET_VREG %edx, rINST # vAA<- %edx; result
- FGETOP_JMP2 %eax # jump to next instruction; getop, jmp
+ FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
@@ -9758,15 +9683,15 @@
* Syntax: op vAA, vBB, vCC
*/
- FETCH_CC 1, %ecx # %ecx<- CC
FETCH_BB 1, %edx # %edx<- BB
+ FETCH_CC 1, %ecx # %ecx<- CC
FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
- addl $4, rPC # update PC
- GET_VREG %ecx # %ecx<- vCC
GET_VREG %edx # %edx<- vBB
+ GET_VREG %ecx # %ecx<- vCC
shr %cl, %edx # %edx<- vBB op +CC
SET_VREG %edx, rINST # vAA<- %edx; result
- FGETOP_JMP2 %eax # jump to next instruction; getop, jmp
+ FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
@@ -9833,6 +9758,7 @@
movq %xmm0, (rFP, rINST, 4) # vAA<- %ecx
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_SUB_LONG: /* 0x9c */
@@ -9898,6 +9824,7 @@
movq %xmm0, (rFP, rINST, 4) # vAA<- %ecx
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_MUL_LONG: /* 0x9d */
@@ -10153,6 +10080,7 @@
movq %xmm0, (rFP, rINST, 4) # vAA<- %ecx
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_OR_LONG: /* 0xa1 */
@@ -10218,6 +10146,7 @@
movq %xmm0, (rFP, rINST, 4) # vAA<- %ecx
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_XOR_LONG: /* 0xa2 */
@@ -10283,6 +10212,7 @@
movq %xmm0, (rFP, rINST, 4) # vAA<- %ecx
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_SHL_LONG: /* 0xa3 */
@@ -10482,6 +10412,7 @@
movss %xmm0, (rFP, rINST, 4) # vAA<- %xmm0; result
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_SUB_FLOAT: /* 0xa7 */
@@ -10546,6 +10477,7 @@
movss %xmm0, (rFP, rINST, 4) # vAA<- %xmm0; result
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_MUL_FLOAT: /* 0xa8 */
@@ -10610,6 +10542,7 @@
movss %xmm0, (rFP, rINST, 4) # vAA<- %xmm0; result
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_DIV_FLOAT: /* 0xa9 */
@@ -10765,6 +10698,7 @@
movq %xmm0, (rFP, rINST, 4) # vAA<- %ecx
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_SUB_DOUBLE: /* 0xac */
@@ -10830,6 +10764,7 @@
movq %xmm0, (rFP, rINST, 4) # vAA<- %ecx
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_MUL_DOUBLE: /* 0xad */
@@ -10895,6 +10830,7 @@
movq %xmm0, (rFP, rINST, 4) # vAA<- %ecx
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_DIV_DOUBLE: /* 0xae */
@@ -11044,15 +10980,16 @@
movl rINST, %edx # %edx<- BA
shr $4, %edx # %edx<- B
- #FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
- OLD_JMP_1 1, %eax
- andl $15, rINST # rINST<- A
- OLD_JMP_2 %eax
+ andl $15, rINST # rINST<- A
+ movl rINST, %ecx # %ecx<- A
+ FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
GET_VREG %edx # %edx<- vB
- OLD_JMP_3 1
- addl %edx, (rFP, rINST, 4) # %ecx<- vA op vB
- #FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
- OLD_JMP_4 %eax
+ GET_VREG %ecx # %ecx<- vA
+ addl %edx, %ecx # %ecx<- vA op vB
+ SET_VREG %ecx, rINST # vAA<- %ecx; result
+ FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+
+
/* ------------------------------ */
@@ -11114,15 +11051,16 @@
movl rINST, %edx # %edx<- BA
shr $4, %edx # %edx<- B
- #FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
- OLD_JMP_1 1, %eax
- andl $15, rINST # rINST<- A
- OLD_JMP_2 %eax
+ andl $15, rINST # rINST<- A
+ movl rINST, %ecx # %ecx<- A
+ FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
GET_VREG %edx # %edx<- vB
- OLD_JMP_3 1
- subl %edx, (rFP, rINST, 4) # %ecx<- vA op vB
- #FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
- OLD_JMP_4 %eax
+ GET_VREG %ecx # %ecx<- vA
+ subl %edx, %ecx # %ecx<- vA op vB
+ SET_VREG %ecx, rINST # vAA<- %ecx; result
+ FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+
+
/* ------------------------------ */
@@ -11148,16 +11086,53 @@
* File: OP_MUL_INT_2ADDR.S
*/
+/* File: x86-atom/binop2addr.S */
+ /* Copyright (C) 2008 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ /*
+ * File: binop2addr.S
+ *
+ * Code: Generic 32-bit "/2addr" binary operation. Provides an
+ * "instr" line to specify an instruction that performs
+ * "%ecx = %ecx op %edx".
+ *
+ * For: add-int/2addr, and-int/2addr, mul-int/2addr, or-int/2addr,
+ * sub-int/2addr, xor-int/2addr
+ *
+ * Description: Perform a binary operation on two sources registers
+ * and store the result in the first source register
+ *
+ * Format: B|A|op (12x)
+ *
+ * Syntax: op vA, vB
+ */
+
movl rINST, %edx # %edx<- BA
shr $4, %edx # %edx<- B
andl $15, rINST # rINST<- A
movl rINST, %ecx # %ecx<- A
FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
+ GET_VREG %edx # %edx<- vB
GET_VREG %ecx # %ecx<- vA
- imul (rFP, %edx, 4), %ecx # %ecx<- vA * vB
- addl $2, rPC # update PC
+ imul %edx, %ecx # %ecx<- vA op vB
SET_VREG %ecx, rINST # vAA<- %ecx; result
- FGETOP_JMP2 %eax # jump to next instruction; getop, jmp
+ FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+
+
+
/* ------------------------------ */
.balign 64
@@ -11216,30 +11191,28 @@
*/
movl rINST, %ecx # %ecx<- BA
- shr $4, %ecx # %ecx<- B
andl $15, rINST # rINST<- A, to be used as dest
movl rINST, %eax # %eax<- A
- GET_VREG %ecx # %edx<- vB
- testl %ecx, %ecx # check for divide by zero
+ shr $4, %ecx # %ecx<- B
GET_VREG %eax # %eax<- vA
- jz common_errDivideByZero # handle divide by zero
+ GET_VREG %ecx # %edx<- vB
+ cmp $0, %ecx # check for divide by zero
+ je common_errDivideByZero # handle divide by zero
cmpl $-1, %ecx # handle -1 special case divide error
- jnz .LOP_DIV_INT_2ADDR_continue
- cmpl $0x80000000, %eax # handle min int special case divide error
+ jne .LOP_DIV_INT_2ADDR_noerror
+ cmpl $0x80000000,%eax # handle min int special case divide error
je .LOP_DIV_INT_2ADDR_break
-
-.LOP_DIV_INT_2ADDR_continue:
+.LOP_DIV_INT_2ADDR_noerror:
cdq # sign-extend %eax to %edx
idiv %ecx # divide %edx:%eax by %ecx
.if 1
- FFETCH_ADV 1, %edx # %ecx<- next instruction hi; fetch, advance
SET_VREG %eax rINST # vAA<- %eax (quotient)
- FGETOP_JMP 1, %edx # jump to next instruction; getop, jmp
.else
- FFETCH_ADV 1, %eax # %ecx<- next instruction hi; fetch, advance
SET_VREG %edx rINST # vAA<- %edx (remainder)
- FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
.endif
+ jmp .LOP_DIV_INT_2ADDR_break2
+ #FFETCH_ADV 1, %edx # %ecx<- next instruction hi; fetch, advance
+ #FGETOP_JMP 1, %edx # jump to next instruction; getop, jmp
@@ -11300,30 +11273,28 @@
*/
movl rINST, %ecx # %ecx<- BA
- shr $4, %ecx # %ecx<- B
andl $15, rINST # rINST<- A, to be used as dest
movl rINST, %eax # %eax<- A
- GET_VREG %ecx # %edx<- vB
- testl %ecx, %ecx # check for divide by zero
+ shr $4, %ecx # %ecx<- B
GET_VREG %eax # %eax<- vA
- jz common_errDivideByZero # handle divide by zero
+ GET_VREG %ecx # %edx<- vB
+ cmp $0, %ecx # check for divide by zero
+ je common_errDivideByZero # handle divide by zero
cmpl $-1, %ecx # handle -1 special case divide error
- jnz .LOP_REM_INT_2ADDR_continue
- cmpl $0x80000000, %eax # handle min int special case divide error
+ jne .LOP_REM_INT_2ADDR_noerror
+ cmpl $0x80000000,%eax # handle min int special case divide error
je .LOP_REM_INT_2ADDR_break
-
-.LOP_REM_INT_2ADDR_continue:
+.LOP_REM_INT_2ADDR_noerror:
cdq # sign-extend %eax to %edx
idiv %ecx # divide %edx:%eax by %ecx
.if 0
- FFETCH_ADV 1, %edx # %ecx<- next instruction hi; fetch, advance
SET_VREG %eax rINST # vAA<- %eax (quotient)
- FGETOP_JMP 1, %edx # jump to next instruction; getop, jmp
.else
- FFETCH_ADV 1, %eax # %ecx<- next instruction hi; fetch, advance
SET_VREG %edx rINST # vAA<- %edx (remainder)
- FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
.endif
+ jmp .LOP_REM_INT_2ADDR_break2
+ #FFETCH_ADV 1, %edx # %ecx<- next instruction hi; fetch, advance
+ #FGETOP_JMP 1, %edx # jump to next instruction; getop, jmp
@@ -11386,15 +11357,16 @@
movl rINST, %edx # %edx<- BA
shr $4, %edx # %edx<- B
- #FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
- OLD_JMP_1 1, %eax
- andl $15, rINST # rINST<- A
- OLD_JMP_2 %eax
+ andl $15, rINST # rINST<- A
+ movl rINST, %ecx # %ecx<- A
+ FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
GET_VREG %edx # %edx<- vB
- OLD_JMP_3 1
- andl %edx, (rFP, rINST, 4) # %ecx<- vA op vB
- #FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
- OLD_JMP_4 %eax
+ GET_VREG %ecx # %ecx<- vA
+ andl %edx, %ecx # %ecx<- vA op vB
+ SET_VREG %ecx, rINST # vAA<- %ecx; result
+ FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+
+
/* ------------------------------ */
@@ -11456,15 +11428,16 @@
movl rINST, %edx # %edx<- BA
shr $4, %edx # %edx<- B
- #FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
- OLD_JMP_1 1, %eax
- andl $15, rINST # rINST<- A
- OLD_JMP_2 %eax
+ andl $15, rINST # rINST<- A
+ movl rINST, %ecx # %ecx<- A
+ FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
GET_VREG %edx # %edx<- vB
- OLD_JMP_3 1
- or %edx, (rFP, rINST, 4) # %ecx<- vA op vB
- #FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
- OLD_JMP_4 %eax
+ GET_VREG %ecx # %ecx<- vA
+ or %edx, %ecx # %ecx<- vA op vB
+ SET_VREG %ecx, rINST # vAA<- %ecx; result
+ FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+
+
/* ------------------------------ */
@@ -11526,15 +11499,16 @@
movl rINST, %edx # %edx<- BA
shr $4, %edx # %edx<- B
- #FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
- OLD_JMP_1 1, %eax
- andl $15, rINST # rINST<- A
- OLD_JMP_2 %eax
+ andl $15, rINST # rINST<- A
+ movl rINST, %ecx # %ecx<- A
+ FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
GET_VREG %edx # %edx<- vB
- OLD_JMP_3 1
- xor %edx, (rFP, rINST, 4) # %ecx<- vA op vB
- #FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
- OLD_JMP_4 %eax
+ GET_VREG %ecx # %ecx<- vA
+ xor %edx, %ecx # %ecx<- vA op vB
+ SET_VREG %ecx, rINST # vAA<- %ecx; result
+ FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+
+
/* ------------------------------ */
@@ -11595,15 +11569,15 @@
movl rINST, %ecx # %ecx<- BA
shr $4, %ecx # %ecx<- B
- FFETCH_ADV 1, %eax # %ecx<- next i nstruction hi; fetch, advance
andl $15, rINST # rINST<- A
- addl $2, rPC # update PC
movl rINST, %edx # %edx<- A
+ FFETCH_ADV 1, %eax # %ecx<- next instruction hi; fetch, advance
GET_VREG %ecx # %ecx<- vB
GET_VREG %edx # %edx<- vA
sal %cl, %edx # %edx<- vA op vB
SET_VREG %edx, rINST # vAA<- %edx; result
- FGETOP_JMP2 %eax # jump to next instruction; getop, jmp
+ FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
@@ -11663,15 +11637,15 @@
movl rINST, %ecx # %ecx<- BA
shr $4, %ecx # %ecx<- B
- FFETCH_ADV 1, %eax # %ecx<- next i nstruction hi; fetch, advance
andl $15, rINST # rINST<- A
- addl $2, rPC # update PC
movl rINST, %edx # %edx<- A
+ FFETCH_ADV 1, %eax # %ecx<- next instruction hi; fetch, advance
GET_VREG %ecx # %ecx<- vB
GET_VREG %edx # %edx<- vA
sar %cl, %edx # %edx<- vA op vB
SET_VREG %edx, rINST # vAA<- %edx; result
- FGETOP_JMP2 %eax # jump to next instruction; getop, jmp
+ FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
@@ -11731,15 +11705,15 @@
movl rINST, %ecx # %ecx<- BA
shr $4, %ecx # %ecx<- B
- FFETCH_ADV 1, %eax # %ecx<- next i nstruction hi; fetch, advance
andl $15, rINST # rINST<- A
- addl $2, rPC # update PC
movl rINST, %edx # %edx<- A
+ FFETCH_ADV 1, %eax # %ecx<- next instruction hi; fetch, advance
GET_VREG %ecx # %ecx<- vB
GET_VREG %edx # %edx<- vA
shr %cl, %edx # %edx<- vA op vB
SET_VREG %edx, rINST # vAA<- %edx; result
- FGETOP_JMP2 %eax # jump to next instruction; getop, jmp
+ FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
@@ -11801,13 +11775,12 @@
movl rINST, %edx # %edx<- BA
shr $4, rINST # rINST<- B
andl $15, %edx # %edx<- A
- FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
movq (rFP, rINST, 4), %xmm1 # %xmm1<- vB
movq (rFP, %edx, 4), %xmm0 # %xmm0<- vA
paddq %xmm1, %xmm0 # %xmm0<- vA op vB
movq %xmm0, (rFP, %edx, 4) # vA<- %xmm0; result
- #FINISH 1 # jump to next instruction
- FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+ FINISH 1 # jump to next instruction
+
/* ------------------------------ */
.balign 64
@@ -11869,13 +11842,12 @@
movl rINST, %edx # %edx<- BA
shr $4, rINST # rINST<- B
andl $15, %edx # %edx<- A
- FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
movq (rFP, rINST, 4), %xmm1 # %xmm1<- vB
movq (rFP, %edx, 4), %xmm0 # %xmm0<- vA
psubq %xmm1, %xmm0 # %xmm0<- vA op vB
movq %xmm0, (rFP, %edx, 4) # vA<- %xmm0; result
- #FINISH 1 # jump to next instruction
- FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+ FINISH 1 # jump to next instruction
+
/* ------------------------------ */
.balign 64
@@ -12130,13 +12102,12 @@
movl rINST, %edx # %edx<- BA
shr $4, rINST # rINST<- B
andl $15, %edx # %edx<- A
- FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
movq (rFP, rINST, 4), %xmm1 # %xmm1<- vB
movq (rFP, %edx, 4), %xmm0 # %xmm0<- vA
pand %xmm1, %xmm0 # %xmm0<- vA op vB
movq %xmm0, (rFP, %edx, 4) # vA<- %xmm0; result
- #FINISH 1 # jump to next instruction
- FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+ FINISH 1 # jump to next instruction
+
/* ------------------------------ */
.balign 64
@@ -12198,13 +12169,12 @@
movl rINST, %edx # %edx<- BA
shr $4, rINST # rINST<- B
andl $15, %edx # %edx<- A
- FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
movq (rFP, rINST, 4), %xmm1 # %xmm1<- vB
movq (rFP, %edx, 4), %xmm0 # %xmm0<- vA
por %xmm1, %xmm0 # %xmm0<- vA op vB
movq %xmm0, (rFP, %edx, 4) # vA<- %xmm0; result
- #FINISH 1 # jump to next instruction
- FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+ FINISH 1 # jump to next instruction
+
/* ------------------------------ */
.balign 64
@@ -12266,13 +12236,12 @@
movl rINST, %edx # %edx<- BA
shr $4, rINST # rINST<- B
andl $15, %edx # %edx<- A
- FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
movq (rFP, rINST, 4), %xmm1 # %xmm1<- vB
movq (rFP, %edx, 4), %xmm0 # %xmm0<- vA
pxor %xmm1, %xmm0 # %xmm0<- vA op vB
movq %xmm0, (rFP, %edx, 4) # vA<- %xmm0; result
- #FINISH 1 # jump to next instruction
- FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+ FINISH 1 # jump to next instruction
+
/* ------------------------------ */
.balign 64
@@ -12479,6 +12448,7 @@
movss %xmm0, (rFP, %ecx, 4) # vA<- %xmm0; result
FGETOP_JMP 1, %edx # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_SUB_FLOAT_2ADDR: /* 0xc7 */
@@ -12545,6 +12515,7 @@
movss %xmm0, (rFP, %ecx, 4) # vA<- %xmm0; result
FGETOP_JMP 1, %edx # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_MUL_FLOAT_2ADDR: /* 0xc8 */
@@ -12611,6 +12582,7 @@
movss %xmm0, (rFP, %ecx, 4) # vA<- %xmm0; result
FGETOP_JMP 1, %edx # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_DIV_FLOAT_2ADDR: /* 0xc9 */
@@ -12762,13 +12734,12 @@
movl rINST, %edx # %edx<- BA
shr $4, rINST # rINST<- B
andl $15, %edx # %edx<- A
- FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
movq (rFP, rINST, 4), %xmm1 # %xmm1<- vB
movq (rFP, %edx, 4), %xmm0 # %xmm0<- vA
addsd %xmm1, %xmm0 # %xmm0<- vA op vB
movq %xmm0, (rFP, %edx, 4) # vA<- %xmm0; result
- #FINISH 1 # jump to next instruction
- FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+ FINISH 1 # jump to next instruction
+
/* ------------------------------ */
.balign 64
@@ -12830,13 +12801,12 @@
movl rINST, %edx # %edx<- BA
shr $4, rINST # rINST<- B
andl $15, %edx # %edx<- A
- FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
movq (rFP, rINST, 4), %xmm1 # %xmm1<- vB
movq (rFP, %edx, 4), %xmm0 # %xmm0<- vA
subsd %xmm1, %xmm0 # %xmm0<- vA op vB
movq %xmm0, (rFP, %edx, 4) # vA<- %xmm0; result
- #FINISH 1 # jump to next instruction
- FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+ FINISH 1 # jump to next instruction
+
/* ------------------------------ */
.balign 64
@@ -12898,13 +12868,12 @@
movl rINST, %edx # %edx<- BA
shr $4, rINST # rINST<- B
andl $15, %edx # %edx<- A
- FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
movq (rFP, rINST, 4), %xmm1 # %xmm1<- vB
movq (rFP, %edx, 4), %xmm0 # %xmm0<- vA
mulsd %xmm1, %xmm0 # %xmm0<- vA op vB
movq %xmm0, (rFP, %edx, 4) # vA<- %xmm0; result
- #FINISH 1 # jump to next instruction
- FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+ FINISH 1 # jump to next instruction
+
/* ------------------------------ */
.balign 64
@@ -13065,6 +13034,7 @@
SET_VREG %ecx, rINST # vA<- %ecx; result
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_RSUB_INT: /* 0xd1 */
@@ -13108,6 +13078,7 @@
subl %ecx, %edx # %edx<- +CCCC sub vB
SET_VREG %edx, rINST # vA<- %edx; result
FINISH 2 # jump to next instruction
+
/* ------------------------------ */
.balign 64
.L_OP_MUL_INT_LIT16: /* 0xd2 */
@@ -13176,6 +13147,7 @@
SET_VREG %ecx, rINST # vA<- %ecx; result
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_DIV_INT_LIT16: /* 0xd3 */
@@ -13236,29 +13208,24 @@
movl rINST, %eax # %eax<- BA
shr $4, %eax # %eax<- B
FETCHs 1, %ecx # %ecx<- +CCCC, sign-extended literal
- testl %ecx, %ecx # check for divide by zero
+ cmp $0, %ecx # check for divide by zero
GET_VREG %eax # %eax<- vB
je common_errDivideByZero # handle divide by zero
- addl $4, rPC # update PC
andl $15, rINST # rINST<- A
cmpl $-1, %ecx # handle -1 special case divide error
- jnz .LOP_DIV_INT_LIT16_continue
+ jne .LOP_DIV_INT_LIT16_noerror
cmpl $0x80000000,%eax # handle min int special case divide error
- je .LOP_DIV_INT_LIT16_break
-.LOP_DIV_INT_LIT16_continue:
+ je .LOP_DIV_INT_LIT16_break
+.LOP_DIV_INT_LIT16_noerror:
cdq # sign-extend %eax to %edx
idiv %ecx # divide %edx:%eax by %ecx
+ #FFETCH_ADV 2, %ecx # %ecx<- next instruction hi; fetch, advance
.if 1
- movzbl (rPC), %edx
- SET_VREG %eax, rINST # vA<- %eax (quotient)
- movzbl 1(rPC), rINST
- jmp *dvmAsmInstructionJmpTable(, %edx, 4)
+ SET_VREG %eax rINST # vA<- %eax (quotient)
.else
- movzbl (rPC), %eax
- SET_VREG %edx, rINST # vA<- %edx (remainder)
- movzbl 1(rPC), rINST
- jmp *dvmAsmInstructionJmpTable(, %eax, 4)
+ SET_VREG %edx rINST # vA<- %edx (remainder)
.endif
+ jmp .LOP_DIV_INT_LIT16_break2
@@ -13322,29 +13289,24 @@
movl rINST, %eax # %eax<- BA
shr $4, %eax # %eax<- B
FETCHs 1, %ecx # %ecx<- +CCCC, sign-extended literal
- testl %ecx, %ecx # check for divide by zero
+ cmp $0, %ecx # check for divide by zero
GET_VREG %eax # %eax<- vB
je common_errDivideByZero # handle divide by zero
- addl $4, rPC # update PC
andl $15, rINST # rINST<- A
cmpl $-1, %ecx # handle -1 special case divide error
- jnz .LOP_REM_INT_LIT16_continue
+ jne .LOP_REM_INT_LIT16_noerror
cmpl $0x80000000,%eax # handle min int special case divide error
- je .LOP_REM_INT_LIT16_break
-.LOP_REM_INT_LIT16_continue:
+ je .LOP_REM_INT_LIT16_break
+.LOP_REM_INT_LIT16_noerror:
cdq # sign-extend %eax to %edx
idiv %ecx # divide %edx:%eax by %ecx
+ #FFETCH_ADV 2, %ecx # %ecx<- next instruction hi; fetch, advance
.if 0
- movzbl (rPC), %edx
- SET_VREG %eax, rINST # vA<- %eax (quotient)
- movzbl 1(rPC), rINST
- jmp *dvmAsmInstructionJmpTable(, %edx, 4)
+ SET_VREG %eax rINST # vA<- %eax (quotient)
.else
- movzbl (rPC), %eax
- SET_VREG %edx, rINST # vA<- %edx (remainder)
- movzbl 1(rPC), rINST
- jmp *dvmAsmInstructionJmpTable(, %eax, 4)
+ SET_VREG %edx rINST # vA<- %edx (remainder)
.endif
+ jmp .LOP_REM_INT_LIT16_break2
@@ -13416,6 +13378,7 @@
SET_VREG %ecx, rINST # vA<- %ecx; result
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_OR_INT_LIT16: /* 0xd6 */
@@ -13484,6 +13447,7 @@
SET_VREG %ecx, rINST # vA<- %ecx; result
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_XOR_INT_LIT16: /* 0xd7 */
@@ -13552,6 +13516,7 @@
SET_VREG %ecx, rINST # vA<- %ecx; result
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_ADD_INT_LIT8: /* 0xd8 */
@@ -13617,6 +13582,7 @@
SET_VREG %ecx, rINST # vAA<- %ecx; result
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_RSUB_INT_LIT8: /* 0xd9 */
@@ -13723,6 +13689,7 @@
SET_VREG %ecx, rINST # vAA<- %ecx; result
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_DIV_INT_LIT8: /* 0xdb */
@@ -13780,30 +13747,26 @@
*/
- FETCH_CCs 1, %ecx # %ecx<- +CC, sign-extended literal
- testl %ecx, %ecx # handle -1 special case divide error
FETCH_BB 1, %eax # %eax<- BB
- jz common_errDivideByZero # handle divide by zero
- addl $4, rPC # update PC
- cmpl $-1, %ecx
+ FETCH_CCs 1, %ecx # %ecx<- +CC, sign-extended literal
+ cmp $0, %ecx # check for divide by zero
GET_VREG %eax # %eax<- vBB
- jnz .LOP_DIV_INT_LIT8_continue
+ je common_errDivideByZero # handle divide by zero
+
+ cmpl $-1, %ecx # handle -1 special case divide error
+ jne .LOP_DIV_INT_LIT8_noerror
cmpl $0x80000000,%eax # handle min int special case divide error
- je .LOP_DIV_INT_LIT8_break
-.LOP_DIV_INT_LIT8_continue:
+ je .LOP_DIV_INT_LIT8_break
+.LOP_DIV_INT_LIT8_noerror:
cdq # sign-extend %eax to %edx
idiv %ecx # divide %edx:%eax by %ecx
+ #FFETCH_ADV 2, %ecx # %ecx<- next instruction hi; fetch, advance
.if 1
- movzbl (rPC), %edx
- SET_VREG %eax, rINST # vA<- %eax (quotient)
- movzbl 1(rPC), rINST
- jmp *dvmAsmInstructionJmpTable(, %edx, 4)
+ SET_VREG %eax rINST # vAA<- %eax (quotient)
.else
- movzbl (rPC), %eax
- SET_VREG %edx, rINST # vA<- %edx (remainder)
- movzbl 1(rPC), rINST
- jmp *dvmAsmInstructionJmpTable(, %eax, 4)
+ SET_VREG %edx rINST # vAA<- %edx (remainder)
.endif
+ jmp .LOP_DIV_INT_LIT8_break2
/* ------------------------------ */
@@ -13863,30 +13826,26 @@
*/
- FETCH_CCs 1, %ecx # %ecx<- +CC, sign-extended literal
- testl %ecx, %ecx # handle -1 special case divide error
FETCH_BB 1, %eax # %eax<- BB
- jz common_errDivideByZero # handle divide by zero
- addl $4, rPC # update PC
- cmpl $-1, %ecx
+ FETCH_CCs 1, %ecx # %ecx<- +CC, sign-extended literal
+ cmp $0, %ecx # check for divide by zero
GET_VREG %eax # %eax<- vBB
- jnz .LOP_REM_INT_LIT8_continue
+ je common_errDivideByZero # handle divide by zero
+
+ cmpl $-1, %ecx # handle -1 special case divide error
+ jne .LOP_REM_INT_LIT8_noerror
cmpl $0x80000000,%eax # handle min int special case divide error
- je .LOP_REM_INT_LIT8_break
-.LOP_REM_INT_LIT8_continue:
+ je .LOP_REM_INT_LIT8_break
+.LOP_REM_INT_LIT8_noerror:
cdq # sign-extend %eax to %edx
idiv %ecx # divide %edx:%eax by %ecx
+ #FFETCH_ADV 2, %ecx # %ecx<- next instruction hi; fetch, advance
.if 0
- movzbl (rPC), %edx
- SET_VREG %eax, rINST # vA<- %eax (quotient)
- movzbl 1(rPC), rINST
- jmp *dvmAsmInstructionJmpTable(, %edx, 4)
+ SET_VREG %eax rINST # vAA<- %eax (quotient)
.else
- movzbl (rPC), %eax
- SET_VREG %edx, rINST # vA<- %edx (remainder)
- movzbl 1(rPC), rINST
- jmp *dvmAsmInstructionJmpTable(, %eax, 4)
+ SET_VREG %edx rINST # vAA<- %edx (remainder)
.endif
+ jmp .LOP_REM_INT_LIT8_break2
/* ------------------------------ */
@@ -13954,6 +13913,7 @@
SET_VREG %ecx, rINST # vAA<- %ecx; result
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_OR_INT_LIT8: /* 0xde */
@@ -14019,6 +13979,7 @@
SET_VREG %ecx, rINST # vAA<- %ecx; result
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_XOR_INT_LIT8: /* 0xdf */
@@ -14084,6 +14045,7 @@
SET_VREG %ecx, rINST # vAA<- %ecx; result
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_SHL_INT_LIT8: /* 0xe0 */
@@ -14149,6 +14111,7 @@
SET_VREG %edx, rINST # vAA<- %edx; result
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_SHR_INT_LIT8: /* 0xe1 */
@@ -14214,6 +14177,7 @@
SET_VREG %edx, rINST # vAA<- %edx; result
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_USHR_INT_LIT8: /* 0xe2 */
@@ -14279,6 +14243,7 @@
SET_VREG %edx, rINST # vAA<- %edx; result
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+
/* ------------------------------ */
.balign 64
.L_OP_IGET_VOLATILE: /* 0xe3 */
@@ -14534,11 +14499,31 @@
/* ------------------------------ */
.balign 64
.L_OP_BREAKPOINT: /* 0xec */
-/* File: x86-atom/OP_BREAKPOINT.S */
-/* File: x86/unused.S */
- jmp common_abort
+ /* Copyright (C) 2008 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ /*
+ * File: stub.S
+ */
+ SAVE_PC_FP_TO_GLUE %edx # save program counter and frame pointer
+ pushl rGLUE # push parameter glue
+ call dvmMterp_OP_BREAKPOINT # call c-based implementation
+ lea 4(%esp), %esp
+ LOAD_PC_FP_FROM_GLUE # restore program counter and frame pointer
+ FINISH_A # jump to next instruction
/* ------------------------------ */
.balign 64
.L_OP_THROW_VERIFICATION_ERROR: /* 0xed */
@@ -14573,16 +14558,16 @@
* Syntax: op vAA, ref@BBBB
*/
- movl rGLUE, %edx # %edx<- pMterpGlue
- movl offGlue_method(%edx), %ecx # %ecx<- glue->method
- EXPORT_PC # in case an exception is thrown
- FETCH 1, %eax # %eax<- BBBB
- movl %eax, -4(%esp) # push parameter BBBB; ref
- movl rINST, -8(%esp) # push parameter AA
- movl %ecx, -12(%esp) # push parameter glue->method
+ movl rGLUE, %edx # %edx<- pMterpGlue
+ movl offGlue_method(%edx), %ecx # %ecx<- glue->method
+ EXPORT_PC # in case an exception is thrown
+ FETCH 1, %eax # %eax<- BBBB
+ movl %eax, -4(%esp) # push parameter BBBB; ref
+ movl rINST, -8(%esp) # push parameter AA
+ movl %ecx, -12(%esp) # push parameter glue->method
lea -12(%esp), %esp
- call dvmThrowVerificationError # call: (const Method* method, int kind, int ref)
- jmp common_exceptionThrown # failed; handle exception
+ call dvmThrowVerificationError # call: (const Method* method, int kind, int ref)
+ jmp common_exceptionThrown # failed; handle exception
/* ------------------------------ */
.balign 64
@@ -14615,14 +14600,14 @@
*
* Format:
*
- * Syntax: A, {vC, vD, vE, vF}, inline@BBBB
+ * Syntax: vAA, {vC, vD, vE, vF}, inline@BBBB
*/
FETCH 1, %ecx # %ecx<- BBBB
movl rGLUE, %eax # %eax<- MterpGlue pointer
addl $offGlue_retval, %eax # %eax<- &glue->retval
EXPORT_PC
- shr $4, rINST # rINST<- A
+ shr $4, rINST # rINST<- B
movl %eax, -8(%esp) # push parameter glue->retval
lea -24(%esp), %esp
jmp .LOP_EXECUTE_INLINE_continue
@@ -14630,8 +14615,7 @@
/* ------------------------------ */
.balign 64
.L_OP_EXECUTE_INLINE_RANGE: /* 0xef */
-/* File: x86-atom/OP_EXECUTE_INLINE_RANGE.S */
- /* Copyright (C) 2010 The Android Open Source Project
+ /* Copyright (C) 2008 The Android Open Source Project
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -14647,28 +14631,15 @@
*/
/*
- * File: OP_EXECUTE_INLINE_RANGE.S
- *
- * Code: Executes a "native inline" instruction. Uses no substitutions.
- *
- * For: execute-inline
- *
- * Description: Executes a "native inline" instruction. This instruction
- * is generated by the optimizer.
- *
- * Format:
- *
- * Syntax: AA, {vCCCC..v(CCCC+AA-1)}, inline@BBBB
+ * File: stub.S
*/
- FETCH 1, %ecx # %ecx<- BBBB
- movl rGLUE, %eax # %eax<- MterpGlue pointer
- addl $offGlue_retval, %eax # %eax<- &glue->retval
- EXPORT_PC
- movl %eax, -8(%esp) # push parameter glue->retval
- lea -24(%esp), %esp
- jmp .LOP_EXECUTE_INLINE_RANGE_continue
-
+ SAVE_PC_FP_TO_GLUE %edx # save program counter and frame pointer
+ pushl rGLUE # push parameter glue
+ call dvmMterp_OP_EXECUTE_INLINE_RANGE # call c-based implementation
+ lea 4(%esp), %esp
+ LOAD_PC_FP_FROM_GLUE # restore program counter and frame pointer
+ FINISH_A # jump to next instruction
/* ------------------------------ */
.balign 64
.L_OP_INVOKE_DIRECT_EMPTY: /* 0xf0 */
@@ -14699,6 +14670,7 @@
*/
FINISH 3
+
/* ------------------------------ */
.balign 64
.L_OP_UNUSED_F1: /* 0xf1 */
@@ -15010,26 +14982,6 @@
*/
/*
- * File: OP_IPUT_OBJECT_QUICK.S
- */
-
-/* File: x86-atom/OP_IPUT_QUICK.S */
- /* Copyright (C) 2008 The Android Open Source Project
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
- /*
* File: OP_IPUT_QUICK.S
* Code: Optimization for iput
*
@@ -15050,9 +15002,15 @@
FFETCH_ADV 2, %edx # %edx<- next instruction hi; fetch, advance
GET_VREG rINST # rINST<- vA
movl rINST, (%eax, %ecx) # object field<- vA
+ testl rINST, rINST # did we write a null object
+ je 1f
+ movl rGLUE, %ecx # get glue
+ movl offGlue_cardTable(%ecx), %ecx # get card table base
+ shrl $GC_CARD_SHIFT, %eax # get gc card index
+ movb %cl, (%eax, %ecx) # mark gc card in table
+1:
FGETOP_JMP 2, %edx # jump to next instruction; getop, jmp
-
/* ------------------------------ */
.balign 64
.L_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */
@@ -15474,6 +15432,7 @@
je common_exceptionThrown # resolve failed; exception thrown
SET_VREG %eax, rINST # vAA<- %eax; pResString[BBBB]
FINISH 3 # jump to next instruction
+
/* continuation for OP_CONST_CLASS */
/*
@@ -15499,6 +15458,7 @@
je common_exceptionThrown # handle exception
SET_VREG %eax, rINST # vAA<- resolved class
FINISH 2 # jump to next instruction
+
/* continuation for OP_CHECK_CAST */
.LOP_CHECK_CAST_resolved:
@@ -15809,8 +15769,14 @@
.LOP_FILLED_NEW_ARRAY_continue:
movl offClassObject_descriptor(%eax), %eax # %eax<- arrayClass->descriptor
movzbl 1(%eax), %eax # %eax<- descriptor[1]
- cmp $'I', %eax # check if array of ints
+ cmpb $'I', %al # check if array of ints
+ je 1f
+ cmpb $'L', %al
+ je 1f
+ cmpb $'[', %al
jne .LOP_FILLED_NEW_ARRAY_notimpl # jump to not implemented
+1:
+ movl %eax, sReg0 # save type
movl rINST, -12(%esp) # push parameter length
movl %eax, -16(%esp) # push parameter descriptor[1]
movl $ALLOC_DONT_TRACK, -8(%esp) # push parameter to allocate flags
@@ -15863,6 +15829,14 @@
jns 1b # or continue at 2
.endif
2:
+ cmpb $'I', sReg0 # check for int array
+ je 3f
+ movl rGLUE, %ecx # %ecx<- MterpGlue pointer
+ movl offGlue_retval(%ecx), %eax # Object head
+ movl offGlue_cardTable(%ecx), %ecx # card table base
+ shrl $GC_CARD_SHIFT, %eax # convert to card num
+ movb %cl,(%ecx, %eax) # mark card based on object head
+3:
FINISH 3 # jump to next instruction
/*
@@ -15913,8 +15887,14 @@
.LOP_FILLED_NEW_ARRAY_RANGE_continue:
movl offClassObject_descriptor(%eax), %eax # %eax<- arrayClass->descriptor
movzbl 1(%eax), %eax # %eax<- descriptor[1]
- cmp $'I', %eax # check if array of ints
+ cmpb $'I', %al # check if array of ints
+ je 1f
+ cmpb $'L', %al
+ je 1f
+ cmpb $'[', %al
jne .LOP_FILLED_NEW_ARRAY_RANGE_notimpl # jump to not implemented
+1:
+ movl %eax, sReg0 # save type
movl rINST, -12(%esp) # push parameter length
movl %eax, -16(%esp) # push parameter descriptor[1]
movl $ALLOC_DONT_TRACK, -8(%esp) # push parameter to allocate flags
@@ -15967,6 +15947,14 @@
jns 1b # or continue at 2
.endif
2:
+ cmpb $'I', sReg0 # check for int array
+ je 3f
+ movl rGLUE, %ecx # %ecx<- MterpGlue pointer
+ movl offGlue_retval(%ecx), %eax # Object head
+ movl offGlue_cardTable(%ecx), %ecx # card table base
+ shrl $GC_CARD_SHIFT, %eax # convert to card num
+ movb %cl,(%ecx, %eax) # mark card based on object head
+3:
FINISH 3 # jump to next instruction
/*
@@ -16069,6 +16057,7 @@
.LOP_APUT_OBJECT_finish:
movl %edx, sReg0 # save &vBB[vCC]
+ movl %eax, sReg1 # save object head
movl offObject_clazz(rINST), %edx # %edx<- obj->clazz
movl %edx, -8(%esp) # push parameter obj->clazz
movl offObject_clazz(%eax), %eax # %eax<- arrayObj->clazz
@@ -16078,10 +16067,17 @@
# call: ClassObject* elemClass, ClassObject* arrayClass)
# return: bool
lea 8(%esp), %esp
- cmp $0, %eax # check for invalid array value
+ testl %eax, %eax # check for invalid array value
je common_errArrayStore # handle invalid array value
movl sReg0, %edx # restore &vBB[vCC]
-
+ movl rINST, offArrayObject_contents(%edx)
+ movl rGLUE, %eax
+ FFETCH_ADV 2, %ecx # %ecx<- next instruction hi; fetch, advance
+ movl offGlue_cardTable(%eax), %eax # get card table base
+ movl sReg1, %edx # restore object head
+ shrl $GC_CARD_SHIFT, %edx # object head to card number
+ movb %al, (%eax, %edx) # mark card using object head
+ FGETOP_JMP 2, %ecx # jump to next instruction; getop, jmp
.LOP_APUT_OBJECT_skip_check:
FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
movl rINST, offArrayObject_contents(%edx)
@@ -16362,10 +16358,17 @@
cmp $0, %ecx # check for null object
je common_errNullObject # handle null object
movl offInstField_byteOffset(%eax), %edx # %edx<- field offset
- FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
GET_VREG rINST # rINST<- vA
- movl rINST, (%edx, %ecx) # object field<- vA
- FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
+ movl rINST, (%edx, %ecx) # object field<- vA
+ FFETCH_ADV 2, %edx # %edx<- next instruction hi; fetch, advance
+ movl rGLUE, %eax # get glue
+ movl offGlue_cardTable(%eax), %eax # get card table base
+ testl rINST, rINST # test if we stored a null value
+ je 1f # skip card mark if null stored
+ shrl $GC_CARD_SHIFT, %ecx # set obeject head to card number
+ movb %al, (%eax, %ecx)
+1:
+ FGETOP_JMP 2, %edx # jump to next instruction; getop, jmp
/* continuation for OP_IPUT_BOOLEAN */
@@ -16700,7 +16703,17 @@
.LOP_SPUT_OBJECT_finish:
FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
GET_VREG rINST # rINST<- vAA
+
+
movl rINST, offStaticField_value(%ecx) # field value<- vAA
+ testl rINST, rINST # stored null object ptr?
+ je 1f
+ movl rGLUE, %edx # get glue
+ movl offField_clazz(%ecx), %ecx # ecx<- field->clazz
+ movl offGlue_cardTable(%edx), %edx # get card table base
+ shrl $GC_CARD_SHIFT, %ecx # head to card number
+ movb %dl, (%edx, %ecx) # mark card
+1:
FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
/* continuation for OP_SPUT_BOOLEAN */
@@ -16904,6 +16917,7 @@
movl %eax, %ecx # %ecx<- method
jne common_invokeMethodNoRange # invoke method common code
jmp common_errNullObject # handle null object
+
/* continuation for OP_INVOKE_STATIC */
.LOP_INVOKE_STATIC_break:
@@ -17052,6 +17066,7 @@
movl %eax, %ecx # %ecx<- method
jne common_invokeMethodRange # invoke method common code
jmp common_errNullObject # handle null object
+
/* continuation for OP_INVOKE_STATIC_RANGE */
.LOP_INVOKE_STATIC_RANGE_break:
@@ -17207,22 +17222,24 @@
/* continuation for OP_DIV_INT */
.LOP_DIV_INT_break:
- FFETCH_ADV 2 %eax
.if 1
movl $0x80000000, (rFP, rINST, 4) # vAA<- min int
.else
movl $0, (rFP, rINST, 4) # vAA<- 0
.endif
- FGETOP_JMP 2 %eax
+.LOP_DIV_INT_break2:
+ FINISH 2 # jump to next instruction
+
/* continuation for OP_REM_INT */
.LOP_REM_INT_break:
- FFETCH_ADV 2 %eax
.if 0
movl $0x80000000, (rFP, rINST, 4) # vAA<- min int
.else
movl $0, (rFP, rINST, 4) # vAA<- 0
.endif
- FGETOP_JMP 2 %eax
+.LOP_REM_INT_break2:
+ FINISH 2 # jump to next instruction
+
/* continuation for OP_MUL_LONG */
/*
@@ -17290,24 +17307,28 @@
/* continuation for OP_DIV_INT_2ADDR */
.LOP_DIV_INT_2ADDR_break:
- FFETCH_ADV 1, %edx # %ecx<- next instruction hi; fetch, advance
.if 1
movl $0x80000000, (rFP, rINST, 4) # vAA<- min int
.else
movl $0, (rFP, rINST, 4) # vAA<- 0
.endif
+.LOP_DIV_INT_2ADDR_break2:
+ FFETCH_ADV 1, %edx # %ecx<- next instruction hi; fetch, advance
FGETOP_JMP 1, %edx # jump to next instruction; getop, jmp
+
/* continuation for OP_REM_INT_2ADDR */
.LOP_REM_INT_2ADDR_break:
- FFETCH_ADV 1, %edx # %ecx<- next instruction hi; fetch, advance
.if 0
movl $0x80000000, (rFP, rINST, 4) # vAA<- min int
.else
movl $0, (rFP, rINST, 4) # vAA<- 0
.endif
+.LOP_REM_INT_2ADDR_break2:
+ FFETCH_ADV 1, %edx # %ecx<- next instruction hi; fetch, advance
FGETOP_JMP 1, %edx # jump to next instruction; getop, jmp
+
/* continuation for OP_MUL_LONG_2ADDR */
/*
@@ -17341,6 +17362,7 @@
movl %edx, 4(rFP, rINST, 4) # vA<- return high
FFETCH_ADV 1, %ecx # %ecx<- next instruction hi; fetch, advance
FGETOP_JMP 1, %ecx # jump to next instruction; getop, jmp
+
/* continuation for OP_REM_LONG_2ADDR */
.LOP_REM_LONG_2ADDR_break:
movq %xmm0, -20(%esp) # push arg vA, vA+1
@@ -17351,6 +17373,7 @@
movl %edx, 4(rFP, rINST, 4) # vA<- return high
FFETCH_ADV 1, %ecx # %ecx<- next instruction hi; fetch, advance
FGETOP_JMP 1, %ecx # jump to next instruction; getop, jmp
+
/* continuation for OP_SHR_LONG_2ADDR */
.LOP_SHR_LONG_2ADDR_finish:
@@ -17375,47 +17398,49 @@
/* continuation for OP_DIV_INT_LIT16 */
.LOP_DIV_INT_LIT16_break:
- movzbl (rPC), %edx
.if 1
movl $0x80000000, (rFP, rINST, 4) # vAA<- min int
.else
movl $0, (rFP, rINST, 4) # vAA<- 0
.endif
- movzbl 1(rPC), rINST
- jmp *dvmAsmInstructionJmpTable(, %edx, 4)
+.LOP_DIV_INT_LIT16_break2:
+
+ FINISH 2 # jump to next instruction
/* continuation for OP_REM_INT_LIT16 */
.LOP_REM_INT_LIT16_break:
- movzbl (rPC), %edx
.if 0
movl $0x80000000, (rFP, rINST, 4) # vAA<- min int
.else
movl $0, (rFP, rINST, 4) # vAA<- 0
.endif
- movzbl 1(rPC), rINST
- jmp *dvmAsmInstructionJmpTable(, %edx, 4)
+.LOP_REM_INT_LIT16_break2:
+
+ FINISH 2 # jump to next instruction
/* continuation for OP_DIV_INT_LIT8 */
.LOP_DIV_INT_LIT8_break:
- movzbl (rPC), %edx
.if 1
movl $0x80000000, (rFP, rINST, 4) # vAA<- min int
.else
movl $0, (rFP, rINST, 4) # vAA<- 0
.endif
- movzbl 1(rPC), rINST
- jmp *dvmAsmInstructionJmpTable(, %edx, 4)
+
+.LOP_DIV_INT_LIT8_break2:
+ FINISH 2 # jump to next instruction
+ #FGETOP_JMP 2, %ecx # jump to next instruction; getop, jmp
/* continuation for OP_REM_INT_LIT8 */
.LOP_REM_INT_LIT8_break:
- movzbl (rPC), %edx
.if 0
movl $0x80000000, (rFP, rINST, 4) # vAA<- min int
.else
movl $0, (rFP, rINST, 4) # vAA<- 0
.endif
- movzbl 1(rPC), rINST
- jmp *dvmAsmInstructionJmpTable(, %edx, 4)
+
+.LOP_REM_INT_LIT8_break2:
+ FINISH 2 # jump to next instruction
+ #FGETOP_JMP 2, %ecx # jump to next instruction; getop, jmp
/* continuation for OP_EXECUTE_INLINE */
@@ -17465,44 +17490,6 @@
lea 24(%esp), %esp # update stack pointer
je common_exceptionThrown # handle exception
FGETOP_JMP 3, %eax # jump to next instruction; getop, jmp
-/* continuation for OP_EXECUTE_INLINE_RANGE */
-
- /*
- * Extract args, call function.
- * rINST = #of args (0-4)
- * %ecx = call index
- */
-
-.LOP_EXECUTE_INLINE_RANGE_continue:
- FETCH 2, %edx # %edx<- FEDC
- cmp $1, rINST # determine number of arguments
- jl 0f # handle zero args
- je 1f # handle one arg
- cmp $3, rINST
- jl 2f # handle two args
- je 3f # handle three args
-4:
- movl 12(rFP, %edx, 4), rINST # rINST<- vF
- movl rINST, 12(%esp) # push parameter vF
-3:
- movl 8(rFP, %edx, 4), rINST # rINST<- vE
- movl rINST, 8(%esp) # push parameter E
-2:
- movl 4(rFP, %edx, 4), rINST # rINST<- vD
- movl rINST, 4(%esp) # push parameter D
-1:
- movl (rFP, %edx, 4), %edx # rINST<- vC
- movl %edx, (%esp) # push parameter C
-0:
- shl $4, %ecx
- movl $gDvmInlineOpsTable, %eax # %eax<- address for table of inline operations
- call *(%eax, %ecx) # call function
-
- cmp $0, %eax # check boolean result of inline
- FFETCH_ADV 3, %eax # %eax<- next instruction hi; fetch, advance
- lea 24(%esp), %esp # update stack pointer
- je common_exceptionThrown # handle exception
- FGETOP_JMP 3, %eax # jump to next instruction; getop, jmp
.size dvmAsmSisterStart, .-dvmAsmSisterStart
.global dvmAsmSisterEnd
@@ -17557,13 +17544,6 @@
*/
.macro MTERP_EXIT
- #lea 40(%ebp), %esp # correct stack pointer
- #movl 24(%ebp), %edi # restore %edi
- #movl 28(%ebp), %esi # restore %esi
- #movl 32(%ebp), %ebx # restore %ebx
- #movl 36(%ebp), %ebp # restore caller base pointer
- #ret # return
-
lea 40(%esp), %esp # correct stack pointer
movl -16(%esp), %edi # restore %edi
movl -12(%esp), %esi # restore %esi
@@ -17871,11 +17851,11 @@
.long .L_OP_SHL_INT_LIT8
.long .L_OP_SHR_INT_LIT8
.long .L_OP_USHR_INT_LIT8
-.long .L_OP_UNUSED_E3
-.long .L_OP_UNUSED_E4
-.long .L_OP_UNUSED_E5
-.long .L_OP_UNUSED_E6
-.long .L_OP_UNUSED_E7
+.long .L_OP_IGET_VOLATILE
+.long .L_OP_IPUT_VOLATILE
+.long .L_OP_SGET_VOLATILE
+.long .L_OP_SPUT_VOLATILE
+.long .L_OP_IGET_OBJECT_VOLATILE
.long .L_OP_IGET_WIDE_VOLATILE
.long .L_OP_IPUT_WIDE_VOLATILE
.long .L_OP_SGET_WIDE_VOLATILE
@@ -17896,9 +17876,9 @@
.long .L_OP_INVOKE_VIRTUAL_QUICK_RANGE
.long .L_OP_INVOKE_SUPER_QUICK
.long .L_OP_INVOKE_SUPER_QUICK_RANGE
-.long .L_OP_UNUSED_FC
-.long .L_OP_UNUSED_FD
-.long .L_OP_UNUSED_FE
+.long .L_OP_IPUT_OBJECT_VOLATILE
+.long .L_OP_SGET_OBJECT_VOLATILE
+.long .L_OP_SPUT_OBJECT_VOLATILE
.long .L_OP_UNUSED_FF
/* File: x86-atom/footer.S */
@@ -17938,26 +17918,22 @@
movl rGLUE, %edx # %edx<- pMterpGlue
movl %ebx, -4(%esp) # save %ebx to the stack
movl offGlue_pSelfSuspendCount(%edx), %ebx # %ebx<- pSuspendCount (int)
-#if defined(WITH_DEBUGGER)
+4:
movl offGlue_pDebuggerActive(%edx), %eax # %eax<- pDebuggerActive
- movl (%eax), %eax # %eax<- get debuggerActive (boolean)
- and $7, %eax # %eax<- mask for boolean (just how many bits does it take?)
-#endif
+ testl %eax, %eax
+ je 5f
+ movzbl (%eax), %eax # %eax<- get debuggerActive (boolean)
+5:
cmp $0, (%ebx) # check if suspend is pending
jne 2f # handle suspend
-#if defined(WITH_DEBUGGER) || defined(WITH_PROFILER)
-#if defined(WITH_PROFILER)
movl offGlue_pActiveProfilers(%edx), %ebx # %ebx<- activeProfilers (int)
- or (%ebx), %eax # %eax<- merge activeProfilers and debuggerActive
-#else
- cmp $0, %eax # check for debuggerActive
-#endif
- jne 3f # debugger or profiler active; switch interp
-#endif
+ orl (%ebx), %eax # %eax<- merge activeProfilers and debuggerActive
movl -8(%esp), %edx # %edx<- restore %edx
+ jne 3f # debugger or profiler active; switch interp
movl -4(%esp), %ebx # %ebx<- restore %ebx
ret # return
2: # check suspended
+ EXPORT_PC
movl offGlue_self(%edx), %eax # %eax<- glue->self
movl %eax, -12(%esp) # push parameter boolean
lea -12(%esp), %esp
@@ -17966,11 +17942,12 @@
movl 4(%esp), %edx # %edx<- restore %edx
movl 8(%esp), %ebx # %ebx<- restore %ebx
lea 12(%esp), %esp
- ret # return
+ ret
3: # debugger/profiler enabled, bail out
- add -8(%esp), rPC # rPC<- pc adjustments
- movl %ecx, offGlue_entryPoint(%edx) # glue->entryPoint<- reentry type
- movl $1, %edx # switch to interp == true
+ leal (rPC, %edx, 2), rPC # adjust pc to show target
+ movl rGLUE, %ecx # %ecx<- pMterpGlue
+ movb $kInterpEntryInstr, offGlue_entryPoint(%ecx)
+ movl $1, %edx # switch interpreter
jmp common_gotoBail # bail
/*
@@ -17982,25 +17959,21 @@
* %edx is PC adjustment in bytes
*/
-common_periodicChecks2:
+common_periodicChecks_backwardBranch:
+ EXPORT_PC
movl rGLUE, %ecx # %ecx<- pMterpGlue
movl offGlue_pSelfSuspendCount(%ecx), rINST # %ebx<- pSuspendCount (int)
-#if defined(WITH_DEBUGGER)
- movl offGlue_pDebuggerActive(%ecx), %eax # %eax<- pDebuggerActive
- movl (%eax), %eax # %eax<- get debuggerActive (boolean)
- and $7, %eax # %eax<- mask for boolean (just how many bits does it take?)
-#endif
+4:
+ movl offGlue_pDebuggerActive(%ecx), %eax # %eax<- pDebuggerActive
+ testl %eax, %eax # test for NULL pointer
+ je 5f
+ movzbl (%eax), %eax # %eax<- get debuggerActive count
+5:
cmp $0, (rINST) # check if suspend is pending
jne 2f # handle suspend
-#if defined(WITH_DEBUGGER) || defined(WITH_PROFILER)
-#if defined(WITH_PROFILER)
movl offGlue_pActiveProfilers(%ecx), rINST # %edx<- activeProfilers (int)
- or (rINST), %eax # %eax<- merge activeProfilers and debuggerActive
-#else
- cmp $0, %eax # check for debuggerActive
-#endif
+ orl (rINST), %eax # %eax<- merge activeProfilers and debuggerActive
jne 3f # debugger or profiler active; switch interp
-#endif
FINISH_RB %edx, %ecx # jump to next instruction
2: # check suspended
movl offGlue_self(%ecx), %eax# %eax<- glue->self
@@ -18011,15 +17984,13 @@
# return: bool
movl rINST, %edx # %edx<- restore %edx
lea 12(%esp), %esp
- FINISH_RB %edx, %ecx # jump to next instruction
-
+ FINISH_RB %edx, %ecx
3: # debugger/profiler enabled, bail out
- add -8(%esp), rPC # rPC<- pc adjustments
- movl $kInterpEntryInstr, offGlue_entryPoint(%ecx) # glue->entryPoint<- reentry type
- movl $1, %edx # switch to interp<- true
+ leal (rPC, %edx, 2), rPC # adjust pc to show target
+ movb $kInterpEntryInstr, offGlue_entryPoint(%ecx)
+ movl $1, %edx # switch interpreter
jmp common_gotoBail # bail
-
/*
* The equivalent of "goto bail", this calls through the "bail handler".
* State registers will be saved to the "glue" area before bailing.
@@ -18238,13 +18209,14 @@
FGETOP_JMP 3, %edx # jump to next instruction; getop, jmp
.LstackOverflow:
+ movl %ecx, -4(%esp) # push method to call
movl rGLUE, %ecx # %ecx<- pMterpGlue
movl offGlue_self(%ecx), %ecx # %ecx<- glue->self
- movl %ecx, -4(%esp) # push parameter self
- lea -4(%esp), %esp
- call dvmHandleStackOverflow # call: (Thread* self)
+ movl %ecx, -8(%esp) # push parameter self
+ lea -8(%esp), %esp
+ call dvmHandleStackOverflow # call: (Thread* self, Method *meth)
# return: void
- lea 4(%esp), %esp
+ lea 8(%esp), %esp
jmp common_exceptionThrown # handle exception
#ifdef ASSIST_DEBUGGER
#endif
@@ -18264,22 +18236,15 @@
movl rGLUE, rINST # %ecx<- pMterpGlue
movl offGlue_pSelfSuspendCount(rINST), %edx # %ebx<- pSuspendCount (int)
-#if defined(WITH_DEBUGGER)
movl offGlue_pDebuggerActive(rINST), %eax # %eax<- pDebuggerActive
movl (%eax), %eax # %eax<- get debuggerActive (boolean)
and $7, %eax # %eax<- mask for boolean (just how many bits does it take?)
-#endif
cmp $0, (%edx) # check if suspend is pending
jne 2f # handle suspend
-#if defined(WITH_DEBUGGER) || defined(WITH_PROFILER)
-#if defined(WITH_PROFILER)
movl offGlue_pActiveProfilers(rINST), %edx # %edx<- activeProfilers (int)
or (%edx), %eax # %eax<- merge activeProfilers and debuggerActive
-#else
cmp $0, %eax # check for debuggerActive
-#endif
jne 3f # debugger or profiler active; switch interp
-#endif
jmp 4f
2: # check suspended
movl offGlue_self(rINST), %eax# %eax<- glue->self
@@ -18381,7 +18346,7 @@
movl %eax, -4(%esp) # save %eax for later
movl %ecx, -12(%esp) # push parameter 2 glue->self
lea -12(%esp), %esp
- call dvmCleanupStackOverflow # call: (Thread* self)
+ call dvmCleanupStackOverflow # call: (Thread* self, Object* exception)
# return: void
lea 12(%esp), %esp
movl -4(%esp), %eax # %eax<- restore %eax
@@ -18431,7 +18396,7 @@
je 1f #
movl %edx, -12(%esp) # push parameter 1 glue->self
lea -12(%esp), %esp
- call dvmCleanupStackOverflow # call: (Thread* self)
+ call dvmCleanupStackOverflow # call: (Thread* self, Object* exception)
# return: void
lea 12(%esp), %esp
@@ -18467,7 +18432,7 @@
jmp .LdeadFood
.LdeadFood:
-.word 0xdeadf00d
+.int 0xdeadf00d
/*
* Invalid array index.
diff --git a/vm/mterp/out/InterpC-x86-atom.c b/vm/mterp/out/InterpC-x86-atom.c
index ec431df..6d088f7 100644
--- a/vm/mterp/out/InterpC-x86-atom.c
+++ b/vm/mterp/out/InterpC-x86-atom.c
@@ -1231,6 +1231,82 @@
HANDLE_SPUT_X(OP_SPUT_WIDE_VOLATILE, "-wide-volatile", LongVolatile, _WIDE)
OP_END
+/* File: c/OP_BREAKPOINT.c */
+HANDLE_OPCODE(OP_BREAKPOINT)
+#if (INTERP_TYPE == INTERP_DBG)
+ {
+ /*
+ * Restart this instruction with the original opcode. We do
+ * this by simply jumping to the handler.
+ *
+ * It's probably not necessary to update "inst", but we do it
+ * for the sake of anything that needs to do disambiguation in a
+ * common handler with INST_INST.
+ *
+ * The breakpoint itself is handled over in updateDebugger(),
+ * because we need to detect other events (method entry, single
+ * step) and report them in the same event packet, and we're not
+ * yet handling those through breakpoint instructions. By the
+ * time we get here, the breakpoint has already been handled and
+ * the thread resumed.
+ */
+ u1 originalOpCode = dvmGetOriginalOpCode(pc);
+ LOGV("+++ break 0x%02x (0x%04x -> 0x%04x)\n", originalOpCode, inst,
+ INST_REPLACE_OP(inst, originalOpCode));
+ inst = INST_REPLACE_OP(inst, originalOpCode);
+ FINISH_BKPT(originalOpCode);
+ }
+#else
+ LOGE("Breakpoint hit in non-debug interpreter\n");
+ dvmAbort();
+#endif
+OP_END
+
+/* File: c/OP_EXECUTE_INLINE_RANGE.c */
+HANDLE_OPCODE(OP_EXECUTE_INLINE_RANGE /*{vCCCC..v(CCCC+AA-1)}, inline@BBBB*/)
+ {
+ u4 arg0, arg1, arg2, arg3;
+ arg0 = arg1 = arg2 = arg3 = 0; /* placate gcc */
+
+ EXPORT_PC();
+
+ vsrc1 = INST_AA(inst); /* #of args */
+ ref = FETCH(1); /* inline call "ref" */
+ vdst = FETCH(2); /* range base */
+ ILOGV("|execute-inline-range args=%d @%d {regs=v%d-v%d}",
+ vsrc1, ref, vdst, vdst+vsrc1-1);
+
+ assert((vdst >> 16) == 0); // 16-bit type -or- high 16 bits clear
+ assert(vsrc1 <= 4);
+
+ switch (vsrc1) {
+ case 4:
+ arg3 = GET_REGISTER(vdst+3);
+ /* fall through */
+ case 3:
+ arg2 = GET_REGISTER(vdst+2);
+ /* fall through */
+ case 2:
+ arg1 = GET_REGISTER(vdst+1);
+ /* fall through */
+ case 1:
+ arg0 = GET_REGISTER(vdst+0);
+ /* fall through */
+ default: // case 0
+ ;
+ }
+
+#if INTERP_TYPE == INTERP_DBG
+ if (!dvmPerformInlineOp4Dbg(arg0, arg1, arg2, arg3, &retval, ref))
+ GOTO_exceptionThrown();
+#else
+ if (!dvmPerformInlineOp4Std(arg0, arg1, arg2, arg3, &retval, ref))
+ GOTO_exceptionThrown();
+#endif
+ }
+ FINISH(3);
+OP_END
+
/* File: c/OP_IPUT_OBJECT_VOLATILE.c */
HANDLE_IPUT_X(OP_IPUT_OBJECT_VOLATILE, "-object-volatile", ObjectVolatile, _AS_OBJECT)
OP_END
diff --git a/vm/mterp/x86-atom/OP_ADD_FLOAT_2ADDR.S b/vm/mterp/x86-atom/OP_ADD_FLOAT_2ADDR.S
index 7d3aa71..3d62703 100644
--- a/vm/mterp/x86-atom/OP_ADD_FLOAT_2ADDR.S
+++ b/vm/mterp/x86-atom/OP_ADD_FLOAT_2ADDR.S
@@ -17,4 +17,4 @@
* File: OP_ADD_FLOAT_2ADDR.S
*/
-%include "x86-atom/binopF2addr.S" {"instr":"addss %xmm1, %xmm0"}
\ No newline at end of file
+%include "x86-atom/binopF2addr.S" {"instr":"addss %xmm1, %xmm0"}
diff --git a/vm/mterp/x86-atom/OP_ADD_INT.S b/vm/mterp/x86-atom/OP_ADD_INT.S
index 4f14bbd..a423e75 100644
--- a/vm/mterp/x86-atom/OP_ADD_INT.S
+++ b/vm/mterp/x86-atom/OP_ADD_INT.S
@@ -17,4 +17,4 @@
* File: OP_ADD_INT.S
*/
-%include "x86-atom/binop.S" {"instr":"addl (rFP, %edx, 4), %ecx"}
\ No newline at end of file
+%include "x86-atom/binop.S" {"instr":"addl %edx, %ecx"}
diff --git a/vm/mterp/x86-atom/OP_ADD_INT_2ADDR.S b/vm/mterp/x86-atom/OP_ADD_INT_2ADDR.S
index 0bdceaa..2a91f41 100644
--- a/vm/mterp/x86-atom/OP_ADD_INT_2ADDR.S
+++ b/vm/mterp/x86-atom/OP_ADD_INT_2ADDR.S
@@ -17,4 +17,4 @@
* File: OP_ADD_INT_2ADDR.S
*/
-%include "x86-atom/binop2addr.S" {"instr":"addl %edx, (rFP, rINST, 4)"}
+%include "x86-atom/binop2addr.S" {"instr":"addl %edx, %ecx"}
diff --git a/vm/mterp/x86-atom/OP_ADD_INT_LIT16.S b/vm/mterp/x86-atom/OP_ADD_INT_LIT16.S
index dbfddcc..72479ba 100644
--- a/vm/mterp/x86-atom/OP_ADD_INT_LIT16.S
+++ b/vm/mterp/x86-atom/OP_ADD_INT_LIT16.S
@@ -17,4 +17,4 @@
* File: OP_ADD_INT_LIT16.S
*/
-%include "x86-atom/binopLit16.S" {"instr":"addl %edx, %ecx"}
\ No newline at end of file
+%include "x86-atom/binopLit16.S" {"instr":"addl %edx, %ecx"}
diff --git a/vm/mterp/x86-atom/OP_AGET.S b/vm/mterp/x86-atom/OP_AGET.S
index 11e88d1..73a27ab 100644
--- a/vm/mterp/x86-atom/OP_AGET.S
+++ b/vm/mterp/x86-atom/OP_AGET.S
@@ -50,4 +50,4 @@
# doing this and the previous instr
# with one instr was not faster
SET_VREG %edx rINST # vAA<- %edx; value
- FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
\ No newline at end of file
+ FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
diff --git a/vm/mterp/x86-atom/OP_AGET_BOOLEAN.S b/vm/mterp/x86-atom/OP_AGET_BOOLEAN.S
index 1579026..1d28745 100644
--- a/vm/mterp/x86-atom/OP_AGET_BOOLEAN.S
+++ b/vm/mterp/x86-atom/OP_AGET_BOOLEAN.S
@@ -17,4 +17,4 @@
* File: OP_AGET_BOOLEAN.S
*/
-%include "x86-atom/OP_AGET.S" { "mov":"zbl", "scale":"1" }
\ No newline at end of file
+%include "x86-atom/OP_AGET.S" { "mov":"zbl", "scale":"1" }
diff --git a/vm/mterp/x86-atom/OP_AGET_BYTE.S b/vm/mterp/x86-atom/OP_AGET_BYTE.S
index 98df227..60e4266 100644
--- a/vm/mterp/x86-atom/OP_AGET_BYTE.S
+++ b/vm/mterp/x86-atom/OP_AGET_BYTE.S
@@ -17,4 +17,4 @@
* File: OP_AGET_BYTE.S
*/
-%include "x86-atom/OP_AGET.S" { "mov":"sbl", "scale":"1" }
\ No newline at end of file
+%include "x86-atom/OP_AGET.S" { "mov":"sbl", "scale":"1" }
diff --git a/vm/mterp/x86-atom/OP_AGET_CHAR.S b/vm/mterp/x86-atom/OP_AGET_CHAR.S
index 3ee5f9f..114d02d 100644
--- a/vm/mterp/x86-atom/OP_AGET_CHAR.S
+++ b/vm/mterp/x86-atom/OP_AGET_CHAR.S
@@ -17,4 +17,4 @@
* File: OP_AGET_CHAR.S
*/
-%include "x86-atom/OP_AGET.S" { "mov":"zwl", "scale":"2" }
\ No newline at end of file
+%include "x86-atom/OP_AGET.S" { "mov":"zwl", "scale":"2" }
diff --git a/vm/mterp/x86-atom/OP_AGET_SHORT.S b/vm/mterp/x86-atom/OP_AGET_SHORT.S
index dd05637..3ddb9b9 100644
--- a/vm/mterp/x86-atom/OP_AGET_SHORT.S
+++ b/vm/mterp/x86-atom/OP_AGET_SHORT.S
@@ -17,4 +17,4 @@
* File: OP_AGET_SHORT.S
*/
-%include "x86-atom/OP_AGET.S" { "mov":"swl", "scale":"2" }
\ No newline at end of file
+%include "x86-atom/OP_AGET.S" { "mov":"swl", "scale":"2" }
diff --git a/vm/mterp/x86-atom/OP_AGET_WIDE.S b/vm/mterp/x86-atom/OP_AGET_WIDE.S
index 413ea1e..db5a930 100644
--- a/vm/mterp/x86-atom/OP_AGET_WIDE.S
+++ b/vm/mterp/x86-atom/OP_AGET_WIDE.S
@@ -40,4 +40,4 @@
FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
movq offArrayObject_contents(%ecx, %edx, 8), %xmm0 # %xmm0<- vBB[vCC]
movq %xmm0, (rFP, rINST, 4) # vAA<- %xmm0; value
- FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
\ No newline at end of file
+ FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
diff --git a/vm/mterp/x86-atom/OP_AND_INT.S b/vm/mterp/x86-atom/OP_AND_INT.S
index 2f84b34..10d223b 100644
--- a/vm/mterp/x86-atom/OP_AND_INT.S
+++ b/vm/mterp/x86-atom/OP_AND_INT.S
@@ -17,4 +17,4 @@
* File: OP_AND_INT.S
*/
-%include "x86-atom/binop.S" {"instr":"andl (rFP, %edx, 4), %ecx"}
+%include "x86-atom/binop.S" {"instr":"andl %edx, %ecx"}
diff --git a/vm/mterp/x86-atom/OP_AND_INT_2ADDR.S b/vm/mterp/x86-atom/OP_AND_INT_2ADDR.S
index bd3ccf5..dcbd531 100644
--- a/vm/mterp/x86-atom/OP_AND_INT_2ADDR.S
+++ b/vm/mterp/x86-atom/OP_AND_INT_2ADDR.S
@@ -17,4 +17,4 @@
* File: OP_AND_INT_2ADDR.S
*/
-%include "x86-atom/binop2addr.S" {"instr":"andl %edx, (rFP, rINST, 4)"}
\ No newline at end of file
+%include "x86-atom/binop2addr.S" {"instr":"andl %edx, %ecx"}
diff --git a/vm/mterp/x86-atom/OP_AND_INT_LIT16.S b/vm/mterp/x86-atom/OP_AND_INT_LIT16.S
index 6935ebd..7e6493d 100644
--- a/vm/mterp/x86-atom/OP_AND_INT_LIT16.S
+++ b/vm/mterp/x86-atom/OP_AND_INT_LIT16.S
@@ -17,4 +17,4 @@
* File: OP_AND_INT_LIT16.S
*/
-%include "x86-atom/binopLit16.S" {"instr":"andl %edx, %ecx"}
\ No newline at end of file
+%include "x86-atom/binopLit16.S" {"instr":"andl %edx, %ecx"}
diff --git a/vm/mterp/x86-atom/OP_APUT.S b/vm/mterp/x86-atom/OP_APUT.S
index e46294b..93b3866 100644
--- a/vm/mterp/x86-atom/OP_APUT.S
+++ b/vm/mterp/x86-atom/OP_APUT.S
@@ -47,4 +47,4 @@
lea (%ecx, %edx, $scale), %ecx # %ecx<- &vBB[vCC]
GET_VREG rINST # rINST<- vAA
mov$mov $value, offArrayObject_contents(%ecx) # vBB[vCC]<- rINSTx; value
- FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
\ No newline at end of file
+ FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
diff --git a/vm/mterp/x86-atom/OP_APUT_BYTE.S b/vm/mterp/x86-atom/OP_APUT_BYTE.S
index 8d3c650..29cb708 100644
--- a/vm/mterp/x86-atom/OP_APUT_BYTE.S
+++ b/vm/mterp/x86-atom/OP_APUT_BYTE.S
@@ -17,4 +17,4 @@
* File: OP_APUT_BYTE.S
*/
-%include "x86-atom/OP_APUT.S" { "mov":"b", "scale":"1", "value":"rINSTbl" }
\ No newline at end of file
+%include "x86-atom/OP_APUT.S" { "mov":"b", "scale":"1", "value":"rINSTbl" }
diff --git a/vm/mterp/x86-atom/OP_APUT_CHAR.S b/vm/mterp/x86-atom/OP_APUT_CHAR.S
index 9aa2067..d43e540 100644
--- a/vm/mterp/x86-atom/OP_APUT_CHAR.S
+++ b/vm/mterp/x86-atom/OP_APUT_CHAR.S
@@ -17,4 +17,4 @@
* File: OP_APUT_CHAR.S
*/
-%include "x86-atom/OP_APUT.S" { "mov":"w", "scale":"2", "value":"rINSTw" }
\ No newline at end of file
+%include "x86-atom/OP_APUT.S" { "mov":"w", "scale":"2", "value":"rINSTw" }
diff --git a/vm/mterp/x86-atom/OP_APUT_OBJECT.S b/vm/mterp/x86-atom/OP_APUT_OBJECT.S
index 8d71400..0e23d71 100644
--- a/vm/mterp/x86-atom/OP_APUT_OBJECT.S
+++ b/vm/mterp/x86-atom/OP_APUT_OBJECT.S
@@ -50,6 +50,7 @@
.L${opcode}_finish:
movl %edx, sReg0 # save &vBB[vCC]
+ movl %eax, sReg1 # save object head
movl offObject_clazz(rINST), %edx # %edx<- obj->clazz
movl %edx, -8(%esp) # push parameter obj->clazz
movl offObject_clazz(%eax), %eax # %eax<- arrayObj->clazz
@@ -59,10 +60,17 @@
# call: ClassObject* elemClass, ClassObject* arrayClass)
# return: bool
lea 8(%esp), %esp
- cmp $$0, %eax # check for invalid array value
+ testl %eax, %eax # check for invalid array value
je common_errArrayStore # handle invalid array value
movl sReg0, %edx # restore &vBB[vCC]
-
+ movl rINST, offArrayObject_contents(%edx)
+ movl rGLUE, %eax
+ FFETCH_ADV 2, %ecx # %ecx<- next instruction hi; fetch, advance
+ movl offGlue_cardTable(%eax), %eax # get card table base
+ movl sReg1, %edx # restore object head
+ shrl $$GC_CARD_SHIFT, %edx # object head to card number
+ movb %al, (%eax, %edx) # mark card using object head
+ FGETOP_JMP 2, %ecx # jump to next instruction; getop, jmp
.L${opcode}_skip_check:
FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
movl rINST, offArrayObject_contents(%edx)
diff --git a/vm/mterp/x86-atom/OP_APUT_SHORT.S b/vm/mterp/x86-atom/OP_APUT_SHORT.S
index b6cbc98..daef0d8 100644
--- a/vm/mterp/x86-atom/OP_APUT_SHORT.S
+++ b/vm/mterp/x86-atom/OP_APUT_SHORT.S
@@ -17,4 +17,4 @@
* File: OP_APUT_SHORT.S
*/
-%include "x86-atom/OP_APUT.S" { "mov":"w", "scale":"2", "value":"rINSTw" }
\ No newline at end of file
+%include "x86-atom/OP_APUT.S" { "mov":"w", "scale":"2", "value":"rINSTw" }
diff --git a/vm/mterp/x86-atom/OP_APUT_WIDE.S b/vm/mterp/x86-atom/OP_APUT_WIDE.S
index dceb67b..b1b9e6a 100644
--- a/vm/mterp/x86-atom/OP_APUT_WIDE.S
+++ b/vm/mterp/x86-atom/OP_APUT_WIDE.S
@@ -40,4 +40,4 @@
FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
movq (rFP, rINST, 4), %xmm0 # %xmm0<- vAA
movq %xmm0, offArrayObject_contents(%ecx, %edx, 8) # vBB[vCC]<- %xmm0; value
- FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
\ No newline at end of file
+ FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
diff --git a/vm/mterp/x86-atom/OP_ARRAY_LENGTH.S b/vm/mterp/x86-atom/OP_ARRAY_LENGTH.S
index 16427f2..485f815 100644
--- a/vm/mterp/x86-atom/OP_ARRAY_LENGTH.S
+++ b/vm/mterp/x86-atom/OP_ARRAY_LENGTH.S
@@ -31,10 +31,10 @@
movl rINST, %eax # %eax<- BA
shr $$4, %eax # %eax<- B
andl $$15, rINST # rINST<- A
- FFETCH_ADV 1, %edx # %edx<- next instruction hi; fetch, advance
GET_VREG %eax # %eax<- vB
- testl %eax, %eax # check for null array object
+ cmp $$0, %eax # check for null array object
je common_errNullObject # handle null array object
+ FFETCH_ADV 1, %edx # %edx<- next instruction hi; fetch, advance
movl offArrayObject_length(%eax), %eax # %eax<- array length
movl %eax, (rFP, rINST, 4) # vA<- %eax; array length
FGETOP_JMP 1, %edx # jump to next instruction; getop, jmp
diff --git a/vm/mterp/x86-atom/OP_BREAKPOINT.S b/vm/mterp/x86-atom/OP_BREAKPOINT.S
index 31d98c1..e69de29 100644
--- a/vm/mterp/x86-atom/OP_BREAKPOINT.S
+++ b/vm/mterp/x86-atom/OP_BREAKPOINT.S
@@ -1 +0,0 @@
-%include "x86/unused.S"
diff --git a/vm/mterp/x86-atom/OP_CMPG_DOUBLE.S b/vm/mterp/x86-atom/OP_CMPG_DOUBLE.S
index 7008394..87f8a3b 100644
--- a/vm/mterp/x86-atom/OP_CMPG_DOUBLE.S
+++ b/vm/mterp/x86-atom/OP_CMPG_DOUBLE.S
@@ -17,4 +17,4 @@
* File: OP_CMPG_DOUBLE.S
*/
-%include "x86-atom/OP_CMPL_FLOAT.S" { "nan":"$0x1", "sod":"l"}
+%include "x86-atom/OP_CMPL_FLOAT.S" { "nan":"$0x1", "sod":"d"}
diff --git a/vm/mterp/x86-atom/OP_CMPL_DOUBLE.S b/vm/mterp/x86-atom/OP_CMPL_DOUBLE.S
index 010b266..2a603a4 100644
--- a/vm/mterp/x86-atom/OP_CMPL_DOUBLE.S
+++ b/vm/mterp/x86-atom/OP_CMPL_DOUBLE.S
@@ -17,4 +17,4 @@
* File: OP_CMPL_DOUBLE.S
*/
-%include "x86-atom/OP_CMPL_FLOAT.S" { "sod":"l" }
+%include "x86-atom/OP_CMPL_FLOAT.S" { "sod":"d" }
diff --git a/vm/mterp/x86-atom/OP_CMPL_FLOAT.S b/vm/mterp/x86-atom/OP_CMPL_FLOAT.S
index 2a95e89..5cb3ec7 100644
--- a/vm/mterp/x86-atom/OP_CMPL_FLOAT.S
+++ b/vm/mterp/x86-atom/OP_CMPL_FLOAT.S
@@ -38,15 +38,9 @@
FETCH_BB 1, %ecx # %ecx<- BB
FETCH_CC 1, %edx # %edx<- CC
-
- fld$sod (rFP, %edx, 4)
- fld$sod (rFP, %ecx, 4)
-
- fucompp
- fnstsw %ax
- sahf
-
FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
+ movs$sod (rFP, %ecx, 4), %xmm0 # %xmm0<- vBB
+ comis$sod (rFP, %edx, 4), %xmm0 # do comparison
ja .L${opcode}_greater
jp .L${opcode}_finalNan
jz .L${opcode}_final
diff --git a/vm/mterp/x86-atom/OP_CONST.S b/vm/mterp/x86-atom/OP_CONST.S
index 94fe963..7ff4c23 100644
--- a/vm/mterp/x86-atom/OP_CONST.S
+++ b/vm/mterp/x86-atom/OP_CONST.S
@@ -33,4 +33,4 @@
or %edx, %ecx # %ecx<- #+BBBBBBBB
FFETCH_ADV 3, %eax # %eax<- next instruction hi; fetch, advance
SET_VREG %ecx, rINST # vAA<- %ecx; literal
- FGETOP_JMP 3, %eax # jump to next instruction; getop, jmp
\ No newline at end of file
+ FGETOP_JMP 3, %eax # jump to next instruction; getop, jmp
diff --git a/vm/mterp/x86-atom/OP_CONST_16.S b/vm/mterp/x86-atom/OP_CONST_16.S
index 13e1cb3..f340696 100644
--- a/vm/mterp/x86-atom/OP_CONST_16.S
+++ b/vm/mterp/x86-atom/OP_CONST_16.S
@@ -31,4 +31,4 @@
FETCHs 1, %edx # %edx<- BBBB
FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
SET_VREG %edx rINST # vAA<- BBBB; literal
- FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
\ No newline at end of file
+ FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
diff --git a/vm/mterp/x86-atom/OP_CONST_4.S b/vm/mterp/x86-atom/OP_CONST_4.S
index d99f151..5396d72 100644
--- a/vm/mterp/x86-atom/OP_CONST_4.S
+++ b/vm/mterp/x86-atom/OP_CONST_4.S
@@ -20,7 +20,7 @@
*
* For: const/4
*
- * Description: Move the given literal value (right-sign-extended to 32
+ * Description: Move the given literal value (right-zero-extended to 32
* bits) into the specified register.
*
* Format: B|A|op (11n)
@@ -30,9 +30,8 @@
movl rINST, %edx # %edx<- BA
andl $$15, rINST # rINST<- A
- FFETCH_ADV 1, %eax # %eax<- next i nstruction hi; fetch, advance
shl $$24, %edx # %edx<- B000
- addl $$2, rPC # update PC
sar $$28, %edx # %edx<- right-zero-extended B
+ FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
SET_VREG %edx, rINST # vA<- %edx; literal
- FGETOP_JMP2 %eax # jump to next instruction; getop, jmp
\ No newline at end of file
+ FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
diff --git a/vm/mterp/x86-atom/OP_CONST_CLASS.S b/vm/mterp/x86-atom/OP_CONST_CLASS.S
index 9000e11..bc6657c 100644
--- a/vm/mterp/x86-atom/OP_CONST_CLASS.S
+++ b/vm/mterp/x86-atom/OP_CONST_CLASS.S
@@ -64,4 +64,4 @@
cmp $$0, %eax # check for null pointer
je common_exceptionThrown # handle exception
SET_VREG %eax, rINST # vAA<- resolved class
- FINISH 2 # jump to next instruction
\ No newline at end of file
+ FINISH 2 # jump to next instruction
diff --git a/vm/mterp/x86-atom/OP_CONST_STRING_JUMBO.S b/vm/mterp/x86-atom/OP_CONST_STRING_JUMBO.S
index 54e5ea7..09d045d 100644
--- a/vm/mterp/x86-atom/OP_CONST_STRING_JUMBO.S
+++ b/vm/mterp/x86-atom/OP_CONST_STRING_JUMBO.S
@@ -63,4 +63,4 @@
cmp $$0, %eax # check if resolved string failed
je common_exceptionThrown # resolve failed; exception thrown
SET_VREG %eax, rINST # vAA<- %eax; pResString[BBBB]
- FINISH 3 # jump to next instruction
\ No newline at end of file
+ FINISH 3 # jump to next instruction
diff --git a/vm/mterp/x86-atom/OP_CONST_WIDE_16.S b/vm/mterp/x86-atom/OP_CONST_WIDE_16.S
index e2df8f2..c980f10 100644
--- a/vm/mterp/x86-atom/OP_CONST_WIDE_16.S
+++ b/vm/mterp/x86-atom/OP_CONST_WIDE_16.S
@@ -34,4 +34,4 @@
FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
movl %edx, (rFP, rINST, 4) # vAA<- ssssBBBB
movl %ecx, 4(rFP, rINST, 4) # vAA+1<- ssssssss
- FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
\ No newline at end of file
+ FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
diff --git a/vm/mterp/x86-atom/OP_CONST_WIDE_32.S b/vm/mterp/x86-atom/OP_CONST_WIDE_32.S
index 333e991..92f8450 100644
--- a/vm/mterp/x86-atom/OP_CONST_WIDE_32.S
+++ b/vm/mterp/x86-atom/OP_CONST_WIDE_32.S
@@ -36,4 +36,4 @@
FFETCH_ADV 3, %eax # %eax<- next instruction hi; fetch, advance
movl %edx, (rFP, rINST, 4) # vAA<- BBBBBBBB
movl %ecx, 4(rFP, rINST, 4) # vAA+1<- ssssssss
- FGETOP_JMP 3, %eax # jump to next instruction; getop, jmp
\ No newline at end of file
+ FGETOP_JMP 3, %eax # jump to next instruction; getop, jmp
diff --git a/vm/mterp/x86-atom/OP_EXECUTE_INLINE.S b/vm/mterp/x86-atom/OP_EXECUTE_INLINE.S
index 5309c26..4f01cef 100644
--- a/vm/mterp/x86-atom/OP_EXECUTE_INLINE.S
+++ b/vm/mterp/x86-atom/OP_EXECUTE_INLINE.S
@@ -25,14 +25,14 @@
*
* Format:
*
- * Syntax: A, {vC, vD, vE, vF}, inline@BBBB
+ * Syntax: vAA, {vC, vD, vE, vF}, inline@BBBB
*/
FETCH 1, %ecx # %ecx<- BBBB
movl rGLUE, %eax # %eax<- MterpGlue pointer
addl $$offGlue_retval, %eax # %eax<- &glue->retval
EXPORT_PC
- shr $$4, rINST # rINST<- A
+ shr $$4, rINST # rINST<- B
movl %eax, -8(%esp) # push parameter glue->retval
lea -24(%esp), %esp
jmp .L${opcode}_continue
@@ -83,4 +83,4 @@
FFETCH_ADV 3, %eax # %eax<- next instruction hi; fetch, advance
lea 24(%esp), %esp # update stack pointer
je common_exceptionThrown # handle exception
- FGETOP_JMP 3, %eax # jump to next instruction; getop, jmp
\ No newline at end of file
+ FGETOP_JMP 3, %eax # jump to next instruction; getop, jmp
diff --git a/vm/mterp/x86-atom/OP_FILLED_NEW_ARRAY.S b/vm/mterp/x86-atom/OP_FILLED_NEW_ARRAY.S
index c6236d7..f804f3e 100644
--- a/vm/mterp/x86-atom/OP_FILLED_NEW_ARRAY.S
+++ b/vm/mterp/x86-atom/OP_FILLED_NEW_ARRAY.S
@@ -80,8 +80,14 @@
.L${opcode}_continue:
movl offClassObject_descriptor(%eax), %eax # %eax<- arrayClass->descriptor
movzbl 1(%eax), %eax # %eax<- descriptor[1]
- cmp $$'I', %eax # check if array of ints
+ cmpb $$'I', %al # check if array of ints
+ je 1f
+ cmpb $$'L', %al
+ je 1f
+ cmpb $$'[', %al
jne .L${opcode}_notimpl # jump to not implemented
+1:
+ movl %eax, sReg0 # save type
movl rINST, -12(%esp) # push parameter length
movl %eax, -16(%esp) # push parameter descriptor[1]
movl $$ALLOC_DONT_TRACK, -8(%esp) # push parameter to allocate flags
@@ -134,6 +140,14 @@
jns 1b # or continue at 2
.endif
2:
+ cmpb $$'I', sReg0 # check for int array
+ je 3f
+ movl rGLUE, %ecx # %ecx<- MterpGlue pointer
+ movl offGlue_retval(%ecx), %eax # Object head
+ movl offGlue_cardTable(%ecx), %ecx # card table base
+ shrl $$GC_CARD_SHIFT, %eax # convert to card num
+ movb %cl,(%ecx, %eax) # mark card based on object head
+3:
FINISH 3 # jump to next instruction
/*
diff --git a/vm/mterp/x86-atom/OP_GOTO.S b/vm/mterp/x86-atom/OP_GOTO.S
index 12d847e..7bd9956 100644
--- a/vm/mterp/x86-atom/OP_GOTO.S
+++ b/vm/mterp/x86-atom/OP_GOTO.S
@@ -32,5 +32,5 @@
movsbl rINSTbl, %edx # %edx<- +AA
shl $$1, %edx # %edx is shifted for byte offset
- js common_periodicChecks2 # do check on backwards branch
+ js common_periodicChecks_backwardBranch # do check on backwards branch
FINISH_RB %edx, %ecx # jump to next instruction
diff --git a/vm/mterp/x86-atom/OP_GOTO_16.S b/vm/mterp/x86-atom/OP_GOTO_16.S
index 6e6e0ac..931d215 100644
--- a/vm/mterp/x86-atom/OP_GOTO_16.S
+++ b/vm/mterp/x86-atom/OP_GOTO_16.S
@@ -30,5 +30,5 @@
FETCHs 1, %edx # %edx<- ssssAAAA (sign-extended)
shl $$1, %edx # %edx is doubled to get the byte offset
- js common_periodicChecks2 # do check on backwards branch
+ js common_periodicChecks_backwardBranch # do check on backwards branch
FINISH_RB %edx, %ecx # jump to next instruction
diff --git a/vm/mterp/x86-atom/OP_GOTO_32.S b/vm/mterp/x86-atom/OP_GOTO_32.S
index 2dadda6..d00c3a4 100644
--- a/vm/mterp/x86-atom/OP_GOTO_32.S
+++ b/vm/mterp/x86-atom/OP_GOTO_32.S
@@ -33,5 +33,5 @@
shl $$16, %ecx # prepare to create +AAAAAAAA
or %ecx, %edx # %edx<- +AAAAAAAA
shl $$1, %edx # %edx is doubled to get the byte offset
- jle common_periodicChecks2 # do check on backwards branch
+ jle common_periodicChecks_backwardBranch # do check on backwards branch
FINISH_RB %edx, %ecx # jump to next instruction
diff --git a/vm/mterp/x86-atom/OP_IF_EQ.S b/vm/mterp/x86-atom/OP_IF_EQ.S
index ba1a2d2..61781a0 100644
--- a/vm/mterp/x86-atom/OP_IF_EQ.S
+++ b/vm/mterp/x86-atom/OP_IF_EQ.S
@@ -17,4 +17,4 @@
* File: OP_IF_EQ.S
*/
-%include "x86-atom/bincmp.S" { "revcmp":"ne" }
\ No newline at end of file
+%include "x86-atom/bincmp.S" { "revcmp":"ne" }
diff --git a/vm/mterp/x86-atom/OP_IF_EQZ.S b/vm/mterp/x86-atom/OP_IF_EQZ.S
index 5aacfc7..2f7c140 100644
--- a/vm/mterp/x86-atom/OP_IF_EQZ.S
+++ b/vm/mterp/x86-atom/OP_IF_EQZ.S
@@ -17,4 +17,4 @@
* File: OP_IF_EQZ.S
*/
-%include "x86-atom/zcmp.S" { "revcmp":"ne" }
\ No newline at end of file
+%include "x86-atom/zcmp.S" { "revcmp":"ne" }
diff --git a/vm/mterp/x86-atom/OP_IF_GE.S b/vm/mterp/x86-atom/OP_IF_GE.S
index 6fbfca5..e90a1e5 100644
--- a/vm/mterp/x86-atom/OP_IF_GE.S
+++ b/vm/mterp/x86-atom/OP_IF_GE.S
@@ -17,4 +17,4 @@
* File: OP_IF_GE.S
*/
-%include "x86-atom/bincmp.S" { "revcmp":"l" }
\ No newline at end of file
+%include "x86-atom/bincmp.S" { "revcmp":"l" }
diff --git a/vm/mterp/x86-atom/OP_IF_GEZ.S b/vm/mterp/x86-atom/OP_IF_GEZ.S
index a953318..8ee71a8 100644
--- a/vm/mterp/x86-atom/OP_IF_GEZ.S
+++ b/vm/mterp/x86-atom/OP_IF_GEZ.S
@@ -17,4 +17,4 @@
* File: OP_IF_GEZ.S
*/
-%include "x86-atom/zcmp.S" { "revcmp":"l" }
\ No newline at end of file
+%include "x86-atom/zcmp.S" { "revcmp":"l" }
diff --git a/vm/mterp/x86-atom/OP_IF_GT.S b/vm/mterp/x86-atom/OP_IF_GT.S
index fa6f8ee..7f19db9 100644
--- a/vm/mterp/x86-atom/OP_IF_GT.S
+++ b/vm/mterp/x86-atom/OP_IF_GT.S
@@ -17,4 +17,4 @@
* File: OP_IF_GT.S
*/
-%include "x86-atom/bincmp.S" { "revcmp":"le" }
\ No newline at end of file
+%include "x86-atom/bincmp.S" { "revcmp":"le" }
diff --git a/vm/mterp/x86-atom/OP_IF_GTZ.S b/vm/mterp/x86-atom/OP_IF_GTZ.S
index 397561f..3f8039f 100644
--- a/vm/mterp/x86-atom/OP_IF_GTZ.S
+++ b/vm/mterp/x86-atom/OP_IF_GTZ.S
@@ -17,4 +17,4 @@
* File: OP_IF_GTZ.S
*/
-%include "x86-atom/zcmp.S" { "revcmp":"le" }
\ No newline at end of file
+%include "x86-atom/zcmp.S" { "revcmp":"le" }
diff --git a/vm/mterp/x86-atom/OP_IF_LE.S b/vm/mterp/x86-atom/OP_IF_LE.S
index 480c2a1..287bd0d 100644
--- a/vm/mterp/x86-atom/OP_IF_LE.S
+++ b/vm/mterp/x86-atom/OP_IF_LE.S
@@ -17,4 +17,4 @@
* File: OP_IF_LE.S
*/
-%include "x86-atom/bincmp.S" { "revcmp":"g" }
\ No newline at end of file
+%include "x86-atom/bincmp.S" { "revcmp":"g" }
diff --git a/vm/mterp/x86-atom/OP_IF_LEZ.S b/vm/mterp/x86-atom/OP_IF_LEZ.S
index ed9048b..b7d31d1 100644
--- a/vm/mterp/x86-atom/OP_IF_LEZ.S
+++ b/vm/mterp/x86-atom/OP_IF_LEZ.S
@@ -17,4 +17,4 @@
* File: OP_IF_LEZ.S
*/
-%include "x86-atom/zcmp.S" { "revcmp":"g" }
\ No newline at end of file
+%include "x86-atom/zcmp.S" { "revcmp":"g" }
diff --git a/vm/mterp/x86-atom/OP_IF_LT.S b/vm/mterp/x86-atom/OP_IF_LT.S
index 16c86b8..7e58e18 100644
--- a/vm/mterp/x86-atom/OP_IF_LT.S
+++ b/vm/mterp/x86-atom/OP_IF_LT.S
@@ -17,4 +17,4 @@
* File: OP_IF_LT.S
*/
-%include "x86-atom/bincmp.S" { "revcmp":"ge" }
\ No newline at end of file
+%include "x86-atom/bincmp.S" { "revcmp":"ge" }
diff --git a/vm/mterp/x86-atom/OP_IF_LTZ.S b/vm/mterp/x86-atom/OP_IF_LTZ.S
index acdf95e..0a3e56b 100644
--- a/vm/mterp/x86-atom/OP_IF_LTZ.S
+++ b/vm/mterp/x86-atom/OP_IF_LTZ.S
@@ -17,4 +17,4 @@
* File: OP_IF_LTZ.S
*/
-%include "x86-atom/zcmp.S" { "revcmp":"ge" }
\ No newline at end of file
+%include "x86-atom/zcmp.S" { "revcmp":"ge" }
diff --git a/vm/mterp/x86-atom/OP_IF_NE.S b/vm/mterp/x86-atom/OP_IF_NE.S
index 5c3da51..929bd05 100644
--- a/vm/mterp/x86-atom/OP_IF_NE.S
+++ b/vm/mterp/x86-atom/OP_IF_NE.S
@@ -17,4 +17,4 @@
* File: OP_IF_NE.S
*/
-%include "x86-atom/bincmp.S" { "revcmp":"e" }
\ No newline at end of file
+%include "x86-atom/bincmp.S" { "revcmp":"e" }
diff --git a/vm/mterp/x86-atom/OP_IF_NEZ.S b/vm/mterp/x86-atom/OP_IF_NEZ.S
index c3286f0..07f2c87 100644
--- a/vm/mterp/x86-atom/OP_IF_NEZ.S
+++ b/vm/mterp/x86-atom/OP_IF_NEZ.S
@@ -17,4 +17,4 @@
* File: OP_IF_NEZ.S
*/
-%include "x86-atom/zcmp.S" { "revcmp":"e" }
\ No newline at end of file
+%include "x86-atom/zcmp.S" { "revcmp":"e" }
diff --git a/vm/mterp/x86-atom/OP_IGET_OBJECT_VOLATILE.S b/vm/mterp/x86-atom/OP_IGET_OBJECT_VOLATILE.S
new file mode 100644
index 0000000..5de2fa3
--- /dev/null
+++ b/vm/mterp/x86-atom/OP_IGET_OBJECT_VOLATILE.S
@@ -0,0 +1 @@
+%include "x86/OP_IGET.S"
diff --git a/vm/mterp/x86-atom/OP_IGET_VOLATILE.S b/vm/mterp/x86-atom/OP_IGET_VOLATILE.S
new file mode 100644
index 0000000..5de2fa3
--- /dev/null
+++ b/vm/mterp/x86-atom/OP_IGET_VOLATILE.S
@@ -0,0 +1 @@
+%include "x86/OP_IGET.S"
diff --git a/vm/mterp/x86-atom/OP_INT_TO_BYTE.S b/vm/mterp/x86-atom/OP_INT_TO_BYTE.S
index 7d0a89d..27cafe9 100644
--- a/vm/mterp/x86-atom/OP_INT_TO_BYTE.S
+++ b/vm/mterp/x86-atom/OP_INT_TO_BYTE.S
@@ -17,4 +17,4 @@
* File: OP_INT_TO_BYTE.S
*/
-%include "x86-atom/unop.S" { "preinstr":"sal $24, %ecx", "instr":"sar $24, %ecx" }
\ No newline at end of file
+%include "x86-atom/unop.S" { "preinstr":"sal $24, %ecx", "instr":"sar $24, %ecx" }
diff --git a/vm/mterp/x86-atom/OP_INVOKE_DIRECT.S b/vm/mterp/x86-atom/OP_INVOKE_DIRECT.S
index 8f2a987..78b6c06 100644
--- a/vm/mterp/x86-atom/OP_INVOKE_DIRECT.S
+++ b/vm/mterp/x86-atom/OP_INVOKE_DIRECT.S
@@ -89,4 +89,4 @@
cmp $$0, %edx # check for null "this"
movl %eax, %ecx # %ecx<- method
jne common_invokeMethod${routine} # invoke method common code
- jmp common_errNullObject # handle null object
\ No newline at end of file
+ jmp common_errNullObject # handle null object
diff --git a/vm/mterp/x86-atom/OP_INVOKE_DIRECT_EMPTY.S b/vm/mterp/x86-atom/OP_INVOKE_DIRECT_EMPTY.S
index 86d8211..85c0418 100644
--- a/vm/mterp/x86-atom/OP_INVOKE_DIRECT_EMPTY.S
+++ b/vm/mterp/x86-atom/OP_INVOKE_DIRECT_EMPTY.S
@@ -23,4 +23,4 @@
* Format: B|A|op CCCC G|F|E|D (35c)
*/
- FINISH 3
\ No newline at end of file
+ FINISH 3
diff --git a/vm/mterp/x86-atom/OP_IPUT_OBJECT.S b/vm/mterp/x86-atom/OP_IPUT_OBJECT.S
index 33727ca..302cf44 100644
--- a/vm/mterp/x86-atom/OP_IPUT_OBJECT.S
+++ b/vm/mterp/x86-atom/OP_IPUT_OBJECT.S
@@ -13,8 +13,69 @@
* limitations under the License.
*/
- /*
- * File: OP_IPUT_OBJECT.S
+ /*
+ * File: OP_IPUT.S
+ *
+ * Code: Generic 32-bit instance field "put" operation. Provides a
+ * "mov" variable which determines the type of mov performed.
+ * Currently, none of the iput's use this variable - may want
+ * to change this, but seems ok for now.
+ *
+ * For: iput-boolean, iput-byte, iput-char, iput-object, iput
+ * iput-short
+ *
+ * Description: Perform the object instance field "get" operation
+ * with the identified field; load the instance value into
+ * the value register.
+ *
+ *
+ * Format: B|A|op CCCC (22c)
+ *
+ * Syntax: op vA, vB, type@CCCC
+ * op vA, vB, field@CCCC
*/
-%include "x86-atom/OP_IPUT.S"
+ movl rGLUE, %edx # %edx<- pMterpGlue
+ movl offGlue_methodClassDex(%edx), %edx # %edx<- pDvmDex
+ FETCH 1, %ecx # %ecx<- CCCC
+ movl offDvmDex_pResFields(%edx), %edx # %edx<- pDvmDex->pResFields
+ cmp $$0, (%edx, %ecx, 4) # check for null ptr; resolved InstField ptr
+ movl (%edx, %ecx, 4), %eax # %eax<- resolved InstField ptr
+ jne .L${opcode}_finish2
+ movl rGLUE, %edx # %edx<- pMterpGlue
+ jmp .L${opcode}_finish
+%break
+
+.L${opcode}_finish:
+ movl offGlue_method(%edx), %edx # %edx<- glue->method
+ EXPORT_PC # in case an exception is thrown
+ movl %ecx, -4(%esp) # push parameter CCCC; field ref
+ movl offMethod_clazz(%edx), %edx # %edx<- method->clazz
+ lea -8(%esp), %esp
+ movl %edx, (%esp) # push parameter method->clazz
+ call dvmResolveInstField # call: (const ClassObject* referrer, u4 ifieldIdx)
+ # return: InstField*
+ lea 8(%esp), %esp
+ cmp $$0, %eax # check if resolved
+ jne .L${opcode}_finish2
+ jmp common_exceptionThrown # not resolved; handle exception
+
+.L${opcode}_finish2:
+ movl rINST, %ecx # %ecx<- BA+
+ shr $$4, %ecx # %ecx<- B
+ and $$15, rINST # rINST<- A
+ GET_VREG %ecx # %ecx<- vB
+ cmp $$0, %ecx # check for null object
+ je common_errNullObject # handle null object
+ movl offInstField_byteOffset(%eax), %edx # %edx<- field offset
+ GET_VREG rINST # rINST<- vA
+ movl rINST, (%edx, %ecx) # object field<- vA
+ FFETCH_ADV 2, %edx # %edx<- next instruction hi; fetch, advance
+ movl rGLUE, %eax # get glue
+ movl offGlue_cardTable(%eax), %eax # get card table base
+ testl rINST, rINST # test if we stored a null value
+ je 1f # skip card mark if null stored
+ shrl $$GC_CARD_SHIFT, %ecx # set obeject head to card number
+ movb %al, (%eax, %ecx)
+1:
+ FGETOP_JMP 2, %edx # jump to next instruction; getop, jmp
diff --git a/vm/mterp/x86-atom/OP_IPUT_OBJECT_QUICK.S b/vm/mterp/x86-atom/OP_IPUT_OBJECT_QUICK.S
index b1edd5e..eee88e9 100644
--- a/vm/mterp/x86-atom/OP_IPUT_OBJECT_QUICK.S
+++ b/vm/mterp/x86-atom/OP_IPUT_OBJECT_QUICK.S
@@ -14,7 +14,31 @@
*/
/*
- * File: OP_IPUT_OBJECT_QUICK.S
+ * File: OP_IPUT_QUICK.S
+ * Code: Optimization for iput
+ *
+ * For: iput-quick
+ *
+ * Format: B|A|op CCCC (22c)
+ *
+ * Syntax: op vA, vB, offset@CCCC
*/
-%include "x86-atom/OP_IPUT_QUICK.S"
+ movl rINST, %eax # %eax<- BA
+ shr $$4, %eax # %eax<- B
+ and $$15, rINST # rINST<- A
+ GET_VREG %eax # %eax<- vB; object to operate on
+ FETCH 1, %ecx # %ecx<- CCCC; field byte offset
+ cmp $$0, %eax # check if object is null
+ je common_errNullObject # handle null object
+ FFETCH_ADV 2, %edx # %edx<- next instruction hi; fetch, advance
+ GET_VREG rINST # rINST<- vA
+ movl rINST, (%eax, %ecx) # object field<- vA
+ testl rINST, rINST # did we write a null object
+ je 1f
+ movl rGLUE, %ecx # get glue
+ movl offGlue_cardTable(%ecx), %ecx # get card table base
+ shrl $$GC_CARD_SHIFT, %eax # get gc card index
+ movb %cl, (%eax, %ecx) # mark gc card in table
+1:
+ FGETOP_JMP 2, %edx # jump to next instruction; getop, jmp
diff --git a/vm/mterp/x86-atom/OP_IPUT_OBJECT_VOLATILE.S b/vm/mterp/x86-atom/OP_IPUT_OBJECT_VOLATILE.S
new file mode 100644
index 0000000..4b024d0
--- /dev/null
+++ b/vm/mterp/x86-atom/OP_IPUT_OBJECT_VOLATILE.S
@@ -0,0 +1 @@
+%include "x86/OP_IPUT_OBJECT.S"
diff --git a/vm/mterp/x86-atom/OP_IPUT_VOLATILE.S b/vm/mterp/x86-atom/OP_IPUT_VOLATILE.S
new file mode 100644
index 0000000..475a0c5
--- /dev/null
+++ b/vm/mterp/x86-atom/OP_IPUT_VOLATILE.S
@@ -0,0 +1 @@
+%include "x86/OP_IPUT.S"
diff --git a/vm/mterp/x86-atom/OP_LONG_TO_INT.S b/vm/mterp/x86-atom/OP_LONG_TO_INT.S
index 3397fc2..0984bc0 100644
--- a/vm/mterp/x86-atom/OP_LONG_TO_INT.S
+++ b/vm/mterp/x86-atom/OP_LONG_TO_INT.S
@@ -17,4 +17,4 @@
* File: OP_LONG_TO_INT.S
*/
-%include "x86-atom/OP_MOVE.S"
\ No newline at end of file
+%include "x86-atom/OP_MOVE.S"
diff --git a/vm/mterp/x86-atom/OP_MOVE.S b/vm/mterp/x86-atom/OP_MOVE.S
index ebc4989..9982ced 100644
--- a/vm/mterp/x86-atom/OP_MOVE.S
+++ b/vm/mterp/x86-atom/OP_MOVE.S
@@ -35,4 +35,4 @@
FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
GET_VREG rINST # rINST<- vB
SET_VREG rINST, %ecx # vA<- vB; %edx
- FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
\ No newline at end of file
+ FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
diff --git a/vm/mterp/x86-atom/OP_MOVE_OBJECT.S b/vm/mterp/x86-atom/OP_MOVE_OBJECT.S
index 9abc5d0..1cd22cb 100644
--- a/vm/mterp/x86-atom/OP_MOVE_OBJECT.S
+++ b/vm/mterp/x86-atom/OP_MOVE_OBJECT.S
@@ -17,4 +17,4 @@
* File: OP_MOVE_OBJECT.S
*/
-%include "x86-atom/OP_MOVE.S"
\ No newline at end of file
+%include "x86-atom/OP_MOVE.S"
diff --git a/vm/mterp/x86-atom/OP_MOVE_OBJECT_FROM16.S b/vm/mterp/x86-atom/OP_MOVE_OBJECT_FROM16.S
index 1c8e661..bfca7da 100644
--- a/vm/mterp/x86-atom/OP_MOVE_OBJECT_FROM16.S
+++ b/vm/mterp/x86-atom/OP_MOVE_OBJECT_FROM16.S
@@ -17,4 +17,4 @@
* File: OP_MOVE_OBJECT_FROM16.S
*/
-%include "x86-atom/OP_MOVE_FROM16.S"
\ No newline at end of file
+%include "x86-atom/OP_MOVE_FROM16.S"
diff --git a/vm/mterp/x86-atom/OP_MOVE_WIDE.S b/vm/mterp/x86-atom/OP_MOVE_WIDE.S
index 9a91d2a..909243b 100644
--- a/vm/mterp/x86-atom/OP_MOVE_WIDE.S
+++ b/vm/mterp/x86-atom/OP_MOVE_WIDE.S
@@ -34,4 +34,4 @@
FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
movq (rFP, %edx, 4), %xmm0 # %xmm0<- vB
movq %xmm0, (rFP, rINST, 4) # vA<- vB
- FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
\ No newline at end of file
+ FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
diff --git a/vm/mterp/x86-atom/OP_MUL_FLOAT.S b/vm/mterp/x86-atom/OP_MUL_FLOAT.S
index 1529dd5..34eba58 100644
--- a/vm/mterp/x86-atom/OP_MUL_FLOAT.S
+++ b/vm/mterp/x86-atom/OP_MUL_FLOAT.S
@@ -17,4 +17,4 @@
* File: OP_MUL_FLOAT.S
*/
-%include "x86-atom/binopF.S" {"instr":"mulss %xmm1, %xmm0"}
\ No newline at end of file
+%include "x86-atom/binopF.S" {"instr":"mulss %xmm1, %xmm0"}
diff --git a/vm/mterp/x86-atom/OP_MUL_FLOAT_2ADDR.S b/vm/mterp/x86-atom/OP_MUL_FLOAT_2ADDR.S
index 4345ce7..dbd615d 100644
--- a/vm/mterp/x86-atom/OP_MUL_FLOAT_2ADDR.S
+++ b/vm/mterp/x86-atom/OP_MUL_FLOAT_2ADDR.S
@@ -17,4 +17,4 @@
* File: OP_MUL_FLOAT_2ADDR.S
*/
-%include "x86-atom/binopF2addr.S" {"instr":"mulss %xmm1, %xmm0"}
\ No newline at end of file
+%include "x86-atom/binopF2addr.S" {"instr":"mulss %xmm1, %xmm0"}
diff --git a/vm/mterp/x86-atom/OP_MUL_INT.S b/vm/mterp/x86-atom/OP_MUL_INT.S
index b01ecda..8f5dac5 100644
--- a/vm/mterp/x86-atom/OP_MUL_INT.S
+++ b/vm/mterp/x86-atom/OP_MUL_INT.S
@@ -15,22 +15,6 @@
/*
* File: OP_MUL_INT.S
- *
- * Code: 32-bit multiply operation. Performs "%ecx = %ecx * %edx"
- *
- * Description: Perform a multiplication operation on two source registers
- * and store the result in a destination register.
- *
- * Format: AA|op CC|BB (23x)
- *
- * Syntax: op vAA, vBB, vCC
*/
- FETCH_BB 1, %ecx # %ecx<- BB
- FETCH_CC 1, %edx # %edx<- CC
- FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
- GET_VREG %ecx # %ecx<- vBB
- addl $$4, rPC # update PC
- imul (rFP, %edx, 4), %ecx # %ecx<- vBB * vCC
- SET_VREG %ecx, rINST # vAA<- %ecx; result
- FGETOP_JMP2 %eax # jump to next instruction; getop, jmp
+%include "x86-atom/binop.S" {"instr":"imul %edx, %ecx"}
diff --git a/vm/mterp/x86-atom/OP_MUL_INT_2ADDR.S b/vm/mterp/x86-atom/OP_MUL_INT_2ADDR.S
index e907178..b544df7 100644
--- a/vm/mterp/x86-atom/OP_MUL_INT_2ADDR.S
+++ b/vm/mterp/x86-atom/OP_MUL_INT_2ADDR.S
@@ -17,13 +17,4 @@
* File: OP_MUL_INT_2ADDR.S
*/
- movl rINST, %edx # %edx<- BA
- shr $$4, %edx # %edx<- B
- andl $$15, rINST # rINST<- A
- movl rINST, %ecx # %ecx<- A
- FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
- GET_VREG %ecx # %ecx<- vA
- imul (rFP, %edx, 4), %ecx # %ecx<- vA * vB
- addl $$2, rPC # update PC
- SET_VREG %ecx, rINST # vAA<- %ecx; result
- FGETOP_JMP2 %eax # jump to next instruction; getop, jmp
+%include "x86-atom/binop2addr.S" {"instr":"imul %edx, %ecx"}
diff --git a/vm/mterp/x86-atom/OP_MUL_INT_LIT16.S b/vm/mterp/x86-atom/OP_MUL_INT_LIT16.S
index 7f3a27a..241531f 100644
--- a/vm/mterp/x86-atom/OP_MUL_INT_LIT16.S
+++ b/vm/mterp/x86-atom/OP_MUL_INT_LIT16.S
@@ -17,4 +17,4 @@
* File: OP_MUL_INT_LIT16.S
*/
-%include "x86-atom/binopLit16.S" {"instr":"imul %edx, %ecx"}
\ No newline at end of file
+%include "x86-atom/binopLit16.S" {"instr":"imul %edx, %ecx"}
diff --git a/vm/mterp/x86-atom/OP_NEG_INT.S b/vm/mterp/x86-atom/OP_NEG_INT.S
index 6770216..68acb89 100644
--- a/vm/mterp/x86-atom/OP_NEG_INT.S
+++ b/vm/mterp/x86-atom/OP_NEG_INT.S
@@ -17,4 +17,4 @@
* File: OP_NEG_INT.S
*/
-%include "x86-atom/unop.S" {"instr":"neg %ecx"}
\ No newline at end of file
+%include "x86-atom/unop.S" {"instr":"neg %ecx"}
diff --git a/vm/mterp/x86-atom/OP_OR_INT.S b/vm/mterp/x86-atom/OP_OR_INT.S
index 59e39a3..0ece38c 100644
--- a/vm/mterp/x86-atom/OP_OR_INT.S
+++ b/vm/mterp/x86-atom/OP_OR_INT.S
@@ -17,4 +17,4 @@
* File: OP_OR_INT.S
*/
-%include "x86-atom/binop.S" {"instr":"or (rFP, %edx, 4), %ecx"}
\ No newline at end of file
+%include "x86-atom/binop.S" {"instr":"or %edx, %ecx"}
diff --git a/vm/mterp/x86-atom/OP_OR_INT_2ADDR.S b/vm/mterp/x86-atom/OP_OR_INT_2ADDR.S
index ddc20ed..693e099 100644
--- a/vm/mterp/x86-atom/OP_OR_INT_2ADDR.S
+++ b/vm/mterp/x86-atom/OP_OR_INT_2ADDR.S
@@ -17,4 +17,4 @@
* File: OP_OR_INT_2ADDR.S
*/
-%include "x86-atom/binop2addr.S" {"instr":"or %edx, (rFP, rINST, 4)"}
\ No newline at end of file
+%include "x86-atom/binop2addr.S" {"instr":"or %edx, %ecx"}
diff --git a/vm/mterp/x86-atom/OP_OR_INT_LIT16.S b/vm/mterp/x86-atom/OP_OR_INT_LIT16.S
index 3715781..5c63867 100644
--- a/vm/mterp/x86-atom/OP_OR_INT_LIT16.S
+++ b/vm/mterp/x86-atom/OP_OR_INT_LIT16.S
@@ -17,4 +17,4 @@
* File: OP_OR_INT_LIT16.S
*/
-%include "x86-atom/binopLit16.S" {"instr":"or %edx, %ecx"}
\ No newline at end of file
+%include "x86-atom/binopLit16.S" {"instr":"or %edx, %ecx"}
diff --git a/vm/mterp/x86-atom/OP_PACKED_SWITCH.S b/vm/mterp/x86-atom/OP_PACKED_SWITCH.S
index 7cb6d64..debac02 100644
--- a/vm/mterp/x86-atom/OP_PACKED_SWITCH.S
+++ b/vm/mterp/x86-atom/OP_PACKED_SWITCH.S
@@ -45,7 +45,7 @@
shl $$1, %eax # shift for byte offset
movl %eax, %edx # %edx<- offset
lea 8(%esp), %esp
- jle common_periodicChecks2 # do backward branch
+ jle common_periodicChecks_backwardBranch # do backward branch
jmp .L${opcode}_finish
%break
.L${opcode}_finish:
diff --git a/vm/mterp/x86-atom/OP_REM_INT.S b/vm/mterp/x86-atom/OP_REM_INT.S
index 2cd8a26..5f62d66 100644
--- a/vm/mterp/x86-atom/OP_REM_INT.S
+++ b/vm/mterp/x86-atom/OP_REM_INT.S
@@ -17,4 +17,4 @@
* File: OP_REM_INT.S
*/
-%include "x86-atom/binopD.S" {"div":"0"}
\ No newline at end of file
+%include "x86-atom/binopD.S" {"div":"0"}
diff --git a/vm/mterp/x86-atom/OP_RETURN_OBJECT.S b/vm/mterp/x86-atom/OP_RETURN_OBJECT.S
index 48308df..3b9c10c 100644
--- a/vm/mterp/x86-atom/OP_RETURN_OBJECT.S
+++ b/vm/mterp/x86-atom/OP_RETURN_OBJECT.S
@@ -17,4 +17,4 @@
* File: OP_RETURN_OBJECT.S
*/
-%include "x86-atom/OP_RETURN_COMMON.S"
\ No newline at end of file
+%include "x86-atom/OP_RETURN_COMMON.S"
diff --git a/vm/mterp/x86-atom/OP_RSUB_INT.S b/vm/mterp/x86-atom/OP_RSUB_INT.S
index 647a98e..87498f9 100644
--- a/vm/mterp/x86-atom/OP_RSUB_INT.S
+++ b/vm/mterp/x86-atom/OP_RSUB_INT.S
@@ -36,4 +36,4 @@
GET_VREG %ecx # %ecx<- vB
subl %ecx, %edx # %edx<- +CCCC sub vB
SET_VREG %edx, rINST # vA<- %edx; result
- FINISH 2 # jump to next instruction
\ No newline at end of file
+ FINISH 2 # jump to next instruction
diff --git a/vm/mterp/x86-atom/OP_SGET_OBJECT_VOLATILE.S b/vm/mterp/x86-atom/OP_SGET_OBJECT_VOLATILE.S
new file mode 100644
index 0000000..5f64fb5
--- /dev/null
+++ b/vm/mterp/x86-atom/OP_SGET_OBJECT_VOLATILE.S
@@ -0,0 +1 @@
+%include "x86/OP_SGET.S"
diff --git a/vm/mterp/x86-atom/OP_SGET_VOLATILE.S b/vm/mterp/x86-atom/OP_SGET_VOLATILE.S
new file mode 100644
index 0000000..5f64fb5
--- /dev/null
+++ b/vm/mterp/x86-atom/OP_SGET_VOLATILE.S
@@ -0,0 +1 @@
+%include "x86/OP_SGET.S"
diff --git a/vm/mterp/x86-atom/OP_SHL_INT.S b/vm/mterp/x86-atom/OP_SHL_INT.S
index ac0f0cc..13e4a11 100644
--- a/vm/mterp/x86-atom/OP_SHL_INT.S
+++ b/vm/mterp/x86-atom/OP_SHL_INT.S
@@ -17,4 +17,4 @@
* File: OP_SHL_INT.S
*/
-%include "x86-atom/binopS.S" {"instr":"sal %cl, %edx"}
\ No newline at end of file
+%include "x86-atom/binopS.S" {"instr":"sal %cl, %edx"}
diff --git a/vm/mterp/x86-atom/OP_SHL_INT_2ADDR.S b/vm/mterp/x86-atom/OP_SHL_INT_2ADDR.S
index 27be297..a27e09a 100644
--- a/vm/mterp/x86-atom/OP_SHL_INT_2ADDR.S
+++ b/vm/mterp/x86-atom/OP_SHL_INT_2ADDR.S
@@ -17,4 +17,4 @@
* File: OP_SHL_INT_2ADDR.S
*/
-%include "x86-atom/binopS2addr.S" {"instr":"sal %cl, %edx"}
\ No newline at end of file
+%include "x86-atom/binopS2addr.S" {"instr":"sal %cl, %edx"}
diff --git a/vm/mterp/x86-atom/OP_SHL_INT_LIT8.S b/vm/mterp/x86-atom/OP_SHL_INT_LIT8.S
index 6e0e4f8..5141e5c 100644
--- a/vm/mterp/x86-atom/OP_SHL_INT_LIT8.S
+++ b/vm/mterp/x86-atom/OP_SHL_INT_LIT8.S
@@ -17,4 +17,4 @@
* File: OP_SHL_INT_LIT8.S
*/
-%include "x86-atom/binopLit8S.S" {"instr":"sal %cl, %edx"}
\ No newline at end of file
+%include "x86-atom/binopLit8S.S" {"instr":"sal %cl, %edx"}
diff --git a/vm/mterp/x86-atom/OP_SHR_INT.S b/vm/mterp/x86-atom/OP_SHR_INT.S
index 2780f30..e7fd28b 100644
--- a/vm/mterp/x86-atom/OP_SHR_INT.S
+++ b/vm/mterp/x86-atom/OP_SHR_INT.S
@@ -17,4 +17,4 @@
* File: OP_SHR_INT.S
*/
-%include "x86-atom/binopS.S" {"instr":"sar %cl, %edx"}
\ No newline at end of file
+%include "x86-atom/binopS.S" {"instr":"sar %cl, %edx"}
diff --git a/vm/mterp/x86-atom/OP_SHR_INT_2ADDR.S b/vm/mterp/x86-atom/OP_SHR_INT_2ADDR.S
index 4229f7d..0d0b461 100644
--- a/vm/mterp/x86-atom/OP_SHR_INT_2ADDR.S
+++ b/vm/mterp/x86-atom/OP_SHR_INT_2ADDR.S
@@ -17,4 +17,4 @@
* File: OP_SHR_INT_2ADDR.S
*/
-%include "x86-atom/binopS2addr.S" {"instr":"sar %cl, %edx"}
\ No newline at end of file
+%include "x86-atom/binopS2addr.S" {"instr":"sar %cl, %edx"}
diff --git a/vm/mterp/x86-atom/OP_SHR_INT_LIT8.S b/vm/mterp/x86-atom/OP_SHR_INT_LIT8.S
index 2cf2e39..3467bf5 100644
--- a/vm/mterp/x86-atom/OP_SHR_INT_LIT8.S
+++ b/vm/mterp/x86-atom/OP_SHR_INT_LIT8.S
@@ -17,4 +17,4 @@
* File: OP_SHR_INT_LIT8.S
*/
-%include "x86-atom/binopLit8S.S" {"instr":"sar %cl, %edx"}
\ No newline at end of file
+%include "x86-atom/binopLit8S.S" {"instr":"sar %cl, %edx"}
diff --git a/vm/mterp/x86-atom/OP_SPUT_OBJECT.S b/vm/mterp/x86-atom/OP_SPUT_OBJECT.S
index 60afb97..88ebaf7 100644
--- a/vm/mterp/x86-atom/OP_SPUT_OBJECT.S
+++ b/vm/mterp/x86-atom/OP_SPUT_OBJECT.S
@@ -15,6 +15,56 @@
/*
* File: OP_SPUT_OBJECT.S
+ *
+ * Code: Generic 32-bit static field "put" operation. Uses no substitutions.
+ *
+ * For: sput-boolean, sput-byte, sput-char, sput-object, sput, sput-short
+ *
+ * Description: Perform the identified object static field operation
+ * with the identified static field; store the field value
+ * register.
+ *
+ * Format: AA|op BBBB (21c)
+ *
+ * Syntax: op vAA, string@BBBB
*/
-%include "x86-atom/OP_SPUT.S"
+ movl rGLUE, %edx # %edx<- pMterpGlue
+ movl offGlue_methodClassDex(%edx), %ecx # %ecx<- pDvmDex
+ FETCH 1, %eax # %eax<- BBBB
+ movl offDvmDex_pResFields(%ecx), %ecx # %ecx<- pResFields
+ cmp $$0, (%ecx, %eax, 4) # check for null ptr; resolved StaticField
+ movl (%ecx, %eax, 4), %ecx # %ecx<- resolved StaticField
+ je .L${opcode}_resolve
+ jmp .L${opcode}_finish
+%break
+
+.L${opcode}_resolve:
+ movl offGlue_method(%edx), %edx # %edx <- glue->method
+ EXPORT_PC # in case an exception is thrown
+ movl %eax, -4(%esp) # push parameter CCCC; field ref
+ movl offMethod_clazz(%edx), %edx # %edx<- method->clazz
+ movl %edx, -8(%esp) # push parameter method->clazz
+ lea -8(%esp), %esp
+ call dvmResolveStaticField # call: (const ClassObject* referrer, u4 ifieldIdx)
+ # return: StaticField*
+ cmp $$0, %eax # check if initalization failed
+ lea 8(%esp), %esp
+ je common_exceptionThrown # failed; handle exception
+ movl %eax, %ecx # %ecx<- result
+
+.L${opcode}_finish:
+ FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
+ GET_VREG rINST # rINST<- vAA
+
+
+ movl rINST, offStaticField_value(%ecx) # field value<- vAA
+ testl rINST, rINST # stored null object ptr?
+ je 1f
+ movl rGLUE, %edx # get glue
+ movl offField_clazz(%ecx), %ecx # ecx<- field->clazz
+ movl offGlue_cardTable(%edx), %edx # get card table base
+ shrl $$GC_CARD_SHIFT, %ecx # head to card number
+ movb %dl, (%edx, %ecx) # mark card
+1:
+ FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
diff --git a/vm/mterp/x86-atom/OP_SPUT_OBJECT_VOLATILE.S b/vm/mterp/x86-atom/OP_SPUT_OBJECT_VOLATILE.S
new file mode 100644
index 0000000..b368e31
--- /dev/null
+++ b/vm/mterp/x86-atom/OP_SPUT_OBJECT_VOLATILE.S
@@ -0,0 +1 @@
+%include "x86/OP_SPUT_OBJECT.S"
diff --git a/vm/mterp/x86-atom/OP_SPUT_VOLATILE.S b/vm/mterp/x86-atom/OP_SPUT_VOLATILE.S
new file mode 100644
index 0000000..7ee4140
--- /dev/null
+++ b/vm/mterp/x86-atom/OP_SPUT_VOLATILE.S
@@ -0,0 +1 @@
+%include "x86/OP_SPUT.S"
diff --git a/vm/mterp/x86-atom/OP_SUB_FLOAT.S b/vm/mterp/x86-atom/OP_SUB_FLOAT.S
index c41f75e..eb79d79 100644
--- a/vm/mterp/x86-atom/OP_SUB_FLOAT.S
+++ b/vm/mterp/x86-atom/OP_SUB_FLOAT.S
@@ -17,4 +17,4 @@
* File: OP_SUB_FLOAT.S
*/
-%include "x86-atom/binopF.S" {"instr":"subss %xmm1, %xmm0"}
\ No newline at end of file
+%include "x86-atom/binopF.S" {"instr":"subss %xmm1, %xmm0"}
diff --git a/vm/mterp/x86-atom/OP_SUB_FLOAT_2ADDR.S b/vm/mterp/x86-atom/OP_SUB_FLOAT_2ADDR.S
index dad1b7c..77f23f1 100644
--- a/vm/mterp/x86-atom/OP_SUB_FLOAT_2ADDR.S
+++ b/vm/mterp/x86-atom/OP_SUB_FLOAT_2ADDR.S
@@ -17,4 +17,4 @@
* File: OP_SUB_FLOAT_2ADDR.S
*/
-%include "x86-atom/binopF2addr.S" {"instr":"subss %xmm1, %xmm0"}
\ No newline at end of file
+%include "x86-atom/binopF2addr.S" {"instr":"subss %xmm1, %xmm0"}
diff --git a/vm/mterp/x86-atom/OP_SUB_INT.S b/vm/mterp/x86-atom/OP_SUB_INT.S
index be530aa..8d342cd 100644
--- a/vm/mterp/x86-atom/OP_SUB_INT.S
+++ b/vm/mterp/x86-atom/OP_SUB_INT.S
@@ -17,4 +17,4 @@
* File: OP_SUB_INT.S
*/
-%include "x86-atom/binop.S" {"instr":"subl (rFP, %edx, 4), %ecx"}
+%include "x86-atom/binop.S" {"instr":"subl %edx, %ecx"}
diff --git a/vm/mterp/x86-atom/OP_SUB_INT_2ADDR.S b/vm/mterp/x86-atom/OP_SUB_INT_2ADDR.S
index 0ecbb57..4d295a4 100644
--- a/vm/mterp/x86-atom/OP_SUB_INT_2ADDR.S
+++ b/vm/mterp/x86-atom/OP_SUB_INT_2ADDR.S
@@ -17,4 +17,4 @@
* File: OP_SUB_INT_2ADDR.S
*/
-%include "x86-atom/binop2addr.S" {"instr":"subl %edx, (rFP, rINST, 4)"}
\ No newline at end of file
+%include "x86-atom/binop2addr.S" {"instr":"subl %edx, %ecx"}
diff --git a/vm/mterp/x86-atom/OP_THROW.S b/vm/mterp/x86-atom/OP_THROW.S
index 85afa7a..120b1e9 100644
--- a/vm/mterp/x86-atom/OP_THROW.S
+++ b/vm/mterp/x86-atom/OP_THROW.S
@@ -28,6 +28,7 @@
*/
movl rGLUE, %eax # %eax<- pMterpGlue
+ EXPORT_PC # export the pc
GET_VREG rINST # rINST<- vAA
cmp $$0, rINST # check for null
movl offGlue_self(%eax), %ecx # %ecx<- glue->self
diff --git a/vm/mterp/x86-atom/OP_THROW_VERIFICATION_ERROR.S b/vm/mterp/x86-atom/OP_THROW_VERIFICATION_ERROR.S
index fcd42c7..f920b50 100644
--- a/vm/mterp/x86-atom/OP_THROW_VERIFICATION_ERROR.S
+++ b/vm/mterp/x86-atom/OP_THROW_VERIFICATION_ERROR.S
@@ -28,13 +28,13 @@
* Syntax: op vAA, ref@BBBB
*/
- movl rGLUE, %edx # %edx<- pMterpGlue
- movl offGlue_method(%edx), %ecx # %ecx<- glue->method
- EXPORT_PC # in case an exception is thrown
- FETCH 1, %eax # %eax<- BBBB
- movl %eax, -4(%esp) # push parameter BBBB; ref
- movl rINST, -8(%esp) # push parameter AA
- movl %ecx, -12(%esp) # push parameter glue->method
+ movl rGLUE, %edx # %edx<- pMterpGlue
+ movl offGlue_method(%edx), %ecx # %ecx<- glue->method
+ EXPORT_PC # in case an exception is thrown
+ FETCH 1, %eax # %eax<- BBBB
+ movl %eax, -4(%esp) # push parameter BBBB; ref
+ movl rINST, -8(%esp) # push parameter AA
+ movl %ecx, -12(%esp) # push parameter glue->method
lea -12(%esp), %esp
- call dvmThrowVerificationError # call: (const Method* method, int kind, int ref)
- jmp common_exceptionThrown # failed; handle exception
+ call dvmThrowVerificationError # call: (const Method* method, int kind, int ref)
+ jmp common_exceptionThrown # failed; handle exception
diff --git a/vm/mterp/x86-atom/OP_USHR_INT_LIT8.S b/vm/mterp/x86-atom/OP_USHR_INT_LIT8.S
index 38516c5..5a54df7 100644
--- a/vm/mterp/x86-atom/OP_USHR_INT_LIT8.S
+++ b/vm/mterp/x86-atom/OP_USHR_INT_LIT8.S
@@ -17,4 +17,4 @@
* File: OP_USHR_INT_LIT8.S
*/
-%include "x86-atom/binopLit8S.S" {"instr":"shr %cl, %edx"}
\ No newline at end of file
+%include "x86-atom/binopLit8S.S" {"instr":"shr %cl, %edx"}
diff --git a/vm/mterp/x86-atom/OP_XOR_INT.S b/vm/mterp/x86-atom/OP_XOR_INT.S
index 6c8e26d..d36b83f 100644
--- a/vm/mterp/x86-atom/OP_XOR_INT.S
+++ b/vm/mterp/x86-atom/OP_XOR_INT.S
@@ -17,4 +17,4 @@
* File: OP_XOR_INT.S
*/
-%include "x86-atom/binop.S" {"instr":"xor (rFP, %edx, 4), %ecx"}
\ No newline at end of file
+%include "x86-atom/binop.S" {"instr":"xor %edx, %ecx"}
diff --git a/vm/mterp/x86-atom/OP_XOR_INT_2ADDR.S b/vm/mterp/x86-atom/OP_XOR_INT_2ADDR.S
index d2b8338..0bab865 100644
--- a/vm/mterp/x86-atom/OP_XOR_INT_2ADDR.S
+++ b/vm/mterp/x86-atom/OP_XOR_INT_2ADDR.S
@@ -17,4 +17,4 @@
* File: OP_XOR_INT_2ADDR.S
*/
-%include "x86-atom/binop2addr.S" {"instr":"xor %edx, (rFP, rINST, 4)"}
\ No newline at end of file
+%include "x86-atom/binop2addr.S" {"instr":"xor %edx, %ecx"}
diff --git a/vm/mterp/x86-atom/OP_XOR_INT_LIT16.S b/vm/mterp/x86-atom/OP_XOR_INT_LIT16.S
index bb841cd..a26bcc5 100644
--- a/vm/mterp/x86-atom/OP_XOR_INT_LIT16.S
+++ b/vm/mterp/x86-atom/OP_XOR_INT_LIT16.S
@@ -17,4 +17,4 @@
* File: OP_XOR_INT_LIT16.S
*/
-%include "x86-atom/binopLit16.S" {"instr":"xor %edx, %ecx"}
\ No newline at end of file
+%include "x86-atom/binopLit16.S" {"instr":"xor %edx, %ecx"}
diff --git a/vm/mterp/x86-atom/TODO.txt b/vm/mterp/x86-atom/TODO.txt
index c2e9fc4..72d8855 100644
--- a/vm/mterp/x86-atom/TODO.txt
+++ b/vm/mterp/x86-atom/TODO.txt
@@ -1,17 +1,4 @@
Items requiring attention:
-(hi) Add gc card marking to aput/iput/sput/new_filled_array
-(hi) Correct stack overflow handling (dvmCleanupStackOverflow takes an
- additional argument now)
-(hi) "debugger active" test in common_periodicChecks must handle
- the case where glue->pDebuggerActive is a NULL pointer (used to
- skip a memory load when debugger support is completely disabled)
-(hi) WITH_DEBUGGER and WITH_PROFILER are no longer defined (but are
- assumed to be enabled)
-
-(md) Correct OP_MONITOR_EXIT (need to adjust PC before throw)
-(md) OP_THROW needs to export the PC
-
(lo) Implement OP_BREAKPOINT
-(lo) Implement OP_EXECUTE_INLINE_RANGE
(lo) Implement OP_*_VOLATILE (12 instructions)
diff --git a/vm/mterp/x86-atom/bincmp.S b/vm/mterp/x86-atom/bincmp.S
index b56a0e1..a8fbed5 100644
--- a/vm/mterp/x86-atom/bincmp.S
+++ b/vm/mterp/x86-atom/bincmp.S
@@ -39,6 +39,6 @@
# comparison is true
FETCHs 1, %edx # %edx<- +CCCC, Branch offset
sal $$1, %edx
- js common_periodicChecks2
+ js common_periodicChecks_backwardBranch
1:
FINISH_RB %edx, %ecx # jump to next instruction
diff --git a/vm/mterp/x86-atom/binop.S b/vm/mterp/x86-atom/binop.S
index 0343190..1706b72 100644
--- a/vm/mterp/x86-atom/binop.S
+++ b/vm/mterp/x86-atom/binop.S
@@ -29,14 +29,11 @@
* Syntax: op vAA, vBB, vCC
*/
-
-
FETCH_BB 1, %ecx # %ecx<- BB
- OLD_JMP_1 2, %eax
- OLD_JMP_2 %eax
FETCH_CC 1, %edx # %edx<- CC
- OLD_JMP_3 2
+ FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
GET_VREG %ecx # %ecx<- vBB
+ GET_VREG %edx # %edx<- vCC
$instr # %ecx<- vBB op vCC
SET_VREG %ecx, rINST # vAA<- %ecx; result
- OLD_JMP_4 %eax
+ FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
diff --git a/vm/mterp/x86-atom/binop2addr.S b/vm/mterp/x86-atom/binop2addr.S
index af135a7..b26b25a 100644
--- a/vm/mterp/x86-atom/binop2addr.S
+++ b/vm/mterp/x86-atom/binop2addr.S
@@ -33,12 +33,13 @@
movl rINST, %edx # %edx<- BA
shr $$4, %edx # %edx<- B
- #FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
- OLD_JMP_1 1, %eax
- andl $$15, rINST # rINST<- A
- OLD_JMP_2 %eax
+ andl $$15, rINST # rINST<- A
+ movl rINST, %ecx # %ecx<- A
+ FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
GET_VREG %edx # %edx<- vB
- OLD_JMP_3 1
- $instr # %ecx<- vA op vB
- #FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
- OLD_JMP_4 %eax
+ GET_VREG %ecx # %ecx<- vA
+ $instr # %ecx<- vA op vB
+ SET_VREG %ecx, rINST # vAA<- %ecx; result
+ FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
+
+
diff --git a/vm/mterp/x86-atom/binopD.S b/vm/mterp/x86-atom/binopD.S
index a3565f3..20a2e9a 100644
--- a/vm/mterp/x86-atom/binopD.S
+++ b/vm/mterp/x86-atom/binopD.S
@@ -31,35 +31,31 @@
%default {"div":"1"}
-
- FETCH_CC 1, %ecx # %ecx<- CC
FETCH_BB 1, %eax # %eax<- BB
- GET_VREG %ecx # %ecx<- vCC
- testl %ecx, %ecx
+ FETCH_CC 1, %ecx # %ecx<- CC
GET_VREG %eax # %eax<- vBB
+ GET_VREG %ecx # %ecx<- vCC
+ cmp $$0, %ecx # check for divide by zero
je common_errDivideByZero # handle divide by zero
cmpl $$-1, %ecx # handle -1 special case divide error
- jnz .L${opcode}_continue
+ jne .L${opcode}_noerror
cmpl $$0x80000000,%eax # handle min int special case divide error
je .L${opcode}_break
-.L${opcode}_continue:
+.L${opcode}_noerror:
cdq # sign-extend %eax to %edx
idiv %ecx # divide %edx:%eax by %ecx
.if $div
- FFETCH_ADV 2 %edx
SET_VREG %eax rINST # vAA<- %eax (quotient)
- FGETOP_JMP 2 %edx
.else
- FFETCH_ADV 2 %eax
- SET_VREG %edx rINST # vAA<- %edx (remainder)
- FGETOP_JMP 2 %eax
+ SET_VREG %edx rINST # vAA<- %edx (remainder)
.endif
+ jmp .L${opcode}_break2
%break
.L${opcode}_break:
- FFETCH_ADV 2 %eax
.if $div
movl $$0x80000000, (rFP, rINST, 4) # vAA<- min int
.else
movl $$0, (rFP, rINST, 4) # vAA<- 0
.endif
- FGETOP_JMP 2 %eax
\ No newline at end of file
+.L${opcode}_break2:
+ FINISH 2 # jump to next instruction
diff --git a/vm/mterp/x86-atom/binopD2addr.S b/vm/mterp/x86-atom/binopD2addr.S
index a4fcf65..392b46b 100644
--- a/vm/mterp/x86-atom/binopD2addr.S
+++ b/vm/mterp/x86-atom/binopD2addr.S
@@ -32,37 +32,37 @@
%default {"div":"1"}
movl rINST, %ecx # %ecx<- BA
- shr $$4, %ecx # %ecx<- B
andl $$15, rINST # rINST<- A, to be used as dest
movl rINST, %eax # %eax<- A
- GET_VREG %ecx # %edx<- vB
- testl %ecx, %ecx # check for divide by zero
+ shr $$4, %ecx # %ecx<- B
GET_VREG %eax # %eax<- vA
- jz common_errDivideByZero # handle divide by zero
+ GET_VREG %ecx # %edx<- vB
+ cmp $$0, %ecx # check for divide by zero
+ je common_errDivideByZero # handle divide by zero
cmpl $$-1, %ecx # handle -1 special case divide error
- jnz .L${opcode}_continue
- cmpl $$0x80000000, %eax # handle min int special case divide error
+ jne .L${opcode}_noerror
+ cmpl $$0x80000000,%eax # handle min int special case divide error
je .L${opcode}_break
-
-.L${opcode}_continue:
+.L${opcode}_noerror:
cdq # sign-extend %eax to %edx
idiv %ecx # divide %edx:%eax by %ecx
.if $div
- FFETCH_ADV 1, %edx # %ecx<- next instruction hi; fetch, advance
SET_VREG %eax rINST # vAA<- %eax (quotient)
- FGETOP_JMP 1, %edx # jump to next instruction; getop, jmp
.else
- FFETCH_ADV 1, %eax # %ecx<- next instruction hi; fetch, advance
SET_VREG %edx rINST # vAA<- %edx (remainder)
- FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
.endif
+ jmp .L${opcode}_break2
+ #FFETCH_ADV 1, %edx # %ecx<- next instruction hi; fetch, advance
+ #FGETOP_JMP 1, %edx # jump to next instruction; getop, jmp
%break
.L${opcode}_break:
- FFETCH_ADV 1, %edx # %ecx<- next instruction hi; fetch, advance
.if $div
movl $$0x80000000, (rFP, rINST, 4) # vAA<- min int
.else
movl $$0, (rFP, rINST, 4) # vAA<- 0
.endif
+.L${opcode}_break2:
+ FFETCH_ADV 1, %edx # %ecx<- next instruction hi; fetch, advance
FGETOP_JMP 1, %edx # jump to next instruction; getop, jmp
+
diff --git a/vm/mterp/x86-atom/binopDLit16.S b/vm/mterp/x86-atom/binopDLit16.S
index 86bb937..3e67d0a 100644
--- a/vm/mterp/x86-atom/binopDLit16.S
+++ b/vm/mterp/x86-atom/binopDLit16.S
@@ -35,37 +35,32 @@
movl rINST, %eax # %eax<- BA
shr $$4, %eax # %eax<- B
FETCHs 1, %ecx # %ecx<- +CCCC, sign-extended literal
- testl %ecx, %ecx # check for divide by zero
+ cmp $$0, %ecx # check for divide by zero
GET_VREG %eax # %eax<- vB
je common_errDivideByZero # handle divide by zero
- addl $$4, rPC # update PC
andl $$15, rINST # rINST<- A
cmpl $$-1, %ecx # handle -1 special case divide error
- jnz .L${opcode}_continue
+ jne .L${opcode}_noerror
cmpl $$0x80000000,%eax # handle min int special case divide error
- je .L${opcode}_break
-.L${opcode}_continue:
+ je .L${opcode}_break
+.L${opcode}_noerror:
cdq # sign-extend %eax to %edx
idiv %ecx # divide %edx:%eax by %ecx
+ #FFETCH_ADV 2, %ecx # %ecx<- next instruction hi; fetch, advance
.if $div
- movzbl (rPC), %edx
- SET_VREG %eax, rINST # vA<- %eax (quotient)
- movzbl 1(rPC), rINST
- jmp *dvmAsmInstructionJmpTable(, %edx, 4)
+ SET_VREG %eax rINST # vA<- %eax (quotient)
.else
- movzbl (rPC), %eax
- SET_VREG %edx, rINST # vA<- %edx (remainder)
- movzbl 1(rPC), rINST
- jmp *dvmAsmInstructionJmpTable(, %eax, 4)
+ SET_VREG %edx rINST # vA<- %edx (remainder)
.endif
+ jmp .L${opcode}_break2
%break
.L${opcode}_break:
- movzbl (rPC), %edx
.if $div
movl $$0x80000000, (rFP, rINST, 4) # vAA<- min int
.else
movl $$0, (rFP, rINST, 4) # vAA<- 0
.endif
- movzbl 1(rPC), rINST
- jmp *dvmAsmInstructionJmpTable(, %edx, 4)
+.L${opcode}_break2:
+
+ FINISH 2 # jump to next instruction
diff --git a/vm/mterp/x86-atom/binopDLit8.S b/vm/mterp/x86-atom/binopDLit8.S
index 295a770..f197714 100644
--- a/vm/mterp/x86-atom/binopDLit8.S
+++ b/vm/mterp/x86-atom/binopDLit8.S
@@ -32,37 +32,34 @@
%default {"div":"1"}
- FETCH_CCs 1, %ecx # %ecx<- +CC, sign-extended literal
- testl %ecx, %ecx # handle -1 special case divide error
FETCH_BB 1, %eax # %eax<- BB
- jz common_errDivideByZero # handle divide by zero
- addl $$4, rPC # update PC
- cmpl $$-1, %ecx
+ FETCH_CCs 1, %ecx # %ecx<- +CC, sign-extended literal
+ cmp $$0, %ecx # check for divide by zero
GET_VREG %eax # %eax<- vBB
- jnz .L${opcode}_continue
+ je common_errDivideByZero # handle divide by zero
+
+ cmpl $$-1, %ecx # handle -1 special case divide error
+ jne .L${opcode}_noerror
cmpl $$0x80000000,%eax # handle min int special case divide error
- je .L${opcode}_break
-.L${opcode}_continue:
+ je .L${opcode}_break
+.L${opcode}_noerror:
cdq # sign-extend %eax to %edx
idiv %ecx # divide %edx:%eax by %ecx
+ #FFETCH_ADV 2, %ecx # %ecx<- next instruction hi; fetch, advance
.if $div
- movzbl (rPC), %edx
- SET_VREG %eax, rINST # vA<- %eax (quotient)
- movzbl 1(rPC), rINST
- jmp *dvmAsmInstructionJmpTable(, %edx, 4)
+ SET_VREG %eax rINST # vAA<- %eax (quotient)
.else
- movzbl (rPC), %eax
- SET_VREG %edx, rINST # vA<- %edx (remainder)
- movzbl 1(rPC), rINST
- jmp *dvmAsmInstructionJmpTable(, %eax, 4)
+ SET_VREG %edx rINST # vAA<- %edx (remainder)
.endif
+ jmp .L${opcode}_break2
%break
.L${opcode}_break:
- movzbl (rPC), %edx
.if $div
movl $$0x80000000, (rFP, rINST, 4) # vAA<- min int
.else
movl $$0, (rFP, rINST, 4) # vAA<- 0
.endif
- movzbl 1(rPC), rINST
- jmp *dvmAsmInstructionJmpTable(, %edx, 4)
+
+.L${opcode}_break2:
+ FINISH 2 # jump to next instruction
+ #FGETOP_JMP 2, %ecx # jump to next instruction; getop, jmp
diff --git a/vm/mterp/x86-atom/binopDivRemLong2Addr.S b/vm/mterp/x86-atom/binopDivRemLong2Addr.S
index d50f776..aa427de 100644
--- a/vm/mterp/x86-atom/binopDivRemLong2Addr.S
+++ b/vm/mterp/x86-atom/binopDivRemLong2Addr.S
@@ -51,4 +51,4 @@
movl %eax, (rFP, rINST, 4) # vA<- return low
movl %edx, 4(rFP, rINST, 4) # vA<- return high
FFETCH_ADV 1, %ecx # %ecx<- next instruction hi; fetch, advance
- FGETOP_JMP 1, %ecx # jump to next instruction; getop, jmp
\ No newline at end of file
+ FGETOP_JMP 1, %ecx # jump to next instruction; getop, jmp
diff --git a/vm/mterp/x86-atom/binopF.S b/vm/mterp/x86-atom/binopF.S
index a2b408f..0c07b97 100644
--- a/vm/mterp/x86-atom/binopF.S
+++ b/vm/mterp/x86-atom/binopF.S
@@ -36,4 +36,4 @@
movss (rFP, %edx, 4), %xmm1 # %xmm1<- vCC
$instr # %xmm0<- vBB op vCC
movss %xmm0, (rFP, rINST, 4) # vAA<- %xmm0; result
- FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
\ No newline at end of file
+ FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
diff --git a/vm/mterp/x86-atom/binopF2addr.S b/vm/mterp/x86-atom/binopF2addr.S
index df1fdf7..135ca0c 100644
--- a/vm/mterp/x86-atom/binopF2addr.S
+++ b/vm/mterp/x86-atom/binopF2addr.S
@@ -38,4 +38,4 @@
movss (rFP, rINST, 4), %xmm1 # %xmm1<- vB
$instr # %xmm0<- vA op vB
movss %xmm0, (rFP, %ecx, 4) # vA<- %xmm0; result
- FGETOP_JMP 1, %edx # jump to next instruction; getop, jmp
\ No newline at end of file
+ FGETOP_JMP 1, %edx # jump to next instruction; getop, jmp
diff --git a/vm/mterp/x86-atom/binopLit16.S b/vm/mterp/x86-atom/binopLit16.S
index 8b1cbd1..4972b4d 100644
--- a/vm/mterp/x86-atom/binopLit16.S
+++ b/vm/mterp/x86-atom/binopLit16.S
@@ -40,4 +40,4 @@
GET_VREG %ecx # %ecx<- vB
$instr # %ecx<- vA op vB
SET_VREG %ecx, rINST # vA<- %ecx; result
- FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
\ No newline at end of file
+ FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
diff --git a/vm/mterp/x86-atom/binopLit8.S b/vm/mterp/x86-atom/binopLit8.S
index f6c4a6b..239e443 100644
--- a/vm/mterp/x86-atom/binopLit8.S
+++ b/vm/mterp/x86-atom/binopLit8.S
@@ -37,4 +37,4 @@
GET_VREG %ecx # %ecx<- vBB
$instr # %ecx<- vBB op +CC
SET_VREG %ecx, rINST # vAA<- %ecx; result
- FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
\ No newline at end of file
+ FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
diff --git a/vm/mterp/x86-atom/binopLit8S.S b/vm/mterp/x86-atom/binopLit8S.S
index c400063..c0360aa 100644
--- a/vm/mterp/x86-atom/binopLit8S.S
+++ b/vm/mterp/x86-atom/binopLit8S.S
@@ -37,4 +37,4 @@
GET_VREG %edx # %edx<- vBB
$instr # %edx<- vBB op +CC
SET_VREG %edx, rINST # vAA<- %edx; result
- FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
\ No newline at end of file
+ FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
diff --git a/vm/mterp/x86-atom/binopS.S b/vm/mterp/x86-atom/binopS.S
index b9c3e26..b09f5c2 100644
--- a/vm/mterp/x86-atom/binopS.S
+++ b/vm/mterp/x86-atom/binopS.S
@@ -29,12 +29,11 @@
* Syntax: op vAA, vBB, vCC
*/
- FETCH_CC 1, %ecx # %ecx<- CC
FETCH_BB 1, %edx # %edx<- BB
+ FETCH_CC 1, %ecx # %ecx<- CC
FFETCH_ADV 2, %eax # %eax<- next instruction hi; fetch, advance
- addl $$4, rPC # update PC
- GET_VREG %ecx # %ecx<- vCC
GET_VREG %edx # %edx<- vBB
+ GET_VREG %ecx # %ecx<- vCC
$instr # %edx<- vBB op +CC
SET_VREG %edx, rINST # vAA<- %edx; result
- FGETOP_JMP2 %eax # jump to next instruction; getop, jmp
\ No newline at end of file
+ FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
diff --git a/vm/mterp/x86-atom/binopS2addr.S b/vm/mterp/x86-atom/binopS2addr.S
index 453f38f..0c3c29a 100644
--- a/vm/mterp/x86-atom/binopS2addr.S
+++ b/vm/mterp/x86-atom/binopS2addr.S
@@ -32,12 +32,11 @@
movl rINST, %ecx # %ecx<- BA
shr $$4, %ecx # %ecx<- B
- FFETCH_ADV 1, %eax # %ecx<- next i nstruction hi; fetch, advance
andl $$15, rINST # rINST<- A
- addl $$2, rPC # update PC
movl rINST, %edx # %edx<- A
+ FFETCH_ADV 1, %eax # %ecx<- next instruction hi; fetch, advance
GET_VREG %ecx # %ecx<- vB
GET_VREG %edx # %edx<- vA
$instr # %edx<- vA op vB
SET_VREG %edx, rINST # vAA<- %edx; result
- FGETOP_JMP2 %eax # jump to next instruction; getop, jmp
\ No newline at end of file
+ FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
diff --git a/vm/mterp/x86-atom/binopWide.S b/vm/mterp/x86-atom/binopWide.S
index 3b27f60..3cd3e52 100644
--- a/vm/mterp/x86-atom/binopWide.S
+++ b/vm/mterp/x86-atom/binopWide.S
@@ -37,4 +37,4 @@
movq (rFP, %edx, 4), %xmm1 # %xmm1<- vCC
$instr # %xmm0<- vBB op vCC
movq %xmm0, (rFP, rINST, 4) # vAA<- %ecx
- FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
\ No newline at end of file
+ FGETOP_JMP 2, %eax # jump to next instruction; getop, jmp
diff --git a/vm/mterp/x86-atom/binopWide2addr.S b/vm/mterp/x86-atom/binopWide2addr.S
index a051c2b..f9aa29c 100644
--- a/vm/mterp/x86-atom/binopWide2addr.S
+++ b/vm/mterp/x86-atom/binopWide2addr.S
@@ -34,10 +34,8 @@
movl rINST, %edx # %edx<- BA
shr $$4, rINST # rINST<- B
andl $$15, %edx # %edx<- A
- FFETCH_ADV 1, %eax # %eax<- next instruction hi; fetch, advance
movq (rFP, rINST, 4), %xmm1 # %xmm1<- vB
movq (rFP, %edx, 4), %xmm0 # %xmm0<- vA
$instr # %xmm0<- vA op vB
movq %xmm0, (rFP, %edx, 4) # vA<- %xmm0; result
- #FINISH 1 # jump to next instruction
- FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
\ No newline at end of file
+ FINISH 1 # jump to next instruction
diff --git a/vm/mterp/x86-atom/entry.S b/vm/mterp/x86-atom/entry.S
index 8a3c9c1..9d7f61e 100644
--- a/vm/mterp/x86-atom/entry.S
+++ b/vm/mterp/x86-atom/entry.S
@@ -46,13 +46,6 @@
*/
.macro MTERP_EXIT
- #lea 40(%ebp), %esp # correct stack pointer
- #movl 24(%ebp), %edi # restore %edi
- #movl 28(%ebp), %esi # restore %esi
- #movl 32(%ebp), %ebx # restore %ebx
- #movl 36(%ebp), %ebp # restore caller base pointer
- #ret # return
-
lea 40(%esp), %esp # correct stack pointer
movl -16(%esp), %edi # restore %edi
movl -12(%esp), %esi # restore %esi
@@ -360,11 +353,11 @@
.long .L_OP_SHL_INT_LIT8
.long .L_OP_SHR_INT_LIT8
.long .L_OP_USHR_INT_LIT8
-.long .L_OP_UNUSED_E3
-.long .L_OP_UNUSED_E4
-.long .L_OP_UNUSED_E5
-.long .L_OP_UNUSED_E6
-.long .L_OP_UNUSED_E7
+.long .L_OP_IGET_VOLATILE
+.long .L_OP_IPUT_VOLATILE
+.long .L_OP_SGET_VOLATILE
+.long .L_OP_SPUT_VOLATILE
+.long .L_OP_IGET_OBJECT_VOLATILE
.long .L_OP_IGET_WIDE_VOLATILE
.long .L_OP_IPUT_WIDE_VOLATILE
.long .L_OP_SGET_WIDE_VOLATILE
@@ -385,7 +378,7 @@
.long .L_OP_INVOKE_VIRTUAL_QUICK_RANGE
.long .L_OP_INVOKE_SUPER_QUICK
.long .L_OP_INVOKE_SUPER_QUICK_RANGE
-.long .L_OP_UNUSED_FC
-.long .L_OP_UNUSED_FD
-.long .L_OP_UNUSED_FE
+.long .L_OP_IPUT_OBJECT_VOLATILE
+.long .L_OP_SGET_OBJECT_VOLATILE
+.long .L_OP_SPUT_OBJECT_VOLATILE
.long .L_OP_UNUSED_FF
diff --git a/vm/mterp/x86-atom/footer.S b/vm/mterp/x86-atom/footer.S
index a3b374f..cb9970d 100644
--- a/vm/mterp/x86-atom/footer.S
+++ b/vm/mterp/x86-atom/footer.S
@@ -34,26 +34,22 @@
movl rGLUE, %edx # %edx<- pMterpGlue
movl %ebx, -4(%esp) # save %ebx to the stack
movl offGlue_pSelfSuspendCount(%edx), %ebx # %ebx<- pSuspendCount (int)
-#if defined(WITH_DEBUGGER)
+4:
movl offGlue_pDebuggerActive(%edx), %eax # %eax<- pDebuggerActive
- movl (%eax), %eax # %eax<- get debuggerActive (boolean)
- and $$7, %eax # %eax<- mask for boolean (just how many bits does it take?)
-#endif
+ testl %eax, %eax
+ je 5f
+ movzbl (%eax), %eax # %eax<- get debuggerActive (boolean)
+5:
cmp $$0, (%ebx) # check if suspend is pending
jne 2f # handle suspend
-#if defined(WITH_DEBUGGER) || defined(WITH_PROFILER)
-#if defined(WITH_PROFILER)
movl offGlue_pActiveProfilers(%edx), %ebx # %ebx<- activeProfilers (int)
- or (%ebx), %eax # %eax<- merge activeProfilers and debuggerActive
-#else
- cmp $$0, %eax # check for debuggerActive
-#endif
- jne 3f # debugger or profiler active; switch interp
-#endif
+ orl (%ebx), %eax # %eax<- merge activeProfilers and debuggerActive
movl -8(%esp), %edx # %edx<- restore %edx
+ jne 3f # debugger or profiler active; switch interp
movl -4(%esp), %ebx # %ebx<- restore %ebx
ret # return
2: # check suspended
+ EXPORT_PC
movl offGlue_self(%edx), %eax # %eax<- glue->self
movl %eax, -12(%esp) # push parameter boolean
lea -12(%esp), %esp
@@ -62,11 +58,12 @@
movl 4(%esp), %edx # %edx<- restore %edx
movl 8(%esp), %ebx # %ebx<- restore %ebx
lea 12(%esp), %esp
- ret # return
+ ret
3: # debugger/profiler enabled, bail out
- add -8(%esp), rPC # rPC<- pc adjustments
- movl %ecx, offGlue_entryPoint(%edx) # glue->entryPoint<- reentry type
- movl $$1, %edx # switch to interp == true
+ leal (rPC, %edx, 2), rPC # adjust pc to show target
+ movl rGLUE, %ecx # %ecx<- pMterpGlue
+ movb $$kInterpEntryInstr, offGlue_entryPoint(%ecx)
+ movl $$1, %edx # switch interpreter
jmp common_gotoBail # bail
/*
@@ -78,25 +75,21 @@
* %edx is PC adjustment in bytes
*/
-common_periodicChecks2:
+common_periodicChecks_backwardBranch:
+ EXPORT_PC
movl rGLUE, %ecx # %ecx<- pMterpGlue
movl offGlue_pSelfSuspendCount(%ecx), rINST # %ebx<- pSuspendCount (int)
-#if defined(WITH_DEBUGGER)
- movl offGlue_pDebuggerActive(%ecx), %eax # %eax<- pDebuggerActive
- movl (%eax), %eax # %eax<- get debuggerActive (boolean)
- and $$7, %eax # %eax<- mask for boolean (just how many bits does it take?)
-#endif
+4:
+ movl offGlue_pDebuggerActive(%ecx), %eax # %eax<- pDebuggerActive
+ testl %eax, %eax # test for NULL pointer
+ je 5f
+ movzbl (%eax), %eax # %eax<- get debuggerActive count
+5:
cmp $$0, (rINST) # check if suspend is pending
jne 2f # handle suspend
-#if defined(WITH_DEBUGGER) || defined(WITH_PROFILER)
-#if defined(WITH_PROFILER)
movl offGlue_pActiveProfilers(%ecx), rINST # %edx<- activeProfilers (int)
- or (rINST), %eax # %eax<- merge activeProfilers and debuggerActive
-#else
- cmp $$0, %eax # check for debuggerActive
-#endif
+ orl (rINST), %eax # %eax<- merge activeProfilers and debuggerActive
jne 3f # debugger or profiler active; switch interp
-#endif
FINISH_RB %edx, %ecx # jump to next instruction
2: # check suspended
movl offGlue_self(%ecx), %eax# %eax<- glue->self
@@ -107,15 +100,13 @@
# return: bool
movl rINST, %edx # %edx<- restore %edx
lea 12(%esp), %esp
- FINISH_RB %edx, %ecx # jump to next instruction
-
+ FINISH_RB %edx, %ecx
3: # debugger/profiler enabled, bail out
- add -8(%esp), rPC # rPC<- pc adjustments
- movl $$kInterpEntryInstr, offGlue_entryPoint(%ecx) # glue->entryPoint<- reentry type
- movl $$1, %edx # switch to interp<- true
+ leal (rPC, %edx, 2), rPC # adjust pc to show target
+ movb $$kInterpEntryInstr, offGlue_entryPoint(%ecx)
+ movl $$1, %edx # switch interpreter
jmp common_gotoBail # bail
-
/*
* The equivalent of "goto bail", this calls through the "bail handler".
* State registers will be saved to the "glue" area before bailing.
@@ -333,13 +324,13 @@
jne common_exceptionThrown # handle exception
FGETOP_JMP 3, %edx # jump to next instruction; getop, jmp
-.LstackOverflow: # %ecx=methodToCall
- movl %ecx, -4(%esp) # push parameter method to call
+.LstackOverflow:
+ movl %ecx, -4(%esp) # push method to call
movl rGLUE, %ecx # %ecx<- pMterpGlue
movl offGlue_self(%ecx), %ecx # %ecx<- glue->self
movl %ecx, -8(%esp) # push parameter self
lea -8(%esp), %esp
- call dvmHandleStackOverflow # call: (Thread* self, Method* method)
+ call dvmHandleStackOverflow # call: (Thread* self, Method *meth)
# return: void
lea 8(%esp), %esp
jmp common_exceptionThrown # handle exception
@@ -361,22 +352,15 @@
movl rGLUE, rINST # %ecx<- pMterpGlue
movl offGlue_pSelfSuspendCount(rINST), %edx # %ebx<- pSuspendCount (int)
-#if defined(WITH_DEBUGGER)
movl offGlue_pDebuggerActive(rINST), %eax # %eax<- pDebuggerActive
movl (%eax), %eax # %eax<- get debuggerActive (boolean)
and $$7, %eax # %eax<- mask for boolean (just how many bits does it take?)
-#endif
cmp $$0, (%edx) # check if suspend is pending
jne 2f # handle suspend
-#if defined(WITH_DEBUGGER) || defined(WITH_PROFILER)
-#if defined(WITH_PROFILER)
movl offGlue_pActiveProfilers(rINST), %edx # %edx<- activeProfilers (int)
or (%edx), %eax # %eax<- merge activeProfilers and debuggerActive
-#else
cmp $$0, %eax # check for debuggerActive
-#endif
jne 3f # debugger or profiler active; switch interp
-#endif
jmp 4f
2: # check suspended
movl offGlue_self(rINST), %eax# %eax<- glue->self
@@ -564,7 +548,7 @@
jmp .LdeadFood
.LdeadFood:
-.word 0xdeadf00d
+.int 0xdeadf00d
/*
* Invalid array index.
diff --git a/vm/mterp/x86-atom/header.S b/vm/mterp/x86-atom/header.S
index 4c7c048..28c19d6 100644
--- a/vm/mterp/x86-atom/header.S
+++ b/vm/mterp/x86-atom/header.S
@@ -288,44 +288,6 @@
jmp *dvmAsmInstructionJmpTable(,\_rFinish, 4)
.endm
- .macro FGETOP_JMP2 _rFinish
- movzbl 1(rPC), rINST
- jmp *dvmAsmInstructionJmpTable(,\_rFinish, 4)
- .endm
-
- .macro OLD_JMP_1 _count _rFinish
- movzbl (\_count*2)(rPC), \_rFinish
- shl $$${handler_size_bits}, \_rFinish
- .endm
-
- .macro OLD_JMP_2 _rFinish
- addl $$dvmAsmInstructionStart,\_rFinish
- .endm
-
- .macro OLD_JMP_3 _count
- addl $$(\_count*2), rPC
- .endm
-
- .macro OLD_JMP_4 _rFinish
- movzbl 1(rPC), rINST
- jmp *\_rFinish
- .endm
-
- .macro OLD_JMP_A_1 _reg _rFinish
- movzbl (rPC, \_reg), \_rFinish
- shl $$${handler_size_bits}, \_rFinish
- .endm
-
- .macro OLD_JMP_A_2 _rFinish
- addl $$dvmAsmInstructionStart,\_rFinish
- .endm
-
- .macro OLD_JMP_A_3 _reg _rFinish
- addl \_reg, rPC
- movzbl 1(rPC, \_reg), rINST
- jmp *\_rFinish
- .endm
-
/*
* Macro pair attempts to speed up FETCH_INST, GET_INST_OPCODE and GOTO_OPCODE
* by using a jump table. _rFinish and _reg should must be the same register for
@@ -468,4 +430,4 @@
.long 0x80000000
.LintMax:
-.long 0x7FFFFFFF
\ No newline at end of file
+.long 0x7FFFFFFF
diff --git a/vm/mterp/x86-atom/unop.S b/vm/mterp/x86-atom/unop.S
index 09af3d0..00f9f8d 100644
--- a/vm/mterp/x86-atom/unop.S
+++ b/vm/mterp/x86-atom/unop.S
@@ -40,4 +40,4 @@
$preinstr # do operation part 1
$instr # do operation part 2
SET_VREG %ecx, rINST # vA<- result
- FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
\ No newline at end of file
+ FGETOP_JMP 1, %eax # jump to next instruction; getop, jmp
diff --git a/vm/mterp/x86-atom/zcmp.S b/vm/mterp/x86-atom/zcmp.S
index f93566e..6614dba 100644
--- a/vm/mterp/x86-atom/zcmp.S
+++ b/vm/mterp/x86-atom/zcmp.S
@@ -38,7 +38,7 @@
* Inline common_backwardBranch
*/
- js common_periodicChecks2 # jump on backwards branch
+ js common_periodicChecks_backwardBranch # jump on backwards branch
1:
FINISH_RB %edx, %ecx # jump to next instruction
