Merge "New interpreter breakout mechanism" into dalvik-dev
diff --git a/vm/Dvm.mk b/vm/Dvm.mk
index aedbd0d..8c10234 100644
--- a/vm/Dvm.mk
+++ b/vm/Dvm.mk
@@ -272,6 +272,7 @@
ifeq ($(dvm_arch),x86)
ifeq ($(dvm_os),linux)
MTERP_ARCH_KNOWN := true
+ LOCAL_CFLAGS += -DDVM_JMP_TABLE_MTERP=1
LOCAL_SRC_FILES += \
arch/$(dvm_arch_variant)/Call386ABI.S \
arch/$(dvm_arch_variant)/Hints386ABI.c \
diff --git a/vm/Thread.c b/vm/Thread.c
index feb521b..94d049c 100644
--- a/vm/Thread.c
+++ b/vm/Thread.c
@@ -971,6 +971,12 @@
thread->interpStackStart = stackBottom + interpStackSize;
thread->interpStackEnd = stackBottom + STACK_OVERFLOW_RESERVE;
+#ifndef DVM_NO_ASM_INTERP
+ thread->mainHandlerTable = dvmAsmInstructionStart;
+ thread->altHandlerTable = dvmAsmAltInstructionStart;
+ thread->curHandlerTable = thread->mainHandlerTable;
+#endif
+
/* give the thread code a chance to set things up */
dvmInitInterpStack(thread, interpStackSize);
diff --git a/vm/Thread.h b/vm/Thread.h
index 33277ba..4aa2663 100644
--- a/vm/Thread.h
+++ b/vm/Thread.h
@@ -142,11 +142,15 @@
InterpEntry entryPoint; // What to do when we start the interpreter
- /* JNI local reference tracking */
-#ifdef USE_INDIRECT_REF
- IndirectRefTable jniLocalRefTable;
+ /* Assembly interpreter handler tables */
+#ifndef DVM_NO_ASM_INTERP
+ void* curHandlerTable; // Either main or alt table
+ void* mainHandlerTable; // Table of actual instruction handler
+ void* altHandlerTable; // Table of breakout handlers
#else
- ReferenceTable jniLocalRefTable;
+ void* unused0; // Consume space to keep offsets
+ void* unused1; // the same between builds with
+ void* unused2; // and without assembly interpreters
#endif
#ifdef WITH_JIT
@@ -166,6 +170,17 @@
JitState jitState;
int icRechainCount;
const void* pProfileCountdown;
+#endif
+
+ /* JNI local reference tracking */
+#ifdef USE_INDIRECT_REF
+ IndirectRefTable jniLocalRefTable;
+#else
+ ReferenceTable jniLocalRefTable;
+#endif
+
+
+#if defined(WITH_JIT)
#if defined(WITH_SELF_VERIFICATION)
/* Buffer for register state during self verification */
struct ShadowSpace* shadowSpace;
diff --git a/vm/interp/Interp.c b/vm/interp/Interp.c
index 1d71a67..9e94449 100644
--- a/vm/interp/Interp.c
+++ b/vm/interp/Interp.c
@@ -1275,6 +1275,15 @@
}
+/*
+ * Inter-instruction handler invoked in between instruction interpretations
+ * to handle exceptional events such as debugging housekeeping, instruction
+ * count profiling, JIT trace building, etc.
+ */
+void dvmCheckInst(u2 *dPC, Thread* self)
+{
+ //TODO add debugger, profiler, JIT, etc. checks here
+}
/*
* Main interpreter loop entry point. Select "standard" or "debug"
diff --git a/vm/interp/Interp.h b/vm/interp/Interp.h
index 55968ce..098429c 100644
--- a/vm/interp/Interp.h
+++ b/vm/interp/Interp.h
@@ -65,4 +65,9 @@
*/
void dvmUpdateInterpBreak(int newMode, bool enable);
+#ifndef DVM_NO_ASM_INTERP
+extern void* dvmAsmInstructionStart[];
+extern void* dvmAsmAltInstructionStart[];
+#endif
+
#endif /*_DALVIK_INTERP_INTERP*/
diff --git a/vm/mterp/Mterp.c b/vm/mterp/Mterp.c
index 1f7052c..f6e329f 100644
--- a/vm/mterp/Mterp.c
+++ b/vm/mterp/Mterp.c
@@ -31,8 +31,8 @@
#ifndef DVM_NO_ASM_INTERP
- extern char dvmAsmInstructionStart[];
- extern char dvmAsmInstructionEnd[];
+ extern void* dvmAsmInstructionStart[];
+ extern void* dvmAsmInstructionEnd[];
#define ASM_DEF_VERIFY
#include "mterp/common/asm-constants.h"
@@ -42,17 +42,22 @@
dvmAbort();
}
+#ifndef DVM_JMP_TABLE_MTERP
/*
- * If an instruction overflows the 64-byte handler size limit, it will
- * push everything up and alter the total size. Check it here.
+ * If we're using computed goto instruction transitions, make sure
+ * none of the handlers overflows the 64-byte limit. This won't tell
+ * which one did, but if any one is too big the total size will
+ * overflow.
*/
const int width = 64;
- int interpSize = dvmAsmInstructionEnd - dvmAsmInstructionStart;
+ int interpSize = (uintptr_t) dvmAsmInstructionEnd -
+ (uintptr_t) dvmAsmInstructionStart;
if (interpSize != 0 && interpSize != kNumPackedOpcodes*width) {
LOGE("ERROR: unexpected asm interp size %d\n", interpSize);
LOGE("(did an instruction handler exceed %d bytes?)\n", width);
dvmAbort();
}
+#endif
#endif // ndef DVM_NO_ASM_INTERP
diff --git a/vm/mterp/README.txt b/vm/mterp/README.txt
index 9e28ebc..c5537d7 100644
--- a/vm/mterp/README.txt
+++ b/vm/mterp/README.txt
@@ -36,13 +36,17 @@
some operations (e.g. making use of PLD instructions on ARMv6 or avoiding
CLZ on ARMv4T).
-Two basic assumptions are made about the operation of the interpreter:
+Depending on architecture, instruction-to-instruction transitions may
+be done as either computed goto or jump table. In the computed goto
+variant, each instruction handler is allocated fixed-size area (e.g. 64
+byte). "Overflow" code is tacked to the end. In the jump table variant,
+all of the instructions handlers are contiguous and may be of any size.
+The interpreter style is selected via the "handler-size" command (see below).
- - The assembly version uses fixed-size areas for each instruction
- (e.g. 64 bytes). "Overflow" code is tacked on to the end.
- - When a C implementation is desired, the assembly version packs all
- local state into a "glue" struct, and passes that into the C function.
- Updates to the state are pulled out of the "glue" on return.
+When a C implementation for an instruction is desired, the assembly
+version packs all local state into the Thread structure and passes
+that to the C function. Updates to the state are pulled out of
+"Thread" on return.
The "arch" value should indicate an architecture family with common
programming characteristics, so "armv5te" would work for all ARMv5TE CPUs,
@@ -61,7 +65,9 @@
handler-size <bytes>
Specify the size of the assembly region, in bytes. On most platforms
- this will need to be a power of 2.
+ this will need to be a power of 2. A handler-size of 0 denotes a
+ special case in which a jump table will be generated, rather than
+ a computed-goto target block.
import <filename>
@@ -94,9 +100,27 @@
opcodes are emitted when this is seen, followed by any code that
didn't fit inside the fixed-size instruction handler space.
+ alt-op-start <directory>
+ alt <opcode> <directory>
+ alt-op-end
-The order of "op" directives is not significant; the generation tool will
-extract ordering info from the VM sources.
+ These three commands operate similar - but not identical - to op-start,
+ op and op-end. When present, they will cause the generation of an
+ alternate opcode handler table. This table is intended to be swapped
+ with the normal handler table when control breaks are needed (generally
+ for use when debugging, profiling or thread-suspend). Note some important
+ differences:
+ Unless an opcode is specifically called out with an "alt" command,
+ its body will be generated by including the assembly file ALT_STUB.S,
+ which should appear in the <directory> specified by alt-op-start.
+ Specifically called-out opcode handlers should be in files named
+ ALT_OP_<opcode>.S in the directory specified on the "alt" command.
+ At minimum, each implementation should have a generic ALT_STUB.S
+ handler and a called-out handler for the dispatch extension opcode
+ ALT_OP_DISPATCH_FF.S.
+
+The order of "op" and "alt" directives are not significant; the generation
+tool will extract ordering info from the VM sources.
Typically the form in which most opcodes currently exist is used in
the "op-start" directive. For a new port you would start with "c",
@@ -112,6 +136,13 @@
instructions, unless "asm-stub" was left blank, in which case it only
emits some labels.)
+In general, the actual implementation of an opcode handler should appear
+only in the handler table created by op-start, op and op-end. The control
+intercept stubs used by alt-op-start, alt and alt-op-end should handle
+any necessary inter-instruction bookeeping and then route to the real handlers
+in the primary table.
+
+
==== Instruction file format ====
@@ -160,6 +191,7 @@
Identifies the split between the main portion of the instruction
handler (which must fit in "handler-size" bytes) and the "sister"
code, which is appended to the end of the instruction handler block.
+ In jump table implementations, %break is ignored.
%verify "message"
diff --git a/vm/mterp/armv5te/ALT_OP_DISPATCH_FF.S b/vm/mterp/armv5te/ALT_OP_DISPATCH_FF.S
new file mode 100644
index 0000000..e3d8010
--- /dev/null
+++ b/vm/mterp/armv5te/ALT_OP_DISPATCH_FF.S
@@ -0,0 +1,5 @@
+%verify "executed"
+ mov ip, rINST, lsr #8 @ ip<- extended opcode
+ add ip, ip, #256 @ add offset for extended opcodes
+ GOTO_OPCODE(ip) @ go to proper extended handler
+
diff --git a/vm/mterp/armv5te/ALT_STUB.S b/vm/mterp/armv5te/ALT_STUB.S
new file mode 100644
index 0000000..fe92076
--- /dev/null
+++ b/vm/mterp/armv5te/ALT_STUB.S
@@ -0,0 +1,9 @@
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (${opnum} * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
diff --git a/vm/mterp/armv5te/OP_DISPATCH_FF.S b/vm/mterp/armv5te/OP_DISPATCH_FF.S
index a4e3864..1ff7981 100644
--- a/vm/mterp/armv5te/OP_DISPATCH_FF.S
+++ b/vm/mterp/armv5te/OP_DISPATCH_FF.S
@@ -1,5 +1,5 @@
%verify "executed"
- mov ip, rINST, lsr #8 @ r9<- extended opcode
+ mov ip, rINST, lsr #8 @ ip<- extended opcode
add ip, ip, #256 @ add offset for extended opcodes
GOTO_OPCODE(ip) @ go to proper extended handler
diff --git a/vm/mterp/armv5te/entry.S b/vm/mterp/armv5te/entry.S
index 14543a3..c472e15 100644
--- a/vm/mterp/armv5te/entry.S
+++ b/vm/mterp/armv5te/entry.S
@@ -62,7 +62,7 @@
mov rSELF, r0 @ set rSELF
ldr r1, [r0, #offThread_entryPoint] @ enum is 4 bytes in aapcs-EABI
LOAD_PC_FP_FROM_SELF() @ load rPC and rFP from "thread"
- adr rIBASE, dvmAsmInstructionStart @ set rIBASE
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ set rIBASE
cmp r1, #kInterpEntryInstr @ usual case?
bne .Lnot_instr @ no, handle it
diff --git a/vm/mterp/armv5te/footer.S b/vm/mterp/armv5te/footer.S
index 00026c2..3bfc15f 100644
--- a/vm/mterp/armv5te/footer.S
+++ b/vm/mterp/armv5te/footer.S
@@ -91,7 +91,7 @@
EXPORT_PC()
mov r0, #0
str r0, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
FETCH_INST()
GET_INST_OPCODE(ip)
GOTO_OPCODE(ip)
@@ -113,7 +113,7 @@
mov rPC,r0
EXPORT_PC()
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
mov r2,#kJitSingleStep @ Ask for single step and then revert
str r2,[rSELF,#offThread_jitState]
mov r1,#1 @ set changeInterp to bail to debug interp
@@ -162,7 +162,7 @@
/* No translation, so request one if profiling isn't disabled*/
2:
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
GET_JIT_PROF_TABLE(r0)
FETCH_INST()
cmp r0, #0
@@ -223,7 +223,7 @@
cmp r0,#0
bxne r0 @ continue native execution if so
EXPORT_PC()
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
FETCH_INST()
GET_INST_OPCODE(ip) @ extract opcode from rINST
GOTO_OPCODE(ip) @ jump to next instruction
@@ -254,7 +254,7 @@
*/
toInterpreter:
EXPORT_PC()
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
FETCH_INST()
GET_JIT_PROF_TABLE(r0)
@ NOTE: intended fallthrough
@@ -371,7 +371,7 @@
1: @ exit to interpreter without check
EXPORT_PC()
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
FETCH_INST()
GET_INST_OPCODE(ip)
GOTO_OPCODE(ip)
diff --git a/vm/mterp/common/asm-constants.h b/vm/mterp/common/asm-constants.h
index 9cf0e85..9cd3853 100644
--- a/vm/mterp/common/asm-constants.h
+++ b/vm/mterp/common/asm-constants.h
@@ -178,27 +178,36 @@
MTERP_OFFSET(offThread_interpStackSize, Thread, interpStackSize, 72)
MTERP_OFFSET(offThread_stackOverflowed, Thread, stackOverflowed, 76)
MTERP_OFFSET(offThread_entryPoint, Thread, entryPoint, 80)
-#ifdef USE_INDIRECT_REF
-MTERP_OFFSET(offThread_jniLocal_topCookie, \
- Thread, jniLocalRefTable.segmentState.all, 84)
-#else
-MTERP_OFFSET(offThread_jniLocal_topCookie, \
- Thread, jniLocalRefTable.nextEntry, 84)
-#endif
+MTERP_OFFSET(offThread_curHandlerTable, Thread, curHandlerTable, 84)
#ifdef WITH_JIT
-MTERP_OFFSET(offThread_jitToInterpEntries,Thread, jitToInterpEntries, 100)
-MTERP_OFFSET(offThread_inJitCodeCache, Thread, inJitCodeCache, 124)
-MTERP_OFFSET(offThread_pJitProfTable, Thread, pJitProfTable, 128)
-MTERP_OFFSET(offThread_ppJitProfTable, Thread, ppJitProfTable, 132)
-MTERP_OFFSET(offThread_jitThreshold, Thread, jitThreshold, 136)
-MTERP_OFFSET(offThread_jitResumeNPC, Thread, jitResumeNPC, 140)
-MTERP_OFFSET(offThread_jitResumeDPC, Thread, jitResumeDPC, 144)
-MTERP_OFFSET(offThread_jitState, Thread, jitState, 148)
-MTERP_OFFSET(offThread_icRechainCount, Thread, icRechainCount, 152)
-MTERP_OFFSET(offThread_pProfileCountdown, Thread, pProfileCountdown, 156)
+MTERP_OFFSET(offThread_jitToInterpEntries,Thread, jitToInterpEntries, 96)
+MTERP_OFFSET(offThread_inJitCodeCache, Thread, inJitCodeCache, 120)
+MTERP_OFFSET(offThread_pJitProfTable, Thread, pJitProfTable, 124)
+MTERP_OFFSET(offThread_ppJitProfTable, Thread, ppJitProfTable, 128)
+MTERP_OFFSET(offThread_jitThreshold, Thread, jitThreshold, 132)
+MTERP_OFFSET(offThread_jitResumeNPC, Thread, jitResumeNPC, 136)
+MTERP_OFFSET(offThread_jitResumeDPC, Thread, jitResumeDPC, 140)
+MTERP_OFFSET(offThread_jitState, Thread, jitState, 144)
+MTERP_OFFSET(offThread_icRechainCount, Thread, icRechainCount, 148)
+MTERP_OFFSET(offThread_pProfileCountdown, Thread, pProfileCountdown, 152)
+#ifdef USE_INDIRECT_REF
+MTERP_OFFSET(offThread_jniLocal_topCookie, \
+ Thread, jniLocalRefTable.segmentState.all, 156)
+#else
+MTERP_OFFSET(offThread_jniLocal_topCookie, \
+ Thread, jniLocalRefTable.nextEntry, 156)
+#endif
#if defined(WITH_SELF_VERIFICATION)
-MTERP_OFFSET(offThread_shadowSpace, Thread, shadowSpace, 160)
+MTERP_OFFSET(offThread_shadowSpace, Thread, shadowSpace, 172)
+#endif
+#else
+#ifdef USE_INDIRECT_REF
+MTERP_OFFSET(offThread_jniLocal_topCookie, \
+ Thread, jniLocalRefTable.segmentState.all, 96)
+#else
+MTERP_OFFSET(offThread_jniLocal_topCookie, \
+ Thread, jniLocalRefTable.nextEntry, 96)
#endif
#endif
diff --git a/vm/mterp/config-armv5te b/vm/mterp/config-armv5te
index 2dceb04..aeff468 100644
--- a/vm/mterp/config-armv5te
+++ b/vm/mterp/config-armv5te
@@ -42,6 +42,11 @@
#op OP_FILL_ARRAY_DATA c
op-end
+# alternate opcode entry points (used to redirect control)
+op-alt-start armv5te
+ alt OP_DISPATCH_FF armv5te
+op-alt-end
+
# "helper" code for C; include if you use any of the C stubs (this generates
# object code, so it's normally excluded)
##import c/gotoTargets.c
diff --git a/vm/mterp/config-armv5te-vfp b/vm/mterp/config-armv5te-vfp
index ce0c521..048b178 100644
--- a/vm/mterp/config-armv5te-vfp
+++ b/vm/mterp/config-armv5te-vfp
@@ -92,6 +92,11 @@
#op OP_INT_TO_SHORT armv6
op-end
+# alternate opcode entry points (used to redirect control)
+op-alt-start armv5te
+ alt OP_DISPATCH_FF armv5te
+op-alt-end
+
# "helper" code for C; include if you use any of the C stubs (this generates
# object code, so it's normally excluded)
##import c/gotoTargets.c
diff --git a/vm/mterp/config-armv7-a b/vm/mterp/config-armv7-a
index e0ccdd3..ed08dd5 100644
--- a/vm/mterp/config-armv7-a
+++ b/vm/mterp/config-armv7-a
@@ -154,6 +154,11 @@
op OP_SUB_FLOAT_2ADDR arm-vfp
op-end
+# alternate opcode entry points (used to redirect control)
+op-alt-start armv5te
+ alt OP_DISPATCH_FF armv5te
+op-alt-end
+
# "helper" code for C; include if you use any of the C stubs (this generates
# object code, so it's normally excluded)
#
diff --git a/vm/mterp/config-armv7-a-neon b/vm/mterp/config-armv7-a-neon
index e66640c..c6ac47f 100644
--- a/vm/mterp/config-armv7-a-neon
+++ b/vm/mterp/config-armv7-a-neon
@@ -154,6 +154,11 @@
op OP_SUB_FLOAT_2ADDR arm-vfp
op-end
+# alternate opcode entry points (used to redirect control)
+op-alt-start armv5te
+ alt OP_DISPATCH_FF armv5te
+op-alt-end
+
# "helper" code for C; include if you use any of the C stubs (this generates
# object code, so it's normally excluded)
##import c/gotoTargets.c
diff --git a/vm/mterp/config-x86 b/vm/mterp/config-x86
index 4d67c51..2af0f28 100644
--- a/vm/mterp/config-x86
+++ b/vm/mterp/config-x86
@@ -16,7 +16,7 @@
# Configuration for "desktop" targets.
#
-handler-size 64
+handler-size 0
# source for the instruction table stub
asm-stub x86/stub.S
@@ -43,6 +43,11 @@
op OP_INVOKE_OBJECT_INIT c
op-end
+# alternate opcode entry points (used to redirect control)
+op-alt-start x86
+ alt OP_DISPATCH_FF x86
+op-alt-end
+
# arch-specific entry point to interpreter
import x86/entry.S
diff --git a/vm/mterp/gen-mterp.py b/vm/mterp/gen-mterp.py
index 8214672..ec354f4 100755
--- a/vm/mterp/gen-mterp.py
+++ b/vm/mterp/gen-mterp.py
@@ -29,10 +29,15 @@
handler_size_bits = -1000
handler_size_bytes = -1000
in_op_start = 0 # 0=not started, 1=started, 2=ended
+in_alt_op_start = 0 # 0=not started, 1=started, 2=ended
default_op_dir = None
+default_alt_op_dir = None
opcode_locations = {}
+alt_opcode_locations = {}
asm_stub_text = []
label_prefix = ".L" # use ".L" to hide labels from gdb
+alt_label_prefix = ".L_ALT" # use ".L" to hide labels from gdb
+jmp_table = False # jump table vs. computed goto style
# Exception class.
class DataParseError(SyntaxError):
@@ -48,27 +53,31 @@
#
# Parse arch config file --
# Set handler_size_bytes to the value of tokens[1], and handler_size_bits to
-# log2(handler_size_bytes). Throws an exception if "bytes" is not a power
-# of two.
+# log2(handler_size_bytes). Throws an exception if "bytes" is not 0 or
+# a power of two.
#
def setHandlerSize(tokens):
- global handler_size_bits, handler_size_bytes
+ global handler_size_bits, handler_size_bytes, jmp_table
if len(tokens) != 2:
raise DataParseError("handler-size requires one argument")
if handler_size_bits != -1000:
raise DataParseError("handler-size may only be set once")
- # compute log2(n), and make sure n is a power of 2
+ # compute log2(n), and make sure n is 0 or a power of 2
handler_size_bytes = bytes = int(tokens[1])
- bits = -1
- while bytes > 0:
- bytes //= 2 # halve with truncating division
- bits += 1
+ if handler_size_bytes == 0:
+ jmp_table = True
+ handler_size_bits = 0;
+ else:
+ bits = -1
+ while bytes > 0:
+ bytes //= 2 # halve with truncating division
+ bits += 1
- if handler_size_bytes == 0 or handler_size_bytes != (1 << bits):
- raise DataParseError("handler-size (%d) must be power of 2 and > 0" \
- % orig_bytes)
- handler_size_bits = bits
+ if handler_size_bytes == 0 or handler_size_bytes != (1 << bits):
+ raise DataParseError("handler-size (%d) must be power of 2" \
+ % orig_bytes)
+ handler_size_bits = bits
#
# Parse arch config file --
@@ -117,6 +126,39 @@
in_op_start = 1
#
+# Parse arch config file
+# Start of optional alternate opcode list.
+#
+def altOpStart(tokens):
+ global in_alt_op_start
+ global default_alt_op_dir
+ if len(tokens) != 2:
+ raise DataParseError("altOpStart takes a directory name argument")
+ if in_alt_op_start != 0:
+ raise DataParseError("altOpStart can only be specified once")
+ default_alt_op_dir = tokens[1]
+ in_alt_op_start = 1
+
+#
+# Parse arch config file --
+# Set location of a single alt opcode's source file.
+#
+def altEntry(tokens):
+ #global alt_opcode_locations
+ if len(tokens) != 3:
+ raise DataParseError("alt requires exactly two arguments")
+ if in_alt_op_start != 1:
+ raise DataParseError("alt statements must be between opStart/opEnd")
+ try:
+ index = opcodes.index(tokens[1])
+ except ValueError:
+ raise DataParseError("unknown opcode %s" % tokens[1])
+ if alt_opcode_locations.has_key(tokens[1]):
+ print "Warning: alt overrides earlier %s (%s -> %s)" \
+ % (tokens[1], alt_opcode_locations[tokens[1]], tokens[2])
+ alt_opcode_locations[tokens[1]] = tokens[2]
+
+#
# Parse arch config file --
# Set location of a single opcode's source file.
#
@@ -149,6 +191,38 @@
loadAndEmitOpcodes()
+#
+# Emit jump table
+#
+def emitJmpTable(start_label, prefix):
+ asm_fp.write("\n .global %s\n" % start_label)
+ asm_fp.write(" .text\n")
+ asm_fp.write("%s:\n" % start_label)
+ for i in xrange(kNumPackedOpcodes):
+ op = opcodes[i]
+ dict = getGlobalSubDict()
+ dict.update({ "opcode":op, "opnum":i })
+ asm_fp.write(" .long " + prefix + \
+ "_%(opcode)s /* 0x%(opnum)02x */\n" % dict)
+
+#
+# Parse arch config file --
+# End of alternate opcode list; emit instruction blocks.
+# If jump table style, emit tables following
+#
+def altOpEnd(tokens):
+ global in_alt_op_start
+ if len(tokens) != 1:
+ raise DataParseError("altOpEnd takes no arguments")
+ if in_alt_op_start != 1:
+ raise DataParseError("altOpEnd follows altOStart, once")
+ in_alt_op_start = 2
+
+ loadAndEmitAltOpcodes()
+
+ if jmp_table:
+ emitJmpTable("dvmAsmInstructionStart", label_prefix);
+ emitJmpTable("dvmAsmAltInstructionStart", alt_label_prefix);
#
# Extract an ordered list of instructions from the VM sources. We use the
@@ -172,6 +246,9 @@
raise SyntaxError, "bad opcode count"
return opcodes
+def emitAlign():
+ if not jmp_table:
+ asm_fp.write(" .balign %d\n" % handler_size_bytes)
#
# Load and emit opcodes for all kNumPackedOpcodes instructions.
@@ -180,11 +257,17 @@
sister_list = []
assert len(opcodes) == kNumPackedOpcodes
need_dummy_start = False
+ if jmp_table:
+ start_label = "dvmAsmInstructionStartCode"
+ end_label = "dvmAsmInstructionEndCode"
+ else:
+ start_label = "dvmAsmInstructionStart"
+ end_label = "dvmAsmInstructionEnd"
# point dvmAsmInstructionStart at the first handler or stub
- asm_fp.write("\n .global dvmAsmInstructionStart\n")
- asm_fp.write(" .type dvmAsmInstructionStart, %function\n")
- asm_fp.write("dvmAsmInstructionStart = " + label_prefix + "_OP_NOP\n")
+ asm_fp.write("\n .global %s\n" % start_label)
+ asm_fp.write(" .type %s, %%function\n" % start_label)
+ asm_fp.write("%s = " % start_label + label_prefix + "_OP_NOP\n")
asm_fp.write(" .text\n\n")
for i in xrange(kNumPackedOpcodes):
@@ -206,29 +289,71 @@
# need to have the dvmAsmInstructionStart label point at OP_NOP, and it's
# too annoying to try to slide it in after the alignment psuedo-op, so
# we take the low road and just emit a dummy OP_NOP here.
- #
- # The dvmAsmInstructionStart will also use the size for OP_NOP, so
- # we want to generate a .size directive that spans all handlers.
if need_dummy_start:
- asm_fp.write(" .balign %d\n" % handler_size_bytes)
+ emitAlign()
asm_fp.write(label_prefix + "_OP_NOP: /* dummy */\n");
- asm_fp.write("\n .balign %d\n" % handler_size_bytes)
- asm_fp.write(" .size .L_OP_NOP, .-.L_OP_NOP\n")
- asm_fp.write(" .global dvmAsmInstructionEnd\n")
- asm_fp.write("dvmAsmInstructionEnd:\n")
+ emitAlign()
+ asm_fp.write(" .size %s, .-%s\n" % (start_label, start_label))
+ asm_fp.write(" .global %s\n" % end_label)
+ asm_fp.write("%s:\n" % end_label)
- emitSectionComment("Sister implementations", asm_fp)
- asm_fp.write(" .global dvmAsmSisterStart\n")
- asm_fp.write(" .type dvmAsmSisterStart, %function\n")
- asm_fp.write(" .text\n")
- asm_fp.write(" .balign 4\n")
- asm_fp.write("dvmAsmSisterStart:\n")
- asm_fp.writelines(sister_list)
+ if not jmp_table:
+ emitSectionComment("Sister implementations", asm_fp)
+ asm_fp.write(" .global dvmAsmSisterStart\n")
+ asm_fp.write(" .type dvmAsmSisterStart, %function\n")
+ asm_fp.write(" .text\n")
+ asm_fp.write(" .balign 4\n")
+ asm_fp.write("dvmAsmSisterStart:\n")
+ asm_fp.writelines(sister_list)
- asm_fp.write("\n .size dvmAsmSisterStart, .-dvmAsmSisterStart\n")
- asm_fp.write(" .global dvmAsmSisterEnd\n")
- asm_fp.write("dvmAsmSisterEnd:\n\n")
+ asm_fp.write("\n .size dvmAsmSisterStart, .-dvmAsmSisterStart\n")
+ asm_fp.write(" .global dvmAsmSisterEnd\n")
+ asm_fp.write("dvmAsmSisterEnd:\n\n")
+
+#
+# Load an alternate entry stub
+#
+def loadAndEmitAltStub(source, opindex):
+ op = opcodes[opindex]
+ if verbose:
+ print " alt emit %s --> stub" % source
+ dict = getGlobalSubDict()
+ dict.update({ "opcode":op, "opnum":opindex })
+
+ emitAsmHeader(asm_fp, dict, alt_label_prefix)
+ appendSourceFile(source, dict, asm_fp, None)
+
+#
+# Load and emit alternate opcodes for all kNumPackedOpcodes instructions.
+#
+def loadAndEmitAltOpcodes():
+ assert len(opcodes) == kNumPackedOpcodes
+ if jmp_table:
+ start_label = "dvmAsmAltInstructionStartCode"
+ end_label = "dvmAsmAltInstructionEndCode"
+ else:
+ start_label = "dvmAsmAltInstructionStart"
+ end_label = "dvmAsmAltInstructionEnd"
+
+ # point dvmAsmInstructionStart at the first handler or stub
+ asm_fp.write("\n .global %s\n" % start_label)
+ asm_fp.write(" .type %s, %%function\n" % start_label)
+ asm_fp.write("%s:\n" % start_label)
+ asm_fp.write(" .text\n\n")
+
+ for i in xrange(kNumPackedOpcodes):
+ op = opcodes[i]
+ if alt_opcode_locations.has_key(op):
+ source = "%s/ALT_%s.S" % (alt_opcode_locations[op], op)
+ else:
+ source = "%s/ALT_STUB.S" % default_alt_op_dir
+ loadAndEmitAltStub(source, i)
+
+ emitAlign()
+ asm_fp.write(" .size %s, .-%s\n" % (start_label, start_label))
+ asm_fp.write(" .global %s\n" % end_label)
+ asm_fp.write("%s:\n" % end_label)
#
# Load a C fragment and emit it, then output an assembly stub.
@@ -257,28 +382,28 @@
if verbose:
print " emit %s --> asm" % source
- emitAsmHeader(asm_fp, dict)
+ emitAsmHeader(asm_fp, dict, label_prefix)
appendSourceFile(source, dict, asm_fp, sister_list)
#
# Output the alignment directive and label for an assembly piece.
#
-def emitAsmHeader(outfp, dict):
+def emitAsmHeader(outfp, dict, prefix):
outfp.write("/* ------------------------------ */\n")
# The alignment directive ensures that the handler occupies
# at least the correct amount of space. We don't try to deal
# with overflow here.
- outfp.write(" .balign %d\n" % handler_size_bytes)
+ emitAlign()
# Emit a label so that gdb will say the right thing. We prepend an
# underscore so the symbol name doesn't clash with the Opcode enum.
- outfp.write(label_prefix + "_%(opcode)s: /* 0x%(opnum)02x */\n" % dict)
+ outfp.write(prefix + "_%(opcode)s: /* 0x%(opnum)02x */\n" % dict)
#
# Output a generic instruction stub that updates the "glue" struct and
# calls the C implementation.
#
def emitAsmStub(outfp, dict):
- emitAsmHeader(outfp, dict)
+ emitAsmHeader(outfp, dict, label_prefix)
for line in asm_stub_text:
templ = Template(line)
outfp.write(templ.substitute(dict))
@@ -337,7 +462,7 @@
elif line.startswith("%break") and sister_list != None:
# allow more than one %break, ignoring all following the first
- if not in_sister:
+ if not jmp_table and not in_sister:
in_sister = True
sister_list.append("\n/* continuation for %(opcode)s */\n"%dict)
continue
@@ -459,6 +584,12 @@
opStart(tokens)
elif tokens[0] == "op-end":
opEnd(tokens)
+ elif tokens[0] == "op-alt-start":
+ altOpStart(tokens)
+ elif tokens[0] == "op-alt-end":
+ altOpEnd(tokens)
+ elif tokens[0] == "alt":
+ altEntry(tokens)
elif tokens[0] == "op":
opEntry(tokens)
else:
diff --git a/vm/mterp/out/InterpAsm-allstubs.S b/vm/mterp/out/InterpAsm-allstubs.S
index 8f3f45c..779fd5f 100644
--- a/vm/mterp/out/InterpAsm-allstubs.S
+++ b/vm/mterp/out/InterpAsm-allstubs.S
@@ -12,9 +12,8 @@
.balign 64
.L_OP_NOP: /* dummy */
-
.balign 64
- .size .L_OP_NOP, .-.L_OP_NOP
+ .size dvmAsmInstructionStart, .-dvmAsmInstructionStart
.global dvmAsmInstructionEnd
dvmAsmInstructionEnd:
diff --git a/vm/mterp/out/InterpAsm-armv5te-vfp.S b/vm/mterp/out/InterpAsm-armv5te-vfp.S
index a0f54e8..cb2c4ae 100644
--- a/vm/mterp/out/InterpAsm-armv5te-vfp.S
+++ b/vm/mterp/out/InterpAsm-armv5te-vfp.S
@@ -290,7 +290,7 @@
mov rSELF, r0 @ set rSELF
ldr r1, [r0, #offThread_entryPoint] @ enum is 4 bytes in aapcs-EABI
LOAD_PC_FP_FROM_SELF() @ load rPC and rFP from "thread"
- adr rIBASE, dvmAsmInstructionStart @ set rIBASE
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ set rIBASE
cmp r1, #kInterpEntryInstr @ usual case?
bne .Lnot_instr @ no, handle it
@@ -7747,7 +7747,7 @@
.balign 64
.L_OP_DISPATCH_FF: /* 0xff */
/* File: armv5te/OP_DISPATCH_FF.S */
- mov ip, rINST, lsr #8 @ r9<- extended opcode
+ mov ip, rINST, lsr #8 @ ip<- extended opcode
add ip, ip, #256 @ add offset for extended opcodes
GOTO_OPCODE(ip) @ go to proper extended handler
@@ -10576,9 +10576,8 @@
bl dvmThrowVerificationError @ always throws
b common_exceptionThrown @ handle exception
-
.balign 64
- .size .L_OP_NOP, .-.L_OP_NOP
+ .size dvmAsmInstructionStart, .-dvmAsmInstructionStart
.global dvmAsmInstructionEnd
dvmAsmInstructionEnd:
@@ -13157,6 +13156,7179 @@
.global dvmAsmSisterEnd
dvmAsmSisterEnd:
+
+ .global dvmAsmAltInstructionStart
+ .type dvmAsmAltInstructionStart, %function
+dvmAsmAltInstructionStart:
+ .text
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NOP: /* 0x00 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (0 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE: /* 0x01 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (1 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_FROM16: /* 0x02 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (2 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_16: /* 0x03 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (3 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_WIDE: /* 0x04 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (4 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_WIDE_FROM16: /* 0x05 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (5 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_WIDE_16: /* 0x06 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (6 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_OBJECT: /* 0x07 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (7 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_OBJECT_FROM16: /* 0x08 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (8 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_OBJECT_16: /* 0x09 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (9 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_RESULT: /* 0x0a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (10 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_RESULT_WIDE: /* 0x0b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (11 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_RESULT_OBJECT: /* 0x0c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (12 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_EXCEPTION: /* 0x0d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (13 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_RETURN_VOID: /* 0x0e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (14 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_RETURN: /* 0x0f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (15 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_RETURN_WIDE: /* 0x10 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (16 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_RETURN_OBJECT: /* 0x11 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (17 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_4: /* 0x12 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (18 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_16: /* 0x13 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (19 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST: /* 0x14 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (20 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_HIGH16: /* 0x15 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (21 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_WIDE_16: /* 0x16 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (22 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_WIDE_32: /* 0x17 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (23 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_WIDE: /* 0x18 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (24 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_WIDE_HIGH16: /* 0x19 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (25 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_STRING: /* 0x1a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (26 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_STRING_JUMBO: /* 0x1b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (27 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_CLASS: /* 0x1c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (28 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MONITOR_ENTER: /* 0x1d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (29 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MONITOR_EXIT: /* 0x1e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (30 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CHECK_CAST: /* 0x1f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (31 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INSTANCE_OF: /* 0x20 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (32 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ARRAY_LENGTH: /* 0x21 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (33 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEW_INSTANCE: /* 0x22 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (34 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEW_ARRAY: /* 0x23 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (35 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_FILLED_NEW_ARRAY: /* 0x24 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (36 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (37 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_FILL_ARRAY_DATA: /* 0x26 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (38 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_THROW: /* 0x27 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (39 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_GOTO: /* 0x28 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (40 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_GOTO_16: /* 0x29 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (41 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_GOTO_32: /* 0x2a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (42 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_PACKED_SWITCH: /* 0x2b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (43 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPARSE_SWITCH: /* 0x2c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (44 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CMPL_FLOAT: /* 0x2d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (45 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CMPG_FLOAT: /* 0x2e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (46 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CMPL_DOUBLE: /* 0x2f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (47 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CMPG_DOUBLE: /* 0x30 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (48 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CMP_LONG: /* 0x31 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (49 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_EQ: /* 0x32 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (50 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_NE: /* 0x33 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (51 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_LT: /* 0x34 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (52 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_GE: /* 0x35 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (53 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_GT: /* 0x36 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (54 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_LE: /* 0x37 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (55 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_EQZ: /* 0x38 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (56 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_NEZ: /* 0x39 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (57 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_LTZ: /* 0x3a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (58 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_GEZ: /* 0x3b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (59 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_GTZ: /* 0x3c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (60 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_LEZ: /* 0x3d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (61 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3E: /* 0x3e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (62 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3F: /* 0x3f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (63 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_40: /* 0x40 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (64 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_41: /* 0x41 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (65 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_42: /* 0x42 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (66 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_43: /* 0x43 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (67 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AGET: /* 0x44 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (68 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AGET_WIDE: /* 0x45 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (69 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AGET_OBJECT: /* 0x46 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (70 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AGET_BOOLEAN: /* 0x47 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (71 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AGET_BYTE: /* 0x48 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (72 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AGET_CHAR: /* 0x49 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (73 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AGET_SHORT: /* 0x4a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (74 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_APUT: /* 0x4b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (75 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_APUT_WIDE: /* 0x4c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (76 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_APUT_OBJECT: /* 0x4d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (77 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_APUT_BOOLEAN: /* 0x4e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (78 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_APUT_BYTE: /* 0x4f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (79 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_APUT_CHAR: /* 0x50 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (80 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_APUT_SHORT: /* 0x51 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (81 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET: /* 0x52 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (82 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_WIDE: /* 0x53 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (83 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_OBJECT: /* 0x54 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (84 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_BOOLEAN: /* 0x55 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (85 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_BYTE: /* 0x56 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (86 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_CHAR: /* 0x57 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (87 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_SHORT: /* 0x58 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (88 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT: /* 0x59 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (89 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_WIDE: /* 0x5a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (90 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_OBJECT: /* 0x5b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (91 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_BOOLEAN: /* 0x5c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (92 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_BYTE: /* 0x5d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (93 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_CHAR: /* 0x5e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (94 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_SHORT: /* 0x5f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (95 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET: /* 0x60 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (96 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_WIDE: /* 0x61 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (97 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_OBJECT: /* 0x62 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (98 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_BOOLEAN: /* 0x63 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (99 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_BYTE: /* 0x64 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (100 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_CHAR: /* 0x65 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (101 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_SHORT: /* 0x66 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (102 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT: /* 0x67 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (103 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_WIDE: /* 0x68 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (104 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_OBJECT: /* 0x69 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (105 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_BOOLEAN: /* 0x6a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (106 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_BYTE: /* 0x6b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (107 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_CHAR: /* 0x6c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (108 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_SHORT: /* 0x6d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (109 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_VIRTUAL: /* 0x6e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (110 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_SUPER: /* 0x6f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (111 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_DIRECT: /* 0x70 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (112 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_STATIC: /* 0x71 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (113 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_INTERFACE: /* 0x72 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (114 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_73: /* 0x73 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (115 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (116 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_SUPER_RANGE: /* 0x75 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (117 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_DIRECT_RANGE: /* 0x76 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (118 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_STATIC_RANGE: /* 0x77 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (119 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (120 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_79: /* 0x79 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (121 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_7A: /* 0x7a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (122 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEG_INT: /* 0x7b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (123 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NOT_INT: /* 0x7c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (124 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEG_LONG: /* 0x7d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (125 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NOT_LONG: /* 0x7e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (126 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEG_FLOAT: /* 0x7f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (127 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEG_DOUBLE: /* 0x80 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (128 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INT_TO_LONG: /* 0x81 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (129 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INT_TO_FLOAT: /* 0x82 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (130 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INT_TO_DOUBLE: /* 0x83 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (131 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_LONG_TO_INT: /* 0x84 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (132 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_LONG_TO_FLOAT: /* 0x85 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (133 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_LONG_TO_DOUBLE: /* 0x86 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (134 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_FLOAT_TO_INT: /* 0x87 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (135 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_FLOAT_TO_LONG: /* 0x88 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (136 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_FLOAT_TO_DOUBLE: /* 0x89 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (137 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DOUBLE_TO_INT: /* 0x8a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (138 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DOUBLE_TO_LONG: /* 0x8b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (139 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DOUBLE_TO_FLOAT: /* 0x8c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (140 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INT_TO_BYTE: /* 0x8d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (141 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INT_TO_CHAR: /* 0x8e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (142 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INT_TO_SHORT: /* 0x8f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (143 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_INT: /* 0x90 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (144 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_INT: /* 0x91 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (145 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_INT: /* 0x92 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (146 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_INT: /* 0x93 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (147 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_INT: /* 0x94 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (148 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AND_INT: /* 0x95 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (149 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_OR_INT: /* 0x96 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (150 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_XOR_INT: /* 0x97 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (151 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHL_INT: /* 0x98 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (152 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHR_INT: /* 0x99 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (153 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_USHR_INT: /* 0x9a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (154 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_LONG: /* 0x9b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (155 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_LONG: /* 0x9c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (156 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_LONG: /* 0x9d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (157 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_LONG: /* 0x9e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (158 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_LONG: /* 0x9f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (159 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AND_LONG: /* 0xa0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (160 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_OR_LONG: /* 0xa1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (161 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_XOR_LONG: /* 0xa2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (162 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHL_LONG: /* 0xa3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (163 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHR_LONG: /* 0xa4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (164 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_USHR_LONG: /* 0xa5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (165 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_FLOAT: /* 0xa6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (166 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_FLOAT: /* 0xa7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (167 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_FLOAT: /* 0xa8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (168 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_FLOAT: /* 0xa9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (169 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_FLOAT: /* 0xaa */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (170 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_DOUBLE: /* 0xab */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (171 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_DOUBLE: /* 0xac */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (172 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_DOUBLE: /* 0xad */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (173 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_DOUBLE: /* 0xae */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (174 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_DOUBLE: /* 0xaf */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (175 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_INT_2ADDR: /* 0xb0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (176 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_INT_2ADDR: /* 0xb1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (177 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_INT_2ADDR: /* 0xb2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (178 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_INT_2ADDR: /* 0xb3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (179 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_INT_2ADDR: /* 0xb4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (180 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AND_INT_2ADDR: /* 0xb5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (181 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_OR_INT_2ADDR: /* 0xb6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (182 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_XOR_INT_2ADDR: /* 0xb7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (183 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHL_INT_2ADDR: /* 0xb8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (184 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHR_INT_2ADDR: /* 0xb9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (185 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_USHR_INT_2ADDR: /* 0xba */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (186 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_LONG_2ADDR: /* 0xbb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (187 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_LONG_2ADDR: /* 0xbc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (188 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_LONG_2ADDR: /* 0xbd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (189 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_LONG_2ADDR: /* 0xbe */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (190 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_LONG_2ADDR: /* 0xbf */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (191 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AND_LONG_2ADDR: /* 0xc0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (192 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_OR_LONG_2ADDR: /* 0xc1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (193 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_XOR_LONG_2ADDR: /* 0xc2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (194 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHL_LONG_2ADDR: /* 0xc3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (195 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHR_LONG_2ADDR: /* 0xc4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (196 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_USHR_LONG_2ADDR: /* 0xc5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (197 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_FLOAT_2ADDR: /* 0xc6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (198 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_FLOAT_2ADDR: /* 0xc7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (199 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_FLOAT_2ADDR: /* 0xc8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (200 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_FLOAT_2ADDR: /* 0xc9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (201 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_FLOAT_2ADDR: /* 0xca */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (202 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_DOUBLE_2ADDR: /* 0xcb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (203 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_DOUBLE_2ADDR: /* 0xcc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (204 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_DOUBLE_2ADDR: /* 0xcd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (205 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_DOUBLE_2ADDR: /* 0xce */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (206 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_DOUBLE_2ADDR: /* 0xcf */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (207 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_INT_LIT16: /* 0xd0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (208 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_RSUB_INT: /* 0xd1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (209 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_INT_LIT16: /* 0xd2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (210 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_INT_LIT16: /* 0xd3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (211 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_INT_LIT16: /* 0xd4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (212 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AND_INT_LIT16: /* 0xd5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (213 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_OR_INT_LIT16: /* 0xd6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (214 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_XOR_INT_LIT16: /* 0xd7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (215 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_INT_LIT8: /* 0xd8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (216 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_RSUB_INT_LIT8: /* 0xd9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (217 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_INT_LIT8: /* 0xda */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (218 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_INT_LIT8: /* 0xdb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (219 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_INT_LIT8: /* 0xdc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (220 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AND_INT_LIT8: /* 0xdd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (221 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_OR_INT_LIT8: /* 0xde */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (222 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_XOR_INT_LIT8: /* 0xdf */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (223 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHL_INT_LIT8: /* 0xe0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (224 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHR_INT_LIT8: /* 0xe1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (225 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_USHR_INT_LIT8: /* 0xe2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (226 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_VOLATILE: /* 0xe3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (227 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_VOLATILE: /* 0xe4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (228 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_VOLATILE: /* 0xe5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (229 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_VOLATILE: /* 0xe6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (230 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (231 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_WIDE_VOLATILE: /* 0xe8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (232 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (233 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_WIDE_VOLATILE: /* 0xea */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (234 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_WIDE_VOLATILE: /* 0xeb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (235 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_BREAKPOINT: /* 0xec */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (236 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_THROW_VERIFICATION_ERROR: /* 0xed */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (237 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_EXECUTE_INLINE: /* 0xee */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (238 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_EXECUTE_INLINE_RANGE: /* 0xef */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (239 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_OBJECT_INIT: /* 0xf0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (240 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_RETURN_VOID_BARRIER: /* 0xf1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (241 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_QUICK: /* 0xf2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (242 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_WIDE_QUICK: /* 0xf3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (243 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_OBJECT_QUICK: /* 0xf4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (244 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_QUICK: /* 0xf5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (245 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_WIDE_QUICK: /* 0xf6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (246 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_OBJECT_QUICK: /* 0xf7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (247 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (248 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (249 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_SUPER_QUICK: /* 0xfa */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (250 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (251 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (252 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_OBJECT_VOLATILE: /* 0xfd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (253 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (254 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DISPATCH_FF: /* 0xff */
+/* File: armv5te/ALT_OP_DISPATCH_FF.S */
+ mov ip, rINST, lsr #8 @ ip<- extended opcode
+ add ip, ip, #256 @ add offset for extended opcodes
+ GOTO_OPCODE(ip) @ go to proper extended handler
+
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_CLASS_JUMBO: /* 0x100 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (256 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CHECK_CAST_JUMBO: /* 0x101 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (257 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INSTANCE_OF_JUMBO: /* 0x102 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (258 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEW_INSTANCE_JUMBO: /* 0x103 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (259 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEW_ARRAY_JUMBO: /* 0x104 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (260 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (261 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_JUMBO: /* 0x106 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (262 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_WIDE_JUMBO: /* 0x107 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (263 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_OBJECT_JUMBO: /* 0x108 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (264 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (265 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_BYTE_JUMBO: /* 0x10a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (266 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_CHAR_JUMBO: /* 0x10b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (267 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_SHORT_JUMBO: /* 0x10c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (268 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_JUMBO: /* 0x10d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (269 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_WIDE_JUMBO: /* 0x10e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (270 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_OBJECT_JUMBO: /* 0x10f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (271 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (272 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_BYTE_JUMBO: /* 0x111 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (273 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_CHAR_JUMBO: /* 0x112 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (274 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_SHORT_JUMBO: /* 0x113 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (275 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_JUMBO: /* 0x114 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (276 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_WIDE_JUMBO: /* 0x115 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (277 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_OBJECT_JUMBO: /* 0x116 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (278 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (279 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_BYTE_JUMBO: /* 0x118 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (280 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_CHAR_JUMBO: /* 0x119 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (281 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_SHORT_JUMBO: /* 0x11a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (282 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_JUMBO: /* 0x11b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (283 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_WIDE_JUMBO: /* 0x11c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (284 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_OBJECT_JUMBO: /* 0x11d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (285 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (286 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_BYTE_JUMBO: /* 0x11f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (287 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_CHAR_JUMBO: /* 0x120 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (288 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_SHORT_JUMBO: /* 0x121 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (289 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (290 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_SUPER_JUMBO: /* 0x123 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (291 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (292 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_STATIC_JUMBO: /* 0x125 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (293 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (294 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_27FF: /* 0x127 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (295 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_28FF: /* 0x128 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (296 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_29FF: /* 0x129 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (297 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_2AFF: /* 0x12a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (298 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_2BFF: /* 0x12b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (299 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_2CFF: /* 0x12c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (300 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_2DFF: /* 0x12d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (301 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_2EFF: /* 0x12e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (302 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_2FFF: /* 0x12f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (303 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_30FF: /* 0x130 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (304 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_31FF: /* 0x131 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (305 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_32FF: /* 0x132 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (306 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_33FF: /* 0x133 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (307 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_34FF: /* 0x134 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (308 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_35FF: /* 0x135 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (309 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_36FF: /* 0x136 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (310 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_37FF: /* 0x137 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (311 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_38FF: /* 0x138 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (312 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_39FF: /* 0x139 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (313 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3AFF: /* 0x13a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (314 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3BFF: /* 0x13b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (315 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3CFF: /* 0x13c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (316 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3DFF: /* 0x13d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (317 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3EFF: /* 0x13e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (318 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3FFF: /* 0x13f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (319 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_40FF: /* 0x140 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (320 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_41FF: /* 0x141 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (321 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_42FF: /* 0x142 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (322 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_43FF: /* 0x143 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (323 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_44FF: /* 0x144 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (324 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_45FF: /* 0x145 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (325 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_46FF: /* 0x146 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (326 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_47FF: /* 0x147 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (327 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_48FF: /* 0x148 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (328 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_49FF: /* 0x149 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (329 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_4AFF: /* 0x14a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (330 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_4BFF: /* 0x14b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (331 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_4CFF: /* 0x14c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (332 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_4DFF: /* 0x14d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (333 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_4EFF: /* 0x14e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (334 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_4FFF: /* 0x14f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (335 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_50FF: /* 0x150 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (336 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_51FF: /* 0x151 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (337 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_52FF: /* 0x152 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (338 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_53FF: /* 0x153 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (339 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_54FF: /* 0x154 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (340 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_55FF: /* 0x155 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (341 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_56FF: /* 0x156 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (342 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_57FF: /* 0x157 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (343 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_58FF: /* 0x158 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (344 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_59FF: /* 0x159 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (345 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_5AFF: /* 0x15a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (346 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_5BFF: /* 0x15b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (347 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_5CFF: /* 0x15c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (348 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_5DFF: /* 0x15d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (349 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_5EFF: /* 0x15e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (350 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_5FFF: /* 0x15f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (351 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_60FF: /* 0x160 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (352 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_61FF: /* 0x161 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (353 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_62FF: /* 0x162 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (354 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_63FF: /* 0x163 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (355 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_64FF: /* 0x164 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (356 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_65FF: /* 0x165 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (357 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_66FF: /* 0x166 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (358 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_67FF: /* 0x167 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (359 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_68FF: /* 0x168 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (360 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_69FF: /* 0x169 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (361 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_6AFF: /* 0x16a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (362 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_6BFF: /* 0x16b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (363 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_6CFF: /* 0x16c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (364 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_6DFF: /* 0x16d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (365 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_6EFF: /* 0x16e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (366 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_6FFF: /* 0x16f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (367 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_70FF: /* 0x170 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (368 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_71FF: /* 0x171 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (369 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_72FF: /* 0x172 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (370 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_73FF: /* 0x173 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (371 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_74FF: /* 0x174 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (372 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_75FF: /* 0x175 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (373 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_76FF: /* 0x176 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (374 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_77FF: /* 0x177 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (375 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_78FF: /* 0x178 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (376 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_79FF: /* 0x179 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (377 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_7AFF: /* 0x17a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (378 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_7BFF: /* 0x17b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (379 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_7CFF: /* 0x17c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (380 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_7DFF: /* 0x17d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (381 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_7EFF: /* 0x17e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (382 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_7FFF: /* 0x17f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (383 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_80FF: /* 0x180 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (384 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_81FF: /* 0x181 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (385 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_82FF: /* 0x182 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (386 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_83FF: /* 0x183 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (387 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_84FF: /* 0x184 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (388 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_85FF: /* 0x185 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (389 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_86FF: /* 0x186 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (390 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_87FF: /* 0x187 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (391 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_88FF: /* 0x188 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (392 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_89FF: /* 0x189 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (393 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_8AFF: /* 0x18a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (394 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_8BFF: /* 0x18b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (395 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_8CFF: /* 0x18c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (396 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_8DFF: /* 0x18d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (397 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_8EFF: /* 0x18e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (398 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_8FFF: /* 0x18f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (399 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_90FF: /* 0x190 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (400 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_91FF: /* 0x191 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (401 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_92FF: /* 0x192 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (402 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_93FF: /* 0x193 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (403 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_94FF: /* 0x194 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (404 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_95FF: /* 0x195 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (405 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_96FF: /* 0x196 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (406 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_97FF: /* 0x197 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (407 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_98FF: /* 0x198 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (408 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_99FF: /* 0x199 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (409 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_9AFF: /* 0x19a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (410 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_9BFF: /* 0x19b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (411 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_9CFF: /* 0x19c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (412 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_9DFF: /* 0x19d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (413 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_9EFF: /* 0x19e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (414 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_9FFF: /* 0x19f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (415 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A0FF: /* 0x1a0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (416 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A1FF: /* 0x1a1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (417 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A2FF: /* 0x1a2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (418 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A3FF: /* 0x1a3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (419 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A4FF: /* 0x1a4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (420 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A5FF: /* 0x1a5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (421 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A6FF: /* 0x1a6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (422 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A7FF: /* 0x1a7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (423 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A8FF: /* 0x1a8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (424 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A9FF: /* 0x1a9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (425 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_AAFF: /* 0x1aa */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (426 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_ABFF: /* 0x1ab */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (427 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_ACFF: /* 0x1ac */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (428 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_ADFF: /* 0x1ad */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (429 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_AEFF: /* 0x1ae */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (430 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_AFFF: /* 0x1af */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (431 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B0FF: /* 0x1b0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (432 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B1FF: /* 0x1b1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (433 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B2FF: /* 0x1b2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (434 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B3FF: /* 0x1b3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (435 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B4FF: /* 0x1b4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (436 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B5FF: /* 0x1b5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (437 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B6FF: /* 0x1b6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (438 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B7FF: /* 0x1b7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (439 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B8FF: /* 0x1b8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (440 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B9FF: /* 0x1b9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (441 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_BAFF: /* 0x1ba */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (442 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_BBFF: /* 0x1bb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (443 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_BCFF: /* 0x1bc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (444 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_BDFF: /* 0x1bd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (445 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_BEFF: /* 0x1be */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (446 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_BFFF: /* 0x1bf */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (447 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C0FF: /* 0x1c0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (448 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C1FF: /* 0x1c1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (449 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C2FF: /* 0x1c2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (450 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C3FF: /* 0x1c3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (451 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C4FF: /* 0x1c4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (452 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C5FF: /* 0x1c5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (453 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C6FF: /* 0x1c6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (454 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C7FF: /* 0x1c7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (455 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C8FF: /* 0x1c8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (456 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C9FF: /* 0x1c9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (457 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_CAFF: /* 0x1ca */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (458 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_CBFF: /* 0x1cb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (459 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_CCFF: /* 0x1cc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (460 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_CDFF: /* 0x1cd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (461 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_CEFF: /* 0x1ce */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (462 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_CFFF: /* 0x1cf */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (463 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D0FF: /* 0x1d0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (464 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D1FF: /* 0x1d1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (465 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D2FF: /* 0x1d2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (466 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D3FF: /* 0x1d3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (467 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D4FF: /* 0x1d4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (468 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D5FF: /* 0x1d5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (469 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D6FF: /* 0x1d6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (470 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D7FF: /* 0x1d7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (471 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D8FF: /* 0x1d8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (472 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D9FF: /* 0x1d9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (473 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_DAFF: /* 0x1da */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (474 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_DBFF: /* 0x1db */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (475 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_DCFF: /* 0x1dc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (476 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_DDFF: /* 0x1dd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (477 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_DEFF: /* 0x1de */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (478 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_DFFF: /* 0x1df */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (479 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E0FF: /* 0x1e0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (480 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E1FF: /* 0x1e1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (481 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E2FF: /* 0x1e2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (482 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E3FF: /* 0x1e3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (483 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E4FF: /* 0x1e4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (484 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E5FF: /* 0x1e5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (485 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E6FF: /* 0x1e6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (486 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E7FF: /* 0x1e7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (487 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E8FF: /* 0x1e8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (488 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E9FF: /* 0x1e9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (489 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_EAFF: /* 0x1ea */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (490 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_EBFF: /* 0x1eb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (491 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_ECFF: /* 0x1ec */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (492 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_EDFF: /* 0x1ed */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (493 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_EEFF: /* 0x1ee */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (494 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_EFFF: /* 0x1ef */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (495 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F0FF: /* 0x1f0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (496 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F1FF: /* 0x1f1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (497 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F2FF: /* 0x1f2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (498 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F3FF: /* 0x1f3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (499 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F4FF: /* 0x1f4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (500 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F5FF: /* 0x1f5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (501 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F6FF: /* 0x1f6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (502 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F7FF: /* 0x1f7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (503 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F8FF: /* 0x1f8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (504 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F9FF: /* 0x1f9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (505 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_FAFF: /* 0x1fa */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (506 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_FBFF: /* 0x1fb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (507 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_FCFF: /* 0x1fc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (508 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_FDFF: /* 0x1fd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (509 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_FEFF: /* 0x1fe */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (510 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (511 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+ .balign 64
+ .size dvmAsmAltInstructionStart, .-dvmAsmAltInstructionStart
+ .global dvmAsmAltInstructionEnd
+dvmAsmAltInstructionEnd:
/* File: armv5te/footer.S */
/*
@@ -13251,7 +20423,7 @@
EXPORT_PC()
mov r0, #0
str r0, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
FETCH_INST()
GET_INST_OPCODE(ip)
GOTO_OPCODE(ip)
@@ -13273,7 +20445,7 @@
mov rPC,r0
EXPORT_PC()
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
mov r2,#kJitSingleStep @ Ask for single step and then revert
str r2,[rSELF,#offThread_jitState]
mov r1,#1 @ set changeInterp to bail to debug interp
@@ -13322,7 +20494,7 @@
/* No translation, so request one if profiling isn't disabled*/
2:
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
GET_JIT_PROF_TABLE(r0)
FETCH_INST()
cmp r0, #0
@@ -13383,7 +20555,7 @@
cmp r0,#0
bxne r0 @ continue native execution if so
EXPORT_PC()
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
FETCH_INST()
GET_INST_OPCODE(ip) @ extract opcode from rINST
GOTO_OPCODE(ip) @ jump to next instruction
@@ -13414,7 +20586,7 @@
*/
toInterpreter:
EXPORT_PC()
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
FETCH_INST()
GET_JIT_PROF_TABLE(r0)
@ NOTE: intended fallthrough
@@ -13531,7 +20703,7 @@
1: @ exit to interpreter without check
EXPORT_PC()
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
FETCH_INST()
GET_INST_OPCODE(ip)
GOTO_OPCODE(ip)
diff --git a/vm/mterp/out/InterpAsm-armv5te.S b/vm/mterp/out/InterpAsm-armv5te.S
index 18f19be..90d8932 100644
--- a/vm/mterp/out/InterpAsm-armv5te.S
+++ b/vm/mterp/out/InterpAsm-armv5te.S
@@ -290,7 +290,7 @@
mov rSELF, r0 @ set rSELF
ldr r1, [r0, #offThread_entryPoint] @ enum is 4 bytes in aapcs-EABI
LOAD_PC_FP_FROM_SELF() @ load rPC and rFP from "thread"
- adr rIBASE, dvmAsmInstructionStart @ set rIBASE
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ set rIBASE
cmp r1, #kInterpEntryInstr @ usual case?
bne .Lnot_instr @ no, handle it
@@ -8069,7 +8069,7 @@
.balign 64
.L_OP_DISPATCH_FF: /* 0xff */
/* File: armv5te/OP_DISPATCH_FF.S */
- mov ip, rINST, lsr #8 @ r9<- extended opcode
+ mov ip, rINST, lsr #8 @ ip<- extended opcode
add ip, ip, #256 @ add offset for extended opcodes
GOTO_OPCODE(ip) @ go to proper extended handler
@@ -10898,9 +10898,8 @@
bl dvmThrowVerificationError @ always throws
b common_exceptionThrown @ handle exception
-
.balign 64
- .size .L_OP_NOP, .-.L_OP_NOP
+ .size dvmAsmInstructionStart, .-dvmAsmInstructionStart
.global dvmAsmInstructionEnd
dvmAsmInstructionEnd:
@@ -13615,6 +13614,7179 @@
.global dvmAsmSisterEnd
dvmAsmSisterEnd:
+
+ .global dvmAsmAltInstructionStart
+ .type dvmAsmAltInstructionStart, %function
+dvmAsmAltInstructionStart:
+ .text
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NOP: /* 0x00 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (0 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE: /* 0x01 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (1 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_FROM16: /* 0x02 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (2 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_16: /* 0x03 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (3 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_WIDE: /* 0x04 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (4 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_WIDE_FROM16: /* 0x05 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (5 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_WIDE_16: /* 0x06 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (6 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_OBJECT: /* 0x07 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (7 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_OBJECT_FROM16: /* 0x08 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (8 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_OBJECT_16: /* 0x09 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (9 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_RESULT: /* 0x0a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (10 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_RESULT_WIDE: /* 0x0b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (11 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_RESULT_OBJECT: /* 0x0c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (12 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_EXCEPTION: /* 0x0d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (13 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_RETURN_VOID: /* 0x0e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (14 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_RETURN: /* 0x0f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (15 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_RETURN_WIDE: /* 0x10 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (16 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_RETURN_OBJECT: /* 0x11 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (17 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_4: /* 0x12 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (18 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_16: /* 0x13 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (19 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST: /* 0x14 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (20 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_HIGH16: /* 0x15 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (21 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_WIDE_16: /* 0x16 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (22 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_WIDE_32: /* 0x17 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (23 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_WIDE: /* 0x18 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (24 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_WIDE_HIGH16: /* 0x19 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (25 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_STRING: /* 0x1a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (26 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_STRING_JUMBO: /* 0x1b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (27 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_CLASS: /* 0x1c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (28 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MONITOR_ENTER: /* 0x1d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (29 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MONITOR_EXIT: /* 0x1e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (30 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CHECK_CAST: /* 0x1f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (31 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INSTANCE_OF: /* 0x20 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (32 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ARRAY_LENGTH: /* 0x21 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (33 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEW_INSTANCE: /* 0x22 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (34 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEW_ARRAY: /* 0x23 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (35 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_FILLED_NEW_ARRAY: /* 0x24 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (36 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (37 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_FILL_ARRAY_DATA: /* 0x26 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (38 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_THROW: /* 0x27 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (39 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_GOTO: /* 0x28 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (40 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_GOTO_16: /* 0x29 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (41 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_GOTO_32: /* 0x2a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (42 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_PACKED_SWITCH: /* 0x2b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (43 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPARSE_SWITCH: /* 0x2c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (44 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CMPL_FLOAT: /* 0x2d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (45 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CMPG_FLOAT: /* 0x2e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (46 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CMPL_DOUBLE: /* 0x2f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (47 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CMPG_DOUBLE: /* 0x30 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (48 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CMP_LONG: /* 0x31 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (49 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_EQ: /* 0x32 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (50 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_NE: /* 0x33 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (51 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_LT: /* 0x34 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (52 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_GE: /* 0x35 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (53 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_GT: /* 0x36 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (54 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_LE: /* 0x37 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (55 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_EQZ: /* 0x38 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (56 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_NEZ: /* 0x39 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (57 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_LTZ: /* 0x3a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (58 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_GEZ: /* 0x3b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (59 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_GTZ: /* 0x3c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (60 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_LEZ: /* 0x3d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (61 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3E: /* 0x3e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (62 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3F: /* 0x3f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (63 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_40: /* 0x40 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (64 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_41: /* 0x41 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (65 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_42: /* 0x42 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (66 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_43: /* 0x43 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (67 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AGET: /* 0x44 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (68 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AGET_WIDE: /* 0x45 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (69 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AGET_OBJECT: /* 0x46 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (70 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AGET_BOOLEAN: /* 0x47 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (71 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AGET_BYTE: /* 0x48 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (72 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AGET_CHAR: /* 0x49 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (73 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AGET_SHORT: /* 0x4a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (74 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_APUT: /* 0x4b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (75 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_APUT_WIDE: /* 0x4c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (76 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_APUT_OBJECT: /* 0x4d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (77 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_APUT_BOOLEAN: /* 0x4e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (78 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_APUT_BYTE: /* 0x4f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (79 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_APUT_CHAR: /* 0x50 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (80 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_APUT_SHORT: /* 0x51 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (81 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET: /* 0x52 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (82 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_WIDE: /* 0x53 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (83 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_OBJECT: /* 0x54 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (84 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_BOOLEAN: /* 0x55 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (85 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_BYTE: /* 0x56 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (86 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_CHAR: /* 0x57 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (87 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_SHORT: /* 0x58 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (88 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT: /* 0x59 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (89 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_WIDE: /* 0x5a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (90 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_OBJECT: /* 0x5b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (91 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_BOOLEAN: /* 0x5c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (92 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_BYTE: /* 0x5d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (93 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_CHAR: /* 0x5e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (94 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_SHORT: /* 0x5f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (95 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET: /* 0x60 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (96 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_WIDE: /* 0x61 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (97 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_OBJECT: /* 0x62 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (98 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_BOOLEAN: /* 0x63 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (99 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_BYTE: /* 0x64 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (100 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_CHAR: /* 0x65 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (101 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_SHORT: /* 0x66 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (102 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT: /* 0x67 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (103 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_WIDE: /* 0x68 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (104 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_OBJECT: /* 0x69 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (105 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_BOOLEAN: /* 0x6a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (106 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_BYTE: /* 0x6b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (107 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_CHAR: /* 0x6c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (108 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_SHORT: /* 0x6d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (109 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_VIRTUAL: /* 0x6e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (110 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_SUPER: /* 0x6f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (111 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_DIRECT: /* 0x70 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (112 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_STATIC: /* 0x71 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (113 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_INTERFACE: /* 0x72 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (114 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_73: /* 0x73 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (115 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (116 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_SUPER_RANGE: /* 0x75 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (117 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_DIRECT_RANGE: /* 0x76 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (118 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_STATIC_RANGE: /* 0x77 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (119 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (120 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_79: /* 0x79 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (121 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_7A: /* 0x7a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (122 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEG_INT: /* 0x7b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (123 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NOT_INT: /* 0x7c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (124 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEG_LONG: /* 0x7d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (125 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NOT_LONG: /* 0x7e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (126 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEG_FLOAT: /* 0x7f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (127 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEG_DOUBLE: /* 0x80 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (128 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INT_TO_LONG: /* 0x81 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (129 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INT_TO_FLOAT: /* 0x82 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (130 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INT_TO_DOUBLE: /* 0x83 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (131 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_LONG_TO_INT: /* 0x84 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (132 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_LONG_TO_FLOAT: /* 0x85 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (133 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_LONG_TO_DOUBLE: /* 0x86 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (134 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_FLOAT_TO_INT: /* 0x87 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (135 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_FLOAT_TO_LONG: /* 0x88 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (136 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_FLOAT_TO_DOUBLE: /* 0x89 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (137 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DOUBLE_TO_INT: /* 0x8a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (138 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DOUBLE_TO_LONG: /* 0x8b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (139 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DOUBLE_TO_FLOAT: /* 0x8c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (140 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INT_TO_BYTE: /* 0x8d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (141 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INT_TO_CHAR: /* 0x8e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (142 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INT_TO_SHORT: /* 0x8f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (143 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_INT: /* 0x90 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (144 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_INT: /* 0x91 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (145 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_INT: /* 0x92 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (146 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_INT: /* 0x93 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (147 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_INT: /* 0x94 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (148 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AND_INT: /* 0x95 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (149 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_OR_INT: /* 0x96 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (150 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_XOR_INT: /* 0x97 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (151 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHL_INT: /* 0x98 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (152 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHR_INT: /* 0x99 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (153 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_USHR_INT: /* 0x9a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (154 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_LONG: /* 0x9b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (155 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_LONG: /* 0x9c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (156 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_LONG: /* 0x9d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (157 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_LONG: /* 0x9e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (158 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_LONG: /* 0x9f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (159 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AND_LONG: /* 0xa0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (160 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_OR_LONG: /* 0xa1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (161 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_XOR_LONG: /* 0xa2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (162 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHL_LONG: /* 0xa3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (163 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHR_LONG: /* 0xa4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (164 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_USHR_LONG: /* 0xa5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (165 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_FLOAT: /* 0xa6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (166 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_FLOAT: /* 0xa7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (167 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_FLOAT: /* 0xa8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (168 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_FLOAT: /* 0xa9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (169 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_FLOAT: /* 0xaa */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (170 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_DOUBLE: /* 0xab */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (171 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_DOUBLE: /* 0xac */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (172 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_DOUBLE: /* 0xad */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (173 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_DOUBLE: /* 0xae */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (174 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_DOUBLE: /* 0xaf */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (175 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_INT_2ADDR: /* 0xb0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (176 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_INT_2ADDR: /* 0xb1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (177 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_INT_2ADDR: /* 0xb2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (178 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_INT_2ADDR: /* 0xb3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (179 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_INT_2ADDR: /* 0xb4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (180 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AND_INT_2ADDR: /* 0xb5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (181 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_OR_INT_2ADDR: /* 0xb6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (182 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_XOR_INT_2ADDR: /* 0xb7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (183 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHL_INT_2ADDR: /* 0xb8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (184 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHR_INT_2ADDR: /* 0xb9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (185 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_USHR_INT_2ADDR: /* 0xba */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (186 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_LONG_2ADDR: /* 0xbb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (187 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_LONG_2ADDR: /* 0xbc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (188 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_LONG_2ADDR: /* 0xbd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (189 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_LONG_2ADDR: /* 0xbe */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (190 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_LONG_2ADDR: /* 0xbf */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (191 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AND_LONG_2ADDR: /* 0xc0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (192 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_OR_LONG_2ADDR: /* 0xc1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (193 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_XOR_LONG_2ADDR: /* 0xc2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (194 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHL_LONG_2ADDR: /* 0xc3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (195 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHR_LONG_2ADDR: /* 0xc4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (196 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_USHR_LONG_2ADDR: /* 0xc5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (197 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_FLOAT_2ADDR: /* 0xc6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (198 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_FLOAT_2ADDR: /* 0xc7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (199 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_FLOAT_2ADDR: /* 0xc8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (200 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_FLOAT_2ADDR: /* 0xc9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (201 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_FLOAT_2ADDR: /* 0xca */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (202 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_DOUBLE_2ADDR: /* 0xcb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (203 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_DOUBLE_2ADDR: /* 0xcc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (204 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_DOUBLE_2ADDR: /* 0xcd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (205 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_DOUBLE_2ADDR: /* 0xce */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (206 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_DOUBLE_2ADDR: /* 0xcf */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (207 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_INT_LIT16: /* 0xd0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (208 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_RSUB_INT: /* 0xd1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (209 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_INT_LIT16: /* 0xd2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (210 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_INT_LIT16: /* 0xd3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (211 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_INT_LIT16: /* 0xd4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (212 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AND_INT_LIT16: /* 0xd5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (213 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_OR_INT_LIT16: /* 0xd6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (214 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_XOR_INT_LIT16: /* 0xd7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (215 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_INT_LIT8: /* 0xd8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (216 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_RSUB_INT_LIT8: /* 0xd9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (217 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_INT_LIT8: /* 0xda */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (218 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_INT_LIT8: /* 0xdb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (219 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_INT_LIT8: /* 0xdc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (220 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AND_INT_LIT8: /* 0xdd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (221 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_OR_INT_LIT8: /* 0xde */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (222 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_XOR_INT_LIT8: /* 0xdf */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (223 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHL_INT_LIT8: /* 0xe0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (224 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHR_INT_LIT8: /* 0xe1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (225 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_USHR_INT_LIT8: /* 0xe2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (226 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_VOLATILE: /* 0xe3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (227 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_VOLATILE: /* 0xe4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (228 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_VOLATILE: /* 0xe5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (229 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_VOLATILE: /* 0xe6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (230 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (231 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_WIDE_VOLATILE: /* 0xe8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (232 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (233 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_WIDE_VOLATILE: /* 0xea */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (234 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_WIDE_VOLATILE: /* 0xeb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (235 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_BREAKPOINT: /* 0xec */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (236 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_THROW_VERIFICATION_ERROR: /* 0xed */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (237 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_EXECUTE_INLINE: /* 0xee */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (238 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_EXECUTE_INLINE_RANGE: /* 0xef */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (239 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_OBJECT_INIT: /* 0xf0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (240 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_RETURN_VOID_BARRIER: /* 0xf1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (241 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_QUICK: /* 0xf2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (242 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_WIDE_QUICK: /* 0xf3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (243 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_OBJECT_QUICK: /* 0xf4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (244 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_QUICK: /* 0xf5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (245 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_WIDE_QUICK: /* 0xf6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (246 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_OBJECT_QUICK: /* 0xf7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (247 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (248 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (249 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_SUPER_QUICK: /* 0xfa */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (250 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (251 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (252 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_OBJECT_VOLATILE: /* 0xfd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (253 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (254 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DISPATCH_FF: /* 0xff */
+/* File: armv5te/ALT_OP_DISPATCH_FF.S */
+ mov ip, rINST, lsr #8 @ ip<- extended opcode
+ add ip, ip, #256 @ add offset for extended opcodes
+ GOTO_OPCODE(ip) @ go to proper extended handler
+
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_CLASS_JUMBO: /* 0x100 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (256 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CHECK_CAST_JUMBO: /* 0x101 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (257 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INSTANCE_OF_JUMBO: /* 0x102 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (258 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEW_INSTANCE_JUMBO: /* 0x103 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (259 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEW_ARRAY_JUMBO: /* 0x104 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (260 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (261 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_JUMBO: /* 0x106 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (262 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_WIDE_JUMBO: /* 0x107 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (263 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_OBJECT_JUMBO: /* 0x108 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (264 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (265 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_BYTE_JUMBO: /* 0x10a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (266 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_CHAR_JUMBO: /* 0x10b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (267 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_SHORT_JUMBO: /* 0x10c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (268 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_JUMBO: /* 0x10d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (269 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_WIDE_JUMBO: /* 0x10e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (270 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_OBJECT_JUMBO: /* 0x10f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (271 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (272 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_BYTE_JUMBO: /* 0x111 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (273 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_CHAR_JUMBO: /* 0x112 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (274 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_SHORT_JUMBO: /* 0x113 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (275 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_JUMBO: /* 0x114 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (276 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_WIDE_JUMBO: /* 0x115 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (277 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_OBJECT_JUMBO: /* 0x116 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (278 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (279 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_BYTE_JUMBO: /* 0x118 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (280 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_CHAR_JUMBO: /* 0x119 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (281 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_SHORT_JUMBO: /* 0x11a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (282 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_JUMBO: /* 0x11b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (283 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_WIDE_JUMBO: /* 0x11c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (284 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_OBJECT_JUMBO: /* 0x11d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (285 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (286 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_BYTE_JUMBO: /* 0x11f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (287 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_CHAR_JUMBO: /* 0x120 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (288 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_SHORT_JUMBO: /* 0x121 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (289 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (290 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_SUPER_JUMBO: /* 0x123 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (291 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (292 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_STATIC_JUMBO: /* 0x125 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (293 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (294 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_27FF: /* 0x127 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (295 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_28FF: /* 0x128 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (296 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_29FF: /* 0x129 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (297 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_2AFF: /* 0x12a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (298 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_2BFF: /* 0x12b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (299 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_2CFF: /* 0x12c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (300 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_2DFF: /* 0x12d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (301 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_2EFF: /* 0x12e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (302 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_2FFF: /* 0x12f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (303 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_30FF: /* 0x130 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (304 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_31FF: /* 0x131 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (305 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_32FF: /* 0x132 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (306 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_33FF: /* 0x133 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (307 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_34FF: /* 0x134 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (308 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_35FF: /* 0x135 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (309 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_36FF: /* 0x136 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (310 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_37FF: /* 0x137 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (311 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_38FF: /* 0x138 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (312 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_39FF: /* 0x139 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (313 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3AFF: /* 0x13a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (314 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3BFF: /* 0x13b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (315 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3CFF: /* 0x13c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (316 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3DFF: /* 0x13d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (317 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3EFF: /* 0x13e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (318 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3FFF: /* 0x13f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (319 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_40FF: /* 0x140 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (320 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_41FF: /* 0x141 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (321 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_42FF: /* 0x142 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (322 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_43FF: /* 0x143 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (323 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_44FF: /* 0x144 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (324 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_45FF: /* 0x145 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (325 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_46FF: /* 0x146 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (326 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_47FF: /* 0x147 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (327 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_48FF: /* 0x148 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (328 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_49FF: /* 0x149 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (329 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_4AFF: /* 0x14a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (330 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_4BFF: /* 0x14b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (331 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_4CFF: /* 0x14c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (332 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_4DFF: /* 0x14d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (333 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_4EFF: /* 0x14e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (334 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_4FFF: /* 0x14f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (335 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_50FF: /* 0x150 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (336 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_51FF: /* 0x151 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (337 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_52FF: /* 0x152 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (338 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_53FF: /* 0x153 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (339 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_54FF: /* 0x154 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (340 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_55FF: /* 0x155 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (341 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_56FF: /* 0x156 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (342 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_57FF: /* 0x157 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (343 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_58FF: /* 0x158 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (344 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_59FF: /* 0x159 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (345 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_5AFF: /* 0x15a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (346 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_5BFF: /* 0x15b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (347 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_5CFF: /* 0x15c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (348 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_5DFF: /* 0x15d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (349 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_5EFF: /* 0x15e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (350 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_5FFF: /* 0x15f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (351 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_60FF: /* 0x160 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (352 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_61FF: /* 0x161 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (353 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_62FF: /* 0x162 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (354 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_63FF: /* 0x163 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (355 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_64FF: /* 0x164 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (356 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_65FF: /* 0x165 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (357 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_66FF: /* 0x166 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (358 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_67FF: /* 0x167 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (359 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_68FF: /* 0x168 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (360 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_69FF: /* 0x169 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (361 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_6AFF: /* 0x16a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (362 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_6BFF: /* 0x16b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (363 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_6CFF: /* 0x16c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (364 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_6DFF: /* 0x16d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (365 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_6EFF: /* 0x16e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (366 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_6FFF: /* 0x16f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (367 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_70FF: /* 0x170 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (368 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_71FF: /* 0x171 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (369 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_72FF: /* 0x172 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (370 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_73FF: /* 0x173 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (371 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_74FF: /* 0x174 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (372 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_75FF: /* 0x175 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (373 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_76FF: /* 0x176 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (374 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_77FF: /* 0x177 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (375 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_78FF: /* 0x178 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (376 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_79FF: /* 0x179 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (377 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_7AFF: /* 0x17a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (378 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_7BFF: /* 0x17b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (379 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_7CFF: /* 0x17c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (380 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_7DFF: /* 0x17d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (381 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_7EFF: /* 0x17e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (382 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_7FFF: /* 0x17f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (383 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_80FF: /* 0x180 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (384 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_81FF: /* 0x181 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (385 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_82FF: /* 0x182 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (386 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_83FF: /* 0x183 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (387 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_84FF: /* 0x184 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (388 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_85FF: /* 0x185 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (389 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_86FF: /* 0x186 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (390 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_87FF: /* 0x187 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (391 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_88FF: /* 0x188 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (392 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_89FF: /* 0x189 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (393 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_8AFF: /* 0x18a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (394 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_8BFF: /* 0x18b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (395 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_8CFF: /* 0x18c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (396 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_8DFF: /* 0x18d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (397 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_8EFF: /* 0x18e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (398 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_8FFF: /* 0x18f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (399 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_90FF: /* 0x190 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (400 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_91FF: /* 0x191 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (401 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_92FF: /* 0x192 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (402 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_93FF: /* 0x193 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (403 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_94FF: /* 0x194 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (404 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_95FF: /* 0x195 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (405 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_96FF: /* 0x196 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (406 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_97FF: /* 0x197 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (407 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_98FF: /* 0x198 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (408 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_99FF: /* 0x199 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (409 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_9AFF: /* 0x19a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (410 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_9BFF: /* 0x19b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (411 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_9CFF: /* 0x19c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (412 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_9DFF: /* 0x19d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (413 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_9EFF: /* 0x19e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (414 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_9FFF: /* 0x19f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (415 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A0FF: /* 0x1a0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (416 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A1FF: /* 0x1a1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (417 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A2FF: /* 0x1a2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (418 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A3FF: /* 0x1a3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (419 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A4FF: /* 0x1a4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (420 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A5FF: /* 0x1a5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (421 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A6FF: /* 0x1a6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (422 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A7FF: /* 0x1a7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (423 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A8FF: /* 0x1a8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (424 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A9FF: /* 0x1a9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (425 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_AAFF: /* 0x1aa */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (426 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_ABFF: /* 0x1ab */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (427 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_ACFF: /* 0x1ac */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (428 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_ADFF: /* 0x1ad */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (429 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_AEFF: /* 0x1ae */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (430 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_AFFF: /* 0x1af */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (431 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B0FF: /* 0x1b0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (432 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B1FF: /* 0x1b1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (433 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B2FF: /* 0x1b2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (434 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B3FF: /* 0x1b3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (435 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B4FF: /* 0x1b4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (436 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B5FF: /* 0x1b5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (437 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B6FF: /* 0x1b6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (438 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B7FF: /* 0x1b7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (439 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B8FF: /* 0x1b8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (440 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B9FF: /* 0x1b9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (441 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_BAFF: /* 0x1ba */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (442 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_BBFF: /* 0x1bb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (443 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_BCFF: /* 0x1bc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (444 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_BDFF: /* 0x1bd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (445 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_BEFF: /* 0x1be */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (446 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_BFFF: /* 0x1bf */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (447 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C0FF: /* 0x1c0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (448 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C1FF: /* 0x1c1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (449 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C2FF: /* 0x1c2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (450 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C3FF: /* 0x1c3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (451 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C4FF: /* 0x1c4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (452 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C5FF: /* 0x1c5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (453 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C6FF: /* 0x1c6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (454 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C7FF: /* 0x1c7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (455 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C8FF: /* 0x1c8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (456 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C9FF: /* 0x1c9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (457 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_CAFF: /* 0x1ca */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (458 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_CBFF: /* 0x1cb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (459 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_CCFF: /* 0x1cc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (460 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_CDFF: /* 0x1cd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (461 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_CEFF: /* 0x1ce */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (462 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_CFFF: /* 0x1cf */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (463 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D0FF: /* 0x1d0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (464 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D1FF: /* 0x1d1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (465 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D2FF: /* 0x1d2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (466 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D3FF: /* 0x1d3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (467 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D4FF: /* 0x1d4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (468 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D5FF: /* 0x1d5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (469 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D6FF: /* 0x1d6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (470 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D7FF: /* 0x1d7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (471 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D8FF: /* 0x1d8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (472 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D9FF: /* 0x1d9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (473 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_DAFF: /* 0x1da */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (474 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_DBFF: /* 0x1db */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (475 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_DCFF: /* 0x1dc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (476 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_DDFF: /* 0x1dd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (477 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_DEFF: /* 0x1de */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (478 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_DFFF: /* 0x1df */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (479 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E0FF: /* 0x1e0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (480 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E1FF: /* 0x1e1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (481 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E2FF: /* 0x1e2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (482 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E3FF: /* 0x1e3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (483 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E4FF: /* 0x1e4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (484 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E5FF: /* 0x1e5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (485 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E6FF: /* 0x1e6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (486 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E7FF: /* 0x1e7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (487 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E8FF: /* 0x1e8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (488 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E9FF: /* 0x1e9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (489 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_EAFF: /* 0x1ea */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (490 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_EBFF: /* 0x1eb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (491 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_ECFF: /* 0x1ec */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (492 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_EDFF: /* 0x1ed */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (493 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_EEFF: /* 0x1ee */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (494 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_EFFF: /* 0x1ef */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (495 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F0FF: /* 0x1f0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (496 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F1FF: /* 0x1f1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (497 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F2FF: /* 0x1f2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (498 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F3FF: /* 0x1f3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (499 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F4FF: /* 0x1f4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (500 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F5FF: /* 0x1f5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (501 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F6FF: /* 0x1f6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (502 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F7FF: /* 0x1f7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (503 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F8FF: /* 0x1f8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (504 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F9FF: /* 0x1f9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (505 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_FAFF: /* 0x1fa */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (506 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_FBFF: /* 0x1fb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (507 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_FCFF: /* 0x1fc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (508 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_FDFF: /* 0x1fd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (509 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_FEFF: /* 0x1fe */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (510 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (511 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+ .balign 64
+ .size dvmAsmAltInstructionStart, .-dvmAsmAltInstructionStart
+ .global dvmAsmAltInstructionEnd
+dvmAsmAltInstructionEnd:
/* File: armv5te/footer.S */
/*
@@ -13709,7 +20881,7 @@
EXPORT_PC()
mov r0, #0
str r0, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
FETCH_INST()
GET_INST_OPCODE(ip)
GOTO_OPCODE(ip)
@@ -13731,7 +20903,7 @@
mov rPC,r0
EXPORT_PC()
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
mov r2,#kJitSingleStep @ Ask for single step and then revert
str r2,[rSELF,#offThread_jitState]
mov r1,#1 @ set changeInterp to bail to debug interp
@@ -13780,7 +20952,7 @@
/* No translation, so request one if profiling isn't disabled*/
2:
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
GET_JIT_PROF_TABLE(r0)
FETCH_INST()
cmp r0, #0
@@ -13841,7 +21013,7 @@
cmp r0,#0
bxne r0 @ continue native execution if so
EXPORT_PC()
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
FETCH_INST()
GET_INST_OPCODE(ip) @ extract opcode from rINST
GOTO_OPCODE(ip) @ jump to next instruction
@@ -13872,7 +21044,7 @@
*/
toInterpreter:
EXPORT_PC()
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
FETCH_INST()
GET_JIT_PROF_TABLE(r0)
@ NOTE: intended fallthrough
@@ -13989,7 +21161,7 @@
1: @ exit to interpreter without check
EXPORT_PC()
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
FETCH_INST()
GET_INST_OPCODE(ip)
GOTO_OPCODE(ip)
diff --git a/vm/mterp/out/InterpAsm-armv7-a-neon.S b/vm/mterp/out/InterpAsm-armv7-a-neon.S
index 0a9a41a..0f69049 100644
--- a/vm/mterp/out/InterpAsm-armv7-a-neon.S
+++ b/vm/mterp/out/InterpAsm-armv7-a-neon.S
@@ -304,7 +304,7 @@
mov rSELF, r0 @ set rSELF
ldr r1, [r0, #offThread_entryPoint] @ enum is 4 bytes in aapcs-EABI
LOAD_PC_FP_FROM_SELF() @ load rPC and rFP from "thread"
- adr rIBASE, dvmAsmInstructionStart @ set rIBASE
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ set rIBASE
cmp r1, #kInterpEntryInstr @ usual case?
bne .Lnot_instr @ no, handle it
@@ -7701,7 +7701,7 @@
.balign 64
.L_OP_DISPATCH_FF: /* 0xff */
/* File: armv5te/OP_DISPATCH_FF.S */
- mov ip, rINST, lsr #8 @ r9<- extended opcode
+ mov ip, rINST, lsr #8 @ ip<- extended opcode
add ip, ip, #256 @ add offset for extended opcodes
GOTO_OPCODE(ip) @ go to proper extended handler
@@ -10530,9 +10530,8 @@
bl dvmThrowVerificationError @ always throws
b common_exceptionThrown @ handle exception
-
.balign 64
- .size .L_OP_NOP, .-.L_OP_NOP
+ .size dvmAsmInstructionStart, .-dvmAsmInstructionStart
.global dvmAsmInstructionEnd
dvmAsmInstructionEnd:
@@ -13095,6 +13094,7179 @@
.global dvmAsmSisterEnd
dvmAsmSisterEnd:
+
+ .global dvmAsmAltInstructionStart
+ .type dvmAsmAltInstructionStart, %function
+dvmAsmAltInstructionStart:
+ .text
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NOP: /* 0x00 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (0 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE: /* 0x01 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (1 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_FROM16: /* 0x02 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (2 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_16: /* 0x03 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (3 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_WIDE: /* 0x04 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (4 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_WIDE_FROM16: /* 0x05 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (5 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_WIDE_16: /* 0x06 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (6 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_OBJECT: /* 0x07 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (7 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_OBJECT_FROM16: /* 0x08 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (8 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_OBJECT_16: /* 0x09 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (9 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_RESULT: /* 0x0a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (10 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_RESULT_WIDE: /* 0x0b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (11 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_RESULT_OBJECT: /* 0x0c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (12 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_EXCEPTION: /* 0x0d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (13 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_RETURN_VOID: /* 0x0e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (14 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_RETURN: /* 0x0f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (15 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_RETURN_WIDE: /* 0x10 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (16 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_RETURN_OBJECT: /* 0x11 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (17 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_4: /* 0x12 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (18 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_16: /* 0x13 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (19 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST: /* 0x14 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (20 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_HIGH16: /* 0x15 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (21 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_WIDE_16: /* 0x16 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (22 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_WIDE_32: /* 0x17 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (23 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_WIDE: /* 0x18 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (24 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_WIDE_HIGH16: /* 0x19 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (25 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_STRING: /* 0x1a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (26 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_STRING_JUMBO: /* 0x1b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (27 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_CLASS: /* 0x1c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (28 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MONITOR_ENTER: /* 0x1d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (29 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MONITOR_EXIT: /* 0x1e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (30 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CHECK_CAST: /* 0x1f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (31 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INSTANCE_OF: /* 0x20 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (32 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ARRAY_LENGTH: /* 0x21 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (33 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEW_INSTANCE: /* 0x22 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (34 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEW_ARRAY: /* 0x23 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (35 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_FILLED_NEW_ARRAY: /* 0x24 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (36 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (37 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_FILL_ARRAY_DATA: /* 0x26 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (38 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_THROW: /* 0x27 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (39 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_GOTO: /* 0x28 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (40 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_GOTO_16: /* 0x29 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (41 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_GOTO_32: /* 0x2a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (42 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_PACKED_SWITCH: /* 0x2b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (43 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPARSE_SWITCH: /* 0x2c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (44 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CMPL_FLOAT: /* 0x2d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (45 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CMPG_FLOAT: /* 0x2e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (46 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CMPL_DOUBLE: /* 0x2f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (47 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CMPG_DOUBLE: /* 0x30 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (48 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CMP_LONG: /* 0x31 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (49 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_EQ: /* 0x32 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (50 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_NE: /* 0x33 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (51 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_LT: /* 0x34 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (52 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_GE: /* 0x35 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (53 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_GT: /* 0x36 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (54 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_LE: /* 0x37 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (55 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_EQZ: /* 0x38 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (56 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_NEZ: /* 0x39 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (57 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_LTZ: /* 0x3a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (58 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_GEZ: /* 0x3b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (59 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_GTZ: /* 0x3c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (60 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_LEZ: /* 0x3d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (61 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3E: /* 0x3e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (62 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3F: /* 0x3f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (63 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_40: /* 0x40 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (64 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_41: /* 0x41 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (65 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_42: /* 0x42 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (66 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_43: /* 0x43 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (67 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AGET: /* 0x44 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (68 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AGET_WIDE: /* 0x45 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (69 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AGET_OBJECT: /* 0x46 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (70 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AGET_BOOLEAN: /* 0x47 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (71 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AGET_BYTE: /* 0x48 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (72 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AGET_CHAR: /* 0x49 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (73 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AGET_SHORT: /* 0x4a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (74 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_APUT: /* 0x4b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (75 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_APUT_WIDE: /* 0x4c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (76 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_APUT_OBJECT: /* 0x4d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (77 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_APUT_BOOLEAN: /* 0x4e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (78 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_APUT_BYTE: /* 0x4f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (79 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_APUT_CHAR: /* 0x50 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (80 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_APUT_SHORT: /* 0x51 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (81 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET: /* 0x52 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (82 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_WIDE: /* 0x53 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (83 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_OBJECT: /* 0x54 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (84 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_BOOLEAN: /* 0x55 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (85 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_BYTE: /* 0x56 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (86 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_CHAR: /* 0x57 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (87 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_SHORT: /* 0x58 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (88 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT: /* 0x59 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (89 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_WIDE: /* 0x5a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (90 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_OBJECT: /* 0x5b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (91 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_BOOLEAN: /* 0x5c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (92 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_BYTE: /* 0x5d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (93 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_CHAR: /* 0x5e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (94 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_SHORT: /* 0x5f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (95 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET: /* 0x60 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (96 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_WIDE: /* 0x61 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (97 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_OBJECT: /* 0x62 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (98 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_BOOLEAN: /* 0x63 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (99 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_BYTE: /* 0x64 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (100 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_CHAR: /* 0x65 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (101 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_SHORT: /* 0x66 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (102 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT: /* 0x67 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (103 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_WIDE: /* 0x68 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (104 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_OBJECT: /* 0x69 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (105 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_BOOLEAN: /* 0x6a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (106 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_BYTE: /* 0x6b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (107 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_CHAR: /* 0x6c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (108 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_SHORT: /* 0x6d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (109 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_VIRTUAL: /* 0x6e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (110 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_SUPER: /* 0x6f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (111 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_DIRECT: /* 0x70 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (112 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_STATIC: /* 0x71 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (113 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_INTERFACE: /* 0x72 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (114 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_73: /* 0x73 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (115 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (116 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_SUPER_RANGE: /* 0x75 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (117 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_DIRECT_RANGE: /* 0x76 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (118 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_STATIC_RANGE: /* 0x77 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (119 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (120 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_79: /* 0x79 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (121 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_7A: /* 0x7a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (122 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEG_INT: /* 0x7b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (123 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NOT_INT: /* 0x7c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (124 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEG_LONG: /* 0x7d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (125 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NOT_LONG: /* 0x7e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (126 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEG_FLOAT: /* 0x7f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (127 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEG_DOUBLE: /* 0x80 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (128 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INT_TO_LONG: /* 0x81 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (129 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INT_TO_FLOAT: /* 0x82 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (130 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INT_TO_DOUBLE: /* 0x83 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (131 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_LONG_TO_INT: /* 0x84 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (132 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_LONG_TO_FLOAT: /* 0x85 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (133 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_LONG_TO_DOUBLE: /* 0x86 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (134 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_FLOAT_TO_INT: /* 0x87 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (135 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_FLOAT_TO_LONG: /* 0x88 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (136 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_FLOAT_TO_DOUBLE: /* 0x89 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (137 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DOUBLE_TO_INT: /* 0x8a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (138 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DOUBLE_TO_LONG: /* 0x8b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (139 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DOUBLE_TO_FLOAT: /* 0x8c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (140 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INT_TO_BYTE: /* 0x8d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (141 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INT_TO_CHAR: /* 0x8e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (142 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INT_TO_SHORT: /* 0x8f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (143 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_INT: /* 0x90 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (144 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_INT: /* 0x91 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (145 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_INT: /* 0x92 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (146 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_INT: /* 0x93 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (147 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_INT: /* 0x94 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (148 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AND_INT: /* 0x95 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (149 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_OR_INT: /* 0x96 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (150 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_XOR_INT: /* 0x97 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (151 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHL_INT: /* 0x98 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (152 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHR_INT: /* 0x99 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (153 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_USHR_INT: /* 0x9a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (154 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_LONG: /* 0x9b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (155 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_LONG: /* 0x9c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (156 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_LONG: /* 0x9d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (157 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_LONG: /* 0x9e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (158 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_LONG: /* 0x9f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (159 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AND_LONG: /* 0xa0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (160 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_OR_LONG: /* 0xa1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (161 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_XOR_LONG: /* 0xa2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (162 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHL_LONG: /* 0xa3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (163 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHR_LONG: /* 0xa4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (164 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_USHR_LONG: /* 0xa5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (165 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_FLOAT: /* 0xa6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (166 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_FLOAT: /* 0xa7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (167 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_FLOAT: /* 0xa8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (168 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_FLOAT: /* 0xa9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (169 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_FLOAT: /* 0xaa */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (170 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_DOUBLE: /* 0xab */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (171 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_DOUBLE: /* 0xac */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (172 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_DOUBLE: /* 0xad */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (173 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_DOUBLE: /* 0xae */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (174 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_DOUBLE: /* 0xaf */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (175 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_INT_2ADDR: /* 0xb0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (176 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_INT_2ADDR: /* 0xb1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (177 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_INT_2ADDR: /* 0xb2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (178 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_INT_2ADDR: /* 0xb3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (179 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_INT_2ADDR: /* 0xb4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (180 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AND_INT_2ADDR: /* 0xb5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (181 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_OR_INT_2ADDR: /* 0xb6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (182 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_XOR_INT_2ADDR: /* 0xb7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (183 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHL_INT_2ADDR: /* 0xb8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (184 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHR_INT_2ADDR: /* 0xb9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (185 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_USHR_INT_2ADDR: /* 0xba */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (186 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_LONG_2ADDR: /* 0xbb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (187 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_LONG_2ADDR: /* 0xbc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (188 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_LONG_2ADDR: /* 0xbd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (189 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_LONG_2ADDR: /* 0xbe */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (190 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_LONG_2ADDR: /* 0xbf */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (191 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AND_LONG_2ADDR: /* 0xc0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (192 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_OR_LONG_2ADDR: /* 0xc1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (193 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_XOR_LONG_2ADDR: /* 0xc2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (194 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHL_LONG_2ADDR: /* 0xc3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (195 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHR_LONG_2ADDR: /* 0xc4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (196 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_USHR_LONG_2ADDR: /* 0xc5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (197 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_FLOAT_2ADDR: /* 0xc6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (198 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_FLOAT_2ADDR: /* 0xc7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (199 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_FLOAT_2ADDR: /* 0xc8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (200 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_FLOAT_2ADDR: /* 0xc9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (201 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_FLOAT_2ADDR: /* 0xca */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (202 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_DOUBLE_2ADDR: /* 0xcb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (203 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_DOUBLE_2ADDR: /* 0xcc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (204 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_DOUBLE_2ADDR: /* 0xcd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (205 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_DOUBLE_2ADDR: /* 0xce */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (206 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_DOUBLE_2ADDR: /* 0xcf */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (207 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_INT_LIT16: /* 0xd0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (208 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_RSUB_INT: /* 0xd1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (209 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_INT_LIT16: /* 0xd2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (210 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_INT_LIT16: /* 0xd3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (211 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_INT_LIT16: /* 0xd4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (212 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AND_INT_LIT16: /* 0xd5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (213 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_OR_INT_LIT16: /* 0xd6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (214 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_XOR_INT_LIT16: /* 0xd7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (215 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_INT_LIT8: /* 0xd8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (216 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_RSUB_INT_LIT8: /* 0xd9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (217 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_INT_LIT8: /* 0xda */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (218 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_INT_LIT8: /* 0xdb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (219 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_INT_LIT8: /* 0xdc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (220 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AND_INT_LIT8: /* 0xdd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (221 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_OR_INT_LIT8: /* 0xde */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (222 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_XOR_INT_LIT8: /* 0xdf */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (223 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHL_INT_LIT8: /* 0xe0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (224 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHR_INT_LIT8: /* 0xe1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (225 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_USHR_INT_LIT8: /* 0xe2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (226 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_VOLATILE: /* 0xe3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (227 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_VOLATILE: /* 0xe4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (228 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_VOLATILE: /* 0xe5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (229 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_VOLATILE: /* 0xe6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (230 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (231 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_WIDE_VOLATILE: /* 0xe8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (232 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (233 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_WIDE_VOLATILE: /* 0xea */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (234 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_WIDE_VOLATILE: /* 0xeb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (235 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_BREAKPOINT: /* 0xec */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (236 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_THROW_VERIFICATION_ERROR: /* 0xed */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (237 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_EXECUTE_INLINE: /* 0xee */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (238 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_EXECUTE_INLINE_RANGE: /* 0xef */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (239 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_OBJECT_INIT: /* 0xf0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (240 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_RETURN_VOID_BARRIER: /* 0xf1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (241 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_QUICK: /* 0xf2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (242 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_WIDE_QUICK: /* 0xf3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (243 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_OBJECT_QUICK: /* 0xf4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (244 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_QUICK: /* 0xf5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (245 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_WIDE_QUICK: /* 0xf6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (246 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_OBJECT_QUICK: /* 0xf7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (247 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (248 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (249 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_SUPER_QUICK: /* 0xfa */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (250 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (251 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (252 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_OBJECT_VOLATILE: /* 0xfd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (253 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (254 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DISPATCH_FF: /* 0xff */
+/* File: armv5te/ALT_OP_DISPATCH_FF.S */
+ mov ip, rINST, lsr #8 @ ip<- extended opcode
+ add ip, ip, #256 @ add offset for extended opcodes
+ GOTO_OPCODE(ip) @ go to proper extended handler
+
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_CLASS_JUMBO: /* 0x100 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (256 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CHECK_CAST_JUMBO: /* 0x101 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (257 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INSTANCE_OF_JUMBO: /* 0x102 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (258 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEW_INSTANCE_JUMBO: /* 0x103 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (259 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEW_ARRAY_JUMBO: /* 0x104 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (260 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (261 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_JUMBO: /* 0x106 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (262 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_WIDE_JUMBO: /* 0x107 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (263 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_OBJECT_JUMBO: /* 0x108 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (264 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (265 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_BYTE_JUMBO: /* 0x10a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (266 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_CHAR_JUMBO: /* 0x10b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (267 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_SHORT_JUMBO: /* 0x10c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (268 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_JUMBO: /* 0x10d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (269 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_WIDE_JUMBO: /* 0x10e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (270 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_OBJECT_JUMBO: /* 0x10f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (271 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (272 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_BYTE_JUMBO: /* 0x111 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (273 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_CHAR_JUMBO: /* 0x112 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (274 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_SHORT_JUMBO: /* 0x113 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (275 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_JUMBO: /* 0x114 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (276 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_WIDE_JUMBO: /* 0x115 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (277 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_OBJECT_JUMBO: /* 0x116 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (278 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (279 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_BYTE_JUMBO: /* 0x118 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (280 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_CHAR_JUMBO: /* 0x119 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (281 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_SHORT_JUMBO: /* 0x11a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (282 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_JUMBO: /* 0x11b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (283 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_WIDE_JUMBO: /* 0x11c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (284 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_OBJECT_JUMBO: /* 0x11d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (285 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (286 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_BYTE_JUMBO: /* 0x11f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (287 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_CHAR_JUMBO: /* 0x120 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (288 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_SHORT_JUMBO: /* 0x121 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (289 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (290 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_SUPER_JUMBO: /* 0x123 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (291 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (292 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_STATIC_JUMBO: /* 0x125 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (293 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (294 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_27FF: /* 0x127 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (295 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_28FF: /* 0x128 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (296 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_29FF: /* 0x129 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (297 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_2AFF: /* 0x12a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (298 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_2BFF: /* 0x12b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (299 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_2CFF: /* 0x12c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (300 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_2DFF: /* 0x12d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (301 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_2EFF: /* 0x12e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (302 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_2FFF: /* 0x12f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (303 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_30FF: /* 0x130 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (304 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_31FF: /* 0x131 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (305 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_32FF: /* 0x132 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (306 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_33FF: /* 0x133 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (307 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_34FF: /* 0x134 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (308 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_35FF: /* 0x135 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (309 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_36FF: /* 0x136 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (310 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_37FF: /* 0x137 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (311 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_38FF: /* 0x138 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (312 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_39FF: /* 0x139 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (313 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3AFF: /* 0x13a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (314 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3BFF: /* 0x13b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (315 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3CFF: /* 0x13c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (316 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3DFF: /* 0x13d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (317 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3EFF: /* 0x13e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (318 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3FFF: /* 0x13f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (319 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_40FF: /* 0x140 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (320 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_41FF: /* 0x141 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (321 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_42FF: /* 0x142 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (322 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_43FF: /* 0x143 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (323 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_44FF: /* 0x144 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (324 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_45FF: /* 0x145 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (325 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_46FF: /* 0x146 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (326 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_47FF: /* 0x147 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (327 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_48FF: /* 0x148 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (328 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_49FF: /* 0x149 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (329 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_4AFF: /* 0x14a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (330 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_4BFF: /* 0x14b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (331 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_4CFF: /* 0x14c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (332 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_4DFF: /* 0x14d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (333 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_4EFF: /* 0x14e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (334 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_4FFF: /* 0x14f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (335 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_50FF: /* 0x150 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (336 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_51FF: /* 0x151 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (337 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_52FF: /* 0x152 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (338 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_53FF: /* 0x153 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (339 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_54FF: /* 0x154 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (340 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_55FF: /* 0x155 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (341 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_56FF: /* 0x156 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (342 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_57FF: /* 0x157 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (343 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_58FF: /* 0x158 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (344 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_59FF: /* 0x159 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (345 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_5AFF: /* 0x15a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (346 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_5BFF: /* 0x15b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (347 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_5CFF: /* 0x15c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (348 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_5DFF: /* 0x15d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (349 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_5EFF: /* 0x15e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (350 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_5FFF: /* 0x15f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (351 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_60FF: /* 0x160 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (352 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_61FF: /* 0x161 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (353 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_62FF: /* 0x162 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (354 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_63FF: /* 0x163 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (355 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_64FF: /* 0x164 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (356 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_65FF: /* 0x165 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (357 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_66FF: /* 0x166 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (358 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_67FF: /* 0x167 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (359 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_68FF: /* 0x168 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (360 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_69FF: /* 0x169 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (361 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_6AFF: /* 0x16a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (362 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_6BFF: /* 0x16b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (363 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_6CFF: /* 0x16c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (364 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_6DFF: /* 0x16d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (365 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_6EFF: /* 0x16e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (366 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_6FFF: /* 0x16f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (367 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_70FF: /* 0x170 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (368 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_71FF: /* 0x171 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (369 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_72FF: /* 0x172 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (370 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_73FF: /* 0x173 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (371 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_74FF: /* 0x174 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (372 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_75FF: /* 0x175 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (373 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_76FF: /* 0x176 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (374 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_77FF: /* 0x177 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (375 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_78FF: /* 0x178 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (376 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_79FF: /* 0x179 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (377 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_7AFF: /* 0x17a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (378 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_7BFF: /* 0x17b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (379 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_7CFF: /* 0x17c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (380 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_7DFF: /* 0x17d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (381 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_7EFF: /* 0x17e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (382 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_7FFF: /* 0x17f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (383 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_80FF: /* 0x180 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (384 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_81FF: /* 0x181 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (385 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_82FF: /* 0x182 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (386 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_83FF: /* 0x183 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (387 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_84FF: /* 0x184 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (388 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_85FF: /* 0x185 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (389 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_86FF: /* 0x186 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (390 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_87FF: /* 0x187 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (391 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_88FF: /* 0x188 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (392 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_89FF: /* 0x189 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (393 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_8AFF: /* 0x18a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (394 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_8BFF: /* 0x18b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (395 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_8CFF: /* 0x18c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (396 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_8DFF: /* 0x18d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (397 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_8EFF: /* 0x18e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (398 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_8FFF: /* 0x18f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (399 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_90FF: /* 0x190 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (400 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_91FF: /* 0x191 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (401 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_92FF: /* 0x192 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (402 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_93FF: /* 0x193 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (403 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_94FF: /* 0x194 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (404 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_95FF: /* 0x195 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (405 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_96FF: /* 0x196 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (406 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_97FF: /* 0x197 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (407 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_98FF: /* 0x198 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (408 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_99FF: /* 0x199 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (409 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_9AFF: /* 0x19a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (410 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_9BFF: /* 0x19b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (411 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_9CFF: /* 0x19c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (412 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_9DFF: /* 0x19d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (413 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_9EFF: /* 0x19e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (414 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_9FFF: /* 0x19f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (415 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A0FF: /* 0x1a0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (416 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A1FF: /* 0x1a1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (417 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A2FF: /* 0x1a2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (418 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A3FF: /* 0x1a3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (419 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A4FF: /* 0x1a4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (420 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A5FF: /* 0x1a5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (421 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A6FF: /* 0x1a6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (422 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A7FF: /* 0x1a7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (423 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A8FF: /* 0x1a8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (424 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A9FF: /* 0x1a9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (425 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_AAFF: /* 0x1aa */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (426 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_ABFF: /* 0x1ab */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (427 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_ACFF: /* 0x1ac */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (428 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_ADFF: /* 0x1ad */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (429 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_AEFF: /* 0x1ae */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (430 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_AFFF: /* 0x1af */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (431 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B0FF: /* 0x1b0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (432 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B1FF: /* 0x1b1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (433 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B2FF: /* 0x1b2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (434 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B3FF: /* 0x1b3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (435 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B4FF: /* 0x1b4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (436 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B5FF: /* 0x1b5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (437 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B6FF: /* 0x1b6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (438 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B7FF: /* 0x1b7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (439 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B8FF: /* 0x1b8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (440 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B9FF: /* 0x1b9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (441 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_BAFF: /* 0x1ba */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (442 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_BBFF: /* 0x1bb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (443 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_BCFF: /* 0x1bc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (444 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_BDFF: /* 0x1bd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (445 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_BEFF: /* 0x1be */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (446 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_BFFF: /* 0x1bf */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (447 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C0FF: /* 0x1c0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (448 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C1FF: /* 0x1c1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (449 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C2FF: /* 0x1c2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (450 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C3FF: /* 0x1c3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (451 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C4FF: /* 0x1c4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (452 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C5FF: /* 0x1c5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (453 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C6FF: /* 0x1c6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (454 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C7FF: /* 0x1c7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (455 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C8FF: /* 0x1c8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (456 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C9FF: /* 0x1c9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (457 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_CAFF: /* 0x1ca */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (458 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_CBFF: /* 0x1cb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (459 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_CCFF: /* 0x1cc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (460 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_CDFF: /* 0x1cd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (461 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_CEFF: /* 0x1ce */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (462 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_CFFF: /* 0x1cf */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (463 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D0FF: /* 0x1d0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (464 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D1FF: /* 0x1d1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (465 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D2FF: /* 0x1d2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (466 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D3FF: /* 0x1d3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (467 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D4FF: /* 0x1d4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (468 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D5FF: /* 0x1d5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (469 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D6FF: /* 0x1d6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (470 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D7FF: /* 0x1d7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (471 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D8FF: /* 0x1d8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (472 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D9FF: /* 0x1d9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (473 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_DAFF: /* 0x1da */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (474 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_DBFF: /* 0x1db */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (475 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_DCFF: /* 0x1dc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (476 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_DDFF: /* 0x1dd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (477 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_DEFF: /* 0x1de */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (478 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_DFFF: /* 0x1df */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (479 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E0FF: /* 0x1e0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (480 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E1FF: /* 0x1e1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (481 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E2FF: /* 0x1e2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (482 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E3FF: /* 0x1e3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (483 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E4FF: /* 0x1e4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (484 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E5FF: /* 0x1e5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (485 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E6FF: /* 0x1e6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (486 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E7FF: /* 0x1e7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (487 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E8FF: /* 0x1e8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (488 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E9FF: /* 0x1e9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (489 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_EAFF: /* 0x1ea */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (490 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_EBFF: /* 0x1eb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (491 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_ECFF: /* 0x1ec */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (492 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_EDFF: /* 0x1ed */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (493 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_EEFF: /* 0x1ee */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (494 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_EFFF: /* 0x1ef */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (495 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F0FF: /* 0x1f0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (496 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F1FF: /* 0x1f1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (497 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F2FF: /* 0x1f2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (498 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F3FF: /* 0x1f3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (499 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F4FF: /* 0x1f4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (500 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F5FF: /* 0x1f5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (501 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F6FF: /* 0x1f6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (502 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F7FF: /* 0x1f7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (503 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F8FF: /* 0x1f8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (504 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F9FF: /* 0x1f9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (505 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_FAFF: /* 0x1fa */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (506 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_FBFF: /* 0x1fb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (507 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_FCFF: /* 0x1fc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (508 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_FDFF: /* 0x1fd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (509 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_FEFF: /* 0x1fe */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (510 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (511 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+ .balign 64
+ .size dvmAsmAltInstructionStart, .-dvmAsmAltInstructionStart
+ .global dvmAsmAltInstructionEnd
+dvmAsmAltInstructionEnd:
/* File: armv5te/footer.S */
/*
@@ -13189,7 +20361,7 @@
EXPORT_PC()
mov r0, #0
str r0, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
FETCH_INST()
GET_INST_OPCODE(ip)
GOTO_OPCODE(ip)
@@ -13211,7 +20383,7 @@
mov rPC,r0
EXPORT_PC()
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
mov r2,#kJitSingleStep @ Ask for single step and then revert
str r2,[rSELF,#offThread_jitState]
mov r1,#1 @ set changeInterp to bail to debug interp
@@ -13260,7 +20432,7 @@
/* No translation, so request one if profiling isn't disabled*/
2:
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
GET_JIT_PROF_TABLE(r0)
FETCH_INST()
cmp r0, #0
@@ -13321,7 +20493,7 @@
cmp r0,#0
bxne r0 @ continue native execution if so
EXPORT_PC()
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
FETCH_INST()
GET_INST_OPCODE(ip) @ extract opcode from rINST
GOTO_OPCODE(ip) @ jump to next instruction
@@ -13352,7 +20524,7 @@
*/
toInterpreter:
EXPORT_PC()
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
FETCH_INST()
GET_JIT_PROF_TABLE(r0)
@ NOTE: intended fallthrough
@@ -13469,7 +20641,7 @@
1: @ exit to interpreter without check
EXPORT_PC()
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
FETCH_INST()
GET_INST_OPCODE(ip)
GOTO_OPCODE(ip)
diff --git a/vm/mterp/out/InterpAsm-armv7-a.S b/vm/mterp/out/InterpAsm-armv7-a.S
index c2e501e..fd218ea 100644
--- a/vm/mterp/out/InterpAsm-armv7-a.S
+++ b/vm/mterp/out/InterpAsm-armv7-a.S
@@ -304,7 +304,7 @@
mov rSELF, r0 @ set rSELF
ldr r1, [r0, #offThread_entryPoint] @ enum is 4 bytes in aapcs-EABI
LOAD_PC_FP_FROM_SELF() @ load rPC and rFP from "thread"
- adr rIBASE, dvmAsmInstructionStart @ set rIBASE
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ set rIBASE
cmp r1, #kInterpEntryInstr @ usual case?
bne .Lnot_instr @ no, handle it
@@ -7701,7 +7701,7 @@
.balign 64
.L_OP_DISPATCH_FF: /* 0xff */
/* File: armv5te/OP_DISPATCH_FF.S */
- mov ip, rINST, lsr #8 @ r9<- extended opcode
+ mov ip, rINST, lsr #8 @ ip<- extended opcode
add ip, ip, #256 @ add offset for extended opcodes
GOTO_OPCODE(ip) @ go to proper extended handler
@@ -10530,9 +10530,8 @@
bl dvmThrowVerificationError @ always throws
b common_exceptionThrown @ handle exception
-
.balign 64
- .size .L_OP_NOP, .-.L_OP_NOP
+ .size dvmAsmInstructionStart, .-dvmAsmInstructionStart
.global dvmAsmInstructionEnd
dvmAsmInstructionEnd:
@@ -13095,6 +13094,7179 @@
.global dvmAsmSisterEnd
dvmAsmSisterEnd:
+
+ .global dvmAsmAltInstructionStart
+ .type dvmAsmAltInstructionStart, %function
+dvmAsmAltInstructionStart:
+ .text
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NOP: /* 0x00 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (0 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE: /* 0x01 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (1 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_FROM16: /* 0x02 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (2 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_16: /* 0x03 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (3 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_WIDE: /* 0x04 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (4 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_WIDE_FROM16: /* 0x05 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (5 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_WIDE_16: /* 0x06 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (6 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_OBJECT: /* 0x07 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (7 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_OBJECT_FROM16: /* 0x08 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (8 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_OBJECT_16: /* 0x09 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (9 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_RESULT: /* 0x0a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (10 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_RESULT_WIDE: /* 0x0b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (11 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_RESULT_OBJECT: /* 0x0c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (12 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MOVE_EXCEPTION: /* 0x0d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (13 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_RETURN_VOID: /* 0x0e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (14 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_RETURN: /* 0x0f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (15 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_RETURN_WIDE: /* 0x10 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (16 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_RETURN_OBJECT: /* 0x11 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (17 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_4: /* 0x12 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (18 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_16: /* 0x13 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (19 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST: /* 0x14 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (20 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_HIGH16: /* 0x15 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (21 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_WIDE_16: /* 0x16 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (22 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_WIDE_32: /* 0x17 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (23 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_WIDE: /* 0x18 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (24 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_WIDE_HIGH16: /* 0x19 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (25 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_STRING: /* 0x1a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (26 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_STRING_JUMBO: /* 0x1b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (27 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_CLASS: /* 0x1c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (28 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MONITOR_ENTER: /* 0x1d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (29 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MONITOR_EXIT: /* 0x1e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (30 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CHECK_CAST: /* 0x1f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (31 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INSTANCE_OF: /* 0x20 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (32 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ARRAY_LENGTH: /* 0x21 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (33 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEW_INSTANCE: /* 0x22 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (34 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEW_ARRAY: /* 0x23 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (35 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_FILLED_NEW_ARRAY: /* 0x24 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (36 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (37 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_FILL_ARRAY_DATA: /* 0x26 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (38 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_THROW: /* 0x27 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (39 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_GOTO: /* 0x28 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (40 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_GOTO_16: /* 0x29 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (41 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_GOTO_32: /* 0x2a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (42 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_PACKED_SWITCH: /* 0x2b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (43 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPARSE_SWITCH: /* 0x2c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (44 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CMPL_FLOAT: /* 0x2d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (45 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CMPG_FLOAT: /* 0x2e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (46 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CMPL_DOUBLE: /* 0x2f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (47 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CMPG_DOUBLE: /* 0x30 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (48 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CMP_LONG: /* 0x31 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (49 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_EQ: /* 0x32 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (50 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_NE: /* 0x33 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (51 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_LT: /* 0x34 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (52 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_GE: /* 0x35 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (53 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_GT: /* 0x36 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (54 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_LE: /* 0x37 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (55 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_EQZ: /* 0x38 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (56 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_NEZ: /* 0x39 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (57 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_LTZ: /* 0x3a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (58 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_GEZ: /* 0x3b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (59 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_GTZ: /* 0x3c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (60 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IF_LEZ: /* 0x3d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (61 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3E: /* 0x3e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (62 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3F: /* 0x3f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (63 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_40: /* 0x40 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (64 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_41: /* 0x41 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (65 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_42: /* 0x42 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (66 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_43: /* 0x43 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (67 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AGET: /* 0x44 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (68 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AGET_WIDE: /* 0x45 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (69 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AGET_OBJECT: /* 0x46 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (70 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AGET_BOOLEAN: /* 0x47 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (71 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AGET_BYTE: /* 0x48 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (72 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AGET_CHAR: /* 0x49 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (73 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AGET_SHORT: /* 0x4a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (74 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_APUT: /* 0x4b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (75 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_APUT_WIDE: /* 0x4c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (76 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_APUT_OBJECT: /* 0x4d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (77 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_APUT_BOOLEAN: /* 0x4e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (78 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_APUT_BYTE: /* 0x4f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (79 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_APUT_CHAR: /* 0x50 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (80 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_APUT_SHORT: /* 0x51 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (81 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET: /* 0x52 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (82 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_WIDE: /* 0x53 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (83 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_OBJECT: /* 0x54 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (84 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_BOOLEAN: /* 0x55 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (85 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_BYTE: /* 0x56 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (86 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_CHAR: /* 0x57 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (87 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_SHORT: /* 0x58 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (88 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT: /* 0x59 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (89 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_WIDE: /* 0x5a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (90 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_OBJECT: /* 0x5b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (91 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_BOOLEAN: /* 0x5c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (92 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_BYTE: /* 0x5d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (93 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_CHAR: /* 0x5e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (94 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_SHORT: /* 0x5f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (95 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET: /* 0x60 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (96 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_WIDE: /* 0x61 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (97 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_OBJECT: /* 0x62 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (98 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_BOOLEAN: /* 0x63 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (99 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_BYTE: /* 0x64 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (100 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_CHAR: /* 0x65 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (101 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_SHORT: /* 0x66 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (102 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT: /* 0x67 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (103 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_WIDE: /* 0x68 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (104 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_OBJECT: /* 0x69 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (105 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_BOOLEAN: /* 0x6a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (106 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_BYTE: /* 0x6b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (107 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_CHAR: /* 0x6c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (108 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_SHORT: /* 0x6d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (109 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_VIRTUAL: /* 0x6e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (110 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_SUPER: /* 0x6f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (111 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_DIRECT: /* 0x70 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (112 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_STATIC: /* 0x71 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (113 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_INTERFACE: /* 0x72 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (114 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_73: /* 0x73 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (115 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (116 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_SUPER_RANGE: /* 0x75 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (117 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_DIRECT_RANGE: /* 0x76 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (118 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_STATIC_RANGE: /* 0x77 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (119 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (120 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_79: /* 0x79 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (121 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_7A: /* 0x7a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (122 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEG_INT: /* 0x7b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (123 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NOT_INT: /* 0x7c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (124 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEG_LONG: /* 0x7d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (125 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NOT_LONG: /* 0x7e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (126 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEG_FLOAT: /* 0x7f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (127 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEG_DOUBLE: /* 0x80 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (128 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INT_TO_LONG: /* 0x81 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (129 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INT_TO_FLOAT: /* 0x82 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (130 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INT_TO_DOUBLE: /* 0x83 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (131 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_LONG_TO_INT: /* 0x84 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (132 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_LONG_TO_FLOAT: /* 0x85 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (133 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_LONG_TO_DOUBLE: /* 0x86 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (134 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_FLOAT_TO_INT: /* 0x87 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (135 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_FLOAT_TO_LONG: /* 0x88 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (136 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_FLOAT_TO_DOUBLE: /* 0x89 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (137 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DOUBLE_TO_INT: /* 0x8a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (138 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DOUBLE_TO_LONG: /* 0x8b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (139 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DOUBLE_TO_FLOAT: /* 0x8c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (140 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INT_TO_BYTE: /* 0x8d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (141 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INT_TO_CHAR: /* 0x8e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (142 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INT_TO_SHORT: /* 0x8f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (143 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_INT: /* 0x90 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (144 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_INT: /* 0x91 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (145 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_INT: /* 0x92 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (146 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_INT: /* 0x93 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (147 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_INT: /* 0x94 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (148 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AND_INT: /* 0x95 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (149 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_OR_INT: /* 0x96 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (150 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_XOR_INT: /* 0x97 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (151 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHL_INT: /* 0x98 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (152 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHR_INT: /* 0x99 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (153 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_USHR_INT: /* 0x9a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (154 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_LONG: /* 0x9b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (155 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_LONG: /* 0x9c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (156 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_LONG: /* 0x9d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (157 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_LONG: /* 0x9e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (158 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_LONG: /* 0x9f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (159 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AND_LONG: /* 0xa0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (160 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_OR_LONG: /* 0xa1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (161 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_XOR_LONG: /* 0xa2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (162 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHL_LONG: /* 0xa3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (163 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHR_LONG: /* 0xa4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (164 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_USHR_LONG: /* 0xa5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (165 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_FLOAT: /* 0xa6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (166 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_FLOAT: /* 0xa7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (167 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_FLOAT: /* 0xa8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (168 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_FLOAT: /* 0xa9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (169 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_FLOAT: /* 0xaa */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (170 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_DOUBLE: /* 0xab */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (171 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_DOUBLE: /* 0xac */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (172 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_DOUBLE: /* 0xad */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (173 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_DOUBLE: /* 0xae */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (174 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_DOUBLE: /* 0xaf */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (175 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_INT_2ADDR: /* 0xb0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (176 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_INT_2ADDR: /* 0xb1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (177 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_INT_2ADDR: /* 0xb2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (178 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_INT_2ADDR: /* 0xb3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (179 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_INT_2ADDR: /* 0xb4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (180 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AND_INT_2ADDR: /* 0xb5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (181 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_OR_INT_2ADDR: /* 0xb6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (182 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_XOR_INT_2ADDR: /* 0xb7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (183 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHL_INT_2ADDR: /* 0xb8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (184 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHR_INT_2ADDR: /* 0xb9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (185 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_USHR_INT_2ADDR: /* 0xba */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (186 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_LONG_2ADDR: /* 0xbb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (187 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_LONG_2ADDR: /* 0xbc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (188 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_LONG_2ADDR: /* 0xbd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (189 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_LONG_2ADDR: /* 0xbe */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (190 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_LONG_2ADDR: /* 0xbf */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (191 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AND_LONG_2ADDR: /* 0xc0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (192 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_OR_LONG_2ADDR: /* 0xc1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (193 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_XOR_LONG_2ADDR: /* 0xc2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (194 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHL_LONG_2ADDR: /* 0xc3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (195 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHR_LONG_2ADDR: /* 0xc4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (196 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_USHR_LONG_2ADDR: /* 0xc5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (197 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_FLOAT_2ADDR: /* 0xc6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (198 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_FLOAT_2ADDR: /* 0xc7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (199 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_FLOAT_2ADDR: /* 0xc8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (200 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_FLOAT_2ADDR: /* 0xc9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (201 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_FLOAT_2ADDR: /* 0xca */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (202 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_DOUBLE_2ADDR: /* 0xcb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (203 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SUB_DOUBLE_2ADDR: /* 0xcc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (204 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_DOUBLE_2ADDR: /* 0xcd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (205 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_DOUBLE_2ADDR: /* 0xce */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (206 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_DOUBLE_2ADDR: /* 0xcf */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (207 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_INT_LIT16: /* 0xd0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (208 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_RSUB_INT: /* 0xd1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (209 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_INT_LIT16: /* 0xd2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (210 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_INT_LIT16: /* 0xd3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (211 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_INT_LIT16: /* 0xd4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (212 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AND_INT_LIT16: /* 0xd5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (213 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_OR_INT_LIT16: /* 0xd6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (214 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_XOR_INT_LIT16: /* 0xd7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (215 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_ADD_INT_LIT8: /* 0xd8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (216 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_RSUB_INT_LIT8: /* 0xd9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (217 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_MUL_INT_LIT8: /* 0xda */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (218 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DIV_INT_LIT8: /* 0xdb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (219 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_REM_INT_LIT8: /* 0xdc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (220 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_AND_INT_LIT8: /* 0xdd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (221 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_OR_INT_LIT8: /* 0xde */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (222 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_XOR_INT_LIT8: /* 0xdf */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (223 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHL_INT_LIT8: /* 0xe0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (224 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SHR_INT_LIT8: /* 0xe1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (225 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_USHR_INT_LIT8: /* 0xe2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (226 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_VOLATILE: /* 0xe3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (227 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_VOLATILE: /* 0xe4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (228 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_VOLATILE: /* 0xe5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (229 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_VOLATILE: /* 0xe6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (230 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (231 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_WIDE_VOLATILE: /* 0xe8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (232 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (233 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_WIDE_VOLATILE: /* 0xea */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (234 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_WIDE_VOLATILE: /* 0xeb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (235 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_BREAKPOINT: /* 0xec */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (236 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_THROW_VERIFICATION_ERROR: /* 0xed */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (237 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_EXECUTE_INLINE: /* 0xee */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (238 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_EXECUTE_INLINE_RANGE: /* 0xef */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (239 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_OBJECT_INIT: /* 0xf0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (240 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_RETURN_VOID_BARRIER: /* 0xf1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (241 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_QUICK: /* 0xf2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (242 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_WIDE_QUICK: /* 0xf3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (243 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_OBJECT_QUICK: /* 0xf4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (244 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_QUICK: /* 0xf5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (245 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_WIDE_QUICK: /* 0xf6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (246 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_OBJECT_QUICK: /* 0xf7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (247 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (248 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (249 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_SUPER_QUICK: /* 0xfa */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (250 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (251 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (252 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_OBJECT_VOLATILE: /* 0xfd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (253 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (254 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_DISPATCH_FF: /* 0xff */
+/* File: armv5te/ALT_OP_DISPATCH_FF.S */
+ mov ip, rINST, lsr #8 @ ip<- extended opcode
+ add ip, ip, #256 @ add offset for extended opcodes
+ GOTO_OPCODE(ip) @ go to proper extended handler
+
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CONST_CLASS_JUMBO: /* 0x100 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (256 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_CHECK_CAST_JUMBO: /* 0x101 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (257 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INSTANCE_OF_JUMBO: /* 0x102 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (258 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEW_INSTANCE_JUMBO: /* 0x103 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (259 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_NEW_ARRAY_JUMBO: /* 0x104 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (260 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (261 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_JUMBO: /* 0x106 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (262 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_WIDE_JUMBO: /* 0x107 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (263 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_OBJECT_JUMBO: /* 0x108 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (264 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (265 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_BYTE_JUMBO: /* 0x10a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (266 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_CHAR_JUMBO: /* 0x10b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (267 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IGET_SHORT_JUMBO: /* 0x10c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (268 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_JUMBO: /* 0x10d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (269 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_WIDE_JUMBO: /* 0x10e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (270 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_OBJECT_JUMBO: /* 0x10f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (271 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (272 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_BYTE_JUMBO: /* 0x111 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (273 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_CHAR_JUMBO: /* 0x112 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (274 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_IPUT_SHORT_JUMBO: /* 0x113 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (275 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_JUMBO: /* 0x114 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (276 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_WIDE_JUMBO: /* 0x115 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (277 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_OBJECT_JUMBO: /* 0x116 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (278 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (279 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_BYTE_JUMBO: /* 0x118 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (280 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_CHAR_JUMBO: /* 0x119 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (281 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SGET_SHORT_JUMBO: /* 0x11a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (282 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_JUMBO: /* 0x11b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (283 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_WIDE_JUMBO: /* 0x11c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (284 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_OBJECT_JUMBO: /* 0x11d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (285 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (286 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_BYTE_JUMBO: /* 0x11f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (287 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_CHAR_JUMBO: /* 0x120 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (288 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_SPUT_SHORT_JUMBO: /* 0x121 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (289 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (290 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_SUPER_JUMBO: /* 0x123 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (291 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (292 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_STATIC_JUMBO: /* 0x125 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (293 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (294 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_27FF: /* 0x127 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (295 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_28FF: /* 0x128 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (296 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_29FF: /* 0x129 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (297 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_2AFF: /* 0x12a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (298 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_2BFF: /* 0x12b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (299 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_2CFF: /* 0x12c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (300 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_2DFF: /* 0x12d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (301 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_2EFF: /* 0x12e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (302 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_2FFF: /* 0x12f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (303 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_30FF: /* 0x130 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (304 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_31FF: /* 0x131 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (305 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_32FF: /* 0x132 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (306 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_33FF: /* 0x133 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (307 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_34FF: /* 0x134 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (308 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_35FF: /* 0x135 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (309 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_36FF: /* 0x136 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (310 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_37FF: /* 0x137 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (311 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_38FF: /* 0x138 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (312 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_39FF: /* 0x139 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (313 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3AFF: /* 0x13a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (314 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3BFF: /* 0x13b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (315 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3CFF: /* 0x13c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (316 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3DFF: /* 0x13d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (317 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3EFF: /* 0x13e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (318 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_3FFF: /* 0x13f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (319 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_40FF: /* 0x140 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (320 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_41FF: /* 0x141 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (321 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_42FF: /* 0x142 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (322 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_43FF: /* 0x143 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (323 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_44FF: /* 0x144 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (324 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_45FF: /* 0x145 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (325 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_46FF: /* 0x146 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (326 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_47FF: /* 0x147 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (327 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_48FF: /* 0x148 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (328 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_49FF: /* 0x149 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (329 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_4AFF: /* 0x14a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (330 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_4BFF: /* 0x14b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (331 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_4CFF: /* 0x14c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (332 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_4DFF: /* 0x14d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (333 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_4EFF: /* 0x14e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (334 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_4FFF: /* 0x14f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (335 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_50FF: /* 0x150 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (336 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_51FF: /* 0x151 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (337 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_52FF: /* 0x152 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (338 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_53FF: /* 0x153 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (339 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_54FF: /* 0x154 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (340 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_55FF: /* 0x155 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (341 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_56FF: /* 0x156 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (342 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_57FF: /* 0x157 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (343 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_58FF: /* 0x158 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (344 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_59FF: /* 0x159 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (345 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_5AFF: /* 0x15a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (346 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_5BFF: /* 0x15b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (347 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_5CFF: /* 0x15c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (348 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_5DFF: /* 0x15d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (349 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_5EFF: /* 0x15e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (350 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_5FFF: /* 0x15f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (351 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_60FF: /* 0x160 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (352 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_61FF: /* 0x161 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (353 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_62FF: /* 0x162 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (354 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_63FF: /* 0x163 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (355 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_64FF: /* 0x164 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (356 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_65FF: /* 0x165 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (357 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_66FF: /* 0x166 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (358 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_67FF: /* 0x167 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (359 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_68FF: /* 0x168 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (360 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_69FF: /* 0x169 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (361 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_6AFF: /* 0x16a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (362 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_6BFF: /* 0x16b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (363 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_6CFF: /* 0x16c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (364 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_6DFF: /* 0x16d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (365 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_6EFF: /* 0x16e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (366 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_6FFF: /* 0x16f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (367 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_70FF: /* 0x170 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (368 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_71FF: /* 0x171 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (369 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_72FF: /* 0x172 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (370 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_73FF: /* 0x173 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (371 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_74FF: /* 0x174 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (372 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_75FF: /* 0x175 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (373 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_76FF: /* 0x176 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (374 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_77FF: /* 0x177 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (375 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_78FF: /* 0x178 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (376 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_79FF: /* 0x179 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (377 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_7AFF: /* 0x17a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (378 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_7BFF: /* 0x17b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (379 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_7CFF: /* 0x17c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (380 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_7DFF: /* 0x17d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (381 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_7EFF: /* 0x17e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (382 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_7FFF: /* 0x17f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (383 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_80FF: /* 0x180 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (384 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_81FF: /* 0x181 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (385 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_82FF: /* 0x182 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (386 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_83FF: /* 0x183 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (387 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_84FF: /* 0x184 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (388 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_85FF: /* 0x185 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (389 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_86FF: /* 0x186 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (390 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_87FF: /* 0x187 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (391 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_88FF: /* 0x188 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (392 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_89FF: /* 0x189 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (393 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_8AFF: /* 0x18a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (394 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_8BFF: /* 0x18b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (395 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_8CFF: /* 0x18c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (396 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_8DFF: /* 0x18d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (397 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_8EFF: /* 0x18e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (398 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_8FFF: /* 0x18f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (399 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_90FF: /* 0x190 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (400 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_91FF: /* 0x191 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (401 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_92FF: /* 0x192 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (402 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_93FF: /* 0x193 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (403 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_94FF: /* 0x194 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (404 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_95FF: /* 0x195 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (405 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_96FF: /* 0x196 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (406 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_97FF: /* 0x197 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (407 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_98FF: /* 0x198 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (408 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_99FF: /* 0x199 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (409 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_9AFF: /* 0x19a */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (410 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_9BFF: /* 0x19b */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (411 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_9CFF: /* 0x19c */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (412 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_9DFF: /* 0x19d */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (413 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_9EFF: /* 0x19e */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (414 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_9FFF: /* 0x19f */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (415 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A0FF: /* 0x1a0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (416 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A1FF: /* 0x1a1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (417 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A2FF: /* 0x1a2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (418 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A3FF: /* 0x1a3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (419 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A4FF: /* 0x1a4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (420 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A5FF: /* 0x1a5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (421 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A6FF: /* 0x1a6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (422 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A7FF: /* 0x1a7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (423 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A8FF: /* 0x1a8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (424 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_A9FF: /* 0x1a9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (425 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_AAFF: /* 0x1aa */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (426 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_ABFF: /* 0x1ab */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (427 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_ACFF: /* 0x1ac */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (428 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_ADFF: /* 0x1ad */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (429 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_AEFF: /* 0x1ae */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (430 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_AFFF: /* 0x1af */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (431 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B0FF: /* 0x1b0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (432 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B1FF: /* 0x1b1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (433 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B2FF: /* 0x1b2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (434 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B3FF: /* 0x1b3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (435 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B4FF: /* 0x1b4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (436 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B5FF: /* 0x1b5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (437 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B6FF: /* 0x1b6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (438 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B7FF: /* 0x1b7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (439 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B8FF: /* 0x1b8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (440 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_B9FF: /* 0x1b9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (441 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_BAFF: /* 0x1ba */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (442 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_BBFF: /* 0x1bb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (443 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_BCFF: /* 0x1bc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (444 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_BDFF: /* 0x1bd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (445 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_BEFF: /* 0x1be */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (446 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_BFFF: /* 0x1bf */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (447 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C0FF: /* 0x1c0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (448 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C1FF: /* 0x1c1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (449 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C2FF: /* 0x1c2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (450 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C3FF: /* 0x1c3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (451 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C4FF: /* 0x1c4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (452 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C5FF: /* 0x1c5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (453 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C6FF: /* 0x1c6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (454 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C7FF: /* 0x1c7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (455 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C8FF: /* 0x1c8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (456 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_C9FF: /* 0x1c9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (457 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_CAFF: /* 0x1ca */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (458 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_CBFF: /* 0x1cb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (459 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_CCFF: /* 0x1cc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (460 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_CDFF: /* 0x1cd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (461 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_CEFF: /* 0x1ce */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (462 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_CFFF: /* 0x1cf */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (463 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D0FF: /* 0x1d0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (464 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D1FF: /* 0x1d1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (465 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D2FF: /* 0x1d2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (466 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D3FF: /* 0x1d3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (467 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D4FF: /* 0x1d4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (468 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D5FF: /* 0x1d5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (469 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D6FF: /* 0x1d6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (470 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D7FF: /* 0x1d7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (471 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D8FF: /* 0x1d8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (472 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_D9FF: /* 0x1d9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (473 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_DAFF: /* 0x1da */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (474 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_DBFF: /* 0x1db */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (475 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_DCFF: /* 0x1dc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (476 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_DDFF: /* 0x1dd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (477 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_DEFF: /* 0x1de */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (478 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_DFFF: /* 0x1df */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (479 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E0FF: /* 0x1e0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (480 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E1FF: /* 0x1e1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (481 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E2FF: /* 0x1e2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (482 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E3FF: /* 0x1e3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (483 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E4FF: /* 0x1e4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (484 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E5FF: /* 0x1e5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (485 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E6FF: /* 0x1e6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (486 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E7FF: /* 0x1e7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (487 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E8FF: /* 0x1e8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (488 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_E9FF: /* 0x1e9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (489 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_EAFF: /* 0x1ea */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (490 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_EBFF: /* 0x1eb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (491 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_ECFF: /* 0x1ec */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (492 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_EDFF: /* 0x1ed */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (493 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_EEFF: /* 0x1ee */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (494 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_EFFF: /* 0x1ef */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (495 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F0FF: /* 0x1f0 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (496 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F1FF: /* 0x1f1 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (497 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F2FF: /* 0x1f2 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (498 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F3FF: /* 0x1f3 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (499 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F4FF: /* 0x1f4 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (500 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F5FF: /* 0x1f5 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (501 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F6FF: /* 0x1f6 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (502 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F7FF: /* 0x1f7 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (503 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F8FF: /* 0x1f8 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (504 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_F9FF: /* 0x1f9 */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (505 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_FAFF: /* 0x1fa */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (506 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_FBFF: /* 0x1fb */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (507 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_FCFF: /* 0x1fc */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (508 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_FDFF: /* 0x1fd */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (509 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_UNUSED_FEFF: /* 0x1fe */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (510 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+/* ------------------------------ */
+ .balign 64
+.L_ALT_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */
+/* File: armv5te/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Note that the call to dvmCheckInst is done as a tail call.
+ */
+ adrl lr, dvmAsmInstructionStart + (511 * 64)
+ mov r0, rPC @ arg0
+ mov r1, rSELF @ arg1
+ b dvmCheckInst @ (dPC,self) tail call to instruction checker
+
+ .balign 64
+ .size dvmAsmAltInstructionStart, .-dvmAsmAltInstructionStart
+ .global dvmAsmAltInstructionEnd
+dvmAsmAltInstructionEnd:
/* File: armv5te/footer.S */
/*
@@ -13189,7 +20361,7 @@
EXPORT_PC()
mov r0, #0
str r0, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
FETCH_INST()
GET_INST_OPCODE(ip)
GOTO_OPCODE(ip)
@@ -13211,7 +20383,7 @@
mov rPC,r0
EXPORT_PC()
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
mov r2,#kJitSingleStep @ Ask for single step and then revert
str r2,[rSELF,#offThread_jitState]
mov r1,#1 @ set changeInterp to bail to debug interp
@@ -13260,7 +20432,7 @@
/* No translation, so request one if profiling isn't disabled*/
2:
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
GET_JIT_PROF_TABLE(r0)
FETCH_INST()
cmp r0, #0
@@ -13321,7 +20493,7 @@
cmp r0,#0
bxne r0 @ continue native execution if so
EXPORT_PC()
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
FETCH_INST()
GET_INST_OPCODE(ip) @ extract opcode from rINST
GOTO_OPCODE(ip) @ jump to next instruction
@@ -13352,7 +20524,7 @@
*/
toInterpreter:
EXPORT_PC()
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
FETCH_INST()
GET_JIT_PROF_TABLE(r0)
@ NOTE: intended fallthrough
@@ -13469,7 +20641,7 @@
1: @ exit to interpreter without check
EXPORT_PC()
- adrl rIBASE, dvmAsmInstructionStart
+ ldr rIBASE, [rSELF, #offThread_curHandlerTable]
FETCH_INST()
GET_INST_OPCODE(ip)
GOTO_OPCODE(ip)
diff --git a/vm/mterp/out/InterpAsm-x86-atom.S b/vm/mterp/out/InterpAsm-x86-atom.S
index 6a3b383..9d982ca 100644
--- a/vm/mterp/out/InterpAsm-x86-atom.S
+++ b/vm/mterp/out/InterpAsm-x86-atom.S
@@ -24841,9 +24841,8 @@
call common_abort
-
.balign 64
- .size .L_OP_NOP, .-.L_OP_NOP
+ .size dvmAsmInstructionStart, .-dvmAsmInstructionStart
.global dvmAsmInstructionEnd
dvmAsmInstructionEnd:
diff --git a/vm/mterp/out/InterpAsm-x86.S b/vm/mterp/out/InterpAsm-x86.S
index f4e8733..4f7a2f5 100644
--- a/vm/mterp/out/InterpAsm-x86.S
+++ b/vm/mterp/out/InterpAsm-x86.S
@@ -64,11 +64,12 @@
rINSTw bx first 16-bit code of current instruction
rINSTbl bl opcode portion of instruction word
rINSTbh bh high byte of inst word, usually contains src/tgt reg names
+ rIBASE edx base of instruction handler table
Notes:
o High order 16 bits of ebx must be zero on entry to handler
o rPC, rFP, rINSTw/rINSTbl valid on handler entry and exit
- o eax, edx and ecx are scratch, rINSTw/ebx sometimes scratch
+ o eax and ecx are scratch, rINSTw/ebx sometimes scratch
*/
@@ -79,6 +80,7 @@
#define rINSTw %bx
#define rINSTbh %bh
#define rINSTbl %bl
+#define rIBASE %edx
/* Frame diagram while executing dvmMterpStdRun, high to low addresses */
@@ -93,13 +95,13 @@
#define rPC_SPILL (-16)
#define rFP_SPILL (-20)
#define rINST_SPILL (-24)
-#define TMP_SPILL1 (-28)
-#define TMP_SPILL2 (-32)
-#define TMP_SPILL3 (-36)
-#define LOCAL0_OFFSET (-40)
-#define LOCAL1_OFFSET (-44)
-#define LOCAL2_OFFSET (-48)
-#define LOCAL3_OFFSET (-52)
+#define rIBASE_SPILL (-28)
+#define TMP_SPILL1 (-32)
+#define TMP_SPILL2 (-36)
+#define TMP_SPILL3 (-20)
+#define LOCAL0_OFFSET (-44)
+#define LOCAL1_OFFSET (-48)
+#define LOCAL2_OFFSET (-52)
/* Out Arg offsets, relative to %sp */
#define OUT_ARG4 ( 16)
#define OUT_ARG3 ( 12)
@@ -221,7 +223,7 @@
.macro GOTO_NEXT
movzx rINSTbl,%eax
movzbl rINSTbh,rINST
- jmp *dvmAsmInstructionJmpTable(,%eax,4)
+ jmp *(rIBASE,%eax,4)
.endm
/*
@@ -230,7 +232,7 @@
*/
.macro GOTO_NEXT_R _reg
movzbl 1(rPC),rINST
- jmp *dvmAsmInstructionJmpTable(,\_reg,4)
+ jmp *(rIBASE,\_reg,4)
.endm
/*
@@ -240,7 +242,7 @@
*/
.macro GOTO_NEXT_JUMBO_R _reg
movzwl 6(rPC),rINST
- jmp *dvmAsmInstructionJmpTable(,\_reg,4)
+ jmp *(rIBASE,\_reg,4)
.endm
/*
@@ -262,310 +264,9 @@
movl \_reg,4*(\_offset)(rFP,\_vreg,4)
.endm
-#if 1
-
-#define rFinish %edx
-
-/* Macros for x86-atom handlers */
- /*
- * Get the 32-bit value from a dalvik register.
- */
-
- .macro GET_VREG _vreg
- movl (rFP,\_vreg, 4), \_vreg
- .endm
-
- /*
- * Fetch the next instruction from the specified offset. Advances rPC
- * to point to the next instruction. "_count" is in 16-bit code units.
- *
- * This must come AFTER anything that can throw an exception, or the
- * exception catch may miss. (This also implies that it must come after
- * EXPORT_PC())
- */
-
- .macro FETCH_ADVANCE_INST _count
- add $(\_count*2), rPC
- movzwl (rPC), rINST
- .endm
-
- /*
- * Fetch the next instruction from an offset specified by _reg. Updates
- * rPC to point to the next instruction. "_reg" must specify the distance
- * in bytes, *not* 16-bit code units, and may be a signed value.
- */
-
- .macro FETCH_ADVANCE_INST_RB _reg
- addl \_reg, rPC
- movzwl (rPC), rINST
- .endm
-
- /*
- * Fetch a half-word code unit from an offset past the current PC. The
- * "_count" value is in 16-bit code units. Does not advance rPC.
- * For example, given instruction of format: AA|op BBBB, it
- * fetches BBBB.
- */
-
- .macro FETCH _count _reg
- movzwl (\_count*2)(rPC), \_reg
- .endm
-
- /*
- * Fetch a half-word code unit from an offset past the current PC. The
- * "_count" value is in 16-bit code units. Does not advance rPC.
- * This variant treats the value as signed.
- */
-
- .macro FETCHs _count _reg
- movswl (\_count*2)(rPC), \_reg
- .endm
-
- /*
- * Fetch the first byte from an offset past the current PC. The
- * "_count" value is in 16-bit code units. Does not advance rPC.
- * For example, given instruction of format: AA|op CC|BB, it
- * fetches BB.
- */
-
- .macro FETCH_BB _count _reg
- movzbl (\_count*2)(rPC), \_reg
- .endm
-
- /*
- * Fetch the second byte from an offset past the current PC. The
- * "_count" value is in 16-bit code units. Does not advance rPC.
- * For example, given instruction of format: AA|op CC|BB, it
- * fetches CC.
- */
-
- .macro FETCH_CC _count _reg
- movzbl (\_count*2 + 1)(rPC), \_reg
- .endm
-
- /*
- * Fetch the second byte from an offset past the current PC. The
- * "_count" value is in 16-bit code units. Does not advance rPC.
- * This variant treats the value as signed.
- */
-
- .macro FETCH_CCs _count _reg
- movsbl (\_count*2 + 1)(rPC), \_reg
- .endm
-
-
- /*
- * Fetch one byte from an offset past the current PC. Pass in the same
- * "_count" as you would for FETCH, and an additional 0/1 indicating which
- * byte of the halfword you want (lo/hi).
- */
-
- .macro FETCH_B _reg _count _byte
- movzbl (\_count*2+\_byte)(rPC), \_reg
- .endm
-
- /*
- * Put the instruction's opcode field into the specified register.
- */
-
- .macro GET_INST_OPCODE _reg
- movzbl rINSTbl, \_reg
- .endm
-
- /*
- * Begin executing the opcode in _reg.
- */
-
- .macro GOTO_OPCODE _reg
- shl $6, \_reg
- addl $dvmAsmInstructionStart,\_reg
- jmp *\_reg
- .endm
-
-
-
- /*
- * Macros pair attempts to speed up FETCH_INST, GET_INST_OPCODE and GOTO_OPCODE
- * by using a jump table. _rFinish should must be the same register for
- * both macros.
- */
-
- .macro FFETCH _rFinish
- movzbl (rPC), \_rFinish
- .endm
-
- .macro FGETOP_JMPa _rFinish
- movzbl 1(rPC), rINST
- jmp *dvmAsmInstructionJmpTable(,\_rFinish, 4)
- .endm
-
- /*
- * Macro pair attempts to speed up FETCH_INST, GET_INST_OPCODE and GOTO_OPCODE
- * by using a jump table. _rFinish and _count should must be the same register for
- * both macros.
- */
-
- .macro FFETCH_ADV _count _rFinish
- movzbl (\_count*2)(rPC), \_rFinish
- .endm
-
- .macro FGETOP_JMP _count _rFinish
- movzbl (\_count*2 + 1)(rPC), rINST
- addl $(\_count*2), rPC
- jmp *dvmAsmInstructionJmpTable(,\_rFinish, 4)
- .endm
-
- .macro FGETOP_JMP2 _rFinish
- movzbl 1(rPC), rINST
- jmp *dvmAsmInstructionJmpTable(,\_rFinish, 4)
- .endm
-
- .macro OLD_JMP_1 _count _rFinish
- movzbl (\_count*2)(rPC), \_rFinish
- shl $6, \_rFinish
- .endm
-
- .macro OLD_JMP_2 _rFinish
- addl $dvmAsmInstructionStart,\_rFinish
- .endm
-
- .macro OLD_JMP_3 _count
- addl $(\_count*2), rPC
- .endm
-
- .macro OLD_JMP_4 _rFinish
- movzbl 1(rPC), rINST
- jmp *\_rFinish
- .endm
-
- .macro OLD_JMP_A_1 _reg _rFinish
- movzbl (rPC, \_reg), \_rFinish
- shl $6, \_rFinish
- .endm
-
- .macro OLD_JMP_A_2 _rFinish
- addl $dvmAsmInstructionStart,\_rFinish
- .endm
-
- .macro OLD_JMP_A_3 _reg _rFinish
- addl \_reg, rPC
- movzbl 1(rPC, \_reg), rINST
- jmp *\_rFinish
- .endm
-
- /*
- * Macro pair attempts to speed up FETCH_INST, GET_INST_OPCODE and GOTO_OPCODE
- * by using a jump table. _rFinish and _reg should must be the same register for
- * both macros.
- */
-
- .macro FFETCH_ADV_RB _reg _rFinish
- movzbl (\_reg, rPC), \_rFinish
- .endm
-
- .macro FGETOP_RB_JMP _reg _rFinish
- movzbl 1(\_reg, rPC), rINST
- addl \_reg, rPC
- jmp *dvmAsmInstructionJmpTable(,\_rFinish, 4)
- .endm
-
- /*
- * Attempts to speed up FETCH_INST, GET_INST_OPCODE using
- * a jump table. This macro should be called before FINISH_JMP where
- * rFinish should be the same register containing the opcode value.
- * This is an attempt to split up FINISH in order to reduce or remove
- * potential stalls due to the wait for rFINISH.
- */
-
- .macro FINISH_FETCH _rFinish
- movzbl (rPC), \_rFinish
- movzbl 1(rPC), rINST
- .endm
-
-
- /*
- * Attempts to speed up FETCH_ADVANCE_INST, GET_INST_OPCODE using
- * a jump table. This macro should be called before FINISH_JMP where
- * rFinish should be the same register containing the opcode value.
- * This is an attempt to split up FINISH in order to reduce or remove
- * potential stalls due to the wait for rFINISH.
- */
-
- .macro FINISH_FETCH_ADVANCE _count _rFinish
- movzbl (\_count*2)(rPC), \_rFinish
- movzbl (\_count*2 + 1)(rPC), rINST
- addl $(\_count*2), rPC
- .endm
-
- /*
- * Attempts to speed up FETCH_ADVANCE_INST_RB, GET_INST_OPCODE using
- * a jump table. This macro should be called before FINISH_JMP where
- * rFinish should be the same register containing the opcode value.
- * This is an attempt to split up FINISH in order to reduce or remove
- * potential stalls due to the wait for rFINISH.
- */
-
- .macro FINISH_FETCH_ADVANCE_RB _reg _rFinish
- movzbl (\_reg, rPC), \_rFinish
- movzbl 1(\_reg, rPC), rINST
- addl \_reg, rPC
- .endm
-
- /*
- * Attempts to speed up GOTO_OPCODE using a jump table. This macro should
- * be called after a FINISH_FETCH* instruction where rFinish should be the
- * same register containing the opcode value. This is an attempt to split up
- * FINISH in order to reduce or remove potential stalls due to the wait for rFINISH.
- */
-
- .macro FINISH_JMP _rFinish
- jmp *dvmAsmInstructionJmpTable(,\_rFinish, 4)
- .endm
-
- /*
- * Attempts to speed up FETCH_INST, GET_INST_OPCODE, GOTO_OPCODE by using
- * a jump table. Uses a single macro - but it should be faster if we
- * split up the fetch for rFinish and the jump using rFinish.
- */
-
- .macro FINISH_A
- movzbl (rPC), rFinish
- movzbl 1(rPC), rINST
- jmp *dvmAsmInstructionJmpTable(,rFinish, 4)
- .endm
-
- /*
- * Attempts to speed up FETCH_ADVANCE_INST, GET_INST_OPCODE,
- * GOTO_OPCODE by using a jump table. Uses a single macro -
- * but it should be faster if we split up the fetch for rFinish
- * and the jump using rFinish.
- */
-
- .macro FINISH _count
- movzbl (\_count*2)(rPC), rFinish
- movzbl (\_count*2 + 1)(rPC), rINST
- addl $(\_count*2), rPC
- jmp *dvmAsmInstructionJmpTable(,rFinish, 4)
- .endm
-
- /*
- * Attempts to speed up FETCH_ADVANCE_INST_RB, GET_INST_OPCODE,
- * GOTO_OPCODE by using a jump table. Uses a single macro -
- * but it should be faster if we split up the fetch for rFinish
- * and the jump using rFinish.
- */
-
- .macro FINISH_RB _reg _rFinish
- movzbl (\_reg, rPC), \_rFinish
- movzbl 1(\_reg, rPC), rINST
- addl \_reg, rPC
- jmp *dvmAsmInstructionJmpTable(,\_rFinish, 4)
- .endm
-
#define sReg0 LOCAL0_OFFSET(%ebp)
#define sReg1 LOCAL1_OFFSET(%ebp)
#define sReg2 LOCAL2_OFFSET(%ebp)
-#define sReg3 LOCAL3_OFFSET(%ebp)
/*
* Hard coded helper values.
@@ -601,7 +302,6 @@
.LintMax:
.long 0x7FFFFFFF
-#endif
/*
@@ -615,21 +315,19 @@
#endif
- .global dvmAsmInstructionStart
- .type dvmAsmInstructionStart, %function
-dvmAsmInstructionStart = .L_OP_NOP
+ .global dvmAsmInstructionStartCode
+ .type dvmAsmInstructionStartCode, %function
+dvmAsmInstructionStartCode = .L_OP_NOP
.text
/* ------------------------------ */
- .balign 64
.L_OP_NOP: /* 0x00 */
/* File: x86/OP_NOP.S */
- FETCH_INST_OPCODE 1 %edx
+ FETCH_INST_OPCODE 1 %ecx
ADVANCE_PC 1
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
/* ------------------------------ */
- .balign 64
.L_OP_MOVE: /* 0x01 */
/* File: x86/OP_MOVE.S */
/* for move, move-object, long-to-int */
@@ -637,42 +335,39 @@
movzbl rINSTbl,%eax # eax<- BA
andb $0xf,%al # eax<- A
shrl $4,rINST # rINST<- B
- GET_VREG_R %ecx rINST
- FETCH_INST_OPCODE 1 %edx
+ GET_VREG_R rINST rINST
+ FETCH_INST_OPCODE 1 %ecx
ADVANCE_PC 1
- SET_VREG %ecx %eax # fp[A]<-fp[B]
- GOTO_NEXT_R %edx
+ SET_VREG rINST %eax # fp[A]<-fp[B]
+ GOTO_NEXT_R %ecx
/* ------------------------------ */
- .balign 64
.L_OP_MOVE_FROM16: /* 0x02 */
/* File: x86/OP_MOVE_FROM16.S */
/* for: move/from16, move-object/from16 */
/* op vAA, vBBBB */
movzx rINSTbl,%eax # eax <= AA
movw 2(rPC),rINSTw # rINSTw <= BBBB
- GET_VREG_R %ecx rINST # ecx<- fp[BBBB]
- FETCH_INST_OPCODE 2 %edx
+ GET_VREG_R rINST rINST # rINST- fp[BBBB]
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- SET_VREG %ecx %eax # fp[AA]<- ecx]
- GOTO_NEXT_R %edx
+ SET_VREG rINST %eax # fp[AA]<- ecx]
+ GOTO_NEXT_R %ecx
/* ------------------------------ */
- .balign 64
.L_OP_MOVE_16: /* 0x03 */
/* File: x86/OP_MOVE_16.S */
/* for: move/16, move-object/16 */
/* op vAAAA, vBBBB */
movzwl 4(rPC),%ecx # ecx<- BBBB
movzwl 2(rPC),%eax # eax<- AAAA
- GET_VREG_R %ecx %ecx
- FETCH_INST_OPCODE 3 %edx
+ GET_VREG_R rINST %ecx
+ FETCH_INST_OPCODE 3 %ecx
ADVANCE_PC 3
- SET_VREG %ecx %eax
- GOTO_NEXT_R %edx
+ SET_VREG rINST %eax
+ GOTO_NEXT_R %ecx
/* ------------------------------ */
- .balign 64
.L_OP_MOVE_WIDE: /* 0x04 */
/* File: x86/OP_MOVE_WIDE.S */
/* move-wide vA, vB */
@@ -682,14 +377,13 @@
GET_VREG_WORD %eax rINST 0 # eax<- v[B+0]
GET_VREG_WORD rINST rINST 1 # rINST<- v[B+1]
andb $0xf,%cl # ecx <- A
- FETCH_INST_OPCODE 1 %edx
SET_VREG_WORD rINST %ecx 1 # v[A+1]<- rINST
- ADVANCE_PC 1
SET_VREG_WORD %eax %ecx 0 # v[A+0]<- eax
- GOTO_NEXT_R %edx
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
/* ------------------------------ */
- .balign 64
.L_OP_MOVE_WIDE_FROM16: /* 0x05 */
/* File: x86/OP_MOVE_WIDE_FROM16.S */
/* move-wide/from16 vAA, vBBBB */
@@ -698,14 +392,13 @@
movzbl rINSTbl,%eax # eax<- AAAA
GET_VREG_WORD rINST %ecx 0 # rINST<- v[BBBB+0]
GET_VREG_WORD %ecx %ecx 1 # ecx<- v[BBBB+1]
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
SET_VREG_WORD rINST %eax 0 # v[AAAA+0]<- rINST
SET_VREG_WORD %ecx %eax 1 # v[AAAA+1]<- eax
- GOTO_NEXT_R %edx
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
/* ------------------------------ */
- .balign 64
.L_OP_MOVE_WIDE_16: /* 0x06 */
/* File: x86/OP_MOVE_WIDE_16.S */
/* move-wide/16 vAAAA, vBBBB */
@@ -714,14 +407,13 @@
movzwl 2(rPC),%eax # eax<- AAAA
GET_VREG_WORD rINST %ecx 0 # rINSTw_WORD<- v[BBBB+0]
GET_VREG_WORD %ecx %ecx 1 # ecx<- v[BBBB+1]
- FETCH_INST_OPCODE 3 %edx
SET_VREG_WORD rINST %eax 0 # v[AAAA+0]<- rINST
- ADVANCE_PC 3
SET_VREG_WORD %ecx %eax 1 # v[AAAA+1]<- ecx
- GOTO_NEXT_R %edx
+ FETCH_INST_OPCODE 3 %ecx
+ ADVANCE_PC 3
+ GOTO_NEXT_R %ecx
/* ------------------------------ */
- .balign 64
.L_OP_MOVE_OBJECT: /* 0x07 */
/* File: x86/OP_MOVE_OBJECT.S */
/* File: x86/OP_MOVE.S */
@@ -730,15 +422,14 @@
movzbl rINSTbl,%eax # eax<- BA
andb $0xf,%al # eax<- A
shrl $4,rINST # rINST<- B
- GET_VREG_R %ecx rINST
- FETCH_INST_OPCODE 1 %edx
+ GET_VREG_R rINST rINST
+ FETCH_INST_OPCODE 1 %ecx
ADVANCE_PC 1
- SET_VREG %ecx %eax # fp[A]<-fp[B]
- GOTO_NEXT_R %edx
+ SET_VREG rINST %eax # fp[A]<-fp[B]
+ GOTO_NEXT_R %ecx
/* ------------------------------ */
- .balign 64
.L_OP_MOVE_OBJECT_FROM16: /* 0x08 */
/* File: x86/OP_MOVE_OBJECT_FROM16.S */
/* File: x86/OP_MOVE_FROM16.S */
@@ -746,15 +437,14 @@
/* op vAA, vBBBB */
movzx rINSTbl,%eax # eax <= AA
movw 2(rPC),rINSTw # rINSTw <= BBBB
- GET_VREG_R %ecx rINST # ecx<- fp[BBBB]
- FETCH_INST_OPCODE 2 %edx
+ GET_VREG_R rINST rINST # rINST- fp[BBBB]
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- SET_VREG %ecx %eax # fp[AA]<- ecx]
- GOTO_NEXT_R %edx
+ SET_VREG rINST %eax # fp[AA]<- ecx]
+ GOTO_NEXT_R %ecx
/* ------------------------------ */
- .balign 64
.L_OP_MOVE_OBJECT_16: /* 0x09 */
/* File: x86/OP_MOVE_OBJECT_16.S */
/* File: x86/OP_MOVE_16.S */
@@ -762,78 +452,70 @@
/* op vAAAA, vBBBB */
movzwl 4(rPC),%ecx # ecx<- BBBB
movzwl 2(rPC),%eax # eax<- AAAA
- GET_VREG_R %ecx %ecx
- FETCH_INST_OPCODE 3 %edx
+ GET_VREG_R rINST %ecx
+ FETCH_INST_OPCODE 3 %ecx
ADVANCE_PC 3
- SET_VREG %ecx %eax
- GOTO_NEXT_R %edx
+ SET_VREG rINST %eax
+ GOTO_NEXT_R %ecx
/* ------------------------------ */
- .balign 64
.L_OP_MOVE_RESULT: /* 0x0a */
/* File: x86/OP_MOVE_RESULT.S */
/* for: move-result, move-result-object */
/* op vAA */
movl rSELF,%eax # eax<- rSELF
- movzx rINSTbl,%ecx # ecx<- AA
- movl offThread_retval(%eax),%eax # eax<- self->retval.l
- FETCH_INST_OPCODE 1 %edx
+ movl offThread_retval(%eax),%eax # eax<- self->retval.l
+ FETCH_INST_OPCODE 1 %ecx
ADVANCE_PC 1
- SET_VREG %eax %ecx # fp[AA]<- retval.l
- GOTO_NEXT_R %edx
+ SET_VREG %eax rINST # fp[AA]<- retval.l
+ GOTO_NEXT_R %ecx
/* ------------------------------ */
- .balign 64
.L_OP_MOVE_RESULT_WIDE: /* 0x0b */
/* File: x86/OP_MOVE_RESULT_WIDE.S */
/* move-result-wide vAA */
movl rSELF,%ecx
movl offThread_retval(%ecx),%eax
movl 4+offThread_retval(%ecx),%ecx
- FETCH_INST_OPCODE 1 %edx
SET_VREG_WORD %eax rINST 0 # v[AA+0] <- eax
SET_VREG_WORD %ecx rINST 1 # v[AA+1] <- ecx
+ FETCH_INST_OPCODE 1 %ecx
ADVANCE_PC 1
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
/* ------------------------------ */
- .balign 64
.L_OP_MOVE_RESULT_OBJECT: /* 0x0c */
/* File: x86/OP_MOVE_RESULT_OBJECT.S */
/* File: x86/OP_MOVE_RESULT.S */
/* for: move-result, move-result-object */
/* op vAA */
movl rSELF,%eax # eax<- rSELF
- movzx rINSTbl,%ecx # ecx<- AA
- movl offThread_retval(%eax),%eax # eax<- self->retval.l
- FETCH_INST_OPCODE 1 %edx
+ movl offThread_retval(%eax),%eax # eax<- self->retval.l
+ FETCH_INST_OPCODE 1 %ecx
ADVANCE_PC 1
- SET_VREG %eax %ecx # fp[AA]<- retval.l
- GOTO_NEXT_R %edx
+ SET_VREG %eax rINST # fp[AA]<- retval.l
+ GOTO_NEXT_R %ecx
/* ------------------------------ */
- .balign 64
.L_OP_MOVE_EXCEPTION: /* 0x0d */
/* File: x86/OP_MOVE_EXCEPTION.S */
/* move-exception vAA */
movl rSELF,%ecx
movl offThread_exception(%ecx),%eax # eax<- dvmGetException bypass
SET_VREG %eax rINST # fp[AA]<- exception object
- FETCH_INST_OPCODE 1 %edx
+ FETCH_INST_OPCODE 1 %eax
ADVANCE_PC 1
movl $0,offThread_exception(%ecx) # dvmClearException bypass
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %eax
/* ------------------------------ */
- .balign 64
.L_OP_RETURN_VOID: /* 0x0e */
/* File: x86/OP_RETURN_VOID.S */
jmp common_returnFromMethod
/* ------------------------------ */
- .balign 64
.L_OP_RETURN: /* 0x0f */
/* File: x86/OP_RETURN.S */
/*
@@ -849,7 +531,6 @@
jmp common_returnFromMethod
/* ------------------------------ */
- .balign 64
.L_OP_RETURN_WIDE: /* 0x10 */
/* File: x86/OP_RETURN_WIDE.S */
/*
@@ -865,7 +546,6 @@
jmp common_returnFromMethod
/* ------------------------------ */
- .balign 64
.L_OP_RETURN_OBJECT: /* 0x11 */
/* File: x86/OP_RETURN_OBJECT.S */
/* File: x86/OP_RETURN.S */
@@ -883,84 +563,79 @@
/* ------------------------------ */
- .balign 64
.L_OP_CONST_4: /* 0x12 */
/* File: x86/OP_CONST_4.S */
/* const/4 vA, #+B */
movsx rINSTbl,%eax # eax<-ssssssBx
- movl $0xf,%ecx
- andl %eax,%ecx # ecx<- A
- FETCH_INST_OPCODE 1 %edx
+ movl $0xf,rINST
+ andl %eax,rINST # rINST<- A
+ FETCH_INST_OPCODE 1 %ecx
ADVANCE_PC 1
sarl $4,%eax
- SET_VREG %eax %ecx
- GOTO_NEXT_R %edx
+ SET_VREG %eax rINST
+ GOTO_NEXT_R %ecx
/* ------------------------------ */
- .balign 64
.L_OP_CONST_16: /* 0x13 */
/* File: x86/OP_CONST_16.S */
/* const/16 vAA, #+BBBB */
movswl 2(rPC),%ecx # ecx<- ssssBBBB
- movl rINST,%eax # eax<- AA
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %eax
ADVANCE_PC 2
- SET_VREG %ecx %eax # vAA<- ssssBBBB
- GOTO_NEXT_R %edx
+ SET_VREG %ecx rINST # vAA<- ssssBBBB
+ GOTO_NEXT_R %eax
/* ------------------------------ */
- .balign 64
.L_OP_CONST: /* 0x14 */
/* File: x86/OP_CONST.S */
/* const vAA, #+BBBBbbbb */
movl 2(rPC),%eax # grab all 32 bits at once
- movl rINST,%ecx # ecx<- AA
- FETCH_INST_OPCODE 3 %edx
+ movl rINST,rINST # rINST<- AA
+ FETCH_INST_OPCODE 3 %ecx
ADVANCE_PC 3
- SET_VREG %eax %ecx # vAA<- eax
- GOTO_NEXT_R %edx
+ SET_VREG %eax rINST # vAA<- eax
+ GOTO_NEXT_R %ecx
/* ------------------------------ */
- .balign 64
.L_OP_CONST_HIGH16: /* 0x15 */
/* File: x86/OP_CONST_HIGH16.S */
/* const/high16 vAA, #+BBBB0000 */
movzwl 2(rPC),%eax # eax<- 0000BBBB
- movl rINST,%ecx # ecx<- AA
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
sall $16,%eax # eax<- BBBB0000
- SET_VREG %eax %ecx # vAA<- eax
- GOTO_NEXT_R %edx
+ SET_VREG %eax rINST # vAA<- eax
+ GOTO_NEXT_R %ecx
/* ------------------------------ */
- .balign 64
.L_OP_CONST_WIDE_16: /* 0x16 */
/* File: x86/OP_CONST_WIDE_16.S */
/* const-wide/16 vAA, #+BBBB */
movswl 2(rPC),%eax # eax<- ssssBBBB
- cltd # rPC:eax<- ssssssssssssBBBB
- SET_VREG_WORD %edx rINST 1 # store msw
- FETCH_INST_OPCODE 2 %edx
+ SPILL(rIBASE) # preserve rIBASE (cltd trashes it)
+ cltd # rIBASE:eax<- ssssssssssssBBBB
+ SET_VREG_WORD rIBASE rINST 1 # store msw
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE) # restore rIBASE
SET_VREG_WORD %eax rINST 0 # store lsw
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
/* ------------------------------ */
- .balign 64
.L_OP_CONST_WIDE_32: /* 0x17 */
/* File: x86/OP_CONST_WIDE_32.S */
/* const-wide/32 vAA, #+BBBBbbbb */
movl 2(rPC),%eax # eax<- BBBBbbbb
- cltd # rPC:eax<- ssssssssssssBBBB
- SET_VREG_WORD %edx rINST,1 # store msw
- FETCH_INST_OPCODE 3 %edx
+ SPILL(rIBASE) # save rIBASE (cltd trashes it)
+ cltd # rIBASE:eax<- ssssssssssssBBBB
+ SET_VREG_WORD rIBASE rINST,1 # store msw
+ FETCH_INST_OPCODE 3 %ecx
+ UNSPILL(rIBASE) # restore rIBASE
SET_VREG_WORD %eax rINST 0 # store lsw
ADVANCE_PC 3
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
/* ------------------------------ */
- .balign 64
.L_OP_CONST_WIDE: /* 0x18 */
/* File: x86/OP_CONST_WIDE.S */
/* const-wide vAA, #+HHHHhhhhBBBBbbbb */
@@ -969,27 +644,25 @@
movl 6(rPC),rINST # rINST<- msw
leal (rFP,%ecx,4),%ecx # dst addr
movl rINST,4(%ecx)
- FETCH_INST_OPCODE 5 %edx
movl %eax,(%ecx)
+ FETCH_INST_OPCODE 5 %ecx
ADVANCE_PC 5
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
/* ------------------------------ */
- .balign 64
.L_OP_CONST_WIDE_HIGH16: /* 0x19 */
/* File: x86/OP_CONST_WIDE_HIGH16.S */
/* const-wide/high16 vAA, #+BBBB000000000000 */
movzwl 2(rPC),%eax # eax<- 0000BBBB
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
sall $16,%eax # eax<- BBBB0000
SET_VREG_WORD %eax rINST 1 # v[AA+1]<- eax
xorl %eax,%eax
SET_VREG_WORD %eax rINST 0 # v[AA+0]<- eax
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
/* ------------------------------ */
- .balign 64
.L_OP_CONST_STRING: /* 0x1a */
/* File: x86/OP_CONST_STRING.S */
@@ -999,16 +672,34 @@
movl offThread_methodClassDex(%ecx),%ecx# ecx<- self->methodClassDex
movl offDvmDex_pResStrings(%ecx),%ecx # ecx<- dvmDex->pResStrings
movl (%ecx,%eax,4),%eax # eax<- rResString[BBBB]
- movl rINST,%ecx
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
testl %eax,%eax # resolved yet?
je .LOP_CONST_STRING_resolve
- SET_VREG %eax %ecx # vAA<- rResString[BBBB]
+ SET_VREG %eax rINST # vAA<- rResString[BBBB]
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
+
+/* This is the less common path, so we'll redo some work
+ here rather than force spills on the common path */
+.LOP_CONST_STRING_resolve:
+ movl rSELF,%eax
+ EXPORT_PC
+ movl offThread_method(%eax),%eax # eax<- self->method
+ movzwl 2(rPC),%ecx # ecx<- BBBB
+ movl offMethod_clazz(%eax),%eax
+ movl %ecx,OUT_ARG1(%esp)
+ movl %eax,OUT_ARG0(%esp)
+ SPILL(rIBASE)
+ call dvmResolveString # go resolve
+ UNSPILL(rIBASE)
+ testl %eax,%eax # failed?
+ je common_exceptionThrown
+ FETCH_INST_OPCODE 2 %ecx
+ SET_VREG %eax rINST
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
/* ------------------------------ */
- .balign 64
.L_OP_CONST_STRING_JUMBO: /* 0x1b */
/* File: x86/OP_CONST_STRING_JUMBO.S */
@@ -1018,16 +709,34 @@
movl offThread_methodClassDex(%ecx),%ecx# ecx<- self->methodClassDex
movl offDvmDex_pResStrings(%ecx),%ecx # ecx<- dvmDex->pResStrings
movl (%ecx,%eax,4),%eax # eax<- rResString[BBBB]
- movl rINST,%ecx
- FETCH_INST_OPCODE 3 %edx
+ FETCH_INST_OPCODE 3 %ecx
testl %eax,%eax # resolved yet?
je .LOP_CONST_STRING_JUMBO_resolve
- SET_VREG %eax %ecx # vAA<- rResString[BBBB]
+ SET_VREG %eax rINST # vAA<- rResString[BBBB]
ADVANCE_PC 3
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
+
+/* This is the less common path, so we'll redo some work
+ here rather than force spills on the common path */
+.LOP_CONST_STRING_JUMBO_resolve:
+ movl rSELF,%eax
+ EXPORT_PC
+ movl offThread_method(%eax),%eax # eax<- self->method
+ movl 2(rPC),%ecx # ecx<- BBBBBBBB
+ movl offMethod_clazz(%eax),%eax
+ movl %ecx,OUT_ARG1(%esp)
+ movl %eax,OUT_ARG0(%esp)
+ SPILL(rIBASE)
+ call dvmResolveString # go resolve
+ UNSPILL(rIBASE)
+ testl %eax,%eax # failed?
+ je common_exceptionThrown
+ FETCH_INST_OPCODE 3 %ecx
+ SET_VREG %eax rINST
+ ADVANCE_PC 3
+ GOTO_NEXT_R %ecx
/* ------------------------------ */
- .balign 64
.L_OP_CONST_CLASS: /* 0x1c */
/* File: x86/OP_CONST_CLASS.S */
@@ -1037,16 +746,35 @@
movl offThread_methodClassDex(%ecx),%ecx# ecx<- self->methodClassDex
movl offDvmDex_pResClasses(%ecx),%ecx # ecx<- dvmDex->pResClasses
movl (%ecx,%eax,4),%eax # eax<- rResClasses[BBBB]
- movl rINST,%ecx
- FETCH_INST_OPCODE 2 %edx
testl %eax,%eax # resolved yet?
je .LOP_CONST_CLASS_resolve
- SET_VREG %eax %ecx # vAA<- rResClasses[BBBB]
+ FETCH_INST_OPCODE 2 %ecx
+ SET_VREG %eax rINST # vAA<- rResClasses[BBBB]
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
+
+/* This is the less common path, so we'll redo some work
+ here rather than force spills on the common path */
+.LOP_CONST_CLASS_resolve:
+ movl rSELF,%eax
+ EXPORT_PC
+ movl offThread_method(%eax),%eax # eax<- self->method
+ movl $1,OUT_ARG2(%esp) # true
+ movzwl 2(rPC),%ecx # ecx<- BBBB
+ movl offMethod_clazz(%eax),%eax
+ movl %ecx,OUT_ARG1(%esp)
+ movl %eax,OUT_ARG0(%esp)
+ SPILL(rIBASE)
+ call dvmResolveClass # go resolve
+ UNSPILL(rIBASE)
+ testl %eax,%eax # failed?
+ je common_exceptionThrown
+ FETCH_INST_OPCODE 2 %ecx
+ SET_VREG %eax rINST
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
/* ------------------------------ */
- .balign 64
.L_OP_MONITOR_ENTER: /* 0x1d */
/* File: x86/OP_MONITOR_ENTER.S */
/*
@@ -1058,11 +786,17 @@
FETCH_INST_WORD 1
testl %eax,%eax # null object?
EXPORT_PC # need for precise GC
- jne .LOP_MONITOR_ENTER_continue
- jmp common_errNullObject
+ je common_errNullObject
+ movl %ecx,OUT_ARG0(%esp)
+ movl %eax,OUT_ARG1(%esp)
+ SPILL(rIBASE)
+ call dvmLockObject # dvmLockObject(self,object)
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
/* ------------------------------ */
- .balign 64
.L_OP_MONITOR_EXIT: /* 0x1e */
/* File: x86/OP_MONITOR_EXIT.S */
/*
@@ -1080,10 +814,19 @@
je .LOP_MONITOR_EXIT_errNullObject # go if so
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
- jmp .LOP_MONITOR_EXIT_continue
+ SPILL(rIBASE)
+ call dvmUnlockObject # unlock(self,obj)
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 1 %ecx
+ testl %eax,%eax # success?
+ ADVANCE_PC 1
+ je common_exceptionThrown # no, exception pending
+ GOTO_NEXT_R %ecx
+.LOP_MONITOR_EXIT_errNullObject:
+ ADVANCE_PC 1 # advance before throw
+ jmp common_errNullObject
/* ------------------------------ */
- .balign 64
.L_OP_CHECK_CAST: /* 0x1f */
/* File: x86/OP_CHECK_CAST.S */
/*
@@ -1105,8175 +848,9 @@
cmpl %eax,%ecx # same class (trivial success)?
jne .LOP_CHECK_CAST_fullcheck # no, do full check
.LOP_CHECK_CAST_okay:
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_INSTANCE_OF: /* 0x20 */
-/* File: x86/OP_INSTANCE_OF.S */
- /*
- * Check to see if an object reference is an instance of a class.
- *
- * Most common situation is a non-null object, being compared against
- * an already-resolved class.
- */
- /* instance-of vA, vB, class@CCCC */
- movl rINST,%eax # eax<- BA
- sarl $4,%eax # eax<- B
- GET_VREG_R %eax %eax # eax<- vB (obj)
- movl rSELF,%ecx
- testl %eax,%eax # object null?
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
- je .LOP_INSTANCE_OF_store # null obj, not instance, store it
- movzwl 2(rPC),%edx # edx<- CCCC
- movl offDvmDex_pResClasses(%ecx),%ecx # ecx<- pDvmDex->pResClasses
- movl (%ecx,%edx,4),%ecx # ecx<- resolved class
- movl offObject_clazz(%eax),%eax # eax<- obj->clazz
- testl %ecx,%ecx # have we resolved this before?
- je .LOP_INSTANCE_OF_resolve # not resolved, do it now
-.LOP_INSTANCE_OF_resolved: # eax<- obj->clazz, ecx<- resolved class
- cmpl %eax,%ecx # same class (trivial success)?
- je .LOP_INSTANCE_OF_trivial # yes, trivial finish
- jmp .LOP_INSTANCE_OF_fullcheck # no, do full check
-
-/* ------------------------------ */
- .balign 64
-.L_OP_ARRAY_LENGTH: /* 0x21 */
-/* File: x86/OP_ARRAY_LENGTH.S */
- /*
- * Return the length of an array.
- */
- mov rINST,%eax # eax<- BA
- sarl $4,rINST # rINST<- B
- GET_VREG_R %ecx rINST # ecx<- vB (object ref)
- andb $0xf,%al # eax<- A
- testl %ecx,%ecx # is null?
- je common_errNullObject
- FETCH_INST_OPCODE 1 %edx
- movl offArrayObject_length(%ecx),%ecx
- ADVANCE_PC 1
- SET_VREG %ecx %eax
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_NEW_INSTANCE: /* 0x22 */
-/* File: x86/OP_NEW_INSTANCE.S */
- /*
- * Create a new instance of a class.
- */
- /* new-instance vAA, class@BBBB */
- movl rSELF,%ecx
- movzwl 2(rPC),%eax # eax<- BBBB
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
- movl offDvmDex_pResClasses(%ecx),%ecx # ecx<- pDvmDex->pResClasses
- EXPORT_PC
- movl (%ecx,%eax,4),%ecx # ecx<- resolved class
- testl %ecx,%ecx # resolved?
- je .LOP_NEW_INSTANCE_resolve # no, go do it
-.LOP_NEW_INSTANCE_resolved: # on entry, ecx<- class
- cmpb $CLASS_INITIALIZED,offClassObject_status(%ecx)
- je .LOP_NEW_INSTANCE_initialized
- jmp .LOP_NEW_INSTANCE_needinit
-
-/* ------------------------------ */
- .balign 64
-.L_OP_NEW_ARRAY: /* 0x23 */
-/* File: x86/OP_NEW_ARRAY.S */
- /*
- * Allocate an array of objects, specified with the array class
- * and a count.
- *
- * The verifier guarantees that this is an array class, so we don't
- * check for it here.
- */
- /* new-array vA, vB, class@CCCC */
- movl rSELF,%ecx
- EXPORT_PC
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
- movzwl 2(rPC),%eax # eax<- CCCC
- movl offDvmDex_pResClasses(%ecx),%ecx # ecx<- pDvmDex->pResClasses
- movl (%ecx,%eax,4),%ecx # ecx<- resolved class
- movzbl rINSTbl,%eax
- sarl $4,%eax # eax<- B
- GET_VREG_R %eax %eax # eax<- vB (array length)
- andb $0xf,rINSTbl # rINST<- A
- testl %eax,%eax
- js common_errNegativeArraySize # bail, passing len in eax
- testl %ecx,%ecx # already resolved?
- jne .LOP_NEW_ARRAY_finish # yes, fast path
- jmp .LOP_NEW_ARRAY_resolve # resolve now
-
-/* ------------------------------ */
- .balign 64
-.L_OP_FILLED_NEW_ARRAY: /* 0x24 */
-/* File: x86/OP_FILLED_NEW_ARRAY.S */
- /*
- * Create a new array with elements filled from registers.
- *
- * for: filled-new-array, filled-new-array/range
- */
- /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
- /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */
- movl rSELF,%eax
- movl offThread_methodClassDex(%eax),%eax # eax<- pDvmDex
- movzwl 2(rPC),%ecx # ecx<- BBBB
- movl offDvmDex_pResClasses(%eax),%eax # eax<- pDvmDex->pResClasses
- movl (%eax,%ecx,4),%eax # eax<- resolved class
- EXPORT_PC
- testl %eax,%eax # already resolved?
- jne .LOP_FILLED_NEW_ARRAY_continue # yes, continue
- # less frequent path, so we'll redo some work
- movl rSELF,%eax
- movl $0,OUT_ARG2(%esp) # arg2<- false
- movl %ecx,OUT_ARG1(%esp) # arg1<- BBBB
- movl offThread_method(%eax),%eax # eax<- self->method
- jmp .LOP_FILLED_NEW_ARRAY_more
-
-/* ------------------------------ */
- .balign 64
-.L_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */
-/* File: x86/OP_FILLED_NEW_ARRAY_RANGE.S */
-/* File: x86/OP_FILLED_NEW_ARRAY.S */
- /*
- * Create a new array with elements filled from registers.
- *
- * for: filled-new-array, filled-new-array/range
- */
- /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
- /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */
- movl rSELF,%eax
- movl offThread_methodClassDex(%eax),%eax # eax<- pDvmDex
- movzwl 2(rPC),%ecx # ecx<- BBBB
- movl offDvmDex_pResClasses(%eax),%eax # eax<- pDvmDex->pResClasses
- movl (%eax,%ecx,4),%eax # eax<- resolved class
- EXPORT_PC
- testl %eax,%eax # already resolved?
- jne .LOP_FILLED_NEW_ARRAY_RANGE_continue # yes, continue
- # less frequent path, so we'll redo some work
- movl rSELF,%eax
- movl $0,OUT_ARG2(%esp) # arg2<- false
- movl %ecx,OUT_ARG1(%esp) # arg1<- BBBB
- movl offThread_method(%eax),%eax # eax<- self->method
- jmp .LOP_FILLED_NEW_ARRAY_RANGE_more
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_FILL_ARRAY_DATA: /* 0x26 */
-/* File: x86/OP_FILL_ARRAY_DATA.S */
- /* fill-array-data vAA, +BBBBBBBB */
- movl 2(rPC),%ecx # ecx<- BBBBbbbb
- leal (rPC,%ecx,2),%ecx # ecx<- PC + BBBBbbbb*2
- GET_VREG_R %eax rINST
- EXPORT_PC
- movl %eax,OUT_ARG0(%esp)
- movl %ecx,OUT_ARG1(%esp)
- call dvmInterpHandleFillArrayData
- FETCH_INST_OPCODE 3 %edx
- testl %eax,%eax # exception thrown?
- je common_exceptionThrown
- ADVANCE_PC 3
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_THROW: /* 0x27 */
-/* File: x86/OP_THROW.S */
- /*
- * Throw an exception object in the current thread.
- */
- /* throw vAA */
- EXPORT_PC
- GET_VREG_R %eax rINST # eax<- exception object
- movl rSELF,%ecx # ecx<- self
- testl %eax,%eax # null object?
- je common_errNullObject
- movl %eax,offThread_exception(%ecx) # thread->exception<- obj
- jmp common_exceptionThrown
-
-/* ------------------------------ */
- .balign 64
-.L_OP_GOTO: /* 0x28 */
-/* File: x86/OP_GOTO.S */
- /*
- * Unconditional branch, 8-bit offset.
- *
- * The branch distance is a signed code-unit offset, which we need to
- * double to get a byte offset.
- */
- /* goto +AA */
- movsbl rINSTbl,rINST # ebx<- ssssssAA
- testl rINST,rINST # test for <0
- js common_backwardBranch
- movl rINST,%eax
- FETCH_INST_INDEXED %eax
- ADVANCE_PC_INDEXED %eax
- GOTO_NEXT
-
-/* ------------------------------ */
- .balign 64
-.L_OP_GOTO_16: /* 0x29 */
-/* File: x86/OP_GOTO_16.S */
- /*
- * Unconditional branch, 16-bit offset.
- *
- * The branch distance is a signed code-unit offset
- */
- /* goto/16 +AAAA */
- movswl 2(rPC),rINST # rINST<- ssssAAAA
- testl rINST,rINST # test for <0
- js common_backwardBranch
- movl rINST,%eax
- FETCH_INST_INDEXED %eax
- ADVANCE_PC_INDEXED %eax
- GOTO_NEXT
-
-/* ------------------------------ */
- .balign 64
-.L_OP_GOTO_32: /* 0x2a */
-/* File: x86/OP_GOTO_32.S */
- /*
- * Unconditional branch, 32-bit offset.
- *
- * The branch distance is a signed code-unit offset.
- *
- * Unlike most opcodes, this one is allowed to branch to itself, so
- * our "backward branch" test must be "<=0" instead of "<0".
- */
- /* goto/32 AAAAAAAA */
- movl 2(rPC),rINST # rINST<- AAAAAAAA
- cmpl $0,rINST # test for <= 0
- jle common_backwardBranch
- movl rINST,%eax
- FETCH_INST_INDEXED %eax
- ADVANCE_PC_INDEXED %eax
- GOTO_NEXT
-
-/* ------------------------------ */
- .balign 64
-.L_OP_PACKED_SWITCH: /* 0x2b */
-/* File: x86/OP_PACKED_SWITCH.S */
- /*
- * Handle a packed-switch or sparse-switch instruction. In both cases
- * we decode it and hand it off to a helper function.
- *
- * We don't really expect backward branches in a switch statement, but
- * they're perfectly legal, so we check for them here.
- *
- * for: packed-switch, sparse-switch
- */
- /* op vAA, +BBBB */
- movl 2(rPC),%ecx # ecx<- BBBBbbbb
- GET_VREG_R %eax rINST # eax<- vAA
- leal (rPC,%ecx,2),%ecx # ecx<- PC + BBBBbbbb*2
- movl %eax,OUT_ARG1(%esp) # ARG1<- vAA
- movl %ecx,OUT_ARG0(%esp) # ARG0<- switchData
- call dvmInterpHandlePackedSwitch
- testl %eax,%eax
- movl %eax,rINST # set up word offset
- jle common_backwardBranch # check on special actions
- ADVANCE_PC_INDEXED rINST
- FETCH_INST
- GOTO_NEXT
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SPARSE_SWITCH: /* 0x2c */
-/* File: x86/OP_SPARSE_SWITCH.S */
-/* File: x86/OP_PACKED_SWITCH.S */
- /*
- * Handle a packed-switch or sparse-switch instruction. In both cases
- * we decode it and hand it off to a helper function.
- *
- * We don't really expect backward branches in a switch statement, but
- * they're perfectly legal, so we check for them here.
- *
- * for: packed-switch, sparse-switch
- */
- /* op vAA, +BBBB */
- movl 2(rPC),%ecx # ecx<- BBBBbbbb
- GET_VREG_R %eax rINST # eax<- vAA
- leal (rPC,%ecx,2),%ecx # ecx<- PC + BBBBbbbb*2
- movl %eax,OUT_ARG1(%esp) # ARG1<- vAA
- movl %ecx,OUT_ARG0(%esp) # ARG0<- switchData
- call dvmInterpHandleSparseSwitch
- testl %eax,%eax
- movl %eax,rINST # set up word offset
- jle common_backwardBranch # check on special actions
- ADVANCE_PC_INDEXED rINST
- FETCH_INST
- GOTO_NEXT
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_CMPL_FLOAT: /* 0x2d */
-/* File: x86/OP_CMPL_FLOAT.S */
-/* File: x86/OP_CMPG_DOUBLE.S */
- /* float/double_cmp[gl] vAA, vBB, vCC */
- movzbl 3(rPC),%eax # eax<- CC
- movzbl 2(rPC),%ecx # ecx<- BB
- .if 0
- fldl (rFP,%eax,4)
- fldl (rFP,%ecx,4)
- .else
- flds (rFP,%eax,4)
- flds (rFP,%ecx,4)
- .endif
- xorl %ecx,%ecx
- fucompp # z if equal, p set if NaN, c set if st0 < st1
- fnstsw %ax
- sahf
- movl rINST,%eax
- FETCH_INST_OPCODE 2 %edx
- jp .LOP_CMPL_FLOAT_isNaN
- je .LOP_CMPL_FLOAT_finish
- sbbl %ecx,%ecx
- jb .LOP_CMPL_FLOAT_finish
- incl %ecx
-.LOP_CMPL_FLOAT_finish:
- SET_VREG %ecx %eax
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_CMPG_FLOAT: /* 0x2e */
-/* File: x86/OP_CMPG_FLOAT.S */
-/* File: x86/OP_CMPG_DOUBLE.S */
- /* float/double_cmp[gl] vAA, vBB, vCC */
- movzbl 3(rPC),%eax # eax<- CC
- movzbl 2(rPC),%ecx # ecx<- BB
- .if 0
- fldl (rFP,%eax,4)
- fldl (rFP,%ecx,4)
- .else
- flds (rFP,%eax,4)
- flds (rFP,%ecx,4)
- .endif
- xorl %ecx,%ecx
- fucompp # z if equal, p set if NaN, c set if st0 < st1
- fnstsw %ax
- sahf
- movl rINST,%eax
- FETCH_INST_OPCODE 2 %edx
- jp .LOP_CMPG_FLOAT_isNaN
- je .LOP_CMPG_FLOAT_finish
- sbbl %ecx,%ecx
- jb .LOP_CMPG_FLOAT_finish
- incl %ecx
-.LOP_CMPG_FLOAT_finish:
- SET_VREG %ecx %eax
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_CMPL_DOUBLE: /* 0x2f */
-/* File: x86/OP_CMPL_DOUBLE.S */
-/* File: x86/OP_CMPG_DOUBLE.S */
- /* float/double_cmp[gl] vAA, vBB, vCC */
- movzbl 3(rPC),%eax # eax<- CC
- movzbl 2(rPC),%ecx # ecx<- BB
- .if 1
- fldl (rFP,%eax,4)
- fldl (rFP,%ecx,4)
- .else
- flds (rFP,%eax,4)
- flds (rFP,%ecx,4)
- .endif
- xorl %ecx,%ecx
- fucompp # z if equal, p set if NaN, c set if st0 < st1
- fnstsw %ax
- sahf
- movl rINST,%eax
- FETCH_INST_OPCODE 2 %edx
- jp .LOP_CMPL_DOUBLE_isNaN
- je .LOP_CMPL_DOUBLE_finish
- sbbl %ecx,%ecx
- jb .LOP_CMPL_DOUBLE_finish
- incl %ecx
-.LOP_CMPL_DOUBLE_finish:
- SET_VREG %ecx %eax
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_CMPG_DOUBLE: /* 0x30 */
-/* File: x86/OP_CMPG_DOUBLE.S */
- /* float/double_cmp[gl] vAA, vBB, vCC */
- movzbl 3(rPC),%eax # eax<- CC
- movzbl 2(rPC),%ecx # ecx<- BB
- .if 1
- fldl (rFP,%eax,4)
- fldl (rFP,%ecx,4)
- .else
- flds (rFP,%eax,4)
- flds (rFP,%ecx,4)
- .endif
- xorl %ecx,%ecx
- fucompp # z if equal, p set if NaN, c set if st0 < st1
- fnstsw %ax
- sahf
- movl rINST,%eax
- FETCH_INST_OPCODE 2 %edx
- jp .LOP_CMPG_DOUBLE_isNaN
- je .LOP_CMPG_DOUBLE_finish
- sbbl %ecx,%ecx
- jb .LOP_CMPG_DOUBLE_finish
- incl %ecx
-.LOP_CMPG_DOUBLE_finish:
- SET_VREG %ecx %eax
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_CMP_LONG: /* 0x31 */
-/* File: x86/OP_CMP_LONG.S */
- /*
- * Compare two 64-bit values. Puts 0, 1, or -1 into the destination
- * register based on the results of the comparison.
- */
- /* cmp-long vAA, vBB, vCC */
- movzbl 2(rPC),%ecx # ecx<- BB
- movzbl 3(rPC),%edx # edx<- CC
- GET_VREG_WORD %eax %ecx,1 # eax<- v[BB+1]
- GET_VREG_WORD %ecx %ecx 0 # ecx<- v[BB+0]
- cmpl 4(rFP,%edx,4),%eax
- jl .LOP_CMP_LONG_smaller
- jg .LOP_CMP_LONG_bigger
- sub (rFP,%edx,4),%ecx
- ja .LOP_CMP_LONG_bigger
- jb .LOP_CMP_LONG_smaller
- jmp .LOP_CMP_LONG_finish
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IF_EQ: /* 0x32 */
-/* File: x86/OP_IF_EQ.S */
-/* File: x86/bincmp.S */
- /*
- * Generic two-operand compare-and-branch operation. Provide a "revcmp"
- * fragment that specifies the *reverse* comparison to perform, e.g.
- * for "if-le" you would use "gt".
- *
- * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
- */
- /* if-cmp vA, vB, +CCCC */
- movzx rINSTbl,%ecx # ecx <- A+
- andb $0xf,%cl # ecx <- A
- GET_VREG_R %eax %ecx # eax <- vA
- sarl $4,rINST # rINST<- B
- cmpl (rFP,rINST,4),%eax # compare (vA, vB)
- movswl 2(rPC),rINST # Get signed branch offset
- movl $2,%eax # assume not taken
- jne 1f
- testl rINST,rINST
- js common_backwardBranch
- movl rINST,%eax
-1:
- FETCH_INST_INDEXED %eax
- ADVANCE_PC_INDEXED %eax
- GOTO_NEXT
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IF_NE: /* 0x33 */
-/* File: x86/OP_IF_NE.S */
-/* File: x86/bincmp.S */
- /*
- * Generic two-operand compare-and-branch operation. Provide a "revcmp"
- * fragment that specifies the *reverse* comparison to perform, e.g.
- * for "if-le" you would use "gt".
- *
- * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
- */
- /* if-cmp vA, vB, +CCCC */
- movzx rINSTbl,%ecx # ecx <- A+
- andb $0xf,%cl # ecx <- A
- GET_VREG_R %eax %ecx # eax <- vA
- sarl $4,rINST # rINST<- B
- cmpl (rFP,rINST,4),%eax # compare (vA, vB)
- movswl 2(rPC),rINST # Get signed branch offset
- movl $2,%eax # assume not taken
- je 1f
- testl rINST,rINST
- js common_backwardBranch
- movl rINST,%eax
-1:
- FETCH_INST_INDEXED %eax
- ADVANCE_PC_INDEXED %eax
- GOTO_NEXT
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IF_LT: /* 0x34 */
-/* File: x86/OP_IF_LT.S */
-/* File: x86/bincmp.S */
- /*
- * Generic two-operand compare-and-branch operation. Provide a "revcmp"
- * fragment that specifies the *reverse* comparison to perform, e.g.
- * for "if-le" you would use "gt".
- *
- * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
- */
- /* if-cmp vA, vB, +CCCC */
- movzx rINSTbl,%ecx # ecx <- A+
- andb $0xf,%cl # ecx <- A
- GET_VREG_R %eax %ecx # eax <- vA
- sarl $4,rINST # rINST<- B
- cmpl (rFP,rINST,4),%eax # compare (vA, vB)
- movswl 2(rPC),rINST # Get signed branch offset
- movl $2,%eax # assume not taken
- jge 1f
- testl rINST,rINST
- js common_backwardBranch
- movl rINST,%eax
-1:
- FETCH_INST_INDEXED %eax
- ADVANCE_PC_INDEXED %eax
- GOTO_NEXT
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IF_GE: /* 0x35 */
-/* File: x86/OP_IF_GE.S */
-/* File: x86/bincmp.S */
- /*
- * Generic two-operand compare-and-branch operation. Provide a "revcmp"
- * fragment that specifies the *reverse* comparison to perform, e.g.
- * for "if-le" you would use "gt".
- *
- * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
- */
- /* if-cmp vA, vB, +CCCC */
- movzx rINSTbl,%ecx # ecx <- A+
- andb $0xf,%cl # ecx <- A
- GET_VREG_R %eax %ecx # eax <- vA
- sarl $4,rINST # rINST<- B
- cmpl (rFP,rINST,4),%eax # compare (vA, vB)
- movswl 2(rPC),rINST # Get signed branch offset
- movl $2,%eax # assume not taken
- jl 1f
- testl rINST,rINST
- js common_backwardBranch
- movl rINST,%eax
-1:
- FETCH_INST_INDEXED %eax
- ADVANCE_PC_INDEXED %eax
- GOTO_NEXT
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IF_GT: /* 0x36 */
-/* File: x86/OP_IF_GT.S */
-/* File: x86/bincmp.S */
- /*
- * Generic two-operand compare-and-branch operation. Provide a "revcmp"
- * fragment that specifies the *reverse* comparison to perform, e.g.
- * for "if-le" you would use "gt".
- *
- * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
- */
- /* if-cmp vA, vB, +CCCC */
- movzx rINSTbl,%ecx # ecx <- A+
- andb $0xf,%cl # ecx <- A
- GET_VREG_R %eax %ecx # eax <- vA
- sarl $4,rINST # rINST<- B
- cmpl (rFP,rINST,4),%eax # compare (vA, vB)
- movswl 2(rPC),rINST # Get signed branch offset
- movl $2,%eax # assume not taken
- jle 1f
- testl rINST,rINST
- js common_backwardBranch
- movl rINST,%eax
-1:
- FETCH_INST_INDEXED %eax
- ADVANCE_PC_INDEXED %eax
- GOTO_NEXT
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IF_LE: /* 0x37 */
-/* File: x86/OP_IF_LE.S */
-/* File: x86/bincmp.S */
- /*
- * Generic two-operand compare-and-branch operation. Provide a "revcmp"
- * fragment that specifies the *reverse* comparison to perform, e.g.
- * for "if-le" you would use "gt".
- *
- * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
- */
- /* if-cmp vA, vB, +CCCC */
- movzx rINSTbl,%ecx # ecx <- A+
- andb $0xf,%cl # ecx <- A
- GET_VREG_R %eax %ecx # eax <- vA
- sarl $4,rINST # rINST<- B
- cmpl (rFP,rINST,4),%eax # compare (vA, vB)
- movswl 2(rPC),rINST # Get signed branch offset
- movl $2,%eax # assume not taken
- jg 1f
- testl rINST,rINST
- js common_backwardBranch
- movl rINST,%eax
-1:
- FETCH_INST_INDEXED %eax
- ADVANCE_PC_INDEXED %eax
- GOTO_NEXT
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IF_EQZ: /* 0x38 */
-/* File: x86/OP_IF_EQZ.S */
-/* File: x86/zcmp.S */
- /*
- * Generic one-operand compare-and-branch operation. Provide a "revcmp"
- * fragment that specifies the *reverse* comparison to perform, e.g.
- * for "if-le" you would use "gt".
- *
- * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
- */
- /* if-cmp vAA, +BBBB */
- cmpl $0,(rFP,rINST,4) # compare (vA, 0)
- movswl 2(rPC),rINST # fetch signed displacement
- movl $2,%eax # assume branch not taken
- jne 1f
- testl rINST,rINST
- js common_backwardBranch
- movl rINST,%eax
-1:
- FETCH_INST_INDEXED %eax
- ADVANCE_PC_INDEXED %eax
- GOTO_NEXT
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IF_NEZ: /* 0x39 */
-/* File: x86/OP_IF_NEZ.S */
-/* File: x86/zcmp.S */
- /*
- * Generic one-operand compare-and-branch operation. Provide a "revcmp"
- * fragment that specifies the *reverse* comparison to perform, e.g.
- * for "if-le" you would use "gt".
- *
- * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
- */
- /* if-cmp vAA, +BBBB */
- cmpl $0,(rFP,rINST,4) # compare (vA, 0)
- movswl 2(rPC),rINST # fetch signed displacement
- movl $2,%eax # assume branch not taken
- je 1f
- testl rINST,rINST
- js common_backwardBranch
- movl rINST,%eax
-1:
- FETCH_INST_INDEXED %eax
- ADVANCE_PC_INDEXED %eax
- GOTO_NEXT
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IF_LTZ: /* 0x3a */
-/* File: x86/OP_IF_LTZ.S */
-/* File: x86/zcmp.S */
- /*
- * Generic one-operand compare-and-branch operation. Provide a "revcmp"
- * fragment that specifies the *reverse* comparison to perform, e.g.
- * for "if-le" you would use "gt".
- *
- * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
- */
- /* if-cmp vAA, +BBBB */
- cmpl $0,(rFP,rINST,4) # compare (vA, 0)
- movswl 2(rPC),rINST # fetch signed displacement
- movl $2,%eax # assume branch not taken
- jge 1f
- testl rINST,rINST
- js common_backwardBranch
- movl rINST,%eax
-1:
- FETCH_INST_INDEXED %eax
- ADVANCE_PC_INDEXED %eax
- GOTO_NEXT
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IF_GEZ: /* 0x3b */
-/* File: x86/OP_IF_GEZ.S */
-/* File: x86/zcmp.S */
- /*
- * Generic one-operand compare-and-branch operation. Provide a "revcmp"
- * fragment that specifies the *reverse* comparison to perform, e.g.
- * for "if-le" you would use "gt".
- *
- * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
- */
- /* if-cmp vAA, +BBBB */
- cmpl $0,(rFP,rINST,4) # compare (vA, 0)
- movswl 2(rPC),rINST # fetch signed displacement
- movl $2,%eax # assume branch not taken
- jl 1f
- testl rINST,rINST
- js common_backwardBranch
- movl rINST,%eax
-1:
- FETCH_INST_INDEXED %eax
- ADVANCE_PC_INDEXED %eax
- GOTO_NEXT
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IF_GTZ: /* 0x3c */
-/* File: x86/OP_IF_GTZ.S */
-/* File: x86/zcmp.S */
- /*
- * Generic one-operand compare-and-branch operation. Provide a "revcmp"
- * fragment that specifies the *reverse* comparison to perform, e.g.
- * for "if-le" you would use "gt".
- *
- * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
- */
- /* if-cmp vAA, +BBBB */
- cmpl $0,(rFP,rINST,4) # compare (vA, 0)
- movswl 2(rPC),rINST # fetch signed displacement
- movl $2,%eax # assume branch not taken
- jle 1f
- testl rINST,rINST
- js common_backwardBranch
- movl rINST,%eax
-1:
- FETCH_INST_INDEXED %eax
- ADVANCE_PC_INDEXED %eax
- GOTO_NEXT
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IF_LEZ: /* 0x3d */
-/* File: x86/OP_IF_LEZ.S */
-/* File: x86/zcmp.S */
- /*
- * Generic one-operand compare-and-branch operation. Provide a "revcmp"
- * fragment that specifies the *reverse* comparison to perform, e.g.
- * for "if-le" you would use "gt".
- *
- * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
- */
- /* if-cmp vAA, +BBBB */
- cmpl $0,(rFP,rINST,4) # compare (vA, 0)
- movswl 2(rPC),rINST # fetch signed displacement
- movl $2,%eax # assume branch not taken
- jg 1f
- testl rINST,rINST
- js common_backwardBranch
- movl rINST,%eax
-1:
- FETCH_INST_INDEXED %eax
- ADVANCE_PC_INDEXED %eax
- GOTO_NEXT
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_3E: /* 0x3e */
-/* File: x86/OP_UNUSED_3E.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_3F: /* 0x3f */
-/* File: x86/OP_UNUSED_3F.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_40: /* 0x40 */
-/* File: x86/OP_UNUSED_40.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_41: /* 0x41 */
-/* File: x86/OP_UNUSED_41.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_42: /* 0x42 */
-/* File: x86/OP_UNUSED_42.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_43: /* 0x43 */
-/* File: x86/OP_UNUSED_43.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_AGET: /* 0x44 */
-/* File: x86/OP_AGET.S */
- /*
- * Array get, 32 bits or less. vAA <- vBB[vCC].
- *
- * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
- */
- /* op vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_R %eax %eax # eax<- vBB (array object)
- GET_VREG_R %ecx %ecx # ecs<- vCC (requested index)
- testl %eax,%eax # null array object?
- je common_errNullObject # bail if so
- cmpl offArrayObject_length(%eax),%ecx
- jae common_errArrayIndex # index >= length, bail. Expects
- # arrayObj in eax
- # index in ecx
- movl offArrayObject_contents(%eax,%ecx,4),%eax
-.LOP_AGET_finish:
- FETCH_INST_OPCODE 2 %edx
- SET_VREG %eax rINST
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_AGET_WIDE: /* 0x45 */
-/* File: x86/OP_AGET_WIDE.S */
- /*
- * Array get, 64 bits. vAA <- vBB[vCC].
- *
- */
- /* op vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_R %eax %eax # eax<- vBB (array object)
- GET_VREG_R %ecx %ecx # ecs<- vCC (requested index)
- testl %eax,%eax # null array object?
- je common_errNullObject # bail if so
- cmpl offArrayObject_length(%eax),%ecx
- jb .LOP_AGET_WIDE_finish # index < length, OK
- jmp common_errArrayIndex # index >= length, bail. Expects
- # arrayObj in eax
- # index in ecx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_AGET_OBJECT: /* 0x46 */
-/* File: x86/OP_AGET_OBJECT.S */
-/* File: x86/OP_AGET.S */
- /*
- * Array get, 32 bits or less. vAA <- vBB[vCC].
- *
- * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
- */
- /* op vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_R %eax %eax # eax<- vBB (array object)
- GET_VREG_R %ecx %ecx # ecs<- vCC (requested index)
- testl %eax,%eax # null array object?
- je common_errNullObject # bail if so
- cmpl offArrayObject_length(%eax),%ecx
- jae common_errArrayIndex # index >= length, bail. Expects
- # arrayObj in eax
- # index in ecx
- movl offArrayObject_contents(%eax,%ecx,4),%eax
-.LOP_AGET_OBJECT_finish:
- FETCH_INST_OPCODE 2 %edx
- SET_VREG %eax rINST
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_AGET_BOOLEAN: /* 0x47 */
-/* File: x86/OP_AGET_BOOLEAN.S */
-/* File: x86/OP_AGET.S */
- /*
- * Array get, 32 bits or less. vAA <- vBB[vCC].
- *
- * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
- */
- /* op vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_R %eax %eax # eax<- vBB (array object)
- GET_VREG_R %ecx %ecx # ecs<- vCC (requested index)
- testl %eax,%eax # null array object?
- je common_errNullObject # bail if so
- cmpl offArrayObject_length(%eax),%ecx
- jae common_errArrayIndex # index >= length, bail. Expects
- # arrayObj in eax
- # index in ecx
- movzbl offArrayObject_contents(%eax,%ecx,1),%eax
-.LOP_AGET_BOOLEAN_finish:
- FETCH_INST_OPCODE 2 %edx
- SET_VREG %eax rINST
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_AGET_BYTE: /* 0x48 */
-/* File: x86/OP_AGET_BYTE.S */
-/* File: x86/OP_AGET.S */
- /*
- * Array get, 32 bits or less. vAA <- vBB[vCC].
- *
- * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
- */
- /* op vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_R %eax %eax # eax<- vBB (array object)
- GET_VREG_R %ecx %ecx # ecs<- vCC (requested index)
- testl %eax,%eax # null array object?
- je common_errNullObject # bail if so
- cmpl offArrayObject_length(%eax),%ecx
- jae common_errArrayIndex # index >= length, bail. Expects
- # arrayObj in eax
- # index in ecx
- movsbl offArrayObject_contents(%eax,%ecx,1),%eax
-.LOP_AGET_BYTE_finish:
- FETCH_INST_OPCODE 2 %edx
- SET_VREG %eax rINST
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_AGET_CHAR: /* 0x49 */
-/* File: x86/OP_AGET_CHAR.S */
-/* File: x86/OP_AGET.S */
- /*
- * Array get, 32 bits or less. vAA <- vBB[vCC].
- *
- * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
- */
- /* op vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_R %eax %eax # eax<- vBB (array object)
- GET_VREG_R %ecx %ecx # ecs<- vCC (requested index)
- testl %eax,%eax # null array object?
- je common_errNullObject # bail if so
- cmpl offArrayObject_length(%eax),%ecx
- jae common_errArrayIndex # index >= length, bail. Expects
- # arrayObj in eax
- # index in ecx
- movzwl offArrayObject_contents(%eax,%ecx,2),%eax
-.LOP_AGET_CHAR_finish:
- FETCH_INST_OPCODE 2 %edx
- SET_VREG %eax rINST
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_AGET_SHORT: /* 0x4a */
-/* File: x86/OP_AGET_SHORT.S */
-/* File: x86/OP_AGET.S */
- /*
- * Array get, 32 bits or less. vAA <- vBB[vCC].
- *
- * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
- */
- /* op vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_R %eax %eax # eax<- vBB (array object)
- GET_VREG_R %ecx %ecx # ecs<- vCC (requested index)
- testl %eax,%eax # null array object?
- je common_errNullObject # bail if so
- cmpl offArrayObject_length(%eax),%ecx
- jae common_errArrayIndex # index >= length, bail. Expects
- # arrayObj in eax
- # index in ecx
- movswl offArrayObject_contents(%eax,%ecx,2),%eax
-.LOP_AGET_SHORT_finish:
- FETCH_INST_OPCODE 2 %edx
- SET_VREG %eax rINST
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_APUT: /* 0x4b */
-/* File: x86/OP_APUT.S */
- /*
- * Array put, 32 bits or less. vBB[vCC] <- vAA
- *
- * for: aput, aput-object, aput-boolean, aput-byte, aput-char, aput-short
- */
- /* op vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_R %eax %eax # eax<- vBB (array object)
- GET_VREG_R %ecx %ecx # ecs<- vCC (requested index)
- testl %eax,%eax # null array object?
- je common_errNullObject # bail if so
- cmpl offArrayObject_length(%eax),%ecx
- jae common_errArrayIndex # index >= length, bail. Expects:
- # arrayObj in eax
- # index in ecx
- leal offArrayObject_contents(%eax,%ecx,4),%eax
-.LOP_APUT_finish:
- GET_VREG_R %ecx rINST
- FETCH_INST_OPCODE 2 %edx
- movl %ecx,(%eax)
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_APUT_WIDE: /* 0x4c */
-/* File: x86/OP_APUT_WIDE.S */
- /*
- * Array put, 64 bits. vBB[vCC]<-vAA.
- *
- */
- /* op vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_R %eax %eax # eax<- vBB (array object)
- GET_VREG_R %ecx %ecx # ecs<- vCC (requested index)
- testl %eax,%eax # null array object?
- je common_errNullObject # bail if so
- cmpl offArrayObject_length(%eax),%ecx
- jb .LOP_APUT_WIDE_finish # index < length, OK
- jmp common_errArrayIndex # index >= length, bail. Expects:
- # arrayObj in eax
- # index in ecx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_APUT_OBJECT: /* 0x4d */
-/* File: x86/OP_APUT_OBJECT.S */
- /*
- * Array put, 32 bits or less. vBB[vCC] <- vAA
- *
- * for: aput, aput-object, aput-boolean, aput-byte, aput-char, aput-short
- */
- /* op vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_R %eax %eax # eax<- vBB (array object)
- GET_VREG_R %ecx %ecx # ecs<- vCC (requested index)
- GET_VREG_R rINST rINST # rINST<- vAA
- testl %eax,%eax # null array object?
- je common_errNullObject # bail if so
- cmpl offArrayObject_length(%eax),%ecx
- jb .LOP_APUT_OBJECT_continue
- jmp common_errArrayIndex # index >= length, bail. Expects
- # arrayObj in eax
- # index in ecx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_APUT_BOOLEAN: /* 0x4e */
-/* File: x86/OP_APUT_BOOLEAN.S */
-/* File: x86/OP_APUT.S */
- /*
- * Array put, 32 bits or less. vBB[vCC] <- vAA
- *
- * for: aput, aput-object, aput-boolean, aput-byte, aput-char, aput-short
- */
- /* op vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_R %eax %eax # eax<- vBB (array object)
- GET_VREG_R %ecx %ecx # ecs<- vCC (requested index)
- testl %eax,%eax # null array object?
- je common_errNullObject # bail if so
- cmpl offArrayObject_length(%eax),%ecx
- jae common_errArrayIndex # index >= length, bail. Expects:
- # arrayObj in eax
- # index in ecx
- leal offArrayObject_contents(%eax,%ecx,1),%eax
-.LOP_APUT_BOOLEAN_finish:
- GET_VREG_R %ecx rINST
- FETCH_INST_OPCODE 2 %edx
- movb %cl,(%eax)
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_APUT_BYTE: /* 0x4f */
-/* File: x86/OP_APUT_BYTE.S */
-/* File: x86/OP_APUT.S */
- /*
- * Array put, 32 bits or less. vBB[vCC] <- vAA
- *
- * for: aput, aput-object, aput-boolean, aput-byte, aput-char, aput-short
- */
- /* op vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_R %eax %eax # eax<- vBB (array object)
- GET_VREG_R %ecx %ecx # ecs<- vCC (requested index)
- testl %eax,%eax # null array object?
- je common_errNullObject # bail if so
- cmpl offArrayObject_length(%eax),%ecx
- jae common_errArrayIndex # index >= length, bail. Expects:
- # arrayObj in eax
- # index in ecx
- leal offArrayObject_contents(%eax,%ecx,1),%eax
-.LOP_APUT_BYTE_finish:
- GET_VREG_R %ecx rINST
- FETCH_INST_OPCODE 2 %edx
- movb %cl,(%eax)
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_APUT_CHAR: /* 0x50 */
-/* File: x86/OP_APUT_CHAR.S */
-/* File: x86/OP_APUT.S */
- /*
- * Array put, 32 bits or less. vBB[vCC] <- vAA
- *
- * for: aput, aput-object, aput-boolean, aput-byte, aput-char, aput-short
- */
- /* op vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_R %eax %eax # eax<- vBB (array object)
- GET_VREG_R %ecx %ecx # ecs<- vCC (requested index)
- testl %eax,%eax # null array object?
- je common_errNullObject # bail if so
- cmpl offArrayObject_length(%eax),%ecx
- jae common_errArrayIndex # index >= length, bail. Expects:
- # arrayObj in eax
- # index in ecx
- leal offArrayObject_contents(%eax,%ecx,2),%eax
-.LOP_APUT_CHAR_finish:
- GET_VREG_R %ecx rINST
- FETCH_INST_OPCODE 2 %edx
- movw %cx,(%eax)
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_APUT_SHORT: /* 0x51 */
-/* File: x86/OP_APUT_SHORT.S */
-/* File: x86/OP_APUT.S */
- /*
- * Array put, 32 bits or less. vBB[vCC] <- vAA
- *
- * for: aput, aput-object, aput-boolean, aput-byte, aput-char, aput-short
- */
- /* op vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_R %eax %eax # eax<- vBB (array object)
- GET_VREG_R %ecx %ecx # ecs<- vCC (requested index)
- testl %eax,%eax # null array object?
- je common_errNullObject # bail if so
- cmpl offArrayObject_length(%eax),%ecx
- jae common_errArrayIndex # index >= length, bail. Expects:
- # arrayObj in eax
- # index in ecx
- leal offArrayObject_contents(%eax,%ecx,2),%eax
-.LOP_APUT_SHORT_finish:
- GET_VREG_R %ecx rINST
- FETCH_INST_OPCODE 2 %edx
- movw %cx,(%eax)
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IGET: /* 0x52 */
-/* File: x86/OP_IGET.S */
- /*
- * General 32-bit instance field get.
- *
- * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
- */
- /* op vA, vB, field@CCCC */
- movl rSELF,%ecx
- movzwl 2(rPC),%edx # edx<- 0000CCCC
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IGET_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp) # needed by dvmResolveInstField
- movl rSELF,%edx
- jmp .LOP_IGET_resolve
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IGET_WIDE: /* 0x53 */
-/* File: x86/OP_IGET_WIDE.S */
- /*
- * 64-bit instance field get.
- *
- */
- /* op vA, vB, field@CCCC */
- movl rSELF,%ecx
- movzwl 2(rPC),%edx # edx<- 0000CCCC
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IGET_WIDE_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp) # for dvmResolveInstField
- movl rSELF,%edx
- jmp .LOP_IGET_WIDE_resolve
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IGET_OBJECT: /* 0x54 */
-/* File: x86/OP_IGET_OBJECT.S */
-/* File: x86/OP_IGET.S */
- /*
- * General 32-bit instance field get.
- *
- * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
- */
- /* op vA, vB, field@CCCC */
- movl rSELF,%ecx
- movzwl 2(rPC),%edx # edx<- 0000CCCC
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IGET_OBJECT_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp) # needed by dvmResolveInstField
- movl rSELF,%edx
- jmp .LOP_IGET_OBJECT_resolve
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IGET_BOOLEAN: /* 0x55 */
-/* File: x86/OP_IGET_BOOLEAN.S */
-/* File: x86/OP_IGET.S */
- /*
- * General 32-bit instance field get.
- *
- * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
- */
- /* op vA, vB, field@CCCC */
- movl rSELF,%ecx
- movzwl 2(rPC),%edx # edx<- 0000CCCC
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IGET_BOOLEAN_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp) # needed by dvmResolveInstField
- movl rSELF,%edx
- jmp .LOP_IGET_BOOLEAN_resolve
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IGET_BYTE: /* 0x56 */
-/* File: x86/OP_IGET_BYTE.S */
-/* File: x86/OP_IGET.S */
- /*
- * General 32-bit instance field get.
- *
- * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
- */
- /* op vA, vB, field@CCCC */
- movl rSELF,%ecx
- movzwl 2(rPC),%edx # edx<- 0000CCCC
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IGET_BYTE_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp) # needed by dvmResolveInstField
- movl rSELF,%edx
- jmp .LOP_IGET_BYTE_resolve
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IGET_CHAR: /* 0x57 */
-/* File: x86/OP_IGET_CHAR.S */
-/* File: x86/OP_IGET.S */
- /*
- * General 32-bit instance field get.
- *
- * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
- */
- /* op vA, vB, field@CCCC */
- movl rSELF,%ecx
- movzwl 2(rPC),%edx # edx<- 0000CCCC
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IGET_CHAR_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp) # needed by dvmResolveInstField
- movl rSELF,%edx
- jmp .LOP_IGET_CHAR_resolve
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IGET_SHORT: /* 0x58 */
-/* File: x86/OP_IGET_SHORT.S */
-/* File: x86/OP_IGET.S */
- /*
- * General 32-bit instance field get.
- *
- * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
- */
- /* op vA, vB, field@CCCC */
- movl rSELF,%ecx
- movzwl 2(rPC),%edx # edx<- 0000CCCC
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IGET_SHORT_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp) # needed by dvmResolveInstField
- movl rSELF,%edx
- jmp .LOP_IGET_SHORT_resolve
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IPUT: /* 0x59 */
-/* File: x86/OP_IPUT.S */
-
- /*
- * General 32-bit instance field put.
- *
- * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short
- */
- /* op vA, vB, field@CCCC */
- movl rSELF,%ecx
- movzwl 2(rPC),%edx # %edx<- 0000CCCC
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IPUT_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp)
- movl rSELF,%edx
- jmp .LOP_IPUT_resolve
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IPUT_WIDE: /* 0x5a */
-/* File: x86/OP_IPUT_WIDE.S */
- /*
- * 64-bit instance field put.
- *
- */
- /* op vA, vB, field@CCCC */
- movl rSELF,%ecx
- movzwl 2(rPC),%edx # edx<- 0000CCCC
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IPUT_WIDE_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp)
- movl rSELF,%edx
- jmp .LOP_IPUT_WIDE_resolve
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IPUT_OBJECT: /* 0x5b */
-/* File: x86/OP_IPUT_OBJECT.S */
- /*
- * Object field put.
- *
- * for: iput-object
- */
- /* op vA, vB, field@CCCC */
- movl rSELF,%ecx
- movzwl 2(rPC),%edx # edx<- 0000CCCC
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IPUT_OBJECT_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp)
- movl rSELF,%edx
- jmp .LOP_IPUT_OBJECT_resolve
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IPUT_BOOLEAN: /* 0x5c */
-/* File: x86/OP_IPUT_BOOLEAN.S */
-/* File: x86/OP_IPUT.S */
-
- /*
- * General 32-bit instance field put.
- *
- * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short
- */
- /* op vA, vB, field@CCCC */
- movl rSELF,%ecx
- movzwl 2(rPC),%edx # %edx<- 0000CCCC
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IPUT_BOOLEAN_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp)
- movl rSELF,%edx
- jmp .LOP_IPUT_BOOLEAN_resolve
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IPUT_BYTE: /* 0x5d */
-/* File: x86/OP_IPUT_BYTE.S */
-/* File: x86/OP_IPUT.S */
-
- /*
- * General 32-bit instance field put.
- *
- * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short
- */
- /* op vA, vB, field@CCCC */
- movl rSELF,%ecx
- movzwl 2(rPC),%edx # %edx<- 0000CCCC
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IPUT_BYTE_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp)
- movl rSELF,%edx
- jmp .LOP_IPUT_BYTE_resolve
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IPUT_CHAR: /* 0x5e */
-/* File: x86/OP_IPUT_CHAR.S */
-/* File: x86/OP_IPUT.S */
-
- /*
- * General 32-bit instance field put.
- *
- * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short
- */
- /* op vA, vB, field@CCCC */
- movl rSELF,%ecx
- movzwl 2(rPC),%edx # %edx<- 0000CCCC
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IPUT_CHAR_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp)
- movl rSELF,%edx
- jmp .LOP_IPUT_CHAR_resolve
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IPUT_SHORT: /* 0x5f */
-/* File: x86/OP_IPUT_SHORT.S */
-/* File: x86/OP_IPUT.S */
-
- /*
- * General 32-bit instance field put.
- *
- * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short
- */
- /* op vA, vB, field@CCCC */
- movl rSELF,%ecx
- movzwl 2(rPC),%edx # %edx<- 0000CCCC
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IPUT_SHORT_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp)
- movl rSELF,%edx
- jmp .LOP_IPUT_SHORT_resolve
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SGET: /* 0x60 */
-/* File: x86/OP_SGET.S */
- /*
- * General 32-bit SGET handler.
- *
- * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
- */
- /* op vAA, field@BBBB */
- movl rSELF,%ecx
- movzwl 2(rPC),%eax # eax<- field ref BBBB
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SGET_resolve # if not, make it so
-.LOP_SGET_finish: # field ptr in eax
- movl offStaticField_value(%eax),%eax
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- SET_VREG %eax rINST
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SGET_WIDE: /* 0x61 */
-/* File: x86/OP_SGET_WIDE.S */
- /*
- * 64-bit SGET handler.
- *
- */
- /* sget-wide vAA, field@BBBB */
- movl rSELF,%ecx
- movzwl 2(rPC),%eax # eax<- field ref BBBB
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SGET_WIDE_resolve # if not, make it so
-.LOP_SGET_WIDE_finish: # field ptr in eax
- movl offStaticField_value(%eax),%ecx # ecx<- lsw
- movl 4+offStaticField_value(%eax),%eax # eax<- msw
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- SET_VREG_WORD %ecx rINST 0
- SET_VREG_WORD %eax rINST 1
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SGET_OBJECT: /* 0x62 */
-/* File: x86/OP_SGET_OBJECT.S */
-/* File: x86/OP_SGET.S */
- /*
- * General 32-bit SGET handler.
- *
- * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
- */
- /* op vAA, field@BBBB */
- movl rSELF,%ecx
- movzwl 2(rPC),%eax # eax<- field ref BBBB
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SGET_OBJECT_resolve # if not, make it so
-.LOP_SGET_OBJECT_finish: # field ptr in eax
- movl offStaticField_value(%eax),%eax
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- SET_VREG %eax rINST
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SGET_BOOLEAN: /* 0x63 */
-/* File: x86/OP_SGET_BOOLEAN.S */
-/* File: x86/OP_SGET.S */
- /*
- * General 32-bit SGET handler.
- *
- * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
- */
- /* op vAA, field@BBBB */
- movl rSELF,%ecx
- movzwl 2(rPC),%eax # eax<- field ref BBBB
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SGET_BOOLEAN_resolve # if not, make it so
-.LOP_SGET_BOOLEAN_finish: # field ptr in eax
- movl offStaticField_value(%eax),%eax
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- SET_VREG %eax rINST
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SGET_BYTE: /* 0x64 */
-/* File: x86/OP_SGET_BYTE.S */
-/* File: x86/OP_SGET.S */
- /*
- * General 32-bit SGET handler.
- *
- * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
- */
- /* op vAA, field@BBBB */
- movl rSELF,%ecx
- movzwl 2(rPC),%eax # eax<- field ref BBBB
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SGET_BYTE_resolve # if not, make it so
-.LOP_SGET_BYTE_finish: # field ptr in eax
- movl offStaticField_value(%eax),%eax
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- SET_VREG %eax rINST
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SGET_CHAR: /* 0x65 */
-/* File: x86/OP_SGET_CHAR.S */
-/* File: x86/OP_SGET.S */
- /*
- * General 32-bit SGET handler.
- *
- * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
- */
- /* op vAA, field@BBBB */
- movl rSELF,%ecx
- movzwl 2(rPC),%eax # eax<- field ref BBBB
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SGET_CHAR_resolve # if not, make it so
-.LOP_SGET_CHAR_finish: # field ptr in eax
- movl offStaticField_value(%eax),%eax
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- SET_VREG %eax rINST
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SGET_SHORT: /* 0x66 */
-/* File: x86/OP_SGET_SHORT.S */
-/* File: x86/OP_SGET.S */
- /*
- * General 32-bit SGET handler.
- *
- * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
- */
- /* op vAA, field@BBBB */
- movl rSELF,%ecx
- movzwl 2(rPC),%eax # eax<- field ref BBBB
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SGET_SHORT_resolve # if not, make it so
-.LOP_SGET_SHORT_finish: # field ptr in eax
- movl offStaticField_value(%eax),%eax
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- SET_VREG %eax rINST
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SPUT: /* 0x67 */
-/* File: x86/OP_SPUT.S */
- /*
- * General 32-bit SPUT handler.
- *
- * for: sput, sput-boolean, sput-byte, sput-char, sput-short
- */
- /* op vAA, field@BBBB */
- movl rSELF,%ecx
- movzwl 2(rPC),%eax # eax<- field ref BBBB
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SPUT_resolve # if not, make it so
-.LOP_SPUT_finish: # field ptr in eax
- GET_VREG_R %ecx rINST
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- movl %ecx,offStaticField_value(%eax)
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SPUT_WIDE: /* 0x68 */
-/* File: x86/OP_SPUT_WIDE.S */
- /*
- * General 32-bit SPUT handler.
- *
- * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short
- */
- /* op vAA, field@BBBB */
- movl rSELF,%ecx
- movzwl 2(rPC),%eax # eax<- field ref BBBB
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SPUT_WIDE_resolve # if not, make it so
-.LOP_SPUT_WIDE_finish: # field ptr in eax
- GET_VREG_WORD %ecx rINST 0 # rINST<- lsw
- GET_VREG_WORD rINST rINST 1 # ecx<- msw
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- movl %ecx,offStaticField_value(%eax)
- movl rINST,4+offStaticField_value(%eax)
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SPUT_OBJECT: /* 0x69 */
-/* File: x86/OP_SPUT_OBJECT.S */
- /*
- * SPUT object handler.
- */
- /* op vAA, field@BBBB */
- movl rSELF,%ecx
- movzwl 2(rPC),%eax # eax<- field ref BBBB
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField
- testl %eax,%eax # resolved entry null?
- je .LOP_SPUT_OBJECT_resolve # if not, make it so
-.LOP_SPUT_OBJECT_finish: # field ptr in eax
- movzbl rINSTbl,%ecx # ecx<- AA
- GET_VREG_R %ecx %ecx
- jmp .LOP_SPUT_OBJECT_continue
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SPUT_BOOLEAN: /* 0x6a */
-/* File: x86/OP_SPUT_BOOLEAN.S */
-/* File: x86/OP_SPUT.S */
- /*
- * General 32-bit SPUT handler.
- *
- * for: sput, sput-boolean, sput-byte, sput-char, sput-short
- */
- /* op vAA, field@BBBB */
- movl rSELF,%ecx
- movzwl 2(rPC),%eax # eax<- field ref BBBB
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SPUT_BOOLEAN_resolve # if not, make it so
-.LOP_SPUT_BOOLEAN_finish: # field ptr in eax
- GET_VREG_R %ecx rINST
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- movl %ecx,offStaticField_value(%eax)
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SPUT_BYTE: /* 0x6b */
-/* File: x86/OP_SPUT_BYTE.S */
-/* File: x86/OP_SPUT.S */
- /*
- * General 32-bit SPUT handler.
- *
- * for: sput, sput-boolean, sput-byte, sput-char, sput-short
- */
- /* op vAA, field@BBBB */
- movl rSELF,%ecx
- movzwl 2(rPC),%eax # eax<- field ref BBBB
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SPUT_BYTE_resolve # if not, make it so
-.LOP_SPUT_BYTE_finish: # field ptr in eax
- GET_VREG_R %ecx rINST
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- movl %ecx,offStaticField_value(%eax)
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SPUT_CHAR: /* 0x6c */
-/* File: x86/OP_SPUT_CHAR.S */
-/* File: x86/OP_SPUT.S */
- /*
- * General 32-bit SPUT handler.
- *
- * for: sput, sput-boolean, sput-byte, sput-char, sput-short
- */
- /* op vAA, field@BBBB */
- movl rSELF,%ecx
- movzwl 2(rPC),%eax # eax<- field ref BBBB
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SPUT_CHAR_resolve # if not, make it so
-.LOP_SPUT_CHAR_finish: # field ptr in eax
- GET_VREG_R %ecx rINST
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- movl %ecx,offStaticField_value(%eax)
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SPUT_SHORT: /* 0x6d */
-/* File: x86/OP_SPUT_SHORT.S */
-/* File: x86/OP_SPUT.S */
- /*
- * General 32-bit SPUT handler.
- *
- * for: sput, sput-boolean, sput-byte, sput-char, sput-short
- */
- /* op vAA, field@BBBB */
- movl rSELF,%ecx
- movzwl 2(rPC),%eax # eax<- field ref BBBB
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SPUT_SHORT_resolve # if not, make it so
-.LOP_SPUT_SHORT_finish: # field ptr in eax
- GET_VREG_R %ecx rINST
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- movl %ecx,offStaticField_value(%eax)
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_INVOKE_VIRTUAL: /* 0x6e */
-/* File: x86/OP_INVOKE_VIRTUAL.S */
-
- /*
- * Handle a virtual method call.
- *
- * for: invoke-virtual, invoke-virtual/range
- */
- /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
- /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
- movl rSELF,%eax
- movzwl 2(rPC),%ecx # ecx<- BBBB
- movl offThread_methodClassDex(%eax),%eax # eax<- pDvmDex
- EXPORT_PC
- movl offDvmDex_pResMethods(%eax),%eax # eax<- pDvmDex->pResMethods
- movl (%eax,%ecx,4),%eax # eax<- resolved baseMethod
- testl %eax,%eax # already resolved?
- jne .LOP_INVOKE_VIRTUAL_continue # yes, continue
- movl rSELF,%eax
- movl %ecx,OUT_ARG1(%esp) # arg1<- ref
- movl offThread_method(%eax),%eax # eax<- self->method
- jmp .LOP_INVOKE_VIRTUAL_more
-
-/* ------------------------------ */
- .balign 64
-.L_OP_INVOKE_SUPER: /* 0x6f */
-/* File: x86/OP_INVOKE_SUPER.S */
- /*
- * Handle a "super" method call.
- *
- * for: invoke-super, invoke-super/range
- */
- /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
- /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
- movl rSELF,rINST
- movzwl 2(rPC),%eax # eax<- BBBB
- movl offThread_methodClassDex(rINST),%ecx # ecx<- pDvmDex
- EXPORT_PC
- movl offDvmDex_pResMethods(%ecx),%ecx # ecx<- pDvmDex->pResMethods
- movl (%ecx,%eax,4),%ecx # ecx<- resolved baseMethod
- movl offThread_method(rINST),%eax # eax<- method
- movzwl 4(rPC),rINST # rINST<- GFED or CCCC
- .if (!0)
- andl $0xf,rINST # rINST<- D (or stays CCCC)
- .endif
- GET_VREG_R rINST rINST # rINST<- "this" ptr
- testl rINST,rINST # null "this"?
- je common_errNullObject # yes, throw
- movl offMethod_clazz(%eax),%eax # eax<- method->clazz
- testl %ecx,%ecx # already resolved?
- jne .LOP_INVOKE_SUPER_continue # yes - go on
- jmp .LOP_INVOKE_SUPER_resolve
-
-/* ------------------------------ */
- .balign 64
-.L_OP_INVOKE_DIRECT: /* 0x70 */
-/* File: x86/OP_INVOKE_DIRECT.S */
- /*
- * Handle a direct method call.
- *
- * (We could defer the "is 'this' pointer null" test to the common
- * method invocation code, and use a flag to indicate that static
- * calls don't count. If we do this as part of copying the arguments
- * out we could avoiding loading the first arg twice.)
- *
- * for: invoke-direct, invoke-direct/range
- */
- /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
- /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
- movl rSELF,%ecx
- movzwl 2(rPC),%eax # eax<- BBBB
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
- EXPORT_PC
- movl offDvmDex_pResMethods(%ecx),%ecx # ecx<- pDvmDex->pResMethods
- movzwl 4(rPC),%edx # edx<- GFED or CCCC
- movl (%ecx,%eax,4),%eax # eax<- resolved methodToCall
- .if (!0)
- andl $0xf,%edx # edx<- D (or stays CCCC)
- .endif
- testl %eax,%eax # already resolved?
- GET_VREG_R %ecx %edx # ecx<- "this" ptr
- je .LOP_INVOKE_DIRECT_resolve # not resolved, do it now
-.LOP_INVOKE_DIRECT_finish:
- testl %ecx,%ecx # null "this"?
- jne common_invokeMethodNoRange # no, continue on
- jmp common_errNullObject
-
-/* ------------------------------ */
- .balign 64
-.L_OP_INVOKE_STATIC: /* 0x71 */
-/* File: x86/OP_INVOKE_STATIC.S */
- /*
- * Handle a static method call.
- *
- * for: invoke-static, invoke-static/range
- */
- /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
- /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
- movl rSELF,%ecx
- movzwl 2(rPC),%eax # eax<- BBBB
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
- EXPORT_PC
- movl offDvmDex_pResMethods(%ecx),%ecx # ecx<- pDvmDex->pResMethods
- movl (%ecx,%eax,4),%eax # eax<- resolved methodToCall
- testl %eax,%eax
- jne common_invokeMethodNoRange
- movl rSELF,%ecx
- movl offThread_method(%ecx),%ecx # ecx<- self->method
- movzwl 2(rPC),%eax
- movl offMethod_clazz(%ecx),%ecx# ecx<- method->clazz
- movl %eax,OUT_ARG1(%esp) # arg1<- BBBB
- movl %ecx,OUT_ARG0(%esp) # arg0<- clazz
- jmp .LOP_INVOKE_STATIC_continue
-
-/* ------------------------------ */
- .balign 64
-.L_OP_INVOKE_INTERFACE: /* 0x72 */
-/* File: x86/OP_INVOKE_INTERFACE.S */
- /*
- * Handle an interface method call.
- *
- * for: invoke-interface, invoke-interface/range
- */
- /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
- /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
- movzwl 4(rPC),%eax # eax<- FEDC or CCCC
- movl rSELF,%ecx
- .if (!0)
- andl $0xf,%eax # eax<- C (or stays CCCC)
- .endif
- GET_VREG_R %eax %eax # eax<- "this"
- EXPORT_PC
- testl %eax,%eax # null this?
- je common_errNullObject # yes, fail
- movl offObject_clazz(%eax),%eax# eax<- thisPtr->clazz
- movl %eax,OUT_ARG0(%esp) # arg0<- class
- movl offThread_methodClassDex(%ecx),%eax # eax<- methodClassDex
- movl offThread_method(%ecx),%ecx # ecx<- method
- movl %eax,OUT_ARG3(%esp) # arg3<- dex
- movzwl 2(rPC),%eax # eax<- BBBB
- movl %ecx,OUT_ARG2(%esp) # arg2<- method
- movl %eax,OUT_ARG1(%esp) # arg1<- BBBB
- jmp .LOP_INVOKE_INTERFACE_continue
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_73: /* 0x73 */
-/* File: x86/OP_UNUSED_73.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */
-/* File: x86/OP_INVOKE_VIRTUAL_RANGE.S */
-/* File: x86/OP_INVOKE_VIRTUAL.S */
-
- /*
- * Handle a virtual method call.
- *
- * for: invoke-virtual, invoke-virtual/range
- */
- /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
- /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
- movl rSELF,%eax
- movzwl 2(rPC),%ecx # ecx<- BBBB
- movl offThread_methodClassDex(%eax),%eax # eax<- pDvmDex
- EXPORT_PC
- movl offDvmDex_pResMethods(%eax),%eax # eax<- pDvmDex->pResMethods
- movl (%eax,%ecx,4),%eax # eax<- resolved baseMethod
- testl %eax,%eax # already resolved?
- jne .LOP_INVOKE_VIRTUAL_RANGE_continue # yes, continue
- movl rSELF,%eax
- movl %ecx,OUT_ARG1(%esp) # arg1<- ref
- movl offThread_method(%eax),%eax # eax<- self->method
- jmp .LOP_INVOKE_VIRTUAL_RANGE_more
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_INVOKE_SUPER_RANGE: /* 0x75 */
-/* File: x86/OP_INVOKE_SUPER_RANGE.S */
-/* File: x86/OP_INVOKE_SUPER.S */
- /*
- * Handle a "super" method call.
- *
- * for: invoke-super, invoke-super/range
- */
- /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
- /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
- movl rSELF,rINST
- movzwl 2(rPC),%eax # eax<- BBBB
- movl offThread_methodClassDex(rINST),%ecx # ecx<- pDvmDex
- EXPORT_PC
- movl offDvmDex_pResMethods(%ecx),%ecx # ecx<- pDvmDex->pResMethods
- movl (%ecx,%eax,4),%ecx # ecx<- resolved baseMethod
- movl offThread_method(rINST),%eax # eax<- method
- movzwl 4(rPC),rINST # rINST<- GFED or CCCC
- .if (!1)
- andl $0xf,rINST # rINST<- D (or stays CCCC)
- .endif
- GET_VREG_R rINST rINST # rINST<- "this" ptr
- testl rINST,rINST # null "this"?
- je common_errNullObject # yes, throw
- movl offMethod_clazz(%eax),%eax # eax<- method->clazz
- testl %ecx,%ecx # already resolved?
- jne .LOP_INVOKE_SUPER_RANGE_continue # yes - go on
- jmp .LOP_INVOKE_SUPER_RANGE_resolve
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_INVOKE_DIRECT_RANGE: /* 0x76 */
-/* File: x86/OP_INVOKE_DIRECT_RANGE.S */
-/* File: x86/OP_INVOKE_DIRECT.S */
- /*
- * Handle a direct method call.
- *
- * (We could defer the "is 'this' pointer null" test to the common
- * method invocation code, and use a flag to indicate that static
- * calls don't count. If we do this as part of copying the arguments
- * out we could avoiding loading the first arg twice.)
- *
- * for: invoke-direct, invoke-direct/range
- */
- /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
- /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
- movl rSELF,%ecx
- movzwl 2(rPC),%eax # eax<- BBBB
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
- EXPORT_PC
- movl offDvmDex_pResMethods(%ecx),%ecx # ecx<- pDvmDex->pResMethods
- movzwl 4(rPC),%edx # edx<- GFED or CCCC
- movl (%ecx,%eax,4),%eax # eax<- resolved methodToCall
- .if (!1)
- andl $0xf,%edx # edx<- D (or stays CCCC)
- .endif
- testl %eax,%eax # already resolved?
- GET_VREG_R %ecx %edx # ecx<- "this" ptr
- je .LOP_INVOKE_DIRECT_RANGE_resolve # not resolved, do it now
-.LOP_INVOKE_DIRECT_RANGE_finish:
- testl %ecx,%ecx # null "this"?
- jne common_invokeMethodRange # no, continue on
- jmp common_errNullObject
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_INVOKE_STATIC_RANGE: /* 0x77 */
-/* File: x86/OP_INVOKE_STATIC_RANGE.S */
-/* File: x86/OP_INVOKE_STATIC.S */
- /*
- * Handle a static method call.
- *
- * for: invoke-static, invoke-static/range
- */
- /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
- /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
- movl rSELF,%ecx
- movzwl 2(rPC),%eax # eax<- BBBB
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
- EXPORT_PC
- movl offDvmDex_pResMethods(%ecx),%ecx # ecx<- pDvmDex->pResMethods
- movl (%ecx,%eax,4),%eax # eax<- resolved methodToCall
- testl %eax,%eax
- jne common_invokeMethodRange
- movl rSELF,%ecx
- movl offThread_method(%ecx),%ecx # ecx<- self->method
- movzwl 2(rPC),%eax
- movl offMethod_clazz(%ecx),%ecx# ecx<- method->clazz
- movl %eax,OUT_ARG1(%esp) # arg1<- BBBB
- movl %ecx,OUT_ARG0(%esp) # arg0<- clazz
- jmp .LOP_INVOKE_STATIC_RANGE_continue
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */
-/* File: x86/OP_INVOKE_INTERFACE_RANGE.S */
-/* File: x86/OP_INVOKE_INTERFACE.S */
- /*
- * Handle an interface method call.
- *
- * for: invoke-interface, invoke-interface/range
- */
- /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
- /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
- movzwl 4(rPC),%eax # eax<- FEDC or CCCC
- movl rSELF,%ecx
- .if (!1)
- andl $0xf,%eax # eax<- C (or stays CCCC)
- .endif
- GET_VREG_R %eax %eax # eax<- "this"
- EXPORT_PC
- testl %eax,%eax # null this?
- je common_errNullObject # yes, fail
- movl offObject_clazz(%eax),%eax# eax<- thisPtr->clazz
- movl %eax,OUT_ARG0(%esp) # arg0<- class
- movl offThread_methodClassDex(%ecx),%eax # eax<- methodClassDex
- movl offThread_method(%ecx),%ecx # ecx<- method
- movl %eax,OUT_ARG3(%esp) # arg3<- dex
- movzwl 2(rPC),%eax # eax<- BBBB
- movl %ecx,OUT_ARG2(%esp) # arg2<- method
- movl %eax,OUT_ARG1(%esp) # arg1<- BBBB
- jmp .LOP_INVOKE_INTERFACE_RANGE_continue
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_79: /* 0x79 */
-/* File: x86/OP_UNUSED_79.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_7A: /* 0x7a */
-/* File: x86/OP_UNUSED_7A.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_NEG_INT: /* 0x7b */
-/* File: x86/OP_NEG_INT.S */
-/* File: x86/unop.S */
- /*
- * Generic 32-bit unary operation. Provide an "instr" line that
- * specifies an instruction that performs "result = op eax".
- */
- /* unop vA, vB */
- movzbl rINSTbl,%ecx # ecx<- A+
- sarl $4,rINST # rINST<- B
- GET_VREG_R %eax rINST # eax<- vB
- andb $0xf,%cl # ecx<- A
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
-
-
- negl %eax
- SET_VREG %eax %ecx
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_NOT_INT: /* 0x7c */
-/* File: x86/OP_NOT_INT.S */
-/* File: x86/unop.S */
- /*
- * Generic 32-bit unary operation. Provide an "instr" line that
- * specifies an instruction that performs "result = op eax".
- */
- /* unop vA, vB */
- movzbl rINSTbl,%ecx # ecx<- A+
- sarl $4,rINST # rINST<- B
- GET_VREG_R %eax rINST # eax<- vB
- andb $0xf,%cl # ecx<- A
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
-
-
- notl %eax
- SET_VREG %eax %ecx
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_NEG_LONG: /* 0x7d */
-/* File: x86/OP_NEG_LONG.S */
- /* unop vA, vB */
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_WORD %eax %ecx 0 # eax<- v[B+0]
- GET_VREG_WORD %ecx %ecx 1 # ecx<- v[B+1]
- negl %eax
- adcl $0,%ecx
- negl %ecx
- FETCH_INST_OPCODE 1 %edx
- SET_VREG_WORD %eax rINST 0 # v[A+0]<- eax
- SET_VREG_WORD %ecx rINST 1 # v[A+1]<- ecx
- ADVANCE_PC 1
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_NOT_LONG: /* 0x7e */
-/* File: x86/OP_NOT_LONG.S */
- /* unop vA, vB */
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_WORD %eax %ecx 0 # eax<- v[B+0]
- GET_VREG_WORD %ecx %ecx 1 # ecx<- v[B+1]
- FETCH_INST_OPCODE 1 %edx
- notl %eax
- notl %ecx
- SET_VREG_WORD %eax rINST 0 # v[A+0]<- eax
- SET_VREG_WORD %ecx rINST 1 # v[A+1]<- ecx
- ADVANCE_PC 1
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_NEG_FLOAT: /* 0x7f */
-/* File: x86/OP_NEG_FLOAT.S */
-/* File: x86/fpcvt.S */
- /*
- * Generic 32-bit FP conversion operation.
- */
- /* unop vA, vB */
- movzbl rINSTbl,%ecx # ecx<- A+
- sarl $4,rINST # rINST<- B
- flds (rFP,rINST,4) # %st0<- vB
- andb $0xf,%cl # ecx<- A
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
- fchs
- fstps (rFP,%ecx,4) # vA<- %st0
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_NEG_DOUBLE: /* 0x80 */
-/* File: x86/OP_NEG_DOUBLE.S */
-/* File: x86/fpcvt.S */
- /*
- * Generic 32-bit FP conversion operation.
- */
- /* unop vA, vB */
- movzbl rINSTbl,%ecx # ecx<- A+
- sarl $4,rINST # rINST<- B
- fldl (rFP,rINST,4) # %st0<- vB
- andb $0xf,%cl # ecx<- A
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
- fchs
- fstpl (rFP,%ecx,4) # vA<- %st0
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_INT_TO_LONG: /* 0x81 */
-/* File: x86/OP_INT_TO_LONG.S */
- /* int to long vA, vB */
- movzbl rINSTbl,%eax # eax<- +A
- sarl $4,%eax # eax<- B
- GET_VREG_R %eax %eax # eax<- vB
- andb $0xf,rINSTbl # rINST<- A
- cltd # edx:eax<- sssssssBBBBBBBB
- SET_VREG_WORD %edx rINST 1 # v[A+1]<- edx/rPC
- FETCH_INST_OPCODE 1 %edx
- SET_VREG_WORD %eax rINST 0 # v[A+0]<- %eax
- ADVANCE_PC 1
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_INT_TO_FLOAT: /* 0x82 */
-/* File: x86/OP_INT_TO_FLOAT.S */
-/* File: x86/fpcvt.S */
- /*
- * Generic 32-bit FP conversion operation.
- */
- /* unop vA, vB */
- movzbl rINSTbl,%ecx # ecx<- A+
- sarl $4,rINST # rINST<- B
- fildl (rFP,rINST,4) # %st0<- vB
- andb $0xf,%cl # ecx<- A
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
-
- fstps (rFP,%ecx,4) # vA<- %st0
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_INT_TO_DOUBLE: /* 0x83 */
-/* File: x86/OP_INT_TO_DOUBLE.S */
-/* File: x86/fpcvt.S */
- /*
- * Generic 32-bit FP conversion operation.
- */
- /* unop vA, vB */
- movzbl rINSTbl,%ecx # ecx<- A+
- sarl $4,rINST # rINST<- B
- fildl (rFP,rINST,4) # %st0<- vB
- andb $0xf,%cl # ecx<- A
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
-
- fstpl (rFP,%ecx,4) # vA<- %st0
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_LONG_TO_INT: /* 0x84 */
-/* File: x86/OP_LONG_TO_INT.S */
-/* we ignore the high word, making this equivalent to a 32-bit reg move */
-/* File: x86/OP_MOVE.S */
- /* for move, move-object, long-to-int */
- /* op vA, vB */
- movzbl rINSTbl,%eax # eax<- BA
- andb $0xf,%al # eax<- A
- shrl $4,rINST # rINST<- B
- GET_VREG_R %ecx rINST
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
- SET_VREG %ecx %eax # fp[A]<-fp[B]
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_LONG_TO_FLOAT: /* 0x85 */
-/* File: x86/OP_LONG_TO_FLOAT.S */
-/* File: x86/fpcvt.S */
- /*
- * Generic 32-bit FP conversion operation.
- */
- /* unop vA, vB */
- movzbl rINSTbl,%ecx # ecx<- A+
- sarl $4,rINST # rINST<- B
- fildll (rFP,rINST,4) # %st0<- vB
- andb $0xf,%cl # ecx<- A
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
-
- fstps (rFP,%ecx,4) # vA<- %st0
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_LONG_TO_DOUBLE: /* 0x86 */
-/* File: x86/OP_LONG_TO_DOUBLE.S */
-/* File: x86/fpcvt.S */
- /*
- * Generic 32-bit FP conversion operation.
- */
- /* unop vA, vB */
- movzbl rINSTbl,%ecx # ecx<- A+
- sarl $4,rINST # rINST<- B
- fildll (rFP,rINST,4) # %st0<- vB
- andb $0xf,%cl # ecx<- A
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
-
- fstpl (rFP,%ecx,4) # vA<- %st0
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_FLOAT_TO_INT: /* 0x87 */
-/* File: x86/OP_FLOAT_TO_INT.S */
-/* File: x86/cvtfp_int.S */
-/* On fp to int conversions, Java requires that
- * if the result > maxint, it should be clamped to maxint. If it is less
- * than minint, it should be clamped to minint. If it is a nan, the result
- * should be zero. Further, the rounding mode is to truncate. This model
- * differs from what is delivered normally via the x86 fpu, so we have
- * to play some games.
- */
- /* float/double to int/long vA, vB */
- movzbl rINSTbl,%ecx # ecx<- A+
- sarl $4,rINST # rINST<- B
- .if 0
- fldl (rFP,rINST,4) # %st0<- vB
- .else
- flds (rFP,rINST,4) # %st0<- vB
- .endif
- ftst
- fnstcw LOCAL0_OFFSET(%ebp) # remember original rounding mode
- movzwl LOCAL0_OFFSET(%ebp),%eax
- movb $0xc,%ah
- movw %ax,LOCAL0_OFFSET+2(%ebp)
- fldcw LOCAL0_OFFSET+2(%ebp) # set "to zero" rounding mode
- FETCH_INST_OPCODE 1 %edx
- andb $0xf,%cl # ecx<- A
- .if 0
- fistpll (rFP,%ecx,4) # convert and store
- .else
- fistpl (rFP,%ecx,4) # convert and store
- .endif
- fldcw LOCAL0_OFFSET(%ebp) # restore previous rounding mode
- jmp .LOP_FLOAT_TO_INT_continue
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_FLOAT_TO_LONG: /* 0x88 */
-/* File: x86/OP_FLOAT_TO_LONG.S */
-/* File: x86/cvtfp_int.S */
-/* On fp to int conversions, Java requires that
- * if the result > maxint, it should be clamped to maxint. If it is less
- * than minint, it should be clamped to minint. If it is a nan, the result
- * should be zero. Further, the rounding mode is to truncate. This model
- * differs from what is delivered normally via the x86 fpu, so we have
- * to play some games.
- */
- /* float/double to int/long vA, vB */
- movzbl rINSTbl,%ecx # ecx<- A+
- sarl $4,rINST # rINST<- B
- .if 0
- fldl (rFP,rINST,4) # %st0<- vB
- .else
- flds (rFP,rINST,4) # %st0<- vB
- .endif
- ftst
- fnstcw LOCAL0_OFFSET(%ebp) # remember original rounding mode
- movzwl LOCAL0_OFFSET(%ebp),%eax
- movb $0xc,%ah
- movw %ax,LOCAL0_OFFSET+2(%ebp)
- fldcw LOCAL0_OFFSET+2(%ebp) # set "to zero" rounding mode
- FETCH_INST_OPCODE 1 %edx
- andb $0xf,%cl # ecx<- A
- .if 1
- fistpll (rFP,%ecx,4) # convert and store
- .else
- fistpl (rFP,%ecx,4) # convert and store
- .endif
- fldcw LOCAL0_OFFSET(%ebp) # restore previous rounding mode
- jmp .LOP_FLOAT_TO_LONG_continue
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_FLOAT_TO_DOUBLE: /* 0x89 */
-/* File: x86/OP_FLOAT_TO_DOUBLE.S */
-/* File: x86/fpcvt.S */
- /*
- * Generic 32-bit FP conversion operation.
- */
- /* unop vA, vB */
- movzbl rINSTbl,%ecx # ecx<- A+
- sarl $4,rINST # rINST<- B
- flds (rFP,rINST,4) # %st0<- vB
- andb $0xf,%cl # ecx<- A
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
-
- fstpl (rFP,%ecx,4) # vA<- %st0
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_DOUBLE_TO_INT: /* 0x8a */
-/* File: x86/OP_DOUBLE_TO_INT.S */
-/* File: x86/cvtfp_int.S */
-/* On fp to int conversions, Java requires that
- * if the result > maxint, it should be clamped to maxint. If it is less
- * than minint, it should be clamped to minint. If it is a nan, the result
- * should be zero. Further, the rounding mode is to truncate. This model
- * differs from what is delivered normally via the x86 fpu, so we have
- * to play some games.
- */
- /* float/double to int/long vA, vB */
- movzbl rINSTbl,%ecx # ecx<- A+
- sarl $4,rINST # rINST<- B
- .if 1
- fldl (rFP,rINST,4) # %st0<- vB
- .else
- flds (rFP,rINST,4) # %st0<- vB
- .endif
- ftst
- fnstcw LOCAL0_OFFSET(%ebp) # remember original rounding mode
- movzwl LOCAL0_OFFSET(%ebp),%eax
- movb $0xc,%ah
- movw %ax,LOCAL0_OFFSET+2(%ebp)
- fldcw LOCAL0_OFFSET+2(%ebp) # set "to zero" rounding mode
- FETCH_INST_OPCODE 1 %edx
- andb $0xf,%cl # ecx<- A
- .if 0
- fistpll (rFP,%ecx,4) # convert and store
- .else
- fistpl (rFP,%ecx,4) # convert and store
- .endif
- fldcw LOCAL0_OFFSET(%ebp) # restore previous rounding mode
- jmp .LOP_DOUBLE_TO_INT_continue
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_DOUBLE_TO_LONG: /* 0x8b */
-/* File: x86/OP_DOUBLE_TO_LONG.S */
-/* File: x86/cvtfp_int.S */
-/* On fp to int conversions, Java requires that
- * if the result > maxint, it should be clamped to maxint. If it is less
- * than minint, it should be clamped to minint. If it is a nan, the result
- * should be zero. Further, the rounding mode is to truncate. This model
- * differs from what is delivered normally via the x86 fpu, so we have
- * to play some games.
- */
- /* float/double to int/long vA, vB */
- movzbl rINSTbl,%ecx # ecx<- A+
- sarl $4,rINST # rINST<- B
- .if 1
- fldl (rFP,rINST,4) # %st0<- vB
- .else
- flds (rFP,rINST,4) # %st0<- vB
- .endif
- ftst
- fnstcw LOCAL0_OFFSET(%ebp) # remember original rounding mode
- movzwl LOCAL0_OFFSET(%ebp),%eax
- movb $0xc,%ah
- movw %ax,LOCAL0_OFFSET+2(%ebp)
- fldcw LOCAL0_OFFSET+2(%ebp) # set "to zero" rounding mode
- FETCH_INST_OPCODE 1 %edx
- andb $0xf,%cl # ecx<- A
- .if 1
- fistpll (rFP,%ecx,4) # convert and store
- .else
- fistpl (rFP,%ecx,4) # convert and store
- .endif
- fldcw LOCAL0_OFFSET(%ebp) # restore previous rounding mode
- jmp .LOP_DOUBLE_TO_LONG_continue
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_DOUBLE_TO_FLOAT: /* 0x8c */
-/* File: x86/OP_DOUBLE_TO_FLOAT.S */
-/* File: x86/fpcvt.S */
- /*
- * Generic 32-bit FP conversion operation.
- */
- /* unop vA, vB */
- movzbl rINSTbl,%ecx # ecx<- A+
- sarl $4,rINST # rINST<- B
- fldl (rFP,rINST,4) # %st0<- vB
- andb $0xf,%cl # ecx<- A
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
-
- fstps (rFP,%ecx,4) # vA<- %st0
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_INT_TO_BYTE: /* 0x8d */
-/* File: x86/OP_INT_TO_BYTE.S */
-/* File: x86/unop.S */
- /*
- * Generic 32-bit unary operation. Provide an "instr" line that
- * specifies an instruction that performs "result = op eax".
- */
- /* unop vA, vB */
- movzbl rINSTbl,%ecx # ecx<- A+
- sarl $4,rINST # rINST<- B
- GET_VREG_R %eax rINST # eax<- vB
- andb $0xf,%cl # ecx<- A
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
-
-
- movsbl %al,%eax
- SET_VREG %eax %ecx
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_INT_TO_CHAR: /* 0x8e */
-/* File: x86/OP_INT_TO_CHAR.S */
-/* File: x86/unop.S */
- /*
- * Generic 32-bit unary operation. Provide an "instr" line that
- * specifies an instruction that performs "result = op eax".
- */
- /* unop vA, vB */
- movzbl rINSTbl,%ecx # ecx<- A+
- sarl $4,rINST # rINST<- B
- GET_VREG_R %eax rINST # eax<- vB
- andb $0xf,%cl # ecx<- A
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
-
-
- movzwl %ax,%eax
- SET_VREG %eax %ecx
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_INT_TO_SHORT: /* 0x8f */
-/* File: x86/OP_INT_TO_SHORT.S */
-/* File: x86/unop.S */
- /*
- * Generic 32-bit unary operation. Provide an "instr" line that
- * specifies an instruction that performs "result = op eax".
- */
- /* unop vA, vB */
- movzbl rINSTbl,%ecx # ecx<- A+
- sarl $4,rINST # rINST<- B
- GET_VREG_R %eax rINST # eax<- vB
- andb $0xf,%cl # ecx<- A
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
-
-
- movswl %ax,%eax
- SET_VREG %eax %ecx
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_ADD_INT: /* 0x90 */
-/* File: x86/OP_ADD_INT.S */
-/* File: x86/binop.S */
- /*
- * Generic 32-bit binary operation. Provide an "instr" line that
- * specifies an instruction that performs "result = eax op (rFP,%ecx,4)".
- * This could be an x86 instruction or a function call. (If the result
- * comes back in a register other than eax, you can override "result".)
- *
- * For: add-int, sub-int, and-int, or-int,
- * xor-int, shl-int, shr-int, ushr-int
- */
- /* binop vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_R %eax %eax # eax<- vBB
- addl (rFP,%ecx,4),%eax # ex: addl (rFP,%ecx,4),%eax
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- SET_VREG %eax rINST
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SUB_INT: /* 0x91 */
-/* File: x86/OP_SUB_INT.S */
-/* File: x86/binop.S */
- /*
- * Generic 32-bit binary operation. Provide an "instr" line that
- * specifies an instruction that performs "result = eax op (rFP,%ecx,4)".
- * This could be an x86 instruction or a function call. (If the result
- * comes back in a register other than eax, you can override "result".)
- *
- * For: add-int, sub-int, and-int, or-int,
- * xor-int, shl-int, shr-int, ushr-int
- */
- /* binop vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_R %eax %eax # eax<- vBB
- subl (rFP,%ecx,4),%eax # ex: addl (rFP,%ecx,4),%eax
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- SET_VREG %eax rINST
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_MUL_INT: /* 0x92 */
-/* File: x86/OP_MUL_INT.S */
- /*
- * 32-bit binary multiplication.
- */
- /* mul vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_R %eax %eax # eax<- vBB
- imull (rFP,%ecx,4),%eax # trashes edx
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- SET_VREG %eax rINST
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_DIV_INT: /* 0x93 */
-/* File: x86/OP_DIV_INT.S */
-/* File: x86/bindiv.S */
-
- /*
- * 32-bit binary div/rem operation. Handles special case of op0=minint and
- * op1=-1.
- */
- /* binop vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_R %eax %eax # eax<- vBB
- GET_VREG_R %ecx %ecx # eax<- vBB
- cmpl $0,%ecx
- je common_errDivideByZero
- cmpl $-1,%ecx
- jne .LOP_DIV_INT_continue_div
- cmpl $0x80000000,%eax
- jne .LOP_DIV_INT_continue_div
- movl $0x80000000,%eax
- jmp .LOP_DIV_INT_finish_div
-
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_REM_INT: /* 0x94 */
-/* File: x86/OP_REM_INT.S */
-/* File: x86/bindiv.S */
-
- /*
- * 32-bit binary div/rem operation. Handles special case of op0=minint and
- * op1=-1.
- */
- /* binop vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_R %eax %eax # eax<- vBB
- GET_VREG_R %ecx %ecx # eax<- vBB
- cmpl $0,%ecx
- je common_errDivideByZero
- cmpl $-1,%ecx
- jne .LOP_REM_INT_continue_div
- cmpl $0x80000000,%eax
- jne .LOP_REM_INT_continue_div
- movl $0,%edx
- jmp .LOP_REM_INT_finish_div
-
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_AND_INT: /* 0x95 */
-/* File: x86/OP_AND_INT.S */
-/* File: x86/binop.S */
- /*
- * Generic 32-bit binary operation. Provide an "instr" line that
- * specifies an instruction that performs "result = eax op (rFP,%ecx,4)".
- * This could be an x86 instruction or a function call. (If the result
- * comes back in a register other than eax, you can override "result".)
- *
- * For: add-int, sub-int, and-int, or-int,
- * xor-int, shl-int, shr-int, ushr-int
- */
- /* binop vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_R %eax %eax # eax<- vBB
- andl (rFP,%ecx,4),%eax # ex: addl (rFP,%ecx,4),%eax
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- SET_VREG %eax rINST
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_OR_INT: /* 0x96 */
-/* File: x86/OP_OR_INT.S */
-/* File: x86/binop.S */
- /*
- * Generic 32-bit binary operation. Provide an "instr" line that
- * specifies an instruction that performs "result = eax op (rFP,%ecx,4)".
- * This could be an x86 instruction or a function call. (If the result
- * comes back in a register other than eax, you can override "result".)
- *
- * For: add-int, sub-int, and-int, or-int,
- * xor-int, shl-int, shr-int, ushr-int
- */
- /* binop vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_R %eax %eax # eax<- vBB
- orl (rFP,%ecx,4),%eax # ex: addl (rFP,%ecx,4),%eax
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- SET_VREG %eax rINST
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_XOR_INT: /* 0x97 */
-/* File: x86/OP_XOR_INT.S */
-/* File: x86/binop.S */
- /*
- * Generic 32-bit binary operation. Provide an "instr" line that
- * specifies an instruction that performs "result = eax op (rFP,%ecx,4)".
- * This could be an x86 instruction or a function call. (If the result
- * comes back in a register other than eax, you can override "result".)
- *
- * For: add-int, sub-int, and-int, or-int,
- * xor-int, shl-int, shr-int, ushr-int
- */
- /* binop vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_R %eax %eax # eax<- vBB
- xorl (rFP,%ecx,4),%eax # ex: addl (rFP,%ecx,4),%eax
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- SET_VREG %eax rINST
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SHL_INT: /* 0x98 */
-/* File: x86/OP_SHL_INT.S */
-/* File: x86/binop1.S */
- /*
- * Generic 32-bit binary operation in which both operands loaded to
- * registers (op0 in eax, op1 in ecx).
- */
- /* binop vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_R %eax %eax # eax<- vBB
- GET_VREG_R %ecx %ecx # eax<- vBB
- sall %cl,%eax # ex: addl %ecx,%eax
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- SET_VREG %eax rINST
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SHR_INT: /* 0x99 */
-/* File: x86/OP_SHR_INT.S */
-/* File: x86/binop1.S */
- /*
- * Generic 32-bit binary operation in which both operands loaded to
- * registers (op0 in eax, op1 in ecx).
- */
- /* binop vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_R %eax %eax # eax<- vBB
- GET_VREG_R %ecx %ecx # eax<- vBB
- sarl %cl,%eax # ex: addl %ecx,%eax
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- SET_VREG %eax rINST
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_USHR_INT: /* 0x9a */
-/* File: x86/OP_USHR_INT.S */
-/* File: x86/binop1.S */
- /*
- * Generic 32-bit binary operation in which both operands loaded to
- * registers (op0 in eax, op1 in ecx).
- */
- /* binop vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_R %eax %eax # eax<- vBB
- GET_VREG_R %ecx %ecx # eax<- vBB
- shrl %cl,%eax # ex: addl %ecx,%eax
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- SET_VREG %eax rINST
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_ADD_LONG: /* 0x9b */
-/* File: x86/OP_ADD_LONG.S */
-/* File: x86/binopWide.S */
- /*
- * Generic 64-bit binary operation.
- */
- /* binop vAA, vBB, vCC */
-
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_WORD %edx %eax 0 # edx<- v[BB+0]
- GET_VREG_WORD %eax %eax 1 # eax<- v[BB+1]
- addl (rFP,%ecx,4),%edx # ex: addl (rFP,%ecx,4),%edx
- adcl 4(rFP,%ecx,4),%eax # ex: adcl 4(rFP,%ecx,4),%eax
- SET_VREG_WORD %edx rINST 0 # v[AA+0] <- edx
- FETCH_INST_OPCODE 2 %edx
- SET_VREG_WORD %eax rINST 1 # v[AA+1] <- eax
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SUB_LONG: /* 0x9c */
-/* File: x86/OP_SUB_LONG.S */
-/* File: x86/binopWide.S */
- /*
- * Generic 64-bit binary operation.
- */
- /* binop vAA, vBB, vCC */
-
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_WORD %edx %eax 0 # edx<- v[BB+0]
- GET_VREG_WORD %eax %eax 1 # eax<- v[BB+1]
- subl (rFP,%ecx,4),%edx # ex: addl (rFP,%ecx,4),%edx
- sbbl 4(rFP,%ecx,4),%eax # ex: adcl 4(rFP,%ecx,4),%eax
- SET_VREG_WORD %edx rINST 0 # v[AA+0] <- edx
- FETCH_INST_OPCODE 2 %edx
- SET_VREG_WORD %eax rINST 1 # v[AA+1] <- eax
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_MUL_LONG: /* 0x9d */
-/* File: x86/OP_MUL_LONG.S */
- /*
- * Signed 64-bit integer multiply.
- *
- * We could definately use more free registers for
- * this code. We spill rINSTw (ebx),
- * giving us eax, ebc, ecx and edx as computational
- * temps. On top of that, we'll spill edi (rFP)
- * for use as the vB pointer and esi (rPC) for use
- * as the vC pointer. Yuck.
- */
- /* mul-long vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- B
- movzbl 3(rPC),%ecx # ecx<- C
- SPILL_TMP2(%esi) # save Dalvik PC
- SPILL(rFP)
- SPILL(rINST)
- leal (rFP,%eax,4),%esi # esi<- &v[B]
- leal (rFP,%ecx,4),rFP # rFP<- &v[C]
- movl 4(%esi),%ecx # ecx<- Bmsw
- imull (rFP),%ecx # ecx<- (Bmsw*Clsw)
- movl 4(rFP),%eax # eax<- Cmsw
- imull (%esi),%eax # eax<- (Cmsw*Blsw)
- addl %eax,%ecx # ecx<- (Bmsw*Clsw)+(Cmsw*Blsw)
- movl (rFP),%eax # eax<- Clsw
- mull (%esi) # eax<- (Clsw*Alsw)
- UNSPILL(rINST)
- UNSPILL(rFP)
- jmp .LOP_MUL_LONG_continue
-
-/* ------------------------------ */
- .balign 64
-.L_OP_DIV_LONG: /* 0x9e */
-/* File: x86/OP_DIV_LONG.S */
- /* div vAA, vBB, vCC */
- movzbl 3(rPC),%eax # eax<- CC
- movzbl 2(rPC),%ecx # ecx<- BB
- GET_VREG_WORD %edx %eax 0
- GET_VREG_WORD %eax %eax 1
- movl %edx,OUT_ARG2(%esp)
- testl %eax,%eax
- je .LOP_DIV_LONG_check_zero
- cmpl $-1,%eax
- je .LOP_DIV_LONG_check_neg1
-.LOP_DIV_LONG_notSpecial:
- GET_VREG_WORD %edx %ecx 0
- GET_VREG_WORD %ecx %ecx 1
-.LOP_DIV_LONG_notSpecial1:
- movl %eax,OUT_ARG3(%esp)
- movl %edx,OUT_ARG0(%esp)
- movl %ecx,OUT_ARG1(%esp)
- jmp .LOP_DIV_LONG_continue
-
-/* ------------------------------ */
- .balign 64
-.L_OP_REM_LONG: /* 0x9f */
-/* File: x86/OP_REM_LONG.S */
-/* File: x86/OP_DIV_LONG.S */
- /* div vAA, vBB, vCC */
- movzbl 3(rPC),%eax # eax<- CC
- movzbl 2(rPC),%ecx # ecx<- BB
- GET_VREG_WORD %edx %eax 0
- GET_VREG_WORD %eax %eax 1
- movl %edx,OUT_ARG2(%esp)
- testl %eax,%eax
- je .LOP_REM_LONG_check_zero
- cmpl $-1,%eax
- je .LOP_REM_LONG_check_neg1
-.LOP_REM_LONG_notSpecial:
- GET_VREG_WORD %edx %ecx 0
- GET_VREG_WORD %ecx %ecx 1
-.LOP_REM_LONG_notSpecial1:
- movl %eax,OUT_ARG3(%esp)
- movl %edx,OUT_ARG0(%esp)
- movl %ecx,OUT_ARG1(%esp)
- jmp .LOP_REM_LONG_continue
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_AND_LONG: /* 0xa0 */
-/* File: x86/OP_AND_LONG.S */
-/* File: x86/binopWide.S */
- /*
- * Generic 64-bit binary operation.
- */
- /* binop vAA, vBB, vCC */
-
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_WORD %edx %eax 0 # edx<- v[BB+0]
- GET_VREG_WORD %eax %eax 1 # eax<- v[BB+1]
- andl (rFP,%ecx,4),%edx # ex: addl (rFP,%ecx,4),%edx
- andl 4(rFP,%ecx,4),%eax # ex: adcl 4(rFP,%ecx,4),%eax
- SET_VREG_WORD %edx rINST 0 # v[AA+0] <- edx
- FETCH_INST_OPCODE 2 %edx
- SET_VREG_WORD %eax rINST 1 # v[AA+1] <- eax
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_OR_LONG: /* 0xa1 */
-/* File: x86/OP_OR_LONG.S */
-/* File: x86/binopWide.S */
- /*
- * Generic 64-bit binary operation.
- */
- /* binop vAA, vBB, vCC */
-
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_WORD %edx %eax 0 # edx<- v[BB+0]
- GET_VREG_WORD %eax %eax 1 # eax<- v[BB+1]
- orl (rFP,%ecx,4),%edx # ex: addl (rFP,%ecx,4),%edx
- orl 4(rFP,%ecx,4),%eax # ex: adcl 4(rFP,%ecx,4),%eax
- SET_VREG_WORD %edx rINST 0 # v[AA+0] <- edx
- FETCH_INST_OPCODE 2 %edx
- SET_VREG_WORD %eax rINST 1 # v[AA+1] <- eax
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_XOR_LONG: /* 0xa2 */
-/* File: x86/OP_XOR_LONG.S */
-/* File: x86/binopWide.S */
- /*
- * Generic 64-bit binary operation.
- */
- /* binop vAA, vBB, vCC */
-
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_WORD %edx %eax 0 # edx<- v[BB+0]
- GET_VREG_WORD %eax %eax 1 # eax<- v[BB+1]
- xorl (rFP,%ecx,4),%edx # ex: addl (rFP,%ecx,4),%edx
- xorl 4(rFP,%ecx,4),%eax # ex: adcl 4(rFP,%ecx,4),%eax
- SET_VREG_WORD %edx rINST 0 # v[AA+0] <- edx
- FETCH_INST_OPCODE 2 %edx
- SET_VREG_WORD %eax rINST 1 # v[AA+1] <- eax
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SHL_LONG: /* 0xa3 */
-/* File: x86/OP_SHL_LONG.S */
- /*
- * Long integer shift. This is different from the generic 32/64-bit
- * binary operations because vAA/vBB are 64-bit but vCC (the shift
- * distance) is 32-bit. Also, Dalvik requires us to mask off the low
- * 6 bits of the shift distance. x86 shifts automatically mask off
- * the low 5 bits of %cl, so have to handle the 64 > shiftcount > 31
- * case specially.
- */
- /* shl-long vAA, vBB, vCC */
- /* ecx gets shift count */
- /* Need to spill edx */
- /* rINSTw gets AA */
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_WORD %edx %eax 1 # ecx<- v[BB+1]
- GET_VREG_R %ecx %ecx # ecx<- vCC
- GET_VREG_WORD %eax %eax 0 # eax<- v[BB+0]
- shldl %eax,%edx
- sall %cl,%eax
- testb $32,%cl
- je 2f
- movl %eax,%edx
- xorl %eax,%eax
-2:
- SET_VREG_WORD %edx rINST 1 # v[AA+1]<- %edx
- FETCH_INST_OPCODE 2 %edx
- jmp .LOP_SHL_LONG_finish
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SHR_LONG: /* 0xa4 */
-/* File: x86/OP_SHR_LONG.S */
- /*
- * Long integer shift. This is different from the generic 32/64-bit
- * binary operations because vAA/vBB are 64-bit but vCC (the shift
- * distance) is 32-bit. Also, Dalvik requires us to mask off the low
- * 6 bits of the shift distance. x86 shifts automatically mask off
- * the low 5 bits of %cl, so have to handle the 64 > shiftcount > 31
- * case specially.
- */
- /* shr-long vAA, vBB, vCC */
- /* ecx gets shift count */
- /* Need to spill edx */
- /* rINSTw gets AA */
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_WORD %edx %eax 1 # edx<- v[BB+1]
- GET_VREG_R %ecx %ecx # ecx<- vCC
- GET_VREG_WORD %eax %eax 0 # eax<- v[BB+0]
- shrdl %edx,%eax
- sarl %cl,%edx
- testb $32,%cl
- je 2f
- movl %edx,%eax
- sarl $31,%edx
-2:
- SET_VREG_WORD %edx rINST 1 # v[AA+1]<- edx
- FETCH_INST_OPCODE 2 %edx
- jmp .LOP_SHR_LONG_finish
-
-/* ------------------------------ */
- .balign 64
-.L_OP_USHR_LONG: /* 0xa5 */
-/* File: x86/OP_USHR_LONG.S */
- /*
- * Long integer shift. This is different from the generic 32/64-bit
- * binary operations because vAA/vBB are 64-bit but vCC (the shift
- * distance) is 32-bit. Also, Dalvik requires us to mask off the low
- * 6 bits of the shift distance. x86 shifts automatically mask off
- * the low 5 bits of %cl, so have to handle the 64 > shiftcount > 31
- * case specially.
- */
- /* shr-long vAA, vBB, vCC */
- /* ecx gets shift count */
- /* Need to spill edx */
- /* rINSTw gets AA */
- movzbl 2(rPC),%eax # eax<- BB
- movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_WORD %edx %eax 1 # edx<- v[BB+1]
- GET_VREG_R %ecx %ecx # ecx<- vCC
- GET_VREG_WORD %eax %eax 0 # eax<- v[BB+0]
- shrdl %edx,%eax
- shrl %cl,%edx
- testb $32,%cl
- je 2f
- movl %edx,%eax
- xorl %edx,%edx
-2:
- SET_VREG_WORD %edx rINST 1 # v[AA+1]<- edx
- FETCH_INST_OPCODE 2 %edx
- jmp .LOP_USHR_LONG_finish
-
-/* ------------------------------ */
- .balign 64
-.L_OP_ADD_FLOAT: /* 0xa6 */
-/* File: x86/OP_ADD_FLOAT.S */
-/* File: x86/binflop.S */
- /*
- * Generic 32-bit binary float operation.
- *
- * For: add-fp, sub-fp, mul-fp, div-fp
- */
- /* binop vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- CC
- movzbl 3(rPC),%ecx # ecx<- BB
- flds (rFP,%eax,4) # vCC to fp stack
- fadds (rFP,%ecx,4) # ex: faddp
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- fstps (rFP,rINST,4) # %st to vAA
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SUB_FLOAT: /* 0xa7 */
-/* File: x86/OP_SUB_FLOAT.S */
-/* File: x86/binflop.S */
- /*
- * Generic 32-bit binary float operation.
- *
- * For: add-fp, sub-fp, mul-fp, div-fp
- */
- /* binop vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- CC
- movzbl 3(rPC),%ecx # ecx<- BB
- flds (rFP,%eax,4) # vCC to fp stack
- fsubs (rFP,%ecx,4) # ex: faddp
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- fstps (rFP,rINST,4) # %st to vAA
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_MUL_FLOAT: /* 0xa8 */
-/* File: x86/OP_MUL_FLOAT.S */
-/* File: x86/binflop.S */
- /*
- * Generic 32-bit binary float operation.
- *
- * For: add-fp, sub-fp, mul-fp, div-fp
- */
- /* binop vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- CC
- movzbl 3(rPC),%ecx # ecx<- BB
- flds (rFP,%eax,4) # vCC to fp stack
- fmuls (rFP,%ecx,4) # ex: faddp
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- fstps (rFP,rINST,4) # %st to vAA
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_DIV_FLOAT: /* 0xa9 */
-/* File: x86/OP_DIV_FLOAT.S */
-/* File: x86/binflop.S */
- /*
- * Generic 32-bit binary float operation.
- *
- * For: add-fp, sub-fp, mul-fp, div-fp
- */
- /* binop vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- CC
- movzbl 3(rPC),%ecx # ecx<- BB
- flds (rFP,%eax,4) # vCC to fp stack
- fdivs (rFP,%ecx,4) # ex: faddp
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- fstps (rFP,rINST,4) # %st to vAA
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_REM_FLOAT: /* 0xaa */
-/* File: x86/OP_REM_FLOAT.S */
- /* rem_float vAA, vBB, vCC */
- movzbl 3(rPC),%ecx # ecx<- BB
- movzbl 2(rPC),%eax # eax<- CC
- flds (rFP,%ecx,4) # vCC to fp stack
- flds (rFP,%eax,4) # vCC to fp stack
- movzbl rINSTbl,%ecx # ecx<- AA
- FETCH_INST_OPCODE 2 %edx
-1:
- fprem
- fstsw %ax
- sahf
- jp 1b
- fstp %st(1)
- ADVANCE_PC 2
- fstps (rFP,%ecx,4) # %st to vAA
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_ADD_DOUBLE: /* 0xab */
-/* File: x86/OP_ADD_DOUBLE.S */
-/* File: x86/binflop.S */
- /*
- * Generic 32-bit binary float operation.
- *
- * For: add-fp, sub-fp, mul-fp, div-fp
- */
- /* binop vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- CC
- movzbl 3(rPC),%ecx # ecx<- BB
- fldl (rFP,%eax,4) # vCC to fp stack
- faddl (rFP,%ecx,4) # ex: faddp
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- fstpl (rFP,rINST,4) # %st to vAA
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SUB_DOUBLE: /* 0xac */
-/* File: x86/OP_SUB_DOUBLE.S */
-/* File: x86/binflop.S */
- /*
- * Generic 32-bit binary float operation.
- *
- * For: add-fp, sub-fp, mul-fp, div-fp
- */
- /* binop vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- CC
- movzbl 3(rPC),%ecx # ecx<- BB
- fldl (rFP,%eax,4) # vCC to fp stack
- fsubl (rFP,%ecx,4) # ex: faddp
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- fstpl (rFP,rINST,4) # %st to vAA
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_MUL_DOUBLE: /* 0xad */
-/* File: x86/OP_MUL_DOUBLE.S */
-/* File: x86/binflop.S */
- /*
- * Generic 32-bit binary float operation.
- *
- * For: add-fp, sub-fp, mul-fp, div-fp
- */
- /* binop vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- CC
- movzbl 3(rPC),%ecx # ecx<- BB
- fldl (rFP,%eax,4) # vCC to fp stack
- fmull (rFP,%ecx,4) # ex: faddp
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- fstpl (rFP,rINST,4) # %st to vAA
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_DIV_DOUBLE: /* 0xae */
-/* File: x86/OP_DIV_DOUBLE.S */
-/* File: x86/binflop.S */
- /*
- * Generic 32-bit binary float operation.
- *
- * For: add-fp, sub-fp, mul-fp, div-fp
- */
- /* binop vAA, vBB, vCC */
- movzbl 2(rPC),%eax # eax<- CC
- movzbl 3(rPC),%ecx # ecx<- BB
- fldl (rFP,%eax,4) # vCC to fp stack
- fdivl (rFP,%ecx,4) # ex: faddp
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- fstpl (rFP,rINST,4) # %st to vAA
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_REM_DOUBLE: /* 0xaf */
-/* File: x86/OP_REM_DOUBLE.S */
- /* rem_float vAA, vBB, vCC */
- movzbl 3(rPC),%ecx # ecx<- BB
- movzbl 2(rPC),%eax # eax<- CC
- fldl (rFP,%ecx,4) # vCC to fp stack
- fldl (rFP,%eax,4) # vCC to fp stack
- movzbl rINSTbl,%ecx # ecx<- AA
- FETCH_INST_OPCODE 2 %edx
-1:
- fprem
- fstsw %ax
- sahf
- jp 1b
- fstp %st(1)
- ADVANCE_PC 2
- fstpl (rFP,%ecx,4) # %st to vAA
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_ADD_INT_2ADDR: /* 0xb0 */
-/* File: x86/OP_ADD_INT_2ADDR.S */
-/* File: x86/binop2addr.S */
- /*
- * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
- * that specifies an instruction that performs "result = r0 op r1".
- * This could be an ARM instruction or a function call. (If the result
- * comes back in a register other than r0, you can override "result".)
- *
- * If "chkzero" is set to 1, we perform a divide-by-zero check on
- * vCC (r1). Useful for integer division and modulus.
- *
- * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
- * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
- * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
- * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
- */
- /* binop/2addr vA, vB */
- movzx rINSTbl,%ecx # ecx<- A+
- sarl $4,rINST # rINST<- B
- GET_VREG_R %eax rINST # eax<- vB
- FETCH_INST_OPCODE 1 %edx
- andb $0xf,%cl # ecx<- A
- addl %eax,(rFP,%ecx,4) # for ex: addl %eax,(rFP,%ecx,4)
- ADVANCE_PC 1
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SUB_INT_2ADDR: /* 0xb1 */
-/* File: x86/OP_SUB_INT_2ADDR.S */
-/* File: x86/binop2addr.S */
- /*
- * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
- * that specifies an instruction that performs "result = r0 op r1".
- * This could be an ARM instruction or a function call. (If the result
- * comes back in a register other than r0, you can override "result".)
- *
- * If "chkzero" is set to 1, we perform a divide-by-zero check on
- * vCC (r1). Useful for integer division and modulus.
- *
- * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
- * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
- * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
- * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
- */
- /* binop/2addr vA, vB */
- movzx rINSTbl,%ecx # ecx<- A+
- sarl $4,rINST # rINST<- B
- GET_VREG_R %eax rINST # eax<- vB
- FETCH_INST_OPCODE 1 %edx
- andb $0xf,%cl # ecx<- A
- subl %eax,(rFP,%ecx,4) # for ex: addl %eax,(rFP,%ecx,4)
- ADVANCE_PC 1
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_MUL_INT_2ADDR: /* 0xb2 */
-/* File: x86/OP_MUL_INT_2ADDR.S */
- /* mul vA, vB */
- movzx rINSTbl,%ecx # ecx<- A+
- sarl $4,rINST # rINST<- B
- GET_VREG_R %eax rINST # eax<- vB
- andb $0xf,%cl # ecx<- A
- imull (rFP,%ecx,4),%eax
- FETCH_INST_OPCODE 1 %edx
- SET_VREG %eax %ecx
- ADVANCE_PC 1
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_DIV_INT_2ADDR: /* 0xb3 */
-/* File: x86/OP_DIV_INT_2ADDR.S */
-/* File: x86/bindiv2addr.S */
- /*
- * 32-bit binary div/rem operation. Handles special case of op0=minint and
- * op1=-1.
- */
- /* div/rem/2addr vA, vB */
- movzx rINSTbl,%ecx # eax<- BA
- sarl $4,%ecx # ecx<- B
- GET_VREG_R %ecx %ecx # eax<- vBB
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_R %eax rINST # eax<- vBB
- cmpl $0,%ecx
- je common_errDivideByZero
- cmpl $-1,%ecx
- jne .LOP_DIV_INT_2ADDR_continue_div2addr
- cmpl $0x80000000,%eax
- jne .LOP_DIV_INT_2ADDR_continue_div2addr
- movl $0x80000000,%eax
- jmp .LOP_DIV_INT_2ADDR_finish_div2addr
-
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_REM_INT_2ADDR: /* 0xb4 */
-/* File: x86/OP_REM_INT_2ADDR.S */
-/* File: x86/bindiv2addr.S */
- /*
- * 32-bit binary div/rem operation. Handles special case of op0=minint and
- * op1=-1.
- */
- /* div/rem/2addr vA, vB */
- movzx rINSTbl,%ecx # eax<- BA
- sarl $4,%ecx # ecx<- B
- GET_VREG_R %ecx %ecx # eax<- vBB
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_R %eax rINST # eax<- vBB
- cmpl $0,%ecx
- je common_errDivideByZero
- cmpl $-1,%ecx
- jne .LOP_REM_INT_2ADDR_continue_div2addr
- cmpl $0x80000000,%eax
- jne .LOP_REM_INT_2ADDR_continue_div2addr
- movl $0,%edx
- jmp .LOP_REM_INT_2ADDR_finish_div2addr
-
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_AND_INT_2ADDR: /* 0xb5 */
-/* File: x86/OP_AND_INT_2ADDR.S */
-/* File: x86/binop2addr.S */
- /*
- * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
- * that specifies an instruction that performs "result = r0 op r1".
- * This could be an ARM instruction or a function call. (If the result
- * comes back in a register other than r0, you can override "result".)
- *
- * If "chkzero" is set to 1, we perform a divide-by-zero check on
- * vCC (r1). Useful for integer division and modulus.
- *
- * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
- * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
- * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
- * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
- */
- /* binop/2addr vA, vB */
- movzx rINSTbl,%ecx # ecx<- A+
- sarl $4,rINST # rINST<- B
- GET_VREG_R %eax rINST # eax<- vB
- FETCH_INST_OPCODE 1 %edx
- andb $0xf,%cl # ecx<- A
- andl %eax,(rFP,%ecx,4) # for ex: addl %eax,(rFP,%ecx,4)
- ADVANCE_PC 1
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_OR_INT_2ADDR: /* 0xb6 */
-/* File: x86/OP_OR_INT_2ADDR.S */
-/* File: x86/binop2addr.S */
- /*
- * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
- * that specifies an instruction that performs "result = r0 op r1".
- * This could be an ARM instruction or a function call. (If the result
- * comes back in a register other than r0, you can override "result".)
- *
- * If "chkzero" is set to 1, we perform a divide-by-zero check on
- * vCC (r1). Useful for integer division and modulus.
- *
- * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
- * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
- * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
- * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
- */
- /* binop/2addr vA, vB */
- movzx rINSTbl,%ecx # ecx<- A+
- sarl $4,rINST # rINST<- B
- GET_VREG_R %eax rINST # eax<- vB
- FETCH_INST_OPCODE 1 %edx
- andb $0xf,%cl # ecx<- A
- orl %eax,(rFP,%ecx,4) # for ex: addl %eax,(rFP,%ecx,4)
- ADVANCE_PC 1
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_XOR_INT_2ADDR: /* 0xb7 */
-/* File: x86/OP_XOR_INT_2ADDR.S */
-/* File: x86/binop2addr.S */
- /*
- * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
- * that specifies an instruction that performs "result = r0 op r1".
- * This could be an ARM instruction or a function call. (If the result
- * comes back in a register other than r0, you can override "result".)
- *
- * If "chkzero" is set to 1, we perform a divide-by-zero check on
- * vCC (r1). Useful for integer division and modulus.
- *
- * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
- * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
- * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
- * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
- */
- /* binop/2addr vA, vB */
- movzx rINSTbl,%ecx # ecx<- A+
- sarl $4,rINST # rINST<- B
- GET_VREG_R %eax rINST # eax<- vB
- FETCH_INST_OPCODE 1 %edx
- andb $0xf,%cl # ecx<- A
- xorl %eax,(rFP,%ecx,4) # for ex: addl %eax,(rFP,%ecx,4)
- ADVANCE_PC 1
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SHL_INT_2ADDR: /* 0xb8 */
-/* File: x86/OP_SHL_INT_2ADDR.S */
-/* File: x86/shop2addr.S */
- /*
- * Generic 32-bit "shift/2addr" operation.
- */
- /* shift/2addr vA, vB */
- movzx rINSTbl,%ecx # eax<- BA
- sarl $4,%ecx # ecx<- B
- GET_VREG_R %ecx %ecx # eax<- vBB
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_R %eax rINST # eax<- vAA
- sall %cl,%eax # ex: sarl %cl,%eax
- FETCH_INST_OPCODE 1 %edx
- SET_VREG %eax rINST
- ADVANCE_PC 1
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SHR_INT_2ADDR: /* 0xb9 */
-/* File: x86/OP_SHR_INT_2ADDR.S */
-/* File: x86/shop2addr.S */
- /*
- * Generic 32-bit "shift/2addr" operation.
- */
- /* shift/2addr vA, vB */
- movzx rINSTbl,%ecx # eax<- BA
- sarl $4,%ecx # ecx<- B
- GET_VREG_R %ecx %ecx # eax<- vBB
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_R %eax rINST # eax<- vAA
- sarl %cl,%eax # ex: sarl %cl,%eax
- FETCH_INST_OPCODE 1 %edx
- SET_VREG %eax rINST
- ADVANCE_PC 1
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_USHR_INT_2ADDR: /* 0xba */
-/* File: x86/OP_USHR_INT_2ADDR.S */
-/* File: x86/shop2addr.S */
- /*
- * Generic 32-bit "shift/2addr" operation.
- */
- /* shift/2addr vA, vB */
- movzx rINSTbl,%ecx # eax<- BA
- sarl $4,%ecx # ecx<- B
- GET_VREG_R %ecx %ecx # eax<- vBB
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_R %eax rINST # eax<- vAA
- shrl %cl,%eax # ex: sarl %cl,%eax
- FETCH_INST_OPCODE 1 %edx
- SET_VREG %eax rINST
- ADVANCE_PC 1
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_ADD_LONG_2ADDR: /* 0xbb */
-/* File: x86/OP_ADD_LONG_2ADDR.S */
-/* File: x86/binopWide2addr.S */
- /*
- * Generic 64-bit binary operation.
- */
- /* binop/2addr vA, vB */
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- GET_VREG_WORD %eax %ecx 0 # eax<- v[B+0]
- GET_VREG_WORD %ecx %ecx 1 # eax<- v[B+1]
- andb $0xF,rINSTbl # rINST<- A
- addl %eax,(rFP,rINST,4) # example: addl %eax,(rFP,rINST,4)
- adcl %ecx,4(rFP,rINST,4) # example: adcl %ecx,4(rFP,rINST,4)
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SUB_LONG_2ADDR: /* 0xbc */
-/* File: x86/OP_SUB_LONG_2ADDR.S */
-/* File: x86/binopWide2addr.S */
- /*
- * Generic 64-bit binary operation.
- */
- /* binop/2addr vA, vB */
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- GET_VREG_WORD %eax %ecx 0 # eax<- v[B+0]
- GET_VREG_WORD %ecx %ecx 1 # eax<- v[B+1]
- andb $0xF,rINSTbl # rINST<- A
- subl %eax,(rFP,rINST,4) # example: addl %eax,(rFP,rINST,4)
- sbbl %ecx,4(rFP,rINST,4) # example: adcl %ecx,4(rFP,rINST,4)
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_MUL_LONG_2ADDR: /* 0xbd */
-/* File: x86/OP_MUL_LONG_2ADDR.S */
- /*
- * Signed 64-bit integer multiply, 2-addr version
- *
- * We could definately use more free registers for
- * this code. We must spill %edx (edx) because it
- * is used by imul. We'll also spill rINST (ebx),
- * giving us eax, ebc, ecx and edx as computational
- * temps. On top of that, we'll spill %esi (edi)
- * for use as the vA pointer and rFP (esi) for use
- * as the vB pointer. Yuck.
- */
- /* mul-long/2addr vA, vB */
- movzbl rINSTbl,%eax # eax<- BA
- andb $0xf,%al # eax<- A
- sarl $4,rINST # rINST<- B
- SPILL_TMP2(%esi)
- SPILL(rFP)
- leal (rFP,%eax,4),%esi # %esi<- &v[A]
- leal (rFP,rINST,4),rFP # rFP<- &v[B]
- movl 4(%esi),%ecx # ecx<- Amsw
- imull (rFP),%ecx # ecx<- (Amsw*Blsw)
- movl 4(rFP),%eax # eax<- Bmsw
- imull (%esi),%eax # eax<- (Bmsw*Alsw)
- addl %eax,%ecx # ecx<- (Amsw*Blsw)+(Bmsw*Alsw)
- movl (rFP),%eax # eax<- Blsw
- mull (%esi) # eax<- (Blsw*Alsw)
- jmp .LOP_MUL_LONG_2ADDR_continue
-
-/* ------------------------------ */
- .balign 64
-.L_OP_DIV_LONG_2ADDR: /* 0xbe */
-/* File: x86/OP_DIV_LONG_2ADDR.S */
- /* div/2addr vA, vB */
- movzbl rINSTbl,%eax
- shrl $4,%eax # eax<- B
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_WORD %edx %eax 0
- GET_VREG_WORD %eax %eax 1
- movl %edx,OUT_ARG2(%esp)
- testl %eax,%eax
- je .LOP_DIV_LONG_2ADDR_check_zero
- cmpl $-1,%eax
- je .LOP_DIV_LONG_2ADDR_check_neg1
-.LOP_DIV_LONG_2ADDR_notSpecial:
- GET_VREG_WORD %edx rINST 0
- GET_VREG_WORD %ecx rINST 1
-.LOP_DIV_LONG_2ADDR_notSpecial1:
- jmp .LOP_DIV_LONG_2ADDR_continue
-
-/* ------------------------------ */
- .balign 64
-.L_OP_REM_LONG_2ADDR: /* 0xbf */
-/* File: x86/OP_REM_LONG_2ADDR.S */
-/* File: x86/OP_DIV_LONG_2ADDR.S */
- /* div/2addr vA, vB */
- movzbl rINSTbl,%eax
- shrl $4,%eax # eax<- B
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_WORD %edx %eax 0
- GET_VREG_WORD %eax %eax 1
- movl %edx,OUT_ARG2(%esp)
- testl %eax,%eax
- je .LOP_REM_LONG_2ADDR_check_zero
- cmpl $-1,%eax
- je .LOP_REM_LONG_2ADDR_check_neg1
-.LOP_REM_LONG_2ADDR_notSpecial:
- GET_VREG_WORD %edx rINST 0
- GET_VREG_WORD %ecx rINST 1
-.LOP_REM_LONG_2ADDR_notSpecial1:
- jmp .LOP_REM_LONG_2ADDR_continue
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_AND_LONG_2ADDR: /* 0xc0 */
-/* File: x86/OP_AND_LONG_2ADDR.S */
-/* File: x86/binopWide2addr.S */
- /*
- * Generic 64-bit binary operation.
- */
- /* binop/2addr vA, vB */
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- GET_VREG_WORD %eax %ecx 0 # eax<- v[B+0]
- GET_VREG_WORD %ecx %ecx 1 # eax<- v[B+1]
- andb $0xF,rINSTbl # rINST<- A
- andl %eax,(rFP,rINST,4) # example: addl %eax,(rFP,rINST,4)
- andl %ecx,4(rFP,rINST,4) # example: adcl %ecx,4(rFP,rINST,4)
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_OR_LONG_2ADDR: /* 0xc1 */
-/* File: x86/OP_OR_LONG_2ADDR.S */
-/* File: x86/binopWide2addr.S */
- /*
- * Generic 64-bit binary operation.
- */
- /* binop/2addr vA, vB */
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- GET_VREG_WORD %eax %ecx 0 # eax<- v[B+0]
- GET_VREG_WORD %ecx %ecx 1 # eax<- v[B+1]
- andb $0xF,rINSTbl # rINST<- A
- orl %eax,(rFP,rINST,4) # example: addl %eax,(rFP,rINST,4)
- orl %ecx,4(rFP,rINST,4) # example: adcl %ecx,4(rFP,rINST,4)
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_XOR_LONG_2ADDR: /* 0xc2 */
-/* File: x86/OP_XOR_LONG_2ADDR.S */
-/* File: x86/binopWide2addr.S */
- /*
- * Generic 64-bit binary operation.
- */
- /* binop/2addr vA, vB */
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- GET_VREG_WORD %eax %ecx 0 # eax<- v[B+0]
- GET_VREG_WORD %ecx %ecx 1 # eax<- v[B+1]
- andb $0xF,rINSTbl # rINST<- A
- xorl %eax,(rFP,rINST,4) # example: addl %eax,(rFP,rINST,4)
- xorl %ecx,4(rFP,rINST,4) # example: adcl %ecx,4(rFP,rINST,4)
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SHL_LONG_2ADDR: /* 0xc3 */
-/* File: x86/OP_SHL_LONG_2ADDR.S */
- /*
- * Long integer shift, 2addr version. vA is 64-bit value/result, vB is
- * 32-bit shift distance.
- */
- /* shl-long/2addr vA, vB */
- /* ecx gets shift count */
- /* Need to spill edx */
- /* rINSTw gets AA */
- movzbl rINSTbl,%ecx # ecx<- BA
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_WORD %eax rINST 0 # eax<- v[AA+0]
- sarl $4,%ecx # ecx<- B
- GET_VREG_WORD %edx rINST 1 # edx<- v[AA+1]
- GET_VREG_R %ecx %ecx # ecx<- vBB
- shldl %eax,%edx
- sall %cl,%eax
- testb $32,%cl
- je 2f
- movl %eax,%edx
- xorl %eax,%eax
-2:
- SET_VREG_WORD %edx rINST 1 # v[AA+1]<- edx
- jmp .LOP_SHL_LONG_2ADDR_finish
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SHR_LONG_2ADDR: /* 0xc4 */
-/* File: x86/OP_SHR_LONG_2ADDR.S */
- /*
- * Long integer shift, 2addr version. vA is 64-bit value/result, vB is
- * 32-bit shift distance.
- */
- /* shl-long/2addr vA, vB */
- /* ecx gets shift count */
- /* Need to spill edx */
- /* rINSTw gets AA */
- movzbl rINSTbl,%ecx # ecx<- BA
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_WORD %eax rINST 0 # eax<- v[AA+0]
- sarl $4,%ecx # ecx<- B
- GET_VREG_WORD %edx rINST 1 # edx<- v[AA+1]
- GET_VREG_R %ecx %ecx # ecx<- vBB
- shrdl %edx,%eax
- sarl %cl,%edx
- testb $32,%cl
- je 2f
- movl %edx,%eax
- sarl $31,%edx
-2:
- SET_VREG_WORD %edx rINST 1 # v[AA+1]<- edx
- jmp .LOP_SHR_LONG_2ADDR_finish
-
-/* ------------------------------ */
- .balign 64
-.L_OP_USHR_LONG_2ADDR: /* 0xc5 */
-/* File: x86/OP_USHR_LONG_2ADDR.S */
- /*
- * Long integer shift, 2addr version. vA is 64-bit value/result, vB is
- * 32-bit shift distance.
- */
- /* shl-long/2addr vA, vB */
- /* ecx gets shift count */
- /* Need to spill edx */
- /* rINSTw gets AA */
- movzbl rINSTbl,%ecx # ecx<- BA
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_WORD %eax rINST 0 # eax<- v[AA+0]
- sarl $4,%ecx # ecx<- B
- GET_VREG_WORD %edx rINST 1 # edx<- v[AA+1]
- GET_VREG_R %ecx %ecx # ecx<- vBB
- shrdl %edx,%eax
- shrl %cl,%edx
- testb $32,%cl
- je 2f
- movl %edx,%eax
- xorl %edx,%edx
-2:
- SET_VREG_WORD %edx rINST 1 # v[AA+1]<- edx
- jmp .LOP_USHR_LONG_2ADDR_finish
-
-/* ------------------------------ */
- .balign 64
-.L_OP_ADD_FLOAT_2ADDR: /* 0xc6 */
-/* File: x86/OP_ADD_FLOAT_2ADDR.S */
-/* File: x86/binflop2addr.S */
- /*
- * Generic 32-bit binary float operation.
- *
- * For: add-fp, sub-fp, mul-fp, div-fp
- */
-
- /* binop/2addr vA, vB */
- movzx rINSTbl,%ecx # ecx<- A+
- andb $0xf,%cl # ecx<- A
- flds (rFP,%ecx,4) # vAA to fp stack
- sarl $4,rINST # rINST<- B
- fadds (rFP,rINST,4) # ex: faddp
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
- fstps (rFP,%ecx,4) # %st to vA
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SUB_FLOAT_2ADDR: /* 0xc7 */
-/* File: x86/OP_SUB_FLOAT_2ADDR.S */
-/* File: x86/binflop2addr.S */
- /*
- * Generic 32-bit binary float operation.
- *
- * For: add-fp, sub-fp, mul-fp, div-fp
- */
-
- /* binop/2addr vA, vB */
- movzx rINSTbl,%ecx # ecx<- A+
- andb $0xf,%cl # ecx<- A
- flds (rFP,%ecx,4) # vAA to fp stack
- sarl $4,rINST # rINST<- B
- fsubs (rFP,rINST,4) # ex: faddp
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
- fstps (rFP,%ecx,4) # %st to vA
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_MUL_FLOAT_2ADDR: /* 0xc8 */
-/* File: x86/OP_MUL_FLOAT_2ADDR.S */
-/* File: x86/binflop2addr.S */
- /*
- * Generic 32-bit binary float operation.
- *
- * For: add-fp, sub-fp, mul-fp, div-fp
- */
-
- /* binop/2addr vA, vB */
- movzx rINSTbl,%ecx # ecx<- A+
- andb $0xf,%cl # ecx<- A
- flds (rFP,%ecx,4) # vAA to fp stack
- sarl $4,rINST # rINST<- B
- fmuls (rFP,rINST,4) # ex: faddp
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
- fstps (rFP,%ecx,4) # %st to vA
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_DIV_FLOAT_2ADDR: /* 0xc9 */
-/* File: x86/OP_DIV_FLOAT_2ADDR.S */
-/* File: x86/binflop2addr.S */
- /*
- * Generic 32-bit binary float operation.
- *
- * For: add-fp, sub-fp, mul-fp, div-fp
- */
-
- /* binop/2addr vA, vB */
- movzx rINSTbl,%ecx # ecx<- A+
- andb $0xf,%cl # ecx<- A
- flds (rFP,%ecx,4) # vAA to fp stack
- sarl $4,rINST # rINST<- B
- fdivs (rFP,rINST,4) # ex: faddp
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
- fstps (rFP,%ecx,4) # %st to vA
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_REM_FLOAT_2ADDR: /* 0xca */
-/* File: x86/OP_REM_FLOAT_2ADDR.S */
- /* rem_float/2addr vA, vB */
- movzx rINSTbl,%ecx # ecx<- A+
- sarl $4,rINST # rINST<- B
- flds (rFP,rINST,4) # vBB to fp stack
- andb $0xf,%cl # ecx<- A
- flds (rFP,%ecx,4) # vAA to fp stack
- FETCH_INST_OPCODE 1 %edx
-1:
- fprem
- fstsw %ax
- sahf
- jp 1b
- fstp %st(1)
- ADVANCE_PC 1
- fstps (rFP,%ecx,4) # %st to vA
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_ADD_DOUBLE_2ADDR: /* 0xcb */
-/* File: x86/OP_ADD_DOUBLE_2ADDR.S */
-/* File: x86/binflop2addr.S */
- /*
- * Generic 32-bit binary float operation.
- *
- * For: add-fp, sub-fp, mul-fp, div-fp
- */
-
- /* binop/2addr vA, vB */
- movzx rINSTbl,%ecx # ecx<- A+
- andb $0xf,%cl # ecx<- A
- fldl (rFP,%ecx,4) # vAA to fp stack
- sarl $4,rINST # rINST<- B
- faddl (rFP,rINST,4) # ex: faddp
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
- fstpl (rFP,%ecx,4) # %st to vA
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SUB_DOUBLE_2ADDR: /* 0xcc */
-/* File: x86/OP_SUB_DOUBLE_2ADDR.S */
-/* File: x86/binflop2addr.S */
- /*
- * Generic 32-bit binary float operation.
- *
- * For: add-fp, sub-fp, mul-fp, div-fp
- */
-
- /* binop/2addr vA, vB */
- movzx rINSTbl,%ecx # ecx<- A+
- andb $0xf,%cl # ecx<- A
- fldl (rFP,%ecx,4) # vAA to fp stack
- sarl $4,rINST # rINST<- B
- fsubl (rFP,rINST,4) # ex: faddp
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
- fstpl (rFP,%ecx,4) # %st to vA
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_MUL_DOUBLE_2ADDR: /* 0xcd */
-/* File: x86/OP_MUL_DOUBLE_2ADDR.S */
-/* File: x86/binflop2addr.S */
- /*
- * Generic 32-bit binary float operation.
- *
- * For: add-fp, sub-fp, mul-fp, div-fp
- */
-
- /* binop/2addr vA, vB */
- movzx rINSTbl,%ecx # ecx<- A+
- andb $0xf,%cl # ecx<- A
- fldl (rFP,%ecx,4) # vAA to fp stack
- sarl $4,rINST # rINST<- B
- fmull (rFP,rINST,4) # ex: faddp
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
- fstpl (rFP,%ecx,4) # %st to vA
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_DIV_DOUBLE_2ADDR: /* 0xce */
-/* File: x86/OP_DIV_DOUBLE_2ADDR.S */
-/* File: x86/binflop2addr.S */
- /*
- * Generic 32-bit binary float operation.
- *
- * For: add-fp, sub-fp, mul-fp, div-fp
- */
-
- /* binop/2addr vA, vB */
- movzx rINSTbl,%ecx # ecx<- A+
- andb $0xf,%cl # ecx<- A
- fldl (rFP,%ecx,4) # vAA to fp stack
- sarl $4,rINST # rINST<- B
- fdivl (rFP,rINST,4) # ex: faddp
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
- fstpl (rFP,%ecx,4) # %st to vA
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_REM_DOUBLE_2ADDR: /* 0xcf */
-/* File: x86/OP_REM_DOUBLE_2ADDR.S */
- /* rem_float/2addr vA, vB */
- movzx rINSTbl,%ecx # ecx<- A+
- sarl $4,rINST # rINST<- B
- fldl (rFP,rINST,4) # vBB to fp stack
- andb $0xf,%cl # ecx<- A
- fldl (rFP,%ecx,4) # vAA to fp stack
- FETCH_INST_OPCODE 1 %edx
-1:
- fprem
- fstsw %ax
- sahf
- jp 1b
- fstp %st(1)
- ADVANCE_PC 1
- fstpl (rFP,%ecx,4) # %st to vA
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_ADD_INT_LIT16: /* 0xd0 */
-/* File: x86/OP_ADD_INT_LIT16.S */
-/* File: x86/binopLit16.S */
- /*
- * Generic 32-bit "lit16" binary operation. Provide an "instr" line
- * that specifies an instruction that performs "result = eax op ecx".
- * This could be an x86 instruction or a function call. (If the result
- * comes back in a register other than eax, you can override "result".)
- *
- * For: add-int/lit16, rsub-int,
- * and-int/lit16, or-int/lit16, xor-int/lit16
- */
- /* binop/lit16 vA, vB, #+CCCC */
- movzbl rINSTbl,%eax # eax<- 000000BA
- sarl $4,%eax # eax<- B
- GET_VREG_R %eax %eax # eax<- vB
- movswl 2(rPC),%ecx # ecx<- ssssCCCC
- andb $0xf,rINSTbl # rINST<- A
- addl %ecx,%eax # for example: addl %ecx, %eax
- SET_VREG %eax rINST
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_RSUB_INT: /* 0xd1 */
-/* File: x86/OP_RSUB_INT.S */
-/* File: x86/binopLit16.S */
- /*
- * Generic 32-bit "lit16" binary operation. Provide an "instr" line
- * that specifies an instruction that performs "result = eax op ecx".
- * This could be an x86 instruction or a function call. (If the result
- * comes back in a register other than eax, you can override "result".)
- *
- * For: add-int/lit16, rsub-int,
- * and-int/lit16, or-int/lit16, xor-int/lit16
- */
- /* binop/lit16 vA, vB, #+CCCC */
- movzbl rINSTbl,%eax # eax<- 000000BA
- sarl $4,%eax # eax<- B
- GET_VREG_R %eax %eax # eax<- vB
- movswl 2(rPC),%ecx # ecx<- ssssCCCC
- andb $0xf,rINSTbl # rINST<- A
- subl %eax,%ecx # for example: addl %ecx, %eax
- SET_VREG %ecx rINST
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_MUL_INT_LIT16: /* 0xd2 */
-/* File: x86/OP_MUL_INT_LIT16.S */
- /* mul/lit16 vA, vB, #+CCCC */
- /* Need A in rINST, ssssCCCC in ecx, vB in eax */
- movzbl rINSTbl,%eax # eax<- 000000BA
- sarl $4,%eax # eax<- B
- GET_VREG_R %eax %eax # eax<- vB
- movswl 2(rPC),%ecx # ecx<- ssssCCCC
- andb $0xf,rINSTbl # rINST<- A
- imull %ecx,%eax # trashes edx
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- SET_VREG %eax rINST
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_DIV_INT_LIT16: /* 0xd3 */
-/* File: x86/OP_DIV_INT_LIT16.S */
-/* File: x86/bindivLit16.S */
- /*
- * 32-bit binary div/rem operation. Handles special case of op0=minint and
- * op1=-1.
- */
- /* div/rem/lit16 vA, vB, #+CCCC */
- /* Need A in rINST, ssssCCCC in ecx, vB in eax */
- movzbl rINSTbl,%eax # eax<- 000000BA
- sarl $4,%eax # eax<- B
- GET_VREG_R %eax %eax # eax<- vB
- movswl 2(rPC),%ecx # ecx<- ssssCCCC
- andb $0xf,rINSTbl # rINST<- A
- cmpl $0,%ecx
- je common_errDivideByZero
- cmpl $-1,%ecx
- jne .LOP_DIV_INT_LIT16_continue_div
- cmpl $0x80000000,%eax
- jne .LOP_DIV_INT_LIT16_continue_div
- movl $0x80000000,%eax
- jmp .LOP_DIV_INT_LIT16_finish_div
-
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_REM_INT_LIT16: /* 0xd4 */
-/* File: x86/OP_REM_INT_LIT16.S */
-/* File: x86/bindivLit16.S */
- /*
- * 32-bit binary div/rem operation. Handles special case of op0=minint and
- * op1=-1.
- */
- /* div/rem/lit16 vA, vB, #+CCCC */
- /* Need A in rINST, ssssCCCC in ecx, vB in eax */
- movzbl rINSTbl,%eax # eax<- 000000BA
- sarl $4,%eax # eax<- B
- GET_VREG_R %eax %eax # eax<- vB
- movswl 2(rPC),%ecx # ecx<- ssssCCCC
- andb $0xf,rINSTbl # rINST<- A
- cmpl $0,%ecx
- je common_errDivideByZero
- cmpl $-1,%ecx
- jne .LOP_REM_INT_LIT16_continue_div
- cmpl $0x80000000,%eax
- jne .LOP_REM_INT_LIT16_continue_div
- movl $0,%edx
- jmp .LOP_REM_INT_LIT16_finish_div
-
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_AND_INT_LIT16: /* 0xd5 */
-/* File: x86/OP_AND_INT_LIT16.S */
-/* File: x86/binopLit16.S */
- /*
- * Generic 32-bit "lit16" binary operation. Provide an "instr" line
- * that specifies an instruction that performs "result = eax op ecx".
- * This could be an x86 instruction or a function call. (If the result
- * comes back in a register other than eax, you can override "result".)
- *
- * For: add-int/lit16, rsub-int,
- * and-int/lit16, or-int/lit16, xor-int/lit16
- */
- /* binop/lit16 vA, vB, #+CCCC */
- movzbl rINSTbl,%eax # eax<- 000000BA
- sarl $4,%eax # eax<- B
- GET_VREG_R %eax %eax # eax<- vB
- movswl 2(rPC),%ecx # ecx<- ssssCCCC
- andb $0xf,rINSTbl # rINST<- A
- andl %ecx,%eax # for example: addl %ecx, %eax
- SET_VREG %eax rINST
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_OR_INT_LIT16: /* 0xd6 */
-/* File: x86/OP_OR_INT_LIT16.S */
-/* File: x86/binopLit16.S */
- /*
- * Generic 32-bit "lit16" binary operation. Provide an "instr" line
- * that specifies an instruction that performs "result = eax op ecx".
- * This could be an x86 instruction or a function call. (If the result
- * comes back in a register other than eax, you can override "result".)
- *
- * For: add-int/lit16, rsub-int,
- * and-int/lit16, or-int/lit16, xor-int/lit16
- */
- /* binop/lit16 vA, vB, #+CCCC */
- movzbl rINSTbl,%eax # eax<- 000000BA
- sarl $4,%eax # eax<- B
- GET_VREG_R %eax %eax # eax<- vB
- movswl 2(rPC),%ecx # ecx<- ssssCCCC
- andb $0xf,rINSTbl # rINST<- A
- orl %ecx,%eax # for example: addl %ecx, %eax
- SET_VREG %eax rINST
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_XOR_INT_LIT16: /* 0xd7 */
-/* File: x86/OP_XOR_INT_LIT16.S */
-/* File: x86/binopLit16.S */
- /*
- * Generic 32-bit "lit16" binary operation. Provide an "instr" line
- * that specifies an instruction that performs "result = eax op ecx".
- * This could be an x86 instruction or a function call. (If the result
- * comes back in a register other than eax, you can override "result".)
- *
- * For: add-int/lit16, rsub-int,
- * and-int/lit16, or-int/lit16, xor-int/lit16
- */
- /* binop/lit16 vA, vB, #+CCCC */
- movzbl rINSTbl,%eax # eax<- 000000BA
- sarl $4,%eax # eax<- B
- GET_VREG_R %eax %eax # eax<- vB
- movswl 2(rPC),%ecx # ecx<- ssssCCCC
- andb $0xf,rINSTbl # rINST<- A
- xor %ecx,%eax # for example: addl %ecx, %eax
- SET_VREG %eax rINST
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_ADD_INT_LIT8: /* 0xd8 */
-/* File: x86/OP_ADD_INT_LIT8.S */
-/* File: x86/binopLit8.S */
- /*
- * Generic 32-bit "lit8" binary operation. Provide an "instr" line
- * that specifies an instruction that performs "result = eax op ecx".
- * This could be an x86 instruction or a function call. (If the result
- * comes back in a register other than r0, you can override "result".)
- *
- * For: add-int/lit8, rsub-int/lit8
- * and-int/lit8, or-int/lit8, xor-int/lit8,
- * shl-int/lit8, shr-int/lit8, ushr-int/lit8
- */
- /* binop/lit8 vAA, vBB, #+CC */
- movzbl 2(rPC),%eax # eax<- BB
- movsbl 3(rPC),%ecx # ecx<- ssssssCC
- GET_VREG_R %eax %eax # eax<- rBB
- addl %ecx,%eax # ex: addl %ecx,%eax
- FETCH_INST_OPCODE 2 %edx
- SET_VREG %eax rINST
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_RSUB_INT_LIT8: /* 0xd9 */
-/* File: x86/OP_RSUB_INT_LIT8.S */
-/* File: x86/binopLit8.S */
- /*
- * Generic 32-bit "lit8" binary operation. Provide an "instr" line
- * that specifies an instruction that performs "result = eax op ecx".
- * This could be an x86 instruction or a function call. (If the result
- * comes back in a register other than r0, you can override "result".)
- *
- * For: add-int/lit8, rsub-int/lit8
- * and-int/lit8, or-int/lit8, xor-int/lit8,
- * shl-int/lit8, shr-int/lit8, ushr-int/lit8
- */
- /* binop/lit8 vAA, vBB, #+CC */
- movzbl 2(rPC),%eax # eax<- BB
- movsbl 3(rPC),%ecx # ecx<- ssssssCC
- GET_VREG_R %eax %eax # eax<- rBB
- subl %eax,%ecx # ex: addl %ecx,%eax
- FETCH_INST_OPCODE 2 %edx
- SET_VREG %ecx rINST
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_MUL_INT_LIT8: /* 0xda */
-/* File: x86/OP_MUL_INT_LIT8.S */
- /* mul/lit8 vAA, vBB, #+CC */
- movzbl 2(rPC),%eax # eax<- BB
- movsbl 3(rPC),%ecx # ecx<- ssssssCC
- GET_VREG_R %eax %eax # eax<- rBB
- imull %ecx,%eax # trashes edx
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- SET_VREG %eax rINST
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_DIV_INT_LIT8: /* 0xdb */
-/* File: x86/OP_DIV_INT_LIT8.S */
-/* File: x86/bindivLit8.S */
- /*
- * 32-bit div/rem "lit8" binary operation. Handles special case of
- * op0=minint & op1=-1
- */
- /* div/rem/lit8 vAA, vBB, #+CC */
- movzbl 2(rPC),%eax # eax<- BB
- movsbl 3(rPC),%ecx # ecx<- ssssssCC
- GET_VREG_R %eax %eax # eax<- rBB
- cmpl $0,%ecx
- je common_errDivideByZero
- cmpl $0x80000000,%eax
- jne .LOP_DIV_INT_LIT8_continue_div
- cmpl $-1,%ecx
- jne .LOP_DIV_INT_LIT8_continue_div
- movl $0x80000000,%eax
- jmp .LOP_DIV_INT_LIT8_finish_div
-
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_REM_INT_LIT8: /* 0xdc */
-/* File: x86/OP_REM_INT_LIT8.S */
-/* File: x86/bindivLit8.S */
- /*
- * 32-bit div/rem "lit8" binary operation. Handles special case of
- * op0=minint & op1=-1
- */
- /* div/rem/lit8 vAA, vBB, #+CC */
- movzbl 2(rPC),%eax # eax<- BB
- movsbl 3(rPC),%ecx # ecx<- ssssssCC
- GET_VREG_R %eax %eax # eax<- rBB
- cmpl $0,%ecx
- je common_errDivideByZero
- cmpl $0x80000000,%eax
- jne .LOP_REM_INT_LIT8_continue_div
- cmpl $-1,%ecx
- jne .LOP_REM_INT_LIT8_continue_div
- movl $0,%edx
- jmp .LOP_REM_INT_LIT8_finish_div
-
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_AND_INT_LIT8: /* 0xdd */
-/* File: x86/OP_AND_INT_LIT8.S */
-/* File: x86/binopLit8.S */
- /*
- * Generic 32-bit "lit8" binary operation. Provide an "instr" line
- * that specifies an instruction that performs "result = eax op ecx".
- * This could be an x86 instruction or a function call. (If the result
- * comes back in a register other than r0, you can override "result".)
- *
- * For: add-int/lit8, rsub-int/lit8
- * and-int/lit8, or-int/lit8, xor-int/lit8,
- * shl-int/lit8, shr-int/lit8, ushr-int/lit8
- */
- /* binop/lit8 vAA, vBB, #+CC */
- movzbl 2(rPC),%eax # eax<- BB
- movsbl 3(rPC),%ecx # ecx<- ssssssCC
- GET_VREG_R %eax %eax # eax<- rBB
- andl %ecx,%eax # ex: addl %ecx,%eax
- FETCH_INST_OPCODE 2 %edx
- SET_VREG %eax rINST
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_OR_INT_LIT8: /* 0xde */
-/* File: x86/OP_OR_INT_LIT8.S */
-/* File: x86/binopLit8.S */
- /*
- * Generic 32-bit "lit8" binary operation. Provide an "instr" line
- * that specifies an instruction that performs "result = eax op ecx".
- * This could be an x86 instruction or a function call. (If the result
- * comes back in a register other than r0, you can override "result".)
- *
- * For: add-int/lit8, rsub-int/lit8
- * and-int/lit8, or-int/lit8, xor-int/lit8,
- * shl-int/lit8, shr-int/lit8, ushr-int/lit8
- */
- /* binop/lit8 vAA, vBB, #+CC */
- movzbl 2(rPC),%eax # eax<- BB
- movsbl 3(rPC),%ecx # ecx<- ssssssCC
- GET_VREG_R %eax %eax # eax<- rBB
- orl %ecx,%eax # ex: addl %ecx,%eax
- FETCH_INST_OPCODE 2 %edx
- SET_VREG %eax rINST
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_XOR_INT_LIT8: /* 0xdf */
-/* File: x86/OP_XOR_INT_LIT8.S */
-/* File: x86/binopLit8.S */
- /*
- * Generic 32-bit "lit8" binary operation. Provide an "instr" line
- * that specifies an instruction that performs "result = eax op ecx".
- * This could be an x86 instruction or a function call. (If the result
- * comes back in a register other than r0, you can override "result".)
- *
- * For: add-int/lit8, rsub-int/lit8
- * and-int/lit8, or-int/lit8, xor-int/lit8,
- * shl-int/lit8, shr-int/lit8, ushr-int/lit8
- */
- /* binop/lit8 vAA, vBB, #+CC */
- movzbl 2(rPC),%eax # eax<- BB
- movsbl 3(rPC),%ecx # ecx<- ssssssCC
- GET_VREG_R %eax %eax # eax<- rBB
- xor %ecx,%eax # ex: addl %ecx,%eax
- FETCH_INST_OPCODE 2 %edx
- SET_VREG %eax rINST
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SHL_INT_LIT8: /* 0xe0 */
-/* File: x86/OP_SHL_INT_LIT8.S */
-/* File: x86/binopLit8.S */
- /*
- * Generic 32-bit "lit8" binary operation. Provide an "instr" line
- * that specifies an instruction that performs "result = eax op ecx".
- * This could be an x86 instruction or a function call. (If the result
- * comes back in a register other than r0, you can override "result".)
- *
- * For: add-int/lit8, rsub-int/lit8
- * and-int/lit8, or-int/lit8, xor-int/lit8,
- * shl-int/lit8, shr-int/lit8, ushr-int/lit8
- */
- /* binop/lit8 vAA, vBB, #+CC */
- movzbl 2(rPC),%eax # eax<- BB
- movsbl 3(rPC),%ecx # ecx<- ssssssCC
- GET_VREG_R %eax %eax # eax<- rBB
- sall %cl,%eax # ex: addl %ecx,%eax
- FETCH_INST_OPCODE 2 %edx
- SET_VREG %eax rINST
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SHR_INT_LIT8: /* 0xe1 */
-/* File: x86/OP_SHR_INT_LIT8.S */
-/* File: x86/binopLit8.S */
- /*
- * Generic 32-bit "lit8" binary operation. Provide an "instr" line
- * that specifies an instruction that performs "result = eax op ecx".
- * This could be an x86 instruction or a function call. (If the result
- * comes back in a register other than r0, you can override "result".)
- *
- * For: add-int/lit8, rsub-int/lit8
- * and-int/lit8, or-int/lit8, xor-int/lit8,
- * shl-int/lit8, shr-int/lit8, ushr-int/lit8
- */
- /* binop/lit8 vAA, vBB, #+CC */
- movzbl 2(rPC),%eax # eax<- BB
- movsbl 3(rPC),%ecx # ecx<- ssssssCC
- GET_VREG_R %eax %eax # eax<- rBB
- sarl %cl,%eax # ex: addl %ecx,%eax
- FETCH_INST_OPCODE 2 %edx
- SET_VREG %eax rINST
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_USHR_INT_LIT8: /* 0xe2 */
-/* File: x86/OP_USHR_INT_LIT8.S */
-/* File: x86/binopLit8.S */
- /*
- * Generic 32-bit "lit8" binary operation. Provide an "instr" line
- * that specifies an instruction that performs "result = eax op ecx".
- * This could be an x86 instruction or a function call. (If the result
- * comes back in a register other than r0, you can override "result".)
- *
- * For: add-int/lit8, rsub-int/lit8
- * and-int/lit8, or-int/lit8, xor-int/lit8,
- * shl-int/lit8, shr-int/lit8, ushr-int/lit8
- */
- /* binop/lit8 vAA, vBB, #+CC */
- movzbl 2(rPC),%eax # eax<- BB
- movsbl 3(rPC),%ecx # ecx<- ssssssCC
- GET_VREG_R %eax %eax # eax<- rBB
- shrl %cl,%eax # ex: addl %ecx,%eax
- FETCH_INST_OPCODE 2 %edx
- SET_VREG %eax rINST
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IGET_VOLATILE: /* 0xe3 */
-/* File: x86/OP_IGET_VOLATILE.S */
-/* File: x86/OP_IGET.S */
- /*
- * General 32-bit instance field get.
- *
- * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
- */
- /* op vA, vB, field@CCCC */
- movl rSELF,%ecx
- movzwl 2(rPC),%edx # edx<- 0000CCCC
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IGET_VOLATILE_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp) # needed by dvmResolveInstField
- movl rSELF,%edx
- jmp .LOP_IGET_VOLATILE_resolve
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IPUT_VOLATILE: /* 0xe4 */
-/* File: x86/OP_IPUT_VOLATILE.S */
-/* File: x86/OP_IPUT.S */
-
- /*
- * General 32-bit instance field put.
- *
- * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short
- */
- /* op vA, vB, field@CCCC */
- movl rSELF,%ecx
- movzwl 2(rPC),%edx # %edx<- 0000CCCC
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IPUT_VOLATILE_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp)
- movl rSELF,%edx
- jmp .LOP_IPUT_VOLATILE_resolve
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SGET_VOLATILE: /* 0xe5 */
-/* File: x86/OP_SGET_VOLATILE.S */
-/* File: x86/OP_SGET.S */
- /*
- * General 32-bit SGET handler.
- *
- * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
- */
- /* op vAA, field@BBBB */
- movl rSELF,%ecx
- movzwl 2(rPC),%eax # eax<- field ref BBBB
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SGET_VOLATILE_resolve # if not, make it so
-.LOP_SGET_VOLATILE_finish: # field ptr in eax
- movl offStaticField_value(%eax),%eax
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- SET_VREG %eax rINST
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SPUT_VOLATILE: /* 0xe6 */
-/* File: x86/OP_SPUT_VOLATILE.S */
-/* File: x86/OP_SPUT.S */
- /*
- * General 32-bit SPUT handler.
- *
- * for: sput, sput-boolean, sput-byte, sput-char, sput-short
- */
- /* op vAA, field@BBBB */
- movl rSELF,%ecx
- movzwl 2(rPC),%eax # eax<- field ref BBBB
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SPUT_VOLATILE_resolve # if not, make it so
-.LOP_SPUT_VOLATILE_finish: # field ptr in eax
- GET_VREG_R %ecx rINST
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- movl %ecx,offStaticField_value(%eax)
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */
-/* File: x86/OP_IGET_OBJECT_VOLATILE.S */
-/* File: x86/OP_IGET.S */
- /*
- * General 32-bit instance field get.
- *
- * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
- */
- /* op vA, vB, field@CCCC */
- movl rSELF,%ecx
- movzwl 2(rPC),%edx # edx<- 0000CCCC
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IGET_OBJECT_VOLATILE_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp) # needed by dvmResolveInstField
- movl rSELF,%edx
- jmp .LOP_IGET_OBJECT_VOLATILE_resolve
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IGET_WIDE_VOLATILE: /* 0xe8 */
- /* (stub) */
- SAVE_PC_FP_TO_SELF %ecx # leaves rSELF in %ecx
- movl %ecx,OUT_ARG0(%esp) # self is first arg to function
- call dvmMterp_OP_IGET_WIDE_VOLATILE # do the real work
- mov rSELF,%ecx
- LOAD_PC_FP_FROM_SELF # retrieve updated values
- FETCH_INST
- GOTO_NEXT
-/* ------------------------------ */
- .balign 64
-.L_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */
- /* (stub) */
- SAVE_PC_FP_TO_SELF %ecx # leaves rSELF in %ecx
- movl %ecx,OUT_ARG0(%esp) # self is first arg to function
- call dvmMterp_OP_IPUT_WIDE_VOLATILE # do the real work
- mov rSELF,%ecx
- LOAD_PC_FP_FROM_SELF # retrieve updated values
- FETCH_INST
- GOTO_NEXT
-/* ------------------------------ */
- .balign 64
-.L_OP_SGET_WIDE_VOLATILE: /* 0xea */
- /* (stub) */
- SAVE_PC_FP_TO_SELF %ecx # leaves rSELF in %ecx
- movl %ecx,OUT_ARG0(%esp) # self is first arg to function
- call dvmMterp_OP_SGET_WIDE_VOLATILE # do the real work
- mov rSELF,%ecx
- LOAD_PC_FP_FROM_SELF # retrieve updated values
- FETCH_INST
- GOTO_NEXT
-/* ------------------------------ */
- .balign 64
-.L_OP_SPUT_WIDE_VOLATILE: /* 0xeb */
- /* (stub) */
- SAVE_PC_FP_TO_SELF %ecx # leaves rSELF in %ecx
- movl %ecx,OUT_ARG0(%esp) # self is first arg to function
- call dvmMterp_OP_SPUT_WIDE_VOLATILE # do the real work
- mov rSELF,%ecx
- LOAD_PC_FP_FROM_SELF # retrieve updated values
- FETCH_INST
- GOTO_NEXT
-/* ------------------------------ */
- .balign 64
-.L_OP_BREAKPOINT: /* 0xec */
-/* File: x86/OP_BREAKPOINT.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_THROW_VERIFICATION_ERROR: /* 0xed */
-/* File: x86/OP_THROW_VERIFICATION_ERROR.S */
- /*
- * Handle a throw-verification-error instruction. This throws an
- * exception for an error discovered during verification. The
- * exception is indicated by AA, with some detail provided by BBBB.
- */
- /* op AA, ref@BBBB */
- movl rSELF,%ecx
- movzwl 2(rPC),%eax # eax<- BBBB
- movl offThread_method(%ecx),%ecx # ecx<- self->method
- EXPORT_PC
- movl %eax,OUT_ARG2(%esp) # arg2<- BBBB
- movl rINST,OUT_ARG1(%esp) # arg1<- AA
- movl %ecx,OUT_ARG0(%esp) # arg0<- method
- call dvmThrowVerificationError # call(method, kind, ref)
- jmp common_exceptionThrown # handle exception
-
-/* ------------------------------ */
- .balign 64
-.L_OP_EXECUTE_INLINE: /* 0xee */
-/* File: x86/OP_EXECUTE_INLINE.S */
- /*
- * Execute a "native inline" instruction.
- *
- * We will be calling through a function table:
- *
- * (*gDvmInlineOpsTable[opIndex].func)(arg0, arg1, arg2, arg3, pResult)
- *
- * Ignores argument count - always loads 4.
- *
- */
- /* [opt] execute-inline vAA, {vC, vD, vE, vF}, inline@BBBB */
- movl rSELF,%ecx
- EXPORT_PC
- movzwl 2(rPC),%eax # eax<- BBBB
- leal offThread_retval(%ecx),%ecx # ecx<- & self->retval
- movl %ecx,OUT_ARG4(%esp)
- call .LOP_EXECUTE_INLINE_continue # make call; will return after
- testl %eax,%eax # successful?
- FETCH_INST_OPCODE 3 %edx
- je common_exceptionThrown # no, handle exception
- ADVANCE_PC 3
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_EXECUTE_INLINE_RANGE: /* 0xef */
- /* (stub) */
- SAVE_PC_FP_TO_SELF %ecx # leaves rSELF in %ecx
- movl %ecx,OUT_ARG0(%esp) # self is first arg to function
- call dvmMterp_OP_EXECUTE_INLINE_RANGE # do the real work
- mov rSELF,%ecx
- LOAD_PC_FP_FROM_SELF # retrieve updated values
- FETCH_INST
- GOTO_NEXT
-/* ------------------------------ */
- .balign 64
-.L_OP_INVOKE_OBJECT_INIT: /* 0xf0 */
- /* (stub) */
- SAVE_PC_FP_TO_SELF %ecx # leaves rSELF in %ecx
- movl %ecx,OUT_ARG0(%esp) # self is first arg to function
- call dvmMterp_OP_INVOKE_OBJECT_INIT # do the real work
- mov rSELF,%ecx
- LOAD_PC_FP_FROM_SELF # retrieve updated values
- FETCH_INST
- GOTO_NEXT
-/* ------------------------------ */
- .balign 64
-.L_OP_RETURN_VOID_BARRIER: /* 0xf1 */
- /* (stub) */
- SAVE_PC_FP_TO_SELF %ecx # leaves rSELF in %ecx
- movl %ecx,OUT_ARG0(%esp) # self is first arg to function
- call dvmMterp_OP_RETURN_VOID_BARRIER # do the real work
- mov rSELF,%ecx
- LOAD_PC_FP_FROM_SELF # retrieve updated values
- FETCH_INST
- GOTO_NEXT
-/* ------------------------------ */
- .balign 64
-.L_OP_IGET_QUICK: /* 0xf2 */
-/* File: x86/OP_IGET_QUICK.S */
- /* For: iget-quick, iget-object-quick */
- /* op vA, vB, offset@CCCC */
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- GET_VREG_R %ecx %ecx # vB (object we're operating on)
- movzwl 2(rPC),%eax # eax<- field byte offset
- cmpl $0,%ecx # is object null?
- je common_errNullObject
- movl (%ecx,%eax,1),%eax
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- andb $0xf,rINSTbl # rINST<- A
- SET_VREG %eax rINST # fp[A]<- result
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IGET_WIDE_QUICK: /* 0xf3 */
-/* File: x86/OP_IGET_WIDE_QUICK.S */
- /* For: iget-wide-quick */
- /* op vA, vB, offset@CCCC */
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- GET_VREG_R %ecx %ecx # vB (object we're operating on)
- movzwl 2(rPC),%eax # eax<- field byte offset
- cmpl $0,%ecx # is object null?
- je common_errNullObject
- leal (%ecx,%eax,1),%eax # eax<- address of 64-bit source
- movl (%eax),%ecx # ecx<- lsw
- movl 4(%eax),%eax # eax<- msw
- andb $0xf,rINSTbl # rINST<- A
- FETCH_INST_OPCODE 2 %edx
- SET_VREG_WORD %ecx rINST 0 # v[A+0]<- lsw
- SET_VREG_WORD %eax rINST 1 # v[A+1]<- msw
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IGET_OBJECT_QUICK: /* 0xf4 */
-/* File: x86/OP_IGET_OBJECT_QUICK.S */
-/* File: x86/OP_IGET_QUICK.S */
- /* For: iget-quick, iget-object-quick */
- /* op vA, vB, offset@CCCC */
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- GET_VREG_R %ecx %ecx # vB (object we're operating on)
- movzwl 2(rPC),%eax # eax<- field byte offset
- cmpl $0,%ecx # is object null?
- je common_errNullObject
- movl (%ecx,%eax,1),%eax
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- andb $0xf,rINSTbl # rINST<- A
- SET_VREG %eax rINST # fp[A]<- result
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IPUT_QUICK: /* 0xf5 */
-/* File: x86/OP_IPUT_QUICK.S */
- /* For: iput-quick */
- /* op vA, vB, offset@CCCC */
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- GET_VREG_R %ecx %ecx # vB (object we're operating on)
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_R rINST,rINST # rINST<- v[A]
- movzwl 2(rPC),%eax # eax<- field byte offset
- testl %ecx,%ecx # is object null?
- FETCH_INST_OPCODE 2 %edx
- je common_errNullObject
- movl rINST,(%ecx,%eax,1)
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IPUT_WIDE_QUICK: /* 0xf6 */
-/* File: x86/OP_IPUT_WIDE_QUICK.S */
- /* For: iput-wide-quick */
- /* op vA, vB, offset@CCCC */
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- GET_VREG_R %ecx %ecx # vB (object we're operating on)
- movzwl 2(rPC),%eax # eax<- field byte offset
- testl %ecx,%ecx # is object null?
- je common_errNullObject
- leal (%ecx,%eax,1),%ecx # ecx<- Address of 64-bit target
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_WORD %eax rINST 0 # eax<- lsw
- GET_VREG_WORD rINST rINST 1 # rINST<- msw
- FETCH_INST_OPCODE 2 %edx
- movl %eax,(%ecx)
- movl rINST,4(%ecx)
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IPUT_OBJECT_QUICK: /* 0xf7 */
-/* File: x86/OP_IPUT_OBJECT_QUICK.S */
- /* For: iput-object-quick */
- /* op vA, vB, offset@CCCC */
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- GET_VREG_R %ecx %ecx # vB (object we're operating on)
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_R rINST rINST # rINST<- v[A]
- movzwl 2(rPC),%eax # eax<- field byte offset
- testl %ecx,%ecx # is object null?
- je common_errNullObject
- movl rINST,(%ecx,%eax,1)
- movl rSELF,%eax
- jmp .LOP_IPUT_OBJECT_QUICK_finish
-
-/* ------------------------------ */
- .balign 64
-.L_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */
-/* File: x86/OP_INVOKE_VIRTUAL_QUICK.S */
- /*
- * Handle an optimized virtual method call.
- *
- * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range
- */
- /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
- /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
- movzwl 4(rPC),%eax # eax<- FEDC or CCCC
- movzwl 2(rPC),%ecx # ecx<- BBBB
- .if (!0)
- andl $0xf,%eax # eax<- C (or stays CCCC)
- .endif
- GET_VREG_R %eax %eax # eax<- vC ("this" ptr)
- testl %eax,%eax # null?
- je common_errNullObject # yep, throw exception
- movl offObject_clazz(%eax),%eax # eax<- thisPtr->clazz
- movl offClassObject_vtable(%eax),%eax # eax<- thisPtr->clazz->vtable
- EXPORT_PC # might throw later - get ready
- movl (%eax,%ecx,4),%eax # eax<- vtable[BBBB]
- jmp common_invokeMethodNoRange
-
-/* ------------------------------ */
- .balign 64
-.L_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */
-/* File: x86/OP_INVOKE_VIRTUAL_QUICK_RANGE.S */
-/* File: x86/OP_INVOKE_VIRTUAL_QUICK.S */
- /*
- * Handle an optimized virtual method call.
- *
- * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range
- */
- /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
- /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
- movzwl 4(rPC),%eax # eax<- FEDC or CCCC
- movzwl 2(rPC),%ecx # ecx<- BBBB
- .if (!1)
- andl $0xf,%eax # eax<- C (or stays CCCC)
- .endif
- GET_VREG_R %eax %eax # eax<- vC ("this" ptr)
- testl %eax,%eax # null?
- je common_errNullObject # yep, throw exception
- movl offObject_clazz(%eax),%eax # eax<- thisPtr->clazz
- movl offClassObject_vtable(%eax),%eax # eax<- thisPtr->clazz->vtable
- EXPORT_PC # might throw later - get ready
- movl (%eax,%ecx,4),%eax # eax<- vtable[BBBB]
- jmp common_invokeMethodRange
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_INVOKE_SUPER_QUICK: /* 0xfa */
-/* File: x86/OP_INVOKE_SUPER_QUICK.S */
- /*
- * Handle an optimized "super" method call.
- *
- * for: [opt] invoke-super-quick, invoke-super-quick/range
- */
- /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
- /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
- movl rSELF,%ecx
- movzwl 4(rPC),%eax # eax<- GFED or CCCC
- movl offThread_method(%ecx),%ecx # ecx<- current method
- .if (!0)
- andl $0xf,%eax # eax<- D (or stays CCCC)
- .endif
- movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
- GET_VREG_R %eax %eax # eax<- "this"
- movl offClassObject_super(%ecx),%ecx # ecx<- method->clazz->super
- testl %eax,%eax # null "this"?
- je common_errNullObject # "this" is null, throw exception
- movzwl 2(rPC),%eax # eax<- BBBB
- movl offClassObject_vtable(%ecx),%ecx # ecx<- vtable
- EXPORT_PC
- movl (%ecx,%eax,4),%eax # eax<- super->vtable[BBBB]
- jmp common_invokeMethodNoRange
-
-/* ------------------------------ */
- .balign 64
-.L_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */
-/* File: x86/OP_INVOKE_SUPER_QUICK_RANGE.S */
-/* File: x86/OP_INVOKE_SUPER_QUICK.S */
- /*
- * Handle an optimized "super" method call.
- *
- * for: [opt] invoke-super-quick, invoke-super-quick/range
- */
- /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
- /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
- movl rSELF,%ecx
- movzwl 4(rPC),%eax # eax<- GFED or CCCC
- movl offThread_method(%ecx),%ecx # ecx<- current method
- .if (!1)
- andl $0xf,%eax # eax<- D (or stays CCCC)
- .endif
- movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
- GET_VREG_R %eax %eax # eax<- "this"
- movl offClassObject_super(%ecx),%ecx # ecx<- method->clazz->super
- testl %eax,%eax # null "this"?
- je common_errNullObject # "this" is null, throw exception
- movzwl 2(rPC),%eax # eax<- BBBB
- movl offClassObject_vtable(%ecx),%ecx # ecx<- vtable
- EXPORT_PC
- movl (%ecx,%eax,4),%eax # eax<- super->vtable[BBBB]
- jmp common_invokeMethodRange
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */
-/* File: x86/OP_IPUT_OBJECT_VOLATILE.S */
-/* File: x86/OP_IPUT_OBJECT.S */
- /*
- * Object field put.
- *
- * for: iput-object
- */
- /* op vA, vB, field@CCCC */
- movl rSELF,%ecx
- movzwl 2(rPC),%edx # edx<- 0000CCCC
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzbl rINSTbl,%ecx # ecx<- BA
- sarl $4,%ecx # ecx<- B
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- andb $0xf,rINSTbl # rINST<- A
- GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IPUT_OBJECT_VOLATILE_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp)
- movl rSELF,%edx
- jmp .LOP_IPUT_OBJECT_VOLATILE_resolve
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SGET_OBJECT_VOLATILE: /* 0xfd */
-/* File: x86/OP_SGET_OBJECT_VOLATILE.S */
-/* File: x86/OP_SGET.S */
- /*
- * General 32-bit SGET handler.
- *
- * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
- */
- /* op vAA, field@BBBB */
- movl rSELF,%ecx
- movzwl 2(rPC),%eax # eax<- field ref BBBB
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SGET_OBJECT_VOLATILE_resolve # if not, make it so
-.LOP_SGET_OBJECT_VOLATILE_finish: # field ptr in eax
- movl offStaticField_value(%eax),%eax
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- SET_VREG %eax rINST
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */
-/* File: x86/OP_SPUT_OBJECT_VOLATILE.S */
-/* File: x86/OP_SPUT_OBJECT.S */
- /*
- * SPUT object handler.
- */
- /* op vAA, field@BBBB */
- movl rSELF,%ecx
- movzwl 2(rPC),%eax # eax<- field ref BBBB
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField
- testl %eax,%eax # resolved entry null?
- je .LOP_SPUT_OBJECT_VOLATILE_resolve # if not, make it so
-.LOP_SPUT_OBJECT_VOLATILE_finish: # field ptr in eax
- movzbl rINSTbl,%ecx # ecx<- AA
- GET_VREG_R %ecx %ecx
- jmp .LOP_SPUT_OBJECT_VOLATILE_continue
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_DISPATCH_FF: /* 0xff */
-/* File: x86/OP_DISPATCH_FF.S */
- leal 256(rINST),%edx
- GOTO_NEXT_JUMBO_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_CONST_CLASS_JUMBO: /* 0x100 */
-/* File: x86/OP_CONST_CLASS_JUMBO.S */
- /* const-class/jumbo vBBBB, Class@AAAAAAAA */
- movl rSELF,%ecx
- movl 2(rPC),%eax # eax<- AAAAAAAA
- movl offThread_methodClassDex(%ecx),%ecx# ecx<- self->methodClassDex
- movl offDvmDex_pResClasses(%ecx),%ecx # ecx<- dvmDex->pResClasses
- movl (%ecx,%eax,4),%eax # eax<- rResClasses[AAAAAAAA]
- FETCH_INST_OPCODE 4 %edx
- testl %eax,%eax # resolved yet?
- je .LOP_CONST_CLASS_JUMBO_resolve
- SET_VREG %eax rINST # vBBBB<- rResClasses[AAAAAAAA]
- ADVANCE_PC 4
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_CHECK_CAST_JUMBO: /* 0x101 */
-/* File: x86/OP_CHECK_CAST_JUMBO.S */
- /*
- * Check to see if a cast from one class to another is allowed.
- */
- /* check-cast/jumbo vBBBB, class@AAAAAAAA */
- movl rSELF,%ecx
- GET_VREG_R rINST,rINST # rINST<- vBBBB (object)
- movl 2(rPC),%eax # eax<- AAAAAAAA
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
- testl rINST,rINST # is oject null?
- movl offDvmDex_pResClasses(%ecx),%ecx # ecx<- pDvmDex->pResClasses
- je .LOP_CHECK_CAST_JUMBO_okay # null obj, cast always succeeds
- movl (%ecx,%eax,4),%eax # eax<- resolved class
- movl offObject_clazz(rINST),%ecx # ecx<- obj->clazz
- testl %eax,%eax # have we resolved this before?
- je .LOP_CHECK_CAST_JUMBO_resolve # no, go do it now
-.LOP_CHECK_CAST_JUMBO_resolved:
- cmpl %eax,%ecx # same class (trivial success)?
- jne .LOP_CHECK_CAST_JUMBO_fullcheck # no, do full check
-.LOP_CHECK_CAST_JUMBO_okay:
- FETCH_INST_OPCODE 4 %edx
- ADVANCE_PC 4
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_INSTANCE_OF_JUMBO: /* 0x102 */
-/* File: x86/OP_INSTANCE_OF_JUMBO.S */
- /*
- * Check to see if an object reference is an instance of a class.
- *
- * Most common situation is a non-null object, being compared against
- * an already-resolved class.
- */
- /* instance-of/jumbo vBBBB, vCCCC, class@AAAAAAAA */
- movzwl 8(rPC),%eax # eax<- CCCC
- GET_VREG_R %eax %eax # eax<- vCCCC (obj)
- movl rSELF,%ecx
- testl %eax,%eax # object null?
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
- je .LOP_INSTANCE_OF_JUMBO_store # null obj, not instance, store it
- movl 2(rPC),%edx # edx<- AAAAAAAA
- movl offDvmDex_pResClasses(%ecx),%ecx # ecx<- pDvmDex->pResClasses
- movl (%ecx,%edx,4),%ecx # ecx<- resolved class
- movl offObject_clazz(%eax),%eax # eax<- obj->clazz
- testl %ecx,%ecx # have we resolved this before?
- je .LOP_INSTANCE_OF_JUMBO_resolve # not resolved, do it now
-.LOP_INSTANCE_OF_JUMBO_resolved: # eax<- obj->clazz, ecx<- resolved class
- cmpl %eax,%ecx # same class (trivial success)?
- je .LOP_INSTANCE_OF_JUMBO_trivial # yes, trivial finish
- jmp .LOP_INSTANCE_OF_JUMBO_fullcheck # no, do full check
-
-/* ------------------------------ */
- .balign 64
-.L_OP_NEW_INSTANCE_JUMBO: /* 0x103 */
-/* File: x86/OP_NEW_INSTANCE_JUMBO.S */
- /*
- * Create a new instance of a class.
- */
- /* new-instance/jumbo vBBBB, class@AAAAAAAA */
- movl rSELF,%ecx
- movl 2(rPC),%eax # eax<- AAAAAAAA
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
- movl offDvmDex_pResClasses(%ecx),%ecx # ecx<- pDvmDex->pResClasses
- EXPORT_PC
- movl (%ecx,%eax,4),%ecx # ecx<- resolved class
- testl %ecx,%ecx # resolved?
- je .LOP_NEW_INSTANCE_JUMBO_resolve # no, go do it
-.LOP_NEW_INSTANCE_JUMBO_resolved: # on entry, ecx<- class
- cmpb $CLASS_INITIALIZED,offClassObject_status(%ecx)
- je .LOP_NEW_INSTANCE_JUMBO_initialized
- jmp .LOP_NEW_INSTANCE_JUMBO_needinit
-
-/* ------------------------------ */
- .balign 64
-.L_OP_NEW_ARRAY_JUMBO: /* 0x104 */
-/* File: x86/OP_NEW_ARRAY_JUMBO.S */
- /*
- * Allocate an array of objects, specified with the array class
- * and a count.
- *
- * The verifier guarantees that this is an array class, so we don't
- * check for it here.
- */
- /* new-array/jumbo vBBBB, vCCCC, class@AAAAAAAA */
- movl rSELF,%ecx
- EXPORT_PC
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
- movl 2(rPC),%eax # eax<- AAAAAAAA
- movl offDvmDex_pResClasses(%ecx),%ecx # ecx<- pDvmDex->pResClasses
- movl (%ecx,%eax,4),%ecx # ecx<- resolved class
- movzwl 8(rPC),%eax # eax<- CCCC
- GET_VREG_R %eax %eax # eax<- vCCCC (array length)
- testl %eax,%eax
- js common_errNegativeArraySize # bail, passing len in eax
- testl %ecx,%ecx # already resolved?
- jne .LOP_NEW_ARRAY_JUMBO_finish # yes, fast path
- jmp .LOP_NEW_ARRAY_JUMBO_resolve # resolve now
-
-/* ------------------------------ */
- .balign 64
-.L_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */
-/* File: x86/OP_FILLED_NEW_ARRAY_JUMBO.S */
- /*
- * Create a new array with elements filled from registers.
- */
- /* filled-new-array/jumbo {vCCCC..v(CCCC+BBBB-1)}, type@AAAAAAAA */
- movl rSELF,%eax
- movl offThread_methodClassDex(%eax),%eax # eax<- pDvmDex
- movl 2(rPC),%ecx # ecx<- AAAAAAAA
- movl offDvmDex_pResClasses(%eax),%eax # eax<- pDvmDex->pResClasses
- movl (%eax,%ecx,4),%eax # eax<- resolved class
- EXPORT_PC
- testl %eax,%eax # already resolved?
- jne .LOP_FILLED_NEW_ARRAY_JUMBO_continue # yes, continue
- # less frequent path, so we'll redo some work
- movl rSELF,%eax
- movl $0,OUT_ARG2(%esp) # arg2<- false
- movl %ecx,OUT_ARG1(%esp) # arg1<- AAAAAAAA
- movl offThread_method(%eax),%eax # eax<- self->method
- jmp .LOP_FILLED_NEW_ARRAY_JUMBO_more
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IGET_JUMBO: /* 0x106 */
-/* File: x86/OP_IGET_JUMBO.S */
- /*
- * Jumbo 32-bit instance field get.
- *
- * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
- * iget-char/jumbo, iget-short/jumbo
- */
- /* exop vBBBB, vCCCC, field@AAAAAAAA */
- movl rSELF,%ecx
- movl 2(rPC),%edx # edx<- AAAAAAAA
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzwl 8(rPC),%ecx # ecx<- CCCC
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IGET_JUMBO_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp) # needed by dvmResolveInstField
- movl rSELF,%edx
- jmp .LOP_IGET_JUMBO_resolve
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IGET_WIDE_JUMBO: /* 0x107 */
-/* File: x86/OP_IGET_WIDE_JUMBO.S */
- /*
- * Jumbo 64-bit instance field get.
- */
- /* iget-wide/jumbo vBBBB, vCCCC, field@AAAA */
- movl rSELF,%ecx
- movl 2(rPC),%edx # edx<- AAAAAAAA
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzwl 8(rPC),%ecx # ecx<- CCCC
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IGET_WIDE_JUMBO_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp) # for dvmResolveInstField
- movl rSELF,%edx
- jmp .LOP_IGET_WIDE_JUMBO_resolve
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IGET_OBJECT_JUMBO: /* 0x108 */
-/* File: x86/OP_IGET_OBJECT_JUMBO.S */
-/* File: x86/OP_IGET_JUMBO.S */
- /*
- * Jumbo 32-bit instance field get.
- *
- * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
- * iget-char/jumbo, iget-short/jumbo
- */
- /* exop vBBBB, vCCCC, field@AAAAAAAA */
- movl rSELF,%ecx
- movl 2(rPC),%edx # edx<- AAAAAAAA
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzwl 8(rPC),%ecx # ecx<- CCCC
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IGET_OBJECT_JUMBO_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp) # needed by dvmResolveInstField
- movl rSELF,%edx
- jmp .LOP_IGET_OBJECT_JUMBO_resolve
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */
-/* File: x86/OP_IGET_BOOLEAN_JUMBO.S */
-/* File: x86/OP_IGET_JUMBO.S */
- /*
- * Jumbo 32-bit instance field get.
- *
- * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
- * iget-char/jumbo, iget-short/jumbo
- */
- /* exop vBBBB, vCCCC, field@AAAAAAAA */
- movl rSELF,%ecx
- movl 2(rPC),%edx # edx<- AAAAAAAA
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzwl 8(rPC),%ecx # ecx<- CCCC
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IGET_BOOLEAN_JUMBO_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp) # needed by dvmResolveInstField
- movl rSELF,%edx
- jmp .LOP_IGET_BOOLEAN_JUMBO_resolve
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IGET_BYTE_JUMBO: /* 0x10a */
-/* File: x86/OP_IGET_BYTE_JUMBO.S */
-/* File: x86/OP_IGET_JUMBO.S */
- /*
- * Jumbo 32-bit instance field get.
- *
- * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
- * iget-char/jumbo, iget-short/jumbo
- */
- /* exop vBBBB, vCCCC, field@AAAAAAAA */
- movl rSELF,%ecx
- movl 2(rPC),%edx # edx<- AAAAAAAA
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzwl 8(rPC),%ecx # ecx<- CCCC
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IGET_BYTE_JUMBO_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp) # needed by dvmResolveInstField
- movl rSELF,%edx
- jmp .LOP_IGET_BYTE_JUMBO_resolve
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IGET_CHAR_JUMBO: /* 0x10b */
-/* File: x86/OP_IGET_CHAR_JUMBO.S */
-/* File: x86/OP_IGET_JUMBO.S */
- /*
- * Jumbo 32-bit instance field get.
- *
- * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
- * iget-char/jumbo, iget-short/jumbo
- */
- /* exop vBBBB, vCCCC, field@AAAAAAAA */
- movl rSELF,%ecx
- movl 2(rPC),%edx # edx<- AAAAAAAA
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzwl 8(rPC),%ecx # ecx<- CCCC
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IGET_CHAR_JUMBO_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp) # needed by dvmResolveInstField
- movl rSELF,%edx
- jmp .LOP_IGET_CHAR_JUMBO_resolve
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IGET_SHORT_JUMBO: /* 0x10c */
-/* File: x86/OP_IGET_SHORT_JUMBO.S */
-/* File: x86/OP_IGET_JUMBO.S */
- /*
- * Jumbo 32-bit instance field get.
- *
- * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
- * iget-char/jumbo, iget-short/jumbo
- */
- /* exop vBBBB, vCCCC, field@AAAAAAAA */
- movl rSELF,%ecx
- movl 2(rPC),%edx # edx<- AAAAAAAA
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzwl 8(rPC),%ecx # ecx<- CCCC
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IGET_SHORT_JUMBO_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp) # needed by dvmResolveInstField
- movl rSELF,%edx
- jmp .LOP_IGET_SHORT_JUMBO_resolve
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IPUT_JUMBO: /* 0x10d */
-/* File: x86/OP_IPUT_JUMBO.S */
- /*
- * Jumbo 32-bit instance field put.
- *
- * for: iput/jumbo, iput-object/jumbo, iput-boolean/jumbo, iput-byte/jumbo,
- iput-char/jumbo, iput-short/jumbo
- */
- /* exop vBBBB, vCCCC, field@AAAAAAAA */
- movl rSELF,%ecx
- movl 2(rPC),%edx # edx<- AAAAAAAA
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzwl 8(rPC),%ecx # ecx<- CCCC
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IPUT_JUMBO_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp)
- movl rSELF,%edx
- jmp .LOP_IPUT_JUMBO_resolve
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IPUT_WIDE_JUMBO: /* 0x10e */
-/* File: x86/OP_IPUT_WIDE_JUMBO.S */
- /*
- * Jumbo 64-bit instance field put.
- */
- /* iput-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */
- movl rSELF,%ecx
- movl 2(rPC),%edx # edx<- AAAAAAAA
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzwl 8(rPC),%ecx # ecx<- CCCC
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IPUT_WIDE_JUMBO_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp)
- movl rSELF,%edx
- jmp .LOP_IPUT_WIDE_JUMBO_resolve
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IPUT_OBJECT_JUMBO: /* 0x10f */
-/* File: x86/OP_IPUT_OBJECT_JUMBO.S */
- /*
- * Jumbo object field put.
- */
- /* iput-object/jumbo vBBBB, vCCCC, field@AAAAAAAA */
- movl rSELF,%ecx
- movl 2(rPC),%edx # edx<- AAAAAAAA
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzwl 8(rPC),%ecx # ecx<- CCCC
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IPUT_OBJECT_JUMBO_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp)
- movl rSELF,%edx
- jmp .LOP_IPUT_OBJECT_JUMBO_resolve
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */
-/* File: x86/OP_IPUT_BOOLEAN_JUMBO.S */
-/* File: x86/OP_IPUT_JUMBO.S */
- /*
- * Jumbo 32-bit instance field put.
- *
- * for: iput/jumbo, iput-object/jumbo, iput-boolean/jumbo, iput-byte/jumbo,
- iput-char/jumbo, iput-short/jumbo
- */
- /* exop vBBBB, vCCCC, field@AAAAAAAA */
- movl rSELF,%ecx
- movl 2(rPC),%edx # edx<- AAAAAAAA
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzwl 8(rPC),%ecx # ecx<- CCCC
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IPUT_BOOLEAN_JUMBO_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp)
- movl rSELF,%edx
- jmp .LOP_IPUT_BOOLEAN_JUMBO_resolve
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IPUT_BYTE_JUMBO: /* 0x111 */
-/* File: x86/OP_IPUT_BYTE_JUMBO.S */
-/* File: x86/OP_IPUT_JUMBO.S */
- /*
- * Jumbo 32-bit instance field put.
- *
- * for: iput/jumbo, iput-object/jumbo, iput-boolean/jumbo, iput-byte/jumbo,
- iput-char/jumbo, iput-short/jumbo
- */
- /* exop vBBBB, vCCCC, field@AAAAAAAA */
- movl rSELF,%ecx
- movl 2(rPC),%edx # edx<- AAAAAAAA
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzwl 8(rPC),%ecx # ecx<- CCCC
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IPUT_BYTE_JUMBO_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp)
- movl rSELF,%edx
- jmp .LOP_IPUT_BYTE_JUMBO_resolve
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IPUT_CHAR_JUMBO: /* 0x112 */
-/* File: x86/OP_IPUT_CHAR_JUMBO.S */
-/* File: x86/OP_IPUT_JUMBO.S */
- /*
- * Jumbo 32-bit instance field put.
- *
- * for: iput/jumbo, iput-object/jumbo, iput-boolean/jumbo, iput-byte/jumbo,
- iput-char/jumbo, iput-short/jumbo
- */
- /* exop vBBBB, vCCCC, field@AAAAAAAA */
- movl rSELF,%ecx
- movl 2(rPC),%edx # edx<- AAAAAAAA
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzwl 8(rPC),%ecx # ecx<- CCCC
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IPUT_CHAR_JUMBO_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp)
- movl rSELF,%edx
- jmp .LOP_IPUT_CHAR_JUMBO_resolve
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_IPUT_SHORT_JUMBO: /* 0x113 */
-/* File: x86/OP_IPUT_SHORT_JUMBO.S */
-/* File: x86/OP_IPUT_JUMBO.S */
- /*
- * Jumbo 32-bit instance field put.
- *
- * for: iput/jumbo, iput-object/jumbo, iput-boolean/jumbo, iput-byte/jumbo,
- iput-char/jumbo, iput-short/jumbo
- */
- /* exop vBBBB, vCCCC, field@AAAAAAAA */
- movl rSELF,%ecx
- movl 2(rPC),%edx # edx<- AAAAAAAA
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
- movzwl 8(rPC),%ecx # ecx<- CCCC
- movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
- GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
- testl %eax,%eax # is resolved entry null?
- jne .LOP_IPUT_SHORT_JUMBO_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp)
- movl rSELF,%edx
- jmp .LOP_IPUT_SHORT_JUMBO_resolve
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SGET_JUMBO: /* 0x114 */
-/* File: x86/OP_SGET_JUMBO.S */
- /*
- * Jumbo 32-bit SGET handler.
- *
- * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
- * sget-char/jumbo, sget-short/jumbo
- */
- /* exop vBBBB, field@AAAAAAAA */
- movl rSELF,%ecx
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl 2(rPC),%eax # eax<- field ref AAAAAAAA
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SGET_JUMBO_resolve # if not, make it so
-.LOP_SGET_JUMBO_finish: # field ptr in eax
- movl offStaticField_value(%eax),%eax
- FETCH_INST_OPCODE 4 %edx
- ADVANCE_PC 4
- SET_VREG %eax rINST
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SGET_WIDE_JUMBO: /* 0x115 */
-/* File: x86/OP_SGET_WIDE_JUMBO.S */
- /*
- * Jumbo 64-bit SGET handler.
- *
- */
- /* sget-wide/jumbo vBBBB, field@AAAAAAAA */
- movl rSELF,%ecx
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl 2(rPC),%eax # eax<- field ref AAAAAAAA
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SGET_WIDE_JUMBO_resolve # if not, make it so
-.LOP_SGET_WIDE_JUMBO_finish: # field ptr in eax
- movl offStaticField_value(%eax),%ecx # ecx<- lsw
- movl 4+offStaticField_value(%eax),%eax # eax<- msw
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- SET_VREG_WORD %ecx rINST 0
- SET_VREG_WORD %eax rINST 1
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SGET_OBJECT_JUMBO: /* 0x116 */
-/* File: x86/OP_SGET_OBJECT_JUMBO.S */
-/* File: x86/OP_SGET_JUMBO.S */
- /*
- * Jumbo 32-bit SGET handler.
- *
- * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
- * sget-char/jumbo, sget-short/jumbo
- */
- /* exop vBBBB, field@AAAAAAAA */
- movl rSELF,%ecx
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl 2(rPC),%eax # eax<- field ref AAAAAAAA
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SGET_OBJECT_JUMBO_resolve # if not, make it so
-.LOP_SGET_OBJECT_JUMBO_finish: # field ptr in eax
- movl offStaticField_value(%eax),%eax
- FETCH_INST_OPCODE 4 %edx
- ADVANCE_PC 4
- SET_VREG %eax rINST
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */
-/* File: x86/OP_SGET_BOOLEAN_JUMBO.S */
-/* File: x86/OP_SGET_JUMBO.S */
- /*
- * Jumbo 32-bit SGET handler.
- *
- * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
- * sget-char/jumbo, sget-short/jumbo
- */
- /* exop vBBBB, field@AAAAAAAA */
- movl rSELF,%ecx
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl 2(rPC),%eax # eax<- field ref AAAAAAAA
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SGET_BOOLEAN_JUMBO_resolve # if not, make it so
-.LOP_SGET_BOOLEAN_JUMBO_finish: # field ptr in eax
- movl offStaticField_value(%eax),%eax
- FETCH_INST_OPCODE 4 %edx
- ADVANCE_PC 4
- SET_VREG %eax rINST
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SGET_BYTE_JUMBO: /* 0x118 */
-/* File: x86/OP_SGET_BYTE_JUMBO.S */
-/* File: x86/OP_SGET_JUMBO.S */
- /*
- * Jumbo 32-bit SGET handler.
- *
- * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
- * sget-char/jumbo, sget-short/jumbo
- */
- /* exop vBBBB, field@AAAAAAAA */
- movl rSELF,%ecx
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl 2(rPC),%eax # eax<- field ref AAAAAAAA
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SGET_BYTE_JUMBO_resolve # if not, make it so
-.LOP_SGET_BYTE_JUMBO_finish: # field ptr in eax
- movl offStaticField_value(%eax),%eax
- FETCH_INST_OPCODE 4 %edx
- ADVANCE_PC 4
- SET_VREG %eax rINST
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SGET_CHAR_JUMBO: /* 0x119 */
-/* File: x86/OP_SGET_CHAR_JUMBO.S */
-/* File: x86/OP_SGET_JUMBO.S */
- /*
- * Jumbo 32-bit SGET handler.
- *
- * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
- * sget-char/jumbo, sget-short/jumbo
- */
- /* exop vBBBB, field@AAAAAAAA */
- movl rSELF,%ecx
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl 2(rPC),%eax # eax<- field ref AAAAAAAA
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SGET_CHAR_JUMBO_resolve # if not, make it so
-.LOP_SGET_CHAR_JUMBO_finish: # field ptr in eax
- movl offStaticField_value(%eax),%eax
- FETCH_INST_OPCODE 4 %edx
- ADVANCE_PC 4
- SET_VREG %eax rINST
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SGET_SHORT_JUMBO: /* 0x11a */
-/* File: x86/OP_SGET_SHORT_JUMBO.S */
-/* File: x86/OP_SGET_JUMBO.S */
- /*
- * Jumbo 32-bit SGET handler.
- *
- * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
- * sget-char/jumbo, sget-short/jumbo
- */
- /* exop vBBBB, field@AAAAAAAA */
- movl rSELF,%ecx
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl 2(rPC),%eax # eax<- field ref AAAAAAAA
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SGET_SHORT_JUMBO_resolve # if not, make it so
-.LOP_SGET_SHORT_JUMBO_finish: # field ptr in eax
- movl offStaticField_value(%eax),%eax
- FETCH_INST_OPCODE 4 %edx
- ADVANCE_PC 4
- SET_VREG %eax rINST
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SPUT_JUMBO: /* 0x11b */
-/* File: x86/OP_SPUT_JUMBO.S */
- /*
- * Jumbo 32-bit SPUT handler.
- *
- * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
- * sput-short/jumbo
- */
- /* exop vBBBB, field@AAAAAAAA */
- movl rSELF,%ecx
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl 2(rPC),%eax # eax<- field ref AAAAAAAA
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SPUT_JUMBO_resolve # if not, make it so
-.LOP_SPUT_JUMBO_finish: # field ptr in eax
- GET_VREG_R %ecx rINST
- FETCH_INST_OPCODE 4 %edx
- ADVANCE_PC 4
- movl %ecx,offStaticField_value(%eax)
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SPUT_WIDE_JUMBO: /* 0x11c */
-/* File: x86/OP_SPUT_WIDE_JUMBO.S */
- /*
- * Jumbo 64-bit SPUT handler.
- */
- /* sput-wide/jumbo vBBBB, field@AAAAAAAA */
- movl rSELF,%ecx
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl 2(rPC),%eax # eax<- field ref AAAAAAAA
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SPUT_WIDE_JUMBO_resolve # if not, make it so
-.LOP_SPUT_WIDE_JUMBO_finish: # field ptr in eax
- GET_VREG_WORD %ecx rINST 0 # ecx<- lsw
- GET_VREG_WORD rINST rINST 1 # rINST<- msw
- FETCH_INST_OPCODE 4 %edx
- ADVANCE_PC 4
- movl %ecx,offStaticField_value(%eax)
- movl rINST,4+offStaticField_value(%eax)
- GOTO_NEXT_R %edx
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SPUT_OBJECT_JUMBO: /* 0x11d */
-/* File: x86/OP_SPUT_OBJECT_JUMBO.S */
- /*
- * Jumbo SPUT object handler.
- */
- /* sput-object/jumbo vBBBB, field@AAAAAAAA */
- movl rSELF,%ecx
- movl 2(rPC),%eax # eax<- field ref AAAAAAAA
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField
- testl %eax,%eax # resolved entry null?
- je .LOP_SPUT_OBJECT_JUMBO_resolve # if not, make it so
-.LOP_SPUT_OBJECT_JUMBO_finish: # field ptr in eax
- GET_VREG_R %ecx rINST
- jmp .LOP_SPUT_OBJECT_JUMBO_continue
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */
-/* File: x86/OP_SPUT_BOOLEAN_JUMBO.S */
-/* File: x86/OP_SPUT_JUMBO.S */
- /*
- * Jumbo 32-bit SPUT handler.
- *
- * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
- * sput-short/jumbo
- */
- /* exop vBBBB, field@AAAAAAAA */
- movl rSELF,%ecx
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl 2(rPC),%eax # eax<- field ref AAAAAAAA
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SPUT_BOOLEAN_JUMBO_resolve # if not, make it so
-.LOP_SPUT_BOOLEAN_JUMBO_finish: # field ptr in eax
- GET_VREG_R %ecx rINST
- FETCH_INST_OPCODE 4 %edx
- ADVANCE_PC 4
- movl %ecx,offStaticField_value(%eax)
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SPUT_BYTE_JUMBO: /* 0x11f */
-/* File: x86/OP_SPUT_BYTE_JUMBO.S */
-/* File: x86/OP_SPUT_JUMBO.S */
- /*
- * Jumbo 32-bit SPUT handler.
- *
- * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
- * sput-short/jumbo
- */
- /* exop vBBBB, field@AAAAAAAA */
- movl rSELF,%ecx
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl 2(rPC),%eax # eax<- field ref AAAAAAAA
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SPUT_BYTE_JUMBO_resolve # if not, make it so
-.LOP_SPUT_BYTE_JUMBO_finish: # field ptr in eax
- GET_VREG_R %ecx rINST
- FETCH_INST_OPCODE 4 %edx
- ADVANCE_PC 4
- movl %ecx,offStaticField_value(%eax)
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SPUT_CHAR_JUMBO: /* 0x120 */
-/* File: x86/OP_SPUT_CHAR_JUMBO.S */
-/* File: x86/OP_SPUT_JUMBO.S */
- /*
- * Jumbo 32-bit SPUT handler.
- *
- * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
- * sput-short/jumbo
- */
- /* exop vBBBB, field@AAAAAAAA */
- movl rSELF,%ecx
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl 2(rPC),%eax # eax<- field ref AAAAAAAA
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SPUT_CHAR_JUMBO_resolve # if not, make it so
-.LOP_SPUT_CHAR_JUMBO_finish: # field ptr in eax
- GET_VREG_R %ecx rINST
- FETCH_INST_OPCODE 4 %edx
- ADVANCE_PC 4
- movl %ecx,offStaticField_value(%eax)
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_SPUT_SHORT_JUMBO: /* 0x121 */
-/* File: x86/OP_SPUT_SHORT_JUMBO.S */
-/* File: x86/OP_SPUT_JUMBO.S */
- /*
- * Jumbo 32-bit SPUT handler.
- *
- * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
- * sput-short/jumbo
- */
- /* exop vBBBB, field@AAAAAAAA */
- movl rSELF,%ecx
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
- movl 2(rPC),%eax # eax<- field ref AAAAAAAA
- movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
- movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
- testl %eax,%eax # resolved entry null?
- je .LOP_SPUT_SHORT_JUMBO_resolve # if not, make it so
-.LOP_SPUT_SHORT_JUMBO_finish: # field ptr in eax
- GET_VREG_R %ecx rINST
- FETCH_INST_OPCODE 4 %edx
- ADVANCE_PC 4
- movl %ecx,offStaticField_value(%eax)
- GOTO_NEXT_R %edx
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */
-/* File: x86/OP_INVOKE_VIRTUAL_JUMBO.S */
- /*
- * Handle a jumbo virtual method call.
- */
- /* invoke-virtual/jumbo vBBBB, {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
- movl rSELF,%eax
- movl 2(rPC),%ecx # ecx<- AAAAAAAA
- movl offThread_methodClassDex(%eax),%eax # eax<- pDvmDex
- EXPORT_PC
- movl offDvmDex_pResMethods(%eax),%eax # eax<- pDvmDex->pResMethods
- movl (%eax,%ecx,4),%eax # eax<- resolved baseMethod
- testl %eax,%eax # already resolved?
- jne .LOP_INVOKE_VIRTUAL_JUMBO_continue # yes, continue
- movl rSELF,%eax
- movl %ecx,OUT_ARG1(%esp) # arg1<- ref
- movl offThread_method(%eax),%eax # eax<- self->method
- jmp .LOP_INVOKE_VIRTUAL_JUMBO_more
-
-/* ------------------------------ */
- .balign 64
-.L_OP_INVOKE_SUPER_JUMBO: /* 0x123 */
-/* File: x86/OP_INVOKE_SUPER_JUMBO.S */
- /*
- * Handle a jumbo "super" method call.
- */
- /* invoke-super/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
- movl rSELF,rINST
- movl 2(rPC),%eax # eax<- AAAAAAAA
- movl offThread_methodClassDex(rINST),%ecx # ecx<- pDvmDex
- EXPORT_PC
- movl offDvmDex_pResMethods(%ecx),%ecx # ecx<- pDvmDex->pResMethods
- movl (%ecx,%eax,4),%ecx # ecx<- resolved baseMethod
- movl offThread_method(rINST),%eax # eax<- method
- movzwl 8(rPC),rINST # rINST<- CCCC
- GET_VREG_R rINST rINST # rINST<- "this" ptr
- testl rINST,rINST # null "this"?
- je common_errNullObject # yes, throw
- movl offMethod_clazz(%eax),%eax # eax<- method->clazz
- testl %ecx,%ecx # already resolved?
- jne .LOP_INVOKE_SUPER_JUMBO_continue # yes - go on
- jmp .LOP_INVOKE_SUPER_JUMBO_resolve
-
-/* ------------------------------ */
- .balign 64
-.L_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */
-/* File: x86/OP_INVOKE_DIRECT_JUMBO.S */
- /*
- * Handle a jumbo direct method call.
- *
- * (We could defer the "is 'this' pointer null" test to the common
- * method invocation code, and use a flag to indicate that static
- * calls don't count. If we do this as part of copying the arguments
- * out we could avoiding loading the first arg twice.)
- */
- /* invoke-direct/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
- movl rSELF,%ecx
- movl 2(rPC),%eax # eax<- AAAAAAAA
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
- EXPORT_PC
- movl offDvmDex_pResMethods(%ecx),%ecx # ecx<- pDvmDex->pResMethods
- movzwl 8(rPC),%edx # edx<- CCCC
- movl (%ecx,%eax,4),%eax # eax<- resolved methodToCall
- testl %eax,%eax # already resolved?
- GET_VREG_R %ecx %edx # ecx<- "this" ptr
- je .LOP_INVOKE_DIRECT_JUMBO_resolve # not resolved, do it now
-.LOP_INVOKE_DIRECT_JUMBO_finish:
- testl %ecx,%ecx # null "this"?
- jne common_invokeMethodJumbo # no, continue on
- jmp common_errNullObject
-
-/* ------------------------------ */
- .balign 64
-.L_OP_INVOKE_STATIC_JUMBO: /* 0x125 */
-/* File: x86/OP_INVOKE_STATIC_JUMBO.S */
- /*
- * Handle a jumbo static method call.
- */
- /* invoke-static/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
- movl rSELF,%ecx
- movl 2(rPC),%eax # eax<- AAAAAAAA
- movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
- EXPORT_PC
- movl offDvmDex_pResMethods(%ecx),%ecx # ecx<- pDvmDex->pResMethods
- movl (%ecx,%eax,4),%eax # eax<- resolved methodToCall
- testl %eax,%eax
- jne common_invokeMethodJumbo
- movl rSELF,%ecx
- movl offThread_method(%ecx),%ecx # ecx<- self->method
- movl 2(rPC),%eax # eax<- AAAAAAAA
- movl offMethod_clazz(%ecx),%ecx# ecx<- method->clazz
- movl %eax,OUT_ARG1(%esp) # arg1<- AAAAAAAA
- movl %ecx,OUT_ARG0(%esp) # arg0<- clazz
- jmp .LOP_INVOKE_STATIC_JUMBO_continue
-
-/* ------------------------------ */
- .balign 64
-.L_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */
-/* File: x86/OP_INVOKE_INTERFACE_JUMBO.S */
- /*
- * Handle a jumbo interface method call.
- */
- /* invoke-interface/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
- movzwl 8(rPC),%eax # eax<- CCCC
- movl rSELF,%ecx
- GET_VREG_R %eax %eax # eax<- "this"
- EXPORT_PC
- testl %eax,%eax # null this?
- je common_errNullObject # yes, fail
- movl offObject_clazz(%eax),%eax# eax<- thisPtr->clazz
- movl %eax,OUT_ARG0(%esp) # arg0<- class
- movl offThread_methodClassDex(%ecx),%eax # eax<- methodClassDex
- movl offThread_method(%ecx),%ecx # ecx<- method
- movl %eax,OUT_ARG3(%esp) # arg3<- dex
- movl 2(rPC),%eax # eax<- AAAAAAAA
- movl %ecx,OUT_ARG2(%esp) # arg2<- method
- movl %eax,OUT_ARG1(%esp) # arg1<- AAAAAAAA
- jmp .LOP_INVOKE_INTERFACE_JUMBO_continue
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_27FF: /* 0x127 */
-/* File: x86/OP_UNUSED_27FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_28FF: /* 0x128 */
-/* File: x86/OP_UNUSED_28FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_29FF: /* 0x129 */
-/* File: x86/OP_UNUSED_29FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_2AFF: /* 0x12a */
-/* File: x86/OP_UNUSED_2AFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_2BFF: /* 0x12b */
-/* File: x86/OP_UNUSED_2BFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_2CFF: /* 0x12c */
-/* File: x86/OP_UNUSED_2CFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_2DFF: /* 0x12d */
-/* File: x86/OP_UNUSED_2DFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_2EFF: /* 0x12e */
-/* File: x86/OP_UNUSED_2EFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_2FFF: /* 0x12f */
-/* File: x86/OP_UNUSED_2FFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_30FF: /* 0x130 */
-/* File: x86/OP_UNUSED_30FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_31FF: /* 0x131 */
-/* File: x86/OP_UNUSED_31FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_32FF: /* 0x132 */
-/* File: x86/OP_UNUSED_32FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_33FF: /* 0x133 */
-/* File: x86/OP_UNUSED_33FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_34FF: /* 0x134 */
-/* File: x86/OP_UNUSED_34FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_35FF: /* 0x135 */
-/* File: x86/OP_UNUSED_35FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_36FF: /* 0x136 */
-/* File: x86/OP_UNUSED_36FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_37FF: /* 0x137 */
-/* File: x86/OP_UNUSED_37FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_38FF: /* 0x138 */
-/* File: x86/OP_UNUSED_38FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_39FF: /* 0x139 */
-/* File: x86/OP_UNUSED_39FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_3AFF: /* 0x13a */
-/* File: x86/OP_UNUSED_3AFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_3BFF: /* 0x13b */
-/* File: x86/OP_UNUSED_3BFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_3CFF: /* 0x13c */
-/* File: x86/OP_UNUSED_3CFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_3DFF: /* 0x13d */
-/* File: x86/OP_UNUSED_3DFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_3EFF: /* 0x13e */
-/* File: x86/OP_UNUSED_3EFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_3FFF: /* 0x13f */
-/* File: x86/OP_UNUSED_3FFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_40FF: /* 0x140 */
-/* File: x86/OP_UNUSED_40FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_41FF: /* 0x141 */
-/* File: x86/OP_UNUSED_41FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_42FF: /* 0x142 */
-/* File: x86/OP_UNUSED_42FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_43FF: /* 0x143 */
-/* File: x86/OP_UNUSED_43FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_44FF: /* 0x144 */
-/* File: x86/OP_UNUSED_44FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_45FF: /* 0x145 */
-/* File: x86/OP_UNUSED_45FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_46FF: /* 0x146 */
-/* File: x86/OP_UNUSED_46FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_47FF: /* 0x147 */
-/* File: x86/OP_UNUSED_47FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_48FF: /* 0x148 */
-/* File: x86/OP_UNUSED_48FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_49FF: /* 0x149 */
-/* File: x86/OP_UNUSED_49FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_4AFF: /* 0x14a */
-/* File: x86/OP_UNUSED_4AFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_4BFF: /* 0x14b */
-/* File: x86/OP_UNUSED_4BFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_4CFF: /* 0x14c */
-/* File: x86/OP_UNUSED_4CFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_4DFF: /* 0x14d */
-/* File: x86/OP_UNUSED_4DFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_4EFF: /* 0x14e */
-/* File: x86/OP_UNUSED_4EFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_4FFF: /* 0x14f */
-/* File: x86/OP_UNUSED_4FFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_50FF: /* 0x150 */
-/* File: x86/OP_UNUSED_50FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_51FF: /* 0x151 */
-/* File: x86/OP_UNUSED_51FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_52FF: /* 0x152 */
-/* File: x86/OP_UNUSED_52FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_53FF: /* 0x153 */
-/* File: x86/OP_UNUSED_53FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_54FF: /* 0x154 */
-/* File: x86/OP_UNUSED_54FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_55FF: /* 0x155 */
-/* File: x86/OP_UNUSED_55FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_56FF: /* 0x156 */
-/* File: x86/OP_UNUSED_56FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_57FF: /* 0x157 */
-/* File: x86/OP_UNUSED_57FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_58FF: /* 0x158 */
-/* File: x86/OP_UNUSED_58FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_59FF: /* 0x159 */
-/* File: x86/OP_UNUSED_59FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_5AFF: /* 0x15a */
-/* File: x86/OP_UNUSED_5AFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_5BFF: /* 0x15b */
-/* File: x86/OP_UNUSED_5BFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_5CFF: /* 0x15c */
-/* File: x86/OP_UNUSED_5CFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_5DFF: /* 0x15d */
-/* File: x86/OP_UNUSED_5DFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_5EFF: /* 0x15e */
-/* File: x86/OP_UNUSED_5EFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_5FFF: /* 0x15f */
-/* File: x86/OP_UNUSED_5FFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_60FF: /* 0x160 */
-/* File: x86/OP_UNUSED_60FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_61FF: /* 0x161 */
-/* File: x86/OP_UNUSED_61FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_62FF: /* 0x162 */
-/* File: x86/OP_UNUSED_62FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_63FF: /* 0x163 */
-/* File: x86/OP_UNUSED_63FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_64FF: /* 0x164 */
-/* File: x86/OP_UNUSED_64FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_65FF: /* 0x165 */
-/* File: x86/OP_UNUSED_65FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_66FF: /* 0x166 */
-/* File: x86/OP_UNUSED_66FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_67FF: /* 0x167 */
-/* File: x86/OP_UNUSED_67FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_68FF: /* 0x168 */
-/* File: x86/OP_UNUSED_68FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_69FF: /* 0x169 */
-/* File: x86/OP_UNUSED_69FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_6AFF: /* 0x16a */
-/* File: x86/OP_UNUSED_6AFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_6BFF: /* 0x16b */
-/* File: x86/OP_UNUSED_6BFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_6CFF: /* 0x16c */
-/* File: x86/OP_UNUSED_6CFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_6DFF: /* 0x16d */
-/* File: x86/OP_UNUSED_6DFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_6EFF: /* 0x16e */
-/* File: x86/OP_UNUSED_6EFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_6FFF: /* 0x16f */
-/* File: x86/OP_UNUSED_6FFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_70FF: /* 0x170 */
-/* File: x86/OP_UNUSED_70FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_71FF: /* 0x171 */
-/* File: x86/OP_UNUSED_71FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_72FF: /* 0x172 */
-/* File: x86/OP_UNUSED_72FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_73FF: /* 0x173 */
-/* File: x86/OP_UNUSED_73FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_74FF: /* 0x174 */
-/* File: x86/OP_UNUSED_74FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_75FF: /* 0x175 */
-/* File: x86/OP_UNUSED_75FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_76FF: /* 0x176 */
-/* File: x86/OP_UNUSED_76FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_77FF: /* 0x177 */
-/* File: x86/OP_UNUSED_77FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_78FF: /* 0x178 */
-/* File: x86/OP_UNUSED_78FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_79FF: /* 0x179 */
-/* File: x86/OP_UNUSED_79FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_7AFF: /* 0x17a */
-/* File: x86/OP_UNUSED_7AFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_7BFF: /* 0x17b */
-/* File: x86/OP_UNUSED_7BFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_7CFF: /* 0x17c */
-/* File: x86/OP_UNUSED_7CFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_7DFF: /* 0x17d */
-/* File: x86/OP_UNUSED_7DFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_7EFF: /* 0x17e */
-/* File: x86/OP_UNUSED_7EFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_7FFF: /* 0x17f */
-/* File: x86/OP_UNUSED_7FFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_80FF: /* 0x180 */
-/* File: x86/OP_UNUSED_80FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_81FF: /* 0x181 */
-/* File: x86/OP_UNUSED_81FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_82FF: /* 0x182 */
-/* File: x86/OP_UNUSED_82FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_83FF: /* 0x183 */
-/* File: x86/OP_UNUSED_83FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_84FF: /* 0x184 */
-/* File: x86/OP_UNUSED_84FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_85FF: /* 0x185 */
-/* File: x86/OP_UNUSED_85FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_86FF: /* 0x186 */
-/* File: x86/OP_UNUSED_86FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_87FF: /* 0x187 */
-/* File: x86/OP_UNUSED_87FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_88FF: /* 0x188 */
-/* File: x86/OP_UNUSED_88FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_89FF: /* 0x189 */
-/* File: x86/OP_UNUSED_89FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_8AFF: /* 0x18a */
-/* File: x86/OP_UNUSED_8AFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_8BFF: /* 0x18b */
-/* File: x86/OP_UNUSED_8BFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_8CFF: /* 0x18c */
-/* File: x86/OP_UNUSED_8CFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_8DFF: /* 0x18d */
-/* File: x86/OP_UNUSED_8DFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_8EFF: /* 0x18e */
-/* File: x86/OP_UNUSED_8EFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_8FFF: /* 0x18f */
-/* File: x86/OP_UNUSED_8FFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_90FF: /* 0x190 */
-/* File: x86/OP_UNUSED_90FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_91FF: /* 0x191 */
-/* File: x86/OP_UNUSED_91FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_92FF: /* 0x192 */
-/* File: x86/OP_UNUSED_92FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_93FF: /* 0x193 */
-/* File: x86/OP_UNUSED_93FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_94FF: /* 0x194 */
-/* File: x86/OP_UNUSED_94FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_95FF: /* 0x195 */
-/* File: x86/OP_UNUSED_95FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_96FF: /* 0x196 */
-/* File: x86/OP_UNUSED_96FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_97FF: /* 0x197 */
-/* File: x86/OP_UNUSED_97FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_98FF: /* 0x198 */
-/* File: x86/OP_UNUSED_98FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_99FF: /* 0x199 */
-/* File: x86/OP_UNUSED_99FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_9AFF: /* 0x19a */
-/* File: x86/OP_UNUSED_9AFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_9BFF: /* 0x19b */
-/* File: x86/OP_UNUSED_9BFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_9CFF: /* 0x19c */
-/* File: x86/OP_UNUSED_9CFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_9DFF: /* 0x19d */
-/* File: x86/OP_UNUSED_9DFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_9EFF: /* 0x19e */
-/* File: x86/OP_UNUSED_9EFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_9FFF: /* 0x19f */
-/* File: x86/OP_UNUSED_9FFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_A0FF: /* 0x1a0 */
-/* File: x86/OP_UNUSED_A0FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_A1FF: /* 0x1a1 */
-/* File: x86/OP_UNUSED_A1FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_A2FF: /* 0x1a2 */
-/* File: x86/OP_UNUSED_A2FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_A3FF: /* 0x1a3 */
-/* File: x86/OP_UNUSED_A3FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_A4FF: /* 0x1a4 */
-/* File: x86/OP_UNUSED_A4FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_A5FF: /* 0x1a5 */
-/* File: x86/OP_UNUSED_A5FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_A6FF: /* 0x1a6 */
-/* File: x86/OP_UNUSED_A6FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_A7FF: /* 0x1a7 */
-/* File: x86/OP_UNUSED_A7FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_A8FF: /* 0x1a8 */
-/* File: x86/OP_UNUSED_A8FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_A9FF: /* 0x1a9 */
-/* File: x86/OP_UNUSED_A9FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_AAFF: /* 0x1aa */
-/* File: x86/OP_UNUSED_AAFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_ABFF: /* 0x1ab */
-/* File: x86/OP_UNUSED_ABFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_ACFF: /* 0x1ac */
-/* File: x86/OP_UNUSED_ACFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_ADFF: /* 0x1ad */
-/* File: x86/OP_UNUSED_ADFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_AEFF: /* 0x1ae */
-/* File: x86/OP_UNUSED_AEFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_AFFF: /* 0x1af */
-/* File: x86/OP_UNUSED_AFFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_B0FF: /* 0x1b0 */
-/* File: x86/OP_UNUSED_B0FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_B1FF: /* 0x1b1 */
-/* File: x86/OP_UNUSED_B1FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_B2FF: /* 0x1b2 */
-/* File: x86/OP_UNUSED_B2FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_B3FF: /* 0x1b3 */
-/* File: x86/OP_UNUSED_B3FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_B4FF: /* 0x1b4 */
-/* File: x86/OP_UNUSED_B4FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_B5FF: /* 0x1b5 */
-/* File: x86/OP_UNUSED_B5FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_B6FF: /* 0x1b6 */
-/* File: x86/OP_UNUSED_B6FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_B7FF: /* 0x1b7 */
-/* File: x86/OP_UNUSED_B7FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_B8FF: /* 0x1b8 */
-/* File: x86/OP_UNUSED_B8FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_B9FF: /* 0x1b9 */
-/* File: x86/OP_UNUSED_B9FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_BAFF: /* 0x1ba */
-/* File: x86/OP_UNUSED_BAFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_BBFF: /* 0x1bb */
-/* File: x86/OP_UNUSED_BBFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_BCFF: /* 0x1bc */
-/* File: x86/OP_UNUSED_BCFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_BDFF: /* 0x1bd */
-/* File: x86/OP_UNUSED_BDFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_BEFF: /* 0x1be */
-/* File: x86/OP_UNUSED_BEFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_BFFF: /* 0x1bf */
-/* File: x86/OP_UNUSED_BFFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_C0FF: /* 0x1c0 */
-/* File: x86/OP_UNUSED_C0FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_C1FF: /* 0x1c1 */
-/* File: x86/OP_UNUSED_C1FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_C2FF: /* 0x1c2 */
-/* File: x86/OP_UNUSED_C2FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_C3FF: /* 0x1c3 */
-/* File: x86/OP_UNUSED_C3FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_C4FF: /* 0x1c4 */
-/* File: x86/OP_UNUSED_C4FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_C5FF: /* 0x1c5 */
-/* File: x86/OP_UNUSED_C5FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_C6FF: /* 0x1c6 */
-/* File: x86/OP_UNUSED_C6FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_C7FF: /* 0x1c7 */
-/* File: x86/OP_UNUSED_C7FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_C8FF: /* 0x1c8 */
-/* File: x86/OP_UNUSED_C8FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_C9FF: /* 0x1c9 */
-/* File: x86/OP_UNUSED_C9FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_CAFF: /* 0x1ca */
-/* File: x86/OP_UNUSED_CAFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_CBFF: /* 0x1cb */
-/* File: x86/OP_UNUSED_CBFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_CCFF: /* 0x1cc */
-/* File: x86/OP_UNUSED_CCFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_CDFF: /* 0x1cd */
-/* File: x86/OP_UNUSED_CDFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_CEFF: /* 0x1ce */
-/* File: x86/OP_UNUSED_CEFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_CFFF: /* 0x1cf */
-/* File: x86/OP_UNUSED_CFFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_D0FF: /* 0x1d0 */
-/* File: x86/OP_UNUSED_D0FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_D1FF: /* 0x1d1 */
-/* File: x86/OP_UNUSED_D1FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_D2FF: /* 0x1d2 */
-/* File: x86/OP_UNUSED_D2FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_D3FF: /* 0x1d3 */
-/* File: x86/OP_UNUSED_D3FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_D4FF: /* 0x1d4 */
-/* File: x86/OP_UNUSED_D4FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_D5FF: /* 0x1d5 */
-/* File: x86/OP_UNUSED_D5FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_D6FF: /* 0x1d6 */
-/* File: x86/OP_UNUSED_D6FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_D7FF: /* 0x1d7 */
-/* File: x86/OP_UNUSED_D7FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_D8FF: /* 0x1d8 */
-/* File: x86/OP_UNUSED_D8FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_D9FF: /* 0x1d9 */
-/* File: x86/OP_UNUSED_D9FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_DAFF: /* 0x1da */
-/* File: x86/OP_UNUSED_DAFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_DBFF: /* 0x1db */
-/* File: x86/OP_UNUSED_DBFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_DCFF: /* 0x1dc */
-/* File: x86/OP_UNUSED_DCFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_DDFF: /* 0x1dd */
-/* File: x86/OP_UNUSED_DDFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_DEFF: /* 0x1de */
-/* File: x86/OP_UNUSED_DEFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_DFFF: /* 0x1df */
-/* File: x86/OP_UNUSED_DFFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_E0FF: /* 0x1e0 */
-/* File: x86/OP_UNUSED_E0FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_E1FF: /* 0x1e1 */
-/* File: x86/OP_UNUSED_E1FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_E2FF: /* 0x1e2 */
-/* File: x86/OP_UNUSED_E2FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_E3FF: /* 0x1e3 */
-/* File: x86/OP_UNUSED_E3FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_E4FF: /* 0x1e4 */
-/* File: x86/OP_UNUSED_E4FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_E5FF: /* 0x1e5 */
-/* File: x86/OP_UNUSED_E5FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_E6FF: /* 0x1e6 */
-/* File: x86/OP_UNUSED_E6FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_E7FF: /* 0x1e7 */
-/* File: x86/OP_UNUSED_E7FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_E8FF: /* 0x1e8 */
-/* File: x86/OP_UNUSED_E8FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_E9FF: /* 0x1e9 */
-/* File: x86/OP_UNUSED_E9FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_EAFF: /* 0x1ea */
-/* File: x86/OP_UNUSED_EAFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_EBFF: /* 0x1eb */
-/* File: x86/OP_UNUSED_EBFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_ECFF: /* 0x1ec */
-/* File: x86/OP_UNUSED_ECFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_EDFF: /* 0x1ed */
-/* File: x86/OP_UNUSED_EDFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_EEFF: /* 0x1ee */
-/* File: x86/OP_UNUSED_EEFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_EFFF: /* 0x1ef */
-/* File: x86/OP_UNUSED_EFFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_F0FF: /* 0x1f0 */
-/* File: x86/OP_UNUSED_F0FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_F1FF: /* 0x1f1 */
-/* File: x86/OP_UNUSED_F1FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_F2FF: /* 0x1f2 */
-/* File: x86/OP_UNUSED_F2FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_F3FF: /* 0x1f3 */
-/* File: x86/OP_UNUSED_F3FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_F4FF: /* 0x1f4 */
-/* File: x86/OP_UNUSED_F4FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_F5FF: /* 0x1f5 */
-/* File: x86/OP_UNUSED_F5FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_F6FF: /* 0x1f6 */
-/* File: x86/OP_UNUSED_F6FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_F7FF: /* 0x1f7 */
-/* File: x86/OP_UNUSED_F7FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_F8FF: /* 0x1f8 */
-/* File: x86/OP_UNUSED_F8FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_F9FF: /* 0x1f9 */
-/* File: x86/OP_UNUSED_F9FF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_FAFF: /* 0x1fa */
-/* File: x86/OP_UNUSED_FAFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_FBFF: /* 0x1fb */
-/* File: x86/OP_UNUSED_FBFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_FCFF: /* 0x1fc */
-/* File: x86/OP_UNUSED_FCFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_FDFF: /* 0x1fd */
-/* File: x86/OP_UNUSED_FDFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_UNUSED_FEFF: /* 0x1fe */
-/* File: x86/OP_UNUSED_FEFF.S */
-/* File: x86/unused.S */
- jmp common_abort
-
-
-/* ------------------------------ */
- .balign 64
-.L_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */
-/* File: x86/OP_THROW_VERIFICATION_ERROR_JUMBO.S */
- /*
- * Handle a jumbo throw-verification-error instruction. This throws an
- * exception for an error discovered during verification. The
- * exception is indicated by BBBB, with some detail provided by AAAAAAAA.
- */
- /* exop BBBB, ref@AAAAAAAA */
- movl rSELF,%ecx
- movl 2(rPC),%eax # eax<- AAAAAAAA
- movl offThread_method(%ecx),%ecx # ecx<- self->method
- EXPORT_PC
- movl %eax,OUT_ARG2(%esp) # arg2<- AAAAAAAA
- movl rINST,OUT_ARG1(%esp) # arg1<- BBBB
- movl %ecx,OUT_ARG0(%esp) # arg0<- method
- call dvmThrowVerificationError # call(method, kind, ref)
- jmp common_exceptionThrown # handle exception
-
-
- .balign 64
- .size .L_OP_NOP, .-.L_OP_NOP
- .global dvmAsmInstructionEnd
-dvmAsmInstructionEnd:
-
-/*
- * ===========================================================================
- * Sister implementations
- * ===========================================================================
- */
- .global dvmAsmSisterStart
- .type dvmAsmSisterStart, %function
- .text
- .balign 4
-dvmAsmSisterStart:
-
-/* continuation for OP_CONST_STRING */
-
-/* This is the less common path, so we'll redo some work
- here rather than force spills on the common path */
-.LOP_CONST_STRING_resolve:
- movl rSELF,%eax
- movl %ecx,rINST # rINST<- AA
- EXPORT_PC
- movl offThread_method(%eax),%eax # eax<- self->method
- movzwl 2(rPC),%ecx # ecx<- BBBB
- movl offMethod_clazz(%eax),%eax
- movl %ecx,OUT_ARG1(%esp)
- movl %eax,OUT_ARG0(%esp)
- call dvmResolveString # go resolve
- testl %eax,%eax # failed?
- je common_exceptionThrown
- SET_VREG %eax rINST
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-/* continuation for OP_CONST_STRING_JUMBO */
-
-/* This is the less common path, so we'll redo some work
- here rather than force spills on the common path */
-.LOP_CONST_STRING_JUMBO_resolve:
- movl rSELF,%eax
- movl %ecx,rINST # rINST<- AA
- EXPORT_PC
- movl offThread_method(%eax),%eax # eax<- self->method
- movl 2(rPC),%ecx # ecx<- BBBBBBBB
- movl offMethod_clazz(%eax),%eax
- movl %ecx,OUT_ARG1(%esp)
- movl %eax,OUT_ARG0(%esp)
- call dvmResolveString # go resolve
- testl %eax,%eax # failed?
- je common_exceptionThrown
- SET_VREG %eax rINST
- FETCH_INST_OPCODE 3 %edx
- ADVANCE_PC 3
- GOTO_NEXT_R %edx
-
-/* continuation for OP_CONST_CLASS */
-
-/* This is the less common path, so we'll redo some work
- here rather than force spills on the common path */
-.LOP_CONST_CLASS_resolve:
- movl rSELF,%eax
- movl %ecx,rINST # rINST<- AA
- EXPORT_PC
- movl offThread_method(%eax),%eax # eax<- self->method
- movl $1,OUT_ARG2(%esp) # true
- movzwl 2(rPC),%ecx # ecx<- BBBB
- movl offMethod_clazz(%eax),%eax
- movl %ecx,OUT_ARG1(%esp)
- movl %eax,OUT_ARG0(%esp)
- call dvmResolveClass # go resolve
- testl %eax,%eax # failed?
- je common_exceptionThrown
- SET_VREG %eax rINST
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-/* continuation for OP_MONITOR_ENTER */
-
-.LOP_MONITOR_ENTER_continue:
- movl %ecx,OUT_ARG0(%esp)
- movl %eax,OUT_ARG1(%esp)
- call dvmLockObject # dvmLockObject(self,object)
- ADVANCE_PC 1
- GOTO_NEXT
-
-/* continuation for OP_MONITOR_EXIT */
-
-.LOP_MONITOR_EXIT_continue:
- call dvmUnlockObject # unlock(self,obj)
- FETCH_INST_OPCODE 1 %edx
- testl %eax,%eax # success?
- ADVANCE_PC 1
- je common_exceptionThrown # no, exception pending
- GOTO_NEXT_R %edx
-.LOP_MONITOR_EXIT_errNullObject:
- ADVANCE_PC 1 # advance before throw
- jmp common_errNullObject
-
-/* continuation for OP_CHECK_CAST */
+ GOTO_NEXT_R %ecx
/*
* Trivial test failed, need to perform full check. This is common.
@@ -9285,7 +862,9 @@
movl %eax,sReg0 # we'll need the desired class on failure
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmInstanceofNonTrivial # eax<- boolean result
+ UNSPILL(rIBASE)
testl %eax,%eax # failed?
jne .LOP_CHECK_CAST_okay # no, success
@@ -9313,21 +892,47 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- metho->clazz
movl $0,OUT_ARG2(%esp) # arg2<- false
movl %ecx,OUT_ARG0(%esp) # arg0<- method->clazz
+ SPILL(rIBASE)
call dvmResolveClass # eax<- resolved ClassObject ptr
+ UNSPILL(rIBASE)
testl %eax,%eax # got null?
je common_exceptionThrown # yes, handle exception
movl offObject_clazz(rINST),%ecx # ecx<- obj->clazz
jmp .LOP_CHECK_CAST_resolved # pick up where we left off
-/* continuation for OP_INSTANCE_OF */
-
+/* ------------------------------ */
+.L_OP_INSTANCE_OF: /* 0x20 */
+/* File: x86/OP_INSTANCE_OF.S */
+ /*
+ * Check to see if an object reference is an instance of a class.
+ *
+ * Most common situation is a non-null object, being compared against
+ * an already-resolved class.
+ */
+ /* instance-of vA, vB, class@CCCC */
+ movl rINST,%eax # eax<- BA
+ sarl $4,%eax # eax<- B
+ GET_VREG_R %eax %eax # eax<- vB (obj)
+ movl rSELF,%ecx
+ testl %eax,%eax # object null?
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
+ SPILL(rIBASE) # preserve rIBASE
+ je .LOP_INSTANCE_OF_store # null obj, not instance, store it
+ movzwl 2(rPC),rIBASE # rIBASE<- CCCC
+ movl offDvmDex_pResClasses(%ecx),%ecx # ecx<- pDvmDex->pResClasses
+ movl (%ecx,rIBASE,4),%ecx # ecx<- resolved class
+ movl offObject_clazz(%eax),%eax # eax<- obj->clazz
+ testl %ecx,%ecx # have we resolved this before?
+ je .LOP_INSTANCE_OF_resolve # not resolved, do it now
+.LOP_INSTANCE_OF_resolved: # eax<- obj->clazz, ecx<- resolved class
+ cmpl %eax,%ecx # same class (trivial success)?
+ je .LOP_INSTANCE_OF_trivial # yes, trivial finish
/*
* Trivial test failed, need to perform full check. This is common.
* eax holds obj->clazz
* ecx holds class resolved from BBBB
* rINST has BA
*/
-.LOP_INSTANCE_OF_fullcheck:
movl %eax,OUT_ARG0(%esp)
movl %ecx,OUT_ARG1(%esp)
call dvmInstanceofNonTrivial # eax<- boolean result
@@ -9338,32 +943,34 @@
* rINST holds BA
*/
.LOP_INSTANCE_OF_store:
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
andb $0xf,rINSTbl # <- A
ADVANCE_PC 2
SET_VREG %eax rINST # vA<- eax
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
/*
* Trivial test succeeded, save and bail.
* r9 holds A
*/
.LOP_INSTANCE_OF_trivial:
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
andb $0xf,rINSTbl # <- A
ADVANCE_PC 2
movl $1,%eax
SET_VREG %eax rINST # vA<- true
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
/*
* Resolution required. This is the least-likely path.
*
- * edx holds BBBB
+ * rIBASE holds BBBB
* rINST holds BA
*/
.LOP_INSTANCE_OF_resolve:
- movl %edx,OUT_ARG1(%esp) # arg1<- BBBB
+ movl rIBASE,OUT_ARG1(%esp) # arg1<- BBBB
movl rSELF,%ecx
movl offThread_method(%ecx),%ecx
movl $1,OUT_ARG2(%esp) # arg2<- true
@@ -9377,14 +984,49 @@
* hold the obj->clazz, and ecx to hold the resolved class
*/
movl %eax,%ecx # ecx<- resolved class
- movl rINST,%eax # eax<- BA
+ movl rINST,%eax # eax<- BA
sarl $4,%eax # eax<- B
GET_VREG_R %eax %eax # eax<- vB (obj)
movl offObject_clazz(%eax),%eax # eax<- obj->clazz
jmp .LOP_INSTANCE_OF_resolved
-/* continuation for OP_NEW_INSTANCE */
+/* ------------------------------ */
+.L_OP_ARRAY_LENGTH: /* 0x21 */
+/* File: x86/OP_ARRAY_LENGTH.S */
+ /*
+ * Return the length of an array.
+ */
+ mov rINST,%eax # eax<- BA
+ sarl $4,rINST # rINST<- B
+ GET_VREG_R %ecx rINST # ecx<- vB (object ref)
+ andb $0xf,%al # eax<- A
+ testl %ecx,%ecx # is null?
+ je common_errNullObject
+ movl offArrayObject_length(%ecx),rINST
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ SET_VREG rINST %eax
+ GOTO_NEXT_R %ecx
+/* ------------------------------ */
+.L_OP_NEW_INSTANCE: /* 0x22 */
+/* File: x86/OP_NEW_INSTANCE.S */
+ /*
+ * Create a new instance of a class.
+ */
+ /* new-instance vAA, class@BBBB */
+ movl rSELF,%ecx
+ movzwl 2(rPC),%eax # eax<- BBBB
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
+ SPILL(rIBASE)
+ movl offDvmDex_pResClasses(%ecx),%ecx # ecx<- pDvmDex->pResClasses
+ EXPORT_PC
+ movl (%ecx,%eax,4),%ecx # ecx<- resolved class
+ testl %ecx,%ecx # resolved?
+ je .LOP_NEW_INSTANCE_resolve # no, go do it
+.LOP_NEW_INSTANCE_resolved: # on entry, ecx<- class
+ cmpb $CLASS_INITIALIZED,offClassObject_status(%ecx)
+ jne .LOP_NEW_INSTANCE_needinit
.LOP_NEW_INSTANCE_initialized: # on entry, ecx<- class
/* TODO: remove test for interface/abstract, now done in verifier */
testl $(ACC_INTERFACE|ACC_ABSTRACT),offClassObject_accessFlags(%ecx)
@@ -9393,12 +1035,13 @@
.LOP_NEW_INSTANCE_finish: # ecx=class
movl %ecx,OUT_ARG0(%esp)
call dvmAllocObject # eax<- new object
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
testl %eax,%eax # success?
je common_exceptionThrown # no, bail out
SET_VREG %eax rINST
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
/*
* Class initialization required.
@@ -9446,14 +1089,37 @@
call dvmThrowExceptionWithClassMessage
jmp common_exceptionThrown
-/* continuation for OP_NEW_ARRAY */
-
+/* ------------------------------ */
+.L_OP_NEW_ARRAY: /* 0x23 */
+/* File: x86/OP_NEW_ARRAY.S */
+ /*
+ * Allocate an array of objects, specified with the array class
+ * and a count.
+ *
+ * The verifier guarantees that this is an array class, so we don't
+ * check for it here.
+ */
+ /* new-array vA, vB, class@CCCC */
+ movl rSELF,%ecx
+ EXPORT_PC
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
+ movzwl 2(rPC),%eax # eax<- CCCC
+ movl offDvmDex_pResClasses(%ecx),%ecx # ecx<- pDvmDex->pResClasses
+ SPILL(rIBASE)
+ movl (%ecx,%eax,4),%ecx # ecx<- resolved class
+ movzbl rINSTbl,%eax
+ sarl $4,%eax # eax<- B
+ GET_VREG_R %eax %eax # eax<- vB (array length)
+ andb $0xf,rINSTbl # rINST<- A
+ testl %eax,%eax
+ js common_errNegativeArraySize # bail, passing len in eax
+ testl %ecx,%ecx # already resolved?
+ jne .LOP_NEW_ARRAY_finish # yes, fast path
/*
* Resolve class. (This is an uncommon case.)
* ecx holds class (null here)
* eax holds array length (vB)
*/
-.LOP_NEW_ARRAY_resolve:
movl rSELF,%ecx
SPILL_TMP1(%eax) # save array length
movl offThread_method(%ecx),%ecx # ecx<- self->method
@@ -9480,16 +1146,38 @@
movl %eax,OUT_ARG1(%esp)
movl $ALLOC_DONT_TRACK,OUT_ARG2(%esp)
call dvmAllocArrayByClass # eax<- call(clazz,length,flags)
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
testl %eax,%eax # failed?
je common_exceptionThrown # yup - go handle
SET_VREG %eax rINST
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_FILLED_NEW_ARRAY */
-
-.LOP_FILLED_NEW_ARRAY_more:
+/* ------------------------------ */
+.L_OP_FILLED_NEW_ARRAY: /* 0x24 */
+/* File: x86/OP_FILLED_NEW_ARRAY.S */
+ /*
+ * Create a new array with elements filled from registers.
+ *
+ * for: filled-new-array, filled-new-array/range
+ */
+ /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
+ /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */
+ movl rSELF,%eax
+ movl offThread_methodClassDex(%eax),%eax # eax<- pDvmDex
+ movzwl 2(rPC),%ecx # ecx<- BBBB
+ movl offDvmDex_pResClasses(%eax),%eax # eax<- pDvmDex->pResClasses
+ SPILL(rIBASE) # preserve rIBASE
+ movl (%eax,%ecx,4),%eax # eax<- resolved class
+ EXPORT_PC
+ testl %eax,%eax # already resolved?
+ jne .LOP_FILLED_NEW_ARRAY_continue # yes, continue
+ # less frequent path, so we'll redo some work
+ movl rSELF,%eax
+ movl $0,OUT_ARG2(%esp) # arg2<- false
+ movl %ecx,OUT_ARG1(%esp) # arg1<- BBBB
+ movl offThread_method(%eax),%eax # eax<- self->method
movl offMethod_clazz(%eax),%eax # eax<- method->clazz
movl %eax,OUT_ARG0(%esp) # arg0<- clazz
call dvmResolveClass # eax<- call(clazz,ref,flag)
@@ -9552,19 +1240,18 @@
UNSPILL_TMP3(%edi)
movl rSELF,%ecx
movl offThread_retval+4(%ecx),%eax # eax<- type
- FETCH_INST_OPCODE 3 %edx
.else
testl rINST,rINST
je 4f
- UNSPILL_TMP1(%edx) # restore "BA"
- andl $0x0f,%edx # edx<- 0000000A
- sall $16,%edx # edx<- 000A0000
- orl %ecx,%edx # edx<- 000AFEDC
+ UNSPILL_TMP1(rIBASE) # restore "BA"
+ andl $0x0f,rIBASE # rIBASE<- 0000000A
+ sall $16,rIBASE # rIBASE<- 000A0000
+ orl %ecx,rIBASE # rIBASE<- 000AFEDC
3:
movl $0xf,%ecx
- andl %edx,%ecx # ecx<- next reg to load
+ andl rIBASE,%ecx # ecx<- next reg to load
GET_VREG_R %ecx %ecx
- shrl $4,%edx
+ shrl $4,rIBASE
leal 4(%eax),%eax
movl %ecx,-4(%eax)
sub $1,rINST
@@ -9572,7 +1259,6 @@
4:
movl rSELF,%ecx
movl offThread_retval+4(%ecx),%eax # eax<- type
- FETCH_INST_OPCODE 3 %edx
.endif
cmpb $'I',%al # Int array?
@@ -9582,8 +1268,10 @@
shrl $GC_CARD_SHIFT,%eax # convert to card num
movb %cl,(%ecx,%eax) # mark card based on object head
5:
+ UNSPILL(rIBASE) # restore rIBASE
+ FETCH_INST_OPCODE 3 %ecx
ADVANCE_PC 3
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
/*
@@ -9598,9 +1286,31 @@
call dvmThrowException
jmp common_exceptionThrown
-/* continuation for OP_FILLED_NEW_ARRAY_RANGE */
-
-.LOP_FILLED_NEW_ARRAY_RANGE_more:
+/* ------------------------------ */
+.L_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */
+/* File: x86/OP_FILLED_NEW_ARRAY_RANGE.S */
+/* File: x86/OP_FILLED_NEW_ARRAY.S */
+ /*
+ * Create a new array with elements filled from registers.
+ *
+ * for: filled-new-array, filled-new-array/range
+ */
+ /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
+ /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */
+ movl rSELF,%eax
+ movl offThread_methodClassDex(%eax),%eax # eax<- pDvmDex
+ movzwl 2(rPC),%ecx # ecx<- BBBB
+ movl offDvmDex_pResClasses(%eax),%eax # eax<- pDvmDex->pResClasses
+ SPILL(rIBASE) # preserve rIBASE
+ movl (%eax,%ecx,4),%eax # eax<- resolved class
+ EXPORT_PC
+ testl %eax,%eax # already resolved?
+ jne .LOP_FILLED_NEW_ARRAY_RANGE_continue # yes, continue
+ # less frequent path, so we'll redo some work
+ movl rSELF,%eax
+ movl $0,OUT_ARG2(%esp) # arg2<- false
+ movl %ecx,OUT_ARG1(%esp) # arg1<- BBBB
+ movl offThread_method(%eax),%eax # eax<- self->method
movl offMethod_clazz(%eax),%eax # eax<- method->clazz
movl %eax,OUT_ARG0(%esp) # arg0<- clazz
call dvmResolveClass # eax<- call(clazz,ref,flag)
@@ -9663,19 +1373,18 @@
UNSPILL_TMP3(%edi)
movl rSELF,%ecx
movl offThread_retval+4(%ecx),%eax # eax<- type
- FETCH_INST_OPCODE 3 %edx
.else
testl rINST,rINST
je 4f
- UNSPILL_TMP1(%edx) # restore "BA"
- andl $0x0f,%edx # edx<- 0000000A
- sall $16,%edx # edx<- 000A0000
- orl %ecx,%edx # edx<- 000AFEDC
+ UNSPILL_TMP1(rIBASE) # restore "BA"
+ andl $0x0f,rIBASE # rIBASE<- 0000000A
+ sall $16,rIBASE # rIBASE<- 000A0000
+ orl %ecx,rIBASE # rIBASE<- 000AFEDC
3:
movl $0xf,%ecx
- andl %edx,%ecx # ecx<- next reg to load
+ andl rIBASE,%ecx # ecx<- next reg to load
GET_VREG_R %ecx %ecx
- shrl $4,%edx
+ shrl $4,rIBASE
leal 4(%eax),%eax
movl %ecx,-4(%eax)
sub $1,rINST
@@ -9683,7 +1392,6 @@
4:
movl rSELF,%ecx
movl offThread_retval+4(%ecx),%eax # eax<- type
- FETCH_INST_OPCODE 3 %edx
.endif
cmpb $'I',%al # Int array?
@@ -9693,8 +1401,10 @@
shrl $GC_CARD_SHIFT,%eax # convert to card num
movb %cl,(%ecx,%eax) # mark card based on object head
5:
+ UNSPILL(rIBASE) # restore rIBASE
+ FETCH_INST_OPCODE 3 %ecx
ADVANCE_PC 3
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
/*
@@ -9709,75 +1419,968 @@
call dvmThrowException
jmp common_exceptionThrown
-/* continuation for OP_CMPL_FLOAT */
+
+/* ------------------------------ */
+.L_OP_FILL_ARRAY_DATA: /* 0x26 */
+/* File: x86/OP_FILL_ARRAY_DATA.S */
+ /* fill-array-data vAA, +BBBBBBBB */
+ movl 2(rPC),%ecx # ecx<- BBBBbbbb
+ leal (rPC,%ecx,2),%ecx # ecx<- PC + BBBBbbbb*2
+ GET_VREG_R %eax rINST
+ EXPORT_PC
+ movl %eax,OUT_ARG0(%esp)
+ movl %ecx,OUT_ARG1(%esp)
+ SPILL(rIBASE)
+ call dvmInterpHandleFillArrayData
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 3 %ecx
+ testl %eax,%eax # exception thrown?
+ je common_exceptionThrown
+ ADVANCE_PC 3
+ GOTO_NEXT_R %ecx
+
+/* ------------------------------ */
+.L_OP_THROW: /* 0x27 */
+/* File: x86/OP_THROW.S */
+ /*
+ * Throw an exception object in the current thread.
+ */
+ /* throw vAA */
+ EXPORT_PC
+ GET_VREG_R %eax rINST # eax<- exception object
+ movl rSELF,%ecx # ecx<- self
+ testl %eax,%eax # null object?
+ je common_errNullObject
+ movl %eax,offThread_exception(%ecx) # thread->exception<- obj
+ jmp common_exceptionThrown
+
+/* ------------------------------ */
+.L_OP_GOTO: /* 0x28 */
+/* File: x86/OP_GOTO.S */
+ /*
+ * Unconditional branch, 8-bit offset.
+ *
+ * The branch distance is a signed code-unit offset, which we need to
+ * double to get a byte offset.
+ */
+ /* goto +AA */
+ movsbl rINSTbl,rINST # ebx<- ssssssAA
+ testl rINST,rINST # test for <0
+ js common_backwardBranch
+ movl rINST,%eax
+ FETCH_INST_INDEXED %eax
+ ADVANCE_PC_INDEXED %eax
+ GOTO_NEXT
+
+/* ------------------------------ */
+.L_OP_GOTO_16: /* 0x29 */
+/* File: x86/OP_GOTO_16.S */
+ /*
+ * Unconditional branch, 16-bit offset.
+ *
+ * The branch distance is a signed code-unit offset
+ */
+ /* goto/16 +AAAA */
+ movswl 2(rPC),rINST # rINST<- ssssAAAA
+ testl rINST,rINST # test for <0
+ js common_backwardBranch
+ movl rINST,%eax
+ FETCH_INST_INDEXED %eax
+ ADVANCE_PC_INDEXED %eax
+ GOTO_NEXT
+
+/* ------------------------------ */
+.L_OP_GOTO_32: /* 0x2a */
+/* File: x86/OP_GOTO_32.S */
+ /*
+ * Unconditional branch, 32-bit offset.
+ *
+ * The branch distance is a signed code-unit offset.
+ *
+ * Unlike most opcodes, this one is allowed to branch to itself, so
+ * our "backward branch" test must be "<=0" instead of "<0".
+ */
+ /* goto/32 AAAAAAAA */
+ movl 2(rPC),rINST # rINST<- AAAAAAAA
+ cmpl $0,rINST # test for <= 0
+ jle common_backwardBranch
+ movl rINST,%eax
+ FETCH_INST_INDEXED %eax
+ ADVANCE_PC_INDEXED %eax
+ GOTO_NEXT
+
+/* ------------------------------ */
+.L_OP_PACKED_SWITCH: /* 0x2b */
+/* File: x86/OP_PACKED_SWITCH.S */
+ /*
+ * Handle a packed-switch or sparse-switch instruction. In both cases
+ * we decode it and hand it off to a helper function.
+ *
+ * We don't really expect backward branches in a switch statement, but
+ * they're perfectly legal, so we check for them here.
+ *
+ * for: packed-switch, sparse-switch
+ */
+ /* op vAA, +BBBB */
+ movl 2(rPC),%ecx # ecx<- BBBBbbbb
+ GET_VREG_R %eax rINST # eax<- vAA
+ leal (rPC,%ecx,2),%ecx # ecx<- PC + BBBBbbbb*2
+ movl %eax,OUT_ARG1(%esp) # ARG1<- vAA
+ movl %ecx,OUT_ARG0(%esp) # ARG0<- switchData
+ SPILL(rIBASE)
+ call dvmInterpHandlePackedSwitch
+ UNSPILL(rIBASE)
+ testl %eax,%eax
+ movl %eax,rINST # set up word offset
+ jle common_backwardBranch # check on special actions
+ ADVANCE_PC_INDEXED rINST
+ FETCH_INST
+ GOTO_NEXT
+
+/* ------------------------------ */
+.L_OP_SPARSE_SWITCH: /* 0x2c */
+/* File: x86/OP_SPARSE_SWITCH.S */
+/* File: x86/OP_PACKED_SWITCH.S */
+ /*
+ * Handle a packed-switch or sparse-switch instruction. In both cases
+ * we decode it and hand it off to a helper function.
+ *
+ * We don't really expect backward branches in a switch statement, but
+ * they're perfectly legal, so we check for them here.
+ *
+ * for: packed-switch, sparse-switch
+ */
+ /* op vAA, +BBBB */
+ movl 2(rPC),%ecx # ecx<- BBBBbbbb
+ GET_VREG_R %eax rINST # eax<- vAA
+ leal (rPC,%ecx,2),%ecx # ecx<- PC + BBBBbbbb*2
+ movl %eax,OUT_ARG1(%esp) # ARG1<- vAA
+ movl %ecx,OUT_ARG0(%esp) # ARG0<- switchData
+ SPILL(rIBASE)
+ call dvmInterpHandleSparseSwitch
+ UNSPILL(rIBASE)
+ testl %eax,%eax
+ movl %eax,rINST # set up word offset
+ jle common_backwardBranch # check on special actions
+ ADVANCE_PC_INDEXED rINST
+ FETCH_INST
+ GOTO_NEXT
+
+
+/* ------------------------------ */
+.L_OP_CMPL_FLOAT: /* 0x2d */
+/* File: x86/OP_CMPL_FLOAT.S */
+/* File: x86/OP_CMPG_DOUBLE.S */
+ /* float/double_cmp[gl] vAA, vBB, vCC */
+ movzbl 3(rPC),%eax # eax<- CC
+ movzbl 2(rPC),%ecx # ecx<- BB
+ .if 0
+ fldl (rFP,%eax,4)
+ fldl (rFP,%ecx,4)
+ .else
+ flds (rFP,%eax,4)
+ flds (rFP,%ecx,4)
+ .endif
+ xorl %ecx,%ecx
+ fucompp # z if equal, p set if NaN, c set if st0 < st1
+ fnstsw %ax
+ sahf
+ FETCH_INST_OPCODE 2 %eax
+ jp .LOP_CMPL_FLOAT_isNaN
+ je .LOP_CMPL_FLOAT_finish
+ sbbl %ecx,%ecx
+ jb .LOP_CMPL_FLOAT_finish
+ incl %ecx
+.LOP_CMPL_FLOAT_finish:
+ SET_VREG %ecx rINST
+ ADVANCE_PC 2
+ GOTO_NEXT_R %eax
.LOP_CMPL_FLOAT_isNaN:
movl $-1,%ecx
jmp .LOP_CMPL_FLOAT_finish
-/* continuation for OP_CMPG_FLOAT */
+
+/* ------------------------------ */
+.L_OP_CMPG_FLOAT: /* 0x2e */
+/* File: x86/OP_CMPG_FLOAT.S */
+/* File: x86/OP_CMPG_DOUBLE.S */
+ /* float/double_cmp[gl] vAA, vBB, vCC */
+ movzbl 3(rPC),%eax # eax<- CC
+ movzbl 2(rPC),%ecx # ecx<- BB
+ .if 0
+ fldl (rFP,%eax,4)
+ fldl (rFP,%ecx,4)
+ .else
+ flds (rFP,%eax,4)
+ flds (rFP,%ecx,4)
+ .endif
+ xorl %ecx,%ecx
+ fucompp # z if equal, p set if NaN, c set if st0 < st1
+ fnstsw %ax
+ sahf
+ FETCH_INST_OPCODE 2 %eax
+ jp .LOP_CMPG_FLOAT_isNaN
+ je .LOP_CMPG_FLOAT_finish
+ sbbl %ecx,%ecx
+ jb .LOP_CMPG_FLOAT_finish
+ incl %ecx
+.LOP_CMPG_FLOAT_finish:
+ SET_VREG %ecx rINST
+ ADVANCE_PC 2
+ GOTO_NEXT_R %eax
.LOP_CMPG_FLOAT_isNaN:
movl $1,%ecx
jmp .LOP_CMPG_FLOAT_finish
-/* continuation for OP_CMPL_DOUBLE */
+
+/* ------------------------------ */
+.L_OP_CMPL_DOUBLE: /* 0x2f */
+/* File: x86/OP_CMPL_DOUBLE.S */
+/* File: x86/OP_CMPG_DOUBLE.S */
+ /* float/double_cmp[gl] vAA, vBB, vCC */
+ movzbl 3(rPC),%eax # eax<- CC
+ movzbl 2(rPC),%ecx # ecx<- BB
+ .if 1
+ fldl (rFP,%eax,4)
+ fldl (rFP,%ecx,4)
+ .else
+ flds (rFP,%eax,4)
+ flds (rFP,%ecx,4)
+ .endif
+ xorl %ecx,%ecx
+ fucompp # z if equal, p set if NaN, c set if st0 < st1
+ fnstsw %ax
+ sahf
+ FETCH_INST_OPCODE 2 %eax
+ jp .LOP_CMPL_DOUBLE_isNaN
+ je .LOP_CMPL_DOUBLE_finish
+ sbbl %ecx,%ecx
+ jb .LOP_CMPL_DOUBLE_finish
+ incl %ecx
+.LOP_CMPL_DOUBLE_finish:
+ SET_VREG %ecx rINST
+ ADVANCE_PC 2
+ GOTO_NEXT_R %eax
.LOP_CMPL_DOUBLE_isNaN:
movl $-1,%ecx
jmp .LOP_CMPL_DOUBLE_finish
-/* continuation for OP_CMPG_DOUBLE */
+
+/* ------------------------------ */
+.L_OP_CMPG_DOUBLE: /* 0x30 */
+/* File: x86/OP_CMPG_DOUBLE.S */
+ /* float/double_cmp[gl] vAA, vBB, vCC */
+ movzbl 3(rPC),%eax # eax<- CC
+ movzbl 2(rPC),%ecx # ecx<- BB
+ .if 1
+ fldl (rFP,%eax,4)
+ fldl (rFP,%ecx,4)
+ .else
+ flds (rFP,%eax,4)
+ flds (rFP,%ecx,4)
+ .endif
+ xorl %ecx,%ecx
+ fucompp # z if equal, p set if NaN, c set if st0 < st1
+ fnstsw %ax
+ sahf
+ FETCH_INST_OPCODE 2 %eax
+ jp .LOP_CMPG_DOUBLE_isNaN
+ je .LOP_CMPG_DOUBLE_finish
+ sbbl %ecx,%ecx
+ jb .LOP_CMPG_DOUBLE_finish
+ incl %ecx
+.LOP_CMPG_DOUBLE_finish:
+ SET_VREG %ecx rINST
+ ADVANCE_PC 2
+ GOTO_NEXT_R %eax
.LOP_CMPG_DOUBLE_isNaN:
movl $1,%ecx
jmp .LOP_CMPG_DOUBLE_finish
-/* continuation for OP_CMP_LONG */
+/* ------------------------------ */
+.L_OP_CMP_LONG: /* 0x31 */
+/* File: x86/OP_CMP_LONG.S */
+ /*
+ * Compare two 64-bit values. Puts 0, 1, or -1 into the destination
+ * register based on the results of the comparison.
+ */
+ // TUNING: rework to avoid rIBASE spill
+ /* cmp-long vAA, vBB, vCC */
+ movzbl 2(rPC),%ecx # ecx<- BB
+ SPILL(rIBASE)
+ movzbl 3(rPC),rIBASE # rIBASE- CC
+ GET_VREG_WORD %eax %ecx,1 # eax<- v[BB+1]
+ GET_VREG_WORD %ecx %ecx 0 # ecx<- v[BB+0]
+ cmpl 4(rFP,rIBASE,4),%eax
+ jl .LOP_CMP_LONG_smaller
+ jg .LOP_CMP_LONG_bigger
+ sub (rFP,rIBASE,4),%ecx
+ ja .LOP_CMP_LONG_bigger
+ jb .LOP_CMP_LONG_smaller
+ SET_VREG %ecx rINST
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
.LOP_CMP_LONG_bigger:
movl $1,%ecx
- jmp .LOP_CMP_LONG_finish
+ SET_VREG %ecx rINST
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
.LOP_CMP_LONG_smaller:
movl $-1,%ecx
-.LOP_CMP_LONG_finish:
SET_VREG %ecx rINST
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_AGET_WIDE */
+/* ------------------------------ */
+.L_OP_IF_EQ: /* 0x32 */
+/* File: x86/OP_IF_EQ.S */
+/* File: x86/bincmp.S */
+ /*
+ * Generic two-operand compare-and-branch operation. Provide a "revcmp"
+ * fragment that specifies the *reverse* comparison to perform, e.g.
+ * for "if-le" you would use "gt".
+ *
+ * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
+ */
+ /* if-cmp vA, vB, +CCCC */
+ movzx rINSTbl,%ecx # ecx <- A+
+ andb $0xf,%cl # ecx <- A
+ GET_VREG_R %eax %ecx # eax <- vA
+ sarl $4,rINST # rINST<- B
+ cmpl (rFP,rINST,4),%eax # compare (vA, vB)
+ movswl 2(rPC),rINST # Get signed branch offset
+ movl $2,%eax # assume not taken
+ jne 1f
+ testl rINST,rINST
+ js common_backwardBranch
+ movl rINST,%eax
+1:
+ FETCH_INST_INDEXED %eax
+ ADVANCE_PC_INDEXED %eax
+ GOTO_NEXT
-.LOP_AGET_WIDE_finish:
+
+/* ------------------------------ */
+.L_OP_IF_NE: /* 0x33 */
+/* File: x86/OP_IF_NE.S */
+/* File: x86/bincmp.S */
+ /*
+ * Generic two-operand compare-and-branch operation. Provide a "revcmp"
+ * fragment that specifies the *reverse* comparison to perform, e.g.
+ * for "if-le" you would use "gt".
+ *
+ * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
+ */
+ /* if-cmp vA, vB, +CCCC */
+ movzx rINSTbl,%ecx # ecx <- A+
+ andb $0xf,%cl # ecx <- A
+ GET_VREG_R %eax %ecx # eax <- vA
+ sarl $4,rINST # rINST<- B
+ cmpl (rFP,rINST,4),%eax # compare (vA, vB)
+ movswl 2(rPC),rINST # Get signed branch offset
+ movl $2,%eax # assume not taken
+ je 1f
+ testl rINST,rINST
+ js common_backwardBranch
+ movl rINST,%eax
+1:
+ FETCH_INST_INDEXED %eax
+ ADVANCE_PC_INDEXED %eax
+ GOTO_NEXT
+
+
+/* ------------------------------ */
+.L_OP_IF_LT: /* 0x34 */
+/* File: x86/OP_IF_LT.S */
+/* File: x86/bincmp.S */
+ /*
+ * Generic two-operand compare-and-branch operation. Provide a "revcmp"
+ * fragment that specifies the *reverse* comparison to perform, e.g.
+ * for "if-le" you would use "gt".
+ *
+ * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
+ */
+ /* if-cmp vA, vB, +CCCC */
+ movzx rINSTbl,%ecx # ecx <- A+
+ andb $0xf,%cl # ecx <- A
+ GET_VREG_R %eax %ecx # eax <- vA
+ sarl $4,rINST # rINST<- B
+ cmpl (rFP,rINST,4),%eax # compare (vA, vB)
+ movswl 2(rPC),rINST # Get signed branch offset
+ movl $2,%eax # assume not taken
+ jge 1f
+ testl rINST,rINST
+ js common_backwardBranch
+ movl rINST,%eax
+1:
+ FETCH_INST_INDEXED %eax
+ ADVANCE_PC_INDEXED %eax
+ GOTO_NEXT
+
+
+/* ------------------------------ */
+.L_OP_IF_GE: /* 0x35 */
+/* File: x86/OP_IF_GE.S */
+/* File: x86/bincmp.S */
+ /*
+ * Generic two-operand compare-and-branch operation. Provide a "revcmp"
+ * fragment that specifies the *reverse* comparison to perform, e.g.
+ * for "if-le" you would use "gt".
+ *
+ * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
+ */
+ /* if-cmp vA, vB, +CCCC */
+ movzx rINSTbl,%ecx # ecx <- A+
+ andb $0xf,%cl # ecx <- A
+ GET_VREG_R %eax %ecx # eax <- vA
+ sarl $4,rINST # rINST<- B
+ cmpl (rFP,rINST,4),%eax # compare (vA, vB)
+ movswl 2(rPC),rINST # Get signed branch offset
+ movl $2,%eax # assume not taken
+ jl 1f
+ testl rINST,rINST
+ js common_backwardBranch
+ movl rINST,%eax
+1:
+ FETCH_INST_INDEXED %eax
+ ADVANCE_PC_INDEXED %eax
+ GOTO_NEXT
+
+
+/* ------------------------------ */
+.L_OP_IF_GT: /* 0x36 */
+/* File: x86/OP_IF_GT.S */
+/* File: x86/bincmp.S */
+ /*
+ * Generic two-operand compare-and-branch operation. Provide a "revcmp"
+ * fragment that specifies the *reverse* comparison to perform, e.g.
+ * for "if-le" you would use "gt".
+ *
+ * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
+ */
+ /* if-cmp vA, vB, +CCCC */
+ movzx rINSTbl,%ecx # ecx <- A+
+ andb $0xf,%cl # ecx <- A
+ GET_VREG_R %eax %ecx # eax <- vA
+ sarl $4,rINST # rINST<- B
+ cmpl (rFP,rINST,4),%eax # compare (vA, vB)
+ movswl 2(rPC),rINST # Get signed branch offset
+ movl $2,%eax # assume not taken
+ jle 1f
+ testl rINST,rINST
+ js common_backwardBranch
+ movl rINST,%eax
+1:
+ FETCH_INST_INDEXED %eax
+ ADVANCE_PC_INDEXED %eax
+ GOTO_NEXT
+
+
+/* ------------------------------ */
+.L_OP_IF_LE: /* 0x37 */
+/* File: x86/OP_IF_LE.S */
+/* File: x86/bincmp.S */
+ /*
+ * Generic two-operand compare-and-branch operation. Provide a "revcmp"
+ * fragment that specifies the *reverse* comparison to perform, e.g.
+ * for "if-le" you would use "gt".
+ *
+ * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
+ */
+ /* if-cmp vA, vB, +CCCC */
+ movzx rINSTbl,%ecx # ecx <- A+
+ andb $0xf,%cl # ecx <- A
+ GET_VREG_R %eax %ecx # eax <- vA
+ sarl $4,rINST # rINST<- B
+ cmpl (rFP,rINST,4),%eax # compare (vA, vB)
+ movswl 2(rPC),rINST # Get signed branch offset
+ movl $2,%eax # assume not taken
+ jg 1f
+ testl rINST,rINST
+ js common_backwardBranch
+ movl rINST,%eax
+1:
+ FETCH_INST_INDEXED %eax
+ ADVANCE_PC_INDEXED %eax
+ GOTO_NEXT
+
+
+/* ------------------------------ */
+.L_OP_IF_EQZ: /* 0x38 */
+/* File: x86/OP_IF_EQZ.S */
+/* File: x86/zcmp.S */
+ /*
+ * Generic one-operand compare-and-branch operation. Provide a "revcmp"
+ * fragment that specifies the *reverse* comparison to perform, e.g.
+ * for "if-le" you would use "gt".
+ *
+ * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
+ */
+ /* if-cmp vAA, +BBBB */
+ cmpl $0,(rFP,rINST,4) # compare (vA, 0)
+ movswl 2(rPC),rINST # fetch signed displacement
+ movl $2,%eax # assume branch not taken
+ jne 1f
+ testl rINST,rINST
+ js common_backwardBranch
+ movl rINST,%eax
+1:
+ FETCH_INST_INDEXED %eax
+ ADVANCE_PC_INDEXED %eax
+ GOTO_NEXT
+
+
+/* ------------------------------ */
+.L_OP_IF_NEZ: /* 0x39 */
+/* File: x86/OP_IF_NEZ.S */
+/* File: x86/zcmp.S */
+ /*
+ * Generic one-operand compare-and-branch operation. Provide a "revcmp"
+ * fragment that specifies the *reverse* comparison to perform, e.g.
+ * for "if-le" you would use "gt".
+ *
+ * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
+ */
+ /* if-cmp vAA, +BBBB */
+ cmpl $0,(rFP,rINST,4) # compare (vA, 0)
+ movswl 2(rPC),rINST # fetch signed displacement
+ movl $2,%eax # assume branch not taken
+ je 1f
+ testl rINST,rINST
+ js common_backwardBranch
+ movl rINST,%eax
+1:
+ FETCH_INST_INDEXED %eax
+ ADVANCE_PC_INDEXED %eax
+ GOTO_NEXT
+
+
+/* ------------------------------ */
+.L_OP_IF_LTZ: /* 0x3a */
+/* File: x86/OP_IF_LTZ.S */
+/* File: x86/zcmp.S */
+ /*
+ * Generic one-operand compare-and-branch operation. Provide a "revcmp"
+ * fragment that specifies the *reverse* comparison to perform, e.g.
+ * for "if-le" you would use "gt".
+ *
+ * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
+ */
+ /* if-cmp vAA, +BBBB */
+ cmpl $0,(rFP,rINST,4) # compare (vA, 0)
+ movswl 2(rPC),rINST # fetch signed displacement
+ movl $2,%eax # assume branch not taken
+ jge 1f
+ testl rINST,rINST
+ js common_backwardBranch
+ movl rINST,%eax
+1:
+ FETCH_INST_INDEXED %eax
+ ADVANCE_PC_INDEXED %eax
+ GOTO_NEXT
+
+
+/* ------------------------------ */
+.L_OP_IF_GEZ: /* 0x3b */
+/* File: x86/OP_IF_GEZ.S */
+/* File: x86/zcmp.S */
+ /*
+ * Generic one-operand compare-and-branch operation. Provide a "revcmp"
+ * fragment that specifies the *reverse* comparison to perform, e.g.
+ * for "if-le" you would use "gt".
+ *
+ * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
+ */
+ /* if-cmp vAA, +BBBB */
+ cmpl $0,(rFP,rINST,4) # compare (vA, 0)
+ movswl 2(rPC),rINST # fetch signed displacement
+ movl $2,%eax # assume branch not taken
+ jl 1f
+ testl rINST,rINST
+ js common_backwardBranch
+ movl rINST,%eax
+1:
+ FETCH_INST_INDEXED %eax
+ ADVANCE_PC_INDEXED %eax
+ GOTO_NEXT
+
+
+/* ------------------------------ */
+.L_OP_IF_GTZ: /* 0x3c */
+/* File: x86/OP_IF_GTZ.S */
+/* File: x86/zcmp.S */
+ /*
+ * Generic one-operand compare-and-branch operation. Provide a "revcmp"
+ * fragment that specifies the *reverse* comparison to perform, e.g.
+ * for "if-le" you would use "gt".
+ *
+ * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
+ */
+ /* if-cmp vAA, +BBBB */
+ cmpl $0,(rFP,rINST,4) # compare (vA, 0)
+ movswl 2(rPC),rINST # fetch signed displacement
+ movl $2,%eax # assume branch not taken
+ jle 1f
+ testl rINST,rINST
+ js common_backwardBranch
+ movl rINST,%eax
+1:
+ FETCH_INST_INDEXED %eax
+ ADVANCE_PC_INDEXED %eax
+ GOTO_NEXT
+
+
+/* ------------------------------ */
+.L_OP_IF_LEZ: /* 0x3d */
+/* File: x86/OP_IF_LEZ.S */
+/* File: x86/zcmp.S */
+ /*
+ * Generic one-operand compare-and-branch operation. Provide a "revcmp"
+ * fragment that specifies the *reverse* comparison to perform, e.g.
+ * for "if-le" you would use "gt".
+ *
+ * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
+ */
+ /* if-cmp vAA, +BBBB */
+ cmpl $0,(rFP,rINST,4) # compare (vA, 0)
+ movswl 2(rPC),rINST # fetch signed displacement
+ movl $2,%eax # assume branch not taken
+ jg 1f
+ testl rINST,rINST
+ js common_backwardBranch
+ movl rINST,%eax
+1:
+ FETCH_INST_INDEXED %eax
+ ADVANCE_PC_INDEXED %eax
+ GOTO_NEXT
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_3E: /* 0x3e */
+/* File: x86/OP_UNUSED_3E.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_3F: /* 0x3f */
+/* File: x86/OP_UNUSED_3F.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_40: /* 0x40 */
+/* File: x86/OP_UNUSED_40.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_41: /* 0x41 */
+/* File: x86/OP_UNUSED_41.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_42: /* 0x42 */
+/* File: x86/OP_UNUSED_42.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_43: /* 0x43 */
+/* File: x86/OP_UNUSED_43.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_AGET: /* 0x44 */
+/* File: x86/OP_AGET.S */
+ /*
+ * Array get, 32 bits or less. vAA <- vBB[vCC].
+ *
+ * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
+ */
+ /* op vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ GET_VREG_R %eax %eax # eax<- vBB (array object)
+ GET_VREG_R %ecx %ecx # ecs<- vCC (requested index)
+ testl %eax,%eax # null array object?
+ je common_errNullObject # bail if so
+ cmpl offArrayObject_length(%eax),%ecx
+ jae common_errArrayIndex # index >= length, bail. Expects
+ # arrayObj in eax
+ # index in ecx
+ movl offArrayObject_contents(%eax,%ecx,4),%eax
+.LOP_AGET_finish:
+ FETCH_INST_OPCODE 2 %ecx
+ SET_VREG %eax rINST
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+/* ------------------------------ */
+.L_OP_AGET_WIDE: /* 0x45 */
+/* File: x86/OP_AGET_WIDE.S */
+ /*
+ * Array get, 64 bits. vAA <- vBB[vCC].
+ *
+ */
+ /* op vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ GET_VREG_R %eax %eax # eax<- vBB (array object)
+ GET_VREG_R %ecx %ecx # ecs<- vCC (requested index)
+ testl %eax,%eax # null array object?
+ je common_errNullObject # bail if so
+ cmpl offArrayObject_length(%eax),%ecx
+ jae common_errArrayIndex # index >= length, bail. Expects
+ # arrayObj in eax
+ # index in ecx
leal offArrayObject_contents(%eax,%ecx,8),%eax
movl (%eax),%ecx
movl 4(%eax),%eax
SET_VREG_WORD %ecx rINST 0
SET_VREG_WORD %eax rINST 1
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_APUT_WIDE */
+/* ------------------------------ */
+.L_OP_AGET_OBJECT: /* 0x46 */
+/* File: x86/OP_AGET_OBJECT.S */
+/* File: x86/OP_AGET.S */
+ /*
+ * Array get, 32 bits or less. vAA <- vBB[vCC].
+ *
+ * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
+ */
+ /* op vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ GET_VREG_R %eax %eax # eax<- vBB (array object)
+ GET_VREG_R %ecx %ecx # ecs<- vCC (requested index)
+ testl %eax,%eax # null array object?
+ je common_errNullObject # bail if so
+ cmpl offArrayObject_length(%eax),%ecx
+ jae common_errArrayIndex # index >= length, bail. Expects
+ # arrayObj in eax
+ # index in ecx
+ movl offArrayObject_contents(%eax,%ecx,4),%eax
+.LOP_AGET_OBJECT_finish:
+ FETCH_INST_OPCODE 2 %ecx
+ SET_VREG %eax rINST
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
-.LOP_APUT_WIDE_finish:
+
+/* ------------------------------ */
+.L_OP_AGET_BOOLEAN: /* 0x47 */
+/* File: x86/OP_AGET_BOOLEAN.S */
+/* File: x86/OP_AGET.S */
+ /*
+ * Array get, 32 bits or less. vAA <- vBB[vCC].
+ *
+ * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
+ */
+ /* op vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ GET_VREG_R %eax %eax # eax<- vBB (array object)
+ GET_VREG_R %ecx %ecx # ecs<- vCC (requested index)
+ testl %eax,%eax # null array object?
+ je common_errNullObject # bail if so
+ cmpl offArrayObject_length(%eax),%ecx
+ jae common_errArrayIndex # index >= length, bail. Expects
+ # arrayObj in eax
+ # index in ecx
+ movzbl offArrayObject_contents(%eax,%ecx,1),%eax
+.LOP_AGET_BOOLEAN_finish:
+ FETCH_INST_OPCODE 2 %ecx
+ SET_VREG %eax rINST
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_AGET_BYTE: /* 0x48 */
+/* File: x86/OP_AGET_BYTE.S */
+/* File: x86/OP_AGET.S */
+ /*
+ * Array get, 32 bits or less. vAA <- vBB[vCC].
+ *
+ * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
+ */
+ /* op vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ GET_VREG_R %eax %eax # eax<- vBB (array object)
+ GET_VREG_R %ecx %ecx # ecs<- vCC (requested index)
+ testl %eax,%eax # null array object?
+ je common_errNullObject # bail if so
+ cmpl offArrayObject_length(%eax),%ecx
+ jae common_errArrayIndex # index >= length, bail. Expects
+ # arrayObj in eax
+ # index in ecx
+ movsbl offArrayObject_contents(%eax,%ecx,1),%eax
+.LOP_AGET_BYTE_finish:
+ FETCH_INST_OPCODE 2 %ecx
+ SET_VREG %eax rINST
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_AGET_CHAR: /* 0x49 */
+/* File: x86/OP_AGET_CHAR.S */
+/* File: x86/OP_AGET.S */
+ /*
+ * Array get, 32 bits or less. vAA <- vBB[vCC].
+ *
+ * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
+ */
+ /* op vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ GET_VREG_R %eax %eax # eax<- vBB (array object)
+ GET_VREG_R %ecx %ecx # ecs<- vCC (requested index)
+ testl %eax,%eax # null array object?
+ je common_errNullObject # bail if so
+ cmpl offArrayObject_length(%eax),%ecx
+ jae common_errArrayIndex # index >= length, bail. Expects
+ # arrayObj in eax
+ # index in ecx
+ movzwl offArrayObject_contents(%eax,%ecx,2),%eax
+.LOP_AGET_CHAR_finish:
+ FETCH_INST_OPCODE 2 %ecx
+ SET_VREG %eax rINST
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_AGET_SHORT: /* 0x4a */
+/* File: x86/OP_AGET_SHORT.S */
+/* File: x86/OP_AGET.S */
+ /*
+ * Array get, 32 bits or less. vAA <- vBB[vCC].
+ *
+ * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
+ */
+ /* op vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ GET_VREG_R %eax %eax # eax<- vBB (array object)
+ GET_VREG_R %ecx %ecx # ecs<- vCC (requested index)
+ testl %eax,%eax # null array object?
+ je common_errNullObject # bail if so
+ cmpl offArrayObject_length(%eax),%ecx
+ jae common_errArrayIndex # index >= length, bail. Expects
+ # arrayObj in eax
+ # index in ecx
+ movswl offArrayObject_contents(%eax,%ecx,2),%eax
+.LOP_AGET_SHORT_finish:
+ FETCH_INST_OPCODE 2 %ecx
+ SET_VREG %eax rINST
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_APUT: /* 0x4b */
+/* File: x86/OP_APUT.S */
+ /*
+ * Array put, 32 bits or less. vBB[vCC] <- vAA
+ *
+ * for: aput, aput-object, aput-boolean, aput-byte, aput-char, aput-short
+ */
+ /* op vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ GET_VREG_R %eax %eax # eax<- vBB (array object)
+ GET_VREG_R %ecx %ecx # ecs<- vCC (requested index)
+ testl %eax,%eax # null array object?
+ je common_errNullObject # bail if so
+ cmpl offArrayObject_length(%eax),%ecx
+ jae common_errArrayIndex # index >= length, bail. Expects:
+ # arrayObj in eax
+ # index in ecx
+ leal offArrayObject_contents(%eax,%ecx,4),%eax
+.LOP_APUT_finish:
+ GET_VREG_R rINST rINST
+ FETCH_INST_OPCODE 2 %ecx
+ movl rINST,(%eax)
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+/* ------------------------------ */
+.L_OP_APUT_WIDE: /* 0x4c */
+/* File: x86/OP_APUT_WIDE.S */
+ /*
+ * Array put, 64 bits. vBB[vCC]<-vAA.
+ *
+ */
+ /* op vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ GET_VREG_R %eax %eax # eax<- vBB (array object)
+ GET_VREG_R %ecx %ecx # ecs<- vCC (requested index)
+ testl %eax,%eax # null array object?
+ je common_errNullObject # bail if so
+ cmpl offArrayObject_length(%eax),%ecx
+ jae common_errArrayIndex # index >= length, bail. Expects:
+ # arrayObj in eax
+ # index in ecx
leal offArrayObject_contents(%eax,%ecx,8),%eax
GET_VREG_WORD %ecx rINST 0
GET_VREG_WORD rINST rINST 1
- movl rINST,4(%eax)
- FETCH_INST_OPCODE 2 %edx
movl %ecx,(%eax)
+ FETCH_INST_OPCODE 2 %ecx
+ movl rINST,4(%eax)
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_APUT_OBJECT */
-
+/* ------------------------------ */
+.L_OP_APUT_OBJECT: /* 0x4d */
+/* File: x86/OP_APUT_OBJECT.S */
+ /*
+ * Array put, 32 bits or less. vBB[vCC] <- vAA
+ *
+ * for: aput, aput-object, aput-boolean, aput-byte, aput-char, aput-short
+ */
+ /* op vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ GET_VREG_R %eax %eax # eax<- vBB (array object)
+ GET_VREG_R %ecx %ecx # ecs<- vCC (requested index)
+ GET_VREG_R rINST rINST # rINST<- vAA
+ testl %eax,%eax # null array object?
+ je common_errNullObject # bail if so
+ cmpl offArrayObject_length(%eax),%ecx
+ jae common_errArrayIndex # index >= length, bail. Expects
+ # arrayObj in eax
+ # index in ecx
/* On entry:
* eax<- array object
* ecx<- index
* rINST<- vAA
*/
-.LOP_APUT_OBJECT_continue:
leal offArrayObject_contents(%eax,%ecx,4),%ecx
testl rINST,rINST # storing null reference?
je .LOP_APUT_OBJECT_skip_check
@@ -9789,7 +2392,9 @@
movl %ecx,OUT_ARG0(%esp)
movl %ecx,sReg0 # store the two classes for later
movl %eax,sReg1
+ SPILL(rIBASE)
call dvmCanPutArrayElement # test object type vs. array type
+ UNSPILL(rIBASE)
UNSPILL_TMP1(%ecx) # recover target address
testl %eax,%eax
movl rSELF,%eax
@@ -9807,28 +2412,163 @@
.LOP_APUT_OBJECT_types_okay:
movl offThread_cardTable(%eax),%eax # get card table base
movl rINST,(%ecx) # store into array
- UNSPILL_TMP2(%ecx) # recover object head
- FETCH_INST_OPCODE 2 %edx
- shrl $GC_CARD_SHIFT,%ecx # object head to card number
- movb %al,(%eax,%ecx) # mark card using object head
+ UNSPILL_TMP2(rINST) # recover object head
+ FETCH_INST_OPCODE 2 %ecx
+ shrl $GC_CARD_SHIFT,rINST # object head to card number
+ movb %al,(%eax,rINST) # mark card using object head
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
.LOP_APUT_OBJECT_skip_check:
movl rINST,(%ecx)
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_IGET */
+/* ------------------------------ */
+.L_OP_APUT_BOOLEAN: /* 0x4e */
+/* File: x86/OP_APUT_BOOLEAN.S */
+/* File: x86/OP_APUT.S */
+ /*
+ * Array put, 32 bits or less. vBB[vCC] <- vAA
+ *
+ * for: aput, aput-object, aput-boolean, aput-byte, aput-char, aput-short
+ */
+ /* op vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ GET_VREG_R %eax %eax # eax<- vBB (array object)
+ GET_VREG_R %ecx %ecx # ecs<- vCC (requested index)
+ testl %eax,%eax # null array object?
+ je common_errNullObject # bail if so
+ cmpl offArrayObject_length(%eax),%ecx
+ jae common_errArrayIndex # index >= length, bail. Expects:
+ # arrayObj in eax
+ # index in ecx
+ leal offArrayObject_contents(%eax,%ecx,1),%eax
+.LOP_APUT_BOOLEAN_finish:
+ GET_VREG_R rINST rINST
+ FETCH_INST_OPCODE 2 %ecx
+ movb rINSTbl,(%eax)
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
-.LOP_IGET_resolve:
+/* ------------------------------ */
+.L_OP_APUT_BYTE: /* 0x4f */
+/* File: x86/OP_APUT_BYTE.S */
+/* File: x86/OP_APUT.S */
+ /*
+ * Array put, 32 bits or less. vBB[vCC] <- vAA
+ *
+ * for: aput, aput-object, aput-boolean, aput-byte, aput-char, aput-short
+ */
+ /* op vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ GET_VREG_R %eax %eax # eax<- vBB (array object)
+ GET_VREG_R %ecx %ecx # ecs<- vCC (requested index)
+ testl %eax,%eax # null array object?
+ je common_errNullObject # bail if so
+ cmpl offArrayObject_length(%eax),%ecx
+ jae common_errArrayIndex # index >= length, bail. Expects:
+ # arrayObj in eax
+ # index in ecx
+ leal offArrayObject_contents(%eax,%ecx,1),%eax
+.LOP_APUT_BYTE_finish:
+ GET_VREG_R rINST rINST
+ FETCH_INST_OPCODE 2 %ecx
+ movb rINSTbl,(%eax)
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_APUT_CHAR: /* 0x50 */
+/* File: x86/OP_APUT_CHAR.S */
+/* File: x86/OP_APUT.S */
+ /*
+ * Array put, 32 bits or less. vBB[vCC] <- vAA
+ *
+ * for: aput, aput-object, aput-boolean, aput-byte, aput-char, aput-short
+ */
+ /* op vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ GET_VREG_R %eax %eax # eax<- vBB (array object)
+ GET_VREG_R %ecx %ecx # ecs<- vCC (requested index)
+ testl %eax,%eax # null array object?
+ je common_errNullObject # bail if so
+ cmpl offArrayObject_length(%eax),%ecx
+ jae common_errArrayIndex # index >= length, bail. Expects:
+ # arrayObj in eax
+ # index in ecx
+ leal offArrayObject_contents(%eax,%ecx,2),%eax
+.LOP_APUT_CHAR_finish:
+ GET_VREG_R rINST rINST
+ FETCH_INST_OPCODE 2 %ecx
+ movw rINSTw,(%eax)
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_APUT_SHORT: /* 0x51 */
+/* File: x86/OP_APUT_SHORT.S */
+/* File: x86/OP_APUT.S */
+ /*
+ * Array put, 32 bits or less. vBB[vCC] <- vAA
+ *
+ * for: aput, aput-object, aput-boolean, aput-byte, aput-char, aput-short
+ */
+ /* op vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ GET_VREG_R %eax %eax # eax<- vBB (array object)
+ GET_VREG_R %ecx %ecx # ecs<- vCC (requested index)
+ testl %eax,%eax # null array object?
+ je common_errNullObject # bail if so
+ cmpl offArrayObject_length(%eax),%ecx
+ jae common_errArrayIndex # index >= length, bail. Expects:
+ # arrayObj in eax
+ # index in ecx
+ leal offArrayObject_contents(%eax,%ecx,2),%eax
+.LOP_APUT_SHORT_finish:
+ GET_VREG_R rINST rINST
+ FETCH_INST_OPCODE 2 %ecx
+ movw rINSTw,(%eax)
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_IGET: /* 0x52 */
+/* File: x86/OP_IGET.S */
+ /*
+ * General 32-bit instance field get.
+ *
+ * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
+ */
+ /* op vA, vB, field@CCCC */
+ movl rSELF,%ecx
+ SPILL(rIBASE) # preserve rIBASE
+ movzwl 2(rPC),rIBASE # rIBASE<- 0000CCCC
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IGET_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp) # needed by dvmResolveInstField
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -9846,19 +2586,37 @@
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
movl (%ecx,%eax,1),%ecx # ecx<- obj.field (8/16/32 bits)
- movl rINST,%eax # eax<- A
- FETCH_INST_OPCODE 2 %edx
- SET_VREG %ecx %eax
+ FETCH_INST_OPCODE 2 %eax
+ UNSPILL(rIBASE)
+ SET_VREG %ecx rINST
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %eax
-/* continuation for OP_IGET_WIDE */
-
-
-.LOP_IGET_WIDE_resolve:
+/* ------------------------------ */
+.L_OP_IGET_WIDE: /* 0x53 */
+/* File: x86/OP_IGET_WIDE.S */
+ /*
+ * 64-bit instance field get.
+ *
+ */
+ /* op vA, vB, field@CCCC */
+ movl rSELF,%ecx
+ SPILL(rIBASE) # preserve rIBASE
+ movzwl 2(rPC),rIBASE # rIBASE<- 0000CCCC
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IGET_WIDE_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp) # for dvmResolveInstField
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save objpointer across call
movl rPC,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
@@ -9880,21 +2638,42 @@
leal (%ecx,%eax,1),%eax # eax<- address of field
movl (%eax),%ecx # ecx<- lsw
movl 4(%eax),%eax # eax<- msw
- FETCH_INST_OPCODE 2 %edx
SET_VREG_WORD %ecx rINST 0
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE) # restore rIBASE
SET_VREG_WORD %eax rINST 1
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_IGET_OBJECT */
-
-
-.LOP_IGET_OBJECT_resolve:
+/* ------------------------------ */
+.L_OP_IGET_OBJECT: /* 0x54 */
+/* File: x86/OP_IGET_OBJECT.S */
+/* File: x86/OP_IGET.S */
+ /*
+ * General 32-bit instance field get.
+ *
+ * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
+ */
+ /* op vA, vB, field@CCCC */
+ movl rSELF,%ecx
+ SPILL(rIBASE) # preserve rIBASE
+ movzwl 2(rPC),rIBASE # rIBASE<- 0000CCCC
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IGET_OBJECT_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp) # needed by dvmResolveInstField
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -9912,21 +2691,42 @@
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
movl (%ecx,%eax,1),%ecx # ecx<- obj.field (8/16/32 bits)
- movl rINST,%eax # eax<- A
- FETCH_INST_OPCODE 2 %edx
- SET_VREG %ecx %eax
+ FETCH_INST_OPCODE 2 %eax
+ UNSPILL(rIBASE)
+ SET_VREG %ecx rINST
ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-/* continuation for OP_IGET_BOOLEAN */
+ GOTO_NEXT_R %eax
-.LOP_IGET_BOOLEAN_resolve:
+/* ------------------------------ */
+.L_OP_IGET_BOOLEAN: /* 0x55 */
+/* File: x86/OP_IGET_BOOLEAN.S */
+/* File: x86/OP_IGET.S */
+ /*
+ * General 32-bit instance field get.
+ *
+ * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
+ */
+ /* op vA, vB, field@CCCC */
+ movl rSELF,%ecx
+ SPILL(rIBASE) # preserve rIBASE
+ movzwl 2(rPC),rIBASE # rIBASE<- 0000CCCC
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IGET_BOOLEAN_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp) # needed by dvmResolveInstField
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -9944,21 +2744,42 @@
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
movzbl (%ecx,%eax,1),%ecx # ecx<- obj.field (8/16/32 bits)
- movl rINST,%eax # eax<- A
- FETCH_INST_OPCODE 2 %edx
- SET_VREG %ecx %eax
+ FETCH_INST_OPCODE 2 %eax
+ UNSPILL(rIBASE)
+ SET_VREG %ecx rINST
ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-/* continuation for OP_IGET_BYTE */
+ GOTO_NEXT_R %eax
-.LOP_IGET_BYTE_resolve:
+/* ------------------------------ */
+.L_OP_IGET_BYTE: /* 0x56 */
+/* File: x86/OP_IGET_BYTE.S */
+/* File: x86/OP_IGET.S */
+ /*
+ * General 32-bit instance field get.
+ *
+ * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
+ */
+ /* op vA, vB, field@CCCC */
+ movl rSELF,%ecx
+ SPILL(rIBASE) # preserve rIBASE
+ movzwl 2(rPC),rIBASE # rIBASE<- 0000CCCC
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IGET_BYTE_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp) # needed by dvmResolveInstField
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -9976,21 +2797,42 @@
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
movsbl (%ecx,%eax,1),%ecx # ecx<- obj.field (8/16/32 bits)
- movl rINST,%eax # eax<- A
- FETCH_INST_OPCODE 2 %edx
- SET_VREG %ecx %eax
+ FETCH_INST_OPCODE 2 %eax
+ UNSPILL(rIBASE)
+ SET_VREG %ecx rINST
ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-/* continuation for OP_IGET_CHAR */
+ GOTO_NEXT_R %eax
-.LOP_IGET_CHAR_resolve:
+/* ------------------------------ */
+.L_OP_IGET_CHAR: /* 0x57 */
+/* File: x86/OP_IGET_CHAR.S */
+/* File: x86/OP_IGET.S */
+ /*
+ * General 32-bit instance field get.
+ *
+ * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
+ */
+ /* op vA, vB, field@CCCC */
+ movl rSELF,%ecx
+ SPILL(rIBASE) # preserve rIBASE
+ movzwl 2(rPC),rIBASE # rIBASE<- 0000CCCC
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IGET_CHAR_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp) # needed by dvmResolveInstField
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -10008,21 +2850,42 @@
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
movzwl (%ecx,%eax,1),%ecx # ecx<- obj.field (8/16/32 bits)
- movl rINST,%eax # eax<- A
- FETCH_INST_OPCODE 2 %edx
- SET_VREG %ecx %eax
+ FETCH_INST_OPCODE 2 %eax
+ UNSPILL(rIBASE)
+ SET_VREG %ecx rINST
ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-/* continuation for OP_IGET_SHORT */
+ GOTO_NEXT_R %eax
-.LOP_IGET_SHORT_resolve:
+/* ------------------------------ */
+.L_OP_IGET_SHORT: /* 0x58 */
+/* File: x86/OP_IGET_SHORT.S */
+/* File: x86/OP_IGET.S */
+ /*
+ * General 32-bit instance field get.
+ *
+ * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
+ */
+ /* op vA, vB, field@CCCC */
+ movl rSELF,%ecx
+ SPILL(rIBASE) # preserve rIBASE
+ movzwl 2(rPC),rIBASE # rIBASE<- 0000CCCC
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IGET_SHORT_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp) # needed by dvmResolveInstField
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -10040,21 +2903,42 @@
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
movswl (%ecx,%eax,1),%ecx # ecx<- obj.field (8/16/32 bits)
- movl rINST,%eax # eax<- A
- FETCH_INST_OPCODE 2 %edx
- SET_VREG %ecx %eax
+ FETCH_INST_OPCODE 2 %eax
+ UNSPILL(rIBASE)
+ SET_VREG %ecx rINST
ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-/* continuation for OP_IPUT */
+ GOTO_NEXT_R %eax
-.LOP_IPUT_resolve:
+/* ------------------------------ */
+.L_OP_IPUT: /* 0x59 */
+/* File: x86/OP_IPUT.S */
+
+ /*
+ * General 32-bit instance field put.
+ *
+ * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short
+ */
+ /* op vA, vB, field@CCCC */
+ movl rSELF,%ecx
+ SPILL (rIBASE)
+ movzwl 2(rPC),rIBASE # rIBASE<- 0000CCCC
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IPUT_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp)
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -10072,20 +2956,39 @@
movl offInstField_byteOffset(%eax),%eax # eax<- byte offset of field
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
- FETCH_INST_OPCODE 2 %edx
movl rINST,(%ecx,%eax,1) # obj.field <- v[A](8/16/32 bits)
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_IPUT_WIDE */
-
-
-.LOP_IPUT_WIDE_resolve:
+/* ------------------------------ */
+.L_OP_IPUT_WIDE: /* 0x5a */
+/* File: x86/OP_IPUT_WIDE.S */
+ /*
+ * 64-bit instance field put.
+ *
+ */
+ /* op vA, vB, field@CCCC */
+ movl rSELF,%ecx
+ SPILL(rIBASE)
+ movzwl 2(rPC),rIBASE # rIBASE<- 0000CCCC
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IPUT_WIDE_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp)
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # ... which returns InstrField ptr
@@ -10097,7 +3000,7 @@
* Currently:
* eax holds resolved field
* ecx holds object
- * %edx is scratch, but needs to be unspilled
+ * rIBASE is scratch, but needs to be unspilled
* rINST holds A
*/
movl offInstField_byteOffset(%eax),%eax # eax<- byte offset of field
@@ -10106,21 +3009,41 @@
leal (%ecx,%eax,1),%eax # eax<- address of field
GET_VREG_WORD %ecx rINST 0 # ecx<- lsw
GET_VREG_WORD rINST rINST 1 # rINST<- msw
- FETCH_INST_OPCODE 2 %edx
movl rINST,4(%eax)
movl %ecx,(%eax)
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_IPUT_OBJECT */
-
-
-.LOP_IPUT_OBJECT_resolve:
+/* ------------------------------ */
+.L_OP_IPUT_OBJECT: /* 0x5b */
+/* File: x86/OP_IPUT_OBJECT.S */
+ /*
+ * Object field put.
+ *
+ * for: iput-object
+ */
+ /* op vA, vB, field@CCCC */
+ movl rSELF,%ecx
+ SPILL(rIBASE)
+ movzwl 2(rPC),rIBASE # rIBASE<- 0000CCCC
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IPUT_OBJECT_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp)
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -10132,7 +3055,7 @@
* Currently:
* eax holds resolved field
* ecx holds object
- * %edx is scratch, but needs to be unspilled
+ * rIBASE is scratch, but needs to be unspilled
* rINST holds A
*/
GET_VREG_R rINST rINST # rINST<- v[A]
@@ -10142,24 +3065,46 @@
movl rINST,(%ecx,%eax) # obj.field <- v[A](8/16/32 bits)
movl rSELF,%eax
testl rINST,rINST # stored a NULL?
- movl offThread_cardTable(%eax),%eax # get card table base
- FETCH_INST_OPCODE 2 %edx
+ movl offThread_cardTable(%eax),%eax # get card table base
je 1f # skip card mark if null store
shrl $GC_CARD_SHIFT,%ecx # object head to card number
movb %al,(%eax,%ecx) # mark card using object head
1:
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_IPUT_BOOLEAN */
+/* ------------------------------ */
+.L_OP_IPUT_BOOLEAN: /* 0x5c */
+/* File: x86/OP_IPUT_BOOLEAN.S */
+/* File: x86/OP_IPUT.S */
-
-.LOP_IPUT_BOOLEAN_resolve:
+ /*
+ * General 32-bit instance field put.
+ *
+ * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short
+ */
+ /* op vA, vB, field@CCCC */
+ movl rSELF,%ecx
+ SPILL (rIBASE)
+ movzwl 2(rPC),rIBASE # rIBASE<- 0000CCCC
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IPUT_BOOLEAN_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp)
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -10177,20 +3122,43 @@
movl offInstField_byteOffset(%eax),%eax # eax<- byte offset of field
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
- FETCH_INST_OPCODE 2 %edx
movb rINSTbl,(%ecx,%eax,1) # obj.field <- v[A](8/16/32 bits)
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-/* continuation for OP_IPUT_BYTE */
+ GOTO_NEXT_R %ecx
-.LOP_IPUT_BYTE_resolve:
+/* ------------------------------ */
+.L_OP_IPUT_BYTE: /* 0x5d */
+/* File: x86/OP_IPUT_BYTE.S */
+/* File: x86/OP_IPUT.S */
+
+ /*
+ * General 32-bit instance field put.
+ *
+ * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short
+ */
+ /* op vA, vB, field@CCCC */
+ movl rSELF,%ecx
+ SPILL (rIBASE)
+ movzwl 2(rPC),rIBASE # rIBASE<- 0000CCCC
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IPUT_BYTE_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp)
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -10208,20 +3176,43 @@
movl offInstField_byteOffset(%eax),%eax # eax<- byte offset of field
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
- FETCH_INST_OPCODE 2 %edx
movb rINSTbl,(%ecx,%eax,1) # obj.field <- v[A](8/16/32 bits)
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-/* continuation for OP_IPUT_CHAR */
+ GOTO_NEXT_R %ecx
-.LOP_IPUT_CHAR_resolve:
+/* ------------------------------ */
+.L_OP_IPUT_CHAR: /* 0x5e */
+/* File: x86/OP_IPUT_CHAR.S */
+/* File: x86/OP_IPUT.S */
+
+ /*
+ * General 32-bit instance field put.
+ *
+ * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short
+ */
+ /* op vA, vB, field@CCCC */
+ movl rSELF,%ecx
+ SPILL (rIBASE)
+ movzwl 2(rPC),rIBASE # rIBASE<- 0000CCCC
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IPUT_CHAR_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp)
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -10239,20 +3230,43 @@
movl offInstField_byteOffset(%eax),%eax # eax<- byte offset of field
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
- FETCH_INST_OPCODE 2 %edx
movw rINSTw,(%ecx,%eax,1) # obj.field <- v[A](8/16/32 bits)
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-/* continuation for OP_IPUT_SHORT */
+ GOTO_NEXT_R %ecx
-.LOP_IPUT_SHORT_resolve:
+/* ------------------------------ */
+.L_OP_IPUT_SHORT: /* 0x5f */
+/* File: x86/OP_IPUT_SHORT.S */
+/* File: x86/OP_IPUT.S */
+
+ /*
+ * General 32-bit instance field put.
+ *
+ * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short
+ */
+ /* op vA, vB, field@CCCC */
+ movl rSELF,%ecx
+ SPILL (rIBASE)
+ movzwl 2(rPC),rIBASE # rIBASE<- 0000CCCC
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IPUT_SHORT_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp)
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -10270,12 +3284,35 @@
movl offInstField_byteOffset(%eax),%eax # eax<- byte offset of field
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
- FETCH_INST_OPCODE 2 %edx
movw rINSTw,(%ecx,%eax,1) # obj.field <- v[A](8/16/32 bits)
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_SGET */
+
+/* ------------------------------ */
+.L_OP_SGET: /* 0x60 */
+/* File: x86/OP_SGET.S */
+ /*
+ * General 32-bit SGET handler.
+ *
+ * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
+ */
+ /* op vAA, field@BBBB */
+ movl rSELF,%ecx
+ movzwl 2(rPC),%eax # eax<- field ref BBBB
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SGET_resolve # if not, make it so
+.LOP_SGET_finish: # field ptr in eax
+ movl offStaticField_value(%eax),%eax
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ SET_VREG %eax rINST
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -10288,12 +3325,36 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SGET_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_SGET_WIDE */
+/* ------------------------------ */
+.L_OP_SGET_WIDE: /* 0x61 */
+/* File: x86/OP_SGET_WIDE.S */
+ /*
+ * 64-bit SGET handler.
+ *
+ */
+ /* sget-wide vAA, field@BBBB */
+ movl rSELF,%ecx
+ movzwl 2(rPC),%eax # eax<- field ref BBBB
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SGET_WIDE_resolve # if not, make it so
+.LOP_SGET_WIDE_finish: # field ptr in eax
+ movl offStaticField_value(%eax),%ecx # ecx<- lsw
+ movl 4+offStaticField_value(%eax),%eax # eax<- msw
+ SET_VREG_WORD %ecx rINST 0
+ FETCH_INST_OPCODE 2 %ecx
+ SET_VREG_WORD %eax rINST 1
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -10306,12 +3367,36 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SGET_WIDE_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_SGET_OBJECT */
+/* ------------------------------ */
+.L_OP_SGET_OBJECT: /* 0x62 */
+/* File: x86/OP_SGET_OBJECT.S */
+/* File: x86/OP_SGET.S */
+ /*
+ * General 32-bit SGET handler.
+ *
+ * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
+ */
+ /* op vAA, field@BBBB */
+ movl rSELF,%ecx
+ movzwl 2(rPC),%eax # eax<- field ref BBBB
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SGET_OBJECT_resolve # if not, make it so
+.LOP_SGET_OBJECT_finish: # field ptr in eax
+ movl offStaticField_value(%eax),%eax
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ SET_VREG %eax rINST
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -10324,12 +3409,37 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SGET_OBJECT_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_SGET_BOOLEAN */
+
+/* ------------------------------ */
+.L_OP_SGET_BOOLEAN: /* 0x63 */
+/* File: x86/OP_SGET_BOOLEAN.S */
+/* File: x86/OP_SGET.S */
+ /*
+ * General 32-bit SGET handler.
+ *
+ * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
+ */
+ /* op vAA, field@BBBB */
+ movl rSELF,%ecx
+ movzwl 2(rPC),%eax # eax<- field ref BBBB
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SGET_BOOLEAN_resolve # if not, make it so
+.LOP_SGET_BOOLEAN_finish: # field ptr in eax
+ movl offStaticField_value(%eax),%eax
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ SET_VREG %eax rINST
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -10342,12 +3452,37 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SGET_BOOLEAN_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_SGET_BYTE */
+
+/* ------------------------------ */
+.L_OP_SGET_BYTE: /* 0x64 */
+/* File: x86/OP_SGET_BYTE.S */
+/* File: x86/OP_SGET.S */
+ /*
+ * General 32-bit SGET handler.
+ *
+ * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
+ */
+ /* op vAA, field@BBBB */
+ movl rSELF,%ecx
+ movzwl 2(rPC),%eax # eax<- field ref BBBB
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SGET_BYTE_resolve # if not, make it so
+.LOP_SGET_BYTE_finish: # field ptr in eax
+ movl offStaticField_value(%eax),%eax
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ SET_VREG %eax rINST
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -10360,12 +3495,37 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SGET_BYTE_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_SGET_CHAR */
+
+/* ------------------------------ */
+.L_OP_SGET_CHAR: /* 0x65 */
+/* File: x86/OP_SGET_CHAR.S */
+/* File: x86/OP_SGET.S */
+ /*
+ * General 32-bit SGET handler.
+ *
+ * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
+ */
+ /* op vAA, field@BBBB */
+ movl rSELF,%ecx
+ movzwl 2(rPC),%eax # eax<- field ref BBBB
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SGET_CHAR_resolve # if not, make it so
+.LOP_SGET_CHAR_finish: # field ptr in eax
+ movl offStaticField_value(%eax),%eax
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ SET_VREG %eax rINST
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -10378,12 +3538,37 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SGET_CHAR_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_SGET_SHORT */
+
+/* ------------------------------ */
+.L_OP_SGET_SHORT: /* 0x66 */
+/* File: x86/OP_SGET_SHORT.S */
+/* File: x86/OP_SGET.S */
+ /*
+ * General 32-bit SGET handler.
+ *
+ * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
+ */
+ /* op vAA, field@BBBB */
+ movl rSELF,%ecx
+ movzwl 2(rPC),%eax # eax<- field ref BBBB
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SGET_SHORT_resolve # if not, make it so
+.LOP_SGET_SHORT_finish: # field ptr in eax
+ movl offStaticField_value(%eax),%eax
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ SET_VREG %eax rINST
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -10396,12 +3581,36 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SGET_SHORT_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_SPUT */
+
+/* ------------------------------ */
+.L_OP_SPUT: /* 0x67 */
+/* File: x86/OP_SPUT.S */
+ /*
+ * General 32-bit SPUT handler.
+ *
+ * for: sput, sput-boolean, sput-byte, sput-char, sput-short
+ */
+ /* op vAA, field@BBBB */
+ movl rSELF,%ecx
+ movzwl 2(rPC),%eax # eax<- field ref BBBB
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SPUT_resolve # if not, make it so
+.LOP_SPUT_finish: # field ptr in eax
+ GET_VREG_R rINST rINST
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ movl rINST,offStaticField_value(%eax)
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -10414,12 +3623,37 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SPUT_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_SPUT_WIDE */
+/* ------------------------------ */
+.L_OP_SPUT_WIDE: /* 0x68 */
+/* File: x86/OP_SPUT_WIDE.S */
+ /*
+ * General 32-bit SPUT handler.
+ *
+ * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short
+ */
+ /* op vAA, field@BBBB */
+ movl rSELF,%ecx
+ movzwl 2(rPC),%eax # eax<- field ref BBBB
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SPUT_WIDE_resolve # if not, make it so
+.LOP_SPUT_WIDE_finish: # field ptr in eax
+ GET_VREG_WORD %ecx rINST 0 # rINST<- lsw
+ GET_VREG_WORD rINST rINST 1 # ecx<- msw
+ movl %ecx,offStaticField_value(%eax)
+ FETCH_INST_OPCODE 2 %ecx
+ movl rINST,4+offStaticField_value(%eax)
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -10432,18 +3666,32 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SPUT_WIDE_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_SPUT_OBJECT */
-
-
-.LOP_SPUT_OBJECT_continue:
+/* ------------------------------ */
+.L_OP_SPUT_OBJECT: /* 0x69 */
+/* File: x86/OP_SPUT_OBJECT.S */
+ /*
+ * SPUT object handler.
+ */
+ /* op vAA, field@BBBB */
+ movl rSELF,%ecx
+ movzwl 2(rPC),%eax # eax<- field ref BBBB
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SPUT_OBJECT_resolve # if not, make it so
+.LOP_SPUT_OBJECT_finish: # field ptr in eax
+ movzbl rINSTbl,%ecx # ecx<- AA
+ GET_VREG_R %ecx %ecx
movl %ecx,offStaticField_value(%eax) # do the store
testl %ecx,%ecx # stored null object ptr?
- FETCH_INST_OPCODE 2 %edx
je 1f # skip card mark if null
movl rSELF,%ecx
movl offField_clazz(%eax),%eax # eax<- method->clazz
@@ -10451,8 +3699,9 @@
shrl $GC_CARD_SHIFT,%eax # head to card number
movb %cl,(%ecx,%eax) # mark card
1:
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
.LOP_SPUT_OBJECT_resolve:
movl rSELF,%ecx
@@ -10462,12 +3711,36 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SPUT_OBJECT_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_SPUT_BOOLEAN */
+/* ------------------------------ */
+.L_OP_SPUT_BOOLEAN: /* 0x6a */
+/* File: x86/OP_SPUT_BOOLEAN.S */
+/* File: x86/OP_SPUT.S */
+ /*
+ * General 32-bit SPUT handler.
+ *
+ * for: sput, sput-boolean, sput-byte, sput-char, sput-short
+ */
+ /* op vAA, field@BBBB */
+ movl rSELF,%ecx
+ movzwl 2(rPC),%eax # eax<- field ref BBBB
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SPUT_BOOLEAN_resolve # if not, make it so
+.LOP_SPUT_BOOLEAN_finish: # field ptr in eax
+ GET_VREG_R rINST rINST
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ movl rINST,offStaticField_value(%eax)
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -10480,12 +3753,37 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SPUT_BOOLEAN_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_SPUT_BYTE */
+
+/* ------------------------------ */
+.L_OP_SPUT_BYTE: /* 0x6b */
+/* File: x86/OP_SPUT_BYTE.S */
+/* File: x86/OP_SPUT.S */
+ /*
+ * General 32-bit SPUT handler.
+ *
+ * for: sput, sput-boolean, sput-byte, sput-char, sput-short
+ */
+ /* op vAA, field@BBBB */
+ movl rSELF,%ecx
+ movzwl 2(rPC),%eax # eax<- field ref BBBB
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SPUT_BYTE_resolve # if not, make it so
+.LOP_SPUT_BYTE_finish: # field ptr in eax
+ GET_VREG_R rINST rINST
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ movl rINST,offStaticField_value(%eax)
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -10498,12 +3796,37 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SPUT_BYTE_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_SPUT_CHAR */
+
+/* ------------------------------ */
+.L_OP_SPUT_CHAR: /* 0x6c */
+/* File: x86/OP_SPUT_CHAR.S */
+/* File: x86/OP_SPUT.S */
+ /*
+ * General 32-bit SPUT handler.
+ *
+ * for: sput, sput-boolean, sput-byte, sput-char, sput-short
+ */
+ /* op vAA, field@BBBB */
+ movl rSELF,%ecx
+ movzwl 2(rPC),%eax # eax<- field ref BBBB
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SPUT_CHAR_resolve # if not, make it so
+.LOP_SPUT_CHAR_finish: # field ptr in eax
+ GET_VREG_R rINST rINST
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ movl rINST,offStaticField_value(%eax)
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -10516,12 +3839,37 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SPUT_CHAR_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_SPUT_SHORT */
+
+/* ------------------------------ */
+.L_OP_SPUT_SHORT: /* 0x6d */
+/* File: x86/OP_SPUT_SHORT.S */
+/* File: x86/OP_SPUT.S */
+ /*
+ * General 32-bit SPUT handler.
+ *
+ * for: sput, sput-boolean, sput-byte, sput-char, sput-short
+ */
+ /* op vAA, field@BBBB */
+ movl rSELF,%ecx
+ movzwl 2(rPC),%eax # eax<- field ref BBBB
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SPUT_SHORT_resolve # if not, make it so
+.LOP_SPUT_SHORT_finish: # field ptr in eax
+ GET_VREG_R rINST rINST
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ movl rINST,offStaticField_value(%eax)
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -10534,15 +3882,36 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SPUT_SHORT_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_INVOKE_VIRTUAL */
+/* ------------------------------ */
+.L_OP_INVOKE_VIRTUAL: /* 0x6e */
+/* File: x86/OP_INVOKE_VIRTUAL.S */
-.LOP_INVOKE_VIRTUAL_more:
+ /*
+ * Handle a virtual method call.
+ *
+ * for: invoke-virtual, invoke-virtual/range
+ */
+ /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
+ /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
+ movl rSELF,%eax
+ movzwl 2(rPC),%ecx # ecx<- BBBB
+ movl offThread_methodClassDex(%eax),%eax # eax<- pDvmDex
+ EXPORT_PC
+ movl offDvmDex_pResMethods(%eax),%eax # eax<- pDvmDex->pResMethods
+ movl (%eax,%ecx,4),%eax # eax<- resolved baseMethod
+ testl %eax,%eax # already resolved?
+ jne .LOP_INVOKE_VIRTUAL_continue # yes, continue
+ movl rSELF,%eax
+ movl %ecx,OUT_ARG1(%esp) # arg1<- ref
+ movl offThread_method(%eax),%eax # eax<- self->method
movl offMethod_clazz(%eax),%eax # ecx<- method->clazz
movl %eax,OUT_ARG0(%esp) # arg0<- clazz
movl $METHOD_VIRTUAL,OUT_ARG2(%esp) # arg2<- flags
@@ -10569,8 +3938,33 @@
movl (%ecx,%eax,4),%eax # eax<- vtable[methodIndex]
jmp common_invokeMethodNoRange
-/* continuation for OP_INVOKE_SUPER */
-
+/* ------------------------------ */
+.L_OP_INVOKE_SUPER: /* 0x6f */
+/* File: x86/OP_INVOKE_SUPER.S */
+ /*
+ * Handle a "super" method call.
+ *
+ * for: invoke-super, invoke-super/range
+ */
+ /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
+ /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
+ movl rSELF,rINST
+ movzwl 2(rPC),%eax # eax<- BBBB
+ movl offThread_methodClassDex(rINST),%ecx # ecx<- pDvmDex
+ EXPORT_PC
+ movl offDvmDex_pResMethods(%ecx),%ecx # ecx<- pDvmDex->pResMethods
+ movl (%ecx,%eax,4),%ecx # ecx<- resolved baseMethod
+ movl offThread_method(rINST),%eax # eax<- method
+ movzwl 4(rPC),rINST # rINST<- GFED or CCCC
+ .if (!0)
+ andl $0xf,rINST # rINST<- D (or stays CCCC)
+ .endif
+ GET_VREG_R rINST rINST # rINST<- "this" ptr
+ testl rINST,rINST # null "this"?
+ je common_errNullObject # yes, throw
+ movl offMethod_clazz(%eax),%eax # eax<- method->clazz
+ testl %ecx,%ecx # already resolved?
+ je .LOP_INVOKE_SUPER_resolve
/*
* At this point:
* ecx = resolved base method [r0]
@@ -10612,7 +4006,38 @@
mov %eax,OUT_ARG1(%esp)
jmp common_errNoSuchMethod
-/* continuation for OP_INVOKE_DIRECT */
+/* ------------------------------ */
+.L_OP_INVOKE_DIRECT: /* 0x70 */
+/* File: x86/OP_INVOKE_DIRECT.S */
+ /*
+ * Handle a direct method call.
+ *
+ * (We could defer the "is 'this' pointer null" test to the common
+ * method invocation code, and use a flag to indicate that static
+ * calls don't count. If we do this as part of copying the arguments
+ * out we could avoiding loading the first arg twice.)
+ *
+ * for: invoke-direct, invoke-direct/range
+ */
+ /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
+ /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
+ movl rSELF,%ecx
+ movzwl 2(rPC),%eax # eax<- BBBB
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
+ EXPORT_PC
+ movl offDvmDex_pResMethods(%ecx),%ecx # ecx<- pDvmDex->pResMethods
+ movzwl 4(rPC),rIBASE # rIBASE<- GFED or CCCC
+ movl (%ecx,%eax,4),%eax # eax<- resolved methodToCall
+ .if (!0)
+ andl $0xf,rIBASE # rIBASE<- D (or stays CCCC)
+ .endif
+ testl %eax,%eax # already resolved?
+ GET_VREG_R %ecx rIBASE # ecx<- "this" ptr
+ je .LOP_INVOKE_DIRECT_resolve # not resolved, do it now
+.LOP_INVOKE_DIRECT_finish:
+ testl %ecx,%ecx # null "this"?
+ jne common_invokeMethodNoRange # no, continue on
+ jmp common_errNullObject
/*
* On entry:
@@ -10635,9 +4060,30 @@
jne .LOP_INVOKE_DIRECT_finish
jmp common_exceptionThrown
-/* continuation for OP_INVOKE_STATIC */
-
-.LOP_INVOKE_STATIC_continue:
+/* ------------------------------ */
+.L_OP_INVOKE_STATIC: /* 0x71 */
+/* File: x86/OP_INVOKE_STATIC.S */
+ /*
+ * Handle a static method call.
+ *
+ * for: invoke-static, invoke-static/range
+ */
+ /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
+ /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
+ movl rSELF,%ecx
+ movzwl 2(rPC),%eax # eax<- BBBB
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
+ EXPORT_PC
+ movl offDvmDex_pResMethods(%ecx),%ecx # ecx<- pDvmDex->pResMethods
+ movl (%ecx,%eax,4),%eax # eax<- resolved methodToCall
+ testl %eax,%eax
+ jne common_invokeMethodNoRange
+ movl rSELF,%ecx
+ movl offThread_method(%ecx),%ecx # ecx<- self->method
+ movzwl 2(rPC),%eax
+ movl offMethod_clazz(%ecx),%ecx# ecx<- method->clazz
+ movl %eax,OUT_ARG1(%esp) # arg1<- BBBB
+ movl %ecx,OUT_ARG0(%esp) # arg0<- clazz
movl $METHOD_STATIC,%eax
movl %eax,OUT_ARG2(%esp) # arg2<- flags
call dvmResolveMethod # call(clazz,ref,flags)
@@ -10645,18 +4091,68 @@
jne common_invokeMethodNoRange
jmp common_exceptionThrown
-/* continuation for OP_INVOKE_INTERFACE */
-
-.LOP_INVOKE_INTERFACE_continue:
+/* ------------------------------ */
+.L_OP_INVOKE_INTERFACE: /* 0x72 */
+/* File: x86/OP_INVOKE_INTERFACE.S */
+ /*
+ * Handle an interface method call.
+ *
+ * for: invoke-interface, invoke-interface/range
+ */
+ /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
+ /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
+ movzwl 4(rPC),%eax # eax<- FEDC or CCCC
+ movl rSELF,%ecx
+ .if (!0)
+ andl $0xf,%eax # eax<- C (or stays CCCC)
+ .endif
+ GET_VREG_R %eax %eax # eax<- "this"
+ EXPORT_PC
+ testl %eax,%eax # null this?
+ je common_errNullObject # yes, fail
+ movl offObject_clazz(%eax),%eax# eax<- thisPtr->clazz
+ movl %eax,OUT_ARG0(%esp) # arg0<- class
+ movl offThread_methodClassDex(%ecx),%eax # eax<- methodClassDex
+ movl offThread_method(%ecx),%ecx # ecx<- method
+ movl %eax,OUT_ARG3(%esp) # arg3<- dex
+ movzwl 2(rPC),%eax # eax<- BBBB
+ movl %ecx,OUT_ARG2(%esp) # arg2<- method
+ movl %eax,OUT_ARG1(%esp) # arg1<- BBBB
call dvmFindInterfaceMethodInCache # eax<- call(class, ref, method, dex)
testl %eax,%eax
je common_exceptionThrown
jmp common_invokeMethodNoRange
-/* continuation for OP_INVOKE_VIRTUAL_RANGE */
+/* ------------------------------ */
+.L_OP_UNUSED_73: /* 0x73 */
+/* File: x86/OP_UNUSED_73.S */
+/* File: x86/unused.S */
+ jmp common_abort
-.LOP_INVOKE_VIRTUAL_RANGE_more:
+/* ------------------------------ */
+.L_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */
+/* File: x86/OP_INVOKE_VIRTUAL_RANGE.S */
+/* File: x86/OP_INVOKE_VIRTUAL.S */
+
+ /*
+ * Handle a virtual method call.
+ *
+ * for: invoke-virtual, invoke-virtual/range
+ */
+ /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
+ /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
+ movl rSELF,%eax
+ movzwl 2(rPC),%ecx # ecx<- BBBB
+ movl offThread_methodClassDex(%eax),%eax # eax<- pDvmDex
+ EXPORT_PC
+ movl offDvmDex_pResMethods(%eax),%eax # eax<- pDvmDex->pResMethods
+ movl (%eax,%ecx,4),%eax # eax<- resolved baseMethod
+ testl %eax,%eax # already resolved?
+ jne .LOP_INVOKE_VIRTUAL_RANGE_continue # yes, continue
+ movl rSELF,%eax
+ movl %ecx,OUT_ARG1(%esp) # arg1<- ref
+ movl offThread_method(%eax),%eax # eax<- self->method
movl offMethod_clazz(%eax),%eax # ecx<- method->clazz
movl %eax,OUT_ARG0(%esp) # arg0<- clazz
movl $METHOD_VIRTUAL,OUT_ARG2(%esp) # arg2<- flags
@@ -10683,8 +4179,35 @@
movl (%ecx,%eax,4),%eax # eax<- vtable[methodIndex]
jmp common_invokeMethodRange
-/* continuation for OP_INVOKE_SUPER_RANGE */
+/* ------------------------------ */
+.L_OP_INVOKE_SUPER_RANGE: /* 0x75 */
+/* File: x86/OP_INVOKE_SUPER_RANGE.S */
+/* File: x86/OP_INVOKE_SUPER.S */
+ /*
+ * Handle a "super" method call.
+ *
+ * for: invoke-super, invoke-super/range
+ */
+ /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
+ /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
+ movl rSELF,rINST
+ movzwl 2(rPC),%eax # eax<- BBBB
+ movl offThread_methodClassDex(rINST),%ecx # ecx<- pDvmDex
+ EXPORT_PC
+ movl offDvmDex_pResMethods(%ecx),%ecx # ecx<- pDvmDex->pResMethods
+ movl (%ecx,%eax,4),%ecx # ecx<- resolved baseMethod
+ movl offThread_method(rINST),%eax # eax<- method
+ movzwl 4(rPC),rINST # rINST<- GFED or CCCC
+ .if (!1)
+ andl $0xf,rINST # rINST<- D (or stays CCCC)
+ .endif
+ GET_VREG_R rINST rINST # rINST<- "this" ptr
+ testl rINST,rINST # null "this"?
+ je common_errNullObject # yes, throw
+ movl offMethod_clazz(%eax),%eax # eax<- method->clazz
+ testl %ecx,%ecx # already resolved?
+ je .LOP_INVOKE_SUPER_RANGE_resolve
/*
* At this point:
* ecx = resolved base method [r0]
@@ -10726,7 +4249,40 @@
mov %eax,OUT_ARG1(%esp)
jmp common_errNoSuchMethod
-/* continuation for OP_INVOKE_DIRECT_RANGE */
+
+/* ------------------------------ */
+.L_OP_INVOKE_DIRECT_RANGE: /* 0x76 */
+/* File: x86/OP_INVOKE_DIRECT_RANGE.S */
+/* File: x86/OP_INVOKE_DIRECT.S */
+ /*
+ * Handle a direct method call.
+ *
+ * (We could defer the "is 'this' pointer null" test to the common
+ * method invocation code, and use a flag to indicate that static
+ * calls don't count. If we do this as part of copying the arguments
+ * out we could avoiding loading the first arg twice.)
+ *
+ * for: invoke-direct, invoke-direct/range
+ */
+ /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
+ /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
+ movl rSELF,%ecx
+ movzwl 2(rPC),%eax # eax<- BBBB
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
+ EXPORT_PC
+ movl offDvmDex_pResMethods(%ecx),%ecx # ecx<- pDvmDex->pResMethods
+ movzwl 4(rPC),rIBASE # rIBASE<- GFED or CCCC
+ movl (%ecx,%eax,4),%eax # eax<- resolved methodToCall
+ .if (!1)
+ andl $0xf,rIBASE # rIBASE<- D (or stays CCCC)
+ .endif
+ testl %eax,%eax # already resolved?
+ GET_VREG_R %ecx rIBASE # ecx<- "this" ptr
+ je .LOP_INVOKE_DIRECT_RANGE_resolve # not resolved, do it now
+.LOP_INVOKE_DIRECT_RANGE_finish:
+ testl %ecx,%ecx # null "this"?
+ jne common_invokeMethodRange # no, continue on
+ jmp common_errNullObject
/*
* On entry:
@@ -10749,9 +4305,32 @@
jne .LOP_INVOKE_DIRECT_RANGE_finish
jmp common_exceptionThrown
-/* continuation for OP_INVOKE_STATIC_RANGE */
-.LOP_INVOKE_STATIC_RANGE_continue:
+/* ------------------------------ */
+.L_OP_INVOKE_STATIC_RANGE: /* 0x77 */
+/* File: x86/OP_INVOKE_STATIC_RANGE.S */
+/* File: x86/OP_INVOKE_STATIC.S */
+ /*
+ * Handle a static method call.
+ *
+ * for: invoke-static, invoke-static/range
+ */
+ /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
+ /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
+ movl rSELF,%ecx
+ movzwl 2(rPC),%eax # eax<- BBBB
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
+ EXPORT_PC
+ movl offDvmDex_pResMethods(%ecx),%ecx # ecx<- pDvmDex->pResMethods
+ movl (%ecx,%eax,4),%eax # eax<- resolved methodToCall
+ testl %eax,%eax
+ jne common_invokeMethodRange
+ movl rSELF,%ecx
+ movl offThread_method(%ecx),%ecx # ecx<- self->method
+ movzwl 2(rPC),%eax
+ movl offMethod_clazz(%ecx),%ecx# ecx<- method->clazz
+ movl %eax,OUT_ARG1(%esp) # arg1<- BBBB
+ movl %ecx,OUT_ARG0(%esp) # arg0<- clazz
movl $METHOD_STATIC,%eax
movl %eax,OUT_ARG2(%esp) # arg2<- flags
call dvmResolveMethod # call(clazz,ref,flags)
@@ -10759,18 +4338,314 @@
jne common_invokeMethodRange
jmp common_exceptionThrown
-/* continuation for OP_INVOKE_INTERFACE_RANGE */
-.LOP_INVOKE_INTERFACE_RANGE_continue:
+/* ------------------------------ */
+.L_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */
+/* File: x86/OP_INVOKE_INTERFACE_RANGE.S */
+/* File: x86/OP_INVOKE_INTERFACE.S */
+ /*
+ * Handle an interface method call.
+ *
+ * for: invoke-interface, invoke-interface/range
+ */
+ /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
+ /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
+ movzwl 4(rPC),%eax # eax<- FEDC or CCCC
+ movl rSELF,%ecx
+ .if (!1)
+ andl $0xf,%eax # eax<- C (or stays CCCC)
+ .endif
+ GET_VREG_R %eax %eax # eax<- "this"
+ EXPORT_PC
+ testl %eax,%eax # null this?
+ je common_errNullObject # yes, fail
+ movl offObject_clazz(%eax),%eax# eax<- thisPtr->clazz
+ movl %eax,OUT_ARG0(%esp) # arg0<- class
+ movl offThread_methodClassDex(%ecx),%eax # eax<- methodClassDex
+ movl offThread_method(%ecx),%ecx # ecx<- method
+ movl %eax,OUT_ARG3(%esp) # arg3<- dex
+ movzwl 2(rPC),%eax # eax<- BBBB
+ movl %ecx,OUT_ARG2(%esp) # arg2<- method
+ movl %eax,OUT_ARG1(%esp) # arg1<- BBBB
call dvmFindInterfaceMethodInCache # eax<- call(class, ref, method, dex)
testl %eax,%eax
je common_exceptionThrown
jmp common_invokeMethodRange
-/* continuation for OP_FLOAT_TO_INT */
+
+/* ------------------------------ */
+.L_OP_UNUSED_79: /* 0x79 */
+/* File: x86/OP_UNUSED_79.S */
+/* File: x86/unused.S */
+ jmp common_abort
-.LOP_FLOAT_TO_INT_continue:
+/* ------------------------------ */
+.L_OP_UNUSED_7A: /* 0x7a */
+/* File: x86/OP_UNUSED_7A.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_NEG_INT: /* 0x7b */
+/* File: x86/OP_NEG_INT.S */
+/* File: x86/unop.S */
+ /*
+ * Generic 32-bit unary operation. Provide an "instr" line that
+ * specifies an instruction that performs "result = op eax".
+ */
+ /* unop vA, vB */
+ movzbl rINSTbl,%ecx # ecx<- A+
+ sarl $4,rINST # rINST<- B
+ GET_VREG_R %eax rINST # eax<- vB
+ andb $0xf,%cl # ecx<- A
+
+
+ negl %eax
+ SET_VREG %eax %ecx
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_NOT_INT: /* 0x7c */
+/* File: x86/OP_NOT_INT.S */
+/* File: x86/unop.S */
+ /*
+ * Generic 32-bit unary operation. Provide an "instr" line that
+ * specifies an instruction that performs "result = op eax".
+ */
+ /* unop vA, vB */
+ movzbl rINSTbl,%ecx # ecx<- A+
+ sarl $4,rINST # rINST<- B
+ GET_VREG_R %eax rINST # eax<- vB
+ andb $0xf,%cl # ecx<- A
+
+
+ notl %eax
+ SET_VREG %eax %ecx
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_NEG_LONG: /* 0x7d */
+/* File: x86/OP_NEG_LONG.S */
+ /* unop vA, vB */
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_WORD %eax %ecx 0 # eax<- v[B+0]
+ GET_VREG_WORD %ecx %ecx 1 # ecx<- v[B+1]
+ negl %eax
+ adcl $0,%ecx
+ negl %ecx
+ SET_VREG_WORD %eax rINST 0 # v[A+0]<- eax
+ FETCH_INST_OPCODE 1 %eax
+ SET_VREG_WORD %ecx rINST 1 # v[A+1]<- ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %eax
+
+/* ------------------------------ */
+.L_OP_NOT_LONG: /* 0x7e */
+/* File: x86/OP_NOT_LONG.S */
+ /* unop vA, vB */
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_WORD %eax %ecx 0 # eax<- v[B+0]
+ GET_VREG_WORD %ecx %ecx 1 # ecx<- v[B+1]
+ notl %eax
+ notl %ecx
+ SET_VREG_WORD %eax rINST 0 # v[A+0]<- eax
+ FETCH_INST_OPCODE 1 %eax
+ SET_VREG_WORD %ecx rINST 1 # v[A+1]<- ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %eax
+
+/* ------------------------------ */
+.L_OP_NEG_FLOAT: /* 0x7f */
+/* File: x86/OP_NEG_FLOAT.S */
+/* File: x86/fpcvt.S */
+ /*
+ * Generic 32-bit FP conversion operation.
+ */
+ /* unop vA, vB */
+ movzbl rINSTbl,%ecx # ecx<- A+
+ sarl $4,rINST # rINST<- B
+ flds (rFP,rINST,4) # %st0<- vB
+ andb $0xf,%cl # ecx<- A
+ fchs
+ fstps (rFP,%ecx,4) # vA<- %st0
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_NEG_DOUBLE: /* 0x80 */
+/* File: x86/OP_NEG_DOUBLE.S */
+/* File: x86/fpcvt.S */
+ /*
+ * Generic 32-bit FP conversion operation.
+ */
+ /* unop vA, vB */
+ movzbl rINSTbl,%ecx # ecx<- A+
+ sarl $4,rINST # rINST<- B
+ fldl (rFP,rINST,4) # %st0<- vB
+ andb $0xf,%cl # ecx<- A
+ fchs
+ fstpl (rFP,%ecx,4) # vA<- %st0
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_INT_TO_LONG: /* 0x81 */
+/* File: x86/OP_INT_TO_LONG.S */
+ /* int to long vA, vB */
+ movzbl rINSTbl,%eax # eax<- +A
+ sarl $4,%eax # eax<- B
+ GET_VREG_R %eax %eax # eax<- vB
+ andb $0xf,rINSTbl # rINST<- A
+ SPILL(rIBASE) # cltd trashes rIBASE/edx
+ cltd # rINST:eax<- sssssssBBBBBBBB
+ SET_VREG_WORD rIBASE rINST 1 # v[A+1]<- rIBASE/rPC
+ FETCH_INST_OPCODE 1 %ecx
+ UNSPILL(rIBASE)
+ SET_VREG_WORD %eax rINST 0 # v[A+0]<- %eax
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
+
+/* ------------------------------ */
+.L_OP_INT_TO_FLOAT: /* 0x82 */
+/* File: x86/OP_INT_TO_FLOAT.S */
+/* File: x86/fpcvt.S */
+ /*
+ * Generic 32-bit FP conversion operation.
+ */
+ /* unop vA, vB */
+ movzbl rINSTbl,%ecx # ecx<- A+
+ sarl $4,rINST # rINST<- B
+ fildl (rFP,rINST,4) # %st0<- vB
+ andb $0xf,%cl # ecx<- A
+
+ fstps (rFP,%ecx,4) # vA<- %st0
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_INT_TO_DOUBLE: /* 0x83 */
+/* File: x86/OP_INT_TO_DOUBLE.S */
+/* File: x86/fpcvt.S */
+ /*
+ * Generic 32-bit FP conversion operation.
+ */
+ /* unop vA, vB */
+ movzbl rINSTbl,%ecx # ecx<- A+
+ sarl $4,rINST # rINST<- B
+ fildl (rFP,rINST,4) # %st0<- vB
+ andb $0xf,%cl # ecx<- A
+
+ fstpl (rFP,%ecx,4) # vA<- %st0
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_LONG_TO_INT: /* 0x84 */
+/* File: x86/OP_LONG_TO_INT.S */
+/* we ignore the high word, making this equivalent to a 32-bit reg move */
+/* File: x86/OP_MOVE.S */
+ /* for move, move-object, long-to-int */
+ /* op vA, vB */
+ movzbl rINSTbl,%eax # eax<- BA
+ andb $0xf,%al # eax<- A
+ shrl $4,rINST # rINST<- B
+ GET_VREG_R rINST rINST
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ SET_VREG rINST %eax # fp[A]<-fp[B]
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_LONG_TO_FLOAT: /* 0x85 */
+/* File: x86/OP_LONG_TO_FLOAT.S */
+/* File: x86/fpcvt.S */
+ /*
+ * Generic 32-bit FP conversion operation.
+ */
+ /* unop vA, vB */
+ movzbl rINSTbl,%ecx # ecx<- A+
+ sarl $4,rINST # rINST<- B
+ fildll (rFP,rINST,4) # %st0<- vB
+ andb $0xf,%cl # ecx<- A
+
+ fstps (rFP,%ecx,4) # vA<- %st0
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_LONG_TO_DOUBLE: /* 0x86 */
+/* File: x86/OP_LONG_TO_DOUBLE.S */
+/* File: x86/fpcvt.S */
+ /*
+ * Generic 32-bit FP conversion operation.
+ */
+ /* unop vA, vB */
+ movzbl rINSTbl,%ecx # ecx<- A+
+ sarl $4,rINST # rINST<- B
+ fildll (rFP,rINST,4) # %st0<- vB
+ andb $0xf,%cl # ecx<- A
+
+ fstpl (rFP,%ecx,4) # vA<- %st0
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_FLOAT_TO_INT: /* 0x87 */
+/* File: x86/OP_FLOAT_TO_INT.S */
+/* File: x86/cvtfp_int.S */
+/* On fp to int conversions, Java requires that
+ * if the result > maxint, it should be clamped to maxint. If it is less
+ * than minint, it should be clamped to minint. If it is a nan, the result
+ * should be zero. Further, the rounding mode is to truncate. This model
+ * differs from what is delivered normally via the x86 fpu, so we have
+ * to play some games.
+ */
+ /* float/double to int/long vA, vB */
+ movzbl rINSTbl,%ecx # ecx<- A+
+ sarl $4,rINST # rINST<- B
+ .if 0
+ fldl (rFP,rINST,4) # %st0<- vB
+ .else
+ flds (rFP,rINST,4) # %st0<- vB
+ .endif
+ ftst
+ fnstcw LOCAL0_OFFSET(%ebp) # remember original rounding mode
+ movzwl LOCAL0_OFFSET(%ebp),%eax
+ movb $0xc,%ah
+ movw %ax,LOCAL0_OFFSET+2(%ebp)
+ fldcw LOCAL0_OFFSET+2(%ebp) # set "to zero" rounding mode
+ andb $0xf,%cl # ecx<- A
+ .if 0
+ fistpll (rFP,%ecx,4) # convert and store
+ .else
+ fistpl (rFP,%ecx,4) # convert and store
+ .endif
+ fldcw LOCAL0_OFFSET(%ebp) # restore previous rounding mode
.if 0
movl $0x80000000,%eax
xorl 4(rFP,%ecx,4),%eax
@@ -10781,8 +4656,9 @@
je .LOP_FLOAT_TO_INT_special_case # fix up result
.LOP_FLOAT_TO_INT_finish:
+ FETCH_INST_OPCODE 1 %ecx
ADVANCE_PC 1
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
.LOP_FLOAT_TO_INT_special_case:
fnstsw %ax
@@ -10800,10 +4676,39 @@
.endif
jmp .LOP_FLOAT_TO_INT_finish
-/* continuation for OP_FLOAT_TO_LONG */
-
-.LOP_FLOAT_TO_LONG_continue:
+/* ------------------------------ */
+.L_OP_FLOAT_TO_LONG: /* 0x88 */
+/* File: x86/OP_FLOAT_TO_LONG.S */
+/* File: x86/cvtfp_int.S */
+/* On fp to int conversions, Java requires that
+ * if the result > maxint, it should be clamped to maxint. If it is less
+ * than minint, it should be clamped to minint. If it is a nan, the result
+ * should be zero. Further, the rounding mode is to truncate. This model
+ * differs from what is delivered normally via the x86 fpu, so we have
+ * to play some games.
+ */
+ /* float/double to int/long vA, vB */
+ movzbl rINSTbl,%ecx # ecx<- A+
+ sarl $4,rINST # rINST<- B
+ .if 0
+ fldl (rFP,rINST,4) # %st0<- vB
+ .else
+ flds (rFP,rINST,4) # %st0<- vB
+ .endif
+ ftst
+ fnstcw LOCAL0_OFFSET(%ebp) # remember original rounding mode
+ movzwl LOCAL0_OFFSET(%ebp),%eax
+ movb $0xc,%ah
+ movw %ax,LOCAL0_OFFSET+2(%ebp)
+ fldcw LOCAL0_OFFSET+2(%ebp) # set "to zero" rounding mode
+ andb $0xf,%cl # ecx<- A
+ .if 1
+ fistpll (rFP,%ecx,4) # convert and store
+ .else
+ fistpl (rFP,%ecx,4) # convert and store
+ .endif
+ fldcw LOCAL0_OFFSET(%ebp) # restore previous rounding mode
.if 1
movl $0x80000000,%eax
xorl 4(rFP,%ecx,4),%eax
@@ -10814,8 +4719,9 @@
je .LOP_FLOAT_TO_LONG_special_case # fix up result
.LOP_FLOAT_TO_LONG_finish:
+ FETCH_INST_OPCODE 1 %ecx
ADVANCE_PC 1
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
.LOP_FLOAT_TO_LONG_special_case:
fnstsw %ax
@@ -10833,10 +4739,58 @@
.endif
jmp .LOP_FLOAT_TO_LONG_finish
-/* continuation for OP_DOUBLE_TO_INT */
+
+/* ------------------------------ */
+.L_OP_FLOAT_TO_DOUBLE: /* 0x89 */
+/* File: x86/OP_FLOAT_TO_DOUBLE.S */
+/* File: x86/fpcvt.S */
+ /*
+ * Generic 32-bit FP conversion operation.
+ */
+ /* unop vA, vB */
+ movzbl rINSTbl,%ecx # ecx<- A+
+ sarl $4,rINST # rINST<- B
+ flds (rFP,rINST,4) # %st0<- vB
+ andb $0xf,%cl # ecx<- A
+
+ fstpl (rFP,%ecx,4) # vA<- %st0
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
-.LOP_DOUBLE_TO_INT_continue:
+/* ------------------------------ */
+.L_OP_DOUBLE_TO_INT: /* 0x8a */
+/* File: x86/OP_DOUBLE_TO_INT.S */
+/* File: x86/cvtfp_int.S */
+/* On fp to int conversions, Java requires that
+ * if the result > maxint, it should be clamped to maxint. If it is less
+ * than minint, it should be clamped to minint. If it is a nan, the result
+ * should be zero. Further, the rounding mode is to truncate. This model
+ * differs from what is delivered normally via the x86 fpu, so we have
+ * to play some games.
+ */
+ /* float/double to int/long vA, vB */
+ movzbl rINSTbl,%ecx # ecx<- A+
+ sarl $4,rINST # rINST<- B
+ .if 1
+ fldl (rFP,rINST,4) # %st0<- vB
+ .else
+ flds (rFP,rINST,4) # %st0<- vB
+ .endif
+ ftst
+ fnstcw LOCAL0_OFFSET(%ebp) # remember original rounding mode
+ movzwl LOCAL0_OFFSET(%ebp),%eax
+ movb $0xc,%ah
+ movw %ax,LOCAL0_OFFSET+2(%ebp)
+ fldcw LOCAL0_OFFSET+2(%ebp) # set "to zero" rounding mode
+ andb $0xf,%cl # ecx<- A
+ .if 0
+ fistpll (rFP,%ecx,4) # convert and store
+ .else
+ fistpl (rFP,%ecx,4) # convert and store
+ .endif
+ fldcw LOCAL0_OFFSET(%ebp) # restore previous rounding mode
.if 0
movl $0x80000000,%eax
xorl 4(rFP,%ecx,4),%eax
@@ -10847,8 +4801,9 @@
je .LOP_DOUBLE_TO_INT_special_case # fix up result
.LOP_DOUBLE_TO_INT_finish:
+ FETCH_INST_OPCODE 1 %ecx
ADVANCE_PC 1
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
.LOP_DOUBLE_TO_INT_special_case:
fnstsw %ax
@@ -10866,10 +4821,39 @@
.endif
jmp .LOP_DOUBLE_TO_INT_finish
-/* continuation for OP_DOUBLE_TO_LONG */
-
-.LOP_DOUBLE_TO_LONG_continue:
+/* ------------------------------ */
+.L_OP_DOUBLE_TO_LONG: /* 0x8b */
+/* File: x86/OP_DOUBLE_TO_LONG.S */
+/* File: x86/cvtfp_int.S */
+/* On fp to int conversions, Java requires that
+ * if the result > maxint, it should be clamped to maxint. If it is less
+ * than minint, it should be clamped to minint. If it is a nan, the result
+ * should be zero. Further, the rounding mode is to truncate. This model
+ * differs from what is delivered normally via the x86 fpu, so we have
+ * to play some games.
+ */
+ /* float/double to int/long vA, vB */
+ movzbl rINSTbl,%ecx # ecx<- A+
+ sarl $4,rINST # rINST<- B
+ .if 1
+ fldl (rFP,rINST,4) # %st0<- vB
+ .else
+ flds (rFP,rINST,4) # %st0<- vB
+ .endif
+ ftst
+ fnstcw LOCAL0_OFFSET(%ebp) # remember original rounding mode
+ movzwl LOCAL0_OFFSET(%ebp),%eax
+ movb $0xc,%ah
+ movw %ax,LOCAL0_OFFSET+2(%ebp)
+ fldcw LOCAL0_OFFSET+2(%ebp) # set "to zero" rounding mode
+ andb $0xf,%cl # ecx<- A
+ .if 1
+ fistpll (rFP,%ecx,4) # convert and store
+ .else
+ fistpl (rFP,%ecx,4) # convert and store
+ .endif
+ fldcw LOCAL0_OFFSET(%ebp) # restore previous rounding mode
.if 1
movl $0x80000000,%eax
xorl 4(rFP,%ecx,4),%eax
@@ -10880,8 +4864,9 @@
je .LOP_DOUBLE_TO_LONG_special_case # fix up result
.LOP_DOUBLE_TO_LONG_finish:
+ FETCH_INST_OPCODE 1 %ecx
ADVANCE_PC 1
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
.LOP_DOUBLE_TO_LONG_special_case:
fnstsw %ax
@@ -10899,290 +4884,2319 @@
.endif
jmp .LOP_DOUBLE_TO_LONG_finish
-/* continuation for OP_DIV_INT */
+
+/* ------------------------------ */
+.L_OP_DOUBLE_TO_FLOAT: /* 0x8c */
+/* File: x86/OP_DOUBLE_TO_FLOAT.S */
+/* File: x86/fpcvt.S */
+ /*
+ * Generic 32-bit FP conversion operation.
+ */
+ /* unop vA, vB */
+ movzbl rINSTbl,%ecx # ecx<- A+
+ sarl $4,rINST # rINST<- B
+ fldl (rFP,rINST,4) # %st0<- vB
+ andb $0xf,%cl # ecx<- A
+
+ fstps (rFP,%ecx,4) # vA<- %st0
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_INT_TO_BYTE: /* 0x8d */
+/* File: x86/OP_INT_TO_BYTE.S */
+/* File: x86/unop.S */
+ /*
+ * Generic 32-bit unary operation. Provide an "instr" line that
+ * specifies an instruction that performs "result = op eax".
+ */
+ /* unop vA, vB */
+ movzbl rINSTbl,%ecx # ecx<- A+
+ sarl $4,rINST # rINST<- B
+ GET_VREG_R %eax rINST # eax<- vB
+ andb $0xf,%cl # ecx<- A
+
+
+ movsbl %al,%eax
+ SET_VREG %eax %ecx
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_INT_TO_CHAR: /* 0x8e */
+/* File: x86/OP_INT_TO_CHAR.S */
+/* File: x86/unop.S */
+ /*
+ * Generic 32-bit unary operation. Provide an "instr" line that
+ * specifies an instruction that performs "result = op eax".
+ */
+ /* unop vA, vB */
+ movzbl rINSTbl,%ecx # ecx<- A+
+ sarl $4,rINST # rINST<- B
+ GET_VREG_R %eax rINST # eax<- vB
+ andb $0xf,%cl # ecx<- A
+
+
+ movzwl %ax,%eax
+ SET_VREG %eax %ecx
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_INT_TO_SHORT: /* 0x8f */
+/* File: x86/OP_INT_TO_SHORT.S */
+/* File: x86/unop.S */
+ /*
+ * Generic 32-bit unary operation. Provide an "instr" line that
+ * specifies an instruction that performs "result = op eax".
+ */
+ /* unop vA, vB */
+ movzbl rINSTbl,%ecx # ecx<- A+
+ sarl $4,rINST # rINST<- B
+ GET_VREG_R %eax rINST # eax<- vB
+ andb $0xf,%cl # ecx<- A
+
+
+ movswl %ax,%eax
+ SET_VREG %eax %ecx
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_ADD_INT: /* 0x90 */
+/* File: x86/OP_ADD_INT.S */
+/* File: x86/binop.S */
+ /*
+ * Generic 32-bit binary operation. Provide an "instr" line that
+ * specifies an instruction that performs "result = eax op (rFP,%ecx,4)".
+ * This could be an x86 instruction or a function call. (If the result
+ * comes back in a register other than eax, you can override "result".)
+ *
+ * For: add-int, sub-int, and-int, or-int,
+ * xor-int, shl-int, shr-int, ushr-int
+ */
+ /* binop vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ GET_VREG_R %eax %eax # eax<- vBB
+ addl (rFP,%ecx,4),%eax # ex: addl (rFP,%ecx,4),%eax
+ SET_VREG %eax rINST
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_SUB_INT: /* 0x91 */
+/* File: x86/OP_SUB_INT.S */
+/* File: x86/binop.S */
+ /*
+ * Generic 32-bit binary operation. Provide an "instr" line that
+ * specifies an instruction that performs "result = eax op (rFP,%ecx,4)".
+ * This could be an x86 instruction or a function call. (If the result
+ * comes back in a register other than eax, you can override "result".)
+ *
+ * For: add-int, sub-int, and-int, or-int,
+ * xor-int, shl-int, shr-int, ushr-int
+ */
+ /* binop vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ GET_VREG_R %eax %eax # eax<- vBB
+ subl (rFP,%ecx,4),%eax # ex: addl (rFP,%ecx,4),%eax
+ SET_VREG %eax rINST
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_MUL_INT: /* 0x92 */
+/* File: x86/OP_MUL_INT.S */
+ /*
+ * 32-bit binary multiplication.
+ */
+ /* mul vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ GET_VREG_R %eax %eax # eax<- vBB
+ SPILL(rIBASE)
+ imull (rFP,%ecx,4),%eax # trashes rIBASE/edx
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ SET_VREG %eax rINST
+ GOTO_NEXT_R %ecx
+
+/* ------------------------------ */
+.L_OP_DIV_INT: /* 0x93 */
+/* File: x86/OP_DIV_INT.S */
+/* File: x86/bindiv.S */
+
+ /*
+ * 32-bit binary div/rem operation. Handles special case of op0=minint and
+ * op1=-1.
+ */
+ /* binop vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ GET_VREG_R %eax %eax # eax<- vBB
+ GET_VREG_R %ecx %ecx # eax<- vBB
+ SPILL(rIBASE)
+ cmpl $0,%ecx
+ je common_errDivideByZero
+ cmpl $-1,%ecx
+ jne .LOP_DIV_INT_continue_div
+ cmpl $0x80000000,%eax
+ jne .LOP_DIV_INT_continue_div
+ movl $0x80000000,%eax
+ SET_VREG %eax rINST
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
.LOP_DIV_INT_continue_div:
cltd
idivl %ecx
-.LOP_DIV_INT_finish_div:
SET_VREG %eax rINST
- FETCH_INST_OPCODE 2 %edx
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_REM_INT */
+
+/* ------------------------------ */
+.L_OP_REM_INT: /* 0x94 */
+/* File: x86/OP_REM_INT.S */
+/* File: x86/bindiv.S */
+
+ /*
+ * 32-bit binary div/rem operation. Handles special case of op0=minint and
+ * op1=-1.
+ */
+ /* binop vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ GET_VREG_R %eax %eax # eax<- vBB
+ GET_VREG_R %ecx %ecx # eax<- vBB
+ SPILL(rIBASE)
+ cmpl $0,%ecx
+ je common_errDivideByZero
+ cmpl $-1,%ecx
+ jne .LOP_REM_INT_continue_div
+ cmpl $0x80000000,%eax
+ jne .LOP_REM_INT_continue_div
+ movl $0,rIBASE
+ SET_VREG rIBASE rINST
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
.LOP_REM_INT_continue_div:
cltd
idivl %ecx
-.LOP_REM_INT_finish_div:
- SET_VREG %edx rINST
- FETCH_INST_OPCODE 2 %edx
+ SET_VREG rIBASE rINST
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_MUL_LONG */
-.LOP_MUL_LONG_continue:
- leal (%ecx,%edx),%edx # full result now in %edx:%eax
+/* ------------------------------ */
+.L_OP_AND_INT: /* 0x95 */
+/* File: x86/OP_AND_INT.S */
+/* File: x86/binop.S */
+ /*
+ * Generic 32-bit binary operation. Provide an "instr" line that
+ * specifies an instruction that performs "result = eax op (rFP,%ecx,4)".
+ * This could be an x86 instruction or a function call. (If the result
+ * comes back in a register other than eax, you can override "result".)
+ *
+ * For: add-int, sub-int, and-int, or-int,
+ * xor-int, shl-int, shr-int, ushr-int
+ */
+ /* binop vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ GET_VREG_R %eax %eax # eax<- vBB
+ andl (rFP,%ecx,4),%eax # ex: addl (rFP,%ecx,4),%eax
+ SET_VREG %eax rINST
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_OR_INT: /* 0x96 */
+/* File: x86/OP_OR_INT.S */
+/* File: x86/binop.S */
+ /*
+ * Generic 32-bit binary operation. Provide an "instr" line that
+ * specifies an instruction that performs "result = eax op (rFP,%ecx,4)".
+ * This could be an x86 instruction or a function call. (If the result
+ * comes back in a register other than eax, you can override "result".)
+ *
+ * For: add-int, sub-int, and-int, or-int,
+ * xor-int, shl-int, shr-int, ushr-int
+ */
+ /* binop vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ GET_VREG_R %eax %eax # eax<- vBB
+ orl (rFP,%ecx,4),%eax # ex: addl (rFP,%ecx,4),%eax
+ SET_VREG %eax rINST
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_XOR_INT: /* 0x97 */
+/* File: x86/OP_XOR_INT.S */
+/* File: x86/binop.S */
+ /*
+ * Generic 32-bit binary operation. Provide an "instr" line that
+ * specifies an instruction that performs "result = eax op (rFP,%ecx,4)".
+ * This could be an x86 instruction or a function call. (If the result
+ * comes back in a register other than eax, you can override "result".)
+ *
+ * For: add-int, sub-int, and-int, or-int,
+ * xor-int, shl-int, shr-int, ushr-int
+ */
+ /* binop vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ GET_VREG_R %eax %eax # eax<- vBB
+ xorl (rFP,%ecx,4),%eax # ex: addl (rFP,%ecx,4),%eax
+ SET_VREG %eax rINST
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_SHL_INT: /* 0x98 */
+/* File: x86/OP_SHL_INT.S */
+/* File: x86/binop1.S */
+ /*
+ * Generic 32-bit binary operation in which both operands loaded to
+ * registers (op0 in eax, op1 in ecx).
+ */
+ /* binop vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ GET_VREG_R %eax %eax # eax<- vBB
+ GET_VREG_R %ecx %ecx # eax<- vBB
+ sall %cl,%eax # ex: addl %ecx,%eax
+ SET_VREG %eax rINST
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_SHR_INT: /* 0x99 */
+/* File: x86/OP_SHR_INT.S */
+/* File: x86/binop1.S */
+ /*
+ * Generic 32-bit binary operation in which both operands loaded to
+ * registers (op0 in eax, op1 in ecx).
+ */
+ /* binop vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ GET_VREG_R %eax %eax # eax<- vBB
+ GET_VREG_R %ecx %ecx # eax<- vBB
+ sarl %cl,%eax # ex: addl %ecx,%eax
+ SET_VREG %eax rINST
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_USHR_INT: /* 0x9a */
+/* File: x86/OP_USHR_INT.S */
+/* File: x86/binop1.S */
+ /*
+ * Generic 32-bit binary operation in which both operands loaded to
+ * registers (op0 in eax, op1 in ecx).
+ */
+ /* binop vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ GET_VREG_R %eax %eax # eax<- vBB
+ GET_VREG_R %ecx %ecx # eax<- vBB
+ shrl %cl,%eax # ex: addl %ecx,%eax
+ SET_VREG %eax rINST
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_ADD_LONG: /* 0x9b */
+/* File: x86/OP_ADD_LONG.S */
+/* File: x86/binopWide.S */
+ /*
+ * Generic 64-bit binary operation.
+ */
+ /* binop vAA, vBB, vCC */
+
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ SPILL(rIBASE) # save rIBASE
+ GET_VREG_WORD rIBASE %eax 0 # rIBASE<- v[BB+0]
+ GET_VREG_WORD %eax %eax 1 # eax<- v[BB+1]
+ addl (rFP,%ecx,4),rIBASE # ex: addl (rFP,%ecx,4),rIBASE
+ adcl 4(rFP,%ecx,4),%eax # ex: adcl 4(rFP,%ecx,4),%eax
+ SET_VREG_WORD rIBASE rINST 0 # v[AA+0] <- rIBASE
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE) # restore rIBASE
+ SET_VREG_WORD %eax rINST 1 # v[AA+1] <- eax
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_SUB_LONG: /* 0x9c */
+/* File: x86/OP_SUB_LONG.S */
+/* File: x86/binopWide.S */
+ /*
+ * Generic 64-bit binary operation.
+ */
+ /* binop vAA, vBB, vCC */
+
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ SPILL(rIBASE) # save rIBASE
+ GET_VREG_WORD rIBASE %eax 0 # rIBASE<- v[BB+0]
+ GET_VREG_WORD %eax %eax 1 # eax<- v[BB+1]
+ subl (rFP,%ecx,4),rIBASE # ex: addl (rFP,%ecx,4),rIBASE
+ sbbl 4(rFP,%ecx,4),%eax # ex: adcl 4(rFP,%ecx,4),%eax
+ SET_VREG_WORD rIBASE rINST 0 # v[AA+0] <- rIBASE
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE) # restore rIBASE
+ SET_VREG_WORD %eax rINST 1 # v[AA+1] <- eax
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_MUL_LONG: /* 0x9d */
+/* File: x86/OP_MUL_LONG.S */
+ /*
+ * Signed 64-bit integer multiply.
+ *
+ * We could definately use more free registers for
+ * this code. We spill rINSTw (ebx),
+ * giving us eax, ebc, ecx and edx as computational
+ * temps. On top of that, we'll spill edi (rFP)
+ * for use as the vB pointer and esi (rPC) for use
+ * as the vC pointer. Yuck.
+ */
+ /* mul-long vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- B
+ movzbl 3(rPC),%ecx # ecx<- C
+ SPILL_TMP2(%esi) # save Dalvik PC
+ SPILL(rFP)
+ SPILL(rINST)
+ SPILL(rIBASE)
+ leal (rFP,%eax,4),%esi # esi<- &v[B]
+ leal (rFP,%ecx,4),rFP # rFP<- &v[C]
+ movl 4(%esi),%ecx # ecx<- Bmsw
+ imull (rFP),%ecx # ecx<- (Bmsw*Clsw)
+ movl 4(rFP),%eax # eax<- Cmsw
+ imull (%esi),%eax # eax<- (Cmsw*Blsw)
+ addl %eax,%ecx # ecx<- (Bmsw*Clsw)+(Cmsw*Blsw)
+ movl (rFP),%eax # eax<- Clsw
+ mull (%esi) # eax<- (Clsw*Alsw)
+ UNSPILL(rINST)
+ UNSPILL(rFP)
+ leal (%ecx,rIBASE),rIBASE # full result now in rIBASE:%eax
UNSPILL_TMP2(%esi) # Restore Dalvik PC
FETCH_INST_OPCODE 2 %ecx # Fetch next instruction
- movl %edx,4(rFP,rINST,4) # v[B+1]<- %edx
+ movl rIBASE,4(rFP,rINST,4)# v[B+1]<- rIBASE
+ UNSPILL(rIBASE)
movl %eax,(rFP,rINST,4) # v[B]<- %eax
ADVANCE_PC 2
GOTO_NEXT_R %ecx
-/* continuation for OP_DIV_LONG */
-
-.LOP_DIV_LONG_continue:
+/* ------------------------------ */
+.L_OP_DIV_LONG: /* 0x9e */
+/* File: x86/OP_DIV_LONG.S */
+ /* div vAA, vBB, vCC */
+ movzbl 3(rPC),%eax # eax<- CC
+ movzbl 2(rPC),%ecx # ecx<- BB
+ SPILL(rIBASE) # save rIBASE/%edx
+ GET_VREG_WORD rIBASE %eax 0
+ GET_VREG_WORD %eax %eax 1
+ movl rIBASE,OUT_ARG2(%esp)
+ testl %eax,%eax
+ je .LOP_DIV_LONG_check_zero
+ cmpl $-1,%eax
+ je .LOP_DIV_LONG_check_neg1
+.LOP_DIV_LONG_notSpecial:
+ GET_VREG_WORD rIBASE %ecx 0
+ GET_VREG_WORD %ecx %ecx 1
+.LOP_DIV_LONG_notSpecial1:
+ movl %eax,OUT_ARG3(%esp)
+ movl rIBASE,OUT_ARG0(%esp)
+ movl %ecx,OUT_ARG1(%esp)
call __divdi3
.LOP_DIV_LONG_finish:
- SET_VREG_WORD %edx rINST 1
+ SET_VREG_WORD rIBASE rINST 1
+ UNSPILL(rIBASE) # restore rIBASE/%edx
SET_VREG_WORD %eax rINST 0
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
.LOP_DIV_LONG_check_zero:
- testl %edx,%edx
+ testl rIBASE,rIBASE
jne .LOP_DIV_LONG_notSpecial
jmp common_errDivideByZero
.LOP_DIV_LONG_check_neg1:
- testl %edx,%eax
+ testl rIBASE,%eax
jne .LOP_DIV_LONG_notSpecial
- GET_VREG_WORD %edx %ecx 0
+ GET_VREG_WORD rIBASE %ecx 0
GET_VREG_WORD %ecx %ecx 1
- testl %edx,%edx
+ testl rIBASE,rIBASE
jne .LOP_DIV_LONG_notSpecial1
cmpl $0x80000000,%ecx
jne .LOP_DIV_LONG_notSpecial1
/* minint / -1, return minint on div, 0 on rem */
xorl %eax,%eax
- movl $0x80000000,%edx
+ movl $0x80000000,rIBASE
jmp .LOP_DIV_LONG_finish
-/* continuation for OP_REM_LONG */
-
-.LOP_REM_LONG_continue:
+/* ------------------------------ */
+.L_OP_REM_LONG: /* 0x9f */
+/* File: x86/OP_REM_LONG.S */
+/* File: x86/OP_DIV_LONG.S */
+ /* div vAA, vBB, vCC */
+ movzbl 3(rPC),%eax # eax<- CC
+ movzbl 2(rPC),%ecx # ecx<- BB
+ SPILL(rIBASE) # save rIBASE/%edx
+ GET_VREG_WORD rIBASE %eax 0
+ GET_VREG_WORD %eax %eax 1
+ movl rIBASE,OUT_ARG2(%esp)
+ testl %eax,%eax
+ je .LOP_REM_LONG_check_zero
+ cmpl $-1,%eax
+ je .LOP_REM_LONG_check_neg1
+.LOP_REM_LONG_notSpecial:
+ GET_VREG_WORD rIBASE %ecx 0
+ GET_VREG_WORD %ecx %ecx 1
+.LOP_REM_LONG_notSpecial1:
+ movl %eax,OUT_ARG3(%esp)
+ movl rIBASE,OUT_ARG0(%esp)
+ movl %ecx,OUT_ARG1(%esp)
call __moddi3
.LOP_REM_LONG_finish:
- SET_VREG_WORD %edx rINST 1
+ SET_VREG_WORD rIBASE rINST 1
+ UNSPILL(rIBASE) # restore rIBASE/%edx
SET_VREG_WORD %eax rINST 0
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
.LOP_REM_LONG_check_zero:
- testl %edx,%edx
+ testl rIBASE,rIBASE
jne .LOP_REM_LONG_notSpecial
jmp common_errDivideByZero
.LOP_REM_LONG_check_neg1:
- testl %edx,%eax
+ testl rIBASE,%eax
jne .LOP_REM_LONG_notSpecial
- GET_VREG_WORD %edx %ecx 0
+ GET_VREG_WORD rIBASE %ecx 0
GET_VREG_WORD %ecx %ecx 1
- testl %edx,%edx
+ testl rIBASE,rIBASE
jne .LOP_REM_LONG_notSpecial1
cmpl $0x80000000,%ecx
jne .LOP_REM_LONG_notSpecial1
/* minint / -1, return minint on div, 0 on rem */
xorl %eax,%eax
- movl $0,%edx
+ movl $0,rIBASE
jmp .LOP_REM_LONG_finish
-/* continuation for OP_SHL_LONG */
-.LOP_SHL_LONG_finish:
+/* ------------------------------ */
+.L_OP_AND_LONG: /* 0xa0 */
+/* File: x86/OP_AND_LONG.S */
+/* File: x86/binopWide.S */
+ /*
+ * Generic 64-bit binary operation.
+ */
+ /* binop vAA, vBB, vCC */
+
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ SPILL(rIBASE) # save rIBASE
+ GET_VREG_WORD rIBASE %eax 0 # rIBASE<- v[BB+0]
+ GET_VREG_WORD %eax %eax 1 # eax<- v[BB+1]
+ andl (rFP,%ecx,4),rIBASE # ex: addl (rFP,%ecx,4),rIBASE
+ andl 4(rFP,%ecx,4),%eax # ex: adcl 4(rFP,%ecx,4),%eax
+ SET_VREG_WORD rIBASE rINST 0 # v[AA+0] <- rIBASE
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE) # restore rIBASE
+ SET_VREG_WORD %eax rINST 1 # v[AA+1] <- eax
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_OR_LONG: /* 0xa1 */
+/* File: x86/OP_OR_LONG.S */
+/* File: x86/binopWide.S */
+ /*
+ * Generic 64-bit binary operation.
+ */
+ /* binop vAA, vBB, vCC */
+
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ SPILL(rIBASE) # save rIBASE
+ GET_VREG_WORD rIBASE %eax 0 # rIBASE<- v[BB+0]
+ GET_VREG_WORD %eax %eax 1 # eax<- v[BB+1]
+ orl (rFP,%ecx,4),rIBASE # ex: addl (rFP,%ecx,4),rIBASE
+ orl 4(rFP,%ecx,4),%eax # ex: adcl 4(rFP,%ecx,4),%eax
+ SET_VREG_WORD rIBASE rINST 0 # v[AA+0] <- rIBASE
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE) # restore rIBASE
+ SET_VREG_WORD %eax rINST 1 # v[AA+1] <- eax
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_XOR_LONG: /* 0xa2 */
+/* File: x86/OP_XOR_LONG.S */
+/* File: x86/binopWide.S */
+ /*
+ * Generic 64-bit binary operation.
+ */
+ /* binop vAA, vBB, vCC */
+
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ SPILL(rIBASE) # save rIBASE
+ GET_VREG_WORD rIBASE %eax 0 # rIBASE<- v[BB+0]
+ GET_VREG_WORD %eax %eax 1 # eax<- v[BB+1]
+ xorl (rFP,%ecx,4),rIBASE # ex: addl (rFP,%ecx,4),rIBASE
+ xorl 4(rFP,%ecx,4),%eax # ex: adcl 4(rFP,%ecx,4),%eax
+ SET_VREG_WORD rIBASE rINST 0 # v[AA+0] <- rIBASE
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE) # restore rIBASE
+ SET_VREG_WORD %eax rINST 1 # v[AA+1] <- eax
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_SHL_LONG: /* 0xa3 */
+/* File: x86/OP_SHL_LONG.S */
+ /*
+ * Long integer shift. This is different from the generic 32/64-bit
+ * binary operations because vAA/vBB are 64-bit but vCC (the shift
+ * distance) is 32-bit. Also, Dalvik requires us to mask off the low
+ * 6 bits of the shift distance. x86 shifts automatically mask off
+ * the low 5 bits of %cl, so have to handle the 64 > shiftcount > 31
+ * case specially.
+ */
+ /* shl-long vAA, vBB, vCC */
+ /* ecx gets shift count */
+ /* Need to spill rINST */
+ /* rINSTw gets AA */
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ SPILL(rIBASE)
+ GET_VREG_WORD rIBASE %eax 1 # ecx<- v[BB+1]
+ GET_VREG_R %ecx %ecx # ecx<- vCC
+ GET_VREG_WORD %eax %eax 0 # eax<- v[BB+0]
+ shldl %eax,rIBASE
+ sall %cl,%eax
+ testb $32,%cl
+ je 2f
+ movl %eax,rIBASE
+ xorl %eax,%eax
+2:
+ SET_VREG_WORD rIBASE rINST 1 # v[AA+1]<- rIBASE
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
SET_VREG_WORD %eax rINST 0 # v[AA+0]<- %eax
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_SHR_LONG */
-
-
-.LOP_SHR_LONG_finish:
+/* ------------------------------ */
+.L_OP_SHR_LONG: /* 0xa4 */
+/* File: x86/OP_SHR_LONG.S */
+ /*
+ * Long integer shift. This is different from the generic 32/64-bit
+ * binary operations because vAA/vBB are 64-bit but vCC (the shift
+ * distance) is 32-bit. Also, Dalvik requires us to mask off the low
+ * 6 bits of the shift distance. x86 shifts automatically mask off
+ * the low 5 bits of %cl, so have to handle the 64 > shiftcount > 31
+ * case specially.
+ */
+ /* shr-long vAA, vBB, vCC */
+ /* ecx gets shift count */
+ /* Need to spill rIBASE */
+ /* rINSTw gets AA */
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ SPILL(rIBASE)
+ GET_VREG_WORD rIBASE %eax 1 # rIBASE<- v[BB+1]
+ GET_VREG_R %ecx %ecx # ecx<- vCC
+ GET_VREG_WORD %eax %eax 0 # eax<- v[BB+0]
+ shrdl rIBASE,%eax
+ sarl %cl,rIBASE
+ testb $32,%cl
+ je 2f
+ movl rIBASE,%eax
+ sarl $31,rIBASE
+2:
+ SET_VREG_WORD rIBASE rINST 1 # v[AA+1]<- rIBASE
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
SET_VREG_WORD %eax rINST 0 # v[AA+0]<- eax
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_USHR_LONG */
-
-
-.LOP_USHR_LONG_finish:
+/* ------------------------------ */
+.L_OP_USHR_LONG: /* 0xa5 */
+/* File: x86/OP_USHR_LONG.S */
+ /*
+ * Long integer shift. This is different from the generic 32/64-bit
+ * binary operations because vAA/vBB are 64-bit but vCC (the shift
+ * distance) is 32-bit. Also, Dalvik requires us to mask off the low
+ * 6 bits of the shift distance. x86 shifts automatically mask off
+ * the low 5 bits of %cl, so have to handle the 64 > shiftcount > 31
+ * case specially.
+ */
+ /* shr-long vAA, vBB, vCC */
+ /* ecx gets shift count */
+ /* Need to spill rIBASE */
+ /* rINSTw gets AA */
+ movzbl 2(rPC),%eax # eax<- BB
+ movzbl 3(rPC),%ecx # ecx<- CC
+ SPILL(rIBASE)
+ GET_VREG_WORD rIBASE %eax 1 # rIBASE<- v[BB+1]
+ GET_VREG_R %ecx %ecx # ecx<- vCC
+ GET_VREG_WORD %eax %eax 0 # eax<- v[BB+0]
+ shrdl rIBASE,%eax
+ shrl %cl,rIBASE
+ testb $32,%cl
+ je 2f
+ movl rIBASE,%eax
+ xorl rIBASE,rIBASE
+2:
+ SET_VREG_WORD rIBASE rINST 1 # v[AA+1]<- rIBASE
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
SET_VREG_WORD %eax rINST 0 # v[BB+0]<- eax
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_DIV_INT_2ADDR */
+/* ------------------------------ */
+.L_OP_ADD_FLOAT: /* 0xa6 */
+/* File: x86/OP_ADD_FLOAT.S */
+/* File: x86/binflop.S */
+ /*
+ * Generic 32-bit binary float operation.
+ *
+ * For: add-fp, sub-fp, mul-fp, div-fp
+ */
+ /* binop vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- CC
+ movzbl 3(rPC),%ecx # ecx<- BB
+ flds (rFP,%eax,4) # vCC to fp stack
+ fadds (rFP,%ecx,4) # ex: faddp
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ fstps (rFP,rINST,4) # %st to vAA
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_SUB_FLOAT: /* 0xa7 */
+/* File: x86/OP_SUB_FLOAT.S */
+/* File: x86/binflop.S */
+ /*
+ * Generic 32-bit binary float operation.
+ *
+ * For: add-fp, sub-fp, mul-fp, div-fp
+ */
+ /* binop vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- CC
+ movzbl 3(rPC),%ecx # ecx<- BB
+ flds (rFP,%eax,4) # vCC to fp stack
+ fsubs (rFP,%ecx,4) # ex: faddp
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ fstps (rFP,rINST,4) # %st to vAA
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_MUL_FLOAT: /* 0xa8 */
+/* File: x86/OP_MUL_FLOAT.S */
+/* File: x86/binflop.S */
+ /*
+ * Generic 32-bit binary float operation.
+ *
+ * For: add-fp, sub-fp, mul-fp, div-fp
+ */
+ /* binop vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- CC
+ movzbl 3(rPC),%ecx # ecx<- BB
+ flds (rFP,%eax,4) # vCC to fp stack
+ fmuls (rFP,%ecx,4) # ex: faddp
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ fstps (rFP,rINST,4) # %st to vAA
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_DIV_FLOAT: /* 0xa9 */
+/* File: x86/OP_DIV_FLOAT.S */
+/* File: x86/binflop.S */
+ /*
+ * Generic 32-bit binary float operation.
+ *
+ * For: add-fp, sub-fp, mul-fp, div-fp
+ */
+ /* binop vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- CC
+ movzbl 3(rPC),%ecx # ecx<- BB
+ flds (rFP,%eax,4) # vCC to fp stack
+ fdivs (rFP,%ecx,4) # ex: faddp
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ fstps (rFP,rINST,4) # %st to vAA
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_REM_FLOAT: /* 0xaa */
+/* File: x86/OP_REM_FLOAT.S */
+ /* rem_float vAA, vBB, vCC */
+ movzbl 3(rPC),%ecx # ecx<- BB
+ movzbl 2(rPC),%eax # eax<- CC
+ flds (rFP,%ecx,4) # vCC to fp stack
+ flds (rFP,%eax,4) # vCC to fp stack
+ movzbl rINSTbl,%ecx # ecx<- AA
+1:
+ fprem
+ fstsw %ax
+ sahf
+ jp 1b
+ fstp %st(1)
+ FETCH_INST_OPCODE 2 %eax
+ ADVANCE_PC 2
+ fstps (rFP,%ecx,4) # %st to vAA
+ GOTO_NEXT_R %eax
+
+/* ------------------------------ */
+.L_OP_ADD_DOUBLE: /* 0xab */
+/* File: x86/OP_ADD_DOUBLE.S */
+/* File: x86/binflop.S */
+ /*
+ * Generic 32-bit binary float operation.
+ *
+ * For: add-fp, sub-fp, mul-fp, div-fp
+ */
+ /* binop vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- CC
+ movzbl 3(rPC),%ecx # ecx<- BB
+ fldl (rFP,%eax,4) # vCC to fp stack
+ faddl (rFP,%ecx,4) # ex: faddp
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ fstpl (rFP,rINST,4) # %st to vAA
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_SUB_DOUBLE: /* 0xac */
+/* File: x86/OP_SUB_DOUBLE.S */
+/* File: x86/binflop.S */
+ /*
+ * Generic 32-bit binary float operation.
+ *
+ * For: add-fp, sub-fp, mul-fp, div-fp
+ */
+ /* binop vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- CC
+ movzbl 3(rPC),%ecx # ecx<- BB
+ fldl (rFP,%eax,4) # vCC to fp stack
+ fsubl (rFP,%ecx,4) # ex: faddp
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ fstpl (rFP,rINST,4) # %st to vAA
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_MUL_DOUBLE: /* 0xad */
+/* File: x86/OP_MUL_DOUBLE.S */
+/* File: x86/binflop.S */
+ /*
+ * Generic 32-bit binary float operation.
+ *
+ * For: add-fp, sub-fp, mul-fp, div-fp
+ */
+ /* binop vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- CC
+ movzbl 3(rPC),%ecx # ecx<- BB
+ fldl (rFP,%eax,4) # vCC to fp stack
+ fmull (rFP,%ecx,4) # ex: faddp
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ fstpl (rFP,rINST,4) # %st to vAA
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_DIV_DOUBLE: /* 0xae */
+/* File: x86/OP_DIV_DOUBLE.S */
+/* File: x86/binflop.S */
+ /*
+ * Generic 32-bit binary float operation.
+ *
+ * For: add-fp, sub-fp, mul-fp, div-fp
+ */
+ /* binop vAA, vBB, vCC */
+ movzbl 2(rPC),%eax # eax<- CC
+ movzbl 3(rPC),%ecx # ecx<- BB
+ fldl (rFP,%eax,4) # vCC to fp stack
+ fdivl (rFP,%ecx,4) # ex: faddp
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ fstpl (rFP,rINST,4) # %st to vAA
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_REM_DOUBLE: /* 0xaf */
+/* File: x86/OP_REM_DOUBLE.S */
+ /* rem_float vAA, vBB, vCC */
+ movzbl 3(rPC),%ecx # ecx<- BB
+ movzbl 2(rPC),%eax # eax<- CC
+ fldl (rFP,%ecx,4) # vCC to fp stack
+ fldl (rFP,%eax,4) # vCC to fp stack
+ FETCH_INST_OPCODE 2 %ecx
+1:
+ fprem
+ fstsw %ax
+ sahf
+ jp 1b
+ fstp %st(1)
+ ADVANCE_PC 2
+ fstpl (rFP,rINST,4) # %st to vAA
+ GOTO_NEXT_R %ecx
+
+/* ------------------------------ */
+.L_OP_ADD_INT_2ADDR: /* 0xb0 */
+/* File: x86/OP_ADD_INT_2ADDR.S */
+/* File: x86/binop2addr.S */
+ /*
+ * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
+ * that specifies an instruction that performs "result = r0 op r1".
+ * This could be an ARM instruction or a function call. (If the result
+ * comes back in a register other than r0, you can override "result".)
+ *
+ * If "chkzero" is set to 1, we perform a divide-by-zero check on
+ * vCC (r1). Useful for integer division and modulus.
+ *
+ * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
+ * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
+ * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
+ * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
+ */
+ /* binop/2addr vA, vB */
+ movzx rINSTbl,%ecx # ecx<- A+
+ sarl $4,rINST # rINST<- B
+ GET_VREG_R %eax rINST # eax<- vB
+ andb $0xf,%cl # ecx<- A
+ addl %eax,(rFP,%ecx,4) # for ex: addl %eax,(rFP,%ecx,4)
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_SUB_INT_2ADDR: /* 0xb1 */
+/* File: x86/OP_SUB_INT_2ADDR.S */
+/* File: x86/binop2addr.S */
+ /*
+ * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
+ * that specifies an instruction that performs "result = r0 op r1".
+ * This could be an ARM instruction or a function call. (If the result
+ * comes back in a register other than r0, you can override "result".)
+ *
+ * If "chkzero" is set to 1, we perform a divide-by-zero check on
+ * vCC (r1). Useful for integer division and modulus.
+ *
+ * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
+ * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
+ * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
+ * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
+ */
+ /* binop/2addr vA, vB */
+ movzx rINSTbl,%ecx # ecx<- A+
+ sarl $4,rINST # rINST<- B
+ GET_VREG_R %eax rINST # eax<- vB
+ andb $0xf,%cl # ecx<- A
+ subl %eax,(rFP,%ecx,4) # for ex: addl %eax,(rFP,%ecx,4)
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_MUL_INT_2ADDR: /* 0xb2 */
+/* File: x86/OP_MUL_INT_2ADDR.S */
+ /* mul vA, vB */
+ movzx rINSTbl,%ecx # ecx<- A+
+ sarl $4,rINST # rINST<- B
+ GET_VREG_R %eax rINST # eax<- vB
+ andb $0xf,%cl # ecx<- A
+ SPILL(rIBASE)
+ imull (rFP,%ecx,4),%eax # trashes rIBASE/edx
+ UNSPILL(rIBASE)
+ SET_VREG %eax %ecx
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
+
+/* ------------------------------ */
+.L_OP_DIV_INT_2ADDR: /* 0xb3 */
+/* File: x86/OP_DIV_INT_2ADDR.S */
+/* File: x86/bindiv2addr.S */
+ /*
+ * 32-bit binary div/rem operation. Handles special case of op0=minint and
+ * op1=-1.
+ */
+ /* div/rem/2addr vA, vB */
+ movzx rINSTbl,%ecx # eax<- BA
+ SPILL(rIBASE)
+ sarl $4,%ecx # ecx<- B
+ GET_VREG_R %ecx %ecx # eax<- vBB
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_R %eax rINST # eax<- vBB
+ cmpl $0,%ecx
+ je common_errDivideByZero
+ cmpl $-1,%ecx
+ jne .LOP_DIV_INT_2ADDR_continue_div2addr
+ cmpl $0x80000000,%eax
+ jne .LOP_DIV_INT_2ADDR_continue_div2addr
+ movl $0x80000000,%eax
+ SET_VREG %eax rINST
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
+
.LOP_DIV_INT_2ADDR_continue_div2addr:
cltd
idivl %ecx
-.LOP_DIV_INT_2ADDR_finish_div2addr:
SET_VREG %eax rINST
- FETCH_INST_OPCODE 1 %edx
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 1 %ecx
ADVANCE_PC 1
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_REM_INT_2ADDR */
+
+/* ------------------------------ */
+.L_OP_REM_INT_2ADDR: /* 0xb4 */
+/* File: x86/OP_REM_INT_2ADDR.S */
+/* File: x86/bindiv2addr.S */
+ /*
+ * 32-bit binary div/rem operation. Handles special case of op0=minint and
+ * op1=-1.
+ */
+ /* div/rem/2addr vA, vB */
+ movzx rINSTbl,%ecx # eax<- BA
+ SPILL(rIBASE)
+ sarl $4,%ecx # ecx<- B
+ GET_VREG_R %ecx %ecx # eax<- vBB
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_R %eax rINST # eax<- vBB
+ cmpl $0,%ecx
+ je common_errDivideByZero
+ cmpl $-1,%ecx
+ jne .LOP_REM_INT_2ADDR_continue_div2addr
+ cmpl $0x80000000,%eax
+ jne .LOP_REM_INT_2ADDR_continue_div2addr
+ movl $0,rIBASE
+ SET_VREG rIBASE rINST
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
+
.LOP_REM_INT_2ADDR_continue_div2addr:
cltd
idivl %ecx
-.LOP_REM_INT_2ADDR_finish_div2addr:
- SET_VREG %edx rINST
- FETCH_INST_OPCODE 1 %edx
+ SET_VREG rIBASE rINST
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 1 %ecx
ADVANCE_PC 1
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_MUL_LONG_2ADDR */
-.LOP_MUL_LONG_2ADDR_continue:
- leal (%ecx,%edx),%edx # full result now in %edx:%eax
- movl %edx,4(%esi) # v[A+1]<- %edx
+/* ------------------------------ */
+.L_OP_AND_INT_2ADDR: /* 0xb5 */
+/* File: x86/OP_AND_INT_2ADDR.S */
+/* File: x86/binop2addr.S */
+ /*
+ * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
+ * that specifies an instruction that performs "result = r0 op r1".
+ * This could be an ARM instruction or a function call. (If the result
+ * comes back in a register other than r0, you can override "result".)
+ *
+ * If "chkzero" is set to 1, we perform a divide-by-zero check on
+ * vCC (r1). Useful for integer division and modulus.
+ *
+ * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
+ * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
+ * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
+ * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
+ */
+ /* binop/2addr vA, vB */
+ movzx rINSTbl,%ecx # ecx<- A+
+ sarl $4,rINST # rINST<- B
+ GET_VREG_R %eax rINST # eax<- vB
+ andb $0xf,%cl # ecx<- A
+ andl %eax,(rFP,%ecx,4) # for ex: addl %eax,(rFP,%ecx,4)
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_OR_INT_2ADDR: /* 0xb6 */
+/* File: x86/OP_OR_INT_2ADDR.S */
+/* File: x86/binop2addr.S */
+ /*
+ * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
+ * that specifies an instruction that performs "result = r0 op r1".
+ * This could be an ARM instruction or a function call. (If the result
+ * comes back in a register other than r0, you can override "result".)
+ *
+ * If "chkzero" is set to 1, we perform a divide-by-zero check on
+ * vCC (r1). Useful for integer division and modulus.
+ *
+ * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
+ * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
+ * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
+ * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
+ */
+ /* binop/2addr vA, vB */
+ movzx rINSTbl,%ecx # ecx<- A+
+ sarl $4,rINST # rINST<- B
+ GET_VREG_R %eax rINST # eax<- vB
+ andb $0xf,%cl # ecx<- A
+ orl %eax,(rFP,%ecx,4) # for ex: addl %eax,(rFP,%ecx,4)
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_XOR_INT_2ADDR: /* 0xb7 */
+/* File: x86/OP_XOR_INT_2ADDR.S */
+/* File: x86/binop2addr.S */
+ /*
+ * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
+ * that specifies an instruction that performs "result = r0 op r1".
+ * This could be an ARM instruction or a function call. (If the result
+ * comes back in a register other than r0, you can override "result".)
+ *
+ * If "chkzero" is set to 1, we perform a divide-by-zero check on
+ * vCC (r1). Useful for integer division and modulus.
+ *
+ * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
+ * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
+ * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
+ * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
+ */
+ /* binop/2addr vA, vB */
+ movzx rINSTbl,%ecx # ecx<- A+
+ sarl $4,rINST # rINST<- B
+ GET_VREG_R %eax rINST # eax<- vB
+ andb $0xf,%cl # ecx<- A
+ xorl %eax,(rFP,%ecx,4) # for ex: addl %eax,(rFP,%ecx,4)
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_SHL_INT_2ADDR: /* 0xb8 */
+/* File: x86/OP_SHL_INT_2ADDR.S */
+/* File: x86/shop2addr.S */
+ /*
+ * Generic 32-bit "shift/2addr" operation.
+ */
+ /* shift/2addr vA, vB */
+ movzx rINSTbl,%ecx # eax<- BA
+ sarl $4,%ecx # ecx<- B
+ GET_VREG_R %ecx %ecx # eax<- vBB
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_R %eax rINST # eax<- vAA
+ sall %cl,%eax # ex: sarl %cl,%eax
+ FETCH_INST_OPCODE 1 %ecx
+ SET_VREG %eax rINST
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_SHR_INT_2ADDR: /* 0xb9 */
+/* File: x86/OP_SHR_INT_2ADDR.S */
+/* File: x86/shop2addr.S */
+ /*
+ * Generic 32-bit "shift/2addr" operation.
+ */
+ /* shift/2addr vA, vB */
+ movzx rINSTbl,%ecx # eax<- BA
+ sarl $4,%ecx # ecx<- B
+ GET_VREG_R %ecx %ecx # eax<- vBB
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_R %eax rINST # eax<- vAA
+ sarl %cl,%eax # ex: sarl %cl,%eax
+ FETCH_INST_OPCODE 1 %ecx
+ SET_VREG %eax rINST
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_USHR_INT_2ADDR: /* 0xba */
+/* File: x86/OP_USHR_INT_2ADDR.S */
+/* File: x86/shop2addr.S */
+ /*
+ * Generic 32-bit "shift/2addr" operation.
+ */
+ /* shift/2addr vA, vB */
+ movzx rINSTbl,%ecx # eax<- BA
+ sarl $4,%ecx # ecx<- B
+ GET_VREG_R %ecx %ecx # eax<- vBB
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_R %eax rINST # eax<- vAA
+ shrl %cl,%eax # ex: sarl %cl,%eax
+ FETCH_INST_OPCODE 1 %ecx
+ SET_VREG %eax rINST
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_ADD_LONG_2ADDR: /* 0xbb */
+/* File: x86/OP_ADD_LONG_2ADDR.S */
+/* File: x86/binopWide2addr.S */
+ /*
+ * Generic 64-bit binary operation.
+ */
+ /* binop/2addr vA, vB */
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ GET_VREG_WORD %eax %ecx 0 # eax<- v[B+0]
+ GET_VREG_WORD %ecx %ecx 1 # eax<- v[B+1]
+ andb $0xF,rINSTbl # rINST<- A
+ addl %eax,(rFP,rINST,4) # example: addl %eax,(rFP,rINST,4)
+ adcl %ecx,4(rFP,rINST,4) # example: adcl %ecx,4(rFP,rINST,4)
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_SUB_LONG_2ADDR: /* 0xbc */
+/* File: x86/OP_SUB_LONG_2ADDR.S */
+/* File: x86/binopWide2addr.S */
+ /*
+ * Generic 64-bit binary operation.
+ */
+ /* binop/2addr vA, vB */
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ GET_VREG_WORD %eax %ecx 0 # eax<- v[B+0]
+ GET_VREG_WORD %ecx %ecx 1 # eax<- v[B+1]
+ andb $0xF,rINSTbl # rINST<- A
+ subl %eax,(rFP,rINST,4) # example: addl %eax,(rFP,rINST,4)
+ sbbl %ecx,4(rFP,rINST,4) # example: adcl %ecx,4(rFP,rINST,4)
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_MUL_LONG_2ADDR: /* 0xbd */
+/* File: x86/OP_MUL_LONG_2ADDR.S */
+ /*
+ * Signed 64-bit integer multiply, 2-addr version
+ *
+ * We could definately use more free registers for
+ * this code. We must spill %edx (rIBASE) because it
+ * is used by imul. We'll also spill rINST (ebx),
+ * giving us eax, ebc, ecx and rIBASE as computational
+ * temps. On top of that, we'll spill %esi (edi)
+ * for use as the vA pointer and rFP (esi) for use
+ * as the vB pointer. Yuck.
+ */
+ /* mul-long/2addr vA, vB */
+ movzbl rINSTbl,%eax # eax<- BA
+ andb $0xf,%al # eax<- A
+ sarl $4,rINST # rINST<- B
+ SPILL_TMP2(%esi)
+ SPILL(rFP)
+ SPILL(rIBASE)
+ leal (rFP,%eax,4),%esi # %esi<- &v[A]
+ leal (rFP,rINST,4),rFP # rFP<- &v[B]
+ movl 4(%esi),%ecx # ecx<- Amsw
+ imull (rFP),%ecx # ecx<- (Amsw*Blsw)
+ movl 4(rFP),%eax # eax<- Bmsw
+ imull (%esi),%eax # eax<- (Bmsw*Alsw)
+ addl %eax,%ecx # ecx<- (Amsw*Blsw)+(Bmsw*Alsw)
+ movl (rFP),%eax # eax<- Blsw
+ mull (%esi) # eax<- (Blsw*Alsw)
+ leal (%ecx,rIBASE),rIBASE # full result now in %edx:%eax
+ movl rIBASE,4(%esi) # v[A+1]<- rIBASE
movl %eax,(%esi) # v[A]<- %eax
UNSPILL_TMP2(%esi)
FETCH_INST_OPCODE 1 %ecx
+ UNSPILL(rIBASE)
UNSPILL(rFP)
ADVANCE_PC 1
GOTO_NEXT_R %ecx
-/* continuation for OP_DIV_LONG_2ADDR */
-
-.LOP_DIV_LONG_2ADDR_continue:
+/* ------------------------------ */
+.L_OP_DIV_LONG_2ADDR: /* 0xbe */
+/* File: x86/OP_DIV_LONG_2ADDR.S */
+ /* div/2addr vA, vB */
+ movzbl rINSTbl,%eax
+ shrl $4,%eax # eax<- B
+ andb $0xf,rINSTbl # rINST<- A
+ SPILL(rIBASE) # save rIBASE/%edx
+ GET_VREG_WORD rIBASE %eax 0
+ GET_VREG_WORD %eax %eax 1
+ movl rIBASE,OUT_ARG2(%esp)
+ testl %eax,%eax
+ je .LOP_DIV_LONG_2ADDR_check_zero
+ cmpl $-1,%eax
+ je .LOP_DIV_LONG_2ADDR_check_neg1
+.LOP_DIV_LONG_2ADDR_notSpecial:
+ GET_VREG_WORD rIBASE rINST 0
+ GET_VREG_WORD %ecx rINST 1
+.LOP_DIV_LONG_2ADDR_notSpecial1:
movl %eax,OUT_ARG3(%esp)
- movl %edx,OUT_ARG0(%esp)
+ movl rIBASE,OUT_ARG0(%esp)
movl %ecx,OUT_ARG1(%esp)
call __divdi3
.LOP_DIV_LONG_2ADDR_finish:
- SET_VREG_WORD %edx rINST 1
+ SET_VREG_WORD rIBASE rINST 1
+ UNSPILL(rIBASE) # restore rIBASE/%edx
SET_VREG_WORD %eax rINST 0
- FETCH_INST_OPCODE 1 %edx
+ FETCH_INST_OPCODE 1 %ecx
ADVANCE_PC 1
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
.LOP_DIV_LONG_2ADDR_check_zero:
- testl %edx,%edx
+ testl rIBASE,rIBASE
jne .LOP_DIV_LONG_2ADDR_notSpecial
jmp common_errDivideByZero
.LOP_DIV_LONG_2ADDR_check_neg1:
- testl %edx,%eax
+ testl rIBASE,%eax
jne .LOP_DIV_LONG_2ADDR_notSpecial
- GET_VREG_WORD %edx rINST 0
+ GET_VREG_WORD rIBASE rINST 0
GET_VREG_WORD %ecx rINST 1
- testl %edx,%edx
+ testl rIBASE,rIBASE
jne .LOP_DIV_LONG_2ADDR_notSpecial1
cmpl $0x80000000,%ecx
jne .LOP_DIV_LONG_2ADDR_notSpecial1
/* minint / -1, return minint on div, 0 on rem */
xorl %eax,%eax
- movl $0x80000000,%edx
+ movl $0x80000000,rIBASE
jmp .LOP_DIV_LONG_2ADDR_finish
-/* continuation for OP_REM_LONG_2ADDR */
-
-.LOP_REM_LONG_2ADDR_continue:
+/* ------------------------------ */
+.L_OP_REM_LONG_2ADDR: /* 0xbf */
+/* File: x86/OP_REM_LONG_2ADDR.S */
+/* File: x86/OP_DIV_LONG_2ADDR.S */
+ /* div/2addr vA, vB */
+ movzbl rINSTbl,%eax
+ shrl $4,%eax # eax<- B
+ andb $0xf,rINSTbl # rINST<- A
+ SPILL(rIBASE) # save rIBASE/%edx
+ GET_VREG_WORD rIBASE %eax 0
+ GET_VREG_WORD %eax %eax 1
+ movl rIBASE,OUT_ARG2(%esp)
+ testl %eax,%eax
+ je .LOP_REM_LONG_2ADDR_check_zero
+ cmpl $-1,%eax
+ je .LOP_REM_LONG_2ADDR_check_neg1
+.LOP_REM_LONG_2ADDR_notSpecial:
+ GET_VREG_WORD rIBASE rINST 0
+ GET_VREG_WORD %ecx rINST 1
+.LOP_REM_LONG_2ADDR_notSpecial1:
movl %eax,OUT_ARG3(%esp)
- movl %edx,OUT_ARG0(%esp)
+ movl rIBASE,OUT_ARG0(%esp)
movl %ecx,OUT_ARG1(%esp)
call __moddi3
.LOP_REM_LONG_2ADDR_finish:
- SET_VREG_WORD %edx rINST 1
+ SET_VREG_WORD rIBASE rINST 1
+ UNSPILL(rIBASE) # restore rIBASE/%edx
SET_VREG_WORD %eax rINST 0
- FETCH_INST_OPCODE 1 %edx
+ FETCH_INST_OPCODE 1 %ecx
ADVANCE_PC 1
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
.LOP_REM_LONG_2ADDR_check_zero:
- testl %edx,%edx
+ testl rIBASE,rIBASE
jne .LOP_REM_LONG_2ADDR_notSpecial
jmp common_errDivideByZero
.LOP_REM_LONG_2ADDR_check_neg1:
- testl %edx,%eax
+ testl rIBASE,%eax
jne .LOP_REM_LONG_2ADDR_notSpecial
- GET_VREG_WORD %edx rINST 0
+ GET_VREG_WORD rIBASE rINST 0
GET_VREG_WORD %ecx rINST 1
- testl %edx,%edx
+ testl rIBASE,rIBASE
jne .LOP_REM_LONG_2ADDR_notSpecial1
cmpl $0x80000000,%ecx
jne .LOP_REM_LONG_2ADDR_notSpecial1
/* minint / -1, return minint on div, 0 on rem */
xorl %eax,%eax
- movl $0,%edx
+ movl $0,rIBASE
jmp .LOP_REM_LONG_2ADDR_finish
-/* continuation for OP_SHL_LONG_2ADDR */
+
+/* ------------------------------ */
+.L_OP_AND_LONG_2ADDR: /* 0xc0 */
+/* File: x86/OP_AND_LONG_2ADDR.S */
+/* File: x86/binopWide2addr.S */
+ /*
+ * Generic 64-bit binary operation.
+ */
+ /* binop/2addr vA, vB */
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ GET_VREG_WORD %eax %ecx 0 # eax<- v[B+0]
+ GET_VREG_WORD %ecx %ecx 1 # eax<- v[B+1]
+ andb $0xF,rINSTbl # rINST<- A
+ andl %eax,(rFP,rINST,4) # example: addl %eax,(rFP,rINST,4)
+ andl %ecx,4(rFP,rINST,4) # example: adcl %ecx,4(rFP,rINST,4)
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
-.LOP_SHL_LONG_2ADDR_finish:
- FETCH_INST_OPCODE 1 %edx
+/* ------------------------------ */
+.L_OP_OR_LONG_2ADDR: /* 0xc1 */
+/* File: x86/OP_OR_LONG_2ADDR.S */
+/* File: x86/binopWide2addr.S */
+ /*
+ * Generic 64-bit binary operation.
+ */
+ /* binop/2addr vA, vB */
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ GET_VREG_WORD %eax %ecx 0 # eax<- v[B+0]
+ GET_VREG_WORD %ecx %ecx 1 # eax<- v[B+1]
+ andb $0xF,rINSTbl # rINST<- A
+ orl %eax,(rFP,rINST,4) # example: addl %eax,(rFP,rINST,4)
+ orl %ecx,4(rFP,rINST,4) # example: adcl %ecx,4(rFP,rINST,4)
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_XOR_LONG_2ADDR: /* 0xc2 */
+/* File: x86/OP_XOR_LONG_2ADDR.S */
+/* File: x86/binopWide2addr.S */
+ /*
+ * Generic 64-bit binary operation.
+ */
+ /* binop/2addr vA, vB */
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ GET_VREG_WORD %eax %ecx 0 # eax<- v[B+0]
+ GET_VREG_WORD %ecx %ecx 1 # eax<- v[B+1]
+ andb $0xF,rINSTbl # rINST<- A
+ xorl %eax,(rFP,rINST,4) # example: addl %eax,(rFP,rINST,4)
+ xorl %ecx,4(rFP,rINST,4) # example: adcl %ecx,4(rFP,rINST,4)
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_SHL_LONG_2ADDR: /* 0xc3 */
+/* File: x86/OP_SHL_LONG_2ADDR.S */
+ /*
+ * Long integer shift, 2addr version. vA is 64-bit value/result, vB is
+ * 32-bit shift distance.
+ */
+ /* shl-long/2addr vA, vB */
+ /* ecx gets shift count */
+ /* Need to spill rIBASE */
+ /* rINSTw gets AA */
+ movzbl rINSTbl,%ecx # ecx<- BA
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_WORD %eax rINST 0 # eax<- v[AA+0]
+ sarl $4,%ecx # ecx<- B
+ SPILL(rIBASE)
+ GET_VREG_WORD rIBASE rINST 1 # rIBASE<- v[AA+1]
+ GET_VREG_R %ecx %ecx # ecx<- vBB
+ shldl %eax,rIBASE
+ sall %cl,%eax
+ testb $32,%cl
+ je 2f
+ movl %eax,rIBASE
+ xorl %eax,%eax
+2:
+ SET_VREG_WORD rIBASE rINST 1 # v[AA+1]<- rIBASE
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 1 %ecx
SET_VREG_WORD %eax rINST 0 # v[AA+0]<- eax
ADVANCE_PC 1
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_SHR_LONG_2ADDR */
-
-
-.LOP_SHR_LONG_2ADDR_finish:
- FETCH_INST_OPCODE 1 %edx
+/* ------------------------------ */
+.L_OP_SHR_LONG_2ADDR: /* 0xc4 */
+/* File: x86/OP_SHR_LONG_2ADDR.S */
+ /*
+ * Long integer shift, 2addr version. vA is 64-bit value/result, vB is
+ * 32-bit shift distance.
+ */
+ /* shl-long/2addr vA, vB */
+ /* ecx gets shift count */
+ /* Need to spill rIBASE */
+ /* rINSTw gets AA */
+ movzbl rINSTbl,%ecx # ecx<- BA
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_WORD %eax rINST 0 # eax<- v[AA+0]
+ sarl $4,%ecx # ecx<- B
+ SPILL(rIBASE)
+ GET_VREG_WORD rIBASE rINST 1 # rIBASE<- v[AA+1]
+ GET_VREG_R %ecx %ecx # ecx<- vBB
+ shrdl rIBASE,%eax
+ sarl %cl,rIBASE
+ testb $32,%cl
+ je 2f
+ movl rIBASE,%eax
+ sarl $31,rIBASE
+2:
+ SET_VREG_WORD rIBASE rINST 1 # v[AA+1]<- rIBASE
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 1 %ecx
SET_VREG_WORD %eax rINST 0 # v[AA+0]<- eax
ADVANCE_PC 1
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_USHR_LONG_2ADDR */
-
-
-.LOP_USHR_LONG_2ADDR_finish:
- FETCH_INST_OPCODE 1 %edx
+/* ------------------------------ */
+.L_OP_USHR_LONG_2ADDR: /* 0xc5 */
+/* File: x86/OP_USHR_LONG_2ADDR.S */
+ /*
+ * Long integer shift, 2addr version. vA is 64-bit value/result, vB is
+ * 32-bit shift distance.
+ */
+ /* shl-long/2addr vA, vB */
+ /* ecx gets shift count */
+ /* Need to spill rIBASE */
+ /* rINSTw gets AA */
+ movzbl rINSTbl,%ecx # ecx<- BA
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_WORD %eax rINST 0 # eax<- v[AA+0]
+ sarl $4,%ecx # ecx<- B
+ SPILL(rIBASE)
+ GET_VREG_WORD rIBASE rINST 1 # rIBASE<- v[AA+1]
+ GET_VREG_R %ecx %ecx # ecx<- vBB
+ shrdl rIBASE,%eax
+ shrl %cl,rIBASE
+ testb $32,%cl
+ je 2f
+ movl rIBASE,%eax
+ xorl rIBASE,rIBASE
+2:
+ SET_VREG_WORD rIBASE rINST 1 # v[AA+1]<- rIBASE
+ FETCH_INST_OPCODE 1 %ecx
+ UNSPILL(rIBASE)
SET_VREG_WORD %eax rINST 0 # v[AA+0]<- eax
ADVANCE_PC 1
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_DIV_INT_LIT16 */
+/* ------------------------------ */
+.L_OP_ADD_FLOAT_2ADDR: /* 0xc6 */
+/* File: x86/OP_ADD_FLOAT_2ADDR.S */
+/* File: x86/binflop2addr.S */
+ /*
+ * Generic 32-bit binary float operation.
+ *
+ * For: add-fp, sub-fp, mul-fp, div-fp
+ */
+
+ /* binop/2addr vA, vB */
+ movzx rINSTbl,%ecx # ecx<- A+
+ andb $0xf,%cl # ecx<- A
+ flds (rFP,%ecx,4) # vAA to fp stack
+ sarl $4,rINST # rINST<- B
+ fadds (rFP,rINST,4) # ex: faddp
+ FETCH_INST_OPCODE 1 %eax
+ ADVANCE_PC 1
+ fstps (rFP,%ecx,4) # %st to vA
+ GOTO_NEXT_R %eax
+
+
+/* ------------------------------ */
+.L_OP_SUB_FLOAT_2ADDR: /* 0xc7 */
+/* File: x86/OP_SUB_FLOAT_2ADDR.S */
+/* File: x86/binflop2addr.S */
+ /*
+ * Generic 32-bit binary float operation.
+ *
+ * For: add-fp, sub-fp, mul-fp, div-fp
+ */
+
+ /* binop/2addr vA, vB */
+ movzx rINSTbl,%ecx # ecx<- A+
+ andb $0xf,%cl # ecx<- A
+ flds (rFP,%ecx,4) # vAA to fp stack
+ sarl $4,rINST # rINST<- B
+ fsubs (rFP,rINST,4) # ex: faddp
+ FETCH_INST_OPCODE 1 %eax
+ ADVANCE_PC 1
+ fstps (rFP,%ecx,4) # %st to vA
+ GOTO_NEXT_R %eax
+
+
+/* ------------------------------ */
+.L_OP_MUL_FLOAT_2ADDR: /* 0xc8 */
+/* File: x86/OP_MUL_FLOAT_2ADDR.S */
+/* File: x86/binflop2addr.S */
+ /*
+ * Generic 32-bit binary float operation.
+ *
+ * For: add-fp, sub-fp, mul-fp, div-fp
+ */
+
+ /* binop/2addr vA, vB */
+ movzx rINSTbl,%ecx # ecx<- A+
+ andb $0xf,%cl # ecx<- A
+ flds (rFP,%ecx,4) # vAA to fp stack
+ sarl $4,rINST # rINST<- B
+ fmuls (rFP,rINST,4) # ex: faddp
+ FETCH_INST_OPCODE 1 %eax
+ ADVANCE_PC 1
+ fstps (rFP,%ecx,4) # %st to vA
+ GOTO_NEXT_R %eax
+
+
+/* ------------------------------ */
+.L_OP_DIV_FLOAT_2ADDR: /* 0xc9 */
+/* File: x86/OP_DIV_FLOAT_2ADDR.S */
+/* File: x86/binflop2addr.S */
+ /*
+ * Generic 32-bit binary float operation.
+ *
+ * For: add-fp, sub-fp, mul-fp, div-fp
+ */
+
+ /* binop/2addr vA, vB */
+ movzx rINSTbl,%ecx # ecx<- A+
+ andb $0xf,%cl # ecx<- A
+ flds (rFP,%ecx,4) # vAA to fp stack
+ sarl $4,rINST # rINST<- B
+ fdivs (rFP,rINST,4) # ex: faddp
+ FETCH_INST_OPCODE 1 %eax
+ ADVANCE_PC 1
+ fstps (rFP,%ecx,4) # %st to vA
+ GOTO_NEXT_R %eax
+
+
+/* ------------------------------ */
+.L_OP_REM_FLOAT_2ADDR: /* 0xca */
+/* File: x86/OP_REM_FLOAT_2ADDR.S */
+ /* rem_float/2addr vA, vB */
+ movzx rINSTbl,%ecx # ecx<- A+
+ sarl $4,rINST # rINST<- B
+ flds (rFP,rINST,4) # vBB to fp stack
+ andb $0xf,%cl # ecx<- A
+ flds (rFP,%ecx,4) # vAA to fp stack
+1:
+ fprem
+ fstsw %ax
+ sahf
+ jp 1b
+ fstp %st(1)
+ FETCH_INST_OPCODE 1 %eax
+ ADVANCE_PC 1
+ fstps (rFP,%ecx,4) # %st to vA
+ GOTO_NEXT_R %eax
+
+/* ------------------------------ */
+.L_OP_ADD_DOUBLE_2ADDR: /* 0xcb */
+/* File: x86/OP_ADD_DOUBLE_2ADDR.S */
+/* File: x86/binflop2addr.S */
+ /*
+ * Generic 32-bit binary float operation.
+ *
+ * For: add-fp, sub-fp, mul-fp, div-fp
+ */
+
+ /* binop/2addr vA, vB */
+ movzx rINSTbl,%ecx # ecx<- A+
+ andb $0xf,%cl # ecx<- A
+ fldl (rFP,%ecx,4) # vAA to fp stack
+ sarl $4,rINST # rINST<- B
+ faddl (rFP,rINST,4) # ex: faddp
+ FETCH_INST_OPCODE 1 %eax
+ ADVANCE_PC 1
+ fstpl (rFP,%ecx,4) # %st to vA
+ GOTO_NEXT_R %eax
+
+
+/* ------------------------------ */
+.L_OP_SUB_DOUBLE_2ADDR: /* 0xcc */
+/* File: x86/OP_SUB_DOUBLE_2ADDR.S */
+/* File: x86/binflop2addr.S */
+ /*
+ * Generic 32-bit binary float operation.
+ *
+ * For: add-fp, sub-fp, mul-fp, div-fp
+ */
+
+ /* binop/2addr vA, vB */
+ movzx rINSTbl,%ecx # ecx<- A+
+ andb $0xf,%cl # ecx<- A
+ fldl (rFP,%ecx,4) # vAA to fp stack
+ sarl $4,rINST # rINST<- B
+ fsubl (rFP,rINST,4) # ex: faddp
+ FETCH_INST_OPCODE 1 %eax
+ ADVANCE_PC 1
+ fstpl (rFP,%ecx,4) # %st to vA
+ GOTO_NEXT_R %eax
+
+
+/* ------------------------------ */
+.L_OP_MUL_DOUBLE_2ADDR: /* 0xcd */
+/* File: x86/OP_MUL_DOUBLE_2ADDR.S */
+/* File: x86/binflop2addr.S */
+ /*
+ * Generic 32-bit binary float operation.
+ *
+ * For: add-fp, sub-fp, mul-fp, div-fp
+ */
+
+ /* binop/2addr vA, vB */
+ movzx rINSTbl,%ecx # ecx<- A+
+ andb $0xf,%cl # ecx<- A
+ fldl (rFP,%ecx,4) # vAA to fp stack
+ sarl $4,rINST # rINST<- B
+ fmull (rFP,rINST,4) # ex: faddp
+ FETCH_INST_OPCODE 1 %eax
+ ADVANCE_PC 1
+ fstpl (rFP,%ecx,4) # %st to vA
+ GOTO_NEXT_R %eax
+
+
+/* ------------------------------ */
+.L_OP_DIV_DOUBLE_2ADDR: /* 0xce */
+/* File: x86/OP_DIV_DOUBLE_2ADDR.S */
+/* File: x86/binflop2addr.S */
+ /*
+ * Generic 32-bit binary float operation.
+ *
+ * For: add-fp, sub-fp, mul-fp, div-fp
+ */
+
+ /* binop/2addr vA, vB */
+ movzx rINSTbl,%ecx # ecx<- A+
+ andb $0xf,%cl # ecx<- A
+ fldl (rFP,%ecx,4) # vAA to fp stack
+ sarl $4,rINST # rINST<- B
+ fdivl (rFP,rINST,4) # ex: faddp
+ FETCH_INST_OPCODE 1 %eax
+ ADVANCE_PC 1
+ fstpl (rFP,%ecx,4) # %st to vA
+ GOTO_NEXT_R %eax
+
+
+/* ------------------------------ */
+.L_OP_REM_DOUBLE_2ADDR: /* 0xcf */
+/* File: x86/OP_REM_DOUBLE_2ADDR.S */
+ /* rem_float/2addr vA, vB */
+ movzx rINSTbl,%ecx # ecx<- A+
+ sarl $4,rINST # rINST<- B
+ fldl (rFP,rINST,4) # vBB to fp stack
+ andb $0xf,%cl # ecx<- A
+ fldl (rFP,%ecx,4) # vAA to fp stack
+1:
+ fprem
+ fstsw %ax
+ sahf
+ jp 1b
+ fstp %st(1)
+ FETCH_INST_OPCODE 1 %eax
+ ADVANCE_PC 1
+ fstpl (rFP,%ecx,4) # %st to vA
+ GOTO_NEXT_R %eax
+
+/* ------------------------------ */
+.L_OP_ADD_INT_LIT16: /* 0xd0 */
+/* File: x86/OP_ADD_INT_LIT16.S */
+/* File: x86/binopLit16.S */
+ /*
+ * Generic 32-bit "lit16" binary operation. Provide an "instr" line
+ * that specifies an instruction that performs "result = eax op ecx".
+ * This could be an x86 instruction or a function call. (If the result
+ * comes back in a register other than eax, you can override "result".)
+ *
+ * For: add-int/lit16, rsub-int,
+ * and-int/lit16, or-int/lit16, xor-int/lit16
+ */
+ /* binop/lit16 vA, vB, #+CCCC */
+ movzbl rINSTbl,%eax # eax<- 000000BA
+ sarl $4,%eax # eax<- B
+ GET_VREG_R %eax %eax # eax<- vB
+ movswl 2(rPC),%ecx # ecx<- ssssCCCC
+ andb $0xf,rINSTbl # rINST<- A
+ addl %ecx,%eax # for example: addl %ecx, %eax
+ SET_VREG %eax rINST
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_RSUB_INT: /* 0xd1 */
+/* File: x86/OP_RSUB_INT.S */
+/* File: x86/binopLit16.S */
+ /*
+ * Generic 32-bit "lit16" binary operation. Provide an "instr" line
+ * that specifies an instruction that performs "result = eax op ecx".
+ * This could be an x86 instruction or a function call. (If the result
+ * comes back in a register other than eax, you can override "result".)
+ *
+ * For: add-int/lit16, rsub-int,
+ * and-int/lit16, or-int/lit16, xor-int/lit16
+ */
+ /* binop/lit16 vA, vB, #+CCCC */
+ movzbl rINSTbl,%eax # eax<- 000000BA
+ sarl $4,%eax # eax<- B
+ GET_VREG_R %eax %eax # eax<- vB
+ movswl 2(rPC),%ecx # ecx<- ssssCCCC
+ andb $0xf,rINSTbl # rINST<- A
+ subl %eax,%ecx # for example: addl %ecx, %eax
+ SET_VREG %ecx rINST
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_MUL_INT_LIT16: /* 0xd2 */
+/* File: x86/OP_MUL_INT_LIT16.S */
+ /* mul/lit16 vA, vB, #+CCCC */
+ /* Need A in rINST, ssssCCCC in ecx, vB in eax */
+ movzbl rINSTbl,%eax # eax<- 000000BA
+ sarl $4,%eax # eax<- B
+ GET_VREG_R %eax %eax # eax<- vB
+ movswl 2(rPC),%ecx # ecx<- ssssCCCC
+ andb $0xf,rINSTbl # rINST<- A
+ SPILL(rIBASE)
+ imull %ecx,%eax # trashes rIBASE/edx
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ SET_VREG %eax rINST
+ GOTO_NEXT_R %ecx
+
+/* ------------------------------ */
+.L_OP_DIV_INT_LIT16: /* 0xd3 */
+/* File: x86/OP_DIV_INT_LIT16.S */
+/* File: x86/bindivLit16.S */
+ /*
+ * 32-bit binary div/rem operation. Handles special case of op0=minint and
+ * op1=-1.
+ */
+ /* div/rem/lit16 vA, vB, #+CCCC */
+ /* Need A in rINST, ssssCCCC in ecx, vB in eax */
+ movzbl rINSTbl,%eax # eax<- 000000BA
+ SPILL(rIBASE)
+ sarl $4,%eax # eax<- B
+ GET_VREG_R %eax %eax # eax<- vB
+ movswl 2(rPC),%ecx # ecx<- ssssCCCC
+ andb $0xf,rINSTbl # rINST<- A
+ cmpl $0,%ecx
+ je common_errDivideByZero
+ cmpl $-1,%ecx
+ jne .LOP_DIV_INT_LIT16_continue_div
+ cmpl $0x80000000,%eax
+ jne .LOP_DIV_INT_LIT16_continue_div
+ movl $0x80000000,%eax
+ SET_VREG %eax rINST
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
.LOP_DIV_INT_LIT16_continue_div:
cltd
idivl %ecx
-.LOP_DIV_INT_LIT16_finish_div:
SET_VREG %eax rINST
- FETCH_INST_OPCODE 2 %edx
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_REM_INT_LIT16 */
+
+/* ------------------------------ */
+.L_OP_REM_INT_LIT16: /* 0xd4 */
+/* File: x86/OP_REM_INT_LIT16.S */
+/* File: x86/bindivLit16.S */
+ /*
+ * 32-bit binary div/rem operation. Handles special case of op0=minint and
+ * op1=-1.
+ */
+ /* div/rem/lit16 vA, vB, #+CCCC */
+ /* Need A in rINST, ssssCCCC in ecx, vB in eax */
+ movzbl rINSTbl,%eax # eax<- 000000BA
+ SPILL(rIBASE)
+ sarl $4,%eax # eax<- B
+ GET_VREG_R %eax %eax # eax<- vB
+ movswl 2(rPC),%ecx # ecx<- ssssCCCC
+ andb $0xf,rINSTbl # rINST<- A
+ cmpl $0,%ecx
+ je common_errDivideByZero
+ cmpl $-1,%ecx
+ jne .LOP_REM_INT_LIT16_continue_div
+ cmpl $0x80000000,%eax
+ jne .LOP_REM_INT_LIT16_continue_div
+ movl $0,rIBASE
+ SET_VREG rIBASE rINST
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
.LOP_REM_INT_LIT16_continue_div:
cltd
idivl %ecx
-.LOP_REM_INT_LIT16_finish_div:
- SET_VREG %edx rINST
- FETCH_INST_OPCODE 2 %edx
+ SET_VREG rIBASE rINST
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_DIV_INT_LIT8 */
+
+/* ------------------------------ */
+.L_OP_AND_INT_LIT16: /* 0xd5 */
+/* File: x86/OP_AND_INT_LIT16.S */
+/* File: x86/binopLit16.S */
+ /*
+ * Generic 32-bit "lit16" binary operation. Provide an "instr" line
+ * that specifies an instruction that performs "result = eax op ecx".
+ * This could be an x86 instruction or a function call. (If the result
+ * comes back in a register other than eax, you can override "result".)
+ *
+ * For: add-int/lit16, rsub-int,
+ * and-int/lit16, or-int/lit16, xor-int/lit16
+ */
+ /* binop/lit16 vA, vB, #+CCCC */
+ movzbl rINSTbl,%eax # eax<- 000000BA
+ sarl $4,%eax # eax<- B
+ GET_VREG_R %eax %eax # eax<- vB
+ movswl 2(rPC),%ecx # ecx<- ssssCCCC
+ andb $0xf,rINSTbl # rINST<- A
+ andl %ecx,%eax # for example: addl %ecx, %eax
+ SET_VREG %eax rINST
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_OR_INT_LIT16: /* 0xd6 */
+/* File: x86/OP_OR_INT_LIT16.S */
+/* File: x86/binopLit16.S */
+ /*
+ * Generic 32-bit "lit16" binary operation. Provide an "instr" line
+ * that specifies an instruction that performs "result = eax op ecx".
+ * This could be an x86 instruction or a function call. (If the result
+ * comes back in a register other than eax, you can override "result".)
+ *
+ * For: add-int/lit16, rsub-int,
+ * and-int/lit16, or-int/lit16, xor-int/lit16
+ */
+ /* binop/lit16 vA, vB, #+CCCC */
+ movzbl rINSTbl,%eax # eax<- 000000BA
+ sarl $4,%eax # eax<- B
+ GET_VREG_R %eax %eax # eax<- vB
+ movswl 2(rPC),%ecx # ecx<- ssssCCCC
+ andb $0xf,rINSTbl # rINST<- A
+ orl %ecx,%eax # for example: addl %ecx, %eax
+ SET_VREG %eax rINST
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_XOR_INT_LIT16: /* 0xd7 */
+/* File: x86/OP_XOR_INT_LIT16.S */
+/* File: x86/binopLit16.S */
+ /*
+ * Generic 32-bit "lit16" binary operation. Provide an "instr" line
+ * that specifies an instruction that performs "result = eax op ecx".
+ * This could be an x86 instruction or a function call. (If the result
+ * comes back in a register other than eax, you can override "result".)
+ *
+ * For: add-int/lit16, rsub-int,
+ * and-int/lit16, or-int/lit16, xor-int/lit16
+ */
+ /* binop/lit16 vA, vB, #+CCCC */
+ movzbl rINSTbl,%eax # eax<- 000000BA
+ sarl $4,%eax # eax<- B
+ GET_VREG_R %eax %eax # eax<- vB
+ movswl 2(rPC),%ecx # ecx<- ssssCCCC
+ andb $0xf,rINSTbl # rINST<- A
+ xor %ecx,%eax # for example: addl %ecx, %eax
+ SET_VREG %eax rINST
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_ADD_INT_LIT8: /* 0xd8 */
+/* File: x86/OP_ADD_INT_LIT8.S */
+/* File: x86/binopLit8.S */
+ /*
+ * Generic 32-bit "lit8" binary operation. Provide an "instr" line
+ * that specifies an instruction that performs "result = eax op ecx".
+ * This could be an x86 instruction or a function call. (If the result
+ * comes back in a register other than r0, you can override "result".)
+ *
+ * For: add-int/lit8, rsub-int/lit8
+ * and-int/lit8, or-int/lit8, xor-int/lit8,
+ * shl-int/lit8, shr-int/lit8, ushr-int/lit8
+ */
+ /* binop/lit8 vAA, vBB, #+CC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movsbl 3(rPC),%ecx # ecx<- ssssssCC
+ GET_VREG_R %eax %eax # eax<- rBB
+ addl %ecx,%eax # ex: addl %ecx,%eax
+ SET_VREG %eax rINST
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_RSUB_INT_LIT8: /* 0xd9 */
+/* File: x86/OP_RSUB_INT_LIT8.S */
+/* File: x86/binopLit8.S */
+ /*
+ * Generic 32-bit "lit8" binary operation. Provide an "instr" line
+ * that specifies an instruction that performs "result = eax op ecx".
+ * This could be an x86 instruction or a function call. (If the result
+ * comes back in a register other than r0, you can override "result".)
+ *
+ * For: add-int/lit8, rsub-int/lit8
+ * and-int/lit8, or-int/lit8, xor-int/lit8,
+ * shl-int/lit8, shr-int/lit8, ushr-int/lit8
+ */
+ /* binop/lit8 vAA, vBB, #+CC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movsbl 3(rPC),%ecx # ecx<- ssssssCC
+ GET_VREG_R %eax %eax # eax<- rBB
+ subl %eax,%ecx # ex: addl %ecx,%eax
+ SET_VREG %ecx rINST
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_MUL_INT_LIT8: /* 0xda */
+/* File: x86/OP_MUL_INT_LIT8.S */
+ /* mul/lit8 vAA, vBB, #+CC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movsbl 3(rPC),%ecx # ecx<- ssssssCC
+ GET_VREG_R %eax %eax # eax<- rBB
+ SPILL(rIBASE)
+ imull %ecx,%eax # trashes rIBASE/edx
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ SET_VREG %eax rINST
+ GOTO_NEXT_R %ecx
+
+/* ------------------------------ */
+.L_OP_DIV_INT_LIT8: /* 0xdb */
+/* File: x86/OP_DIV_INT_LIT8.S */
+/* File: x86/bindivLit8.S */
+ /*
+ * 32-bit div/rem "lit8" binary operation. Handles special case of
+ * op0=minint & op1=-1
+ */
+ /* div/rem/lit8 vAA, vBB, #+CC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movsbl 3(rPC),%ecx # ecx<- ssssssCC
+ SPILL(rIBASE)
+ GET_VREG_R %eax %eax # eax<- rBB
+ cmpl $0,%ecx
+ je common_errDivideByZero
+ cmpl $0x80000000,%eax
+ jne .LOP_DIV_INT_LIT8_continue_div
+ cmpl $-1,%ecx
+ jne .LOP_DIV_INT_LIT8_continue_div
+ movl $0x80000000,%eax
+ SET_VREG %eax rINST
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
.LOP_DIV_INT_LIT8_continue_div:
cltd
idivl %ecx
-.LOP_DIV_INT_LIT8_finish_div:
SET_VREG %eax rINST
- FETCH_INST_OPCODE 2 %edx
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_REM_INT_LIT8 */
+
+/* ------------------------------ */
+.L_OP_REM_INT_LIT8: /* 0xdc */
+/* File: x86/OP_REM_INT_LIT8.S */
+/* File: x86/bindivLit8.S */
+ /*
+ * 32-bit div/rem "lit8" binary operation. Handles special case of
+ * op0=minint & op1=-1
+ */
+ /* div/rem/lit8 vAA, vBB, #+CC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movsbl 3(rPC),%ecx # ecx<- ssssssCC
+ SPILL(rIBASE)
+ GET_VREG_R %eax %eax # eax<- rBB
+ cmpl $0,%ecx
+ je common_errDivideByZero
+ cmpl $0x80000000,%eax
+ jne .LOP_REM_INT_LIT8_continue_div
+ cmpl $-1,%ecx
+ jne .LOP_REM_INT_LIT8_continue_div
+ movl $0,rIBASE
+ SET_VREG rIBASE rINST
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
.LOP_REM_INT_LIT8_continue_div:
cltd
idivl %ecx
-.LOP_REM_INT_LIT8_finish_div:
- SET_VREG %edx rINST
- FETCH_INST_OPCODE 2 %edx
+ SET_VREG rIBASE rINST
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-/* continuation for OP_IGET_VOLATILE */
+ GOTO_NEXT_R %ecx
-.LOP_IGET_VOLATILE_resolve:
+/* ------------------------------ */
+.L_OP_AND_INT_LIT8: /* 0xdd */
+/* File: x86/OP_AND_INT_LIT8.S */
+/* File: x86/binopLit8.S */
+ /*
+ * Generic 32-bit "lit8" binary operation. Provide an "instr" line
+ * that specifies an instruction that performs "result = eax op ecx".
+ * This could be an x86 instruction or a function call. (If the result
+ * comes back in a register other than r0, you can override "result".)
+ *
+ * For: add-int/lit8, rsub-int/lit8
+ * and-int/lit8, or-int/lit8, xor-int/lit8,
+ * shl-int/lit8, shr-int/lit8, ushr-int/lit8
+ */
+ /* binop/lit8 vAA, vBB, #+CC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movsbl 3(rPC),%ecx # ecx<- ssssssCC
+ GET_VREG_R %eax %eax # eax<- rBB
+ andl %ecx,%eax # ex: addl %ecx,%eax
+ SET_VREG %eax rINST
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_OR_INT_LIT8: /* 0xde */
+/* File: x86/OP_OR_INT_LIT8.S */
+/* File: x86/binopLit8.S */
+ /*
+ * Generic 32-bit "lit8" binary operation. Provide an "instr" line
+ * that specifies an instruction that performs "result = eax op ecx".
+ * This could be an x86 instruction or a function call. (If the result
+ * comes back in a register other than r0, you can override "result".)
+ *
+ * For: add-int/lit8, rsub-int/lit8
+ * and-int/lit8, or-int/lit8, xor-int/lit8,
+ * shl-int/lit8, shr-int/lit8, ushr-int/lit8
+ */
+ /* binop/lit8 vAA, vBB, #+CC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movsbl 3(rPC),%ecx # ecx<- ssssssCC
+ GET_VREG_R %eax %eax # eax<- rBB
+ orl %ecx,%eax # ex: addl %ecx,%eax
+ SET_VREG %eax rINST
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_XOR_INT_LIT8: /* 0xdf */
+/* File: x86/OP_XOR_INT_LIT8.S */
+/* File: x86/binopLit8.S */
+ /*
+ * Generic 32-bit "lit8" binary operation. Provide an "instr" line
+ * that specifies an instruction that performs "result = eax op ecx".
+ * This could be an x86 instruction or a function call. (If the result
+ * comes back in a register other than r0, you can override "result".)
+ *
+ * For: add-int/lit8, rsub-int/lit8
+ * and-int/lit8, or-int/lit8, xor-int/lit8,
+ * shl-int/lit8, shr-int/lit8, ushr-int/lit8
+ */
+ /* binop/lit8 vAA, vBB, #+CC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movsbl 3(rPC),%ecx # ecx<- ssssssCC
+ GET_VREG_R %eax %eax # eax<- rBB
+ xor %ecx,%eax # ex: addl %ecx,%eax
+ SET_VREG %eax rINST
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_SHL_INT_LIT8: /* 0xe0 */
+/* File: x86/OP_SHL_INT_LIT8.S */
+/* File: x86/binopLit8.S */
+ /*
+ * Generic 32-bit "lit8" binary operation. Provide an "instr" line
+ * that specifies an instruction that performs "result = eax op ecx".
+ * This could be an x86 instruction or a function call. (If the result
+ * comes back in a register other than r0, you can override "result".)
+ *
+ * For: add-int/lit8, rsub-int/lit8
+ * and-int/lit8, or-int/lit8, xor-int/lit8,
+ * shl-int/lit8, shr-int/lit8, ushr-int/lit8
+ */
+ /* binop/lit8 vAA, vBB, #+CC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movsbl 3(rPC),%ecx # ecx<- ssssssCC
+ GET_VREG_R %eax %eax # eax<- rBB
+ sall %cl,%eax # ex: addl %ecx,%eax
+ SET_VREG %eax rINST
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_SHR_INT_LIT8: /* 0xe1 */
+/* File: x86/OP_SHR_INT_LIT8.S */
+/* File: x86/binopLit8.S */
+ /*
+ * Generic 32-bit "lit8" binary operation. Provide an "instr" line
+ * that specifies an instruction that performs "result = eax op ecx".
+ * This could be an x86 instruction or a function call. (If the result
+ * comes back in a register other than r0, you can override "result".)
+ *
+ * For: add-int/lit8, rsub-int/lit8
+ * and-int/lit8, or-int/lit8, xor-int/lit8,
+ * shl-int/lit8, shr-int/lit8, ushr-int/lit8
+ */
+ /* binop/lit8 vAA, vBB, #+CC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movsbl 3(rPC),%ecx # ecx<- ssssssCC
+ GET_VREG_R %eax %eax # eax<- rBB
+ sarl %cl,%eax # ex: addl %ecx,%eax
+ SET_VREG %eax rINST
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_USHR_INT_LIT8: /* 0xe2 */
+/* File: x86/OP_USHR_INT_LIT8.S */
+/* File: x86/binopLit8.S */
+ /*
+ * Generic 32-bit "lit8" binary operation. Provide an "instr" line
+ * that specifies an instruction that performs "result = eax op ecx".
+ * This could be an x86 instruction or a function call. (If the result
+ * comes back in a register other than r0, you can override "result".)
+ *
+ * For: add-int/lit8, rsub-int/lit8
+ * and-int/lit8, or-int/lit8, xor-int/lit8,
+ * shl-int/lit8, shr-int/lit8, ushr-int/lit8
+ */
+ /* binop/lit8 vAA, vBB, #+CC */
+ movzbl 2(rPC),%eax # eax<- BB
+ movsbl 3(rPC),%ecx # ecx<- ssssssCC
+ GET_VREG_R %eax %eax # eax<- rBB
+ shrl %cl,%eax # ex: addl %ecx,%eax
+ SET_VREG %eax rINST
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_IGET_VOLATILE: /* 0xe3 */
+/* File: x86/OP_IGET_VOLATILE.S */
+/* File: x86/OP_IGET.S */
+ /*
+ * General 32-bit instance field get.
+ *
+ * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
+ */
+ /* op vA, vB, field@CCCC */
+ movl rSELF,%ecx
+ SPILL(rIBASE) # preserve rIBASE
+ movzwl 2(rPC),rIBASE # rIBASE<- 0000CCCC
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IGET_VOLATILE_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp) # needed by dvmResolveInstField
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -11200,21 +7214,43 @@
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
movl (%ecx,%eax,1),%ecx # ecx<- obj.field (8/16/32 bits)
- movl rINST,%eax # eax<- A
- FETCH_INST_OPCODE 2 %edx
- SET_VREG %ecx %eax
+ FETCH_INST_OPCODE 2 %eax
+ UNSPILL(rIBASE)
+ SET_VREG %ecx rINST
ADVANCE_PC 2
- GOTO_NEXT_R %edx
-
-/* continuation for OP_IPUT_VOLATILE */
+ GOTO_NEXT_R %eax
-.LOP_IPUT_VOLATILE_resolve:
+/* ------------------------------ */
+.L_OP_IPUT_VOLATILE: /* 0xe4 */
+/* File: x86/OP_IPUT_VOLATILE.S */
+/* File: x86/OP_IPUT.S */
+
+ /*
+ * General 32-bit instance field put.
+ *
+ * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short
+ */
+ /* op vA, vB, field@CCCC */
+ movl rSELF,%ecx
+ SPILL (rIBASE)
+ movzwl 2(rPC),rIBASE # rIBASE<- 0000CCCC
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IPUT_VOLATILE_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp)
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -11232,12 +7268,36 @@
movl offInstField_byteOffset(%eax),%eax # eax<- byte offset of field
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
- FETCH_INST_OPCODE 2 %edx
movl rINST,(%ecx,%eax,1) # obj.field <- v[A](8/16/32 bits)
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_SGET_VOLATILE */
+
+/* ------------------------------ */
+.L_OP_SGET_VOLATILE: /* 0xe5 */
+/* File: x86/OP_SGET_VOLATILE.S */
+/* File: x86/OP_SGET.S */
+ /*
+ * General 32-bit SGET handler.
+ *
+ * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
+ */
+ /* op vAA, field@BBBB */
+ movl rSELF,%ecx
+ movzwl 2(rPC),%eax # eax<- field ref BBBB
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SGET_VOLATILE_resolve # if not, make it so
+.LOP_SGET_VOLATILE_finish: # field ptr in eax
+ movl offStaticField_value(%eax),%eax
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ SET_VREG %eax rINST
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -11250,12 +7310,37 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SGET_VOLATILE_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_SPUT_VOLATILE */
+
+/* ------------------------------ */
+.L_OP_SPUT_VOLATILE: /* 0xe6 */
+/* File: x86/OP_SPUT_VOLATILE.S */
+/* File: x86/OP_SPUT.S */
+ /*
+ * General 32-bit SPUT handler.
+ *
+ * for: sput, sput-boolean, sput-byte, sput-char, sput-short
+ */
+ /* op vAA, field@BBBB */
+ movl rSELF,%ecx
+ movzwl 2(rPC),%eax # eax<- field ref BBBB
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SPUT_VOLATILE_resolve # if not, make it so
+.LOP_SPUT_VOLATILE_finish: # field ptr in eax
+ GET_VREG_R rINST rINST
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ movl rINST,offStaticField_value(%eax)
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -11268,20 +7353,43 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SPUT_VOLATILE_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_IGET_OBJECT_VOLATILE */
-
-.LOP_IGET_OBJECT_VOLATILE_resolve:
+/* ------------------------------ */
+.L_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */
+/* File: x86/OP_IGET_OBJECT_VOLATILE.S */
+/* File: x86/OP_IGET.S */
+ /*
+ * General 32-bit instance field get.
+ *
+ * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
+ */
+ /* op vA, vB, field@CCCC */
+ movl rSELF,%ecx
+ SPILL(rIBASE) # preserve rIBASE
+ movzwl 2(rPC),rIBASE # rIBASE<- 0000CCCC
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IGET_OBJECT_VOLATILE_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp) # needed by dvmResolveInstField
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -11299,13 +7407,110 @@
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
movl (%ecx,%eax,1),%ecx # ecx<- obj.field (8/16/32 bits)
- movl rINST,%eax # eax<- A
- FETCH_INST_OPCODE 2 %edx
- SET_VREG %ecx %eax
+ FETCH_INST_OPCODE 2 %eax
+ UNSPILL(rIBASE)
+ SET_VREG %ecx rINST
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %eax
-/* continuation for OP_EXECUTE_INLINE */
+
+/* ------------------------------ */
+.L_OP_IGET_WIDE_VOLATILE: /* 0xe8 */
+ /* (stub) */
+ SAVE_PC_FP_TO_SELF %ecx # leaves rSELF in %ecx
+ movl %ecx,OUT_ARG0(%esp) # self is first arg to function
+ call dvmMterp_OP_IGET_WIDE_VOLATILE # do the real work
+ movl rSELF,%ecx
+ LOAD_PC_FP_FROM_SELF # retrieve updated values
+ movl offThread_curHandlerTable(%ecx),rIBASE # set up rIBASE
+ FETCH_INST
+ GOTO_NEXT
+/* ------------------------------ */
+.L_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */
+ /* (stub) */
+ SAVE_PC_FP_TO_SELF %ecx # leaves rSELF in %ecx
+ movl %ecx,OUT_ARG0(%esp) # self is first arg to function
+ call dvmMterp_OP_IPUT_WIDE_VOLATILE # do the real work
+ movl rSELF,%ecx
+ LOAD_PC_FP_FROM_SELF # retrieve updated values
+ movl offThread_curHandlerTable(%ecx),rIBASE # set up rIBASE
+ FETCH_INST
+ GOTO_NEXT
+/* ------------------------------ */
+.L_OP_SGET_WIDE_VOLATILE: /* 0xea */
+ /* (stub) */
+ SAVE_PC_FP_TO_SELF %ecx # leaves rSELF in %ecx
+ movl %ecx,OUT_ARG0(%esp) # self is first arg to function
+ call dvmMterp_OP_SGET_WIDE_VOLATILE # do the real work
+ movl rSELF,%ecx
+ LOAD_PC_FP_FROM_SELF # retrieve updated values
+ movl offThread_curHandlerTable(%ecx),rIBASE # set up rIBASE
+ FETCH_INST
+ GOTO_NEXT
+/* ------------------------------ */
+.L_OP_SPUT_WIDE_VOLATILE: /* 0xeb */
+ /* (stub) */
+ SAVE_PC_FP_TO_SELF %ecx # leaves rSELF in %ecx
+ movl %ecx,OUT_ARG0(%esp) # self is first arg to function
+ call dvmMterp_OP_SPUT_WIDE_VOLATILE # do the real work
+ movl rSELF,%ecx
+ LOAD_PC_FP_FROM_SELF # retrieve updated values
+ movl offThread_curHandlerTable(%ecx),rIBASE # set up rIBASE
+ FETCH_INST
+ GOTO_NEXT
+/* ------------------------------ */
+.L_OP_BREAKPOINT: /* 0xec */
+/* File: x86/OP_BREAKPOINT.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_THROW_VERIFICATION_ERROR: /* 0xed */
+/* File: x86/OP_THROW_VERIFICATION_ERROR.S */
+ /*
+ * Handle a throw-verification-error instruction. This throws an
+ * exception for an error discovered during verification. The
+ * exception is indicated by AA, with some detail provided by BBBB.
+ */
+ /* op AA, ref@BBBB */
+ movl rSELF,%ecx
+ movzwl 2(rPC),%eax # eax<- BBBB
+ movl offThread_method(%ecx),%ecx # ecx<- self->method
+ EXPORT_PC
+ movl %eax,OUT_ARG2(%esp) # arg2<- BBBB
+ movl rINST,OUT_ARG1(%esp) # arg1<- AA
+ movl %ecx,OUT_ARG0(%esp) # arg0<- method
+ call dvmThrowVerificationError # call(method, kind, ref)
+ jmp common_exceptionThrown # handle exception
+
+/* ------------------------------ */
+.L_OP_EXECUTE_INLINE: /* 0xee */
+/* File: x86/OP_EXECUTE_INLINE.S */
+ /*
+ * Execute a "native inline" instruction.
+ *
+ * We will be calling through a function table:
+ *
+ * (*gDvmInlineOpsTable[opIndex].func)(arg0, arg1, arg2, arg3, pResult)
+ *
+ * Ignores argument count - always loads 4.
+ *
+ */
+ /* [opt] execute-inline vAA, {vC, vD, vE, vF}, inline@BBBB */
+ movl rSELF,%ecx
+ EXPORT_PC
+ movzwl 2(rPC),%eax # eax<- BBBB
+ leal offThread_retval(%ecx),%ecx # ecx<- & self->retval
+ SPILL(rIBASE) # preserve rIBASE
+ movl %ecx,OUT_ARG4(%esp)
+ call .LOP_EXECUTE_INLINE_continue # make call; will return after
+ UNSPILL(rIBASE) # restore rIBASE
+ testl %eax,%eax # successful?
+ FETCH_INST_OPCODE 3 %ecx
+ je common_exceptionThrown # no, handle exception
+ ADVANCE_PC 3
+ GOTO_NEXT_R %ecx
.LOP_EXECUTE_INLINE_continue:
/*
@@ -11317,58 +7522,327 @@
*
* Go ahead and load all 4 args, even if not used.
*/
- movzwl 4(rPC),%edx
+ movzwl 4(rPC),rIBASE
movl $0xf,%ecx
- andl %edx,%ecx
+ andl rIBASE,%ecx
GET_VREG_R %ecx %ecx
- sarl $4,%edx
+ sarl $4,rIBASE
movl %ecx,4+OUT_ARG0(%esp)
movl $0xf,%ecx
- andl %edx,%ecx
+ andl rIBASE,%ecx
GET_VREG_R %ecx %ecx
- sarl $4,%edx
+ sarl $4,rIBASE
movl %ecx,4+OUT_ARG1(%esp)
movl $0xf,%ecx
- andl %edx,%ecx
+ andl rIBASE,%ecx
GET_VREG_R %ecx %ecx
- sarl $4,%edx
+ sarl $4,rIBASE
movl %ecx,4+OUT_ARG2(%esp)
movl $0xf,%ecx
- andl %edx,%ecx
+ andl rIBASE,%ecx
GET_VREG_R %ecx %ecx
- sarl $4,%edx
+ sarl $4,rIBASE
movl %ecx,4+OUT_ARG3(%esp)
sall $4,%eax # index *= sizeof(table entry)
jmp *gDvmInlineOpsTable(%eax)
# will return to caller of .LOP_EXECUTE_INLINE_continue
-/* continuation for OP_IPUT_OBJECT_QUICK */
+/* ------------------------------ */
+.L_OP_EXECUTE_INLINE_RANGE: /* 0xef */
+ /* (stub) */
+ SAVE_PC_FP_TO_SELF %ecx # leaves rSELF in %ecx
+ movl %ecx,OUT_ARG0(%esp) # self is first arg to function
+ call dvmMterp_OP_EXECUTE_INLINE_RANGE # do the real work
+ movl rSELF,%ecx
+ LOAD_PC_FP_FROM_SELF # retrieve updated values
+ movl offThread_curHandlerTable(%ecx),rIBASE # set up rIBASE
+ FETCH_INST
+ GOTO_NEXT
+/* ------------------------------ */
+.L_OP_INVOKE_OBJECT_INIT: /* 0xf0 */
+ /* (stub) */
+ SAVE_PC_FP_TO_SELF %ecx # leaves rSELF in %ecx
+ movl %ecx,OUT_ARG0(%esp) # self is first arg to function
+ call dvmMterp_OP_INVOKE_OBJECT_INIT # do the real work
+ movl rSELF,%ecx
+ LOAD_PC_FP_FROM_SELF # retrieve updated values
+ movl offThread_curHandlerTable(%ecx),rIBASE # set up rIBASE
+ FETCH_INST
+ GOTO_NEXT
+/* ------------------------------ */
+.L_OP_RETURN_VOID_BARRIER: /* 0xf1 */
+ /* (stub) */
+ SAVE_PC_FP_TO_SELF %ecx # leaves rSELF in %ecx
+ movl %ecx,OUT_ARG0(%esp) # self is first arg to function
+ call dvmMterp_OP_RETURN_VOID_BARRIER # do the real work
+ movl rSELF,%ecx
+ LOAD_PC_FP_FROM_SELF # retrieve updated values
+ movl offThread_curHandlerTable(%ecx),rIBASE # set up rIBASE
+ FETCH_INST
+ GOTO_NEXT
+/* ------------------------------ */
+.L_OP_IGET_QUICK: /* 0xf2 */
+/* File: x86/OP_IGET_QUICK.S */
+ /* For: iget-quick, iget-object-quick */
+ /* op vA, vB, offset@CCCC */
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ GET_VREG_R %ecx %ecx # vB (object we're operating on)
+ movzwl 2(rPC),%eax # eax<- field byte offset
+ cmpl $0,%ecx # is object null?
+ je common_errNullObject
+ movl (%ecx,%eax,1),%eax
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ andb $0xf,rINSTbl # rINST<- A
+ SET_VREG %eax rINST # fp[A]<- result
+ GOTO_NEXT_R %ecx
-.LOP_IPUT_OBJECT_QUICK_finish:
+/* ------------------------------ */
+.L_OP_IGET_WIDE_QUICK: /* 0xf3 */
+/* File: x86/OP_IGET_WIDE_QUICK.S */
+ /* For: iget-wide-quick */
+ /* op vA, vB, offset@CCCC */
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ GET_VREG_R %ecx %ecx # vB (object we're operating on)
+ movzwl 2(rPC),%eax # eax<- field byte offset
+ cmpl $0,%ecx # is object null?
+ je common_errNullObject
+ leal (%ecx,%eax,1),%eax # eax<- address of 64-bit source
+ movl (%eax),%ecx # ecx<- lsw
+ movl 4(%eax),%eax # eax<- msw
+ andb $0xf,rINSTbl # rINST<- A
+ SET_VREG_WORD %ecx rINST 0 # v[A+0]<- lsw
+ FETCH_INST_OPCODE 2 %ecx
+ SET_VREG_WORD %eax rINST 1 # v[A+1]<- msw
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+/* ------------------------------ */
+.L_OP_IGET_OBJECT_QUICK: /* 0xf4 */
+/* File: x86/OP_IGET_OBJECT_QUICK.S */
+/* File: x86/OP_IGET_QUICK.S */
+ /* For: iget-quick, iget-object-quick */
+ /* op vA, vB, offset@CCCC */
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ GET_VREG_R %ecx %ecx # vB (object we're operating on)
+ movzwl 2(rPC),%eax # eax<- field byte offset
+ cmpl $0,%ecx # is object null?
+ je common_errNullObject
+ movl (%ecx,%eax,1),%eax
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ andb $0xf,rINSTbl # rINST<- A
+ SET_VREG %eax rINST # fp[A]<- result
+ GOTO_NEXT_R %ecx
+
+
+/* ------------------------------ */
+.L_OP_IPUT_QUICK: /* 0xf5 */
+/* File: x86/OP_IPUT_QUICK.S */
+ /* For: iput-quick */
+ /* op vA, vB, offset@CCCC */
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ GET_VREG_R %ecx %ecx # vB (object we're operating on)
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_R rINST,rINST # rINST<- v[A]
+ movzwl 2(rPC),%eax # eax<- field byte offset
+ testl %ecx,%ecx # is object null?
+ je common_errNullObject
+ movl rINST,(%ecx,%eax,1)
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+/* ------------------------------ */
+.L_OP_IPUT_WIDE_QUICK: /* 0xf6 */
+/* File: x86/OP_IPUT_WIDE_QUICK.S */
+ /* For: iput-wide-quick */
+ /* op vA, vB, offset@CCCC */
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ GET_VREG_R %ecx %ecx # vB (object we're operating on)
+ movzwl 2(rPC),%eax # eax<- field byte offset
+ testl %ecx,%ecx # is object null?
+ je common_errNullObject
+ leal (%ecx,%eax,1),%ecx # ecx<- Address of 64-bit target
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_WORD %eax rINST 0 # eax<- lsw
+ GET_VREG_WORD rINST rINST 1 # rINST<- msw
+ movl %eax,(%ecx)
+ movl rINST,4(%ecx)
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
+/* ------------------------------ */
+.L_OP_IPUT_OBJECT_QUICK: /* 0xf7 */
+/* File: x86/OP_IPUT_OBJECT_QUICK.S */
+ /* For: iput-object-quick */
+ /* op vA, vB, offset@CCCC */
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ GET_VREG_R %ecx %ecx # vB (object we're operating on)
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_R rINST rINST # rINST<- v[A]
+ movzwl 2(rPC),%eax # eax<- field byte offset
+ testl %ecx,%ecx # is object null?
+ je common_errNullObject
+ movl rINST,(%ecx,%eax,1)
+ movl rSELF,%eax
testl rINST,rINST # did we store null?
- FETCH_INST_OPCODE 2 %edx
movl offThread_cardTable(%eax),%eax # get card table base
je 1f # skip card mark if null store
shrl $GC_CARD_SHIFT,%ecx # object head to card number
movb %al,(%eax,%ecx) # mark card based on object head
1:
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_IPUT_OBJECT_VOLATILE */
+/* ------------------------------ */
+.L_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */
+/* File: x86/OP_INVOKE_VIRTUAL_QUICK.S */
+ /*
+ * Handle an optimized virtual method call.
+ *
+ * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range
+ */
+ /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
+ /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
+ movzwl 4(rPC),%eax # eax<- FEDC or CCCC
+ movzwl 2(rPC),%ecx # ecx<- BBBB
+ .if (!0)
+ andl $0xf,%eax # eax<- C (or stays CCCC)
+ .endif
+ GET_VREG_R %eax %eax # eax<- vC ("this" ptr)
+ testl %eax,%eax # null?
+ je common_errNullObject # yep, throw exception
+ movl offObject_clazz(%eax),%eax # eax<- thisPtr->clazz
+ movl offClassObject_vtable(%eax),%eax # eax<- thisPtr->clazz->vtable
+ EXPORT_PC # might throw later - get ready
+ movl (%eax,%ecx,4),%eax # eax<- vtable[BBBB]
+ jmp common_invokeMethodNoRange
+
+/* ------------------------------ */
+.L_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */
+/* File: x86/OP_INVOKE_VIRTUAL_QUICK_RANGE.S */
+/* File: x86/OP_INVOKE_VIRTUAL_QUICK.S */
+ /*
+ * Handle an optimized virtual method call.
+ *
+ * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range
+ */
+ /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
+ /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
+ movzwl 4(rPC),%eax # eax<- FEDC or CCCC
+ movzwl 2(rPC),%ecx # ecx<- BBBB
+ .if (!1)
+ andl $0xf,%eax # eax<- C (or stays CCCC)
+ .endif
+ GET_VREG_R %eax %eax # eax<- vC ("this" ptr)
+ testl %eax,%eax # null?
+ je common_errNullObject # yep, throw exception
+ movl offObject_clazz(%eax),%eax # eax<- thisPtr->clazz
+ movl offClassObject_vtable(%eax),%eax # eax<- thisPtr->clazz->vtable
+ EXPORT_PC # might throw later - get ready
+ movl (%eax,%ecx,4),%eax # eax<- vtable[BBBB]
+ jmp common_invokeMethodRange
-.LOP_IPUT_OBJECT_VOLATILE_resolve:
+/* ------------------------------ */
+.L_OP_INVOKE_SUPER_QUICK: /* 0xfa */
+/* File: x86/OP_INVOKE_SUPER_QUICK.S */
+ /*
+ * Handle an optimized "super" method call.
+ *
+ * for: [opt] invoke-super-quick, invoke-super-quick/range
+ */
+ /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
+ /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
+ movl rSELF,%ecx
+ movzwl 4(rPC),%eax # eax<- GFED or CCCC
+ movl offThread_method(%ecx),%ecx # ecx<- current method
+ .if (!0)
+ andl $0xf,%eax # eax<- D (or stays CCCC)
+ .endif
+ movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
+ GET_VREG_R %eax %eax # eax<- "this"
+ movl offClassObject_super(%ecx),%ecx # ecx<- method->clazz->super
+ testl %eax,%eax # null "this"?
+ je common_errNullObject # "this" is null, throw exception
+ movzwl 2(rPC),%eax # eax<- BBBB
+ movl offClassObject_vtable(%ecx),%ecx # ecx<- vtable
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl (%ecx,%eax,4),%eax # eax<- super->vtable[BBBB]
+ jmp common_invokeMethodNoRange
+
+/* ------------------------------ */
+.L_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */
+/* File: x86/OP_INVOKE_SUPER_QUICK_RANGE.S */
+/* File: x86/OP_INVOKE_SUPER_QUICK.S */
+ /*
+ * Handle an optimized "super" method call.
+ *
+ * for: [opt] invoke-super-quick, invoke-super-quick/range
+ */
+ /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
+ /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
+ movl rSELF,%ecx
+ movzwl 4(rPC),%eax # eax<- GFED or CCCC
+ movl offThread_method(%ecx),%ecx # ecx<- current method
+ .if (!1)
+ andl $0xf,%eax # eax<- D (or stays CCCC)
+ .endif
+ movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
+ GET_VREG_R %eax %eax # eax<- "this"
+ movl offClassObject_super(%ecx),%ecx # ecx<- method->clazz->super
+ testl %eax,%eax # null "this"?
+ je common_errNullObject # "this" is null, throw exception
+ movzwl 2(rPC),%eax # eax<- BBBB
+ movl offClassObject_vtable(%ecx),%ecx # ecx<- vtable
+ EXPORT_PC
+ movl (%ecx,%eax,4),%eax # eax<- super->vtable[BBBB]
+ jmp common_invokeMethodRange
+
+
+/* ------------------------------ */
+.L_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */
+/* File: x86/OP_IPUT_OBJECT_VOLATILE.S */
+/* File: x86/OP_IPUT_OBJECT.S */
+ /*
+ * Object field put.
+ *
+ * for: iput-object
+ */
+ /* op vA, vB, field@CCCC */
+ movl rSELF,%ecx
+ SPILL(rIBASE)
+ movzwl 2(rPC),rIBASE # rIBASE<- 0000CCCC
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzbl rINSTbl,%ecx # ecx<- BA
+ sarl $4,%ecx # ecx<- B
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ andb $0xf,rINSTbl # rINST<- A
+ GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IPUT_OBJECT_VOLATILE_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp)
+ movl rSELF,rIBASE
+ EXPORT_PC
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -11380,7 +7854,7 @@
* Currently:
* eax holds resolved field
* ecx holds object
- * %edx is scratch, but needs to be unspilled
+ * rIBASE is scratch, but needs to be unspilled
* rINST holds A
*/
GET_VREG_R rINST rINST # rINST<- v[A]
@@ -11390,16 +7864,40 @@
movl rINST,(%ecx,%eax) # obj.field <- v[A](8/16/32 bits)
movl rSELF,%eax
testl rINST,rINST # stored a NULL?
- movl offThread_cardTable(%eax),%eax # get card table base
- FETCH_INST_OPCODE 2 %edx
+ movl offThread_cardTable(%eax),%eax # get card table base
je 1f # skip card mark if null store
shrl $GC_CARD_SHIFT,%ecx # object head to card number
movb %al,(%eax,%ecx) # mark card using object head
1:
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_SGET_OBJECT_VOLATILE */
+
+/* ------------------------------ */
+.L_OP_SGET_OBJECT_VOLATILE: /* 0xfd */
+/* File: x86/OP_SGET_OBJECT_VOLATILE.S */
+/* File: x86/OP_SGET.S */
+ /*
+ * General 32-bit SGET handler.
+ *
+ * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
+ */
+ /* op vAA, field@BBBB */
+ movl rSELF,%ecx
+ movzwl 2(rPC),%eax # eax<- field ref BBBB
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SGET_OBJECT_VOLATILE_resolve # if not, make it so
+.LOP_SGET_OBJECT_VOLATILE_finish: # field ptr in eax
+ movl offStaticField_value(%eax),%eax
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ SET_VREG %eax rINST
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -11412,18 +7910,34 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SGET_OBJECT_VOLATILE_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_SPUT_OBJECT_VOLATILE */
-
-.LOP_SPUT_OBJECT_VOLATILE_continue:
+/* ------------------------------ */
+.L_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */
+/* File: x86/OP_SPUT_OBJECT_VOLATILE.S */
+/* File: x86/OP_SPUT_OBJECT.S */
+ /*
+ * SPUT object handler.
+ */
+ /* op vAA, field@BBBB */
+ movl rSELF,%ecx
+ movzwl 2(rPC),%eax # eax<- field ref BBBB
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SPUT_OBJECT_VOLATILE_resolve # if not, make it so
+.LOP_SPUT_OBJECT_VOLATILE_finish: # field ptr in eax
+ movzbl rINSTbl,%ecx # ecx<- AA
+ GET_VREG_R %ecx %ecx
movl %ecx,offStaticField_value(%eax) # do the store
testl %ecx,%ecx # stored null object ptr?
- FETCH_INST_OPCODE 2 %edx
je 1f # skip card mark if null
movl rSELF,%ecx
movl offField_clazz(%eax),%eax # eax<- method->clazz
@@ -11431,8 +7945,9 @@
shrl $GC_CARD_SHIFT,%eax # head to card number
movb %cl,(%ecx,%eax) # mark card
1:
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
.LOP_SPUT_OBJECT_VOLATILE_resolve:
movl rSELF,%ecx
@@ -11442,12 +7957,35 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SPUT_OBJECT_VOLATILE_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_CONST_CLASS_JUMBO */
+
+/* ------------------------------ */
+.L_OP_DISPATCH_FF: /* 0xff */
+/* File: x86/OP_DISPATCH_FF.S */
+ leal 256(rINST),%ecx
+ GOTO_NEXT_JUMBO_R %ecx
+
+/* ------------------------------ */
+.L_OP_CONST_CLASS_JUMBO: /* 0x100 */
+/* File: x86/OP_CONST_CLASS_JUMBO.S */
+ /* const-class/jumbo vBBBB, Class@AAAAAAAA */
+ movl rSELF,%ecx
+ movl 2(rPC),%eax # eax<- AAAAAAAA
+ movl offThread_methodClassDex(%ecx),%ecx# ecx<- self->methodClassDex
+ movl offDvmDex_pResClasses(%ecx),%ecx # ecx<- dvmDex->pResClasses
+ FETCH_INST_OPCODE 4 %ecx
+ movl (%ecx,%eax,4),%eax # eax<- rResClasses[AAAAAAAA]
+ testl %eax,%eax # resolved yet?
+ je .LOP_CONST_CLASS_JUMBO_resolve
+ SET_VREG %eax rINST # vBBBB<- rResClasses[AAAAAAAA]
+ ADVANCE_PC 4
+ GOTO_NEXT_R %ecx
/* This is the less common path, so we'll redo some work
here rather than force spills on the common path */
@@ -11460,15 +7998,41 @@
movl offMethod_clazz(%eax),%eax
movl %ecx,OUT_ARG1(%esp)
movl %eax,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveClass # go resolve
+ UNSPILL(rIBASE)
testl %eax,%eax # failed?
je common_exceptionThrown
+ FETCH_INST_OPCODE 4 %ecx
SET_VREG %eax rINST
- FETCH_INST_OPCODE 4 %edx
ADVANCE_PC 4
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_CHECK_CAST_JUMBO */
+/* ------------------------------ */
+.L_OP_CHECK_CAST_JUMBO: /* 0x101 */
+/* File: x86/OP_CHECK_CAST_JUMBO.S */
+ /*
+ * Check to see if a cast from one class to another is allowed.
+ */
+ /* check-cast/jumbo vBBBB, class@AAAAAAAA */
+ movl rSELF,%ecx
+ GET_VREG_R rINST,rINST # rINST<- vBBBB (object)
+ movl 2(rPC),%eax # eax<- AAAAAAAA
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
+ testl rINST,rINST # is oject null?
+ movl offDvmDex_pResClasses(%ecx),%ecx # ecx<- pDvmDex->pResClasses
+ je .LOP_CHECK_CAST_JUMBO_okay # null obj, cast always succeeds
+ movl (%ecx,%eax,4),%eax # eax<- resolved class
+ movl offObject_clazz(rINST),%ecx # ecx<- obj->clazz
+ testl %eax,%eax # have we resolved this before?
+ je .LOP_CHECK_CAST_JUMBO_resolve # no, go do it now
+.LOP_CHECK_CAST_JUMBO_resolved:
+ cmpl %eax,%ecx # same class (trivial success)?
+ jne .LOP_CHECK_CAST_JUMBO_fullcheck # no, do full check
+.LOP_CHECK_CAST_JUMBO_okay:
+ FETCH_INST_OPCODE 4 %ecx
+ ADVANCE_PC 4
+ GOTO_NEXT_R %ecx
/*
* Trivial test failed, need to perform full check. This is common.
@@ -11480,7 +8044,9 @@
movl %eax,sReg0 # we'll need the desired class on failure
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmInstanceofNonTrivial # eax<- boolean result
+ UNSPILL(rIBASE)
testl %eax,%eax # failed?
jne .LOP_CHECK_CAST_JUMBO_okay # no, success
@@ -11508,21 +8074,46 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- metho->clazz
movl $0,OUT_ARG2(%esp) # arg2<- false
movl %ecx,OUT_ARG0(%esp) # arg0<- method->clazz
+ SPILL(rIBASE)
call dvmResolveClass # eax<- resolved ClassObject ptr
+ UNSPILL(rIBASE)
testl %eax,%eax # got null?
je common_exceptionThrown # yes, handle exception
movl offObject_clazz(rINST),%ecx # ecx<- obj->clazz
jmp .LOP_CHECK_CAST_JUMBO_resolved # pick up where we left off
-/* continuation for OP_INSTANCE_OF_JUMBO */
-
+/* ------------------------------ */
+.L_OP_INSTANCE_OF_JUMBO: /* 0x102 */
+/* File: x86/OP_INSTANCE_OF_JUMBO.S */
+ /*
+ * Check to see if an object reference is an instance of a class.
+ *
+ * Most common situation is a non-null object, being compared against
+ * an already-resolved class.
+ */
+ /* instance-of/jumbo vBBBB, vCCCC, class@AAAAAAAA */
+ movzwl 8(rPC),%eax # eax<- CCCC
+ GET_VREG_R %eax %eax # eax<- vCCCC (obj)
+ movl rSELF,%ecx
+ testl %eax,%eax # object null?
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
+ SPILL(rIBASE) # preserve rIBASE
+ je .LOP_INSTANCE_OF_JUMBO_store # null obj, not instance, store it
+ movl 2(rPC),rIBASE # edx<- AAAAAAAA
+ movl offDvmDex_pResClasses(%ecx),%ecx # ecx<- pDvmDex->pResClasses
+ movl (%ecx,rIBASE,4),%ecx # ecx<- resolved class
+ movl offObject_clazz(%eax),%eax # eax<- obj->clazz
+ testl %ecx,%ecx # have we resolved this before?
+ je .LOP_INSTANCE_OF_JUMBO_resolve # not resolved, do it now
+.LOP_INSTANCE_OF_JUMBO_resolved: # eax<- obj->clazz, ecx<- resolved class
+ cmpl %eax,%ecx # same class (trivial success)?
+ je .LOP_INSTANCE_OF_JUMBO_trivial # yes, trivial finish
/*
* Trivial test failed, need to perform full check. This is common.
* eax holds obj->clazz
* ecx holds class resolved from BBBB
* rINST has BA
*/
-.LOP_INSTANCE_OF_JUMBO_fullcheck:
movl %eax,OUT_ARG0(%esp)
movl %ecx,OUT_ARG1(%esp)
call dvmInstanceofNonTrivial # eax<- boolean result
@@ -11533,21 +8124,23 @@
* rINST holds BBBB
*/
.LOP_INSTANCE_OF_JUMBO_store:
- FETCH_INST_OPCODE 5 %edx
+ FETCH_INST_OPCODE 5 %ecx
+ UNSPILL(rIBASE)
ADVANCE_PC 5
SET_VREG %eax rINST # vBBBB<- eax
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
/*
* Trivial test succeeded, save and bail.
* r9 holds BBBB
*/
.LOP_INSTANCE_OF_JUMBO_trivial:
- FETCH_INST_OPCODE 5 %edx
+ FETCH_INST_OPCODE 5 %ecx
+ UNSPILL(rIBASE)
ADVANCE_PC 5
movl $1,%eax
SET_VREG %eax rINST # vBBBB<- true
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
/*
* Resolution required. This is the least-likely path.
@@ -11555,7 +8148,7 @@
* edx holds AAAAAAAA
*/
.LOP_INSTANCE_OF_JUMBO_resolve:
- movl %edx,OUT_ARG1(%esp) # arg1<- AAAAAAAA
+ movl rIBASE,OUT_ARG1(%esp) # arg1<- AAAAAAAA
movl rSELF,%ecx
movl offThread_method(%ecx),%ecx
movl $1,OUT_ARG2(%esp) # arg2<- true
@@ -11574,8 +8167,25 @@
movl offObject_clazz(%eax),%eax # eax<- obj->clazz
jmp .LOP_INSTANCE_OF_JUMBO_resolved
-/* continuation for OP_NEW_INSTANCE_JUMBO */
-
+/* ------------------------------ */
+.L_OP_NEW_INSTANCE_JUMBO: /* 0x103 */
+/* File: x86/OP_NEW_INSTANCE_JUMBO.S */
+ /*
+ * Create a new instance of a class.
+ */
+ /* new-instance/jumbo vBBBB, class@AAAAAAAA */
+ movl rSELF,%ecx
+ movl 2(rPC),%eax # eax<- AAAAAAAA
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
+ movl offDvmDex_pResClasses(%ecx),%ecx # ecx<- pDvmDex->pResClasses
+ EXPORT_PC
+ movl (%ecx,%eax,4),%ecx # ecx<- resolved class
+ SPILL(rIBASE)
+ testl %ecx,%ecx # resolved?
+ je .LOP_NEW_INSTANCE_JUMBO_resolve # no, go do it
+.LOP_NEW_INSTANCE_JUMBO_resolved: # on entry, ecx<- class
+ cmpb $CLASS_INITIALIZED,offClassObject_status(%ecx)
+ jne .LOP_NEW_INSTANCE_JUMBO_needinit
.LOP_NEW_INSTANCE_JUMBO_initialized: # on entry, ecx<- class
/* TODO: remove test for interface/abstract, now done in verifier */
testl $(ACC_INTERFACE|ACC_ABSTRACT),offClassObject_accessFlags(%ecx)
@@ -11584,12 +8194,13 @@
.LOP_NEW_INSTANCE_JUMBO_finish: # ecx=class
movl %ecx,OUT_ARG0(%esp)
call dvmAllocObject # eax<- new object
- FETCH_INST_OPCODE 4 %edx
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 4 %ecx
testl %eax,%eax # success?
je common_exceptionThrown # no, bail out
SET_VREG %eax rINST
ADVANCE_PC 4
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
/*
* Class initialization required.
@@ -11637,14 +8248,35 @@
call dvmThrowExceptionWithClassMessage
jmp common_exceptionThrown
-/* continuation for OP_NEW_ARRAY_JUMBO */
-
+/* ------------------------------ */
+.L_OP_NEW_ARRAY_JUMBO: /* 0x104 */
+/* File: x86/OP_NEW_ARRAY_JUMBO.S */
+ /*
+ * Allocate an array of objects, specified with the array class
+ * and a count.
+ *
+ * The verifier guarantees that this is an array class, so we don't
+ * check for it here.
+ */
+ /* new-array/jumbo vBBBB, vCCCC, class@AAAAAAAA */
+ movl rSELF,%ecx
+ EXPORT_PC
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
+ movl 2(rPC),%eax # eax<- AAAAAAAA
+ movl offDvmDex_pResClasses(%ecx),%ecx # ecx<- pDvmDex->pResClasses
+ SPILL(rIBASE)
+ movl (%ecx,%eax,4),%ecx # ecx<- resolved class
+ movzwl 8(rPC),%eax # eax<- CCCC
+ GET_VREG_R %eax %eax # eax<- vCCCC (array length)
+ testl %eax,%eax
+ js common_errNegativeArraySize # bail, passing len in eax
+ testl %ecx,%ecx # already resolved?
+ jne .LOP_NEW_ARRAY_JUMBO_finish # yes, fast path
/*
* Resolve class. (This is an uncommon case.)
* ecx holds class (null here)
* eax holds array length (vCCCC)
*/
-.LOP_NEW_ARRAY_JUMBO_resolve:
movl rSELF,%ecx
SPILL_TMP1(%eax) # save array length
movl offThread_method(%ecx),%ecx # ecx<- self->method
@@ -11671,19 +8303,39 @@
movl %eax,OUT_ARG1(%esp)
movl $ALLOC_DONT_TRACK,OUT_ARG2(%esp)
call dvmAllocArrayByClass # eax<- call(clazz,length,flags)
- FETCH_INST_OPCODE 5 %edx
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 5 %ecx
testl %eax,%eax # failed?
je common_exceptionThrown # yup - go handle
SET_VREG %eax rINST
ADVANCE_PC 5
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_FILLED_NEW_ARRAY_JUMBO */
-
-.LOP_FILLED_NEW_ARRAY_JUMBO_more:
+/* ------------------------------ */
+.L_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */
+/* File: x86/OP_FILLED_NEW_ARRAY_JUMBO.S */
+ /*
+ * Create a new array with elements filled from registers.
+ */
+ /* filled-new-array/jumbo {vCCCC..v(CCCC+BBBB-1)}, type@AAAAAAAA */
+ movl rSELF,%eax
+ movl offThread_methodClassDex(%eax),%eax # eax<- pDvmDex
+ movl 2(rPC),%ecx # ecx<- AAAAAAAA
+ movl offDvmDex_pResClasses(%eax),%eax # eax<- pDvmDex->pResClasses
+ movl (%eax,%ecx,4),%eax # eax<- resolved class
+ EXPORT_PC
+ testl %eax,%eax # already resolved?
+ jne .LOP_FILLED_NEW_ARRAY_JUMBO_continue # yes, continue
+ # less frequent path, so we'll redo some work
+ movl rSELF,%eax
+ movl $0,OUT_ARG2(%esp) # arg2<- false
+ movl %ecx,OUT_ARG1(%esp) # arg1<- AAAAAAAA
+ movl offThread_method(%eax),%eax # eax<- self->method
movl offMethod_clazz(%eax),%eax # eax<- method->clazz
movl %eax,OUT_ARG0(%esp) # arg0<- clazz
+ SPILL(rIBASE)
call dvmResolveClass # eax<- call(clazz,ref,flag)
+ UNSPILL(rIBASE)
testl %eax,%eax # null?
je common_exceptionThrown # yes, handle it
@@ -11709,7 +8361,9 @@
1:
movl %ecx,offThread_retval+4(%eax) # save type
movl rINST,OUT_ARG1(%esp) # arg1<- BBBB (length)
+ SPILL(rIBASE)
call dvmAllocArrayByClass # eax<- call(arrayClass, length, flags)
+ UNSPILL(rIBASE)
movl rSELF,%ecx
testl %eax,%eax # alloc successful?
je common_exceptionThrown # no, handle exception
@@ -11736,7 +8390,6 @@
UNSPILL_TMP3(%edi)
movl rSELF,%ecx
movl offThread_retval+4(%ecx),%eax # eax<- type
- FETCH_INST_OPCODE 5 %edx
cmpb $'I',%al # Int array?
je 5f # skip card mark if so
@@ -11745,8 +8398,9 @@
shrl $GC_CARD_SHIFT,%eax # convert to card num
movb %cl,(%ecx,%eax) # mark card based on object head
5:
+ FETCH_INST_OPCODE 5 %ecx
ADVANCE_PC 5
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
/*
@@ -11761,15 +8415,33 @@
call dvmThrowException
jmp common_exceptionThrown
-/* continuation for OP_IGET_JUMBO */
-
-
-.LOP_IGET_JUMBO_resolve:
+/* ------------------------------ */
+.L_OP_IGET_JUMBO: /* 0x106 */
+/* File: x86/OP_IGET_JUMBO.S */
+ /*
+ * Jumbo 32-bit instance field get.
+ *
+ * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
+ * iget-char/jumbo, iget-short/jumbo
+ */
+ /* exop vBBBB, vCCCC, field@AAAAAAAA */
+ movl rSELF,%ecx
+ SPILL(rIBASE) # preserve rIBASE
+ movl 2(rPC),rIBASE # rIBASE<- AAAAAAAA
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzwl 8(rPC),%ecx # ecx<- CCCC
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IGET_JUMBO_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp) # needed by dvmResolveInstField
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -11787,19 +8459,34 @@
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
movl (%ecx,%eax,1),%ecx # ecx<- obj.field (8/16/32 bits)
- movl rINST,%eax # eax<- BBBB
- FETCH_INST_OPCODE 5 %edx
- SET_VREG %ecx %eax
+ FETCH_INST_OPCODE 5 %eax
+ UNSPILL(rIBASE) # restore rIBASE
+ SET_VREG %ecx rINST
ADVANCE_PC 5
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %eax
-/* continuation for OP_IGET_WIDE_JUMBO */
-
-
-.LOP_IGET_WIDE_JUMBO_resolve:
+/* ------------------------------ */
+.L_OP_IGET_WIDE_JUMBO: /* 0x107 */
+/* File: x86/OP_IGET_WIDE_JUMBO.S */
+ /*
+ * Jumbo 64-bit instance field get.
+ */
+ /* iget-wide/jumbo vBBBB, vCCCC, field@AAAA */
+ movl rSELF,%ecx
+ SPILL(rIBASE) # preserve rIBASE
+ movl 2(rPC),rIBASE # rIBASE<- AAAAAAAA
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzwl 8(rPC),%ecx # ecx<- CCCC
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IGET_WIDE_JUMBO_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp) # for dvmResolveInstField
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save objpointer across call
movl rPC,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
@@ -11821,21 +8508,41 @@
leal (%ecx,%eax,1),%eax # eax<- address of field
movl (%eax),%ecx # ecx<- lsw
movl 4(%eax),%eax # eax<- msw
- FETCH_INST_OPCODE 5 %edx
SET_VREG_WORD %ecx rINST 0
+ FETCH_INST_OPCODE 5 %ecx
+ UNSPILL(rIBASE) # restore rIBASE
SET_VREG_WORD %eax rINST 1
ADVANCE_PC 5
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_IGET_OBJECT_JUMBO */
-
-
-.LOP_IGET_OBJECT_JUMBO_resolve:
+/* ------------------------------ */
+.L_OP_IGET_OBJECT_JUMBO: /* 0x108 */
+/* File: x86/OP_IGET_OBJECT_JUMBO.S */
+/* File: x86/OP_IGET_JUMBO.S */
+ /*
+ * Jumbo 32-bit instance field get.
+ *
+ * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
+ * iget-char/jumbo, iget-short/jumbo
+ */
+ /* exop vBBBB, vCCCC, field@AAAAAAAA */
+ movl rSELF,%ecx
+ SPILL(rIBASE) # preserve rIBASE
+ movl 2(rPC),rIBASE # rIBASE<- AAAAAAAA
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzwl 8(rPC),%ecx # ecx<- CCCC
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IGET_OBJECT_JUMBO_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp) # needed by dvmResolveInstField
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -11853,21 +8560,41 @@
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
movl (%ecx,%eax,1),%ecx # ecx<- obj.field (8/16/32 bits)
- movl rINST,%eax # eax<- BBBB
- FETCH_INST_OPCODE 5 %edx
- SET_VREG %ecx %eax
+ FETCH_INST_OPCODE 5 %eax
+ UNSPILL(rIBASE) # restore rIBASE
+ SET_VREG %ecx rINST
ADVANCE_PC 5
- GOTO_NEXT_R %edx
-
-/* continuation for OP_IGET_BOOLEAN_JUMBO */
+ GOTO_NEXT_R %eax
-.LOP_IGET_BOOLEAN_JUMBO_resolve:
+/* ------------------------------ */
+.L_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */
+/* File: x86/OP_IGET_BOOLEAN_JUMBO.S */
+/* File: x86/OP_IGET_JUMBO.S */
+ /*
+ * Jumbo 32-bit instance field get.
+ *
+ * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
+ * iget-char/jumbo, iget-short/jumbo
+ */
+ /* exop vBBBB, vCCCC, field@AAAAAAAA */
+ movl rSELF,%ecx
+ SPILL(rIBASE) # preserve rIBASE
+ movl 2(rPC),rIBASE # rIBASE<- AAAAAAAA
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzwl 8(rPC),%ecx # ecx<- CCCC
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IGET_BOOLEAN_JUMBO_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp) # needed by dvmResolveInstField
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -11885,21 +8612,41 @@
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
movzbl (%ecx,%eax,1),%ecx # ecx<- obj.field (8/16/32 bits)
- movl rINST,%eax # eax<- BBBB
- FETCH_INST_OPCODE 5 %edx
- SET_VREG %ecx %eax
+ FETCH_INST_OPCODE 5 %eax
+ UNSPILL(rIBASE) # restore rIBASE
+ SET_VREG %ecx rINST
ADVANCE_PC 5
- GOTO_NEXT_R %edx
-
-/* continuation for OP_IGET_BYTE_JUMBO */
+ GOTO_NEXT_R %eax
-.LOP_IGET_BYTE_JUMBO_resolve:
+/* ------------------------------ */
+.L_OP_IGET_BYTE_JUMBO: /* 0x10a */
+/* File: x86/OP_IGET_BYTE_JUMBO.S */
+/* File: x86/OP_IGET_JUMBO.S */
+ /*
+ * Jumbo 32-bit instance field get.
+ *
+ * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
+ * iget-char/jumbo, iget-short/jumbo
+ */
+ /* exop vBBBB, vCCCC, field@AAAAAAAA */
+ movl rSELF,%ecx
+ SPILL(rIBASE) # preserve rIBASE
+ movl 2(rPC),rIBASE # rIBASE<- AAAAAAAA
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzwl 8(rPC),%ecx # ecx<- CCCC
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IGET_BYTE_JUMBO_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp) # needed by dvmResolveInstField
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -11917,21 +8664,41 @@
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
movsbl (%ecx,%eax,1),%ecx # ecx<- obj.field (8/16/32 bits)
- movl rINST,%eax # eax<- BBBB
- FETCH_INST_OPCODE 5 %edx
- SET_VREG %ecx %eax
+ FETCH_INST_OPCODE 5 %eax
+ UNSPILL(rIBASE) # restore rIBASE
+ SET_VREG %ecx rINST
ADVANCE_PC 5
- GOTO_NEXT_R %edx
-
-/* continuation for OP_IGET_CHAR_JUMBO */
+ GOTO_NEXT_R %eax
-.LOP_IGET_CHAR_JUMBO_resolve:
+/* ------------------------------ */
+.L_OP_IGET_CHAR_JUMBO: /* 0x10b */
+/* File: x86/OP_IGET_CHAR_JUMBO.S */
+/* File: x86/OP_IGET_JUMBO.S */
+ /*
+ * Jumbo 32-bit instance field get.
+ *
+ * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
+ * iget-char/jumbo, iget-short/jumbo
+ */
+ /* exop vBBBB, vCCCC, field@AAAAAAAA */
+ movl rSELF,%ecx
+ SPILL(rIBASE) # preserve rIBASE
+ movl 2(rPC),rIBASE # rIBASE<- AAAAAAAA
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzwl 8(rPC),%ecx # ecx<- CCCC
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IGET_CHAR_JUMBO_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp) # needed by dvmResolveInstField
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -11949,21 +8716,41 @@
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
movzwl (%ecx,%eax,1),%ecx # ecx<- obj.field (8/16/32 bits)
- movl rINST,%eax # eax<- BBBB
- FETCH_INST_OPCODE 5 %edx
- SET_VREG %ecx %eax
+ FETCH_INST_OPCODE 5 %eax
+ UNSPILL(rIBASE) # restore rIBASE
+ SET_VREG %ecx rINST
ADVANCE_PC 5
- GOTO_NEXT_R %edx
-
-/* continuation for OP_IGET_SHORT_JUMBO */
+ GOTO_NEXT_R %eax
-.LOP_IGET_SHORT_JUMBO_resolve:
+/* ------------------------------ */
+.L_OP_IGET_SHORT_JUMBO: /* 0x10c */
+/* File: x86/OP_IGET_SHORT_JUMBO.S */
+/* File: x86/OP_IGET_JUMBO.S */
+ /*
+ * Jumbo 32-bit instance field get.
+ *
+ * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
+ * iget-char/jumbo, iget-short/jumbo
+ */
+ /* exop vBBBB, vCCCC, field@AAAAAAAA */
+ movl rSELF,%ecx
+ SPILL(rIBASE) # preserve rIBASE
+ movl 2(rPC),rIBASE # rIBASE<- AAAAAAAA
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzwl 8(rPC),%ecx # ecx<- CCCC
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IGET_SHORT_JUMBO_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp) # needed by dvmResolveInstField
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -11981,21 +8768,40 @@
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
movswl (%ecx,%eax,1),%ecx # ecx<- obj.field (8/16/32 bits)
- movl rINST,%eax # eax<- BBBB
- FETCH_INST_OPCODE 5 %edx
- SET_VREG %ecx %eax
+ FETCH_INST_OPCODE 5 %eax
+ UNSPILL(rIBASE) # restore rIBASE
+ SET_VREG %ecx rINST
ADVANCE_PC 5
- GOTO_NEXT_R %edx
-
-/* continuation for OP_IPUT_JUMBO */
+ GOTO_NEXT_R %eax
-.LOP_IPUT_JUMBO_resolve:
+/* ------------------------------ */
+.L_OP_IPUT_JUMBO: /* 0x10d */
+/* File: x86/OP_IPUT_JUMBO.S */
+ /*
+ * Jumbo 32-bit instance field put.
+ *
+ * for: iput/jumbo, iput-object/jumbo, iput-boolean/jumbo, iput-byte/jumbo,
+ iput-char/jumbo, iput-short/jumbo
+ */
+ /* exop vBBBB, vCCCC, field@AAAAAAAA */
+ movl rSELF,%ecx
+ SPILL(rIBASE)
+ movl 2(rPC),rIBASE # rIBASE<- AAAAAAAA
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzwl 8(rPC),%ecx # ecx<- CCCC
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IPUT_JUMBO_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp)
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -12013,20 +8819,36 @@
movl offInstField_byteOffset(%eax),%eax # eax<- byte offset of field
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
- FETCH_INST_OPCODE 5 %edx
movl rINST,(%ecx,%eax,1) # obj.field <- v[BBBB](8/16/32 bits)
+ FETCH_INST_OPCODE 5 %ecx
+ UNSPILL(rIBASE)
ADVANCE_PC 5
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_IPUT_WIDE_JUMBO */
-
-
-.LOP_IPUT_WIDE_JUMBO_resolve:
+/* ------------------------------ */
+.L_OP_IPUT_WIDE_JUMBO: /* 0x10e */
+/* File: x86/OP_IPUT_WIDE_JUMBO.S */
+ /*
+ * Jumbo 64-bit instance field put.
+ */
+ /* iput-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */
+ movl rSELF,%ecx
+ SPILL(rIBASE)
+ movl 2(rPC),rIBASE # rIBASE<- AAAAAAAA
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzwl 8(rPC),%ecx # ecx<- CCCC
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IPUT_WIDE_JUMBO_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp)
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # ... which returns InstrField ptr
@@ -12038,7 +8860,7 @@
* Currently:
* eax holds resolved field
* ecx holds object
- * %edx is scratch, but needs to be unspilled
+ * rIBASE is scratch, but needs to be unspilled
* rINST holds BBBB
*/
movl offInstField_byteOffset(%eax),%eax # eax<- byte offset of field
@@ -12047,21 +8869,37 @@
leal (%ecx,%eax,1),%eax # eax<- address of field
GET_VREG_WORD %ecx rINST 0 # ecx<- lsw
GET_VREG_WORD rINST rINST 1 # rINST<- msw
- FETCH_INST_OPCODE 5 %edx
movl rINST,4(%eax)
movl %ecx,(%eax)
+ FETCH_INST_OPCODE 5 %ecx
+ UNSPILL(rIBASE)
ADVANCE_PC 5
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_IPUT_OBJECT_JUMBO */
-
-
-.LOP_IPUT_OBJECT_JUMBO_resolve:
+/* ------------------------------ */
+.L_OP_IPUT_OBJECT_JUMBO: /* 0x10f */
+/* File: x86/OP_IPUT_OBJECT_JUMBO.S */
+ /*
+ * Jumbo object field put.
+ */
+ /* iput-object/jumbo vBBBB, vCCCC, field@AAAAAAAA */
+ movl rSELF,%ecx
+ SPILL(rIBASE)
+ movl 2(rPC),rIBASE # rIBASE<- AAAAAAAA
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzwl 8(rPC),%ecx # ecx<- CCCC
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IPUT_OBJECT_JUMBO_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp)
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -12073,7 +8911,7 @@
* Currently:
* eax holds resolved field
* ecx holds object
- * %edx is scratch, but needs to be unspilled
+ * rIBASE is scratch, but needs to be unspilled
* rINST holds BBBB
*/
GET_VREG_R rINST rINST # rINST<- v[BBBB]
@@ -12083,24 +8921,44 @@
movl rINST,(%ecx,%eax) # obj.field <- v[BBBB](8/16/32 bits)
movl rSELF,%eax
testl rINST,rINST # stored a NULL?
- movl offThread_cardTable(%eax),%eax # get card table base
- FETCH_INST_OPCODE 5 %edx
+ movl offThread_cardTable(%eax),%eax # get card table base
je 1f # skip card mark if null store
shrl $GC_CARD_SHIFT,%ecx # object head to card number
movb %al,(%eax,%ecx) # mark card using object head
1:
+ FETCH_INST_OPCODE 5 %ecx
+ UNSPILL(rIBASE)
ADVANCE_PC 5
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_IPUT_BOOLEAN_JUMBO */
-
-
-.LOP_IPUT_BOOLEAN_JUMBO_resolve:
+/* ------------------------------ */
+.L_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */
+/* File: x86/OP_IPUT_BOOLEAN_JUMBO.S */
+/* File: x86/OP_IPUT_JUMBO.S */
+ /*
+ * Jumbo 32-bit instance field put.
+ *
+ * for: iput/jumbo, iput-object/jumbo, iput-boolean/jumbo, iput-byte/jumbo,
+ iput-char/jumbo, iput-short/jumbo
+ */
+ /* exop vBBBB, vCCCC, field@AAAAAAAA */
+ movl rSELF,%ecx
+ SPILL(rIBASE)
+ movl 2(rPC),rIBASE # rIBASE<- AAAAAAAA
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzwl 8(rPC),%ecx # ecx<- CCCC
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IPUT_BOOLEAN_JUMBO_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp)
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -12118,20 +8976,41 @@
movl offInstField_byteOffset(%eax),%eax # eax<- byte offset of field
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
- FETCH_INST_OPCODE 5 %edx
movb rINSTbl,(%ecx,%eax,1) # obj.field <- v[BBBB](8/16/32 bits)
+ FETCH_INST_OPCODE 5 %ecx
+ UNSPILL(rIBASE)
ADVANCE_PC 5
- GOTO_NEXT_R %edx
-
-/* continuation for OP_IPUT_BYTE_JUMBO */
+ GOTO_NEXT_R %ecx
-.LOP_IPUT_BYTE_JUMBO_resolve:
+/* ------------------------------ */
+.L_OP_IPUT_BYTE_JUMBO: /* 0x111 */
+/* File: x86/OP_IPUT_BYTE_JUMBO.S */
+/* File: x86/OP_IPUT_JUMBO.S */
+ /*
+ * Jumbo 32-bit instance field put.
+ *
+ * for: iput/jumbo, iput-object/jumbo, iput-boolean/jumbo, iput-byte/jumbo,
+ iput-char/jumbo, iput-short/jumbo
+ */
+ /* exop vBBBB, vCCCC, field@AAAAAAAA */
+ movl rSELF,%ecx
+ SPILL(rIBASE)
+ movl 2(rPC),rIBASE # rIBASE<- AAAAAAAA
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzwl 8(rPC),%ecx # ecx<- CCCC
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IPUT_BYTE_JUMBO_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp)
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -12149,20 +9028,41 @@
movl offInstField_byteOffset(%eax),%eax # eax<- byte offset of field
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
- FETCH_INST_OPCODE 5 %edx
movb rINSTbl,(%ecx,%eax,1) # obj.field <- v[BBBB](8/16/32 bits)
+ FETCH_INST_OPCODE 5 %ecx
+ UNSPILL(rIBASE)
ADVANCE_PC 5
- GOTO_NEXT_R %edx
-
-/* continuation for OP_IPUT_CHAR_JUMBO */
+ GOTO_NEXT_R %ecx
-.LOP_IPUT_CHAR_JUMBO_resolve:
+/* ------------------------------ */
+.L_OP_IPUT_CHAR_JUMBO: /* 0x112 */
+/* File: x86/OP_IPUT_CHAR_JUMBO.S */
+/* File: x86/OP_IPUT_JUMBO.S */
+ /*
+ * Jumbo 32-bit instance field put.
+ *
+ * for: iput/jumbo, iput-object/jumbo, iput-boolean/jumbo, iput-byte/jumbo,
+ iput-char/jumbo, iput-short/jumbo
+ */
+ /* exop vBBBB, vCCCC, field@AAAAAAAA */
+ movl rSELF,%ecx
+ SPILL(rIBASE)
+ movl 2(rPC),rIBASE # rIBASE<- AAAAAAAA
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzwl 8(rPC),%ecx # ecx<- CCCC
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IPUT_CHAR_JUMBO_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp)
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -12180,20 +9080,41 @@
movl offInstField_byteOffset(%eax),%eax # eax<- byte offset of field
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
- FETCH_INST_OPCODE 5 %edx
movw rINSTw,(%ecx,%eax,1) # obj.field <- v[BBBB](8/16/32 bits)
+ FETCH_INST_OPCODE 5 %ecx
+ UNSPILL(rIBASE)
ADVANCE_PC 5
- GOTO_NEXT_R %edx
-
-/* continuation for OP_IPUT_SHORT_JUMBO */
+ GOTO_NEXT_R %ecx
-.LOP_IPUT_SHORT_JUMBO_resolve:
+/* ------------------------------ */
+.L_OP_IPUT_SHORT_JUMBO: /* 0x113 */
+/* File: x86/OP_IPUT_SHORT_JUMBO.S */
+/* File: x86/OP_IPUT_JUMBO.S */
+ /*
+ * Jumbo 32-bit instance field put.
+ *
+ * for: iput/jumbo, iput-object/jumbo, iput-boolean/jumbo, iput-byte/jumbo,
+ iput-char/jumbo, iput-short/jumbo
+ */
+ /* exop vBBBB, vCCCC, field@AAAAAAAA */
+ movl rSELF,%ecx
+ SPILL(rIBASE)
+ movl 2(rPC),rIBASE # rIBASE<- AAAAAAAA
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ movzwl 8(rPC),%ecx # ecx<- CCCC
+ movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
+ GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
+ movl (%eax,rIBASE,4),%eax # resolved entry
+ testl %eax,%eax # is resolved entry null?
+ jne .LOP_IPUT_SHORT_JUMBO_finish # no, already resolved
+ movl rIBASE,OUT_ARG1(%esp)
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -12211,12 +9132,36 @@
movl offInstField_byteOffset(%eax),%eax # eax<- byte offset of field
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
- FETCH_INST_OPCODE 5 %edx
movw rINSTw,(%ecx,%eax,1) # obj.field <- v[BBBB](8/16/32 bits)
+ FETCH_INST_OPCODE 5 %ecx
+ UNSPILL(rIBASE)
ADVANCE_PC 5
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
-/* continuation for OP_SGET_JUMBO */
+
+/* ------------------------------ */
+.L_OP_SGET_JUMBO: /* 0x114 */
+/* File: x86/OP_SGET_JUMBO.S */
+ /*
+ * Jumbo 32-bit SGET handler.
+ *
+ * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
+ * sget-char/jumbo, sget-short/jumbo
+ */
+ /* exop vBBBB, field@AAAAAAAA */
+ movl rSELF,%ecx
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl 2(rPC),%eax # eax<- field ref AAAAAAAA
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SGET_JUMBO_resolve # if not, make it so
+.LOP_SGET_JUMBO_finish: # field ptr in eax
+ movl offStaticField_value(%eax),%eax
+ FETCH_INST_OPCODE 4 %ecx
+ ADVANCE_PC 4
+ SET_VREG %eax rINST
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -12229,12 +9174,36 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SGET_JUMBO_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_SGET_WIDE_JUMBO */
+/* ------------------------------ */
+.L_OP_SGET_WIDE_JUMBO: /* 0x115 */
+/* File: x86/OP_SGET_WIDE_JUMBO.S */
+ /*
+ * Jumbo 64-bit SGET handler.
+ *
+ */
+ /* sget-wide/jumbo vBBBB, field@AAAAAAAA */
+ movl rSELF,%ecx
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl 2(rPC),%eax # eax<- field ref AAAAAAAA
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SGET_WIDE_JUMBO_resolve # if not, make it so
+.LOP_SGET_WIDE_JUMBO_finish: # field ptr in eax
+ movl offStaticField_value(%eax),%ecx # ecx<- lsw
+ movl 4+offStaticField_value(%eax),%eax # eax<- msw
+ SET_VREG_WORD %ecx rINST 0
+ FETCH_INST_OPCODE 2 %ecx
+ SET_VREG_WORD %eax rINST 1
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -12247,12 +9216,37 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SGET_WIDE_JUMBO_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_SGET_OBJECT_JUMBO */
+/* ------------------------------ */
+.L_OP_SGET_OBJECT_JUMBO: /* 0x116 */
+/* File: x86/OP_SGET_OBJECT_JUMBO.S */
+/* File: x86/OP_SGET_JUMBO.S */
+ /*
+ * Jumbo 32-bit SGET handler.
+ *
+ * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
+ * sget-char/jumbo, sget-short/jumbo
+ */
+ /* exop vBBBB, field@AAAAAAAA */
+ movl rSELF,%ecx
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl 2(rPC),%eax # eax<- field ref AAAAAAAA
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SGET_OBJECT_JUMBO_resolve # if not, make it so
+.LOP_SGET_OBJECT_JUMBO_finish: # field ptr in eax
+ movl offStaticField_value(%eax),%eax
+ FETCH_INST_OPCODE 4 %ecx
+ ADVANCE_PC 4
+ SET_VREG %eax rINST
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -12265,12 +9259,38 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SGET_OBJECT_JUMBO_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_SGET_BOOLEAN_JUMBO */
+
+/* ------------------------------ */
+.L_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */
+/* File: x86/OP_SGET_BOOLEAN_JUMBO.S */
+/* File: x86/OP_SGET_JUMBO.S */
+ /*
+ * Jumbo 32-bit SGET handler.
+ *
+ * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
+ * sget-char/jumbo, sget-short/jumbo
+ */
+ /* exop vBBBB, field@AAAAAAAA */
+ movl rSELF,%ecx
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl 2(rPC),%eax # eax<- field ref AAAAAAAA
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SGET_BOOLEAN_JUMBO_resolve # if not, make it so
+.LOP_SGET_BOOLEAN_JUMBO_finish: # field ptr in eax
+ movl offStaticField_value(%eax),%eax
+ FETCH_INST_OPCODE 4 %ecx
+ ADVANCE_PC 4
+ SET_VREG %eax rINST
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -12283,12 +9303,38 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SGET_BOOLEAN_JUMBO_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_SGET_BYTE_JUMBO */
+
+/* ------------------------------ */
+.L_OP_SGET_BYTE_JUMBO: /* 0x118 */
+/* File: x86/OP_SGET_BYTE_JUMBO.S */
+/* File: x86/OP_SGET_JUMBO.S */
+ /*
+ * Jumbo 32-bit SGET handler.
+ *
+ * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
+ * sget-char/jumbo, sget-short/jumbo
+ */
+ /* exop vBBBB, field@AAAAAAAA */
+ movl rSELF,%ecx
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl 2(rPC),%eax # eax<- field ref AAAAAAAA
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SGET_BYTE_JUMBO_resolve # if not, make it so
+.LOP_SGET_BYTE_JUMBO_finish: # field ptr in eax
+ movl offStaticField_value(%eax),%eax
+ FETCH_INST_OPCODE 4 %ecx
+ ADVANCE_PC 4
+ SET_VREG %eax rINST
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -12301,12 +9347,38 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SGET_BYTE_JUMBO_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_SGET_CHAR_JUMBO */
+
+/* ------------------------------ */
+.L_OP_SGET_CHAR_JUMBO: /* 0x119 */
+/* File: x86/OP_SGET_CHAR_JUMBO.S */
+/* File: x86/OP_SGET_JUMBO.S */
+ /*
+ * Jumbo 32-bit SGET handler.
+ *
+ * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
+ * sget-char/jumbo, sget-short/jumbo
+ */
+ /* exop vBBBB, field@AAAAAAAA */
+ movl rSELF,%ecx
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl 2(rPC),%eax # eax<- field ref AAAAAAAA
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SGET_CHAR_JUMBO_resolve # if not, make it so
+.LOP_SGET_CHAR_JUMBO_finish: # field ptr in eax
+ movl offStaticField_value(%eax),%eax
+ FETCH_INST_OPCODE 4 %ecx
+ ADVANCE_PC 4
+ SET_VREG %eax rINST
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -12319,12 +9391,38 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SGET_CHAR_JUMBO_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_SGET_SHORT_JUMBO */
+
+/* ------------------------------ */
+.L_OP_SGET_SHORT_JUMBO: /* 0x11a */
+/* File: x86/OP_SGET_SHORT_JUMBO.S */
+/* File: x86/OP_SGET_JUMBO.S */
+ /*
+ * Jumbo 32-bit SGET handler.
+ *
+ * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
+ * sget-char/jumbo, sget-short/jumbo
+ */
+ /* exop vBBBB, field@AAAAAAAA */
+ movl rSELF,%ecx
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl 2(rPC),%eax # eax<- field ref AAAAAAAA
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SGET_SHORT_JUMBO_resolve # if not, make it so
+.LOP_SGET_SHORT_JUMBO_finish: # field ptr in eax
+ movl offStaticField_value(%eax),%eax
+ FETCH_INST_OPCODE 4 %ecx
+ ADVANCE_PC 4
+ SET_VREG %eax rINST
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -12337,12 +9435,37 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SGET_SHORT_JUMBO_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_SPUT_JUMBO */
+
+/* ------------------------------ */
+.L_OP_SPUT_JUMBO: /* 0x11b */
+/* File: x86/OP_SPUT_JUMBO.S */
+ /*
+ * Jumbo 32-bit SPUT handler.
+ *
+ * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
+ * sput-short/jumbo
+ */
+ /* exop vBBBB, field@AAAAAAAA */
+ movl rSELF,%ecx
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl 2(rPC),%eax # eax<- field ref AAAAAAAA
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SPUT_JUMBO_resolve # if not, make it so
+.LOP_SPUT_JUMBO_finish: # field ptr in eax
+ GET_VREG_R rINST rINST
+ FETCH_INST_OPCODE 4 %ecx
+ ADVANCE_PC 4
+ movl rINST,offStaticField_value(%eax)
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -12355,12 +9478,35 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SPUT_JUMBO_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_SPUT_WIDE_JUMBO */
+/* ------------------------------ */
+.L_OP_SPUT_WIDE_JUMBO: /* 0x11c */
+/* File: x86/OP_SPUT_WIDE_JUMBO.S */
+ /*
+ * Jumbo 64-bit SPUT handler.
+ */
+ /* sput-wide/jumbo vBBBB, field@AAAAAAAA */
+ movl rSELF,%ecx
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl 2(rPC),%eax # eax<- field ref AAAAAAAA
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SPUT_WIDE_JUMBO_resolve # if not, make it so
+.LOP_SPUT_WIDE_JUMBO_finish: # field ptr in eax
+ GET_VREG_WORD %ecx rINST 0 # ecx<- lsw
+ GET_VREG_WORD rINST rINST 1 # rINST<- msw
+ movl %ecx,offStaticField_value(%eax)
+ FETCH_INST_OPCODE 4 %ecx
+ movl rINST,4+offStaticField_value(%eax)
+ ADVANCE_PC 4
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -12373,18 +9519,31 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SPUT_WIDE_JUMBO_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_SPUT_OBJECT_JUMBO */
-
-
-.LOP_SPUT_OBJECT_JUMBO_continue:
+/* ------------------------------ */
+.L_OP_SPUT_OBJECT_JUMBO: /* 0x11d */
+/* File: x86/OP_SPUT_OBJECT_JUMBO.S */
+ /*
+ * Jumbo SPUT object handler.
+ */
+ /* sput-object/jumbo vBBBB, field@AAAAAAAA */
+ movl rSELF,%ecx
+ movl 2(rPC),%eax # eax<- field ref AAAAAAAA
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SPUT_OBJECT_JUMBO_resolve # if not, make it so
+.LOP_SPUT_OBJECT_JUMBO_finish: # field ptr in eax
+ GET_VREG_R %ecx rINST
movl %ecx,offStaticField_value(%eax) # do the store
testl %ecx,%ecx # stored null object ptr?
- FETCH_INST_OPCODE 4 %edx
je 1f # skip card mark if null
movl rSELF,%ecx
movl offField_clazz(%eax),%eax # eax<- method->clazz
@@ -12392,8 +9551,9 @@
shrl $GC_CARD_SHIFT,%eax # head to card number
movb %cl,(%ecx,%eax) # mark card
1:
+ FETCH_INST_OPCODE 4 %ecx
ADVANCE_PC 4
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
.LOP_SPUT_OBJECT_JUMBO_resolve:
movl rSELF,%ecx
@@ -12403,12 +9563,37 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SPUT_OBJECT_JUMBO_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_SPUT_BOOLEAN_JUMBO */
+/* ------------------------------ */
+.L_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */
+/* File: x86/OP_SPUT_BOOLEAN_JUMBO.S */
+/* File: x86/OP_SPUT_JUMBO.S */
+ /*
+ * Jumbo 32-bit SPUT handler.
+ *
+ * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
+ * sput-short/jumbo
+ */
+ /* exop vBBBB, field@AAAAAAAA */
+ movl rSELF,%ecx
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl 2(rPC),%eax # eax<- field ref AAAAAAAA
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SPUT_BOOLEAN_JUMBO_resolve # if not, make it so
+.LOP_SPUT_BOOLEAN_JUMBO_finish: # field ptr in eax
+ GET_VREG_R rINST rINST
+ FETCH_INST_OPCODE 4 %ecx
+ ADVANCE_PC 4
+ movl rINST,offStaticField_value(%eax)
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -12421,12 +9606,38 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SPUT_BOOLEAN_JUMBO_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_SPUT_BYTE_JUMBO */
+
+/* ------------------------------ */
+.L_OP_SPUT_BYTE_JUMBO: /* 0x11f */
+/* File: x86/OP_SPUT_BYTE_JUMBO.S */
+/* File: x86/OP_SPUT_JUMBO.S */
+ /*
+ * Jumbo 32-bit SPUT handler.
+ *
+ * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
+ * sput-short/jumbo
+ */
+ /* exop vBBBB, field@AAAAAAAA */
+ movl rSELF,%ecx
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl 2(rPC),%eax # eax<- field ref AAAAAAAA
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SPUT_BYTE_JUMBO_resolve # if not, make it so
+.LOP_SPUT_BYTE_JUMBO_finish: # field ptr in eax
+ GET_VREG_R rINST rINST
+ FETCH_INST_OPCODE 4 %ecx
+ ADVANCE_PC 4
+ movl rINST,offStaticField_value(%eax)
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -12439,12 +9650,38 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SPUT_BYTE_JUMBO_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_SPUT_CHAR_JUMBO */
+
+/* ------------------------------ */
+.L_OP_SPUT_CHAR_JUMBO: /* 0x120 */
+/* File: x86/OP_SPUT_CHAR_JUMBO.S */
+/* File: x86/OP_SPUT_JUMBO.S */
+ /*
+ * Jumbo 32-bit SPUT handler.
+ *
+ * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
+ * sput-short/jumbo
+ */
+ /* exop vBBBB, field@AAAAAAAA */
+ movl rSELF,%ecx
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl 2(rPC),%eax # eax<- field ref AAAAAAAA
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SPUT_CHAR_JUMBO_resolve # if not, make it so
+.LOP_SPUT_CHAR_JUMBO_finish: # field ptr in eax
+ GET_VREG_R rINST rINST
+ FETCH_INST_OPCODE 4 %ecx
+ ADVANCE_PC 4
+ movl rINST,offStaticField_value(%eax)
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -12457,12 +9694,38 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SPUT_CHAR_JUMBO_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_SPUT_SHORT_JUMBO */
+
+/* ------------------------------ */
+.L_OP_SPUT_SHORT_JUMBO: /* 0x121 */
+/* File: x86/OP_SPUT_SHORT_JUMBO.S */
+/* File: x86/OP_SPUT_JUMBO.S */
+ /*
+ * Jumbo 32-bit SPUT handler.
+ *
+ * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
+ * sput-short/jumbo
+ */
+ /* exop vBBBB, field@AAAAAAAA */
+ movl rSELF,%ecx
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- DvmDex
+ movl 2(rPC),%eax # eax<- field ref AAAAAAAA
+ movl offDvmDex_pResFields(%ecx),%ecx # ecx<- dvmDex->pResFields
+ movl (%ecx,%eax,4),%eax # eax<- resolved StaticField ptr
+ testl %eax,%eax # resolved entry null?
+ je .LOP_SPUT_SHORT_JUMBO_resolve # if not, make it so
+.LOP_SPUT_SHORT_JUMBO_finish: # field ptr in eax
+ GET_VREG_R rINST rINST
+ FETCH_INST_OPCODE 4 %ecx
+ ADVANCE_PC 4
+ movl rINST,offStaticField_value(%eax)
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -12475,15 +9738,32 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .LOP_SPUT_SHORT_JUMBO_finish # success, continue
jmp common_exceptionThrown # no, handle exception
-/* continuation for OP_INVOKE_VIRTUAL_JUMBO */
-
-.LOP_INVOKE_VIRTUAL_JUMBO_more:
+/* ------------------------------ */
+.L_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */
+/* File: x86/OP_INVOKE_VIRTUAL_JUMBO.S */
+ /*
+ * Handle a jumbo virtual method call.
+ */
+ /* invoke-virtual/jumbo vBBBB, {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
+ movl rSELF,%eax
+ movl 2(rPC),%ecx # ecx<- AAAAAAAA
+ movl offThread_methodClassDex(%eax),%eax # eax<- pDvmDex
+ EXPORT_PC
+ movl offDvmDex_pResMethods(%eax),%eax # eax<- pDvmDex->pResMethods
+ movl (%eax,%ecx,4),%eax # eax<- resolved baseMethod
+ testl %eax,%eax # already resolved?
+ jne .LOP_INVOKE_VIRTUAL_JUMBO_continue # yes, continue
+ movl rSELF,%eax
+ movl %ecx,OUT_ARG1(%esp) # arg1<- ref
+ movl offThread_method(%eax),%eax # eax<- self->method
movl offMethod_clazz(%eax),%eax # ecx<- method->clazz
movl %eax,OUT_ARG0(%esp) # arg0<- clazz
movl $METHOD_VIRTUAL,OUT_ARG2(%esp) # arg2<- flags
@@ -12507,8 +9787,27 @@
movl (%ecx,%eax,4),%eax # eax<- vtable[methodIndex]
jmp common_invokeMethodJumbo
-/* continuation for OP_INVOKE_SUPER_JUMBO */
-
+/* ------------------------------ */
+.L_OP_INVOKE_SUPER_JUMBO: /* 0x123 */
+/* File: x86/OP_INVOKE_SUPER_JUMBO.S */
+ /*
+ * Handle a jumbo "super" method call.
+ */
+ /* invoke-super/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
+ movl rSELF,rINST
+ movl 2(rPC),%eax # eax<- AAAAAAAA
+ movl offThread_methodClassDex(rINST),%ecx # ecx<- pDvmDex
+ EXPORT_PC
+ movl offDvmDex_pResMethods(%ecx),%ecx # ecx<- pDvmDex->pResMethods
+ movl (%ecx,%eax,4),%ecx # ecx<- resolved baseMethod
+ movl offThread_method(rINST),%eax # eax<- method
+ movzwl 8(rPC),rINST # rINST<- CCCC
+ GET_VREG_R rINST rINST # rINST<- "this" ptr
+ testl rINST,rINST # null "this"?
+ je common_errNullObject # yes, throw
+ movl offMethod_clazz(%eax),%eax # eax<- method->clazz
+ testl %ecx,%ecx # already resolved?
+ je .LOP_INVOKE_SUPER_JUMBO_resolve
/*
* At this point:
* ecx = resolved base method [r0]
@@ -12550,7 +9849,32 @@
mov %eax,OUT_ARG1(%esp)
jmp common_errNoSuchMethod
-/* continuation for OP_INVOKE_DIRECT_JUMBO */
+/* ------------------------------ */
+.L_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */
+/* File: x86/OP_INVOKE_DIRECT_JUMBO.S */
+ /*
+ * Handle a jumbo direct method call.
+ *
+ * (We could defer the "is 'this' pointer null" test to the common
+ * method invocation code, and use a flag to indicate that static
+ * calls don't count. If we do this as part of copying the arguments
+ * out we could avoiding loading the first arg twice.)
+ */
+ /* invoke-direct/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
+ movl rSELF,%ecx
+ movl 2(rPC),%eax # eax<- AAAAAAAA
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
+ EXPORT_PC
+ movl offDvmDex_pResMethods(%ecx),%ecx # ecx<- pDvmDex->pResMethods
+ movzwl 8(rPC),rIBASE # rIBASE<- CCCC
+ movl (%ecx,%eax,4),%eax # eax<- resolved methodToCall
+ testl %eax,%eax # already resolved?
+ GET_VREG_R %ecx rIBASE # ecx<- "this" ptr
+ je .LOP_INVOKE_DIRECT_JUMBO_resolve # not resolved, do it now
+.LOP_INVOKE_DIRECT_JUMBO_finish:
+ testl %ecx,%ecx # null "this"?
+ jne common_invokeMethodJumbo # no, continue on
+ jmp common_errNullObject
/*
* On entry:
@@ -12573,9 +9897,27 @@
jne .LOP_INVOKE_DIRECT_JUMBO_finish
jmp common_exceptionThrown
-/* continuation for OP_INVOKE_STATIC_JUMBO */
-
-.LOP_INVOKE_STATIC_JUMBO_continue:
+/* ------------------------------ */
+.L_OP_INVOKE_STATIC_JUMBO: /* 0x125 */
+/* File: x86/OP_INVOKE_STATIC_JUMBO.S */
+ /*
+ * Handle a jumbo static method call.
+ */
+ /* invoke-static/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
+ movl rSELF,%ecx
+ movl 2(rPC),%eax # eax<- AAAAAAAA
+ movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
+ EXPORT_PC
+ movl offDvmDex_pResMethods(%ecx),%ecx # ecx<- pDvmDex->pResMethods
+ movl (%ecx,%eax,4),%eax # eax<- resolved methodToCall
+ testl %eax,%eax
+ jne common_invokeMethodJumbo
+ movl rSELF,%ecx
+ movl offThread_method(%ecx),%ecx # ecx<- self->method
+ movl 2(rPC),%eax # eax<- AAAAAAAA
+ movl offMethod_clazz(%ecx),%ecx# ecx<- method->clazz
+ movl %eax,OUT_ARG1(%esp) # arg1<- AAAAAAAA
+ movl %ecx,OUT_ARG0(%esp) # arg0<- clazz
movl $METHOD_STATIC,%eax
movl %eax,OUT_ARG2(%esp) # arg2<- flags
call dvmResolveMethod # call(clazz,ref,flags)
@@ -12583,18 +9925,11300 @@
jne common_invokeMethodJumbo
jmp common_exceptionThrown
-/* continuation for OP_INVOKE_INTERFACE_JUMBO */
-
-.LOP_INVOKE_INTERFACE_JUMBO_continue:
+/* ------------------------------ */
+.L_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */
+/* File: x86/OP_INVOKE_INTERFACE_JUMBO.S */
+ /*
+ * Handle a jumbo interface method call.
+ */
+ /* invoke-interface/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
+ movzwl 8(rPC),%eax # eax<- CCCC
+ movl rSELF,%ecx
+ GET_VREG_R %eax %eax # eax<- "this"
+ EXPORT_PC
+ testl %eax,%eax # null this?
+ je common_errNullObject # yes, fail
+ movl offObject_clazz(%eax),%eax# eax<- thisPtr->clazz
+ movl %eax,OUT_ARG0(%esp) # arg0<- class
+ movl offThread_methodClassDex(%ecx),%eax # eax<- methodClassDex
+ movl offThread_method(%ecx),%ecx # ecx<- method
+ movl %eax,OUT_ARG3(%esp) # arg3<- dex
+ movl 2(rPC),%eax # eax<- AAAAAAAA
+ movl %ecx,OUT_ARG2(%esp) # arg2<- method
+ movl %eax,OUT_ARG1(%esp) # arg1<- AAAAAAAA
call dvmFindInterfaceMethodInCache # eax<- call(class, ref, method, dex)
testl %eax,%eax
je common_exceptionThrown
jmp common_invokeMethodJumbo
- .size dvmAsmSisterStart, .-dvmAsmSisterStart
- .global dvmAsmSisterEnd
-dvmAsmSisterEnd:
+/* ------------------------------ */
+.L_OP_UNUSED_27FF: /* 0x127 */
+/* File: x86/OP_UNUSED_27FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+/* ------------------------------ */
+.L_OP_UNUSED_28FF: /* 0x128 */
+/* File: x86/OP_UNUSED_28FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_29FF: /* 0x129 */
+/* File: x86/OP_UNUSED_29FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_2AFF: /* 0x12a */
+/* File: x86/OP_UNUSED_2AFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_2BFF: /* 0x12b */
+/* File: x86/OP_UNUSED_2BFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_2CFF: /* 0x12c */
+/* File: x86/OP_UNUSED_2CFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_2DFF: /* 0x12d */
+/* File: x86/OP_UNUSED_2DFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_2EFF: /* 0x12e */
+/* File: x86/OP_UNUSED_2EFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_2FFF: /* 0x12f */
+/* File: x86/OP_UNUSED_2FFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_30FF: /* 0x130 */
+/* File: x86/OP_UNUSED_30FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_31FF: /* 0x131 */
+/* File: x86/OP_UNUSED_31FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_32FF: /* 0x132 */
+/* File: x86/OP_UNUSED_32FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_33FF: /* 0x133 */
+/* File: x86/OP_UNUSED_33FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_34FF: /* 0x134 */
+/* File: x86/OP_UNUSED_34FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_35FF: /* 0x135 */
+/* File: x86/OP_UNUSED_35FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_36FF: /* 0x136 */
+/* File: x86/OP_UNUSED_36FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_37FF: /* 0x137 */
+/* File: x86/OP_UNUSED_37FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_38FF: /* 0x138 */
+/* File: x86/OP_UNUSED_38FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_39FF: /* 0x139 */
+/* File: x86/OP_UNUSED_39FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_3AFF: /* 0x13a */
+/* File: x86/OP_UNUSED_3AFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_3BFF: /* 0x13b */
+/* File: x86/OP_UNUSED_3BFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_3CFF: /* 0x13c */
+/* File: x86/OP_UNUSED_3CFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_3DFF: /* 0x13d */
+/* File: x86/OP_UNUSED_3DFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_3EFF: /* 0x13e */
+/* File: x86/OP_UNUSED_3EFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_3FFF: /* 0x13f */
+/* File: x86/OP_UNUSED_3FFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_40FF: /* 0x140 */
+/* File: x86/OP_UNUSED_40FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_41FF: /* 0x141 */
+/* File: x86/OP_UNUSED_41FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_42FF: /* 0x142 */
+/* File: x86/OP_UNUSED_42FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_43FF: /* 0x143 */
+/* File: x86/OP_UNUSED_43FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_44FF: /* 0x144 */
+/* File: x86/OP_UNUSED_44FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_45FF: /* 0x145 */
+/* File: x86/OP_UNUSED_45FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_46FF: /* 0x146 */
+/* File: x86/OP_UNUSED_46FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_47FF: /* 0x147 */
+/* File: x86/OP_UNUSED_47FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_48FF: /* 0x148 */
+/* File: x86/OP_UNUSED_48FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_49FF: /* 0x149 */
+/* File: x86/OP_UNUSED_49FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_4AFF: /* 0x14a */
+/* File: x86/OP_UNUSED_4AFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_4BFF: /* 0x14b */
+/* File: x86/OP_UNUSED_4BFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_4CFF: /* 0x14c */
+/* File: x86/OP_UNUSED_4CFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_4DFF: /* 0x14d */
+/* File: x86/OP_UNUSED_4DFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_4EFF: /* 0x14e */
+/* File: x86/OP_UNUSED_4EFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_4FFF: /* 0x14f */
+/* File: x86/OP_UNUSED_4FFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_50FF: /* 0x150 */
+/* File: x86/OP_UNUSED_50FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_51FF: /* 0x151 */
+/* File: x86/OP_UNUSED_51FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_52FF: /* 0x152 */
+/* File: x86/OP_UNUSED_52FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_53FF: /* 0x153 */
+/* File: x86/OP_UNUSED_53FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_54FF: /* 0x154 */
+/* File: x86/OP_UNUSED_54FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_55FF: /* 0x155 */
+/* File: x86/OP_UNUSED_55FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_56FF: /* 0x156 */
+/* File: x86/OP_UNUSED_56FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_57FF: /* 0x157 */
+/* File: x86/OP_UNUSED_57FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_58FF: /* 0x158 */
+/* File: x86/OP_UNUSED_58FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_59FF: /* 0x159 */
+/* File: x86/OP_UNUSED_59FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_5AFF: /* 0x15a */
+/* File: x86/OP_UNUSED_5AFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_5BFF: /* 0x15b */
+/* File: x86/OP_UNUSED_5BFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_5CFF: /* 0x15c */
+/* File: x86/OP_UNUSED_5CFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_5DFF: /* 0x15d */
+/* File: x86/OP_UNUSED_5DFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_5EFF: /* 0x15e */
+/* File: x86/OP_UNUSED_5EFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_5FFF: /* 0x15f */
+/* File: x86/OP_UNUSED_5FFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_60FF: /* 0x160 */
+/* File: x86/OP_UNUSED_60FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_61FF: /* 0x161 */
+/* File: x86/OP_UNUSED_61FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_62FF: /* 0x162 */
+/* File: x86/OP_UNUSED_62FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_63FF: /* 0x163 */
+/* File: x86/OP_UNUSED_63FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_64FF: /* 0x164 */
+/* File: x86/OP_UNUSED_64FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_65FF: /* 0x165 */
+/* File: x86/OP_UNUSED_65FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_66FF: /* 0x166 */
+/* File: x86/OP_UNUSED_66FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_67FF: /* 0x167 */
+/* File: x86/OP_UNUSED_67FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_68FF: /* 0x168 */
+/* File: x86/OP_UNUSED_68FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_69FF: /* 0x169 */
+/* File: x86/OP_UNUSED_69FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_6AFF: /* 0x16a */
+/* File: x86/OP_UNUSED_6AFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_6BFF: /* 0x16b */
+/* File: x86/OP_UNUSED_6BFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_6CFF: /* 0x16c */
+/* File: x86/OP_UNUSED_6CFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_6DFF: /* 0x16d */
+/* File: x86/OP_UNUSED_6DFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_6EFF: /* 0x16e */
+/* File: x86/OP_UNUSED_6EFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_6FFF: /* 0x16f */
+/* File: x86/OP_UNUSED_6FFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_70FF: /* 0x170 */
+/* File: x86/OP_UNUSED_70FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_71FF: /* 0x171 */
+/* File: x86/OP_UNUSED_71FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_72FF: /* 0x172 */
+/* File: x86/OP_UNUSED_72FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_73FF: /* 0x173 */
+/* File: x86/OP_UNUSED_73FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_74FF: /* 0x174 */
+/* File: x86/OP_UNUSED_74FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_75FF: /* 0x175 */
+/* File: x86/OP_UNUSED_75FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_76FF: /* 0x176 */
+/* File: x86/OP_UNUSED_76FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_77FF: /* 0x177 */
+/* File: x86/OP_UNUSED_77FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_78FF: /* 0x178 */
+/* File: x86/OP_UNUSED_78FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_79FF: /* 0x179 */
+/* File: x86/OP_UNUSED_79FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_7AFF: /* 0x17a */
+/* File: x86/OP_UNUSED_7AFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_7BFF: /* 0x17b */
+/* File: x86/OP_UNUSED_7BFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_7CFF: /* 0x17c */
+/* File: x86/OP_UNUSED_7CFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_7DFF: /* 0x17d */
+/* File: x86/OP_UNUSED_7DFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_7EFF: /* 0x17e */
+/* File: x86/OP_UNUSED_7EFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_7FFF: /* 0x17f */
+/* File: x86/OP_UNUSED_7FFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_80FF: /* 0x180 */
+/* File: x86/OP_UNUSED_80FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_81FF: /* 0x181 */
+/* File: x86/OP_UNUSED_81FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_82FF: /* 0x182 */
+/* File: x86/OP_UNUSED_82FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_83FF: /* 0x183 */
+/* File: x86/OP_UNUSED_83FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_84FF: /* 0x184 */
+/* File: x86/OP_UNUSED_84FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_85FF: /* 0x185 */
+/* File: x86/OP_UNUSED_85FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_86FF: /* 0x186 */
+/* File: x86/OP_UNUSED_86FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_87FF: /* 0x187 */
+/* File: x86/OP_UNUSED_87FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_88FF: /* 0x188 */
+/* File: x86/OP_UNUSED_88FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_89FF: /* 0x189 */
+/* File: x86/OP_UNUSED_89FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_8AFF: /* 0x18a */
+/* File: x86/OP_UNUSED_8AFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_8BFF: /* 0x18b */
+/* File: x86/OP_UNUSED_8BFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_8CFF: /* 0x18c */
+/* File: x86/OP_UNUSED_8CFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_8DFF: /* 0x18d */
+/* File: x86/OP_UNUSED_8DFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_8EFF: /* 0x18e */
+/* File: x86/OP_UNUSED_8EFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_8FFF: /* 0x18f */
+/* File: x86/OP_UNUSED_8FFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_90FF: /* 0x190 */
+/* File: x86/OP_UNUSED_90FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_91FF: /* 0x191 */
+/* File: x86/OP_UNUSED_91FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_92FF: /* 0x192 */
+/* File: x86/OP_UNUSED_92FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_93FF: /* 0x193 */
+/* File: x86/OP_UNUSED_93FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_94FF: /* 0x194 */
+/* File: x86/OP_UNUSED_94FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_95FF: /* 0x195 */
+/* File: x86/OP_UNUSED_95FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_96FF: /* 0x196 */
+/* File: x86/OP_UNUSED_96FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_97FF: /* 0x197 */
+/* File: x86/OP_UNUSED_97FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_98FF: /* 0x198 */
+/* File: x86/OP_UNUSED_98FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_99FF: /* 0x199 */
+/* File: x86/OP_UNUSED_99FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_9AFF: /* 0x19a */
+/* File: x86/OP_UNUSED_9AFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_9BFF: /* 0x19b */
+/* File: x86/OP_UNUSED_9BFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_9CFF: /* 0x19c */
+/* File: x86/OP_UNUSED_9CFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_9DFF: /* 0x19d */
+/* File: x86/OP_UNUSED_9DFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_9EFF: /* 0x19e */
+/* File: x86/OP_UNUSED_9EFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_9FFF: /* 0x19f */
+/* File: x86/OP_UNUSED_9FFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_A0FF: /* 0x1a0 */
+/* File: x86/OP_UNUSED_A0FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_A1FF: /* 0x1a1 */
+/* File: x86/OP_UNUSED_A1FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_A2FF: /* 0x1a2 */
+/* File: x86/OP_UNUSED_A2FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_A3FF: /* 0x1a3 */
+/* File: x86/OP_UNUSED_A3FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_A4FF: /* 0x1a4 */
+/* File: x86/OP_UNUSED_A4FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_A5FF: /* 0x1a5 */
+/* File: x86/OP_UNUSED_A5FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_A6FF: /* 0x1a6 */
+/* File: x86/OP_UNUSED_A6FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_A7FF: /* 0x1a7 */
+/* File: x86/OP_UNUSED_A7FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_A8FF: /* 0x1a8 */
+/* File: x86/OP_UNUSED_A8FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_A9FF: /* 0x1a9 */
+/* File: x86/OP_UNUSED_A9FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_AAFF: /* 0x1aa */
+/* File: x86/OP_UNUSED_AAFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_ABFF: /* 0x1ab */
+/* File: x86/OP_UNUSED_ABFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_ACFF: /* 0x1ac */
+/* File: x86/OP_UNUSED_ACFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_ADFF: /* 0x1ad */
+/* File: x86/OP_UNUSED_ADFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_AEFF: /* 0x1ae */
+/* File: x86/OP_UNUSED_AEFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_AFFF: /* 0x1af */
+/* File: x86/OP_UNUSED_AFFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_B0FF: /* 0x1b0 */
+/* File: x86/OP_UNUSED_B0FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_B1FF: /* 0x1b1 */
+/* File: x86/OP_UNUSED_B1FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_B2FF: /* 0x1b2 */
+/* File: x86/OP_UNUSED_B2FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_B3FF: /* 0x1b3 */
+/* File: x86/OP_UNUSED_B3FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_B4FF: /* 0x1b4 */
+/* File: x86/OP_UNUSED_B4FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_B5FF: /* 0x1b5 */
+/* File: x86/OP_UNUSED_B5FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_B6FF: /* 0x1b6 */
+/* File: x86/OP_UNUSED_B6FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_B7FF: /* 0x1b7 */
+/* File: x86/OP_UNUSED_B7FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_B8FF: /* 0x1b8 */
+/* File: x86/OP_UNUSED_B8FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_B9FF: /* 0x1b9 */
+/* File: x86/OP_UNUSED_B9FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_BAFF: /* 0x1ba */
+/* File: x86/OP_UNUSED_BAFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_BBFF: /* 0x1bb */
+/* File: x86/OP_UNUSED_BBFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_BCFF: /* 0x1bc */
+/* File: x86/OP_UNUSED_BCFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_BDFF: /* 0x1bd */
+/* File: x86/OP_UNUSED_BDFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_BEFF: /* 0x1be */
+/* File: x86/OP_UNUSED_BEFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_BFFF: /* 0x1bf */
+/* File: x86/OP_UNUSED_BFFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_C0FF: /* 0x1c0 */
+/* File: x86/OP_UNUSED_C0FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_C1FF: /* 0x1c1 */
+/* File: x86/OP_UNUSED_C1FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_C2FF: /* 0x1c2 */
+/* File: x86/OP_UNUSED_C2FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_C3FF: /* 0x1c3 */
+/* File: x86/OP_UNUSED_C3FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_C4FF: /* 0x1c4 */
+/* File: x86/OP_UNUSED_C4FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_C5FF: /* 0x1c5 */
+/* File: x86/OP_UNUSED_C5FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_C6FF: /* 0x1c6 */
+/* File: x86/OP_UNUSED_C6FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_C7FF: /* 0x1c7 */
+/* File: x86/OP_UNUSED_C7FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_C8FF: /* 0x1c8 */
+/* File: x86/OP_UNUSED_C8FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_C9FF: /* 0x1c9 */
+/* File: x86/OP_UNUSED_C9FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_CAFF: /* 0x1ca */
+/* File: x86/OP_UNUSED_CAFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_CBFF: /* 0x1cb */
+/* File: x86/OP_UNUSED_CBFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_CCFF: /* 0x1cc */
+/* File: x86/OP_UNUSED_CCFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_CDFF: /* 0x1cd */
+/* File: x86/OP_UNUSED_CDFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_CEFF: /* 0x1ce */
+/* File: x86/OP_UNUSED_CEFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_CFFF: /* 0x1cf */
+/* File: x86/OP_UNUSED_CFFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_D0FF: /* 0x1d0 */
+/* File: x86/OP_UNUSED_D0FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_D1FF: /* 0x1d1 */
+/* File: x86/OP_UNUSED_D1FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_D2FF: /* 0x1d2 */
+/* File: x86/OP_UNUSED_D2FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_D3FF: /* 0x1d3 */
+/* File: x86/OP_UNUSED_D3FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_D4FF: /* 0x1d4 */
+/* File: x86/OP_UNUSED_D4FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_D5FF: /* 0x1d5 */
+/* File: x86/OP_UNUSED_D5FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_D6FF: /* 0x1d6 */
+/* File: x86/OP_UNUSED_D6FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_D7FF: /* 0x1d7 */
+/* File: x86/OP_UNUSED_D7FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_D8FF: /* 0x1d8 */
+/* File: x86/OP_UNUSED_D8FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_D9FF: /* 0x1d9 */
+/* File: x86/OP_UNUSED_D9FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_DAFF: /* 0x1da */
+/* File: x86/OP_UNUSED_DAFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_DBFF: /* 0x1db */
+/* File: x86/OP_UNUSED_DBFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_DCFF: /* 0x1dc */
+/* File: x86/OP_UNUSED_DCFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_DDFF: /* 0x1dd */
+/* File: x86/OP_UNUSED_DDFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_DEFF: /* 0x1de */
+/* File: x86/OP_UNUSED_DEFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_DFFF: /* 0x1df */
+/* File: x86/OP_UNUSED_DFFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_E0FF: /* 0x1e0 */
+/* File: x86/OP_UNUSED_E0FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_E1FF: /* 0x1e1 */
+/* File: x86/OP_UNUSED_E1FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_E2FF: /* 0x1e2 */
+/* File: x86/OP_UNUSED_E2FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_E3FF: /* 0x1e3 */
+/* File: x86/OP_UNUSED_E3FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_E4FF: /* 0x1e4 */
+/* File: x86/OP_UNUSED_E4FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_E5FF: /* 0x1e5 */
+/* File: x86/OP_UNUSED_E5FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_E6FF: /* 0x1e6 */
+/* File: x86/OP_UNUSED_E6FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_E7FF: /* 0x1e7 */
+/* File: x86/OP_UNUSED_E7FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_E8FF: /* 0x1e8 */
+/* File: x86/OP_UNUSED_E8FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_E9FF: /* 0x1e9 */
+/* File: x86/OP_UNUSED_E9FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_EAFF: /* 0x1ea */
+/* File: x86/OP_UNUSED_EAFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_EBFF: /* 0x1eb */
+/* File: x86/OP_UNUSED_EBFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_ECFF: /* 0x1ec */
+/* File: x86/OP_UNUSED_ECFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_EDFF: /* 0x1ed */
+/* File: x86/OP_UNUSED_EDFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_EEFF: /* 0x1ee */
+/* File: x86/OP_UNUSED_EEFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_EFFF: /* 0x1ef */
+/* File: x86/OP_UNUSED_EFFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_F0FF: /* 0x1f0 */
+/* File: x86/OP_UNUSED_F0FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_F1FF: /* 0x1f1 */
+/* File: x86/OP_UNUSED_F1FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_F2FF: /* 0x1f2 */
+/* File: x86/OP_UNUSED_F2FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_F3FF: /* 0x1f3 */
+/* File: x86/OP_UNUSED_F3FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_F4FF: /* 0x1f4 */
+/* File: x86/OP_UNUSED_F4FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_F5FF: /* 0x1f5 */
+/* File: x86/OP_UNUSED_F5FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_F6FF: /* 0x1f6 */
+/* File: x86/OP_UNUSED_F6FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_F7FF: /* 0x1f7 */
+/* File: x86/OP_UNUSED_F7FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_F8FF: /* 0x1f8 */
+/* File: x86/OP_UNUSED_F8FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_F9FF: /* 0x1f9 */
+/* File: x86/OP_UNUSED_F9FF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_FAFF: /* 0x1fa */
+/* File: x86/OP_UNUSED_FAFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_FBFF: /* 0x1fb */
+/* File: x86/OP_UNUSED_FBFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_FCFF: /* 0x1fc */
+/* File: x86/OP_UNUSED_FCFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_FDFF: /* 0x1fd */
+/* File: x86/OP_UNUSED_FDFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_UNUSED_FEFF: /* 0x1fe */
+/* File: x86/OP_UNUSED_FEFF.S */
+/* File: x86/unused.S */
+ jmp common_abort
+
+
+/* ------------------------------ */
+.L_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */
+/* File: x86/OP_THROW_VERIFICATION_ERROR_JUMBO.S */
+ /*
+ * Handle a jumbo throw-verification-error instruction. This throws an
+ * exception for an error discovered during verification. The
+ * exception is indicated by BBBB, with some detail provided by AAAAAAAA.
+ */
+ /* exop BBBB, ref@AAAAAAAA */
+ movl rSELF,%ecx
+ movl 2(rPC),%eax # eax<- AAAAAAAA
+ movl offThread_method(%ecx),%ecx # ecx<- self->method
+ EXPORT_PC
+ movl %eax,OUT_ARG2(%esp) # arg2<- AAAAAAAA
+ movl rINST,OUT_ARG1(%esp) # arg1<- BBBB
+ movl %ecx,OUT_ARG0(%esp) # arg0<- method
+ call dvmThrowVerificationError # call(method, kind, ref)
+ jmp common_exceptionThrown # handle exception
+
+ .size dvmAsmInstructionStartCode, .-dvmAsmInstructionStartCode
+ .global dvmAsmInstructionEndCode
+dvmAsmInstructionEndCode:
+
+ .global dvmAsmAltInstructionStartCode
+ .type dvmAsmAltInstructionStartCode, %function
+dvmAsmAltInstructionStartCode:
+ .text
+
+/* ------------------------------ */
+.L_ALT_OP_NOP: /* 0x00 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(0*4)
+
+/* ------------------------------ */
+.L_ALT_OP_MOVE: /* 0x01 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(1*4)
+
+/* ------------------------------ */
+.L_ALT_OP_MOVE_FROM16: /* 0x02 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(2*4)
+
+/* ------------------------------ */
+.L_ALT_OP_MOVE_16: /* 0x03 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(3*4)
+
+/* ------------------------------ */
+.L_ALT_OP_MOVE_WIDE: /* 0x04 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(4*4)
+
+/* ------------------------------ */
+.L_ALT_OP_MOVE_WIDE_FROM16: /* 0x05 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(5*4)
+
+/* ------------------------------ */
+.L_ALT_OP_MOVE_WIDE_16: /* 0x06 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(6*4)
+
+/* ------------------------------ */
+.L_ALT_OP_MOVE_OBJECT: /* 0x07 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(7*4)
+
+/* ------------------------------ */
+.L_ALT_OP_MOVE_OBJECT_FROM16: /* 0x08 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(8*4)
+
+/* ------------------------------ */
+.L_ALT_OP_MOVE_OBJECT_16: /* 0x09 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(9*4)
+
+/* ------------------------------ */
+.L_ALT_OP_MOVE_RESULT: /* 0x0a */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(10*4)
+
+/* ------------------------------ */
+.L_ALT_OP_MOVE_RESULT_WIDE: /* 0x0b */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(11*4)
+
+/* ------------------------------ */
+.L_ALT_OP_MOVE_RESULT_OBJECT: /* 0x0c */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(12*4)
+
+/* ------------------------------ */
+.L_ALT_OP_MOVE_EXCEPTION: /* 0x0d */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(13*4)
+
+/* ------------------------------ */
+.L_ALT_OP_RETURN_VOID: /* 0x0e */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(14*4)
+
+/* ------------------------------ */
+.L_ALT_OP_RETURN: /* 0x0f */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(15*4)
+
+/* ------------------------------ */
+.L_ALT_OP_RETURN_WIDE: /* 0x10 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(16*4)
+
+/* ------------------------------ */
+.L_ALT_OP_RETURN_OBJECT: /* 0x11 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(17*4)
+
+/* ------------------------------ */
+.L_ALT_OP_CONST_4: /* 0x12 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(18*4)
+
+/* ------------------------------ */
+.L_ALT_OP_CONST_16: /* 0x13 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(19*4)
+
+/* ------------------------------ */
+.L_ALT_OP_CONST: /* 0x14 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(20*4)
+
+/* ------------------------------ */
+.L_ALT_OP_CONST_HIGH16: /* 0x15 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(21*4)
+
+/* ------------------------------ */
+.L_ALT_OP_CONST_WIDE_16: /* 0x16 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(22*4)
+
+/* ------------------------------ */
+.L_ALT_OP_CONST_WIDE_32: /* 0x17 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(23*4)
+
+/* ------------------------------ */
+.L_ALT_OP_CONST_WIDE: /* 0x18 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(24*4)
+
+/* ------------------------------ */
+.L_ALT_OP_CONST_WIDE_HIGH16: /* 0x19 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(25*4)
+
+/* ------------------------------ */
+.L_ALT_OP_CONST_STRING: /* 0x1a */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(26*4)
+
+/* ------------------------------ */
+.L_ALT_OP_CONST_STRING_JUMBO: /* 0x1b */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(27*4)
+
+/* ------------------------------ */
+.L_ALT_OP_CONST_CLASS: /* 0x1c */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(28*4)
+
+/* ------------------------------ */
+.L_ALT_OP_MONITOR_ENTER: /* 0x1d */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(29*4)
+
+/* ------------------------------ */
+.L_ALT_OP_MONITOR_EXIT: /* 0x1e */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(30*4)
+
+/* ------------------------------ */
+.L_ALT_OP_CHECK_CAST: /* 0x1f */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(31*4)
+
+/* ------------------------------ */
+.L_ALT_OP_INSTANCE_OF: /* 0x20 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(32*4)
+
+/* ------------------------------ */
+.L_ALT_OP_ARRAY_LENGTH: /* 0x21 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(33*4)
+
+/* ------------------------------ */
+.L_ALT_OP_NEW_INSTANCE: /* 0x22 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(34*4)
+
+/* ------------------------------ */
+.L_ALT_OP_NEW_ARRAY: /* 0x23 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(35*4)
+
+/* ------------------------------ */
+.L_ALT_OP_FILLED_NEW_ARRAY: /* 0x24 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(36*4)
+
+/* ------------------------------ */
+.L_ALT_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(37*4)
+
+/* ------------------------------ */
+.L_ALT_OP_FILL_ARRAY_DATA: /* 0x26 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(38*4)
+
+/* ------------------------------ */
+.L_ALT_OP_THROW: /* 0x27 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(39*4)
+
+/* ------------------------------ */
+.L_ALT_OP_GOTO: /* 0x28 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(40*4)
+
+/* ------------------------------ */
+.L_ALT_OP_GOTO_16: /* 0x29 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(41*4)
+
+/* ------------------------------ */
+.L_ALT_OP_GOTO_32: /* 0x2a */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(42*4)
+
+/* ------------------------------ */
+.L_ALT_OP_PACKED_SWITCH: /* 0x2b */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(43*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SPARSE_SWITCH: /* 0x2c */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(44*4)
+
+/* ------------------------------ */
+.L_ALT_OP_CMPL_FLOAT: /* 0x2d */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(45*4)
+
+/* ------------------------------ */
+.L_ALT_OP_CMPG_FLOAT: /* 0x2e */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(46*4)
+
+/* ------------------------------ */
+.L_ALT_OP_CMPL_DOUBLE: /* 0x2f */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(47*4)
+
+/* ------------------------------ */
+.L_ALT_OP_CMPG_DOUBLE: /* 0x30 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(48*4)
+
+/* ------------------------------ */
+.L_ALT_OP_CMP_LONG: /* 0x31 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(49*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IF_EQ: /* 0x32 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(50*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IF_NE: /* 0x33 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(51*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IF_LT: /* 0x34 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(52*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IF_GE: /* 0x35 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(53*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IF_GT: /* 0x36 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(54*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IF_LE: /* 0x37 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(55*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IF_EQZ: /* 0x38 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(56*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IF_NEZ: /* 0x39 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(57*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IF_LTZ: /* 0x3a */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(58*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IF_GEZ: /* 0x3b */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(59*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IF_GTZ: /* 0x3c */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(60*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IF_LEZ: /* 0x3d */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(61*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_3E: /* 0x3e */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(62*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_3F: /* 0x3f */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(63*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_40: /* 0x40 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(64*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_41: /* 0x41 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(65*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_42: /* 0x42 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(66*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_43: /* 0x43 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(67*4)
+
+/* ------------------------------ */
+.L_ALT_OP_AGET: /* 0x44 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(68*4)
+
+/* ------------------------------ */
+.L_ALT_OP_AGET_WIDE: /* 0x45 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(69*4)
+
+/* ------------------------------ */
+.L_ALT_OP_AGET_OBJECT: /* 0x46 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(70*4)
+
+/* ------------------------------ */
+.L_ALT_OP_AGET_BOOLEAN: /* 0x47 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(71*4)
+
+/* ------------------------------ */
+.L_ALT_OP_AGET_BYTE: /* 0x48 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(72*4)
+
+/* ------------------------------ */
+.L_ALT_OP_AGET_CHAR: /* 0x49 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(73*4)
+
+/* ------------------------------ */
+.L_ALT_OP_AGET_SHORT: /* 0x4a */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(74*4)
+
+/* ------------------------------ */
+.L_ALT_OP_APUT: /* 0x4b */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(75*4)
+
+/* ------------------------------ */
+.L_ALT_OP_APUT_WIDE: /* 0x4c */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(76*4)
+
+/* ------------------------------ */
+.L_ALT_OP_APUT_OBJECT: /* 0x4d */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(77*4)
+
+/* ------------------------------ */
+.L_ALT_OP_APUT_BOOLEAN: /* 0x4e */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(78*4)
+
+/* ------------------------------ */
+.L_ALT_OP_APUT_BYTE: /* 0x4f */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(79*4)
+
+/* ------------------------------ */
+.L_ALT_OP_APUT_CHAR: /* 0x50 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(80*4)
+
+/* ------------------------------ */
+.L_ALT_OP_APUT_SHORT: /* 0x51 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(81*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IGET: /* 0x52 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(82*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IGET_WIDE: /* 0x53 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(83*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IGET_OBJECT: /* 0x54 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(84*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IGET_BOOLEAN: /* 0x55 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(85*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IGET_BYTE: /* 0x56 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(86*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IGET_CHAR: /* 0x57 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(87*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IGET_SHORT: /* 0x58 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(88*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IPUT: /* 0x59 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(89*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IPUT_WIDE: /* 0x5a */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(90*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IPUT_OBJECT: /* 0x5b */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(91*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IPUT_BOOLEAN: /* 0x5c */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(92*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IPUT_BYTE: /* 0x5d */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(93*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IPUT_CHAR: /* 0x5e */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(94*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IPUT_SHORT: /* 0x5f */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(95*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SGET: /* 0x60 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(96*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SGET_WIDE: /* 0x61 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(97*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SGET_OBJECT: /* 0x62 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(98*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SGET_BOOLEAN: /* 0x63 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(99*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SGET_BYTE: /* 0x64 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(100*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SGET_CHAR: /* 0x65 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(101*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SGET_SHORT: /* 0x66 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(102*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SPUT: /* 0x67 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(103*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SPUT_WIDE: /* 0x68 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(104*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SPUT_OBJECT: /* 0x69 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(105*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SPUT_BOOLEAN: /* 0x6a */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(106*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SPUT_BYTE: /* 0x6b */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(107*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SPUT_CHAR: /* 0x6c */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(108*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SPUT_SHORT: /* 0x6d */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(109*4)
+
+/* ------------------------------ */
+.L_ALT_OP_INVOKE_VIRTUAL: /* 0x6e */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(110*4)
+
+/* ------------------------------ */
+.L_ALT_OP_INVOKE_SUPER: /* 0x6f */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(111*4)
+
+/* ------------------------------ */
+.L_ALT_OP_INVOKE_DIRECT: /* 0x70 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(112*4)
+
+/* ------------------------------ */
+.L_ALT_OP_INVOKE_STATIC: /* 0x71 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(113*4)
+
+/* ------------------------------ */
+.L_ALT_OP_INVOKE_INTERFACE: /* 0x72 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(114*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_73: /* 0x73 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(115*4)
+
+/* ------------------------------ */
+.L_ALT_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(116*4)
+
+/* ------------------------------ */
+.L_ALT_OP_INVOKE_SUPER_RANGE: /* 0x75 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(117*4)
+
+/* ------------------------------ */
+.L_ALT_OP_INVOKE_DIRECT_RANGE: /* 0x76 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(118*4)
+
+/* ------------------------------ */
+.L_ALT_OP_INVOKE_STATIC_RANGE: /* 0x77 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(119*4)
+
+/* ------------------------------ */
+.L_ALT_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(120*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_79: /* 0x79 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(121*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_7A: /* 0x7a */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(122*4)
+
+/* ------------------------------ */
+.L_ALT_OP_NEG_INT: /* 0x7b */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(123*4)
+
+/* ------------------------------ */
+.L_ALT_OP_NOT_INT: /* 0x7c */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(124*4)
+
+/* ------------------------------ */
+.L_ALT_OP_NEG_LONG: /* 0x7d */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(125*4)
+
+/* ------------------------------ */
+.L_ALT_OP_NOT_LONG: /* 0x7e */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(126*4)
+
+/* ------------------------------ */
+.L_ALT_OP_NEG_FLOAT: /* 0x7f */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(127*4)
+
+/* ------------------------------ */
+.L_ALT_OP_NEG_DOUBLE: /* 0x80 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(128*4)
+
+/* ------------------------------ */
+.L_ALT_OP_INT_TO_LONG: /* 0x81 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(129*4)
+
+/* ------------------------------ */
+.L_ALT_OP_INT_TO_FLOAT: /* 0x82 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(130*4)
+
+/* ------------------------------ */
+.L_ALT_OP_INT_TO_DOUBLE: /* 0x83 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(131*4)
+
+/* ------------------------------ */
+.L_ALT_OP_LONG_TO_INT: /* 0x84 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(132*4)
+
+/* ------------------------------ */
+.L_ALT_OP_LONG_TO_FLOAT: /* 0x85 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(133*4)
+
+/* ------------------------------ */
+.L_ALT_OP_LONG_TO_DOUBLE: /* 0x86 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(134*4)
+
+/* ------------------------------ */
+.L_ALT_OP_FLOAT_TO_INT: /* 0x87 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(135*4)
+
+/* ------------------------------ */
+.L_ALT_OP_FLOAT_TO_LONG: /* 0x88 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(136*4)
+
+/* ------------------------------ */
+.L_ALT_OP_FLOAT_TO_DOUBLE: /* 0x89 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(137*4)
+
+/* ------------------------------ */
+.L_ALT_OP_DOUBLE_TO_INT: /* 0x8a */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(138*4)
+
+/* ------------------------------ */
+.L_ALT_OP_DOUBLE_TO_LONG: /* 0x8b */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(139*4)
+
+/* ------------------------------ */
+.L_ALT_OP_DOUBLE_TO_FLOAT: /* 0x8c */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(140*4)
+
+/* ------------------------------ */
+.L_ALT_OP_INT_TO_BYTE: /* 0x8d */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(141*4)
+
+/* ------------------------------ */
+.L_ALT_OP_INT_TO_CHAR: /* 0x8e */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(142*4)
+
+/* ------------------------------ */
+.L_ALT_OP_INT_TO_SHORT: /* 0x8f */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(143*4)
+
+/* ------------------------------ */
+.L_ALT_OP_ADD_INT: /* 0x90 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(144*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SUB_INT: /* 0x91 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(145*4)
+
+/* ------------------------------ */
+.L_ALT_OP_MUL_INT: /* 0x92 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(146*4)
+
+/* ------------------------------ */
+.L_ALT_OP_DIV_INT: /* 0x93 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(147*4)
+
+/* ------------------------------ */
+.L_ALT_OP_REM_INT: /* 0x94 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(148*4)
+
+/* ------------------------------ */
+.L_ALT_OP_AND_INT: /* 0x95 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(149*4)
+
+/* ------------------------------ */
+.L_ALT_OP_OR_INT: /* 0x96 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(150*4)
+
+/* ------------------------------ */
+.L_ALT_OP_XOR_INT: /* 0x97 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(151*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SHL_INT: /* 0x98 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(152*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SHR_INT: /* 0x99 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(153*4)
+
+/* ------------------------------ */
+.L_ALT_OP_USHR_INT: /* 0x9a */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(154*4)
+
+/* ------------------------------ */
+.L_ALT_OP_ADD_LONG: /* 0x9b */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(155*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SUB_LONG: /* 0x9c */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(156*4)
+
+/* ------------------------------ */
+.L_ALT_OP_MUL_LONG: /* 0x9d */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(157*4)
+
+/* ------------------------------ */
+.L_ALT_OP_DIV_LONG: /* 0x9e */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(158*4)
+
+/* ------------------------------ */
+.L_ALT_OP_REM_LONG: /* 0x9f */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(159*4)
+
+/* ------------------------------ */
+.L_ALT_OP_AND_LONG: /* 0xa0 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(160*4)
+
+/* ------------------------------ */
+.L_ALT_OP_OR_LONG: /* 0xa1 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(161*4)
+
+/* ------------------------------ */
+.L_ALT_OP_XOR_LONG: /* 0xa2 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(162*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SHL_LONG: /* 0xa3 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(163*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SHR_LONG: /* 0xa4 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(164*4)
+
+/* ------------------------------ */
+.L_ALT_OP_USHR_LONG: /* 0xa5 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(165*4)
+
+/* ------------------------------ */
+.L_ALT_OP_ADD_FLOAT: /* 0xa6 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(166*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SUB_FLOAT: /* 0xa7 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(167*4)
+
+/* ------------------------------ */
+.L_ALT_OP_MUL_FLOAT: /* 0xa8 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(168*4)
+
+/* ------------------------------ */
+.L_ALT_OP_DIV_FLOAT: /* 0xa9 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(169*4)
+
+/* ------------------------------ */
+.L_ALT_OP_REM_FLOAT: /* 0xaa */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(170*4)
+
+/* ------------------------------ */
+.L_ALT_OP_ADD_DOUBLE: /* 0xab */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(171*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SUB_DOUBLE: /* 0xac */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(172*4)
+
+/* ------------------------------ */
+.L_ALT_OP_MUL_DOUBLE: /* 0xad */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(173*4)
+
+/* ------------------------------ */
+.L_ALT_OP_DIV_DOUBLE: /* 0xae */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(174*4)
+
+/* ------------------------------ */
+.L_ALT_OP_REM_DOUBLE: /* 0xaf */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(175*4)
+
+/* ------------------------------ */
+.L_ALT_OP_ADD_INT_2ADDR: /* 0xb0 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(176*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SUB_INT_2ADDR: /* 0xb1 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(177*4)
+
+/* ------------------------------ */
+.L_ALT_OP_MUL_INT_2ADDR: /* 0xb2 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(178*4)
+
+/* ------------------------------ */
+.L_ALT_OP_DIV_INT_2ADDR: /* 0xb3 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(179*4)
+
+/* ------------------------------ */
+.L_ALT_OP_REM_INT_2ADDR: /* 0xb4 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(180*4)
+
+/* ------------------------------ */
+.L_ALT_OP_AND_INT_2ADDR: /* 0xb5 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(181*4)
+
+/* ------------------------------ */
+.L_ALT_OP_OR_INT_2ADDR: /* 0xb6 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(182*4)
+
+/* ------------------------------ */
+.L_ALT_OP_XOR_INT_2ADDR: /* 0xb7 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(183*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SHL_INT_2ADDR: /* 0xb8 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(184*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SHR_INT_2ADDR: /* 0xb9 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(185*4)
+
+/* ------------------------------ */
+.L_ALT_OP_USHR_INT_2ADDR: /* 0xba */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(186*4)
+
+/* ------------------------------ */
+.L_ALT_OP_ADD_LONG_2ADDR: /* 0xbb */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(187*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SUB_LONG_2ADDR: /* 0xbc */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(188*4)
+
+/* ------------------------------ */
+.L_ALT_OP_MUL_LONG_2ADDR: /* 0xbd */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(189*4)
+
+/* ------------------------------ */
+.L_ALT_OP_DIV_LONG_2ADDR: /* 0xbe */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(190*4)
+
+/* ------------------------------ */
+.L_ALT_OP_REM_LONG_2ADDR: /* 0xbf */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(191*4)
+
+/* ------------------------------ */
+.L_ALT_OP_AND_LONG_2ADDR: /* 0xc0 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(192*4)
+
+/* ------------------------------ */
+.L_ALT_OP_OR_LONG_2ADDR: /* 0xc1 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(193*4)
+
+/* ------------------------------ */
+.L_ALT_OP_XOR_LONG_2ADDR: /* 0xc2 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(194*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SHL_LONG_2ADDR: /* 0xc3 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(195*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SHR_LONG_2ADDR: /* 0xc4 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(196*4)
+
+/* ------------------------------ */
+.L_ALT_OP_USHR_LONG_2ADDR: /* 0xc5 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(197*4)
+
+/* ------------------------------ */
+.L_ALT_OP_ADD_FLOAT_2ADDR: /* 0xc6 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(198*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SUB_FLOAT_2ADDR: /* 0xc7 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(199*4)
+
+/* ------------------------------ */
+.L_ALT_OP_MUL_FLOAT_2ADDR: /* 0xc8 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(200*4)
+
+/* ------------------------------ */
+.L_ALT_OP_DIV_FLOAT_2ADDR: /* 0xc9 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(201*4)
+
+/* ------------------------------ */
+.L_ALT_OP_REM_FLOAT_2ADDR: /* 0xca */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(202*4)
+
+/* ------------------------------ */
+.L_ALT_OP_ADD_DOUBLE_2ADDR: /* 0xcb */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(203*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SUB_DOUBLE_2ADDR: /* 0xcc */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(204*4)
+
+/* ------------------------------ */
+.L_ALT_OP_MUL_DOUBLE_2ADDR: /* 0xcd */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(205*4)
+
+/* ------------------------------ */
+.L_ALT_OP_DIV_DOUBLE_2ADDR: /* 0xce */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(206*4)
+
+/* ------------------------------ */
+.L_ALT_OP_REM_DOUBLE_2ADDR: /* 0xcf */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(207*4)
+
+/* ------------------------------ */
+.L_ALT_OP_ADD_INT_LIT16: /* 0xd0 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(208*4)
+
+/* ------------------------------ */
+.L_ALT_OP_RSUB_INT: /* 0xd1 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(209*4)
+
+/* ------------------------------ */
+.L_ALT_OP_MUL_INT_LIT16: /* 0xd2 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(210*4)
+
+/* ------------------------------ */
+.L_ALT_OP_DIV_INT_LIT16: /* 0xd3 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(211*4)
+
+/* ------------------------------ */
+.L_ALT_OP_REM_INT_LIT16: /* 0xd4 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(212*4)
+
+/* ------------------------------ */
+.L_ALT_OP_AND_INT_LIT16: /* 0xd5 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(213*4)
+
+/* ------------------------------ */
+.L_ALT_OP_OR_INT_LIT16: /* 0xd6 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(214*4)
+
+/* ------------------------------ */
+.L_ALT_OP_XOR_INT_LIT16: /* 0xd7 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(215*4)
+
+/* ------------------------------ */
+.L_ALT_OP_ADD_INT_LIT8: /* 0xd8 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(216*4)
+
+/* ------------------------------ */
+.L_ALT_OP_RSUB_INT_LIT8: /* 0xd9 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(217*4)
+
+/* ------------------------------ */
+.L_ALT_OP_MUL_INT_LIT8: /* 0xda */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(218*4)
+
+/* ------------------------------ */
+.L_ALT_OP_DIV_INT_LIT8: /* 0xdb */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(219*4)
+
+/* ------------------------------ */
+.L_ALT_OP_REM_INT_LIT8: /* 0xdc */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(220*4)
+
+/* ------------------------------ */
+.L_ALT_OP_AND_INT_LIT8: /* 0xdd */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(221*4)
+
+/* ------------------------------ */
+.L_ALT_OP_OR_INT_LIT8: /* 0xde */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(222*4)
+
+/* ------------------------------ */
+.L_ALT_OP_XOR_INT_LIT8: /* 0xdf */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(223*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SHL_INT_LIT8: /* 0xe0 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(224*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SHR_INT_LIT8: /* 0xe1 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(225*4)
+
+/* ------------------------------ */
+.L_ALT_OP_USHR_INT_LIT8: /* 0xe2 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(226*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IGET_VOLATILE: /* 0xe3 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(227*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IPUT_VOLATILE: /* 0xe4 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(228*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SGET_VOLATILE: /* 0xe5 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(229*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SPUT_VOLATILE: /* 0xe6 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(230*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(231*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IGET_WIDE_VOLATILE: /* 0xe8 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(232*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(233*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SGET_WIDE_VOLATILE: /* 0xea */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(234*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SPUT_WIDE_VOLATILE: /* 0xeb */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(235*4)
+
+/* ------------------------------ */
+.L_ALT_OP_BREAKPOINT: /* 0xec */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(236*4)
+
+/* ------------------------------ */
+.L_ALT_OP_THROW_VERIFICATION_ERROR: /* 0xed */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(237*4)
+
+/* ------------------------------ */
+.L_ALT_OP_EXECUTE_INLINE: /* 0xee */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(238*4)
+
+/* ------------------------------ */
+.L_ALT_OP_EXECUTE_INLINE_RANGE: /* 0xef */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(239*4)
+
+/* ------------------------------ */
+.L_ALT_OP_INVOKE_OBJECT_INIT: /* 0xf0 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(240*4)
+
+/* ------------------------------ */
+.L_ALT_OP_RETURN_VOID_BARRIER: /* 0xf1 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(241*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IGET_QUICK: /* 0xf2 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(242*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IGET_WIDE_QUICK: /* 0xf3 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(243*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IGET_OBJECT_QUICK: /* 0xf4 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(244*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IPUT_QUICK: /* 0xf5 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(245*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IPUT_WIDE_QUICK: /* 0xf6 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(246*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IPUT_OBJECT_QUICK: /* 0xf7 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(247*4)
+
+/* ------------------------------ */
+.L_ALT_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(248*4)
+
+/* ------------------------------ */
+.L_ALT_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(249*4)
+
+/* ------------------------------ */
+.L_ALT_OP_INVOKE_SUPER_QUICK: /* 0xfa */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(250*4)
+
+/* ------------------------------ */
+.L_ALT_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(251*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(252*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SGET_OBJECT_VOLATILE: /* 0xfd */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(253*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(254*4)
+
+/* ------------------------------ */
+.L_ALT_OP_DISPATCH_FF: /* 0xff */
+/* File: x86/ALT_OP_DISPATCH_FF.S */
+ leal 256(rINST),%ecx
+ GOTO_NEXT_JUMBO_R %ecx
+
+/* ------------------------------ */
+.L_ALT_OP_CONST_CLASS_JUMBO: /* 0x100 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(256*4)
+
+/* ------------------------------ */
+.L_ALT_OP_CHECK_CAST_JUMBO: /* 0x101 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(257*4)
+
+/* ------------------------------ */
+.L_ALT_OP_INSTANCE_OF_JUMBO: /* 0x102 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(258*4)
+
+/* ------------------------------ */
+.L_ALT_OP_NEW_INSTANCE_JUMBO: /* 0x103 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(259*4)
+
+/* ------------------------------ */
+.L_ALT_OP_NEW_ARRAY_JUMBO: /* 0x104 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(260*4)
+
+/* ------------------------------ */
+.L_ALT_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(261*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IGET_JUMBO: /* 0x106 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(262*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IGET_WIDE_JUMBO: /* 0x107 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(263*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IGET_OBJECT_JUMBO: /* 0x108 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(264*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(265*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IGET_BYTE_JUMBO: /* 0x10a */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(266*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IGET_CHAR_JUMBO: /* 0x10b */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(267*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IGET_SHORT_JUMBO: /* 0x10c */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(268*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IPUT_JUMBO: /* 0x10d */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(269*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IPUT_WIDE_JUMBO: /* 0x10e */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(270*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IPUT_OBJECT_JUMBO: /* 0x10f */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(271*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(272*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IPUT_BYTE_JUMBO: /* 0x111 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(273*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IPUT_CHAR_JUMBO: /* 0x112 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(274*4)
+
+/* ------------------------------ */
+.L_ALT_OP_IPUT_SHORT_JUMBO: /* 0x113 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(275*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SGET_JUMBO: /* 0x114 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(276*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SGET_WIDE_JUMBO: /* 0x115 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(277*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SGET_OBJECT_JUMBO: /* 0x116 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(278*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(279*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SGET_BYTE_JUMBO: /* 0x118 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(280*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SGET_CHAR_JUMBO: /* 0x119 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(281*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SGET_SHORT_JUMBO: /* 0x11a */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(282*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SPUT_JUMBO: /* 0x11b */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(283*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SPUT_WIDE_JUMBO: /* 0x11c */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(284*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SPUT_OBJECT_JUMBO: /* 0x11d */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(285*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(286*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SPUT_BYTE_JUMBO: /* 0x11f */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(287*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SPUT_CHAR_JUMBO: /* 0x120 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(288*4)
+
+/* ------------------------------ */
+.L_ALT_OP_SPUT_SHORT_JUMBO: /* 0x121 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(289*4)
+
+/* ------------------------------ */
+.L_ALT_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(290*4)
+
+/* ------------------------------ */
+.L_ALT_OP_INVOKE_SUPER_JUMBO: /* 0x123 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(291*4)
+
+/* ------------------------------ */
+.L_ALT_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(292*4)
+
+/* ------------------------------ */
+.L_ALT_OP_INVOKE_STATIC_JUMBO: /* 0x125 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(293*4)
+
+/* ------------------------------ */
+.L_ALT_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(294*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_27FF: /* 0x127 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(295*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_28FF: /* 0x128 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(296*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_29FF: /* 0x129 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(297*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_2AFF: /* 0x12a */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(298*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_2BFF: /* 0x12b */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(299*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_2CFF: /* 0x12c */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(300*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_2DFF: /* 0x12d */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(301*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_2EFF: /* 0x12e */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(302*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_2FFF: /* 0x12f */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(303*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_30FF: /* 0x130 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(304*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_31FF: /* 0x131 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(305*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_32FF: /* 0x132 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(306*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_33FF: /* 0x133 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(307*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_34FF: /* 0x134 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(308*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_35FF: /* 0x135 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(309*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_36FF: /* 0x136 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(310*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_37FF: /* 0x137 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(311*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_38FF: /* 0x138 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(312*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_39FF: /* 0x139 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(313*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_3AFF: /* 0x13a */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(314*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_3BFF: /* 0x13b */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(315*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_3CFF: /* 0x13c */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(316*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_3DFF: /* 0x13d */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(317*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_3EFF: /* 0x13e */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(318*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_3FFF: /* 0x13f */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(319*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_40FF: /* 0x140 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(320*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_41FF: /* 0x141 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(321*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_42FF: /* 0x142 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(322*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_43FF: /* 0x143 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(323*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_44FF: /* 0x144 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(324*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_45FF: /* 0x145 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(325*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_46FF: /* 0x146 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(326*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_47FF: /* 0x147 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(327*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_48FF: /* 0x148 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(328*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_49FF: /* 0x149 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(329*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_4AFF: /* 0x14a */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(330*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_4BFF: /* 0x14b */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(331*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_4CFF: /* 0x14c */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(332*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_4DFF: /* 0x14d */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(333*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_4EFF: /* 0x14e */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(334*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_4FFF: /* 0x14f */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(335*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_50FF: /* 0x150 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(336*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_51FF: /* 0x151 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(337*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_52FF: /* 0x152 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(338*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_53FF: /* 0x153 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(339*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_54FF: /* 0x154 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(340*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_55FF: /* 0x155 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(341*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_56FF: /* 0x156 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(342*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_57FF: /* 0x157 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(343*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_58FF: /* 0x158 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(344*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_59FF: /* 0x159 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(345*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_5AFF: /* 0x15a */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(346*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_5BFF: /* 0x15b */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(347*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_5CFF: /* 0x15c */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(348*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_5DFF: /* 0x15d */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(349*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_5EFF: /* 0x15e */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(350*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_5FFF: /* 0x15f */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(351*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_60FF: /* 0x160 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(352*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_61FF: /* 0x161 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(353*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_62FF: /* 0x162 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(354*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_63FF: /* 0x163 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(355*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_64FF: /* 0x164 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(356*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_65FF: /* 0x165 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(357*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_66FF: /* 0x166 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(358*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_67FF: /* 0x167 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(359*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_68FF: /* 0x168 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(360*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_69FF: /* 0x169 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(361*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_6AFF: /* 0x16a */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(362*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_6BFF: /* 0x16b */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(363*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_6CFF: /* 0x16c */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(364*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_6DFF: /* 0x16d */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(365*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_6EFF: /* 0x16e */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(366*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_6FFF: /* 0x16f */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(367*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_70FF: /* 0x170 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(368*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_71FF: /* 0x171 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(369*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_72FF: /* 0x172 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(370*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_73FF: /* 0x173 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(371*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_74FF: /* 0x174 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(372*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_75FF: /* 0x175 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(373*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_76FF: /* 0x176 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(374*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_77FF: /* 0x177 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(375*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_78FF: /* 0x178 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(376*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_79FF: /* 0x179 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(377*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_7AFF: /* 0x17a */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(378*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_7BFF: /* 0x17b */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(379*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_7CFF: /* 0x17c */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(380*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_7DFF: /* 0x17d */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(381*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_7EFF: /* 0x17e */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(382*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_7FFF: /* 0x17f */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(383*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_80FF: /* 0x180 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(384*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_81FF: /* 0x181 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(385*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_82FF: /* 0x182 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(386*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_83FF: /* 0x183 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(387*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_84FF: /* 0x184 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(388*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_85FF: /* 0x185 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(389*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_86FF: /* 0x186 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(390*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_87FF: /* 0x187 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(391*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_88FF: /* 0x188 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(392*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_89FF: /* 0x189 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(393*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_8AFF: /* 0x18a */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(394*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_8BFF: /* 0x18b */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(395*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_8CFF: /* 0x18c */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(396*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_8DFF: /* 0x18d */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(397*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_8EFF: /* 0x18e */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(398*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_8FFF: /* 0x18f */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(399*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_90FF: /* 0x190 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(400*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_91FF: /* 0x191 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(401*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_92FF: /* 0x192 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(402*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_93FF: /* 0x193 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(403*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_94FF: /* 0x194 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(404*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_95FF: /* 0x195 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(405*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_96FF: /* 0x196 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(406*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_97FF: /* 0x197 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(407*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_98FF: /* 0x198 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(408*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_99FF: /* 0x199 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(409*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_9AFF: /* 0x19a */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(410*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_9BFF: /* 0x19b */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(411*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_9CFF: /* 0x19c */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(412*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_9DFF: /* 0x19d */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(413*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_9EFF: /* 0x19e */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(414*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_9FFF: /* 0x19f */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(415*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_A0FF: /* 0x1a0 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(416*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_A1FF: /* 0x1a1 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(417*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_A2FF: /* 0x1a2 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(418*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_A3FF: /* 0x1a3 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(419*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_A4FF: /* 0x1a4 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(420*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_A5FF: /* 0x1a5 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(421*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_A6FF: /* 0x1a6 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(422*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_A7FF: /* 0x1a7 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(423*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_A8FF: /* 0x1a8 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(424*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_A9FF: /* 0x1a9 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(425*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_AAFF: /* 0x1aa */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(426*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_ABFF: /* 0x1ab */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(427*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_ACFF: /* 0x1ac */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(428*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_ADFF: /* 0x1ad */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(429*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_AEFF: /* 0x1ae */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(430*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_AFFF: /* 0x1af */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(431*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_B0FF: /* 0x1b0 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(432*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_B1FF: /* 0x1b1 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(433*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_B2FF: /* 0x1b2 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(434*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_B3FF: /* 0x1b3 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(435*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_B4FF: /* 0x1b4 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(436*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_B5FF: /* 0x1b5 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(437*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_B6FF: /* 0x1b6 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(438*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_B7FF: /* 0x1b7 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(439*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_B8FF: /* 0x1b8 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(440*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_B9FF: /* 0x1b9 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(441*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_BAFF: /* 0x1ba */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(442*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_BBFF: /* 0x1bb */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(443*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_BCFF: /* 0x1bc */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(444*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_BDFF: /* 0x1bd */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(445*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_BEFF: /* 0x1be */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(446*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_BFFF: /* 0x1bf */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(447*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_C0FF: /* 0x1c0 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(448*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_C1FF: /* 0x1c1 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(449*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_C2FF: /* 0x1c2 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(450*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_C3FF: /* 0x1c3 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(451*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_C4FF: /* 0x1c4 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(452*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_C5FF: /* 0x1c5 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(453*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_C6FF: /* 0x1c6 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(454*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_C7FF: /* 0x1c7 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(455*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_C8FF: /* 0x1c8 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(456*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_C9FF: /* 0x1c9 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(457*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_CAFF: /* 0x1ca */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(458*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_CBFF: /* 0x1cb */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(459*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_CCFF: /* 0x1cc */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(460*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_CDFF: /* 0x1cd */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(461*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_CEFF: /* 0x1ce */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(462*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_CFFF: /* 0x1cf */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(463*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_D0FF: /* 0x1d0 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(464*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_D1FF: /* 0x1d1 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(465*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_D2FF: /* 0x1d2 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(466*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_D3FF: /* 0x1d3 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(467*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_D4FF: /* 0x1d4 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(468*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_D5FF: /* 0x1d5 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(469*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_D6FF: /* 0x1d6 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(470*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_D7FF: /* 0x1d7 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(471*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_D8FF: /* 0x1d8 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(472*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_D9FF: /* 0x1d9 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(473*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_DAFF: /* 0x1da */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(474*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_DBFF: /* 0x1db */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(475*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_DCFF: /* 0x1dc */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(476*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_DDFF: /* 0x1dd */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(477*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_DEFF: /* 0x1de */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(478*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_DFFF: /* 0x1df */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(479*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_E0FF: /* 0x1e0 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(480*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_E1FF: /* 0x1e1 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(481*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_E2FF: /* 0x1e2 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(482*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_E3FF: /* 0x1e3 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(483*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_E4FF: /* 0x1e4 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(484*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_E5FF: /* 0x1e5 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(485*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_E6FF: /* 0x1e6 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(486*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_E7FF: /* 0x1e7 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(487*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_E8FF: /* 0x1e8 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(488*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_E9FF: /* 0x1e9 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(489*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_EAFF: /* 0x1ea */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(490*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_EBFF: /* 0x1eb */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(491*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_ECFF: /* 0x1ec */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(492*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_EDFF: /* 0x1ed */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(493*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_EEFF: /* 0x1ee */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(494*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_EFFF: /* 0x1ef */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(495*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_F0FF: /* 0x1f0 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(496*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_F1FF: /* 0x1f1 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(497*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_F2FF: /* 0x1f2 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(498*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_F3FF: /* 0x1f3 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(499*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_F4FF: /* 0x1f4 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(500*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_F5FF: /* 0x1f5 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(501*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_F6FF: /* 0x1f6 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(502*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_F7FF: /* 0x1f7 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(503*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_F8FF: /* 0x1f8 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(504*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_F9FF: /* 0x1f9 */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(505*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_FAFF: /* 0x1fa */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(506*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_FBFF: /* 0x1fb */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(507*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_FCFF: /* 0x1fc */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(508*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_FDFF: /* 0x1fd */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(509*4)
+
+/* ------------------------------ */
+.L_ALT_OP_UNUSED_FEFF: /* 0x1fe */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(510*4)
+
+/* ------------------------------ */
+.L_ALT_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */
+/* File: x86/ALT_STUB.S */
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(511*4)
+
+ .size dvmAsmAltInstructionStartCode, .-dvmAsmAltInstructionStartCode
+ .global dvmAsmAltInstructionEndCode
+dvmAsmAltInstructionEndCode:
+
+ .global dvmAsmInstructionStart
+ .text
+dvmAsmInstructionStart:
+ .long .L_OP_NOP /* 0x00 */
+ .long .L_OP_MOVE /* 0x01 */
+ .long .L_OP_MOVE_FROM16 /* 0x02 */
+ .long .L_OP_MOVE_16 /* 0x03 */
+ .long .L_OP_MOVE_WIDE /* 0x04 */
+ .long .L_OP_MOVE_WIDE_FROM16 /* 0x05 */
+ .long .L_OP_MOVE_WIDE_16 /* 0x06 */
+ .long .L_OP_MOVE_OBJECT /* 0x07 */
+ .long .L_OP_MOVE_OBJECT_FROM16 /* 0x08 */
+ .long .L_OP_MOVE_OBJECT_16 /* 0x09 */
+ .long .L_OP_MOVE_RESULT /* 0x0a */
+ .long .L_OP_MOVE_RESULT_WIDE /* 0x0b */
+ .long .L_OP_MOVE_RESULT_OBJECT /* 0x0c */
+ .long .L_OP_MOVE_EXCEPTION /* 0x0d */
+ .long .L_OP_RETURN_VOID /* 0x0e */
+ .long .L_OP_RETURN /* 0x0f */
+ .long .L_OP_RETURN_WIDE /* 0x10 */
+ .long .L_OP_RETURN_OBJECT /* 0x11 */
+ .long .L_OP_CONST_4 /* 0x12 */
+ .long .L_OP_CONST_16 /* 0x13 */
+ .long .L_OP_CONST /* 0x14 */
+ .long .L_OP_CONST_HIGH16 /* 0x15 */
+ .long .L_OP_CONST_WIDE_16 /* 0x16 */
+ .long .L_OP_CONST_WIDE_32 /* 0x17 */
+ .long .L_OP_CONST_WIDE /* 0x18 */
+ .long .L_OP_CONST_WIDE_HIGH16 /* 0x19 */
+ .long .L_OP_CONST_STRING /* 0x1a */
+ .long .L_OP_CONST_STRING_JUMBO /* 0x1b */
+ .long .L_OP_CONST_CLASS /* 0x1c */
+ .long .L_OP_MONITOR_ENTER /* 0x1d */
+ .long .L_OP_MONITOR_EXIT /* 0x1e */
+ .long .L_OP_CHECK_CAST /* 0x1f */
+ .long .L_OP_INSTANCE_OF /* 0x20 */
+ .long .L_OP_ARRAY_LENGTH /* 0x21 */
+ .long .L_OP_NEW_INSTANCE /* 0x22 */
+ .long .L_OP_NEW_ARRAY /* 0x23 */
+ .long .L_OP_FILLED_NEW_ARRAY /* 0x24 */
+ .long .L_OP_FILLED_NEW_ARRAY_RANGE /* 0x25 */
+ .long .L_OP_FILL_ARRAY_DATA /* 0x26 */
+ .long .L_OP_THROW /* 0x27 */
+ .long .L_OP_GOTO /* 0x28 */
+ .long .L_OP_GOTO_16 /* 0x29 */
+ .long .L_OP_GOTO_32 /* 0x2a */
+ .long .L_OP_PACKED_SWITCH /* 0x2b */
+ .long .L_OP_SPARSE_SWITCH /* 0x2c */
+ .long .L_OP_CMPL_FLOAT /* 0x2d */
+ .long .L_OP_CMPG_FLOAT /* 0x2e */
+ .long .L_OP_CMPL_DOUBLE /* 0x2f */
+ .long .L_OP_CMPG_DOUBLE /* 0x30 */
+ .long .L_OP_CMP_LONG /* 0x31 */
+ .long .L_OP_IF_EQ /* 0x32 */
+ .long .L_OP_IF_NE /* 0x33 */
+ .long .L_OP_IF_LT /* 0x34 */
+ .long .L_OP_IF_GE /* 0x35 */
+ .long .L_OP_IF_GT /* 0x36 */
+ .long .L_OP_IF_LE /* 0x37 */
+ .long .L_OP_IF_EQZ /* 0x38 */
+ .long .L_OP_IF_NEZ /* 0x39 */
+ .long .L_OP_IF_LTZ /* 0x3a */
+ .long .L_OP_IF_GEZ /* 0x3b */
+ .long .L_OP_IF_GTZ /* 0x3c */
+ .long .L_OP_IF_LEZ /* 0x3d */
+ .long .L_OP_UNUSED_3E /* 0x3e */
+ .long .L_OP_UNUSED_3F /* 0x3f */
+ .long .L_OP_UNUSED_40 /* 0x40 */
+ .long .L_OP_UNUSED_41 /* 0x41 */
+ .long .L_OP_UNUSED_42 /* 0x42 */
+ .long .L_OP_UNUSED_43 /* 0x43 */
+ .long .L_OP_AGET /* 0x44 */
+ .long .L_OP_AGET_WIDE /* 0x45 */
+ .long .L_OP_AGET_OBJECT /* 0x46 */
+ .long .L_OP_AGET_BOOLEAN /* 0x47 */
+ .long .L_OP_AGET_BYTE /* 0x48 */
+ .long .L_OP_AGET_CHAR /* 0x49 */
+ .long .L_OP_AGET_SHORT /* 0x4a */
+ .long .L_OP_APUT /* 0x4b */
+ .long .L_OP_APUT_WIDE /* 0x4c */
+ .long .L_OP_APUT_OBJECT /* 0x4d */
+ .long .L_OP_APUT_BOOLEAN /* 0x4e */
+ .long .L_OP_APUT_BYTE /* 0x4f */
+ .long .L_OP_APUT_CHAR /* 0x50 */
+ .long .L_OP_APUT_SHORT /* 0x51 */
+ .long .L_OP_IGET /* 0x52 */
+ .long .L_OP_IGET_WIDE /* 0x53 */
+ .long .L_OP_IGET_OBJECT /* 0x54 */
+ .long .L_OP_IGET_BOOLEAN /* 0x55 */
+ .long .L_OP_IGET_BYTE /* 0x56 */
+ .long .L_OP_IGET_CHAR /* 0x57 */
+ .long .L_OP_IGET_SHORT /* 0x58 */
+ .long .L_OP_IPUT /* 0x59 */
+ .long .L_OP_IPUT_WIDE /* 0x5a */
+ .long .L_OP_IPUT_OBJECT /* 0x5b */
+ .long .L_OP_IPUT_BOOLEAN /* 0x5c */
+ .long .L_OP_IPUT_BYTE /* 0x5d */
+ .long .L_OP_IPUT_CHAR /* 0x5e */
+ .long .L_OP_IPUT_SHORT /* 0x5f */
+ .long .L_OP_SGET /* 0x60 */
+ .long .L_OP_SGET_WIDE /* 0x61 */
+ .long .L_OP_SGET_OBJECT /* 0x62 */
+ .long .L_OP_SGET_BOOLEAN /* 0x63 */
+ .long .L_OP_SGET_BYTE /* 0x64 */
+ .long .L_OP_SGET_CHAR /* 0x65 */
+ .long .L_OP_SGET_SHORT /* 0x66 */
+ .long .L_OP_SPUT /* 0x67 */
+ .long .L_OP_SPUT_WIDE /* 0x68 */
+ .long .L_OP_SPUT_OBJECT /* 0x69 */
+ .long .L_OP_SPUT_BOOLEAN /* 0x6a */
+ .long .L_OP_SPUT_BYTE /* 0x6b */
+ .long .L_OP_SPUT_CHAR /* 0x6c */
+ .long .L_OP_SPUT_SHORT /* 0x6d */
+ .long .L_OP_INVOKE_VIRTUAL /* 0x6e */
+ .long .L_OP_INVOKE_SUPER /* 0x6f */
+ .long .L_OP_INVOKE_DIRECT /* 0x70 */
+ .long .L_OP_INVOKE_STATIC /* 0x71 */
+ .long .L_OP_INVOKE_INTERFACE /* 0x72 */
+ .long .L_OP_UNUSED_73 /* 0x73 */
+ .long .L_OP_INVOKE_VIRTUAL_RANGE /* 0x74 */
+ .long .L_OP_INVOKE_SUPER_RANGE /* 0x75 */
+ .long .L_OP_INVOKE_DIRECT_RANGE /* 0x76 */
+ .long .L_OP_INVOKE_STATIC_RANGE /* 0x77 */
+ .long .L_OP_INVOKE_INTERFACE_RANGE /* 0x78 */
+ .long .L_OP_UNUSED_79 /* 0x79 */
+ .long .L_OP_UNUSED_7A /* 0x7a */
+ .long .L_OP_NEG_INT /* 0x7b */
+ .long .L_OP_NOT_INT /* 0x7c */
+ .long .L_OP_NEG_LONG /* 0x7d */
+ .long .L_OP_NOT_LONG /* 0x7e */
+ .long .L_OP_NEG_FLOAT /* 0x7f */
+ .long .L_OP_NEG_DOUBLE /* 0x80 */
+ .long .L_OP_INT_TO_LONG /* 0x81 */
+ .long .L_OP_INT_TO_FLOAT /* 0x82 */
+ .long .L_OP_INT_TO_DOUBLE /* 0x83 */
+ .long .L_OP_LONG_TO_INT /* 0x84 */
+ .long .L_OP_LONG_TO_FLOAT /* 0x85 */
+ .long .L_OP_LONG_TO_DOUBLE /* 0x86 */
+ .long .L_OP_FLOAT_TO_INT /* 0x87 */
+ .long .L_OP_FLOAT_TO_LONG /* 0x88 */
+ .long .L_OP_FLOAT_TO_DOUBLE /* 0x89 */
+ .long .L_OP_DOUBLE_TO_INT /* 0x8a */
+ .long .L_OP_DOUBLE_TO_LONG /* 0x8b */
+ .long .L_OP_DOUBLE_TO_FLOAT /* 0x8c */
+ .long .L_OP_INT_TO_BYTE /* 0x8d */
+ .long .L_OP_INT_TO_CHAR /* 0x8e */
+ .long .L_OP_INT_TO_SHORT /* 0x8f */
+ .long .L_OP_ADD_INT /* 0x90 */
+ .long .L_OP_SUB_INT /* 0x91 */
+ .long .L_OP_MUL_INT /* 0x92 */
+ .long .L_OP_DIV_INT /* 0x93 */
+ .long .L_OP_REM_INT /* 0x94 */
+ .long .L_OP_AND_INT /* 0x95 */
+ .long .L_OP_OR_INT /* 0x96 */
+ .long .L_OP_XOR_INT /* 0x97 */
+ .long .L_OP_SHL_INT /* 0x98 */
+ .long .L_OP_SHR_INT /* 0x99 */
+ .long .L_OP_USHR_INT /* 0x9a */
+ .long .L_OP_ADD_LONG /* 0x9b */
+ .long .L_OP_SUB_LONG /* 0x9c */
+ .long .L_OP_MUL_LONG /* 0x9d */
+ .long .L_OP_DIV_LONG /* 0x9e */
+ .long .L_OP_REM_LONG /* 0x9f */
+ .long .L_OP_AND_LONG /* 0xa0 */
+ .long .L_OP_OR_LONG /* 0xa1 */
+ .long .L_OP_XOR_LONG /* 0xa2 */
+ .long .L_OP_SHL_LONG /* 0xa3 */
+ .long .L_OP_SHR_LONG /* 0xa4 */
+ .long .L_OP_USHR_LONG /* 0xa5 */
+ .long .L_OP_ADD_FLOAT /* 0xa6 */
+ .long .L_OP_SUB_FLOAT /* 0xa7 */
+ .long .L_OP_MUL_FLOAT /* 0xa8 */
+ .long .L_OP_DIV_FLOAT /* 0xa9 */
+ .long .L_OP_REM_FLOAT /* 0xaa */
+ .long .L_OP_ADD_DOUBLE /* 0xab */
+ .long .L_OP_SUB_DOUBLE /* 0xac */
+ .long .L_OP_MUL_DOUBLE /* 0xad */
+ .long .L_OP_DIV_DOUBLE /* 0xae */
+ .long .L_OP_REM_DOUBLE /* 0xaf */
+ .long .L_OP_ADD_INT_2ADDR /* 0xb0 */
+ .long .L_OP_SUB_INT_2ADDR /* 0xb1 */
+ .long .L_OP_MUL_INT_2ADDR /* 0xb2 */
+ .long .L_OP_DIV_INT_2ADDR /* 0xb3 */
+ .long .L_OP_REM_INT_2ADDR /* 0xb4 */
+ .long .L_OP_AND_INT_2ADDR /* 0xb5 */
+ .long .L_OP_OR_INT_2ADDR /* 0xb6 */
+ .long .L_OP_XOR_INT_2ADDR /* 0xb7 */
+ .long .L_OP_SHL_INT_2ADDR /* 0xb8 */
+ .long .L_OP_SHR_INT_2ADDR /* 0xb9 */
+ .long .L_OP_USHR_INT_2ADDR /* 0xba */
+ .long .L_OP_ADD_LONG_2ADDR /* 0xbb */
+ .long .L_OP_SUB_LONG_2ADDR /* 0xbc */
+ .long .L_OP_MUL_LONG_2ADDR /* 0xbd */
+ .long .L_OP_DIV_LONG_2ADDR /* 0xbe */
+ .long .L_OP_REM_LONG_2ADDR /* 0xbf */
+ .long .L_OP_AND_LONG_2ADDR /* 0xc0 */
+ .long .L_OP_OR_LONG_2ADDR /* 0xc1 */
+ .long .L_OP_XOR_LONG_2ADDR /* 0xc2 */
+ .long .L_OP_SHL_LONG_2ADDR /* 0xc3 */
+ .long .L_OP_SHR_LONG_2ADDR /* 0xc4 */
+ .long .L_OP_USHR_LONG_2ADDR /* 0xc5 */
+ .long .L_OP_ADD_FLOAT_2ADDR /* 0xc6 */
+ .long .L_OP_SUB_FLOAT_2ADDR /* 0xc7 */
+ .long .L_OP_MUL_FLOAT_2ADDR /* 0xc8 */
+ .long .L_OP_DIV_FLOAT_2ADDR /* 0xc9 */
+ .long .L_OP_REM_FLOAT_2ADDR /* 0xca */
+ .long .L_OP_ADD_DOUBLE_2ADDR /* 0xcb */
+ .long .L_OP_SUB_DOUBLE_2ADDR /* 0xcc */
+ .long .L_OP_MUL_DOUBLE_2ADDR /* 0xcd */
+ .long .L_OP_DIV_DOUBLE_2ADDR /* 0xce */
+ .long .L_OP_REM_DOUBLE_2ADDR /* 0xcf */
+ .long .L_OP_ADD_INT_LIT16 /* 0xd0 */
+ .long .L_OP_RSUB_INT /* 0xd1 */
+ .long .L_OP_MUL_INT_LIT16 /* 0xd2 */
+ .long .L_OP_DIV_INT_LIT16 /* 0xd3 */
+ .long .L_OP_REM_INT_LIT16 /* 0xd4 */
+ .long .L_OP_AND_INT_LIT16 /* 0xd5 */
+ .long .L_OP_OR_INT_LIT16 /* 0xd6 */
+ .long .L_OP_XOR_INT_LIT16 /* 0xd7 */
+ .long .L_OP_ADD_INT_LIT8 /* 0xd8 */
+ .long .L_OP_RSUB_INT_LIT8 /* 0xd9 */
+ .long .L_OP_MUL_INT_LIT8 /* 0xda */
+ .long .L_OP_DIV_INT_LIT8 /* 0xdb */
+ .long .L_OP_REM_INT_LIT8 /* 0xdc */
+ .long .L_OP_AND_INT_LIT8 /* 0xdd */
+ .long .L_OP_OR_INT_LIT8 /* 0xde */
+ .long .L_OP_XOR_INT_LIT8 /* 0xdf */
+ .long .L_OP_SHL_INT_LIT8 /* 0xe0 */
+ .long .L_OP_SHR_INT_LIT8 /* 0xe1 */
+ .long .L_OP_USHR_INT_LIT8 /* 0xe2 */
+ .long .L_OP_IGET_VOLATILE /* 0xe3 */
+ .long .L_OP_IPUT_VOLATILE /* 0xe4 */
+ .long .L_OP_SGET_VOLATILE /* 0xe5 */
+ .long .L_OP_SPUT_VOLATILE /* 0xe6 */
+ .long .L_OP_IGET_OBJECT_VOLATILE /* 0xe7 */
+ .long .L_OP_IGET_WIDE_VOLATILE /* 0xe8 */
+ .long .L_OP_IPUT_WIDE_VOLATILE /* 0xe9 */
+ .long .L_OP_SGET_WIDE_VOLATILE /* 0xea */
+ .long .L_OP_SPUT_WIDE_VOLATILE /* 0xeb */
+ .long .L_OP_BREAKPOINT /* 0xec */
+ .long .L_OP_THROW_VERIFICATION_ERROR /* 0xed */
+ .long .L_OP_EXECUTE_INLINE /* 0xee */
+ .long .L_OP_EXECUTE_INLINE_RANGE /* 0xef */
+ .long .L_OP_INVOKE_OBJECT_INIT /* 0xf0 */
+ .long .L_OP_RETURN_VOID_BARRIER /* 0xf1 */
+ .long .L_OP_IGET_QUICK /* 0xf2 */
+ .long .L_OP_IGET_WIDE_QUICK /* 0xf3 */
+ .long .L_OP_IGET_OBJECT_QUICK /* 0xf4 */
+ .long .L_OP_IPUT_QUICK /* 0xf5 */
+ .long .L_OP_IPUT_WIDE_QUICK /* 0xf6 */
+ .long .L_OP_IPUT_OBJECT_QUICK /* 0xf7 */
+ .long .L_OP_INVOKE_VIRTUAL_QUICK /* 0xf8 */
+ .long .L_OP_INVOKE_VIRTUAL_QUICK_RANGE /* 0xf9 */
+ .long .L_OP_INVOKE_SUPER_QUICK /* 0xfa */
+ .long .L_OP_INVOKE_SUPER_QUICK_RANGE /* 0xfb */
+ .long .L_OP_IPUT_OBJECT_VOLATILE /* 0xfc */
+ .long .L_OP_SGET_OBJECT_VOLATILE /* 0xfd */
+ .long .L_OP_SPUT_OBJECT_VOLATILE /* 0xfe */
+ .long .L_OP_DISPATCH_FF /* 0xff */
+ .long .L_OP_CONST_CLASS_JUMBO /* 0x100 */
+ .long .L_OP_CHECK_CAST_JUMBO /* 0x101 */
+ .long .L_OP_INSTANCE_OF_JUMBO /* 0x102 */
+ .long .L_OP_NEW_INSTANCE_JUMBO /* 0x103 */
+ .long .L_OP_NEW_ARRAY_JUMBO /* 0x104 */
+ .long .L_OP_FILLED_NEW_ARRAY_JUMBO /* 0x105 */
+ .long .L_OP_IGET_JUMBO /* 0x106 */
+ .long .L_OP_IGET_WIDE_JUMBO /* 0x107 */
+ .long .L_OP_IGET_OBJECT_JUMBO /* 0x108 */
+ .long .L_OP_IGET_BOOLEAN_JUMBO /* 0x109 */
+ .long .L_OP_IGET_BYTE_JUMBO /* 0x10a */
+ .long .L_OP_IGET_CHAR_JUMBO /* 0x10b */
+ .long .L_OP_IGET_SHORT_JUMBO /* 0x10c */
+ .long .L_OP_IPUT_JUMBO /* 0x10d */
+ .long .L_OP_IPUT_WIDE_JUMBO /* 0x10e */
+ .long .L_OP_IPUT_OBJECT_JUMBO /* 0x10f */
+ .long .L_OP_IPUT_BOOLEAN_JUMBO /* 0x110 */
+ .long .L_OP_IPUT_BYTE_JUMBO /* 0x111 */
+ .long .L_OP_IPUT_CHAR_JUMBO /* 0x112 */
+ .long .L_OP_IPUT_SHORT_JUMBO /* 0x113 */
+ .long .L_OP_SGET_JUMBO /* 0x114 */
+ .long .L_OP_SGET_WIDE_JUMBO /* 0x115 */
+ .long .L_OP_SGET_OBJECT_JUMBO /* 0x116 */
+ .long .L_OP_SGET_BOOLEAN_JUMBO /* 0x117 */
+ .long .L_OP_SGET_BYTE_JUMBO /* 0x118 */
+ .long .L_OP_SGET_CHAR_JUMBO /* 0x119 */
+ .long .L_OP_SGET_SHORT_JUMBO /* 0x11a */
+ .long .L_OP_SPUT_JUMBO /* 0x11b */
+ .long .L_OP_SPUT_WIDE_JUMBO /* 0x11c */
+ .long .L_OP_SPUT_OBJECT_JUMBO /* 0x11d */
+ .long .L_OP_SPUT_BOOLEAN_JUMBO /* 0x11e */
+ .long .L_OP_SPUT_BYTE_JUMBO /* 0x11f */
+ .long .L_OP_SPUT_CHAR_JUMBO /* 0x120 */
+ .long .L_OP_SPUT_SHORT_JUMBO /* 0x121 */
+ .long .L_OP_INVOKE_VIRTUAL_JUMBO /* 0x122 */
+ .long .L_OP_INVOKE_SUPER_JUMBO /* 0x123 */
+ .long .L_OP_INVOKE_DIRECT_JUMBO /* 0x124 */
+ .long .L_OP_INVOKE_STATIC_JUMBO /* 0x125 */
+ .long .L_OP_INVOKE_INTERFACE_JUMBO /* 0x126 */
+ .long .L_OP_UNUSED_27FF /* 0x127 */
+ .long .L_OP_UNUSED_28FF /* 0x128 */
+ .long .L_OP_UNUSED_29FF /* 0x129 */
+ .long .L_OP_UNUSED_2AFF /* 0x12a */
+ .long .L_OP_UNUSED_2BFF /* 0x12b */
+ .long .L_OP_UNUSED_2CFF /* 0x12c */
+ .long .L_OP_UNUSED_2DFF /* 0x12d */
+ .long .L_OP_UNUSED_2EFF /* 0x12e */
+ .long .L_OP_UNUSED_2FFF /* 0x12f */
+ .long .L_OP_UNUSED_30FF /* 0x130 */
+ .long .L_OP_UNUSED_31FF /* 0x131 */
+ .long .L_OP_UNUSED_32FF /* 0x132 */
+ .long .L_OP_UNUSED_33FF /* 0x133 */
+ .long .L_OP_UNUSED_34FF /* 0x134 */
+ .long .L_OP_UNUSED_35FF /* 0x135 */
+ .long .L_OP_UNUSED_36FF /* 0x136 */
+ .long .L_OP_UNUSED_37FF /* 0x137 */
+ .long .L_OP_UNUSED_38FF /* 0x138 */
+ .long .L_OP_UNUSED_39FF /* 0x139 */
+ .long .L_OP_UNUSED_3AFF /* 0x13a */
+ .long .L_OP_UNUSED_3BFF /* 0x13b */
+ .long .L_OP_UNUSED_3CFF /* 0x13c */
+ .long .L_OP_UNUSED_3DFF /* 0x13d */
+ .long .L_OP_UNUSED_3EFF /* 0x13e */
+ .long .L_OP_UNUSED_3FFF /* 0x13f */
+ .long .L_OP_UNUSED_40FF /* 0x140 */
+ .long .L_OP_UNUSED_41FF /* 0x141 */
+ .long .L_OP_UNUSED_42FF /* 0x142 */
+ .long .L_OP_UNUSED_43FF /* 0x143 */
+ .long .L_OP_UNUSED_44FF /* 0x144 */
+ .long .L_OP_UNUSED_45FF /* 0x145 */
+ .long .L_OP_UNUSED_46FF /* 0x146 */
+ .long .L_OP_UNUSED_47FF /* 0x147 */
+ .long .L_OP_UNUSED_48FF /* 0x148 */
+ .long .L_OP_UNUSED_49FF /* 0x149 */
+ .long .L_OP_UNUSED_4AFF /* 0x14a */
+ .long .L_OP_UNUSED_4BFF /* 0x14b */
+ .long .L_OP_UNUSED_4CFF /* 0x14c */
+ .long .L_OP_UNUSED_4DFF /* 0x14d */
+ .long .L_OP_UNUSED_4EFF /* 0x14e */
+ .long .L_OP_UNUSED_4FFF /* 0x14f */
+ .long .L_OP_UNUSED_50FF /* 0x150 */
+ .long .L_OP_UNUSED_51FF /* 0x151 */
+ .long .L_OP_UNUSED_52FF /* 0x152 */
+ .long .L_OP_UNUSED_53FF /* 0x153 */
+ .long .L_OP_UNUSED_54FF /* 0x154 */
+ .long .L_OP_UNUSED_55FF /* 0x155 */
+ .long .L_OP_UNUSED_56FF /* 0x156 */
+ .long .L_OP_UNUSED_57FF /* 0x157 */
+ .long .L_OP_UNUSED_58FF /* 0x158 */
+ .long .L_OP_UNUSED_59FF /* 0x159 */
+ .long .L_OP_UNUSED_5AFF /* 0x15a */
+ .long .L_OP_UNUSED_5BFF /* 0x15b */
+ .long .L_OP_UNUSED_5CFF /* 0x15c */
+ .long .L_OP_UNUSED_5DFF /* 0x15d */
+ .long .L_OP_UNUSED_5EFF /* 0x15e */
+ .long .L_OP_UNUSED_5FFF /* 0x15f */
+ .long .L_OP_UNUSED_60FF /* 0x160 */
+ .long .L_OP_UNUSED_61FF /* 0x161 */
+ .long .L_OP_UNUSED_62FF /* 0x162 */
+ .long .L_OP_UNUSED_63FF /* 0x163 */
+ .long .L_OP_UNUSED_64FF /* 0x164 */
+ .long .L_OP_UNUSED_65FF /* 0x165 */
+ .long .L_OP_UNUSED_66FF /* 0x166 */
+ .long .L_OP_UNUSED_67FF /* 0x167 */
+ .long .L_OP_UNUSED_68FF /* 0x168 */
+ .long .L_OP_UNUSED_69FF /* 0x169 */
+ .long .L_OP_UNUSED_6AFF /* 0x16a */
+ .long .L_OP_UNUSED_6BFF /* 0x16b */
+ .long .L_OP_UNUSED_6CFF /* 0x16c */
+ .long .L_OP_UNUSED_6DFF /* 0x16d */
+ .long .L_OP_UNUSED_6EFF /* 0x16e */
+ .long .L_OP_UNUSED_6FFF /* 0x16f */
+ .long .L_OP_UNUSED_70FF /* 0x170 */
+ .long .L_OP_UNUSED_71FF /* 0x171 */
+ .long .L_OP_UNUSED_72FF /* 0x172 */
+ .long .L_OP_UNUSED_73FF /* 0x173 */
+ .long .L_OP_UNUSED_74FF /* 0x174 */
+ .long .L_OP_UNUSED_75FF /* 0x175 */
+ .long .L_OP_UNUSED_76FF /* 0x176 */
+ .long .L_OP_UNUSED_77FF /* 0x177 */
+ .long .L_OP_UNUSED_78FF /* 0x178 */
+ .long .L_OP_UNUSED_79FF /* 0x179 */
+ .long .L_OP_UNUSED_7AFF /* 0x17a */
+ .long .L_OP_UNUSED_7BFF /* 0x17b */
+ .long .L_OP_UNUSED_7CFF /* 0x17c */
+ .long .L_OP_UNUSED_7DFF /* 0x17d */
+ .long .L_OP_UNUSED_7EFF /* 0x17e */
+ .long .L_OP_UNUSED_7FFF /* 0x17f */
+ .long .L_OP_UNUSED_80FF /* 0x180 */
+ .long .L_OP_UNUSED_81FF /* 0x181 */
+ .long .L_OP_UNUSED_82FF /* 0x182 */
+ .long .L_OP_UNUSED_83FF /* 0x183 */
+ .long .L_OP_UNUSED_84FF /* 0x184 */
+ .long .L_OP_UNUSED_85FF /* 0x185 */
+ .long .L_OP_UNUSED_86FF /* 0x186 */
+ .long .L_OP_UNUSED_87FF /* 0x187 */
+ .long .L_OP_UNUSED_88FF /* 0x188 */
+ .long .L_OP_UNUSED_89FF /* 0x189 */
+ .long .L_OP_UNUSED_8AFF /* 0x18a */
+ .long .L_OP_UNUSED_8BFF /* 0x18b */
+ .long .L_OP_UNUSED_8CFF /* 0x18c */
+ .long .L_OP_UNUSED_8DFF /* 0x18d */
+ .long .L_OP_UNUSED_8EFF /* 0x18e */
+ .long .L_OP_UNUSED_8FFF /* 0x18f */
+ .long .L_OP_UNUSED_90FF /* 0x190 */
+ .long .L_OP_UNUSED_91FF /* 0x191 */
+ .long .L_OP_UNUSED_92FF /* 0x192 */
+ .long .L_OP_UNUSED_93FF /* 0x193 */
+ .long .L_OP_UNUSED_94FF /* 0x194 */
+ .long .L_OP_UNUSED_95FF /* 0x195 */
+ .long .L_OP_UNUSED_96FF /* 0x196 */
+ .long .L_OP_UNUSED_97FF /* 0x197 */
+ .long .L_OP_UNUSED_98FF /* 0x198 */
+ .long .L_OP_UNUSED_99FF /* 0x199 */
+ .long .L_OP_UNUSED_9AFF /* 0x19a */
+ .long .L_OP_UNUSED_9BFF /* 0x19b */
+ .long .L_OP_UNUSED_9CFF /* 0x19c */
+ .long .L_OP_UNUSED_9DFF /* 0x19d */
+ .long .L_OP_UNUSED_9EFF /* 0x19e */
+ .long .L_OP_UNUSED_9FFF /* 0x19f */
+ .long .L_OP_UNUSED_A0FF /* 0x1a0 */
+ .long .L_OP_UNUSED_A1FF /* 0x1a1 */
+ .long .L_OP_UNUSED_A2FF /* 0x1a2 */
+ .long .L_OP_UNUSED_A3FF /* 0x1a3 */
+ .long .L_OP_UNUSED_A4FF /* 0x1a4 */
+ .long .L_OP_UNUSED_A5FF /* 0x1a5 */
+ .long .L_OP_UNUSED_A6FF /* 0x1a6 */
+ .long .L_OP_UNUSED_A7FF /* 0x1a7 */
+ .long .L_OP_UNUSED_A8FF /* 0x1a8 */
+ .long .L_OP_UNUSED_A9FF /* 0x1a9 */
+ .long .L_OP_UNUSED_AAFF /* 0x1aa */
+ .long .L_OP_UNUSED_ABFF /* 0x1ab */
+ .long .L_OP_UNUSED_ACFF /* 0x1ac */
+ .long .L_OP_UNUSED_ADFF /* 0x1ad */
+ .long .L_OP_UNUSED_AEFF /* 0x1ae */
+ .long .L_OP_UNUSED_AFFF /* 0x1af */
+ .long .L_OP_UNUSED_B0FF /* 0x1b0 */
+ .long .L_OP_UNUSED_B1FF /* 0x1b1 */
+ .long .L_OP_UNUSED_B2FF /* 0x1b2 */
+ .long .L_OP_UNUSED_B3FF /* 0x1b3 */
+ .long .L_OP_UNUSED_B4FF /* 0x1b4 */
+ .long .L_OP_UNUSED_B5FF /* 0x1b5 */
+ .long .L_OP_UNUSED_B6FF /* 0x1b6 */
+ .long .L_OP_UNUSED_B7FF /* 0x1b7 */
+ .long .L_OP_UNUSED_B8FF /* 0x1b8 */
+ .long .L_OP_UNUSED_B9FF /* 0x1b9 */
+ .long .L_OP_UNUSED_BAFF /* 0x1ba */
+ .long .L_OP_UNUSED_BBFF /* 0x1bb */
+ .long .L_OP_UNUSED_BCFF /* 0x1bc */
+ .long .L_OP_UNUSED_BDFF /* 0x1bd */
+ .long .L_OP_UNUSED_BEFF /* 0x1be */
+ .long .L_OP_UNUSED_BFFF /* 0x1bf */
+ .long .L_OP_UNUSED_C0FF /* 0x1c0 */
+ .long .L_OP_UNUSED_C1FF /* 0x1c1 */
+ .long .L_OP_UNUSED_C2FF /* 0x1c2 */
+ .long .L_OP_UNUSED_C3FF /* 0x1c3 */
+ .long .L_OP_UNUSED_C4FF /* 0x1c4 */
+ .long .L_OP_UNUSED_C5FF /* 0x1c5 */
+ .long .L_OP_UNUSED_C6FF /* 0x1c6 */
+ .long .L_OP_UNUSED_C7FF /* 0x1c7 */
+ .long .L_OP_UNUSED_C8FF /* 0x1c8 */
+ .long .L_OP_UNUSED_C9FF /* 0x1c9 */
+ .long .L_OP_UNUSED_CAFF /* 0x1ca */
+ .long .L_OP_UNUSED_CBFF /* 0x1cb */
+ .long .L_OP_UNUSED_CCFF /* 0x1cc */
+ .long .L_OP_UNUSED_CDFF /* 0x1cd */
+ .long .L_OP_UNUSED_CEFF /* 0x1ce */
+ .long .L_OP_UNUSED_CFFF /* 0x1cf */
+ .long .L_OP_UNUSED_D0FF /* 0x1d0 */
+ .long .L_OP_UNUSED_D1FF /* 0x1d1 */
+ .long .L_OP_UNUSED_D2FF /* 0x1d2 */
+ .long .L_OP_UNUSED_D3FF /* 0x1d3 */
+ .long .L_OP_UNUSED_D4FF /* 0x1d4 */
+ .long .L_OP_UNUSED_D5FF /* 0x1d5 */
+ .long .L_OP_UNUSED_D6FF /* 0x1d6 */
+ .long .L_OP_UNUSED_D7FF /* 0x1d7 */
+ .long .L_OP_UNUSED_D8FF /* 0x1d8 */
+ .long .L_OP_UNUSED_D9FF /* 0x1d9 */
+ .long .L_OP_UNUSED_DAFF /* 0x1da */
+ .long .L_OP_UNUSED_DBFF /* 0x1db */
+ .long .L_OP_UNUSED_DCFF /* 0x1dc */
+ .long .L_OP_UNUSED_DDFF /* 0x1dd */
+ .long .L_OP_UNUSED_DEFF /* 0x1de */
+ .long .L_OP_UNUSED_DFFF /* 0x1df */
+ .long .L_OP_UNUSED_E0FF /* 0x1e0 */
+ .long .L_OP_UNUSED_E1FF /* 0x1e1 */
+ .long .L_OP_UNUSED_E2FF /* 0x1e2 */
+ .long .L_OP_UNUSED_E3FF /* 0x1e3 */
+ .long .L_OP_UNUSED_E4FF /* 0x1e4 */
+ .long .L_OP_UNUSED_E5FF /* 0x1e5 */
+ .long .L_OP_UNUSED_E6FF /* 0x1e6 */
+ .long .L_OP_UNUSED_E7FF /* 0x1e7 */
+ .long .L_OP_UNUSED_E8FF /* 0x1e8 */
+ .long .L_OP_UNUSED_E9FF /* 0x1e9 */
+ .long .L_OP_UNUSED_EAFF /* 0x1ea */
+ .long .L_OP_UNUSED_EBFF /* 0x1eb */
+ .long .L_OP_UNUSED_ECFF /* 0x1ec */
+ .long .L_OP_UNUSED_EDFF /* 0x1ed */
+ .long .L_OP_UNUSED_EEFF /* 0x1ee */
+ .long .L_OP_UNUSED_EFFF /* 0x1ef */
+ .long .L_OP_UNUSED_F0FF /* 0x1f0 */
+ .long .L_OP_UNUSED_F1FF /* 0x1f1 */
+ .long .L_OP_UNUSED_F2FF /* 0x1f2 */
+ .long .L_OP_UNUSED_F3FF /* 0x1f3 */
+ .long .L_OP_UNUSED_F4FF /* 0x1f4 */
+ .long .L_OP_UNUSED_F5FF /* 0x1f5 */
+ .long .L_OP_UNUSED_F6FF /* 0x1f6 */
+ .long .L_OP_UNUSED_F7FF /* 0x1f7 */
+ .long .L_OP_UNUSED_F8FF /* 0x1f8 */
+ .long .L_OP_UNUSED_F9FF /* 0x1f9 */
+ .long .L_OP_UNUSED_FAFF /* 0x1fa */
+ .long .L_OP_UNUSED_FBFF /* 0x1fb */
+ .long .L_OP_UNUSED_FCFF /* 0x1fc */
+ .long .L_OP_UNUSED_FDFF /* 0x1fd */
+ .long .L_OP_UNUSED_FEFF /* 0x1fe */
+ .long .L_OP_THROW_VERIFICATION_ERROR_JUMBO /* 0x1ff */
+
+ .global dvmAsmAltInstructionStart
+ .text
+dvmAsmAltInstructionStart:
+ .long .L_ALT_OP_NOP /* 0x00 */
+ .long .L_ALT_OP_MOVE /* 0x01 */
+ .long .L_ALT_OP_MOVE_FROM16 /* 0x02 */
+ .long .L_ALT_OP_MOVE_16 /* 0x03 */
+ .long .L_ALT_OP_MOVE_WIDE /* 0x04 */
+ .long .L_ALT_OP_MOVE_WIDE_FROM16 /* 0x05 */
+ .long .L_ALT_OP_MOVE_WIDE_16 /* 0x06 */
+ .long .L_ALT_OP_MOVE_OBJECT /* 0x07 */
+ .long .L_ALT_OP_MOVE_OBJECT_FROM16 /* 0x08 */
+ .long .L_ALT_OP_MOVE_OBJECT_16 /* 0x09 */
+ .long .L_ALT_OP_MOVE_RESULT /* 0x0a */
+ .long .L_ALT_OP_MOVE_RESULT_WIDE /* 0x0b */
+ .long .L_ALT_OP_MOVE_RESULT_OBJECT /* 0x0c */
+ .long .L_ALT_OP_MOVE_EXCEPTION /* 0x0d */
+ .long .L_ALT_OP_RETURN_VOID /* 0x0e */
+ .long .L_ALT_OP_RETURN /* 0x0f */
+ .long .L_ALT_OP_RETURN_WIDE /* 0x10 */
+ .long .L_ALT_OP_RETURN_OBJECT /* 0x11 */
+ .long .L_ALT_OP_CONST_4 /* 0x12 */
+ .long .L_ALT_OP_CONST_16 /* 0x13 */
+ .long .L_ALT_OP_CONST /* 0x14 */
+ .long .L_ALT_OP_CONST_HIGH16 /* 0x15 */
+ .long .L_ALT_OP_CONST_WIDE_16 /* 0x16 */
+ .long .L_ALT_OP_CONST_WIDE_32 /* 0x17 */
+ .long .L_ALT_OP_CONST_WIDE /* 0x18 */
+ .long .L_ALT_OP_CONST_WIDE_HIGH16 /* 0x19 */
+ .long .L_ALT_OP_CONST_STRING /* 0x1a */
+ .long .L_ALT_OP_CONST_STRING_JUMBO /* 0x1b */
+ .long .L_ALT_OP_CONST_CLASS /* 0x1c */
+ .long .L_ALT_OP_MONITOR_ENTER /* 0x1d */
+ .long .L_ALT_OP_MONITOR_EXIT /* 0x1e */
+ .long .L_ALT_OP_CHECK_CAST /* 0x1f */
+ .long .L_ALT_OP_INSTANCE_OF /* 0x20 */
+ .long .L_ALT_OP_ARRAY_LENGTH /* 0x21 */
+ .long .L_ALT_OP_NEW_INSTANCE /* 0x22 */
+ .long .L_ALT_OP_NEW_ARRAY /* 0x23 */
+ .long .L_ALT_OP_FILLED_NEW_ARRAY /* 0x24 */
+ .long .L_ALT_OP_FILLED_NEW_ARRAY_RANGE /* 0x25 */
+ .long .L_ALT_OP_FILL_ARRAY_DATA /* 0x26 */
+ .long .L_ALT_OP_THROW /* 0x27 */
+ .long .L_ALT_OP_GOTO /* 0x28 */
+ .long .L_ALT_OP_GOTO_16 /* 0x29 */
+ .long .L_ALT_OP_GOTO_32 /* 0x2a */
+ .long .L_ALT_OP_PACKED_SWITCH /* 0x2b */
+ .long .L_ALT_OP_SPARSE_SWITCH /* 0x2c */
+ .long .L_ALT_OP_CMPL_FLOAT /* 0x2d */
+ .long .L_ALT_OP_CMPG_FLOAT /* 0x2e */
+ .long .L_ALT_OP_CMPL_DOUBLE /* 0x2f */
+ .long .L_ALT_OP_CMPG_DOUBLE /* 0x30 */
+ .long .L_ALT_OP_CMP_LONG /* 0x31 */
+ .long .L_ALT_OP_IF_EQ /* 0x32 */
+ .long .L_ALT_OP_IF_NE /* 0x33 */
+ .long .L_ALT_OP_IF_LT /* 0x34 */
+ .long .L_ALT_OP_IF_GE /* 0x35 */
+ .long .L_ALT_OP_IF_GT /* 0x36 */
+ .long .L_ALT_OP_IF_LE /* 0x37 */
+ .long .L_ALT_OP_IF_EQZ /* 0x38 */
+ .long .L_ALT_OP_IF_NEZ /* 0x39 */
+ .long .L_ALT_OP_IF_LTZ /* 0x3a */
+ .long .L_ALT_OP_IF_GEZ /* 0x3b */
+ .long .L_ALT_OP_IF_GTZ /* 0x3c */
+ .long .L_ALT_OP_IF_LEZ /* 0x3d */
+ .long .L_ALT_OP_UNUSED_3E /* 0x3e */
+ .long .L_ALT_OP_UNUSED_3F /* 0x3f */
+ .long .L_ALT_OP_UNUSED_40 /* 0x40 */
+ .long .L_ALT_OP_UNUSED_41 /* 0x41 */
+ .long .L_ALT_OP_UNUSED_42 /* 0x42 */
+ .long .L_ALT_OP_UNUSED_43 /* 0x43 */
+ .long .L_ALT_OP_AGET /* 0x44 */
+ .long .L_ALT_OP_AGET_WIDE /* 0x45 */
+ .long .L_ALT_OP_AGET_OBJECT /* 0x46 */
+ .long .L_ALT_OP_AGET_BOOLEAN /* 0x47 */
+ .long .L_ALT_OP_AGET_BYTE /* 0x48 */
+ .long .L_ALT_OP_AGET_CHAR /* 0x49 */
+ .long .L_ALT_OP_AGET_SHORT /* 0x4a */
+ .long .L_ALT_OP_APUT /* 0x4b */
+ .long .L_ALT_OP_APUT_WIDE /* 0x4c */
+ .long .L_ALT_OP_APUT_OBJECT /* 0x4d */
+ .long .L_ALT_OP_APUT_BOOLEAN /* 0x4e */
+ .long .L_ALT_OP_APUT_BYTE /* 0x4f */
+ .long .L_ALT_OP_APUT_CHAR /* 0x50 */
+ .long .L_ALT_OP_APUT_SHORT /* 0x51 */
+ .long .L_ALT_OP_IGET /* 0x52 */
+ .long .L_ALT_OP_IGET_WIDE /* 0x53 */
+ .long .L_ALT_OP_IGET_OBJECT /* 0x54 */
+ .long .L_ALT_OP_IGET_BOOLEAN /* 0x55 */
+ .long .L_ALT_OP_IGET_BYTE /* 0x56 */
+ .long .L_ALT_OP_IGET_CHAR /* 0x57 */
+ .long .L_ALT_OP_IGET_SHORT /* 0x58 */
+ .long .L_ALT_OP_IPUT /* 0x59 */
+ .long .L_ALT_OP_IPUT_WIDE /* 0x5a */
+ .long .L_ALT_OP_IPUT_OBJECT /* 0x5b */
+ .long .L_ALT_OP_IPUT_BOOLEAN /* 0x5c */
+ .long .L_ALT_OP_IPUT_BYTE /* 0x5d */
+ .long .L_ALT_OP_IPUT_CHAR /* 0x5e */
+ .long .L_ALT_OP_IPUT_SHORT /* 0x5f */
+ .long .L_ALT_OP_SGET /* 0x60 */
+ .long .L_ALT_OP_SGET_WIDE /* 0x61 */
+ .long .L_ALT_OP_SGET_OBJECT /* 0x62 */
+ .long .L_ALT_OP_SGET_BOOLEAN /* 0x63 */
+ .long .L_ALT_OP_SGET_BYTE /* 0x64 */
+ .long .L_ALT_OP_SGET_CHAR /* 0x65 */
+ .long .L_ALT_OP_SGET_SHORT /* 0x66 */
+ .long .L_ALT_OP_SPUT /* 0x67 */
+ .long .L_ALT_OP_SPUT_WIDE /* 0x68 */
+ .long .L_ALT_OP_SPUT_OBJECT /* 0x69 */
+ .long .L_ALT_OP_SPUT_BOOLEAN /* 0x6a */
+ .long .L_ALT_OP_SPUT_BYTE /* 0x6b */
+ .long .L_ALT_OP_SPUT_CHAR /* 0x6c */
+ .long .L_ALT_OP_SPUT_SHORT /* 0x6d */
+ .long .L_ALT_OP_INVOKE_VIRTUAL /* 0x6e */
+ .long .L_ALT_OP_INVOKE_SUPER /* 0x6f */
+ .long .L_ALT_OP_INVOKE_DIRECT /* 0x70 */
+ .long .L_ALT_OP_INVOKE_STATIC /* 0x71 */
+ .long .L_ALT_OP_INVOKE_INTERFACE /* 0x72 */
+ .long .L_ALT_OP_UNUSED_73 /* 0x73 */
+ .long .L_ALT_OP_INVOKE_VIRTUAL_RANGE /* 0x74 */
+ .long .L_ALT_OP_INVOKE_SUPER_RANGE /* 0x75 */
+ .long .L_ALT_OP_INVOKE_DIRECT_RANGE /* 0x76 */
+ .long .L_ALT_OP_INVOKE_STATIC_RANGE /* 0x77 */
+ .long .L_ALT_OP_INVOKE_INTERFACE_RANGE /* 0x78 */
+ .long .L_ALT_OP_UNUSED_79 /* 0x79 */
+ .long .L_ALT_OP_UNUSED_7A /* 0x7a */
+ .long .L_ALT_OP_NEG_INT /* 0x7b */
+ .long .L_ALT_OP_NOT_INT /* 0x7c */
+ .long .L_ALT_OP_NEG_LONG /* 0x7d */
+ .long .L_ALT_OP_NOT_LONG /* 0x7e */
+ .long .L_ALT_OP_NEG_FLOAT /* 0x7f */
+ .long .L_ALT_OP_NEG_DOUBLE /* 0x80 */
+ .long .L_ALT_OP_INT_TO_LONG /* 0x81 */
+ .long .L_ALT_OP_INT_TO_FLOAT /* 0x82 */
+ .long .L_ALT_OP_INT_TO_DOUBLE /* 0x83 */
+ .long .L_ALT_OP_LONG_TO_INT /* 0x84 */
+ .long .L_ALT_OP_LONG_TO_FLOAT /* 0x85 */
+ .long .L_ALT_OP_LONG_TO_DOUBLE /* 0x86 */
+ .long .L_ALT_OP_FLOAT_TO_INT /* 0x87 */
+ .long .L_ALT_OP_FLOAT_TO_LONG /* 0x88 */
+ .long .L_ALT_OP_FLOAT_TO_DOUBLE /* 0x89 */
+ .long .L_ALT_OP_DOUBLE_TO_INT /* 0x8a */
+ .long .L_ALT_OP_DOUBLE_TO_LONG /* 0x8b */
+ .long .L_ALT_OP_DOUBLE_TO_FLOAT /* 0x8c */
+ .long .L_ALT_OP_INT_TO_BYTE /* 0x8d */
+ .long .L_ALT_OP_INT_TO_CHAR /* 0x8e */
+ .long .L_ALT_OP_INT_TO_SHORT /* 0x8f */
+ .long .L_ALT_OP_ADD_INT /* 0x90 */
+ .long .L_ALT_OP_SUB_INT /* 0x91 */
+ .long .L_ALT_OP_MUL_INT /* 0x92 */
+ .long .L_ALT_OP_DIV_INT /* 0x93 */
+ .long .L_ALT_OP_REM_INT /* 0x94 */
+ .long .L_ALT_OP_AND_INT /* 0x95 */
+ .long .L_ALT_OP_OR_INT /* 0x96 */
+ .long .L_ALT_OP_XOR_INT /* 0x97 */
+ .long .L_ALT_OP_SHL_INT /* 0x98 */
+ .long .L_ALT_OP_SHR_INT /* 0x99 */
+ .long .L_ALT_OP_USHR_INT /* 0x9a */
+ .long .L_ALT_OP_ADD_LONG /* 0x9b */
+ .long .L_ALT_OP_SUB_LONG /* 0x9c */
+ .long .L_ALT_OP_MUL_LONG /* 0x9d */
+ .long .L_ALT_OP_DIV_LONG /* 0x9e */
+ .long .L_ALT_OP_REM_LONG /* 0x9f */
+ .long .L_ALT_OP_AND_LONG /* 0xa0 */
+ .long .L_ALT_OP_OR_LONG /* 0xa1 */
+ .long .L_ALT_OP_XOR_LONG /* 0xa2 */
+ .long .L_ALT_OP_SHL_LONG /* 0xa3 */
+ .long .L_ALT_OP_SHR_LONG /* 0xa4 */
+ .long .L_ALT_OP_USHR_LONG /* 0xa5 */
+ .long .L_ALT_OP_ADD_FLOAT /* 0xa6 */
+ .long .L_ALT_OP_SUB_FLOAT /* 0xa7 */
+ .long .L_ALT_OP_MUL_FLOAT /* 0xa8 */
+ .long .L_ALT_OP_DIV_FLOAT /* 0xa9 */
+ .long .L_ALT_OP_REM_FLOAT /* 0xaa */
+ .long .L_ALT_OP_ADD_DOUBLE /* 0xab */
+ .long .L_ALT_OP_SUB_DOUBLE /* 0xac */
+ .long .L_ALT_OP_MUL_DOUBLE /* 0xad */
+ .long .L_ALT_OP_DIV_DOUBLE /* 0xae */
+ .long .L_ALT_OP_REM_DOUBLE /* 0xaf */
+ .long .L_ALT_OP_ADD_INT_2ADDR /* 0xb0 */
+ .long .L_ALT_OP_SUB_INT_2ADDR /* 0xb1 */
+ .long .L_ALT_OP_MUL_INT_2ADDR /* 0xb2 */
+ .long .L_ALT_OP_DIV_INT_2ADDR /* 0xb3 */
+ .long .L_ALT_OP_REM_INT_2ADDR /* 0xb4 */
+ .long .L_ALT_OP_AND_INT_2ADDR /* 0xb5 */
+ .long .L_ALT_OP_OR_INT_2ADDR /* 0xb6 */
+ .long .L_ALT_OP_XOR_INT_2ADDR /* 0xb7 */
+ .long .L_ALT_OP_SHL_INT_2ADDR /* 0xb8 */
+ .long .L_ALT_OP_SHR_INT_2ADDR /* 0xb9 */
+ .long .L_ALT_OP_USHR_INT_2ADDR /* 0xba */
+ .long .L_ALT_OP_ADD_LONG_2ADDR /* 0xbb */
+ .long .L_ALT_OP_SUB_LONG_2ADDR /* 0xbc */
+ .long .L_ALT_OP_MUL_LONG_2ADDR /* 0xbd */
+ .long .L_ALT_OP_DIV_LONG_2ADDR /* 0xbe */
+ .long .L_ALT_OP_REM_LONG_2ADDR /* 0xbf */
+ .long .L_ALT_OP_AND_LONG_2ADDR /* 0xc0 */
+ .long .L_ALT_OP_OR_LONG_2ADDR /* 0xc1 */
+ .long .L_ALT_OP_XOR_LONG_2ADDR /* 0xc2 */
+ .long .L_ALT_OP_SHL_LONG_2ADDR /* 0xc3 */
+ .long .L_ALT_OP_SHR_LONG_2ADDR /* 0xc4 */
+ .long .L_ALT_OP_USHR_LONG_2ADDR /* 0xc5 */
+ .long .L_ALT_OP_ADD_FLOAT_2ADDR /* 0xc6 */
+ .long .L_ALT_OP_SUB_FLOAT_2ADDR /* 0xc7 */
+ .long .L_ALT_OP_MUL_FLOAT_2ADDR /* 0xc8 */
+ .long .L_ALT_OP_DIV_FLOAT_2ADDR /* 0xc9 */
+ .long .L_ALT_OP_REM_FLOAT_2ADDR /* 0xca */
+ .long .L_ALT_OP_ADD_DOUBLE_2ADDR /* 0xcb */
+ .long .L_ALT_OP_SUB_DOUBLE_2ADDR /* 0xcc */
+ .long .L_ALT_OP_MUL_DOUBLE_2ADDR /* 0xcd */
+ .long .L_ALT_OP_DIV_DOUBLE_2ADDR /* 0xce */
+ .long .L_ALT_OP_REM_DOUBLE_2ADDR /* 0xcf */
+ .long .L_ALT_OP_ADD_INT_LIT16 /* 0xd0 */
+ .long .L_ALT_OP_RSUB_INT /* 0xd1 */
+ .long .L_ALT_OP_MUL_INT_LIT16 /* 0xd2 */
+ .long .L_ALT_OP_DIV_INT_LIT16 /* 0xd3 */
+ .long .L_ALT_OP_REM_INT_LIT16 /* 0xd4 */
+ .long .L_ALT_OP_AND_INT_LIT16 /* 0xd5 */
+ .long .L_ALT_OP_OR_INT_LIT16 /* 0xd6 */
+ .long .L_ALT_OP_XOR_INT_LIT16 /* 0xd7 */
+ .long .L_ALT_OP_ADD_INT_LIT8 /* 0xd8 */
+ .long .L_ALT_OP_RSUB_INT_LIT8 /* 0xd9 */
+ .long .L_ALT_OP_MUL_INT_LIT8 /* 0xda */
+ .long .L_ALT_OP_DIV_INT_LIT8 /* 0xdb */
+ .long .L_ALT_OP_REM_INT_LIT8 /* 0xdc */
+ .long .L_ALT_OP_AND_INT_LIT8 /* 0xdd */
+ .long .L_ALT_OP_OR_INT_LIT8 /* 0xde */
+ .long .L_ALT_OP_XOR_INT_LIT8 /* 0xdf */
+ .long .L_ALT_OP_SHL_INT_LIT8 /* 0xe0 */
+ .long .L_ALT_OP_SHR_INT_LIT8 /* 0xe1 */
+ .long .L_ALT_OP_USHR_INT_LIT8 /* 0xe2 */
+ .long .L_ALT_OP_IGET_VOLATILE /* 0xe3 */
+ .long .L_ALT_OP_IPUT_VOLATILE /* 0xe4 */
+ .long .L_ALT_OP_SGET_VOLATILE /* 0xe5 */
+ .long .L_ALT_OP_SPUT_VOLATILE /* 0xe6 */
+ .long .L_ALT_OP_IGET_OBJECT_VOLATILE /* 0xe7 */
+ .long .L_ALT_OP_IGET_WIDE_VOLATILE /* 0xe8 */
+ .long .L_ALT_OP_IPUT_WIDE_VOLATILE /* 0xe9 */
+ .long .L_ALT_OP_SGET_WIDE_VOLATILE /* 0xea */
+ .long .L_ALT_OP_SPUT_WIDE_VOLATILE /* 0xeb */
+ .long .L_ALT_OP_BREAKPOINT /* 0xec */
+ .long .L_ALT_OP_THROW_VERIFICATION_ERROR /* 0xed */
+ .long .L_ALT_OP_EXECUTE_INLINE /* 0xee */
+ .long .L_ALT_OP_EXECUTE_INLINE_RANGE /* 0xef */
+ .long .L_ALT_OP_INVOKE_OBJECT_INIT /* 0xf0 */
+ .long .L_ALT_OP_RETURN_VOID_BARRIER /* 0xf1 */
+ .long .L_ALT_OP_IGET_QUICK /* 0xf2 */
+ .long .L_ALT_OP_IGET_WIDE_QUICK /* 0xf3 */
+ .long .L_ALT_OP_IGET_OBJECT_QUICK /* 0xf4 */
+ .long .L_ALT_OP_IPUT_QUICK /* 0xf5 */
+ .long .L_ALT_OP_IPUT_WIDE_QUICK /* 0xf6 */
+ .long .L_ALT_OP_IPUT_OBJECT_QUICK /* 0xf7 */
+ .long .L_ALT_OP_INVOKE_VIRTUAL_QUICK /* 0xf8 */
+ .long .L_ALT_OP_INVOKE_VIRTUAL_QUICK_RANGE /* 0xf9 */
+ .long .L_ALT_OP_INVOKE_SUPER_QUICK /* 0xfa */
+ .long .L_ALT_OP_INVOKE_SUPER_QUICK_RANGE /* 0xfb */
+ .long .L_ALT_OP_IPUT_OBJECT_VOLATILE /* 0xfc */
+ .long .L_ALT_OP_SGET_OBJECT_VOLATILE /* 0xfd */
+ .long .L_ALT_OP_SPUT_OBJECT_VOLATILE /* 0xfe */
+ .long .L_ALT_OP_DISPATCH_FF /* 0xff */
+ .long .L_ALT_OP_CONST_CLASS_JUMBO /* 0x100 */
+ .long .L_ALT_OP_CHECK_CAST_JUMBO /* 0x101 */
+ .long .L_ALT_OP_INSTANCE_OF_JUMBO /* 0x102 */
+ .long .L_ALT_OP_NEW_INSTANCE_JUMBO /* 0x103 */
+ .long .L_ALT_OP_NEW_ARRAY_JUMBO /* 0x104 */
+ .long .L_ALT_OP_FILLED_NEW_ARRAY_JUMBO /* 0x105 */
+ .long .L_ALT_OP_IGET_JUMBO /* 0x106 */
+ .long .L_ALT_OP_IGET_WIDE_JUMBO /* 0x107 */
+ .long .L_ALT_OP_IGET_OBJECT_JUMBO /* 0x108 */
+ .long .L_ALT_OP_IGET_BOOLEAN_JUMBO /* 0x109 */
+ .long .L_ALT_OP_IGET_BYTE_JUMBO /* 0x10a */
+ .long .L_ALT_OP_IGET_CHAR_JUMBO /* 0x10b */
+ .long .L_ALT_OP_IGET_SHORT_JUMBO /* 0x10c */
+ .long .L_ALT_OP_IPUT_JUMBO /* 0x10d */
+ .long .L_ALT_OP_IPUT_WIDE_JUMBO /* 0x10e */
+ .long .L_ALT_OP_IPUT_OBJECT_JUMBO /* 0x10f */
+ .long .L_ALT_OP_IPUT_BOOLEAN_JUMBO /* 0x110 */
+ .long .L_ALT_OP_IPUT_BYTE_JUMBO /* 0x111 */
+ .long .L_ALT_OP_IPUT_CHAR_JUMBO /* 0x112 */
+ .long .L_ALT_OP_IPUT_SHORT_JUMBO /* 0x113 */
+ .long .L_ALT_OP_SGET_JUMBO /* 0x114 */
+ .long .L_ALT_OP_SGET_WIDE_JUMBO /* 0x115 */
+ .long .L_ALT_OP_SGET_OBJECT_JUMBO /* 0x116 */
+ .long .L_ALT_OP_SGET_BOOLEAN_JUMBO /* 0x117 */
+ .long .L_ALT_OP_SGET_BYTE_JUMBO /* 0x118 */
+ .long .L_ALT_OP_SGET_CHAR_JUMBO /* 0x119 */
+ .long .L_ALT_OP_SGET_SHORT_JUMBO /* 0x11a */
+ .long .L_ALT_OP_SPUT_JUMBO /* 0x11b */
+ .long .L_ALT_OP_SPUT_WIDE_JUMBO /* 0x11c */
+ .long .L_ALT_OP_SPUT_OBJECT_JUMBO /* 0x11d */
+ .long .L_ALT_OP_SPUT_BOOLEAN_JUMBO /* 0x11e */
+ .long .L_ALT_OP_SPUT_BYTE_JUMBO /* 0x11f */
+ .long .L_ALT_OP_SPUT_CHAR_JUMBO /* 0x120 */
+ .long .L_ALT_OP_SPUT_SHORT_JUMBO /* 0x121 */
+ .long .L_ALT_OP_INVOKE_VIRTUAL_JUMBO /* 0x122 */
+ .long .L_ALT_OP_INVOKE_SUPER_JUMBO /* 0x123 */
+ .long .L_ALT_OP_INVOKE_DIRECT_JUMBO /* 0x124 */
+ .long .L_ALT_OP_INVOKE_STATIC_JUMBO /* 0x125 */
+ .long .L_ALT_OP_INVOKE_INTERFACE_JUMBO /* 0x126 */
+ .long .L_ALT_OP_UNUSED_27FF /* 0x127 */
+ .long .L_ALT_OP_UNUSED_28FF /* 0x128 */
+ .long .L_ALT_OP_UNUSED_29FF /* 0x129 */
+ .long .L_ALT_OP_UNUSED_2AFF /* 0x12a */
+ .long .L_ALT_OP_UNUSED_2BFF /* 0x12b */
+ .long .L_ALT_OP_UNUSED_2CFF /* 0x12c */
+ .long .L_ALT_OP_UNUSED_2DFF /* 0x12d */
+ .long .L_ALT_OP_UNUSED_2EFF /* 0x12e */
+ .long .L_ALT_OP_UNUSED_2FFF /* 0x12f */
+ .long .L_ALT_OP_UNUSED_30FF /* 0x130 */
+ .long .L_ALT_OP_UNUSED_31FF /* 0x131 */
+ .long .L_ALT_OP_UNUSED_32FF /* 0x132 */
+ .long .L_ALT_OP_UNUSED_33FF /* 0x133 */
+ .long .L_ALT_OP_UNUSED_34FF /* 0x134 */
+ .long .L_ALT_OP_UNUSED_35FF /* 0x135 */
+ .long .L_ALT_OP_UNUSED_36FF /* 0x136 */
+ .long .L_ALT_OP_UNUSED_37FF /* 0x137 */
+ .long .L_ALT_OP_UNUSED_38FF /* 0x138 */
+ .long .L_ALT_OP_UNUSED_39FF /* 0x139 */
+ .long .L_ALT_OP_UNUSED_3AFF /* 0x13a */
+ .long .L_ALT_OP_UNUSED_3BFF /* 0x13b */
+ .long .L_ALT_OP_UNUSED_3CFF /* 0x13c */
+ .long .L_ALT_OP_UNUSED_3DFF /* 0x13d */
+ .long .L_ALT_OP_UNUSED_3EFF /* 0x13e */
+ .long .L_ALT_OP_UNUSED_3FFF /* 0x13f */
+ .long .L_ALT_OP_UNUSED_40FF /* 0x140 */
+ .long .L_ALT_OP_UNUSED_41FF /* 0x141 */
+ .long .L_ALT_OP_UNUSED_42FF /* 0x142 */
+ .long .L_ALT_OP_UNUSED_43FF /* 0x143 */
+ .long .L_ALT_OP_UNUSED_44FF /* 0x144 */
+ .long .L_ALT_OP_UNUSED_45FF /* 0x145 */
+ .long .L_ALT_OP_UNUSED_46FF /* 0x146 */
+ .long .L_ALT_OP_UNUSED_47FF /* 0x147 */
+ .long .L_ALT_OP_UNUSED_48FF /* 0x148 */
+ .long .L_ALT_OP_UNUSED_49FF /* 0x149 */
+ .long .L_ALT_OP_UNUSED_4AFF /* 0x14a */
+ .long .L_ALT_OP_UNUSED_4BFF /* 0x14b */
+ .long .L_ALT_OP_UNUSED_4CFF /* 0x14c */
+ .long .L_ALT_OP_UNUSED_4DFF /* 0x14d */
+ .long .L_ALT_OP_UNUSED_4EFF /* 0x14e */
+ .long .L_ALT_OP_UNUSED_4FFF /* 0x14f */
+ .long .L_ALT_OP_UNUSED_50FF /* 0x150 */
+ .long .L_ALT_OP_UNUSED_51FF /* 0x151 */
+ .long .L_ALT_OP_UNUSED_52FF /* 0x152 */
+ .long .L_ALT_OP_UNUSED_53FF /* 0x153 */
+ .long .L_ALT_OP_UNUSED_54FF /* 0x154 */
+ .long .L_ALT_OP_UNUSED_55FF /* 0x155 */
+ .long .L_ALT_OP_UNUSED_56FF /* 0x156 */
+ .long .L_ALT_OP_UNUSED_57FF /* 0x157 */
+ .long .L_ALT_OP_UNUSED_58FF /* 0x158 */
+ .long .L_ALT_OP_UNUSED_59FF /* 0x159 */
+ .long .L_ALT_OP_UNUSED_5AFF /* 0x15a */
+ .long .L_ALT_OP_UNUSED_5BFF /* 0x15b */
+ .long .L_ALT_OP_UNUSED_5CFF /* 0x15c */
+ .long .L_ALT_OP_UNUSED_5DFF /* 0x15d */
+ .long .L_ALT_OP_UNUSED_5EFF /* 0x15e */
+ .long .L_ALT_OP_UNUSED_5FFF /* 0x15f */
+ .long .L_ALT_OP_UNUSED_60FF /* 0x160 */
+ .long .L_ALT_OP_UNUSED_61FF /* 0x161 */
+ .long .L_ALT_OP_UNUSED_62FF /* 0x162 */
+ .long .L_ALT_OP_UNUSED_63FF /* 0x163 */
+ .long .L_ALT_OP_UNUSED_64FF /* 0x164 */
+ .long .L_ALT_OP_UNUSED_65FF /* 0x165 */
+ .long .L_ALT_OP_UNUSED_66FF /* 0x166 */
+ .long .L_ALT_OP_UNUSED_67FF /* 0x167 */
+ .long .L_ALT_OP_UNUSED_68FF /* 0x168 */
+ .long .L_ALT_OP_UNUSED_69FF /* 0x169 */
+ .long .L_ALT_OP_UNUSED_6AFF /* 0x16a */
+ .long .L_ALT_OP_UNUSED_6BFF /* 0x16b */
+ .long .L_ALT_OP_UNUSED_6CFF /* 0x16c */
+ .long .L_ALT_OP_UNUSED_6DFF /* 0x16d */
+ .long .L_ALT_OP_UNUSED_6EFF /* 0x16e */
+ .long .L_ALT_OP_UNUSED_6FFF /* 0x16f */
+ .long .L_ALT_OP_UNUSED_70FF /* 0x170 */
+ .long .L_ALT_OP_UNUSED_71FF /* 0x171 */
+ .long .L_ALT_OP_UNUSED_72FF /* 0x172 */
+ .long .L_ALT_OP_UNUSED_73FF /* 0x173 */
+ .long .L_ALT_OP_UNUSED_74FF /* 0x174 */
+ .long .L_ALT_OP_UNUSED_75FF /* 0x175 */
+ .long .L_ALT_OP_UNUSED_76FF /* 0x176 */
+ .long .L_ALT_OP_UNUSED_77FF /* 0x177 */
+ .long .L_ALT_OP_UNUSED_78FF /* 0x178 */
+ .long .L_ALT_OP_UNUSED_79FF /* 0x179 */
+ .long .L_ALT_OP_UNUSED_7AFF /* 0x17a */
+ .long .L_ALT_OP_UNUSED_7BFF /* 0x17b */
+ .long .L_ALT_OP_UNUSED_7CFF /* 0x17c */
+ .long .L_ALT_OP_UNUSED_7DFF /* 0x17d */
+ .long .L_ALT_OP_UNUSED_7EFF /* 0x17e */
+ .long .L_ALT_OP_UNUSED_7FFF /* 0x17f */
+ .long .L_ALT_OP_UNUSED_80FF /* 0x180 */
+ .long .L_ALT_OP_UNUSED_81FF /* 0x181 */
+ .long .L_ALT_OP_UNUSED_82FF /* 0x182 */
+ .long .L_ALT_OP_UNUSED_83FF /* 0x183 */
+ .long .L_ALT_OP_UNUSED_84FF /* 0x184 */
+ .long .L_ALT_OP_UNUSED_85FF /* 0x185 */
+ .long .L_ALT_OP_UNUSED_86FF /* 0x186 */
+ .long .L_ALT_OP_UNUSED_87FF /* 0x187 */
+ .long .L_ALT_OP_UNUSED_88FF /* 0x188 */
+ .long .L_ALT_OP_UNUSED_89FF /* 0x189 */
+ .long .L_ALT_OP_UNUSED_8AFF /* 0x18a */
+ .long .L_ALT_OP_UNUSED_8BFF /* 0x18b */
+ .long .L_ALT_OP_UNUSED_8CFF /* 0x18c */
+ .long .L_ALT_OP_UNUSED_8DFF /* 0x18d */
+ .long .L_ALT_OP_UNUSED_8EFF /* 0x18e */
+ .long .L_ALT_OP_UNUSED_8FFF /* 0x18f */
+ .long .L_ALT_OP_UNUSED_90FF /* 0x190 */
+ .long .L_ALT_OP_UNUSED_91FF /* 0x191 */
+ .long .L_ALT_OP_UNUSED_92FF /* 0x192 */
+ .long .L_ALT_OP_UNUSED_93FF /* 0x193 */
+ .long .L_ALT_OP_UNUSED_94FF /* 0x194 */
+ .long .L_ALT_OP_UNUSED_95FF /* 0x195 */
+ .long .L_ALT_OP_UNUSED_96FF /* 0x196 */
+ .long .L_ALT_OP_UNUSED_97FF /* 0x197 */
+ .long .L_ALT_OP_UNUSED_98FF /* 0x198 */
+ .long .L_ALT_OP_UNUSED_99FF /* 0x199 */
+ .long .L_ALT_OP_UNUSED_9AFF /* 0x19a */
+ .long .L_ALT_OP_UNUSED_9BFF /* 0x19b */
+ .long .L_ALT_OP_UNUSED_9CFF /* 0x19c */
+ .long .L_ALT_OP_UNUSED_9DFF /* 0x19d */
+ .long .L_ALT_OP_UNUSED_9EFF /* 0x19e */
+ .long .L_ALT_OP_UNUSED_9FFF /* 0x19f */
+ .long .L_ALT_OP_UNUSED_A0FF /* 0x1a0 */
+ .long .L_ALT_OP_UNUSED_A1FF /* 0x1a1 */
+ .long .L_ALT_OP_UNUSED_A2FF /* 0x1a2 */
+ .long .L_ALT_OP_UNUSED_A3FF /* 0x1a3 */
+ .long .L_ALT_OP_UNUSED_A4FF /* 0x1a4 */
+ .long .L_ALT_OP_UNUSED_A5FF /* 0x1a5 */
+ .long .L_ALT_OP_UNUSED_A6FF /* 0x1a6 */
+ .long .L_ALT_OP_UNUSED_A7FF /* 0x1a7 */
+ .long .L_ALT_OP_UNUSED_A8FF /* 0x1a8 */
+ .long .L_ALT_OP_UNUSED_A9FF /* 0x1a9 */
+ .long .L_ALT_OP_UNUSED_AAFF /* 0x1aa */
+ .long .L_ALT_OP_UNUSED_ABFF /* 0x1ab */
+ .long .L_ALT_OP_UNUSED_ACFF /* 0x1ac */
+ .long .L_ALT_OP_UNUSED_ADFF /* 0x1ad */
+ .long .L_ALT_OP_UNUSED_AEFF /* 0x1ae */
+ .long .L_ALT_OP_UNUSED_AFFF /* 0x1af */
+ .long .L_ALT_OP_UNUSED_B0FF /* 0x1b0 */
+ .long .L_ALT_OP_UNUSED_B1FF /* 0x1b1 */
+ .long .L_ALT_OP_UNUSED_B2FF /* 0x1b2 */
+ .long .L_ALT_OP_UNUSED_B3FF /* 0x1b3 */
+ .long .L_ALT_OP_UNUSED_B4FF /* 0x1b4 */
+ .long .L_ALT_OP_UNUSED_B5FF /* 0x1b5 */
+ .long .L_ALT_OP_UNUSED_B6FF /* 0x1b6 */
+ .long .L_ALT_OP_UNUSED_B7FF /* 0x1b7 */
+ .long .L_ALT_OP_UNUSED_B8FF /* 0x1b8 */
+ .long .L_ALT_OP_UNUSED_B9FF /* 0x1b9 */
+ .long .L_ALT_OP_UNUSED_BAFF /* 0x1ba */
+ .long .L_ALT_OP_UNUSED_BBFF /* 0x1bb */
+ .long .L_ALT_OP_UNUSED_BCFF /* 0x1bc */
+ .long .L_ALT_OP_UNUSED_BDFF /* 0x1bd */
+ .long .L_ALT_OP_UNUSED_BEFF /* 0x1be */
+ .long .L_ALT_OP_UNUSED_BFFF /* 0x1bf */
+ .long .L_ALT_OP_UNUSED_C0FF /* 0x1c0 */
+ .long .L_ALT_OP_UNUSED_C1FF /* 0x1c1 */
+ .long .L_ALT_OP_UNUSED_C2FF /* 0x1c2 */
+ .long .L_ALT_OP_UNUSED_C3FF /* 0x1c3 */
+ .long .L_ALT_OP_UNUSED_C4FF /* 0x1c4 */
+ .long .L_ALT_OP_UNUSED_C5FF /* 0x1c5 */
+ .long .L_ALT_OP_UNUSED_C6FF /* 0x1c6 */
+ .long .L_ALT_OP_UNUSED_C7FF /* 0x1c7 */
+ .long .L_ALT_OP_UNUSED_C8FF /* 0x1c8 */
+ .long .L_ALT_OP_UNUSED_C9FF /* 0x1c9 */
+ .long .L_ALT_OP_UNUSED_CAFF /* 0x1ca */
+ .long .L_ALT_OP_UNUSED_CBFF /* 0x1cb */
+ .long .L_ALT_OP_UNUSED_CCFF /* 0x1cc */
+ .long .L_ALT_OP_UNUSED_CDFF /* 0x1cd */
+ .long .L_ALT_OP_UNUSED_CEFF /* 0x1ce */
+ .long .L_ALT_OP_UNUSED_CFFF /* 0x1cf */
+ .long .L_ALT_OP_UNUSED_D0FF /* 0x1d0 */
+ .long .L_ALT_OP_UNUSED_D1FF /* 0x1d1 */
+ .long .L_ALT_OP_UNUSED_D2FF /* 0x1d2 */
+ .long .L_ALT_OP_UNUSED_D3FF /* 0x1d3 */
+ .long .L_ALT_OP_UNUSED_D4FF /* 0x1d4 */
+ .long .L_ALT_OP_UNUSED_D5FF /* 0x1d5 */
+ .long .L_ALT_OP_UNUSED_D6FF /* 0x1d6 */
+ .long .L_ALT_OP_UNUSED_D7FF /* 0x1d7 */
+ .long .L_ALT_OP_UNUSED_D8FF /* 0x1d8 */
+ .long .L_ALT_OP_UNUSED_D9FF /* 0x1d9 */
+ .long .L_ALT_OP_UNUSED_DAFF /* 0x1da */
+ .long .L_ALT_OP_UNUSED_DBFF /* 0x1db */
+ .long .L_ALT_OP_UNUSED_DCFF /* 0x1dc */
+ .long .L_ALT_OP_UNUSED_DDFF /* 0x1dd */
+ .long .L_ALT_OP_UNUSED_DEFF /* 0x1de */
+ .long .L_ALT_OP_UNUSED_DFFF /* 0x1df */
+ .long .L_ALT_OP_UNUSED_E0FF /* 0x1e0 */
+ .long .L_ALT_OP_UNUSED_E1FF /* 0x1e1 */
+ .long .L_ALT_OP_UNUSED_E2FF /* 0x1e2 */
+ .long .L_ALT_OP_UNUSED_E3FF /* 0x1e3 */
+ .long .L_ALT_OP_UNUSED_E4FF /* 0x1e4 */
+ .long .L_ALT_OP_UNUSED_E5FF /* 0x1e5 */
+ .long .L_ALT_OP_UNUSED_E6FF /* 0x1e6 */
+ .long .L_ALT_OP_UNUSED_E7FF /* 0x1e7 */
+ .long .L_ALT_OP_UNUSED_E8FF /* 0x1e8 */
+ .long .L_ALT_OP_UNUSED_E9FF /* 0x1e9 */
+ .long .L_ALT_OP_UNUSED_EAFF /* 0x1ea */
+ .long .L_ALT_OP_UNUSED_EBFF /* 0x1eb */
+ .long .L_ALT_OP_UNUSED_ECFF /* 0x1ec */
+ .long .L_ALT_OP_UNUSED_EDFF /* 0x1ed */
+ .long .L_ALT_OP_UNUSED_EEFF /* 0x1ee */
+ .long .L_ALT_OP_UNUSED_EFFF /* 0x1ef */
+ .long .L_ALT_OP_UNUSED_F0FF /* 0x1f0 */
+ .long .L_ALT_OP_UNUSED_F1FF /* 0x1f1 */
+ .long .L_ALT_OP_UNUSED_F2FF /* 0x1f2 */
+ .long .L_ALT_OP_UNUSED_F3FF /* 0x1f3 */
+ .long .L_ALT_OP_UNUSED_F4FF /* 0x1f4 */
+ .long .L_ALT_OP_UNUSED_F5FF /* 0x1f5 */
+ .long .L_ALT_OP_UNUSED_F6FF /* 0x1f6 */
+ .long .L_ALT_OP_UNUSED_F7FF /* 0x1f7 */
+ .long .L_ALT_OP_UNUSED_F8FF /* 0x1f8 */
+ .long .L_ALT_OP_UNUSED_F9FF /* 0x1f9 */
+ .long .L_ALT_OP_UNUSED_FAFF /* 0x1fa */
+ .long .L_ALT_OP_UNUSED_FBFF /* 0x1fb */
+ .long .L_ALT_OP_UNUSED_FCFF /* 0x1fc */
+ .long .L_ALT_OP_UNUSED_FDFF /* 0x1fd */
+ .long .L_ALT_OP_UNUSED_FEFF /* 0x1fe */
+ .long .L_ALT_OP_THROW_VERIFICATION_ERROR_JUMBO /* 0x1ff */
/* File: x86/entry.S */
/*
* Copyright (C) 2008 The Android Open Source Project
@@ -12643,6 +21267,7 @@
/* Set up "named" registers */
movl offThread_pc(%ecx),rPC
movl offThread_fp(%ecx),rFP
+ movl offThread_curHandlerTable(%ecx),rIBASE
/* Remember %esp for future "longjmp" */
movl %esp,offThread_bailPtr(%ecx)
@@ -12711,527 +21336,6 @@
.asciz "Bad entry point %d\n"
-/*
- * FIXME: Should have the config/rebuild mechanism generate this
- * for targets that need it.
- */
-
-/* Jump table */
-dvmAsmInstructionJmpTable = .LdvmAsmInstructionJmpTable
-.LdvmAsmInstructionJmpTable:
-.long .L_OP_NOP
-.long .L_OP_MOVE
-.long .L_OP_MOVE_FROM16
-.long .L_OP_MOVE_16
-.long .L_OP_MOVE_WIDE
-.long .L_OP_MOVE_WIDE_FROM16
-.long .L_OP_MOVE_WIDE_16
-.long .L_OP_MOVE_OBJECT
-.long .L_OP_MOVE_OBJECT_FROM16
-.long .L_OP_MOVE_OBJECT_16
-.long .L_OP_MOVE_RESULT
-.long .L_OP_MOVE_RESULT_WIDE
-.long .L_OP_MOVE_RESULT_OBJECT
-.long .L_OP_MOVE_EXCEPTION
-.long .L_OP_RETURN_VOID
-.long .L_OP_RETURN
-.long .L_OP_RETURN_WIDE
-.long .L_OP_RETURN_OBJECT
-.long .L_OP_CONST_4
-.long .L_OP_CONST_16
-.long .L_OP_CONST
-.long .L_OP_CONST_HIGH16
-.long .L_OP_CONST_WIDE_16
-.long .L_OP_CONST_WIDE_32
-.long .L_OP_CONST_WIDE
-.long .L_OP_CONST_WIDE_HIGH16
-.long .L_OP_CONST_STRING
-.long .L_OP_CONST_STRING_JUMBO
-.long .L_OP_CONST_CLASS
-.long .L_OP_MONITOR_ENTER
-.long .L_OP_MONITOR_EXIT
-.long .L_OP_CHECK_CAST
-.long .L_OP_INSTANCE_OF
-.long .L_OP_ARRAY_LENGTH
-.long .L_OP_NEW_INSTANCE
-.long .L_OP_NEW_ARRAY
-.long .L_OP_FILLED_NEW_ARRAY
-.long .L_OP_FILLED_NEW_ARRAY_RANGE
-.long .L_OP_FILL_ARRAY_DATA
-.long .L_OP_THROW
-.long .L_OP_GOTO
-.long .L_OP_GOTO_16
-.long .L_OP_GOTO_32
-.long .L_OP_PACKED_SWITCH
-.long .L_OP_SPARSE_SWITCH
-.long .L_OP_CMPL_FLOAT
-.long .L_OP_CMPG_FLOAT
-.long .L_OP_CMPL_DOUBLE
-.long .L_OP_CMPG_DOUBLE
-.long .L_OP_CMP_LONG
-.long .L_OP_IF_EQ
-.long .L_OP_IF_NE
-.long .L_OP_IF_LT
-.long .L_OP_IF_GE
-.long .L_OP_IF_GT
-.long .L_OP_IF_LE
-.long .L_OP_IF_EQZ
-.long .L_OP_IF_NEZ
-.long .L_OP_IF_LTZ
-.long .L_OP_IF_GEZ
-.long .L_OP_IF_GTZ
-.long .L_OP_IF_LEZ
-.long .L_OP_UNUSED_3E
-.long .L_OP_UNUSED_3F
-.long .L_OP_UNUSED_40
-.long .L_OP_UNUSED_41
-.long .L_OP_UNUSED_42
-.long .L_OP_UNUSED_43
-.long .L_OP_AGET
-.long .L_OP_AGET_WIDE
-.long .L_OP_AGET_OBJECT
-.long .L_OP_AGET_BOOLEAN
-.long .L_OP_AGET_BYTE
-.long .L_OP_AGET_CHAR
-.long .L_OP_AGET_SHORT
-.long .L_OP_APUT
-.long .L_OP_APUT_WIDE
-.long .L_OP_APUT_OBJECT
-.long .L_OP_APUT_BOOLEAN
-.long .L_OP_APUT_BYTE
-.long .L_OP_APUT_CHAR
-.long .L_OP_APUT_SHORT
-.long .L_OP_IGET
-.long .L_OP_IGET_WIDE
-.long .L_OP_IGET_OBJECT
-.long .L_OP_IGET_BOOLEAN
-.long .L_OP_IGET_BYTE
-.long .L_OP_IGET_CHAR
-.long .L_OP_IGET_SHORT
-.long .L_OP_IPUT
-.long .L_OP_IPUT_WIDE
-.long .L_OP_IPUT_OBJECT
-.long .L_OP_IPUT_BOOLEAN
-.long .L_OP_IPUT_BYTE
-.long .L_OP_IPUT_CHAR
-.long .L_OP_IPUT_SHORT
-.long .L_OP_SGET
-.long .L_OP_SGET_WIDE
-.long .L_OP_SGET_OBJECT
-.long .L_OP_SGET_BOOLEAN
-.long .L_OP_SGET_BYTE
-.long .L_OP_SGET_CHAR
-.long .L_OP_SGET_SHORT
-.long .L_OP_SPUT
-.long .L_OP_SPUT_WIDE
-.long .L_OP_SPUT_OBJECT
-.long .L_OP_SPUT_BOOLEAN
-.long .L_OP_SPUT_BYTE
-.long .L_OP_SPUT_CHAR
-.long .L_OP_SPUT_SHORT
-.long .L_OP_INVOKE_VIRTUAL
-.long .L_OP_INVOKE_SUPER
-.long .L_OP_INVOKE_DIRECT
-.long .L_OP_INVOKE_STATIC
-.long .L_OP_INVOKE_INTERFACE
-.long .L_OP_UNUSED_73
-.long .L_OP_INVOKE_VIRTUAL_RANGE
-.long .L_OP_INVOKE_SUPER_RANGE
-.long .L_OP_INVOKE_DIRECT_RANGE
-.long .L_OP_INVOKE_STATIC_RANGE
-.long .L_OP_INVOKE_INTERFACE_RANGE
-.long .L_OP_UNUSED_79
-.long .L_OP_UNUSED_7A
-.long .L_OP_NEG_INT
-.long .L_OP_NOT_INT
-.long .L_OP_NEG_LONG
-.long .L_OP_NOT_LONG
-.long .L_OP_NEG_FLOAT
-.long .L_OP_NEG_DOUBLE
-.long .L_OP_INT_TO_LONG
-.long .L_OP_INT_TO_FLOAT
-.long .L_OP_INT_TO_DOUBLE
-.long .L_OP_LONG_TO_INT
-.long .L_OP_LONG_TO_FLOAT
-.long .L_OP_LONG_TO_DOUBLE
-.long .L_OP_FLOAT_TO_INT
-.long .L_OP_FLOAT_TO_LONG
-.long .L_OP_FLOAT_TO_DOUBLE
-.long .L_OP_DOUBLE_TO_INT
-.long .L_OP_DOUBLE_TO_LONG
-.long .L_OP_DOUBLE_TO_FLOAT
-.long .L_OP_INT_TO_BYTE
-.long .L_OP_INT_TO_CHAR
-.long .L_OP_INT_TO_SHORT
-.long .L_OP_ADD_INT
-.long .L_OP_SUB_INT
-.long .L_OP_MUL_INT
-.long .L_OP_DIV_INT
-.long .L_OP_REM_INT
-.long .L_OP_AND_INT
-.long .L_OP_OR_INT
-.long .L_OP_XOR_INT
-.long .L_OP_SHL_INT
-.long .L_OP_SHR_INT
-.long .L_OP_USHR_INT
-.long .L_OP_ADD_LONG
-.long .L_OP_SUB_LONG
-.long .L_OP_MUL_LONG
-.long .L_OP_DIV_LONG
-.long .L_OP_REM_LONG
-.long .L_OP_AND_LONG
-.long .L_OP_OR_LONG
-.long .L_OP_XOR_LONG
-.long .L_OP_SHL_LONG
-.long .L_OP_SHR_LONG
-.long .L_OP_USHR_LONG
-.long .L_OP_ADD_FLOAT
-.long .L_OP_SUB_FLOAT
-.long .L_OP_MUL_FLOAT
-.long .L_OP_DIV_FLOAT
-.long .L_OP_REM_FLOAT
-.long .L_OP_ADD_DOUBLE
-.long .L_OP_SUB_DOUBLE
-.long .L_OP_MUL_DOUBLE
-.long .L_OP_DIV_DOUBLE
-.long .L_OP_REM_DOUBLE
-.long .L_OP_ADD_INT_2ADDR
-.long .L_OP_SUB_INT_2ADDR
-.long .L_OP_MUL_INT_2ADDR
-.long .L_OP_DIV_INT_2ADDR
-.long .L_OP_REM_INT_2ADDR
-.long .L_OP_AND_INT_2ADDR
-.long .L_OP_OR_INT_2ADDR
-.long .L_OP_XOR_INT_2ADDR
-.long .L_OP_SHL_INT_2ADDR
-.long .L_OP_SHR_INT_2ADDR
-.long .L_OP_USHR_INT_2ADDR
-.long .L_OP_ADD_LONG_2ADDR
-.long .L_OP_SUB_LONG_2ADDR
-.long .L_OP_MUL_LONG_2ADDR
-.long .L_OP_DIV_LONG_2ADDR
-.long .L_OP_REM_LONG_2ADDR
-.long .L_OP_AND_LONG_2ADDR
-.long .L_OP_OR_LONG_2ADDR
-.long .L_OP_XOR_LONG_2ADDR
-.long .L_OP_SHL_LONG_2ADDR
-.long .L_OP_SHR_LONG_2ADDR
-.long .L_OP_USHR_LONG_2ADDR
-.long .L_OP_ADD_FLOAT_2ADDR
-.long .L_OP_SUB_FLOAT_2ADDR
-.long .L_OP_MUL_FLOAT_2ADDR
-.long .L_OP_DIV_FLOAT_2ADDR
-.long .L_OP_REM_FLOAT_2ADDR
-.long .L_OP_ADD_DOUBLE_2ADDR
-.long .L_OP_SUB_DOUBLE_2ADDR
-.long .L_OP_MUL_DOUBLE_2ADDR
-.long .L_OP_DIV_DOUBLE_2ADDR
-.long .L_OP_REM_DOUBLE_2ADDR
-.long .L_OP_ADD_INT_LIT16
-.long .L_OP_RSUB_INT
-.long .L_OP_MUL_INT_LIT16
-.long .L_OP_DIV_INT_LIT16
-.long .L_OP_REM_INT_LIT16
-.long .L_OP_AND_INT_LIT16
-.long .L_OP_OR_INT_LIT16
-.long .L_OP_XOR_INT_LIT16
-.long .L_OP_ADD_INT_LIT8
-.long .L_OP_RSUB_INT_LIT8
-.long .L_OP_MUL_INT_LIT8
-.long .L_OP_DIV_INT_LIT8
-.long .L_OP_REM_INT_LIT8
-.long .L_OP_AND_INT_LIT8
-.long .L_OP_OR_INT_LIT8
-.long .L_OP_XOR_INT_LIT8
-.long .L_OP_SHL_INT_LIT8
-.long .L_OP_SHR_INT_LIT8
-.long .L_OP_USHR_INT_LIT8
-.long .L_OP_IGET_VOLATILE
-.long .L_OP_IPUT_VOLATILE
-.long .L_OP_SGET_VOLATILE
-.long .L_OP_SPUT_VOLATILE
-.long .L_OP_IGET_OBJECT_VOLATILE
-.long .L_OP_IGET_WIDE_VOLATILE
-.long .L_OP_IPUT_WIDE_VOLATILE
-.long .L_OP_SGET_WIDE_VOLATILE
-.long .L_OP_SPUT_WIDE_VOLATILE
-.long .L_OP_BREAKPOINT
-.long .L_OP_THROW_VERIFICATION_ERROR
-.long .L_OP_EXECUTE_INLINE
-.long .L_OP_EXECUTE_INLINE_RANGE
-.long .L_OP_INVOKE_OBJECT_INIT
-.long .L_OP_RETURN_VOID_BARRIER
-.long .L_OP_IGET_QUICK
-.long .L_OP_IGET_WIDE_QUICK
-.long .L_OP_IGET_OBJECT_QUICK
-.long .L_OP_IPUT_QUICK
-.long .L_OP_IPUT_WIDE_QUICK
-.long .L_OP_IPUT_OBJECT_QUICK
-.long .L_OP_INVOKE_VIRTUAL_QUICK
-.long .L_OP_INVOKE_VIRTUAL_QUICK_RANGE
-.long .L_OP_INVOKE_SUPER_QUICK
-.long .L_OP_INVOKE_SUPER_QUICK_RANGE
-.long .L_OP_IPUT_OBJECT_VOLATILE
-.long .L_OP_SGET_OBJECT_VOLATILE
-.long .L_OP_SPUT_OBJECT_VOLATILE
-.long .L_OP_DISPATCH_FF
-.long .L_OP_CONST_CLASS_JUMBO
-.long .L_OP_CHECK_CAST_JUMBO
-.long .L_OP_INSTANCE_OF_JUMBO
-.long .L_OP_NEW_INSTANCE_JUMBO
-.long .L_OP_NEW_ARRAY_JUMBO
-.long .L_OP_FILLED_NEW_ARRAY_JUMBO
-.long .L_OP_IGET_JUMBO
-.long .L_OP_IGET_WIDE_JUMBO
-.long .L_OP_IGET_OBJECT_JUMBO
-.long .L_OP_IGET_BOOLEAN_JUMBO
-.long .L_OP_IGET_BYTE_JUMBO
-.long .L_OP_IGET_CHAR_JUMBO
-.long .L_OP_IGET_SHORT_JUMBO
-.long .L_OP_IPUT_JUMBO
-.long .L_OP_IPUT_WIDE_JUMBO
-.long .L_OP_IPUT_OBJECT_JUMBO
-.long .L_OP_IPUT_BOOLEAN_JUMBO
-.long .L_OP_IPUT_BYTE_JUMBO
-.long .L_OP_IPUT_CHAR_JUMBO
-.long .L_OP_IPUT_SHORT_JUMBO
-.long .L_OP_SGET_JUMBO
-.long .L_OP_SGET_WIDE_JUMBO
-.long .L_OP_SGET_OBJECT_JUMBO
-.long .L_OP_SGET_BOOLEAN_JUMBO
-.long .L_OP_SGET_BYTE_JUMBO
-.long .L_OP_SGET_CHAR_JUMBO
-.long .L_OP_SGET_SHORT_JUMBO
-.long .L_OP_SPUT_JUMBO
-.long .L_OP_SPUT_WIDE_JUMBO
-.long .L_OP_SPUT_OBJECT_JUMBO
-.long .L_OP_SPUT_BOOLEAN_JUMBO
-.long .L_OP_SPUT_BYTE_JUMBO
-.long .L_OP_SPUT_CHAR_JUMBO
-.long .L_OP_SPUT_SHORT_JUMBO
-.long .L_OP_INVOKE_VIRTUAL_JUMBO
-.long .L_OP_INVOKE_SUPER_JUMBO
-.long .L_OP_INVOKE_DIRECT_JUMBO
-.long .L_OP_INVOKE_STATIC_JUMBO
-.long .L_OP_INVOKE_INTERFACE_JUMBO
-.long .L_OP_UNUSED_27FF
-.long .L_OP_UNUSED_28FF
-.long .L_OP_UNUSED_29FF
-.long .L_OP_UNUSED_2AFF
-.long .L_OP_UNUSED_2BFF
-.long .L_OP_UNUSED_2CFF
-.long .L_OP_UNUSED_2DFF
-.long .L_OP_UNUSED_2EFF
-.long .L_OP_UNUSED_2FFF
-.long .L_OP_UNUSED_30FF
-.long .L_OP_UNUSED_31FF
-.long .L_OP_UNUSED_32FF
-.long .L_OP_UNUSED_33FF
-.long .L_OP_UNUSED_34FF
-.long .L_OP_UNUSED_35FF
-.long .L_OP_UNUSED_36FF
-.long .L_OP_UNUSED_37FF
-.long .L_OP_UNUSED_38FF
-.long .L_OP_UNUSED_39FF
-.long .L_OP_UNUSED_3AFF
-.long .L_OP_UNUSED_3BFF
-.long .L_OP_UNUSED_3CFF
-.long .L_OP_UNUSED_3DFF
-.long .L_OP_UNUSED_3EFF
-.long .L_OP_UNUSED_3FFF
-.long .L_OP_UNUSED_40FF
-.long .L_OP_UNUSED_41FF
-.long .L_OP_UNUSED_42FF
-.long .L_OP_UNUSED_43FF
-.long .L_OP_UNUSED_44FF
-.long .L_OP_UNUSED_45FF
-.long .L_OP_UNUSED_46FF
-.long .L_OP_UNUSED_47FF
-.long .L_OP_UNUSED_48FF
-.long .L_OP_UNUSED_49FF
-.long .L_OP_UNUSED_4AFF
-.long .L_OP_UNUSED_4BFF
-.long .L_OP_UNUSED_4CFF
-.long .L_OP_UNUSED_4DFF
-.long .L_OP_UNUSED_4EFF
-.long .L_OP_UNUSED_4FFF
-.long .L_OP_UNUSED_50FF
-.long .L_OP_UNUSED_51FF
-.long .L_OP_UNUSED_52FF
-.long .L_OP_UNUSED_53FF
-.long .L_OP_UNUSED_54FF
-.long .L_OP_UNUSED_55FF
-.long .L_OP_UNUSED_56FF
-.long .L_OP_UNUSED_57FF
-.long .L_OP_UNUSED_58FF
-.long .L_OP_UNUSED_59FF
-.long .L_OP_UNUSED_5AFF
-.long .L_OP_UNUSED_5BFF
-.long .L_OP_UNUSED_5CFF
-.long .L_OP_UNUSED_5DFF
-.long .L_OP_UNUSED_5EFF
-.long .L_OP_UNUSED_5FFF
-.long .L_OP_UNUSED_60FF
-.long .L_OP_UNUSED_61FF
-.long .L_OP_UNUSED_62FF
-.long .L_OP_UNUSED_63FF
-.long .L_OP_UNUSED_64FF
-.long .L_OP_UNUSED_65FF
-.long .L_OP_UNUSED_66FF
-.long .L_OP_UNUSED_67FF
-.long .L_OP_UNUSED_68FF
-.long .L_OP_UNUSED_69FF
-.long .L_OP_UNUSED_6AFF
-.long .L_OP_UNUSED_6BFF
-.long .L_OP_UNUSED_6CFF
-.long .L_OP_UNUSED_6DFF
-.long .L_OP_UNUSED_6EFF
-.long .L_OP_UNUSED_6FFF
-.long .L_OP_UNUSED_70FF
-.long .L_OP_UNUSED_71FF
-.long .L_OP_UNUSED_72FF
-.long .L_OP_UNUSED_73FF
-.long .L_OP_UNUSED_74FF
-.long .L_OP_UNUSED_75FF
-.long .L_OP_UNUSED_76FF
-.long .L_OP_UNUSED_77FF
-.long .L_OP_UNUSED_78FF
-.long .L_OP_UNUSED_79FF
-.long .L_OP_UNUSED_7AFF
-.long .L_OP_UNUSED_7BFF
-.long .L_OP_UNUSED_7CFF
-.long .L_OP_UNUSED_7DFF
-.long .L_OP_UNUSED_7EFF
-.long .L_OP_UNUSED_7FFF
-.long .L_OP_UNUSED_80FF
-.long .L_OP_UNUSED_81FF
-.long .L_OP_UNUSED_82FF
-.long .L_OP_UNUSED_83FF
-.long .L_OP_UNUSED_84FF
-.long .L_OP_UNUSED_85FF
-.long .L_OP_UNUSED_86FF
-.long .L_OP_UNUSED_87FF
-.long .L_OP_UNUSED_88FF
-.long .L_OP_UNUSED_89FF
-.long .L_OP_UNUSED_8AFF
-.long .L_OP_UNUSED_8BFF
-.long .L_OP_UNUSED_8CFF
-.long .L_OP_UNUSED_8DFF
-.long .L_OP_UNUSED_8EFF
-.long .L_OP_UNUSED_8FFF
-.long .L_OP_UNUSED_90FF
-.long .L_OP_UNUSED_91FF
-.long .L_OP_UNUSED_92FF
-.long .L_OP_UNUSED_93FF
-.long .L_OP_UNUSED_94FF
-.long .L_OP_UNUSED_95FF
-.long .L_OP_UNUSED_96FF
-.long .L_OP_UNUSED_97FF
-.long .L_OP_UNUSED_98FF
-.long .L_OP_UNUSED_99FF
-.long .L_OP_UNUSED_9AFF
-.long .L_OP_UNUSED_9BFF
-.long .L_OP_UNUSED_9CFF
-.long .L_OP_UNUSED_9DFF
-.long .L_OP_UNUSED_9EFF
-.long .L_OP_UNUSED_9FFF
-.long .L_OP_UNUSED_A0FF
-.long .L_OP_UNUSED_A1FF
-.long .L_OP_UNUSED_A2FF
-.long .L_OP_UNUSED_A3FF
-.long .L_OP_UNUSED_A4FF
-.long .L_OP_UNUSED_A5FF
-.long .L_OP_UNUSED_A6FF
-.long .L_OP_UNUSED_A7FF
-.long .L_OP_UNUSED_A8FF
-.long .L_OP_UNUSED_A9FF
-.long .L_OP_UNUSED_AAFF
-.long .L_OP_UNUSED_ABFF
-.long .L_OP_UNUSED_ACFF
-.long .L_OP_UNUSED_ADFF
-.long .L_OP_UNUSED_AEFF
-.long .L_OP_UNUSED_AFFF
-.long .L_OP_UNUSED_B0FF
-.long .L_OP_UNUSED_B1FF
-.long .L_OP_UNUSED_B2FF
-.long .L_OP_UNUSED_B3FF
-.long .L_OP_UNUSED_B4FF
-.long .L_OP_UNUSED_B5FF
-.long .L_OP_UNUSED_B6FF
-.long .L_OP_UNUSED_B7FF
-.long .L_OP_UNUSED_B8FF
-.long .L_OP_UNUSED_B9FF
-.long .L_OP_UNUSED_BAFF
-.long .L_OP_UNUSED_BBFF
-.long .L_OP_UNUSED_BCFF
-.long .L_OP_UNUSED_BDFF
-.long .L_OP_UNUSED_BEFF
-.long .L_OP_UNUSED_BFFF
-.long .L_OP_UNUSED_C0FF
-.long .L_OP_UNUSED_C1FF
-.long .L_OP_UNUSED_C2FF
-.long .L_OP_UNUSED_C3FF
-.long .L_OP_UNUSED_C4FF
-.long .L_OP_UNUSED_C5FF
-.long .L_OP_UNUSED_C6FF
-.long .L_OP_UNUSED_C7FF
-.long .L_OP_UNUSED_C8FF
-.long .L_OP_UNUSED_C9FF
-.long .L_OP_UNUSED_CAFF
-.long .L_OP_UNUSED_CBFF
-.long .L_OP_UNUSED_CCFF
-.long .L_OP_UNUSED_CDFF
-.long .L_OP_UNUSED_CEFF
-.long .L_OP_UNUSED_CFFF
-.long .L_OP_UNUSED_D0FF
-.long .L_OP_UNUSED_D1FF
-.long .L_OP_UNUSED_D2FF
-.long .L_OP_UNUSED_D3FF
-.long .L_OP_UNUSED_D4FF
-.long .L_OP_UNUSED_D5FF
-.long .L_OP_UNUSED_D6FF
-.long .L_OP_UNUSED_D7FF
-.long .L_OP_UNUSED_D8FF
-.long .L_OP_UNUSED_D9FF
-.long .L_OP_UNUSED_DAFF
-.long .L_OP_UNUSED_DBFF
-.long .L_OP_UNUSED_DCFF
-.long .L_OP_UNUSED_DDFF
-.long .L_OP_UNUSED_DEFF
-.long .L_OP_UNUSED_DFFF
-.long .L_OP_UNUSED_E0FF
-.long .L_OP_UNUSED_E1FF
-.long .L_OP_UNUSED_E2FF
-.long .L_OP_UNUSED_E3FF
-.long .L_OP_UNUSED_E4FF
-.long .L_OP_UNUSED_E5FF
-.long .L_OP_UNUSED_E6FF
-.long .L_OP_UNUSED_E7FF
-.long .L_OP_UNUSED_E8FF
-.long .L_OP_UNUSED_E9FF
-.long .L_OP_UNUSED_EAFF
-.long .L_OP_UNUSED_EBFF
-.long .L_OP_UNUSED_ECFF
-.long .L_OP_UNUSED_EDFF
-.long .L_OP_UNUSED_EEFF
-.long .L_OP_UNUSED_EFFF
-.long .L_OP_UNUSED_F0FF
-.long .L_OP_UNUSED_F1FF
-.long .L_OP_UNUSED_F2FF
-.long .L_OP_UNUSED_F3FF
-.long .L_OP_UNUSED_F4FF
-.long .L_OP_UNUSED_F5FF
-.long .L_OP_UNUSED_F6FF
-.long .L_OP_UNUSED_F7FF
-.long .L_OP_UNUSED_F8FF
-.long .L_OP_UNUSED_F9FF
-.long .L_OP_UNUSED_FAFF
-.long .L_OP_UNUSED_FBFF
-.long .L_OP_UNUSED_FCFF
-.long .L_OP_UNUSED_FDFF
-.long .L_OP_UNUSED_FEFF
-.long .L_OP_THROW_VERIFICATION_ERROR_JUMBO
-
/* File: x86/footer.S */
/*
* Copyright (C) 2008 The Android Open Source Project
@@ -13274,8 +21378,10 @@
movl rPC, OUT_ARG0(%esp)
call dvmBumpPunt
#endif
- FETCH_INST_R %edx
- GOTO_NEXT_R %edx
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx),rIBASE
+ FETCH_INST_R %ecx
+ GOTO_NEXT_R %ecx
.global dvmJitToInterpSingleStep
/*
@@ -13315,8 +21421,10 @@
call *%eax # exec translation if we've got one
# won't return
1:
- FETCH_INST_R %edx
- GOTO_NEXT_R %edx
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx),rIBASE
+ FETCH_INST_R %ecx
+ GOTO_NEXT_R %ecx
/*
* Return from the translation cache and immediately request a
@@ -13342,8 +21450,10 @@
GET_JIT_PROF_TABLE %ecx %eax
cmpl $0, %eax # JIT enabled?
jnz 2f # Request one if so
- FETCH_INST_R %edx # Continue interpreting if not
- GOTO_NEXT_R %edx
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx),rIBASE
+ FETCH_INST_R %ecx # Continue interpreting if not
+ GOTO_NEXT_R %ecx
2:
movl $kJitTSelectRequestHot,rINST # ask for trace select
jmp common_selectTrace
@@ -13393,9 +21503,10 @@
movl rSELF,%ecx
call common_periodicChecks # rPC and ecx/rSELF preserved
#if defined(WITH_JIT)
- GET_JIT_PROF_TABLE %ecx %edx
+ GET_JIT_PROF_TABLE %ecx rIBASE
ADVANCE_PC_INDEXED rINST
- cmpl $0,%edx
+ cmpl $0,rIBASE
+ movl offThread_curHandlerTable(%ecx),rIBASE
FETCH_INST
jz 1f # Profiling off - continue
.global updateProfile
@@ -13438,6 +21549,7 @@
movl $1,rINST
jmp common_gotoBail
#else
+ movl offThread_curHandlerTable(%ecx),rIBASE
ADVANCE_PC_INDEXED rINST
FETCH_INST
GOTO_NEXT
@@ -13451,6 +21563,7 @@
* On entry:
* eax = Method* methodToCall
* rINSTw trashed, must reload
+ * rIBASE trashed, must reload before resuming interpreter
*/
common_invokeMethodJumbo:
@@ -13474,6 +21587,7 @@
* On entry:
* eax = Method* methodToCall
* rINSTw trashed, must reload
+ * rIBASE trashed, must reload before resuming interpreter
*/
common_invokeMethodRange:
@@ -13515,6 +21629,7 @@
/*
* %eax is "Method* methodToCall", the method we're trying to call
* prepare to copy args to "outs" area of current frame
+ * rIBASE trashed, must reload before resuming interpreter
*/
common_invokeMethodNoRange:
@@ -13621,6 +21736,7 @@
movl offMethod_insns(%eax), rPC # rPC<- methodToCall->insns
movl LOCAL1_OFFSET(%ebp), rFP # rFP<- newFP
movl rFP, offThread_curFrame(%ecx) # self->curFrame<- newFP
+ movl offThread_curHandlerTable(%ecx),rIBASE
FETCH_INST
GOTO_NEXT # jump to methodToCall->insns
@@ -13636,9 +21752,9 @@
movl %eax, offStackSaveArea_localRefCookie(%edx) # newSaveArea->localRefCookie<- top
movl %edx, OUT_ARG4(%esp) # save newSaveArea
movl LOCAL1_OFFSET(%ebp), %edx # %edx<- newFP
- movl %edx, offThread_curFrame(%ecx) # self->self->curFrame<- newFP
- movl %ecx, OUT_ARG3(%esp) # save self->self
- movl %ecx, OUT_ARG2(%esp) # push parameter self->self
+ movl %edx, offThread_curFrame(%ecx) # self->curFrame<- newFP
+ movl %ecx, OUT_ARG3(%esp) # save self
+ movl %ecx, OUT_ARG2(%esp) # push parameter self
movl rSELF,%ecx # %ecx<- pthread
movl OUT_ARG1(%esp), %eax # %eax<- methodToCall
lea offThread_retval(%ecx), %ecx # %ecx<- &retval
@@ -13648,15 +21764,16 @@
call *offMethod_nativeFunc(%eax) # call methodToCall->nativeFunc
lea 4(%esp), %esp
movl OUT_ARG4(%esp), %ecx # %ecx<- newSaveArea
- movl OUT_ARG3(%esp), %eax # %eax<- self->self
+ movl OUT_ARG3(%esp), %eax # %eax<- self
movl offStackSaveArea_localRefCookie(%ecx), %edx # %edx<- old top
cmp $0, offThread_exception(%eax) # check for exception
- movl rFP, offThread_curFrame(%eax) # self->self->curFrame<- rFP
+ movl rFP, offThread_curFrame(%eax) # self->curFrame<- rFP
movl %edx, offThread_jniLocal_topCookie(%eax) # new top <- old top
jne common_exceptionThrown # handle exception
- FETCH_INST_OPCODE 3 %edx
+ movl offThread_curHandlerTable(%eax),rIBASE
+ FETCH_INST_OPCODE 3 %ecx
ADVANCE_PC 3
- GOTO_NEXT_R %edx # jump to next instruction
+ GOTO_NEXT_R %ecx # jump to next instruction
.LstackOverflow: # eax=methodToCall
movl %eax, OUT_ARG1(%esp) # push parameter methodToCall
@@ -13752,16 +21869,17 @@
je common_gotoBail # break frame, bail out completely
movl offStackSaveArea_savedPc(%eax),rPC # pc<- saveArea->savedPC
- movl rINST,offThread_method(%ecx) # self->method = newSave->meethod
- movl rFP,offThread_curFrame(%ecx) # self->curFrame = fp
- movl offMethod_clazz(rINST),%eax # eax<- method->clazz
- FETCH_INST_OPCODE 3 %edx
- movl offClassObject_pDvmDex(%eax),%eax # eax<- method->clazz->pDvmDex
+ movl rINST,offThread_method(%ecx) # self->method = newSave->meethod
+ movl rFP,offThread_curFrame(%ecx) # self->curFrame = fp
+ movl offMethod_clazz(rINST),%eax # eax<- method->clazz
+ movl offThread_curHandlerTable(%ecx),rIBASE
+ movl offClassObject_pDvmDex(%eax),rINST # rINST<- method->clazz->pDvmDex
+ FETCH_INST_OPCODE 3 %eax
+ movl rINST,offThread_methodClassDex(%ecx)
ADVANCE_PC 3
- movl %eax,offThread_methodClassDex(%ecx)
/* not bailing - restore entry mode to default */
movb $kInterpEntryInstr,offThread_entryPoint(%ecx)
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %eax
/*
* Prepare to strip the current frame and "longjump" back to caller of
@@ -13786,7 +21904,10 @@
* and start executing at the next instruction.
*/
common_resumeAfterGlueCall:
- LOAD_PC_FP_FROM_SELF
+ movl rSELF, %eax
+ movl offThread_pc(%eax),rPC
+ movl offThread_fp(%eax),rFP
+ movl offThread_curHandlerTable(%eax),rIBASE
FETCH_INST
GOTO_NEXT
diff --git a/vm/mterp/x86-atom/TODO.txt b/vm/mterp/x86-atom/TODO.txt
index 5ff0083..0da4d71 100644
--- a/vm/mterp/x86-atom/TODO.txt
+++ b/vm/mterp/x86-atom/TODO.txt
@@ -14,6 +14,8 @@
(hi) Rename dvmJitGetCodeAddr to dvmJitGetTraceAddr.
(hi) Remove references to rGLUE and replace with rSELF
(hi) Rework footer.s's suspend check to reflect suspendCount change
+(hi) Rework interpreter to co-exist the new switching model which
+ elminiates a separate debug interpreter.
(md) Correct OP_MONITOR_EXIT (need to adjust PC before throw)
(md) OP_THROW needs to export the PC
diff --git a/vm/mterp/x86/ALT_OP_DISPATCH_FF.S b/vm/mterp/x86/ALT_OP_DISPATCH_FF.S
new file mode 100644
index 0000000..fbd5a3d
--- /dev/null
+++ b/vm/mterp/x86/ALT_OP_DISPATCH_FF.S
@@ -0,0 +1,3 @@
+%verify "executed"
+ leal 256(rINST),%ecx
+ GOTO_NEXT_JUMBO_R %ecx
diff --git a/vm/mterp/x86/ALT_STUB.S b/vm/mterp/x86/ALT_STUB.S
new file mode 100644
index 0000000..c29dbc9
--- /dev/null
+++ b/vm/mterp/x86/ALT_STUB.S
@@ -0,0 +1,13 @@
+/*
+ * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
+ * any interesting requests and then jump to the real instruction
+ * handler. Unlike the Arm handler, we can't do this as a tail call
+ * because rIBASE is caller save and we need to reload it.
+ */
+ movl rSELF, %eax
+ movl rPC, OUT_ARG0(%esp)
+ movl %eax, OUT_ARG1(%esp)
+ call dvmCheckInst # (dPC, self)
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx), rIBASE # reload rIBASE
+ jmp *dvmAsmInstructionStart+(${opnum}*4)
diff --git a/vm/mterp/x86/OP_ADD_LONG.S b/vm/mterp/x86/OP_ADD_LONG.S
index b1edd3d..bc157f6 100644
--- a/vm/mterp/x86/OP_ADD_LONG.S
+++ b/vm/mterp/x86/OP_ADD_LONG.S
@@ -1,2 +1,2 @@
%verify "executed"
-%include "x86/binopWide.S" {"instr1":"addl (rFP,%ecx,4),%edx", "instr2":"adcl 4(rFP,%ecx,4),%eax"}
+%include "x86/binopWide.S" {"instr1":"addl (rFP,%ecx,4),rIBASE", "instr2":"adcl 4(rFP,%ecx,4),%eax"}
diff --git a/vm/mterp/x86/OP_AGET.S b/vm/mterp/x86/OP_AGET.S
index 65ff582..42dfa0a 100644
--- a/vm/mterp/x86/OP_AGET.S
+++ b/vm/mterp/x86/OP_AGET.S
@@ -18,7 +18,7 @@
# index in ecx
$load offArrayObject_contents(%eax,%ecx,$shift),%eax
.L${opcode}_finish:
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
SET_VREG %eax rINST
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_AGET_WIDE.S b/vm/mterp/x86/OP_AGET_WIDE.S
index 96d1c89..32266bc 100644
--- a/vm/mterp/x86/OP_AGET_WIDE.S
+++ b/vm/mterp/x86/OP_AGET_WIDE.S
@@ -11,18 +11,14 @@
testl %eax,%eax # null array object?
je common_errNullObject # bail if so
cmpl offArrayObject_length(%eax),%ecx
- jb .L${opcode}_finish # index < length, OK
- jmp common_errArrayIndex # index >= length, bail. Expects
+ jae common_errArrayIndex # index >= length, bail. Expects
# arrayObj in eax
# index in ecx
-%break
-
-.L${opcode}_finish:
leal offArrayObject_contents(%eax,%ecx,8),%eax
movl (%eax),%ecx
movl 4(%eax),%eax
SET_VREG_WORD %ecx rINST 0
SET_VREG_WORD %eax rINST 1
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_AND_LONG.S b/vm/mterp/x86/OP_AND_LONG.S
index 8a1152e..06df873 100644
--- a/vm/mterp/x86/OP_AND_LONG.S
+++ b/vm/mterp/x86/OP_AND_LONG.S
@@ -1,2 +1,2 @@
%verify "executed"
-%include "x86/binopWide.S" {"instr1":"andl (rFP,%ecx,4),%edx", "instr2":"andl 4(rFP,%ecx,4),%eax"}
+%include "x86/binopWide.S" {"instr1":"andl (rFP,%ecx,4),rIBASE", "instr2":"andl 4(rFP,%ecx,4),%eax"}
diff --git a/vm/mterp/x86/OP_APUT.S b/vm/mterp/x86/OP_APUT.S
index 797b692..f51c9c7 100644
--- a/vm/mterp/x86/OP_APUT.S
+++ b/vm/mterp/x86/OP_APUT.S
@@ -1,4 +1,4 @@
-%default { "reg":"%ecx", "store":"movl", "shift":"4" }
+%default { "reg":"rINST", "store":"movl", "shift":"4" }
%verify "executed"
/*
* Array put, 32 bits or less. vBB[vCC] <- vAA
@@ -18,8 +18,8 @@
# index in ecx
leal offArrayObject_contents(%eax,%ecx,$shift),%eax
.L${opcode}_finish:
- GET_VREG_R %ecx rINST
- FETCH_INST_OPCODE 2 %edx
+ GET_VREG_R rINST rINST
+ FETCH_INST_OPCODE 2 %ecx
$store $reg,(%eax)
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_APUT_BOOLEAN.S b/vm/mterp/x86/OP_APUT_BOOLEAN.S
index 14f8c7f..fb1e8db 100644
--- a/vm/mterp/x86/OP_APUT_BOOLEAN.S
+++ b/vm/mterp/x86/OP_APUT_BOOLEAN.S
@@ -1,2 +1,2 @@
%verify "executed"
-%include "x86/OP_APUT.S" {"reg":"%cl", "store":"movb", "shift":"1" }
+%include "x86/OP_APUT.S" {"reg":"rINSTbl", "store":"movb", "shift":"1" }
diff --git a/vm/mterp/x86/OP_APUT_BYTE.S b/vm/mterp/x86/OP_APUT_BYTE.S
index d92225f..366c8c5 100644
--- a/vm/mterp/x86/OP_APUT_BYTE.S
+++ b/vm/mterp/x86/OP_APUT_BYTE.S
@@ -1,2 +1,2 @@
%verify "executed"
-%include "x86/OP_APUT.S" { "reg":"%cl", "store":"movb", "shift":"1" }
+%include "x86/OP_APUT.S" { "reg":"rINSTbl", "store":"movb", "shift":"1" }
diff --git a/vm/mterp/x86/OP_APUT_CHAR.S b/vm/mterp/x86/OP_APUT_CHAR.S
index d466007..9c87384 100644
--- a/vm/mterp/x86/OP_APUT_CHAR.S
+++ b/vm/mterp/x86/OP_APUT_CHAR.S
@@ -1,2 +1,2 @@
%verify "executed"
-%include "x86/OP_APUT.S" { "reg":"%cx", "store":"movw", "shift":"2" }
+%include "x86/OP_APUT.S" { "reg":"rINSTw", "store":"movw", "shift":"2" }
diff --git a/vm/mterp/x86/OP_APUT_OBJECT.S b/vm/mterp/x86/OP_APUT_OBJECT.S
index 64d7e94..4dd579c 100644
--- a/vm/mterp/x86/OP_APUT_OBJECT.S
+++ b/vm/mterp/x86/OP_APUT_OBJECT.S
@@ -13,18 +13,14 @@
testl %eax,%eax # null array object?
je common_errNullObject # bail if so
cmpl offArrayObject_length(%eax),%ecx
- jb .L${opcode}_continue
- jmp common_errArrayIndex # index >= length, bail. Expects
+ jae common_errArrayIndex # index >= length, bail. Expects
# arrayObj in eax
# index in ecx
-%break
-
/* On entry:
* eax<- array object
* ecx<- index
* rINST<- vAA
*/
-.L${opcode}_continue:
leal offArrayObject_contents(%eax,%ecx,4),%ecx
testl rINST,rINST # storing null reference?
je .L${opcode}_skip_check
@@ -36,7 +32,9 @@
movl %ecx,OUT_ARG0(%esp)
movl %ecx,sReg0 # store the two classes for later
movl %eax,sReg1
+ SPILL(rIBASE)
call dvmCanPutArrayElement # test object type vs. array type
+ UNSPILL(rIBASE)
UNSPILL_TMP1(%ecx) # recover target address
testl %eax,%eax
movl rSELF,%eax
@@ -54,15 +52,15 @@
.L${opcode}_types_okay:
movl offThread_cardTable(%eax),%eax # get card table base
movl rINST,(%ecx) # store into array
- UNSPILL_TMP2(%ecx) # recover object head
- FETCH_INST_OPCODE 2 %edx
- shrl $$GC_CARD_SHIFT,%ecx # object head to card number
- movb %al,(%eax,%ecx) # mark card using object head
+ UNSPILL_TMP2(rINST) # recover object head
+ FETCH_INST_OPCODE 2 %ecx
+ shrl $$GC_CARD_SHIFT,rINST # object head to card number
+ movb %al,(%eax,rINST) # mark card using object head
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
.L${opcode}_skip_check:
movl rINST,(%ecx)
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_APUT_SHORT.S b/vm/mterp/x86/OP_APUT_SHORT.S
index d466007..9c87384 100644
--- a/vm/mterp/x86/OP_APUT_SHORT.S
+++ b/vm/mterp/x86/OP_APUT_SHORT.S
@@ -1,2 +1,2 @@
%verify "executed"
-%include "x86/OP_APUT.S" { "reg":"%cx", "store":"movw", "shift":"2" }
+%include "x86/OP_APUT.S" { "reg":"rINSTw", "store":"movw", "shift":"2" }
diff --git a/vm/mterp/x86/OP_APUT_WIDE.S b/vm/mterp/x86/OP_APUT_WIDE.S
index 3647c3e..cd1e723 100644
--- a/vm/mterp/x86/OP_APUT_WIDE.S
+++ b/vm/mterp/x86/OP_APUT_WIDE.S
@@ -11,18 +11,14 @@
testl %eax,%eax # null array object?
je common_errNullObject # bail if so
cmpl offArrayObject_length(%eax),%ecx
- jb .L${opcode}_finish # index < length, OK
- jmp common_errArrayIndex # index >= length, bail. Expects:
+ jae common_errArrayIndex # index >= length, bail. Expects:
# arrayObj in eax
# index in ecx
-%break
-
-.L${opcode}_finish:
leal offArrayObject_contents(%eax,%ecx,8),%eax
GET_VREG_WORD %ecx rINST 0
GET_VREG_WORD rINST rINST 1
- movl rINST,4(%eax)
- FETCH_INST_OPCODE 2 %edx
movl %ecx,(%eax)
+ FETCH_INST_OPCODE 2 %ecx
+ movl rINST,4(%eax)
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_ARRAY_LENGTH.S b/vm/mterp/x86/OP_ARRAY_LENGTH.S
index 1666d0e..25caca3 100644
--- a/vm/mterp/x86/OP_ARRAY_LENGTH.S
+++ b/vm/mterp/x86/OP_ARRAY_LENGTH.S
@@ -8,8 +8,8 @@
andb $$0xf,%al # eax<- A
testl %ecx,%ecx # is null?
je common_errNullObject
- FETCH_INST_OPCODE 1 %edx
- movl offArrayObject_length(%ecx),%ecx
+ movl offArrayObject_length(%ecx),rINST
+ FETCH_INST_OPCODE 1 %ecx
ADVANCE_PC 1
- SET_VREG %ecx %eax
- GOTO_NEXT_R %edx
+ SET_VREG rINST %eax
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_CHECK_CAST.S b/vm/mterp/x86/OP_CHECK_CAST.S
index 53fdd77..0543a99 100644
--- a/vm/mterp/x86/OP_CHECK_CAST.S
+++ b/vm/mterp/x86/OP_CHECK_CAST.S
@@ -24,10 +24,9 @@
cmpl %eax,%ecx # same class (trivial success)?
jne .L${opcode}_fullcheck # no, do full check
.L${opcode}_okay:
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
-%break
+ GOTO_NEXT_R %ecx
/*
* Trivial test failed, need to perform full check. This is common.
@@ -39,7 +38,9 @@
movl %eax,sReg0 # we'll need the desired class on failure
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmInstanceofNonTrivial # eax<- boolean result
+ UNSPILL(rIBASE)
testl %eax,%eax # failed?
jne .L${opcode}_okay # no, success
@@ -67,7 +68,9 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- metho->clazz
movl $$0,OUT_ARG2(%esp) # arg2<- false
movl %ecx,OUT_ARG0(%esp) # arg0<- method->clazz
+ SPILL(rIBASE)
call dvmResolveClass # eax<- resolved ClassObject ptr
+ UNSPILL(rIBASE)
testl %eax,%eax # got null?
je common_exceptionThrown # yes, handle exception
movl offObject_clazz(rINST),%ecx # ecx<- obj->clazz
diff --git a/vm/mterp/x86/OP_CHECK_CAST_JUMBO.S b/vm/mterp/x86/OP_CHECK_CAST_JUMBO.S
index e161197..bf99bd7 100644
--- a/vm/mterp/x86/OP_CHECK_CAST_JUMBO.S
+++ b/vm/mterp/x86/OP_CHECK_CAST_JUMBO.S
@@ -24,10 +24,9 @@
cmpl %eax,%ecx # same class (trivial success)?
jne .L${opcode}_fullcheck # no, do full check
.L${opcode}_okay:
- FETCH_INST_OPCODE 4 %edx
+ FETCH_INST_OPCODE 4 %ecx
ADVANCE_PC 4
- GOTO_NEXT_R %edx
-%break
+ GOTO_NEXT_R %ecx
/*
* Trivial test failed, need to perform full check. This is common.
@@ -39,7 +38,9 @@
movl %eax,sReg0 # we'll need the desired class on failure
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmInstanceofNonTrivial # eax<- boolean result
+ UNSPILL(rIBASE)
testl %eax,%eax # failed?
jne .L${opcode}_okay # no, success
@@ -67,7 +68,9 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- metho->clazz
movl $$0,OUT_ARG2(%esp) # arg2<- false
movl %ecx,OUT_ARG0(%esp) # arg0<- method->clazz
+ SPILL(rIBASE)
call dvmResolveClass # eax<- resolved ClassObject ptr
+ UNSPILL(rIBASE)
testl %eax,%eax # got null?
je common_exceptionThrown # yes, handle exception
movl offObject_clazz(rINST),%ecx # ecx<- obj->clazz
diff --git a/vm/mterp/x86/OP_CMPG_DOUBLE.S b/vm/mterp/x86/OP_CMPG_DOUBLE.S
index e50f0d6..1388d7c 100644
--- a/vm/mterp/x86/OP_CMPG_DOUBLE.S
+++ b/vm/mterp/x86/OP_CMPG_DOUBLE.S
@@ -17,18 +17,16 @@
fucompp # z if equal, p set if NaN, c set if st0 < st1
fnstsw %ax
sahf
- movl rINST,%eax
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %eax
jp .L${opcode}_isNaN
je .L${opcode}_finish
sbbl %ecx,%ecx
jb .L${opcode}_finish
incl %ecx
.L${opcode}_finish:
- SET_VREG %ecx %eax
+ SET_VREG %ecx rINST
ADVANCE_PC 2
- GOTO_NEXT_R %edx
-%break
+ GOTO_NEXT_R %eax
.L${opcode}_isNaN:
movl $$$nanval,%ecx
diff --git a/vm/mterp/x86/OP_CMP_LONG.S b/vm/mterp/x86/OP_CMP_LONG.S
index e2b7436..5202c27 100644
--- a/vm/mterp/x86/OP_CMP_LONG.S
+++ b/vm/mterp/x86/OP_CMP_LONG.S
@@ -6,27 +6,37 @@
* Compare two 64-bit values. Puts 0, 1, or -1 into the destination
* register based on the results of the comparison.
*/
+ // TUNING: rework to avoid rIBASE spill
/* cmp-long vAA, vBB, vCC */
movzbl 2(rPC),%ecx # ecx<- BB
- movzbl 3(rPC),%edx # edx<- CC
+ SPILL(rIBASE)
+ movzbl 3(rPC),rIBASE # rIBASE- CC
GET_VREG_WORD %eax %ecx,1 # eax<- v[BB+1]
GET_VREG_WORD %ecx %ecx 0 # ecx<- v[BB+0]
- cmpl 4(rFP,%edx,4),%eax
+ cmpl 4(rFP,rIBASE,4),%eax
jl .L${opcode}_smaller
jg .L${opcode}_bigger
- sub (rFP,%edx,4),%ecx
+ sub (rFP,rIBASE,4),%ecx
ja .L${opcode}_bigger
jb .L${opcode}_smaller
- jmp .L${opcode}_finish
-%break
+ SET_VREG %ecx rINST
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
.L${opcode}_bigger:
movl $$1,%ecx
- jmp .L${opcode}_finish
+ SET_VREG %ecx rINST
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
+
.L${opcode}_smaller:
movl $$-1,%ecx
-.L${opcode}_finish:
SET_VREG %ecx rINST
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_CONST.S b/vm/mterp/x86/OP_CONST.S
index b1ff401..cb70824 100644
--- a/vm/mterp/x86/OP_CONST.S
+++ b/vm/mterp/x86/OP_CONST.S
@@ -1,8 +1,8 @@
%verify "executed"
/* const vAA, #+BBBBbbbb */
movl 2(rPC),%eax # grab all 32 bits at once
- movl rINST,%ecx # ecx<- AA
- FETCH_INST_OPCODE 3 %edx
+ movl rINST,rINST # rINST<- AA
+ FETCH_INST_OPCODE 3 %ecx
ADVANCE_PC 3
- SET_VREG %eax %ecx # vAA<- eax
- GOTO_NEXT_R %edx
+ SET_VREG %eax rINST # vAA<- eax
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_CONST_16.S b/vm/mterp/x86/OP_CONST_16.S
index df3d423..b956ee6 100644
--- a/vm/mterp/x86/OP_CONST_16.S
+++ b/vm/mterp/x86/OP_CONST_16.S
@@ -1,8 +1,7 @@
%verify "executed"
/* const/16 vAA, #+BBBB */
movswl 2(rPC),%ecx # ecx<- ssssBBBB
- movl rINST,%eax # eax<- AA
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %eax
ADVANCE_PC 2
- SET_VREG %ecx %eax # vAA<- ssssBBBB
- GOTO_NEXT_R %edx
+ SET_VREG %ecx rINST # vAA<- ssssBBBB
+ GOTO_NEXT_R %eax
diff --git a/vm/mterp/x86/OP_CONST_4.S b/vm/mterp/x86/OP_CONST_4.S
index 54d1e44..3db437a 100644
--- a/vm/mterp/x86/OP_CONST_4.S
+++ b/vm/mterp/x86/OP_CONST_4.S
@@ -1,10 +1,10 @@
%verify "executed"
/* const/4 vA, #+B */
movsx rINSTbl,%eax # eax<-ssssssBx
- movl $$0xf,%ecx
- andl %eax,%ecx # ecx<- A
- FETCH_INST_OPCODE 1 %edx
+ movl $$0xf,rINST
+ andl %eax,rINST # rINST<- A
+ FETCH_INST_OPCODE 1 %ecx
ADVANCE_PC 1
sarl $$4,%eax
- SET_VREG %eax %ecx
- GOTO_NEXT_R %edx
+ SET_VREG %eax rINST
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_CONST_CLASS.S b/vm/mterp/x86/OP_CONST_CLASS.S
index 5320c28..8b12226 100644
--- a/vm/mterp/x86/OP_CONST_CLASS.S
+++ b/vm/mterp/x86/OP_CONST_CLASS.S
@@ -8,20 +8,17 @@
movl offThread_methodClassDex(%ecx),%ecx# ecx<- self->methodClassDex
movl offDvmDex_pResClasses(%ecx),%ecx # ecx<- dvmDex->pResClasses
movl (%ecx,%eax,4),%eax # eax<- rResClasses[BBBB]
- movl rINST,%ecx
- FETCH_INST_OPCODE 2 %edx
testl %eax,%eax # resolved yet?
je .L${opcode}_resolve
- SET_VREG %eax %ecx # vAA<- rResClasses[BBBB]
+ FETCH_INST_OPCODE 2 %ecx
+ SET_VREG %eax rINST # vAA<- rResClasses[BBBB]
ADVANCE_PC 2
- GOTO_NEXT_R %edx
-%break
+ GOTO_NEXT_R %ecx
/* This is the less common path, so we'll redo some work
here rather than force spills on the common path */
.L${opcode}_resolve:
movl rSELF,%eax
- movl %ecx,rINST # rINST<- AA
EXPORT_PC
movl offThread_method(%eax),%eax # eax<- self->method
movl $$1,OUT_ARG2(%esp) # true
@@ -29,10 +26,12 @@
movl offMethod_clazz(%eax),%eax
movl %ecx,OUT_ARG1(%esp)
movl %eax,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveClass # go resolve
+ UNSPILL(rIBASE)
testl %eax,%eax # failed?
je common_exceptionThrown
+ FETCH_INST_OPCODE 2 %ecx
SET_VREG %eax rINST
- FETCH_INST_OPCODE 2 %edx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_CONST_CLASS_JUMBO.S b/vm/mterp/x86/OP_CONST_CLASS_JUMBO.S
index 9fa6742..44162da 100644
--- a/vm/mterp/x86/OP_CONST_CLASS_JUMBO.S
+++ b/vm/mterp/x86/OP_CONST_CLASS_JUMBO.S
@@ -6,14 +6,13 @@
movl 2(rPC),%eax # eax<- AAAAAAAA
movl offThread_methodClassDex(%ecx),%ecx# ecx<- self->methodClassDex
movl offDvmDex_pResClasses(%ecx),%ecx # ecx<- dvmDex->pResClasses
+ FETCH_INST_OPCODE 4 %ecx
movl (%ecx,%eax,4),%eax # eax<- rResClasses[AAAAAAAA]
- FETCH_INST_OPCODE 4 %edx
testl %eax,%eax # resolved yet?
je .L${opcode}_resolve
SET_VREG %eax rINST # vBBBB<- rResClasses[AAAAAAAA]
ADVANCE_PC 4
- GOTO_NEXT_R %edx
-%break
+ GOTO_NEXT_R %ecx
/* This is the less common path, so we'll redo some work
here rather than force spills on the common path */
@@ -26,10 +25,12 @@
movl offMethod_clazz(%eax),%eax
movl %ecx,OUT_ARG1(%esp)
movl %eax,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveClass # go resolve
+ UNSPILL(rIBASE)
testl %eax,%eax # failed?
je common_exceptionThrown
+ FETCH_INST_OPCODE 4 %ecx
SET_VREG %eax rINST
- FETCH_INST_OPCODE 4 %edx
ADVANCE_PC 4
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_CONST_HIGH16.S b/vm/mterp/x86/OP_CONST_HIGH16.S
index 3c3b2d7..9ecf7c6 100644
--- a/vm/mterp/x86/OP_CONST_HIGH16.S
+++ b/vm/mterp/x86/OP_CONST_HIGH16.S
@@ -1,9 +1,8 @@
%verify "executed"
/* const/high16 vAA, #+BBBB0000 */
movzwl 2(rPC),%eax # eax<- 0000BBBB
- movl rINST,%ecx # ecx<- AA
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
sall $$16,%eax # eax<- BBBB0000
- SET_VREG %eax %ecx # vAA<- eax
- GOTO_NEXT_R %edx
+ SET_VREG %eax rINST # vAA<- eax
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_CONST_STRING.S b/vm/mterp/x86/OP_CONST_STRING.S
index f73c352..538cace 100644
--- a/vm/mterp/x86/OP_CONST_STRING.S
+++ b/vm/mterp/x86/OP_CONST_STRING.S
@@ -8,30 +8,29 @@
movl offThread_methodClassDex(%ecx),%ecx# ecx<- self->methodClassDex
movl offDvmDex_pResStrings(%ecx),%ecx # ecx<- dvmDex->pResStrings
movl (%ecx,%eax,4),%eax # eax<- rResString[BBBB]
- movl rINST,%ecx
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
testl %eax,%eax # resolved yet?
je .L${opcode}_resolve
- SET_VREG %eax %ecx # vAA<- rResString[BBBB]
+ SET_VREG %eax rINST # vAA<- rResString[BBBB]
ADVANCE_PC 2
- GOTO_NEXT_R %edx
-%break
+ GOTO_NEXT_R %ecx
/* This is the less common path, so we'll redo some work
here rather than force spills on the common path */
.L${opcode}_resolve:
movl rSELF,%eax
- movl %ecx,rINST # rINST<- AA
EXPORT_PC
movl offThread_method(%eax),%eax # eax<- self->method
movzwl 2(rPC),%ecx # ecx<- BBBB
movl offMethod_clazz(%eax),%eax
movl %ecx,OUT_ARG1(%esp)
movl %eax,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveString # go resolve
+ UNSPILL(rIBASE)
testl %eax,%eax # failed?
je common_exceptionThrown
+ FETCH_INST_OPCODE 2 %ecx
SET_VREG %eax rINST
- FETCH_INST_OPCODE 2 %edx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_CONST_STRING_JUMBO.S b/vm/mterp/x86/OP_CONST_STRING_JUMBO.S
index 424d6b9..6148244 100644
--- a/vm/mterp/x86/OP_CONST_STRING_JUMBO.S
+++ b/vm/mterp/x86/OP_CONST_STRING_JUMBO.S
@@ -8,30 +8,29 @@
movl offThread_methodClassDex(%ecx),%ecx# ecx<- self->methodClassDex
movl offDvmDex_pResStrings(%ecx),%ecx # ecx<- dvmDex->pResStrings
movl (%ecx,%eax,4),%eax # eax<- rResString[BBBB]
- movl rINST,%ecx
- FETCH_INST_OPCODE 3 %edx
+ FETCH_INST_OPCODE 3 %ecx
testl %eax,%eax # resolved yet?
je .L${opcode}_resolve
- SET_VREG %eax %ecx # vAA<- rResString[BBBB]
+ SET_VREG %eax rINST # vAA<- rResString[BBBB]
ADVANCE_PC 3
- GOTO_NEXT_R %edx
-%break
+ GOTO_NEXT_R %ecx
/* This is the less common path, so we'll redo some work
here rather than force spills on the common path */
.L${opcode}_resolve:
movl rSELF,%eax
- movl %ecx,rINST # rINST<- AA
EXPORT_PC
movl offThread_method(%eax),%eax # eax<- self->method
movl 2(rPC),%ecx # ecx<- BBBBBBBB
movl offMethod_clazz(%eax),%eax
movl %ecx,OUT_ARG1(%esp)
movl %eax,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveString # go resolve
+ UNSPILL(rIBASE)
testl %eax,%eax # failed?
je common_exceptionThrown
+ FETCH_INST_OPCODE 3 %ecx
SET_VREG %eax rINST
- FETCH_INST_OPCODE 3 %edx
ADVANCE_PC 3
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_CONST_WIDE.S b/vm/mterp/x86/OP_CONST_WIDE.S
index b4273df..253af78 100644
--- a/vm/mterp/x86/OP_CONST_WIDE.S
+++ b/vm/mterp/x86/OP_CONST_WIDE.S
@@ -5,7 +5,7 @@
movl 6(rPC),rINST # rINST<- msw
leal (rFP,%ecx,4),%ecx # dst addr
movl rINST,4(%ecx)
- FETCH_INST_OPCODE 5 %edx
movl %eax,(%ecx)
+ FETCH_INST_OPCODE 5 %ecx
ADVANCE_PC 5
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_CONST_WIDE_16.S b/vm/mterp/x86/OP_CONST_WIDE_16.S
index b720748..ee8004c 100644
--- a/vm/mterp/x86/OP_CONST_WIDE_16.S
+++ b/vm/mterp/x86/OP_CONST_WIDE_16.S
@@ -1,9 +1,11 @@
%verify "executed"
/* const-wide/16 vAA, #+BBBB */
movswl 2(rPC),%eax # eax<- ssssBBBB
- cltd # rPC:eax<- ssssssssssssBBBB
- SET_VREG_WORD %edx rINST 1 # store msw
- FETCH_INST_OPCODE 2 %edx
+ SPILL(rIBASE) # preserve rIBASE (cltd trashes it)
+ cltd # rIBASE:eax<- ssssssssssssBBBB
+ SET_VREG_WORD rIBASE rINST 1 # store msw
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE) # restore rIBASE
SET_VREG_WORD %eax rINST 0 # store lsw
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_CONST_WIDE_32.S b/vm/mterp/x86/OP_CONST_WIDE_32.S
index b059529..12cdd01 100644
--- a/vm/mterp/x86/OP_CONST_WIDE_32.S
+++ b/vm/mterp/x86/OP_CONST_WIDE_32.S
@@ -1,9 +1,11 @@
%verify "executed"
/* const-wide/32 vAA, #+BBBBbbbb */
movl 2(rPC),%eax # eax<- BBBBbbbb
- cltd # rPC:eax<- ssssssssssssBBBB
- SET_VREG_WORD %edx rINST,1 # store msw
- FETCH_INST_OPCODE 3 %edx
+ SPILL(rIBASE) # save rIBASE (cltd trashes it)
+ cltd # rIBASE:eax<- ssssssssssssBBBB
+ SET_VREG_WORD rIBASE rINST,1 # store msw
+ FETCH_INST_OPCODE 3 %ecx
+ UNSPILL(rIBASE) # restore rIBASE
SET_VREG_WORD %eax rINST 0 # store lsw
ADVANCE_PC 3
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_CONST_WIDE_HIGH16.S b/vm/mterp/x86/OP_CONST_WIDE_HIGH16.S
index dae78cb..15a0c55 100644
--- a/vm/mterp/x86/OP_CONST_WIDE_HIGH16.S
+++ b/vm/mterp/x86/OP_CONST_WIDE_HIGH16.S
@@ -1,10 +1,10 @@
%verify "executed"
/* const-wide/high16 vAA, #+BBBB000000000000 */
movzwl 2(rPC),%eax # eax<- 0000BBBB
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
sall $$16,%eax # eax<- BBBB0000
SET_VREG_WORD %eax rINST 1 # v[AA+1]<- eax
xorl %eax,%eax
SET_VREG_WORD %eax rINST 0 # v[AA+0]<- eax
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_DISPATCH_FF.S b/vm/mterp/x86/OP_DISPATCH_FF.S
index 8729847..fbd5a3d 100644
--- a/vm/mterp/x86/OP_DISPATCH_FF.S
+++ b/vm/mterp/x86/OP_DISPATCH_FF.S
@@ -1,3 +1,3 @@
%verify "executed"
- leal 256(rINST),%edx
- GOTO_NEXT_JUMBO_R %edx
+ leal 256(rINST),%ecx
+ GOTO_NEXT_JUMBO_R %ecx
diff --git a/vm/mterp/x86/OP_DIV_LONG.S b/vm/mterp/x86/OP_DIV_LONG.S
index 4a7704b..0dc5546 100644
--- a/vm/mterp/x86/OP_DIV_LONG.S
+++ b/vm/mterp/x86/OP_DIV_LONG.S
@@ -3,46 +3,44 @@
/* div vAA, vBB, vCC */
movzbl 3(rPC),%eax # eax<- CC
movzbl 2(rPC),%ecx # ecx<- BB
- GET_VREG_WORD %edx %eax 0
+ SPILL(rIBASE) # save rIBASE/%edx
+ GET_VREG_WORD rIBASE %eax 0
GET_VREG_WORD %eax %eax 1
- movl %edx,OUT_ARG2(%esp)
+ movl rIBASE,OUT_ARG2(%esp)
testl %eax,%eax
je .L${opcode}_check_zero
cmpl $$-1,%eax
je .L${opcode}_check_neg1
.L${opcode}_notSpecial:
- GET_VREG_WORD %edx %ecx 0
+ GET_VREG_WORD rIBASE %ecx 0
GET_VREG_WORD %ecx %ecx 1
.L${opcode}_notSpecial1:
movl %eax,OUT_ARG3(%esp)
- movl %edx,OUT_ARG0(%esp)
+ movl rIBASE,OUT_ARG0(%esp)
movl %ecx,OUT_ARG1(%esp)
- jmp .L${opcode}_continue
-%break
-
-.L${opcode}_continue:
call $routine
.L${opcode}_finish:
- SET_VREG_WORD %edx rINST 1
+ SET_VREG_WORD rIBASE rINST 1
+ UNSPILL(rIBASE) # restore rIBASE/%edx
SET_VREG_WORD %eax rINST 0
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
.L${opcode}_check_zero:
- testl %edx,%edx
+ testl rIBASE,rIBASE
jne .L${opcode}_notSpecial
jmp common_errDivideByZero
.L${opcode}_check_neg1:
- testl %edx,%eax
+ testl rIBASE,%eax
jne .L${opcode}_notSpecial
- GET_VREG_WORD %edx %ecx 0
+ GET_VREG_WORD rIBASE %ecx 0
GET_VREG_WORD %ecx %ecx 1
- testl %edx,%edx
+ testl rIBASE,rIBASE
jne .L${opcode}_notSpecial1
cmpl $$0x80000000,%ecx
jne .L${opcode}_notSpecial1
/* minint / -1, return minint on div, 0 on rem */
xorl %eax,%eax
- movl $special,%edx
+ movl $special,rIBASE
jmp .L${opcode}_finish
diff --git a/vm/mterp/x86/OP_DIV_LONG_2ADDR.S b/vm/mterp/x86/OP_DIV_LONG_2ADDR.S
index 64de025..4722098 100644
--- a/vm/mterp/x86/OP_DIV_LONG_2ADDR.S
+++ b/vm/mterp/x86/OP_DIV_LONG_2ADDR.S
@@ -4,46 +4,44 @@
movzbl rINSTbl,%eax
shrl $$4,%eax # eax<- B
andb $$0xf,rINSTbl # rINST<- A
- GET_VREG_WORD %edx %eax 0
+ SPILL(rIBASE) # save rIBASE/%edx
+ GET_VREG_WORD rIBASE %eax 0
GET_VREG_WORD %eax %eax 1
- movl %edx,OUT_ARG2(%esp)
+ movl rIBASE,OUT_ARG2(%esp)
testl %eax,%eax
je .L${opcode}_check_zero
cmpl $$-1,%eax
je .L${opcode}_check_neg1
.L${opcode}_notSpecial:
- GET_VREG_WORD %edx rINST 0
+ GET_VREG_WORD rIBASE rINST 0
GET_VREG_WORD %ecx rINST 1
.L${opcode}_notSpecial1:
- jmp .L${opcode}_continue
-%break
-
-.L${opcode}_continue:
movl %eax,OUT_ARG3(%esp)
- movl %edx,OUT_ARG0(%esp)
+ movl rIBASE,OUT_ARG0(%esp)
movl %ecx,OUT_ARG1(%esp)
call $routine
.L${opcode}_finish:
- SET_VREG_WORD %edx rINST 1
+ SET_VREG_WORD rIBASE rINST 1
+ UNSPILL(rIBASE) # restore rIBASE/%edx
SET_VREG_WORD %eax rINST 0
- FETCH_INST_OPCODE 1 %edx
+ FETCH_INST_OPCODE 1 %ecx
ADVANCE_PC 1
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
.L${opcode}_check_zero:
- testl %edx,%edx
+ testl rIBASE,rIBASE
jne .L${opcode}_notSpecial
jmp common_errDivideByZero
.L${opcode}_check_neg1:
- testl %edx,%eax
+ testl rIBASE,%eax
jne .L${opcode}_notSpecial
- GET_VREG_WORD %edx rINST 0
+ GET_VREG_WORD rIBASE rINST 0
GET_VREG_WORD %ecx rINST 1
- testl %edx,%edx
+ testl rIBASE,rIBASE
jne .L${opcode}_notSpecial1
cmpl $$0x80000000,%ecx
jne .L${opcode}_notSpecial1
/* minint / -1, return minint on div, 0 on rem */
xorl %eax,%eax
- movl $special,%edx
+ movl $special,rIBASE
jmp .L${opcode}_finish
diff --git a/vm/mterp/x86/OP_EXECUTE_INLINE.S b/vm/mterp/x86/OP_EXECUTE_INLINE.S
index 17b6edb..ec91076 100644
--- a/vm/mterp/x86/OP_EXECUTE_INLINE.S
+++ b/vm/mterp/x86/OP_EXECUTE_INLINE.S
@@ -15,14 +15,15 @@
EXPORT_PC
movzwl 2(rPC),%eax # eax<- BBBB
leal offThread_retval(%ecx),%ecx # ecx<- & self->retval
+ SPILL(rIBASE) # preserve rIBASE
movl %ecx,OUT_ARG4(%esp)
call .L${opcode}_continue # make call; will return after
+ UNSPILL(rIBASE) # restore rIBASE
testl %eax,%eax # successful?
- FETCH_INST_OPCODE 3 %edx
+ FETCH_INST_OPCODE 3 %ecx
je common_exceptionThrown # no, handle exception
ADVANCE_PC 3
- GOTO_NEXT_R %edx
-%break
+ GOTO_NEXT_R %ecx
.L${opcode}_continue:
/*
@@ -34,30 +35,30 @@
*
* Go ahead and load all 4 args, even if not used.
*/
- movzwl 4(rPC),%edx
+ movzwl 4(rPC),rIBASE
movl $$0xf,%ecx
- andl %edx,%ecx
+ andl rIBASE,%ecx
GET_VREG_R %ecx %ecx
- sarl $$4,%edx
+ sarl $$4,rIBASE
movl %ecx,4+OUT_ARG0(%esp)
movl $$0xf,%ecx
- andl %edx,%ecx
+ andl rIBASE,%ecx
GET_VREG_R %ecx %ecx
- sarl $$4,%edx
+ sarl $$4,rIBASE
movl %ecx,4+OUT_ARG1(%esp)
movl $$0xf,%ecx
- andl %edx,%ecx
+ andl rIBASE,%ecx
GET_VREG_R %ecx %ecx
- sarl $$4,%edx
+ sarl $$4,rIBASE
movl %ecx,4+OUT_ARG2(%esp)
movl $$0xf,%ecx
- andl %edx,%ecx
+ andl rIBASE,%ecx
GET_VREG_R %ecx %ecx
- sarl $$4,%edx
+ sarl $$4,rIBASE
movl %ecx,4+OUT_ARG3(%esp)
sall $$4,%eax # index *= sizeof(table entry)
diff --git a/vm/mterp/x86/OP_FILLED_NEW_ARRAY.S b/vm/mterp/x86/OP_FILLED_NEW_ARRAY.S
index e51b163..91a26b8 100644
--- a/vm/mterp/x86/OP_FILLED_NEW_ARRAY.S
+++ b/vm/mterp/x86/OP_FILLED_NEW_ARRAY.S
@@ -12,6 +12,7 @@
movl offThread_methodClassDex(%eax),%eax # eax<- pDvmDex
movzwl 2(rPC),%ecx # ecx<- BBBB
movl offDvmDex_pResClasses(%eax),%eax # eax<- pDvmDex->pResClasses
+ SPILL(rIBASE) # preserve rIBASE
movl (%eax,%ecx,4),%eax # eax<- resolved class
EXPORT_PC
testl %eax,%eax # already resolved?
@@ -21,10 +22,6 @@
movl $$0,OUT_ARG2(%esp) # arg2<- false
movl %ecx,OUT_ARG1(%esp) # arg1<- BBBB
movl offThread_method(%eax),%eax # eax<- self->method
- jmp .L${opcode}_more
-%break
-
-.L${opcode}_more:
movl offMethod_clazz(%eax),%eax # eax<- method->clazz
movl %eax,OUT_ARG0(%esp) # arg0<- clazz
call dvmResolveClass # eax<- call(clazz,ref,flag)
@@ -87,19 +84,18 @@
UNSPILL_TMP3(%edi)
movl rSELF,%ecx
movl offThread_retval+4(%ecx),%eax # eax<- type
- FETCH_INST_OPCODE 3 %edx
.else
testl rINST,rINST
je 4f
- UNSPILL_TMP1(%edx) # restore "BA"
- andl $$0x0f,%edx # edx<- 0000000A
- sall $$16,%edx # edx<- 000A0000
- orl %ecx,%edx # edx<- 000AFEDC
+ UNSPILL_TMP1(rIBASE) # restore "BA"
+ andl $$0x0f,rIBASE # rIBASE<- 0000000A
+ sall $$16,rIBASE # rIBASE<- 000A0000
+ orl %ecx,rIBASE # rIBASE<- 000AFEDC
3:
movl $$0xf,%ecx
- andl %edx,%ecx # ecx<- next reg to load
+ andl rIBASE,%ecx # ecx<- next reg to load
GET_VREG_R %ecx %ecx
- shrl $$4,%edx
+ shrl $$4,rIBASE
leal 4(%eax),%eax
movl %ecx,-4(%eax)
sub $$1,rINST
@@ -107,7 +103,6 @@
4:
movl rSELF,%ecx
movl offThread_retval+4(%ecx),%eax # eax<- type
- FETCH_INST_OPCODE 3 %edx
.endif
cmpb $$'I',%al # Int array?
@@ -117,8 +112,10 @@
shrl $$GC_CARD_SHIFT,%eax # convert to card num
movb %cl,(%ecx,%eax) # mark card based on object head
5:
+ UNSPILL(rIBASE) # restore rIBASE
+ FETCH_INST_OPCODE 3 %ecx
ADVANCE_PC 3
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
/*
diff --git a/vm/mterp/x86/OP_FILLED_NEW_ARRAY_JUMBO.S b/vm/mterp/x86/OP_FILLED_NEW_ARRAY_JUMBO.S
index 3a9bff7..1a285f1 100644
--- a/vm/mterp/x86/OP_FILLED_NEW_ARRAY_JUMBO.S
+++ b/vm/mterp/x86/OP_FILLED_NEW_ARRAY_JUMBO.S
@@ -17,13 +17,11 @@
movl $$0,OUT_ARG2(%esp) # arg2<- false
movl %ecx,OUT_ARG1(%esp) # arg1<- AAAAAAAA
movl offThread_method(%eax),%eax # eax<- self->method
- jmp .L${opcode}_more
-%break
-
-.L${opcode}_more:
movl offMethod_clazz(%eax),%eax # eax<- method->clazz
movl %eax,OUT_ARG0(%esp) # arg0<- clazz
+ SPILL(rIBASE)
call dvmResolveClass # eax<- call(clazz,ref,flag)
+ UNSPILL(rIBASE)
testl %eax,%eax # null?
je common_exceptionThrown # yes, handle it
@@ -49,7 +47,9 @@
1:
movl %ecx,offThread_retval+4(%eax) # save type
movl rINST,OUT_ARG1(%esp) # arg1<- BBBB (length)
+ SPILL(rIBASE)
call dvmAllocArrayByClass # eax<- call(arrayClass, length, flags)
+ UNSPILL(rIBASE)
movl rSELF,%ecx
testl %eax,%eax # alloc successful?
je common_exceptionThrown # no, handle exception
@@ -76,7 +76,6 @@
UNSPILL_TMP3(%edi)
movl rSELF,%ecx
movl offThread_retval+4(%ecx),%eax # eax<- type
- FETCH_INST_OPCODE 5 %edx
cmpb $$'I',%al # Int array?
je 5f # skip card mark if so
@@ -85,8 +84,9 @@
shrl $$GC_CARD_SHIFT,%eax # convert to card num
movb %cl,(%ecx,%eax) # mark card based on object head
5:
+ FETCH_INST_OPCODE 5 %ecx
ADVANCE_PC 5
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
/*
diff --git a/vm/mterp/x86/OP_FILL_ARRAY_DATA.S b/vm/mterp/x86/OP_FILL_ARRAY_DATA.S
index 28826f4..5ca17a6 100644
--- a/vm/mterp/x86/OP_FILL_ARRAY_DATA.S
+++ b/vm/mterp/x86/OP_FILL_ARRAY_DATA.S
@@ -6,9 +6,11 @@
EXPORT_PC
movl %eax,OUT_ARG0(%esp)
movl %ecx,OUT_ARG1(%esp)
+ SPILL(rIBASE)
call dvmInterpHandleFillArrayData
- FETCH_INST_OPCODE 3 %edx
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 3 %ecx
testl %eax,%eax # exception thrown?
je common_exceptionThrown
ADVANCE_PC 3
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_IGET.S b/vm/mterp/x86/OP_IGET.S
index 3f383d4..5740690 100644
--- a/vm/mterp/x86/OP_IGET.S
+++ b/vm/mterp/x86/OP_IGET.S
@@ -11,28 +11,24 @@
*/
/* op vA, vB, field@CCCC */
movl rSELF,%ecx
- movzwl 2(rPC),%edx # edx<- 0000CCCC
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ SPILL(rIBASE) # preserve rIBASE
+ movzwl 2(rPC),rIBASE # rIBASE<- 0000CCCC
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
movzbl rINSTbl,%ecx # ecx<- BA
sarl $$4,%ecx # ecx<- B
movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
andb $$0xf,rINSTbl # rINST<- A
GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
+ movl (%eax,rIBASE,4),%eax # resolved entry
testl %eax,%eax # is resolved entry null?
jne .L${opcode}_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp) # needed by dvmResolveInstField
- movl rSELF,%edx
- jmp .L${opcode}_resolve
-%break
-
-
-.L${opcode}_resolve:
+ movl rIBASE,OUT_ARG1(%esp) # needed by dvmResolveInstField
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -50,8 +46,8 @@
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
$load (%ecx,%eax,1),%ecx # ecx<- obj.field (8/16/32 bits)
- movl rINST,%eax # eax<- A
- FETCH_INST_OPCODE 2 %edx
- SET_VREG %ecx %eax
+ FETCH_INST_OPCODE 2 %eax
+ UNSPILL(rIBASE)
+ SET_VREG %ecx rINST
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %eax
diff --git a/vm/mterp/x86/OP_IGET_JUMBO.S b/vm/mterp/x86/OP_IGET_JUMBO.S
index 580422f..da88f65 100644
--- a/vm/mterp/x86/OP_IGET_JUMBO.S
+++ b/vm/mterp/x86/OP_IGET_JUMBO.S
@@ -12,26 +12,22 @@
*/
/* exop vBBBB, vCCCC, field@AAAAAAAA */
movl rSELF,%ecx
- movl 2(rPC),%edx # edx<- AAAAAAAA
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ SPILL(rIBASE) # preserve rIBASE
+ movl 2(rPC),rIBASE # rIBASE<- AAAAAAAA
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
movzwl 8(rPC),%ecx # ecx<- CCCC
movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
+ movl (%eax,rIBASE,4),%eax # resolved entry
testl %eax,%eax # is resolved entry null?
jne .L${opcode}_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp) # needed by dvmResolveInstField
- movl rSELF,%edx
- jmp .L${opcode}_resolve
-%break
-
-
-.L${opcode}_resolve:
+ movl rIBASE,OUT_ARG1(%esp) # needed by dvmResolveInstField
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -49,8 +45,8 @@
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
$load (%ecx,%eax,1),%ecx # ecx<- obj.field (8/16/32 bits)
- movl rINST,%eax # eax<- BBBB
- FETCH_INST_OPCODE 5 %edx
- SET_VREG %ecx %eax
+ FETCH_INST_OPCODE 5 %eax
+ UNSPILL(rIBASE) # restore rIBASE
+ SET_VREG %ecx rINST
ADVANCE_PC 5
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %eax
diff --git a/vm/mterp/x86/OP_IGET_QUICK.S b/vm/mterp/x86/OP_IGET_QUICK.S
index 51a5937..86f1f66 100644
--- a/vm/mterp/x86/OP_IGET_QUICK.S
+++ b/vm/mterp/x86/OP_IGET_QUICK.S
@@ -9,8 +9,8 @@
cmpl $$0,%ecx # is object null?
je common_errNullObject
movl (%ecx,%eax,1),%eax
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
andb $$0xf,rINSTbl # rINST<- A
SET_VREG %eax rINST # fp[A]<- result
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_IGET_WIDE.S b/vm/mterp/x86/OP_IGET_WIDE.S
index f49fb5c..723c9b7 100644
--- a/vm/mterp/x86/OP_IGET_WIDE.S
+++ b/vm/mterp/x86/OP_IGET_WIDE.S
@@ -9,26 +9,22 @@
*/
/* op vA, vB, field@CCCC */
movl rSELF,%ecx
- movzwl 2(rPC),%edx # edx<- 0000CCCC
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ SPILL(rIBASE) # preserve rIBASE
+ movzwl 2(rPC),rIBASE # rIBASE<- 0000CCCC
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
movzbl rINSTbl,%ecx # ecx<- BA
sarl $$4,%ecx # ecx<- B
movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
andb $$0xf,rINSTbl # rINST<- A
GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
+ movl (%eax,rIBASE,4),%eax # resolved entry
testl %eax,%eax # is resolved entry null?
jne .L${opcode}_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp) # for dvmResolveInstField
- movl rSELF,%edx
- jmp .L${opcode}_resolve
-%break
-
-
-.L${opcode}_resolve:
+ movl rIBASE,OUT_ARG1(%esp) # for dvmResolveInstField
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save objpointer across call
movl rPC,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
@@ -50,8 +46,9 @@
leal (%ecx,%eax,1),%eax # eax<- address of field
movl (%eax),%ecx # ecx<- lsw
movl 4(%eax),%eax # eax<- msw
- FETCH_INST_OPCODE 2 %edx
SET_VREG_WORD %ecx rINST 0
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE) # restore rIBASE
SET_VREG_WORD %eax rINST 1
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_IGET_WIDE_JUMBO.S b/vm/mterp/x86/OP_IGET_WIDE_JUMBO.S
index c21b235..f20970f 100644
--- a/vm/mterp/x86/OP_IGET_WIDE_JUMBO.S
+++ b/vm/mterp/x86/OP_IGET_WIDE_JUMBO.S
@@ -8,24 +8,20 @@
*/
/* iget-wide/jumbo vBBBB, vCCCC, field@AAAA */
movl rSELF,%ecx
- movl 2(rPC),%edx # edx<- AAAAAAAA
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ SPILL(rIBASE) # preserve rIBASE
+ movl 2(rPC),rIBASE # rIBASE<- AAAAAAAA
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
movzwl 8(rPC),%ecx # ecx<- CCCC
movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
+ movl (%eax,rIBASE,4),%eax # resolved entry
testl %eax,%eax # is resolved entry null?
jne .L${opcode}_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp) # for dvmResolveInstField
- movl rSELF,%edx
- jmp .L${opcode}_resolve
-%break
-
-
-.L${opcode}_resolve:
+ movl rIBASE,OUT_ARG1(%esp) # for dvmResolveInstField
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save objpointer across call
movl rPC,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
@@ -47,8 +43,9 @@
leal (%ecx,%eax,1),%eax # eax<- address of field
movl (%eax),%ecx # ecx<- lsw
movl 4(%eax),%eax # eax<- msw
- FETCH_INST_OPCODE 5 %edx
SET_VREG_WORD %ecx rINST 0
+ FETCH_INST_OPCODE 5 %ecx
+ UNSPILL(rIBASE) # restore rIBASE
SET_VREG_WORD %eax rINST 1
ADVANCE_PC 5
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_IGET_WIDE_QUICK.S b/vm/mterp/x86/OP_IGET_WIDE_QUICK.S
index 3867eea..dd63c73 100644
--- a/vm/mterp/x86/OP_IGET_WIDE_QUICK.S
+++ b/vm/mterp/x86/OP_IGET_WIDE_QUICK.S
@@ -12,8 +12,8 @@
movl (%eax),%ecx # ecx<- lsw
movl 4(%eax),%eax # eax<- msw
andb $$0xf,rINSTbl # rINST<- A
- FETCH_INST_OPCODE 2 %edx
SET_VREG_WORD %ecx rINST 0 # v[A+0]<- lsw
+ FETCH_INST_OPCODE 2 %ecx
SET_VREG_WORD %eax rINST 1 # v[A+1]<- msw
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_INSTANCE_OF.S b/vm/mterp/x86/OP_INSTANCE_OF.S
index 4139056..c54f4f7 100644
--- a/vm/mterp/x86/OP_INSTANCE_OF.S
+++ b/vm/mterp/x86/OP_INSTANCE_OF.S
@@ -12,32 +12,29 @@
* an already-resolved class.
*/
/* instance-of vA, vB, class@CCCC */
- movl rINST,%eax # eax<- BA
+ movl rINST,%eax # eax<- BA
sarl $$4,%eax # eax<- B
GET_VREG_R %eax %eax # eax<- vB (obj)
movl rSELF,%ecx
testl %eax,%eax # object null?
movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
+ SPILL(rIBASE) # preserve rIBASE
je .L${opcode}_store # null obj, not instance, store it
- movzwl 2(rPC),%edx # edx<- CCCC
+ movzwl 2(rPC),rIBASE # rIBASE<- CCCC
movl offDvmDex_pResClasses(%ecx),%ecx # ecx<- pDvmDex->pResClasses
- movl (%ecx,%edx,4),%ecx # ecx<- resolved class
+ movl (%ecx,rIBASE,4),%ecx # ecx<- resolved class
movl offObject_clazz(%eax),%eax # eax<- obj->clazz
testl %ecx,%ecx # have we resolved this before?
je .L${opcode}_resolve # not resolved, do it now
.L${opcode}_resolved: # eax<- obj->clazz, ecx<- resolved class
cmpl %eax,%ecx # same class (trivial success)?
je .L${opcode}_trivial # yes, trivial finish
- jmp .L${opcode}_fullcheck # no, do full check
-%break
-
/*
* Trivial test failed, need to perform full check. This is common.
* eax holds obj->clazz
* ecx holds class resolved from BBBB
* rINST has BA
*/
-.L${opcode}_fullcheck:
movl %eax,OUT_ARG0(%esp)
movl %ecx,OUT_ARG1(%esp)
call dvmInstanceofNonTrivial # eax<- boolean result
@@ -48,32 +45,34 @@
* rINST holds BA
*/
.L${opcode}_store:
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
andb $$0xf,rINSTbl # <- A
ADVANCE_PC 2
SET_VREG %eax rINST # vA<- eax
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
/*
* Trivial test succeeded, save and bail.
* r9 holds A
*/
.L${opcode}_trivial:
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
andb $$0xf,rINSTbl # <- A
ADVANCE_PC 2
movl $$1,%eax
SET_VREG %eax rINST # vA<- true
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
/*
* Resolution required. This is the least-likely path.
*
- * edx holds BBBB
+ * rIBASE holds BBBB
* rINST holds BA
*/
.L${opcode}_resolve:
- movl %edx,OUT_ARG1(%esp) # arg1<- BBBB
+ movl rIBASE,OUT_ARG1(%esp) # arg1<- BBBB
movl rSELF,%ecx
movl offThread_method(%ecx),%ecx
movl $$1,OUT_ARG2(%esp) # arg2<- true
@@ -87,7 +86,7 @@
* hold the obj->clazz, and ecx to hold the resolved class
*/
movl %eax,%ecx # ecx<- resolved class
- movl rINST,%eax # eax<- BA
+ movl rINST,%eax # eax<- BA
sarl $$4,%eax # eax<- B
GET_VREG_R %eax %eax # eax<- vB (obj)
movl offObject_clazz(%eax),%eax # eax<- obj->clazz
diff --git a/vm/mterp/x86/OP_INSTANCE_OF_JUMBO.S b/vm/mterp/x86/OP_INSTANCE_OF_JUMBO.S
index 2888c76..590277e 100644
--- a/vm/mterp/x86/OP_INSTANCE_OF_JUMBO.S
+++ b/vm/mterp/x86/OP_INSTANCE_OF_JUMBO.S
@@ -17,26 +17,23 @@
movl rSELF,%ecx
testl %eax,%eax # object null?
movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
+ SPILL(rIBASE) # preserve rIBASE
je .L${opcode}_store # null obj, not instance, store it
- movl 2(rPC),%edx # edx<- AAAAAAAA
+ movl 2(rPC),rIBASE # edx<- AAAAAAAA
movl offDvmDex_pResClasses(%ecx),%ecx # ecx<- pDvmDex->pResClasses
- movl (%ecx,%edx,4),%ecx # ecx<- resolved class
+ movl (%ecx,rIBASE,4),%ecx # ecx<- resolved class
movl offObject_clazz(%eax),%eax # eax<- obj->clazz
testl %ecx,%ecx # have we resolved this before?
je .L${opcode}_resolve # not resolved, do it now
.L${opcode}_resolved: # eax<- obj->clazz, ecx<- resolved class
cmpl %eax,%ecx # same class (trivial success)?
je .L${opcode}_trivial # yes, trivial finish
- jmp .L${opcode}_fullcheck # no, do full check
-%break
-
/*
* Trivial test failed, need to perform full check. This is common.
* eax holds obj->clazz
* ecx holds class resolved from BBBB
* rINST has BA
*/
-.L${opcode}_fullcheck:
movl %eax,OUT_ARG0(%esp)
movl %ecx,OUT_ARG1(%esp)
call dvmInstanceofNonTrivial # eax<- boolean result
@@ -47,21 +44,23 @@
* rINST holds BBBB
*/
.L${opcode}_store:
- FETCH_INST_OPCODE 5 %edx
+ FETCH_INST_OPCODE 5 %ecx
+ UNSPILL(rIBASE)
ADVANCE_PC 5
SET_VREG %eax rINST # vBBBB<- eax
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
/*
* Trivial test succeeded, save and bail.
* r9 holds BBBB
*/
.L${opcode}_trivial:
- FETCH_INST_OPCODE 5 %edx
+ FETCH_INST_OPCODE 5 %ecx
+ UNSPILL(rIBASE)
ADVANCE_PC 5
movl $$1,%eax
SET_VREG %eax rINST # vBBBB<- true
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
/*
* Resolution required. This is the least-likely path.
@@ -69,7 +68,7 @@
* edx holds AAAAAAAA
*/
.L${opcode}_resolve:
- movl %edx,OUT_ARG1(%esp) # arg1<- AAAAAAAA
+ movl rIBASE,OUT_ARG1(%esp) # arg1<- AAAAAAAA
movl rSELF,%ecx
movl offThread_method(%ecx),%ecx
movl $$1,OUT_ARG2(%esp) # arg2<- true
diff --git a/vm/mterp/x86/OP_INT_TO_LONG.S b/vm/mterp/x86/OP_INT_TO_LONG.S
index 6d5d0aa..551efaf 100644
--- a/vm/mterp/x86/OP_INT_TO_LONG.S
+++ b/vm/mterp/x86/OP_INT_TO_LONG.S
@@ -4,9 +4,11 @@
sarl $$4,%eax # eax<- B
GET_VREG_R %eax %eax # eax<- vB
andb $$0xf,rINSTbl # rINST<- A
- cltd # edx:eax<- sssssssBBBBBBBB
- SET_VREG_WORD %edx rINST 1 # v[A+1]<- edx/rPC
- FETCH_INST_OPCODE 1 %edx
+ SPILL(rIBASE) # cltd trashes rIBASE/edx
+ cltd # rINST:eax<- sssssssBBBBBBBB
+ SET_VREG_WORD rIBASE rINST 1 # v[A+1]<- rIBASE/rPC
+ FETCH_INST_OPCODE 1 %ecx
+ UNSPILL(rIBASE)
SET_VREG_WORD %eax rINST 0 # v[A+0]<- %eax
ADVANCE_PC 1
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_INVOKE_DIRECT.S b/vm/mterp/x86/OP_INVOKE_DIRECT.S
index 9070228..7d27c6f 100644
--- a/vm/mterp/x86/OP_INVOKE_DIRECT.S
+++ b/vm/mterp/x86/OP_INVOKE_DIRECT.S
@@ -18,19 +18,18 @@
movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
EXPORT_PC
movl offDvmDex_pResMethods(%ecx),%ecx # ecx<- pDvmDex->pResMethods
- movzwl 4(rPC),%edx # edx<- GFED or CCCC
+ movzwl 4(rPC),rIBASE # rIBASE<- GFED or CCCC
movl (%ecx,%eax,4),%eax # eax<- resolved methodToCall
.if (!$isrange)
- andl $$0xf,%edx # edx<- D (or stays CCCC)
+ andl $$0xf,rIBASE # rIBASE<- D (or stays CCCC)
.endif
testl %eax,%eax # already resolved?
- GET_VREG_R %ecx %edx # ecx<- "this" ptr
+ GET_VREG_R %ecx rIBASE # ecx<- "this" ptr
je .L${opcode}_resolve # not resolved, do it now
.L${opcode}_finish:
testl %ecx,%ecx # null "this"?
jne common_invokeMethod${routine} # no, continue on
jmp common_errNullObject
-%break
/*
* On entry:
diff --git a/vm/mterp/x86/OP_INVOKE_DIRECT_JUMBO.S b/vm/mterp/x86/OP_INVOKE_DIRECT_JUMBO.S
index 1040775..b1576c5 100644
--- a/vm/mterp/x86/OP_INVOKE_DIRECT_JUMBO.S
+++ b/vm/mterp/x86/OP_INVOKE_DIRECT_JUMBO.S
@@ -14,16 +14,15 @@
movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
EXPORT_PC
movl offDvmDex_pResMethods(%ecx),%ecx # ecx<- pDvmDex->pResMethods
- movzwl 8(rPC),%edx # edx<- CCCC
+ movzwl 8(rPC),rIBASE # rIBASE<- CCCC
movl (%ecx,%eax,4),%eax # eax<- resolved methodToCall
testl %eax,%eax # already resolved?
- GET_VREG_R %ecx %edx # ecx<- "this" ptr
+ GET_VREG_R %ecx rIBASE # ecx<- "this" ptr
je .L${opcode}_resolve # not resolved, do it now
.L${opcode}_finish:
testl %ecx,%ecx # null "this"?
jne common_invokeMethodJumbo # no, continue on
jmp common_errNullObject
-%break
/*
* On entry:
diff --git a/vm/mterp/x86/OP_INVOKE_INTERFACE.S b/vm/mterp/x86/OP_INVOKE_INTERFACE.S
index 1e2032d..3fa4c94 100644
--- a/vm/mterp/x86/OP_INVOKE_INTERFACE.S
+++ b/vm/mterp/x86/OP_INVOKE_INTERFACE.S
@@ -26,10 +26,6 @@
movzwl 2(rPC),%eax # eax<- BBBB
movl %ecx,OUT_ARG2(%esp) # arg2<- method
movl %eax,OUT_ARG1(%esp) # arg1<- BBBB
- jmp .L${opcode}_continue
-%break
-
-.L${opcode}_continue:
call dvmFindInterfaceMethodInCache # eax<- call(class, ref, method, dex)
testl %eax,%eax
je common_exceptionThrown
diff --git a/vm/mterp/x86/OP_INVOKE_INTERFACE_JUMBO.S b/vm/mterp/x86/OP_INVOKE_INTERFACE_JUMBO.S
index 7da63b8..ee0ecdb 100644
--- a/vm/mterp/x86/OP_INVOKE_INTERFACE_JUMBO.S
+++ b/vm/mterp/x86/OP_INVOKE_INTERFACE_JUMBO.S
@@ -19,10 +19,6 @@
movl 2(rPC),%eax # eax<- AAAAAAAA
movl %ecx,OUT_ARG2(%esp) # arg2<- method
movl %eax,OUT_ARG1(%esp) # arg1<- AAAAAAAA
- jmp .L${opcode}_continue
-%break
-
-.L${opcode}_continue:
call dvmFindInterfaceMethodInCache # eax<- call(class, ref, method, dex)
testl %eax,%eax
je common_exceptionThrown
diff --git a/vm/mterp/x86/OP_INVOKE_STATIC.S b/vm/mterp/x86/OP_INVOKE_STATIC.S
index d677f2b..ca68a84 100644
--- a/vm/mterp/x86/OP_INVOKE_STATIC.S
+++ b/vm/mterp/x86/OP_INVOKE_STATIC.S
@@ -22,10 +22,6 @@
movl offMethod_clazz(%ecx),%ecx# ecx<- method->clazz
movl %eax,OUT_ARG1(%esp) # arg1<- BBBB
movl %ecx,OUT_ARG0(%esp) # arg0<- clazz
- jmp .L${opcode}_continue
-%break
-
-.L${opcode}_continue:
movl $$METHOD_STATIC,%eax
movl %eax,OUT_ARG2(%esp) # arg2<- flags
call dvmResolveMethod # call(clazz,ref,flags)
diff --git a/vm/mterp/x86/OP_INVOKE_STATIC_JUMBO.S b/vm/mterp/x86/OP_INVOKE_STATIC_JUMBO.S
index 80496d6..1f98d3d 100644
--- a/vm/mterp/x86/OP_INVOKE_STATIC_JUMBO.S
+++ b/vm/mterp/x86/OP_INVOKE_STATIC_JUMBO.S
@@ -18,10 +18,6 @@
movl offMethod_clazz(%ecx),%ecx# ecx<- method->clazz
movl %eax,OUT_ARG1(%esp) # arg1<- AAAAAAAA
movl %ecx,OUT_ARG0(%esp) # arg0<- clazz
- jmp .L${opcode}_continue
-%break
-
-.L${opcode}_continue:
movl $$METHOD_STATIC,%eax
movl %eax,OUT_ARG2(%esp) # arg2<- flags
call dvmResolveMethod # call(clazz,ref,flags)
diff --git a/vm/mterp/x86/OP_INVOKE_SUPER.S b/vm/mterp/x86/OP_INVOKE_SUPER.S
index 02ec6f4..c8ca2e1 100644
--- a/vm/mterp/x86/OP_INVOKE_SUPER.S
+++ b/vm/mterp/x86/OP_INVOKE_SUPER.S
@@ -24,10 +24,7 @@
je common_errNullObject # yes, throw
movl offMethod_clazz(%eax),%eax # eax<- method->clazz
testl %ecx,%ecx # already resolved?
- jne .L${opcode}_continue # yes - go on
- jmp .L${opcode}_resolve
-%break
-
+ je .L${opcode}_resolve
/*
* At this point:
* ecx = resolved base method [r0]
diff --git a/vm/mterp/x86/OP_INVOKE_SUPER_JUMBO.S b/vm/mterp/x86/OP_INVOKE_SUPER_JUMBO.S
index 631aa3c..b090963 100644
--- a/vm/mterp/x86/OP_INVOKE_SUPER_JUMBO.S
+++ b/vm/mterp/x86/OP_INVOKE_SUPER_JUMBO.S
@@ -17,10 +17,7 @@
je common_errNullObject # yes, throw
movl offMethod_clazz(%eax),%eax # eax<- method->clazz
testl %ecx,%ecx # already resolved?
- jne .L${opcode}_continue # yes - go on
- jmp .L${opcode}_resolve
-%break
-
+ je .L${opcode}_resolve
/*
* At this point:
* ecx = resolved base method [r0]
diff --git a/vm/mterp/x86/OP_INVOKE_VIRTUAL.S b/vm/mterp/x86/OP_INVOKE_VIRTUAL.S
index 63ecb18..24d0170 100644
--- a/vm/mterp/x86/OP_INVOKE_VIRTUAL.S
+++ b/vm/mterp/x86/OP_INVOKE_VIRTUAL.S
@@ -21,11 +21,6 @@
movl rSELF,%eax
movl %ecx,OUT_ARG1(%esp) # arg1<- ref
movl offThread_method(%eax),%eax # eax<- self->method
- jmp .L${opcode}_more
-%break
-
-
-.L${opcode}_more:
movl offMethod_clazz(%eax),%eax # ecx<- method->clazz
movl %eax,OUT_ARG0(%esp) # arg0<- clazz
movl $$METHOD_VIRTUAL,OUT_ARG2(%esp) # arg2<- flags
diff --git a/vm/mterp/x86/OP_INVOKE_VIRTUAL_JUMBO.S b/vm/mterp/x86/OP_INVOKE_VIRTUAL_JUMBO.S
index 6d73151..085b591 100644
--- a/vm/mterp/x86/OP_INVOKE_VIRTUAL_JUMBO.S
+++ b/vm/mterp/x86/OP_INVOKE_VIRTUAL_JUMBO.S
@@ -16,11 +16,6 @@
movl rSELF,%eax
movl %ecx,OUT_ARG1(%esp) # arg1<- ref
movl offThread_method(%eax),%eax # eax<- self->method
- jmp .L${opcode}_more
-%break
-
-
-.L${opcode}_more:
movl offMethod_clazz(%eax),%eax # ecx<- method->clazz
movl %eax,OUT_ARG0(%esp) # arg0<- clazz
movl $$METHOD_VIRTUAL,OUT_ARG2(%esp) # arg2<- flags
diff --git a/vm/mterp/x86/OP_IPUT.S b/vm/mterp/x86/OP_IPUT.S
index ec8a780..2c718b2 100644
--- a/vm/mterp/x86/OP_IPUT.S
+++ b/vm/mterp/x86/OP_IPUT.S
@@ -12,28 +12,24 @@
*/
/* op vA, vB, field@CCCC */
movl rSELF,%ecx
- movzwl 2(rPC),%edx # %edx<- 0000CCCC
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ SPILL (rIBASE)
+ movzwl 2(rPC),rIBASE # rIBASE<- 0000CCCC
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
movzbl rINSTbl,%ecx # ecx<- BA
sarl $$4,%ecx # ecx<- B
movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
andb $$0xf,rINSTbl # rINST<- A
GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
+ movl (%eax,rIBASE,4),%eax # resolved entry
testl %eax,%eax # is resolved entry null?
jne .L${opcode}_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp)
- movl rSELF,%edx
- jmp .L${opcode}_resolve
-%break
-
-
-.L${opcode}_resolve:
+ movl rIBASE,OUT_ARG1(%esp)
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -51,7 +47,8 @@
movl offInstField_byteOffset(%eax),%eax # eax<- byte offset of field
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
- FETCH_INST_OPCODE 2 %edx
$store $reg,(%ecx,%eax,1) # obj.field <- v[A](8/16/32 bits)
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_IPUT_JUMBO.S b/vm/mterp/x86/OP_IPUT_JUMBO.S
index b01cd8c..474cac5 100644
--- a/vm/mterp/x86/OP_IPUT_JUMBO.S
+++ b/vm/mterp/x86/OP_IPUT_JUMBO.S
@@ -12,26 +12,22 @@
*/
/* exop vBBBB, vCCCC, field@AAAAAAAA */
movl rSELF,%ecx
- movl 2(rPC),%edx # edx<- AAAAAAAA
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ SPILL(rIBASE)
+ movl 2(rPC),rIBASE # rIBASE<- AAAAAAAA
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
movzwl 8(rPC),%ecx # ecx<- CCCC
movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
+ movl (%eax,rIBASE,4),%eax # resolved entry
testl %eax,%eax # is resolved entry null?
jne .L${opcode}_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp)
- movl rSELF,%edx
- jmp .L${opcode}_resolve
-%break
-
-
-.L${opcode}_resolve:
+ movl rIBASE,OUT_ARG1(%esp)
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -49,7 +45,8 @@
movl offInstField_byteOffset(%eax),%eax # eax<- byte offset of field
testl %ecx,%ecx # object null?
je common_errNullObject # object was null
- FETCH_INST_OPCODE 5 %edx
$store $reg,(%ecx,%eax,1) # obj.field <- v[BBBB](8/16/32 bits)
+ FETCH_INST_OPCODE 5 %ecx
+ UNSPILL(rIBASE)
ADVANCE_PC 5
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_IPUT_OBJECT.S b/vm/mterp/x86/OP_IPUT_OBJECT.S
index 65aa186..6c9fd6e 100644
--- a/vm/mterp/x86/OP_IPUT_OBJECT.S
+++ b/vm/mterp/x86/OP_IPUT_OBJECT.S
@@ -11,28 +11,24 @@
*/
/* op vA, vB, field@CCCC */
movl rSELF,%ecx
- movzwl 2(rPC),%edx # edx<- 0000CCCC
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ SPILL(rIBASE)
+ movzwl 2(rPC),rIBASE # rIBASE<- 0000CCCC
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
movzbl rINSTbl,%ecx # ecx<- BA
sarl $$4,%ecx # ecx<- B
movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
andb $$0xf,rINSTbl # rINST<- A
GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
+ movl (%eax,rIBASE,4),%eax # resolved entry
testl %eax,%eax # is resolved entry null?
jne .L${opcode}_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp)
- movl rSELF,%edx
- jmp .L${opcode}_resolve
-%break
-
-
-.L${opcode}_resolve:
+ movl rIBASE,OUT_ARG1(%esp)
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -44,7 +40,7 @@
* Currently:
* eax holds resolved field
* ecx holds object
- * %edx is scratch, but needs to be unspilled
+ * rIBASE is scratch, but needs to be unspilled
* rINST holds A
*/
GET_VREG_R rINST rINST # rINST<- v[A]
@@ -54,11 +50,12 @@
movl rINST,(%ecx,%eax) # obj.field <- v[A](8/16/32 bits)
movl rSELF,%eax
testl rINST,rINST # stored a NULL?
- movl offThread_cardTable(%eax),%eax # get card table base
- FETCH_INST_OPCODE 2 %edx
+ movl offThread_cardTable(%eax),%eax # get card table base
je 1f # skip card mark if null store
shrl $$GC_CARD_SHIFT,%ecx # object head to card number
movb %al,(%eax,%ecx) # mark card using object head
1:
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_IPUT_OBJECT_JUMBO.S b/vm/mterp/x86/OP_IPUT_OBJECT_JUMBO.S
index 7b6589f..c699595 100644
--- a/vm/mterp/x86/OP_IPUT_OBJECT_JUMBO.S
+++ b/vm/mterp/x86/OP_IPUT_OBJECT_JUMBO.S
@@ -9,26 +9,22 @@
*/
/* iput-object/jumbo vBBBB, vCCCC, field@AAAAAAAA */
movl rSELF,%ecx
- movl 2(rPC),%edx # edx<- AAAAAAAA
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ SPILL(rIBASE)
+ movl 2(rPC),rIBASE # rIBASE<- AAAAAAAA
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
movzwl 8(rPC),%ecx # ecx<- CCCC
movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
+ movl (%eax,rIBASE,4),%eax # resolved entry
testl %eax,%eax # is resolved entry null?
jne .L${opcode}_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp)
- movl rSELF,%edx
- jmp .L${opcode}_resolve
-%break
-
-
-.L${opcode}_resolve:
+ movl rIBASE,OUT_ARG1(%esp)
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # returns InstrField ptr
@@ -40,7 +36,7 @@
* Currently:
* eax holds resolved field
* ecx holds object
- * %edx is scratch, but needs to be unspilled
+ * rIBASE is scratch, but needs to be unspilled
* rINST holds BBBB
*/
GET_VREG_R rINST rINST # rINST<- v[BBBB]
@@ -50,11 +46,12 @@
movl rINST,(%ecx,%eax) # obj.field <- v[BBBB](8/16/32 bits)
movl rSELF,%eax
testl rINST,rINST # stored a NULL?
- movl offThread_cardTable(%eax),%eax # get card table base
- FETCH_INST_OPCODE 5 %edx
+ movl offThread_cardTable(%eax),%eax # get card table base
je 1f # skip card mark if null store
shrl $$GC_CARD_SHIFT,%ecx # object head to card number
movb %al,(%eax,%ecx) # mark card using object head
1:
+ FETCH_INST_OPCODE 5 %ecx
+ UNSPILL(rIBASE)
ADVANCE_PC 5
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_IPUT_OBJECT_QUICK.S b/vm/mterp/x86/OP_IPUT_OBJECT_QUICK.S
index 8f5db6f..b628e57 100644
--- a/vm/mterp/x86/OP_IPUT_OBJECT_QUICK.S
+++ b/vm/mterp/x86/OP_IPUT_OBJECT_QUICK.S
@@ -12,16 +12,12 @@
je common_errNullObject
movl rINST,(%ecx,%eax,1)
movl rSELF,%eax
- jmp .L${opcode}_finish
-%break
-
-.L${opcode}_finish:
testl rINST,rINST # did we store null?
- FETCH_INST_OPCODE 2 %edx
movl offThread_cardTable(%eax),%eax # get card table base
je 1f # skip card mark if null store
shrl $$GC_CARD_SHIFT,%ecx # object head to card number
movb %al,(%eax,%ecx) # mark card based on object head
1:
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_IPUT_QUICK.S b/vm/mterp/x86/OP_IPUT_QUICK.S
index 6cec0d1..cd4fe3b 100644
--- a/vm/mterp/x86/OP_IPUT_QUICK.S
+++ b/vm/mterp/x86/OP_IPUT_QUICK.S
@@ -9,8 +9,8 @@
GET_VREG_R rINST,rINST # rINST<- v[A]
movzwl 2(rPC),%eax # eax<- field byte offset
testl %ecx,%ecx # is object null?
- FETCH_INST_OPCODE 2 %edx
je common_errNullObject
movl rINST,(%ecx,%eax,1)
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_IPUT_WIDE.S b/vm/mterp/x86/OP_IPUT_WIDE.S
index 8c8b465..d481d02 100644
--- a/vm/mterp/x86/OP_IPUT_WIDE.S
+++ b/vm/mterp/x86/OP_IPUT_WIDE.S
@@ -9,28 +9,24 @@
*/
/* op vA, vB, field@CCCC */
movl rSELF,%ecx
- movzwl 2(rPC),%edx # edx<- 0000CCCC
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ SPILL(rIBASE)
+ movzwl 2(rPC),rIBASE # rIBASE<- 0000CCCC
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
movzbl rINSTbl,%ecx # ecx<- BA
sarl $$4,%ecx # ecx<- B
movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
andb $$0xf,rINSTbl # rINST<- A
GET_VREG_R %ecx %ecx # ecx<- fp[B], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
+ movl (%eax,rIBASE,4),%eax # resolved entry
testl %eax,%eax # is resolved entry null?
jne .L${opcode}_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp)
- movl rSELF,%edx
- jmp .L${opcode}_resolve
-%break
-
-
-.L${opcode}_resolve:
+ movl rIBASE,OUT_ARG1(%esp)
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # ... which returns InstrField ptr
@@ -42,7 +38,7 @@
* Currently:
* eax holds resolved field
* ecx holds object
- * %edx is scratch, but needs to be unspilled
+ * rIBASE is scratch, but needs to be unspilled
* rINST holds A
*/
movl offInstField_byteOffset(%eax),%eax # eax<- byte offset of field
@@ -51,8 +47,9 @@
leal (%ecx,%eax,1),%eax # eax<- address of field
GET_VREG_WORD %ecx rINST 0 # ecx<- lsw
GET_VREG_WORD rINST rINST 1 # rINST<- msw
- FETCH_INST_OPCODE 2 %edx
movl rINST,4(%eax)
movl %ecx,(%eax)
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_IPUT_WIDE_JUMBO.S b/vm/mterp/x86/OP_IPUT_WIDE_JUMBO.S
index 37495d2..38c40b1 100644
--- a/vm/mterp/x86/OP_IPUT_WIDE_JUMBO.S
+++ b/vm/mterp/x86/OP_IPUT_WIDE_JUMBO.S
@@ -8,26 +8,22 @@
*/
/* iput-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */
movl rSELF,%ecx
- movl 2(rPC),%edx # edx<- AAAAAAAA
- movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
+ SPILL(rIBASE)
+ movl 2(rPC),rIBASE # rIBASE<- AAAAAAAA
+ movl offThread_methodClassDex(%ecx),%eax # eax<- DvmDex
movzwl 8(rPC),%ecx # ecx<- CCCC
movl offDvmDex_pResFields(%eax),%eax # eax<- pDvmDex->pResFields
GET_VREG_R %ecx %ecx # ecx<- fp[CCCC], the object ptr
- movl (%eax,%edx,4),%eax # resolved entry
+ movl (%eax,rIBASE,4),%eax # resolved entry
testl %eax,%eax # is resolved entry null?
jne .L${opcode}_finish # no, already resolved
- movl %edx,OUT_ARG1(%esp)
- movl rSELF,%edx
- jmp .L${opcode}_resolve
-%break
-
-
-.L${opcode}_resolve:
+ movl rIBASE,OUT_ARG1(%esp)
+ movl rSELF,rIBASE
EXPORT_PC
- movl offThread_method(%edx),%edx # edx<- current method
- movl offMethod_clazz(%edx),%edx # edx<- method->clazz
+ movl offThread_method(rIBASE),rIBASE # rIBASE<- current method
+ movl offMethod_clazz(rIBASE),rIBASE # rIBASE<- method->clazz
SPILL_TMP1(%ecx) # save obj pointer across call
- movl %edx,OUT_ARG0(%esp) # pass in method->clazz
+ movl rIBASE,OUT_ARG0(%esp) # pass in method->clazz
call dvmResolveInstField # ... to dvmResolveInstField
UNSPILL_TMP1(%ecx)
testl %eax,%eax # ... which returns InstrField ptr
@@ -39,7 +35,7 @@
* Currently:
* eax holds resolved field
* ecx holds object
- * %edx is scratch, but needs to be unspilled
+ * rIBASE is scratch, but needs to be unspilled
* rINST holds BBBB
*/
movl offInstField_byteOffset(%eax),%eax # eax<- byte offset of field
@@ -48,8 +44,9 @@
leal (%ecx,%eax,1),%eax # eax<- address of field
GET_VREG_WORD %ecx rINST 0 # ecx<- lsw
GET_VREG_WORD rINST rINST 1 # rINST<- msw
- FETCH_INST_OPCODE 5 %edx
movl rINST,4(%eax)
movl %ecx,(%eax)
+ FETCH_INST_OPCODE 5 %ecx
+ UNSPILL(rIBASE)
ADVANCE_PC 5
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_IPUT_WIDE_QUICK.S b/vm/mterp/x86/OP_IPUT_WIDE_QUICK.S
index 63bf89a..12eeed6 100644
--- a/vm/mterp/x86/OP_IPUT_WIDE_QUICK.S
+++ b/vm/mterp/x86/OP_IPUT_WIDE_QUICK.S
@@ -12,8 +12,8 @@
andb $$0xf,rINSTbl # rINST<- A
GET_VREG_WORD %eax rINST 0 # eax<- lsw
GET_VREG_WORD rINST rINST 1 # rINST<- msw
- FETCH_INST_OPCODE 2 %edx
movl %eax,(%ecx)
movl rINST,4(%ecx)
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_MONITOR_ENTER.S b/vm/mterp/x86/OP_MONITOR_ENTER.S
index aa8d105..a630db1 100644
--- a/vm/mterp/x86/OP_MONITOR_ENTER.S
+++ b/vm/mterp/x86/OP_MONITOR_ENTER.S
@@ -9,13 +9,12 @@
FETCH_INST_WORD 1
testl %eax,%eax # null object?
EXPORT_PC # need for precise GC
- jne .L${opcode}_continue
- jmp common_errNullObject
-%break
-
-.L${opcode}_continue:
+ je common_errNullObject
movl %ecx,OUT_ARG0(%esp)
movl %eax,OUT_ARG1(%esp)
+ SPILL(rIBASE)
call dvmLockObject # dvmLockObject(self,object)
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 1 %ecx
ADVANCE_PC 1
- GOTO_NEXT
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_MONITOR_EXIT.S b/vm/mterp/x86/OP_MONITOR_EXIT.S
index 4e4c0b4..98bc373 100644
--- a/vm/mterp/x86/OP_MONITOR_EXIT.S
+++ b/vm/mterp/x86/OP_MONITOR_EXIT.S
@@ -16,16 +16,14 @@
je .L${opcode}_errNullObject # go if so
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
- jmp .L${opcode}_continue
-%break
-
-.L${opcode}_continue:
+ SPILL(rIBASE)
call dvmUnlockObject # unlock(self,obj)
- FETCH_INST_OPCODE 1 %edx
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 1 %ecx
testl %eax,%eax # success?
ADVANCE_PC 1
je common_exceptionThrown # no, exception pending
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
.L${opcode}_errNullObject:
ADVANCE_PC 1 # advance before throw
jmp common_errNullObject
diff --git a/vm/mterp/x86/OP_MOVE.S b/vm/mterp/x86/OP_MOVE.S
index 0953bec..ec05288 100644
--- a/vm/mterp/x86/OP_MOVE.S
+++ b/vm/mterp/x86/OP_MOVE.S
@@ -4,8 +4,8 @@
movzbl rINSTbl,%eax # eax<- BA
andb $$0xf,%al # eax<- A
shrl $$4,rINST # rINST<- B
- GET_VREG_R %ecx rINST
- FETCH_INST_OPCODE 1 %edx
+ GET_VREG_R rINST rINST
+ FETCH_INST_OPCODE 1 %ecx
ADVANCE_PC 1
- SET_VREG %ecx %eax # fp[A]<-fp[B]
- GOTO_NEXT_R %edx
+ SET_VREG rINST %eax # fp[A]<-fp[B]
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_MOVE_16.S b/vm/mterp/x86/OP_MOVE_16.S
index 6554135..e25230a 100644
--- a/vm/mterp/x86/OP_MOVE_16.S
+++ b/vm/mterp/x86/OP_MOVE_16.S
@@ -3,8 +3,8 @@
/* op vAAAA, vBBBB */
movzwl 4(rPC),%ecx # ecx<- BBBB
movzwl 2(rPC),%eax # eax<- AAAA
- GET_VREG_R %ecx %ecx
- FETCH_INST_OPCODE 3 %edx
+ GET_VREG_R rINST %ecx
+ FETCH_INST_OPCODE 3 %ecx
ADVANCE_PC 3
- SET_VREG %ecx %eax
- GOTO_NEXT_R %edx
+ SET_VREG rINST %eax
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_MOVE_EXCEPTION.S b/vm/mterp/x86/OP_MOVE_EXCEPTION.S
index 0aeb443..0853866 100644
--- a/vm/mterp/x86/OP_MOVE_EXCEPTION.S
+++ b/vm/mterp/x86/OP_MOVE_EXCEPTION.S
@@ -3,7 +3,7 @@
movl rSELF,%ecx
movl offThread_exception(%ecx),%eax # eax<- dvmGetException bypass
SET_VREG %eax rINST # fp[AA]<- exception object
- FETCH_INST_OPCODE 1 %edx
+ FETCH_INST_OPCODE 1 %eax
ADVANCE_PC 1
movl $$0,offThread_exception(%ecx) # dvmClearException bypass
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %eax
diff --git a/vm/mterp/x86/OP_MOVE_FROM16.S b/vm/mterp/x86/OP_MOVE_FROM16.S
index 3c99c55..120edb5 100644
--- a/vm/mterp/x86/OP_MOVE_FROM16.S
+++ b/vm/mterp/x86/OP_MOVE_FROM16.S
@@ -3,8 +3,8 @@
/* op vAA, vBBBB */
movzx rINSTbl,%eax # eax <= AA
movw 2(rPC),rINSTw # rINSTw <= BBBB
- GET_VREG_R %ecx rINST # ecx<- fp[BBBB]
- FETCH_INST_OPCODE 2 %edx
+ GET_VREG_R rINST rINST # rINST- fp[BBBB]
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- SET_VREG %ecx %eax # fp[AA]<- ecx]
- GOTO_NEXT_R %edx
+ SET_VREG rINST %eax # fp[AA]<- ecx]
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_MOVE_RESULT.S b/vm/mterp/x86/OP_MOVE_RESULT.S
index 4c01e2d..4a6917b 100644
--- a/vm/mterp/x86/OP_MOVE_RESULT.S
+++ b/vm/mterp/x86/OP_MOVE_RESULT.S
@@ -2,9 +2,8 @@
/* for: move-result, move-result-object */
/* op vAA */
movl rSELF,%eax # eax<- rSELF
- movzx rINSTbl,%ecx # ecx<- AA
- movl offThread_retval(%eax),%eax # eax<- self->retval.l
- FETCH_INST_OPCODE 1 %edx
+ movl offThread_retval(%eax),%eax # eax<- self->retval.l
+ FETCH_INST_OPCODE 1 %ecx
ADVANCE_PC 1
- SET_VREG %eax %ecx # fp[AA]<- retval.l
- GOTO_NEXT_R %edx
+ SET_VREG %eax rINST # fp[AA]<- retval.l
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_MOVE_RESULT_WIDE.S b/vm/mterp/x86/OP_MOVE_RESULT_WIDE.S
index 13e2f16..022bdb3 100644
--- a/vm/mterp/x86/OP_MOVE_RESULT_WIDE.S
+++ b/vm/mterp/x86/OP_MOVE_RESULT_WIDE.S
@@ -3,8 +3,8 @@
movl rSELF,%ecx
movl offThread_retval(%ecx),%eax
movl 4+offThread_retval(%ecx),%ecx
- FETCH_INST_OPCODE 1 %edx
SET_VREG_WORD %eax rINST 0 # v[AA+0] <- eax
SET_VREG_WORD %ecx rINST 1 # v[AA+1] <- ecx
+ FETCH_INST_OPCODE 1 %ecx
ADVANCE_PC 1
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_MOVE_WIDE.S b/vm/mterp/x86/OP_MOVE_WIDE.S
index 2d89e3b..df59574 100644
--- a/vm/mterp/x86/OP_MOVE_WIDE.S
+++ b/vm/mterp/x86/OP_MOVE_WIDE.S
@@ -6,8 +6,8 @@
GET_VREG_WORD %eax rINST 0 # eax<- v[B+0]
GET_VREG_WORD rINST rINST 1 # rINST<- v[B+1]
andb $$0xf,%cl # ecx <- A
- FETCH_INST_OPCODE 1 %edx
SET_VREG_WORD rINST %ecx 1 # v[A+1]<- rINST
- ADVANCE_PC 1
SET_VREG_WORD %eax %ecx 0 # v[A+0]<- eax
- GOTO_NEXT_R %edx
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_MOVE_WIDE_16.S b/vm/mterp/x86/OP_MOVE_WIDE_16.S
index 4cec42c..26ea8a4 100644
--- a/vm/mterp/x86/OP_MOVE_WIDE_16.S
+++ b/vm/mterp/x86/OP_MOVE_WIDE_16.S
@@ -5,8 +5,8 @@
movzwl 2(rPC),%eax # eax<- AAAA
GET_VREG_WORD rINST %ecx 0 # rINSTw_WORD<- v[BBBB+0]
GET_VREG_WORD %ecx %ecx 1 # ecx<- v[BBBB+1]
- FETCH_INST_OPCODE 3 %edx
SET_VREG_WORD rINST %eax 0 # v[AAAA+0]<- rINST
- ADVANCE_PC 3
SET_VREG_WORD %ecx %eax 1 # v[AAAA+1]<- ecx
- GOTO_NEXT_R %edx
+ FETCH_INST_OPCODE 3 %ecx
+ ADVANCE_PC 3
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_MOVE_WIDE_FROM16.S b/vm/mterp/x86/OP_MOVE_WIDE_FROM16.S
index 6b59c68..3d820ad 100644
--- a/vm/mterp/x86/OP_MOVE_WIDE_FROM16.S
+++ b/vm/mterp/x86/OP_MOVE_WIDE_FROM16.S
@@ -5,8 +5,8 @@
movzbl rINSTbl,%eax # eax<- AAAA
GET_VREG_WORD rINST %ecx 0 # rINST<- v[BBBB+0]
GET_VREG_WORD %ecx %ecx 1 # ecx<- v[BBBB+1]
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
SET_VREG_WORD rINST %eax 0 # v[AAAA+0]<- rINST
SET_VREG_WORD %ecx %eax 1 # v[AAAA+1]<- eax
- GOTO_NEXT_R %edx
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_MUL_INT.S b/vm/mterp/x86/OP_MUL_INT.S
index df4be1d..a958114 100644
--- a/vm/mterp/x86/OP_MUL_INT.S
+++ b/vm/mterp/x86/OP_MUL_INT.S
@@ -6,8 +6,10 @@
movzbl 2(rPC),%eax # eax<- BB
movzbl 3(rPC),%ecx # ecx<- CC
GET_VREG_R %eax %eax # eax<- vBB
- imull (rFP,%ecx,4),%eax # trashes edx
- FETCH_INST_OPCODE 2 %edx
+ SPILL(rIBASE)
+ imull (rFP,%ecx,4),%eax # trashes rIBASE/edx
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
SET_VREG %eax rINST
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_MUL_INT_2ADDR.S b/vm/mterp/x86/OP_MUL_INT_2ADDR.S
index 00d294f..ebd5160 100644
--- a/vm/mterp/x86/OP_MUL_INT_2ADDR.S
+++ b/vm/mterp/x86/OP_MUL_INT_2ADDR.S
@@ -1,11 +1,13 @@
%verify "executed"
/* mul vA, vB */
- movzx rINSTbl,%ecx # ecx<- A+
+ movzx rINSTbl,%ecx # ecx<- A+
sarl $$4,rINST # rINST<- B
- GET_VREG_R %eax rINST # eax<- vB
- andb $$0xf,%cl # ecx<- A
- imull (rFP,%ecx,4),%eax
- FETCH_INST_OPCODE 1 %edx
+ GET_VREG_R %eax rINST # eax<- vB
+ andb $$0xf,%cl # ecx<- A
+ SPILL(rIBASE)
+ imull (rFP,%ecx,4),%eax # trashes rIBASE/edx
+ UNSPILL(rIBASE)
SET_VREG %eax %ecx
+ FETCH_INST_OPCODE 1 %ecx
ADVANCE_PC 1
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_MUL_INT_LIT16.S b/vm/mterp/x86/OP_MUL_INT_LIT16.S
index 57c9d4c..a196c7e 100644
--- a/vm/mterp/x86/OP_MUL_INT_LIT16.S
+++ b/vm/mterp/x86/OP_MUL_INT_LIT16.S
@@ -6,8 +6,10 @@
GET_VREG_R %eax %eax # eax<- vB
movswl 2(rPC),%ecx # ecx<- ssssCCCC
andb $$0xf,rINSTbl # rINST<- A
- imull %ecx,%eax # trashes edx
- FETCH_INST_OPCODE 2 %edx
+ SPILL(rIBASE)
+ imull %ecx,%eax # trashes rIBASE/edx
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
SET_VREG %eax rINST
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_MUL_INT_LIT8.S b/vm/mterp/x86/OP_MUL_INT_LIT8.S
index f662d25..f36ffc7 100644
--- a/vm/mterp/x86/OP_MUL_INT_LIT8.S
+++ b/vm/mterp/x86/OP_MUL_INT_LIT8.S
@@ -3,8 +3,10 @@
movzbl 2(rPC),%eax # eax<- BB
movsbl 3(rPC),%ecx # ecx<- ssssssCC
GET_VREG_R %eax %eax # eax<- rBB
- imull %ecx,%eax # trashes edx
- FETCH_INST_OPCODE 2 %edx
+ SPILL(rIBASE)
+ imull %ecx,%eax # trashes rIBASE/edx
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
SET_VREG %eax rINST
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_MUL_LONG.S b/vm/mterp/x86/OP_MUL_LONG.S
index 4213299..7cf6ccb 100644
--- a/vm/mterp/x86/OP_MUL_LONG.S
+++ b/vm/mterp/x86/OP_MUL_LONG.S
@@ -15,6 +15,7 @@
SPILL_TMP2(%esi) # save Dalvik PC
SPILL(rFP)
SPILL(rINST)
+ SPILL(rIBASE)
leal (rFP,%eax,4),%esi # esi<- &v[B]
leal (rFP,%ecx,4),rFP # rFP<- &v[C]
movl 4(%esi),%ecx # ecx<- Bmsw
@@ -26,14 +27,11 @@
mull (%esi) # eax<- (Clsw*Alsw)
UNSPILL(rINST)
UNSPILL(rFP)
- jmp .L${opcode}_continue
-%break
-
-.L${opcode}_continue:
- leal (%ecx,%edx),%edx # full result now in %edx:%eax
+ leal (%ecx,rIBASE),rIBASE # full result now in rIBASE:%eax
UNSPILL_TMP2(%esi) # Restore Dalvik PC
FETCH_INST_OPCODE 2 %ecx # Fetch next instruction
- movl %edx,4(rFP,rINST,4) # v[B+1]<- %edx
+ movl rIBASE,4(rFP,rINST,4)# v[B+1]<- rIBASE
+ UNSPILL(rIBASE)
movl %eax,(rFP,rINST,4) # v[B]<- %eax
ADVANCE_PC 2
GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_MUL_LONG_2ADDR.S b/vm/mterp/x86/OP_MUL_LONG_2ADDR.S
index b8c41ab..9a0930c 100644
--- a/vm/mterp/x86/OP_MUL_LONG_2ADDR.S
+++ b/vm/mterp/x86/OP_MUL_LONG_2ADDR.S
@@ -3,9 +3,9 @@
* Signed 64-bit integer multiply, 2-addr version
*
* We could definately use more free registers for
- * this code. We must spill %edx (edx) because it
+ * this code. We must spill %edx (rIBASE) because it
* is used by imul. We'll also spill rINST (ebx),
- * giving us eax, ebc, ecx and edx as computational
+ * giving us eax, ebc, ecx and rIBASE as computational
* temps. On top of that, we'll spill %esi (edi)
* for use as the vA pointer and rFP (esi) for use
* as the vB pointer. Yuck.
@@ -16,6 +16,7 @@
sarl $$4,rINST # rINST<- B
SPILL_TMP2(%esi)
SPILL(rFP)
+ SPILL(rIBASE)
leal (rFP,%eax,4),%esi # %esi<- &v[A]
leal (rFP,rINST,4),rFP # rFP<- &v[B]
movl 4(%esi),%ecx # ecx<- Amsw
@@ -25,15 +26,12 @@
addl %eax,%ecx # ecx<- (Amsw*Blsw)+(Bmsw*Alsw)
movl (rFP),%eax # eax<- Blsw
mull (%esi) # eax<- (Blsw*Alsw)
- jmp .L${opcode}_continue
-%break
-
-.L${opcode}_continue:
- leal (%ecx,%edx),%edx # full result now in %edx:%eax
- movl %edx,4(%esi) # v[A+1]<- %edx
+ leal (%ecx,rIBASE),rIBASE # full result now in %edx:%eax
+ movl rIBASE,4(%esi) # v[A+1]<- rIBASE
movl %eax,(%esi) # v[A]<- %eax
UNSPILL_TMP2(%esi)
FETCH_INST_OPCODE 1 %ecx
+ UNSPILL(rIBASE)
UNSPILL(rFP)
ADVANCE_PC 1
GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_NEG_LONG.S b/vm/mterp/x86/OP_NEG_LONG.S
index a69afbc..9543351 100644
--- a/vm/mterp/x86/OP_NEG_LONG.S
+++ b/vm/mterp/x86/OP_NEG_LONG.S
@@ -8,8 +8,8 @@
negl %eax
adcl $$0,%ecx
negl %ecx
- FETCH_INST_OPCODE 1 %edx
SET_VREG_WORD %eax rINST 0 # v[A+0]<- eax
+ FETCH_INST_OPCODE 1 %eax
SET_VREG_WORD %ecx rINST 1 # v[A+1]<- ecx
ADVANCE_PC 1
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %eax
diff --git a/vm/mterp/x86/OP_NEW_ARRAY.S b/vm/mterp/x86/OP_NEW_ARRAY.S
index ec3b3a9..c9690d3 100644
--- a/vm/mterp/x86/OP_NEW_ARRAY.S
+++ b/vm/mterp/x86/OP_NEW_ARRAY.S
@@ -14,6 +14,7 @@
movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
movzwl 2(rPC),%eax # eax<- CCCC
movl offDvmDex_pResClasses(%ecx),%ecx # ecx<- pDvmDex->pResClasses
+ SPILL(rIBASE)
movl (%ecx,%eax,4),%ecx # ecx<- resolved class
movzbl rINSTbl,%eax
sarl $$4,%eax # eax<- B
@@ -23,15 +24,11 @@
js common_errNegativeArraySize # bail, passing len in eax
testl %ecx,%ecx # already resolved?
jne .L${opcode}_finish # yes, fast path
- jmp .L${opcode}_resolve # resolve now
-%break
-
/*
* Resolve class. (This is an uncommon case.)
* ecx holds class (null here)
* eax holds array length (vB)
*/
-.L${opcode}_resolve:
movl rSELF,%ecx
SPILL_TMP1(%eax) # save array length
movl offThread_method(%ecx),%ecx # ecx<- self->method
@@ -58,9 +55,10 @@
movl %eax,OUT_ARG1(%esp)
movl $$ALLOC_DONT_TRACK,OUT_ARG2(%esp)
call dvmAllocArrayByClass # eax<- call(clazz,length,flags)
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
testl %eax,%eax # failed?
je common_exceptionThrown # yup - go handle
SET_VREG %eax rINST
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_NEW_ARRAY_JUMBO.S b/vm/mterp/x86/OP_NEW_ARRAY_JUMBO.S
index 463738e..5d72759 100644
--- a/vm/mterp/x86/OP_NEW_ARRAY_JUMBO.S
+++ b/vm/mterp/x86/OP_NEW_ARRAY_JUMBO.S
@@ -14,6 +14,7 @@
movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
movl 2(rPC),%eax # eax<- AAAAAAAA
movl offDvmDex_pResClasses(%ecx),%ecx # ecx<- pDvmDex->pResClasses
+ SPILL(rIBASE)
movl (%ecx,%eax,4),%ecx # ecx<- resolved class
movzwl 8(rPC),%eax # eax<- CCCC
GET_VREG_R %eax %eax # eax<- vCCCC (array length)
@@ -21,15 +22,11 @@
js common_errNegativeArraySize # bail, passing len in eax
testl %ecx,%ecx # already resolved?
jne .L${opcode}_finish # yes, fast path
- jmp .L${opcode}_resolve # resolve now
-%break
-
/*
* Resolve class. (This is an uncommon case.)
* ecx holds class (null here)
* eax holds array length (vCCCC)
*/
-.L${opcode}_resolve:
movl rSELF,%ecx
SPILL_TMP1(%eax) # save array length
movl offThread_method(%ecx),%ecx # ecx<- self->method
@@ -56,9 +53,10 @@
movl %eax,OUT_ARG1(%esp)
movl $$ALLOC_DONT_TRACK,OUT_ARG2(%esp)
call dvmAllocArrayByClass # eax<- call(clazz,length,flags)
- FETCH_INST_OPCODE 5 %edx
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 5 %ecx
testl %eax,%eax # failed?
je common_exceptionThrown # yup - go handle
SET_VREG %eax rINST
ADVANCE_PC 5
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_NEW_INSTANCE.S b/vm/mterp/x86/OP_NEW_INSTANCE.S
index fe9f2ca..00a178b 100644
--- a/vm/mterp/x86/OP_NEW_INSTANCE.S
+++ b/vm/mterp/x86/OP_NEW_INSTANCE.S
@@ -13,6 +13,7 @@
movl rSELF,%ecx
movzwl 2(rPC),%eax # eax<- BBBB
movl offThread_methodClassDex(%ecx),%ecx # ecx<- pDvmDex
+ SPILL(rIBASE)
movl offDvmDex_pResClasses(%ecx),%ecx # ecx<- pDvmDex->pResClasses
EXPORT_PC
movl (%ecx,%eax,4),%ecx # ecx<- resolved class
@@ -20,10 +21,7 @@
je .L${opcode}_resolve # no, go do it
.L${opcode}_resolved: # on entry, ecx<- class
cmpb $$CLASS_INITIALIZED,offClassObject_status(%ecx)
- je .L${opcode}_initialized
- jmp .L${opcode}_needinit
-%break
-
+ jne .L${opcode}_needinit
.L${opcode}_initialized: # on entry, ecx<- class
/* TODO: remove test for interface/abstract, now done in verifier */
testl $$(ACC_INTERFACE|ACC_ABSTRACT),offClassObject_accessFlags(%ecx)
@@ -32,12 +30,13 @@
.L${opcode}_finish: # ecx=class
movl %ecx,OUT_ARG0(%esp)
call dvmAllocObject # eax<- new object
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
testl %eax,%eax # success?
je common_exceptionThrown # no, bail out
SET_VREG %eax rINST
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
/*
* Class initialization required.
diff --git a/vm/mterp/x86/OP_NEW_INSTANCE_JUMBO.S b/vm/mterp/x86/OP_NEW_INSTANCE_JUMBO.S
index bc8a950..96ae85f 100644
--- a/vm/mterp/x86/OP_NEW_INSTANCE_JUMBO.S
+++ b/vm/mterp/x86/OP_NEW_INSTANCE_JUMBO.S
@@ -16,14 +16,12 @@
movl offDvmDex_pResClasses(%ecx),%ecx # ecx<- pDvmDex->pResClasses
EXPORT_PC
movl (%ecx,%eax,4),%ecx # ecx<- resolved class
+ SPILL(rIBASE)
testl %ecx,%ecx # resolved?
je .L${opcode}_resolve # no, go do it
.L${opcode}_resolved: # on entry, ecx<- class
cmpb $$CLASS_INITIALIZED,offClassObject_status(%ecx)
- je .L${opcode}_initialized
- jmp .L${opcode}_needinit
-%break
-
+ jne .L${opcode}_needinit
.L${opcode}_initialized: # on entry, ecx<- class
/* TODO: remove test for interface/abstract, now done in verifier */
testl $$(ACC_INTERFACE|ACC_ABSTRACT),offClassObject_accessFlags(%ecx)
@@ -32,12 +30,13 @@
.L${opcode}_finish: # ecx=class
movl %ecx,OUT_ARG0(%esp)
call dvmAllocObject # eax<- new object
- FETCH_INST_OPCODE 4 %edx
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 4 %ecx
testl %eax,%eax # success?
je common_exceptionThrown # no, bail out
SET_VREG %eax rINST
ADVANCE_PC 4
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
/*
* Class initialization required.
diff --git a/vm/mterp/x86/OP_NOP.S b/vm/mterp/x86/OP_NOP.S
index 167d842..99fa2b6 100644
--- a/vm/mterp/x86/OP_NOP.S
+++ b/vm/mterp/x86/OP_NOP.S
@@ -1,4 +1,4 @@
%verify "executed"
- FETCH_INST_OPCODE 1 %edx
+ FETCH_INST_OPCODE 1 %ecx
ADVANCE_PC 1
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_NOT_LONG.S b/vm/mterp/x86/OP_NOT_LONG.S
index bdecf46..54e1c44 100644
--- a/vm/mterp/x86/OP_NOT_LONG.S
+++ b/vm/mterp/x86/OP_NOT_LONG.S
@@ -5,10 +5,10 @@
andb $$0xf,rINSTbl # rINST<- A
GET_VREG_WORD %eax %ecx 0 # eax<- v[B+0]
GET_VREG_WORD %ecx %ecx 1 # ecx<- v[B+1]
- FETCH_INST_OPCODE 1 %edx
notl %eax
notl %ecx
SET_VREG_WORD %eax rINST 0 # v[A+0]<- eax
+ FETCH_INST_OPCODE 1 %eax
SET_VREG_WORD %ecx rINST 1 # v[A+1]<- ecx
ADVANCE_PC 1
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %eax
diff --git a/vm/mterp/x86/OP_OR_LONG.S b/vm/mterp/x86/OP_OR_LONG.S
index ebeb05a..90f0e3e 100644
--- a/vm/mterp/x86/OP_OR_LONG.S
+++ b/vm/mterp/x86/OP_OR_LONG.S
@@ -1,2 +1,2 @@
%verify "executed"
-%include "x86/binopWide.S" {"instr1":"orl (rFP,%ecx,4),%edx", "instr2":"orl 4(rFP,%ecx,4),%eax"}
+%include "x86/binopWide.S" {"instr1":"orl (rFP,%ecx,4),rIBASE", "instr2":"orl 4(rFP,%ecx,4),%eax"}
diff --git a/vm/mterp/x86/OP_PACKED_SWITCH.S b/vm/mterp/x86/OP_PACKED_SWITCH.S
index 1b48635..bae1226 100644
--- a/vm/mterp/x86/OP_PACKED_SWITCH.S
+++ b/vm/mterp/x86/OP_PACKED_SWITCH.S
@@ -15,7 +15,9 @@
leal (rPC,%ecx,2),%ecx # ecx<- PC + BBBBbbbb*2
movl %eax,OUT_ARG1(%esp) # ARG1<- vAA
movl %ecx,OUT_ARG0(%esp) # ARG0<- switchData
+ SPILL(rIBASE)
call $func
+ UNSPILL(rIBASE)
testl %eax,%eax
movl %eax,rINST # set up word offset
jle common_backwardBranch # check on special actions
diff --git a/vm/mterp/x86/OP_REM_DOUBLE.S b/vm/mterp/x86/OP_REM_DOUBLE.S
index bad3e22..d670a31 100644
--- a/vm/mterp/x86/OP_REM_DOUBLE.S
+++ b/vm/mterp/x86/OP_REM_DOUBLE.S
@@ -4,8 +4,7 @@
movzbl 2(rPC),%eax # eax<- CC
fldl (rFP,%ecx,4) # vCC to fp stack
fldl (rFP,%eax,4) # vCC to fp stack
- movzbl rINSTbl,%ecx # ecx<- AA
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
1:
fprem
fstsw %ax
@@ -13,5 +12,5 @@
jp 1b
fstp %st(1)
ADVANCE_PC 2
- fstpl (rFP,%ecx,4) # %st to vAA
- GOTO_NEXT_R %edx
+ fstpl (rFP,rINST,4) # %st to vAA
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_REM_DOUBLE_2ADDR.S b/vm/mterp/x86/OP_REM_DOUBLE_2ADDR.S
index aaee1d4..ee751d0 100644
--- a/vm/mterp/x86/OP_REM_DOUBLE_2ADDR.S
+++ b/vm/mterp/x86/OP_REM_DOUBLE_2ADDR.S
@@ -5,13 +5,13 @@
fldl (rFP,rINST,4) # vBB to fp stack
andb $$0xf,%cl # ecx<- A
fldl (rFP,%ecx,4) # vAA to fp stack
- FETCH_INST_OPCODE 1 %edx
1:
fprem
fstsw %ax
sahf
jp 1b
fstp %st(1)
+ FETCH_INST_OPCODE 1 %eax
ADVANCE_PC 1
fstpl (rFP,%ecx,4) # %st to vA
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %eax
diff --git a/vm/mterp/x86/OP_REM_FLOAT.S b/vm/mterp/x86/OP_REM_FLOAT.S
index 12af510..342bf3e 100644
--- a/vm/mterp/x86/OP_REM_FLOAT.S
+++ b/vm/mterp/x86/OP_REM_FLOAT.S
@@ -5,13 +5,13 @@
flds (rFP,%ecx,4) # vCC to fp stack
flds (rFP,%eax,4) # vCC to fp stack
movzbl rINSTbl,%ecx # ecx<- AA
- FETCH_INST_OPCODE 2 %edx
1:
fprem
fstsw %ax
sahf
jp 1b
fstp %st(1)
+ FETCH_INST_OPCODE 2 %eax
ADVANCE_PC 2
fstps (rFP,%ecx,4) # %st to vAA
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %eax
diff --git a/vm/mterp/x86/OP_REM_FLOAT_2ADDR.S b/vm/mterp/x86/OP_REM_FLOAT_2ADDR.S
index 6a5f716..1f494bd 100644
--- a/vm/mterp/x86/OP_REM_FLOAT_2ADDR.S
+++ b/vm/mterp/x86/OP_REM_FLOAT_2ADDR.S
@@ -5,13 +5,13 @@
flds (rFP,rINST,4) # vBB to fp stack
andb $$0xf,%cl # ecx<- A
flds (rFP,%ecx,4) # vAA to fp stack
- FETCH_INST_OPCODE 1 %edx
1:
fprem
fstsw %ax
sahf
jp 1b
fstp %st(1)
+ FETCH_INST_OPCODE 1 %eax
ADVANCE_PC 1
fstps (rFP,%ecx,4) # %st to vA
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %eax
diff --git a/vm/mterp/x86/OP_REM_INT.S b/vm/mterp/x86/OP_REM_INT.S
index 601b383..6e4fd04 100644
--- a/vm/mterp/x86/OP_REM_INT.S
+++ b/vm/mterp/x86/OP_REM_INT.S
@@ -1,2 +1,2 @@
%verify "executed"
-%include "x86/bindiv.S" {"result":"%edx","special":"$0"}
+%include "x86/bindiv.S" {"result":"rIBASE","special":"$0"}
diff --git a/vm/mterp/x86/OP_REM_INT_2ADDR.S b/vm/mterp/x86/OP_REM_INT_2ADDR.S
index cfb60bd..4a11617 100644
--- a/vm/mterp/x86/OP_REM_INT_2ADDR.S
+++ b/vm/mterp/x86/OP_REM_INT_2ADDR.S
@@ -1,2 +1,2 @@
%verify "executed"
-%include "x86/bindiv2addr.S" {"result":"%edx","special":"$0"}
+%include "x86/bindiv2addr.S" {"result":"rIBASE","special":"$0"}
diff --git a/vm/mterp/x86/OP_REM_INT_LIT16.S b/vm/mterp/x86/OP_REM_INT_LIT16.S
index a5fdb1e..5c4afd6 100644
--- a/vm/mterp/x86/OP_REM_INT_LIT16.S
+++ b/vm/mterp/x86/OP_REM_INT_LIT16.S
@@ -1,2 +1,2 @@
%verify "executed"
-%include "x86/bindivLit16.S" {"result":"%edx","special":"$0"}
+%include "x86/bindivLit16.S" {"result":"rIBASE","special":"$0"}
diff --git a/vm/mterp/x86/OP_REM_INT_LIT8.S b/vm/mterp/x86/OP_REM_INT_LIT8.S
index 9d06fcd..53e12ee 100644
--- a/vm/mterp/x86/OP_REM_INT_LIT8.S
+++ b/vm/mterp/x86/OP_REM_INT_LIT8.S
@@ -1,2 +1,2 @@
%verify "executed"
-%include "x86/bindivLit8.S" {"result":"%edx","special":"$0"}
+%include "x86/bindivLit8.S" {"result":"rIBASE","special":"$0"}
diff --git a/vm/mterp/x86/OP_SGET.S b/vm/mterp/x86/OP_SGET.S
index 3152cb0..8ff0632 100644
--- a/vm/mterp/x86/OP_SGET.S
+++ b/vm/mterp/x86/OP_SGET.S
@@ -17,11 +17,10 @@
je .L${opcode}_resolve # if not, make it so
.L${opcode}_finish: # field ptr in eax
movl offStaticField_value(%eax),%eax
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
SET_VREG %eax rINST
- GOTO_NEXT_R %edx
-%break
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -34,7 +33,9 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .L${opcode}_finish # success, continue
jmp common_exceptionThrown # no, handle exception
diff --git a/vm/mterp/x86/OP_SGET_JUMBO.S b/vm/mterp/x86/OP_SGET_JUMBO.S
index a46759a..2b3e2a8 100644
--- a/vm/mterp/x86/OP_SGET_JUMBO.S
+++ b/vm/mterp/x86/OP_SGET_JUMBO.S
@@ -18,11 +18,10 @@
je .L${opcode}_resolve # if not, make it so
.L${opcode}_finish: # field ptr in eax
movl offStaticField_value(%eax),%eax
- FETCH_INST_OPCODE 4 %edx
+ FETCH_INST_OPCODE 4 %ecx
ADVANCE_PC 4
SET_VREG %eax rINST
- GOTO_NEXT_R %edx
-%break
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -35,7 +34,9 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .L${opcode}_finish # success, continue
jmp common_exceptionThrown # no, handle exception
diff --git a/vm/mterp/x86/OP_SGET_WIDE.S b/vm/mterp/x86/OP_SGET_WIDE.S
index 6dac296..432763d 100644
--- a/vm/mterp/x86/OP_SGET_WIDE.S
+++ b/vm/mterp/x86/OP_SGET_WIDE.S
@@ -17,12 +17,11 @@
.L${opcode}_finish: # field ptr in eax
movl offStaticField_value(%eax),%ecx # ecx<- lsw
movl 4+offStaticField_value(%eax),%eax # eax<- msw
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
SET_VREG_WORD %ecx rINST 0
+ FETCH_INST_OPCODE 2 %ecx
SET_VREG_WORD %eax rINST 1
- GOTO_NEXT_R %edx
-%break
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -35,7 +34,9 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .L${opcode}_finish # success, continue
jmp common_exceptionThrown # no, handle exception
diff --git a/vm/mterp/x86/OP_SGET_WIDE_JUMBO.S b/vm/mterp/x86/OP_SGET_WIDE_JUMBO.S
index 887ff3d..2d8fa8f 100644
--- a/vm/mterp/x86/OP_SGET_WIDE_JUMBO.S
+++ b/vm/mterp/x86/OP_SGET_WIDE_JUMBO.S
@@ -17,12 +17,11 @@
.L${opcode}_finish: # field ptr in eax
movl offStaticField_value(%eax),%ecx # ecx<- lsw
movl 4+offStaticField_value(%eax),%eax # eax<- msw
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
SET_VREG_WORD %ecx rINST 0
+ FETCH_INST_OPCODE 2 %ecx
SET_VREG_WORD %eax rINST 1
- GOTO_NEXT_R %edx
-%break
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -35,7 +34,9 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .L${opcode}_finish # success, continue
jmp common_exceptionThrown # no, handle exception
diff --git a/vm/mterp/x86/OP_SHL_LONG.S b/vm/mterp/x86/OP_SHL_LONG.S
index f181340..0750f80 100644
--- a/vm/mterp/x86/OP_SHL_LONG.S
+++ b/vm/mterp/x86/OP_SHL_LONG.S
@@ -9,26 +9,24 @@
*/
/* shl-long vAA, vBB, vCC */
/* ecx gets shift count */
- /* Need to spill edx */
+ /* Need to spill rINST */
/* rINSTw gets AA */
movzbl 2(rPC),%eax # eax<- BB
movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_WORD %edx %eax 1 # ecx<- v[BB+1]
+ SPILL(rIBASE)
+ GET_VREG_WORD rIBASE %eax 1 # ecx<- v[BB+1]
GET_VREG_R %ecx %ecx # ecx<- vCC
GET_VREG_WORD %eax %eax 0 # eax<- v[BB+0]
- shldl %eax,%edx
+ shldl %eax,rIBASE
sall %cl,%eax
testb $$32,%cl
je 2f
- movl %eax,%edx
+ movl %eax,rIBASE
xorl %eax,%eax
2:
- SET_VREG_WORD %edx rINST 1 # v[AA+1]<- %edx
- FETCH_INST_OPCODE 2 %edx
- jmp .L${opcode}_finish
-%break
-
-.L${opcode}_finish:
+ SET_VREG_WORD rIBASE rINST 1 # v[AA+1]<- rIBASE
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
SET_VREG_WORD %eax rINST 0 # v[AA+0]<- %eax
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_SHL_LONG_2ADDR.S b/vm/mterp/x86/OP_SHL_LONG_2ADDR.S
index 30f3d1b..b8bbce9 100644
--- a/vm/mterp/x86/OP_SHL_LONG_2ADDR.S
+++ b/vm/mterp/x86/OP_SHL_LONG_2ADDR.S
@@ -5,28 +5,25 @@
*/
/* shl-long/2addr vA, vB */
/* ecx gets shift count */
- /* Need to spill edx */
+ /* Need to spill rIBASE */
/* rINSTw gets AA */
movzbl rINSTbl,%ecx # ecx<- BA
andb $$0xf,rINSTbl # rINST<- A
GET_VREG_WORD %eax rINST 0 # eax<- v[AA+0]
sarl $$4,%ecx # ecx<- B
- GET_VREG_WORD %edx rINST 1 # edx<- v[AA+1]
+ SPILL(rIBASE)
+ GET_VREG_WORD rIBASE rINST 1 # rIBASE<- v[AA+1]
GET_VREG_R %ecx %ecx # ecx<- vBB
- shldl %eax,%edx
+ shldl %eax,rIBASE
sall %cl,%eax
testb $$32,%cl
je 2f
- movl %eax,%edx
+ movl %eax,rIBASE
xorl %eax,%eax
2:
- SET_VREG_WORD %edx rINST 1 # v[AA+1]<- edx
- jmp .L${opcode}_finish
-%break
-
-
-.L${opcode}_finish:
- FETCH_INST_OPCODE 1 %edx
+ SET_VREG_WORD rIBASE rINST 1 # v[AA+1]<- rIBASE
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 1 %ecx
SET_VREG_WORD %eax rINST 0 # v[AA+0]<- eax
ADVANCE_PC 1
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_SHR_LONG.S b/vm/mterp/x86/OP_SHR_LONG.S
index 45a07ae..d79d624 100644
--- a/vm/mterp/x86/OP_SHR_LONG.S
+++ b/vm/mterp/x86/OP_SHR_LONG.S
@@ -9,27 +9,24 @@
*/
/* shr-long vAA, vBB, vCC */
/* ecx gets shift count */
- /* Need to spill edx */
+ /* Need to spill rIBASE */
/* rINSTw gets AA */
movzbl 2(rPC),%eax # eax<- BB
movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_WORD %edx %eax 1 # edx<- v[BB+1]
+ SPILL(rIBASE)
+ GET_VREG_WORD rIBASE %eax 1 # rIBASE<- v[BB+1]
GET_VREG_R %ecx %ecx # ecx<- vCC
GET_VREG_WORD %eax %eax 0 # eax<- v[BB+0]
- shrdl %edx,%eax
- sarl %cl,%edx
+ shrdl rIBASE,%eax
+ sarl %cl,rIBASE
testb $$32,%cl
je 2f
- movl %edx,%eax
- sarl $$31,%edx
+ movl rIBASE,%eax
+ sarl $$31,rIBASE
2:
- SET_VREG_WORD %edx rINST 1 # v[AA+1]<- edx
- FETCH_INST_OPCODE 2 %edx
- jmp .L${opcode}_finish
-%break
-
-
-.L${opcode}_finish:
+ SET_VREG_WORD rIBASE rINST 1 # v[AA+1]<- rIBASE
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
SET_VREG_WORD %eax rINST 0 # v[AA+0]<- eax
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_SHR_LONG_2ADDR.S b/vm/mterp/x86/OP_SHR_LONG_2ADDR.S
index 9987cf7..d380e12 100644
--- a/vm/mterp/x86/OP_SHR_LONG_2ADDR.S
+++ b/vm/mterp/x86/OP_SHR_LONG_2ADDR.S
@@ -5,28 +5,25 @@
*/
/* shl-long/2addr vA, vB */
/* ecx gets shift count */
- /* Need to spill edx */
+ /* Need to spill rIBASE */
/* rINSTw gets AA */
movzbl rINSTbl,%ecx # ecx<- BA
andb $$0xf,rINSTbl # rINST<- A
GET_VREG_WORD %eax rINST 0 # eax<- v[AA+0]
sarl $$4,%ecx # ecx<- B
- GET_VREG_WORD %edx rINST 1 # edx<- v[AA+1]
+ SPILL(rIBASE)
+ GET_VREG_WORD rIBASE rINST 1 # rIBASE<- v[AA+1]
GET_VREG_R %ecx %ecx # ecx<- vBB
- shrdl %edx,%eax
- sarl %cl,%edx
+ shrdl rIBASE,%eax
+ sarl %cl,rIBASE
testb $$32,%cl
je 2f
- movl %edx,%eax
- sarl $$31,%edx
+ movl rIBASE,%eax
+ sarl $$31,rIBASE
2:
- SET_VREG_WORD %edx rINST 1 # v[AA+1]<- edx
- jmp .L${opcode}_finish
-%break
-
-
-.L${opcode}_finish:
- FETCH_INST_OPCODE 1 %edx
+ SET_VREG_WORD rIBASE rINST 1 # v[AA+1]<- rIBASE
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 1 %ecx
SET_VREG_WORD %eax rINST 0 # v[AA+0]<- eax
ADVANCE_PC 1
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_SPUT.S b/vm/mterp/x86/OP_SPUT.S
index 7a4296d..bc76533 100644
--- a/vm/mterp/x86/OP_SPUT.S
+++ b/vm/mterp/x86/OP_SPUT.S
@@ -16,12 +16,11 @@
testl %eax,%eax # resolved entry null?
je .L${opcode}_resolve # if not, make it so
.L${opcode}_finish: # field ptr in eax
- GET_VREG_R %ecx rINST
- FETCH_INST_OPCODE 2 %edx
+ GET_VREG_R rINST rINST
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- movl %ecx,offStaticField_value(%eax)
- GOTO_NEXT_R %edx
-%break
+ movl rINST,offStaticField_value(%eax)
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -34,7 +33,9 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .L${opcode}_finish # success, continue
jmp common_exceptionThrown # no, handle exception
diff --git a/vm/mterp/x86/OP_SPUT_JUMBO.S b/vm/mterp/x86/OP_SPUT_JUMBO.S
index 5c10b45..3f3d42a 100644
--- a/vm/mterp/x86/OP_SPUT_JUMBO.S
+++ b/vm/mterp/x86/OP_SPUT_JUMBO.S
@@ -17,12 +17,11 @@
testl %eax,%eax # resolved entry null?
je .L${opcode}_resolve # if not, make it so
.L${opcode}_finish: # field ptr in eax
- GET_VREG_R %ecx rINST
- FETCH_INST_OPCODE 4 %edx
+ GET_VREG_R rINST rINST
+ FETCH_INST_OPCODE 4 %ecx
ADVANCE_PC 4
- movl %ecx,offStaticField_value(%eax)
- GOTO_NEXT_R %edx
-%break
+ movl rINST,offStaticField_value(%eax)
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -35,7 +34,9 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .L${opcode}_finish # success, continue
jmp common_exceptionThrown # no, handle exception
diff --git a/vm/mterp/x86/OP_SPUT_OBJECT.S b/vm/mterp/x86/OP_SPUT_OBJECT.S
index 8e325f3..45d84c7 100644
--- a/vm/mterp/x86/OP_SPUT_OBJECT.S
+++ b/vm/mterp/x86/OP_SPUT_OBJECT.S
@@ -16,14 +16,8 @@
.L${opcode}_finish: # field ptr in eax
movzbl rINSTbl,%ecx # ecx<- AA
GET_VREG_R %ecx %ecx
- jmp .L${opcode}_continue
-%break
-
-
-.L${opcode}_continue:
movl %ecx,offStaticField_value(%eax) # do the store
testl %ecx,%ecx # stored null object ptr?
- FETCH_INST_OPCODE 2 %edx
je 1f # skip card mark if null
movl rSELF,%ecx
movl offField_clazz(%eax),%eax # eax<- method->clazz
@@ -31,8 +25,9 @@
shrl $$GC_CARD_SHIFT,%eax # head to card number
movb %cl,(%ecx,%eax) # mark card
1:
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
.L${opcode}_resolve:
movl rSELF,%ecx
@@ -42,7 +37,9 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .L${opcode}_finish # success, continue
jmp common_exceptionThrown # no, handle exception
diff --git a/vm/mterp/x86/OP_SPUT_OBJECT_JUMBO.S b/vm/mterp/x86/OP_SPUT_OBJECT_JUMBO.S
index 0ab1b20..5aab782 100644
--- a/vm/mterp/x86/OP_SPUT_OBJECT_JUMBO.S
+++ b/vm/mterp/x86/OP_SPUT_OBJECT_JUMBO.S
@@ -15,14 +15,8 @@
je .L${opcode}_resolve # if not, make it so
.L${opcode}_finish: # field ptr in eax
GET_VREG_R %ecx rINST
- jmp .L${opcode}_continue
-%break
-
-
-.L${opcode}_continue:
movl %ecx,offStaticField_value(%eax) # do the store
testl %ecx,%ecx # stored null object ptr?
- FETCH_INST_OPCODE 4 %edx
je 1f # skip card mark if null
movl rSELF,%ecx
movl offField_clazz(%eax),%eax # eax<- method->clazz
@@ -30,8 +24,9 @@
shrl $$GC_CARD_SHIFT,%eax # head to card number
movb %cl,(%ecx,%eax) # mark card
1:
+ FETCH_INST_OPCODE 4 %ecx
ADVANCE_PC 4
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
.L${opcode}_resolve:
movl rSELF,%ecx
@@ -41,7 +36,9 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .L${opcode}_finish # success, continue
jmp common_exceptionThrown # no, handle exception
diff --git a/vm/mterp/x86/OP_SPUT_WIDE.S b/vm/mterp/x86/OP_SPUT_WIDE.S
index 6855911..d4c5841 100644
--- a/vm/mterp/x86/OP_SPUT_WIDE.S
+++ b/vm/mterp/x86/OP_SPUT_WIDE.S
@@ -18,12 +18,11 @@
.L${opcode}_finish: # field ptr in eax
GET_VREG_WORD %ecx rINST 0 # rINST<- lsw
GET_VREG_WORD rINST rINST 1 # ecx<- msw
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
movl %ecx,offStaticField_value(%eax)
+ FETCH_INST_OPCODE 2 %ecx
movl rINST,4+offStaticField_value(%eax)
- GOTO_NEXT_R %edx
-%break
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -36,7 +35,9 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .L${opcode}_finish # success, continue
jmp common_exceptionThrown # no, handle exception
diff --git a/vm/mterp/x86/OP_SPUT_WIDE_JUMBO.S b/vm/mterp/x86/OP_SPUT_WIDE_JUMBO.S
index 22448d9..1fe544c 100644
--- a/vm/mterp/x86/OP_SPUT_WIDE_JUMBO.S
+++ b/vm/mterp/x86/OP_SPUT_WIDE_JUMBO.S
@@ -16,12 +16,11 @@
.L${opcode}_finish: # field ptr in eax
GET_VREG_WORD %ecx rINST 0 # ecx<- lsw
GET_VREG_WORD rINST rINST 1 # rINST<- msw
- FETCH_INST_OPCODE 4 %edx
- ADVANCE_PC 4
movl %ecx,offStaticField_value(%eax)
+ FETCH_INST_OPCODE 4 %ecx
movl rINST,4+offStaticField_value(%eax)
- GOTO_NEXT_R %edx
-%break
+ ADVANCE_PC 4
+ GOTO_NEXT_R %ecx
/*
* Go resolve the field
@@ -34,7 +33,9 @@
movl offMethod_clazz(%ecx),%ecx # ecx<- method->clazz
movl %eax,OUT_ARG1(%esp)
movl %ecx,OUT_ARG0(%esp)
+ SPILL(rIBASE)
call dvmResolveStaticField # eax<- resolved StaticField ptr
+ UNSPILL(rIBASE)
testl %eax,%eax
jne .L${opcode}_finish # success, continue
jmp common_exceptionThrown # no, handle exception
diff --git a/vm/mterp/x86/OP_SUB_LONG.S b/vm/mterp/x86/OP_SUB_LONG.S
index cd95435..485818c 100644
--- a/vm/mterp/x86/OP_SUB_LONG.S
+++ b/vm/mterp/x86/OP_SUB_LONG.S
@@ -1,2 +1,2 @@
%verify "executed"
-%include "x86/binopWide.S" {"instr1":"subl (rFP,%ecx,4),%edx", "instr2":"sbbl 4(rFP,%ecx,4),%eax"}
+%include "x86/binopWide.S" {"instr1":"subl (rFP,%ecx,4),rIBASE", "instr2":"sbbl 4(rFP,%ecx,4),%eax"}
diff --git a/vm/mterp/x86/OP_USHR_LONG.S b/vm/mterp/x86/OP_USHR_LONG.S
index e23de7e..4f3647e 100644
--- a/vm/mterp/x86/OP_USHR_LONG.S
+++ b/vm/mterp/x86/OP_USHR_LONG.S
@@ -9,27 +9,24 @@
*/
/* shr-long vAA, vBB, vCC */
/* ecx gets shift count */
- /* Need to spill edx */
+ /* Need to spill rIBASE */
/* rINSTw gets AA */
movzbl 2(rPC),%eax # eax<- BB
movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_WORD %edx %eax 1 # edx<- v[BB+1]
+ SPILL(rIBASE)
+ GET_VREG_WORD rIBASE %eax 1 # rIBASE<- v[BB+1]
GET_VREG_R %ecx %ecx # ecx<- vCC
GET_VREG_WORD %eax %eax 0 # eax<- v[BB+0]
- shrdl %edx,%eax
- shrl %cl,%edx
+ shrdl rIBASE,%eax
+ shrl %cl,rIBASE
testb $$32,%cl
je 2f
- movl %edx,%eax
- xorl %edx,%edx
+ movl rIBASE,%eax
+ xorl rIBASE,rIBASE
2:
- SET_VREG_WORD %edx rINST 1 # v[AA+1]<- edx
- FETCH_INST_OPCODE 2 %edx
- jmp .L${opcode}_finish
-%break
-
-
-.L${opcode}_finish:
+ SET_VREG_WORD rIBASE rINST 1 # v[AA+1]<- rIBASE
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE)
SET_VREG_WORD %eax rINST 0 # v[BB+0]<- eax
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_USHR_LONG_2ADDR.S b/vm/mterp/x86/OP_USHR_LONG_2ADDR.S
index b00ec61..d4396b4 100644
--- a/vm/mterp/x86/OP_USHR_LONG_2ADDR.S
+++ b/vm/mterp/x86/OP_USHR_LONG_2ADDR.S
@@ -5,28 +5,25 @@
*/
/* shl-long/2addr vA, vB */
/* ecx gets shift count */
- /* Need to spill edx */
+ /* Need to spill rIBASE */
/* rINSTw gets AA */
movzbl rINSTbl,%ecx # ecx<- BA
andb $$0xf,rINSTbl # rINST<- A
GET_VREG_WORD %eax rINST 0 # eax<- v[AA+0]
sarl $$4,%ecx # ecx<- B
- GET_VREG_WORD %edx rINST 1 # edx<- v[AA+1]
+ SPILL(rIBASE)
+ GET_VREG_WORD rIBASE rINST 1 # rIBASE<- v[AA+1]
GET_VREG_R %ecx %ecx # ecx<- vBB
- shrdl %edx,%eax
- shrl %cl,%edx
+ shrdl rIBASE,%eax
+ shrl %cl,rIBASE
testb $$32,%cl
je 2f
- movl %edx,%eax
- xorl %edx,%edx
+ movl rIBASE,%eax
+ xorl rIBASE,rIBASE
2:
- SET_VREG_WORD %edx rINST 1 # v[AA+1]<- edx
- jmp .L${opcode}_finish
-%break
-
-
-.L${opcode}_finish:
- FETCH_INST_OPCODE 1 %edx
+ SET_VREG_WORD rIBASE rINST 1 # v[AA+1]<- rIBASE
+ FETCH_INST_OPCODE 1 %ecx
+ UNSPILL(rIBASE)
SET_VREG_WORD %eax rINST 0 # v[AA+0]<- eax
ADVANCE_PC 1
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/OP_XOR_LONG.S b/vm/mterp/x86/OP_XOR_LONG.S
index e9fa59a..3cd5ffb 100644
--- a/vm/mterp/x86/OP_XOR_LONG.S
+++ b/vm/mterp/x86/OP_XOR_LONG.S
@@ -1,2 +1,2 @@
%verify "executed"
-%include "x86/binopWide.S" {"instr1":"xorl (rFP,%ecx,4),%edx", "instr2":"xorl 4(rFP,%ecx,4),%eax"}
+%include "x86/binopWide.S" {"instr1":"xorl (rFP,%ecx,4),rIBASE", "instr2":"xorl 4(rFP,%ecx,4),%eax"}
diff --git a/vm/mterp/x86/bindiv.S b/vm/mterp/x86/bindiv.S
index b2aafc3..cbd2f3d 100644
--- a/vm/mterp/x86/bindiv.S
+++ b/vm/mterp/x86/bindiv.S
@@ -9,6 +9,7 @@
movzbl 3(rPC),%ecx # ecx<- CC
GET_VREG_R %eax %eax # eax<- vBB
GET_VREG_R %ecx %ecx # eax<- vBB
+ SPILL(rIBASE)
cmpl $$0,%ecx
je common_errDivideByZero
cmpl $$-1,%ecx
@@ -16,14 +17,17 @@
cmpl $$0x80000000,%eax
jne .L${opcode}_continue_div
movl $special,$result
- jmp .L${opcode}_finish_div
+ SET_VREG $result rINST
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
-%break
.L${opcode}_continue_div:
cltd
idivl %ecx
-.L${opcode}_finish_div:
SET_VREG $result rINST
- FETCH_INST_OPCODE 2 %edx
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/bindiv2addr.S b/vm/mterp/x86/bindiv2addr.S
index fdbc4ec..cc415be 100644
--- a/vm/mterp/x86/bindiv2addr.S
+++ b/vm/mterp/x86/bindiv2addr.S
@@ -5,6 +5,7 @@
*/
/* div/rem/2addr vA, vB */
movzx rINSTbl,%ecx # eax<- BA
+ SPILL(rIBASE)
sarl $$4,%ecx # ecx<- B
GET_VREG_R %ecx %ecx # eax<- vBB
andb $$0xf,rINSTbl # rINST<- A
@@ -16,14 +17,17 @@
cmpl $$0x80000000,%eax
jne .L${opcode}_continue_div2addr
movl $special,$result
- jmp .L${opcode}_finish_div2addr
+ SET_VREG $result rINST
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
-%break
.L${opcode}_continue_div2addr:
cltd
idivl %ecx
-.L${opcode}_finish_div2addr:
SET_VREG $result rINST
- FETCH_INST_OPCODE 1 %edx
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 1 %ecx
ADVANCE_PC 1
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/bindivLit16.S b/vm/mterp/x86/bindivLit16.S
index 70bf183..c935367 100644
--- a/vm/mterp/x86/bindivLit16.S
+++ b/vm/mterp/x86/bindivLit16.S
@@ -6,6 +6,7 @@
/* div/rem/lit16 vA, vB, #+CCCC */
/* Need A in rINST, ssssCCCC in ecx, vB in eax */
movzbl rINSTbl,%eax # eax<- 000000BA
+ SPILL(rIBASE)
sarl $$4,%eax # eax<- B
GET_VREG_R %eax %eax # eax<- vB
movswl 2(rPC),%ecx # ecx<- ssssCCCC
@@ -17,14 +18,17 @@
cmpl $$0x80000000,%eax
jne .L${opcode}_continue_div
movl $special,$result
- jmp .L${opcode}_finish_div
+ SET_VREG $result rINST
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
-%break
.L${opcode}_continue_div:
cltd
idivl %ecx
-.L${opcode}_finish_div:
SET_VREG $result rINST
- FETCH_INST_OPCODE 2 %edx
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/bindivLit8.S b/vm/mterp/x86/bindivLit8.S
index 4bd61a6..94adef4 100644
--- a/vm/mterp/x86/bindivLit8.S
+++ b/vm/mterp/x86/bindivLit8.S
@@ -6,6 +6,7 @@
/* div/rem/lit8 vAA, vBB, #+CC */
movzbl 2(rPC),%eax # eax<- BB
movsbl 3(rPC),%ecx # ecx<- ssssssCC
+ SPILL(rIBASE)
GET_VREG_R %eax %eax # eax<- rBB
cmpl $$0,%ecx
je common_errDivideByZero
@@ -14,14 +15,17 @@
cmpl $$-1,%ecx
jne .L${opcode}_continue_div
movl $special,$result
- jmp .L${opcode}_finish_div
+ SET_VREG $result rINST
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
-%break
.L${opcode}_continue_div:
cltd
idivl %ecx
-.L${opcode}_finish_div:
SET_VREG $result rINST
- FETCH_INST_OPCODE 2 %edx
+ UNSPILL(rIBASE)
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/binflop.S b/vm/mterp/x86/binflop.S
index 0bcbb07..a432956 100644
--- a/vm/mterp/x86/binflop.S
+++ b/vm/mterp/x86/binflop.S
@@ -8,7 +8,7 @@
movzbl 3(rPC),%ecx # ecx<- BB
$load (rFP,%eax,4) # vCC to fp stack
$instr (rFP,%ecx,4) # ex: faddp
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
$store (rFP,rINST,4) # %st to vAA
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/binflop2addr.S b/vm/mterp/x86/binflop2addr.S
index 54ca894..c616d8b 100644
--- a/vm/mterp/x86/binflop2addr.S
+++ b/vm/mterp/x86/binflop2addr.S
@@ -10,7 +10,7 @@
$load (rFP,%ecx,4) # vAA to fp stack
sarl $$4,rINST # rINST<- B
$instr (rFP,rINST,4) # ex: faddp
- FETCH_INST_OPCODE 1 %edx
+ FETCH_INST_OPCODE 1 %eax
ADVANCE_PC 1
$store (rFP,%ecx,4) # %st to vA
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %eax
diff --git a/vm/mterp/x86/binop.S b/vm/mterp/x86/binop.S
index c7511e0..af2e908 100644
--- a/vm/mterp/x86/binop.S
+++ b/vm/mterp/x86/binop.S
@@ -13,7 +13,7 @@
movzbl 3(rPC),%ecx # ecx<- CC
GET_VREG_R %eax %eax # eax<- vBB
$instr # ex: addl (rFP,%ecx,4),%eax
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
SET_VREG $result rINST
- GOTO_NEXT_R %edx
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/binop1.S b/vm/mterp/x86/binop1.S
index c4d4b1e..38c2daf 100644
--- a/vm/mterp/x86/binop1.S
+++ b/vm/mterp/x86/binop1.S
@@ -9,7 +9,7 @@
GET_VREG_R %eax %eax # eax<- vBB
GET_VREG_R %ecx %ecx # eax<- vBB
$instr # ex: addl %ecx,%eax
- FETCH_INST_OPCODE 2 %edx
- ADVANCE_PC 2
SET_VREG $result rINST
- GOTO_NEXT_R %edx
+ FETCH_INST_OPCODE 2 %ecx
+ ADVANCE_PC 2
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/binop2addr.S b/vm/mterp/x86/binop2addr.S
index 0b040c7..7cd8c5b 100644
--- a/vm/mterp/x86/binop2addr.S
+++ b/vm/mterp/x86/binop2addr.S
@@ -17,8 +17,8 @@
movzx rINSTbl,%ecx # ecx<- A+
sarl $$4,rINST # rINST<- B
GET_VREG_R %eax rINST # eax<- vB
- FETCH_INST_OPCODE 1 %edx
andb $$0xf,%cl # ecx<- A
$instr # for ex: addl %eax,(rFP,%ecx,4)
+ FETCH_INST_OPCODE 1 %ecx
ADVANCE_PC 1
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/binopLit16.S b/vm/mterp/x86/binopLit16.S
index 3c985cc..4ca6c77 100644
--- a/vm/mterp/x86/binopLit16.S
+++ b/vm/mterp/x86/binopLit16.S
@@ -16,6 +16,6 @@
andb $$0xf,rINSTbl # rINST<- A
$instr # for example: addl %ecx, %eax
SET_VREG $result rINST
- FETCH_INST_OPCODE 2 %edx
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/binopLit8.S b/vm/mterp/x86/binopLit8.S
index d0bce9e..08e2efd 100644
--- a/vm/mterp/x86/binopLit8.S
+++ b/vm/mterp/x86/binopLit8.S
@@ -14,7 +14,7 @@
movsbl 3(rPC),%ecx # ecx<- ssssssCC
GET_VREG_R %eax %eax # eax<- rBB
$instr # ex: addl %ecx,%eax
- FETCH_INST_OPCODE 2 %edx
SET_VREG $result rINST
+ FETCH_INST_OPCODE 2 %ecx
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/binopWide.S b/vm/mterp/x86/binopWide.S
index 4131785..6114aff 100644
--- a/vm/mterp/x86/binopWide.S
+++ b/vm/mterp/x86/binopWide.S
@@ -5,12 +5,14 @@
movzbl 2(rPC),%eax # eax<- BB
movzbl 3(rPC),%ecx # ecx<- CC
- GET_VREG_WORD %edx %eax 0 # edx<- v[BB+0]
+ SPILL(rIBASE) # save rIBASE
+ GET_VREG_WORD rIBASE %eax 0 # rIBASE<- v[BB+0]
GET_VREG_WORD %eax %eax 1 # eax<- v[BB+1]
- $instr1 # ex: addl (rFP,%ecx,4),%edx
+ $instr1 # ex: addl (rFP,%ecx,4),rIBASE
$instr2 # ex: adcl 4(rFP,%ecx,4),%eax
- SET_VREG_WORD %edx rINST 0 # v[AA+0] <- edx
- FETCH_INST_OPCODE 2 %edx
+ SET_VREG_WORD rIBASE rINST 0 # v[AA+0] <- rIBASE
+ FETCH_INST_OPCODE 2 %ecx
+ UNSPILL(rIBASE) # restore rIBASE
SET_VREG_WORD %eax rINST 1 # v[AA+1] <- eax
ADVANCE_PC 2
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/binopWide2addr.S b/vm/mterp/x86/binopWide2addr.S
index be9084b..fa42644 100644
--- a/vm/mterp/x86/binopWide2addr.S
+++ b/vm/mterp/x86/binopWide2addr.S
@@ -9,6 +9,6 @@
andb $$0xF,rINSTbl # rINST<- A
$instr1 # example: addl %eax,(rFP,rINST,4)
$instr2 # example: adcl %ecx,4(rFP,rINST,4)
- FETCH_INST_OPCODE 1 %edx
+ FETCH_INST_OPCODE 1 %ecx
ADVANCE_PC 1
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/cvtfp_int.S b/vm/mterp/x86/cvtfp_int.S
index 13dc936..7590943 100644
--- a/vm/mterp/x86/cvtfp_int.S
+++ b/vm/mterp/x86/cvtfp_int.S
@@ -20,7 +20,6 @@
movb $$0xc,%ah
movw %ax,LOCAL0_OFFSET+2(%ebp)
fldcw LOCAL0_OFFSET+2(%ebp) # set "to zero" rounding mode
- FETCH_INST_OPCODE 1 %edx
andb $$0xf,%cl # ecx<- A
.if $tgtlong
fistpll (rFP,%ecx,4) # convert and store
@@ -28,11 +27,6 @@
fistpl (rFP,%ecx,4) # convert and store
.endif
fldcw LOCAL0_OFFSET(%ebp) # restore previous rounding mode
- jmp .L${opcode}_continue
-%break
-
-
-.L${opcode}_continue:
.if $tgtlong
movl $$0x80000000,%eax
xorl 4(rFP,%ecx,4),%eax
@@ -43,8 +37,9 @@
je .L${opcode}_special_case # fix up result
.L${opcode}_finish:
+ FETCH_INST_OPCODE 1 %ecx
ADVANCE_PC 1
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
.L${opcode}_special_case:
fnstsw %ax
diff --git a/vm/mterp/x86/entry.S b/vm/mterp/x86/entry.S
index 5a3aeec..b1b89a8 100644
--- a/vm/mterp/x86/entry.S
+++ b/vm/mterp/x86/entry.S
@@ -45,6 +45,7 @@
/* Set up "named" registers */
movl offThread_pc(%ecx),rPC
movl offThread_fp(%ecx),rFP
+ movl offThread_curHandlerTable(%ecx),rIBASE
/* Remember %esp for future "longjmp" */
movl %esp,offThread_bailPtr(%ecx)
@@ -112,524 +113,3 @@
.LstrBadEntryPoint:
.asciz "Bad entry point %d\n"
-
-/*
- * FIXME: Should have the config/rebuild mechanism generate this
- * for targets that need it.
- */
-
-/* Jump table */
-dvmAsmInstructionJmpTable = .LdvmAsmInstructionJmpTable
-.LdvmAsmInstructionJmpTable:
-.long .L_OP_NOP
-.long .L_OP_MOVE
-.long .L_OP_MOVE_FROM16
-.long .L_OP_MOVE_16
-.long .L_OP_MOVE_WIDE
-.long .L_OP_MOVE_WIDE_FROM16
-.long .L_OP_MOVE_WIDE_16
-.long .L_OP_MOVE_OBJECT
-.long .L_OP_MOVE_OBJECT_FROM16
-.long .L_OP_MOVE_OBJECT_16
-.long .L_OP_MOVE_RESULT
-.long .L_OP_MOVE_RESULT_WIDE
-.long .L_OP_MOVE_RESULT_OBJECT
-.long .L_OP_MOVE_EXCEPTION
-.long .L_OP_RETURN_VOID
-.long .L_OP_RETURN
-.long .L_OP_RETURN_WIDE
-.long .L_OP_RETURN_OBJECT
-.long .L_OP_CONST_4
-.long .L_OP_CONST_16
-.long .L_OP_CONST
-.long .L_OP_CONST_HIGH16
-.long .L_OP_CONST_WIDE_16
-.long .L_OP_CONST_WIDE_32
-.long .L_OP_CONST_WIDE
-.long .L_OP_CONST_WIDE_HIGH16
-.long .L_OP_CONST_STRING
-.long .L_OP_CONST_STRING_JUMBO
-.long .L_OP_CONST_CLASS
-.long .L_OP_MONITOR_ENTER
-.long .L_OP_MONITOR_EXIT
-.long .L_OP_CHECK_CAST
-.long .L_OP_INSTANCE_OF
-.long .L_OP_ARRAY_LENGTH
-.long .L_OP_NEW_INSTANCE
-.long .L_OP_NEW_ARRAY
-.long .L_OP_FILLED_NEW_ARRAY
-.long .L_OP_FILLED_NEW_ARRAY_RANGE
-.long .L_OP_FILL_ARRAY_DATA
-.long .L_OP_THROW
-.long .L_OP_GOTO
-.long .L_OP_GOTO_16
-.long .L_OP_GOTO_32
-.long .L_OP_PACKED_SWITCH
-.long .L_OP_SPARSE_SWITCH
-.long .L_OP_CMPL_FLOAT
-.long .L_OP_CMPG_FLOAT
-.long .L_OP_CMPL_DOUBLE
-.long .L_OP_CMPG_DOUBLE
-.long .L_OP_CMP_LONG
-.long .L_OP_IF_EQ
-.long .L_OP_IF_NE
-.long .L_OP_IF_LT
-.long .L_OP_IF_GE
-.long .L_OP_IF_GT
-.long .L_OP_IF_LE
-.long .L_OP_IF_EQZ
-.long .L_OP_IF_NEZ
-.long .L_OP_IF_LTZ
-.long .L_OP_IF_GEZ
-.long .L_OP_IF_GTZ
-.long .L_OP_IF_LEZ
-.long .L_OP_UNUSED_3E
-.long .L_OP_UNUSED_3F
-.long .L_OP_UNUSED_40
-.long .L_OP_UNUSED_41
-.long .L_OP_UNUSED_42
-.long .L_OP_UNUSED_43
-.long .L_OP_AGET
-.long .L_OP_AGET_WIDE
-.long .L_OP_AGET_OBJECT
-.long .L_OP_AGET_BOOLEAN
-.long .L_OP_AGET_BYTE
-.long .L_OP_AGET_CHAR
-.long .L_OP_AGET_SHORT
-.long .L_OP_APUT
-.long .L_OP_APUT_WIDE
-.long .L_OP_APUT_OBJECT
-.long .L_OP_APUT_BOOLEAN
-.long .L_OP_APUT_BYTE
-.long .L_OP_APUT_CHAR
-.long .L_OP_APUT_SHORT
-.long .L_OP_IGET
-.long .L_OP_IGET_WIDE
-.long .L_OP_IGET_OBJECT
-.long .L_OP_IGET_BOOLEAN
-.long .L_OP_IGET_BYTE
-.long .L_OP_IGET_CHAR
-.long .L_OP_IGET_SHORT
-.long .L_OP_IPUT
-.long .L_OP_IPUT_WIDE
-.long .L_OP_IPUT_OBJECT
-.long .L_OP_IPUT_BOOLEAN
-.long .L_OP_IPUT_BYTE
-.long .L_OP_IPUT_CHAR
-.long .L_OP_IPUT_SHORT
-.long .L_OP_SGET
-.long .L_OP_SGET_WIDE
-.long .L_OP_SGET_OBJECT
-.long .L_OP_SGET_BOOLEAN
-.long .L_OP_SGET_BYTE
-.long .L_OP_SGET_CHAR
-.long .L_OP_SGET_SHORT
-.long .L_OP_SPUT
-.long .L_OP_SPUT_WIDE
-.long .L_OP_SPUT_OBJECT
-.long .L_OP_SPUT_BOOLEAN
-.long .L_OP_SPUT_BYTE
-.long .L_OP_SPUT_CHAR
-.long .L_OP_SPUT_SHORT
-.long .L_OP_INVOKE_VIRTUAL
-.long .L_OP_INVOKE_SUPER
-.long .L_OP_INVOKE_DIRECT
-.long .L_OP_INVOKE_STATIC
-.long .L_OP_INVOKE_INTERFACE
-.long .L_OP_UNUSED_73
-.long .L_OP_INVOKE_VIRTUAL_RANGE
-.long .L_OP_INVOKE_SUPER_RANGE
-.long .L_OP_INVOKE_DIRECT_RANGE
-.long .L_OP_INVOKE_STATIC_RANGE
-.long .L_OP_INVOKE_INTERFACE_RANGE
-.long .L_OP_UNUSED_79
-.long .L_OP_UNUSED_7A
-.long .L_OP_NEG_INT
-.long .L_OP_NOT_INT
-.long .L_OP_NEG_LONG
-.long .L_OP_NOT_LONG
-.long .L_OP_NEG_FLOAT
-.long .L_OP_NEG_DOUBLE
-.long .L_OP_INT_TO_LONG
-.long .L_OP_INT_TO_FLOAT
-.long .L_OP_INT_TO_DOUBLE
-.long .L_OP_LONG_TO_INT
-.long .L_OP_LONG_TO_FLOAT
-.long .L_OP_LONG_TO_DOUBLE
-.long .L_OP_FLOAT_TO_INT
-.long .L_OP_FLOAT_TO_LONG
-.long .L_OP_FLOAT_TO_DOUBLE
-.long .L_OP_DOUBLE_TO_INT
-.long .L_OP_DOUBLE_TO_LONG
-.long .L_OP_DOUBLE_TO_FLOAT
-.long .L_OP_INT_TO_BYTE
-.long .L_OP_INT_TO_CHAR
-.long .L_OP_INT_TO_SHORT
-.long .L_OP_ADD_INT
-.long .L_OP_SUB_INT
-.long .L_OP_MUL_INT
-.long .L_OP_DIV_INT
-.long .L_OP_REM_INT
-.long .L_OP_AND_INT
-.long .L_OP_OR_INT
-.long .L_OP_XOR_INT
-.long .L_OP_SHL_INT
-.long .L_OP_SHR_INT
-.long .L_OP_USHR_INT
-.long .L_OP_ADD_LONG
-.long .L_OP_SUB_LONG
-.long .L_OP_MUL_LONG
-.long .L_OP_DIV_LONG
-.long .L_OP_REM_LONG
-.long .L_OP_AND_LONG
-.long .L_OP_OR_LONG
-.long .L_OP_XOR_LONG
-.long .L_OP_SHL_LONG
-.long .L_OP_SHR_LONG
-.long .L_OP_USHR_LONG
-.long .L_OP_ADD_FLOAT
-.long .L_OP_SUB_FLOAT
-.long .L_OP_MUL_FLOAT
-.long .L_OP_DIV_FLOAT
-.long .L_OP_REM_FLOAT
-.long .L_OP_ADD_DOUBLE
-.long .L_OP_SUB_DOUBLE
-.long .L_OP_MUL_DOUBLE
-.long .L_OP_DIV_DOUBLE
-.long .L_OP_REM_DOUBLE
-.long .L_OP_ADD_INT_2ADDR
-.long .L_OP_SUB_INT_2ADDR
-.long .L_OP_MUL_INT_2ADDR
-.long .L_OP_DIV_INT_2ADDR
-.long .L_OP_REM_INT_2ADDR
-.long .L_OP_AND_INT_2ADDR
-.long .L_OP_OR_INT_2ADDR
-.long .L_OP_XOR_INT_2ADDR
-.long .L_OP_SHL_INT_2ADDR
-.long .L_OP_SHR_INT_2ADDR
-.long .L_OP_USHR_INT_2ADDR
-.long .L_OP_ADD_LONG_2ADDR
-.long .L_OP_SUB_LONG_2ADDR
-.long .L_OP_MUL_LONG_2ADDR
-.long .L_OP_DIV_LONG_2ADDR
-.long .L_OP_REM_LONG_2ADDR
-.long .L_OP_AND_LONG_2ADDR
-.long .L_OP_OR_LONG_2ADDR
-.long .L_OP_XOR_LONG_2ADDR
-.long .L_OP_SHL_LONG_2ADDR
-.long .L_OP_SHR_LONG_2ADDR
-.long .L_OP_USHR_LONG_2ADDR
-.long .L_OP_ADD_FLOAT_2ADDR
-.long .L_OP_SUB_FLOAT_2ADDR
-.long .L_OP_MUL_FLOAT_2ADDR
-.long .L_OP_DIV_FLOAT_2ADDR
-.long .L_OP_REM_FLOAT_2ADDR
-.long .L_OP_ADD_DOUBLE_2ADDR
-.long .L_OP_SUB_DOUBLE_2ADDR
-.long .L_OP_MUL_DOUBLE_2ADDR
-.long .L_OP_DIV_DOUBLE_2ADDR
-.long .L_OP_REM_DOUBLE_2ADDR
-.long .L_OP_ADD_INT_LIT16
-.long .L_OP_RSUB_INT
-.long .L_OP_MUL_INT_LIT16
-.long .L_OP_DIV_INT_LIT16
-.long .L_OP_REM_INT_LIT16
-.long .L_OP_AND_INT_LIT16
-.long .L_OP_OR_INT_LIT16
-.long .L_OP_XOR_INT_LIT16
-.long .L_OP_ADD_INT_LIT8
-.long .L_OP_RSUB_INT_LIT8
-.long .L_OP_MUL_INT_LIT8
-.long .L_OP_DIV_INT_LIT8
-.long .L_OP_REM_INT_LIT8
-.long .L_OP_AND_INT_LIT8
-.long .L_OP_OR_INT_LIT8
-.long .L_OP_XOR_INT_LIT8
-.long .L_OP_SHL_INT_LIT8
-.long .L_OP_SHR_INT_LIT8
-.long .L_OP_USHR_INT_LIT8
-.long .L_OP_IGET_VOLATILE
-.long .L_OP_IPUT_VOLATILE
-.long .L_OP_SGET_VOLATILE
-.long .L_OP_SPUT_VOLATILE
-.long .L_OP_IGET_OBJECT_VOLATILE
-.long .L_OP_IGET_WIDE_VOLATILE
-.long .L_OP_IPUT_WIDE_VOLATILE
-.long .L_OP_SGET_WIDE_VOLATILE
-.long .L_OP_SPUT_WIDE_VOLATILE
-.long .L_OP_BREAKPOINT
-.long .L_OP_THROW_VERIFICATION_ERROR
-.long .L_OP_EXECUTE_INLINE
-.long .L_OP_EXECUTE_INLINE_RANGE
-.long .L_OP_INVOKE_OBJECT_INIT
-.long .L_OP_RETURN_VOID_BARRIER
-.long .L_OP_IGET_QUICK
-.long .L_OP_IGET_WIDE_QUICK
-.long .L_OP_IGET_OBJECT_QUICK
-.long .L_OP_IPUT_QUICK
-.long .L_OP_IPUT_WIDE_QUICK
-.long .L_OP_IPUT_OBJECT_QUICK
-.long .L_OP_INVOKE_VIRTUAL_QUICK
-.long .L_OP_INVOKE_VIRTUAL_QUICK_RANGE
-.long .L_OP_INVOKE_SUPER_QUICK
-.long .L_OP_INVOKE_SUPER_QUICK_RANGE
-.long .L_OP_IPUT_OBJECT_VOLATILE
-.long .L_OP_SGET_OBJECT_VOLATILE
-.long .L_OP_SPUT_OBJECT_VOLATILE
-.long .L_OP_DISPATCH_FF
-.long .L_OP_CONST_CLASS_JUMBO
-.long .L_OP_CHECK_CAST_JUMBO
-.long .L_OP_INSTANCE_OF_JUMBO
-.long .L_OP_NEW_INSTANCE_JUMBO
-.long .L_OP_NEW_ARRAY_JUMBO
-.long .L_OP_FILLED_NEW_ARRAY_JUMBO
-.long .L_OP_IGET_JUMBO
-.long .L_OP_IGET_WIDE_JUMBO
-.long .L_OP_IGET_OBJECT_JUMBO
-.long .L_OP_IGET_BOOLEAN_JUMBO
-.long .L_OP_IGET_BYTE_JUMBO
-.long .L_OP_IGET_CHAR_JUMBO
-.long .L_OP_IGET_SHORT_JUMBO
-.long .L_OP_IPUT_JUMBO
-.long .L_OP_IPUT_WIDE_JUMBO
-.long .L_OP_IPUT_OBJECT_JUMBO
-.long .L_OP_IPUT_BOOLEAN_JUMBO
-.long .L_OP_IPUT_BYTE_JUMBO
-.long .L_OP_IPUT_CHAR_JUMBO
-.long .L_OP_IPUT_SHORT_JUMBO
-.long .L_OP_SGET_JUMBO
-.long .L_OP_SGET_WIDE_JUMBO
-.long .L_OP_SGET_OBJECT_JUMBO
-.long .L_OP_SGET_BOOLEAN_JUMBO
-.long .L_OP_SGET_BYTE_JUMBO
-.long .L_OP_SGET_CHAR_JUMBO
-.long .L_OP_SGET_SHORT_JUMBO
-.long .L_OP_SPUT_JUMBO
-.long .L_OP_SPUT_WIDE_JUMBO
-.long .L_OP_SPUT_OBJECT_JUMBO
-.long .L_OP_SPUT_BOOLEAN_JUMBO
-.long .L_OP_SPUT_BYTE_JUMBO
-.long .L_OP_SPUT_CHAR_JUMBO
-.long .L_OP_SPUT_SHORT_JUMBO
-.long .L_OP_INVOKE_VIRTUAL_JUMBO
-.long .L_OP_INVOKE_SUPER_JUMBO
-.long .L_OP_INVOKE_DIRECT_JUMBO
-.long .L_OP_INVOKE_STATIC_JUMBO
-.long .L_OP_INVOKE_INTERFACE_JUMBO
-.long .L_OP_UNUSED_27FF
-.long .L_OP_UNUSED_28FF
-.long .L_OP_UNUSED_29FF
-.long .L_OP_UNUSED_2AFF
-.long .L_OP_UNUSED_2BFF
-.long .L_OP_UNUSED_2CFF
-.long .L_OP_UNUSED_2DFF
-.long .L_OP_UNUSED_2EFF
-.long .L_OP_UNUSED_2FFF
-.long .L_OP_UNUSED_30FF
-.long .L_OP_UNUSED_31FF
-.long .L_OP_UNUSED_32FF
-.long .L_OP_UNUSED_33FF
-.long .L_OP_UNUSED_34FF
-.long .L_OP_UNUSED_35FF
-.long .L_OP_UNUSED_36FF
-.long .L_OP_UNUSED_37FF
-.long .L_OP_UNUSED_38FF
-.long .L_OP_UNUSED_39FF
-.long .L_OP_UNUSED_3AFF
-.long .L_OP_UNUSED_3BFF
-.long .L_OP_UNUSED_3CFF
-.long .L_OP_UNUSED_3DFF
-.long .L_OP_UNUSED_3EFF
-.long .L_OP_UNUSED_3FFF
-.long .L_OP_UNUSED_40FF
-.long .L_OP_UNUSED_41FF
-.long .L_OP_UNUSED_42FF
-.long .L_OP_UNUSED_43FF
-.long .L_OP_UNUSED_44FF
-.long .L_OP_UNUSED_45FF
-.long .L_OP_UNUSED_46FF
-.long .L_OP_UNUSED_47FF
-.long .L_OP_UNUSED_48FF
-.long .L_OP_UNUSED_49FF
-.long .L_OP_UNUSED_4AFF
-.long .L_OP_UNUSED_4BFF
-.long .L_OP_UNUSED_4CFF
-.long .L_OP_UNUSED_4DFF
-.long .L_OP_UNUSED_4EFF
-.long .L_OP_UNUSED_4FFF
-.long .L_OP_UNUSED_50FF
-.long .L_OP_UNUSED_51FF
-.long .L_OP_UNUSED_52FF
-.long .L_OP_UNUSED_53FF
-.long .L_OP_UNUSED_54FF
-.long .L_OP_UNUSED_55FF
-.long .L_OP_UNUSED_56FF
-.long .L_OP_UNUSED_57FF
-.long .L_OP_UNUSED_58FF
-.long .L_OP_UNUSED_59FF
-.long .L_OP_UNUSED_5AFF
-.long .L_OP_UNUSED_5BFF
-.long .L_OP_UNUSED_5CFF
-.long .L_OP_UNUSED_5DFF
-.long .L_OP_UNUSED_5EFF
-.long .L_OP_UNUSED_5FFF
-.long .L_OP_UNUSED_60FF
-.long .L_OP_UNUSED_61FF
-.long .L_OP_UNUSED_62FF
-.long .L_OP_UNUSED_63FF
-.long .L_OP_UNUSED_64FF
-.long .L_OP_UNUSED_65FF
-.long .L_OP_UNUSED_66FF
-.long .L_OP_UNUSED_67FF
-.long .L_OP_UNUSED_68FF
-.long .L_OP_UNUSED_69FF
-.long .L_OP_UNUSED_6AFF
-.long .L_OP_UNUSED_6BFF
-.long .L_OP_UNUSED_6CFF
-.long .L_OP_UNUSED_6DFF
-.long .L_OP_UNUSED_6EFF
-.long .L_OP_UNUSED_6FFF
-.long .L_OP_UNUSED_70FF
-.long .L_OP_UNUSED_71FF
-.long .L_OP_UNUSED_72FF
-.long .L_OP_UNUSED_73FF
-.long .L_OP_UNUSED_74FF
-.long .L_OP_UNUSED_75FF
-.long .L_OP_UNUSED_76FF
-.long .L_OP_UNUSED_77FF
-.long .L_OP_UNUSED_78FF
-.long .L_OP_UNUSED_79FF
-.long .L_OP_UNUSED_7AFF
-.long .L_OP_UNUSED_7BFF
-.long .L_OP_UNUSED_7CFF
-.long .L_OP_UNUSED_7DFF
-.long .L_OP_UNUSED_7EFF
-.long .L_OP_UNUSED_7FFF
-.long .L_OP_UNUSED_80FF
-.long .L_OP_UNUSED_81FF
-.long .L_OP_UNUSED_82FF
-.long .L_OP_UNUSED_83FF
-.long .L_OP_UNUSED_84FF
-.long .L_OP_UNUSED_85FF
-.long .L_OP_UNUSED_86FF
-.long .L_OP_UNUSED_87FF
-.long .L_OP_UNUSED_88FF
-.long .L_OP_UNUSED_89FF
-.long .L_OP_UNUSED_8AFF
-.long .L_OP_UNUSED_8BFF
-.long .L_OP_UNUSED_8CFF
-.long .L_OP_UNUSED_8DFF
-.long .L_OP_UNUSED_8EFF
-.long .L_OP_UNUSED_8FFF
-.long .L_OP_UNUSED_90FF
-.long .L_OP_UNUSED_91FF
-.long .L_OP_UNUSED_92FF
-.long .L_OP_UNUSED_93FF
-.long .L_OP_UNUSED_94FF
-.long .L_OP_UNUSED_95FF
-.long .L_OP_UNUSED_96FF
-.long .L_OP_UNUSED_97FF
-.long .L_OP_UNUSED_98FF
-.long .L_OP_UNUSED_99FF
-.long .L_OP_UNUSED_9AFF
-.long .L_OP_UNUSED_9BFF
-.long .L_OP_UNUSED_9CFF
-.long .L_OP_UNUSED_9DFF
-.long .L_OP_UNUSED_9EFF
-.long .L_OP_UNUSED_9FFF
-.long .L_OP_UNUSED_A0FF
-.long .L_OP_UNUSED_A1FF
-.long .L_OP_UNUSED_A2FF
-.long .L_OP_UNUSED_A3FF
-.long .L_OP_UNUSED_A4FF
-.long .L_OP_UNUSED_A5FF
-.long .L_OP_UNUSED_A6FF
-.long .L_OP_UNUSED_A7FF
-.long .L_OP_UNUSED_A8FF
-.long .L_OP_UNUSED_A9FF
-.long .L_OP_UNUSED_AAFF
-.long .L_OP_UNUSED_ABFF
-.long .L_OP_UNUSED_ACFF
-.long .L_OP_UNUSED_ADFF
-.long .L_OP_UNUSED_AEFF
-.long .L_OP_UNUSED_AFFF
-.long .L_OP_UNUSED_B0FF
-.long .L_OP_UNUSED_B1FF
-.long .L_OP_UNUSED_B2FF
-.long .L_OP_UNUSED_B3FF
-.long .L_OP_UNUSED_B4FF
-.long .L_OP_UNUSED_B5FF
-.long .L_OP_UNUSED_B6FF
-.long .L_OP_UNUSED_B7FF
-.long .L_OP_UNUSED_B8FF
-.long .L_OP_UNUSED_B9FF
-.long .L_OP_UNUSED_BAFF
-.long .L_OP_UNUSED_BBFF
-.long .L_OP_UNUSED_BCFF
-.long .L_OP_UNUSED_BDFF
-.long .L_OP_UNUSED_BEFF
-.long .L_OP_UNUSED_BFFF
-.long .L_OP_UNUSED_C0FF
-.long .L_OP_UNUSED_C1FF
-.long .L_OP_UNUSED_C2FF
-.long .L_OP_UNUSED_C3FF
-.long .L_OP_UNUSED_C4FF
-.long .L_OP_UNUSED_C5FF
-.long .L_OP_UNUSED_C6FF
-.long .L_OP_UNUSED_C7FF
-.long .L_OP_UNUSED_C8FF
-.long .L_OP_UNUSED_C9FF
-.long .L_OP_UNUSED_CAFF
-.long .L_OP_UNUSED_CBFF
-.long .L_OP_UNUSED_CCFF
-.long .L_OP_UNUSED_CDFF
-.long .L_OP_UNUSED_CEFF
-.long .L_OP_UNUSED_CFFF
-.long .L_OP_UNUSED_D0FF
-.long .L_OP_UNUSED_D1FF
-.long .L_OP_UNUSED_D2FF
-.long .L_OP_UNUSED_D3FF
-.long .L_OP_UNUSED_D4FF
-.long .L_OP_UNUSED_D5FF
-.long .L_OP_UNUSED_D6FF
-.long .L_OP_UNUSED_D7FF
-.long .L_OP_UNUSED_D8FF
-.long .L_OP_UNUSED_D9FF
-.long .L_OP_UNUSED_DAFF
-.long .L_OP_UNUSED_DBFF
-.long .L_OP_UNUSED_DCFF
-.long .L_OP_UNUSED_DDFF
-.long .L_OP_UNUSED_DEFF
-.long .L_OP_UNUSED_DFFF
-.long .L_OP_UNUSED_E0FF
-.long .L_OP_UNUSED_E1FF
-.long .L_OP_UNUSED_E2FF
-.long .L_OP_UNUSED_E3FF
-.long .L_OP_UNUSED_E4FF
-.long .L_OP_UNUSED_E5FF
-.long .L_OP_UNUSED_E6FF
-.long .L_OP_UNUSED_E7FF
-.long .L_OP_UNUSED_E8FF
-.long .L_OP_UNUSED_E9FF
-.long .L_OP_UNUSED_EAFF
-.long .L_OP_UNUSED_EBFF
-.long .L_OP_UNUSED_ECFF
-.long .L_OP_UNUSED_EDFF
-.long .L_OP_UNUSED_EEFF
-.long .L_OP_UNUSED_EFFF
-.long .L_OP_UNUSED_F0FF
-.long .L_OP_UNUSED_F1FF
-.long .L_OP_UNUSED_F2FF
-.long .L_OP_UNUSED_F3FF
-.long .L_OP_UNUSED_F4FF
-.long .L_OP_UNUSED_F5FF
-.long .L_OP_UNUSED_F6FF
-.long .L_OP_UNUSED_F7FF
-.long .L_OP_UNUSED_F8FF
-.long .L_OP_UNUSED_F9FF
-.long .L_OP_UNUSED_FAFF
-.long .L_OP_UNUSED_FBFF
-.long .L_OP_UNUSED_FCFF
-.long .L_OP_UNUSED_FDFF
-.long .L_OP_UNUSED_FEFF
-.long .L_OP_THROW_VERIFICATION_ERROR_JUMBO
diff --git a/vm/mterp/x86/footer.S b/vm/mterp/x86/footer.S
index 721b395..54dcbb4 100644
--- a/vm/mterp/x86/footer.S
+++ b/vm/mterp/x86/footer.S
@@ -39,8 +39,10 @@
movl rPC, OUT_ARG0(%esp)
call dvmBumpPunt
#endif
- FETCH_INST_R %edx
- GOTO_NEXT_R %edx
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx),rIBASE
+ FETCH_INST_R %ecx
+ GOTO_NEXT_R %ecx
.global dvmJitToInterpSingleStep
/*
@@ -80,8 +82,10 @@
call *%eax # exec translation if we've got one
# won't return
1:
- FETCH_INST_R %edx
- GOTO_NEXT_R %edx
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx),rIBASE
+ FETCH_INST_R %ecx
+ GOTO_NEXT_R %ecx
/*
* Return from the translation cache and immediately request a
@@ -107,8 +111,10 @@
GET_JIT_PROF_TABLE %ecx %eax
cmpl $$0, %eax # JIT enabled?
jnz 2f # Request one if so
- FETCH_INST_R %edx # Continue interpreting if not
- GOTO_NEXT_R %edx
+ movl rSELF, %ecx
+ movl offThread_curHandlerTable(%ecx),rIBASE
+ FETCH_INST_R %ecx # Continue interpreting if not
+ GOTO_NEXT_R %ecx
2:
movl $$kJitTSelectRequestHot,rINST # ask for trace select
jmp common_selectTrace
@@ -158,9 +164,10 @@
movl rSELF,%ecx
call common_periodicChecks # rPC and ecx/rSELF preserved
#if defined(WITH_JIT)
- GET_JIT_PROF_TABLE %ecx %edx
+ GET_JIT_PROF_TABLE %ecx rIBASE
ADVANCE_PC_INDEXED rINST
- cmpl $$0,%edx
+ cmpl $$0,rIBASE
+ movl offThread_curHandlerTable(%ecx),rIBASE
FETCH_INST
jz 1f # Profiling off - continue
.global updateProfile
@@ -203,6 +210,7 @@
movl $$1,rINST
jmp common_gotoBail
#else
+ movl offThread_curHandlerTable(%ecx),rIBASE
ADVANCE_PC_INDEXED rINST
FETCH_INST
GOTO_NEXT
@@ -216,6 +224,7 @@
* On entry:
* eax = Method* methodToCall
* rINSTw trashed, must reload
+ * rIBASE trashed, must reload before resuming interpreter
*/
common_invokeMethodJumbo:
@@ -239,6 +248,7 @@
* On entry:
* eax = Method* methodToCall
* rINSTw trashed, must reload
+ * rIBASE trashed, must reload before resuming interpreter
*/
common_invokeMethodRange:
@@ -280,6 +290,7 @@
/*
* %eax is "Method* methodToCall", the method we're trying to call
* prepare to copy args to "outs" area of current frame
+ * rIBASE trashed, must reload before resuming interpreter
*/
common_invokeMethodNoRange:
@@ -386,6 +397,7 @@
movl offMethod_insns(%eax), rPC # rPC<- methodToCall->insns
movl LOCAL1_OFFSET(%ebp), rFP # rFP<- newFP
movl rFP, offThread_curFrame(%ecx) # self->curFrame<- newFP
+ movl offThread_curHandlerTable(%ecx),rIBASE
FETCH_INST
GOTO_NEXT # jump to methodToCall->insns
@@ -401,9 +413,9 @@
movl %eax, offStackSaveArea_localRefCookie(%edx) # newSaveArea->localRefCookie<- top
movl %edx, OUT_ARG4(%esp) # save newSaveArea
movl LOCAL1_OFFSET(%ebp), %edx # %edx<- newFP
- movl %edx, offThread_curFrame(%ecx) # self->self->curFrame<- newFP
- movl %ecx, OUT_ARG3(%esp) # save self->self
- movl %ecx, OUT_ARG2(%esp) # push parameter self->self
+ movl %edx, offThread_curFrame(%ecx) # self->curFrame<- newFP
+ movl %ecx, OUT_ARG3(%esp) # save self
+ movl %ecx, OUT_ARG2(%esp) # push parameter self
movl rSELF,%ecx # %ecx<- pthread
movl OUT_ARG1(%esp), %eax # %eax<- methodToCall
lea offThread_retval(%ecx), %ecx # %ecx<- &retval
@@ -413,15 +425,16 @@
call *offMethod_nativeFunc(%eax) # call methodToCall->nativeFunc
lea 4(%esp), %esp
movl OUT_ARG4(%esp), %ecx # %ecx<- newSaveArea
- movl OUT_ARG3(%esp), %eax # %eax<- self->self
+ movl OUT_ARG3(%esp), %eax # %eax<- self
movl offStackSaveArea_localRefCookie(%ecx), %edx # %edx<- old top
cmp $$0, offThread_exception(%eax) # check for exception
- movl rFP, offThread_curFrame(%eax) # self->self->curFrame<- rFP
+ movl rFP, offThread_curFrame(%eax) # self->curFrame<- rFP
movl %edx, offThread_jniLocal_topCookie(%eax) # new top <- old top
jne common_exceptionThrown # handle exception
- FETCH_INST_OPCODE 3 %edx
+ movl offThread_curHandlerTable(%eax),rIBASE
+ FETCH_INST_OPCODE 3 %ecx
ADVANCE_PC 3
- GOTO_NEXT_R %edx # jump to next instruction
+ GOTO_NEXT_R %ecx # jump to next instruction
.LstackOverflow: # eax=methodToCall
movl %eax, OUT_ARG1(%esp) # push parameter methodToCall
@@ -517,16 +530,17 @@
je common_gotoBail # break frame, bail out completely
movl offStackSaveArea_savedPc(%eax),rPC # pc<- saveArea->savedPC
- movl rINST,offThread_method(%ecx) # self->method = newSave->meethod
- movl rFP,offThread_curFrame(%ecx) # self->curFrame = fp
- movl offMethod_clazz(rINST),%eax # eax<- method->clazz
- FETCH_INST_OPCODE 3 %edx
- movl offClassObject_pDvmDex(%eax),%eax # eax<- method->clazz->pDvmDex
+ movl rINST,offThread_method(%ecx) # self->method = newSave->meethod
+ movl rFP,offThread_curFrame(%ecx) # self->curFrame = fp
+ movl offMethod_clazz(rINST),%eax # eax<- method->clazz
+ movl offThread_curHandlerTable(%ecx),rIBASE
+ movl offClassObject_pDvmDex(%eax),rINST # rINST<- method->clazz->pDvmDex
+ FETCH_INST_OPCODE 3 %eax
+ movl rINST,offThread_methodClassDex(%ecx)
ADVANCE_PC 3
- movl %eax,offThread_methodClassDex(%ecx)
/* not bailing - restore entry mode to default */
movb $$kInterpEntryInstr,offThread_entryPoint(%ecx)
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %eax
/*
* Prepare to strip the current frame and "longjump" back to caller of
@@ -551,7 +565,10 @@
* and start executing at the next instruction.
*/
common_resumeAfterGlueCall:
- LOAD_PC_FP_FROM_SELF
+ movl rSELF, %eax
+ movl offThread_pc(%eax),rPC
+ movl offThread_fp(%eax),rFP
+ movl offThread_curHandlerTable(%eax),rIBASE
FETCH_INST
GOTO_NEXT
diff --git a/vm/mterp/x86/fpcvt.S b/vm/mterp/x86/fpcvt.S
index 22d09bd..983b9eb 100644
--- a/vm/mterp/x86/fpcvt.S
+++ b/vm/mterp/x86/fpcvt.S
@@ -7,8 +7,8 @@
sarl $$4,rINST # rINST<- B
$load (rFP,rINST,4) # %st0<- vB
andb $$0xf,%cl # ecx<- A
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
$instr
$store (rFP,%ecx,4) # vA<- %st0
- GOTO_NEXT_R %edx
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/header.S b/vm/mterp/x86/header.S
index b3791b8..68b9441 100644
--- a/vm/mterp/x86/header.S
+++ b/vm/mterp/x86/header.S
@@ -57,11 +57,12 @@
rINSTw bx first 16-bit code of current instruction
rINSTbl bl opcode portion of instruction word
rINSTbh bh high byte of inst word, usually contains src/tgt reg names
+ rIBASE edx base of instruction handler table
Notes:
o High order 16 bits of ebx must be zero on entry to handler
o rPC, rFP, rINSTw/rINSTbl valid on handler entry and exit
- o eax, edx and ecx are scratch, rINSTw/ebx sometimes scratch
+ o eax and ecx are scratch, rINSTw/ebx sometimes scratch
*/
@@ -72,6 +73,7 @@
#define rINSTw %bx
#define rINSTbh %bh
#define rINSTbl %bl
+#define rIBASE %edx
/* Frame diagram while executing dvmMterpStdRun, high to low addresses */
@@ -86,13 +88,13 @@
#define rPC_SPILL (-16)
#define rFP_SPILL (-20)
#define rINST_SPILL (-24)
-#define TMP_SPILL1 (-28)
-#define TMP_SPILL2 (-32)
-#define TMP_SPILL3 (-36)
-#define LOCAL0_OFFSET (-40)
-#define LOCAL1_OFFSET (-44)
-#define LOCAL2_OFFSET (-48)
-#define LOCAL3_OFFSET (-52)
+#define rIBASE_SPILL (-28)
+#define TMP_SPILL1 (-32)
+#define TMP_SPILL2 (-36)
+#define TMP_SPILL3 (-20)
+#define LOCAL0_OFFSET (-44)
+#define LOCAL1_OFFSET (-48)
+#define LOCAL2_OFFSET (-52)
/* Out Arg offsets, relative to %sp */
#define OUT_ARG4 ( 16)
#define OUT_ARG3 ( 12)
@@ -214,7 +216,7 @@
.macro GOTO_NEXT
movzx rINSTbl,%eax
movzbl rINSTbh,rINST
- jmp *dvmAsmInstructionJmpTable(,%eax,4)
+ jmp *(rIBASE,%eax,4)
.endm
/*
@@ -223,7 +225,7 @@
*/
.macro GOTO_NEXT_R _reg
movzbl 1(rPC),rINST
- jmp *dvmAsmInstructionJmpTable(,\_reg,4)
+ jmp *(rIBASE,\_reg,4)
.endm
/*
@@ -233,7 +235,7 @@
*/
.macro GOTO_NEXT_JUMBO_R _reg
movzwl 6(rPC),rINST
- jmp *dvmAsmInstructionJmpTable(,\_reg,4)
+ jmp *(rIBASE,\_reg,4)
.endm
/*
@@ -255,310 +257,9 @@
movl \_reg,4*(\_offset)(rFP,\_vreg,4)
.endm
-#if 1
-
-#define rFinish %edx
-
-/* Macros for x86-atom handlers */
- /*
- * Get the 32-bit value from a dalvik register.
- */
-
- .macro GET_VREG _vreg
- movl (rFP,\_vreg, 4), \_vreg
- .endm
-
- /*
- * Fetch the next instruction from the specified offset. Advances rPC
- * to point to the next instruction. "_count" is in 16-bit code units.
- *
- * This must come AFTER anything that can throw an exception, or the
- * exception catch may miss. (This also implies that it must come after
- * EXPORT_PC())
- */
-
- .macro FETCH_ADVANCE_INST _count
- add $$(\_count*2), rPC
- movzwl (rPC), rINST
- .endm
-
- /*
- * Fetch the next instruction from an offset specified by _reg. Updates
- * rPC to point to the next instruction. "_reg" must specify the distance
- * in bytes, *not* 16-bit code units, and may be a signed value.
- */
-
- .macro FETCH_ADVANCE_INST_RB _reg
- addl \_reg, rPC
- movzwl (rPC), rINST
- .endm
-
- /*
- * Fetch a half-word code unit from an offset past the current PC. The
- * "_count" value is in 16-bit code units. Does not advance rPC.
- * For example, given instruction of format: AA|op BBBB, it
- * fetches BBBB.
- */
-
- .macro FETCH _count _reg
- movzwl (\_count*2)(rPC), \_reg
- .endm
-
- /*
- * Fetch a half-word code unit from an offset past the current PC. The
- * "_count" value is in 16-bit code units. Does not advance rPC.
- * This variant treats the value as signed.
- */
-
- .macro FETCHs _count _reg
- movswl (\_count*2)(rPC), \_reg
- .endm
-
- /*
- * Fetch the first byte from an offset past the current PC. The
- * "_count" value is in 16-bit code units. Does not advance rPC.
- * For example, given instruction of format: AA|op CC|BB, it
- * fetches BB.
- */
-
- .macro FETCH_BB _count _reg
- movzbl (\_count*2)(rPC), \_reg
- .endm
-
- /*
- * Fetch the second byte from an offset past the current PC. The
- * "_count" value is in 16-bit code units. Does not advance rPC.
- * For example, given instruction of format: AA|op CC|BB, it
- * fetches CC.
- */
-
- .macro FETCH_CC _count _reg
- movzbl (\_count*2 + 1)(rPC), \_reg
- .endm
-
- /*
- * Fetch the second byte from an offset past the current PC. The
- * "_count" value is in 16-bit code units. Does not advance rPC.
- * This variant treats the value as signed.
- */
-
- .macro FETCH_CCs _count _reg
- movsbl (\_count*2 + 1)(rPC), \_reg
- .endm
-
-
- /*
- * Fetch one byte from an offset past the current PC. Pass in the same
- * "_count" as you would for FETCH, and an additional 0/1 indicating which
- * byte of the halfword you want (lo/hi).
- */
-
- .macro FETCH_B _reg _count _byte
- movzbl (\_count*2+\_byte)(rPC), \_reg
- .endm
-
- /*
- * Put the instruction's opcode field into the specified register.
- */
-
- .macro GET_INST_OPCODE _reg
- movzbl rINSTbl, \_reg
- .endm
-
- /*
- * Begin executing the opcode in _reg.
- */
-
- .macro GOTO_OPCODE _reg
- shl $$${handler_size_bits}, \_reg
- addl $$dvmAsmInstructionStart,\_reg
- jmp *\_reg
- .endm
-
-
-
- /*
- * Macros pair attempts to speed up FETCH_INST, GET_INST_OPCODE and GOTO_OPCODE
- * by using a jump table. _rFinish should must be the same register for
- * both macros.
- */
-
- .macro FFETCH _rFinish
- movzbl (rPC), \_rFinish
- .endm
-
- .macro FGETOP_JMPa _rFinish
- movzbl 1(rPC), rINST
- jmp *dvmAsmInstructionJmpTable(,\_rFinish, 4)
- .endm
-
- /*
- * Macro pair attempts to speed up FETCH_INST, GET_INST_OPCODE and GOTO_OPCODE
- * by using a jump table. _rFinish and _count should must be the same register for
- * both macros.
- */
-
- .macro FFETCH_ADV _count _rFinish
- movzbl (\_count*2)(rPC), \_rFinish
- .endm
-
- .macro FGETOP_JMP _count _rFinish
- movzbl (\_count*2 + 1)(rPC), rINST
- addl $$(\_count*2), rPC
- jmp *dvmAsmInstructionJmpTable(,\_rFinish, 4)
- .endm
-
- .macro FGETOP_JMP2 _rFinish
- movzbl 1(rPC), rINST
- jmp *dvmAsmInstructionJmpTable(,\_rFinish, 4)
- .endm
-
- .macro OLD_JMP_1 _count _rFinish
- movzbl (\_count*2)(rPC), \_rFinish
- shl $$${handler_size_bits}, \_rFinish
- .endm
-
- .macro OLD_JMP_2 _rFinish
- addl $$dvmAsmInstructionStart,\_rFinish
- .endm
-
- .macro OLD_JMP_3 _count
- addl $$(\_count*2), rPC
- .endm
-
- .macro OLD_JMP_4 _rFinish
- movzbl 1(rPC), rINST
- jmp *\_rFinish
- .endm
-
- .macro OLD_JMP_A_1 _reg _rFinish
- movzbl (rPC, \_reg), \_rFinish
- shl $$${handler_size_bits}, \_rFinish
- .endm
-
- .macro OLD_JMP_A_2 _rFinish
- addl $$dvmAsmInstructionStart,\_rFinish
- .endm
-
- .macro OLD_JMP_A_3 _reg _rFinish
- addl \_reg, rPC
- movzbl 1(rPC, \_reg), rINST
- jmp *\_rFinish
- .endm
-
- /*
- * Macro pair attempts to speed up FETCH_INST, GET_INST_OPCODE and GOTO_OPCODE
- * by using a jump table. _rFinish and _reg should must be the same register for
- * both macros.
- */
-
- .macro FFETCH_ADV_RB _reg _rFinish
- movzbl (\_reg, rPC), \_rFinish
- .endm
-
- .macro FGETOP_RB_JMP _reg _rFinish
- movzbl 1(\_reg, rPC), rINST
- addl \_reg, rPC
- jmp *dvmAsmInstructionJmpTable(,\_rFinish, 4)
- .endm
-
- /*
- * Attempts to speed up FETCH_INST, GET_INST_OPCODE using
- * a jump table. This macro should be called before FINISH_JMP where
- * rFinish should be the same register containing the opcode value.
- * This is an attempt to split up FINISH in order to reduce or remove
- * potential stalls due to the wait for rFINISH.
- */
-
- .macro FINISH_FETCH _rFinish
- movzbl (rPC), \_rFinish
- movzbl 1(rPC), rINST
- .endm
-
-
- /*
- * Attempts to speed up FETCH_ADVANCE_INST, GET_INST_OPCODE using
- * a jump table. This macro should be called before FINISH_JMP where
- * rFinish should be the same register containing the opcode value.
- * This is an attempt to split up FINISH in order to reduce or remove
- * potential stalls due to the wait for rFINISH.
- */
-
- .macro FINISH_FETCH_ADVANCE _count _rFinish
- movzbl (\_count*2)(rPC), \_rFinish
- movzbl (\_count*2 + 1)(rPC), rINST
- addl $$(\_count*2), rPC
- .endm
-
- /*
- * Attempts to speed up FETCH_ADVANCE_INST_RB, GET_INST_OPCODE using
- * a jump table. This macro should be called before FINISH_JMP where
- * rFinish should be the same register containing the opcode value.
- * This is an attempt to split up FINISH in order to reduce or remove
- * potential stalls due to the wait for rFINISH.
- */
-
- .macro FINISH_FETCH_ADVANCE_RB _reg _rFinish
- movzbl (\_reg, rPC), \_rFinish
- movzbl 1(\_reg, rPC), rINST
- addl \_reg, rPC
- .endm
-
- /*
- * Attempts to speed up GOTO_OPCODE using a jump table. This macro should
- * be called after a FINISH_FETCH* instruction where rFinish should be the
- * same register containing the opcode value. This is an attempt to split up
- * FINISH in order to reduce or remove potential stalls due to the wait for rFINISH.
- */
-
- .macro FINISH_JMP _rFinish
- jmp *dvmAsmInstructionJmpTable(,\_rFinish, 4)
- .endm
-
- /*
- * Attempts to speed up FETCH_INST, GET_INST_OPCODE, GOTO_OPCODE by using
- * a jump table. Uses a single macro - but it should be faster if we
- * split up the fetch for rFinish and the jump using rFinish.
- */
-
- .macro FINISH_A
- movzbl (rPC), rFinish
- movzbl 1(rPC), rINST
- jmp *dvmAsmInstructionJmpTable(,rFinish, 4)
- .endm
-
- /*
- * Attempts to speed up FETCH_ADVANCE_INST, GET_INST_OPCODE,
- * GOTO_OPCODE by using a jump table. Uses a single macro -
- * but it should be faster if we split up the fetch for rFinish
- * and the jump using rFinish.
- */
-
- .macro FINISH _count
- movzbl (\_count*2)(rPC), rFinish
- movzbl (\_count*2 + 1)(rPC), rINST
- addl $$(\_count*2), rPC
- jmp *dvmAsmInstructionJmpTable(,rFinish, 4)
- .endm
-
- /*
- * Attempts to speed up FETCH_ADVANCE_INST_RB, GET_INST_OPCODE,
- * GOTO_OPCODE by using a jump table. Uses a single macro -
- * but it should be faster if we split up the fetch for rFinish
- * and the jump using rFinish.
- */
-
- .macro FINISH_RB _reg _rFinish
- movzbl (\_reg, rPC), \_rFinish
- movzbl 1(\_reg, rPC), rINST
- addl \_reg, rPC
- jmp *dvmAsmInstructionJmpTable(,\_rFinish, 4)
- .endm
-
#define sReg0 LOCAL0_OFFSET(%ebp)
#define sReg1 LOCAL1_OFFSET(%ebp)
#define sReg2 LOCAL2_OFFSET(%ebp)
-#define sReg3 LOCAL3_OFFSET(%ebp)
/*
* Hard coded helper values.
@@ -594,7 +295,6 @@
.LintMax:
.long 0x7FFFFFFF
-#endif
/*
diff --git a/vm/mterp/x86/shop2addr.S b/vm/mterp/x86/shop2addr.S
index c1c0e17..c891259 100644
--- a/vm/mterp/x86/shop2addr.S
+++ b/vm/mterp/x86/shop2addr.S
@@ -9,7 +9,7 @@
andb $$0xf,rINSTbl # rINST<- A
GET_VREG_R %eax rINST # eax<- vAA
$instr # ex: sarl %cl,%eax
- FETCH_INST_OPCODE 1 %edx
+ FETCH_INST_OPCODE 1 %ecx
SET_VREG $result rINST
ADVANCE_PC 1
- GOTO_NEXT_R %edx
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/stub.S b/vm/mterp/x86/stub.S
index 9799bed..fb5c977 100644
--- a/vm/mterp/x86/stub.S
+++ b/vm/mterp/x86/stub.S
@@ -2,7 +2,8 @@
SAVE_PC_FP_TO_SELF %ecx # leaves rSELF in %ecx
movl %ecx,OUT_ARG0(%esp) # self is first arg to function
call dvmMterp_${opcode} # do the real work
- mov rSELF,%ecx
+ movl rSELF,%ecx
LOAD_PC_FP_FROM_SELF # retrieve updated values
+ movl offThread_curHandlerTable(%ecx),rIBASE # set up rIBASE
FETCH_INST
GOTO_NEXT
diff --git a/vm/mterp/x86/unop.S b/vm/mterp/x86/unop.S
index faa41f4..ad9c79b 100644
--- a/vm/mterp/x86/unop.S
+++ b/vm/mterp/x86/unop.S
@@ -8,10 +8,10 @@
sarl $$4,rINST # rINST<- B
GET_VREG_R %eax rINST # eax<- vB
andb $$0xf,%cl # ecx<- A
- FETCH_INST_OPCODE 1 %edx
- ADVANCE_PC 1
$pre0
$pre1
$instr
SET_VREG %eax %ecx
- GOTO_NEXT_R %edx
+ FETCH_INST_OPCODE 1 %ecx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %ecx
diff --git a/vm/mterp/x86/unopWide.S b/vm/mterp/x86/unopWide.S
index 385b4ba..41b5d10 100644
--- a/vm/mterp/x86/unopWide.S
+++ b/vm/mterp/x86/unopWide.S
@@ -14,8 +14,8 @@
$instr1 # ex: negl %eax
$instr2 # ex: adcl $$0,%ecx
$instr3 # ex: negl %ecx
- GET_INST_OPCODE 1 %edx
- ADVANCE_PC 1
SET_VREG_WORD %eax rINST 0 # v[A+0] <- eax
+ GET_INST_OPCODE 1 %eax
SET_VREG_WORD %ecx rINST 1 # v[A+1] <- ecx
- GOTO_NEXT_R %edx
+ ADVANCE_PC 1
+ GOTO_NEXT_R %eax
