Atomic op cleanup.
Replaced VM-local macros for barrier and CAS calls with the actual
versions provided by cutils.
ATOMIC_CMP_SWAP(addr,old,new) --> android_atomic_release_cas(old,new,addr)
MEM_BARRIER --> ANDROID_MEMBAR_FULL
Renamed android_quasiatomic* to dvmQuasiAtomic*.
Didn't change how anything works, just the names.
Change-Id: I8c68f28e1f7c9cb832183e0918d097dfe6a2cac8
diff --git a/vm/Atomic.c b/vm/Atomic.c
index 5ea5250..4cc425e 100644
--- a/vm/Atomic.c
+++ b/vm/Atomic.c
@@ -24,6 +24,8 @@
* TODO: unify ARM/x86/sh implementations using the to-be-written
* spin lock implementation. We don't want to rely on mutex innards,
* and it would be great if all platforms were running the same code.
+ *
+ * TODO: provide ARMv7-A-specific implementation using LDREXD/STREXD.
*/
#if defined(HAVE_MACOSX_IPC)
@@ -40,13 +42,15 @@
#define NEED_QUASIATOMICS 1
#else
-int android_quasiatomic_cmpxchg_64(int64_t oldvalue, int64_t newvalue,
- volatile int64_t* addr) {
+int dvmQuasiAtomicCas64(int64_t oldvalue, int64_t newvalue,
+ volatile int64_t* addr)
+{
return OSAtomicCompareAndSwap64Barrier(oldvalue, newvalue,
(int64_t*)addr) == 0;
}
-int64_t android_quasiatomic_swap_64(int64_t value, volatile int64_t* addr) {
+int64_t dvmQuasiAtomicSwap64(int64_t value, volatile int64_t* addr)
+{
int64_t oldValue;
do {
oldValue = *addr;
@@ -54,7 +58,8 @@
return oldValue;
}
-int64_t android_quasiatomic_read_64(volatile int64_t* addr) {
+int64_t dvmQuasiAtomicRead64(volatile int64_t* addr)
+{
return OSAtomicAdd64Barrier(0, addr);
}
#endif
@@ -89,7 +94,8 @@
&_swap_locks[((unsigned)(void*)(addr) >> 3U) % SWAP_LOCK_COUNT]
-int64_t android_quasiatomic_swap_64(int64_t value, volatile int64_t* addr) {
+int64_t dvmQuasiAtomicSwap64(int64_t value, volatile int64_t* addr)
+{
int64_t oldValue;
pthread_mutex_t* lock = SWAP_LOCK(addr);
@@ -102,8 +108,9 @@
return oldValue;
}
-int android_quasiatomic_cmpxchg_64(int64_t oldvalue, int64_t newvalue,
- volatile int64_t* addr) {
+int dvmQuasiAtomicCas64(int64_t oldvalue, int64_t newvalue,
+ volatile int64_t* addr)
+{
int result;
pthread_mutex_t* lock = SWAP_LOCK(addr);
@@ -119,7 +126,8 @@
return result;
}
-int64_t android_quasiatomic_read_64(volatile int64_t* addr) {
+int64_t dvmQuasiAtomicRead64(volatile int64_t* addr)
+{
int64_t result;
pthread_mutex_t* lock = SWAP_LOCK(addr);
@@ -162,8 +170,9 @@
/* global spinlock for all 64-bit quasiatomic operations */
static int32_t quasiatomic_spinlock = 0;
-int android_quasiatomic_cmpxchg_64(int64_t oldvalue, int64_t newvalue,
- volatile int64_t* addr) {
+int dvmQuasiAtomicCas64(int64_t oldvalue, int64_t newvalue,
+ volatile int64_t* addr)
+{
int result;
while (android_atomic_acquire_cas(0, 1, &quasiatomic_spinlock)) {
@@ -186,7 +195,8 @@
return result;
}
-int64_t android_quasiatomic_read_64(volatile int64_t* addr) {
+int64_t dvmQuasiAtomicRead64(volatile int64_t* addr)
+{
int64_t result;
while (android_atomic_acquire_cas(0, 1, &quasiatomic_spinlock)) {
@@ -203,7 +213,8 @@
return result;
}
-int64_t android_quasiatomic_swap_64(int64_t value, volatile int64_t* addr) {
+int64_t dvmQuasiAtomicSwap64(int64_t value, volatile int64_t* addr)
+{
int64_t result;
while (android_atomic_acquire_cas(0, 1, &quasiatomic_spinlock)) {
diff --git a/vm/Atomic.h b/vm/Atomic.h
index 27a5ea0..0585c95 100644
--- a/vm/Atomic.h
+++ b/vm/Atomic.h
@@ -24,42 +24,32 @@
#include <cutils/atomic-inline.h> /* and some uncommon ones */
/*
- * Full memory barrier. Ensures compiler ordering and SMP behavior.
- */
-#define MEM_BARRIER() ANDROID_MEMBAR_FULL()
-
-/*
- * 32-bit atomic compare-and-swap macro. Performs a memory barrier
- * before the swap (store-release).
- *
- * If *_addr equals "_old", replace it with "_new" and return nonzero
- * (i.e. returns "false" if the operation fails).
- *
- * Underlying function is currently declared:
- * int release_cas(int32_t old, int32_t new, volatile int32_t* addr)
- *
- * TODO: rename macro to ATOMIC_RELEASE_CAS
- */
-#define ATOMIC_CMP_SWAP(_addr, _old, _new) \
- (android_atomic_release_cas((_old), (_new), (_addr)) == 0)
-
-
-/*
* NOTE: Two "quasiatomic" operations on the exact same memory address
* are guaranteed to operate atomically with respect to each other,
* but no guarantees are made about quasiatomic operations mixed with
* non-quasiatomic operations on the same address, nor about
* quasiatomic operations that are performed on partially-overlapping
* memory.
+ *
+ * None of these provide a memory barrier.
*/
/*
- * TODO: rename android_quasiatomic_* to dvmQuasiatomic*. Don't want to do
- * that yet due to branch merge issues.
+ * Swap the 64-bit value at "addr" with "value". Returns the previous
+ * value.
*/
-int64_t android_quasiatomic_swap_64(int64_t value, volatile int64_t* addr);
-int64_t android_quasiatomic_read_64(volatile int64_t* addr);
-int android_quasiatomic_cmpxchg_64(int64_t oldvalue, int64_t newvalue,
+int64_t dvmQuasiAtomicSwap64(int64_t value, volatile int64_t* addr);
+
+/*
+ * Read the 64-bit value at "addr".
+ */
+int64_t dvmQuasiAtomicRead64(volatile int64_t* addr);
+
+/*
+ * If the value at "addr" is equal to "oldvalue", replace it with "newvalue"
+ * and return 0. Otherwise, don't swap, and return nonzero.
+ */
+int dvmQuasiAtomicCas64(int64_t oldvalue, int64_t newvalue,
volatile int64_t* addr);
#endif /*_DALVIK_ATOMIC*/
diff --git a/vm/AtomicCache.c b/vm/AtomicCache.c
index f91de1e..b4f9862 100644
--- a/vm/AtomicCache.c
+++ b/vm/AtomicCache.c
@@ -105,8 +105,9 @@
* the version counter (at 2^31). Probably not a real concern.
*/
if ((firstVersion & ATOMIC_LOCK_FLAG) != 0 ||
- !ATOMIC_CMP_SWAP((volatile s4*) &pEntry->version,
- firstVersion, firstVersion | ATOMIC_LOCK_FLAG))
+ android_atomic_release_cas(
+ firstVersion, firstVersion | ATOMIC_LOCK_FLAG,
+ (volatile s4*) &pEntry->version) != 0)
{
/*
* We couldn't get the write lock. Return without updating the table.
@@ -130,7 +131,7 @@
/* volatile incr */
pEntry->version++;
- MEM_BARRIER();
+ ANDROID_MEMBAR_FULL();
pEntry->key1 = key1;
pEntry->key2 = key2;
@@ -138,15 +139,16 @@
/* volatile incr */
pEntry->version++;
- MEM_BARRIER();
+ ANDROID_MEMBAR_FULL();
/*
* Clear the lock flag. Nobody else should have been able to modify
* pEntry->version, so if this fails the world is broken.
*/
firstVersion += 2;
- if (!ATOMIC_CMP_SWAP((volatile s4*) &pEntry->version,
- firstVersion | ATOMIC_LOCK_FLAG, firstVersion))
+ if (android_atomic_release_cas(
+ firstVersion | ATOMIC_LOCK_FLAG, firstVersion,
+ (volatile s4*) &pEntry->version) != 0)
{
//LOGE("unable to reset the instanceof cache ownership\n");
dvmAbort();
diff --git a/vm/Profile.c b/vm/Profile.c
index a8d1d8a..f2c0c0f 100644
--- a/vm/Profile.c
+++ b/vm/Profile.c
@@ -227,7 +227,8 @@
LOGE("Can't have %d active profilers\n", newValue);
dvmAbort();
}
- } while (!ATOMIC_CMP_SWAP(&gDvm.activeProfilers, oldValue, newValue));
+ } while (android_atomic_release_cas(oldValue, newValue,
+ &gDvm.activeProfilers) != 0);
LOGD("+++ active profiler count now %d\n", newValue);
#if defined(WITH_JIT)
@@ -404,7 +405,7 @@
storeLongLE(state->buf + 8, state->startWhen);
state->curOffset = TRACE_HEADER_LEN;
- MEM_BARRIER();
+ ANDROID_MEMBAR_FULL();
/*
* Set the "enabled" flag. Once we do this, threads will wait to be
@@ -519,7 +520,7 @@
* after that completes.
*/
state->traceEnabled = false;
- MEM_BARRIER();
+ ANDROID_MEMBAR_FULL();
sched_yield();
usleep(250 * 1000);
@@ -696,7 +697,8 @@
state->overflow = true;
return;
}
- } while (!ATOMIC_CMP_SWAP(&state->curOffset, oldOffset, newOffset));
+ } while (android_atomic_release_cas(oldOffset, newOffset,
+ &state->curOffset) != 0);
//assert(METHOD_ACTION((u4) method) == 0);
diff --git a/vm/Sync.c b/vm/Sync.c
index 8f906ac..5380f3e 100644
--- a/vm/Sync.c
+++ b/vm/Sync.c
@@ -170,8 +170,8 @@
/* replace the head of the list with the new monitor */
do {
mon->next = gDvm.monitorList;
- } while (!ATOMIC_CMP_SWAP((int32_t*)(void*)&gDvm.monitorList,
- (int32_t)mon->next, (int32_t)mon));
+ } while (android_atomic_release_cas((int32_t)mon->next, (int32_t)mon,
+ (int32_t*)(void*)&gDvm.monitorList) != 0);
return mon;
}
@@ -894,7 +894,7 @@
thin &= LW_HASH_STATE_MASK << LW_HASH_STATE_SHIFT;
thin |= (u4)mon | LW_SHAPE_FAT;
/* Publish the updated lock word. */
- MEM_BARRIER();
+ ANDROID_MEMBAR_FULL();
obj->lock = thin;
}
@@ -937,7 +937,8 @@
* will have tried this before calling out to the VM.
*/
newThin = thin | (threadId << LW_LOCK_OWNER_SHIFT);
- if (!ATOMIC_CMP_SWAP((int32_t *)thinp, thin, newThin)) {
+ if (android_atomic_release_cas(thin, newThin,
+ (int32_t*)thinp) != 0) {
/*
* The acquire failed. Try again.
*/
@@ -969,8 +970,8 @@
* owner field.
*/
newThin = thin | (threadId << LW_LOCK_OWNER_SHIFT);
- if (ATOMIC_CMP_SWAP((int32_t *)thinp,
- thin, newThin)) {
+ if (android_atomic_release_cas(thin, newThin,
+ (int32_t *)thinp) == 0) {
/*
* The acquire succeed. Break out of the
* loop and proceed to inflate the lock.
@@ -1291,7 +1292,7 @@
* something.
*/
thread->interrupted = true;
- MEM_BARRIER();
+ ANDROID_MEMBAR_FULL();
/*
* Is the thread waiting?
@@ -1379,9 +1380,10 @@
*/
lock = DVM_LOCK_INITIAL_THIN_VALUE;
lock |= (LW_HASH_STATE_HASHED << LW_HASH_STATE_SHIFT);
- if (ATOMIC_CMP_SWAP((int32_t *)lw,
+ if (android_atomic_release_cas(
(int32_t)DVM_LOCK_INITIAL_THIN_VALUE,
- (int32_t)lock)) {
+ (int32_t)lock,
+ (int32_t *)lw) == 0) {
/*
* A new lockword has been installed with a hash state
* of hashed. Use the raw object address.
diff --git a/vm/compiler/codegen/arm/Assemble.c b/vm/compiler/codegen/arm/Assemble.c
index abc07c8..3dc4b29 100644
--- a/vm/compiler/codegen/arm/Assemble.c
+++ b/vm/compiler/codegen/arm/Assemble.c
@@ -1453,7 +1453,7 @@
* The update order matters - make sure clazz is updated last since it
* will bring the uninitialized chaining cell to life.
*/
- MEM_BARRIER();
+ ANDROID_MEMBAR_FULL();
cellAddr->clazz = newContent->clazz;
cacheflush((intptr_t) cellAddr, (intptr_t) (cellAddr+1), 0);
UPDATE_CODE_CACHE_PATCHES();
diff --git a/vm/interp/Interp.c b/vm/interp/Interp.c
index d6c3bc1..dafdbda 100644
--- a/vm/interp/Interp.c
+++ b/vm/interp/Interp.c
@@ -273,7 +273,7 @@
*addr, method->clazz->descriptor, method->name,
instrOffset);
} else {
- MEM_BARRIER();
+ ANDROID_MEMBAR_FULL();
dvmDexChangeDex1(method->clazz->pDvmDex, (u1*)addr,
OP_BREAKPOINT);
}
@@ -328,7 +328,7 @@
*/
dvmDexChangeDex1(method->clazz->pDvmDex, (u1*)addr,
pBreak->originalOpCode);
- MEM_BARRIER();
+ ANDROID_MEMBAR_FULL();
if (idx != pSet->count-1) {
/* shift down */
diff --git a/vm/interp/Jit.c b/vm/interp/Jit.c
index 4c28993..ebf308e 100644
--- a/vm/interp/Jit.c
+++ b/vm/interp/Jit.c
@@ -499,8 +499,8 @@
oldValue = slot->u;
newValue = oldValue;
newValue.info.traceConstruction = value;
- } while (!ATOMIC_CMP_SWAP( &slot->u.infoWord,
- oldValue.infoWord, newValue.infoWord));
+ } while (android_atomic_release_cas(oldValue.infoWord, newValue.infoWord,
+ &slot->u.infoWord) != 0);
}
void resetTracehead(InterpState* interpState, JitEntry *slot)
@@ -546,7 +546,7 @@
* (the simple, and common case). Otherwise we're going
* to have to find a free slot and chain it.
*/
- MEM_BARRIER(); /* Make sure we reload [].dPC after lock */
+ ANDROID_MEMBAR_FULL(); /* Make sure we reload [].dPC after lock */
if (gDvmJit.pJitEntryTable[idx].dPC != NULL) {
u4 prev;
while (gDvmJit.pJitEntryTable[idx].u.info.chain != chainEndMarker) {
@@ -583,9 +583,9 @@
oldValue = gDvmJit.pJitEntryTable[prev].u;
newValue = oldValue;
newValue.info.chain = idx;
- } while (!ATOMIC_CMP_SWAP(
- &gDvmJit.pJitEntryTable[prev].u.infoWord,
- oldValue.infoWord, newValue.infoWord));
+ } while (android_atomic_release_cas(oldValue.infoWord,
+ newValue.infoWord,
+ &gDvmJit.pJitEntryTable[prev].u.infoWord) != 0);
}
}
if (gDvmJit.pJitEntryTable[idx].dPC == NULL) {
@@ -935,9 +935,9 @@
oldValue = jitEntry->u;
newValue = oldValue;
newValue.info.instructionSet = set;
- } while (!ATOMIC_CMP_SWAP(
- &jitEntry->u.infoWord,
- oldValue.infoWord, newValue.infoWord));
+ } while (android_atomic_release_cas(
+ oldValue.infoWord, newValue.infoWord,
+ &jitEntry->u.infoWord) != 0);
jitEntry->codeAddress = nPC;
}
diff --git a/vm/jdwp/JdwpHandler.c b/vm/jdwp/JdwpHandler.c
index 978b56b..8dd4cc6 100644
--- a/vm/jdwp/JdwpHandler.c
+++ b/vm/jdwp/JdwpHandler.c
@@ -2114,7 +2114,7 @@
dvmDbgActive();
state->lastActivitySec = 0;
- MEM_BARRIER();
+ ANDROID_MEMBAR_FULL();
}
/*
@@ -2196,7 +2196,7 @@
dvmJdwpGetNowMsec(&lastSec, &lastMsec);
state->lastActivityMsec = lastMsec;
- MEM_BARRIER(); // updating a 64-bit value
+ ANDROID_MEMBAR_FULL(); // updating a 64-bit value
state->lastActivitySec = lastSec;
}
diff --git a/vm/jdwp/JdwpMain.c b/vm/jdwp/JdwpMain.c
index 66d999c..96747ad 100644
--- a/vm/jdwp/JdwpMain.c
+++ b/vm/jdwp/JdwpMain.c
@@ -231,7 +231,7 @@
*/
state->debugThreadHandle = dvmThreadSelf()->handle;
state->run = true;
- MEM_BARRIER();
+ ANDROID_MEMBAR_FULL();
state->debugThreadStarted = true; // touch this last
dvmDbgLockMutex(&state->threadStartLock);
diff --git a/vm/mterp/armv4t/OP_IGET_WIDE.S b/vm/mterp/armv4t/OP_IGET_WIDE.S
index a725ca3..5940f56 100644
--- a/vm/mterp/armv4t/OP_IGET_WIDE.S
+++ b/vm/mterp/armv4t/OP_IGET_WIDE.S
@@ -36,7 +36,7 @@
beq common_errNullObject @ object was null
.if $volatile
add r0, r9, r3 @ r0<- address of field
- bl android_quasiatomic_read_64 @ r0/r1<- contents of field
+ bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
.else
add r9, r9, r3 @ r9<- obj + field offset
ldmia r9, {r0-r1} @ r0/r1<- obj.field (64-bit align ok)
diff --git a/vm/mterp/armv4t/OP_IPUT_WIDE.S b/vm/mterp/armv4t/OP_IPUT_WIDE.S
index 482a0b2..d0f7315 100644
--- a/vm/mterp/armv4t/OP_IPUT_WIDE.S
+++ b/vm/mterp/armv4t/OP_IPUT_WIDE.S
@@ -39,7 +39,7 @@
GET_INST_OPCODE(r10) @ extract opcode from rINST
add r2, r9, r3 @ r2<- object + byte offset
.if $volatile
- bl android_quasiatomic_swap_64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
.else
stmia r2, {r0-r1} @ obj.field (64 bits, aligned)<- r0/r1
.endif
diff --git a/vm/mterp/armv4t/OP_SGET_WIDE.S b/vm/mterp/armv4t/OP_SGET_WIDE.S
index 102b577..91e195d 100644
--- a/vm/mterp/armv4t/OP_SGET_WIDE.S
+++ b/vm/mterp/armv4t/OP_SGET_WIDE.S
@@ -17,7 +17,7 @@
mov r9, rINST, lsr #8 @ r9<- AA
add r0, r0, #offStaticField_value @ r0<- pointer to data
.if $volatile
- bl android_quasiatomic_read_64 @ r0/r1<- contents of field
+ bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
.else
ldmia r0, {r0-r1} @ r0/r1<- field value (aligned)
.endif
diff --git a/vm/mterp/armv4t/OP_SPUT_WIDE.S b/vm/mterp/armv4t/OP_SPUT_WIDE.S
index 8f92ed6..a67e2d8 100644
--- a/vm/mterp/armv4t/OP_SPUT_WIDE.S
+++ b/vm/mterp/armv4t/OP_SPUT_WIDE.S
@@ -21,7 +21,7 @@
GET_INST_OPCODE(r10) @ extract opcode from rINST
add r2, r2, #offStaticField_value @ r2<- pointer to data
.if $volatile
- bl android_quasiatomic_swap_64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
.else
stmia r2, {r0-r1} @ field<- vAA/vAA+1
.endif
diff --git a/vm/mterp/armv5te/OP_IGET_WIDE.S b/vm/mterp/armv5te/OP_IGET_WIDE.S
index 1188361..b1572ba 100644
--- a/vm/mterp/armv5te/OP_IGET_WIDE.S
+++ b/vm/mterp/armv5te/OP_IGET_WIDE.S
@@ -36,7 +36,7 @@
beq common_errNullObject @ object was null
.if $volatile
add r0, r9, r3 @ r0<- address of field
- bl android_quasiatomic_read_64 @ r0/r1<- contents of field
+ bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
.else
ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok)
.endif
diff --git a/vm/mterp/armv5te/OP_IPUT_WIDE.S b/vm/mterp/armv5te/OP_IPUT_WIDE.S
index 64186ca..4a28721 100644
--- a/vm/mterp/armv5te/OP_IPUT_WIDE.S
+++ b/vm/mterp/armv5te/OP_IPUT_WIDE.S
@@ -39,7 +39,7 @@
GET_INST_OPCODE(r10) @ extract opcode from rINST
.if $volatile
add r2, r9, r3 @ r2<- target address
- bl android_quasiatomic_swap_64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
.else
strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
.endif
diff --git a/vm/mterp/armv5te/OP_SGET_WIDE.S b/vm/mterp/armv5te/OP_SGET_WIDE.S
index 908bced..768b9da 100644
--- a/vm/mterp/armv5te/OP_SGET_WIDE.S
+++ b/vm/mterp/armv5te/OP_SGET_WIDE.S
@@ -17,7 +17,7 @@
mov r9, rINST, lsr #8 @ r9<- AA
.if $volatile
add r0, r0, #offStaticField_value @ r0<- pointer to data
- bl android_quasiatomic_read_64 @ r0/r1<- contents of field
+ bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
.else
ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned)
.endif
diff --git a/vm/mterp/armv5te/OP_SPUT_WIDE.S b/vm/mterp/armv5te/OP_SPUT_WIDE.S
index 646b9c9..330c72b 100644
--- a/vm/mterp/armv5te/OP_SPUT_WIDE.S
+++ b/vm/mterp/armv5te/OP_SPUT_WIDE.S
@@ -21,7 +21,7 @@
GET_INST_OPCODE(r10) @ extract opcode from rINST
.if $volatile
add r2, r2, #offStaticField_value @ r2<- pointer to data
- bl android_quasiatomic_swap_64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
.else
strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1
.endif
diff --git a/vm/mterp/out/InterpAsm-armv4t.S b/vm/mterp/out/InterpAsm-armv4t.S
index e94dbfb..17fb783 100644
--- a/vm/mterp/out/InterpAsm-armv4t.S
+++ b/vm/mterp/out/InterpAsm-armv4t.S
@@ -2831,7 +2831,7 @@
mov r9, rINST, lsr #8 @ r9<- AA
add r0, r0, #offStaticField_value @ r0<- pointer to data
.if 0
- bl android_quasiatomic_read_64 @ r0/r1<- contents of field
+ bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
.else
ldmia r0, {r0-r1} @ r0/r1<- field value (aligned)
.endif
@@ -3017,7 +3017,7 @@
GET_INST_OPCODE(r10) @ extract opcode from rINST
add r2, r2, #offStaticField_value @ r2<- pointer to data
.if 0
- bl android_quasiatomic_swap_64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
.else
stmia r2, {r0-r1} @ field<- vAA/vAA+1
.endif
@@ -7508,7 +7508,7 @@
mov r9, rINST, lsr #8 @ r9<- AA
add r0, r0, #offStaticField_value @ r0<- pointer to data
.if 1
- bl android_quasiatomic_read_64 @ r0/r1<- contents of field
+ bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
.else
ldmia r0, {r0-r1} @ r0/r1<- field value (aligned)
.endif
@@ -7542,7 +7542,7 @@
GET_INST_OPCODE(r10) @ extract opcode from rINST
add r2, r2, #offStaticField_value @ r2<- pointer to data
.if 1
- bl android_quasiatomic_swap_64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
.else
stmia r2, {r0-r1} @ field<- vAA/vAA+1
.endif
@@ -8575,7 +8575,7 @@
beq common_errNullObject @ object was null
.if 0
add r0, r9, r3 @ r0<- address of field
- bl android_quasiatomic_read_64 @ r0/r1<- contents of field
+ bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
.else
add r9, r9, r3 @ r9<- obj + field offset
ldmia r9, {r0-r1} @ r0/r1<- obj.field (64-bit align ok)
@@ -8727,7 +8727,7 @@
GET_INST_OPCODE(r10) @ extract opcode from rINST
add r2, r9, r3 @ r2<- object + byte offset
.if 0
- bl android_quasiatomic_swap_64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
.else
stmia r2, {r0-r1} @ obj.field (64 bits, aligned)<- r0/r1
.endif
@@ -9337,7 +9337,7 @@
beq common_errNullObject @ object was null
.if 1
add r0, r9, r3 @ r0<- address of field
- bl android_quasiatomic_read_64 @ r0/r1<- contents of field
+ bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
.else
add r9, r9, r3 @ r9<- obj + field offset
ldmia r9, {r0-r1} @ r0/r1<- obj.field (64-bit align ok)
@@ -9369,7 +9369,7 @@
GET_INST_OPCODE(r10) @ extract opcode from rINST
add r2, r9, r3 @ r2<- object + byte offset
.if 1
- bl android_quasiatomic_swap_64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
.else
stmia r2, {r0-r1} @ obj.field (64 bits, aligned)<- r0/r1
.endif
diff --git a/vm/mterp/out/InterpAsm-armv5te-vfp.S b/vm/mterp/out/InterpAsm-armv5te-vfp.S
index fa0a04d..bfcd110 100644
--- a/vm/mterp/out/InterpAsm-armv5te-vfp.S
+++ b/vm/mterp/out/InterpAsm-armv5te-vfp.S
@@ -2811,7 +2811,7 @@
mov r9, rINST, lsr #8 @ r9<- AA
.if 0
add r0, r0, #offStaticField_value @ r0<- pointer to data
- bl android_quasiatomic_read_64 @ r0/r1<- contents of field
+ bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
.else
ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned)
.endif
@@ -2997,7 +2997,7 @@
GET_INST_OPCODE(r10) @ extract opcode from rINST
.if 0
add r2, r2, #offStaticField_value @ r2<- pointer to data
- bl android_quasiatomic_swap_64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
.else
strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1
.endif
@@ -7188,7 +7188,7 @@
mov r9, rINST, lsr #8 @ r9<- AA
.if 1
add r0, r0, #offStaticField_value @ r0<- pointer to data
- bl android_quasiatomic_read_64 @ r0/r1<- contents of field
+ bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
.else
ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned)
.endif
@@ -7222,7 +7222,7 @@
GET_INST_OPCODE(r10) @ extract opcode from rINST
.if 1
add r2, r2, #offStaticField_value @ r2<- pointer to data
- bl android_quasiatomic_swap_64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
.else
strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1
.endif
@@ -8115,7 +8115,7 @@
beq common_errNullObject @ object was null
.if 0
add r0, r9, r3 @ r0<- address of field
- bl android_quasiatomic_read_64 @ r0/r1<- contents of field
+ bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
.else
ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok)
.endif
@@ -8266,7 +8266,7 @@
GET_INST_OPCODE(r10) @ extract opcode from rINST
.if 0
add r2, r9, r3 @ r2<- target address
- bl android_quasiatomic_swap_64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
.else
strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
.endif
@@ -8876,7 +8876,7 @@
beq common_errNullObject @ object was null
.if 1
add r0, r9, r3 @ r0<- address of field
- bl android_quasiatomic_read_64 @ r0/r1<- contents of field
+ bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
.else
ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok)
.endif
@@ -8907,7 +8907,7 @@
GET_INST_OPCODE(r10) @ extract opcode from rINST
.if 1
add r2, r9, r3 @ r2<- target address
- bl android_quasiatomic_swap_64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
.else
strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
.endif
diff --git a/vm/mterp/out/InterpAsm-armv5te.S b/vm/mterp/out/InterpAsm-armv5te.S
index c8e92d5..9f69bd0 100644
--- a/vm/mterp/out/InterpAsm-armv5te.S
+++ b/vm/mterp/out/InterpAsm-armv5te.S
@@ -2833,7 +2833,7 @@
mov r9, rINST, lsr #8 @ r9<- AA
.if 0
add r0, r0, #offStaticField_value @ r0<- pointer to data
- bl android_quasiatomic_read_64 @ r0/r1<- contents of field
+ bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
.else
ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned)
.endif
@@ -3019,7 +3019,7 @@
GET_INST_OPCODE(r10) @ extract opcode from rINST
.if 0
add r2, r2, #offStaticField_value @ r2<- pointer to data
- bl android_quasiatomic_swap_64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
.else
strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1
.endif
@@ -7510,7 +7510,7 @@
mov r9, rINST, lsr #8 @ r9<- AA
.if 1
add r0, r0, #offStaticField_value @ r0<- pointer to data
- bl android_quasiatomic_read_64 @ r0/r1<- contents of field
+ bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
.else
ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned)
.endif
@@ -7544,7 +7544,7 @@
GET_INST_OPCODE(r10) @ extract opcode from rINST
.if 1
add r2, r2, #offStaticField_value @ r2<- pointer to data
- bl android_quasiatomic_swap_64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
.else
strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1
.endif
@@ -8573,7 +8573,7 @@
beq common_errNullObject @ object was null
.if 0
add r0, r9, r3 @ r0<- address of field
- bl android_quasiatomic_read_64 @ r0/r1<- contents of field
+ bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
.else
ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok)
.endif
@@ -8724,7 +8724,7 @@
GET_INST_OPCODE(r10) @ extract opcode from rINST
.if 0
add r2, r9, r3 @ r2<- target address
- bl android_quasiatomic_swap_64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
.else
strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
.endif
@@ -9334,7 +9334,7 @@
beq common_errNullObject @ object was null
.if 1
add r0, r9, r3 @ r0<- address of field
- bl android_quasiatomic_read_64 @ r0/r1<- contents of field
+ bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
.else
ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok)
.endif
@@ -9365,7 +9365,7 @@
GET_INST_OPCODE(r10) @ extract opcode from rINST
.if 1
add r2, r9, r3 @ r2<- target address
- bl android_quasiatomic_swap_64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
.else
strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
.endif
diff --git a/vm/mterp/out/InterpAsm-armv7-a-neon.S b/vm/mterp/out/InterpAsm-armv7-a-neon.S
index 31c9207..3ac09aa 100644
--- a/vm/mterp/out/InterpAsm-armv7-a-neon.S
+++ b/vm/mterp/out/InterpAsm-armv7-a-neon.S
@@ -2801,7 +2801,7 @@
mov r9, rINST, lsr #8 @ r9<- AA
.if 0
add r0, r0, #offStaticField_value @ r0<- pointer to data
- bl android_quasiatomic_read_64 @ r0/r1<- contents of field
+ bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
.else
ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned)
.endif
@@ -2987,7 +2987,7 @@
GET_INST_OPCODE(r10) @ extract opcode from rINST
.if 0
add r2, r2, #offStaticField_value @ r2<- pointer to data
- bl android_quasiatomic_swap_64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
.else
strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1
.endif
@@ -7132,7 +7132,7 @@
mov r9, rINST, lsr #8 @ r9<- AA
.if 1
add r0, r0, #offStaticField_value @ r0<- pointer to data
- bl android_quasiatomic_read_64 @ r0/r1<- contents of field
+ bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
.else
ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned)
.endif
@@ -7166,7 +7166,7 @@
GET_INST_OPCODE(r10) @ extract opcode from rINST
.if 1
add r2, r2, #offStaticField_value @ r2<- pointer to data
- bl android_quasiatomic_swap_64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
.else
strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1
.endif
@@ -8802,7 +8802,7 @@
beq common_errNullObject @ object was null
.if 1
add r0, r9, r3 @ r0<- address of field
- bl android_quasiatomic_read_64 @ r0/r1<- contents of field
+ bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
.else
ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok)
.endif
@@ -8833,7 +8833,7 @@
GET_INST_OPCODE(r10) @ extract opcode from rINST
.if 1
add r2, r9, r3 @ r2<- target address
- bl android_quasiatomic_swap_64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
.else
strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
.endif
diff --git a/vm/mterp/out/InterpAsm-armv7-a.S b/vm/mterp/out/InterpAsm-armv7-a.S
index 5174fc1..db84031 100644
--- a/vm/mterp/out/InterpAsm-armv7-a.S
+++ b/vm/mterp/out/InterpAsm-armv7-a.S
@@ -2801,7 +2801,7 @@
mov r9, rINST, lsr #8 @ r9<- AA
.if 0
add r0, r0, #offStaticField_value @ r0<- pointer to data
- bl android_quasiatomic_read_64 @ r0/r1<- contents of field
+ bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
.else
ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned)
.endif
@@ -2987,7 +2987,7 @@
GET_INST_OPCODE(r10) @ extract opcode from rINST
.if 0
add r2, r2, #offStaticField_value @ r2<- pointer to data
- bl android_quasiatomic_swap_64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
.else
strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1
.endif
@@ -7132,7 +7132,7 @@
mov r9, rINST, lsr #8 @ r9<- AA
.if 1
add r0, r0, #offStaticField_value @ r0<- pointer to data
- bl android_quasiatomic_read_64 @ r0/r1<- contents of field
+ bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
.else
ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned)
.endif
@@ -7166,7 +7166,7 @@
GET_INST_OPCODE(r10) @ extract opcode from rINST
.if 1
add r2, r2, #offStaticField_value @ r2<- pointer to data
- bl android_quasiatomic_swap_64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
.else
strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1
.endif
@@ -8802,7 +8802,7 @@
beq common_errNullObject @ object was null
.if 1
add r0, r9, r3 @ r0<- address of field
- bl android_quasiatomic_read_64 @ r0/r1<- contents of field
+ bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
.else
ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok)
.endif
@@ -8833,7 +8833,7 @@
GET_INST_OPCODE(r10) @ extract opcode from rINST
.if 1
add r2, r9, r3 @ r2<- target address
- bl android_quasiatomic_swap_64 @ stores r0/r1 into addr r2
+ bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
.else
strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
.endif
diff --git a/vm/native/sun_misc_Unsafe.c b/vm/native/sun_misc_Unsafe.c
index b1f3e83..5294368 100644
--- a/vm/native/sun_misc_Unsafe.c
+++ b/vm/native/sun_misc_Unsafe.c
@@ -106,7 +106,7 @@
// Note: android_atomic_cmpxchg() returns 0 on success, not failure.
int result =
- android_quasiatomic_cmpxchg_64(expectedValue, newValue, address);
+ dvmQuasiAtomicCas64(expectedValue, newValue, address);
RETURN_BOOLEAN(result == 0);
}
@@ -173,7 +173,7 @@
s8 offset = GET_ARG_LONG(args, 2);
volatile s8* address = (volatile s8*) (((u1*) obj) + offset);
- RETURN_LONG(android_quasiatomic_read_64(address));
+ RETURN_LONG(dvmQuasiAtomicRead64(address));
}
/*
@@ -188,7 +188,7 @@
s8 value = GET_ARG_LONG(args, 4);
volatile s8* address = (volatile s8*) (((u1*) obj) + offset);
- android_quasiatomic_swap_64(value, address);
+ dvmQuasiAtomicSwap64(value, address);
RETURN_VOID();
}
diff --git a/vm/oo/Array.c b/vm/oo/Array.c
index 94911b5..6e706ef 100644
--- a/vm/oo/Array.c
+++ b/vm/oo/Array.c
@@ -598,8 +598,8 @@
ClassObject* primClass = createPrimitiveClass(idx);
dvmReleaseTrackedAlloc((Object*) primClass, NULL);
- if (!ATOMIC_CMP_SWAP((int*) &gDvm.primitiveClass[idx],
- 0, (int) primClass))
+ if (android_atomic_release_cas(0, (int) primClass,
+ (int*) &gDvm.primitiveClass[idx]) != 0)
{
/*
* Looks like somebody beat us to it. Free up the one we
diff --git a/vm/oo/Class.c b/vm/oo/Class.c
index db0ce7b..16cba12 100644
--- a/vm/oo/Class.c
+++ b/vm/oo/Class.c
@@ -1129,7 +1129,8 @@
do {
oldValue = gDvm.classSerialNumber;
newValue = oldValue + 1;
- } while (!ATOMIC_CMP_SWAP(&gDvm.classSerialNumber, oldValue, newValue));
+ } while (android_atomic_release_cas(oldValue, newValue,
+ &gDvm.classSerialNumber) != 0);
clazz->serialNumber = (u4) oldValue;
}
diff --git a/vm/oo/Object.h b/vm/oo/Object.h
index 4afc82c..92ec1d6 100644
--- a/vm/oo/Object.h
+++ b/vm/oo/Object.h
@@ -716,7 +716,7 @@
}
INLINE s8 dvmGetFieldLongVolatile(const Object* obj, int offset) {
const s8* addr = BYTE_OFFSET(obj, offset);
- return android_quasiatomic_read_64((s8*)addr);
+ return dvmQuasiAtomicRead64((s8*)addr);
}
INLINE void dvmSetFieldBoolean(Object* obj, int offset, bool val) {
@@ -748,7 +748,7 @@
}
INLINE void dvmSetFieldLongVolatile(Object* obj, int offset, s8 val) {
s8* addr = BYTE_OFFSET(obj, offset);
- android_quasiatomic_swap_64(val, addr);
+ dvmQuasiAtomicSwap64(val, addr);
}
/*
@@ -787,7 +787,7 @@
}
INLINE s8 dvmGetStaticFieldLongVolatile(const StaticField* sfield) {
const s8* addr = &sfield->value.j;
- return android_quasiatomic_read_64((s8*)addr);
+ return dvmQuasiAtomicRead64((s8*)addr);
}
INLINE void dvmSetStaticFieldBoolean(StaticField* sfield, bool val) {
@@ -819,7 +819,7 @@
}
INLINE void dvmSetStaticFieldLongVolatile(StaticField* sfield, s8 val) {
s8* addr = &sfield->value.j;
- android_quasiatomic_swap_64(val, addr);
+ dvmQuasiAtomicSwap64(val, addr);
}
/*
diff --git a/vm/test/AtomicSpeed.c b/vm/test/AtomicSpeed.c
index 0f723fc..db64f36 100644
--- a/vm/test/AtomicSpeed.c
+++ b/vm/test/AtomicSpeed.c
@@ -47,29 +47,29 @@
j += i; j += i; j += i; j += i; j += i;
#else
// succeed 10x (Dream: 155.9ns)
- (void)ATOMIC_CMP_SWAP(valuePtr, 7, 7);
- (void)ATOMIC_CMP_SWAP(valuePtr, 7, 7);
- (void)ATOMIC_CMP_SWAP(valuePtr, 7, 7);
- (void)ATOMIC_CMP_SWAP(valuePtr, 7, 7);
- (void)ATOMIC_CMP_SWAP(valuePtr, 7, 7);
- (void)ATOMIC_CMP_SWAP(valuePtr, 7, 7);
- (void)ATOMIC_CMP_SWAP(valuePtr, 7, 7);
- (void)ATOMIC_CMP_SWAP(valuePtr, 7, 7);
- (void)ATOMIC_CMP_SWAP(valuePtr, 7, 7);
- (void)ATOMIC_CMP_SWAP(valuePtr, 7, 7);
+ (void)android_atomic_release_cas(7, 7, valuePtr);
+ (void)android_atomic_release_cas(7, 7, valuePtr);
+ (void)android_atomic_release_cas(7, 7, valuePtr);
+ (void)android_atomic_release_cas(7, 7, valuePtr);
+ (void)android_atomic_release_cas(7, 7, valuePtr);
+ (void)android_atomic_release_cas(7, 7, valuePtr);
+ (void)android_atomic_release_cas(7, 7, valuePtr);
+ (void)android_atomic_release_cas(7, 7, valuePtr);
+ (void)android_atomic_release_cas(7, 7, valuePtr);
+ (void)android_atomic_release_cas(7, 7, valuePtr);
// fail 10x (Dream: 158.5ns)
/*
- ATOMIC_CMP_SWAP(valuePtr, 6, 7);
- ATOMIC_CMP_SWAP(valuePtr, 6, 7);
- ATOMIC_CMP_SWAP(valuePtr, 6, 7);
- ATOMIC_CMP_SWAP(valuePtr, 6, 7);
- ATOMIC_CMP_SWAP(valuePtr, 6, 7);
- ATOMIC_CMP_SWAP(valuePtr, 6, 7);
- ATOMIC_CMP_SWAP(valuePtr, 6, 7);
- ATOMIC_CMP_SWAP(valuePtr, 6, 7);
- ATOMIC_CMP_SWAP(valuePtr, 6, 7);
- ATOMIC_CMP_SWAP(valuePtr, 6, 7);
+ (void)android_atomic_release_cas(6, 7, valuePtr);
+ (void)android_atomic_release_cas(6, 7, valuePtr);
+ (void)android_atomic_release_cas(6, 7, valuePtr);
+ (void)android_atomic_release_cas(6, 7, valuePtr);
+ (void)android_atomic_release_cas(6, 7, valuePtr);
+ (void)android_atomic_release_cas(6, 7, valuePtr);
+ (void)android_atomic_release_cas(6, 7, valuePtr);
+ (void)android_atomic_release_cas(6, 7, valuePtr);
+ (void)android_atomic_release_cas(6, 7, valuePtr);
+ (void)android_atomic_release_cas(6, 7, valuePtr);
*/
#endif
}
