[JIT] Regalloc cleanup
Remove vestiges of code intended for linear scan register allocation
in the trace compiler. New plan is to stick with local allocation for
traces and build a new linear scan allocator for the method compiler.
Change-Id: Ic265ab5a7936b144cbe7fa4dc667fa7aba579045
diff --git a/vm/compiler/Frontend.c b/vm/compiler/Frontend.c
index ab04215..c0aa821 100644
--- a/vm/compiler/Frontend.c
+++ b/vm/compiler/Frontend.c
@@ -906,8 +906,8 @@
dvmCompilerDumpCompilationUnit(&cUnit);
}
- /* Allocate Registers */
- dvmCompilerRegAlloc(&cUnit);
+ /* Allocate Registers using simple local allocation scheme */
+ dvmCompilerLocalRegAlloc(&cUnit);
/* Convert MIR to LIR, etc. */
dvmCompilerMIR2LIR(&cUnit);
diff --git a/vm/compiler/Ralloc.c b/vm/compiler/Ralloc.c
index 130ff3c..d772a31 100644
--- a/vm/compiler/Ralloc.c
+++ b/vm/compiler/Ralloc.c
@@ -18,13 +18,6 @@
#include "CompilerInternals.h"
#include "Dataflow.h"
-typedef struct LiveRange {
- int ssaName;
- bool active;
- int first;
- int last;
-} LiveRange;
-
/*
* Quick & dirty - make FP usage sticky. This is strictly a hint - local
* code generation will handle misses. It might be worthwhile to collaborate
@@ -54,45 +47,17 @@
}
}
-/*
- * Determine whether to use simple or aggressive register allocation. In
- * general, loops and full methods will get aggressive.
- */
-static bool simpleTrace(CompilationUnit *cUnit)
-{
- //TODO: flesh out
- return true;
-}
-
-/*
- * Target-independent register allocation. Requires target-dependent
- * helper functions and assumes free list, temp list and spill region.
- * Uses a variant of linear scan and produces a mapping between SSA names
- * and location. Location may be original Dalvik register, hardware
- * register or spill location.
- *
- * Method:
- * 0. Allocate the structure to hold the SSA name life ranges
- * 1. Number each MIR instruction, counting by 2.
- * +0 -> The "read" of the operands
- * +1 -> The definition of the target resource
- * 2. Compute live ranges for all SSA names *not* including the
- * subscript 0 original Dalvik names. Phi functions ignored
- * at this point.
- * 3. Sort the live range list by lowest range start.
- * 4. Process and remove all Phi functions.
- * o If there is no live range collisions among all operands and
- * the target of a Phi function, collapse operands and target
- * and rewrite using target SSA name.
- * o If there is a collision, introduce copies.
- * 5. Allocate in order of increasing live range start.
- */
static const RegLocation freshLoc = {kLocDalvikFrame, 0, 0, INVALID_REG,
INVALID_REG, INVALID_SREG};
-void dvmCompilerRegAlloc(CompilationUnit *cUnit)
+
+/*
+ * Local register allocation for simple traces. Most of the work for
+ * local allocation is done on the fly. Here we do some initialization
+ * and type inference.
+ */
+void dvmCompilerLocalRegAlloc(CompilationUnit *cUnit)
{
int i;
- LiveRange *ranges;
RegLocation *loc;
/* Allocate the location map */
@@ -113,21 +78,9 @@
inferTypes(cUnit, bb);
}
- if (simpleTrace(cUnit)) {
- /*
- * Just rename everything back to subscript 0 names and don't do
- * any explicit promotion. Local allocator will opportunistically
- * promote on the fly.
- */
- for (i=0; i < cUnit->numSSARegs; i++) {
- cUnit->regLocation[i].sRegLow =
+ /* Remap SSA names back to original frame locations. */
+ for (i=0; i < cUnit->numSSARegs; i++) {
+ cUnit->regLocation[i].sRegLow =
DECODE_REG(dvmConvertSSARegToDalvik(cUnit, loc[i].sRegLow));
- }
- } else {
- // Compute live ranges
- ranges = (LiveRange *)dvmCompilerNew(cUnit->numSSARegs * sizeof(*ranges), true);
- for (i=0; i < cUnit->numSSARegs; i++)
- ranges[i].active = false;
- //TODO: phi squash & linear scan promotion
}
}
diff --git a/vm/compiler/codegen/CompilerCodegen.h b/vm/compiler/codegen/CompilerCodegen.h
index d871c3b..70a2bbd 100644
--- a/vm/compiler/codegen/CompilerCodegen.h
+++ b/vm/compiler/codegen/CompilerCodegen.h
@@ -44,7 +44,7 @@
void dvmCompilerPatchInlineCache(void);
/* Implemented in codegen/<target>/Ralloc.c */
-void dvmCompilerRegAlloc(CompilationUnit *cUnit);
+void dvmCompilerLocalRegAlloc(CompilationUnit *cUnit);
/* Implemented in codegen/<target>/Thumb<version>Util.c */
void dvmCompilerInitializeRegAlloc(CompilationUnit *cUnit);
diff --git a/vm/compiler/codegen/RallocUtil.c b/vm/compiler/codegen/RallocUtil.c
index 32977eb..5116243 100644
--- a/vm/compiler/codegen/RallocUtil.c
+++ b/vm/compiler/codegen/RallocUtil.c
@@ -364,10 +364,6 @@
dvmCompilerAbort(cUnit);
}
-/*
- * FIXME - this needs to also check the preserved pool once we start
- * start using preserved registers.
- */
extern RegisterInfo *dvmCompilerIsLive(CompilationUnit *cUnit, int reg)
{
RegisterInfo *p = cUnit->regPool->coreTemps;
diff --git a/vm/compiler/codegen/arm/ArmLIR.h b/vm/compiler/codegen/arm/ArmLIR.h
index 213344c..4f3434d 100644
--- a/vm/compiler/codegen/arm/ArmLIR.h
+++ b/vm/compiler/codegen/arm/ArmLIR.h
@@ -119,10 +119,6 @@
int numFPTemps;
RegisterInfo *FPTemps;
int nextFPTemp;
- int numCoreRegs;
- RegisterInfo *coreRegs;
- int numFPRegs;
- RegisterInfo *FPRegs;
} RegisterPool;
typedef enum ResourceEncodingPos {
diff --git a/vm/compiler/codegen/arm/Thumb/Gen.c b/vm/compiler/codegen/arm/Thumb/Gen.c
index 046a702..07f3f09 100644
--- a/vm/compiler/codegen/arm/Thumb/Gen.c
+++ b/vm/compiler/codegen/arm/Thumb/Gen.c
@@ -120,14 +120,8 @@
dvmCompilerNew(numTemps * sizeof(*pool->coreTemps), true);
pool->numFPTemps = 0;
pool->FPTemps = NULL;
- pool->numCoreRegs = 0;
- pool->coreRegs = NULL;
- pool->numFPRegs = 0;
- pool->FPRegs = NULL;
dvmCompilerInitPool(pool->coreTemps, coreTemps, pool->numCoreTemps);
dvmCompilerInitPool(pool->FPTemps, NULL, 0);
- dvmCompilerInitPool(pool->coreRegs, NULL, 0);
- dvmCompilerInitPool(pool->FPRegs, NULL, 0);
pool->nullCheckedRegs =
dvmCompilerAllocBitVector(cUnit->numSSARegs, false);
}
diff --git a/vm/compiler/codegen/arm/Thumb2/Gen.c b/vm/compiler/codegen/arm/Thumb2/Gen.c
index 8d12d77..0891524 100644
--- a/vm/compiler/codegen/arm/Thumb2/Gen.c
+++ b/vm/compiler/codegen/arm/Thumb2/Gen.c
@@ -97,14 +97,8 @@
pool->numFPTemps = numFPTemps;
pool->FPTemps = (RegisterInfo *)
dvmCompilerNew(numFPTemps * sizeof(*cUnit->regPool->FPTemps), true);
- pool->numCoreRegs = 0;
- pool->coreRegs = NULL;
- pool->numFPRegs = 0;
- pool->FPRegs = NULL;
dvmCompilerInitPool(pool->coreTemps, coreTemps, pool->numCoreTemps);
dvmCompilerInitPool(pool->FPTemps, fpTemps, pool->numFPTemps);
- dvmCompilerInitPool(pool->coreRegs, NULL, 0);
- dvmCompilerInitPool(pool->FPRegs, NULL, 0);
pool->nullCheckedRegs =
dvmCompilerAllocBitVector(cUnit->numSSARegs, false);
}
diff --git a/vm/compiler/codegen/x86/X86LIR.h b/vm/compiler/codegen/x86/X86LIR.h
index 8acf015..19f08e1 100644
--- a/vm/compiler/codegen/x86/X86LIR.h
+++ b/vm/compiler/codegen/x86/X86LIR.h
@@ -80,10 +80,6 @@
int numFPTemps;
RegisterInfo *FPTemps;
int nextFPTemp;
- int numCoreRegs;
- RegisterInfo *coreRegs;
- int numMMRegs;
- RegisterInfo *MMRegs;
} RegisterPool;
typedef enum OpSize {
