Merge "Allocate a contiguous region of virtual memory to be subdivided among the various heaps managed by the garbage collector. Because we cannot tell how far the break has been advanced by morecore, we over allocate virtual memory and grain each heap on a multiple of the maximum heap size. If we could reckon the position of the break, we could allocate just as many pages as required. This requires exporting more state from mspace.c, a refinement I will reserve for a future change list." into dalvik-dev
diff --git a/vm/compiler/codegen/arm/Assemble.c b/vm/compiler/codegen/arm/Assemble.c
index f854b7a..6d901b9 100644
--- a/vm/compiler/codegen/arm/Assemble.c
+++ b/vm/compiler/codegen/arm/Assemble.c
@@ -1864,6 +1864,7 @@
kSVSignedHalfword,
kSVWord,
kSVDoubleword,
+ kSVVariable,
};
/* Load the value of a decoded register from the stack */
@@ -1928,6 +1929,11 @@
break;
case kSVWord:
data = *((u4*) addr);
+ break;
+ default:
+ LOGE("*** ERROR: BAD SIZE IN selfVerificationLoad: %d", size);
+ data = 0;
+ dvmAbort();
}
//LOGD("*** HEAP LOAD: Addr: 0x%x Data: 0x%x Size: %d", addr, data, size);
@@ -2003,6 +2009,10 @@
break;
case kSVWord:
*((u4*) addr) = data;
+ break;
+ default:
+ LOGE("*** ERROR: BAD SIZE IN selfVerificationSave: %d", size);
+ dvmAbort();
}
}
@@ -2066,6 +2076,8 @@
kMemOpStrhRRI5 = 0x10, // strh(1) [10000] imm_5[10..6] rn[5..3] rd[2..0]
kMemOpLdrhRRI5 = 0x11, // ldrh(1) [10001] imm_5[10..6] rn[5..3] rd[2..0]
kMemOpLdrSpRel = 0x13, // ldr(4) [10011] rd[10..8] imm_8[7..0]
+ kMemOpStmia = 0x18, // stmia [11000] rn[10..8] reglist [7..0]
+ kMemOpLdmia = 0x19, // ldmia [11001] rn[10..8] reglist [7..0]
kMemOpStrRRR = 0x28, // str(2) [0101000] rm[8..6] rn[5..3] rd[2..0]
kMemOpStrhRRR = 0x29, // strh(2) [0101001] rm[8..6] rn[5..3] rd[2..0]
kMemOpStrbRRR = 0x2A, // strb(2) [0101010] rm[8..6] rn[5..3] rd[2..0]
@@ -2074,6 +2086,10 @@
kMemOpLdrhRRR = 0x2D, // ldrh(2) [0101101] rm[8..6] rn[5..3] rd[2..0]
kMemOpLdrbRRR = 0x2E, // ldrb(2) [0101110] rm[8..6] rn[5..3] rd[2..0]
kMemOpLdrshRRR = 0x2F, // ldrsh [0101111] rm[8..6] rn[5..3] rd[2..0]
+ kMemOp2Stmia = 0xE88, // stmia [111010001000[ rn[19..16] mask[15..0]
+ kMemOp2Ldmia = 0xE89, // ldmia [111010001001[ rn[19..16] mask[15..0]
+ kMemOp2Stmia2 = 0xE8A, // stmia [111010001010[ rn[19..16] mask[15..0]
+ kMemOp2Ldmia2 = 0xE8B, // ldmia [111010001011[ rn[19..16] mask[15..0]
kMemOp2Vstr = 0xED8, // Used for Vstrs and Vstrd
kMemOp2Vldr = 0xED9, // Used for Vldrs and Vldrd
kMemOp2Vstr2 = 0xEDC, // Used for Vstrs and Vstrd
@@ -2137,12 +2153,15 @@
int rm = insn & 0xF;
int rn = (insn >> 16) & 0xF;
int rt = (insn >> 12) & 0xF;
+ bool wBack = true;
// Update the link register
selfVerificationMemRegStore(sp, old_lr+4, 13);
// Determine whether the mem op is a store or load
switch (opcode12) {
+ case kMemOp2Stmia:
+ case kMemOp2Stmia2:
case kMemOp2Vstr:
case kMemOp2Vstr2:
case kMemOp2StrbRRR:
@@ -2182,6 +2201,12 @@
case kMemOp2Vldr2:
if (opcode4 == kMemOp2Double) size = kSVDoubleword;
break;
+ case kMemOp2Stmia:
+ case kMemOp2Ldmia:
+ case kMemOp2Stmia2:
+ case kMemOp2Ldmia2:
+ size = kSVVariable;
+ break;
}
// Load the value of the address
@@ -2201,8 +2226,7 @@
if (insn & 0x400000) rt |= 0x10;
rt = rt << 1;
} else {
- LOGD("*** ERROR: UNRECOGNIZED VECTOR MEM OP");
- assert(0);
+ LOGE("*** ERROR: UNRECOGNIZED VECTOR MEM OP: %x", opcode4);
dvmAbort();
}
rt += 14;
@@ -2227,15 +2251,35 @@
case kMemOp2LdrshRRI12:
offset = imm12;
break;
+ case kMemOp2Stmia:
+ case kMemOp2Ldmia:
+ wBack = false;
+ case kMemOp2Stmia2:
+ case kMemOp2Ldmia2:
+ offset = 0;
+ break;
default:
- LOGD("*** ERROR: UNRECOGNIZED MEM OP");
- assert(0);
+ LOGE("*** ERROR: UNRECOGNIZED THUMB2 MEM OP: %x", opcode12);
+ offset = 0;
dvmAbort();
}
// Handle the decoded mem op accordingly
if (store) {
- if (size == kSVDoubleword) {
+ if (size == kSVVariable) {
+ LOGD("*** THUMB2 STMIA CURRENTLY UNUSED (AND UNTESTED)");
+ int i;
+ int regList = insn & 0xFFFF;
+ for (i = 0; i < 16; i++) {
+ if (regList & 0x1) {
+ data = selfVerificationMemRegLoad(sp, i);
+ selfVerificationStore(addr, data, kSVWord);
+ addr += 4;
+ }
+ regList = regList >> 1;
+ }
+ if (wBack) selfVerificationMemRegStore(sp, addr, rn);
+ } else if (size == kSVDoubleword) {
double_data = selfVerificationMemRegLoadDouble(sp, rt);
selfVerificationStoreDoubleword(addr+offset, double_data);
} else {
@@ -2243,7 +2287,20 @@
selfVerificationStore(addr+offset, data, size);
}
} else {
- if (size == kSVDoubleword) {
+ if (size == kSVVariable) {
+ LOGD("*** THUMB2 LDMIA CURRENTLY UNUSED (AND UNTESTED)");
+ int i;
+ int regList = insn & 0xFFFF;
+ for (i = 0; i < 16; i++) {
+ if (regList & 0x1) {
+ data = selfVerificationLoad(addr, kSVWord);
+ selfVerificationMemRegStore(sp, data, i);
+ addr += 4;
+ }
+ regList = regList >> 1;
+ }
+ if (wBack) selfVerificationMemRegStore(sp, addr, rn);
+ } else if (size == kSVDoubleword) {
double_data = selfVerificationLoadDoubleword(addr+offset);
selfVerificationMemRegStoreDouble(sp, double_data, rt);
} else {
@@ -2278,6 +2335,7 @@
case kMemOpStrRRI5:
case kMemOpStrbRRI5:
case kMemOpStrhRRI5:
+ case kMemOpStmia:
store = true;
}
@@ -2310,11 +2368,17 @@
case kMemOpLdrhRRI5:
size = kSVHalfword;
break;
+ case kMemOpStmia:
+ case kMemOpLdmia:
+ size = kSVVariable;
+ break;
}
// Load the value of the address
if (opcode5 == kMemOpLdrPcRel)
addr = selfVerificationMemRegLoad(sp, 4);
+ else if (opcode5 == kMemOpStmia || opcode5 == kMemOpLdmia)
+ addr = selfVerificationMemRegLoad(sp, rd);
else
addr = selfVerificationMemRegLoad(sp, rn);
@@ -2340,19 +2404,53 @@
case kMemOpLdrbRRI5:
offset = imm;
break;
+ case kMemOpStmia:
+ case kMemOpLdmia:
+ offset = 0;
+ break;
default:
- LOGD("*** ERROR: UNRECOGNIZED MEM OP");
- assert(0);
+ LOGE("*** ERROR: UNRECOGNIZED THUMB MEM OP: %x", opcode5);
+ offset = 0;
dvmAbort();
}
// Handle the decoded mem op accordingly
if (store) {
- data = selfVerificationMemRegLoad(sp, rt);
- selfVerificationStore(addr+offset, data, size);
+ if (size == kSVVariable) {
+ int i;
+ int regList = insn & 0xFF;
+ for (i = 0; i < 8; i++) {
+ if (regList & 0x1) {
+ data = selfVerificationMemRegLoad(sp, i);
+ selfVerificationStore(addr, data, kSVWord);
+ addr += 4;
+ }
+ regList = regList >> 1;
+ }
+ selfVerificationMemRegStore(sp, addr, rd);
+ } else {
+ data = selfVerificationMemRegLoad(sp, rt);
+ selfVerificationStore(addr+offset, data, size);
+ }
} else {
- data = selfVerificationLoad(addr+offset, size);
- selfVerificationMemRegStore(sp, data, rt);
+ if (size == kSVVariable) {
+ bool wBack = true;
+ int i;
+ int regList = insn & 0xFF;
+ for (i = 0; i < 8; i++) {
+ if (regList & 0x1) {
+ if (i == rd) wBack = false;
+ data = selfVerificationLoad(addr, kSVWord);
+ selfVerificationMemRegStore(sp, data, i);
+ addr += 4;
+ }
+ regList = regList >> 1;
+ }
+ if (wBack) selfVerificationMemRegStore(sp, addr, rd);
+ } else {
+ data = selfVerificationLoad(addr+offset, size);
+ selfVerificationMemRegStore(sp, data, rt);
+ }
}
}
}
diff --git a/vm/compiler/codegen/arm/CodegenCommon.c b/vm/compiler/codegen/arm/CodegenCommon.c
index c3fa8c3..ee4c877 100644
--- a/vm/compiler/codegen/arm/CodegenCommon.c
+++ b/vm/compiler/codegen/arm/CodegenCommon.c
@@ -250,7 +250,7 @@
((mir->next->dalvikInsn.opCode == OP_MOVE_RESULT) ||
(mir->next->dalvikInsn.opCode == OP_MOVE_RESULT_OBJECT))) {
mir->next->dalvikInsn.opCode = OP_NOP;
- return getDestLoc(cUnit, mir->next, 0);
+ return dvmCompilerGetDest(cUnit, mir->next, 0);
} else {
RegLocation res = LOC_DALVIK_RETURN_VAL;
res.fp = fpHint;
@@ -304,7 +304,7 @@
if (mir->next &&
(mir->next->dalvikInsn.opCode == OP_MOVE_RESULT_WIDE)) {
mir->next->dalvikInsn.opCode = OP_NOP;
- return getDestLocWide(cUnit, mir->next, 0, 1);
+ return dvmCompilerGetDestWide(cUnit, mir->next, 0, 1);
} else {
RegLocation res = LOC_DALVIK_RETURN_VAL_WIDE;
res.fp = fpHint;
@@ -330,7 +330,7 @@
ArmLIR *pcrLabel)
{
/* Forget all def info (because we might rollback here. Bug #2367397 */
- resetDefTracking(cUnit);
+ dvmCompilerResetDefTracking(cUnit);
/* Set up the place holder to reconstruct this Dalvik PC */
if (pcrLabel == NULL) {
diff --git a/vm/compiler/codegen/arm/CodegenDriver.c b/vm/compiler/codegen/arm/CodegenDriver.c
index 1bf80cb..5b4e83f 100644
--- a/vm/compiler/codegen/arm/CodegenDriver.c
+++ b/vm/compiler/codegen/arm/CodegenDriver.c
@@ -33,26 +33,26 @@
*/
RegLocation rlSrc;
RegLocation rlDest;
- flushAllRegs(cUnit); /* Send everything to home location */
+ dvmCompilerFlushAllRegs(cUnit); /* Send everything to home location */
if (srcSize == 1) {
- rlSrc = getSrcLoc(cUnit, mir, 0);
+ rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
loadValueDirectFixed(cUnit, rlSrc, r0);
} else {
- rlSrc = getSrcLocWide(cUnit, mir, 0, 1);
+ rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
loadValueDirectWideFixed(cUnit, rlSrc, r0, r1);
}
loadConstant(cUnit, r2, (int)funct);
opReg(cUnit, kOpBlx, r2);
- clobberCallRegs(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
if (tgtSize == 1) {
RegLocation rlResult;
- rlDest = getDestLoc(cUnit, mir, 0);
- rlResult = getReturnLoc(cUnit);
+ rlDest = dvmCompilerGetDest(cUnit, mir, 0);
+ rlResult = dvmCompilerGetReturn(cUnit);
storeValue(cUnit, rlDest, rlResult);
} else {
RegLocation rlResult;
- rlDest = getDestLocWide(cUnit, mir, 0, 1);
- rlResult = getReturnLocWide(cUnit);
+ rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
+ rlResult = dvmCompilerGetReturnWide(cUnit);
storeValueWide(cUnit, rlDest, rlResult);
}
return false;
@@ -101,13 +101,13 @@
default:
return true;
}
- flushAllRegs(cUnit); /* Send everything to home location */
+ dvmCompilerFlushAllRegs(cUnit); /* Send everything to home location */
loadValueDirectFixed(cUnit, rlSrc1, r0);
loadValueDirectFixed(cUnit, rlSrc2, r1);
loadConstant(cUnit, r2, (int)funct);
opReg(cUnit, kOpBlx, r2);
- clobberCallRegs(cUnit);
- rlResult = getReturnLoc(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
+ rlResult = dvmCompilerGetReturn(cUnit);
storeValue(cUnit, rlDest, rlResult);
return false;
}
@@ -154,13 +154,13 @@
default:
return true;
}
- flushAllRegs(cUnit); /* Send everything to home location */
+ dvmCompilerFlushAllRegs(cUnit); /* Send everything to home location */
loadConstant(cUnit, rlr, (int)funct);
loadValueDirectWideFixed(cUnit, rlSrc1, r0, r1);
loadValueDirectWideFixed(cUnit, rlSrc2, r2, r3);
opReg(cUnit, kOpBlx, rlr);
- clobberCallRegs(cUnit);
- rlResult = getReturnLocWide(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
+ rlResult = dvmCompilerGetReturnWide(cUnit);
storeValueWide(cUnit, rlDest, rlResult);
return false;
}
@@ -253,18 +253,18 @@
static void genIGetWide(CompilationUnit *cUnit, MIR *mir, int fieldOffset)
{
DecodedInstruction *dInsn = &mir->dalvikInsn;
- RegLocation rlObj = getSrcLoc(cUnit, mir, 0);
- RegLocation rlDest = getDestLocWide(cUnit, mir, 0, 1);
+ RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 0);
+ RegLocation rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
RegLocation rlResult;
rlObj = loadValue(cUnit, rlObj, kCoreReg);
- int regPtr = allocTemp(cUnit);
+ int regPtr = dvmCompilerAllocTemp(cUnit);
assert(rlDest.wide);
genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset,
NULL);/* null object? */
opRegRegImm(cUnit, kOpAdd, regPtr, rlObj.lowReg, fieldOffset);
- rlResult = evalLoc(cUnit, rlDest, kAnyReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
#if defined(WITH_SELF_VERIFICATION)
cUnit->heapMemOp = true;
#endif
@@ -272,7 +272,7 @@
#if defined(WITH_SELF_VERIFICATION)
cUnit->heapMemOp = false;
#endif
- freeTemp(cUnit, regPtr);
+ dvmCompilerFreeTemp(cUnit, regPtr);
storeValueWide(cUnit, rlDest, rlResult);
}
@@ -280,14 +280,14 @@
static void genIPutWide(CompilationUnit *cUnit, MIR *mir, int fieldOffset)
{
DecodedInstruction *dInsn = &mir->dalvikInsn;
- RegLocation rlSrc = getSrcLocWide(cUnit, mir, 0, 1);
- RegLocation rlObj = getSrcLoc(cUnit, mir, 2);
+ RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
+ RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 2);
rlObj = loadValue(cUnit, rlObj, kCoreReg);
int regPtr;
rlSrc = loadValueWide(cUnit, rlSrc, kAnyReg);
genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset,
NULL);/* null object? */
- regPtr = allocTemp(cUnit);
+ regPtr = dvmCompilerAllocTemp(cUnit);
opRegRegImm(cUnit, kOpAdd, regPtr, rlObj.lowReg, fieldOffset);
#if defined(WITH_SELF_VERIFICATION)
cUnit->heapMemOp = true;
@@ -296,7 +296,7 @@
#if defined(WITH_SELF_VERIFICATION)
cUnit->heapMemOp = false;
#endif
- freeTemp(cUnit, regPtr);
+ dvmCompilerFreeTemp(cUnit, regPtr);
}
/*
@@ -309,10 +309,10 @@
int regPtr;
RegLocation rlResult;
DecodedInstruction *dInsn = &mir->dalvikInsn;
- RegLocation rlObj = getSrcLoc(cUnit, mir, 0);
- RegLocation rlDest = getDestLoc(cUnit, mir, 0);
+ RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 0);
+ RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
rlObj = loadValue(cUnit, rlObj, kCoreReg);
- rlResult = evalLoc(cUnit, rlDest, kAnyReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset,
NULL);/* null object? */
#if defined(WITH_SELF_VERIFICATION)
@@ -334,8 +334,8 @@
int fieldOffset)
{
DecodedInstruction *dInsn = &mir->dalvikInsn;
- RegLocation rlSrc = getSrcLoc(cUnit, mir, 0);
- RegLocation rlObj = getSrcLoc(cUnit, mir, 1);
+ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
+ RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 1);
rlObj = loadValue(cUnit, rlObj, kCoreReg);
rlSrc = loadValue(cUnit, rlSrc, kAnyReg);
int regPtr;
@@ -373,31 +373,31 @@
rlArray.lowReg, mir->offset, NULL);
}
- regPtr = allocTemp(cUnit);
+ regPtr = dvmCompilerAllocTemp(cUnit);
if (!(mir->OptimizationFlags & MIR_IGNORE_RANGE_CHECK)) {
- int regLen = allocTemp(cUnit);
+ int regLen = dvmCompilerAllocTemp(cUnit);
/* Get len */
loadWordDisp(cUnit, rlArray.lowReg, lenOffset, regLen);
/* regPtr -> array data */
opRegRegImm(cUnit, kOpAdd, regPtr, rlArray.lowReg, dataOffset);
genBoundsCheck(cUnit, rlIndex.lowReg, regLen, mir->offset,
pcrLabel);
- freeTemp(cUnit, regLen);
+ dvmCompilerFreeTemp(cUnit, regLen);
} else {
/* regPtr -> array data */
opRegRegImm(cUnit, kOpAdd, regPtr, rlArray.lowReg, dataOffset);
}
if ((size == kLong) || (size == kDouble)) {
if (scale) {
- int rNewIndex = allocTemp(cUnit);
+ int rNewIndex = dvmCompilerAllocTemp(cUnit);
opRegRegImm(cUnit, kOpLsl, rNewIndex, rlIndex.lowReg, scale);
opRegReg(cUnit, kOpAdd, regPtr, rNewIndex);
- freeTemp(cUnit, rNewIndex);
+ dvmCompilerFreeTemp(cUnit, rNewIndex);
} else {
opRegReg(cUnit, kOpAdd, regPtr, rlIndex.lowReg);
}
- rlResult = evalLoc(cUnit, rlDest, kAnyReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
#if defined(WITH_SELF_VERIFICATION)
cUnit->heapMemOp = true;
#endif
@@ -405,10 +405,10 @@
#if defined(WITH_SELF_VERIFICATION)
cUnit->heapMemOp = false;
#endif
- freeTemp(cUnit, regPtr);
+ dvmCompilerFreeTemp(cUnit, regPtr);
storeValueWide(cUnit, rlDest, rlResult);
} else {
- rlResult = evalLoc(cUnit, rlDest, kAnyReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
#if defined(WITH_SELF_VERIFICATION)
cUnit->heapMemOp = true;
#endif
@@ -417,7 +417,7 @@
#if defined(WITH_SELF_VERIFICATION)
cUnit->heapMemOp = false;
#endif
- freeTemp(cUnit, regPtr);
+ dvmCompilerFreeTemp(cUnit, regPtr);
storeValue(cUnit, rlDest, rlResult);
}
}
@@ -437,11 +437,11 @@
rlArray = loadValue(cUnit, rlArray, kCoreReg);
rlIndex = loadValue(cUnit, rlIndex, kCoreReg);
- if (isTemp(cUnit, rlArray.lowReg)) {
- clobberReg(cUnit, rlArray.lowReg);
+ if (dvmCompilerIsTemp(cUnit, rlArray.lowReg)) {
+ dvmCompilerClobber(cUnit, rlArray.lowReg);
regPtr = rlArray.lowReg;
} else {
- regPtr = allocTemp(cUnit);
+ regPtr = dvmCompilerAllocTemp(cUnit);
genRegCopy(cUnit, regPtr, rlArray.lowReg);
}
@@ -454,7 +454,7 @@
}
if (!(mir->OptimizationFlags & MIR_IGNORE_RANGE_CHECK)) {
- int regLen = allocTemp(cUnit);
+ int regLen = dvmCompilerAllocTemp(cUnit);
//NOTE: max live temps(4) here.
/* Get len */
loadWordDisp(cUnit, rlArray.lowReg, lenOffset, regLen);
@@ -462,7 +462,7 @@
opRegImm(cUnit, kOpAdd, regPtr, dataOffset);
genBoundsCheck(cUnit, rlIndex.lowReg, regLen, mir->offset,
pcrLabel);
- freeTemp(cUnit, regLen);
+ dvmCompilerFreeTemp(cUnit, regLen);
} else {
/* regPtr -> array data */
opRegImm(cUnit, kOpAdd, regPtr, dataOffset);
@@ -471,10 +471,10 @@
if ((size == kLong) || (size == kDouble)) {
//TODO: need specific wide routine that can handle fp regs
if (scale) {
- int rNewIndex = allocTemp(cUnit);
+ int rNewIndex = dvmCompilerAllocTemp(cUnit);
opRegRegImm(cUnit, kOpLsl, rNewIndex, rlIndex.lowReg, scale);
opRegReg(cUnit, kOpAdd, regPtr, rNewIndex);
- freeTemp(cUnit, rNewIndex);
+ dvmCompilerFreeTemp(cUnit, rNewIndex);
} else {
opRegReg(cUnit, kOpAdd, regPtr, rlIndex.lowReg);
}
@@ -486,7 +486,7 @@
#if defined(WITH_SELF_VERIFICATION)
cUnit->heapMemOp = false;
#endif
- freeTemp(cUnit, regPtr);
+ dvmCompilerFreeTemp(cUnit, regPtr);
} else {
rlSrc = loadValue(cUnit, rlSrc, kAnyReg);
#if defined(WITH_SELF_VERIFICATION)
@@ -528,7 +528,7 @@
default:
return true;
}
- rlResult = getReturnLocWide(cUnit);
+ rlResult = dvmCompilerGetReturnWide(cUnit);
storeValueWide(cUnit, rlDest, rlResult);
return false;
}
@@ -549,7 +549,7 @@
switch (mir->dalvikInsn.opCode) {
case OP_NOT_LONG:
rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
opRegReg(cUnit, kOpMvn, rlResult.lowReg, rlSrc2.lowReg);
opRegReg(cUnit, kOpMvn, rlResult.highReg, rlSrc2.highReg);
storeValueWide(cUnit, rlDest, rlResult);
@@ -599,9 +599,9 @@
break;
case OP_NEG_LONG: {
//TUNING: can improve this using Thumb2 code
- int tReg = allocTemp(cUnit);
+ int tReg = dvmCompilerAllocTemp(cUnit);
rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
loadConstantValue(cUnit, tReg, 0);
opRegRegReg(cUnit, kOpSub, rlResult.lowReg,
tReg, rlSrc2.lowReg);
@@ -618,16 +618,16 @@
genLong3Addr(cUnit, firstOp, secondOp, rlDest, rlSrc1, rlSrc2);
} else {
// Adjust return regs in to handle case of rem returning r2/r3
- flushAllRegs(cUnit); /* Send everything to home location */
+ dvmCompilerFlushAllRegs(cUnit); /* Send everything to home location */
loadValueDirectWideFixed(cUnit, rlSrc1, r0, r1);
loadConstant(cUnit, rlr, (int) callTgt);
loadValueDirectWideFixed(cUnit, rlSrc2, r2, r3);
opReg(cUnit, kOpBlx, rlr);
- clobberCallRegs(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
if (retReg == r0)
- rlResult = getReturnLocWide(cUnit);
+ rlResult = dvmCompilerGetReturnWide(cUnit);
else
- rlResult = getReturnLocWideAlt(cUnit);
+ rlResult = dvmCompilerGetReturnWideAlt(cUnit);
storeValueWide(cUnit, rlDest, rlResult);
}
return false;
@@ -721,20 +721,20 @@
if (!callOut) {
rlSrc1 = loadValue(cUnit, rlSrc1, kCoreReg);
if (unary) {
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
opRegReg(cUnit, op, rlResult.lowReg,
rlSrc1.lowReg);
} else {
rlSrc2 = loadValue(cUnit, rlSrc2, kCoreReg);
if (shiftOp) {
- int tReg = allocTemp(cUnit);
+ int tReg = dvmCompilerAllocTemp(cUnit);
opRegRegImm(cUnit, kOpAnd, tReg, rlSrc2.lowReg, 31);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
opRegRegReg(cUnit, op, rlResult.lowReg,
rlSrc1.lowReg, tReg);
- freeTemp(cUnit, tReg);
+ dvmCompilerFreeTemp(cUnit, tReg);
} else {
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
opRegRegReg(cUnit, op, rlResult.lowReg,
rlSrc1.lowReg, rlSrc2.lowReg);
}
@@ -742,7 +742,7 @@
storeValue(cUnit, rlDest, rlResult);
} else {
RegLocation rlResult;
- flushAllRegs(cUnit); /* Send everything to home location */
+ dvmCompilerFlushAllRegs(cUnit); /* Send everything to home location */
loadValueDirectFixed(cUnit, rlSrc2, r1);
loadConstant(cUnit, r2, (int) callTgt);
loadValueDirectFixed(cUnit, rlSrc1, r0);
@@ -750,11 +750,11 @@
genNullCheck(cUnit, rlSrc2.sRegLow, r1, mir->offset, NULL);
}
opReg(cUnit, kOpBlx, r2);
- clobberCallRegs(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
if (retReg == r0)
- rlResult = getReturnLoc(cUnit);
+ rlResult = dvmCompilerGetReturn(cUnit);
else
- rlResult = getReturnLocAlt(cUnit);
+ rlResult = dvmCompilerGetReturnAlt(cUnit);
storeValue(cUnit, rlDest, rlResult);
}
return false;
@@ -768,21 +768,21 @@
RegLocation rlSrc2;
/* Deduce sizes of operands */
if (mir->ssaRep->numUses == 2) {
- rlSrc1 = getSrcLoc(cUnit, mir, 0);
- rlSrc2 = getSrcLoc(cUnit, mir, 1);
+ rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 0);
+ rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 1);
} else if (mir->ssaRep->numUses == 3) {
- rlSrc1 = getSrcLocWide(cUnit, mir, 0, 1);
- rlSrc2 = getSrcLoc(cUnit, mir, 2);
+ rlSrc1 = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
+ rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 2);
} else {
- rlSrc1 = getSrcLocWide(cUnit, mir, 0, 1);
- rlSrc2 = getSrcLocWide(cUnit, mir, 2, 3);
+ rlSrc1 = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
+ rlSrc2 = dvmCompilerGetSrcWide(cUnit, mir, 2, 3);
assert(mir->ssaRep->numUses == 4);
}
if (mir->ssaRep->numDefs == 1) {
- rlDest = getDestLoc(cUnit, mir, 0);
+ rlDest = dvmCompilerGetDest(cUnit, mir, 0);
} else {
assert(mir->ssaRep->numDefs == 2);
- rlDest = getDestLocWide(cUnit, mir, 0, 1);
+ rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
}
if ((opCode >= OP_ADD_LONG_2ADDR) && (opCode <= OP_XOR_LONG_2ADDR)) {
@@ -871,10 +871,10 @@
* live values, so we clobber them immediately after loading to prevent
* them from being used as sources for subsequent loads.
*/
- lockAllTemps(cUnit);
+ dvmCompilerLockAllTemps(cUnit);
for (i = 0; i < dInsn->vA; i++) {
regMask |= 1 << i;
- rlArg = getSrcLoc(cUnit, mir, numDone++);
+ rlArg = dvmCompilerGetSrc(cUnit, mir, numDone++);
loadValueDirectFixed(cUnit, rlArg, i);
}
if (regMask) {
@@ -883,7 +883,7 @@
sizeof(StackSaveArea) + (dInsn->vA << 2));
/* generate null check */
if (pcrLabel) {
- *pcrLabel = genNullCheck(cUnit, getSrcSSAName(mir, 0), r0,
+ *pcrLabel = genNullCheck(cUnit, dvmCompilerSSASrc(mir, 0), r0,
mir->offset, NULL);
}
storeMultiple(cUnit, r7, regMask);
@@ -905,7 +905,7 @@
* region - even though some might conceivably have valid copies
* cached in a preserved register.
*/
- lockAllTemps(cUnit);
+ dvmCompilerLockAllTemps(cUnit);
/*
* r4PC : &rFP[vC]
@@ -924,7 +924,7 @@
sizeof(StackSaveArea) + (numArgs << 2));
/* generate null check */
if (pcrLabel) {
- *pcrLabel = genNullCheck(cUnit, getSrcSSAName(mir, 0), r0,
+ *pcrLabel = genNullCheck(cUnit, dvmCompilerSSASrc(mir, 0), r0,
mir->offset, NULL);
}
@@ -993,11 +993,11 @@
* memory by the point, so register usage restrictions no
* longer apply. All temp & preserved registers may be used.
*/
- lockAllTemps(cUnit);
+ dvmCompilerLockAllTemps(cUnit);
ArmLIR *retChainingCell = &labelList[bb->fallThrough->id];
/* r1 = &retChainingCell */
- lockTemp(cUnit, r1);
+ dvmCompilerLockTemp(cUnit, r1);
ArmLIR *addrRetChain = opRegRegImm(cUnit, kOpAdd, r1, rpc, 0);
/* r4PC = dalvikCallsite */
loadConstant(cUnit, r4PC,
@@ -1057,7 +1057,7 @@
* longer apply. Lock temps to prevent them from being
* allocated by utility routines.
*/
- lockAllTemps(cUnit);
+ dvmCompilerLockAllTemps(cUnit);
/* "this" is already left in r0 by genProcessArgs* */
@@ -1163,7 +1163,7 @@
* memory by the point, so register usage restrictions no
* longer apply. All temp & preserved registers may be used.
*/
- lockAllTemps(cUnit);
+ dvmCompilerLockAllTemps(cUnit);
/* r3 now contains this->clazz */
loadWordDisp(cUnit, r0, offsetof(Object, clazz), r3);
@@ -1208,7 +1208,7 @@
static void genPuntToInterp(CompilationUnit *cUnit, unsigned int offset)
{
/* r0 = dalvik pc */
- flushAllRegs(cUnit);
+ dvmCompilerFlushAllRegs(cUnit);
loadConstant(cUnit, r0, (int) (cUnit->method->insns + offset));
loadWordDisp(cUnit, r0, offsetof(Object, clazz), r3);
loadWordDisp(cUnit, rGLUE, offsetof(InterpState,
@@ -1227,7 +1227,7 @@
kInstrCanThrow;
//Ugly, but necessary. Flush all Dalvik regs so Interp can find them
- flushAllRegs(cUnit);
+ dvmCompilerFlushAllRegs(cUnit);
if ((mir->next == NULL) || (flags & flagsToCheck)) {
genPuntToInterp(cUnit, mir->offset);
@@ -1258,8 +1258,8 @@
{
bool isEnter = (mir->dalvikInsn.opCode == OP_MONITOR_ENTER);
genExportPC(cUnit, mir);
- flushAllRegs(cUnit); /* Send everything to home location */
- RegLocation rlSrc = getSrcLoc(cUnit, mir, 0);
+ dvmCompilerFlushAllRegs(cUnit); /* Send everything to home location */
+ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
loadValueDirectFixed(cUnit, rlSrc, r1);
loadWordDisp(cUnit, rGLUE, offsetof(InterpState, self), r0);
genNullCheck(cUnit, rlSrc.sRegLow, r1, mir->offset, NULL);
@@ -1276,7 +1276,7 @@
loadConstant(cUnit, r2, (int)dvmUnlockObject);
/* Do the call */
opReg(cUnit, kOpBlx, r2);
- clobberCallRegs(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
}
}
@@ -1324,15 +1324,15 @@
RegLocation rlDest;
RegLocation rlResult;
if (mir->ssaRep->numDefs == 2) {
- rlDest = getDestLocWide(cUnit, mir, 0, 1);
+ rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
} else {
- rlDest = getDestLoc(cUnit, mir, 0);
+ rlDest = dvmCompilerGetDest(cUnit, mir, 0);
}
switch (mir->dalvikInsn.opCode) {
case OP_CONST:
case OP_CONST_4: {
- rlResult = evalLoc(cUnit, rlDest, kAnyReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
loadConstantValue(cUnit, rlResult.lowReg, mir->dalvikInsn.vB);
storeValue(cUnit, rlDest, rlResult);
break;
@@ -1340,7 +1340,7 @@
case OP_CONST_WIDE_32: {
//TUNING: single routine to load constant pair for support doubles
//TUNING: load 0/-1 separately to avoid load dependency
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
loadConstantValue(cUnit, rlResult.lowReg, mir->dalvikInsn.vB);
opRegRegImm(cUnit, kOpAsr, rlResult.highReg,
rlResult.lowReg, 31);
@@ -1358,11 +1358,11 @@
RegLocation rlDest;
RegLocation rlResult;
if (mir->ssaRep->numDefs == 2) {
- rlDest = getDestLocWide(cUnit, mir, 0, 1);
+ rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
} else {
- rlDest = getDestLoc(cUnit, mir, 0);
+ rlDest = dvmCompilerGetDest(cUnit, mir, 0);
}
- rlResult = evalLoc(cUnit, rlDest, kAnyReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
switch (mir->dalvikInsn.opCode) {
case OP_CONST_HIGH16: {
@@ -1401,8 +1401,8 @@
void *strPtr = (void*)
(cUnit->method->clazz->pDvmDex->pResStrings[mir->dalvikInsn.vB]);
assert(strPtr != NULL);
- rlDest = getDestLoc(cUnit, mir, 0);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlDest = dvmCompilerGetDest(cUnit, mir, 0);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
loadConstantValue(cUnit, rlResult.lowReg, (int) strPtr );
storeValue(cUnit, rlDest, rlResult);
break;
@@ -1411,8 +1411,8 @@
void *classPtr = (void*)
(cUnit->method->clazz->pDvmDex->pResClasses[mir->dalvikInsn.vB]);
assert(classPtr != NULL);
- rlDest = getDestLoc(cUnit, mir, 0);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlDest = dvmCompilerGetDest(cUnit, mir, 0);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
loadConstantValue(cUnit, rlResult.lowReg, (int) classPtr );
storeValue(cUnit, rlDest, rlResult);
break;
@@ -1424,12 +1424,12 @@
case OP_SGET_SHORT:
case OP_SGET: {
int valOffset = offsetof(StaticField, value);
- int tReg = allocTemp(cUnit);
+ int tReg = dvmCompilerAllocTemp(cUnit);
void *fieldPtr = (void*)
(cUnit->method->clazz->pDvmDex->pResFields[mir->dalvikInsn.vB]);
assert(fieldPtr != NULL);
- rlDest = getDestLoc(cUnit, mir, 0);
- rlResult = evalLoc(cUnit, rlDest, kAnyReg, true);
+ rlDest = dvmCompilerGetDest(cUnit, mir, 0);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
loadConstant(cUnit, tReg, (int) fieldPtr + valOffset);
#if defined(WITH_SELF_VERIFICATION)
cUnit->heapMemOp = true;
@@ -1445,10 +1445,10 @@
int valOffset = offsetof(StaticField, value);
void *fieldPtr = (void*)
(cUnit->method->clazz->pDvmDex->pResFields[mir->dalvikInsn.vB]);
- int tReg = allocTemp(cUnit);
+ int tReg = dvmCompilerAllocTemp(cUnit);
assert(fieldPtr != NULL);
- rlDest = getDestLocWide(cUnit, mir, 0, 1);
- rlResult = evalLoc(cUnit, rlDest, kAnyReg, true);
+ rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
loadConstant(cUnit, tReg, (int) fieldPtr + valOffset);
#if defined(WITH_SELF_VERIFICATION)
cUnit->heapMemOp = true;
@@ -1467,12 +1467,12 @@
case OP_SPUT_SHORT:
case OP_SPUT: {
int valOffset = offsetof(StaticField, value);
- int tReg = allocTemp(cUnit);
+ int tReg = dvmCompilerAllocTemp(cUnit);
void *fieldPtr = (void*)
(cUnit->method->clazz->pDvmDex->pResFields[mir->dalvikInsn.vB]);
assert(fieldPtr != NULL);
- rlSrc = getSrcLoc(cUnit, mir, 0);
+ rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
rlSrc = loadValue(cUnit, rlSrc, kAnyReg);
loadConstant(cUnit, tReg, (int) fieldPtr + valOffset);
#if defined(WITH_SELF_VERIFICATION)
@@ -1485,13 +1485,13 @@
break;
}
case OP_SPUT_WIDE: {
- int tReg = allocTemp(cUnit);
+ int tReg = dvmCompilerAllocTemp(cUnit);
int valOffset = offsetof(StaticField, value);
void *fieldPtr = (void*)
(cUnit->method->clazz->pDvmDex->pResFields[mir->dalvikInsn.vB]);
assert(fieldPtr != NULL);
- rlSrc = getSrcLocWide(cUnit, mir, 0, 1);
+ rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
rlSrc = loadValueWide(cUnit, rlSrc, kAnyReg);
loadConstant(cUnit, tReg, (int) fieldPtr + valOffset);
#if defined(WITH_SELF_VERIFICATION)
@@ -1517,13 +1517,13 @@
* with. However, Alloc might throw, so we need to genExportPC()
*/
assert((classPtr->accessFlags & (ACC_INTERFACE|ACC_ABSTRACT)) == 0);
- flushAllRegs(cUnit); /* Send everything to home location */
+ dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
genExportPC(cUnit, mir);
loadConstant(cUnit, r2, (int)dvmAllocObject);
loadConstant(cUnit, r0, (int) classPtr);
loadConstant(cUnit, r1, ALLOC_DONT_TRACK);
opReg(cUnit, kOpBlx, r2);
- clobberCallRegs(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
/* generate a branch over if allocation is successful */
opRegImm(cUnit, kOpCmp, r0, 0); /* NULL? */
ArmLIR *branchOver = opCondBranch(cUnit, kArmCondNe);
@@ -1538,8 +1538,8 @@
ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
target->defMask = ENCODE_ALL;
branchOver->generic.target = (LIR *) target;
- rlDest = getDestLoc(cUnit, mir, 0);
- rlResult = getReturnLoc(cUnit);
+ rlDest = dvmCompilerGetDest(cUnit, mir, 0);
+ rlResult = dvmCompilerGetReturn(cUnit);
storeValue(cUnit, rlDest, rlResult);
break;
}
@@ -1563,9 +1563,9 @@
genInterpSingleStep(cUnit, mir);
return false;
}
- flushAllRegs(cUnit); /* Send everything to home location */
+ dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
loadConstant(cUnit, r1, (int) classPtr );
- rlSrc = getSrcLoc(cUnit, mir, 0);
+ rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
opRegImm(cUnit, kOpCmp, rlSrc.lowReg, 0); /* Null? */
ArmLIR *branch1 = opCondBranch(cUnit, kArmCondEq);
@@ -1581,7 +1581,7 @@
opRegReg(cUnit, kOpCmp, r0, r1);
ArmLIR *branch2 = opCondBranch(cUnit, kArmCondEq);
opReg(cUnit, kOpBlx, r2);
- clobberCallRegs(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
/*
* If null, check cast failed - punt to the interpreter. Because
* interpreter will be the one throwing, we don't need to
@@ -1609,10 +1609,10 @@
case OP_MOVE_EXCEPTION: {
int offset = offsetof(InterpState, self);
int exOffset = offsetof(Thread, exception);
- int selfReg = allocTemp(cUnit);
- int resetReg = allocTemp(cUnit);
- RegLocation rlDest = getDestLoc(cUnit, mir, 0);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ int selfReg = dvmCompilerAllocTemp(cUnit);
+ int resetReg = dvmCompilerAllocTemp(cUnit);
+ RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
loadWordDisp(cUnit, rGLUE, offset, selfReg);
loadConstant(cUnit, resetReg, 0);
loadWordDisp(cUnit, selfReg, exOffset, rlResult.lowReg);
@@ -1622,21 +1622,21 @@
}
case OP_MOVE_RESULT:
case OP_MOVE_RESULT_OBJECT: {
- RegLocation rlDest = getDestLoc(cUnit, mir, 0);
+ RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
RegLocation rlSrc = LOC_DALVIK_RETURN_VAL;
rlSrc.fp = rlDest.fp;
storeValue(cUnit, rlDest, rlSrc);
break;
}
case OP_MOVE_RESULT_WIDE: {
- RegLocation rlDest = getDestLocWide(cUnit, mir, 0, 1);
+ RegLocation rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
RegLocation rlSrc = LOC_DALVIK_RETURN_VAL_WIDE;
rlSrc.fp = rlDest.fp;
storeValueWide(cUnit, rlDest, rlSrc);
break;
}
case OP_RETURN_WIDE: {
- RegLocation rlSrc = getSrcLocWide(cUnit, mir, 0, 1);
+ RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
RegLocation rlDest = LOC_DALVIK_RETURN_VAL_WIDE;
rlDest.fp = rlSrc.fp;
storeValueWide(cUnit, rlDest, rlSrc);
@@ -1645,7 +1645,7 @@
}
case OP_RETURN:
case OP_RETURN_OBJECT: {
- RegLocation rlSrc = getSrcLoc(cUnit, mir, 0);
+ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
RegLocation rlDest = LOC_DALVIK_RETURN_VAL;
rlDest.fp = rlSrc.fp;
storeValue(cUnit, rlDest, rlSrc);
@@ -1682,13 +1682,13 @@
}
if (mir->ssaRep->numUses == 2)
- rlSrc = getSrcLocWide(cUnit, mir, 0, 1);
+ rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
else
- rlSrc = getSrcLoc(cUnit, mir, 0);
+ rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
if (mir->ssaRep->numDefs == 2)
- rlDest = getDestLocWide(cUnit, mir, 0, 1);
+ rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
else
- rlDest = getDestLoc(cUnit, mir, 0);
+ rlDest = dvmCompilerGetDest(cUnit, mir, 0);
switch (opCode) {
case OP_DOUBLE_TO_INT:
@@ -1716,8 +1716,8 @@
storeValueWide(cUnit, rlDest, rlSrc);
break;
case OP_INT_TO_LONG:
- rlSrc = updateLoc(cUnit, rlSrc);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlSrc = dvmCompilerUpdateLoc(cUnit, rlSrc);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
//TUNING: shouldn't loadValueDirect already check for phys reg?
if (rlSrc.location == kLocPhysReg) {
genRegCopy(cUnit, rlResult.lowReg, rlSrc.lowReg);
@@ -1729,8 +1729,8 @@
storeValueWide(cUnit, rlDest, rlResult);
break;
case OP_LONG_TO_INT:
- rlSrc = updateLocWide(cUnit, rlSrc);
- rlSrc = wideToNarrowLoc(cUnit, rlSrc);
+ rlSrc = dvmCompilerUpdateLocWide(cUnit, rlSrc);
+ rlSrc = dvmCompilerWideToNarrow(cUnit, rlSrc);
// Intentional fallthrough
case OP_MOVE:
case OP_MOVE_OBJECT:
@@ -1738,19 +1738,19 @@
break;
case OP_INT_TO_BYTE:
rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
opRegReg(cUnit, kOp2Byte, rlResult.lowReg, rlSrc.lowReg);
storeValue(cUnit, rlDest, rlResult);
break;
case OP_INT_TO_SHORT:
rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
opRegReg(cUnit, kOp2Short, rlResult.lowReg, rlSrc.lowReg);
storeValue(cUnit, rlDest, rlResult);
break;
case OP_INT_TO_CHAR:
rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
opRegReg(cUnit, kOp2Char, rlResult.lowReg, rlSrc.lowReg);
storeValue(cUnit, rlDest, rlResult);
break;
@@ -1759,7 +1759,7 @@
rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
genNullCheck(cUnit, rlSrc.sRegLow, rlSrc.lowReg,
mir->offset, NULL);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
loadWordDisp(cUnit, rlSrc.lowReg, lenOffset,
rlResult.lowReg);
storeValue(cUnit, rlDest, rlResult);
@@ -1778,15 +1778,15 @@
RegLocation rlResult;
int BBBB = mir->dalvikInsn.vB;
if (dalvikOpCode == OP_CONST_WIDE_16) {
- rlDest = getDestLocWide(cUnit, mir, 0, 1);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
loadConstantValue(cUnit, rlResult.lowReg, BBBB);
//TUNING: do high separately to avoid load dependency
opRegRegImm(cUnit, kOpAsr, rlResult.highReg, rlResult.lowReg, 31);
storeValueWide(cUnit, rlDest, rlResult);
} else if (dalvikOpCode == OP_CONST_16) {
- rlDest = getDestLoc(cUnit, mir, 0);
- rlResult = evalLoc(cUnit, rlDest, kAnyReg, true);
+ rlDest = dvmCompilerGetDest(cUnit, mir, 0);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
loadConstantValue(cUnit, rlResult.lowReg, BBBB);
storeValue(cUnit, rlDest, rlResult);
} else
@@ -1800,7 +1800,7 @@
{
OpCode dalvikOpCode = mir->dalvikInsn.opCode;
ArmConditionCode cond;
- RegLocation rlSrc = getSrcLoc(cUnit, mir, 0);
+ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
opRegImm(cUnit, kOpCmp, rlSrc.lowReg, 0);
@@ -1838,8 +1838,8 @@
static bool handleFmt22b_Fmt22s(CompilationUnit *cUnit, MIR *mir)
{
OpCode dalvikOpCode = mir->dalvikInsn.opCode;
- RegLocation rlSrc = getSrcLoc(cUnit, mir, 0);
- RegLocation rlDest = getDestLoc(cUnit, mir, 0);
+ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
+ RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
RegLocation rlResult;
int lit = mir->dalvikInsn.vC;
OpKind op = 0; /* Make gcc happy */
@@ -1855,9 +1855,9 @@
int tReg;
//TUNING: add support for use of Arm rsub op
rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
- tReg = allocTemp(cUnit);
+ tReg = dvmCompilerAllocTemp(cUnit);
loadConstant(cUnit, tReg, lit);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
opRegRegReg(cUnit, kOpSub, rlResult.lowReg,
tReg, rlSrc.lowReg);
storeValue(cUnit, rlDest, rlResult);
@@ -1910,9 +1910,9 @@
genInterpSingleStep(cUnit, mir);
return false;
}
- flushAllRegs(cUnit); /* Send everything to home location */
+ dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
loadValueDirectFixed(cUnit, rlSrc, r0);
- clobberReg(cUnit, r0);
+ dvmCompilerClobber(cUnit, r0);
if ((dalvikOpCode == OP_DIV_INT_LIT8) ||
(dalvikOpCode == OP_DIV_INT_LIT16)) {
loadConstant(cUnit, r2, (int)__aeabi_idiv);
@@ -1923,11 +1923,11 @@
}
loadConstant(cUnit, r1, lit);
opReg(cUnit, kOpBlx, r2);
- clobberCallRegs(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
if (isDiv)
- rlResult = getReturnLoc(cUnit);
+ rlResult = dvmCompilerGetReturn(cUnit);
else
- rlResult = getReturnLocAlt(cUnit);
+ rlResult = dvmCompilerGetReturnAlt(cUnit);
storeValue(cUnit, rlDest, rlResult);
return false;
break;
@@ -1935,7 +1935,7 @@
return true;
}
rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
// Avoid shifts by literal 0 - no support in Thumb. Change to copy
if (shiftOp && (lit == 0)) {
genRegCopy(cUnit, rlResult.lowReg, rlSrc.lowReg);
@@ -1964,13 +1964,13 @@
switch (dalvikOpCode) {
case OP_NEW_ARRAY: {
// Generates a call - use explicit registers
- RegLocation rlSrc = getSrcLoc(cUnit, mir, 0);
- RegLocation rlDest = getDestLoc(cUnit, mir, 0);
+ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
+ RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
RegLocation rlResult;
void *classPtr = (void*)
(cUnit->method->clazz->pDvmDex->pResClasses[mir->dalvikInsn.vC]);
assert(classPtr != NULL);
- flushAllRegs(cUnit); /* Send everything to home location */
+ dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
genExportPC(cUnit, mir);
loadValueDirectFixed(cUnit, rlSrc, r1); /* Len */
loadConstant(cUnit, r0, (int) classPtr );
@@ -1983,7 +1983,7 @@
genRegImmCheck(cUnit, kArmCondMi, r1, 0, mir->offset, NULL);
loadConstant(cUnit, r2, ALLOC_DONT_TRACK);
opReg(cUnit, kOpBlx, r3);
- clobberCallRegs(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
/* generate a branch over if allocation is successful */
opRegImm(cUnit, kOpCmp, r0, 0); /* NULL? */
ArmLIR *branchOver = opCondBranch(cUnit, kArmCondNe);
@@ -1998,14 +1998,14 @@
ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
target->defMask = ENCODE_ALL;
branchOver->generic.target = (LIR *) target;
- rlResult = getReturnLoc(cUnit);
+ rlResult = dvmCompilerGetReturn(cUnit);
storeValue(cUnit, rlDest, rlResult);
break;
}
case OP_INSTANCE_OF: {
// May generate a call - use explicit registers
- RegLocation rlSrc = getSrcLoc(cUnit, mir, 0);
- RegLocation rlDest = getDestLoc(cUnit, mir, 0);
+ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
+ RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
RegLocation rlResult;
ClassObject *classPtr =
(cUnit->method->clazz->pDvmDex->pResClasses[mir->dalvikInsn.vC]);
@@ -2022,7 +2022,7 @@
genInterpSingleStep(cUnit, mir);
break;
}
- flushAllRegs(cUnit); /* Send everything to home location */
+ dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
loadValueDirectFixed(cUnit, rlSrc, r0); /* Ref */
loadConstant(cUnit, r2, (int) classPtr );
//TUNING: compare to 0 primative to allow use of CB[N]Z
@@ -2039,11 +2039,11 @@
genRegCopy(cUnit, r0, r1);
genRegCopy(cUnit, r1, r2);
opReg(cUnit, kOpBlx, r3);
- clobberCallRegs(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
/* branch target here */
ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
target->defMask = ENCODE_ALL;
- rlResult = getReturnLoc(cUnit);
+ rlResult = dvmCompilerGetReturn(cUnit);
storeValue(cUnit, rlDest, rlResult);
branch1->generic.target = (LIR *)target;
branch2->generic.target = (LIR *)target;
@@ -2121,8 +2121,8 @@
{
OpCode dalvikOpCode = mir->dalvikInsn.opCode;
ArmConditionCode cond;
- RegLocation rlSrc1 = getSrcLoc(cUnit, mir, 0);
- RegLocation rlSrc2 = getSrcLoc(cUnit, mir, 1);
+ RegLocation rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 0);
+ RegLocation rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 1);
rlSrc1 = loadValue(cUnit, rlSrc1, kCoreReg);
rlSrc2 = loadValue(cUnit, rlSrc2, kCoreReg);
@@ -2167,14 +2167,14 @@
case OP_MOVE_OBJECT_16:
case OP_MOVE_FROM16:
case OP_MOVE_OBJECT_FROM16: {
- storeValue(cUnit, getDestLoc(cUnit, mir, 0),
- getSrcLoc(cUnit, mir, 0));
+ storeValue(cUnit, dvmCompilerGetDest(cUnit, mir, 0),
+ dvmCompilerGetSrc(cUnit, mir, 0));
break;
}
case OP_MOVE_WIDE_16:
case OP_MOVE_WIDE_FROM16: {
- storeValueWide(cUnit, getDestLocWide(cUnit, mir, 0, 1),
- getSrcLocWide(cUnit, mir, 0, 1));
+ storeValueWide(cUnit, dvmCompilerGetDestWide(cUnit, mir, 0, 1),
+ dvmCompilerGetSrcWide(cUnit, mir, 0, 1));
break;
}
default:
@@ -2197,30 +2197,30 @@
/* APUTs have 3 sources and no targets */
if (mir->ssaRep->numDefs == 0) {
if (mir->ssaRep->numUses == 3) {
- rlDest = getSrcLoc(cUnit, mir, 0);
- rlSrc1 = getSrcLoc(cUnit, mir, 1);
- rlSrc2 = getSrcLoc(cUnit, mir, 2);
+ rlDest = dvmCompilerGetSrc(cUnit, mir, 0);
+ rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 1);
+ rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 2);
} else {
assert(mir->ssaRep->numUses == 4);
- rlDest = getSrcLocWide(cUnit, mir, 0, 1);
- rlSrc1 = getSrcLoc(cUnit, mir, 2);
- rlSrc2 = getSrcLoc(cUnit, mir, 3);
+ rlDest = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
+ rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 2);
+ rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 3);
}
} else {
/* Two sources and 1 dest. Deduce the operand sizes */
if (mir->ssaRep->numUses == 4) {
- rlSrc1 = getSrcLocWide(cUnit, mir, 0, 1);
- rlSrc2 = getSrcLocWide(cUnit, mir, 2, 3);
+ rlSrc1 = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
+ rlSrc2 = dvmCompilerGetSrcWide(cUnit, mir, 2, 3);
} else {
assert(mir->ssaRep->numUses == 2);
- rlSrc1 = getSrcLoc(cUnit, mir, 0);
- rlSrc2 = getSrcLoc(cUnit, mir, 1);
+ rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 0);
+ rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 1);
}
if (mir->ssaRep->numDefs == 2) {
- rlDest = getDestLocWide(cUnit, mir, 0, 1);
+ rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
} else {
assert(mir->ssaRep->numDefs == 1);
- rlDest = getDestLoc(cUnit, mir, 0);
+ rlDest = dvmCompilerGetDest(cUnit, mir, 0);
}
}
@@ -2408,16 +2408,16 @@
OpCode dalvikOpCode = mir->dalvikInsn.opCode;
switch (dalvikOpCode) {
case OP_FILL_ARRAY_DATA: {
- RegLocation rlSrc = getSrcLoc(cUnit, mir, 0);
+ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
// Making a call - use explicit registers
- flushAllRegs(cUnit); /* Send everything to home location */
+ dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
genExportPC(cUnit, mir);
loadValueDirectFixed(cUnit, rlSrc, r0);
loadConstant(cUnit, r2, (int)dvmInterpHandleFillArrayData);
loadConstant(cUnit, r1,
(int) (cUnit->method->insns + mir->offset + mir->dalvikInsn.vB));
opReg(cUnit, kOpBlx, r2);
- clobberCallRegs(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
/* generate a branch over if successful */
opRegImm(cUnit, kOpCmp, r0, 0); /* NULL? */
ArmLIR *branchOver = opCondBranch(cUnit, kArmCondNe);
@@ -2436,10 +2436,10 @@
*/
case OP_PACKED_SWITCH:
case OP_SPARSE_SWITCH: {
- RegLocation rlSrc = getSrcLoc(cUnit, mir, 0);
- flushAllRegs(cUnit); /* Send everything to home location */
+ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
+ dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
loadValueDirectFixed(cUnit, rlSrc, r1);
- lockAllTemps(cUnit);
+ dvmCompilerLockAllTemps(cUnit);
const u2 *switchData =
cUnit->method->insns + mir->offset + mir->dalvikInsn.vB;
u2 size = switchData[1];
@@ -2455,7 +2455,7 @@
/* r2 <- pc of the instruction following the blx */
opRegReg(cUnit, kOpMov, r2, rpc);
opReg(cUnit, kOpBlx, r4PC);
- clobberCallRegs(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
/* pc <- computed goto target */
opRegReg(cUnit, kOpMov, rpc, r0);
break;
@@ -2632,7 +2632,7 @@
int methodIndex = dInsn->vB;
/* Ensure that nothing is both live and dirty */
- flushAllRegs(cUnit);
+ dvmCompilerFlushAllRegs(cUnit);
if (mir->dalvikInsn.opCode == OP_INVOKE_INTERFACE)
genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel);
@@ -2830,8 +2830,8 @@
return false;
#else
ArmLIR *rollback;
- RegLocation rlThis = getSrcLoc(cUnit, mir, 0);
- RegLocation rlComp = getSrcLoc(cUnit, mir, 1);
+ RegLocation rlThis = dvmCompilerGetSrc(cUnit, mir, 0);
+ RegLocation rlComp = dvmCompilerGetSrc(cUnit, mir, 1);
loadValueDirectFixed(cUnit, rlThis, r0);
loadValueDirectFixed(cUnit, rlComp, r1);
@@ -2844,7 +2844,8 @@
* expansion.
*/
genDispatchToHandler(cUnit, TEMPLATE_STRING_COMPARETO);
- storeValue(cUnit, inlinedTarget(cUnit, mir, false), getReturnLoc(cUnit));
+ storeValue(cUnit, inlinedTarget(cUnit, mir, false),
+ dvmCompilerGetReturn(cUnit));
return true;
#endif
}
@@ -2854,13 +2855,13 @@
#if defined(USE_GLOBAL_STRING_DEFS)
return false;
#else
- RegLocation rlThis = getSrcLoc(cUnit, mir, 0);
- RegLocation rlChar = getSrcLoc(cUnit, mir, 1);
+ RegLocation rlThis = dvmCompilerGetSrc(cUnit, mir, 0);
+ RegLocation rlChar = dvmCompilerGetSrc(cUnit, mir, 1);
loadValueDirectFixed(cUnit, rlThis, r0);
loadValueDirectFixed(cUnit, rlChar, r1);
if (!singleI) {
- RegLocation rlStart = getSrcLoc(cUnit, mir, 2);
+ RegLocation rlStart = dvmCompilerGetSrc(cUnit, mir, 2);
loadValueDirectFixed(cUnit, rlStart, r2);
} else {
loadConstant(cUnit, r2, 0);
@@ -2868,7 +2869,8 @@
/* Test objects for NULL */
genNullCheck(cUnit, rlThis.sRegLow, r0, mir->offset, NULL);
genDispatchToHandler(cUnit, TEMPLATE_STRING_INDEXOF);
- storeValue(cUnit, inlinedTarget(cUnit, mir, false), getReturnLoc(cUnit));
+ storeValue(cUnit, inlinedTarget(cUnit, mir, false),
+ dvmCompilerGetReturn(cUnit));
return true;
#endif
}
@@ -2942,16 +2944,16 @@
default:
dvmAbort();
}
- flushAllRegs(cUnit); /* Send everything to home location */
- clobberCallRegs(cUnit);
- clobberReg(cUnit, r4PC);
- clobberReg(cUnit, r7);
+ dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
+ dvmCompilerColbberCallRegs(cUnit);
+ dvmCompilerClobber(cUnit, r4PC);
+ dvmCompilerClobber(cUnit, r7);
opRegRegImm(cUnit, kOpAdd, r4PC, rGLUE, offset);
opImm(cUnit, kOpPush, (1<<r4PC) | (1<<r7));
loadConstant(cUnit, r4PC, (int)inLineTable[operation].func);
genExportPC(cUnit, mir);
for (i=0; i < dInsn->vA; i++) {
- loadValueDirect(cUnit, getSrcLoc(cUnit, mir, i), i);
+ loadValueDirect(cUnit, dvmCompilerGetSrc(cUnit, mir, i), i);
}
opReg(cUnit, kOpBlx, r4PC);
opRegImm(cUnit, kOpAdd, r13, 8);
@@ -2974,8 +2976,8 @@
static bool handleFmt51l(CompilationUnit *cUnit, MIR *mir)
{
//TUNING: We're using core regs here - not optimal when target is a double
- RegLocation rlDest = getDestLocWide(cUnit, mir, 0, 1);
- RegLocation rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ RegLocation rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
+ RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
loadConstantValue(cUnit, rlResult.lowReg,
mir->dalvikInsn.vB_wide & 0xFFFFFFFFUL);
loadConstantValue(cUnit, rlResult.highReg,
@@ -3112,7 +3114,7 @@
(ArmLIR *) cUnit->loopAnalysis->branchToPCR);
/* regLength <- len(arrayRef) */
- regLength = allocTemp(cUnit);
+ regLength = dvmCompilerAllocTemp(cUnit);
loadWordDisp(cUnit, rlArray.lowReg, lenOffset, regLength);
int delta = maxC;
@@ -3125,10 +3127,10 @@
}
if (delta) {
- int tReg = allocTemp(cUnit);
+ int tReg = dvmCompilerAllocTemp(cUnit);
opRegRegImm(cUnit, kOpAdd, tReg, rlIdxEnd.lowReg, delta);
rlIdxEnd.lowReg = tReg;
- freeTemp(cUnit, tReg);
+ dvmCompilerFreeTemp(cUnit, tReg);
}
/* Punt if "regIdxEnd < len(Array)" is false */
genRegRegCheck(cUnit, kArmCondGe, rlIdxEnd.lowReg, regLength, 0,
@@ -3147,7 +3149,7 @@
{
DecodedInstruction *dInsn = &mir->dalvikInsn;
const int lenOffset = offsetof(ArrayObject, length);
- const int regLength = allocTemp(cUnit);
+ const int regLength = dvmCompilerAllocTemp(cUnit);
const int maxC = dInsn->arg[0];
const int minC = dInsn->arg[1];
RegLocation rlArray = cUnit->regLocation[mir->dalvikInsn.vA];
@@ -3163,10 +3165,10 @@
loadWordDisp(cUnit, rlArray.lowReg, lenOffset, regLength);
if (maxC) {
- int tReg = allocTemp(cUnit);
+ int tReg = dvmCompilerAllocTemp(cUnit);
opRegRegImm(cUnit, kOpAdd, tReg, rlIdxInit.lowReg, maxC);
rlIdxInit.lowReg = tReg;
- freeTemp(cUnit, tReg);
+ dvmCompilerFreeTemp(cUnit, tReg);
}
/* Punt if "regIdxInit < len(Array)" is false */
@@ -3345,9 +3347,9 @@
} else if (blockList[i]->blockType == kDalvikByteCode) {
labelList[i].opCode = kArmPseudoNormalBlockLabel;
/* Reset the register state */
- resetRegPool(cUnit);
- clobberAllRegs(cUnit);
- resetNullCheckTracker(cUnit);
+ dvmCompilerResetRegPool(cUnit);
+ dvmCompilerClobberAllRegs(cUnit);
+ dvmCompilerResetNullCheck(cUnit);
} else {
switch (blockList[i]->blockType) {
case kChainingCellNormal:
@@ -3418,13 +3420,13 @@
for (mir = blockList[i]->firstMIRInsn; mir; mir = mir->next) {
- resetRegPool(cUnit);
+ dvmCompilerResetRegPool(cUnit);
if (gDvmJit.disableOpt & (1 << kTrackLiveTemps)) {
- clobberAllRegs(cUnit);
+ dvmCompilerClobberAllRegs(cUnit);
}
if (gDvmJit.disableOpt & (1 << kSuppressLoads)) {
- resetDefTracking(cUnit);
+ dvmCompilerResetDefTracking(cUnit);
}
if (mir->dalvikInsn.opCode >= kMirOpFirst) {
diff --git a/vm/compiler/codegen/arm/CodegenFactory.c b/vm/compiler/codegen/arm/CodegenFactory.c
index e5a56cc..594cfd5 100644
--- a/vm/compiler/codegen/arm/CodegenFactory.c
+++ b/vm/compiler/codegen/arm/CodegenFactory.c
@@ -47,14 +47,14 @@
static void loadValueDirect(CompilationUnit *cUnit, RegLocation rlSrc,
int reg1)
{
- rlSrc = updateLoc(cUnit, rlSrc); /* Is our value hiding in a live temp? */
+ rlSrc = dvmCompilerUpdateLoc(cUnit, rlSrc);
if (rlSrc.location == kLocPhysReg) {
genRegCopy(cUnit, reg1, rlSrc.lowReg);
} else if (rlSrc.location == kLocRetval) {
loadWordDisp(cUnit, rGLUE, offsetof(InterpState, retval), reg1);
} else {
assert(rlSrc.location == kLocDalvikFrame);
- loadWordDisp(cUnit, rFP, sReg2vReg(cUnit, rlSrc.sRegLow) << 2,
+ loadWordDisp(cUnit, rFP, dvmCompilerS2VReg(cUnit, rlSrc.sRegLow) << 2,
reg1);
}
}
@@ -67,8 +67,8 @@
static void loadValueDirectFixed(CompilationUnit *cUnit, RegLocation rlSrc,
int reg1)
{
- clobberReg(cUnit, reg1);
- markRegInUse(cUnit, reg1);
+ dvmCompilerClobber(cUnit, reg1);
+ dvmcompilerMarkInUse(cUnit, reg1);
loadValueDirect(cUnit, rlSrc, reg1);
}
@@ -80,7 +80,7 @@
static void loadValueDirectWide(CompilationUnit *cUnit, RegLocation rlSrc,
int regLo, int regHi)
{
- rlSrc = updateLocWide(cUnit, rlSrc);
+ rlSrc = dvmCompilerUpdateLocWide(cUnit, rlSrc);
if (rlSrc.location == kLocPhysReg) {
genRegCopyWide(cUnit, regLo, regHi, rlSrc.lowReg, rlSrc.highReg);
} else if (rlSrc.location == kLocRetval) {
@@ -89,7 +89,7 @@
} else {
assert(rlSrc.location == kLocDalvikFrame);
loadBaseDispWide(cUnit, NULL, rFP,
- sReg2vReg(cUnit, rlSrc.sRegLow) << 2,
+ dvmCompilerS2VReg(cUnit, rlSrc.sRegLow) << 2,
regLo, regHi, INVALID_SREG);
}
}
@@ -102,10 +102,10 @@
static void loadValueDirectWideFixed(CompilationUnit *cUnit, RegLocation rlSrc,
int regLo, int regHi)
{
- clobberReg(cUnit, regLo);
- clobberReg(cUnit, regHi);
- markRegInUse(cUnit, regLo);
- markRegInUse(cUnit, regHi);
+ dvmCompilerClobber(cUnit, regLo);
+ dvmCompilerClobber(cUnit, regHi);
+ dvmcompilerMarkInUse(cUnit, regLo);
+ dvmcompilerMarkInUse(cUnit, regHi);
loadValueDirectWide(cUnit, rlSrc, regLo, regHi);
}
@@ -113,15 +113,15 @@
RegisterClass opKind)
{
RegisterInfo *pReg;
- rlSrc = evalLoc(cUnit, rlSrc, opKind, false);
+ rlSrc = dvmCompilerEvalLoc(cUnit, rlSrc, opKind, false);
if (rlSrc.location == kLocDalvikFrame) {
loadValueDirect(cUnit, rlSrc, rlSrc.lowReg);
rlSrc.location = kLocPhysReg;
- markRegLive(cUnit, rlSrc.lowReg, rlSrc.sRegLow);
+ dvmCompilerMarkLive(cUnit, rlSrc.lowReg, rlSrc.sRegLow);
} else if (rlSrc.location == kLocRetval) {
loadWordDisp(cUnit, rGLUE, offsetof(InterpState, retval), rlSrc.lowReg);
rlSrc.location = kLocPhysReg;
- clobberReg(cUnit, rlSrc.lowReg);
+ dvmCompilerClobber(cUnit, rlSrc.lowReg);
}
return rlSrc;
}
@@ -134,43 +134,44 @@
LIR *defEnd;
assert(!rlDest.wide);
assert(!rlSrc.wide);
- killNullCheckedLocation(cUnit, rlDest);
- rlSrc = updateLoc(cUnit, rlSrc);
- rlDest = updateLoc(cUnit, rlDest);
+ dvmCompilerKillNullCheckedLoc(cUnit, rlDest);
+ rlSrc = dvmCompilerUpdateLoc(cUnit, rlSrc);
+ rlDest = dvmCompilerUpdateLoc(cUnit, rlDest);
if (rlSrc.location == kLocPhysReg) {
- if (isLive(cUnit, rlSrc.lowReg) || (rlDest.location == kLocPhysReg)) {
+ if (dvmCompilerIsLive(cUnit, rlSrc.lowReg) ||
+ (rlDest.location == kLocPhysReg)) {
// Src is live or Dest has assigned reg.
- rlDest = evalLoc(cUnit, rlDest, kAnyReg, false);
+ rlDest = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, false);
genRegCopy(cUnit, rlDest.lowReg, rlSrc.lowReg);
} else {
// Just re-assign the registers. Dest gets Src's regs
rlDest.lowReg = rlSrc.lowReg;
- clobberReg(cUnit, rlSrc.lowReg);
+ dvmCompilerClobber(cUnit, rlSrc.lowReg);
}
} else {
// Load Src either into promoted Dest or temps allocated for Dest
- rlDest = evalLoc(cUnit, rlDest, kAnyReg, false);
+ rlDest = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, false);
loadValueDirect(cUnit, rlSrc, rlDest.lowReg);
}
// Dest is now live and dirty (until/if we flush it to home location)
- markRegLive(cUnit, rlDest.lowReg, rlDest.sRegLow);
- markRegDirty(cUnit, rlDest.lowReg);
+ dvmCompilerMarkLive(cUnit, rlDest.lowReg, rlDest.sRegLow);
+ dvmCompilerMarkDirty(cUnit, rlDest.lowReg);
if (rlDest.location == kLocRetval) {
storeBaseDisp(cUnit, rGLUE, offsetof(InterpState, retval),
rlDest.lowReg, kWord);
- clobberReg(cUnit, rlDest.lowReg);
+ dvmCompilerClobber(cUnit, rlDest.lowReg);
} else {
- resetDefLoc(cUnit, rlDest);
- if (liveOut(cUnit, rlDest.sRegLow)) {
+ dvmCompilerResetDefLoc(cUnit, rlDest);
+ if (dvmCompilerLiveOut(cUnit, rlDest.sRegLow)) {
defStart = (LIR *)cUnit->lastLIRInsn;
- int vReg = sReg2vReg(cUnit, rlDest.sRegLow);
+ int vReg = dvmCompilerS2VReg(cUnit, rlDest.sRegLow);
storeBaseDisp(cUnit, rFP, vReg << 2, rlDest.lowReg, kWord);
- markRegClean(cUnit, rlDest.lowReg);
+ dvmCompilerMarkClean(cUnit, rlDest.lowReg);
defEnd = (LIR *)cUnit->lastLIRInsn;
- markDef(cUnit, rlDest, defStart, defEnd);
+ dvmCompilerMarkDef(cUnit, rlDest, defStart, defEnd);
}
}
}
@@ -181,18 +182,19 @@
RegisterInfo *pRegLo;
RegisterInfo *pRegHi;
assert(rlSrc.wide);
- rlSrc = evalLoc(cUnit, rlSrc, opKind, false);
+ rlSrc = dvmCompilerEvalLoc(cUnit, rlSrc, opKind, false);
if (rlSrc.location == kLocDalvikFrame) {
loadValueDirectWide(cUnit, rlSrc, rlSrc.lowReg, rlSrc.highReg);
rlSrc.location = kLocPhysReg;
- markRegLive(cUnit, rlSrc.lowReg, rlSrc.sRegLow);
- markRegLive(cUnit, rlSrc.highReg, hiSReg(rlSrc.sRegLow));
+ dvmCompilerMarkLive(cUnit, rlSrc.lowReg, rlSrc.sRegLow);
+ dvmCompilerMarkLive(cUnit, rlSrc.highReg,
+ dvmCompilerSRegHi(rlSrc.sRegLow));
} else if (rlSrc.location == kLocRetval) {
loadBaseDispWide(cUnit, NULL, rGLUE, offsetof(InterpState, retval),
rlSrc.lowReg, rlSrc.highReg, INVALID_SREG);
rlSrc.location = kLocPhysReg;
- clobberReg(cUnit, rlSrc.lowReg);
- clobberReg(cUnit, rlSrc.highReg);
+ dvmCompilerClobber(cUnit, rlSrc.lowReg);
+ dvmCompilerClobber(cUnit, rlSrc.highReg);
}
return rlSrc;
}
@@ -208,54 +210,57 @@
assert(FPREG(rlSrc.lowReg)==FPREG(rlSrc.highReg));
assert(rlDest.wide);
assert(rlSrc.wide);
- killNullCheckedLocation(cUnit, rlDest);
+ dvmCompilerKillNullCheckedLoc(cUnit, rlDest);
if (rlSrc.location == kLocPhysReg) {
- if (isLive(cUnit, rlSrc.lowReg) || isLive(cUnit, rlSrc.highReg) ||
+ if (dvmCompilerIsLive(cUnit, rlSrc.lowReg) ||
+ dvmCompilerIsLive(cUnit, rlSrc.highReg) ||
(rlDest.location == kLocPhysReg)) {
// Src is live or Dest has assigned reg.
- rlDest = evalLoc(cUnit, rlDest, kAnyReg, false);
+ rlDest = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, false);
genRegCopyWide(cUnit, rlDest.lowReg, rlDest.highReg,
rlSrc.lowReg, rlSrc.highReg);
} else {
// Just re-assign the registers. Dest gets Src's regs
rlDest.lowReg = rlSrc.lowReg;
rlDest.highReg = rlSrc.highReg;
- clobberReg(cUnit, rlSrc.lowReg);
- clobberReg(cUnit, rlSrc.highReg);
+ dvmCompilerClobber(cUnit, rlSrc.lowReg);
+ dvmCompilerClobber(cUnit, rlSrc.highReg);
}
} else {
// Load Src either into promoted Dest or temps allocated for Dest
- rlDest = evalLoc(cUnit, rlDest, kAnyReg, false);
+ rlDest = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, false);
loadValueDirectWide(cUnit, rlSrc, rlDest.lowReg,
rlDest.highReg);
}
// Dest is now live and dirty (until/if we flush it to home location)
- markRegLive(cUnit, rlDest.lowReg, rlDest.sRegLow);
- markRegLive(cUnit, rlDest.highReg, hiSReg(rlDest.sRegLow));
- markRegDirty(cUnit, rlDest.lowReg);
- markRegDirty(cUnit, rlDest.highReg);
- markRegPair(cUnit, rlDest.lowReg, rlDest.highReg);
+ dvmCompilerMarkLive(cUnit, rlDest.lowReg, rlDest.sRegLow);
+ dvmCompilerMarkLive(cUnit, rlDest.highReg,
+ dvmCompilerSRegHi(rlDest.sRegLow));
+ dvmCompilerMarkDirty(cUnit, rlDest.lowReg);
+ dvmCompilerMarkDirty(cUnit, rlDest.highReg);
+ dvmCompilerMarkPair(cUnit, rlDest.lowReg, rlDest.highReg);
if (rlDest.location == kLocRetval) {
storeBaseDispWide(cUnit, rGLUE, offsetof(InterpState, retval),
rlDest.lowReg, rlDest.highReg);
- clobberReg(cUnit, rlDest.lowReg);
- clobberReg(cUnit, rlDest.highReg);
+ dvmCompilerClobber(cUnit, rlDest.lowReg);
+ dvmCompilerClobber(cUnit, rlDest.highReg);
} else {
- resetDefLocWide(cUnit, rlDest);
- if (liveOut(cUnit, rlDest.sRegLow) ||
- liveOut(cUnit, hiSReg(rlDest.sRegLow))) {
+ dvmCompilerResetDefLocWide(cUnit, rlDest);
+ if (dvmCompilerLiveOut(cUnit, rlDest.sRegLow) ||
+ dvmCompilerLiveOut(cUnit, dvmCompilerSRegHi(rlDest.sRegLow))) {
defStart = (LIR *)cUnit->lastLIRInsn;
- int vReg = sReg2vReg(cUnit, rlDest.sRegLow);
- assert((vReg+1) == sReg2vReg(cUnit, hiSReg(rlDest.sRegLow)));
+ int vReg = dvmCompilerS2VReg(cUnit, rlDest.sRegLow);
+ assert((vReg+1) == dvmCompilerS2VReg(cUnit,
+ dvmCompilerSRegHi(rlDest.sRegLow)));
storeBaseDispWide(cUnit, rFP, vReg << 2, rlDest.lowReg,
rlDest.highReg);
- markRegClean(cUnit, rlDest.lowReg);
- markRegClean(cUnit, rlDest.highReg);
+ dvmCompilerMarkClean(cUnit, rlDest.lowReg);
+ dvmCompilerMarkClean(cUnit, rlDest.highReg);
defEnd = (LIR *)cUnit->lastLIRInsn;
- markDefWide(cUnit, rlDest, defStart, defEnd);
+ dvmCompilerMarkDefWide(cUnit, rlDest, defStart, defEnd);
}
}
}
@@ -325,7 +330,7 @@
* we fake BLX_1 is a two operand instruction and the absolute target
* address is stored in operand[1].
*/
- clobberHandlerRegs(cUnit);
+ dvmCompilerClobberHandlerRegs(cUnit);
newLIR2(cUnit, kThumbBlx1,
(int) gDvmJit.codeCache + templateEntryOffsets[opCode],
(int) gDvmJit.codeCache + templateEntryOffsets[opCode]);
diff --git a/vm/compiler/codegen/arm/FP/Thumb2VFP.c b/vm/compiler/codegen/arm/FP/Thumb2VFP.c
index c0d5d6b..6c70862 100644
--- a/vm/compiler/codegen/arm/FP/Thumb2VFP.c
+++ b/vm/compiler/codegen/arm/FP/Thumb2VFP.c
@@ -55,7 +55,7 @@
}
rlSrc1 = loadValue(cUnit, rlSrc1, kFPReg);
rlSrc2 = loadValue(cUnit, rlSrc2, kFPReg);
- rlResult = evalLoc(cUnit, rlDest, kFPReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kFPReg, true);
newLIR3(cUnit, op, rlResult.lowReg, rlSrc1.lowReg, rlSrc2.lowReg);
storeValue(cUnit, rlDest, rlResult);
return false;
@@ -99,7 +99,7 @@
assert(rlSrc1.wide);
rlSrc2 = loadValueWide(cUnit, rlSrc2, kFPReg);
assert(rlSrc2.wide);
- rlResult = evalLoc(cUnit, rlDest, kFPReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kFPReg, true);
assert(rlDest.wide);
assert(rlResult.wide);
newLIR3(cUnit, op, S2D(rlResult.lowReg, rlResult.highReg),
@@ -160,22 +160,22 @@
return true;
}
if (longSrc) {
- rlSrc = getSrcLocWide(cUnit, mir, 0, 1);
+ rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
rlSrc = loadValueWide(cUnit, rlSrc, kFPReg);
srcReg = S2D(rlSrc.lowReg, rlSrc.highReg);
} else {
- rlSrc = getSrcLoc(cUnit, mir, 0);
+ rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
rlSrc = loadValue(cUnit, rlSrc, kFPReg);
srcReg = rlSrc.lowReg;
}
if (longDest) {
- rlDest = getDestLocWide(cUnit, mir, 0, 1);
- rlResult = evalLoc(cUnit, rlDest, kFPReg, true);
+ rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kFPReg, true);
newLIR2(cUnit, op, S2D(rlResult.lowReg, rlResult.highReg), srcReg);
storeValueWide(cUnit, rlDest, rlResult);
} else {
- rlDest = getDestLoc(cUnit, mir, 0);
- rlResult = evalLoc(cUnit, rlDest, kFPReg, true);
+ rlDest = dvmCompilerGetDest(cUnit, mir, 0);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kFPReg, true);
newLIR2(cUnit, op, rlResult.lowReg, srcReg);
storeValue(cUnit, rlDest, rlResult);
}
@@ -186,17 +186,17 @@
{
ArmLIR *branch;
DecodedInstruction *dInsn = &mir->dalvikInsn;
- RegLocation rlSrc = getSrcLocWide(cUnit, mir, 0, 1);
+ RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
RegLocation rlDest = inlinedTargetWide(cUnit, mir, true);
rlSrc = loadValueWide(cUnit, rlSrc, kFPReg);
- RegLocation rlResult = evalLoc(cUnit, rlDest, kFPReg, true);
+ RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kFPReg, true);
newLIR2(cUnit, kThumb2Vsqrtd, S2D(rlResult.lowReg, rlResult.highReg),
S2D(rlSrc.lowReg, rlSrc.highReg));
newLIR2(cUnit, kThumb2Vcmpd, S2D(rlResult.lowReg, rlResult.highReg),
S2D(rlResult.lowReg, rlResult.highReg));
newLIR0(cUnit, kThumb2Fmstat);
branch = newLIR2(cUnit, kThumbBCond, 0, kArmCondEq);
- clobberCallRegs(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
loadConstant(cUnit, r2, (int)sqrt);
newLIR3(cUnit, kThumb2Fmrrd, r0, r1, S2D(rlSrc.lowReg, rlSrc.highReg));
newLIR1(cUnit, kThumbBlxR, r2);
@@ -240,16 +240,16 @@
if (isDouble) {
rlSrc1 = loadValueWide(cUnit, rlSrc1, kFPReg);
rlSrc2 = loadValueWide(cUnit, rlSrc2, kFPReg);
- clobberSReg(cUnit, rlDest.sRegLow);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ dvmCompilerClobberSReg(cUnit, rlDest.sRegLow);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
loadConstant(cUnit, rlResult.lowReg, defaultResult);
newLIR2(cUnit, kThumb2Vcmpd, S2D(rlSrc1.lowReg, r1Src2.highReg),
S2D(rlSrc2.lowReg, rlSrc2.highReg));
} else {
rlSrc1 = loadValue(cUnit, rlSrc1, kFPReg);
rlSrc2 = loadValue(cUnit, rlSrc2, kFPReg);
- clobberSReg(cUnit, rlDest.sRegLow);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ dvmCompilerClobberSReg(cUnit, rlDest.sRegLow);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
loadConstant(cUnit, rlResult.lowReg, defaultResult);
newLIR2(cUnit, kThumb2Vcmps, rlSrc1.lowReg, rlSrc2.lowReg);
}
diff --git a/vm/compiler/codegen/arm/FP/ThumbVFP.c b/vm/compiler/codegen/arm/FP/ThumbVFP.c
index 099f3c6..adf5fa1 100644
--- a/vm/compiler/codegen/arm/FP/ThumbVFP.c
+++ b/vm/compiler/codegen/arm/FP/ThumbVFP.c
@@ -28,7 +28,8 @@
static void loadValueAddress(CompilationUnit *cUnit, RegLocation rlSrc,
int rDest)
{
- rlSrc = rlSrc.wide ? updateLocWide(cUnit, rlSrc) : updateLoc(cUnit, rlSrc);
+ rlSrc = rlSrc.wide ? dvmCompilerUpdateLocWide(cUnit, rlSrc) :
+ dvmCompilerUpdateLoc(cUnit, rlSrc);
if (rlSrc.location == kLocPhysReg) {
if (rlSrc.wide) {
dvmCompilerFlushRegWideForV5TEVFP(cUnit, rlSrc.lowReg,
@@ -38,12 +39,12 @@
}
}
opRegRegImm(cUnit, kOpAdd, rDest, rFP,
- sReg2vReg(cUnit, rlSrc.sRegLow) << 2);
+ dvmCompilerS2VReg(cUnit, rlSrc.sRegLow) << 2);
}
static bool genInlineSqrt(CompilationUnit *cUnit, MIR *mir)
{
- RegLocation rlSrc = getSrcLocWide(cUnit, mir, 0, 1);
+ RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
RegLocation rlResult = LOC_C_RETURN_WIDE;
RegLocation rlDest = LOC_DALVIK_RETURN_VAL_WIDE;
loadValueAddress(cUnit, rlSrc, r2);
@@ -96,14 +97,14 @@
return true;
}
loadValueAddress(cUnit, rlDest, r0);
- clobberReg(cUnit, r0);
+ dvmCompilerClobber(cUnit, r0);
loadValueAddress(cUnit, rlSrc1, r1);
- clobberReg(cUnit, r1);
+ dvmCompilerClobber(cUnit, r1);
loadValueAddress(cUnit, rlSrc2, r2);
genDispatchToHandler(cUnit, opCode);
- rlDest = updateLoc(cUnit, rlDest);
+ rlDest = dvmCompilerUpdateLoc(cUnit, rlDest);
if (rlDest.location == kLocPhysReg) {
- clobberReg(cUnit, rlDest.lowReg);
+ dvmCompilerClobber(cUnit, rlDest.lowReg);
}
return false;
}
@@ -141,15 +142,15 @@
return true;
}
loadValueAddress(cUnit, rlDest, r0);
- clobberReg(cUnit, r0);
+ dvmCompilerClobber(cUnit, r0);
loadValueAddress(cUnit, rlSrc1, r1);
- clobberReg(cUnit, r1);
+ dvmCompilerClobber(cUnit, r1);
loadValueAddress(cUnit, rlSrc2, r2);
genDispatchToHandler(cUnit, opCode);
- rlDest = updateLocWide(cUnit, rlDest);
+ rlDest = dvmCompilerUpdateLocWide(cUnit, rlDest);
if (rlDest.location == kLocPhysReg) {
- clobberReg(cUnit, rlDest.lowReg);
- clobberReg(cUnit, rlDest.highReg);
+ dvmCompilerClobber(cUnit, rlDest.lowReg);
+ dvmCompilerClobber(cUnit, rlDest.highReg);
}
return false;
}
@@ -203,35 +204,35 @@
}
if (longSrc) {
- rlSrc = getSrcLocWide(cUnit, mir, 0, 1);
+ rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
} else {
- rlSrc = getSrcLoc(cUnit, mir, 0);
+ rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
}
if (longDest) {
- rlDest = getDestLocWide(cUnit, mir, 0, 1);
+ rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
} else {
- rlDest = getDestLoc(cUnit, mir, 0);
+ rlDest = dvmCompilerGetDest(cUnit, mir, 0);
}
loadValueAddress(cUnit, rlDest, r0);
- clobberReg(cUnit, r0);
+ dvmCompilerClobber(cUnit, r0);
loadValueAddress(cUnit, rlSrc, r1);
genDispatchToHandler(cUnit, template);
if (rlDest.wide) {
- rlDest = updateLocWide(cUnit, rlDest);
- clobberReg(cUnit, rlDest.highReg);
+ rlDest = dvmCompilerUpdateLocWide(cUnit, rlDest);
+ dvmCompilerClobber(cUnit, rlDest.highReg);
} else {
- rlDest = updateLoc(cUnit, rlDest);
+ rlDest = dvmCompilerUpdateLoc(cUnit, rlDest);
}
- clobberReg(cUnit, rlDest.lowReg);
+ dvmCompilerClobber(cUnit, rlDest.lowReg);
return false;
}
static bool genCmpFP(CompilationUnit *cUnit, MIR *mir, RegLocation rlDest,
- RegLocation rlSrc1, RegLocation rlSrc2)
+ RegLocation rlSrc1, RegLocation rlSrc2)
{
TemplateOpCode template;
- RegLocation rlResult = getReturnLoc(cUnit);
+ RegLocation rlResult = dvmCompilerGetReturn(cUnit);
bool wide = true;
switch(mir->dalvikInsn.opCode) {
@@ -253,7 +254,7 @@
return true;
}
loadValueAddress(cUnit, rlSrc1, r0);
- clobberReg(cUnit, r0);
+ dvmCompilerClobber(cUnit, r0);
loadValueAddress(cUnit, rlSrc2, r1);
genDispatchToHandler(cUnit, template);
storeValue(cUnit, rlDest, rlResult);
diff --git a/vm/compiler/codegen/arm/Ralloc.h b/vm/compiler/codegen/arm/Ralloc.h
index dce1939..987638a 100644
--- a/vm/compiler/codegen/arm/Ralloc.h
+++ b/vm/compiler/codegen/arm/Ralloc.h
@@ -27,19 +27,14 @@
#include "compiler/Dataflow.h"
#include "compiler/codegen/arm/ArmLIR.h"
-/*
- * The following are register allocation routines exposed to the code generator
- * FIXME - dvmCompiler prefixes are not added yet
- */
-
-static inline int sReg2vReg(CompilationUnit *cUnit, int sReg)
+static inline int dvmCompilerS2VReg(CompilationUnit *cUnit, int sReg)
{
assert(sReg != INVALID_SREG);
return DECODE_REG(dvmConvertSSARegToDalvik(cUnit, sReg));
}
/* Reset the tracker to unknown state */
-static inline void resetNullCheckTracker(CompilationUnit *cUnit)
+static inline void dvmCompilerResetNullCheck(CompilationUnit *cUnit)
{
dvmClearAllBits(cUnit->regPool->nullCheckedRegs);
}
@@ -54,138 +49,144 @@
* identified by the dataflow pass what it's new name is.
*/
-static inline int hiSReg(int lowSreg) {
+static inline int dvmCompilerSRegHi(int lowSreg) {
return (lowSreg == INVALID_SREG) ? INVALID_SREG : lowSreg + 1;
}
-static inline bool liveOut(CompilationUnit *cUnit, int sReg)
+static inline bool dvmCompilerLiveOut(CompilationUnit *cUnit, int sReg)
{
//TODO: fully implement
return true;
}
-static inline int getSrcSSAName(MIR *mir, int num)
+static inline int dvmCompilerSSASrc(MIR *mir, int num)
{
assert(mir->ssaRep->numUses > num);
return mir->ssaRep->uses[num];
}
-extern RegLocation evalLoc(CompilationUnit *cUnit, RegLocation loc,
- int regClass, bool update);
+extern RegLocation dvmCompilerEvalLoc(CompilationUnit *cUnit, RegLocation loc,
+ int regClass, bool update);
/* Mark a temp register as dead. Does not affect allocation state. */
-extern void clobberReg(CompilationUnit *cUnit, int reg);
+extern void dvmCompilerClobber(CompilationUnit *cUnit, int reg);
-extern RegLocation updateLoc(CompilationUnit *cUnit, RegLocation loc);
+extern RegLocation dvmCompilerUpdateLoc(CompilationUnit *cUnit,
+ RegLocation loc);
/* see comments for updateLoc */
-extern RegLocation updateLocWide(CompilationUnit *cUnit, RegLocation loc);
+extern RegLocation dvmCompilerUpdateLocWide(CompilationUnit *cUnit,
+ RegLocation loc);
/* Clobber all of the temps that might be used by a handler. */
-extern void clobberHandlerRegs(CompilationUnit *cUnit);
+extern void dvmCompilerClobberHandlerRegs(CompilationUnit *cUnit);
-extern void markRegLive(CompilationUnit *cUnit, int reg, int sReg);
+extern void dvmCompilerMarkLive(CompilationUnit *cUnit, int reg, int sReg);
-extern void markRegDirty(CompilationUnit *cUnit, int reg);
+extern void dvmCompilerMarkDirty(CompilationUnit *cUnit, int reg);
-extern void markRegPair(CompilationUnit *cUnit, int lowReg, int highReg);
+extern void dvmCompilerMarkPair(CompilationUnit *cUnit, int lowReg,
+ int highReg);
-extern void markRegClean(CompilationUnit *cUnit, int reg);
+extern void dvmCompilerMarkClean(CompilationUnit *cUnit, int reg);
-extern void resetDef(CompilationUnit *cUnit, int reg);
+extern void dvmCompilerResetDef(CompilationUnit *cUnit, int reg);
-extern void resetDefLoc(CompilationUnit *cUnit, RegLocation rl);
+extern void dvmCompilerResetDefLoc(CompilationUnit *cUnit, RegLocation rl);
/* Set up temp & preserved register pools specialized by target */
-extern void initPool(RegisterInfo *regs, int *regNums, int num);
+extern void dvmCompilerInitPool(RegisterInfo *regs, int *regNums, int num);
/*
* Mark the beginning and end LIR of a def sequence. Note that
* on entry start points to the LIR prior to the beginning of the
* sequence.
*/
-extern void markDef(CompilationUnit *cUnit, RegLocation rl,
- LIR *start, LIR *finish);
+extern void dvmCompilerMarkDef(CompilationUnit *cUnit, RegLocation rl,
+ LIR *start, LIR *finish);
/*
* Mark the beginning and end LIR of a def sequence. Note that
* on entry start points to the LIR prior to the beginning of the
* sequence.
*/
-extern void markDefWide(CompilationUnit *cUnit, RegLocation rl,
- LIR *start, LIR *finish);
+extern void dvmCompilerMarkDefWide(CompilationUnit *cUnit, RegLocation rl,
+ LIR *start, LIR *finish);
-extern RegLocation getSrcLocWide(CompilationUnit *cUnit, MIR *mir,
+extern RegLocation dvmCompilerGetSrcWide(CompilationUnit *cUnit, MIR *mir,
int low, int high);
-extern RegLocation getDestLocWide(CompilationUnit *cUnit, MIR *mir,
- int low, int high);
+extern RegLocation dvmCompilerGetDestWide(CompilationUnit *cUnit, MIR *mir,
+ int low, int high);
// Get the LocRecord associated with an SSA name use.
-extern RegLocation getSrcLoc(CompilationUnit *cUnit, MIR *mir, int num);
+extern RegLocation dvmCompilerGetSrc(CompilationUnit *cUnit, MIR *mir, int num);
// Get the LocRecord associated with an SSA name def.
-extern RegLocation getDestLoc(CompilationUnit *cUnit, MIR *mir, int num);
+extern RegLocation dvmCompilerGetDest(CompilationUnit *cUnit, MIR *mir,
+ int num);
-extern RegLocation getReturnLocWide(CompilationUnit *cUnit);
+extern RegLocation dvmCompilerGetReturnWide(CompilationUnit *cUnit);
/* Clobber all regs that might be used by an external C call */
-extern void clobberCallRegs(CompilationUnit *cUnit);
+extern void dvmCompilerColbberCallRegs(CompilationUnit *cUnit);
-extern RegisterInfo *isTemp(CompilationUnit *cUnit, int reg);
+extern RegisterInfo *dvmCompilerIsTemp(CompilationUnit *cUnit, int reg);
-extern void markRegInUse(CompilationUnit *cUnit, int reg);
+extern void dvmcompilerMarkInUse(CompilationUnit *cUnit, int reg);
-extern int allocTemp(CompilationUnit *cUnit);
+extern int dvmCompilerAllocTemp(CompilationUnit *cUnit);
-extern int allocTempFloat(CompilationUnit *cUnit);
+extern int dvmCompilerAllocTempFloat(CompilationUnit *cUnit);
//REDO: too many assumptions.
-extern int allocTempDouble(CompilationUnit *cUnit);
+extern int dvmCompilerAllocTempDouble(CompilationUnit *cUnit);
-extern void freeTemp(CompilationUnit *cUnit, int reg);
+extern void dvmCompilerFreeTemp(CompilationUnit *cUnit, int reg);
-extern void resetDefLocWide(CompilationUnit *cUnit, RegLocation rl);
+extern void dvmCompilerResetDefLocWide(CompilationUnit *cUnit, RegLocation rl);
-extern void resetDefTracking(CompilationUnit *cUnit);
+extern void dvmCompilerResetDefTracking(CompilationUnit *cUnit);
/* Kill the corresponding bit in the null-checked register list */
-extern void killNullCheckedLocation(CompilationUnit *cUnit, RegLocation loc);
+extern void dvmCompilerKillNullCheckedLoc(CompilationUnit *cUnit,
+ RegLocation loc);
//FIXME - this needs to also check the preserved pool.
-extern RegisterInfo *isLive(CompilationUnit *cUnit, int reg);
+extern RegisterInfo *dvmCompilerIsLive(CompilationUnit *cUnit, int reg);
/* To be used when explicitly managing register use */
-extern void lockAllTemps(CompilationUnit *cUnit);
+extern void dvmCompilerLockAllTemps(CompilationUnit *cUnit);
-extern void flushAllRegs(CompilationUnit *cUnit);
+extern void dvmCompilerFlushAllRegs(CompilationUnit *cUnit);
-extern RegLocation getReturnLocWideAlt(CompilationUnit *cUnit);
+extern RegLocation dvmCompilerGetReturnWideAlt(CompilationUnit *cUnit);
-extern RegLocation getReturnLoc(CompilationUnit *cUnit);
+extern RegLocation dvmCompilerGetReturn(CompilationUnit *cUnit);
-extern RegLocation getReturnLocAlt(CompilationUnit *cUnit);
+extern RegLocation dvmCompilerGetReturnAlt(CompilationUnit *cUnit);
/* Clobber any temp associated with an sReg. Could be in either class */
-extern void clobberSReg(CompilationUnit *cUnit, int sReg);
+extern void dvmCompilerClobberSReg(CompilationUnit *cUnit, int sReg);
/* Return a temp if one is available, -1 otherwise */
-extern int allocFreeTemp(CompilationUnit *cUnit);
+extern int dvmCompilerAllocFreeTemp(CompilationUnit *cUnit);
/*
- * Similar to allocTemp(), but forces the allocation of a specific
+ * Similar to dvmCompilerAllocTemp(), but forces the allocation of a specific
* register. No check is made to see if the register was previously
* allocated. Use with caution.
*/
-extern void lockTemp(CompilationUnit *cUnit, int reg);
+extern void dvmCompilerLockTemp(CompilationUnit *cUnit, int reg);
-extern RegLocation wideToNarrowLoc(CompilationUnit *cUnit, RegLocation rl);
+extern RegLocation dvmCompilerWideToNarrow(CompilationUnit *cUnit,
+ RegLocation rl);
/*
* Free all allocated temps in the temp pools. Note that this does
* not affect the "liveness" of a temp register, which will stay
* live until it is either explicitly killed or reallocated.
*/
-extern void resetRegPool(CompilationUnit *cUnit);
+extern void dvmCompilerResetRegPool(CompilationUnit *cUnit);
-extern void clobberAllRegs(CompilationUnit *cUnit);
+extern void dvmCompilerClobberAllRegs(CompilationUnit *cUnit);
-extern void resetDefTracking(CompilationUnit *cUnit);
+extern void dvmCompilerResetDefTracking(CompilationUnit *cUnit);
diff --git a/vm/compiler/codegen/arm/RallocUtil.c b/vm/compiler/codegen/arm/RallocUtil.c
index 5c12846..6c2fef1 100644
--- a/vm/compiler/codegen/arm/RallocUtil.c
+++ b/vm/compiler/codegen/arm/RallocUtil.c
@@ -30,11 +30,6 @@
#include "Ralloc.h"
/*
- * FIXME - dvmCompiler prefixes are not added yet to routines exposed to the
- * code generator.
- */
-
-/*
* Register usage for 16-bit Thumb systems:
* r0-r3: Temp/argument
* lr(r14): Temp for translations, return address for handlers
@@ -73,7 +68,7 @@
* not affect the "liveness" of a temp register, which will stay
* live until it is either explicitly killed or reallocated.
*/
-extern void resetRegPool(CompilationUnit *cUnit)
+extern void dvmCompilerResetRegPool(CompilationUnit *cUnit)
{
int i;
for (i=0; i < cUnit->regPool->numCoreTemps; i++) {
@@ -85,7 +80,7 @@
}
/* Set up temp & preserved register pools specialized by target */
-extern void initPool(RegisterInfo *regs, int *regNums, int num)
+extern void dvmCompilerInitPool(RegisterInfo *regs, int *regNums, int num)
{
int i;
for (i=0; i < num; i++) {
@@ -142,10 +137,11 @@
if ((info1->live && info1->dirty) || (info2->live && info2->dirty)) {
info1->dirty = false;
info2->dirty = false;
- if (sReg2vReg(cUnit, info2->sReg) < sReg2vReg(cUnit, info1->sReg))
+ if (dvmCompilerS2VReg(cUnit, info2->sReg) <
+ dvmCompilerS2VReg(cUnit, info1->sReg))
info1 = info2;
dvmCompilerFlushRegWideImpl(cUnit, rFP,
- sReg2vReg(cUnit, info1->sReg) << 2,
+ dvmCompilerS2VReg(cUnit, info1->sReg) << 2,
info1->reg, info1->partner);
}
}
@@ -155,7 +151,8 @@
RegisterInfo *info = getRegInfo(cUnit, reg);
if (info->live && info->dirty) {
info->dirty = false;
- dvmCompilerFlushRegImpl(cUnit, rFP, sReg2vReg(cUnit, info->sReg) << 2,
+ dvmCompilerFlushRegImpl(cUnit, rFP,
+ dvmCompilerS2VReg(cUnit, info->sReg) << 2,
reg, kWord);
}
}
@@ -190,7 +187,7 @@
}
/* Mark a temp register as dead. Does not affect allocation state. */
-void clobberReg(CompilationUnit *cUnit, int reg)
+void dvmCompilerClobber(CompilationUnit *cUnit, int reg)
{
if (!clobberRegBody(cUnit, cUnit->regPool->coreTemps,
cUnit->regPool->numCoreTemps, reg)) {
@@ -212,7 +209,7 @@
}
/* Clobber any temp associated with an sReg. Could be in either class */
-extern void clobberSReg(CompilationUnit *cUnit, int sReg)
+extern void dvmCompilerClobberSReg(CompilationUnit *cUnit, int sReg)
{
clobberSRegBody(cUnit->regPool->coreTemps, cUnit->regPool->numCoreTemps,
sReg);
@@ -227,7 +224,7 @@
//Tuning: redo this to widen the live window on freed temps
for (i=0; i< numTemps; i++) {
if (!p[i].inUse && !p[i].live) {
- clobberReg(cUnit, p[i].reg);
+ dvmCompilerClobber(cUnit, p[i].reg);
p[i].inUse = true;
p[i].pair = false;
return p[i].reg;
@@ -235,7 +232,7 @@
}
for (i=0; i< numTemps; i++) {
if (!p[i].inUse) {
- clobberReg(cUnit, p[i].reg);
+ dvmCompilerClobber(cUnit, p[i].reg);
p[i].inUse = true;
p[i].pair = false;
return p[i].reg;
@@ -249,7 +246,7 @@
}
//REDO: too many assumptions.
-extern int allocTempDouble(CompilationUnit *cUnit)
+extern int dvmCompilerAllocTempDouble(CompilationUnit *cUnit)
{
RegisterInfo *p = cUnit->regPool->FPTemps;
int numTemps = cUnit->regPool->numFPTemps;
@@ -258,8 +255,8 @@
for (i=0; i < numTemps; i+=2) {
if ((!p[i].inUse && !p[i].live) &&
(!p[i+1].inUse && !p[i+1].live)) {
- clobberReg(cUnit, p[i].reg);
- clobberReg(cUnit, p[i+1].reg);
+ dvmCompilerClobber(cUnit, p[i].reg);
+ dvmCompilerClobber(cUnit, p[i+1].reg);
p[i].inUse = true;
p[i+1].inUse = true;
assert((p[i].reg+1) == p[i+1].reg);
@@ -269,8 +266,8 @@
}
for (i=0; i < numTemps; i+=2) {
if (!p[i].inUse && !p[i+1].inUse) {
- clobberReg(cUnit, p[i].reg);
- clobberReg(cUnit, p[i+1].reg);
+ dvmCompilerClobber(cUnit, p[i].reg);
+ dvmCompilerClobber(cUnit, p[i+1].reg);
p[i].inUse = true;
p[i+1].inUse = true;
assert((p[i].reg+1) == p[i+1].reg);
@@ -285,19 +282,19 @@
}
/* Return a temp if one is available, -1 otherwise */
-extern int allocFreeTemp(CompilationUnit *cUnit)
+extern int dvmCompilerAllocFreeTemp(CompilationUnit *cUnit)
{
return allocTempBody(cUnit, cUnit->regPool->coreTemps,
cUnit->regPool->numCoreTemps, true);
}
-extern int allocTemp(CompilationUnit *cUnit)
+extern int dvmCompilerAllocTemp(CompilationUnit *cUnit)
{
return allocTempBody(cUnit, cUnit->regPool->coreTemps,
cUnit->regPool->numCoreTemps, true);
}
-extern int allocTempFloat(CompilationUnit *cUnit)
+extern int dvmCompilerAllocTempFloat(CompilationUnit *cUnit)
{
return allocTempBody(cUnit, cUnit->regPool->FPTemps,
cUnit->regPool->numFPTemps, true);
@@ -344,7 +341,7 @@
return res;
}
-extern void freeTemp(CompilationUnit *cUnit, int reg)
+extern void dvmCompilerFreeTemp(CompilationUnit *cUnit, int reg)
{
RegisterInfo *p = cUnit->regPool->coreTemps;
int numTemps = cUnit->regPool->numCoreTemps;
@@ -370,7 +367,7 @@
}
//FIXME - this needs to also check the preserved pool.
-extern RegisterInfo *isLive(CompilationUnit *cUnit, int reg)
+extern RegisterInfo *dvmCompilerIsLive(CompilationUnit *cUnit, int reg)
{
RegisterInfo *p = cUnit->regPool->coreTemps;
int numTemps = cUnit->regPool->numCoreTemps;
@@ -390,7 +387,7 @@
return NULL;
}
-extern RegisterInfo *isTemp(CompilationUnit *cUnit, int reg)
+extern RegisterInfo *dvmCompilerIsTemp(CompilationUnit *cUnit, int reg)
{
RegisterInfo *p = cUnit->regPool->coreTemps;
int numTemps = cUnit->regPool->numCoreTemps;
@@ -411,11 +408,11 @@
}
/*
- * Similar to allocTemp(), but forces the allocation of a specific
+ * Similar to dvmCompilerAllocTemp(), but forces the allocation of a specific
* register. No check is made to see if the register was previously
* allocated. Use with caution.
*/
-extern void lockTemp(CompilationUnit *cUnit, int reg)
+extern void dvmCompilerLockTemp(CompilationUnit *cUnit, int reg)
{
RegisterInfo *p = cUnit->regPool->coreTemps;
int numTemps = cUnit->regPool->numCoreTemps;
@@ -442,36 +439,36 @@
static void lockArgRegs(CompilationUnit *cUnit)
{
- lockTemp(cUnit, r0);
- lockTemp(cUnit, r1);
- lockTemp(cUnit, r2);
- lockTemp(cUnit, r3);
+ dvmCompilerLockTemp(cUnit, r0);
+ dvmCompilerLockTemp(cUnit, r1);
+ dvmCompilerLockTemp(cUnit, r2);
+ dvmCompilerLockTemp(cUnit, r3);
}
/* Clobber all regs that might be used by an external C call */
-extern void clobberCallRegs(CompilationUnit *cUnit)
+extern void dvmCompilerColbberCallRegs(CompilationUnit *cUnit)
{
- clobberReg(cUnit, r0);
- clobberReg(cUnit, r1);
- clobberReg(cUnit, r2);
- clobberReg(cUnit, r3);
- clobberReg(cUnit, r9); // Not sure we need to do this, be convervative
- clobberReg(cUnit, r11);
- clobberReg(cUnit, r12);
- clobberReg(cUnit, rlr);
+ dvmCompilerClobber(cUnit, r0);
+ dvmCompilerClobber(cUnit, r1);
+ dvmCompilerClobber(cUnit, r2);
+ dvmCompilerClobber(cUnit, r3);
+ dvmCompilerClobber(cUnit, r9); // Need to do this?, be convervative
+ dvmCompilerClobber(cUnit, r11);
+ dvmCompilerClobber(cUnit, r12);
+ dvmCompilerClobber(cUnit, rlr);
}
/* Clobber all of the temps that might be used by a handler. */
-extern void clobberHandlerRegs(CompilationUnit *cUnit)
+extern void dvmCompilerClobberHandlerRegs(CompilationUnit *cUnit)
{
//TUNING: reduce the set of regs used by handlers. Only a few need lots.
- clobberCallRegs(cUnit);
- clobberReg(cUnit, r4PC);
- clobberReg(cUnit, r9);
- clobberReg(cUnit, r10);
+ dvmCompilerColbberCallRegs(cUnit);
+ dvmCompilerClobber(cUnit, r4PC);
+ dvmCompilerClobber(cUnit, r9);
+ dvmCompilerClobber(cUnit, r10);
}
-extern void resetDef(CompilationUnit *cUnit, int reg)
+extern void dvmCompilerResetDef(CompilationUnit *cUnit, int reg)
{
RegisterInfo *p = getRegInfo(cUnit, reg);
p->defStart = NULL;
@@ -497,7 +494,7 @@
* on entry start points to the LIR prior to the beginning of the
* sequence.
*/
-extern void markDef(CompilationUnit *cUnit, RegLocation rl,
+extern void dvmCompilerMarkDef(CompilationUnit *cUnit, RegLocation rl,
LIR *start, LIR *finish)
{
assert(!rl.wide);
@@ -513,19 +510,20 @@
* on entry start points to the LIR prior to the beginning of the
* sequence.
*/
-extern void markDefWide(CompilationUnit *cUnit, RegLocation rl,
+extern void dvmCompilerMarkDefWide(CompilationUnit *cUnit, RegLocation rl,
LIR *start, LIR *finish)
{
assert(rl.wide);
assert(start && start->next);
assert(finish);
RegisterInfo *p = getRegInfo(cUnit, rl.lowReg);
- resetDef(cUnit, rl.highReg); // Only track low of pair
+ dvmCompilerResetDef(cUnit, rl.highReg); // Only track low of pair
p->defStart = start->next;
p->defEnd = finish;
}
-extern RegLocation wideToNarrowLoc(CompilationUnit *cUnit, RegLocation rl)
+extern RegLocation dvmCompilerWideToNarrow(CompilationUnit *cUnit,
+ RegLocation rl)
{
assert(rl.wide);
if (rl.location == kLocPhysReg) {
@@ -556,7 +554,7 @@
return rl;
}
-extern void resetDefLoc(CompilationUnit *cUnit, RegLocation rl)
+extern void dvmCompilerResetDefLoc(CompilationUnit *cUnit, RegLocation rl)
{
assert(!rl.wide);
if (!(gDvmJit.disableOpt & (1 << kSuppressLoads))) {
@@ -565,10 +563,10 @@
nullifyRange(cUnit, p->defStart, p->defEnd,
p->sReg, rl.sRegLow);
}
- resetDef(cUnit, rl.lowReg);
+ dvmCompilerResetDef(cUnit, rl.lowReg);
}
-extern void resetDefLocWide(CompilationUnit *cUnit, RegLocation rl)
+extern void dvmCompilerResetDefLocWide(CompilationUnit *cUnit, RegLocation rl)
{
assert(rl.wide);
if (!(gDvmJit.disableOpt & (1 << kSuppressLoads))) {
@@ -577,38 +575,38 @@
nullifyRange(cUnit, p->defStart, p->defEnd,
p->sReg, rl.sRegLow);
}
- resetDef(cUnit, rl.lowReg);
- resetDef(cUnit, rl.highReg);
+ dvmCompilerResetDef(cUnit, rl.lowReg);
+ dvmCompilerResetDef(cUnit, rl.highReg);
}
-extern void resetDefTracking(CompilationUnit *cUnit)
+extern void dvmCompilerResetDefTracking(CompilationUnit *cUnit)
{
int i;
for (i=0; i< cUnit->regPool->numCoreTemps; i++) {
- resetDef(cUnit, cUnit->regPool->coreTemps[i].reg);
+ dvmCompilerResetDef(cUnit, cUnit->regPool->coreTemps[i].reg);
}
for (i=0; i< cUnit->regPool->numFPTemps; i++) {
- resetDef(cUnit, cUnit->regPool->FPTemps[i].reg);
+ dvmCompilerResetDef(cUnit, cUnit->regPool->FPTemps[i].reg);
}
}
-extern void clobberAllRegs(CompilationUnit *cUnit)
+extern void dvmCompilerClobberAllRegs(CompilationUnit *cUnit)
{
int i;
for (i=0; i< cUnit->regPool->numCoreTemps; i++) {
- clobberReg(cUnit, cUnit->regPool->coreTemps[i].reg);
+ dvmCompilerClobber(cUnit, cUnit->regPool->coreTemps[i].reg);
}
for (i=0; i< cUnit->regPool->numFPTemps; i++) {
- clobberReg(cUnit, cUnit->regPool->FPTemps[i].reg);
+ dvmCompilerClobber(cUnit, cUnit->regPool->FPTemps[i].reg);
}
}
/* To be used when explicitly managing register use */
-extern void lockAllTemps(CompilationUnit *cUnit)
+extern void dvmCompilerLockAllTemps(CompilationUnit *cUnit)
{
int i;
for (i=0; i< cUnit->regPool->numCoreTemps; i++) {
- lockTemp(cUnit, cUnit->regPool->coreTemps[i].reg);
+ dvmCompilerLockTemp(cUnit, cUnit->regPool->coreTemps[i].reg);
}
}
@@ -628,13 +626,13 @@
}
}
-extern void flushAllRegs(CompilationUnit *cUnit)
+extern void dvmCompilerFlushAllRegs(CompilationUnit *cUnit)
{
flushAllRegsBody(cUnit, cUnit->regPool->coreTemps,
cUnit->regPool->numCoreTemps);
flushAllRegsBody(cUnit, cUnit->regPool->FPTemps,
cUnit->regPool->numFPTemps);
- clobberAllRegs(cUnit);
+ dvmCompilerClobberAllRegs(cUnit);
}
@@ -650,13 +648,13 @@
}
}
-extern void markRegLive(CompilationUnit *cUnit, int reg, int sReg)
+extern void dvmCompilerMarkLive(CompilationUnit *cUnit, int reg, int sReg)
{
RegisterInfo *info = getRegInfo(cUnit, reg);
if ((info->reg == reg) && (info->sReg == sReg) && info->live) {
return; /* already live */
} else if (sReg != INVALID_SREG) {
- clobberSReg(cUnit, sReg);
+ dvmCompilerClobberSReg(cUnit, sReg);
info->live = true;
} else {
/* Can't be live if no associated sReg */
@@ -665,7 +663,7 @@
info->sReg = sReg;
}
-extern void markRegPair(CompilationUnit *cUnit, int lowReg, int highReg)
+extern void dvmCompilerMarkPair(CompilationUnit *cUnit, int lowReg, int highReg)
{
RegisterInfo *infoLo = getRegInfo(cUnit, lowReg);
RegisterInfo *infoHi = getRegInfo(cUnit, highReg);
@@ -680,19 +678,19 @@
info->pair = false;
}
-extern void markRegClean(CompilationUnit *cUnit, int reg)
+extern void dvmCompilerMarkClean(CompilationUnit *cUnit, int reg)
{
RegisterInfo *info = getRegInfo(cUnit, reg);
info->dirty = false;
}
-extern void markRegDirty(CompilationUnit *cUnit, int reg)
+extern void dvmCompilerMarkDirty(CompilationUnit *cUnit, int reg)
{
RegisterInfo *info = getRegInfo(cUnit, reg);
info->dirty = true;
}
-extern void markRegInUse(CompilationUnit *cUnit, int reg)
+extern void dvmcompilerMarkInUse(CompilationUnit *cUnit, int reg)
{
RegisterInfo *info = getRegInfo(cUnit, reg);
info->inUse = true;
@@ -722,15 +720,15 @@
* is a bit complex when dealing with FP regs. Examine code to see
* if it's worthwhile trying to be more clever here.
*/
-extern RegLocation updateLoc(CompilationUnit *cUnit, RegLocation loc)
+extern RegLocation dvmCompilerUpdateLoc(CompilationUnit *cUnit, RegLocation loc)
{
assert(!loc.wide);
if (loc.location == kLocDalvikFrame) {
RegisterInfo *infoLo = allocLive(cUnit, loc.sRegLow, kAnyReg);
if (infoLo) {
if (infoLo->pair) {
- clobberReg(cUnit, infoLo->reg);
- clobberReg(cUnit, infoLo->partner);
+ dvmCompilerClobber(cUnit, infoLo->reg);
+ dvmCompilerClobber(cUnit, infoLo->partner);
} else {
loc.lowReg = infoLo->reg;
loc.location = kLocPhysReg;
@@ -742,12 +740,14 @@
}
/* see comments for updateLoc */
-extern RegLocation updateLocWide(CompilationUnit *cUnit, RegLocation loc)
+extern RegLocation dvmCompilerUpdateLocWide(CompilationUnit *cUnit,
+ RegLocation loc)
{
assert(loc.wide);
if (loc.location == kLocDalvikFrame) {
RegisterInfo *infoLo = allocLive(cUnit, loc.sRegLow, kAnyReg);
- RegisterInfo *infoHi = allocLive(cUnit, hiSReg(loc.sRegLow), kAnyReg);
+ RegisterInfo *infoHi = allocLive(cUnit,
+ dvmCompilerSRegHi(loc.sRegLow), kAnyReg);
bool match = true;
match = match && (infoLo != NULL);
match = match && (infoHi != NULL);
@@ -760,20 +760,20 @@
loc.lowReg = infoLo->reg;
loc.highReg = infoHi->reg;
loc.location = kLocPhysReg;
- markRegPair(cUnit, loc.lowReg, loc.highReg);
+ dvmCompilerMarkPair(cUnit, loc.lowReg, loc.highReg);
assert(!FPREG(loc.lowReg) || ((loc.lowReg & 0x1) == 0));
return loc;
}
/* Can't easily reuse - just clobber any overlaps */
if (infoLo) {
- clobberReg(cUnit, infoLo->reg);
+ dvmCompilerClobber(cUnit, infoLo->reg);
if (infoLo->pair)
- clobberReg(cUnit, infoLo->partner);
+ dvmCompilerClobber(cUnit, infoLo->partner);
}
if (infoHi) {
- clobberReg(cUnit, infoHi->reg);
+ dvmCompilerClobber(cUnit, infoHi->reg);
if (infoHi->pair)
- clobberReg(cUnit, infoHi->partner);
+ dvmCompilerClobber(cUnit, infoHi->partner);
}
}
@@ -788,7 +788,7 @@
int lowReg;
int highReg;
- loc = updateLocWide(cUnit, loc);
+ loc = dvmCompilerUpdateLocWide(cUnit, loc);
/* If already in registers, we can assume proper form. Right reg class? */
if (loc.location == kLocPhysReg) {
@@ -803,11 +803,11 @@
loc.highReg);
copyRegInfo(cUnit, lowReg, loc.lowReg);
copyRegInfo(cUnit, highReg, loc.highReg);
- clobberReg(cUnit, loc.lowReg);
- clobberReg(cUnit, loc.highReg);
+ dvmCompilerClobber(cUnit, loc.lowReg);
+ dvmCompilerClobber(cUnit, loc.highReg);
loc.lowReg = lowReg;
loc.highReg = highReg;
- markRegPair(cUnit, loc.lowReg, loc.highReg);
+ dvmCompilerMarkPair(cUnit, loc.lowReg, loc.highReg);
assert(!FPREG(loc.lowReg) || ((loc.lowReg & 0x1) == 0));
}
return loc;
@@ -815,30 +815,30 @@
assert((loc.location != kLocRetval) || (loc.sRegLow == INVALID_SREG));
assert((loc.location != kLocRetval) ||
- (hiSReg(loc.sRegLow) == INVALID_SREG));
+ (dvmCompilerSRegHi(loc.sRegLow) == INVALID_SREG));
newRegs = dvmCompilerAllocTypedTempPair(cUnit, loc.fp, regClass);
loc.lowReg = newRegs & 0xff;
loc.highReg = (newRegs >> 8) & 0xff;
- markRegPair(cUnit, loc.lowReg, loc.highReg);
+ dvmCompilerMarkPair(cUnit, loc.lowReg, loc.highReg);
if (update) {
loc.location = kLocPhysReg;
- markRegLive(cUnit, loc.lowReg, loc.sRegLow);
- markRegLive(cUnit, loc.highReg, hiSReg(loc.sRegLow));
+ dvmCompilerMarkLive(cUnit, loc.lowReg, loc.sRegLow);
+ dvmCompilerMarkLive(cUnit, loc.highReg, dvmCompilerSRegHi(loc.sRegLow));
}
assert(!FPREG(loc.lowReg) || ((loc.lowReg & 0x1) == 0));
return loc;
}
-extern RegLocation evalLoc(CompilationUnit *cUnit, RegLocation loc,
- int regClass, bool update)
+extern RegLocation dvmCompilerEvalLoc(CompilationUnit *cUnit, RegLocation loc,
+ int regClass, bool update)
{
RegisterInfo *infoLo = NULL;
int newReg;
if (loc.wide)
return evalLocWide(cUnit, loc, regClass, update);
- loc = updateLoc(cUnit, loc);
+ loc = dvmCompilerUpdateLoc(cUnit, loc);
if (loc.location == kLocPhysReg) {
if (!regClassMatches(regClass, loc.lowReg)) {
@@ -846,7 +846,7 @@
newReg = dvmCompilerAllocTypedTemp(cUnit, loc.fp, regClass);
dvmCompilerRegCopy(cUnit, newReg, loc.lowReg);
copyRegInfo(cUnit, newReg, loc.lowReg);
- clobberReg(cUnit, loc.lowReg);
+ dvmCompilerClobber(cUnit, loc.lowReg);
loc.lowReg = newReg;
}
return loc;
@@ -859,7 +859,7 @@
if (update) {
loc.location = kLocPhysReg;
- markRegLive(cUnit, loc.lowReg, loc.sRegLow);
+ dvmCompilerMarkLive(cUnit, loc.lowReg, loc.sRegLow);
}
return loc;
}
@@ -871,16 +871,18 @@
}
// Get the LocRecord associated with an SSA name use.
-extern RegLocation getSrcLoc(CompilationUnit *cUnit, MIR *mir, int num)
+extern RegLocation dvmCompilerGetSrc(CompilationUnit *cUnit, MIR *mir, int num)
{
- RegLocation loc = cUnit->regLocation[SREG(cUnit, getSrcSSAName(mir, num))];
- loc.fp = cUnit->regLocation[getSrcSSAName(mir, num)].fp;
+ RegLocation loc = cUnit->regLocation[
+ SREG(cUnit, dvmCompilerSSASrc(mir, num))];
+ loc.fp = cUnit->regLocation[dvmCompilerSSASrc(mir, num)].fp;
loc.wide = false;
return loc;
}
// Get the LocRecord associated with an SSA name def.
-extern RegLocation getDestLoc(CompilationUnit *cUnit, MIR *mir, int num)
+extern RegLocation dvmCompilerGetDest(CompilationUnit *cUnit, MIR *mir,
+ int num)
{
RegLocation loc = cUnit->regLocation[SREG(cUnit, getDestSSAName(mir, num))];
loc.fp = cUnit->regLocation[getDestSSAName(mir, num)].fp;
@@ -889,17 +891,17 @@
}
static RegLocation getLocWide(CompilationUnit *cUnit, MIR *mir,
- int low, int high, bool isSrc)
+ int low, int high, bool isSrc)
{
RegLocation lowLoc;
RegLocation highLoc;
/* Copy loc record for low word and patch in data from high word */
if (isSrc) {
- lowLoc = getSrcLoc(cUnit, mir, low);
- highLoc = getSrcLoc(cUnit, mir, high);
+ lowLoc = dvmCompilerGetSrc(cUnit, mir, low);
+ highLoc = dvmCompilerGetSrc(cUnit, mir, high);
} else {
- lowLoc = getDestLoc(cUnit, mir, low);
- highLoc = getDestLoc(cUnit, mir, high);
+ lowLoc = dvmCompilerGetDest(cUnit, mir, low);
+ highLoc = dvmCompilerGetDest(cUnit, mir, high);
}
/* Avoid this case by either promoting both or neither. */
assert(lowLoc.location == highLoc.location);
@@ -912,69 +914,70 @@
return lowLoc;
}
-extern RegLocation getDestLocWide(CompilationUnit *cUnit, MIR *mir,
- int low, int high)
+extern RegLocation dvmCompilerGetDestWide(CompilationUnit *cUnit, MIR *mir,
+ int low, int high)
{
return getLocWide(cUnit, mir, low, high, false);
}
-extern RegLocation getSrcLocWide(CompilationUnit *cUnit, MIR *mir,
+extern RegLocation dvmCompilerGetSrcWide(CompilationUnit *cUnit, MIR *mir,
int low, int high)
{
return getLocWide(cUnit, mir, low, high, true);
}
-extern RegLocation getReturnLocWide(CompilationUnit *cUnit)
+extern RegLocation dvmCompilerGetReturnWide(CompilationUnit *cUnit)
{
RegLocation res = LOC_C_RETURN_WIDE;
- clobberReg(cUnit, r0);
- clobberReg(cUnit, r1);
- markRegInUse(cUnit, r0);
- markRegInUse(cUnit, r1);
- markRegPair(cUnit, res.lowReg, res.highReg);
+ dvmCompilerClobber(cUnit, r0);
+ dvmCompilerClobber(cUnit, r1);
+ dvmcompilerMarkInUse(cUnit, r0);
+ dvmcompilerMarkInUse(cUnit, r1);
+ dvmCompilerMarkPair(cUnit, res.lowReg, res.highReg);
return res;
}
-extern RegLocation getReturnLocWideAlt(CompilationUnit *cUnit)
+extern RegLocation dvmCompilerGetReturnWideAlt(CompilationUnit *cUnit)
{
RegLocation res = LOC_C_RETURN_WIDE;
res.lowReg = r2;
res.highReg = r3;
- clobberReg(cUnit, r2);
- clobberReg(cUnit, r3);
- markRegInUse(cUnit, r2);
- markRegInUse(cUnit, r3);
- markRegPair(cUnit, res.lowReg, res.highReg);
+ dvmCompilerClobber(cUnit, r2);
+ dvmCompilerClobber(cUnit, r3);
+ dvmcompilerMarkInUse(cUnit, r2);
+ dvmcompilerMarkInUse(cUnit, r3);
+ dvmCompilerMarkPair(cUnit, res.lowReg, res.highReg);
return res;
}
-extern RegLocation getReturnLoc(CompilationUnit *cUnit)
+extern RegLocation dvmCompilerGetReturn(CompilationUnit *cUnit)
{
RegLocation res = LOC_C_RETURN;
- clobberReg(cUnit, r0);
- markRegInUse(cUnit, r0);
+ dvmCompilerClobber(cUnit, r0);
+ dvmcompilerMarkInUse(cUnit, r0);
return res;
}
-extern RegLocation getReturnLocAlt(CompilationUnit *cUnit)
+extern RegLocation dvmCompilerGetReturnAlt(CompilationUnit *cUnit)
{
RegLocation res = LOC_C_RETURN;
res.lowReg = r1;
- clobberReg(cUnit, r1);
- markRegInUse(cUnit, r1);
+ dvmCompilerClobber(cUnit, r1);
+ dvmcompilerMarkInUse(cUnit, r1);
return res;
}
/* Kill the corresponding bit in the null-checked register list */
-extern void killNullCheckedLocation(CompilationUnit *cUnit,
- RegLocation loc)
+extern void dvmCompilerKillNullCheckedLoc(CompilationUnit *cUnit,
+ RegLocation loc)
{
if (loc.location != kLocRetval) {
assert(loc.sRegLow != INVALID_SREG);
dvmClearBit(cUnit->regPool->nullCheckedRegs, loc.sRegLow);
if (loc.wide) {
- assert(hiSReg(loc.sRegLow) != INVALID_SREG);
- dvmClearBit(cUnit->regPool->nullCheckedRegs, hiSReg(loc.sRegLow));
+ assert(dvmCompilerSRegHi(loc.sRegLow) != INVALID_SREG);
+ dvmClearBit(cUnit->regPool->nullCheckedRegs,
+ dvmCompilerSRegHi(loc.sRegLow));
}
}
}
diff --git a/vm/compiler/codegen/arm/Thumb/Factory.c b/vm/compiler/codegen/arm/Thumb/Factory.c
index 586e640..5bf4048 100644
--- a/vm/compiler/codegen/arm/Thumb/Factory.c
+++ b/vm/compiler/codegen/arm/Thumb/Factory.c
@@ -47,13 +47,13 @@
static ArmLIR *loadConstantValue(CompilationUnit *cUnit, int rDest, int value)
{
ArmLIR *res;
- int tDest = LOWREG(rDest) ? rDest : allocTemp(cUnit);
+ int tDest = LOWREG(rDest) ? rDest : dvmCompilerAllocTemp(cUnit);
/* See if the value can be constructed cheaply */
if ((value >= 0) && (value <= 255)) {
res = newLIR2(cUnit, kThumbMovImm, tDest, value);
if (rDest != tDest) {
opRegReg(cUnit, kOpMov, rDest, tDest);
- freeTemp(cUnit, tDest);
+ dvmCompilerFreeTemp(cUnit, tDest);
}
return res;
} else if ((value & 0xFFFFFF00) == 0xFFFFFF00) {
@@ -61,7 +61,7 @@
newLIR2(cUnit, kThumbMvn, tDest, tDest);
if (rDest != tDest) {
opRegReg(cUnit, kOpMov, rDest, tDest);
- freeTemp(cUnit, tDest);
+ dvmCompilerFreeTemp(cUnit, tDest);
}
return res;
}
@@ -87,7 +87,7 @@
}
if (rDest != tDest) {
opRegReg(cUnit, kOpMov, rDest, tDest);
- freeTemp(cUnit, tDest);
+ dvmCompilerFreeTemp(cUnit, tDest);
}
return res;
}
@@ -98,9 +98,9 @@
*/
static ArmLIR *loadConstant(CompilationUnit *cUnit, int rDest, int value)
{
- if (isTemp(cUnit, rDest)) {
- clobberReg(cUnit, rDest);
- markRegInUse(cUnit, rDest);
+ if (dvmCompilerIsTemp(cUnit, rDest)) {
+ dvmCompilerClobber(cUnit, rDest);
+ dvmcompilerMarkInUse(cUnit, rDest);
}
return loadConstantValue(cUnit, rDest, value);
}
@@ -198,7 +198,7 @@
if (shortForm)
res = newLIR2(cUnit, opCode, rDestSrc1, absValue);
else {
- int rScratch = allocTemp(cUnit);
+ int rScratch = dvmCompilerAllocTemp(cUnit);
res = loadConstant(cUnit, rScratch, value);
if (op == kOpCmp)
newLIR2(cUnit, opCode, rDestSrc1, rScratch);
@@ -223,8 +223,8 @@
if (rDest == rSrc1) {
return opRegReg(cUnit, op, rDest, rSrc2);
} else if (rDest == rSrc2) {
- assert(isTemp(cUnit, rSrc1));
- clobberReg(cUnit, rSrc1);
+ assert(dvmCompilerIsTemp(cUnit, rSrc1));
+ dvmCompilerClobber(cUnit, rSrc1);
opRegReg(cUnit, op, rSrc1, rSrc2);
return opRegReg(cUnit, kOpMov, rDest, rSrc1);
} else {
@@ -303,7 +303,7 @@
case kOpOr:
case kOpXor:
if (rDest == rSrc1) {
- int rScratch = allocTemp(cUnit);
+ int rScratch = dvmCompilerAllocTemp(cUnit);
res = loadConstant(cUnit, rScratch, value);
opRegReg(cUnit, op, rDest, rScratch);
} else {
@@ -322,7 +322,7 @@
res = loadConstant(cUnit, rDest, value);
newLIR3(cUnit, opCode, rDest, rSrc1, rDest);
} else {
- int rScratch = allocTemp(cUnit);
+ int rScratch = dvmCompilerAllocTemp(cUnit);
res = loadConstant(cUnit, rScratch, value);
newLIR3(cUnit, opCode, rDest, rSrc1, rScratch);
}
@@ -434,7 +434,7 @@
int rNewIndex = rIndex;
if (scale) {
// Scale the index, but can't trash the original.
- rNewIndex = allocTemp(cUnit);
+ rNewIndex = dvmCompilerAllocTemp(cUnit);
first = opRegRegImm(cUnit, kOpLsl, rNewIndex, rIndex, scale);
}
switch (size) {
@@ -462,7 +462,7 @@
res->branchInsertSV = true;
#endif
if (scale)
- freeTemp(cUnit, rNewIndex);
+ dvmCompilerFreeTemp(cUnit, rNewIndex);
return (first) ? first : res;
}
@@ -475,7 +475,7 @@
ArmOpCode opCode = kThumbBkpt;
int rNewIndex = rIndex;
if (scale) {
- rNewIndex = allocTemp(cUnit);
+ rNewIndex = dvmCompilerAllocTemp(cUnit);
first = opRegRegImm(cUnit, kOpLsl, rNewIndex, rIndex, scale);
}
switch (size) {
@@ -499,7 +499,7 @@
res->branchInsertSV = true;
#endif
if (scale)
- freeTemp(cUnit, rNewIndex);
+ dvmCompilerFreeTemp(cUnit, rNewIndex);
return (first) ? first : res;
}
@@ -508,6 +508,10 @@
ArmLIR *res;
genBarrier(cUnit);
res = newLIR2(cUnit, kThumbLdmia, rBase, rMask);
+#if defined(WITH_SELF_VERIFICATION)
+ if (cUnit->heapMemOp)
+ res->branchInsertSV = true;
+#endif
genBarrier(cUnit);
return res;
}
@@ -517,6 +521,10 @@
ArmLIR *res;
genBarrier(cUnit);
res = newLIR2(cUnit, kThumbStmia, rBase, rMask);
+#if defined(WITH_SELF_VERIFICATION)
+ if (cUnit->heapMemOp)
+ res->branchInsertSV = true;
+#endif
genBarrier(cUnit);
return res;
}
@@ -609,7 +617,7 @@
}
} else {
if (pair) {
- int rTmp = allocFreeTemp(cUnit);
+ int rTmp = dvmCompilerAllocFreeTemp(cUnit);
if (rTmp < 0) {
//UNIMP: need to spill if no temps.
assert(0);
@@ -617,9 +625,9 @@
res = opRegRegImm(cUnit, kOpAdd, rTmp, rBase, displacement);
//TUNING: how to mark loadPair if Dalvik access?
loadPair(cUnit, rTmp, rDest, rDestHi);
- freeTemp(cUnit, rTmp);
+ dvmCompilerFreeTemp(cUnit, rTmp);
} else {
- int rTmp = (rBase == rDest) ? allocFreeTemp(cUnit) : rDest;
+ int rTmp = (rBase == rDest) ? dvmCompilerAllocFreeTemp(cUnit) : rDest;
if (rTmp < 0) {
//UNIMP: need to spill if no temps.
assert(0);
@@ -630,7 +638,7 @@
annotateDalvikRegAccess(load, displacement >> 2,
true /* isLoad */);
if (rTmp != rDest)
- freeTemp(cUnit, rTmp);
+ dvmCompilerFreeTemp(cUnit, rTmp);
}
}
#if defined(WITH_SELF_VERIFICATION)
@@ -724,7 +732,7 @@
store2 = newLIR3(cUnit, opCode, rSrcHi, rBase, encodedDisp + 1);
}
} else {
- int rScratch = allocTemp(cUnit);
+ int rScratch = dvmCompilerAllocTemp(cUnit);
if (pair) {
//TUNING: how to mark storePair as Dalvik access if it is?
res = opRegRegImm(cUnit, kOpAdd, rScratch, rBase, displacement);
@@ -737,7 +745,7 @@
false /* isLoad */);
}
}
- freeTemp(cUnit, rScratch);
+ dvmCompilerFreeTemp(cUnit, rScratch);
}
#if defined(WITH_SELF_VERIFICATION)
if (store != NULL && cUnit->heapMemOp)
@@ -812,7 +820,7 @@
}
static void genRegCopyWide(CompilationUnit *cUnit, int destLo, int destHi,
- int srcLo, int srcHi)
+ int srcLo, int srcHi)
{
// Handle overlap
if (srcHi == destLo) {
@@ -825,17 +833,17 @@
}
static inline ArmLIR *genRegImmCheck(CompilationUnit *cUnit,
- ArmConditionCode cond, int reg,
- int checkValue, int dOffset,
- ArmLIR *pcrLabel)
+ ArmConditionCode cond, int reg,
+ int checkValue, int dOffset,
+ ArmLIR *pcrLabel)
{
int tReg;
ArmLIR *res;
if ((checkValue & 0xff) != checkValue) {
- tReg = allocTemp(cUnit);
+ tReg = dvmCompilerAllocTemp(cUnit);
loadConstant(cUnit, tReg, checkValue);
res = genRegRegCheck(cUnit, cond, reg, tReg, dOffset, pcrLabel);
- freeTemp(cUnit, tReg);
+ dvmCompilerFreeTemp(cUnit, tReg);
return res;
}
newLIR2(cUnit, kThumbCmpRI8, reg, checkValue);
diff --git a/vm/compiler/codegen/arm/Thumb/Gen.c b/vm/compiler/codegen/arm/Thumb/Gen.c
index 2e03fe1..a274e19 100644
--- a/vm/compiler/codegen/arm/Thumb/Gen.c
+++ b/vm/compiler/codegen/arm/Thumb/Gen.c
@@ -31,18 +31,18 @@
{
RegLocation rlResult;
rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
opRegRegImm(cUnit, kOpAdd, rlResult.lowReg,
rlSrc.lowReg, 0x80000000);
storeValue(cUnit, rlDest, rlResult);
}
static void genNegDouble(CompilationUnit *cUnit, RegLocation rlDest,
- RegLocation rlSrc)
+ RegLocation rlSrc)
{
RegLocation rlResult;
rlSrc = loadValueWide(cUnit, rlSrc, kCoreReg);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
opRegRegImm(cUnit, kOpAdd, rlResult.highReg, rlSrc.highReg,
0x80000000);
genRegCopy(cUnit, rlResult.lowReg, rlSrc.lowReg);
@@ -56,7 +56,7 @@
loadValueDirectWideFixed(cUnit, rlSrc1, r0, r1);
loadValueDirectWideFixed(cUnit, rlSrc2, r2, r3);
genDispatchToHandler(cUnit, TEMPLATE_MUL_LONG);
- rlResult = getReturnLocWide(cUnit);
+ rlResult = dvmCompilerGetReturnWide(cUnit);
storeValueWide(cUnit, rlDest, rlResult);
}
@@ -79,10 +79,10 @@
opRegReg(cUnit, firstOp, rlSrc1.lowReg, rlResult.lowReg);
opRegReg(cUnit, secondOp, rlSrc1.highReg, rlResult.highReg);
// Old reg assignments are now invalid
- clobberReg(cUnit, rlResult.lowReg);
- clobberReg(cUnit, rlResult.highReg);
- clobberReg(cUnit, rlSrc1.lowReg);
- clobberReg(cUnit, rlSrc1.highReg);
+ dvmCompilerClobber(cUnit, rlResult.lowReg);
+ dvmCompilerClobber(cUnit, rlResult.highReg);
+ dvmCompilerClobber(cUnit, rlSrc1.lowReg);
+ dvmCompilerClobber(cUnit, rlSrc1.highReg);
rlDest.location = kLocDalvikFrame;
assert(rlSrc1.location == kLocPhysReg);
// Reassign registers - rlDest will now get rlSrc1's old regs
@@ -90,7 +90,7 @@
} else {
// Copy Src1 to Dest
rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, false);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, false);
loadValueDirectWide(cUnit, rlSrc1, rlResult.lowReg,
rlResult.highReg);
rlResult.location = kLocPhysReg;
@@ -115,10 +115,10 @@
pool->coreRegs = NULL;
pool->numFPRegs = 0;
pool->FPRegs = NULL;
- initPool(pool->coreTemps, coreTemps, pool->numCoreTemps);
- initPool(pool->FPTemps, NULL, 0);
- initPool(pool->coreRegs, NULL, 0);
- initPool(pool->FPRegs, NULL, 0);
+ dvmCompilerInitPool(pool->coreTemps, coreTemps, pool->numCoreTemps);
+ dvmCompilerInitPool(pool->FPTemps, NULL, 0);
+ dvmCompilerInitPool(pool->coreRegs, NULL, 0);
+ dvmCompilerInitPool(pool->FPRegs, NULL, 0);
pool->nullCheckedRegs =
dvmCompilerAllocBitVector(cUnit->numSSARegs, false);
}
@@ -127,8 +127,8 @@
static ArmLIR *genExportPC(CompilationUnit *cUnit, MIR *mir)
{
ArmLIR *res;
- int rDPC = allocTemp(cUnit);
- int rAddr = allocTemp(cUnit);
+ int rDPC = dvmCompilerAllocTemp(cUnit);
+ int rAddr = dvmCompilerAllocTemp(cUnit);
int offset = offsetof(StackSaveArea, xtra.currentPc);
res = loadConstant(cUnit, rDPC, (int) (cUnit->method->insns + mir->offset));
newLIR2(cUnit, kThumbMovRR, rAddr, rFP);
@@ -149,7 +149,7 @@
loadValueDirectWideFixed(cUnit, rlSrc1, r0, r1);
loadValueDirectWideFixed(cUnit, rlSrc2, r2, r3);
genDispatchToHandler(cUnit, TEMPLATE_CMP_LONG);
- rlResult = getReturnLoc(cUnit);
+ rlResult = dvmCompilerGetReturn(cUnit);
storeValue(cUnit, rlDest, rlResult);
}
@@ -157,10 +157,10 @@
{
DecodedInstruction *dInsn = &mir->dalvikInsn;
int offset = offsetof(InterpState, retval);
- RegLocation rlObj = getSrcLoc(cUnit, mir, 0);
+ RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 0);
int regObj = loadValue(cUnit, rlObj, kCoreReg).lowReg;
- int reg1 = allocTemp(cUnit);
- genNullCheck(cUnit, getSrcSSAName(mir, 0), regObj, mir->offset, NULL);
+ int reg1 = dvmCompilerAllocTemp(cUnit);
+ genNullCheck(cUnit, dvmCompilerSSASrc(mir, 0), regObj, mir->offset, NULL);
loadWordDisp(cUnit, regObj, gDvm.offJavaLangString_count, reg1);
storeWordDisp(cUnit, rGLUE, offset, reg1);
return false;
@@ -171,13 +171,13 @@
DecodedInstruction *dInsn = &mir->dalvikInsn;
int offset = offsetof(InterpState, retval);
int contents = offsetof(ArrayObject, contents);
- RegLocation rlObj = getSrcLoc(cUnit, mir, 0);
- RegLocation rlIdx = getSrcLoc(cUnit, mir, 1);
+ RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 0);
+ RegLocation rlIdx = dvmCompilerGetSrc(cUnit, mir, 1);
int regObj = loadValue(cUnit, rlObj, kCoreReg).lowReg;
int regIdx = loadValue(cUnit, rlIdx, kCoreReg).lowReg;
- int regMax = allocTemp(cUnit);
- int regOff = allocTemp(cUnit);
- ArmLIR * pcrLabel = genNullCheck(cUnit, getSrcSSAName(mir, 0),
+ int regMax = dvmCompilerAllocTemp(cUnit);
+ int regOff = dvmCompilerAllocTemp(cUnit);
+ ArmLIR * pcrLabel = genNullCheck(cUnit, dvmCompilerSSASrc(mir, 0),
regObj, mir->offset, NULL);
loadWordDisp(cUnit, regObj, gDvm.offJavaLangString_count, regMax);
loadWordDisp(cUnit, regObj, gDvm.offJavaLangString_offset, regOff);
@@ -188,61 +188,61 @@
newLIR3(cUnit, kThumbAddRRR, regIdx, regIdx, regOff);
newLIR3(cUnit, kThumbAddRRR, regIdx, regIdx, regIdx);
newLIR3(cUnit, kThumbLdrhRRR, regMax, regObj, regIdx);
- freeTemp(cUnit, regOff);
+ dvmCompilerFreeTemp(cUnit, regOff);
storeWordDisp(cUnit, rGLUE, offset, regMax);
//FIXME: rewrite this to not clobber
- clobberReg(cUnit, regObj);
- clobberReg(cUnit, regIdx);
+ dvmCompilerClobber(cUnit, regObj);
+ dvmCompilerClobber(cUnit, regIdx);
return false;
}
static bool genInlinedAbsInt(CompilationUnit *cUnit, MIR *mir)
{
int offset = offsetof(InterpState, retval);
- RegLocation rlSrc = getSrcLoc(cUnit, mir, 0);
+ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
int reg0 = loadValue(cUnit, rlSrc, kCoreReg).lowReg;
- int sign = allocTemp(cUnit);
+ int sign = dvmCompilerAllocTemp(cUnit);
/* abs(x) = y<=x>>31, (x+y)^y. Shorter in ARM/THUMB2, no skip in THUMB */
newLIR3(cUnit, kThumbAsrRRI5, sign, reg0, 31);
newLIR3(cUnit, kThumbAddRRR, reg0, reg0, sign);
newLIR2(cUnit, kThumbEorRR, reg0, sign);
- freeTemp(cUnit, sign);
+ dvmCompilerFreeTemp(cUnit, sign);
storeWordDisp(cUnit, rGLUE, offset, reg0);
//FIXME: rewrite this to not clobber
- clobberReg(cUnit, reg0);
+ dvmCompilerClobber(cUnit, reg0);
return false;
}
static bool genInlinedAbsFloat(CompilationUnit *cUnit, MIR *mir)
{
int offset = offsetof(InterpState, retval);
- RegLocation rlSrc = getSrcLoc(cUnit, mir, 0);
+ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
int reg0 = loadValue(cUnit, rlSrc, kCoreReg).lowReg;
- int signMask = allocTemp(cUnit);
+ int signMask = dvmCompilerAllocTemp(cUnit);
loadConstant(cUnit, signMask, 0x7fffffff);
newLIR2(cUnit, kThumbAndRR, reg0, signMask);
- freeTemp(cUnit, signMask);
+ dvmCompilerFreeTemp(cUnit, signMask);
storeWordDisp(cUnit, rGLUE, offset, reg0);
//FIXME: rewrite this to not clobber
- clobberReg(cUnit, reg0);
+ dvmCompilerClobber(cUnit, reg0);
return true;
}
static bool genInlinedAbsDouble(CompilationUnit *cUnit, MIR *mir)
{
int offset = offsetof(InterpState, retval);
- RegLocation rlSrc = getSrcLocWide(cUnit, mir, 0, 1);
+ RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
RegLocation regSrc = loadValueWide(cUnit, rlSrc, kCoreReg);
int reglo = regSrc.lowReg;
int reghi = regSrc.highReg;
- int signMask = allocTemp(cUnit);
+ int signMask = dvmCompilerAllocTemp(cUnit);
loadConstant(cUnit, signMask, 0x7fffffff);
storeWordDisp(cUnit, rGLUE, offset, reglo);
newLIR2(cUnit, kThumbAndRR, reghi, signMask);
- freeTemp(cUnit, signMask);
+ dvmCompilerFreeTemp(cUnit, signMask);
storeWordDisp(cUnit, rGLUE, offset + 4, reghi);
//FIXME: rewrite this to not clobber
- clobberReg(cUnit, reghi);
+ dvmCompilerClobber(cUnit, reghi);
return true;
}
@@ -250,8 +250,8 @@
static bool genInlinedMinMaxInt(CompilationUnit *cUnit, MIR *mir, bool isMin)
{
int offset = offsetof(InterpState, retval);
- RegLocation rlSrc1 = getSrcLoc(cUnit, mir, 0);
- RegLocation rlSrc2 = getSrcLoc(cUnit, mir, 1);
+ RegLocation rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 0);
+ RegLocation rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 1);
int reg0 = loadValue(cUnit, rlSrc1, kCoreReg).lowReg;
int reg1 = loadValue(cUnit, rlSrc2, kCoreReg).lowReg;
newLIR2(cUnit, kThumbCmpRR, reg0, reg1);
@@ -263,29 +263,29 @@
newLIR3(cUnit, kThumbStrRRI5, reg0, rGLUE, offset >> 2);
branch1->generic.target = (LIR *)target;
//FIXME: rewrite this to not clobber
- clobberReg(cUnit,reg0);
+ dvmCompilerClobber(cUnit,reg0);
return false;
}
static bool genInlinedAbsLong(CompilationUnit *cUnit, MIR *mir)
{
int offset = offsetof(InterpState, retval);
- RegLocation rlSrc = getSrcLocWide(cUnit, mir, 0, 1);
+ RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
RegLocation regSrc = loadValueWide(cUnit, rlSrc, kCoreReg);
int oplo = regSrc.lowReg;
int ophi = regSrc.highReg;
- int sign = allocTemp(cUnit);
+ int sign = dvmCompilerAllocTemp(cUnit);
/* abs(x) = y<=x>>31, (x+y)^y. Shorter in ARM/THUMB2, no skip in THUMB */
newLIR3(cUnit, kThumbAsrRRI5, sign, ophi, 31);
newLIR3(cUnit, kThumbAddRRR, oplo, oplo, sign);
newLIR2(cUnit, kThumbAdcRR, ophi, sign);
newLIR2(cUnit, kThumbEorRR, oplo, sign);
newLIR2(cUnit, kThumbEorRR, ophi, sign);
- freeTemp(cUnit, sign);
+ dvmCompilerFreeTemp(cUnit, sign);
storeWordDisp(cUnit, rGLUE, offset, oplo);
storeWordDisp(cUnit, rGLUE, offset + 4, ophi);
//FIXME: rewrite this to not clobber
- clobberReg(cUnit, oplo);
- clobberReg(cUnit, ophi);
+ dvmCompilerClobber(cUnit, oplo);
+ dvmCompilerClobber(cUnit, ophi);
return false;
}
diff --git a/vm/compiler/codegen/arm/Thumb/Ralloc.c b/vm/compiler/codegen/arm/Thumb/Ralloc.c
index e9dd9a5..6769972 100644
--- a/vm/compiler/codegen/arm/Thumb/Ralloc.c
+++ b/vm/compiler/codegen/arm/Thumb/Ralloc.c
@@ -32,13 +32,13 @@
int highReg;
int lowReg;
int res = 0;
- lowReg = allocTemp(cUnit);
- highReg = allocTemp(cUnit);
+ lowReg = dvmCompilerAllocTemp(cUnit);
+ highReg = dvmCompilerAllocTemp(cUnit);
res = (lowReg & 0xff) | ((highReg & 0xff) << 8);
return res;
}
int dvmCompilerAllocTypedTemp(CompilationUnit *cUnit, bool fpHint, int regClass)
{
- return allocTemp(cUnit);
+ return dvmCompilerAllocTemp(cUnit);
}
diff --git a/vm/compiler/codegen/arm/Thumb2/Factory.c b/vm/compiler/codegen/arm/Thumb2/Factory.c
index 433953e..0db2045 100644
--- a/vm/compiler/codegen/arm/Thumb2/Factory.c
+++ b/vm/compiler/codegen/arm/Thumb2/Factory.c
@@ -25,7 +25,7 @@
static int coreTemps[] = {r0, r1, r2, r3, r4PC, r7, r8, r9, r10, r11, r12};
static int corePreserved[] = {};
static int fpTemps[] = {fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
- fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31};
+ fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31};
static int fpPreserved[] = {};
static int encodeImmSingle(int value)
@@ -187,9 +187,9 @@
*/
static ArmLIR *loadConstant(CompilationUnit *cUnit, int rDest, int value)
{
- if (isTemp(cUnit, rDest)) {
- clobberReg(cUnit, rDest);
- markRegInUse(cUnit, rDest);
+ if (dvmCompilerIsTemp(cUnit, rDest)) {
+ dvmCompilerClobber(cUnit, rDest);
+ dvmcompilerMarkInUse(cUnit, rDest);
}
return loadConstantValue(cUnit, rDest, value);
}
@@ -530,10 +530,10 @@
if (modImm >= 0) {
res = newLIR2(cUnit, kThumb2CmpRI8, rSrc1, modImm);
} else {
- int rTmp = allocTemp(cUnit);
+ int rTmp = dvmCompilerAllocTemp(cUnit);
res = loadConstant(cUnit, rTmp, value);
opRegReg(cUnit, kOpCmp, rSrc1, rTmp);
- freeTemp(cUnit, rTmp);
+ dvmCompilerFreeTemp(cUnit, rTmp);
}
return res;
}
@@ -544,13 +544,13 @@
if (modImm >= 0) {
return newLIR3(cUnit, opCode, rDest, rSrc1, modImm);
} else {
- int rScratch = allocTemp(cUnit);
+ int rScratch = dvmCompilerAllocTemp(cUnit);
loadConstant(cUnit, rScratch, value);
if (EncodingMap[altOpCode].flags & IS_QUAD_OP)
res = newLIR4(cUnit, altOpCode, rDest, rSrc1, rScratch, 0);
else
res = newLIR3(cUnit, altOpCode, rDest, rSrc1, rScratch);
- freeTemp(cUnit, rScratch);
+ dvmCompilerFreeTemp(cUnit, rScratch);
return res;
}
}
@@ -677,7 +677,7 @@
switch (size) {
case kSingle:
- regPtr = allocTemp(cUnit);
+ regPtr = dvmCompilerAllocTemp(cUnit);
if (scale) {
newLIR4(cUnit, kThumb2AddRRR, regPtr, rBase, rIndex,
encodeShift(kArmLsl, scale));
@@ -741,7 +741,7 @@
switch (size) {
case kSingle:
- regPtr = allocTemp(cUnit);
+ regPtr = dvmCompilerAllocTemp(cUnit);
if (scale) {
newLIR4(cUnit, kThumb2AddRRR, regPtr, rBase, rIndex,
encodeShift(kArmLsl, scale));
@@ -887,10 +887,10 @@
if (shortForm) {
load = res = newLIR3(cUnit, opCode, rDest, rBase, encodedDisp);
} else {
- int regOffset = allocTemp(cUnit);
+ int regOffset = dvmCompilerAllocTemp(cUnit);
res = loadConstant(cUnit, regOffset, encodedDisp);
load = loadBaseIndexed(cUnit, rBase, regOffset, rDest, 0, size);
- freeTemp(cUnit, regOffset);
+ dvmCompilerFreeTemp(cUnit, regOffset);
}
if (rBase == rFP) {
@@ -912,8 +912,8 @@
}
static ArmLIR *loadBaseDispWide(CompilationUnit *cUnit, MIR *mir, int rBase,
- int displacement, int rDestLo, int rDestHi,
- int sReg)
+ int displacement, int rDestLo, int rDestHi,
+ int sReg)
{
return loadBaseDispBody(cUnit, mir, rBase, displacement, rDestLo, rDestHi,
kLong, sReg);
@@ -921,8 +921,8 @@
static ArmLIR *storeBaseDispBody(CompilationUnit *cUnit, int rBase,
- int displacement, int rSrc, int rSrcHi,
- OpSize size)
+ int displacement, int rSrc, int rSrcHi,
+ OpSize size)
{
ArmLIR *res, *store;
ArmOpCode opCode = kThumbBkpt;
@@ -1001,10 +1001,10 @@
if (shortForm) {
store = res = newLIR3(cUnit, opCode, rSrc, rBase, encodedDisp);
} else {
- int rScratch = allocTemp(cUnit);
+ int rScratch = dvmCompilerAllocTemp(cUnit);
res = loadConstant(cUnit, rScratch, encodedDisp);
store = storeBaseIndexed(cUnit, rBase, rScratch, rSrc, 0, size);
- freeTemp(cUnit, rScratch);
+ dvmCompilerFreeTemp(cUnit, rScratch);
}
if (rBase == rFP) {
@@ -1038,6 +1038,10 @@
} else {
res = newLIR2(cUnit, kThumb2Ldmia, rBase, rMask);
}
+#if defined(WITH_SELF_VERIFICATION)
+ if (cUnit->heapMemOp)
+ res->branchInsertSV = true;
+#endif
genBarrier(cUnit);
return res;
}
@@ -1051,6 +1055,10 @@
} else {
res = newLIR2(cUnit, kThumb2Stmia, rBase, rMask);
}
+#if defined(WITH_SELF_VERIFICATION)
+ if (cUnit->heapMemOp)
+ res->branchInsertSV = true;
+#endif
genBarrier(cUnit);
return res;
}
@@ -1071,9 +1079,9 @@
* satisfies.
*/
static ArmLIR *genRegImmCheck(CompilationUnit *cUnit,
- ArmConditionCode cond, int reg,
- int checkValue, int dOffset,
- ArmLIR *pcrLabel)
+ ArmConditionCode cond, int reg,
+ int checkValue, int dOffset,
+ ArmLIR *pcrLabel)
{
ArmLIR *branch;
int modImm;
@@ -1097,7 +1105,7 @@
} else if (modImm >= 0) {
newLIR2(cUnit, kThumb2CmpRI8, reg, modImm);
} else {
- int tReg = allocTemp(cUnit);
+ int tReg = dvmCompilerAllocTemp(cUnit);
loadConstant(cUnit, tReg, checkValue);
opRegReg(cUnit, kOpCmp, reg, tReg);
}
diff --git a/vm/compiler/codegen/arm/Thumb2/Gen.c b/vm/compiler/codegen/arm/Thumb2/Gen.c
index 1f947c2..071964a 100644
--- a/vm/compiler/codegen/arm/Thumb2/Gen.c
+++ b/vm/compiler/codegen/arm/Thumb2/Gen.c
@@ -27,17 +27,17 @@
{
RegLocation rlResult;
rlSrc = loadValue(cUnit, rlSrc, kFPReg);
- rlResult = evalLoc(cUnit, rlDest, kFPReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kFPReg, true);
newLIR2(cUnit, kThumb2Vnegs, rlResult.lowReg, rlSrc.lowReg);
storeValue(cUnit, rlDest, rlResult);
}
static void genNegDouble(CompilationUnit *cUnit, RegLocation rlDest,
- RegLocation rlSrc)
+ RegLocation rlSrc)
{
RegLocation rlResult;
rlSrc = loadValueWide(cUnit, rlSrc, kFPReg);
- rlResult = evalLoc(cUnit, rlDest, kFPReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kFPReg, true);
newLIR2(cUnit, kThumb2Vnegd, S2D(rlResult.lowReg, rlResult.highReg),
S2D(rlSrc.lowReg, rlSrc.highReg));
storeValueWide(cUnit, rlDest, rlResult);
@@ -52,9 +52,9 @@
RegLocation rlSrc1, RegLocation rlSrc2)
{
RegLocation rlResult;
- int resLo = allocTemp(cUnit);
- int resHi = allocTemp(cUnit);
- int tmp1 = allocTemp(cUnit);
+ int resLo = dvmCompilerAllocTemp(cUnit);
+ int resHi = dvmCompilerAllocTemp(cUnit);
+ int tmp1 = dvmCompilerAllocTemp(cUnit);
rlSrc1 = loadValueWide(cUnit, rlSrc1, kCoreReg);
rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg);
@@ -63,9 +63,9 @@
newLIR4(cUnit, kThumb2Umull, resLo, resHi, rlSrc2.lowReg, rlSrc1.lowReg);
newLIR4(cUnit, kThumb2Mla, tmp1, rlSrc1.lowReg, rlSrc2.highReg, tmp1);
newLIR4(cUnit, kThumb2AddRRR, resHi, tmp1, resHi, 0);
- freeTemp(cUnit, tmp1);
+ dvmCompilerFreeTemp(cUnit, tmp1);
- rlResult = getReturnLocWide(cUnit); // Just as a template, will patch
+ rlResult = dvmCompilerGetReturnWide(cUnit); // Just as a template, will patch
rlResult.lowReg = resLo;
rlResult.highReg = resHi;
storeValueWide(cUnit, rlDest, rlResult);
@@ -78,7 +78,7 @@
RegLocation rlResult;
rlSrc1 = loadValueWide(cUnit, rlSrc1, kCoreReg);
rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
opRegRegReg(cUnit, firstOp, rlResult.lowReg, rlSrc1.lowReg, rlSrc2.lowReg);
opRegRegReg(cUnit, secondOp, rlResult.highReg, rlSrc1.highReg,
rlSrc2.highReg);
@@ -102,10 +102,10 @@
pool->coreRegs = NULL;
pool->numFPRegs = 0;
pool->FPRegs = NULL;
- initPool(pool->coreTemps, coreTemps, pool->numCoreTemps);
- initPool(pool->FPTemps, fpTemps, pool->numFPTemps);
- initPool(pool->coreRegs, NULL, 0);
- initPool(pool->FPRegs, NULL, 0);
+ dvmCompilerInitPool(pool->coreTemps, coreTemps, pool->numCoreTemps);
+ dvmCompilerInitPool(pool->FPTemps, fpTemps, pool->numFPTemps);
+ dvmCompilerInitPool(pool->coreRegs, NULL, 0);
+ dvmCompilerInitPool(pool->FPRegs, NULL, 0);
pool->nullCheckedRegs =
dvmCompilerAllocBitVector(cUnit->numSSARegs, false);
}
@@ -155,11 +155,11 @@
{
ArmLIR *res;
int offset = offsetof(StackSaveArea, xtra.currentPc);
- int rDPC = allocTemp(cUnit);
+ int rDPC = dvmCompilerAllocTemp(cUnit);
res = loadConstant(cUnit, rDPC, (int) (cUnit->method->insns + mir->offset));
newLIR3(cUnit, kThumb2StrRRI8Predec, rDPC, rFP,
sizeof(StackSaveArea) - offset);
- freeTemp(cUnit, rDPC);
+ dvmCompilerFreeTemp(cUnit, rDPC);
return res;
}
@@ -192,15 +192,15 @@
*/
static void genMonitor(CompilationUnit *cUnit, MIR *mir)
{
- RegLocation rlSrc = getSrcLoc(cUnit, mir, 0);
+ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
bool enter = (mir->dalvikInsn.opCode == OP_MONITOR_ENTER);
ArmLIR *target;
ArmLIR *branch;
assert(LW_SHAPE_THIN == 0);
loadValueDirectFixed(cUnit, rlSrc, r1); // Get obj
- lockAllTemps(cUnit); // Prepare for explicit register usage
- freeTemp(cUnit, r4PC); // Free up r4 for general use
+ dvmCompilerLockAllTemps(cUnit); // Prepare for explicit register usage
+ dvmCompilerFreeTemp(cUnit, r4PC); // Free up r4 for general use
loadWordDisp(cUnit, rGLUE, offsetof(InterpState, self), r0); // Get self
genNullCheck(cUnit, rlSrc.sRegLow, r1, mir->offset, NULL);
loadWordDisp(cUnit, r0, offsetof(Thread, threadId), r3); // Get threadId
@@ -253,7 +253,7 @@
sizeof(StackSaveArea) -
offsetof(StackSaveArea, xtra.currentPc));
opReg(cUnit, kOpBlx, r7);
- clobberCallRegs(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
}
// Resume here
@@ -286,7 +286,7 @@
ArmLIR *target2;
rlSrc1 = loadValueWide(cUnit, rlSrc1, kCoreReg);
rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg);
- rlTemp.lowReg = allocTemp(cUnit);
+ rlTemp.lowReg = dvmCompilerAllocTemp(cUnit);
loadConstant(cUnit, rlTemp.lowReg, -1);
opRegReg(cUnit, kOpCmp, rlSrc1.highReg, rlSrc2.highReg);
ArmLIR *branch1 = opCondBranch(cUnit, kArmCondLt);
@@ -315,10 +315,10 @@
static bool genInlinedStringLength(CompilationUnit *cUnit, MIR *mir)
{
- RegLocation rlObj = getSrcLoc(cUnit, mir, 0);
+ RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 0);
RegLocation rlDest = inlinedTarget(cUnit, mir, false);
rlObj = loadValue(cUnit, rlObj, kCoreReg);
- RegLocation rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset, NULL);
loadWordDisp(cUnit, rlObj.lowReg, gDvm.offJavaLangString_count,
rlResult.lowReg);
@@ -329,25 +329,25 @@
static bool genInlinedStringCharAt(CompilationUnit *cUnit, MIR *mir)
{
int contents = offsetof(ArrayObject, contents);
- RegLocation rlObj = getSrcLoc(cUnit, mir, 0);
- RegLocation rlIdx = getSrcLoc(cUnit, mir, 1);
+ RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 0);
+ RegLocation rlIdx = dvmCompilerGetSrc(cUnit, mir, 1);
RegLocation rlDest = inlinedTarget(cUnit, mir, false);
RegLocation rlResult;
rlObj = loadValue(cUnit, rlObj, kCoreReg);
rlIdx = loadValue(cUnit, rlIdx, kCoreReg);
- int regMax = allocTemp(cUnit);
- int regOff = allocTemp(cUnit);
- int regPtr = allocTemp(cUnit);
+ int regMax = dvmCompilerAllocTemp(cUnit);
+ int regOff = dvmCompilerAllocTemp(cUnit);
+ int regPtr = dvmCompilerAllocTemp(cUnit);
ArmLIR *pcrLabel = genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg,
mir->offset, NULL);
loadWordDisp(cUnit, rlObj.lowReg, gDvm.offJavaLangString_count, regMax);
loadWordDisp(cUnit, rlObj.lowReg, gDvm.offJavaLangString_offset, regOff);
loadWordDisp(cUnit, rlObj.lowReg, gDvm.offJavaLangString_value, regPtr);
genBoundsCheck(cUnit, rlIdx.lowReg, regMax, mir->offset, pcrLabel);
- freeTemp(cUnit, regMax);
+ dvmCompilerFreeTemp(cUnit, regMax);
opRegImm(cUnit, kOpAdd, regPtr, contents);
opRegReg(cUnit, kOpAdd, regOff, rlIdx.lowReg);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
loadBaseIndexed(cUnit, regPtr, regOff, rlResult.lowReg, 1, kUnsignedHalf);
storeValue(cUnit, rlDest, rlResult);
return false;
@@ -355,11 +355,11 @@
static bool genInlinedAbsInt(CompilationUnit *cUnit, MIR *mir)
{
- RegLocation rlSrc = getSrcLoc(cUnit, mir, 0);
+ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
RegLocation rlDest = inlinedTarget(cUnit, mir, false);;
- RegLocation rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
- int signReg = allocTemp(cUnit);
+ RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
+ int signReg = dvmCompilerAllocTemp(cUnit);
/*
* abs(x) = y<=x>>31, (x+y)^y.
* Thumb2's IT block also yields 3 instructions, but imposes
@@ -374,10 +374,10 @@
static bool genInlinedAbsFloat(CompilationUnit *cUnit, MIR *mir)
{
- RegLocation rlSrc = getSrcLoc(cUnit, mir, 0);
+ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
RegLocation rlDest = inlinedTarget(cUnit, mir, true);
rlSrc = loadValue(cUnit, rlSrc, kFPReg);
- RegLocation rlResult = evalLoc(cUnit, rlDest, kFPReg, true);
+ RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kFPReg, true);
newLIR2(cUnit, kThumb2Vabss, rlResult.lowReg, rlSrc.lowReg);
storeValue(cUnit, rlDest, rlResult);
return true;
@@ -385,10 +385,10 @@
static bool genInlinedAbsDouble(CompilationUnit *cUnit, MIR *mir)
{
- RegLocation rlSrc = getSrcLocWide(cUnit, mir, 0, 1);
+ RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
RegLocation rlDest = inlinedTargetWide(cUnit, mir, true);
rlSrc = loadValueWide(cUnit, rlSrc, kFPReg);
- RegLocation rlResult = evalLoc(cUnit, rlDest, kFPReg, true);
+ RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kFPReg, true);
newLIR2(cUnit, kThumb2Vabsd, S2D(rlResult.lowReg, rlResult.highReg),
S2D(rlSrc.lowReg, rlSrc.highReg));
storeValueWide(cUnit, rlDest, rlResult);
@@ -397,12 +397,12 @@
static bool genInlinedMinMaxInt(CompilationUnit *cUnit, MIR *mir, bool isMin)
{
- RegLocation rlSrc1 = getSrcLoc(cUnit, mir, 0);
- RegLocation rlSrc2 = getSrcLoc(cUnit, mir, 1);
+ RegLocation rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 0);
+ RegLocation rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 1);
rlSrc1 = loadValue(cUnit, rlSrc1, kCoreReg);
rlSrc2 = loadValue(cUnit, rlSrc2, kCoreReg);
RegLocation rlDest = inlinedTarget(cUnit, mir, false);
- RegLocation rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
opRegReg(cUnit, kOpCmp, rlSrc1.lowReg, rlSrc2.lowReg);
genIT(cUnit, (isMin) ? kArmCondGt : kArmCondLt, "E");
opRegReg(cUnit, kOpMov, rlResult.lowReg, rlSrc2.lowReg);
@@ -414,11 +414,11 @@
static bool genInlinedAbsLong(CompilationUnit *cUnit, MIR *mir)
{
- RegLocation rlSrc = getSrcLocWide(cUnit, mir, 0, 1);
+ RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
RegLocation rlDest = inlinedTargetWide(cUnit, mir, false);
rlSrc = loadValueWide(cUnit, rlSrc, kCoreReg);
- RegLocation rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
- int signReg = allocTemp(cUnit);
+ RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
+ int signReg = dvmCompilerAllocTemp(cUnit);
/*
* abs(x) = y<=x>>31, (x+y)^y.
* Thumb2 IT block allows slightly shorter sequence,
diff --git a/vm/compiler/codegen/arm/Thumb2/Ralloc.c b/vm/compiler/codegen/arm/Thumb2/Ralloc.c
index 0e089a7..bfd7f3f 100644
--- a/vm/compiler/codegen/arm/Thumb2/Ralloc.c
+++ b/vm/compiler/codegen/arm/Thumb2/Ralloc.c
@@ -33,11 +33,11 @@
int lowReg;
int res = 0;
if (((regClass == kAnyReg) && fpHint) || (regClass == kFPReg)) {
- lowReg = allocTempDouble(cUnit);
+ lowReg = dvmCompilerAllocTempDouble(cUnit);
highReg = lowReg + 1;
} else {
- lowReg = allocTemp(cUnit);
- highReg = allocTemp(cUnit);
+ lowReg = dvmCompilerAllocTemp(cUnit);
+ highReg = dvmCompilerAllocTemp(cUnit);
}
res = (lowReg & 0xff) | ((highReg & 0xff) << 8);
return res;
@@ -47,6 +47,6 @@
int regClass)
{
if (((regClass == kAnyReg) && fpHint) || (regClass == kFPReg))
- return allocTempFloat(cUnit);
- return allocTemp(cUnit);
+ return dvmCompilerAllocTempFloat(cUnit);
+ return dvmCompilerAllocTemp(cUnit);
}
