Fix for double breakpoint (issue 4378296)
Breakpoints are given special handling in the interpreter. They
are first interpreted as a breakpoint (with notification to the
debugger), and then the actual instruction associated with the
breakpoint location is interpreted.
The bug here was that the "dvmCheckBefore()" handler was invoked
prior to both "interpretations" - rather than just the first.
Note that this defect appears only in the Arm mterp, the portable
interpreter and x86 mterp did the right thing.
Change-Id: Ied957edc0c248b5d4d94910beb7af6c03ffe885d
diff --git a/vm/mterp/armv5te/OP_BREAKPOINT.S b/vm/mterp/armv5te/OP_BREAKPOINT.S
index 662227c..b4ea333 100644
--- a/vm/mterp/armv5te/OP_BREAKPOINT.S
+++ b/vm/mterp/armv5te/OP_BREAKPOINT.S
@@ -9,6 +9,7 @@
mov r0, rPC
bl dvmGetOriginalOpcode @ (rPC)
FETCH(rINST, 0) @ reload OP_BREAKPOINT + rest of inst
+ ldr r1, [rSELF, #offThread_mainHandlerTable]
and rINST, #0xff00
orr rINST, rINST, r0
- GOTO_OPCODE(r0)
+ GOTO_OPCODE_BASE(r1, r0)
diff --git a/vm/mterp/out/InterpAsm-armv5te-vfp.S b/vm/mterp/out/InterpAsm-armv5te-vfp.S
index 77be638..d2880a4 100644
--- a/vm/mterp/out/InterpAsm-armv5te-vfp.S
+++ b/vm/mterp/out/InterpAsm-armv5te-vfp.S
@@ -7258,9 +7258,10 @@
mov r0, rPC
bl dvmGetOriginalOpcode @ (rPC)
FETCH(rINST, 0) @ reload OP_BREAKPOINT + rest of inst
+ ldr r1, [rSELF, #offThread_mainHandlerTable]
and rINST, #0xff00
orr rINST, rINST, r0
- GOTO_OPCODE(r0)
+ GOTO_OPCODE_BASE(r1, r0)
/* ------------------------------ */
.balign 64
diff --git a/vm/mterp/out/InterpAsm-armv5te.S b/vm/mterp/out/InterpAsm-armv5te.S
index b46c3ee..edb5086 100644
--- a/vm/mterp/out/InterpAsm-armv5te.S
+++ b/vm/mterp/out/InterpAsm-armv5te.S
@@ -7580,9 +7580,10 @@
mov r0, rPC
bl dvmGetOriginalOpcode @ (rPC)
FETCH(rINST, 0) @ reload OP_BREAKPOINT + rest of inst
+ ldr r1, [rSELF, #offThread_mainHandlerTable]
and rINST, #0xff00
orr rINST, rINST, r0
- GOTO_OPCODE(r0)
+ GOTO_OPCODE_BASE(r1, r0)
/* ------------------------------ */
.balign 64
diff --git a/vm/mterp/out/InterpAsm-armv7-a-neon.S b/vm/mterp/out/InterpAsm-armv7-a-neon.S
index 4694cf7..fa64024 100644
--- a/vm/mterp/out/InterpAsm-armv7-a-neon.S
+++ b/vm/mterp/out/InterpAsm-armv7-a-neon.S
@@ -7216,9 +7216,10 @@
mov r0, rPC
bl dvmGetOriginalOpcode @ (rPC)
FETCH(rINST, 0) @ reload OP_BREAKPOINT + rest of inst
+ ldr r1, [rSELF, #offThread_mainHandlerTable]
and rINST, #0xff00
orr rINST, rINST, r0
- GOTO_OPCODE(r0)
+ GOTO_OPCODE_BASE(r1, r0)
/* ------------------------------ */
.balign 64
diff --git a/vm/mterp/out/InterpAsm-armv7-a.S b/vm/mterp/out/InterpAsm-armv7-a.S
index 5a291f0..4f9b974 100644
--- a/vm/mterp/out/InterpAsm-armv7-a.S
+++ b/vm/mterp/out/InterpAsm-armv7-a.S
@@ -7216,9 +7216,10 @@
mov r0, rPC
bl dvmGetOriginalOpcode @ (rPC)
FETCH(rINST, 0) @ reload OP_BREAKPOINT + rest of inst
+ ldr r1, [rSELF, #offThread_mainHandlerTable]
and rINST, #0xff00
orr rINST, rINST, r0
- GOTO_OPCODE(r0)
+ GOTO_OPCODE_BASE(r1, r0)
/* ------------------------------ */
.balign 64
