hostsidetests/securitybulletin/securityPatch/CVE-2017-0333/local_poc.h - platform/cts - Git at Google

 #ifndef __LOCAL_POC_H__
 #define __LOCAL_POC_H__

 #define DRM_IOCTL_BASE 'd'
 #define DRM_IOW(nr, type) _IOW(DRM_IOCTL_BASE, nr, type)
 #define DRM_IOWR(nr, type) _IOWR(DRM_IOCTL_BASE, nr, type)

 #define DRM_COMMAND_BASE 0x40
 #define DRM_NOUVEAU_EVENT_NVIF 0x80000000

 /* reserved object handles when using deprecated object APIs - these
  * are here so that libdrm can allow interoperability with the new
  * object APIs
  */
 #define NOUVEAU_ABI16_CLIENT 0xffffffff
 #define NOUVEAU_ABI16_DEVICE 0xdddddddd
 #define NOUVEAU_ABI16_CHAN(n) (0xcccc0000 | (n))

 #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
 #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
 #define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
 #define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
 #define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4)

 #define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */
 #define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
 #define NOUVEAU_GEM_TILE_16BPP 0x00000001
 #define NOUVEAU_GEM_TILE_32BPP 0x00000002
 #define NOUVEAU_GEM_TILE_ZETA 0x00000004
 #define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008

 struct drm_nouveau_gem_info {
   uint32_t handle;
   uint32_t domain;
   uint64_t size;
   uint64_t offset;
   uint64_t map_handle;
   uint32_t tile_mode;
   uint32_t tile_flags;
 };

 struct drm_nouveau_gem_new {
   struct drm_nouveau_gem_info info;
   uint32_t channel_hint;
   uint32_t align;
 };

 struct drm_nouveau_gem_set_tiling {
   uint32_t handle;
   uint32_t tile_mode;
   uint32_t tile_flags;
 };

 #define NOUVEAU_GEM_MAX_BUFFERS 1024
 struct drm_nouveau_gem_pushbuf_bo_presumed {
   uint32_t valid;
   uint32_t domain;
   uint64_t offset;
 };

 struct drm_nouveau_gem_pushbuf_bo {
   uint64_t user_priv;
   uint32_t handle;
   uint32_t read_domains;
   uint32_t write_domains;
   uint32_t valid_domains;
   struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
 };

 #define NOUVEAU_GEM_RELOC_LOW (1 << 0)
 #define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
 #define NOUVEAU_GEM_RELOC_OR (1 << 2)
 #define NOUVEAU_GEM_MAX_RELOCS 1024
 struct drm_nouveau_gem_pushbuf_reloc {
   uint32_t reloc_bo_index;
   uint32_t reloc_bo_offset;
   uint32_t bo_index;
   uint32_t flags;
   uint32_t data;
   uint32_t vor;
   uint32_t tor;
 };

 #define NOUVEAU_GEM_MAX_PUSH 512
 struct drm_nouveau_gem_pushbuf_push {
   uint32_t bo_index;
   uint32_t pad;
   uint64_t offset;
   uint64_t length;
 };

 struct drm_nouveau_gem_pushbuf {
   uint32_t channel;
   uint32_t nr_buffers;
   uint64_t buffers;
   uint32_t nr_relocs;
   uint32_t nr_push;
   uint64_t relocs;
   uint64_t push;
   uint32_t suffix0;
   uint32_t suffix1;
   uint64_t vram_available;
   uint64_t gart_available;
 };

 #define NOUVEAU_GEM_PUSHBUF_2_FENCE_WAIT 0x00000001
 #define NOUVEAU_GEM_PUSHBUF_2_FENCE_EMIT 0x00000002
 struct drm_nouveau_gem_pushbuf_2 {
   uint32_t channel;
   uint32_t flags;
   uint32_t nr_push;
   uint32_t nr_buffers;
   int32_t fence; /* in/out, depends on flags */
   uint32_t pad;
   uint64_t push;    /* in raw hw format */
   uint64_t buffers; /* ptr to drm_nouveau_gem_pushbuf_bo */
   uint64_t vram_available;
   uint64_t gart_available;
 };

 #define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
 #define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
 struct drm_nouveau_gem_cpu_prep {
   uint32_t handle;
   uint32_t flags;
 };

 struct drm_nouveau_gem_cpu_fini {
   uint32_t handle;
 };

 struct drm_nouveau_gem_as_alloc {
   uint64_t pages;     /* in, page length */
   uint32_t page_size; /* in, byte page size */
 #define NOUVEAU_GEM_AS_SPARSE 0x1
   uint32_t flags;
   uint64_t align;   /* in, requested alignment in bytes */
   uint64_t address; /* in/out, non-zero for fixed address allocation */
 };

 struct drm_nouveau_gem_as_free {
   uint64_t address; /* in, byte address */
 };

 #define NOUVEAU_GEM_CHANNEL_FIFO_ERROR_IDLE_TIMEOUT 8
 #define NOUVEAU_GEM_CHANNEL_GR_ERROR_SW_NOTIFY 13
 #define NOUVEAU_GEM_CHANNEL_FIFO_ERROR_MMU_ERR_FLT 31
 #define NOUVEAU_GEM_CHANNEL_PBDMA_ERROR 32
 struct drm_nouveau_gem_set_error_notifier {
   uint32_t channel;
   uint32_t buffer;
   uint32_t offset; /* bytes, u32-aligned */
 };

 struct drm_nouveau_gem_map {
   uint32_t handle;
   uint32_t domain;
   uint64_t offset;
   uint64_t delta;
   uint64_t length;
   uint32_t tile_mode;
   uint32_t tile_flags;
 };

 struct drm_nouveau_gem_unmap {
   uint32_t handle;
   uint32_t pad;
   uint64_t offset;
   uint64_t delta;
   uint64_t length;
 };

 struct nvif_ioctl_v0 {
   __u8 version;
 #define NVIF_IOCTL_V0_OWNER_NVIF 0x00
 #define NVIF_IOCTL_V0_OWNER_ANY 0xff
   __u8 owner;
 #define NVIF_IOCTL_V0_NOP 0x00
 #define NVIF_IOCTL_V0_SCLASS 0x01
 #define NVIF_IOCTL_V0_NEW 0x02
 #define NVIF_IOCTL_V0_DEL 0x03
 #define NVIF_IOCTL_V0_MTHD 0x04
 #define NVIF_IOCTL_V0_RD 0x05
 #define NVIF_IOCTL_V0_WR 0x06
 #define NVIF_IOCTL_V0_MAP 0x07
 #define NVIF_IOCTL_V0_UNMAP 0x08
 #define NVIF_IOCTL_V0_NTFY_NEW 0x09
 #define NVIF_IOCTL_V0_NTFY_DEL 0x0a
 #define NVIF_IOCTL_V0_NTFY_GET 0x0b
 #define NVIF_IOCTL_V0_NTFY_PUT 0x0c
   __u8 type;
   __u8 path_nr;
 #define NVIF_IOCTL_V0_ROUTE_NVIF 0x00
 #define NVIF_IOCTL_V0_ROUTE_HIDDEN 0xff
   __u8 pad04[3];
   __u8 route;
   __u64 token;
   __u32 path[8]; /* in reverse */
   __u8 data[];   /* ioctl data (below) */
 };

 #define DRM_NOUVEAU_GETPARAM 0x00          /* deprecated */
 #define DRM_NOUVEAU_SETPARAM 0x01          /* deprecated */
 #define DRM_NOUVEAU_CHANNEL_ALLOC 0x02     /* deprecated */
 #define DRM_NOUVEAU_CHANNEL_FREE 0x03      /* deprecated */
 #define DRM_NOUVEAU_GROBJ_ALLOC 0x04       /* deprecated */
 #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */
 #define DRM_NOUVEAU_GPUOBJ_FREE 0x06       /* deprecated */
 #define DRM_NOUVEAU_NVIF 0x07
 #define DRM_NOUVEAU_GEM_NEW 0x40
 #define DRM_NOUVEAU_GEM_PUSHBUF 0x41
 #define DRM_NOUVEAU_GEM_CPU_PREP 0x42
 #define DRM_NOUVEAU_GEM_CPU_FINI 0x43
 #define DRM_NOUVEAU_GEM_INFO 0x44
 /*
  * range (0x50+DRM_COMMAND_BASE)..DRM_COMMAND_END is reserved for staging,
  * unstable ioctls
  */
 #define DRM_NOUVEAU_STAGING_IOCTL 0x50
 #define DRM_NOUVEAU_GEM_SET_TILING (DRM_NOUVEAU_STAGING_IOCTL + 0x0)
 #define DRM_NOUVEAU_GEM_PUSHBUF_2 (DRM_NOUVEAU_STAGING_IOCTL + 0x1)
 #define DRM_NOUVEAU_GEM_SET_INFO (DRM_NOUVEAU_STAGING_IOCTL + 0x2)
 #define DRM_NOUVEAU_GEM_AS_ALLOC (DRM_NOUVEAU_STAGING_IOCTL + 0x3)
 #define DRM_NOUVEAU_GEM_AS_FREE (DRM_NOUVEAU_STAGING_IOCTL + 0x4)
 #define DRM_NOUVEAU_GEM_SET_ERROR_NOTIFIER (DRM_NOUVEAU_STAGING_IOCTL + 0x5)
 #define DRM_NOUVEAU_GEM_MAP (DRM_NOUVEAU_STAGING_IOCTL + 0x6)
 #define DRM_NOUVEAU_GEM_UNMAP (DRM_NOUVEAU_STAGING_IOCTL + 0x7)

 #define DRM_IOCTL_NOUVEAU_GEM_NEW \
   DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
 #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF                  \
   DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, \
            struct drm_nouveau_gem_pushbuf)
 #define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP                 \
   DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, \
           struct drm_nouveau_gem_cpu_prep)
 #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI                 \
   DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, \
           struct drm_nouveau_gem_cpu_fini)
 #define DRM_IOCTL_NOUVEAU_GEM_INFO \
   DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
 #define DRM_IOCTL_NOUVEAU_GEM_SET_TILING                  \
   DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_SET_TILING, \
            struct drm_nouveau_gem_set_tiling)
 #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF_2                  \
   DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF_2, \
            struct drm_nouveau_gem_pushbuf_2)
 #define DRM_IOCTL_NOUVEAU_GEM_SET_INFO                  \
   DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_SET_INFO, \
            struct drm_nouveau_gem_info)
 #define DRM_IOCTL_NOUVEAU_GEM_AS_ALLOC                  \
   DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_AS_ALLOC, \
            struct drm_nouveau_gem_as_alloc)
 #define DRM_IOCTL_NOUVEAU_GEM_AS_FREE                  \
   DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_AS_FREE, \
            struct drm_nouveau_gem_as_free)
 #define DRM_IOCTL_NOUVEAU_GEM_SET_ERROR_NOTIFIER                  \
   DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_SET_ERROR_NOTIFIER, \
            struct drm_nouveau_gem_set_error_notifier)
 #define DRM_IOCTL_NOUVEAU_GEM_MAP \
   DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_MAP, struct drm_nouveau_gem_map)
 #define DRM_IOCTL_NOUVEAU_GEM_UNMAP                  \
   DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_UNMAP, \
            struct drm_nouveau_gem_unmap)

 #define DRM_IOCTL_NOUVEAU_NVIF \
   DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_NVIF, struct nvif_ioctl_v0)

 #endif
	#ifndef __LOCAL_POC_H__
	#define __LOCAL_POC_H__

	#define DRM_IOCTL_BASE 'd'
	#define DRM_IOW(nr, type) _IOW(DRM_IOCTL_BASE, nr, type)
	#define DRM_IOWR(nr, type) _IOWR(DRM_IOCTL_BASE, nr, type)

	#define DRM_COMMAND_BASE 0x40
	#define DRM_NOUVEAU_EVENT_NVIF 0x80000000

	/* reserved object handles when using deprecated object APIs - these
	* are here so that libdrm can allow interoperability with the new
	* object APIs
	*/
	#define NOUVEAU_ABI16_CLIENT 0xffffffff
	#define NOUVEAU_ABI16_DEVICE 0xdddddddd
	#define NOUVEAU_ABI16_CHAN(n) (0xcccc0000 \| (n))

	#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
	#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
	#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
	#define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
	#define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4)

	#define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */
	#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
	#define NOUVEAU_GEM_TILE_16BPP 0x00000001
	#define NOUVEAU_GEM_TILE_32BPP 0x00000002
	#define NOUVEAU_GEM_TILE_ZETA 0x00000004
	#define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008

	struct drm_nouveau_gem_info {
	uint32_t handle;
	uint32_t domain;
	uint64_t size;
	uint64_t offset;
	uint64_t map_handle;
	uint32_t tile_mode;
	uint32_t tile_flags;
	};

	struct drm_nouveau_gem_new {
	struct drm_nouveau_gem_info info;
	uint32_t channel_hint;
	uint32_t align;
	};

	struct drm_nouveau_gem_set_tiling {
	uint32_t handle;
	uint32_t tile_mode;
	uint32_t tile_flags;
	};

	#define NOUVEAU_GEM_MAX_BUFFERS 1024
	struct drm_nouveau_gem_pushbuf_bo_presumed {
	uint32_t valid;
	uint32_t domain;
	uint64_t offset;
	};

	struct drm_nouveau_gem_pushbuf_bo {
	uint64_t user_priv;
	uint32_t handle;
	uint32_t read_domains;
	uint32_t write_domains;
	uint32_t valid_domains;
	struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
	};

	#define NOUVEAU_GEM_RELOC_LOW (1 << 0)
	#define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
	#define NOUVEAU_GEM_RELOC_OR (1 << 2)
	#define NOUVEAU_GEM_MAX_RELOCS 1024
	struct drm_nouveau_gem_pushbuf_reloc {
	uint32_t reloc_bo_index;
	uint32_t reloc_bo_offset;
	uint32_t bo_index;
	uint32_t flags;
	uint32_t data;
	uint32_t vor;
	uint32_t tor;
	};

	#define NOUVEAU_GEM_MAX_PUSH 512
	struct drm_nouveau_gem_pushbuf_push {
	uint32_t bo_index;
	uint32_t pad;
	uint64_t offset;
	uint64_t length;
	};

	struct drm_nouveau_gem_pushbuf {
	uint32_t channel;
	uint32_t nr_buffers;
	uint64_t buffers;
	uint32_t nr_relocs;
	uint32_t nr_push;
	uint64_t relocs;
	uint64_t push;
	uint32_t suffix0;
	uint32_t suffix1;
	uint64_t vram_available;
	uint64_t gart_available;
	};

	#define NOUVEAU_GEM_PUSHBUF_2_FENCE_WAIT 0x00000001
	#define NOUVEAU_GEM_PUSHBUF_2_FENCE_EMIT 0x00000002
	struct drm_nouveau_gem_pushbuf_2 {
	uint32_t channel;
	uint32_t flags;
	uint32_t nr_push;
	uint32_t nr_buffers;
	int32_t fence; /* in/out, depends on flags */
	uint32_t pad;
	uint64_t push; /* in raw hw format */
	uint64_t buffers; /* ptr to drm_nouveau_gem_pushbuf_bo */
	uint64_t vram_available;
	uint64_t gart_available;
	};

	#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
	#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
	struct drm_nouveau_gem_cpu_prep {
	uint32_t handle;
	uint32_t flags;
	};

	struct drm_nouveau_gem_cpu_fini {
	uint32_t handle;
	};

	struct drm_nouveau_gem_as_alloc {
	uint64_t pages; /* in, page length */
	uint32_t page_size; /* in, byte page size */
	#define NOUVEAU_GEM_AS_SPARSE 0x1
	uint32_t flags;
	uint64_t align; /* in, requested alignment in bytes */
	uint64_t address; /* in/out, non-zero for fixed address allocation */
	};

	struct drm_nouveau_gem_as_free {
	uint64_t address; /* in, byte address */
	};

	#define NOUVEAU_GEM_CHANNEL_FIFO_ERROR_IDLE_TIMEOUT 8
	#define NOUVEAU_GEM_CHANNEL_GR_ERROR_SW_NOTIFY 13
	#define NOUVEAU_GEM_CHANNEL_FIFO_ERROR_MMU_ERR_FLT 31
	#define NOUVEAU_GEM_CHANNEL_PBDMA_ERROR 32
	struct drm_nouveau_gem_set_error_notifier {
	uint32_t channel;
	uint32_t buffer;
	uint32_t offset; /* bytes, u32-aligned */
	};

	struct drm_nouveau_gem_map {
	uint32_t handle;
	uint32_t domain;
	uint64_t offset;
	uint64_t delta;
	uint64_t length;
	uint32_t tile_mode;
	uint32_t tile_flags;
	};

	struct drm_nouveau_gem_unmap {
	uint32_t handle;
	uint32_t pad;
	uint64_t offset;
	uint64_t delta;
	uint64_t length;
	};

	struct nvif_ioctl_v0 {
	__u8 version;
	#define NVIF_IOCTL_V0_OWNER_NVIF 0x00
	#define NVIF_IOCTL_V0_OWNER_ANY 0xff
	__u8 owner;
	#define NVIF_IOCTL_V0_NOP 0x00
	#define NVIF_IOCTL_V0_SCLASS 0x01
	#define NVIF_IOCTL_V0_NEW 0x02
	#define NVIF_IOCTL_V0_DEL 0x03
	#define NVIF_IOCTL_V0_MTHD 0x04
	#define NVIF_IOCTL_V0_RD 0x05
	#define NVIF_IOCTL_V0_WR 0x06
	#define NVIF_IOCTL_V0_MAP 0x07
	#define NVIF_IOCTL_V0_UNMAP 0x08
	#define NVIF_IOCTL_V0_NTFY_NEW 0x09
	#define NVIF_IOCTL_V0_NTFY_DEL 0x0a
	#define NVIF_IOCTL_V0_NTFY_GET 0x0b
	#define NVIF_IOCTL_V0_NTFY_PUT 0x0c
	__u8 type;
	__u8 path_nr;
	#define NVIF_IOCTL_V0_ROUTE_NVIF 0x00
	#define NVIF_IOCTL_V0_ROUTE_HIDDEN 0xff
	__u8 pad04[3];
	__u8 route;
	__u64 token;
	__u32 path[8]; /* in reverse */
	__u8 data[]; /* ioctl data (below) */
	};

	#define DRM_NOUVEAU_GETPARAM 0x00 /* deprecated */
	#define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */
	#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 /* deprecated */
	#define DRM_NOUVEAU_CHANNEL_FREE 0x03 /* deprecated */
	#define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */
	#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */
	#define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */
	#define DRM_NOUVEAU_NVIF 0x07
	#define DRM_NOUVEAU_GEM_NEW 0x40
	#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
	#define DRM_NOUVEAU_GEM_CPU_PREP 0x42
	#define DRM_NOUVEAU_GEM_CPU_FINI 0x43
	#define DRM_NOUVEAU_GEM_INFO 0x44
	/*
	* range (0x50+DRM_COMMAND_BASE)..DRM_COMMAND_END is reserved for staging,
	* unstable ioctls
	*/
	#define DRM_NOUVEAU_STAGING_IOCTL 0x50
	#define DRM_NOUVEAU_GEM_SET_TILING (DRM_NOUVEAU_STAGING_IOCTL + 0x0)
	#define DRM_NOUVEAU_GEM_PUSHBUF_2 (DRM_NOUVEAU_STAGING_IOCTL + 0x1)
	#define DRM_NOUVEAU_GEM_SET_INFO (DRM_NOUVEAU_STAGING_IOCTL + 0x2)
	#define DRM_NOUVEAU_GEM_AS_ALLOC (DRM_NOUVEAU_STAGING_IOCTL + 0x3)
	#define DRM_NOUVEAU_GEM_AS_FREE (DRM_NOUVEAU_STAGING_IOCTL + 0x4)
	#define DRM_NOUVEAU_GEM_SET_ERROR_NOTIFIER (DRM_NOUVEAU_STAGING_IOCTL + 0x5)
	#define DRM_NOUVEAU_GEM_MAP (DRM_NOUVEAU_STAGING_IOCTL + 0x6)
	#define DRM_NOUVEAU_GEM_UNMAP (DRM_NOUVEAU_STAGING_IOCTL + 0x7)

	#define DRM_IOCTL_NOUVEAU_GEM_NEW \
	DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
	#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF \
	DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, \
	struct drm_nouveau_gem_pushbuf)
	#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP \
	DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, \
	struct drm_nouveau_gem_cpu_prep)
	#define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI \
	DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, \
	struct drm_nouveau_gem_cpu_fini)
	#define DRM_IOCTL_NOUVEAU_GEM_INFO \
	DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
	#define DRM_IOCTL_NOUVEAU_GEM_SET_TILING \
	DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_SET_TILING, \
	struct drm_nouveau_gem_set_tiling)
	#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF_2 \
	DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF_2, \
	struct drm_nouveau_gem_pushbuf_2)
	#define DRM_IOCTL_NOUVEAU_GEM_SET_INFO \
	DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_SET_INFO, \
	struct drm_nouveau_gem_info)
	#define DRM_IOCTL_NOUVEAU_GEM_AS_ALLOC \
	DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_AS_ALLOC, \
	struct drm_nouveau_gem_as_alloc)
	#define DRM_IOCTL_NOUVEAU_GEM_AS_FREE \
	DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_AS_FREE, \
	struct drm_nouveau_gem_as_free)
	#define DRM_IOCTL_NOUVEAU_GEM_SET_ERROR_NOTIFIER \
	DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_SET_ERROR_NOTIFIER, \
	struct drm_nouveau_gem_set_error_notifier)
	#define DRM_IOCTL_NOUVEAU_GEM_MAP \
	DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_MAP, struct drm_nouveau_gem_map)
	#define DRM_IOCTL_NOUVEAU_GEM_UNMAP \
	DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_UNMAP, \
	struct drm_nouveau_gem_unmap)

	#define DRM_IOCTL_NOUVEAU_NVIF \
	DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_NVIF, struct nvif_ioctl_v0)

	#endif