| /** |
| * Copyright (C) 2018 The Android Open Source Project |
| * |
| * Licensed under the Apache License, Version 2.0 (the "License"); |
| * you may not use this file except in compliance with the License. |
| * You may obtain a copy of the License at |
| * |
| * http://www.apache.org/licenses/LICENSE-2.0 |
| * |
| * Unless required by applicable law or agreed to in writing, software |
| * distributed under the License is distributed on an "AS IS" BASIS, |
| * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| * See the License for the specific language governing permissions vand |
| * limitations under the License. |
| */ |
| #ifndef DRM_ENVIROMENT_H |
| #include <stdint.h> |
| #include <unistd.h> |
| |
| enum drm_map_type { |
| _DRM_FRAME_BUFFER = 0, |
| _DRM_REGISTERS = 1, |
| _DRM_SHM = 2, |
| _DRM_AGP = 3, |
| _DRM_SCATTER_GATHER = 4, |
| _DRM_CONSISTENT = 5, |
| }; |
| |
| enum drm_map_flags { |
| _DRM_RESTRICTED = 0x01, |
| _DRM_READ_ONLY = 0x02, |
| _DRM_LOCKED = 0x04, |
| _DRM_KERNEL = 0x08, |
| _DRM_WRITE_COMBINING = 0x10, |
| _DRM_CONTAINS_LOCK = 0x20, |
| _DRM_REMOVABLE = 0x40, |
| _DRM_DRIVER = 0x80 |
| }; |
| |
| enum host1x_class { |
| HOST1X_CLASS_HOST1X = 0x1, |
| HOST1X_CLASS_NVENC = 0x21, |
| HOST1X_CLASS_VI = 0x30, |
| HOST1X_CLASS_ISPA = 0x32, |
| HOST1X_CLASS_ISPB = 0x34, |
| HOST1X_CLASS_GR2D = 0x51, |
| HOST1X_CLASS_GR2D_SB = 0x52, |
| HOST1X_CLASS_VIC = 0x5D, |
| HOST1X_CLASS_GR3D = 0x60, |
| HOST1X_CLASS_NVJPG = 0xC0, |
| HOST1X_CLASS_NVDEC = 0xF0, |
| }; |
| |
| struct drm_map { |
| unsigned long offset; |
| unsigned long size; |
| enum drm_map_type type; |
| enum drm_map_flags flags; |
| void* handle; |
| int mtrr; |
| }; |
| |
| struct drm_version { |
| int version_major; |
| int version_minor; |
| int version_patchlevel; |
| size_t name_len; |
| char* name; |
| size_t date_len; |
| char* date; |
| size_t desc_len; |
| char* desc; |
| }; |
| |
| struct drm_buf_desc { |
| int count; |
| int size; |
| int low_mark; |
| int high_mark; |
| enum { |
| _DRM_PAGE_ALIGN = 0x01, |
| _DRM_AGP_BUFFER = 0x02, |
| _DRM_SG_BUFFER = 0x04, |
| _DRM_FB_BUFFER = 0x08, |
| _DRM_PCI_BUFFER_RO = 0x10 |
| } flags; |
| unsigned long agp_start; |
| }; |
| |
| struct drm_buf_info { |
| int count; |
| struct drm_buf_desc* list; |
| }; |
| |
| struct drm_buf_free { |
| int count; |
| int* list; |
| }; |
| |
| struct drm_nouveau_gem_info { |
| uint32_t handle; |
| uint32_t domain; |
| uint64_t size; |
| uint64_t offset; |
| uint64_t map_handle; |
| uint32_t tile_mode; |
| uint32_t tile_flags; |
| }; |
| |
| struct drm_nouveau_gem_map { |
| uint32_t handle; |
| uint32_t domain; |
| uint64_t offset; |
| uint64_t delta; |
| uint64_t length; |
| uint32_t tile_mode; |
| uint32_t tile_flags; |
| }; |
| |
| struct drm_nouveau_gem_unmap { |
| uint32_t handle; |
| uint32_t pad; |
| uint64_t offset; |
| uint64_t delta; |
| uint64_t length; |
| }; |
| |
| struct drm_nouveau_gem_new { |
| struct drm_nouveau_gem_info info; |
| uint32_t channel_hint; |
| uint32_t align; |
| }; |
| |
| struct drm_nouveau_gem_pushbuf { |
| uint32_t channel; |
| uint32_t nr_buffers; |
| uint64_t buffers; |
| uint32_t nr_relocs; |
| uint32_t nr_push; |
| uint64_t relocs; |
| uint64_t push; |
| uint32_t suffix0; |
| uint32_t suffix1; |
| uint64_t vram_available; |
| uint64_t gart_available; |
| }; |
| |
| struct drm_nouveau_gem_pushbuf_bo_presumed { |
| uint32_t valid; |
| uint32_t domain; |
| uint64_t offset; |
| }; |
| struct drm_nouveau_gem_pushbuf_bo { |
| uint64_t user_priv; |
| uint32_t handle; |
| uint32_t read_domains; |
| uint32_t write_domains; |
| uint32_t valid_domains; |
| struct drm_nouveau_gem_pushbuf_bo_presumed presumed; |
| }; |
| |
| struct drm_nouveau_channel_alloc { |
| uint32_t fb_ctxdma_handle; |
| uint32_t tt_ctxdma_handle; |
| int channel; |
| uint32_t pushbuf_domains; |
| uint32_t notifier_handle; |
| struct { |
| uint32_t handle; |
| uint32_t grclass; |
| } subchan[8]; |
| uint32_t nr_subchan; |
| }; |
| |
| #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) |
| #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) |
| #define NOUVEAU_GEM_DOMAIN_GART (1 << 2) |
| #define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3) |
| #define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4) |
| |
| #define DRM_COMMAND_BASE 0x40 |
| #define DRM_COMMAND_END 0xA0 |
| |
| #define DRM_NOUVEAU_GETPARAM 0x00 |
| #define DRM_NOUVEAU_SETPARAM 0x01 |
| #define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 |
| #define DRM_NOUVEAU_CHANNEL_FREE 0x03 |
| #define DRM_NOUVEAU_GROBJ_ALLOC 0x04 |
| #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 |
| #define DRM_NOUVEAU_GPUOBJ_FREE 0x06 |
| #define DRM_NOUVEAU_NVIF 0x07 |
| #define DRM_NOUVEAU_GEM_NEW 0x40 |
| #define DRM_NOUVEAU_GEM_PUSHBUF 0x41 |
| #define DRM_NOUVEAU_GEM_CPU_PREP 0x42 |
| #define DRM_NOUVEAU_GEM_CPU_FINI 0x43 |
| #define DRM_NOUVEAU_GEM_INFO 0x44 |
| #define DRM_NOUVEAU_STAGING_IOCTL 0x50 |
| #define DRM_NOUVEAU_GEM_SET_TILING (DRM_NOUVEAU_STAGING_IOCTL + 0x0) |
| #define DRM_NOUVEAU_GEM_PUSHBUF_2 (DRM_NOUVEAU_STAGING_IOCTL + 0x1) |
| #define DRM_NOUVEAU_GEM_SET_INFO (DRM_NOUVEAU_STAGING_IOCTL + 0x2) |
| #define DRM_NOUVEAU_GEM_AS_ALLOC (DRM_NOUVEAU_STAGING_IOCTL + 0x3) |
| #define DRM_NOUVEAU_GEM_AS_FREE (DRM_NOUVEAU_STAGING_IOCTL + 0x4) |
| #define DRM_NOUVEAU_GEM_SET_ERROR_NOTIFIER (DRM_NOUVEAU_STAGING_IOCTL + 0x5) |
| #define DRM_NOUVEAU_GEM_MAP (DRM_NOUVEAU_STAGING_IOCTL + 0x6) |
| #define DRM_NOUVEAU_GEM_UNMAP (DRM_NOUVEAU_STAGING_IOCTL + 0x7) |
| |
| #define DRM_IOCTL_BASE 'd' |
| #define DRM_IOR(nr, type) _IOR(DRM_IOCTL_BASE, nr, type) |
| #define DRM_IOW(nr, type) _IOW(DRM_IOCTL_BASE, nr, type) |
| #define DRM_IOWR(nr, type) _IOWR(DRM_IOCTL_BASE, nr, type) |
| #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map) |
| #define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version) |
| #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info) |
| #define DRM_IOCTL_FREE_BUFS DRM_IOW(0x1a, struct drm_buf_free) |
| |
| #define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc) |
| #define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new) |
| #define DRM_IOCTL_NOUVEAU_GEM_MAP DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_MAP, struct drm_nouveau_gem_map) |
| #define DRM_IOCTL_NOUVEAU_GEM_UNMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_UNMAP, struct drm_nouveau_gem_unmap) |
| #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf) |
| #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) |
| |
| #define DRM_TEGRA_GEM_CREATE_TILED (1 << 0) |
| #define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1) |
| |
| struct drm_tegra_gem_create { |
| __u64 size; |
| __u32 flags; |
| __u32 handle; |
| }; |
| |
| struct drm_tegra_gem_mmap { |
| __u32 handle; |
| __u32 offset; |
| }; |
| |
| struct drm_tegra_syncpt_read { |
| __u32 id; |
| __u32 value; |
| }; |
| |
| struct drm_tegra_syncpt_incr { |
| __u32 id; |
| __u32 pad; |
| }; |
| |
| struct drm_tegra_syncpt_wait { |
| __u32 id; |
| __u32 thresh; |
| __u32 timeout; |
| __u32 value; |
| }; |
| |
| #define DRM_TEGRA_NO_TIMEOUT (0xffffffff) |
| |
| struct drm_tegra_open_channel { |
| __u32 client; |
| __u32 pad; |
| __u64 context; |
| }; |
| |
| struct drm_tegra_close_channel { |
| __u64 context; |
| }; |
| |
| struct drm_tegra_get_syncpt { |
| __u64 context; |
| __u32 index; |
| __u32 id; |
| }; |
| |
| struct drm_tegra_get_syncpt_base { |
| __u64 context; |
| __u32 syncpt; |
| __u32 id; |
| }; |
| |
| struct drm_tegra_syncpt { |
| __u32 id; |
| __u32 incrs; |
| }; |
| |
| struct drm_tegra_cmdbuf { |
| __u32 handle; |
| __u32 offset; |
| __u32 words; |
| __u32 pad; |
| }; |
| |
| struct drm_tegra_reloc { |
| struct { |
| __u32 handle; |
| __u32 offset; |
| } cmdbuf; |
| struct { |
| __u32 handle; |
| __u32 offset; |
| } target; |
| __u32 shift; |
| __u32 pad; |
| }; |
| |
| struct drm_tegra_waitchk { |
| __u32 handle; |
| __u32 offset; |
| __u32 syncpt; |
| __u32 thresh; |
| }; |
| |
| struct drm_tegra_submit { |
| __u64 context; |
| __u32 num_syncpts; |
| __u32 num_cmdbufs; |
| __u32 num_relocs; |
| __u32 num_waitchks; |
| __u32 waitchk_mask; |
| __u32 timeout; |
| __u64 syncpts; |
| __u64 cmdbufs; |
| __u64 relocs; |
| __u64 waitchks; |
| __u32 fence; |
| __u32 reserved0; |
| __u64 fences; |
| |
| __u32 reserved1[2]; |
| }; |
| |
| #define DRM_TEGRA_GEM_TILING_MODE_PITCH 0 |
| #define DRM_TEGRA_GEM_TILING_MODE_TILED 1 |
| #define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2 |
| |
| struct drm_tegra_gem_set_tiling { |
| __u32 handle; |
| __u32 mode; |
| __u32 value; |
| __u32 pad; |
| }; |
| |
| struct drm_tegra_gem_get_tiling { |
| __u32 handle; |
| __u32 mode; |
| __u32 value; |
| __u32 pad; |
| }; |
| |
| #define DRM_TEGRA_GEM_BOTTOM_UP (1 << 0) |
| #define DRM_TEGRA_GEM_FLAGS (DRM_TEGRA_GEM_BOTTOM_UP) |
| |
| struct drm_tegra_gem_set_flags { |
| __u32 handle; |
| __u32 flags; |
| }; |
| |
| struct drm_tegra_gem_get_flags { |
| __u32 handle; |
| __u32 flags; |
| }; |
| |
| enum request_type { |
| DRM_TEGRA_REQ_TYPE_CLK_HZ = 0, |
| DRM_TEGRA_REQ_TYPE_BW_KBPS, |
| }; |
| |
| struct drm_tegra_get_clk_rate { |
| __u32 id; |
| __u32 type; |
| __u64 data; |
| }; |
| |
| struct drm_tegra_set_clk_rate { |
| __u32 id; |
| __u32 type; |
| __u64 data; |
| }; |
| |
| struct drm_tegra_constraint { |
| __u64 context; |
| __u32 index; |
| __u32 type; |
| __u32 rate; |
| __u32 pad; |
| }; |
| |
| struct drm_tegra_keepon { |
| __u64 context; |
| }; |
| |
| #define DRM_TEGRA_GEM_CREATE 0x00 |
| #define DRM_TEGRA_GEM_MMAP 0x01 |
| #define DRM_TEGRA_SYNCPT_READ 0x02 |
| #define DRM_TEGRA_SYNCPT_INCR 0x03 |
| #define DRM_TEGRA_SYNCPT_WAIT 0x04 |
| #define DRM_TEGRA_OPEN_CHANNEL 0x05 |
| #define DRM_TEGRA_CLOSE_CHANNEL 0x06 |
| #define DRM_TEGRA_GET_SYNCPT 0x07 |
| #define DRM_TEGRA_SUBMIT 0x08 |
| #define DRM_TEGRA_GET_SYNCPT_BASE 0x09 |
| #define DRM_TEGRA_GEM_SET_TILING 0x0a |
| #define DRM_TEGRA_GEM_GET_TILING 0x0b |
| #define DRM_TEGRA_GEM_SET_FLAGS 0x0c |
| #define DRM_TEGRA_GEM_GET_FLAGS 0x0d |
| #define DRM_TEGRA_GET_CLK_RATE 0x0e |
| #define DRM_TEGRA_SET_CLK_RATE 0x0f |
| #define DRM_TEGRA_START_KEEPON 0x10 |
| #define DRM_TEGRA_STOP_KEEPON 0x11 |
| #define DRM_TEGRA_GET_CLK_CONSTRAINT 0x12 |
| #define DRM_TEGRA_SET_CLK_CONSTRAINT 0x13 |
| |
| #define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create) |
| #define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap) |
| #define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read) |
| #define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr) |
| #define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait) |
| #define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel) |
| #define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel) |
| #define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt) |
| #define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit) |
| #define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base) |
| #define DRM_IOCTL_TEGRA_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_TILING, struct drm_tegra_gem_set_tiling) |
| #define DRM_IOCTL_TEGRA_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling) |
| #define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags) |
| #define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags) |
| #define DRM_IOCTL_TEGRA_GET_CLK_RATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_CLK_RATE, struct drm_tegra_get_clk_rate) |
| #define DRM_IOCTL_TEGRA_SET_CLK_RATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SET_CLK_RATE, struct drm_tegra_set_clk_rate) |
| #define DRM_IOCTL_TEGRA_START_KEEPON DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_START_KEEPON, struct drm_tegra_keepon) |
| #define DRM_IOCTL_TEGRA_STOP_KEEPON DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_STOP_KEEPON, struct drm_tegra_keepon) |
| #define DRM_IOCTL_TEGRA_GET_CLK_CONSTRAINT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_CLK_CONSTRAINT, struct drm_tegra_constraint) |
| #define DRM_IOCTL_TEGRA_SET_CLK_CONSTRAINT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SET_CLK_CONSTRAINT, struct drm_tegra_constraint) |
| |
| #endif |