[MIPSR6] Use C-coded string ops on mips32r6/mips64r6
The existing assembler code uses deprecated lwl/lwr/swl/swr ops.
Replacing those with misalignment-forgiving lw/sw ops may
involve careful performance tuning.
(cherry picked from commit bc5a3ec6df66d2456667ddf1d6dfaf623552169d)
Change-Id: I35167da27f2d406339b7f24b4a1fb270c87bc12e
diff --git a/libc/arch-mips/mips.mk b/libc/arch-mips/mips.mk
index cb76985..bf3b8ae 100644
--- a/libc/arch-mips/mips.mk
+++ b/libc/arch-mips/mips.mk
@@ -59,10 +59,21 @@
arch-mips/bionic/setjmp.S \
arch-mips/bionic/sigsetjmp.S \
arch-mips/bionic/syscall.S \
+
+ifndef ARCH_MIPS_REV6
+libc_bionic_src_files_mips += \
arch-mips/string/memcpy.S \
arch-mips/string/memset.S \
arch-mips/string/mips_strlen.c \
+else
+libc_bionic_src_files_mips += \
+ bionic/memcpy.cpp \
+ bionic/memset.c
+libc_common_src_files_mips += \
+ upstream-openbsd/lib/libc/string/strlen.c
+endif
+
libc_netbsd_src_files_mips := \
upstream-netbsd/common/lib/libc/hash/sha1/sha1.c \