[MIPS] Invalidate cached pid in vfork.
Bug: http://b/23008979
Change-Id: I43e0c7db42602441313af4607a992caa8c7d6221
diff --git a/libc/arch-mips/bionic/vfork.S b/libc/arch-mips/bionic/vfork.S
index 1849624..7ccf70b 100644
--- a/libc/arch-mips/bionic/vfork.S
+++ b/libc/arch-mips/bionic/vfork.S
@@ -37,6 +37,14 @@
.set noreorder
.cpload t9
+ // __get_tls()[TLS_SLOT_THREAD_ID]->cached_pid_ = 0
+ .set push
+ .set mips32r2
+ rdhwr v0, $29 // v0 = tls; kernel trap on mips32r1
+ .set pop
+ lw v0, REGSZ*1(v0) // v0 = v0[TLS_SLOT_THREAD_ID ie 1]
+ sw $0, REGSZ*2+4(v0) // v0->cached_pid_ = 0
+
li a0, (CLONE_VM | CLONE_VFORK | SIGCHLD)
li a1, 0
li a2, 0
diff --git a/libc/arch-mips64/bionic/vfork.S b/libc/arch-mips64/bionic/vfork.S
index d180a8c..e0a39ed 100644
--- a/libc/arch-mips64/bionic/vfork.S
+++ b/libc/arch-mips64/bionic/vfork.S
@@ -46,6 +46,12 @@
PTR_SUBU sp, FRAMESZ
#endif
SETUP_GP64(a5, vfork)
+
+ // __get_tls()[TLS_SLOT_THREAD_ID]->cached_pid_ = 0
+ rdhwr v0, $29 // v0 = tls
+ REG_L v0, REGSZ*1(v0) // v0 = v0[TLS_SLOT_THREAD_ID ie 1]
+ sw $0, REGSZ*2+4(v0) // v0->cached_pid_ = 0
+
LI a0, (CLONE_VM | CLONE_VFORK | SIGCHLD)
move a1, $0
move a2, $0
