Remove _flush_cache(2) for mips64.
Also remove declaration.
The only user is compiler-rt, and they can replace that call with one to
syscall(2). compiler-rt doesn't currently build on mips64 anyway.
Bug: 11156955
Change-Id: Ieae0ba49c8e7aa50253401fc1d7c2d17bc867d39
diff --git a/libc/SYSCALLS.TXT b/libc/SYSCALLS.TXT
index 38ae831..bfa13b7 100644
--- a/libc/SYSCALLS.TXT
+++ b/libc/SYSCALLS.TXT
@@ -315,7 +315,7 @@
int cacheflush:__ARM_NR_cacheflush(long start, long end, long flags) arm
# MIPS-specific
-int _flush_cache:cacheflush(char* addr, const int nbytes, const int op) mips,mips64
+int _flush_cache:cacheflush(char* addr, const int nbytes, const int op) mips
int __set_tls:set_thread_area(void*) mips,mips64
# x86-specific
diff --git a/libc/arch-mips64/syscalls/_flush_cache.S b/libc/arch-mips64/syscalls/_flush_cache.S
deleted file mode 100644
index 997ccec..0000000
--- a/libc/arch-mips64/syscalls/_flush_cache.S
+++ /dev/null
@@ -1,27 +0,0 @@
-/* Generated by gensyscalls.py. Do not edit. */
-
-#include <private/bionic_asm.h>
-
- .hidden __set_errno
-
-ENTRY(_flush_cache)
- .set push
- .set noreorder
- li v0, __NR_cacheflush
- syscall
- bnez a3, 1f
- move a0, v0
- j ra
- nop
-1:
- move t0, ra
- bal 2f
- nop
-2:
- .cpsetup ra, t1, 2b
- LA t9,__set_errno
- .cpreturn
- j t9
- move ra, t0
- .set pop
-END(_flush_cache)
diff --git a/libc/include/sys/cachectl.h b/libc/include/sys/cachectl.h
index 57e6ae7..a302ff8 100644
--- a/libc/include/sys/cachectl.h
+++ b/libc/include/sys/cachectl.h
@@ -31,6 +31,5 @@
#ifdef __mips__
#include <asm/cachectl.h>
extern int __cachectl (void *addr, __const int nbytes, __const int op);
-extern int _flush_cache (char *addr, __const int nbytes, __const int op);
#endif
#endif /* sys/cachectl.h */
