assert to DCHECK conversion
Also replaced static function defs with a STATIC macro to make normally
hidden functions visible to DCHECK's traceback listing). Additionally,
added some portions of the new type & size inference mechanism (but not
taking advantage of them yet).
Change-Id: Ib42a08777f28ab879d0df37617e1b77e3f09ba52
diff --git a/src/compiler/CompilerUtility.h b/src/compiler/CompilerUtility.h
index eaf712d..1d969e7 100644
--- a/src/compiler/CompilerUtility.h
+++ b/src/compiler/CompilerUtility.h
@@ -109,6 +109,6 @@
void oatDumpBlockBitVector(const GrowableList* blocks, char* msg,
const ArenaBitVector* bv, int length);
void oatGetBlockName(struct BasicBlock* bb, char* name);
-
+const char* oatGetShortyFromTargetIdx(CompilationUnit*, int);
#endif // ART_SRC_COMPILER_COMPILER_UTILITY_H_
diff --git a/src/compiler/Dalvik.h b/src/compiler/Dalvik.h
index d57b72e..21b4297 100644
--- a/src/compiler/Dalvik.h
+++ b/src/compiler/Dalvik.h
@@ -67,6 +67,13 @@
// From alloc/CardTable.h
#define GC_CARD_SHIFT 7
+// use to switch visibility on DCHECK tracebacks
+#if 1
+#define STATIC
+#else
+#define STATIC static
+#endif
+
#include "Compiler.h"
#endif
diff --git a/src/compiler/Dataflow.cc b/src/compiler/Dataflow.cc
index d4b5339..97a5e7b 100644
--- a/src/compiler/Dataflow.cc
+++ b/src/compiler/Dataflow.cc
@@ -1852,7 +1852,7 @@
}
/* Any register that is used before being defined is considered live-in */
-static inline void handleLiveInUse(ArenaBitVector* useV, ArenaBitVector* defV,
+STATIC inline void handleLiveInUse(ArenaBitVector* useV, ArenaBitVector* defV,
ArenaBitVector* liveInV, int dalvikRegId)
{
oatSetBit(useV, dalvikRegId);
@@ -1862,7 +1862,7 @@
}
/* Mark a reg as being defined */
-static inline void handleDef(ArenaBitVector* defV, int dalvikRegId)
+STATIC inline void handleDef(ArenaBitVector* defV, int dalvikRegId)
{
oatSetBit(defV, dalvikRegId);
}
@@ -1921,7 +1921,7 @@
}
/* Find out the latest SSA register for a given Dalvik register */
-static void handleSSAUse(CompilationUnit* cUnit, int* uses, int dalvikReg,
+STATIC void handleSSAUse(CompilationUnit* cUnit, int* uses, int dalvikReg,
int regIndex)
{
int encodedValue = cUnit->dalvikToSSAMap[dalvikReg];
@@ -1930,7 +1930,7 @@
}
/* Setup a new SSA register for a given Dalvik register */
-static void handleSSADef(CompilationUnit* cUnit, int* defs, int dalvikReg,
+STATIC void handleSSADef(CompilationUnit* cUnit, int* defs, int dalvikReg,
int regIndex)
{
int ssaReg = cUnit->numSSARegs++;
@@ -1947,7 +1947,7 @@
}
/* Look up new SSA names for format_35c instructions */
-static void dataFlowSSAFormat35C(CompilationUnit* cUnit, MIR* mir)
+STATIC void dataFlowSSAFormat35C(CompilationUnit* cUnit, MIR* mir)
{
DecodedInstruction *dInsn = &mir->dalvikInsn;
int numUses = dInsn->vA;
@@ -1955,6 +1955,8 @@
mir->ssaRep->numUses = numUses;
mir->ssaRep->uses = (int *)oatNew(sizeof(int) * numUses, false);
+ // NOTE: will be filled in during type & size inference pass
+ mir->ssaRep->fpUse = (bool *)oatNew(sizeof(bool) * numUses, false);
for (i = 0; i < numUses; i++) {
handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->arg[i], i);
@@ -1962,7 +1964,7 @@
}
/* Look up new SSA names for format_3rc instructions */
-static void dataFlowSSAFormat3RC(CompilationUnit* cUnit, MIR* mir)
+STATIC void dataFlowSSAFormat3RC(CompilationUnit* cUnit, MIR* mir)
{
DecodedInstruction *dInsn = &mir->dalvikInsn;
int numUses = dInsn->vA;
@@ -1970,6 +1972,8 @@
mir->ssaRep->numUses = numUses;
mir->ssaRep->uses = (int *)oatNew(sizeof(int) * numUses, false);
+ // NOTE: will be filled in during type & size inference pass
+ mir->ssaRep->fpUse = (bool *)oatNew(sizeof(bool) * numUses, false);
for (i = 0; i < numUses; i++) {
handleSSAUse(cUnit, mir->ssaRep->uses, dInsn->vC+i, i);
@@ -2119,7 +2123,7 @@
}
/* Setup a constant value for opcodes thare have the DF_SETS_CONST attribute */
-static void setConstant(CompilationUnit* cUnit, int ssaReg, int value)
+STATIC void setConstant(CompilationUnit* cUnit, int ssaReg, int value)
{
oatSetBit(cUnit->isConstantV, ssaReg);
cUnit->constantValues[ssaReg] = value;
@@ -2360,7 +2364,7 @@
}
}
-static bool nullCheckEliminationInit(struct CompilationUnit* cUnit,
+STATIC bool nullCheckEliminationInit(struct CompilationUnit* cUnit,
struct BasicBlock* bb)
{
if (bb->dataFlowInfo == NULL) return false;
@@ -2371,7 +2375,7 @@
}
/* Eliminate unnecessary null checks for a basic block. */
-static bool eliminateNullChecks( struct CompilationUnit* cUnit,
+STATIC bool eliminateNullChecks( struct CompilationUnit* cUnit,
struct BasicBlock* bb)
{
if (bb->dataFlowInfo == NULL) return false;
@@ -2395,7 +2399,7 @@
ArenaBitVectorIterator bvIterator;
oatBitVectorIteratorInit(bb->predecessors, &bvIterator);
int predBBIdx = oatBitVectorIteratorNext(&bvIterator);
- DCHECK(predBBIdx != -1);
+ DCHECK_NE(predBBIdx, -1);
BasicBlock* predBB = (BasicBlock*)oatGrowableListGetElement(
blockList, predBBIdx);
oatCopyBitVector(cUnit->tempSSARegisterV,
diff --git a/src/compiler/Frontend.cc b/src/compiler/Frontend.cc
index 9659903..a829f13 100644
--- a/src/compiler/Frontend.cc
+++ b/src/compiler/Frontend.cc
@@ -21,7 +21,7 @@
#include "object.h"
#include "runtime.h"
-static inline bool contentIsInsn(const u2* codePtr) {
+STATIC inline bool contentIsInsn(const u2* codePtr) {
u2 instr = *codePtr;
Opcode opcode = (Opcode)(instr & 0xff);
@@ -35,7 +35,7 @@
/*
* Parse an instruction, return the length of the instruction
*/
-static inline int parseInsn(const u2* codePtr, DecodedInstruction* decInsn,
+STATIC inline int parseInsn(const u2* codePtr, DecodedInstruction* decInsn,
bool printMe)
{
// Don't parse instruction data
@@ -57,7 +57,7 @@
#define UNKNOWN_TARGET 0xffffffff
-static inline bool isGoto(MIR* insn)
+STATIC inline bool isGoto(MIR* insn)
{
switch (insn->dalvikInsn.opcode) {
case OP_GOTO:
@@ -72,7 +72,7 @@
/*
* Identify unconditional branch instructions
*/
-static inline bool isUnconditionalBranch(MIR* insn)
+STATIC inline bool isUnconditionalBranch(MIR* insn)
{
switch (insn->dalvikInsn.opcode) {
case OP_RETURN_VOID:
@@ -86,7 +86,7 @@
}
/* Split an existing block from the specified code offset into two */
-static BasicBlock *splitBlock(CompilationUnit* cUnit,
+STATIC BasicBlock *splitBlock(CompilationUnit* cUnit,
unsigned int codeOffset,
BasicBlock* origBlock)
{
@@ -156,7 +156,7 @@
* Given a code offset, find out the block that starts with it. If the offset
* is in the middle of an existing block, split it into two.
*/
-static BasicBlock *findBlock(CompilationUnit* cUnit,
+STATIC BasicBlock *findBlock(CompilationUnit* cUnit,
unsigned int codeOffset,
bool split, bool create)
{
@@ -348,7 +348,7 @@
}
/* Verify if all the successor is connected with all the claimed predecessors */
-static bool verifyPredInfo(CompilationUnit* cUnit, BasicBlock* bb)
+STATIC bool verifyPredInfo(CompilationUnit* cUnit, BasicBlock* bb)
{
ArenaBitVectorIterator bvIterator;
@@ -392,7 +392,7 @@
}
/* Identify code range in try blocks and set up the empty catch blocks */
-static void processTryCatchBlocks(CompilationUnit* cUnit)
+STATIC void processTryCatchBlocks(CompilationUnit* cUnit)
{
const Method* method = cUnit->method;
art::ClassLinker* class_linker = art::Runtime::Current()->GetClassLinker();
@@ -435,7 +435,7 @@
}
/* Process instructions with the kInstrCanBranch flag */
-static void processCanBranch(CompilationUnit* cUnit, BasicBlock* curBlock,
+STATIC void processCanBranch(CompilationUnit* cUnit, BasicBlock* curBlock,
MIR* insn, int curOffset, int width, int flags,
const u2* codePtr, const u2* codeEnd)
{
@@ -508,7 +508,7 @@
}
/* Process instructions with the kInstrCanSwitch flag */
-static void processCanSwitch(CompilationUnit* cUnit, BasicBlock* curBlock,
+STATIC void processCanSwitch(CompilationUnit* cUnit, BasicBlock* curBlock,
MIR* insn, int curOffset, int width, int flags)
{
u2* switchData= (u2 *) (cUnit->insns + curOffset +
@@ -529,7 +529,7 @@
* Total size is (4+size*2) 16-bit code units.
*/
if (insn->dalvikInsn.opcode == OP_PACKED_SWITCH) {
- assert(switchData[0] == kPackedSwitchSignature);
+ DCHECK_EQ(switchData[0], kPackedSwitchSignature);
size = switchData[1];
firstKey = switchData[2] | (switchData[3] << 16);
targetTable = (int *) &switchData[4];
@@ -544,7 +544,7 @@
* Total size is (2+size*4) 16-bit code units.
*/
} else {
- assert(switchData[0] == kSparseSwitchSignature);
+ DCHECK_EQ(switchData[0], kSparseSwitchSignature);
size = switchData[1];
keyTable = (int *) &switchData[2];
targetTable = (int *) &switchData[2 + size*2];
@@ -589,7 +589,7 @@
}
/* Process instructions with the kInstrCanThrow flag */
-static void processCanThrow(CompilationUnit* cUnit, BasicBlock* curBlock,
+STATIC void processCanThrow(CompilationUnit* cUnit, BasicBlock* curBlock,
MIR* insn, int curOffset, int width, int flags,
ArenaBitVector* tryBlockAddr, const u2* codePtr,
const u2* codeEnd)
@@ -817,7 +817,7 @@
* instruction is not an unconditional branch, connect them through
* the fall-through link.
*/
- assert(curBlock->fallThrough == NULL ||
+ DCHECK(curBlock->fallThrough == NULL ||
curBlock->fallThrough == nextBlock ||
curBlock->fallThrough == exitBlock);
diff --git a/src/compiler/IntermediateRep.cc b/src/compiler/IntermediateRep.cc
index 23486ba..a7da037 100644
--- a/src/compiler/IntermediateRep.cc
+++ b/src/compiler/IntermediateRep.cc
@@ -32,7 +32,7 @@
void oatAppendMIR(BasicBlock* bb, MIR* mir)
{
if (bb->firstMIRInsn == NULL) {
- assert(bb->lastMIRInsn == NULL);
+ DCHECK(bb->lastMIRInsn == NULL);
bb->lastMIRInsn = bb->firstMIRInsn = mir;
mir->prev = mir->next = NULL;
} else {
@@ -47,7 +47,7 @@
void oatPrependMIR(BasicBlock* bb, MIR* mir)
{
if (bb->firstMIRInsn == NULL) {
- assert(bb->lastMIRInsn == NULL);
+ DCHECK(bb->lastMIRInsn == NULL);
bb->lastMIRInsn = bb->firstMIRInsn = mir;
mir->prev = mir->next = NULL;
} else {
@@ -81,7 +81,7 @@
void oatAppendLIR(CompilationUnit *cUnit, LIR* lir)
{
if (cUnit->firstLIRInsn == NULL) {
- assert(cUnit->lastLIRInsn == NULL);
+ DCHECK(cUnit->lastLIRInsn == NULL);
cUnit->lastLIRInsn = cUnit->firstLIRInsn = lir;
lir->prev = lir->next = NULL;
} else {
@@ -100,7 +100,7 @@
*/
void oatInsertLIRBefore(LIR* currentLIR, LIR* newLIR)
{
- assert(currentLIR->prev != NULL);
+ DCHECK(currentLIR->prev != NULL);
LIR *prevLIR = currentLIR->prev;
prevLIR->next = newLIR;
diff --git a/src/compiler/Ralloc.cc b/src/compiler/Ralloc.cc
index 11e18a7..7111f6d 100644
--- a/src/compiler/Ralloc.cc
+++ b/src/compiler/Ralloc.cc
@@ -19,7 +19,7 @@
#include "Dataflow.h"
#include "codegen/Ralloc.h"
-static bool setFp(CompilationUnit* cUnit, int index, bool isFP) {
+STATIC bool setFp(CompilationUnit* cUnit, int index, bool isFP) {
bool change = false;
if (isFP && !cUnit->regLocation[index].fp) {
cUnit->regLocation[index].fp = true;
@@ -33,7 +33,7 @@
* as it doesn't propagate. We're guaranteed at least one pass through
* the cfg.
*/
-static bool inferTypeAndSize(CompilationUnit* cUnit, BasicBlock* bb)
+STATIC bool inferTypeAndSize(CompilationUnit* cUnit, BasicBlock* bb)
{
MIR *mir;
bool changed = false; // Did anything change?
@@ -60,7 +60,51 @@
}
if (attrs & DF_UC_WIDE) {
cUnit->regLocation[ssaRep->uses[next]].wide = true;
+ next += 2;
}
+
+ // Special-case handling for format 35c/3rc invokes
+ Opcode opcode = mir->dalvikInsn.opcode;
+ int flags = (opcode >= kNumPackedOpcodes) ? 0 :
+ dexGetFlagsFromOpcode(opcode);
+ if ((flags & kInstrInvoke) &&
+ (attrs & (DF_FORMAT_35C | DF_FORMAT_3RC))) {
+ DCHECK_EQ(next, 0);
+ int target_idx = mir->dalvikInsn.vB;
+ const char* shorty =
+ oatGetShortyFromTargetIdx(cUnit, target_idx);
+ int numUses = mir->dalvikInsn.vA;
+ // If this is a non-static invoke, skip implicit "this"
+ if (((mir->dalvikInsn.opcode != OP_INVOKE_STATIC) &&
+ (mir->dalvikInsn.opcode != OP_INVOKE_STATIC_RANGE))) {
+ next++;
+ }
+ uint32_t cpos = 1;
+ if (strlen(shorty) > 1) {
+ for (int i = next; i < numUses;) {
+ DCHECK_LT(cpos, strlen(shorty));
+ switch(shorty[cpos++]) {
+ case 'D':
+ ssaRep->fpUse[i] = true;
+ ssaRep->fpUse[i+1] = true;
+ cUnit->regLocation[ssaRep->uses[i]].wide = true;
+ i++;
+ break;
+ case 'J':
+ cUnit->regLocation[ssaRep->uses[i]].wide = true;
+ i++;
+ break;
+ case 'F':
+ ssaRep->fpUse[i] = true;
+ break;
+ default:
+ break;
+ }
+ i++;
+ }
+ }
+ }
+
for (int i=0; ssaRep->fpUse && i< ssaRep->numUses; i++) {
if (ssaRep->fpUse[i])
changed |= setFp(cUnit, ssaRep->uses[i], true);
diff --git a/src/compiler/SSATransformation.cc b/src/compiler/SSATransformation.cc
index 1a488bb..35f43ac 100644
--- a/src/compiler/SSATransformation.cc
+++ b/src/compiler/SSATransformation.cc
@@ -18,7 +18,7 @@
#include "Dataflow.h"
/* Enter the node to the dfsOrder list then visit its successors */
-static void recordDFSPreOrder(CompilationUnit* cUnit, BasicBlock* block)
+STATIC void recordDFSPreOrder(CompilationUnit* cUnit, BasicBlock* block)
{
if (block->visited || block->hidden) return;
@@ -45,7 +45,7 @@
}
/* Sort the blocks by the Depth-First-Search pre-order */
-static void computeDFSOrder(CompilationUnit* cUnit)
+STATIC void computeDFSOrder(CompilationUnit* cUnit)
{
/* Initialize or reset the DFS order list */
if (cUnit->dfsOrder.elemList == NULL) {
@@ -67,7 +67,7 @@
* Mark block bit on the per-Dalvik register vector to denote that Dalvik
* register idx is defined in BasicBlock bb.
*/
-static bool fillDefBlockMatrix(CompilationUnit* cUnit, BasicBlock* bb)
+STATIC bool fillDefBlockMatrix(CompilationUnit* cUnit, BasicBlock* bb)
{
if (bb->dataFlowInfo == NULL) return false;
@@ -83,7 +83,7 @@
return true;
}
-static void computeDefBlockMatrix(CompilationUnit* cUnit)
+STATIC void computeDefBlockMatrix(CompilationUnit* cUnit)
{
int numRegisters = cUnit->numDalvikRegisters;
/* Allocate numDalvikRegisters bit vector pointers */
@@ -115,7 +115,7 @@
}
/* Compute the post-order traversal of the CFG */
-static void computeDomPostOrderTraversal(CompilationUnit* cUnit, BasicBlock* bb)
+STATIC void computeDomPostOrderTraversal(CompilationUnit* cUnit, BasicBlock* bb)
{
ArenaBitVectorIterator bvIterator;
oatBitVectorIteratorInit(bb->iDominated, &bvIterator);
@@ -139,7 +139,7 @@
}
}
-static void checkForDominanceFrontier(BasicBlock* domBB,
+STATIC void checkForDominanceFrontier(BasicBlock* domBB,
const BasicBlock* succBB)
{
/*
@@ -154,7 +154,7 @@
}
/* Worker function to compute the dominance frontier */
-static bool computeDominanceFrontier(CompilationUnit* cUnit, BasicBlock* bb)
+STATIC bool computeDominanceFrontier(CompilationUnit* cUnit, BasicBlock* bb)
{
GrowableList* blockList = &cUnit->blockList;
@@ -201,7 +201,7 @@
}
/* Worker function for initializing domination-related data structures */
-static bool initializeDominationInfo(CompilationUnit* cUnit, BasicBlock* bb)
+STATIC bool initializeDominationInfo(CompilationUnit* cUnit, BasicBlock* bb)
{
int numTotalBlocks = cUnit->blockList.numUsed;
@@ -224,7 +224,7 @@
}
/* Worker function to compute each block's dominators */
-static bool computeBlockDominators(CompilationUnit* cUnit, BasicBlock* bb)
+STATIC bool computeBlockDominators(CompilationUnit* cUnit, BasicBlock* bb)
{
GrowableList* blockList = &cUnit->blockList;
int numTotalBlocks = blockList->numUsed;
@@ -260,7 +260,7 @@
}
/* Worker function to compute the idom */
-static bool computeImmediateDominator(CompilationUnit* cUnit, BasicBlock* bb)
+STATIC bool computeImmediateDominator(CompilationUnit* cUnit, BasicBlock* bb)
{
GrowableList* blockList = &cUnit->blockList;
ArenaBitVector* tempBlockV = cUnit->tempBlockV;
@@ -274,14 +274,14 @@
oatBitVectorIteratorInit(tempBlockV, &bvIterator);
/* Should not see any dead block */
- assert(oatCountSetBits(tempBlockV) != 0);
+ DCHECK_NE(oatCountSetBits(tempBlockV), 0);
if (oatCountSetBits(tempBlockV) == 1) {
iDom = (BasicBlock* ) oatGrowableListGetElement(
blockList, oatBitVectorIteratorNext(&bvIterator));
bb->iDom = iDom;
} else {
int iDomIdx = oatBitVectorIteratorNext(&bvIterator);
- assert(iDomIdx != -1);
+ DCHECK_NE(iDomIdx, -1);
while (true) {
int nextDom = oatBitVectorIteratorNext(&bvIterator);
if (nextDom == -1) break;
@@ -303,7 +303,7 @@
}
/* Compute dominators, immediate dominator, and dominance fronter */
-static void computeDominators(CompilationUnit* cUnit)
+STATIC void computeDominators(CompilationUnit* cUnit)
{
int numReachableBlocks = cUnit->numReachableBlocks;
int numTotalBlocks = cUnit->blockList.numUsed;
@@ -343,7 +343,7 @@
}
computeDomPostOrderTraversal(cUnit, cUnit->entryBlock);
- assert(cUnit->domPostOrderTraversal.numUsed ==
+ DCHECK_EQ(cUnit->domPostOrderTraversal.numUsed,
(unsigned) cUnit->numReachableBlocks);
/* Now compute the dominance frontier for each block */
@@ -356,7 +356,7 @@
* Perform dest U= src1 ^ ~src2
* This is probably not general enough to be placed in BitVector.[ch].
*/
-static void computeSuccLiveIn(ArenaBitVector* dest,
+STATIC void computeSuccLiveIn(ArenaBitVector* dest,
const ArenaBitVector* src1,
const ArenaBitVector* src2)
{
@@ -378,7 +378,7 @@
* The calculated result is used for phi-node pruning - where we only need to
* insert a phi node if the variable is live-in to the block.
*/
-static bool computeBlockLiveIns(CompilationUnit* cUnit, BasicBlock* bb)
+STATIC bool computeBlockLiveIns(CompilationUnit* cUnit, BasicBlock* bb)
{
ArenaBitVector* tempDalvikRegisterV = cUnit->tempDalvikRegisterV;
@@ -415,7 +415,7 @@
}
/* Insert phi nodes to for each variable to the dominance frontiers */
-static void insertPhiNodes(CompilationUnit* cUnit)
+STATIC void insertPhiNodes(CompilationUnit* cUnit)
{
int dalvikReg;
const GrowableList* blockList = &cUnit->blockList;
@@ -497,7 +497,7 @@
* Worker function to insert phi-operands with latest SSA names from
* predecessor blocks
*/
-static bool insertPhiNodeOperands(CompilationUnit* cUnit, BasicBlock* bb)
+STATIC bool insertPhiNodeOperands(CompilationUnit* cUnit, BasicBlock* bb)
{
ArenaBitVector* ssaRegV = cUnit->tempSSARegisterV;
ArenaBitVectorIterator bvIterator;
@@ -552,7 +552,7 @@
return true;
}
-static void doDFSPreOrderSSARename(CompilationUnit* cUnit, BasicBlock* block)
+STATIC void doDFSPreOrderSSARename(CompilationUnit* cUnit, BasicBlock* block)
{
if (block->visited || block->hidden) return;
diff --git a/src/compiler/Utility.cc b/src/compiler/Utility.cc
index 7b99966..b9fe050 100644
--- a/src/compiler/Utility.cc
+++ b/src/compiler/Utility.cc
@@ -25,7 +25,7 @@
/* Allocate the initial memory block for arena-based allocation */
bool oatHeapInit(void)
{
- assert(arenaHead == NULL);
+ DCHECK(arenaHead == NULL);
arenaHead =
(ArenaMemBlock *) malloc(sizeof(ArenaMemBlock) + ARENA_DEFAULT_SIZE);
if (arenaHead == NULL) {
@@ -106,7 +106,7 @@
}
/* Expand the capacity of a growable list */
-static void expandGrowableList(GrowableList* gList)
+STATIC void expandGrowableList(GrowableList* gList)
{
int newLength = gList->numAllocated;
if (newLength < 128) {
@@ -124,7 +124,7 @@
/* Insert a new element into the growable list */
void oatInsertGrowableList(GrowableList* gList, intptr_t elem)
{
- assert(gList->numAllocated != 0);
+ DCHECK(gList->numAllocated != 0);
if (gList->numUsed == gList->numAllocated) {
expandGrowableList(gList);
}
@@ -141,14 +141,14 @@
intptr_t oatGrowableListIteratorNext(GrowableListIterator* iterator)
{
- assert(iterator->size == iterator->list->numUsed);
+ DCHECK_EQ(iterator->size, iterator->list->numUsed);
if (iterator->idx == iterator->size) return 0;
return iterator->list->elemList[iterator->idx++];
}
intptr_t oatGrowableListGetElement(const GrowableList* gList, size_t idx)
{
- assert(idx < gList->numUsed);
+ DCHECK_LT(idx, gList->numUsed);
return gList->elemList[idx];
}
@@ -212,7 +212,7 @@
ArenaBitVector* bv;
unsigned int count;
- assert(sizeof(bv->storage[0]) == 4); /* assuming 32-bit units */
+ DCHECK(sizeof(bv->storage[0]) == 4); /* assuming 32-bit units */
bv = (ArenaBitVector*) oatNew(sizeof(ArenaBitVector), false);
@@ -229,7 +229,7 @@
*/
bool oatIsBitSet(const ArenaBitVector* pBits, unsigned int num)
{
- assert(num < pBits->storageSize * sizeof(u4) * 8);
+ DCHECK_LT(num, pBits->storageSize * sizeof(u4) * 8);
unsigned int val = pBits->storage[num >> 5] & (1 << (num & 0x1f));
return (val != 0);
@@ -261,7 +261,7 @@
/* Round up to word boundaries for "num+1" bits */
unsigned int newSize = (num + 1 + 31) >> 5;
- assert(newSize > pBits->storageSize);
+ DCHECK_GT(newSize, pBits->storageSize);
u4 *newStorage = (u4*)oatNew(newSize * sizeof(u4), false);
memcpy(newStorage, pBits->storage, pBits->storageSize * sizeof(u4));
memset(&newStorage[pBits->storageSize], 0,
@@ -346,7 +346,7 @@
/*
* If the vector sizes don't match, log an error and abort.
*/
-static void checkSizes(const ArenaBitVector* bv1, const ArenaBitVector* bv2)
+STATIC void checkSizes(const ArenaBitVector* bv1, const ArenaBitVector* bv2)
{
if (bv1->storageSize != bv2->storageSize) {
LOG(FATAL) << "Mismatched vector sizes (" << bv1->storageSize <<
@@ -459,7 +459,7 @@
const ArenaBitVector* pBits = iterator->pBits;
u4 bitIndex = iterator->idx;
- assert(iterator->bitSize == pBits->storageSize * sizeof(u4) * 8);
+ DCHECK_EQ(iterator->bitSize, pBits->storageSize * sizeof(u4) * 8);
if (bitIndex >= iterator->bitSize) return -1;
for (; bitIndex < iterator->bitSize; bitIndex++) {
@@ -482,7 +482,7 @@
void oatSetInitialBits(ArenaBitVector* pBits, unsigned int numBits)
{
unsigned int idx;
- assert(((numBits + 31) >> 5) <= pBits->storageSize);
+ DCHECK_LE(((numBits + 31) >> 5), pBits->storageSize);
for (idx = 0; idx < (numBits >> 5); idx++) {
pBits->storage[idx] = -1;
}
@@ -512,3 +512,13 @@
break;
}
}
+
+const char* oatGetShortyFromTargetIdx(CompilationUnit *cUnit, int targetIdx)
+{
+ art::DexCache* dex_cache =
+ cUnit->method->GetDeclaringClass()->GetDexCache();
+ art::ClassLinker* class_linker = art::Runtime::Current()->GetClassLinker();
+ const art::DexFile& dex_file = class_linker->FindDexFile(dex_cache);
+ const art::DexFile::MethodId& methodId = dex_file.GetMethodId(targetIdx);
+ return dex_file.GetShorty(methodId.proto_idx_);
+}
diff --git a/src/compiler/codegen/CodegenFactory.cc b/src/compiler/codegen/CodegenFactory.cc
index dbd9141..108bc83 100644
--- a/src/compiler/codegen/CodegenFactory.cc
+++ b/src/compiler/codegen/CodegenFactory.cc
@@ -32,14 +32,14 @@
/* Load a word at base + displacement. Displacement must be word multiple */
-static TGT_LIR* loadWordDisp(CompilationUnit* cUnit, int rBase,
+STATIC TGT_LIR* loadWordDisp(CompilationUnit* cUnit, int rBase,
int displacement, int rDest)
{
return loadBaseDisp(cUnit, NULL, rBase, displacement, rDest, kWord,
INVALID_SREG);
}
-static TGT_LIR* storeWordDisp(CompilationUnit* cUnit, int rBase,
+STATIC TGT_LIR* storeWordDisp(CompilationUnit* cUnit, int rBase,
int displacement, int rSrc)
{
return storeBaseDisp(cUnit, rBase, displacement, rSrc, kWord);
@@ -50,14 +50,14 @@
* using this routine, as it doesn't perform any bookkeeping regarding
* register liveness. That is the responsibility of the caller.
*/
-static void loadValueDirect(CompilationUnit* cUnit, RegLocation rlSrc,
+STATIC void loadValueDirect(CompilationUnit* cUnit, RegLocation rlSrc,
int reg1)
{
rlSrc = oatUpdateLoc(cUnit, rlSrc);
if (rlSrc.location == kLocPhysReg) {
genRegCopy(cUnit, reg1, rlSrc.lowReg);
} else {
- assert(rlSrc.location == kLocDalvikFrame);
+ DCHECK(rlSrc.location == kLocDalvikFrame);
loadWordDisp(cUnit, rSP, rlSrc.spOffset, reg1);
}
}
@@ -67,7 +67,7 @@
* register. Should be used when loading to a fixed register (for example,
* loading arguments to an out of line call.
*/
-static void loadValueDirectFixed(CompilationUnit* cUnit, RegLocation rlSrc,
+STATIC void loadValueDirectFixed(CompilationUnit* cUnit, RegLocation rlSrc,
int reg1)
{
oatClobber(cUnit, reg1);
@@ -80,14 +80,14 @@
* using this routine, as it doesn't perform any bookkeeping regarding
* register liveness. That is the responsibility of the caller.
*/
-static void loadValueDirectWide(CompilationUnit* cUnit, RegLocation rlSrc,
+STATIC void loadValueDirectWide(CompilationUnit* cUnit, RegLocation rlSrc,
int regLo, int regHi)
{
rlSrc = oatUpdateLocWide(cUnit, rlSrc);
if (rlSrc.location == kLocPhysReg) {
genRegCopyWide(cUnit, regLo, regHi, rlSrc.lowReg, rlSrc.highReg);
} else {
- assert(rlSrc.location == kLocDalvikFrame);
+ DCHECK(rlSrc.location == kLocDalvikFrame);
loadBaseDispWide(cUnit, NULL, rSP, rlSrc.spOffset,
regLo, regHi, INVALID_SREG);
}
@@ -98,7 +98,7 @@
* registers. Should be used when loading to a fixed registers (for example,
* loading arguments to an out of line call.
*/
-static void loadValueDirectWideFixed(CompilationUnit* cUnit, RegLocation rlSrc,
+STATIC void loadValueDirectWideFixed(CompilationUnit* cUnit, RegLocation rlSrc,
int regLo, int regHi)
{
oatClobber(cUnit, regLo);
@@ -108,7 +108,7 @@
loadValueDirectWide(cUnit, rlSrc, regLo, regHi);
}
-static RegLocation loadValue(CompilationUnit* cUnit, RegLocation rlSrc,
+STATIC RegLocation loadValue(CompilationUnit* cUnit, RegLocation rlSrc,
RegisterClass opKind)
{
rlSrc = oatEvalLoc(cUnit, rlSrc, opKind, false);
@@ -120,13 +120,13 @@
return rlSrc;
}
-static void storeValue(CompilationUnit* cUnit, RegLocation rlDest,
+STATIC void storeValue(CompilationUnit* cUnit, RegLocation rlDest,
RegLocation rlSrc)
{
LIR* defStart;
LIR* defEnd;
- assert(!rlDest.wide);
- assert(!rlSrc.wide);
+ DCHECK(!rlDest.wide);
+ DCHECK(!rlSrc.wide);
rlSrc = oatUpdateLoc(cUnit, rlSrc);
rlDest = oatUpdateLoc(cUnit, rlDest);
if (rlSrc.location == kLocPhysReg) {
@@ -162,10 +162,10 @@
}
}
-static RegLocation loadValueWide(CompilationUnit* cUnit, RegLocation rlSrc,
+STATIC RegLocation loadValueWide(CompilationUnit* cUnit, RegLocation rlSrc,
RegisterClass opKind)
{
- assert(rlSrc.wide);
+ DCHECK(rlSrc.wide);
rlSrc = oatEvalLoc(cUnit, rlSrc, opKind, false);
if (rlSrc.location == kLocDalvikFrame) {
loadValueDirectWide(cUnit, rlSrc, rlSrc.lowReg, rlSrc.highReg);
@@ -177,7 +177,7 @@
return rlSrc;
}
-static void storeValueWide(CompilationUnit* cUnit, RegLocation rlDest,
+STATIC void storeValueWide(CompilationUnit* cUnit, RegLocation rlDest,
RegLocation rlSrc)
{
LIR* defStart;
@@ -186,9 +186,9 @@
LOG(WARNING) << "rlSrc.lowreg:" << rlSrc.lowReg << ", rlSrc.highReg:"
<< rlSrc.highReg;
}
- assert(FPREG(rlSrc.lowReg)==FPREG(rlSrc.highReg));
- assert(rlDest.wide);
- assert(rlSrc.wide);
+ DCHECK_EQ(FPREG(rlSrc.lowReg), FPREG(rlSrc.highReg));
+ DCHECK(rlDest.wide);
+ DCHECK(rlSrc.wide);
if (rlSrc.location == kLocPhysReg) {
if (oatIsLive(cUnit, rlSrc.lowReg) ||
oatIsLive(cUnit, rlSrc.highReg) ||
@@ -225,7 +225,7 @@
(oatLiveOut(cUnit, rlDest.sRegLow) ||
oatLiveOut(cUnit, oatSRegHi(rlDest.sRegLow)))) {
defStart = (LIR*)cUnit->lastLIRInsn;
- assert((oatS2VReg(cUnit, rlDest.sRegLow)+1) ==
+ DCHECK_EQ((oatS2VReg(cUnit, rlDest.sRegLow)+1),
oatS2VReg(cUnit, oatSRegHi(rlDest.sRegLow)));
storeBaseDispWide(cUnit, rSP, rlDest.spOffset,
rlDest.lowReg, rlDest.highReg);
diff --git a/src/compiler/codegen/Ralloc.h b/src/compiler/codegen/Ralloc.h
index ad19475..0c3fbca 100644
--- a/src/compiler/codegen/Ralloc.h
+++ b/src/compiler/codegen/Ralloc.h
@@ -31,7 +31,7 @@
* Must use a core register for data types narrower than word (due
* to possible unaligned load/store.
*/
-static inline RegisterClass oatRegClassBySize(OpSize size)
+STATIC inline RegisterClass oatRegClassBySize(OpSize size)
{
return (size == kUnsignedHalf ||
size == kSignedHalf ||
@@ -39,9 +39,9 @@
size == kSignedByte ) ? kCoreReg : kAnyReg;
}
-static inline int oatS2VReg(CompilationUnit* cUnit, int sReg)
+STATIC inline int oatS2VReg(CompilationUnit* cUnit, int sReg)
{
- assert(sReg != INVALID_SREG);
+ DCHECK_NE(sReg, INVALID_SREG);
return DECODE_REG(oatConvertSSARegToDalvik(cUnit, sReg));
}
@@ -55,20 +55,20 @@
* identified by the dataflow pass what it's new name is.
*/
-static inline int oatSRegHi(int lowSreg) {
+STATIC inline int oatSRegHi(int lowSreg) {
return (lowSreg == INVALID_SREG) ? INVALID_SREG : lowSreg + 1;
}
-static inline bool oatLiveOut(CompilationUnit* cUnit, int sReg)
+STATIC inline bool oatLiveOut(CompilationUnit* cUnit, int sReg)
{
//For now.
return true;
}
-static inline int oatSSASrc(MIR* mir, int num)
+STATIC inline int oatSSASrc(MIR* mir, int num)
{
- assert(mir->ssaRep->numUses > num);
+ DCHECK_GT(mir->ssaRep->numUses, num);
return mir->ssaRep->uses[num];
}
@@ -84,6 +84,9 @@
extern RegLocation oatUpdateLocWide(CompilationUnit* cUnit,
RegLocation loc);
+extern RegLocation oatUpdateRawLoc(CompilationUnit* cUnit,
+ RegLocation loc);
+
extern void oatMarkLive(CompilationUnit* cUnit, int reg, int sReg);
extern void oatMarkTemp(CompilationUnit* cUnit, int reg);
diff --git a/src/compiler/codegen/RallocUtil.cc b/src/compiler/codegen/RallocUtil.cc
index 6198b42..6875718 100644
--- a/src/compiler/codegen/RallocUtil.cc
+++ b/src/compiler/codegen/RallocUtil.cc
@@ -71,7 +71,7 @@
}
}
-static void dumpRegPool(RegisterInfo* p, int numRegs)
+STATIC void dumpRegPool(RegisterInfo* p, int numRegs)
{
int i;
LOG(INFO) << "================================================";
@@ -88,7 +88,7 @@
}
/* Get info for a reg. */
-static RegisterInfo* getRegInfo(CompilationUnit* cUnit, int reg)
+STATIC RegisterInfo* getRegInfo(CompilationUnit* cUnit, int reg)
{
int numRegs = cUnit->regPool->numCoreRegs;
RegisterInfo* p = cUnit->regPool->coreRegs;
@@ -113,7 +113,7 @@
{
RegisterInfo* info1 = getRegInfo(cUnit, reg1);
RegisterInfo* info2 = getRegInfo(cUnit, reg2);
- assert(info1 && info2 && info1->pair && info2->pair &&
+ DCHECK(info1 && info2 && info1->pair && info2->pair &&
(info1->partner == info2->reg) &&
(info2->partner == info1->reg));
if ((info1->live && info1->dirty) || (info2->live && info2->dirty)) {
@@ -147,7 +147,7 @@
}
/* return true if found reg to clobber */
-static bool clobberRegBody(CompilationUnit* cUnit, RegisterInfo* p,
+STATIC bool clobberRegBody(CompilationUnit* cUnit, RegisterInfo* p,
int numRegs, int reg)
{
int i;
@@ -187,7 +187,7 @@
}
}
-static void clobberSRegBody(RegisterInfo* p, int numRegs, int sReg)
+STATIC void clobberSRegBody(RegisterInfo* p, int numRegs, int sReg)
{
int i;
for (i=0; i< numRegs; i++) {
@@ -236,7 +236,7 @@
* even/odd allocation, but go ahead and allocate anything if not
* available. If nothing's available, return -1.
*/
-static int allocPreservedSingle(CompilationUnit* cUnit, int sReg, bool even)
+STATIC int allocPreservedSingle(CompilationUnit* cUnit, int sReg, bool even)
{
int res = -1;
RegisterInfo* FPRegs = cUnit->regPool->FPRegs;
@@ -266,7 +266,7 @@
* allocate if we can't meet the requirements for the pair of
* sReg<=sX[even] & (sReg+1)<= sX+1.
*/
-static int allocPreservedDouble(CompilationUnit* cUnit, int sReg)
+STATIC int allocPreservedDouble(CompilationUnit* cUnit, int sReg)
{
int res = -1; // Assume failure
if (cUnit->regLocation[sReg+1].fpLocation == kLocPhysReg) {
@@ -285,7 +285,7 @@
// OK - good to go.
res = p->reg;
p->inUse = true;
- assert((res & 1) == 0);
+ DCHECK_EQ((res & 1), 0);
cUnit->fpSpillMask |= (1 << (res & FP_REG_MASK));
cUnit->fpVmapTable.push_back(sReg);
cUnit->numSpills++;
@@ -345,7 +345,7 @@
return res;
}
-static int allocTempBody(CompilationUnit* cUnit, RegisterInfo* p, int numRegs,
+STATIC int allocTempBody(CompilationUnit* cUnit, RegisterInfo* p, int numRegs,
int* nextTemp, bool required)
{
int i;
@@ -403,8 +403,8 @@
oatClobber(cUnit, p[next+1].reg);
p[next].inUse = true;
p[next+1].inUse = true;
- assert((p[next].reg+1) == p[next+1].reg);
- assert((p[next].reg & 0x1) == 0);
+ DCHECK_EQ((p[next].reg+1), p[next+1].reg);
+ DCHECK_EQ((p[next].reg & 0x1), 0);
cUnit->regPool->nextFPReg += 2;
return p[next].reg;
}
@@ -420,8 +420,8 @@
oatClobber(cUnit, p[next+1].reg);
p[next].inUse = true;
p[next+1].inUse = true;
- assert((p[next].reg+1) == p[next+1].reg);
- assert((p[next].reg & 0x1) == 0);
+ DCHECK_EQ((p[next].reg+1), p[next+1].reg);
+ DCHECK_EQ((p[next].reg & 0x1), 0);
cUnit->regPool->nextFPReg += 2;
return p[next].reg;
}
@@ -453,7 +453,7 @@
&cUnit->regPool->nextFPReg, true);
}
-static RegisterInfo* allocLiveBody(RegisterInfo* p, int numRegs, int sReg)
+STATIC RegisterInfo* allocLiveBody(RegisterInfo* p, int numRegs, int sReg)
{
int i;
if (sReg == -1)
@@ -468,7 +468,7 @@
return NULL;
}
-static RegisterInfo* allocLive(CompilationUnit* cUnit, int sReg,
+STATIC RegisterInfo* allocLive(CompilationUnit* cUnit, int sReg,
int regClass)
{
RegisterInfo* res = NULL;
@@ -565,7 +565,7 @@
int i;
for (i=0; i< numRegs; i++) {
if (p[i].reg == reg) {
- assert(p[i].isTemp);
+ DCHECK(p[i].isTemp);
p[i].inUse = true;
p[i].live = false;
return;
@@ -575,7 +575,7 @@
numRegs = cUnit->regPool->numFPRegs;
for (i=0; i< numRegs; i++) {
if (p[i].reg == reg) {
- assert(p[i].isTemp);
+ DCHECK(p[i].isTemp);
p[i].inUse = true;
p[i].live = false;
return;
@@ -591,12 +591,12 @@
p->defEnd = NULL;
}
-static void nullifyRange(CompilationUnit* cUnit, LIR *start, LIR *finish,
+STATIC void nullifyRange(CompilationUnit* cUnit, LIR *start, LIR *finish,
int sReg1, int sReg2)
{
if (start && finish) {
LIR *p;
- assert(sReg1 == sReg2);
+ DCHECK_EQ(sReg1, sReg2);
for (p = start; ;p = p->next) {
((ArmLIR *)p)->flags.isNop = true;
if (p == finish)
@@ -613,9 +613,9 @@
extern void oatMarkDef(CompilationUnit* cUnit, RegLocation rl,
LIR *start, LIR *finish)
{
- assert(!rl.wide);
- assert(start && start->next);
- assert(finish);
+ DCHECK(!rl.wide);
+ DCHECK(start && start->next);
+ DCHECK(finish);
RegisterInfo* p = getRegInfo(cUnit, rl.lowReg);
p->defStart = start->next;
p->defEnd = finish;
@@ -629,9 +629,9 @@
extern void oatMarkDefWide(CompilationUnit* cUnit, RegLocation rl,
LIR *start, LIR *finish)
{
- assert(rl.wide);
- assert(start && start->next);
- assert(finish);
+ DCHECK(rl.wide);
+ DCHECK(start && start->next);
+ DCHECK(finish);
RegisterInfo* p = getRegInfo(cUnit, rl.lowReg);
oatResetDef(cUnit, rl.highReg); // Only track low of pair
p->defStart = start->next;
@@ -641,7 +641,7 @@
extern RegLocation oatWideToNarrow(CompilationUnit* cUnit,
RegLocation rl)
{
- assert(rl.wide);
+ DCHECK(rl.wide);
if (rl.location == kLocPhysReg) {
RegisterInfo* infoLo = getRegInfo(cUnit, rl.lowReg);
RegisterInfo* infoHi = getRegInfo(cUnit, rl.highReg);
@@ -662,10 +662,10 @@
extern void oatResetDefLoc(CompilationUnit* cUnit, RegLocation rl)
{
- assert(!rl.wide);
+ DCHECK(!rl.wide);
if (!(cUnit->disableOpt & (1 << kSuppressLoads))) {
RegisterInfo* p = getRegInfo(cUnit, rl.lowReg);
- assert(!p->pair);
+ DCHECK(!p->pair);
nullifyRange(cUnit, p->defStart, p->defEnd,
p->sReg, rl.sRegLow);
}
@@ -674,10 +674,10 @@
extern void oatResetDefLocWide(CompilationUnit* cUnit, RegLocation rl)
{
- assert(rl.wide);
+ DCHECK(rl.wide);
if (!(cUnit->disableOpt & (1 << kSuppressLoads))) {
RegisterInfo* p = getRegInfo(cUnit, rl.lowReg);
- assert(p->pair);
+ DCHECK(p->pair);
nullifyRange(cUnit, p->defStart, p->defEnd,
p->sReg, rl.sRegLow);
}
@@ -728,7 +728,7 @@
}
// Make sure nothing is live and dirty
-static void flushAllRegsBody(CompilationUnit* cUnit, RegisterInfo* info,
+STATIC void flushAllRegsBody(CompilationUnit* cUnit, RegisterInfo* info,
int numRegs)
{
int i;
@@ -754,7 +754,7 @@
//TUNING: rewrite all of this reg stuff. Probably use an attribute table
-static bool regClassMatches(int regClass, int reg)
+STATIC bool regClassMatches(int regClass, int reg)
{
if (regClass == kAnyReg) {
return true;
@@ -777,7 +777,7 @@
}
} else {
/* Can't be live if no associated sReg */
- assert(info->isTemp);
+ DCHECK(info->isTemp);
info->live = false;
}
info->sReg = sReg;
@@ -834,7 +834,7 @@
info->inUse = true;
}
-static void copyRegInfo(CompilationUnit* cUnit, int newReg, int oldReg)
+STATIC void copyRegInfo(CompilationUnit* cUnit, int newReg, int oldReg)
{
RegisterInfo* newInfo = getRegInfo(cUnit, newReg);
RegisterInfo* oldInfo = getRegInfo(cUnit, oldReg);
@@ -858,7 +858,7 @@
extern RegLocation oatUpdateLoc(CompilationUnit* cUnit, RegLocation loc)
{
- assert(!loc.wide);
+ DCHECK(!loc.wide);
if (loc.location == kLocDalvikFrame) {
RegisterInfo* infoLo = allocLive(cUnit, loc.sRegLow, kAnyReg);
if (infoLo) {
@@ -879,7 +879,7 @@
extern RegLocation oatUpdateLocWide(CompilationUnit* cUnit,
RegLocation loc)
{
- assert(loc.wide);
+ DCHECK(loc.wide);
if (loc.location == kLocDalvikFrame) {
// Are the dalvik regs already live in physical registers?
RegisterInfo* infoLo = allocLive(cUnit, loc.sRegLow, kAnyReg);
@@ -907,7 +907,7 @@
loc.highReg = infoHi->reg;
loc.location = kLocPhysReg;
oatMarkPair(cUnit, loc.lowReg, loc.highReg);
- assert(!FPREG(loc.lowReg) || ((loc.lowReg & 0x1) == 0));
+ DCHECK(!FPREG(loc.lowReg) || ((loc.lowReg & 0x1) == 0));
return loc;
}
// Can't easily reuse - clobber any overlaps
@@ -925,10 +925,21 @@
return loc;
}
-static RegLocation evalLocWide(CompilationUnit* cUnit, RegLocation loc,
+
+/* For use in cases we don't know (or care) width */
+extern RegLocation oatUpdateRawLoc(CompilationUnit* cUnit,
+ RegLocation loc)
+{
+ if (loc.wide)
+ return oatUpdateLocWide(cUnit, loc);
+ else
+ return oatUpdateLoc(cUnit, loc);
+}
+
+STATIC RegLocation evalLocWide(CompilationUnit* cUnit, RegLocation loc,
int regClass, bool update)
{
- assert(loc.wide);
+ DCHECK(loc.wide);
int newRegs;
int lowReg;
int highReg;
@@ -937,8 +948,8 @@
/* If already in registers, we can assume proper form. Right reg class? */
if (loc.location == kLocPhysReg) {
- assert(FPREG(loc.lowReg) == FPREG(loc.highReg));
- assert(!FPREG(loc.lowReg) || ((loc.lowReg & 0x1) == 0));
+ DCHECK_EQ(FPREG(loc.lowReg), FPREG(loc.highReg));
+ DCHECK(!FPREG(loc.lowReg) || ((loc.lowReg & 0x1) == 0));
if (!regClassMatches(regClass, loc.lowReg)) {
/* Wrong register class. Reallocate and copy */
newRegs = oatAllocTypedTempPair(cUnit, loc.fp, regClass);
@@ -953,13 +964,13 @@
loc.lowReg = lowReg;
loc.highReg = highReg;
oatMarkPair(cUnit, loc.lowReg, loc.highReg);
- assert(!FPREG(loc.lowReg) || ((loc.lowReg & 0x1) == 0));
+ DCHECK(!FPREG(loc.lowReg) || ((loc.lowReg & 0x1) == 0));
}
return loc;
}
- assert(loc.sRegLow != INVALID_SREG);
- assert(oatSRegHi(loc.sRegLow) != INVALID_SREG);
+ DCHECK_NE(loc.sRegLow, INVALID_SREG);
+ DCHECK_NE(oatSRegHi(loc.sRegLow), INVALID_SREG);
newRegs = oatAllocTypedTempPair(cUnit, loc.fp, regClass);
loc.lowReg = newRegs & 0xff;
@@ -971,7 +982,7 @@
oatMarkLive(cUnit, loc.lowReg, loc.sRegLow);
oatMarkLive(cUnit, loc.highReg, oatSRegHi(loc.sRegLow));
}
- assert(!FPREG(loc.lowReg) || ((loc.lowReg & 0x1) == 0));
+ DCHECK(!FPREG(loc.lowReg) || ((loc.lowReg & 0x1) == 0));
return loc;
}
@@ -997,7 +1008,7 @@
return loc;
}
- assert(loc.sRegLow != INVALID_SREG);
+ DCHECK_NE(loc.sRegLow, INVALID_SREG);
newReg = oatAllocTypedTemp(cUnit, loc.fp, regClass);
loc.lowReg = newReg;
@@ -1012,13 +1023,13 @@
extern RegLocation oatGetDest(CompilationUnit* cUnit, MIR* mir, int num)
{
RegLocation res = cUnit->regLocation[mir->ssaRep->defs[num]];
- assert(!res.wide);
+ DCHECK(!res.wide);
return res;
}
extern RegLocation oatGetSrc(CompilationUnit* cUnit, MIR* mir, int num)
{
RegLocation res = cUnit->regLocation[mir->ssaRep->uses[num]];
- assert(!res.wide);
+ DCHECK(!res.wide);
return res;
}
extern RegLocation oatGetRawSrc(CompilationUnit* cUnit, MIR* mir, int num)
@@ -1030,7 +1041,7 @@
int low, int high)
{
RegLocation res = cUnit->regLocation[mir->ssaRep->defs[low]];
- assert(res.wide);
+ DCHECK(res.wide);
return res;
}
@@ -1038,6 +1049,6 @@
int low, int high)
{
RegLocation res = cUnit->regLocation[mir->ssaRep->uses[low]];
- assert(res.wide);
+ DCHECK(res.wide);
return res;
}
diff --git a/src/compiler/codegen/arm/ArchFactory.cc b/src/compiler/codegen/arm/ArchFactory.cc
index 8012d7d..ec37876 100644
--- a/src/compiler/codegen/arm/ArchFactory.cc
+++ b/src/compiler/codegen/arm/ArchFactory.cc
@@ -22,8 +22,8 @@
*
*/
-static ArmLIR* genUnconditionalBranch(CompilationUnit*, ArmLIR*);
-static ArmLIR* genConditionalBranch(CompilationUnit*, ArmConditionCode,
+STATIC ArmLIR* genUnconditionalBranch(CompilationUnit*, ArmLIR*);
+STATIC ArmLIR* genConditionalBranch(CompilationUnit*, ArmConditionCode,
ArmLIR*);
/*
@@ -31,7 +31,7 @@
* to allow easy change between placing the current Method* in a
* dedicated register or its home location in the frame.
*/
-static void loadCurrMethodDirect(CompilationUnit *cUnit, int rTgt)
+STATIC void loadCurrMethodDirect(CompilationUnit *cUnit, int rTgt)
{
#if defined(METHOD_IN_REG)
genRegCopy(cUnit, rTgt, rMETHOD);
@@ -40,7 +40,7 @@
#endif
}
-static int loadCurrMethod(CompilationUnit *cUnit)
+STATIC int loadCurrMethod(CompilationUnit *cUnit)
{
#if defined(METHOD_IN_REG)
return rMETHOD;
@@ -51,7 +51,7 @@
#endif
}
-static ArmLIR* genImmedCheck(CompilationUnit* cUnit, ArmConditionCode cCode,
+STATIC ArmLIR* genImmedCheck(CompilationUnit* cUnit, ArmConditionCode cCode,
int reg, int immVal, MIR* mir, ArmThrowKind kind)
{
ArmLIR* tgt = (ArmLIR*)oatNew(sizeof(ArmLIR), true);
@@ -71,7 +71,7 @@
}
/* Perform null-check on a register. */
-static ArmLIR* genNullCheck(CompilationUnit* cUnit, int sReg, int mReg,
+STATIC ArmLIR* genNullCheck(CompilationUnit* cUnit, int sReg, int mReg,
MIR* mir)
{
if (!(cUnit->disableOpt & (1 << kNullCheckElimination)) &&
@@ -82,7 +82,7 @@
}
/* Perform check on two registers */
-static TGT_LIR* genRegRegCheck(CompilationUnit* cUnit, ArmConditionCode cCode,
+STATIC TGT_LIR* genRegRegCheck(CompilationUnit* cUnit, ArmConditionCode cCode,
int reg1, int reg2, MIR* mir, ArmThrowKind kind)
{
ArmLIR* tgt = (ArmLIR*)oatNew(sizeof(ArmLIR), true);
diff --git a/src/compiler/codegen/arm/ArchUtility.cc b/src/compiler/codegen/arm/ArchUtility.cc
index 350f38c..ccafecb 100644
--- a/src/compiler/codegen/arm/ArchUtility.cc
+++ b/src/compiler/codegen/arm/ArchUtility.cc
@@ -44,7 +44,7 @@
"ror"};
/* Decode and print a ARM register name */
-static char* decodeRegList(ArmOpcode opcode, int vector, char* buf)
+STATIC char* decodeRegList(ArmOpcode opcode, int vector, char* buf)
{
int i;
bool printed = false;
@@ -68,7 +68,7 @@
return buf;
}
-static char* decodeFPCSRegList(int count, int base, char* buf)
+STATIC char* decodeFPCSRegList(int count, int base, char* buf)
{
sprintf(buf, "s%d", base);
for (int i = 1; i < count; i++) {
@@ -77,7 +77,7 @@
return buf;
}
-static int expandImmediate(int value)
+STATIC int expandImmediate(int value)
{
int mode = (value & 0xf00) >> 8;
u4 bits = value & 0xff;
@@ -103,7 +103,7 @@
* Interpret a format string and build a string no longer than size
* See format key in Assemble.c.
*/
-static void buildInsnString(const char* fmt, ArmLIR* lir, char* buf,
+STATIC void buildInsnString(const char* fmt, ArmLIR* lir, char* buf,
unsigned char* baseAddr, int size)
{
int i;
@@ -116,13 +116,13 @@
int operand;
if (*fmt == '!') {
fmt++;
- assert(fmt < fmtEnd);
+ DCHECK_LT(fmt, fmtEnd);
nc = *fmt++;
if (nc=='!') {
strcpy(tbuf, "!");
} else {
- assert(fmt < fmtEnd);
- assert((unsigned)(nc-'0') < 4);
+ DCHECK_LT(fmt, fmtEnd);
+ DCHECK((unsigned)(nc-'0') < 4);
operand = lir->operands[nc-'0'];
switch(*fmt++) {
case 'H':
diff --git a/src/compiler/codegen/arm/ArmRallocUtil.cc b/src/compiler/codegen/arm/ArmRallocUtil.cc
index 0908c6d..3de0e79 100644
--- a/src/compiler/codegen/arm/ArmRallocUtil.cc
+++ b/src/compiler/codegen/arm/ArmRallocUtil.cc
@@ -36,7 +36,7 @@
} RefCounts;
/* USE SSA names to count references of base Dalvik vRegs. */
-static void countRefs(CompilationUnit *cUnit, BasicBlock* bb,
+STATIC void countRefs(CompilationUnit *cUnit, BasicBlock* bb,
RefCounts* counts, bool fp)
{
MIR* mir;
@@ -83,7 +83,7 @@
for (i=0; i< ssaRep->numUses; i++) {
int origSreg = DECODE_REG(
oatConvertSSARegToDalvik(cUnit, ssaRep->uses[i]));
- assert(origSreg < cUnit->method->NumRegisters());
+ DCHECK_LT(origSreg, cUnit->method->NumRegisters());
bool fpUse = ssaRep->fpUse ? ssaRep->fpUse[i] : false;
if (fp == fpUse) {
counts[origSreg].count++;
@@ -96,7 +96,7 @@
}
int origSreg = DECODE_REG(
oatConvertSSARegToDalvik(cUnit, ssaRep->defs[i]));
- assert(origSreg < cUnit->method->NumRegisters());
+ DCHECK_LT(origSreg, cUnit->method->NumRegisters());
bool fpDef = ssaRep->fpDef ? ssaRep->fpDef[i] : false;
if (fp == fpDef) {
counts[origSreg].count++;
@@ -107,14 +107,14 @@
}
/* qsort callback function, sort descending */
-static int sortCounts(const void *val1, const void *val2)
+STATIC int sortCounts(const void *val1, const void *val2)
{
const RefCounts* op1 = (const RefCounts*)val1;
const RefCounts* op2 = (const RefCounts*)val2;
return (op1->count == op2->count) ? 0 : (op1->count < op2->count ? 1 : -1);
}
-static void dumpCounts(const RefCounts* arr, int size, const char* msg)
+STATIC void dumpCounts(const RefCounts* arr, int size, const char* msg)
{
LOG(INFO) << msg;
for (int i = 0; i < size; i++) {
diff --git a/src/compiler/codegen/arm/Assemble.cc b/src/compiler/codegen/arm/Assemble.cc
index d22c267..dff9ddd 100644
--- a/src/compiler/codegen/arm/Assemble.cc
+++ b/src/compiler/codegen/arm/Assemble.cc
@@ -966,7 +966,7 @@
*/
#define PADDING_MOV_R5_R5 0x1C2D
-static void pushWord(std::vector<short>&buf, int data) {
+STATIC void pushWord(std::vector<short>&buf, int data) {
buf.push_back( data & 0xffff);
buf.push_back( (data >> 16) & 0xffff);
}
@@ -977,7 +977,7 @@
}
/* Write the numbers in the constant to the output stream */
-static void installLiteralPools(CompilationUnit* cUnit)
+STATIC void installLiteralPools(CompilationUnit* cUnit)
{
alignBuffer(cUnit->codeBuffer, cUnit->dataOffset);
ArmLIR* dataLIR = (ArmLIR*) cUnit->literalList;
@@ -988,7 +988,7 @@
}
/* Write the switch tables to the output stream */
-static void installSwitchTables(CompilationUnit* cUnit)
+STATIC void installSwitchTables(CompilationUnit* cUnit)
{
GrowableListIterator iterator;
oatGrowableListIteratorInit(&cUnit->switchTables, &iterator);
@@ -1015,7 +1015,7 @@
tabRec->targets[elems]->generic.offset - bxOffset);
}
} else {
- assert(tabRec->table[0] == kPackedSwitchSignature);
+ DCHECK_EQ(tabRec->table[0], kPackedSwitchSignature);
for (int elems = 0; elems < tabRec->table[1]; elems++) {
int disp = tabRec->targets[elems]->generic.offset - bxOffset;
if (cUnit->printMe) {
@@ -1030,7 +1030,7 @@
}
/* Write the fill array dta to the output stream */
-static void installFillArrayData(CompilationUnit* cUnit)
+STATIC void installFillArrayData(CompilationUnit* cUnit)
{
GrowableListIterator iterator;
oatGrowableListIteratorInit(&cUnit->fillArrayData, &iterator);
@@ -1050,7 +1050,7 @@
* discover that pc-relative displacements may not fit the selected
* instruction.
*/
-static AssemblerStatus assembleInstructions(CompilationUnit* cUnit,
+STATIC AssemblerStatus assembleInstructions(CompilationUnit* cUnit,
intptr_t startAddr)
{
ArmLIR* lir;
@@ -1173,7 +1173,7 @@
lir->opcode == kThumb2BCond) {
ArmLIR *targetLIR = (ArmLIR *) lir->generic.target;
int delta = 0;
- assert(targetLIR);
+ DCHECK(targetLIR);
intptr_t pc = lir->generic.offset + 4;
intptr_t target = targetLIR->generic.offset;
delta = target - pc;
@@ -1212,7 +1212,7 @@
res = kRetryAll;
}
} else if (lir->opcode == kThumbBlx1) {
- assert(NEXT_LIR(lir)->opcode == kThumbBlx2);
+ DCHECK(NEXT_LIR(lir)->opcode == kThumbBlx2);
/* curPC is Thumb */
intptr_t curPC = (startAddr + lir->generic.offset + 4) & ~3;
intptr_t target = lir->operands[1];
@@ -1222,18 +1222,18 @@
target |= 0x2;
}
int delta = target - curPC;
- assert((delta >= -(1<<22)) && (delta <= ((1<<22)-2)));
+ DCHECK((delta >= -(1<<22)) && (delta <= ((1<<22)-2)));
lir->operands[0] = (delta >> 12) & 0x7ff;
NEXT_LIR(lir)->operands[0] = (delta>> 1) & 0x7ff;
} else if (lir->opcode == kThumbBl1) {
- assert(NEXT_LIR(lir)->opcode == kThumbBl2);
+ DCHECK(NEXT_LIR(lir)->opcode == kThumbBl2);
/* Both curPC and target are Thumb */
intptr_t curPC = startAddr + lir->generic.offset + 4;
intptr_t target = lir->operands[1];
int delta = target - curPC;
- assert((delta >= -(1<<22)) && (delta <= ((1<<22)-2)));
+ DCHECK((delta >= -(1<<22)) && (delta <= ((1<<22)-2)));
lir->operands[0] = (delta >> 12) & 0x7ff;
NEXT_LIR(lir)->operands[0] = (delta>> 1) & 0x7ff;
@@ -1344,8 +1344,8 @@
bits |= value;
break;
case kFmtDfp: {
- assert(DOUBLEREG(operand));
- assert((operand & 0x1) == 0);
+ DCHECK(DOUBLEREG(operand));
+ DCHECK((operand & 0x1) == 0);
int regName = (operand & FP_REG_MASK) >> 1;
/* Snag the 1-bit slice and position it */
value = ((regName & 0x10) >> 4) <<
@@ -1357,7 +1357,7 @@
break;
}
case kFmtSfp:
- assert(SINGLEREG(operand));
+ DCHECK(SINGLEREG(operand));
/* Snag the 1-bit slice and position it */
value = (operand & 0x1) <<
encoder->fieldLoc[i].end;
@@ -1394,7 +1394,7 @@
}
break;
default:
- assert(0);
+ LOG(FATAL) << "Bad fmt:" << (int)encoder->fieldLoc[i].kind;
}
}
if (encoder->size == 2) {
@@ -1405,7 +1405,7 @@
return res;
}
-static int assignLiteralOffsetCommon(LIR* lir, int offset)
+STATIC int assignLiteralOffsetCommon(LIR* lir, int offset)
{
for (;lir != NULL; lir = lir->next) {
lir->offset = offset;
@@ -1414,7 +1414,7 @@
return offset;
}
-static void createMappingTable(CompilationUnit* cUnit)
+STATIC void createMappingTable(CompilationUnit* cUnit)
{
ArmLIR* armLIR;
int currentDalvikOffset = -1;
@@ -1433,13 +1433,13 @@
}
/* Determine the offset of each literal field */
-static int assignLiteralOffset(CompilationUnit* cUnit, int offset)
+STATIC int assignLiteralOffset(CompilationUnit* cUnit, int offset)
{
offset = assignLiteralOffsetCommon(cUnit->literalList, offset);
return offset;
}
-static int assignSwitchTablesOffset(CompilationUnit* cUnit, int offset)
+STATIC int assignSwitchTablesOffset(CompilationUnit* cUnit, int offset)
{
GrowableListIterator iterator;
oatGrowableListIteratorInit(&cUnit->switchTables, &iterator);
@@ -1451,14 +1451,14 @@
if (tabRec->table[0] == kSparseSwitchSignature) {
offset += tabRec->table[1] * (sizeof(int) * 2);
} else {
- assert(tabRec->table[0] == kPackedSwitchSignature);
+ DCHECK_EQ(tabRec->table[0], kPackedSwitchSignature);
offset += tabRec->table[1] * sizeof(int);
}
}
return offset;
}
-static int assignFillArrayDataOffset(CompilationUnit* cUnit, int offset)
+STATIC int assignFillArrayDataOffset(CompilationUnit* cUnit, int offset)
{
GrowableListIterator iterator;
oatGrowableListIteratorInit(&cUnit->fillArrayData, &iterator);
diff --git a/src/compiler/codegen/arm/Codegen.h b/src/compiler/codegen/arm/Codegen.h
index 9a1dc54..24e2b3e 100644
--- a/src/compiler/codegen/arm/Codegen.h
+++ b/src/compiler/codegen/arm/Codegen.h
@@ -28,21 +28,21 @@
/*
* loadConstant() sometimes needs to add a small imm to a pre-existing constant
*/
-static ArmLIR *opRegImm(CompilationUnit* cUnit, OpKind op, int rDestSrc1,
+STATIC ArmLIR *opRegImm(CompilationUnit* cUnit, OpKind op, int rDestSrc1,
int value);
-static ArmLIR *opRegReg(CompilationUnit* cUnit, OpKind op, int rDestSrc1,
+STATIC ArmLIR *opRegReg(CompilationUnit* cUnit, OpKind op, int rDestSrc1,
int rSrc2);
/* Forward decalraton the portable versions due to circular dependency */
-static bool genArithOpFloatPortable(CompilationUnit* cUnit, MIR* mir,
+STATIC bool genArithOpFloatPortable(CompilationUnit* cUnit, MIR* mir,
RegLocation rlDest, RegLocation rlSrc1,
RegLocation rlSrc2);
-static bool genArithOpDoublePortable(CompilationUnit* cUnit, MIR* mir,
+STATIC bool genArithOpDoublePortable(CompilationUnit* cUnit, MIR* mir,
RegLocation rlDest, RegLocation rlSrc1,
RegLocation rlSrc2);
-static bool genConversionPortable(CompilationUnit* cUnit, MIR* mir);
+STATIC bool genConversionPortable(CompilationUnit* cUnit, MIR* mir);
#endif
diff --git a/src/compiler/codegen/arm/CodegenCommon.cc b/src/compiler/codegen/arm/CodegenCommon.cc
index 08da8d8..4a2768c 100644
--- a/src/compiler/codegen/arm/CodegenCommon.cc
+++ b/src/compiler/codegen/arm/CodegenCommon.cc
@@ -27,11 +27,11 @@
/* Track exercised opcodes */
static int opcodeCoverage[kNumPackedOpcodes];
-static void setMemRefType(ArmLIR* lir, bool isLoad, int memType)
+STATIC void setMemRefType(ArmLIR* lir, bool isLoad, int memType)
{
u8 *maskPtr;
u8 mask = ENCODE_MEM;;
- assert(EncodingMap[lir->opcode].flags & (IS_LOAD | IS_STORE));
+ DCHECK(EncodingMap[lir->opcode].flags & (IS_LOAD | IS_STORE));
if (isLoad) {
maskPtr = &lir->useMask;
} else {
@@ -42,7 +42,7 @@
/* ..and then add back the one we need */
switch(memType) {
case kLiteral:
- assert(isLoad);
+ DCHECK(isLoad);
*maskPtr |= ENCODE_LITERAL;
break;
case kDalvikReg:
@@ -53,7 +53,7 @@
break;
case kMustNotAlias:
/* Currently only loads can be marked as kMustNotAlias */
- assert(!(EncodingMap[lir->opcode].flags & IS_STORE));
+ DCHECK(!(EncodingMap[lir->opcode].flags & IS_STORE));
*maskPtr |= ENCODE_MUST_NOT_ALIAS;
break;
default:
@@ -65,7 +65,7 @@
* Mark load/store instructions that access Dalvik registers through r5FP +
* offset.
*/
-static void annotateDalvikRegAccess(ArmLIR* lir, int regId, bool isLoad)
+STATIC void annotateDalvikRegAccess(ArmLIR* lir, int regId, bool isLoad)
{
setMemRefType(lir, isLoad, kDalvikReg);
@@ -82,7 +82,7 @@
/*
* Decode the register id.
*/
-static inline u8 getRegMaskCommon(int reg)
+STATIC inline u8 getRegMaskCommon(int reg)
{
u8 seed;
int shift;
@@ -102,7 +102,7 @@
/*
* Mark the corresponding bit(s).
*/
-static inline void setupRegMask(u8* mask, int reg)
+STATIC inline void setupRegMask(u8* mask, int reg)
{
*mask |= getRegMaskCommon(reg);
}
@@ -110,7 +110,7 @@
/*
* Set up the proper fields in the resource mask
*/
-static void setupResourceMasks(ArmLIR* lir)
+STATIC void setupResourceMasks(ArmLIR* lir)
{
int opcode = lir->opcode;
int flags;
@@ -237,10 +237,10 @@
* The following are building blocks to construct low-level IRs with 0 - 4
* operands.
*/
-static ArmLIR* newLIR0(CompilationUnit* cUnit, ArmOpcode opcode)
+STATIC ArmLIR* newLIR0(CompilationUnit* cUnit, ArmOpcode opcode)
{
ArmLIR* insn = (ArmLIR* ) oatNew(sizeof(ArmLIR), true);
- assert(isPseudoOpcode(opcode) || (EncodingMap[opcode].flags & NO_OPERAND));
+ DCHECK(isPseudoOpcode(opcode) || (EncodingMap[opcode].flags & NO_OPERAND));
insn->opcode = opcode;
setupResourceMasks(insn);
insn->generic.dalvikOffset = cUnit->currentDalvikOffset;
@@ -248,11 +248,11 @@
return insn;
}
-static ArmLIR* newLIR1(CompilationUnit* cUnit, ArmOpcode opcode,
+STATIC ArmLIR* newLIR1(CompilationUnit* cUnit, ArmOpcode opcode,
int dest)
{
ArmLIR* insn = (ArmLIR* ) oatNew(sizeof(ArmLIR), true);
- assert(isPseudoOpcode(opcode) || (EncodingMap[opcode].flags & IS_UNARY_OP));
+ DCHECK(isPseudoOpcode(opcode) || (EncodingMap[opcode].flags & IS_UNARY_OP));
insn->opcode = opcode;
insn->operands[0] = dest;
setupResourceMasks(insn);
@@ -261,11 +261,11 @@
return insn;
}
-static ArmLIR* newLIR2(CompilationUnit* cUnit, ArmOpcode opcode,
+STATIC ArmLIR* newLIR2(CompilationUnit* cUnit, ArmOpcode opcode,
int dest, int src1)
{
ArmLIR* insn = (ArmLIR* ) oatNew(sizeof(ArmLIR), true);
- assert(isPseudoOpcode(opcode) ||
+ DCHECK(isPseudoOpcode(opcode) ||
(EncodingMap[opcode].flags & IS_BINARY_OP));
insn->opcode = opcode;
insn->operands[0] = dest;
@@ -276,7 +276,7 @@
return insn;
}
-static ArmLIR* newLIR3(CompilationUnit* cUnit, ArmOpcode opcode,
+STATIC ArmLIR* newLIR3(CompilationUnit* cUnit, ArmOpcode opcode,
int dest, int src1, int src2)
{
ArmLIR* insn = (ArmLIR* ) oatNew(sizeof(ArmLIR), true);
@@ -296,11 +296,11 @@
}
#if defined(_ARMV7_A) || defined(_ARMV7_A_NEON)
-static ArmLIR* newLIR4(CompilationUnit* cUnit, ArmOpcode opcode,
+STATIC ArmLIR* newLIR4(CompilationUnit* cUnit, ArmOpcode opcode,
int dest, int src1, int src2, int info)
{
ArmLIR* insn = (ArmLIR* ) oatNew(sizeof(ArmLIR), true);
- assert(isPseudoOpcode(opcode) ||
+ DCHECK(isPseudoOpcode(opcode) ||
(EncodingMap[opcode].flags & IS_QUAD_OP));
insn->opcode = opcode;
insn->operands[0] = dest;
@@ -318,7 +318,7 @@
* Search the existing constants in the literal pool for an exact or close match
* within specified delta (greater or equal to 0).
*/
-static ArmLIR* scanLiteralPool(LIR* dataTarget, int value, unsigned int delta)
+STATIC ArmLIR* scanLiteralPool(LIR* dataTarget, int value, unsigned int delta)
{
while (dataTarget) {
if (((unsigned) (value - ((ArmLIR* ) dataTarget)->operands[0])) <=
@@ -330,7 +330,7 @@
}
/* Search the existing constants in the literal pool for an exact wide match */
-static ArmLIR* scanLiteralPoolWide(LIR* dataTarget, int valLo, int valHi)
+STATIC ArmLIR* scanLiteralPoolWide(LIR* dataTarget, int valLo, int valHi)
{
bool loMatch = false;
LIR* loTarget = NULL;
@@ -354,7 +354,7 @@
*/
/* Add a 32-bit constant either in the constant pool or mixed with code */
-static ArmLIR* addWordData(CompilationUnit* cUnit, LIR* *constantListP,
+STATIC ArmLIR* addWordData(CompilationUnit* cUnit, LIR* *constantListP,
int value)
{
/* Add the constant to the literal pool */
@@ -373,7 +373,7 @@
}
/* Add a 64-bit constant to the constant pool or mixed with code */
-static ArmLIR* addWideData(CompilationUnit* cUnit, LIR* *constantListP,
+STATIC ArmLIR* addWideData(CompilationUnit* cUnit, LIR* *constantListP,
int valLo, int valHi)
{
ArmLIR* res;
@@ -393,7 +393,7 @@
* Generate an kArmPseudoBarrier marker to indicate the boundary of special
* blocks.
*/
-static void genBarrier(CompilationUnit* cUnit)
+STATIC void genBarrier(CompilationUnit* cUnit)
{
ArmLIR* barrier = newLIR0(cUnit, kArmPseudoBarrier);
/* Mark all resources as being clobbered */
diff --git a/src/compiler/codegen/arm/FP/Thumb2VFP.cc b/src/compiler/codegen/arm/FP/Thumb2VFP.cc
index 3cfb157..60cb476 100644
--- a/src/compiler/codegen/arm/FP/Thumb2VFP.cc
+++ b/src/compiler/codegen/arm/FP/Thumb2VFP.cc
@@ -14,7 +14,7 @@
* limitations under the License.
*/
-static bool genArithOpFloat(CompilationUnit* cUnit, MIR* mir,
+STATIC bool genArithOpFloat(CompilationUnit* cUnit, MIR* mir,
RegLocation rlDest, RegLocation rlSrc1,
RegLocation rlSrc2)
{
@@ -60,7 +60,7 @@
return false;
}
-static bool genArithOpDouble(CompilationUnit* cUnit, MIR* mir,
+STATIC bool genArithOpDouble(CompilationUnit* cUnit, MIR* mir,
RegLocation rlDest, RegLocation rlSrc1,
RegLocation rlSrc2)
{
@@ -95,12 +95,12 @@
}
rlSrc1 = loadValueWide(cUnit, rlSrc1, kFPReg);
- assert(rlSrc1.wide);
+ DCHECK(rlSrc1.wide);
rlSrc2 = loadValueWide(cUnit, rlSrc2, kFPReg);
- assert(rlSrc2.wide);
+ DCHECK(rlSrc2.wide);
rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
- assert(rlDest.wide);
- assert(rlResult.wide);
+ DCHECK(rlDest.wide);
+ DCHECK(rlResult.wide);
newLIR3(cUnit, (ArmOpcode)op, S2D(rlResult.lowReg, rlResult.highReg),
S2D(rlSrc1.lowReg, rlSrc1.highReg),
S2D(rlSrc2.lowReg, rlSrc2.highReg));
@@ -108,7 +108,7 @@
return false;
}
-static bool genConversion(CompilationUnit* cUnit, MIR* mir)
+STATIC bool genConversion(CompilationUnit* cUnit, MIR* mir)
{
Opcode opcode = mir->dalvikInsn.opcode;
int op = kThumbBkpt;
@@ -182,7 +182,7 @@
return false;
}
-static bool genCmpFP(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
+STATIC bool genCmpFP(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
RegLocation rlSrc1, RegLocation rlSrc2)
{
bool isDouble;
@@ -225,7 +225,7 @@
loadConstant(cUnit, rlResult.lowReg, defaultResult);
newLIR2(cUnit, kThumb2Vcmps, rlSrc1.lowReg, rlSrc2.lowReg);
}
- assert(!FPREG(rlResult.lowReg));
+ DCHECK(!FPREG(rlResult.lowReg));
newLIR0(cUnit, kThumb2Fmstat);
genIT(cUnit, (defaultResult == -1) ? kArmCondGt : kArmCondMi, "");
diff --git a/src/compiler/codegen/arm/LocalOptimizations.cc b/src/compiler/codegen/arm/LocalOptimizations.cc
index 8d6f3a5..b2bc333 100644
--- a/src/compiler/codegen/arm/LocalOptimizations.cc
+++ b/src/compiler/codegen/arm/LocalOptimizations.cc
@@ -30,7 +30,7 @@
#define LDLD_DISTANCE 4
#define LD_LATENCY 2
-static inline bool isDalvikRegisterClobbered(ArmLIR* lir1, ArmLIR* lir2)
+STATIC inline bool isDalvikRegisterClobbered(ArmLIR* lir1, ArmLIR* lir2)
{
int reg1Lo = DECODE_ALIAS_INFO_REG(lir1->aliasInfo);
int reg1Hi = reg1Lo + DECODE_ALIAS_INFO_WIDE(lir1->aliasInfo);
@@ -41,7 +41,7 @@
}
/* Convert a more expensive instruction (ie load) into a move */
-static void convertMemOpIntoMove(CompilationUnit* cUnit, ArmLIR* origLIR,
+STATIC void convertMemOpIntoMove(CompilationUnit* cUnit, ArmLIR* origLIR,
int dest, int src)
{
/* Insert a move to replace the load */
@@ -74,7 +74,7 @@
* 1) They are must-aliases
* 2) The memory location is not written to in between
*/
-static void applyLoadStoreElimination(CompilationUnit* cUnit,
+STATIC void applyLoadStoreElimination(CompilationUnit* cUnit,
ArmLIR* headLIR,
ArmLIR* tailLIR)
{
@@ -142,7 +142,7 @@
* Should only see literal loads in the instruction
* stream.
*/
- assert(!(EncodingMap[checkLIR->opcode].flags &
+ DCHECK(!(EncodingMap[checkLIR->opcode].flags &
IS_STORE));
/* Same value && same register type */
if (checkLIR->aliasInfo == thisLIR->aliasInfo &&
@@ -257,7 +257,7 @@
* Perform a pass of bottom-up walk, from the second instruction in the
* superblock, to try to hoist loads to earlier slots.
*/
-static void applyLoadHoisting(CompilationUnit* cUnit,
+STATIC void applyLoadHoisting(CompilationUnit* cUnit,
ArmLIR* headLIR,
ArmLIR* tailLIR)
{
@@ -328,7 +328,7 @@
}
/* Conservatively treat all heap refs as may-alias */
} else {
- assert(aliasCondition == ENCODE_HEAP_REF);
+ DCHECK_EQ(aliasCondition, ENCODE_HEAP_REF);
stopHere = true;
}
/* Memory content may be updated. Stop looking now. */
diff --git a/src/compiler/codegen/arm/MethodCodegenDriver.cc b/src/compiler/codegen/arm/MethodCodegenDriver.cc
index c5241ca..0c99e18 100644
--- a/src/compiler/codegen/arm/MethodCodegenDriver.cc
+++ b/src/compiler/codegen/arm/MethodCodegenDriver.cc
@@ -16,19 +16,19 @@
#define DISPLAY_MISSING_TARGETS 1
-static const RegLocation badLoc = {kLocDalvikFrame, 0, 0, INVALID_REG,
+STATIC const RegLocation badLoc = {kLocDalvikFrame, 0, 0, INVALID_REG,
INVALID_REG, INVALID_SREG, 0,
kLocDalvikFrame, INVALID_REG, INVALID_REG,
INVALID_OFFSET};
-static const RegLocation retLoc = LOC_DALVIK_RETURN_VAL;
-static const RegLocation retLocWide = LOC_DALVIK_RETURN_VAL_WIDE;
+STATIC const RegLocation retLoc = LOC_DALVIK_RETURN_VAL;
+STATIC const RegLocation retLocWide = LOC_DALVIK_RETURN_VAL_WIDE;
/*
* Let helper function take care of everything. Will call
* Array::AllocFromCode(type_idx, method, count);
* Note: AllocFromCode will handle checks for errNegativeArraySize.
*/
-static void genNewArray(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
+STATIC void genNewArray(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
RegLocation rlSrc)
{
oatFlushAllRegs(cUnit); /* Everything to home location */
@@ -49,7 +49,7 @@
* code throws runtime exception "bad Filled array req" for 'D' and 'J'.
* Current code also throws internal unimp if not 'L', '[' or 'I'.
*/
-static void genFilledNewArray(CompilationUnit* cUnit, MIR* mir, bool isRange)
+STATIC void genFilledNewArray(CompilationUnit* cUnit, MIR* mir, bool isRange)
{
DecodedInstruction* dInsn = &mir->dalvikInsn;
int elems = dInsn->vA;
@@ -163,7 +163,7 @@
return NULL; // resort to slow path
}
-static void genSput(CompilationUnit* cUnit, MIR* mir, RegLocation rlSrc)
+STATIC void genSput(CompilationUnit* cUnit, MIR* mir, RegLocation rlSrc)
{
bool isObject = ((mir->dalvikInsn.opcode == OP_SPUT_OBJECT) ||
(mir->dalvikInsn.opcode == OP_SPUT_OBJECT_VOLATILE));
@@ -221,7 +221,7 @@
}
}
-static void genSputWide(CompilationUnit* cUnit, MIR* mir, RegLocation rlSrc)
+STATIC void genSputWide(CompilationUnit* cUnit, MIR* mir, RegLocation rlSrc)
{
int fieldIdx = mir->dalvikInsn.vB;
uint32_t typeIdx;
@@ -273,7 +273,7 @@
}
-static void genSgetWide(CompilationUnit* cUnit, MIR* mir,
+STATIC void genSgetWide(CompilationUnit* cUnit, MIR* mir,
RegLocation rlResult, RegLocation rlDest)
{
int fieldIdx = mir->dalvikInsn.vB;
@@ -326,7 +326,7 @@
}
}
-static void genSget(CompilationUnit* cUnit, MIR* mir,
+STATIC void genSget(CompilationUnit* cUnit, MIR* mir,
RegLocation rlResult, RegLocation rlDest)
{
int fieldIdx = mir->dalvikInsn.vB;
@@ -390,7 +390,7 @@
* Bit of a hack here - in leiu of a real scheduling pass,
* emit the next instruction in static & direct invoke sequences.
*/
-static int nextSDCallInsn(CompilationUnit* cUnit, MIR* mir,
+STATIC int nextSDCallInsn(CompilationUnit* cUnit, MIR* mir,
DecodedInstruction* dInsn, int state,
ArmLIR* rollback)
{
@@ -424,7 +424,7 @@
* Note also that we'll load the first argument ("this") into
* r1 here rather than the standard loadArgRegs.
*/
-static int nextVCallInsn(CompilationUnit* cUnit, MIR* mir,
+STATIC int nextVCallInsn(CompilationUnit* cUnit, MIR* mir,
DecodedInstruction* dInsn, int state,
ArmLIR* rollback)
{
@@ -464,11 +464,11 @@
return state + 1;
}
-static int nextVCallInsnSP(CompilationUnit* cUnit, MIR* mir,
+STATIC int nextVCallInsnSP(CompilationUnit* cUnit, MIR* mir,
DecodedInstruction* dInsn, int state,
ArmLIR* rollback)
{
- DCHECK(rollback != NULL);
+ DCHECK(rollback == NULL);
RegLocation rlArg;
ArmLIR* skipBranch;
ArmLIR* skipTarget;
@@ -520,7 +520,7 @@
case 5:
// get this->klass_->vtable_ [usr rLR, set rLR]
loadWordDisp(cUnit, rLR, Class::VTableOffset().Int32Value(), rLR);
- DCHECK((art::Array::DataOffset().Int32Value() & 0x3) == 0);
+ DCHECK_EQ((art::Array::DataOffset().Int32Value() & 0x3), 0);
// In load shadow fold vtable_ object header size into method_index_
opRegImm(cUnit, kOpAdd, r0,
art::Array::DataOffset().Int32Value() / 4);
@@ -537,7 +537,7 @@
}
/* Load up to 3 arguments in r1..r3 */
-static int loadArgRegs(CompilationUnit* cUnit, MIR* mir,
+STATIC int loadArgRegs(CompilationUnit* cUnit, MIR* mir,
DecodedInstruction* dInsn, int callState,
int *args, NextCallInsn nextCallInsn, ArmLIR* rollback)
{
@@ -554,7 +554,7 @@
}
// Interleave launch code for INVOKE_INTERFACE.
-static int nextInterfaceCallInsn(CompilationUnit* cUnit, MIR* mir,
+STATIC int nextInterfaceCallInsn(CompilationUnit* cUnit, MIR* mir,
DecodedInstruction* dInsn, int state,
ArmLIR* rollback)
{
@@ -576,7 +576,7 @@
* Interleave launch code for INVOKE_SUPER. See comments
* for nextVCallIns.
*/
-static int nextSuperCallInsn(CompilationUnit* cUnit, MIR* mir,
+STATIC int nextSuperCallInsn(CompilationUnit* cUnit, MIR* mir,
DecodedInstruction* dInsn, int state,
ArmLIR* rollback)
{
@@ -630,11 +630,11 @@
}
/* Slow-path version of nextSuperCallInsn */
-static int nextSuperCallInsnSP(CompilationUnit* cUnit, MIR* mir,
+STATIC int nextSuperCallInsnSP(CompilationUnit* cUnit, MIR* mir,
DecodedInstruction* dInsn, int state,
ArmLIR* rollback)
{
- DCHECK(rollback != NULL);
+ DCHECK(rollback == NULL);
RegLocation rlArg;
ArmLIR* skipBranch;
ArmLIR* skipTarget;
@@ -717,7 +717,7 @@
* the target method pointer. Note, this may also be called
* for "range" variants if the number of arguments is 5 or fewer.
*/
-static int genDalvikArgsNoRange(CompilationUnit* cUnit, MIR* mir,
+STATIC int genDalvikArgsNoRange(CompilationUnit* cUnit, MIR* mir,
DecodedInstruction* dInsn, int callState,
ArmLIR** pcrLabel, bool isRange,
NextCallInsn nextCallInsn, ArmLIR* rollback,
@@ -790,7 +790,7 @@
* Pass arg0, arg1 & arg2 in r1-r3
*
*/
-static int genDalvikArgsRange(CompilationUnit* cUnit, MIR* mir,
+STATIC int genDalvikArgsRange(CompilationUnit* cUnit, MIR* mir,
DecodedInstruction* dInsn, int callState,
ArmLIR** pcrLabel, NextCallInsn nextCallInsn,
ArmLIR* rollback, bool skipThis)
@@ -888,7 +888,7 @@
#ifdef DISPLAY_MISSING_TARGETS
// Debugging routine - if null target, branch to DebugMe
-static void genShowTarget(CompilationUnit* cUnit)
+STATIC void genShowTarget(CompilationUnit* cUnit)
{
ArmLIR* branchOver = genCmpImmBranch(cUnit, kArmCondNe, rLR, 0);
loadWordDisp(cUnit, rSELF,
@@ -899,7 +899,7 @@
}
#endif
-static void genInvokeStaticDirect(CompilationUnit* cUnit, MIR* mir,
+STATIC void genInvokeStaticDirect(CompilationUnit* cUnit, MIR* mir,
bool direct, bool range)
{
DecodedInstruction* dInsn = &mir->dalvikInsn;
@@ -932,7 +932,7 @@
* All invoke-interface calls bounce off of art_invoke_interface_trampoline,
* which will locate the target and continue on via a tail call.
*/
-static void genInvokeInterface(CompilationUnit* cUnit, MIR* mir)
+STATIC void genInvokeInterface(CompilationUnit* cUnit, MIR* mir)
{
DecodedInstruction* dInsn = &mir->dalvikInsn;
int callState = 0;
@@ -959,7 +959,7 @@
opReg(cUnit, kOpBlx, rLR);
}
-static void genInvokeSuper(CompilationUnit* cUnit, MIR* mir)
+STATIC void genInvokeSuper(CompilationUnit* cUnit, MIR* mir)
{
DecodedInstruction* dInsn = &mir->dalvikInsn;
int callState = 0;
@@ -1011,7 +1011,7 @@
opReg(cUnit, kOpBlx, rLR);
}
-static void genInvokeVirtual(CompilationUnit* cUnit, MIR* mir)
+STATIC void genInvokeVirtual(CompilationUnit* cUnit, MIR* mir)
{
DecodedInstruction* dInsn = &mir->dalvikInsn;
int callState = 0;
@@ -1050,7 +1050,7 @@
opReg(cUnit, kOpBlx, rLR);
}
-static bool compileDalvikInstruction(CompilationUnit* cUnit, MIR* mir,
+STATIC bool compileDalvikInstruction(CompilationUnit* cUnit, MIR* mir,
BasicBlock* bb, ArmLIR* labelList)
{
bool res = false; // Assume success
@@ -1134,8 +1134,8 @@
* registers are live and may not be used for address
* formation in storeValueWide.
*/
- assert(retLocWide.lowReg == r0);
- assert(retLocWide.highReg == r1);
+ DCHECK(retLocWide.lowReg == r0);
+ DCHECK(retLocWide.highReg == r1);
oatLockTemp(cUnit, retLocWide.lowReg);
oatLockTemp(cUnit, retLocWide.highReg);
storeValueWide(cUnit, rlDest, retLocWide);
@@ -1148,7 +1148,7 @@
if (mir->optimizationFlags & MIR_INLINED)
break; // Nop - combined w/ previous invoke
/* See comment for OP_MOVE_RESULT_WIDE */
- assert(retLoc.lowReg == r0);
+ DCHECK(retLoc.lowReg == r0);
oatLockTemp(cUnit, retLoc.lowReg);
storeValue(cUnit, rlDest, retLoc);
oatFreeTemp(cUnit, retLoc.lowReg);
@@ -1719,7 +1719,7 @@
return res;
}
-static const char *extendedMIROpNames[kMirOpLast - kMirOpFirst] = {
+STATIC const char *extendedMIROpNames[kMirOpLast - kMirOpFirst] = {
"kMirOpPhi",
"kMirOpNullNRangeUpCheck",
"kMirOpNullNRangeDownCheck",
@@ -1729,7 +1729,7 @@
};
/* Extended MIR instructions like PHI */
-static void handleExtendedMethodMIR(CompilationUnit* cUnit, MIR* mir)
+STATIC void handleExtendedMethodMIR(CompilationUnit* cUnit, MIR* mir)
{
int opOffset = mir->dalvikInsn.opcode - kMirOpFirst;
char* msg = (char*)oatNew(strlen(extendedMIROpNames[opOffset]) + 1, false);
@@ -1752,7 +1752,7 @@
* to a callee-save register, flush them to the frame.
* Note: at this pointCopy any ins that are passed in register to their
* home location */
-static void flushIns(CompilationUnit* cUnit)
+STATIC void flushIns(CompilationUnit* cUnit)
{
if (cUnit->method->NumIns() == 0)
return;
@@ -1803,7 +1803,7 @@
}
/* Handle the content in each basic block */
-static bool methodBlockCodeGen(CompilationUnit* cUnit, BasicBlock* bb)
+STATIC bool methodBlockCodeGen(CompilationUnit* cUnit, BasicBlock* bb)
{
MIR* mir;
ArmLIR* labelList = (ArmLIR*) cUnit->blockLabelList;
@@ -1998,7 +1998,7 @@
}
}
-static void handleSuspendLaunchpads(CompilationUnit *cUnit)
+STATIC void handleSuspendLaunchpads(CompilationUnit *cUnit)
{
ArmLIR** suspendLabel =
(ArmLIR **) cUnit->suspendLaunchpads.elemList;
@@ -2019,7 +2019,7 @@
}
}
-static void handleThrowLaunchpads(CompilationUnit *cUnit)
+STATIC void handleThrowLaunchpads(CompilationUnit *cUnit)
{
ArmLIR** throwLabel =
(ArmLIR **) cUnit->throwLaunchpads.elemList;
diff --git a/src/compiler/codegen/arm/Thumb2/Factory.cc b/src/compiler/codegen/arm/Thumb2/Factory.cc
index 9321753..c8e428f 100644
--- a/src/compiler/codegen/arm/Thumb2/Factory.cc
+++ b/src/compiler/codegen/arm/Thumb2/Factory.cc
@@ -33,7 +33,7 @@
static int fpTemps[] = {fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15};
-static int encodeImmSingle(int value)
+STATIC int encodeImmSingle(int value)
{
int res;
int bitA = (value & 0x80000000) >> 31;
@@ -55,11 +55,11 @@
return res;
}
-static ArmLIR* loadFPConstantValue(CompilationUnit* cUnit, int rDest,
+STATIC ArmLIR* loadFPConstantValue(CompilationUnit* cUnit, int rDest,
int value)
{
int encodedImm = encodeImmSingle(value);
- assert(SINGLEREG(rDest));
+ DCHECK(SINGLEREG(rDest));
if (encodedImm >= 0) {
return newLIR2(cUnit, kThumb2Vmovs_IMM8, rDest, encodedImm);
}
@@ -80,7 +80,7 @@
return loadPcRel;
}
-static int leadingZeros(u4 val)
+STATIC int leadingZeros(u4 val)
{
u4 alt;
int n;
@@ -103,7 +103,7 @@
* Determine whether value can be encoded as a Thumb2 modified
* immediate. If not, return -1. If so, return i:imm3:a:bcdefgh form.
*/
-static int modifiedImmediate(u4 value)
+STATIC int modifiedImmediate(u4 value)
{
int zLeading;
int zTrailing;
@@ -141,7 +141,7 @@
* 1) rDest is freshly returned from oatAllocTemp or
* 2) The codegen is under fixed register usage
*/
-static ArmLIR* loadConstantNoClobber(CompilationUnit* cUnit, int rDest,
+STATIC ArmLIR* loadConstantNoClobber(CompilationUnit* cUnit, int rDest,
int value)
{
ArmLIR* res;
@@ -201,7 +201,7 @@
* Load an immediate value into a fixed or temp register. Target
* register is clobbered, and marked inUse.
*/
-static ArmLIR* loadConstant(CompilationUnit* cUnit, int rDest, int value)
+STATIC ArmLIR* loadConstant(CompilationUnit* cUnit, int rDest, int value)
{
if (oatIsTemp(cUnit, rDest)) {
oatClobber(cUnit, rDest);
@@ -210,7 +210,7 @@
return loadConstantNoClobber(cUnit, rDest, value);
}
-static ArmLIR* opNone(CompilationUnit* cUnit, OpKind op)
+STATIC ArmLIR* opNone(CompilationUnit* cUnit, OpKind op)
{
ArmOpcode opcode = kThumbBkpt;
switch (op) {
@@ -218,17 +218,17 @@
opcode = kThumbBUncond;
break;
default:
- assert(0);
+ LOG(FATAL) << "Bad opcode " << (int)op;
}
return newLIR0(cUnit, opcode);
}
-static ArmLIR* opCondBranch(CompilationUnit* cUnit, ArmConditionCode cc)
+STATIC ArmLIR* opCondBranch(CompilationUnit* cUnit, ArmConditionCode cc)
{
return newLIR2(cUnit, kThumb2BCond, 0 /* offset to be patched */, cc);
}
-static ArmLIR* opReg(CompilationUnit* cUnit, OpKind op, int rDestSrc)
+STATIC ArmLIR* opReg(CompilationUnit* cUnit, OpKind op, int rDestSrc)
{
ArmOpcode opcode = kThumbBkpt;
switch (op) {
@@ -236,12 +236,12 @@
opcode = kThumbBlxR;
break;
default:
- assert(0);
+ LOG(FATAL) << "Bad opcode " << (int)op;
}
return newLIR1(cUnit, opcode, rDestSrc);
}
-static ArmLIR* opRegRegShift(CompilationUnit* cUnit, OpKind op, int rDestSrc1,
+STATIC ArmLIR* opRegRegShift(CompilationUnit* cUnit, OpKind op, int rDestSrc1,
int rSrc2, int shift)
{
bool thumbForm = ((shift == 0) && LOWREG(rDestSrc1) && LOWREG(rSrc2));
@@ -257,7 +257,7 @@
opcode = (thumbForm) ? kThumbBicRR : kThumb2BicRRR;
break;
case kOpCmn:
- assert(shift == 0);
+ DCHECK_EQ(shift, 0);
opcode = (thumbForm) ? kThumbCmnRR : kThumb2CmnRR;
break;
case kOpCmp:
@@ -276,7 +276,7 @@
opcode = (thumbForm) ? kThumbEorRR : kThumb2EorRRR;
break;
case kOpMov:
- assert(shift == 0);
+ DCHECK_EQ(shift, 0);
if (LOWREG(rDestSrc1) && LOWREG(rSrc2))
opcode = kThumbMovRR;
else if (!LOWREG(rDestSrc1) && !LOWREG(rSrc2))
@@ -287,14 +287,14 @@
opcode = kThumbMovRR_L2H;
break;
case kOpMul:
- assert(shift == 0);
+ DCHECK_EQ(shift, 0);
opcode = (thumbForm) ? kThumbMul : kThumb2MulRRR;
break;
case kOpMvn:
opcode = (thumbForm) ? kThumbMvn : kThumb2MnvRR;
break;
case kOpNeg:
- assert(shift == 0);
+ DCHECK_EQ(shift, 0);
opcode = (thumbForm) ? kThumbNeg : kThumb2NegRR;
break;
case kOpOr:
@@ -307,19 +307,19 @@
opcode = (thumbForm) ? kThumbTst : kThumb2TstRR;
break;
case kOpLsl:
- assert(shift == 0);
+ DCHECK_EQ(shift, 0);
opcode = (thumbForm) ? kThumbLslRR : kThumb2LslRRR;
break;
case kOpLsr:
- assert(shift == 0);
+ DCHECK_EQ(shift, 0);
opcode = (thumbForm) ? kThumbLsrRR : kThumb2LsrRRR;
break;
case kOpAsr:
- assert(shift == 0);
+ DCHECK_EQ(shift, 0);
opcode = (thumbForm) ? kThumbAsrRR : kThumb2AsrRRR;
break;
case kOpRor:
- assert(shift == 0);
+ DCHECK_EQ(shift, 0);
opcode = (thumbForm) ? kThumbRorRR : kThumb2RorRRR;
break;
case kOpAdd:
@@ -329,19 +329,19 @@
opcode = (thumbForm) ? kThumbSubRRR : kThumb2SubRRR;
break;
case kOp2Byte:
- assert(shift == 0);
+ DCHECK_EQ(shift, 0);
return newLIR4(cUnit, kThumb2Sbfx, rDestSrc1, rSrc2, 0, 8);
case kOp2Short:
- assert(shift == 0);
+ DCHECK_EQ(shift, 0);
return newLIR4(cUnit, kThumb2Sbfx, rDestSrc1, rSrc2, 0, 16);
case kOp2Char:
- assert(shift == 0);
+ DCHECK_EQ(shift, 0);
return newLIR4(cUnit, kThumb2Ubfx, rDestSrc1, rSrc2, 0, 16);
default:
- assert(0);
+ LOG(FATAL) << "Bad opcode: " << (int)op;
break;
}
- assert(opcode >= 0);
+ DCHECK(opcode >= 0);
if (EncodingMap[opcode].flags & IS_BINARY_OP)
return newLIR2(cUnit, opcode, rDestSrc1, rSrc2);
else if (EncodingMap[opcode].flags & IS_TERTIARY_OP) {
@@ -352,18 +352,18 @@
} else if (EncodingMap[opcode].flags & IS_QUAD_OP)
return newLIR4(cUnit, opcode, rDestSrc1, rDestSrc1, rSrc2, shift);
else {
- assert(0);
+ LOG(FATAL) << "Unexpected encoding operand count";
return NULL;
}
}
-static ArmLIR* opRegReg(CompilationUnit* cUnit, OpKind op, int rDestSrc1,
+STATIC ArmLIR* opRegReg(CompilationUnit* cUnit, OpKind op, int rDestSrc1,
int rSrc2)
{
return opRegRegShift(cUnit, op, rDestSrc1, rSrc2, 0);
}
-static ArmLIR* opRegRegRegShift(CompilationUnit* cUnit, OpKind op,
+STATIC ArmLIR* opRegRegRegShift(CompilationUnit* cUnit, OpKind op,
int rDest, int rSrc1, int rSrc2, int shift)
{
ArmOpcode opcode = kThumbBkpt;
@@ -389,7 +389,7 @@
opcode = kThumb2EorRRR;
break;
case kOpMul:
- assert(shift == 0);
+ DCHECK_EQ(shift, 0);
opcode = kThumb2MulRRR;
break;
case kOpOr:
@@ -399,41 +399,41 @@
opcode = kThumb2SbcRRR;
break;
case kOpLsl:
- assert(shift == 0);
+ DCHECK_EQ(shift, 0);
opcode = kThumb2LslRRR;
break;
case kOpLsr:
- assert(shift == 0);
+ DCHECK_EQ(shift, 0);
opcode = kThumb2LsrRRR;
break;
case kOpAsr:
- assert(shift == 0);
+ DCHECK_EQ(shift, 0);
opcode = kThumb2AsrRRR;
break;
case kOpRor:
- assert(shift == 0);
+ DCHECK_EQ(shift, 0);
opcode = kThumb2RorRRR;
break;
default:
- assert(0);
+ LOG(FATAL) << "Bad opcode: " << (int)op;
break;
}
- assert(opcode >= 0);
+ DCHECK(opcode >= 0);
if (EncodingMap[opcode].flags & IS_QUAD_OP)
return newLIR4(cUnit, opcode, rDest, rSrc1, rSrc2, shift);
else {
- assert(EncodingMap[opcode].flags & IS_TERTIARY_OP);
+ DCHECK(EncodingMap[opcode].flags & IS_TERTIARY_OP);
return newLIR3(cUnit, opcode, rDest, rSrc1, rSrc2);
}
}
-static ArmLIR* opRegRegReg(CompilationUnit* cUnit, OpKind op, int rDest,
+STATIC ArmLIR* opRegRegReg(CompilationUnit* cUnit, OpKind op, int rDest,
int rSrc1, int rSrc2)
{
return opRegRegRegShift(cUnit, op, rDest, rSrc1, rSrc2, 0);
}
-static ArmLIR* opRegRegImm(CompilationUnit* cUnit, OpKind op, int rDest,
+STATIC ArmLIR* opRegRegImm(CompilationUnit* cUnit, OpKind op, int rDest,
int rSrc1, int value)
{
ArmLIR* res;
@@ -539,7 +539,7 @@
return res;
}
default:
- assert(0);
+ LOG(FATAL) << "Bad opcode: " << (int)op;
}
if (modImm >= 0) {
@@ -557,7 +557,7 @@
}
/* Handle Thumb-only variants here - otherwise punt to opRegRegImm */
-static ArmLIR* opRegImm(CompilationUnit* cUnit, OpKind op, int rDestSrc1,
+STATIC ArmLIR* opRegImm(CompilationUnit* cUnit, OpKind op, int rDestSrc1,
int value)
{
bool neg = (value < 0);
@@ -567,7 +567,7 @@
switch (op) {
case kOpAdd:
if ( !neg && (rDestSrc1 == r13sp) && (value <= 508)) { /* sp */
- assert((value & 0x3) == 0);
+ DCHECK_EQ((value & 0x3), 0);
return newLIR1(cUnit, kThumbAddSpI7, value >> 2);
} else if (shortForm) {
opcode = (neg) ? kThumbSubRI8 : kThumbAddRI8;
@@ -575,7 +575,7 @@
break;
case kOpSub:
if (!neg && (rDestSrc1 == r13sp) && (value <= 508)) { /* sp */
- assert((value & 0x3) == 0);
+ DCHECK_EQ((value & 0x3), 0);
return newLIR1(cUnit, kThumbSubSpI7, value >> 2);
} else if (shortForm) {
opcode = (neg) ? kThumbAddRI8 : kThumbSubRI8;
@@ -607,7 +607,7 @@
* Determine whether value can be encoded as a Thumb2 floating point
* immediate. If not, return -1. If so return encoded 8-bit value.
*/
-static int encodeImmDoubleHigh(int value)
+STATIC int encodeImmDoubleHigh(int value)
{
int res;
int bitA = (value & 0x80000000) >> 31;
@@ -629,7 +629,7 @@
return res;
}
-static int encodeImmDouble(int valLo, int valHi)
+STATIC int encodeImmDouble(int valLo, int valHi)
{
int res = -1;
if (valLo == 0)
@@ -637,7 +637,7 @@
return res;
}
-static ArmLIR* loadConstantValueWide(CompilationUnit* cUnit, int rDestLo,
+STATIC ArmLIR* loadConstantValueWide(CompilationUnit* cUnit, int rDestLo,
int rDestHi, int valLo, int valHi)
{
int encodedImm = encodeImmDouble(valLo, valHi);
@@ -672,11 +672,11 @@
return res;
}
-static int encodeShift(int code, int amount) {
+STATIC int encodeShift(int code, int amount) {
return ((amount & 0x1f) << 2) | code;
}
-static ArmLIR* loadBaseIndexed(CompilationUnit* cUnit, int rBase,
+STATIC ArmLIR* loadBaseIndexed(CompilationUnit* cUnit, int rBase,
int rIndex, int rDest, int scale, OpSize size)
{
bool allLowRegs = LOWREG(rBase) && LOWREG(rIndex) && LOWREG(rDest);
@@ -686,8 +686,8 @@
int regPtr;
if (FPREG(rDest)) {
- assert(SINGLEREG(rDest));
- assert((size == kWord) || (size == kSingle));
+ DCHECK(SINGLEREG(rDest));
+ DCHECK((size == kWord) || (size == kSingle));
opcode = kThumb2Vldrs;
size = kSingle;
} else {
@@ -722,7 +722,7 @@
opcode = (thumbForm) ? kThumbLdrsbRRR : kThumb2LdrsbRRR;
break;
default:
- assert(0);
+ LOG(FATAL) << "Bad size: " << (int)size;
}
if (thumbForm)
load = newLIR3(cUnit, opcode, rDest, rBase, rIndex);
@@ -732,7 +732,7 @@
return load;
}
-static ArmLIR* storeBaseIndexed(CompilationUnit* cUnit, int rBase,
+STATIC ArmLIR* storeBaseIndexed(CompilationUnit* cUnit, int rBase,
int rIndex, int rSrc, int scale, OpSize size)
{
bool allLowRegs = LOWREG(rBase) && LOWREG(rIndex) && LOWREG(rSrc);
@@ -742,8 +742,8 @@
int regPtr;
if (FPREG(rSrc)) {
- assert(SINGLEREG(rSrc));
- assert((size == kWord) || (size == kSingle));
+ DCHECK(SINGLEREG(rSrc));
+ DCHECK((size == kWord) || (size == kSingle));
opcode = kThumb2Vstrs;
size = kSingle;
} else {
@@ -774,7 +774,7 @@
opcode = (thumbForm) ? kThumbStrbRRR : kThumb2StrbRRR;
break;
default:
- assert(0);
+ LOG(FATAL) << "Bad size: " << (int)size;
}
if (thumbForm)
store = newLIR3(cUnit, opcode, rSrc, rBase, rIndex);
@@ -789,7 +789,7 @@
* on base (which must have an associated sReg and MIR). If not
* performing null check, incoming MIR can be null.
*/
-static ArmLIR* loadBaseDispBody(CompilationUnit* cUnit, MIR* mir, int rBase,
+STATIC ArmLIR* loadBaseDispBody(CompilationUnit* cUnit, MIR* mir, int rBase,
int displacement, int rDest, int rDestHi,
OpSize size, int sReg)
{
@@ -806,7 +806,7 @@
case kLong:
if (FPREG(rDest)) {
if (SINGLEREG(rDest)) {
- assert(FPREG(rDestHi));
+ DCHECK(FPREG(rDestHi));
rDest = S2D(rDest, rDestHi);
}
opcode = kThumb2Vldrd;
@@ -843,7 +843,7 @@
encodedDisp >>= 2;
opcode = kThumbLdrSpRel;
} else if (allLowRegs && displacement < 128 && displacement >= 0) {
- assert((displacement & 0x3) == 0);
+ DCHECK_EQ((displacement & 0x3), 0);
shortForm = true;
encodedDisp >>= 2;
opcode = kThumbLdrRRI5;
@@ -854,7 +854,7 @@
break;
case kUnsignedHalf:
if (allLowRegs && displacement < 64 && displacement >= 0) {
- assert((displacement & 0x1) == 0);
+ DCHECK_EQ((displacement & 0x1), 0);
shortForm = true;
encodedDisp >>= 1;
opcode = kThumbLdrhRRI5;
@@ -885,7 +885,7 @@
}
break;
default:
- assert(0);
+ LOG(FATAL) << "Bad size: " << (int)size;
}
if (shortForm) {
@@ -904,7 +904,7 @@
return load;
}
-static ArmLIR* loadBaseDisp(CompilationUnit* cUnit, MIR* mir, int rBase,
+STATIC ArmLIR* loadBaseDisp(CompilationUnit* cUnit, MIR* mir, int rBase,
int displacement, int rDest, OpSize size,
int sReg)
{
@@ -912,7 +912,7 @@
size, sReg);
}
-static ArmLIR* loadBaseDispWide(CompilationUnit* cUnit, MIR* mir, int rBase,
+STATIC ArmLIR* loadBaseDispWide(CompilationUnit* cUnit, MIR* mir, int rBase,
int displacement, int rDestLo, int rDestHi,
int sReg)
{
@@ -921,7 +921,7 @@
}
-static ArmLIR* storeBaseDispBody(CompilationUnit* cUnit, int rBase,
+STATIC ArmLIR* storeBaseDispBody(CompilationUnit* cUnit, int rBase,
int displacement, int rSrc, int rSrcHi,
OpSize size)
{
@@ -943,7 +943,7 @@
return res;
}
if (SINGLEREG(rSrc)) {
- assert(FPREG(rSrcHi));
+ DCHECK(FPREG(rSrcHi));
rSrc = S2D(rSrc, rSrcHi);
}
opcode = kThumb2Vstrd;
@@ -955,7 +955,7 @@
case kSingle:
case kWord:
if (FPREG(rSrc)) {
- assert(SINGLEREG(rSrc));
+ DCHECK(SINGLEREG(rSrc));
opcode = kThumb2Vstrs;
if (displacement <= 1020) {
shortForm = true;
@@ -964,7 +964,7 @@
break;
}
if (allLowRegs && displacement < 128 && displacement >= 0) {
- assert((displacement & 0x3) == 0);
+ DCHECK_EQ((displacement & 0x3), 0);
shortForm = true;
encodedDisp >>= 2;
opcode = kThumbStrRRI5;
@@ -976,7 +976,7 @@
case kUnsignedHalf:
case kSignedHalf:
if (allLowRegs && displacement < 64 && displacement >= 0) {
- assert((displacement & 0x1) == 0);
+ DCHECK_EQ((displacement & 0x1), 0);
shortForm = true;
encodedDisp >>= 1;
opcode = kThumbStrhRRI5;
@@ -996,7 +996,7 @@
}
break;
default:
- assert(0);
+ LOG(FATAL) << "Bad size: " << (int)size;
}
if (shortForm) {
store = res = newLIR3(cUnit, opcode, rSrc, rBase, encodedDisp);
@@ -1014,24 +1014,24 @@
return res;
}
-static ArmLIR* storeBaseDisp(CompilationUnit* cUnit, int rBase,
+STATIC ArmLIR* storeBaseDisp(CompilationUnit* cUnit, int rBase,
int displacement, int rSrc, OpSize size)
{
return storeBaseDispBody(cUnit, rBase, displacement, rSrc, -1, size);
}
-static ArmLIR* storeBaseDispWide(CompilationUnit* cUnit, int rBase,
+STATIC ArmLIR* storeBaseDispWide(CompilationUnit* cUnit, int rBase,
int displacement, int rSrcLo, int rSrcHi)
{
return storeBaseDispBody(cUnit, rBase, displacement, rSrcLo, rSrcHi, kLong);
}
-static void storePair(CompilationUnit* cUnit, int base, int lowReg, int highReg)
+STATIC void storePair(CompilationUnit* cUnit, int base, int lowReg, int highReg)
{
storeBaseDispWide(cUnit, base, 0, lowReg, highReg);
}
-static void loadPair(CompilationUnit* cUnit, int base, int lowReg, int highReg)
+STATIC void loadPair(CompilationUnit* cUnit, int base, int lowReg, int highReg)
{
loadBaseDispWide(cUnit, NULL, base, 0, lowReg, highReg, INVALID_SREG);
}
@@ -1040,7 +1040,7 @@
* Generate a register comparison to an immediate and branch. Caller
* is responsible for setting branch target field.
*/
-static ArmLIR* genCmpImmBranch(CompilationUnit* cUnit,
+STATIC ArmLIR* genCmpImmBranch(CompilationUnit* cUnit,
ArmConditionCode cond, int reg,
int checkValue)
{
@@ -1067,7 +1067,7 @@
return branch;
}
-static ArmLIR* fpRegCopy(CompilationUnit* cUnit, int rDest, int rSrc)
+STATIC ArmLIR* fpRegCopy(CompilationUnit* cUnit, int rDest, int rSrc)
{
ArmLIR* res = (ArmLIR* ) oatNew(sizeof(ArmLIR), true);
res->generic.dalvikOffset = cUnit->currentDalvikOffset;
@@ -1076,14 +1076,14 @@
if (rDest == rSrc) {
res->flags.isNop = true;
} else {
- assert(DOUBLEREG(rDest) == DOUBLEREG(rSrc));
+ DCHECK_EQ(DOUBLEREG(rDest), DOUBLEREG(rSrc));
if (DOUBLEREG(rDest)) {
res->opcode = kThumb2Vmovd;
} else {
if (SINGLEREG(rDest)) {
res->opcode = SINGLEREG(rSrc) ? kThumb2Vmovs : kThumb2Fmsr;
} else {
- assert(SINGLEREG(rSrc));
+ DCHECK(SINGLEREG(rSrc));
res->opcode = kThumb2Fmrs;
}
}
@@ -1094,7 +1094,7 @@
return res;
}
-static ArmLIR* genRegCopyNoInsert(CompilationUnit* cUnit, int rDest, int rSrc)
+STATIC ArmLIR* genRegCopyNoInsert(CompilationUnit* cUnit, int rDest, int rSrc)
{
ArmLIR* res;
ArmOpcode opcode;
@@ -1121,20 +1121,20 @@
return res;
}
-static ArmLIR* genRegCopy(CompilationUnit* cUnit, int rDest, int rSrc)
+STATIC ArmLIR* genRegCopy(CompilationUnit* cUnit, int rDest, int rSrc)
{
ArmLIR* res = genRegCopyNoInsert(cUnit, rDest, rSrc);
oatAppendLIR(cUnit, (LIR*)res);
return res;
}
-static void genRegCopyWide(CompilationUnit* cUnit, int destLo, int destHi,
+STATIC void genRegCopyWide(CompilationUnit* cUnit, int destLo, int destHi,
int srcLo, int srcHi)
{
bool destFP = FPREG(destLo) && FPREG(destHi);
bool srcFP = FPREG(srcLo) && FPREG(srcHi);
- assert(FPREG(srcLo) == FPREG(srcHi));
- assert(FPREG(destLo) == FPREG(destHi));
+ DCHECK_EQ(FPREG(srcLo), FPREG(srcHi));
+ DCHECK_EQ(FPREG(destLo), FPREG(destHi));
if (destFP) {
if (srcFP) {
genRegCopy(cUnit, S2D(destLo, destHi), S2D(srcLo, srcHi));
diff --git a/src/compiler/codegen/arm/Thumb2/Gen.cc b/src/compiler/codegen/arm/Thumb2/Gen.cc
index 8f83cbb..43b8ddc 100644
--- a/src/compiler/codegen/arm/Thumb2/Gen.cc
+++ b/src/compiler/codegen/arm/Thumb2/Gen.cc
@@ -45,23 +45,23 @@
* "switchData" must be 32-bit aligned.
*/
#if __BYTE_ORDER == __LITTLE_ENDIAN
-static inline s4 s4FromSwitchData(const void* switchData) {
+STATIC inline s4 s4FromSwitchData(const void* switchData) {
return *(s4*) switchData;
}
#else
-static inline s4 s4FromSwitchData(const void* switchData) {
+STATIC inline s4 s4FromSwitchData(const void* switchData) {
u2* data = switchData;
return data[0] | (((s4) data[1]) << 16);
}
#endif
-static ArmLIR* callRuntimeHelper(CompilationUnit* cUnit, int reg)
+STATIC ArmLIR* callRuntimeHelper(CompilationUnit* cUnit, int reg)
{
return opReg(cUnit, kOpBlx, reg);
}
/* Generate unconditional branch instructions */
-static ArmLIR* genUnconditionalBranch(CompilationUnit* cUnit, ArmLIR* target)
+STATIC ArmLIR* genUnconditionalBranch(CompilationUnit* cUnit, ArmLIR* target)
{
ArmLIR* branch = opNone(cUnit, kOpUncondBr);
branch->generic.target = (LIR*) target;
@@ -78,7 +78,7 @@
* met, and an "E" means the instruction is executed if the condition
* is not met.
*/
-static ArmLIR* genIT(CompilationUnit* cUnit, ArmConditionCode code,
+STATIC ArmLIR* genIT(CompilationUnit* cUnit, ArmConditionCode code,
const char* guide)
{
int mask;
@@ -114,7 +114,7 @@
* all resource flags on this to prevent code motion across
* target boundaries. KeyVal is just there for debugging.
*/
-static ArmLIR* insertCaseLabel(CompilationUnit* cUnit, int vaddr, int keyVal)
+STATIC ArmLIR* insertCaseLabel(CompilationUnit* cUnit, int vaddr, int keyVal)
{
ArmLIR* lir;
for (lir = (ArmLIR*)cUnit->firstLIRInsn; lir; lir = NEXT_LIR(lir)) {
@@ -133,7 +133,7 @@
return NULL; // Quiet gcc
}
-static void markPackedCaseLabels(CompilationUnit* cUnit, SwitchTable *tabRec)
+STATIC void markPackedCaseLabels(CompilationUnit* cUnit, SwitchTable *tabRec)
{
const u2* table = tabRec->table;
int baseVaddr = tabRec->vaddr;
@@ -146,7 +146,7 @@
}
}
-static void markSparseCaseLabels(CompilationUnit* cUnit, SwitchTable *tabRec)
+STATIC void markSparseCaseLabels(CompilationUnit* cUnit, SwitchTable *tabRec)
{
const u2* table = tabRec->table;
int baseVaddr = tabRec->vaddr;
@@ -177,7 +177,7 @@
}
}
-static void dumpSparseSwitchTable(const u2* table)
+STATIC void dumpSparseSwitchTable(const u2* table)
/*
* Sparse switch data format:
* ushort ident = 0x0200 magic value
@@ -200,7 +200,7 @@
}
}
-static void dumpPackedSwitchTable(const u2* table)
+STATIC void dumpPackedSwitchTable(const u2* table)
/*
* Packed switch data format:
* ushort ident = 0x0100 magic value
@@ -242,7 +242,7 @@
* add rPC, rDisp ; This is the branch from which we compute displacement
* cbnz rIdx, lp
*/
-static void genSparseSwitch(CompilationUnit* cUnit, MIR* mir,
+STATIC void genSparseSwitch(CompilationUnit* cUnit, MIR* mir,
RegLocation rlSrc)
{
const u2* table = cUnit->insns + mir->offset + mir->dalvikInsn.vB;
@@ -292,7 +292,7 @@
}
-static void genPackedSwitch(CompilationUnit* cUnit, MIR* mir,
+STATIC void genPackedSwitch(CompilationUnit* cUnit, MIR* mir,
RegLocation rlSrc)
{
const u2* table = cUnit->insns + mir->offset + mir->dalvikInsn.vB;
@@ -350,7 +350,7 @@
*
* Total size is 4+(width * size + 1)/2 16-bit code units.
*/
-static void genFillArrayData(CompilationUnit* cUnit, MIR* mir,
+STATIC void genFillArrayData(CompilationUnit* cUnit, MIR* mir,
RegLocation rlSrc)
{
const u2* table = cUnit->insns + mir->offset + mir->dalvikInsn.vB;
@@ -379,7 +379,7 @@
/*
* Mark garbage collection card. Skip if the value we're storing is null.
*/
-static void markGCCard(CompilationUnit* cUnit, int valReg, int tgtAddrReg)
+STATIC void markGCCard(CompilationUnit* cUnit, int valReg, int tgtAddrReg)
{
#ifdef CONCURRENT_GARBAGE_COLLECTOR
// TODO: re-enable when concurrent collector is active
@@ -403,7 +403,7 @@
* Helper function for Iget/put when field not resolved at compile time.
* Will trash call temps and return with the field offset in r0.
*/
-static void getFieldOffset(CompilationUnit* cUnit, MIR* mir)
+STATIC void getFieldOffset(CompilationUnit* cUnit, MIR* mir)
{
int fieldIdx = mir->dalvikInsn.vC;
LOG(INFO) << "Field " << fieldNameFromIndex(cUnit->method, fieldIdx)
@@ -438,7 +438,7 @@
loadWordDisp(cUnit, r0, art::Field::OffsetOffset().Int32Value(), r0);
}
-static void genIGet(CompilationUnit* cUnit, MIR* mir, OpSize size,
+STATIC void genIGet(CompilationUnit* cUnit, MIR* mir, OpSize size,
RegLocation rlDest, RegLocation rlObj)
{
Field* fieldPtr = cUnit->method->GetDeclaringClass()->GetDexCache()->
@@ -473,7 +473,7 @@
}
}
-static void genIPut(CompilationUnit* cUnit, MIR* mir, OpSize size,
+STATIC void genIPut(CompilationUnit* cUnit, MIR* mir, OpSize size,
RegLocation rlSrc, RegLocation rlObj, bool isObject)
{
Field* fieldPtr = cUnit->method->GetDeclaringClass()->GetDexCache()->
@@ -509,7 +509,7 @@
}
}
-static void genIGetWide(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
+STATIC void genIGetWide(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
RegLocation rlObj)
{
Field* fieldPtr = cUnit->method->GetDeclaringClass()->GetDexCache()->
@@ -535,7 +535,7 @@
rlObj = loadValue(cUnit, rlObj, kCoreReg);
int regPtr = oatAllocTemp(cUnit);
- assert(rlDest.wide);
+ DCHECK(rlDest.wide);
genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir);/* null obj? */
opRegRegImm(cUnit, kOpAdd, regPtr, rlObj.lowReg, fieldOffset);
@@ -552,7 +552,7 @@
}
}
-static void genIPutWide(CompilationUnit* cUnit, MIR* mir, RegLocation rlSrc,
+STATIC void genIPutWide(CompilationUnit* cUnit, MIR* mir, RegLocation rlSrc,
RegLocation rlObj)
{
Field* fieldPtr = cUnit->method->GetDeclaringClass()->GetDexCache()->
@@ -590,7 +590,7 @@
}
}
-static void genConstClass(CompilationUnit* cUnit, MIR* mir,
+STATIC void genConstClass(CompilationUnit* cUnit, MIR* mir,
RegLocation rlDest, RegLocation rlSrc)
{
art::Class* classPtr = cUnit->method->GetDexCacheResolvedTypes()->
@@ -632,7 +632,7 @@
}
}
-static void genConstString(CompilationUnit* cUnit, MIR* mir,
+STATIC void genConstString(CompilationUnit* cUnit, MIR* mir,
RegLocation rlDest, RegLocation rlSrc)
{
/* All strings should be available at compile time */
@@ -654,7 +654,7 @@
* Let helper function take care of everything. Will
* call Class::NewInstanceFromCode(type_idx, method);
*/
-static void genNewInstance(CompilationUnit* cUnit, MIR* mir,
+STATIC void genNewInstance(CompilationUnit* cUnit, MIR* mir,
RegLocation rlDest)
{
oatFlushAllRegs(cUnit); /* Everything to home location */
@@ -676,7 +676,7 @@
callRuntimeHelper(cUnit, rLR); // art_deliver_exception(exception);
}
-static void genInstanceof(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
+STATIC void genInstanceof(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
RegLocation rlSrc)
{
// May generate a call - use explicit registers
@@ -709,7 +709,7 @@
/* When taken r0 has NULL which can be used for store directly */
ArmLIR* branch1 = genCmpImmBranch(cUnit, kArmCondEq, r3, 0);
/* load object->clazz */
- assert(Object::ClassOffset().Int32Value() == 0);
+ DCHECK_EQ(Object::ClassOffset().Int32Value(), 0);
loadWordDisp(cUnit, r3, Object::ClassOffset().Int32Value(), r1);
/* r1 now contains object->clazz */
loadWordDisp(cUnit, rSELF,
@@ -730,7 +730,7 @@
branch2->generic.target = (LIR*)target;
}
-static void genCheckCast(CompilationUnit* cUnit, MIR* mir, RegLocation rlSrc)
+STATIC void genCheckCast(CompilationUnit* cUnit, MIR* mir, RegLocation rlSrc)
{
// May generate a call - use explicit registers
oatLockCallTemps(cUnit);
@@ -762,7 +762,7 @@
/* Null is OK - continue */
ArmLIR* branch1 = genCmpImmBranch(cUnit, kArmCondEq, r0, 0);
/* load object->clazz */
- assert(Object::ClassOffset().Int32Value() == 0);
+ DCHECK_EQ(Object::ClassOffset().Int32Value(), 0);
loadWordDisp(cUnit, r0, Object::ClassOffset().Int32Value(), r1);
/* r1 now contains object->clazz */
loadWordDisp(cUnit, rSELF,
@@ -780,7 +780,7 @@
branch2->generic.target = (LIR*)target;
}
-static void genNegFloat(CompilationUnit* cUnit, RegLocation rlDest,
+STATIC void genNegFloat(CompilationUnit* cUnit, RegLocation rlDest,
RegLocation rlSrc)
{
RegLocation rlResult;
@@ -790,7 +790,7 @@
storeValue(cUnit, rlDest, rlResult);
}
-static void genNegDouble(CompilationUnit* cUnit, RegLocation rlDest,
+STATIC void genNegDouble(CompilationUnit* cUnit, RegLocation rlDest,
RegLocation rlSrc)
{
RegLocation rlResult;
@@ -801,7 +801,7 @@
storeValueWide(cUnit, rlDest, rlResult);
}
-static void freeRegLocTemps(CompilationUnit* cUnit, RegLocation rlKeep,
+STATIC void freeRegLocTemps(CompilationUnit* cUnit, RegLocation rlKeep,
RegLocation rlFree)
{
if ((rlFree.lowReg != rlKeep.lowReg) && (rlFree.lowReg != rlKeep.highReg))
@@ -810,7 +810,7 @@
oatFreeTemp(cUnit, rlFree.lowReg);
}
-static void genLong3Addr(CompilationUnit* cUnit, MIR* mir, OpKind firstOp,
+STATIC void genLong3Addr(CompilationUnit* cUnit, MIR* mir, OpKind firstOp,
OpKind secondOp, RegLocation rlDest,
RegLocation rlSrc1, RegLocation rlSrc2)
{
@@ -901,7 +901,7 @@
* preserved.
*
*/
-static void genMonitorEnter(CompilationUnit* cUnit, MIR* mir,
+STATIC void genMonitorEnter(CompilationUnit* cUnit, MIR* mir,
RegLocation rlSrc)
{
ArmLIR* target;
@@ -950,7 +950,7 @@
* a zero recursion count, it's safe to punch it back to the
* initial, unlock thin state with a store word.
*/
-static void genMonitorExit(CompilationUnit* cUnit, MIR* mir,
+STATIC void genMonitorExit(CompilationUnit* cUnit, MIR* mir,
RegLocation rlSrc)
{
ArmLIR* target;
@@ -1007,7 +1007,7 @@
* neg rX
* done:
*/
-static void genCmpLong(CompilationUnit* cUnit, MIR* mir,
+STATIC void genCmpLong(CompilationUnit* cUnit, MIR* mir,
RegLocation rlDest, RegLocation rlSrc1,
RegLocation rlSrc2)
{
@@ -1043,7 +1043,7 @@
branch3->generic.target = branch1->generic.target;
}
-static void genMultiplyByTwoBitMultiplier(CompilationUnit* cUnit,
+STATIC void genMultiplyByTwoBitMultiplier(CompilationUnit* cUnit,
RegLocation rlSrc, RegLocation rlResult, int lit,
int firstBit, int secondBit)
{
@@ -1054,7 +1054,7 @@
}
}
-static bool genConversionCall(CompilationUnit* cUnit, MIR* mir, int funcOffset,
+STATIC bool genConversionCall(CompilationUnit* cUnit, MIR* mir, int funcOffset,
int srcSize, int tgtSize)
{
/*
@@ -1088,7 +1088,7 @@
return false;
}
-static bool genArithOpFloatPortable(CompilationUnit* cUnit, MIR* mir,
+STATIC bool genArithOpFloatPortable(CompilationUnit* cUnit, MIR* mir,
RegLocation rlDest, RegLocation rlSrc1,
RegLocation rlSrc2)
{
@@ -1134,7 +1134,7 @@
return false;
}
-static bool genArithOpDoublePortable(CompilationUnit* cUnit, MIR* mir,
+STATIC bool genArithOpDoublePortable(CompilationUnit* cUnit, MIR* mir,
RegLocation rlDest, RegLocation rlSrc1,
RegLocation rlSrc2)
{
@@ -1180,7 +1180,7 @@
return false;
}
-static bool genConversionPortable(CompilationUnit* cUnit, MIR* mir)
+STATIC bool genConversionPortable(CompilationUnit* cUnit, MIR* mir)
{
Opcode opcode = mir->dalvikInsn.opcode;
@@ -1222,7 +1222,7 @@
}
/* Generate conditional branch instructions */
-static ArmLIR* genConditionalBranch(CompilationUnit* cUnit,
+STATIC ArmLIR* genConditionalBranch(CompilationUnit* cUnit,
ArmConditionCode cond,
ArmLIR* target)
{
@@ -1235,7 +1235,7 @@
* Generate array store
*
*/
-static void genArrayObjPut(CompilationUnit* cUnit, MIR* mir,
+STATIC void genArrayObjPut(CompilationUnit* cUnit, MIR* mir,
RegLocation rlArray, RegLocation rlIndex,
RegLocation rlSrc, int scale)
{
@@ -1293,7 +1293,7 @@
/*
* Generate array load
*/
-static void genArrayGet(CompilationUnit* cUnit, MIR* mir, OpSize size,
+STATIC void genArrayGet(CompilationUnit* cUnit, MIR* mir, OpSize size,
RegLocation rlArray, RegLocation rlIndex,
RegLocation rlDest, int scale)
{
@@ -1355,7 +1355,7 @@
* Generate array store
*
*/
-static void genArrayPut(CompilationUnit* cUnit, MIR* mir, OpSize size,
+STATIC void genArrayPut(CompilationUnit* cUnit, MIR* mir, OpSize size,
RegLocation rlArray, RegLocation rlIndex,
RegLocation rlSrc, int scale)
{
@@ -1416,7 +1416,7 @@
}
}
-static bool genShiftOpLong(CompilationUnit* cUnit, MIR* mir,
+STATIC bool genShiftOpLong(CompilationUnit* cUnit, MIR* mir,
RegLocation rlDest, RegLocation rlSrc1,
RegLocation rlShift)
{
@@ -1450,7 +1450,7 @@
return false;
}
-static bool genArithOpLong(CompilationUnit* cUnit, MIR* mir,
+STATIC bool genArithOpLong(CompilationUnit* cUnit, MIR* mir,
RegLocation rlDest, RegLocation rlSrc1,
RegLocation rlSrc2)
{
@@ -1549,7 +1549,7 @@
return false;
}
-static bool genArithOpInt(CompilationUnit* cUnit, MIR* mir,
+STATIC bool genArithOpInt(CompilationUnit* cUnit, MIR* mir,
RegLocation rlDest, RegLocation rlSrc1,
RegLocation rlSrc2)
{
@@ -1672,7 +1672,7 @@
}
/* Check if we need to check for pending suspend request */
-static void genSuspendTest(CompilationUnit* cUnit, MIR* mir)
+STATIC void genSuspendTest(CompilationUnit* cUnit, MIR* mir)
{
if (mir->optimizationFlags & MIR_IGNORE_SUSPEND_CHECK) {
return;
@@ -1691,7 +1691,7 @@
}
/* Check for pending suspend request. */
-static void genSuspendPoll(CompilationUnit* cUnit, MIR* mir)
+STATIC void genSuspendPoll(CompilationUnit* cUnit, MIR* mir)
{
if (mir->optimizationFlags & MIR_IGNORE_SUSPEND_CHECK) {
return;
@@ -1734,20 +1734,20 @@
* or produce corresponding Thumb instructions directly.
*/
-static bool isPowerOfTwo(int x)
+STATIC bool isPowerOfTwo(int x)
{
return (x & (x - 1)) == 0;
}
// Returns true if no more than two bits are set in 'x'.
-static bool isPopCountLE2(unsigned int x)
+STATIC bool isPopCountLE2(unsigned int x)
{
x &= x - 1;
return (x & (x - 1)) == 0;
}
// Returns the index of the lowest set bit in 'x'.
-static int lowestSetBit(unsigned int x) {
+STATIC int lowestSetBit(unsigned int x) {
int bit_posn = 0;
while ((x & 0xf) == 0) {
bit_posn += 4;
@@ -1762,7 +1762,7 @@
// Returns true if it added instructions to 'cUnit' to divide 'rlSrc' by 'lit'
// and store the result in 'rlDest'.
-static bool handleEasyDivide(CompilationUnit* cUnit, Opcode dalvikOpcode,
+STATIC bool handleEasyDivide(CompilationUnit* cUnit, Opcode dalvikOpcode,
RegLocation rlSrc, RegLocation rlDest, int lit)
{
if (lit < 2 || !isPowerOfTwo(lit)) {
@@ -1814,7 +1814,7 @@
// Returns true if it added instructions to 'cUnit' to multiply 'rlSrc' by 'lit'
// and store the result in 'rlDest'.
-static bool handleEasyMultiply(CompilationUnit* cUnit,
+STATIC bool handleEasyMultiply(CompilationUnit* cUnit,
RegLocation rlSrc, RegLocation rlDest, int lit)
{
// Can we simplify this multiplication?
@@ -1847,7 +1847,7 @@
firstBit, secondBit);
} else {
// Reverse subtract: (src << (shift + 1)) - src.
- assert(powerOfTwoMinusOne);
+ DCHECK(powerOfTwoMinusOne);
// TUNING: rsb dst, src, src lsl#lowestSetBit(lit + 1)
int tReg = oatAllocTemp(cUnit);
opRegRegImm(cUnit, kOpLsl, tReg, rlSrc.lowReg, lowestSetBit(lit + 1));
@@ -1857,7 +1857,7 @@
return true;
}
-static bool genArithOpIntLit(CompilationUnit* cUnit, MIR* mir,
+STATIC bool genArithOpIntLit(CompilationUnit* cUnit, MIR* mir,
RegLocation rlDest, RegLocation rlSrc,
int lit)
{
